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-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_spi.h81
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h96
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_tc.h146
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_udp.h77
4 files changed, 400 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h b/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
new file mode 100644
index 000000000000..bff5ea45f604
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
@@ -0,0 +1,81 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Serial Peripheral Interface (SPI) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_SPI_H
17#define AT91RM9200_SPI_H
18
19#define AT91_SPI_CR 0x00 /* Control Register */
20#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
21#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
22#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
23#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
24
25#define AT91_SPI_MR 0x04 /* Mode Register */
26#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
27#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
28#define AT91_SPI_PS_FIXED (0 << 1)
29#define AT91_SPI_PS_VARIABLE (1 << 1)
30#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
31#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection */
32#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
33#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
34#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
35#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
36
37#define AT91_SPI_RDR 0x08 /* Receive Data Register */
38#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
39#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
40
41#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
42#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
43#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
44#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
45
46#define AT91_SPI_SR 0x10 /* Status Register */
47#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
48#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
49#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
50#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
51#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
52#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
53#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
54#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
55#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
56#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
57#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
58
59#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
60#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
61#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
62
63#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
64#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
65#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
66#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
67#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
68#define AT91_SPI_BITS_8 (0 << 4)
69#define AT91_SPI_BITS_9 (1 << 4)
70#define AT91_SPI_BITS_10 (2 << 4)
71#define AT91_SPI_BITS_11 (3 << 4)
72#define AT91_SPI_BITS_12 (4 << 4)
73#define AT91_SPI_BITS_13 (5 << 4)
74#define AT91_SPI_BITS_14 (6 << 4)
75#define AT91_SPI_BITS_15 (7 << 4)
76#define AT91_SPI_BITS_16 (8 << 4)
77#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
78#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
79#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
80
81#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
new file mode 100644
index 000000000000..ac880227147f
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
@@ -0,0 +1,96 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Serial Synchronous Controller (SSC) registers.
7 * Based on AT91RM9200 datasheet revision E.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91RM9200_SSC_H
16#define AT91RM9200_SSC_H
17
18#define AT91_SSC_CR 0x00 /* Control Register */
19#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
20#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */
21#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */
22#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */
23#define AT91_SSC_SWRST (1 << 15) /* Software Reset */
24
25#define AT91_SSC_CMR 0x04 /* Clock Mode Register */
26#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */
27
28#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */
29#define AT91_SSC_CKS (3 << 0) /* Clock Selection */
30#define AT91_SSC_CKS_DIV (0 << 0)
31#define AT91_SSC_CKS_CLOCK (1 << 0)
32#define AT91_SSC_CKS_PIN (2 << 0)
33#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */
34#define AT91_SSC_CKO_NONE (0 << 2)
35#define AT91_SSC_CKO_CONTINUOUS (1 << 2)
36#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
37#define AT91_SSC_CKI_FALLING (0 << 5)
38#define AT91_SSC_CK_RISING (1 << 5)
39#define AT91_SSC_START (0xf << 8) /* Start Selection */
40#define AT91_SSC_START_CONTINUOUS (0 << 8)
41#define AT91_SSC_START_TX_RX (1 << 8)
42#define AT91_SSC_START_LOW_RF (2 << 8)
43#define AT91_SSC_START_HIGH_RF (3 << 8)
44#define AT91_SSC_START_FALLING_RF (4 << 8)
45#define AT91_SSC_START_RISING_RF (5 << 8)
46#define AT91_SSC_START_LEVEL_RF (6 << 8)
47#define AT91_SSC_START_EDGE_RF (7 << 8)
48#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
49#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
50
51#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */
52#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */
53#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */
54#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */
55#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */
56#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */
57#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */
58#define AT91_SSC_FSOS_NONE (0 << 20)
59#define AT91_SSC_FSOS_NEGATIVE (1 << 20)
60#define AT91_SSC_FSOS_POSITIVE (2 << 20)
61#define AT91_SSC_FSOS_LOW (3 << 20)
62#define AT91_SSC_FSOS_HIGH (4 << 20)
63#define AT91_SSC_FSOS_TOGGLE (5 << 20)
64#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */
65#define AT91_SSC_FSEDGE_POSITIVE (0 << 24)
66#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24)
67
68#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */
69#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */
70#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */
71#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */
72
73#define AT91_SSC_RHR 0x20 /* Receive Holding Register */
74#define AT91_SSC_THR 0x24 /* Transmit Holding Register */
75#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
76#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
77
78#define AT91_SSC_SR 0x40 /* Status Register */
79#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
80#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
81#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */
82#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */
83#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */
84#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
85#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
86#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
87#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
88#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
89#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
90#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */
91
92#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */
93#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */
94#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */
95
96#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
new file mode 100644
index 000000000000..f4da752bb0c8
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
@@ -0,0 +1,146 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Timer/Counter Unit (TC) registers.
7 * Based on AT91RM9200 datasheet revision E.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91RM9200_TC_H
16#define AT91RM9200_TC_H
17
18#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
19#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
20
21#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
22#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
23#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
24#define AT91_TC_TC0XC0S_NONE (1 << 0)
25#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
26#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
27#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
28#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
29#define AT91_TC_TC1XC1S_NONE (1 << 2)
30#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
31#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
32#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
33#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
34#define AT91_TC_TC2XC2S_NONE (1 << 4)
35#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
36#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
37
38
39#define AT91_TC_CCR 0x00 /* Channel Control Register */
40#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
41#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
42#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
43
44#define AT91_TC_CMR 0x04 /* Channel Mode Register */
45#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
46#define AT91_TC_TIMER_CLOCK1 (0 << 0)
47#define AT91_TC_TIMER_CLOCK2 (1 << 0)
48#define AT91_TC_TIMER_CLOCK3 (2 << 0)
49#define AT91_TC_TIMER_CLOCK4 (3 << 0)
50#define AT91_TC_TIMER_CLOCK5 (4 << 0)
51#define AT91_TC_XC0 (5 << 0)
52#define AT91_TC_XC1 (6 << 0)
53#define AT91_TC_XC2 (7 << 0)
54#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
55#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
56#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
57#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
58#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
59#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
60#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
61#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
62#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
63#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
64
65#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
66#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
67#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
68#define AT91_TC_EEVTEDG_NONE (0 << 8)
69#define AT91_TC_EEVTEDG_RISING (1 << 8)
70#define AT91_TC_EEVTEDG_FALLING (2 << 8)
71#define AT91_TC_EEVTEDG_BOTH (3 << 8)
72#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
73#define AT91_TC_EEVT_TIOB (0 << 10)
74#define AT91_TC_EEVT_XC0 (1 << 10)
75#define AT91_TC_EEVT_XC1 (2 << 10)
76#define AT91_TC_EEVT_XC2 (3 << 10)
77#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
78#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
79#define AT91_TC_WAVESEL_UP (0 << 13)
80#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
81#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
82#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
83#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
84#define AT91_TC_ACPA_NONE (0 << 16)
85#define AT91_TC_ACPA_SET (1 << 16)
86#define AT91_TC_ACPA_CLEAR (2 << 16)
87#define AT91_TC_ACPA_TOGGLE (3 << 16)
88#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
89#define AT91_TC_ACPC_NONE (0 << 18)
90#define AT91_TC_ACPC_SET (1 << 18)
91#define AT91_TC_ACPC_CLEAR (2 << 18)
92#define AT91_TC_ACPC_TOGGLE (3 << 18)
93#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
94#define AT91_TC_AEEVT_NONE (0 << 20)
95#define AT91_TC_AEEVT_SET (1 << 20)
96#define AT91_TC_AEEVT_CLEAR (2 << 20)
97#define AT91_TC_AEEVT_TOGGLE (3 << 20)
98#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
99#define AT91_TC_ASWTRG_NONE (0 << 22)
100#define AT91_TC_ASWTRG_SET (1 << 22)
101#define AT91_TC_ASWTRG_CLEAR (2 << 22)
102#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
103#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
104#define AT91_TC_BCPB_NONE (0 << 24)
105#define AT91_TC_BCPB_SET (1 << 24)
106#define AT91_TC_BCPB_CLEAR (2 << 24)
107#define AT91_TC_BCPB_TOGGLE (3 << 24)
108#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
109#define AT91_TC_BCPC_NONE (0 << 26)
110#define AT91_TC_BCPC_SET (1 << 26)
111#define AT91_TC_BCPC_CLEAR (2 << 26)
112#define AT91_TC_BCPC_TOGGLE (3 << 26)
113#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
114#define AT91_TC_BEEVT_NONE (0 << 28)
115#define AT91_TC_BEEVT_SET (1 << 28)
116#define AT91_TC_BEEVT_CLEAR (2 << 28)
117#define AT91_TC_BEEVT_TOGGLE (3 << 28)
118#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
119#define AT91_TC_BSWTRG_NONE (0 << 30)
120#define AT91_TC_BSWTRG_SET (1 << 30)
121#define AT91_TC_BSWTRG_CLEAR (2 << 30)
122#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
123
124#define AT91_TC_CV 0x10 /* Counter Value */
125#define AT91_TC_RA 0x14 /* Register A */
126#define AT91_TC_RB 0x18 /* Register B */
127#define AT91_TC_RC 0x1c /* Register C */
128
129#define AT91_TC_SR 0x20 /* Status Register */
130#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
131#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
132#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
133#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
134#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
135#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
136#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
137#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
138#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
139#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
140#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
141
142#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
143#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
144#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
145
146#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h b/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
new file mode 100644
index 000000000000..951e3f61cef4
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
@@ -0,0 +1,77 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * USB Device Port (UDP) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_UDP_H
17#define AT91RM9200_UDP_H
18
19#define AT91_UDP_FRM_NUM 0x00 /* Frame Number Register */
20#define AT91_UDP_NUM (0x7ff << 0) /* Frame Number */
21#define AT91_UDP_FRM_ERR (1 << 16) /* Frame Error */
22#define AT91_UDP_FRM_OK (1 << 17) /* Frame OK */
23
24#define AT91_UDP_GLB_STAT 0x04 /* Global State Register */
25#define AT91_UDP_FADDEN (1 << 0) /* Function Address Enable */
26#define AT91_UDP_CONFG (1 << 1) /* Configured */
27#define AT91_UDP_ESR (1 << 2) /* Enable Send Resume */
28#define AT91_UDP_RSMINPR (1 << 3) /* Resume has been sent */
29#define AT91_UDP_RMWUPE (1 << 4) /* Remote Wake Up Enable */
30
31#define AT91_UDP_FADDR 0x08 /* Function Address Register */
32#define AT91_UDP_FADD (0x7f << 0) /* Function Address Value */
33#define AT91_UDP_FEN (1 << 8) /* Function Enable */
34
35#define AT91_UDP_IER 0x10 /* Interrupt Enable Register */
36#define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */
37#define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */
38
39#define AT91_UDP_ISR 0x1c /* Interrupt Status Register */
40#define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */
41#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */
42#define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */
43#define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status */
44#define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */
45#define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrpt Status */
46#define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status */
47
48#define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */
49#define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */
50
51#define AT91_UDP_CSR(n) (0x30 + ((n) * 4)) /* Endpoint Control/Status Registers 0-7 */
52#define AT91_UDP_TXCOMP (1 << 0) /* Generates IN packet with data previously written in DPR */
53#define AT91_UDP_RX_DATA_BK0 (1 << 1) /* Receive Data Bank 0 */
54#define AT91_UDP_RXSETUP (1 << 2) /* Send STALL to the host */
55#define AT91_UDP_STALLSENT (1 << 3) /* Stall Sent / Isochronous error (Isochronous endpoints) */
56#define AT91_UDP_TXPKTRDY (1 << 4) /* Transmit Packet Ready */
57#define AT91_UDP_FORCESTALL (1 << 5) /* Force Stall */
58#define AT91_UDP_RX_DATA_BK1 (1 << 6) /* Receive Data Bank 1 */
59#define AT91_UDP_DIR (1 << 7) /* Transfer Direction */
60#define AT91_UDP_EPTYPE (7 << 8) /* Endpoint Type */
61#define AT91_UDP_EPTYPE_CTRL (0 << 8)
62#define AT91_UDP_EPTYPE_ISO_OUT (1 << 8)
63#define AT91_UDP_EPTYPE_BULK_OUT (2 << 8)
64#define AT91_UDP_EPTYPE_INT_OUT (3 << 8)
65#define AT91_UDP_EPTYPE_ISO_IN (5 << 8)
66#define AT91_UDP_EPTYPE_BULK_IN (6 << 8)
67#define AT91_UDP_EPTYPE_INT_IN (7 << 8)
68#define AT91_UDP_DTGLE (1 << 11) /* Data Toggle */
69#define AT91_UDP_EPEDS (1 << 15) /* Endpoint Enable/Disable */
70#define AT91_UDP_RXBYTECNT (0x7ff << 16) /* Number of bytes in FIFO */
71
72#define AT91_UDP_FDR(n) (0x50 + ((n) * 4)) /* Endpoint FIFO Data Registers 0-7 */
73
74#define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */
75#define AT91_UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */
76
77#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-29 09:09:25 -0500