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-rw-r--r--arch/arm/mach-orion/addr-map.c14
-rw-r--r--arch/arm/mach-orion/common.c52
-rw-r--r--arch/arm/mach-orion/db88f5281-setup.c4
-rw-r--r--arch/arm/mach-orion/dns323-setup.c8
-rw-r--r--arch/arm/mach-orion/kurobox_pro-setup.c8
-rw-r--r--arch/arm/mach-orion/pci.c10
-rw-r--r--arch/arm/mach-orion/rd88f5182-setup.c8
-rw-r--r--arch/arm/mach-orion/ts209-setup.c10
-rw-r--r--include/asm-arm/arch-orion/debug-macro.S9
-rw-r--r--include/asm-arm/arch-orion/entry-macro.S4
-rw-r--r--include/asm-arm/arch-orion/hardware.h13
-rw-r--r--include/asm-arm/arch-orion/orion.h102
-rw-r--r--include/asm-arm/arch-orion/uncompress.h4
13 files changed, 135 insertions, 111 deletions
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c
index 488da3811a68..2e2fd63643c3 100644
--- a/arch/arm/mach-orion/addr-map.c
+++ b/arch/arm/mach-orion/addr-map.c
@@ -265,15 +265,15 @@ void __init orion_setup_cpu_wins(void)
265 } 265 }
266 266
267 /* 267 /*
268 * Setup windows for PCI+PCIE IO+MAM space 268 * Setup windows for PCI+PCIe IO+MEM space.
269 */ 269 */
270 orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE, 270 orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
271 ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP); 271 ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
272 orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE, 272 orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
273 ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP); 273 ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
274 orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE, 274 orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
275 ORION_PCIE_MEM_SIZE, -1); 275 ORION_PCIE_MEM_SIZE, -1);
276 orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE, 276 orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
277 ORION_PCI_MEM_SIZE, -1); 277 ORION_PCI_MEM_SIZE, -1);
278} 278}
279 279
diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c
index 5f41fc537fa5..5f0ee4b8a9b7 100644
--- a/arch/arm/mach-orion/common.c
+++ b/arch/arm/mach-orion/common.c
@@ -27,26 +27,26 @@
27 ****************************************************************************/ 27 ****************************************************************************/
28static struct map_desc orion_io_desc[] __initdata = { 28static struct map_desc orion_io_desc[] __initdata = {
29 { 29 {
30 .virtual = ORION_REGS_BASE, 30 .virtual = ORION_REGS_VIRT_BASE,
31 .pfn = __phys_to_pfn(ORION_REGS_BASE), 31 .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE),
32 .length = ORION_REGS_SIZE, 32 .length = ORION_REGS_SIZE,
33 .type = MT_DEVICE 33 .type = MT_DEVICE
34 }, 34 },
35 { 35 {
36 .virtual = ORION_PCIE_IO_BASE, 36 .virtual = ORION_PCIE_IO_VIRT_BASE,
37 .pfn = __phys_to_pfn(ORION_PCIE_IO_BASE), 37 .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE),
38 .length = ORION_PCIE_IO_SIZE, 38 .length = ORION_PCIE_IO_SIZE,
39 .type = MT_DEVICE 39 .type = MT_DEVICE
40 }, 40 },
41 { 41 {
42 .virtual = ORION_PCI_IO_BASE, 42 .virtual = ORION_PCI_IO_VIRT_BASE,
43 .pfn = __phys_to_pfn(ORION_PCI_IO_BASE), 43 .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE),
44 .length = ORION_PCI_IO_SIZE, 44 .length = ORION_PCI_IO_SIZE,
45 .type = MT_DEVICE 45 .type = MT_DEVICE
46 }, 46 },
47 { 47 {
48 .virtual = ORION_PCIE_WA_BASE, 48 .virtual = ORION_PCIE_WA_VIRT_BASE,
49 .pfn = __phys_to_pfn(ORION_PCIE_WA_BASE), 49 .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE),
50 .length = ORION_PCIE_WA_SIZE, 50 .length = ORION_PCIE_WA_SIZE,
51 .type = MT_DEVICE 51 .type = MT_DEVICE
52 }, 52 },
@@ -63,8 +63,8 @@ void __init orion_map_io(void)
63 63
64static struct resource orion_uart_resources[] = { 64static struct resource orion_uart_resources[] = {
65 { 65 {
66 .start = UART0_BASE, 66 .start = UART0_PHYS_BASE,
67 .end = UART0_BASE + 0xff, 67 .end = UART0_PHYS_BASE + 0xff,
68 .flags = IORESOURCE_MEM, 68 .flags = IORESOURCE_MEM,
69 }, 69 },
70 { 70 {
@@ -73,8 +73,8 @@ static struct resource orion_uart_resources[] = {
73 .flags = IORESOURCE_IRQ, 73 .flags = IORESOURCE_IRQ,
74 }, 74 },
75 { 75 {
76 .start = UART1_BASE, 76 .start = UART1_PHYS_BASE,
77 .end = UART1_BASE + 0xff, 77 .end = UART1_PHYS_BASE + 0xff,
78 .flags = IORESOURCE_MEM, 78 .flags = IORESOURCE_MEM,
79 }, 79 },
80 { 80 {
@@ -86,8 +86,8 @@ static struct resource orion_uart_resources[] = {
86 86
87static struct plat_serial8250_port orion_uart_data[] = { 87static struct plat_serial8250_port orion_uart_data[] = {
88 { 88 {
89 .mapbase = UART0_BASE, 89 .mapbase = UART0_PHYS_BASE,
90 .membase = (char *)UART0_BASE, 90 .membase = (char *)UART0_VIRT_BASE,
91 .irq = IRQ_ORION_UART0, 91 .irq = IRQ_ORION_UART0,
92 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 92 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
93 .iotype = UPIO_MEM, 93 .iotype = UPIO_MEM,
@@ -95,8 +95,8 @@ static struct plat_serial8250_port orion_uart_data[] = {
95 .uartclk = ORION_TCLK, 95 .uartclk = ORION_TCLK,
96 }, 96 },
97 { 97 {
98 .mapbase = UART1_BASE, 98 .mapbase = UART1_PHYS_BASE,
99 .membase = (char *)UART1_BASE, 99 .membase = (char *)UART1_VIRT_BASE,
100 .irq = IRQ_ORION_UART1, 100 .irq = IRQ_ORION_UART1,
101 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 101 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
102 .iotype = UPIO_MEM, 102 .iotype = UPIO_MEM,
@@ -122,8 +122,8 @@ static struct platform_device orion_uart = {
122 122
123static struct resource orion_ehci0_resources[] = { 123static struct resource orion_ehci0_resources[] = {
124 { 124 {
125 .start = ORION_USB0_REG_BASE, 125 .start = ORION_USB0_PHYS_BASE,
126 .end = ORION_USB0_REG_BASE + SZ_4K, 126 .end = ORION_USB0_PHYS_BASE + SZ_4K,
127 .flags = IORESOURCE_MEM, 127 .flags = IORESOURCE_MEM,
128 }, 128 },
129 { 129 {
@@ -135,8 +135,8 @@ static struct resource orion_ehci0_resources[] = {
135 135
136static struct resource orion_ehci1_resources[] = { 136static struct resource orion_ehci1_resources[] = {
137 { 137 {
138 .start = ORION_USB1_REG_BASE, 138 .start = ORION_USB1_PHYS_BASE,
139 .end = ORION_USB1_REG_BASE + SZ_4K, 139 .end = ORION_USB1_PHYS_BASE + SZ_4K,
140 .flags = IORESOURCE_MEM, 140 .flags = IORESOURCE_MEM,
141 }, 141 },
142 { 142 {
@@ -177,8 +177,8 @@ static struct platform_device orion_ehci1 = {
177 177
178static struct resource orion_eth_shared_resources[] = { 178static struct resource orion_eth_shared_resources[] = {
179 { 179 {
180 .start = ORION_ETH_REG_BASE, 180 .start = ORION_ETH_PHYS_BASE,
181 .end = ORION_ETH_REG_BASE + 0xffff, 181 .end = ORION_ETH_PHYS_BASE + 0xffff,
182 .flags = IORESOURCE_MEM, 182 .flags = IORESOURCE_MEM,
183 }, 183 },
184}; 184};
@@ -227,8 +227,8 @@ static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
227static struct resource orion_i2c_resources[] = { 227static struct resource orion_i2c_resources[] = {
228 { 228 {
229 .name = "i2c base", 229 .name = "i2c base",
230 .start = I2C_BASE, 230 .start = I2C_PHYS_BASE,
231 .end = I2C_BASE + 0x20 -1, 231 .end = I2C_PHYS_BASE + 0x20 -1,
232 .flags = IORESOURCE_MEM, 232 .flags = IORESOURCE_MEM,
233 }, 233 },
234 { 234 {
@@ -255,8 +255,8 @@ static struct platform_device orion_i2c = {
255static struct resource orion_sata_resources[] = { 255static struct resource orion_sata_resources[] = {
256 { 256 {
257 .name = "sata base", 257 .name = "sata base",
258 .start = ORION_SATA_REG_BASE, 258 .start = ORION_SATA_PHYS_BASE,
259 .end = ORION_SATA_REG_BASE + 0x5000 - 1, 259 .end = ORION_SATA_PHYS_BASE + 0x5000 - 1,
260 .flags = IORESOURCE_MEM, 260 .flags = IORESOURCE_MEM,
261 }, 261 },
262 { 262 {
diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c
index cb2a95ce5b57..5ef44e1a2d36 100644
--- a/arch/arm/mach-orion/db88f5281-setup.c
+++ b/arch/arm/mach-orion/db88f5281-setup.c
@@ -354,8 +354,8 @@ static void __init db88f5281_init(void)
354 354
355MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") 355MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
356 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ 356 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
357 .phys_io = ORION_REGS_BASE, 357 .phys_io = ORION_REGS_PHYS_BASE,
358 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc, 358 .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc,
359 .boot_params = 0x00000100, 359 .boot_params = 0x00000100,
360 .init_machine = db88f5281_init, 360 .init_machine = db88f5281_init,
361 .map_io = orion_map_io, 361 .map_io = orion_map_io,
diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c
index c8a806f249c6..02b280c24820 100644
--- a/arch/arm/mach-orion/dns323-setup.c
+++ b/arch/arm/mach-orion/dns323-setup.c
@@ -259,8 +259,8 @@ static void __init dns323_init(void)
259 * 259 *
260 * Open a special address decode windows for the PCIE WA. 260 * Open a special address decode windows for the PCIE WA.
261 */ 261 */
262 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 262 orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
263 orion_write(ORION_REGS_BASE | 0x20070, 263 orion_write(ORION_REGS_VIRT_BASE | 0x20070,
264 (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 264 (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
265 265
266 /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ 266 /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
@@ -312,8 +312,8 @@ static void __init dns323_init(void)
312/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ 312/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
313MACHINE_START(DNS323, "D-Link DNS-323") 313MACHINE_START(DNS323, "D-Link DNS-323")
314 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ 314 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
315 .phys_io = ORION_REGS_BASE, 315 .phys_io = ORION_REGS_PHYS_BASE,
316 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 316 .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
317 .boot_params = 0x00000100, 317 .boot_params = 0x00000100,
318 .init_machine = dns323_init, 318 .init_machine = dns323_init,
319 .map_io = orion_map_io, 319 .map_io = orion_map_io,
diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c
index 2d812ed6b5c7..9bdd987edbb6 100644
--- a/arch/arm/mach-orion/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion/kurobox_pro-setup.c
@@ -192,8 +192,8 @@ static void __init kurobox_pro_init(void)
192 /* 192 /*
193 * Open a special address decode windows for the PCIE WA. 193 * Open a special address decode windows for the PCIE WA.
194 */ 194 */
195 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 195 orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
196 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 196 orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
197 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 197 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
198 198
199 /* 199 /*
@@ -224,8 +224,8 @@ static void __init kurobox_pro_init(void)
224 224
225MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") 225MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
226 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 226 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
227 .phys_io = ORION_REGS_BASE, 227 .phys_io = ORION_REGS_PHYS_BASE,
228 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 228 .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
229 .boot_params = 0x00000100, 229 .boot_params = 0x00000100,
230 .init_machine = kurobox_pro_init, 230 .init_machine = kurobox_pro_init,
231 .map_io = orion_map_io, 231 .map_io = orion_map_io,
diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c
index 0498d7c69b30..b109bb46681e 100644
--- a/arch/arm/mach-orion/pci.c
+++ b/arch/arm/mach-orion/pci.c
@@ -156,7 +156,7 @@ static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
156 orion_pcie_id(&dev, &rev); 156 orion_pcie_id(&dev, &rev);
157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 /* extended register space */ 158 /* extended register space */
159 pcie_addr = ORION_PCIE_WA_BASE; 159 pcie_addr = ORION_PCIE_WA_VIRT_BASE;
160 pcie_addr |= PCIE_CONF_BUS(bus->number) | 160 pcie_addr |= PCIE_CONF_BUS(bus->number) |
161 PCIE_CONF_DEV(PCI_SLOT(devfn)) | 161 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
162 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | 162 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
@@ -241,7 +241,7 @@ static int orion_pcie_setup(struct pci_sys_data *sys)
241 */ 241 */
242 res[0].name = "PCI-EX I/O Space"; 242 res[0].name = "PCI-EX I/O Space";
243 res[0].flags = IORESOURCE_IO; 243 res[0].flags = IORESOURCE_IO;
244 res[0].start = ORION_PCIE_IO_REMAP; 244 res[0].start = ORION_PCIE_IO_BUS_BASE;
245 res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; 245 res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
246 if (request_resource(&ioport_resource, &res[0])) 246 if (request_resource(&ioport_resource, &res[0]))
247 panic("Request PCIE IO resource failed\n"); 247 panic("Request PCIE IO resource failed\n");
@@ -252,7 +252,7 @@ static int orion_pcie_setup(struct pci_sys_data *sys)
252 */ 252 */
253 res[1].name = "PCI-EX Memory Space"; 253 res[1].name = "PCI-EX Memory Space";
254 res[1].flags = IORESOURCE_MEM; 254 res[1].flags = IORESOURCE_MEM;
255 res[1].start = ORION_PCIE_MEM_BASE; 255 res[1].start = ORION_PCIE_MEM_PHYS_BASE;
256 res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; 256 res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
257 if (request_resource(&iomem_resource, &res[1])) 257 if (request_resource(&iomem_resource, &res[1]))
258 panic("Request PCIE Memory resource failed\n"); 258 panic("Request PCIE Memory resource failed\n");
@@ -477,7 +477,7 @@ static int orion_pci_setup(struct pci_sys_data *sys)
477 */ 477 */
478 res[0].name = "PCI I/O Space"; 478 res[0].name = "PCI I/O Space";
479 res[0].flags = IORESOURCE_IO; 479 res[0].flags = IORESOURCE_IO;
480 res[0].start = ORION_PCI_IO_REMAP; 480 res[0].start = ORION_PCI_IO_BUS_BASE;
481 res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; 481 res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
482 if (request_resource(&ioport_resource, &res[0])) 482 if (request_resource(&ioport_resource, &res[0]))
483 panic("Request PCI IO resource failed\n"); 483 panic("Request PCI IO resource failed\n");
@@ -488,7 +488,7 @@ static int orion_pci_setup(struct pci_sys_data *sys)
488 */ 488 */
489 res[1].name = "PCI Memory Space"; 489 res[1].name = "PCI Memory Space";
490 res[1].flags = IORESOURCE_MEM; 490 res[1].flags = IORESOURCE_MEM;
491 res[1].start = ORION_PCI_MEM_BASE; 491 res[1].start = ORION_PCI_MEM_PHYS_BASE;
492 res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; 492 res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
493 if (request_resource(&iomem_resource, &res[1])) 493 if (request_resource(&iomem_resource, &res[1]))
494 panic("Request PCI Memory resource failed\n"); 494 panic("Request PCI Memory resource failed\n");
diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c
index 797c54c80c2b..e851b8ca5ac6 100644
--- a/arch/arm/mach-orion/rd88f5182-setup.c
+++ b/arch/arm/mach-orion/rd88f5182-setup.c
@@ -263,8 +263,8 @@ static void __init rd88f5182_init(void)
263 /* 263 /*
264 * Open a special address decode windows for the PCIE WA. 264 * Open a special address decode windows for the PCIE WA.
265 */ 265 */
266 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 266 orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
267 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 267 orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
268 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 268 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
269 269
270 /* 270 /*
@@ -305,8 +305,8 @@ static void __init rd88f5182_init(void)
305 305
306MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") 306MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
307 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 307 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
308 .phys_io = ORION_REGS_BASE, 308 .phys_io = ORION_REGS_PHYS_BASE,
309 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 309 .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
310 .boot_params = 0x00000100, 310 .boot_params = 0x00000100,
311 .init_machine = rd88f5182_init, 311 .init_machine = rd88f5182_init,
312 .map_io = orion_map_io, 312 .map_io = orion_map_io,
diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c
index e3e930efd155..8edb2ac09662 100644
--- a/arch/arm/mach-orion/ts209-setup.c
+++ b/arch/arm/mach-orion/ts209-setup.c
@@ -244,7 +244,7 @@ static struct platform_device *qnap_ts209_devices[] __initdata = {
244 * QNAP TS-[12]09 specific power off method via UART1-attached PIC 244 * QNAP TS-[12]09 specific power off method via UART1-attached PIC
245 */ 245 */
246 246
247#define UART1_REG(x) (UART1_BASE + ((UART_##x) << 2)) 247#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
248 248
249static void qnap_ts209_power_off(void) 249static void qnap_ts209_power_off(void)
250{ 250{
@@ -282,8 +282,8 @@ static void __init qnap_ts209_init(void)
282 /* 282 /*
283 * Open a special address decode windows for the PCIE WA. 283 * Open a special address decode windows for the PCIE WA.
284 */ 284 */
285 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 285 orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
286 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 286 orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
287 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 287 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
288 288
289 /* 289 /*
@@ -325,8 +325,8 @@ static void __init qnap_ts209_init(void)
325 325
326MACHINE_START(TS209, "QNAP TS-109/TS-209") 326MACHINE_START(TS209, "QNAP TS-109/TS-209")
327 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ 327 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
328 .phys_io = ORION_REGS_BASE, 328 .phys_io = ORION_REGS_PHYS_BASE,
329 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 329 .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
330 .boot_params = 0x00000100, 330 .boot_params = 0x00000100,
331 .init_machine = qnap_ts209_init, 331 .init_machine = qnap_ts209_init,
332 .map_io = orion_map_io, 332 .map_io = orion_map_io,
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S
index e2a80641f214..2746220f5d85 100644
--- a/include/asm-arm/arch-orion/debug-macro.S
+++ b/include/asm-arm/arch-orion/debug-macro.S
@@ -8,9 +8,14 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9*/ 9*/
10 10
11#include <asm/arch/orion.h>
12
11 .macro addruart,rx 13 .macro addruart,rx
12 mov \rx, #0xf1000000 14 mrc p15, 0, \rx, c1, c0
13 orr \rx, \rx, #0x00012000 15 tst \rx, #1 @ MMU enabled?
16 ldreq \rx, =ORION_REGS_PHYS_BASE
17 ldrne \rx, =ORION_REGS_VIRT_BASE
18 orr \rx, \rx, #0x00012000
14 .endm 19 .endm
15 20
16#define UART_SHIFT 2 21#define UART_SHIFT 2
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion/entry-macro.S
index b76075a7e44b..cda096b2acfd 100644
--- a/include/asm-arm/arch-orion/entry-macro.S
+++ b/include/asm-arm/arch-orion/entry-macro.S
@@ -3,8 +3,8 @@
3 * 3 *
4 * Low-level IRQ helper macros for Orion platforms 4 * Low-level IRQ helper macros for Orion platforms
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any 7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 10
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h
index 8a12d213fbdc..65da374de735 100644
--- a/include/asm-arm/arch-orion/hardware.h
+++ b/include/asm-arm/arch-orion/hardware.h
@@ -4,7 +4,6 @@
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 *
8 */ 7 */
9 8
10#ifndef __ASM_ARCH_HARDWARE_H__ 9#ifndef __ASM_ARCH_HARDWARE_H__
@@ -12,13 +11,11 @@
12 11
13#include "orion.h" 12#include "orion.h"
14 13
15#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE 14#define pcibios_assign_all_busses() 1
16#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
17 15
18#define pcibios_assign_all_busses() 1 16#define PCIBIOS_MIN_IO 0x00001000
17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE
19 19
20#define PCIBIOS_MIN_IO 0x1000
21#define PCIBIOS_MIN_MEM 0x01000000
22#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
23 20
24#endif /* _ASM_ARCH_HARDWARE_H */ 21#endif
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
index f787f752e58c..4a8025466a33 100644
--- a/include/asm-arm/arch-orion/orion.h
+++ b/include/asm-arm/arch-orion/orion.h
@@ -14,32 +14,40 @@
14#ifndef __ASM_ARCH_ORION_H__ 14#ifndef __ASM_ARCH_ORION_H__
15#define __ASM_ARCH_ORION_H__ 15#define __ASM_ARCH_ORION_H__
16 16
17/******************************************************************************* 17/*****************************************************************************
18 * Orion Address Map 18 * Orion Address Map
19 * Use the same mapping (1:1 virtual:physical) of internal registers and 19 *
20 * PCI system (PCI+PCIE) for all machines. 20 * virt phys size
21 * Each machine defines the rest of its mapping (e.g. device bus flashes) 21 * f0000000 f0000000 16M PCIe WA space (Orion-NAS only)
22 ******************************************************************************/ 22 * f1000000 f1000000 1M on-chip peripheral registers
23#define ORION_REGS_BASE 0xf1000000 23 * f2000000 f2000000 1M PCIe I/O space
24 * f2100000 f2100000 1M PCI I/O space
25 ****************************************************************************/
26#define ORION_REGS_PHYS_BASE 0xf1000000
27#define ORION_REGS_VIRT_BASE 0xf1000000
24#define ORION_REGS_SIZE SZ_1M 28#define ORION_REGS_SIZE SZ_1M
25 29
26#define ORION_PCI_SYS_MEM_BASE 0xe0000000 30#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
27#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE 31#define ORION_PCIE_IO_VIRT_BASE 0xf2000000
28#define ORION_PCIE_MEM_SIZE SZ_128M 32#define ORION_PCIE_IO_BUS_BASE 0x00000000
29#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
30#define ORION_PCI_MEM_SIZE SZ_128M
31
32#define ORION_PCI_SYS_IO_BASE 0xf2000000
33#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
34#define ORION_PCIE_IO_SIZE SZ_1M 33#define ORION_PCIE_IO_SIZE SZ_1M
35#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE) 34
36#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE) 35#define ORION_PCI_IO_PHYS_BASE 0xf2100000
36#define ORION_PCI_IO_VIRT_BASE 0xf2100000
37#define ORION_PCI_IO_BUS_BASE 0x00100000
37#define ORION_PCI_IO_SIZE SZ_1M 38#define ORION_PCI_IO_SIZE SZ_1M
38#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE) 39
39/* Relevant only for Orion-NAS */ 40/* Relevant only for Orion-NAS */
40#define ORION_PCIE_WA_BASE 0xf0000000 41#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
42#define ORION_PCIE_WA_VIRT_BASE 0xf0000000
41#define ORION_PCIE_WA_SIZE SZ_16M 43#define ORION_PCIE_WA_SIZE SZ_16M
42 44
45#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000
46#define ORION_PCIE_MEM_SIZE SZ_128M
47
48#define ORION_PCI_MEM_PHYS_BASE 0xe8000000
49#define ORION_PCI_MEM_SIZE SZ_128M
50
43/******************************************************************************* 51/*******************************************************************************
44 * Supported Devices & Revisions 52 * Supported Devices & Revisions
45 ******************************************************************************/ 53 ******************************************************************************/
@@ -57,25 +65,42 @@
57/******************************************************************************* 65/*******************************************************************************
58 * Orion Registers Map 66 * Orion Registers Map
59 ******************************************************************************/ 67 ******************************************************************************/
60#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000) 68#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000)
61#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000) 69#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x))
62#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000) 70
63#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000) 71#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000)
64#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000) 72#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000)
65#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000) 73#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x))
66#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000) 74#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000)
67#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000) 75#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000)
68#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000) 76#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000)
69 77#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100)
70#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x)) 78#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100)
71#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x)) 79
72#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x)) 80#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
73#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x)) 81#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
74#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x)) 82
75#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x)) 83#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
76#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x)) 84#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
77#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x)) 85
78#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x)) 86#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000)
87#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x))
88
89#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000)
90#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000)
91#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x))
92
93#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000)
94#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000)
95#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x))
96
97#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000)
98#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000)
99#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x))
100
101#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000)
102#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000)
103#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x))
79 104
80/******************************************************************************* 105/*******************************************************************************
81 * Device Bus Registers 106 * Device Bus Registers
@@ -100,9 +125,6 @@
100#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) 125#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
101#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) 126#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
102#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) 127#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
103#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
104#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
105#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
106#define GPIO_MAX 32 128#define GPIO_MAX 32
107 129
108/*************************************************************************** 130/***************************************************************************
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h
index 0cab78ad6332..59f44039909a 100644
--- a/include/asm-arm/arch-orion/uncompress.h
+++ b/include/asm-arm/arch-orion/uncompress.h
@@ -10,8 +10,8 @@
10 10
11#include <asm/arch/orion.h> 11#include <asm/arch/orion.h>
12 12
13#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14)) 13#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
14#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0)) 14#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
15 15
16#define LSR_THRE 0x20 16#define LSR_THRE 0x20
17 17
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 05:36:21 -0500