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-rw-r--r--Documentation/DocBook/kernel-api.tmpl4
-rw-r--r--arch/i386/pci/fixup.c59
-rw-r--r--drivers/pci/access.c89
-rw-r--r--drivers/pci/hotplug/acpiphp_glue.c8
-rw-r--r--drivers/pci/hotplug/cpcihp_zt5550.c25
-rw-r--r--drivers/pci/hotplug/cpqphp_core.c24
-rw-r--r--drivers/pci/hotplug/rpaphp.h3
-rw-r--r--drivers/pci/hotplug/rpaphp_core.c5
-rw-r--r--drivers/pci/hotplug/rpaphp_pci.c11
-rw-r--r--drivers/pci/hotplug/shpchp.h122
-rw-r--r--drivers/pci/hotplug/shpchp_core.c111
-rw-r--r--drivers/pci/hotplug/shpchp_ctrl.c2034
-rw-r--r--drivers/pci/hotplug/shpchp_hpc.c175
-rw-r--r--drivers/pci/hotplug/shpchp_pci.c861
-rw-r--r--drivers/pci/hotplug/shpchp_sysfs.c119
-rw-r--r--drivers/pci/hotplug/shpchprm.h55
-rw-r--r--drivers/pci/hotplug/shpchprm_acpi.c1649
-rw-r--r--drivers/pci/hotplug/shpchprm_legacy.c395
-rw-r--r--drivers/pci/hotplug/shpchprm_legacy.h113
-rw-r--r--drivers/pci/hotplug/shpchprm_nonacpi.c389
-rw-r--r--drivers/pci/hotplug/shpchprm_nonacpi.h56
-rw-r--r--drivers/pci/msi.c2
-rw-r--r--drivers/pci/pci-driver.c17
-rw-r--r--drivers/pci/pci-sysfs.c20
-rw-r--r--drivers/pci/pci.c21
-rw-r--r--drivers/pci/pci.h7
-rw-r--r--drivers/pci/probe.c1
-rw-r--r--drivers/pci/proc.c28
-rw-r--r--drivers/pci/quirks.c37
-rw-r--r--drivers/pci/syscall.c14
-rw-r--r--drivers/scsi/ipr.c2
-rw-r--r--drivers/scsi/megaraid/megaraid_mbox.c10
-rw-r--r--drivers/video/cirrusfb.c24
-rw-r--r--include/linux/pci.h7
-rw-r--r--include/linux/pci_ids.h563
-rw-r--r--sound/oss/ymfpci.c17
-rw-r--r--sound/pci/bt87x.c11
37 files changed, 739 insertions, 6349 deletions
diff --git a/Documentation/DocBook/kernel-api.tmpl b/Documentation/DocBook/kernel-api.tmpl
index d650ce36485f..4d9b66d8b4db 100644
--- a/Documentation/DocBook/kernel-api.tmpl
+++ b/Documentation/DocBook/kernel-api.tmpl
@@ -286,7 +286,9 @@ X!Edrivers/pci/search.c
286 --> 286 -->
287!Edrivers/pci/msi.c 287!Edrivers/pci/msi.c
288!Edrivers/pci/bus.c 288!Edrivers/pci/bus.c
289!Edrivers/pci/hotplug.c 289<!-- FIXME: Removed for now since no structured comments in source
290X!Edrivers/pci/hotplug.c
291-->
290!Edrivers/pci/probe.c 292!Edrivers/pci/probe.c
291!Edrivers/pci/rom.c 293!Edrivers/pci/rom.c
292 </sect1> 294 </sect1>
diff --git a/arch/i386/pci/fixup.c b/arch/i386/pci/fixup.c
index 8e8e895e1b5a..330fd2b68075 100644
--- a/arch/i386/pci/fixup.c
+++ b/arch/i386/pci/fixup.c
@@ -2,6 +2,8 @@
2 * Exceptions for specific devices. Usually work-arounds for fatal design flaws. 2 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
3 */ 3 */
4 4
5#include <linux/delay.h>
6#include <linux/dmi.h>
5#include <linux/pci.h> 7#include <linux/pci.h>
6#include <linux/init.h> 8#include <linux/init.h>
7#include "pci.h" 9#include "pci.h"
@@ -384,3 +386,60 @@ static void __devinit pci_fixup_video(struct pci_dev *pdev)
384 } 386 }
385} 387}
386DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video); 388DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
389
390/*
391 * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
392 *
393 * We pretend to bring them out of full D3 state, and restore the proper
394 * IRQ, PCI cache line size, and BARs, otherwise the device won't function
395 * properly. In some cases, the device will generate an interrupt on
396 * the wrong IRQ line, causing any devices sharing the the line it's
397 * *supposed* to use to be disabled by the kernel's IRQ debug code.
398 */
399static u16 toshiba_line_size;
400
401static struct dmi_system_id __devinit toshiba_ohci1394_dmi_table[] = {
402 {
403 .ident = "Toshiba PS5 based laptop",
404 .matches = {
405 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
406 DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
407 },
408 },
409 {
410 .ident = "Toshiba PSM4 based laptop",
411 .matches = {
412 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
413 DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
414 },
415 },
416 { }
417};
418
419static void __devinit pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
420{
421 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
422 return; /* only applies to certain Toshibas (so far) */
423
424 dev->current_state = PCI_D3cold;
425 pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
426}
427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
428 pci_pre_fixup_toshiba_ohci1394);
429
430static void __devinit pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
431{
432 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
433 return; /* only applies to certain Toshibas (so far) */
434
435 /* Restore config space on Toshiba laptops */
436 mdelay(10);
437 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
438 pci_write_config_word(dev, PCI_INTERRUPT_LINE, dev->irq);
439 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
440 pci_resource_start(dev, 0));
441 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
442 pci_resource_start(dev, 1));
443}
444DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
445 pci_post_fixup_toshiba_ohci1394);
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 24a76de49f41..2a42add7f563 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -60,3 +60,92 @@ EXPORT_SYMBOL(pci_bus_read_config_dword);
60EXPORT_SYMBOL(pci_bus_write_config_byte); 60EXPORT_SYMBOL(pci_bus_write_config_byte);
61EXPORT_SYMBOL(pci_bus_write_config_word); 61EXPORT_SYMBOL(pci_bus_write_config_word);
62EXPORT_SYMBOL(pci_bus_write_config_dword); 62EXPORT_SYMBOL(pci_bus_write_config_dword);
63
64static u32 pci_user_cached_config(struct pci_dev *dev, int pos)
65{
66 u32 data;
67
68 data = dev->saved_config_space[pos/sizeof(dev->saved_config_space[0])];
69 data >>= (pos % sizeof(dev->saved_config_space[0])) * 8;
70 return data;
71}
72
73#define PCI_USER_READ_CONFIG(size,type) \
74int pci_user_read_config_##size \
75 (struct pci_dev *dev, int pos, type *val) \
76{ \
77 unsigned long flags; \
78 int ret = 0; \
79 u32 data = -1; \
80 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
81 spin_lock_irqsave(&pci_lock, flags); \
82 if (likely(!dev->block_ucfg_access)) \
83 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
84 pos, sizeof(type), &data); \
85 else if (pos < sizeof(dev->saved_config_space)) \
86 data = pci_user_cached_config(dev, pos); \
87 spin_unlock_irqrestore(&pci_lock, flags); \
88 *val = (type)data; \
89 return ret; \
90}
91
92#define PCI_USER_WRITE_CONFIG(size,type) \
93int pci_user_write_config_##size \
94 (struct pci_dev *dev, int pos, type val) \
95{ \
96 unsigned long flags; \
97 int ret = -EIO; \
98 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
99 spin_lock_irqsave(&pci_lock, flags); \
100 if (likely(!dev->block_ucfg_access)) \
101 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
102 pos, sizeof(type), val); \
103 spin_unlock_irqrestore(&pci_lock, flags); \
104 return ret; \
105}
106
107PCI_USER_READ_CONFIG(byte, u8)
108PCI_USER_READ_CONFIG(word, u16)
109PCI_USER_READ_CONFIG(dword, u32)
110PCI_USER_WRITE_CONFIG(byte, u8)
111PCI_USER_WRITE_CONFIG(word, u16)
112PCI_USER_WRITE_CONFIG(dword, u32)
113
114/**
115 * pci_block_user_cfg_access - Block userspace PCI config reads/writes
116 * @dev: pci device struct
117 *
118 * This function blocks any userspace PCI config accesses from occurring.
119 * When blocked, any writes will be bit bucketed and reads will return the
120 * data saved using pci_save_state for the first 64 bytes of config
121 * space and return 0xff for all other config reads.
122 **/
123void pci_block_user_cfg_access(struct pci_dev *dev)
124{
125 unsigned long flags;
126
127 pci_save_state(dev);
128
129 /* spinlock to synchronize with anyone reading config space now */
130 spin_lock_irqsave(&pci_lock, flags);
131 dev->block_ucfg_access = 1;
132 spin_unlock_irqrestore(&pci_lock, flags);
133}
134EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
135
136/**
137 * pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes
138 * @dev: pci device struct
139 *
140 * This function allows userspace PCI config accesses to resume.
141 **/
142void pci_unblock_user_cfg_access(struct pci_dev *dev)
143{
144 unsigned long flags;
145
146 /* spinlock to synchronize with anyone reading saved config space */
147 spin_lock_irqsave(&pci_lock, flags);
148 dev->block_ucfg_access = 0;
149 spin_unlock_irqrestore(&pci_lock, flags);
150}
151EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 424e7de181ae..8e21f6ab89a1 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -58,6 +58,9 @@ static LIST_HEAD(bridge_list);
58 58
59static void handle_hotplug_event_bridge (acpi_handle, u32, void *); 59static void handle_hotplug_event_bridge (acpi_handle, u32, void *);
60static void handle_hotplug_event_func (acpi_handle, u32, void *); 60static void handle_hotplug_event_func (acpi_handle, u32, void *);
61static void acpiphp_sanitize_bus(struct pci_bus *bus);
62static void acpiphp_set_hpp_values(acpi_handle handle, struct pci_bus *bus);
63
61 64
62/* 65/*
63 * initialization & terminatation routines 66 * initialization & terminatation routines
@@ -796,8 +799,13 @@ static int enable_device(struct acpiphp_slot *slot)
796 } 799 }
797 } 800 }
798 801
802 pci_bus_size_bridges(bus);
799 pci_bus_assign_resources(bus); 803 pci_bus_assign_resources(bus);
804 acpiphp_sanitize_bus(bus);
805 pci_enable_bridges(bus);
800 pci_bus_add_devices(bus); 806 pci_bus_add_devices(bus);
807 acpiphp_set_hpp_values(DEVICE_ACPI_HANDLE(&bus->self->dev), bus);
808 acpiphp_configure_ioapics(DEVICE_ACPI_HANDLE(&bus->self->dev));
801 809
802 /* associate pci_dev to our representation */ 810 /* associate pci_dev to our representation */
803 list_for_each (l, &slot->funcs) { 811 list_for_each (l, &slot->funcs) {
diff --git a/drivers/pci/hotplug/cpcihp_zt5550.c b/drivers/pci/hotplug/cpcihp_zt5550.c
index e9928024be78..790abadd816c 100644
--- a/drivers/pci/hotplug/cpcihp_zt5550.c
+++ b/drivers/pci/hotplug/cpcihp_zt5550.c
@@ -78,11 +78,20 @@ static void __iomem *csr_int_mask;
78 78
79static int zt5550_hc_config(struct pci_dev *pdev) 79static int zt5550_hc_config(struct pci_dev *pdev)
80{ 80{
81 int ret;
82
81 /* Since we know that no boards exist with two HC chips, treat it as an error */ 83 /* Since we know that no boards exist with two HC chips, treat it as an error */
82 if(hc_dev) { 84 if(hc_dev) {
83 err("too many host controller devices?"); 85 err("too many host controller devices?");
84 return -EBUSY; 86 return -EBUSY;
85 } 87 }
88
89 ret = pci_enable_device(pdev);
90 if(ret) {
91 err("cannot enable %s\n", pci_name(pdev));
92 return ret;
93 }
94
86 hc_dev = pdev; 95 hc_dev = pdev;
87 dbg("hc_dev = %p", hc_dev); 96 dbg("hc_dev = %p", hc_dev);
88 dbg("pci resource start %lx", pci_resource_start(hc_dev, 1)); 97 dbg("pci resource start %lx", pci_resource_start(hc_dev, 1));
@@ -91,7 +100,8 @@ static int zt5550_hc_config(struct pci_dev *pdev)
91 if(!request_mem_region(pci_resource_start(hc_dev, 1), 100 if(!request_mem_region(pci_resource_start(hc_dev, 1),
92 pci_resource_len(hc_dev, 1), MY_NAME)) { 101 pci_resource_len(hc_dev, 1), MY_NAME)) {
93 err("cannot reserve MMIO region"); 102 err("cannot reserve MMIO region");
94 return -ENOMEM; 103 ret = -ENOMEM;
104 goto exit_disable_device;
95 } 105 }
96 106
97 hc_registers = 107 hc_registers =
@@ -99,9 +109,8 @@ static int zt5550_hc_config(struct pci_dev *pdev)
99 if(!hc_registers) { 109 if(!hc_registers) {
100 err("cannot remap MMIO region %lx @ %lx", 110 err("cannot remap MMIO region %lx @ %lx",
101 pci_resource_len(hc_dev, 1), pci_resource_start(hc_dev, 1)); 111 pci_resource_len(hc_dev, 1), pci_resource_start(hc_dev, 1));
102 release_mem_region(pci_resource_start(hc_dev, 1), 112 ret = -ENODEV;
103 pci_resource_len(hc_dev, 1)); 113 goto exit_release_region;
104 return -ENODEV;
105 } 114 }
106 115
107 csr_hc_index = hc_registers + CSR_HCINDEX; 116 csr_hc_index = hc_registers + CSR_HCINDEX;
@@ -124,6 +133,13 @@ static int zt5550_hc_config(struct pci_dev *pdev)
124 writeb((u8) ALL_DIRECT_INTS_MASK, csr_int_mask); 133 writeb((u8) ALL_DIRECT_INTS_MASK, csr_int_mask);
125 dbg("disabled timer0, timer1 and ENUM interrupts"); 134 dbg("disabled timer0, timer1 and ENUM interrupts");
126 return 0; 135 return 0;
136
137exit_release_region:
138 release_mem_region(pci_resource_start(hc_dev, 1),
139 pci_resource_len(hc_dev, 1));
140exit_disable_device:
141 pci_disable_device(hc_dev);
142 return ret;
127} 143}
128 144
129static int zt5550_hc_cleanup(void) 145static int zt5550_hc_cleanup(void)
@@ -134,6 +150,7 @@ static int zt5550_hc_cleanup(void)
134 iounmap(hc_registers); 150 iounmap(hc_registers);
135 release_mem_region(pci_resource_start(hc_dev, 1), 151 release_mem_region(pci_resource_start(hc_dev, 1),
136 pci_resource_len(hc_dev, 1)); 152 pci_resource_len(hc_dev, 1));
153 pci_disable_device(hc_dev);
137 return 0; 154 return 0;
138} 155}
139 156
diff --git a/drivers/pci/hotplug/cpqphp_core.c b/drivers/pci/hotplug/cpqphp_core.c
index 8c6d3987d461..9aed8efe6a11 100644
--- a/drivers/pci/hotplug/cpqphp_core.c
+++ b/drivers/pci/hotplug/cpqphp_core.c
@@ -794,12 +794,21 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
794 u32 rc; 794 u32 rc;
795 struct controller *ctrl; 795 struct controller *ctrl;
796 struct pci_func *func; 796 struct pci_func *func;
797 int err;
798
799 err = pci_enable_device(pdev);
800 if (err) {
801 printk(KERN_ERR MY_NAME ": cannot enable PCI device %s (%d)\n",
802 pci_name(pdev), err);
803 return err;
804 }
797 805
798 // Need to read VID early b/c it's used to differentiate CPQ and INTC discovery 806 // Need to read VID early b/c it's used to differentiate CPQ and INTC discovery
799 rc = pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor_id); 807 rc = pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor_id);
800 if (rc || ((vendor_id != PCI_VENDOR_ID_COMPAQ) && (vendor_id != PCI_VENDOR_ID_INTEL))) { 808 if (rc || ((vendor_id != PCI_VENDOR_ID_COMPAQ) && (vendor_id != PCI_VENDOR_ID_INTEL))) {
801 err(msg_HPC_non_compaq_or_intel); 809 err(msg_HPC_non_compaq_or_intel);
802 return -ENODEV; 810 rc = -ENODEV;
811 goto err_disable_device;
803 } 812 }
804 dbg("Vendor ID: %x\n", vendor_id); 813 dbg("Vendor ID: %x\n", vendor_id);
805 814
@@ -807,7 +816,8 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
807 dbg("revision: %d\n", rev); 816 dbg("revision: %d\n", rev);
808 if (rc || ((vendor_id == PCI_VENDOR_ID_COMPAQ) && (!rev))) { 817 if (rc || ((vendor_id == PCI_VENDOR_ID_COMPAQ) && (!rev))) {
809 err(msg_HPC_rev_error); 818 err(msg_HPC_rev_error);
810 return -ENODEV; 819 rc = -ENODEV;
820 goto err_disable_device;
811 } 821 }
812 822
813 /* Check for the proper subsytem ID's 823 /* Check for the proper subsytem ID's
@@ -820,18 +830,20 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
820 rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vid); 830 rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vid);
821 if (rc) { 831 if (rc) {
822 err("%s : pci_read_config_word failed\n", __FUNCTION__); 832 err("%s : pci_read_config_word failed\n", __FUNCTION__);
823 return rc; 833 goto err_disable_device;
824 } 834 }
825 dbg("Subsystem Vendor ID: %x\n", subsystem_vid); 835 dbg("Subsystem Vendor ID: %x\n", subsystem_vid);
826 if ((subsystem_vid != PCI_VENDOR_ID_COMPAQ) && (subsystem_vid != PCI_VENDOR_ID_INTEL)) { 836 if ((subsystem_vid != PCI_VENDOR_ID_COMPAQ) && (subsystem_vid != PCI_VENDOR_ID_INTEL)) {
827 err(msg_HPC_non_compaq_or_intel); 837 err(msg_HPC_non_compaq_or_intel);
828 return -ENODEV; 838 rc = -ENODEV;
839 goto err_disable_device;
829 } 840 }
830 841
831 ctrl = (struct controller *) kmalloc(sizeof(struct controller), GFP_KERNEL); 842 ctrl = (struct controller *) kmalloc(sizeof(struct controller), GFP_KERNEL);
832 if (!ctrl) { 843 if (!ctrl) {
833 err("%s : out of memory\n", __FUNCTION__); 844 err("%s : out of memory\n", __FUNCTION__);
834 return -ENOMEM; 845 rc = -ENOMEM;
846 goto err_disable_device;
835 } 847 }
836 memset(ctrl, 0, sizeof(struct controller)); 848 memset(ctrl, 0, sizeof(struct controller));
837 849
@@ -1264,6 +1276,8 @@ err_free_bus:
1264 kfree(ctrl->pci_bus); 1276 kfree(ctrl->pci_bus);
1265err_free_ctrl: 1277err_free_ctrl:
1266 kfree(ctrl); 1278 kfree(ctrl);
1279err_disable_device:
1280 pci_disable_device(pdev);
1267 return rc; 1281 return rc;
1268} 1282}
1269 1283
diff --git a/drivers/pci/hotplug/rpaphp.h b/drivers/pci/hotplug/rpaphp.h
index 61d94d1e29cb..71ea5f9bb284 100644
--- a/drivers/pci/hotplug/rpaphp.h
+++ b/drivers/pci/hotplug/rpaphp.h
@@ -92,9 +92,10 @@ extern struct pci_bus *rpaphp_find_pci_bus(struct device_node *dn);
92extern int rpaphp_claim_resource(struct pci_dev *dev, int resource); 92extern int rpaphp_claim_resource(struct pci_dev *dev, int resource);
93extern int rpaphp_enable_pci_slot(struct slot *slot); 93extern int rpaphp_enable_pci_slot(struct slot *slot);
94extern int register_pci_slot(struct slot *slot); 94extern int register_pci_slot(struct slot *slot);
95extern int rpaphp_unconfig_pci_adapter(struct slot *slot);
96extern int rpaphp_get_pci_adapter_status(struct slot *slot, int is_init, u8 * value); 95extern int rpaphp_get_pci_adapter_status(struct slot *slot, int is_init, u8 * value);
96
97extern int rpaphp_config_pci_adapter(struct pci_bus *bus); 97extern int rpaphp_config_pci_adapter(struct pci_bus *bus);
98extern int rpaphp_unconfig_pci_adapter(struct pci_bus *bus);
98 99
99/* rpaphp_core.c */ 100/* rpaphp_core.c */
100extern int rpaphp_add_slot(struct device_node *dn); 101extern int rpaphp_add_slot(struct device_node *dn);
diff --git a/drivers/pci/hotplug/rpaphp_core.c b/drivers/pci/hotplug/rpaphp_core.c
index c830ff0acdc3..cf075c34b578 100644
--- a/drivers/pci/hotplug/rpaphp_core.c
+++ b/drivers/pci/hotplug/rpaphp_core.c
@@ -426,8 +426,11 @@ static int disable_slot(struct hotplug_slot *hotplug_slot)
426 426
427 dbg("DISABLING SLOT %s\n", slot->name); 427 dbg("DISABLING SLOT %s\n", slot->name);
428 down(&rpaphp_sem); 428 down(&rpaphp_sem);
429 retval = rpaphp_unconfig_pci_adapter(slot); 429 retval = rpaphp_unconfig_pci_adapter(slot->bus);
430 up(&rpaphp_sem); 430 up(&rpaphp_sem);
431 slot->state = NOT_CONFIGURED;
432 info("%s: devices in slot[%s] unconfigured.\n", __FUNCTION__,
433 slot->name);
431exit: 434exit:
432 dbg("%s - Exit: rc[%d]\n", __FUNCTION__, retval); 435 dbg("%s - Exit: rc[%d]\n", __FUNCTION__, retval);
433 return retval; 436 return retval;
diff --git a/drivers/pci/hotplug/rpaphp_pci.c b/drivers/pci/hotplug/rpaphp_pci.c
index 49e4d10a6488..46c157d26a2f 100644
--- a/drivers/pci/hotplug/rpaphp_pci.c
+++ b/drivers/pci/hotplug/rpaphp_pci.c
@@ -319,20 +319,15 @@ static void rpaphp_eeh_remove_bus_device(struct pci_dev *dev)
319 return; 319 return;
320} 320}
321 321
322int rpaphp_unconfig_pci_adapter(struct slot *slot) 322int rpaphp_unconfig_pci_adapter(struct pci_bus *bus)
323{ 323{
324 struct pci_dev *dev, *tmp; 324 struct pci_dev *dev, *tmp;
325 int retval = 0;
326 325
327 list_for_each_entry_safe(dev, tmp, slot->pci_devs, bus_list) { 326 list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
328 rpaphp_eeh_remove_bus_device(dev); 327 rpaphp_eeh_remove_bus_device(dev);
329 pci_remove_bus_device(dev); 328 pci_remove_bus_device(dev);
330 } 329 }
331 330 return 0;
332 slot->state = NOT_CONFIGURED;
333 info("%s: devices in slot[%s] unconfigured.\n", __FUNCTION__,
334 slot->name);
335 return retval;
336} 331}
337 332
338static int setup_pci_hotplug_slot_info(struct slot *slot) 333static int setup_pci_hotplug_slot_info(struct slot *slot)
diff --git a/drivers/pci/hotplug/shpchp.h b/drivers/pci/hotplug/shpchp.h
index b7d1c61d6bbb..abe2cf411e68 100644
--- a/drivers/pci/hotplug/shpchp.h
+++ b/drivers/pci/hotplug/shpchp.h
@@ -32,8 +32,6 @@
32#include <linux/types.h> 32#include <linux/types.h>
33#include <linux/pci.h> 33#include <linux/pci.h>
34#include <linux/delay.h> 34#include <linux/delay.h>
35#include <asm/semaphore.h>
36#include <asm/io.h>
37#include "pci_hotplug.h" 35#include "pci_hotplug.h"
38 36
39#if !defined(MODULE) 37#if !defined(MODULE)
@@ -52,42 +50,18 @@ extern int shpchp_debug;
52#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg) 50#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
53#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg) 51#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
54 52
55struct pci_func {
56 struct pci_func *next;
57 u8 bus;
58 u8 device;
59 u8 function;
60 u8 is_a_board;
61 u16 status;
62 u8 configured;
63 u8 switch_save;
64 u8 presence_save;
65 u8 pwr_save;
66 u32 base_length[0x06];
67 u8 base_type[0x06];
68 u16 reserved2;
69 u32 config_space[0x20];
70 struct pci_resource *mem_head;
71 struct pci_resource *p_mem_head;
72 struct pci_resource *io_head;
73 struct pci_resource *bus_head;
74 struct pci_dev* pci_dev;
75};
76
77#define SLOT_MAGIC 0x67267321 53#define SLOT_MAGIC 0x67267321
78struct slot { 54struct slot {
79 u32 magic; 55 u32 magic;
80 struct slot *next; 56 struct slot *next;
81 u8 bus; 57 u8 bus;
82 u8 device; 58 u8 device;
59 u16 status;
83 u32 number; 60 u32 number;
84 u8 is_a_board; 61 u8 is_a_board;
85 u8 configured;
86 u8 state; 62 u8 state;
87 u8 switch_save;
88 u8 presence_save; 63 u8 presence_save;
89 u32 capabilities; 64 u8 pwr_save;
90 u16 reserved2;
91 struct timer_list task_event; 65 struct timer_list task_event;
92 u8 hp_slot; 66 u8 hp_slot;
93 struct controller *ctrl; 67 struct controller *ctrl;
@@ -96,12 +70,6 @@ struct slot {
96 struct list_head slot_list; 70 struct list_head slot_list;
97}; 71};
98 72
99struct pci_resource {
100 struct pci_resource * next;
101 u32 base;
102 u32 length;
103};
104
105struct event_info { 73struct event_info {
106 u32 event_type; 74 u32 event_type;
107 u8 hp_slot; 75 u8 hp_slot;
@@ -110,13 +78,9 @@ struct event_info {
110struct controller { 78struct controller {
111 struct controller *next; 79 struct controller *next;
112 struct semaphore crit_sect; /* critical section semaphore */ 80 struct semaphore crit_sect; /* critical section semaphore */
113 void * hpc_ctlr_handle; /* HPC controller handle */ 81 struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */
114 int num_slots; /* Number of slots on ctlr */ 82 int num_slots; /* Number of slots on ctlr */
115 int slot_num_inc; /* 1 or -1 */ 83 int slot_num_inc; /* 1 or -1 */
116 struct pci_resource *mem_head;
117 struct pci_resource *p_mem_head;
118 struct pci_resource *io_head;
119 struct pci_resource *bus_head;
120 struct pci_dev *pci_dev; 84 struct pci_dev *pci_dev;
121 struct pci_bus *pci_bus; 85 struct pci_bus *pci_bus;
122 struct event_info event_queue[10]; 86 struct event_info event_queue[10];
@@ -124,33 +88,21 @@ struct controller {
124 struct hpc_ops *hpc_ops; 88 struct hpc_ops *hpc_ops;
125 wait_queue_head_t queue; /* sleep & wake process */ 89 wait_queue_head_t queue; /* sleep & wake process */
126 u8 next_event; 90 u8 next_event;
127 u8 seg;
128 u8 bus; 91 u8 bus;
129 u8 device; 92 u8 device;
130 u8 function; 93 u8 function;
131 u8 rev;
132 u8 slot_device_offset; 94 u8 slot_device_offset;
133 u8 add_support; 95 u8 add_support;
134 enum pci_bus_speed speed; 96 enum pci_bus_speed speed;
135 u32 first_slot; /* First physical slot number */ 97 u32 first_slot; /* First physical slot number */
136 u8 slot_bus; /* Bus where the slots handled by this controller sit */ 98 u8 slot_bus; /* Bus where the slots handled by this controller sit */
137 u8 push_flag;
138 u16 ctlrcap;
139 u16 vendor_id;
140};
141
142struct irq_mapping {
143 u8 barber_pole;
144 u8 valid_INT;
145 u8 interrupt[4];
146}; 99};
147 100
148struct resource_lists { 101struct hotplug_params {
149 struct pci_resource *mem_head; 102 u8 cache_line_size;
150 struct pci_resource *p_mem_head; 103 u8 latency_timer;
151 struct pci_resource *io_head; 104 u8 enable_serr;
152 struct pci_resource *bus_head; 105 u8 enable_perr;
153 struct irq_mapping *irqs;
154}; 106};
155 107
156/* Define AMD SHPC ID */ 108/* Define AMD SHPC ID */
@@ -194,24 +146,16 @@ struct resource_lists {
194 * error Messages 146 * error Messages
195 */ 147 */
196#define msg_initialization_err "Initialization failure, error=%d\n" 148#define msg_initialization_err "Initialization failure, error=%d\n"
197#define msg_HPC_rev_error "Unsupported revision of the PCI hot plug controller found.\n"
198#define msg_HPC_non_shpc "The PCI hot plug controller is not supported by this driver.\n"
199#define msg_HPC_not_supported "This system is not supported by this version of shpcphd mdoule. Upgrade to a newer version of shpchpd\n"
200#define msg_unable_to_save "Unable to store PCI hot plug add resource information. This system must be rebooted before adding any PCI devices.\n"
201#define msg_button_on "PCI slot #%d - powering on due to button press.\n" 149#define msg_button_on "PCI slot #%d - powering on due to button press.\n"
202#define msg_button_off "PCI slot #%d - powering off due to button press.\n" 150#define msg_button_off "PCI slot #%d - powering off due to button press.\n"
203#define msg_button_cancel "PCI slot #%d - action canceled due to button press.\n" 151#define msg_button_cancel "PCI slot #%d - action canceled due to button press.\n"
204#define msg_button_ignore "PCI slot #%d - button press ignored. (action in progress...)\n"
205 152
206/* sysfs functions for the hotplug controller info */ 153/* sysfs functions for the hotplug controller info */
207extern void shpchp_create_ctrl_files (struct controller *ctrl); 154extern void shpchp_create_ctrl_files (struct controller *ctrl);
208 155
209/* controller functions */ 156/* controller functions */
210extern int shpchprm_find_available_resources(struct controller *ctrl);
211extern int shpchp_event_start_thread(void); 157extern int shpchp_event_start_thread(void);
212extern void shpchp_event_stop_thread(void); 158extern void shpchp_event_stop_thread(void);
213extern struct pci_func *shpchp_slot_create(unsigned char busnumber);
214extern struct pci_func *shpchp_slot_find(unsigned char bus, unsigned char device, unsigned char index);
215extern int shpchp_enable_slot(struct slot *slot); 159extern int shpchp_enable_slot(struct slot *slot);
216extern int shpchp_disable_slot(struct slot *slot); 160extern int shpchp_disable_slot(struct slot *slot);
217 161
@@ -220,29 +164,20 @@ extern u8 shpchp_handle_switch_change(u8 hp_slot, void *inst_id);
220extern u8 shpchp_handle_presence_change(u8 hp_slot, void *inst_id); 164extern u8 shpchp_handle_presence_change(u8 hp_slot, void *inst_id);
221extern u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id); 165extern u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id);
222 166
223/* resource functions */
224extern int shpchp_resource_sort_and_combine(struct pci_resource **head);
225
226/* pci functions */ 167/* pci functions */
227extern int shpchp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num);
228/*extern int shpchp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num, struct slot *slot);*/
229extern int shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num); 168extern int shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num);
230extern int shpchp_save_used_resources(struct controller *ctrl, struct pci_func * func, int flag); 169extern int shpchp_configure_device(struct slot *p_slot);
231extern int shpchp_save_slot_config(struct controller *ctrl, struct pci_func * new_slot); 170extern int shpchp_unconfigure_device(struct slot *p_slot);
232extern void shpchp_destroy_board_resources(struct pci_func * func); 171extern void get_hp_hw_control_from_firmware(struct pci_dev *dev);
233extern int shpchp_return_board_resources(struct pci_func * func, struct resource_lists * resources); 172extern void get_hp_params_from_firmware(struct pci_dev *dev,
234extern void shpchp_destroy_resource_list(struct resource_lists * resources); 173 struct hotplug_params *hpp);
235extern int shpchp_configure_device(struct controller* ctrl, struct pci_func* func); 174extern int shpchprm_get_physical_slot_number(struct controller *ctrl,
236extern int shpchp_unconfigure_device(struct pci_func* func); 175 u32 *sun, u8 busnum, u8 devnum);
176extern void shpchp_remove_ctrl_files(struct controller *ctrl);
237 177
238 178
239/* Global variables */ 179/* Global variables */
240extern struct controller *shpchp_ctrl_list; 180extern struct controller *shpchp_ctrl_list;
241extern struct pci_func *shpchp_slot_list[256];
242
243/* These are added to support AMD shpc */
244extern u8 shpchp_nic_irq;
245extern u8 shpchp_disk_irq;
246 181
247struct ctrl_reg { 182struct ctrl_reg {
248 volatile u32 base_offset; 183 volatile u32 base_offset;
@@ -298,7 +233,7 @@ enum ctrl_offsets {
298 SLOT11 = offsetof(struct ctrl_reg, slot11), 233 SLOT11 = offsetof(struct ctrl_reg, slot11),
299 SLOT12 = offsetof(struct ctrl_reg, slot12), 234 SLOT12 = offsetof(struct ctrl_reg, slot12),
300}; 235};
301typedef u8(*php_intr_callback_t) (unsigned int change_id, void *instance_id); 236typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id);
302struct php_ctlr_state_s { 237struct php_ctlr_state_s {
303 struct php_ctlr_state_s *pnext; 238 struct php_ctlr_state_s *pnext;
304 struct pci_dev *pci_dev; 239 struct pci_dev *pci_dev;
@@ -359,12 +294,9 @@ static inline struct slot *shpchp_find_slot (struct controller *ctrl, u8 device)
359 294
360 p_slot = ctrl->slot; 295 p_slot = ctrl->slot;
361 296
362 dbg("p_slot = %p\n", p_slot);
363
364 while (p_slot && (p_slot->device != device)) { 297 while (p_slot && (p_slot->device != device)) {
365 tmp_slot = p_slot; 298 tmp_slot = p_slot;
366 p_slot = p_slot->next; 299 p_slot = p_slot->next;
367 dbg("In while loop, p_slot = %p\n", p_slot);
368 } 300 }
369 if (p_slot == NULL) { 301 if (p_slot == NULL) {
370 err("ERROR: shpchp_find_slot device=0x%x\n", device); 302 err("ERROR: shpchp_find_slot device=0x%x\n", device);
@@ -379,8 +311,6 @@ static inline int wait_for_ctrl_irq (struct controller *ctrl)
379 DECLARE_WAITQUEUE(wait, current); 311 DECLARE_WAITQUEUE(wait, current);
380 int retval = 0; 312 int retval = 0;
381 313
382 dbg("%s : start\n",__FUNCTION__);
383
384 add_wait_queue(&ctrl->queue, &wait); 314 add_wait_queue(&ctrl->queue, &wait);
385 315
386 if (!shpchp_poll_mode) { 316 if (!shpchp_poll_mode) {
@@ -394,19 +324,9 @@ static inline int wait_for_ctrl_irq (struct controller *ctrl)
394 if (signal_pending(current)) 324 if (signal_pending(current))
395 retval = -EINTR; 325 retval = -EINTR;
396 326
397 dbg("%s : end\n", __FUNCTION__);
398 return retval; 327 return retval;
399} 328}
400 329
401/* Puts node back in the resource list pointed to by head */
402static inline void return_resource(struct pci_resource **head, struct pci_resource *node)
403{
404 if (!node || !head)
405 return;
406 node->next = *head;
407 *head = node;
408}
409
410#define SLOT_NAME_SIZE 10 330#define SLOT_NAME_SIZE 10
411 331
412static inline void make_slot_name(char *buffer, int buffer_size, struct slot *slot) 332static inline void make_slot_name(char *buffer, int buffer_size, struct slot *slot)
@@ -420,11 +340,7 @@ enum php_ctlr_type {
420 ACPI 340 ACPI
421}; 341};
422 342
423int shpc_init( struct controller *ctrl, struct pci_dev *pdev, 343int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
424 php_intr_callback_t attention_button_callback,
425 php_intr_callback_t switch_change_callback,
426 php_intr_callback_t presence_change_callback,
427 php_intr_callback_t power_fault_callback);
428 344
429int shpc_get_ctlr_slot_config( struct controller *ctrl, 345int shpc_get_ctlr_slot_config( struct controller *ctrl,
430 int *num_ctlr_slots, 346 int *num_ctlr_slots,
@@ -437,8 +353,6 @@ struct hpc_ops {
437 int (*power_on_slot ) (struct slot *slot); 353 int (*power_on_slot ) (struct slot *slot);
438 int (*slot_enable ) (struct slot *slot); 354 int (*slot_enable ) (struct slot *slot);
439 int (*slot_disable ) (struct slot *slot); 355 int (*slot_disable ) (struct slot *slot);
440 int (*enable_all_slots) (struct slot *slot);
441 int (*pwr_on_all_slots) (struct slot *slot);
442 int (*set_bus_speed_mode) (struct slot *slot, enum pci_bus_speed speed); 356 int (*set_bus_speed_mode) (struct slot *slot, enum pci_bus_speed speed);
443 int (*get_power_status) (struct slot *slot, u8 *status); 357 int (*get_power_status) (struct slot *slot, u8 *status);
444 int (*get_attention_status) (struct slot *slot, u8 *status); 358 int (*get_attention_status) (struct slot *slot, u8 *status);
diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c
index 6f7d8a29957a..63628e01dd43 100644
--- a/drivers/pci/hotplug/shpchp_core.c
+++ b/drivers/pci/hotplug/shpchp_core.c
@@ -27,26 +27,18 @@
27 * 27 *
28 */ 28 */
29 29
30#include <linux/config.h>
31#include <linux/module.h> 30#include <linux/module.h>
32#include <linux/moduleparam.h> 31#include <linux/moduleparam.h>
33#include <linux/kernel.h> 32#include <linux/kernel.h>
34#include <linux/types.h> 33#include <linux/types.h>
35#include <linux/proc_fs.h>
36#include <linux/slab.h>
37#include <linux/workqueue.h>
38#include <linux/pci.h> 34#include <linux/pci.h>
39#include <linux/init.h>
40#include <asm/uaccess.h>
41#include "shpchp.h" 35#include "shpchp.h"
42#include "shpchprm.h"
43 36
44/* Global variables */ 37/* Global variables */
45int shpchp_debug; 38int shpchp_debug;
46int shpchp_poll_mode; 39int shpchp_poll_mode;
47int shpchp_poll_time; 40int shpchp_poll_time;
48struct controller *shpchp_ctrl_list; /* = NULL */ 41struct controller *shpchp_ctrl_list; /* = NULL */
49struct pci_func *shpchp_slot_list[256];
50 42
51#define DRIVER_VERSION "0.4" 43#define DRIVER_VERSION "0.4"
52#define DRIVER_AUTHOR "Dan Zink <dan.zink@compaq.com>, Greg Kroah-Hartman <greg@kroah.com>, Dely Sy <dely.l.sy@intel.com>" 44#define DRIVER_AUTHOR "Dan Zink <dan.zink@compaq.com>, Greg Kroah-Hartman <greg@kroah.com>, Dely Sy <dely.l.sy@intel.com>"
@@ -113,8 +105,6 @@ static int init_slots(struct controller *ctrl)
113 u32 slot_number, sun; 105 u32 slot_number, sun;
114 int result = -ENOMEM; 106 int result = -ENOMEM;
115 107
116 dbg("%s\n",__FUNCTION__);
117
118 number_of_slots = ctrl->num_slots; 108 number_of_slots = ctrl->num_slots;
119 slot_device = ctrl->slot_device_offset; 109 slot_device = ctrl->slot_device_offset;
120 slot_number = ctrl->first_slot; 110 slot_number = ctrl->first_slot;
@@ -352,6 +342,17 @@ static int get_cur_bus_speed (struct hotplug_slot *hotplug_slot, enum pci_bus_sp
352 return 0; 342 return 0;
353} 343}
354 344
345static int is_shpc_capable(struct pci_dev *dev)
346{
347 if ((dev->vendor == PCI_VENDOR_ID_AMD) || (dev->device ==
348 PCI_DEVICE_ID_AMD_GOLAM_7450))
349 return 1;
350 if (pci_find_capability(dev, PCI_CAP_ID_SHPC))
351 return 1;
352
353 return 0;
354}
355
355static int shpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 356static int shpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
356{ 357{
357 int rc; 358 int rc;
@@ -360,6 +361,9 @@ static int shpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
360 int first_device_num; /* first PCI device number supported by this SHPC */ 361 int first_device_num; /* first PCI device number supported by this SHPC */
361 int num_ctlr_slots; /* number of slots supported by this SHPC */ 362 int num_ctlr_slots; /* number of slots supported by this SHPC */
362 363
364 if (!is_shpc_capable(pdev))
365 return -ENODEV;
366
363 ctrl = (struct controller *) kmalloc(sizeof(struct controller), GFP_KERNEL); 367 ctrl = (struct controller *) kmalloc(sizeof(struct controller), GFP_KERNEL);
364 if (!ctrl) { 368 if (!ctrl) {
365 err("%s : out of memory\n", __FUNCTION__); 369 err("%s : out of memory\n", __FUNCTION__);
@@ -367,19 +371,12 @@ static int shpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
367 } 371 }
368 memset(ctrl, 0, sizeof(struct controller)); 372 memset(ctrl, 0, sizeof(struct controller));
369 373
370 dbg("DRV_thread pid = %d\n", current->pid); 374 rc = shpc_init(ctrl, pdev);
371
372 rc = shpc_init(ctrl, pdev,
373 (php_intr_callback_t) shpchp_handle_attention_button,
374 (php_intr_callback_t) shpchp_handle_switch_change,
375 (php_intr_callback_t) shpchp_handle_presence_change,
376 (php_intr_callback_t) shpchp_handle_power_fault);
377 if (rc) { 375 if (rc) {
378 dbg("%s: controller initialization failed\n", SHPC_MODULE_NAME); 376 dbg("%s: controller initialization failed\n", SHPC_MODULE_NAME);
379 goto err_out_free_ctrl; 377 goto err_out_free_ctrl;
380 } 378 }
381 379
382 dbg("%s: controller initialization success\n", __FUNCTION__);
383 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 380 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
384 381
385 pci_set_drvdata(pdev, ctrl); 382 pci_set_drvdata(pdev, ctrl);
@@ -411,23 +408,8 @@ static int shpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
411 first_device_num = ctrl->slot_device_offset; 408 first_device_num = ctrl->slot_device_offset;
412 num_ctlr_slots = ctrl->num_slots; 409 num_ctlr_slots = ctrl->num_slots;
413 410
414 /* Store PCI Config Space for all devices on this bus */ 411 ctrl->add_support = 1;
415 rc = shpchp_save_config(ctrl, ctrl->slot_bus, num_ctlr_slots, first_device_num);
416 if (rc) {
417 err("%s: unable to save PCI configuration data, error %d\n", __FUNCTION__, rc);
418 goto err_out_free_ctrl_bus;
419 }
420
421 /* Get IO, memory, and IRQ resources for new devices */
422 rc = shpchprm_find_available_resources(ctrl);
423 ctrl->add_support = !rc;
424 412
425 if (rc) {
426 dbg("shpchprm_find_available_resources = %#x\n", rc);
427 err("unable to locate PCI configuration resources for hot plug add.\n");
428 goto err_out_free_ctrl_bus;
429 }
430
431 /* Setup the slot information structures */ 413 /* Setup the slot information structures */
432 rc = init_slots(ctrl); 414 rc = init_slots(ctrl);
433 if (rc) { 415 if (rc) {
@@ -477,7 +459,6 @@ err_out_none:
477 459
478static int shpc_start_thread(void) 460static int shpc_start_thread(void)
479{ 461{
480 int loop;
481 int retval = 0; 462 int retval = 0;
482 463
483 dbg("Initialize + Start the notification/polling mechanism \n"); 464 dbg("Initialize + Start the notification/polling mechanism \n");
@@ -488,48 +469,21 @@ static int shpc_start_thread(void)
488 return retval; 469 return retval;
489 } 470 }
490 471
491 dbg("Initialize slot lists\n");
492 /* One slot list for each bus in the system */
493 for (loop = 0; loop < 256; loop++) {
494 shpchp_slot_list[loop] = NULL;
495 }
496
497 return retval; 472 return retval;
498} 473}
499 474
500static inline void __exit
501free_shpchp_res(struct pci_resource *res)
502{
503 struct pci_resource *tres;
504
505 while (res) {
506 tres = res;
507 res = res->next;
508 kfree(tres);
509 }
510}
511
512static void __exit unload_shpchpd(void) 475static void __exit unload_shpchpd(void)
513{ 476{
514 struct pci_func *next;
515 struct pci_func *TempSlot;
516 int loop;
517 struct controller *ctrl; 477 struct controller *ctrl;
518 struct controller *tctrl; 478 struct controller *tctrl;
519 479
520 ctrl = shpchp_ctrl_list; 480 ctrl = shpchp_ctrl_list;
521 481
522 while (ctrl) { 482 while (ctrl) {
483 shpchp_remove_ctrl_files(ctrl);
523 cleanup_slots(ctrl); 484 cleanup_slots(ctrl);
524 485
525 free_shpchp_res(ctrl->io_head);
526 free_shpchp_res(ctrl->mem_head);
527 free_shpchp_res(ctrl->p_mem_head);
528 free_shpchp_res(ctrl->bus_head);
529
530 kfree (ctrl->pci_bus); 486 kfree (ctrl->pci_bus);
531
532 dbg("%s: calling release_ctlr\n", __FUNCTION__);
533 ctrl->hpc_ops->release_ctlr(ctrl); 487 ctrl->hpc_ops->release_ctlr(ctrl);
534 488
535 tctrl = ctrl; 489 tctrl = ctrl;
@@ -538,20 +492,6 @@ static void __exit unload_shpchpd(void)
538 kfree(tctrl); 492 kfree(tctrl);
539 } 493 }
540 494
541 for (loop = 0; loop < 256; loop++) {
542 next = shpchp_slot_list[loop];
543 while (next != NULL) {
544 free_shpchp_res(next->io_head);
545 free_shpchp_res(next->mem_head);
546 free_shpchp_res(next->p_mem_head);
547 free_shpchp_res(next->bus_head);
548
549 TempSlot = next;
550 next = next->next;
551 kfree(TempSlot);
552 }
553 }
554
555 /* Stop the notification mechanism */ 495 /* Stop the notification mechanism */
556 shpchp_event_stop_thread(); 496 shpchp_event_stop_thread();
557 497
@@ -596,20 +536,14 @@ static int __init shpcd_init(void)
596 if (retval) 536 if (retval)
597 goto error_hpc_init; 537 goto error_hpc_init;
598 538
599 retval = shpchprm_init(PCI); 539 retval = pci_register_driver(&shpc_driver);
600 if (!retval) { 540 dbg("%s: pci_register_driver = %d\n", __FUNCTION__, retval);
601 retval = pci_register_driver(&shpc_driver); 541 info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
602 dbg("%s: pci_register_driver = %d\n", __FUNCTION__, retval);
603 info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
604 }
605 542
606error_hpc_init: 543error_hpc_init:
607 if (retval) { 544 if (retval) {
608 shpchprm_cleanup();
609 shpchp_event_stop_thread(); 545 shpchp_event_stop_thread();
610 } else 546 }
611 shpchprm_print_pirt();
612
613 return retval; 547 return retval;
614} 548}
615 549
@@ -618,9 +552,6 @@ static void __exit shpcd_cleanup(void)
618 dbg("unload_shpchpd()\n"); 552 dbg("unload_shpchpd()\n");
619 unload_shpchpd(); 553 unload_shpchpd();
620 554
621 shpchprm_cleanup();
622
623 dbg("pci_unregister_driver\n");
624 pci_unregister_driver(&shpc_driver); 555 pci_unregister_driver(&shpc_driver);
625 556
626 info(DRIVER_DESC " version: " DRIVER_VERSION " unloaded\n"); 557 info(DRIVER_DESC " version: " DRIVER_VERSION " unloaded\n");
diff --git a/drivers/pci/hotplug/shpchp_ctrl.c b/drivers/pci/hotplug/shpchp_ctrl.c
index 91c9903e621f..58619359ad08 100644
--- a/drivers/pci/hotplug/shpchp_ctrl.c
+++ b/drivers/pci/hotplug/shpchp_ctrl.c
@@ -27,24 +27,14 @@
27 * 27 *
28 */ 28 */
29 29
30#include <linux/config.h>
31#include <linux/module.h> 30#include <linux/module.h>
32#include <linux/kernel.h> 31#include <linux/kernel.h>
33#include <linux/types.h> 32#include <linux/types.h>
34#include <linux/slab.h>
35#include <linux/workqueue.h>
36#include <linux/interrupt.h>
37#include <linux/delay.h>
38#include <linux/wait.h>
39#include <linux/smp_lock.h> 33#include <linux/smp_lock.h>
40#include <linux/pci.h> 34#include <linux/pci.h>
35#include "../pci.h"
41#include "shpchp.h" 36#include "shpchp.h"
42#include "shpchprm.h"
43 37
44static u32 configure_new_device(struct controller *ctrl, struct pci_func *func,
45 u8 behind_bridge, struct resource_lists *resources, u8 bridge_bus, u8 bridge_dev);
46static int configure_new_function( struct controller *ctrl, struct pci_func *func,
47 u8 behind_bridge, struct resource_lists *resources, u8 bridge_bus, u8 bridge_dev);
48static void interrupt_event_handler(struct controller *ctrl); 38static void interrupt_event_handler(struct controller *ctrl);
49 39
50static struct semaphore event_semaphore; /* mutex for process loop (up if something to process) */ 40static struct semaphore event_semaphore; /* mutex for process loop (up if something to process) */
@@ -52,28 +42,22 @@ static struct semaphore event_exit; /* guard ensure thread has exited before ca
52static int event_finished; 42static int event_finished;
53static unsigned long pushbutton_pending; /* = 0 */ 43static unsigned long pushbutton_pending; /* = 0 */
54 44
55u8 shpchp_disk_irq;
56u8 shpchp_nic_irq;
57
58u8 shpchp_handle_attention_button(u8 hp_slot, void *inst_id) 45u8 shpchp_handle_attention_button(u8 hp_slot, void *inst_id)
59{ 46{
60 struct controller *ctrl = (struct controller *) inst_id; 47 struct controller *ctrl = (struct controller *) inst_id;
61 struct slot *p_slot; 48 struct slot *p_slot;
62 u8 rc = 0; 49 u8 rc = 0;
63 u8 getstatus; 50 u8 getstatus;
64 struct pci_func *func;
65 struct event_info *taskInfo; 51 struct event_info *taskInfo;
66 52
67 /* Attention Button Change */ 53 /* Attention Button Change */
68 dbg("shpchp: Attention button interrupt received.\n"); 54 dbg("shpchp: Attention button interrupt received.\n");
69 55
70 func = shpchp_slot_find(ctrl->slot_bus, (hp_slot + ctrl->slot_device_offset), 0);
71
72 /* This is the structure that tells the worker thread what to do */ 56 /* This is the structure that tells the worker thread what to do */
73 taskInfo = &(ctrl->event_queue[ctrl->next_event]); 57 taskInfo = &(ctrl->event_queue[ctrl->next_event]);
74 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); 58 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset);
75 59
76 p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save)); 60 p_slot->hpc_ops->get_adapter_status(p_slot, &(p_slot->presence_save));
77 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 61 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
78 62
79 ctrl->next_event = (ctrl->next_event + 1) % 10; 63 ctrl->next_event = (ctrl->next_event + 1) % 10;
@@ -118,14 +102,11 @@ u8 shpchp_handle_switch_change(u8 hp_slot, void *inst_id)
118 struct slot *p_slot; 102 struct slot *p_slot;
119 u8 rc = 0; 103 u8 rc = 0;
120 u8 getstatus; 104 u8 getstatus;
121 struct pci_func *func;
122 struct event_info *taskInfo; 105 struct event_info *taskInfo;
123 106
124 /* Switch Change */ 107 /* Switch Change */
125 dbg("shpchp: Switch interrupt received.\n"); 108 dbg("shpchp: Switch interrupt received.\n");
126 109
127 func = shpchp_slot_find(ctrl->slot_bus, (hp_slot + ctrl->slot_device_offset), 0);
128
129 /* This is the structure that tells the worker thread 110 /* This is the structure that tells the worker thread
130 * what to do 111 * what to do
131 */ 112 */
@@ -135,19 +116,18 @@ u8 shpchp_handle_switch_change(u8 hp_slot, void *inst_id)
135 116
136 rc++; 117 rc++;
137 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); 118 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset);
138 p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save)); 119 p_slot->hpc_ops->get_adapter_status(p_slot, &(p_slot->presence_save));
139 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 120 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
140 dbg("%s: Card present %x Power status %x\n", __FUNCTION__, 121 dbg("%s: Card present %x Power status %x\n", __FUNCTION__,
141 func->presence_save, func->pwr_save); 122 p_slot->presence_save, p_slot->pwr_save);
142 123
143 if (getstatus) { 124 if (getstatus) {
144 /* 125 /*
145 * Switch opened 126 * Switch opened
146 */ 127 */
147 info("Latch open on Slot(%d)\n", ctrl->first_slot + hp_slot); 128 info("Latch open on Slot(%d)\n", ctrl->first_slot + hp_slot);
148 func->switch_save = 0;
149 taskInfo->event_type = INT_SWITCH_OPEN; 129 taskInfo->event_type = INT_SWITCH_OPEN;
150 if (func->pwr_save && func->presence_save) { 130 if (p_slot->pwr_save && p_slot->presence_save) {
151 taskInfo->event_type = INT_POWER_FAULT; 131 taskInfo->event_type = INT_POWER_FAULT;
152 err("Surprise Removal of card\n"); 132 err("Surprise Removal of card\n");
153 } 133 }
@@ -156,7 +136,6 @@ u8 shpchp_handle_switch_change(u8 hp_slot, void *inst_id)
156 * Switch closed 136 * Switch closed
157 */ 137 */
158 info("Latch close on Slot(%d)\n", ctrl->first_slot + hp_slot); 138 info("Latch close on Slot(%d)\n", ctrl->first_slot + hp_slot);
159 func->switch_save = 0x10;
160 taskInfo->event_type = INT_SWITCH_CLOSE; 139 taskInfo->event_type = INT_SWITCH_CLOSE;
161 } 140 }
162 141
@@ -172,14 +151,11 @@ u8 shpchp_handle_presence_change(u8 hp_slot, void *inst_id)
172 struct slot *p_slot; 151 struct slot *p_slot;
173 u8 rc = 0; 152 u8 rc = 0;
174 /*u8 temp_byte;*/ 153 /*u8 temp_byte;*/
175 struct pci_func *func;
176 struct event_info *taskInfo; 154 struct event_info *taskInfo;
177 155
178 /* Presence Change */ 156 /* Presence Change */
179 dbg("shpchp: Presence/Notify input change.\n"); 157 dbg("shpchp: Presence/Notify input change.\n");
180 158
181 func = shpchp_slot_find(ctrl->slot_bus, (hp_slot + ctrl->slot_device_offset), 0);
182
183 /* This is the structure that tells the worker thread 159 /* This is the structure that tells the worker thread
184 * what to do 160 * what to do
185 */ 161 */
@@ -193,8 +169,8 @@ u8 shpchp_handle_presence_change(u8 hp_slot, void *inst_id)
193 /* 169 /*
194 * Save the presence state 170 * Save the presence state
195 */ 171 */
196 p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save)); 172 p_slot->hpc_ops->get_adapter_status(p_slot, &(p_slot->presence_save));
197 if (func->presence_save) { 173 if (p_slot->presence_save) {
198 /* 174 /*
199 * Card Present 175 * Card Present
200 */ 176 */
@@ -219,14 +195,11 @@ u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id)
219 struct controller *ctrl = (struct controller *) inst_id; 195 struct controller *ctrl = (struct controller *) inst_id;
220 struct slot *p_slot; 196 struct slot *p_slot;
221 u8 rc = 0; 197 u8 rc = 0;
222 struct pci_func *func;
223 struct event_info *taskInfo; 198 struct event_info *taskInfo;
224 199
225 /* Power fault */ 200 /* Power fault */
226 dbg("shpchp: Power fault interrupt received.\n"); 201 dbg("shpchp: Power fault interrupt received.\n");
227 202
228 func = shpchp_slot_find(ctrl->slot_bus, (hp_slot + ctrl->slot_device_offset), 0);
229
230 /* This is the structure that tells the worker thread 203 /* This is the structure that tells the worker thread
231 * what to do 204 * what to do
232 */ 205 */
@@ -242,7 +215,7 @@ u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id)
242 * Power fault Cleared 215 * Power fault Cleared
243 */ 216 */
244 info("Power fault cleared on Slot(%d)\n", ctrl->first_slot + hp_slot); 217 info("Power fault cleared on Slot(%d)\n", ctrl->first_slot + hp_slot);
245 func->status = 0x00; 218 p_slot->status = 0x00;
246 taskInfo->event_type = INT_POWER_FAULT_CLEAR; 219 taskInfo->event_type = INT_POWER_FAULT_CLEAR;
247 } else { 220 } else {
248 /* 221 /*
@@ -251,7 +224,7 @@ u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id)
251 info("Power fault on Slot(%d)\n", ctrl->first_slot + hp_slot); 224 info("Power fault on Slot(%d)\n", ctrl->first_slot + hp_slot);
252 taskInfo->event_type = INT_POWER_FAULT; 225 taskInfo->event_type = INT_POWER_FAULT;
253 /* set power fault status for this board */ 226 /* set power fault status for this board */
254 func->status = 0xFF; 227 p_slot->status = 0xFF;
255 info("power fault bit %x set\n", hp_slot); 228 info("power fault bit %x set\n", hp_slot);
256 } 229 }
257 if (rc) 230 if (rc)
@@ -260,799 +233,13 @@ u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id)
260 return rc; 233 return rc;
261} 234}
262 235
263
264/*
265 * sort_by_size
266 *
267 * Sorts nodes on the list by their length.
268 * Smallest first.
269 *
270 */
271static int sort_by_size(struct pci_resource **head)
272{
273 struct pci_resource *current_res;
274 struct pci_resource *next_res;
275 int out_of_order = 1;
276
277 if (!(*head))
278 return(1);
279
280 if (!((*head)->next))
281 return(0);
282
283 while (out_of_order) {
284 out_of_order = 0;
285
286 /* Special case for swapping list head */
287 if (((*head)->next) &&
288 ((*head)->length > (*head)->next->length)) {
289 out_of_order++;
290 current_res = *head;
291 *head = (*head)->next;
292 current_res->next = (*head)->next;
293 (*head)->next = current_res;
294 }
295
296 current_res = *head;
297
298 while (current_res->next && current_res->next->next) {
299 if (current_res->next->length > current_res->next->next->length) {
300 out_of_order++;
301 next_res = current_res->next;
302 current_res->next = current_res->next->next;
303 current_res = current_res->next;
304 next_res->next = current_res->next;
305 current_res->next = next_res;
306 } else
307 current_res = current_res->next;
308 }
309 } /* End of out_of_order loop */
310
311 return(0);
312}
313
314
315/*
316 * sort_by_max_size
317 *
318 * Sorts nodes on the list by their length.
319 * Largest first.
320 *
321 */
322static int sort_by_max_size(struct pci_resource **head)
323{
324 struct pci_resource *current_res;
325 struct pci_resource *next_res;
326 int out_of_order = 1;
327
328 if (!(*head))
329 return(1);
330
331 if (!((*head)->next))
332 return(0);
333
334 while (out_of_order) {
335 out_of_order = 0;
336
337 /* Special case for swapping list head */
338 if (((*head)->next) &&
339 ((*head)->length < (*head)->next->length)) {
340 out_of_order++;
341 current_res = *head;
342 *head = (*head)->next;
343 current_res->next = (*head)->next;
344 (*head)->next = current_res;
345 }
346
347 current_res = *head;
348
349 while (current_res->next && current_res->next->next) {
350 if (current_res->next->length < current_res->next->next->length) {
351 out_of_order++;
352 next_res = current_res->next;
353 current_res->next = current_res->next->next;
354 current_res = current_res->next;
355 next_res->next = current_res->next;
356 current_res->next = next_res;
357 } else
358 current_res = current_res->next;
359 }
360 } /* End of out_of_order loop */
361
362 return(0);
363}
364
365
366/*
367 * do_pre_bridge_resource_split
368 *
369 * Returns zero or one node of resources that aren't in use
370 *
371 */
372static struct pci_resource *do_pre_bridge_resource_split (struct pci_resource **head, struct pci_resource **orig_head, u32 alignment)
373{
374 struct pci_resource *prevnode = NULL;
375 struct pci_resource *node;
376 struct pci_resource *split_node;
377 u32 rc;
378 u32 temp_dword;
379 dbg("do_pre_bridge_resource_split\n");
380
381 if (!(*head) || !(*orig_head))
382 return(NULL);
383
384 rc = shpchp_resource_sort_and_combine(head);
385
386 if (rc)
387 return(NULL);
388
389 if ((*head)->base != (*orig_head)->base)
390 return(NULL);
391
392 if ((*head)->length == (*orig_head)->length)
393 return(NULL);
394
395
396 /* If we got here, there the bridge requires some of the resource, but
397 * we may be able to split some off of the front
398 */
399 node = *head;
400
401 if (node->length & (alignment -1)) {
402 /* This one isn't an aligned length, so we'll make a new entry
403 * and split it up.
404 */
405 split_node = kmalloc(sizeof(*split_node), GFP_KERNEL);
406
407 if (!split_node)
408 return(NULL);
409
410 temp_dword = (node->length | (alignment-1)) + 1 - alignment;
411
412 split_node->base = node->base;
413 split_node->length = temp_dword;
414
415 node->length -= temp_dword;
416 node->base += split_node->length;
417
418 /* Put it in the list */
419 *head = split_node;
420 split_node->next = node;
421 }
422
423 if (node->length < alignment) {
424 return(NULL);
425 }
426
427 /* Now unlink it */
428 if (*head == node) {
429 *head = node->next;
430 node->next = NULL;
431 } else {
432 prevnode = *head;
433 while (prevnode->next != node)
434 prevnode = prevnode->next;
435
436 prevnode->next = node->next;
437 node->next = NULL;
438 }
439
440 return(node);
441}
442
443
444/*
445 * do_bridge_resource_split
446 *
447 * Returns zero or one node of resources that aren't in use
448 *
449 */
450static struct pci_resource *do_bridge_resource_split (struct pci_resource **head, u32 alignment)
451{
452 struct pci_resource *prevnode = NULL;
453 struct pci_resource *node;
454 u32 rc;
455 u32 temp_dword;
456
457 if (!(*head))
458 return(NULL);
459
460 rc = shpchp_resource_sort_and_combine(head);
461
462 if (rc)
463 return(NULL);
464
465 node = *head;
466
467 while (node->next) {
468 prevnode = node;
469 node = node->next;
470 kfree(prevnode);
471 }
472
473 if (node->length < alignment) {
474 kfree(node);
475 return(NULL);
476 }
477
478 if (node->base & (alignment - 1)) {
479 /* Short circuit if adjusted size is too small */
480 temp_dword = (node->base | (alignment-1)) + 1;
481 if ((node->length - (temp_dword - node->base)) < alignment) {
482 kfree(node);
483 return(NULL);
484 }
485
486 node->length -= (temp_dword - node->base);
487 node->base = temp_dword;
488 }
489
490 if (node->length & (alignment - 1)) {
491 /* There's stuff in use after this node */
492 kfree(node);
493 return(NULL);
494 }
495
496 return(node);
497}
498
499
500/*
501 * get_io_resource
502 *
503 * this function sorts the resource list by size and then
504 * returns the first node of "size" length that is not in the
505 * ISA aliasing window. If it finds a node larger than "size"
506 * it will split it up.
507 *
508 * size must be a power of two.
509 */
510static struct pci_resource *get_io_resource (struct pci_resource **head, u32 size)
511{
512 struct pci_resource *prevnode;
513 struct pci_resource *node;
514 struct pci_resource *split_node = NULL;
515 u32 temp_dword;
516
517 if (!(*head))
518 return(NULL);
519
520 if ( shpchp_resource_sort_and_combine(head) )
521 return(NULL);
522
523 if ( sort_by_size(head) )
524 return(NULL);
525
526 for (node = *head; node; node = node->next) {
527 if (node->length < size)
528 continue;
529
530 if (node->base & (size - 1)) {
531 /* This one isn't base aligned properly
532 so we'll make a new entry and split it up */
533 temp_dword = (node->base | (size-1)) + 1;
534
535 /*/ Short circuit if adjusted size is too small */
536 if ((node->length - (temp_dword - node->base)) < size)
537 continue;
538
539 split_node = kmalloc(sizeof(*split_node), GFP_KERNEL);
540
541 if (!split_node)
542 return(NULL);
543
544 split_node->base = node->base;
545 split_node->length = temp_dword - node->base;
546 node->base = temp_dword;
547 node->length -= split_node->length;
548
549 /* Put it in the list */
550 split_node->next = node->next;
551 node->next = split_node;
552 } /* End of non-aligned base */
553
554 /* Don't need to check if too small since we already did */
555 if (node->length > size) {
556 /* This one is longer than we need
557 so we'll make a new entry and split it up */
558 split_node = kmalloc(sizeof(*split_node), GFP_KERNEL);
559
560 if (!split_node)
561 return(NULL);
562
563 split_node->base = node->base + size;
564 split_node->length = node->length - size;
565 node->length = size;
566
567 /* Put it in the list */
568 split_node->next = node->next;
569 node->next = split_node;
570 } /* End of too big on top end */
571
572 /* For IO make sure it's not in the ISA aliasing space */
573 if (node->base & 0x300L)
574 continue;
575
576 /* If we got here, then it is the right size
577 Now take it out of the list */
578 if (*head == node) {
579 *head = node->next;
580 } else {
581 prevnode = *head;
582 while (prevnode->next != node)
583 prevnode = prevnode->next;
584
585 prevnode->next = node->next;
586 }
587 node->next = NULL;
588 /* Stop looping */
589 break;
590 }
591
592 return(node);
593}
594
595
596/*
597 * get_max_resource
598 *
599 * Gets the largest node that is at least "size" big from the
600 * list pointed to by head. It aligns the node on top and bottom
601 * to "size" alignment before returning it.
602 * J.I. modified to put max size limits of; 64M->32M->16M->8M->4M->1M
603 * This is needed to avoid allocating entire ACPI _CRS res to one child bridge/slot.
604 */
605static struct pci_resource *get_max_resource (struct pci_resource **head, u32 size)
606{
607 struct pci_resource *max;
608 struct pci_resource *temp;
609 struct pci_resource *split_node;
610 u32 temp_dword;
611 u32 max_size[] = { 0x4000000, 0x2000000, 0x1000000, 0x0800000, 0x0400000, 0x0200000, 0x0100000, 0x00 };
612 int i;
613
614 if (!(*head))
615 return(NULL);
616
617 if (shpchp_resource_sort_and_combine(head))
618 return(NULL);
619
620 if (sort_by_max_size(head))
621 return(NULL);
622
623 for (max = *head;max; max = max->next) {
624
625 /* If not big enough we could probably just bail,
626 instead we'll continue to the next. */
627 if (max->length < size)
628 continue;
629
630 if (max->base & (size - 1)) {
631 /* This one isn't base aligned properly
632 so we'll make a new entry and split it up */
633 temp_dword = (max->base | (size-1)) + 1;
634
635 /* Short circuit if adjusted size is too small */
636 if ((max->length - (temp_dword - max->base)) < size)
637 continue;
638
639 split_node = kmalloc(sizeof(*split_node), GFP_KERNEL);
640
641 if (!split_node)
642 return(NULL);
643
644 split_node->base = max->base;
645 split_node->length = temp_dword - max->base;
646 max->base = temp_dword;
647 max->length -= split_node->length;
648
649 /* Put it next in the list */
650 split_node->next = max->next;
651 max->next = split_node;
652 }
653
654 if ((max->base + max->length) & (size - 1)) {
655 /* This one isn't end aligned properly at the top
656 so we'll make a new entry and split it up */
657 split_node = kmalloc(sizeof(*split_node), GFP_KERNEL);
658
659 if (!split_node)
660 return(NULL);
661 temp_dword = ((max->base + max->length) & ~(size - 1));
662 split_node->base = temp_dword;
663 split_node->length = max->length + max->base
664 - split_node->base;
665 max->length -= split_node->length;
666
667 /* Put it in the list */
668 split_node->next = max->next;
669 max->next = split_node;
670 }
671
672 /* Make sure it didn't shrink too much when we aligned it */
673 if (max->length < size)
674 continue;
675
676 for ( i = 0; max_size[i] > size; i++) {
677 if (max->length > max_size[i]) {
678 split_node = kmalloc(sizeof(*split_node),
679 GFP_KERNEL);
680 if (!split_node)
681 break; /* return (NULL); */
682 split_node->base = max->base + max_size[i];
683 split_node->length = max->length - max_size[i];
684 max->length = max_size[i];
685 /* Put it next in the list */
686 split_node->next = max->next;
687 max->next = split_node;
688 break;
689 }
690 }
691
692 /* Now take it out of the list */
693 temp = (struct pci_resource*) *head;
694 if (temp == max) {
695 *head = max->next;
696 } else {
697 while (temp && temp->next != max) {
698 temp = temp->next;
699 }
700
701 temp->next = max->next;
702 }
703
704 max->next = NULL;
705 return(max);
706 }
707
708 /* If we get here, we couldn't find one */
709 return(NULL);
710}
711
712
713/*
714 * get_resource
715 *
716 * this function sorts the resource list by size and then
717 * returns the first node of "size" length. If it finds a node
718 * larger than "size" it will split it up.
719 *
720 * size must be a power of two.
721 */
722static struct pci_resource *get_resource (struct pci_resource **head, u32 size)
723{
724 struct pci_resource *prevnode;
725 struct pci_resource *node;
726 struct pci_resource *split_node;
727 u32 temp_dword;
728
729 if (!(*head))
730 return(NULL);
731
732 if ( shpchp_resource_sort_and_combine(head) )
733 return(NULL);
734
735 if ( sort_by_size(head) )
736 return(NULL);
737
738 for (node = *head; node; node = node->next) {
739 dbg("%s: req_size =0x%x node=%p, base=0x%x, length=0x%x\n",
740 __FUNCTION__, size, node, node->base, node->length);
741 if (node->length < size)
742 continue;
743
744 if (node->base & (size - 1)) {
745 dbg("%s: not aligned\n", __FUNCTION__);
746 /* this one isn't base aligned properly
747 so we'll make a new entry and split it up */
748 temp_dword = (node->base | (size-1)) + 1;
749
750 /* Short circuit if adjusted size is too small */
751 if ((node->length - (temp_dword - node->base)) < size)
752 continue;
753
754 split_node = kmalloc(sizeof(*split_node), GFP_KERNEL);
755
756 if (!split_node)
757 return(NULL);
758
759 split_node->base = node->base;
760 split_node->length = temp_dword - node->base;
761 node->base = temp_dword;
762 node->length -= split_node->length;
763
764 /* Put it in the list */
765 split_node->next = node->next;
766 node->next = split_node;
767 } /* End of non-aligned base */
768
769 /* Don't need to check if too small since we already did */
770 if (node->length > size) {
771 dbg("%s: too big\n", __FUNCTION__);
772 /* this one is longer than we need
773 so we'll make a new entry and split it up */
774 split_node = kmalloc(sizeof(*split_node), GFP_KERNEL);
775
776 if (!split_node)
777 return(NULL);
778
779 split_node->base = node->base + size;
780 split_node->length = node->length - size;
781 node->length = size;
782
783 /* Put it in the list */
784 split_node->next = node->next;
785 node->next = split_node;
786 } /* End of too big on top end */
787
788 dbg("%s: got one!!!\n", __FUNCTION__);
789 /* If we got here, then it is the right size
790 Now take it out of the list */
791 if (*head == node) {
792 *head = node->next;
793 } else {
794 prevnode = *head;
795 while (prevnode->next != node)
796 prevnode = prevnode->next;
797
798 prevnode->next = node->next;
799 }
800 node->next = NULL;
801 /* Stop looping */
802 break;
803 }
804 return(node);
805}
806
807
808/*
809 * shpchp_resource_sort_and_combine
810 *
811 * Sorts all of the nodes in the list in ascending order by
812 * their base addresses. Also does garbage collection by
813 * combining adjacent nodes.
814 *
815 * returns 0 if success
816 */
817int shpchp_resource_sort_and_combine(struct pci_resource **head)
818{
819 struct pci_resource *node1;
820 struct pci_resource *node2;
821 int out_of_order = 1;
822
823 dbg("%s: head = %p, *head = %p\n", __FUNCTION__, head, *head);
824
825 if (!(*head))
826 return(1);
827
828 dbg("*head->next = %p\n",(*head)->next);
829
830 if (!(*head)->next)
831 return(0); /* only one item on the list, already sorted! */
832
833 dbg("*head->base = 0x%x\n",(*head)->base);
834 dbg("*head->next->base = 0x%x\n",(*head)->next->base);
835 while (out_of_order) {
836 out_of_order = 0;
837
838 /* Special case for swapping list head */
839 if (((*head)->next) &&
840 ((*head)->base > (*head)->next->base)) {
841 node1 = *head;
842 (*head) = (*head)->next;
843 node1->next = (*head)->next;
844 (*head)->next = node1;
845 out_of_order++;
846 }
847
848 node1 = (*head);
849
850 while (node1->next && node1->next->next) {
851 if (node1->next->base > node1->next->next->base) {
852 out_of_order++;
853 node2 = node1->next;
854 node1->next = node1->next->next;
855 node1 = node1->next;
856 node2->next = node1->next;
857 node1->next = node2;
858 } else
859 node1 = node1->next;
860 }
861 } /* End of out_of_order loop */
862
863 node1 = *head;
864
865 while (node1 && node1->next) {
866 if ((node1->base + node1->length) == node1->next->base) {
867 /* Combine */
868 dbg("8..\n");
869 node1->length += node1->next->length;
870 node2 = node1->next;
871 node1->next = node1->next->next;
872 kfree(node2);
873 } else
874 node1 = node1->next;
875 }
876
877 return(0);
878}
879
880
881/**
882 * shpchp_slot_create - Creates a node and adds it to the proper bus.
883 * @busnumber - bus where new node is to be located
884 *
885 * Returns pointer to the new node or NULL if unsuccessful
886 */
887struct pci_func *shpchp_slot_create(u8 busnumber)
888{
889 struct pci_func *new_slot;
890 struct pci_func *next;
891
892 new_slot = kmalloc(sizeof(*new_slot), GFP_KERNEL);
893
894 if (new_slot == NULL) {
895 return(new_slot);
896 }
897
898 memset(new_slot, 0, sizeof(struct pci_func));
899
900 new_slot->next = NULL;
901 new_slot->configured = 1;
902
903 if (shpchp_slot_list[busnumber] == NULL) {
904 shpchp_slot_list[busnumber] = new_slot;
905 } else {
906 next = shpchp_slot_list[busnumber];
907 while (next->next != NULL)
908 next = next->next;
909 next->next = new_slot;
910 }
911 return(new_slot);
912}
913
914
915/*
916 * slot_remove - Removes a node from the linked list of slots.
917 * @old_slot: slot to remove
918 *
919 * Returns 0 if successful, !0 otherwise.
920 */
921static int slot_remove(struct pci_func * old_slot)
922{
923 struct pci_func *next;
924
925 if (old_slot == NULL)
926 return(1);
927
928 next = shpchp_slot_list[old_slot->bus];
929
930 if (next == NULL) {
931 return(1);
932 }
933
934 if (next == old_slot) {
935 shpchp_slot_list[old_slot->bus] = old_slot->next;
936 shpchp_destroy_board_resources(old_slot);
937 kfree(old_slot);
938 return(0);
939 }
940
941 while ((next->next != old_slot) && (next->next != NULL)) {
942 next = next->next;
943 }
944
945 if (next->next == old_slot) {
946 next->next = old_slot->next;
947 shpchp_destroy_board_resources(old_slot);
948 kfree(old_slot);
949 return(0);
950 } else
951 return(2);
952}
953
954
955/**
956 * bridge_slot_remove - Removes a node from the linked list of slots.
957 * @bridge: bridge to remove
958 *
959 * Returns 0 if successful, !0 otherwise.
960 */
961static int bridge_slot_remove(struct pci_func *bridge)
962{
963 u8 subordinateBus, secondaryBus;
964 u8 tempBus;
965 struct pci_func *next;
966
967 if (bridge == NULL)
968 return(1);
969
970 secondaryBus = (bridge->config_space[0x06] >> 8) & 0xFF;
971 subordinateBus = (bridge->config_space[0x06] >> 16) & 0xFF;
972
973 for (tempBus = secondaryBus; tempBus <= subordinateBus; tempBus++) {
974 next = shpchp_slot_list[tempBus];
975
976 while (!slot_remove(next)) {
977 next = shpchp_slot_list[tempBus];
978 }
979 }
980
981 next = shpchp_slot_list[bridge->bus];
982
983 if (next == NULL) {
984 return(1);
985 }
986
987 if (next == bridge) {
988 shpchp_slot_list[bridge->bus] = bridge->next;
989 kfree(bridge);
990 return(0);
991 }
992
993 while ((next->next != bridge) && (next->next != NULL)) {
994 next = next->next;
995 }
996
997 if (next->next == bridge) {
998 next->next = bridge->next;
999 kfree(bridge);
1000 return(0);
1001 } else
1002 return(2);
1003}
1004
1005
1006/**
1007 * shpchp_slot_find - Looks for a node by bus, and device, multiple functions accessed
1008 * @bus: bus to find
1009 * @device: device to find
1010 * @index: is 0 for first function found, 1 for the second...
1011 *
1012 * Returns pointer to the node if successful, %NULL otherwise.
1013 */
1014struct pci_func *shpchp_slot_find(u8 bus, u8 device, u8 index)
1015{
1016 int found = -1;
1017 struct pci_func *func;
1018
1019 func = shpchp_slot_list[bus];
1020
1021 if ((func == NULL) || ((func->device == device) && (index == 0)))
1022 return(func);
1023
1024 if (func->device == device)
1025 found++;
1026
1027 while (func->next != NULL) {
1028 func = func->next;
1029
1030 if (func->device == device)
1031 found++;
1032
1033 if (found == index)
1034 return(func);
1035 }
1036
1037 return(NULL);
1038}
1039
1040static int is_bridge(struct pci_func * func)
1041{
1042 /* Check the header type */
1043 if (((func->config_space[0x03] >> 16) & 0xFF) == 0x01)
1044 return 1;
1045 else
1046 return 0;
1047}
1048
1049
1050/* The following routines constitute the bulk of the 236/* The following routines constitute the bulk of the
1051 hotplug controller logic 237 hotplug controller logic
1052 */ 238 */
1053static u32 change_bus_speed(struct controller *ctrl, struct slot *p_slot, enum pci_bus_speed speed) 239static int change_bus_speed(struct controller *ctrl, struct slot *p_slot,
240 enum pci_bus_speed speed)
1054{ 241{
1055 u32 rc = 0; 242 int rc = 0;
1056 243
1057 dbg("%s: change to speed %d\n", __FUNCTION__, speed); 244 dbg("%s: change to speed %d\n", __FUNCTION__, speed);
1058 down(&ctrl->crit_sect); 245 down(&ctrl->crit_sect);
@@ -1074,10 +261,11 @@ static u32 change_bus_speed(struct controller *ctrl, struct slot *p_slot, enum p
1074 return rc; 261 return rc;
1075} 262}
1076 263
1077static u32 fix_bus_speed(struct controller *ctrl, struct slot *pslot, u8 flag, 264static int fix_bus_speed(struct controller *ctrl, struct slot *pslot,
1078enum pci_bus_speed asp, enum pci_bus_speed bsp, enum pci_bus_speed msp) 265 u8 flag, enum pci_bus_speed asp, enum pci_bus_speed bsp,
266 enum pci_bus_speed msp)
1079{ 267{
1080 u32 rc = 0; 268 int rc = 0;
1081 269
1082 if (flag != 0) { /* Other slots on the same bus are occupied */ 270 if (flag != 0) { /* Other slots on the same bus are occupied */
1083 if ( asp < bsp ) { 271 if ( asp < bsp ) {
@@ -1116,23 +304,20 @@ enum pci_bus_speed asp, enum pci_bus_speed bsp, enum pci_bus_speed msp)
1116 * Configures board 304 * Configures board
1117 * 305 *
1118 */ 306 */
1119static u32 board_added(struct pci_func * func, struct controller * ctrl) 307static int board_added(struct slot *p_slot)
1120{ 308{
1121 u8 hp_slot; 309 u8 hp_slot;
1122 u8 slots_not_empty = 0; 310 u8 slots_not_empty = 0;
1123 int index; 311 int rc = 0;
1124 u32 temp_register = 0xFFFFFFFF;
1125 u32 retval, rc = 0;
1126 struct pci_func *new_func = NULL;
1127 struct slot *p_slot;
1128 struct resource_lists res_lists;
1129 enum pci_bus_speed adapter_speed, bus_speed, max_bus_speed; 312 enum pci_bus_speed adapter_speed, bus_speed, max_bus_speed;
1130 u8 pi, mode; 313 u8 pi, mode;
314 struct controller *ctrl = p_slot->ctrl;
1131 315
1132 p_slot = shpchp_find_slot(ctrl, func->device); 316 hp_slot = p_slot->device - ctrl->slot_device_offset;
1133 hp_slot = func->device - ctrl->slot_device_offset;
1134 317
1135 dbg("%s: func->device, slot_offset, hp_slot = %d, %d ,%d\n", __FUNCTION__, func->device, ctrl->slot_device_offset, hp_slot); 318 dbg("%s: p_slot->device, slot_offset, hp_slot = %d, %d ,%d\n",
319 __FUNCTION__, p_slot->device,
320 ctrl->slot_device_offset, hp_slot);
1136 321
1137 /* Wait for exclusive access to hardware */ 322 /* Wait for exclusive access to hardware */
1138 down(&ctrl->crit_sect); 323 down(&ctrl->crit_sect);
@@ -1320,143 +505,68 @@ static u32 board_added(struct pci_func * func, struct controller * ctrl)
1320 up(&ctrl->crit_sect); 505 up(&ctrl->crit_sect);
1321 506
1322 /* Wait for ~1 second */ 507 /* Wait for ~1 second */
1323 dbg("%s: before long_delay\n", __FUNCTION__);
1324 wait_for_ctrl_irq (ctrl); 508 wait_for_ctrl_irq (ctrl);
1325 dbg("%s: after long_delay\n", __FUNCTION__);
1326 509
1327 dbg("%s: func status = %x\n", __FUNCTION__, func->status); 510 dbg("%s: slot status = %x\n", __FUNCTION__, p_slot->status);
1328 /* Check for a power fault */ 511 /* Check for a power fault */
1329 if (func->status == 0xFF) { 512 if (p_slot->status == 0xFF) {
1330 /* power fault occurred, but it was benign */ 513 /* power fault occurred, but it was benign */
1331 temp_register = 0xFFFFFFFF; 514 dbg("%s: power fault\n", __FUNCTION__);
1332 dbg("%s: temp register set to %x by power fault\n", __FUNCTION__, temp_register);
1333 rc = POWER_FAILURE; 515 rc = POWER_FAILURE;
1334 func->status = 0; 516 p_slot->status = 0;
1335 } else { 517 goto err_exit;
1336 /* Get vendor/device ID u32 */
1337 rc = pci_bus_read_config_dword (ctrl->pci_dev->subordinate, PCI_DEVFN(func->device, func->function),
1338 PCI_VENDOR_ID, &temp_register);
1339 dbg("%s: pci_bus_read_config_dword returns %d\n", __FUNCTION__, rc);
1340 dbg("%s: temp_register is %x\n", __FUNCTION__, temp_register);
1341
1342 if (rc != 0) {
1343 /* Something's wrong here */
1344 temp_register = 0xFFFFFFFF;
1345 dbg("%s: temp register set to %x by error\n", __FUNCTION__, temp_register);
1346 }
1347 /* Preset return code. It will be changed later if things go okay. */
1348 rc = NO_ADAPTER_PRESENT;
1349 } 518 }
1350 519
1351 /* All F's is an empty slot or an invalid board */ 520 if (shpchp_configure_device(p_slot)) {
1352 if (temp_register != 0xFFFFFFFF) { /* Check for a board in the slot */ 521 err("Cannot add device at 0x%x:0x%x\n", p_slot->bus,
1353 res_lists.io_head = ctrl->io_head; 522 p_slot->device);
1354 res_lists.mem_head = ctrl->mem_head; 523 goto err_exit;
1355 res_lists.p_mem_head = ctrl->p_mem_head; 524 }
1356 res_lists.bus_head = ctrl->bus_head;
1357 res_lists.irqs = NULL;
1358
1359 rc = configure_new_device(ctrl, func, 0, &res_lists, 0, 0);
1360 dbg("%s: back from configure_new_device\n", __FUNCTION__);
1361
1362 ctrl->io_head = res_lists.io_head;
1363 ctrl->mem_head = res_lists.mem_head;
1364 ctrl->p_mem_head = res_lists.p_mem_head;
1365 ctrl->bus_head = res_lists.bus_head;
1366
1367 shpchp_resource_sort_and_combine(&(ctrl->mem_head));
1368 shpchp_resource_sort_and_combine(&(ctrl->p_mem_head));
1369 shpchp_resource_sort_and_combine(&(ctrl->io_head));
1370 shpchp_resource_sort_and_combine(&(ctrl->bus_head));
1371
1372 if (rc) {
1373 /* Wait for exclusive access to hardware */
1374 down(&ctrl->crit_sect);
1375
1376 /* turn off slot, turn on Amber LED, turn off Green LED */
1377 retval = p_slot->hpc_ops->slot_disable(p_slot);
1378 if (retval) {
1379 err("%s: Issue of Slot Enable command failed\n", __FUNCTION__);
1380 /* Done with exclusive hardware access */
1381 up(&ctrl->crit_sect);
1382 return retval;
1383 }
1384 /* Wait for the command to complete */
1385 wait_for_ctrl_irq (ctrl);
1386
1387 retval = p_slot->hpc_ops->check_cmd_status(ctrl);
1388 if (retval) {
1389 err("%s: Failed to disable slot, error code(%d)\n", __FUNCTION__, retval);
1390 /* Done with exclusive hardware access */
1391 up(&ctrl->crit_sect);
1392 return retval;
1393 }
1394
1395 /* Done with exclusive hardware access */
1396 up(&ctrl->crit_sect);
1397 525
1398 return(rc); 526 p_slot->status = 0;
1399 } 527 p_slot->is_a_board = 0x01;
1400 shpchp_save_slot_config(ctrl, func); 528 p_slot->pwr_save = 1;
1401 529
1402 func->status = 0; 530 /* Wait for exclusive access to hardware */
1403 func->switch_save = 0x10; 531 down(&ctrl->crit_sect);
1404 func->is_a_board = 0x01;
1405 func->pwr_save = 1;
1406 532
1407 /* Next, we will instantiate the linux pci_dev structures 533 p_slot->hpc_ops->green_led_on(p_slot);
1408 * (with appropriate driver notification, if already present)
1409 */
1410 index = 0;
1411 do {
1412 new_func = shpchp_slot_find(ctrl->slot_bus, func->device, index++);
1413 if (new_func && !new_func->pci_dev) {
1414 dbg("%s:call pci_hp_configure_dev\n", __FUNCTION__);
1415 shpchp_configure_device(ctrl, new_func);
1416 }
1417 } while (new_func);
1418 534
1419 /* Wait for exclusive access to hardware */ 535 /* Wait for the command to complete */
1420 down(&ctrl->crit_sect); 536 wait_for_ctrl_irq (ctrl);
1421 537
1422 p_slot->hpc_ops->green_led_on(p_slot); 538 /* Done with exclusive hardware access */
539 up(&ctrl->crit_sect);
1423 540
1424 /* Wait for the command to complete */ 541 return 0;
1425 wait_for_ctrl_irq (ctrl);
1426 542
543err_exit:
544 /* Wait for exclusive access to hardware */
545 down(&ctrl->crit_sect);
1427 546
547 /* turn off slot, turn on Amber LED, turn off Green LED */
548 rc = p_slot->hpc_ops->slot_disable(p_slot);
549 if (rc) {
550 err("%s: Issue of Slot Disable command failed\n", __FUNCTION__);
1428 /* Done with exclusive hardware access */ 551 /* Done with exclusive hardware access */
1429 up(&ctrl->crit_sect); 552 up(&ctrl->crit_sect);
553 return rc;
554 }
555 /* Wait for the command to complete */
556 wait_for_ctrl_irq (ctrl);
1430 557
1431 } else { 558 rc = p_slot->hpc_ops->check_cmd_status(ctrl);
1432 /* Wait for exclusive access to hardware */ 559 if (rc) {
1433 down(&ctrl->crit_sect); 560 err("%s: Failed to disable slot, error code(%d)\n", __FUNCTION__, rc);
1434
1435 /* turn off slot, turn on Amber LED, turn off Green LED */
1436 rc = p_slot->hpc_ops->slot_disable(p_slot);
1437 if (rc) {
1438 err("%s: Issue of Slot Disable command failed\n", __FUNCTION__);
1439 /* Done with exclusive hardware access */
1440 up(&ctrl->crit_sect);
1441 return rc;
1442 }
1443 /* Wait for the command to complete */
1444 wait_for_ctrl_irq (ctrl);
1445
1446 rc = p_slot->hpc_ops->check_cmd_status(ctrl);
1447 if (rc) {
1448 err("%s: Failed to disable slot, error code(%d)\n", __FUNCTION__, rc);
1449 /* Done with exclusive hardware access */
1450 up(&ctrl->crit_sect);
1451 return rc;
1452 }
1453
1454 /* Done with exclusive hardware access */ 561 /* Done with exclusive hardware access */
1455 up(&ctrl->crit_sect); 562 up(&ctrl->crit_sect);
1456 563 return rc;
1457 return(rc);
1458 } 564 }
1459 return 0; 565
566 /* Done with exclusive hardware access */
567 up(&ctrl->crit_sect);
568
569 return(rc);
1460} 570}
1461 571
1462 572
@@ -1464,55 +574,23 @@ static u32 board_added(struct pci_func * func, struct controller * ctrl)
1464 * remove_board - Turns off slot and LED's 574 * remove_board - Turns off slot and LED's
1465 * 575 *
1466 */ 576 */
1467static u32 remove_board(struct pci_func *func, struct controller *ctrl) 577static int remove_board(struct slot *p_slot)
1468{ 578{
1469 int index; 579 struct controller *ctrl = p_slot->ctrl;
1470 u8 skip = 0;
1471 u8 device;
1472 u8 hp_slot; 580 u8 hp_slot;
1473 u32 rc; 581 int rc;
1474 struct resource_lists res_lists;
1475 struct pci_func *temp_func;
1476 struct slot *p_slot;
1477
1478 if (func == NULL)
1479 return(1);
1480 582
1481 if (shpchp_unconfigure_device(func)) 583 if (shpchp_unconfigure_device(p_slot))
1482 return(1); 584 return(1);
1483 585
1484 device = func->device; 586 hp_slot = p_slot->device - ctrl->slot_device_offset;
1485
1486 hp_slot = func->device - ctrl->slot_device_offset;
1487 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); 587 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset);
1488 588
1489 dbg("In %s, hp_slot = %d\n", __FUNCTION__, hp_slot); 589 dbg("In %s, hp_slot = %d\n", __FUNCTION__, hp_slot);
1490 590
1491 if ((ctrl->add_support) &&
1492 !(func->bus_head || func->mem_head || func->p_mem_head || func->io_head)) {
1493 /* Here we check to see if we've saved any of the board's
1494 * resources already. If so, we'll skip the attempt to
1495 * determine what's being used.
1496 */
1497 index = 0;
1498
1499 temp_func = func;
1500
1501 while ((temp_func = shpchp_slot_find(temp_func->bus, temp_func->device, index++))) {
1502 if (temp_func->bus_head || temp_func->mem_head
1503 || temp_func->p_mem_head || temp_func->io_head) {
1504 skip = 1;
1505 break;
1506 }
1507 }
1508
1509 if (!skip)
1510 rc = shpchp_save_used_resources(ctrl, func, DISABLE_CARD);
1511 }
1512 /* Change status to shutdown */ 591 /* Change status to shutdown */
1513 if (func->is_a_board) 592 if (p_slot->is_a_board)
1514 func->status = 0x01; 593 p_slot->status = 0x01;
1515 func->configured = 0;
1516 594
1517 /* Wait for exclusive access to hardware */ 595 /* Wait for exclusive access to hardware */
1518 down(&ctrl->crit_sect); 596 down(&ctrl->crit_sect);
@@ -1549,55 +627,8 @@ static u32 remove_board(struct pci_func *func, struct controller *ctrl)
1549 /* Done with exclusive hardware access */ 627 /* Done with exclusive hardware access */
1550 up(&ctrl->crit_sect); 628 up(&ctrl->crit_sect);
1551 629
1552 if (ctrl->add_support) { 630 p_slot->pwr_save = 0;
1553 while (func) { 631 p_slot->is_a_board = 0;
1554 res_lists.io_head = ctrl->io_head;
1555 res_lists.mem_head = ctrl->mem_head;
1556 res_lists.p_mem_head = ctrl->p_mem_head;
1557 res_lists.bus_head = ctrl->bus_head;
1558
1559 dbg("Returning resources to ctlr lists for (B/D/F) = (%#x/%#x/%#x)\n", func->bus,
1560 func->device, func->function);
1561
1562 shpchp_return_board_resources(func, &res_lists);
1563
1564 ctrl->io_head = res_lists.io_head;
1565 ctrl->mem_head = res_lists.mem_head;
1566 ctrl->p_mem_head = res_lists.p_mem_head;
1567 ctrl->bus_head = res_lists.bus_head;
1568
1569 shpchp_resource_sort_and_combine(&(ctrl->mem_head));
1570 shpchp_resource_sort_and_combine(&(ctrl->p_mem_head));
1571 shpchp_resource_sort_and_combine(&(ctrl->io_head));
1572 shpchp_resource_sort_and_combine(&(ctrl->bus_head));
1573
1574 if (is_bridge(func)) {
1575 dbg("PCI Bridge Hot-Remove s:b:d:f(%02x:%02x:%02x:%02x)\n", ctrl->seg, func->bus,
1576 func->device, func->function);
1577 bridge_slot_remove(func);
1578 } else
1579 dbg("PCI Function Hot-Remove s:b:d:f(%02x:%02x:%02x:%02x)\n", ctrl->seg, func->bus,
1580 func->device, func->function);
1581 slot_remove(func);
1582
1583 func = shpchp_slot_find(ctrl->slot_bus, device, 0);
1584 }
1585
1586 /* Setup slot structure with entry for empty slot */
1587 func = shpchp_slot_create(ctrl->slot_bus);
1588
1589 if (func == NULL) {
1590 return(1);
1591 }
1592
1593 func->bus = ctrl->slot_bus;
1594 func->device = device;
1595 func->function = 0;
1596 func->configured = 0;
1597 func->switch_save = 0x10;
1598 func->pwr_save = 0;
1599 func->is_a_board = 0;
1600 }
1601 632
1602 return 0; 633 return 0;
1603} 634}
@@ -1633,13 +664,11 @@ static void shpchp_pushbutton_thread (unsigned long slot)
1633 p_slot->hpc_ops->get_power_status(p_slot, &getstatus); 664 p_slot->hpc_ops->get_power_status(p_slot, &getstatus);
1634 if (getstatus) { 665 if (getstatus) {
1635 p_slot->state = POWEROFF_STATE; 666 p_slot->state = POWEROFF_STATE;
1636 dbg("In power_down_board, b:d(%x:%x)\n", p_slot->bus, p_slot->device);
1637 667
1638 shpchp_disable_slot(p_slot); 668 shpchp_disable_slot(p_slot);
1639 p_slot->state = STATIC_STATE; 669 p_slot->state = STATIC_STATE;
1640 } else { 670 } else {
1641 p_slot->state = POWERON_STATE; 671 p_slot->state = POWERON_STATE;
1642 dbg("In add_board, b:d(%x:%x)\n", p_slot->bus, p_slot->device);
1643 672
1644 if (shpchp_enable_slot(p_slot)) { 673 if (shpchp_enable_slot(p_slot)) {
1645 /* Wait for exclusive access to hardware */ 674 /* Wait for exclusive access to hardware */
@@ -1701,7 +730,6 @@ int shpchp_event_start_thread (void)
1701 err ("Can't start up our event thread\n"); 730 err ("Can't start up our event thread\n");
1702 return -1; 731 return -1;
1703 } 732 }
1704 dbg("Our event thread pid = %d\n", pid);
1705 return 0; 733 return 0;
1706} 734}
1707 735
@@ -1709,9 +737,7 @@ int shpchp_event_start_thread (void)
1709void shpchp_event_stop_thread (void) 737void shpchp_event_stop_thread (void)
1710{ 738{
1711 event_finished = 1; 739 event_finished = 1;
1712 dbg("event_thread finish command given\n");
1713 up(&event_semaphore); 740 up(&event_semaphore);
1714 dbg("wait for event_thread to exit\n");
1715 down(&event_exit); 741 down(&event_exit);
1716} 742}
1717 743
@@ -1739,12 +765,10 @@ static void interrupt_event_handler(struct controller *ctrl)
1739{ 765{
1740 int loop = 0; 766 int loop = 0;
1741 int change = 1; 767 int change = 1;
1742 struct pci_func *func;
1743 u8 hp_slot; 768 u8 hp_slot;
1744 u8 getstatus; 769 u8 getstatus;
1745 struct slot *p_slot; 770 struct slot *p_slot;
1746 771
1747 dbg("%s:\n", __FUNCTION__);
1748 while (change) { 772 while (change) {
1749 change = 0; 773 change = 0;
1750 774
@@ -1754,12 +778,8 @@ static void interrupt_event_handler(struct controller *ctrl)
1754 ctrl->event_queue[loop].event_type); 778 ctrl->event_queue[loop].event_type);
1755 hp_slot = ctrl->event_queue[loop].hp_slot; 779 hp_slot = ctrl->event_queue[loop].hp_slot;
1756 780
1757 func = shpchp_slot_find(ctrl->slot_bus, (hp_slot + ctrl->slot_device_offset), 0);
1758
1759 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); 781 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset);
1760 782
1761 dbg("%s: hp_slot %d, func %p, p_slot %p\n", __FUNCTION__, hp_slot, func, p_slot);
1762
1763 if (ctrl->event_queue[loop].event_type == INT_BUTTON_CANCEL) { 783 if (ctrl->event_queue[loop].event_type == INT_BUTTON_CANCEL) {
1764 dbg("%s: button cancel\n", __FUNCTION__); 784 dbg("%s: button cancel\n", __FUNCTION__);
1765 del_timer(&p_slot->task_event); 785 del_timer(&p_slot->task_event);
@@ -1880,13 +900,6 @@ int shpchp_enable_slot (struct slot *p_slot)
1880{ 900{
1881 u8 getstatus = 0; 901 u8 getstatus = 0;
1882 int rc; 902 int rc;
1883 struct pci_func *func;
1884
1885 func = shpchp_slot_find(p_slot->bus, p_slot->device, 0);
1886 if (!func) {
1887 dbg("%s: Error! slot NULL\n", __FUNCTION__);
1888 return -ENODEV;
1889 }
1890 903
1891 /* Check to see if (latch closed, card present, power off) */ 904 /* Check to see if (latch closed, card present, power off) */
1892 down(&p_slot->ctrl->crit_sect); 905 down(&p_slot->ctrl->crit_sect);
@@ -1910,72 +923,34 @@ int shpchp_enable_slot (struct slot *p_slot)
1910 } 923 }
1911 up(&p_slot->ctrl->crit_sect); 924 up(&p_slot->ctrl->crit_sect);
1912 925
1913 slot_remove(func); 926 p_slot->is_a_board = 1;
1914
1915 func = shpchp_slot_create(p_slot->bus);
1916 if (func == NULL)
1917 return -ENOMEM;
1918
1919 func->bus = p_slot->bus;
1920 func->device = p_slot->device;
1921 func->function = 0;
1922 func->configured = 0;
1923 func->is_a_board = 1;
1924 927
1925 /* We have to save the presence info for these slots */ 928 /* We have to save the presence info for these slots */
1926 p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save)); 929 p_slot->hpc_ops->get_adapter_status(p_slot, &(p_slot->presence_save));
1927 p_slot->hpc_ops->get_power_status(p_slot, &(func->pwr_save)); 930 p_slot->hpc_ops->get_power_status(p_slot, &(p_slot->pwr_save));
1928 dbg("%s: func->pwr_save %x\n", __FUNCTION__, func->pwr_save); 931 dbg("%s: p_slot->pwr_save %x\n", __FUNCTION__, p_slot->pwr_save);
1929 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 932 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
1930 func->switch_save = !getstatus? 0x10:0;
1931 933
1932 rc = board_added(func, p_slot->ctrl); 934 rc = board_added(p_slot);
1933 if (rc) { 935 if (rc) {
1934 if (is_bridge(func)) 936 p_slot->hpc_ops->get_adapter_status(p_slot,
1935 bridge_slot_remove(func); 937 &(p_slot->presence_save));
1936 else
1937 slot_remove(func);
1938
1939 /* Setup slot structure with entry for empty slot */
1940 func = shpchp_slot_create(p_slot->bus);
1941 if (func == NULL)
1942 return -ENOMEM; /* Out of memory */
1943
1944 func->bus = p_slot->bus;
1945 func->device = p_slot->device;
1946 func->function = 0;
1947 func->configured = 0;
1948 func->is_a_board = 1;
1949
1950 /* We have to save the presence info for these slots */
1951 p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save));
1952 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 938 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
1953 func->switch_save = !getstatus? 0x10:0;
1954 } 939 }
1955 940
1956 if (p_slot) 941 update_slot_info(p_slot);
1957 update_slot_info(p_slot);
1958
1959 return rc; 942 return rc;
1960} 943}
1961 944
1962 945
1963int shpchp_disable_slot (struct slot *p_slot) 946int shpchp_disable_slot (struct slot *p_slot)
1964{ 947{
1965 u8 class_code, header_type, BCR;
1966 u8 index = 0;
1967 u8 getstatus = 0; 948 u8 getstatus = 0;
1968 u32 rc = 0;
1969 int ret = 0; 949 int ret = 0;
1970 unsigned int devfn;
1971 struct pci_bus *pci_bus;
1972 struct pci_func *func;
1973 950
1974 if (!p_slot->ctrl) 951 if (!p_slot->ctrl)
1975 return -ENODEV; 952 return -ENODEV;
1976 953
1977 pci_bus = p_slot->ctrl->pci_dev->subordinate;
1978
1979 /* Check to see if (latch closed, card present, power on) */ 954 /* Check to see if (latch closed, card present, power on) */
1980 down(&p_slot->ctrl->crit_sect); 955 down(&p_slot->ctrl->crit_sect);
1981 956
@@ -1999,849 +974,8 @@ int shpchp_disable_slot (struct slot *p_slot)
1999 } 974 }
2000 up(&p_slot->ctrl->crit_sect); 975 up(&p_slot->ctrl->crit_sect);
2001 976
2002 func = shpchp_slot_find(p_slot->bus, p_slot->device, index++); 977 ret = remove_board(p_slot);
2003 978 update_slot_info(p_slot);
2004 /* Make sure there are no video controllers here 979 return ret;
2005 * for all func of p_slot
2006 */
2007 while (func && !rc) {
2008 pci_bus->number = func->bus;
2009 devfn = PCI_DEVFN(func->device, func->function);
2010
2011 /* Check the Class Code */
2012 rc = pci_bus_read_config_byte (pci_bus, devfn, 0x0B, &class_code);
2013 if (rc)
2014 return -ENODEV;
2015
2016 if (class_code == PCI_BASE_CLASS_DISPLAY) {
2017 /* Display/Video adapter (not supported) */
2018 rc = REMOVE_NOT_SUPPORTED;
2019 } else {
2020 /* See if it's a bridge */
2021 rc = pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
2022 if (rc)
2023 return -ENODEV;
2024
2025 /* If it's a bridge, check the VGA Enable bit */
2026 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
2027 rc = pci_bus_read_config_byte (pci_bus, devfn, PCI_BRIDGE_CONTROL, &BCR);
2028 if (rc)
2029 return -ENODEV;
2030
2031 /* If the VGA Enable bit is set, remove isn't supported */
2032 if (BCR & PCI_BRIDGE_CTL_VGA) {
2033 rc = REMOVE_NOT_SUPPORTED;
2034 }
2035 }
2036 }
2037
2038 func = shpchp_slot_find(p_slot->bus, p_slot->device, index++);
2039 }
2040
2041 func = shpchp_slot_find(p_slot->bus, p_slot->device, 0);
2042 if ((func != NULL) && !rc) {
2043 rc = remove_board(func, p_slot->ctrl);
2044 } else if (!rc)
2045 rc = -ENODEV;
2046
2047 if (p_slot)
2048 update_slot_info(p_slot);
2049
2050 return rc;
2051}
2052
2053
2054/**
2055 * configure_new_device - Configures the PCI header information of one board.
2056 *
2057 * @ctrl: pointer to controller structure
2058 * @func: pointer to function structure
2059 * @behind_bridge: 1 if this is a recursive call, 0 if not
2060 * @resources: pointer to set of resource lists
2061 *
2062 * Returns 0 if success
2063 *
2064 */
2065static u32 configure_new_device (struct controller * ctrl, struct pci_func * func,
2066 u8 behind_bridge, struct resource_lists * resources, u8 bridge_bus, u8 bridge_dev)
2067{
2068 u8 temp_byte, function, max_functions, stop_it;
2069 int rc;
2070 u32 ID;
2071 struct pci_func *new_slot;
2072 struct pci_bus lpci_bus, *pci_bus;
2073 int index;
2074
2075 new_slot = func;
2076
2077 dbg("%s\n", __FUNCTION__);
2078 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
2079 pci_bus = &lpci_bus;
2080 pci_bus->number = func->bus;
2081
2082 /* Check for Multi-function device */
2083 rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(func->device, func->function), 0x0E, &temp_byte);
2084 if (rc) {
2085 dbg("%s: rc = %d\n", __FUNCTION__, rc);
2086 return rc;
2087 }
2088
2089 if (temp_byte & 0x80) /* Multi-function device */
2090 max_functions = 8;
2091 else
2092 max_functions = 1;
2093
2094 function = 0;
2095
2096 do {
2097 rc = configure_new_function(ctrl, new_slot, behind_bridge, resources, bridge_bus, bridge_dev);
2098
2099 if (rc) {
2100 dbg("configure_new_function failed %d\n",rc);
2101 index = 0;
2102
2103 while (new_slot) {
2104 new_slot = shpchp_slot_find(new_slot->bus, new_slot->device, index++);
2105
2106 if (new_slot)
2107 shpchp_return_board_resources(new_slot, resources);
2108 }
2109
2110 return(rc);
2111 }
2112
2113 function++;
2114
2115 stop_it = 0;
2116
2117 /* The following loop skips to the next present function
2118 * and creates a board structure
2119 */
2120
2121 while ((function < max_functions) && (!stop_it)) {
2122 pci_bus_read_config_dword(pci_bus, PCI_DEVFN(func->device, function), 0x00, &ID);
2123
2124 if (ID == 0xFFFFFFFF) { /* There's nothing there. */
2125 function++;
2126 } else { /* There's something there */
2127 /* Setup slot structure. */
2128 new_slot = shpchp_slot_create(func->bus);
2129
2130 if (new_slot == NULL) {
2131 /* Out of memory */
2132 return(1);
2133 }
2134
2135 new_slot->bus = func->bus;
2136 new_slot->device = func->device;
2137 new_slot->function = function;
2138 new_slot->is_a_board = 1;
2139 new_slot->status = 0;
2140
2141 stop_it++;
2142 }
2143 }
2144
2145 } while (function < max_functions);
2146 dbg("returning from configure_new_device\n");
2147
2148 return 0;
2149}
2150
2151
2152/*
2153 * Configuration logic that involves the hotplug data structures and
2154 * their bookkeeping
2155 */
2156
2157
2158/**
2159 * configure_new_function - Configures the PCI header information of one device
2160 *
2161 * @ctrl: pointer to controller structure
2162 * @func: pointer to function structure
2163 * @behind_bridge: 1 if this is a recursive call, 0 if not
2164 * @resources: pointer to set of resource lists
2165 *
2166 * Calls itself recursively for bridged devices.
2167 * Returns 0 if success
2168 *
2169 */
2170static int configure_new_function (struct controller * ctrl, struct pci_func * func,
2171 u8 behind_bridge, struct resource_lists *resources, u8 bridge_bus, u8 bridge_dev)
2172{
2173 int cloop;
2174 u8 temp_byte;
2175 u8 device;
2176 u8 class_code;
2177 u16 temp_word;
2178 u32 rc;
2179 u32 temp_register;
2180 u32 base;
2181 u32 ID;
2182 unsigned int devfn;
2183 struct pci_resource *mem_node;
2184 struct pci_resource *p_mem_node;
2185 struct pci_resource *io_node;
2186 struct pci_resource *bus_node;
2187 struct pci_resource *hold_mem_node;
2188 struct pci_resource *hold_p_mem_node;
2189 struct pci_resource *hold_IO_node;
2190 struct pci_resource *hold_bus_node;
2191 struct irq_mapping irqs;
2192 struct pci_func *new_slot;
2193 struct pci_bus lpci_bus, *pci_bus;
2194 struct resource_lists temp_resources;
2195#if defined(CONFIG_X86_64)
2196 u8 IRQ=0;
2197#endif
2198
2199 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
2200 pci_bus = &lpci_bus;
2201 pci_bus->number = func->bus;
2202 devfn = PCI_DEVFN(func->device, func->function);
2203
2204 /* Check for Bridge */
2205 rc = pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &temp_byte);
2206 if (rc)
2207 return rc;
2208
2209 if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */
2210 /* set Primary bus */
2211 dbg("set Primary bus = 0x%x\n", func->bus);
2212 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_PRIMARY_BUS, func->bus);
2213 if (rc)
2214 return rc;
2215
2216 /* find range of busses to use */
2217 bus_node = get_max_resource(&resources->bus_head, 1L);
2218
2219 /* If we don't have any busses to allocate, we can't continue */
2220 if (!bus_node) {
2221 err("Got NO bus resource to use\n");
2222 return -ENOMEM;
2223 }
2224 dbg("Got ranges of buses to use: base:len=0x%x:%x\n", bus_node->base, bus_node->length);
2225
2226 /* set Secondary bus */
2227 temp_byte = (u8)bus_node->base;
2228 dbg("set Secondary bus = 0x%x\n", temp_byte);
2229 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, temp_byte);
2230 if (rc)
2231 return rc;
2232
2233 /* set subordinate bus */
2234 temp_byte = (u8)(bus_node->base + bus_node->length - 1);
2235 dbg("set subordinate bus = 0x%x\n", temp_byte);
2236 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_SUBORDINATE_BUS, temp_byte);
2237 if (rc)
2238 return rc;
2239
2240 /* Set HP parameters (Cache Line Size, Latency Timer) */
2241 rc = shpchprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_BRIDGE);
2242 if (rc)
2243 return rc;
2244
2245 /* Setup the IO, memory, and prefetchable windows */
2246
2247 io_node = get_max_resource(&(resources->io_head), 0x1000L);
2248 if (io_node) {
2249 dbg("io_node(base, len, next) (%x, %x, %p)\n", io_node->base, io_node->length, io_node->next);
2250 }
2251
2252 mem_node = get_max_resource(&(resources->mem_head), 0x100000L);
2253 if (mem_node) {
2254 dbg("mem_node(base, len, next) (%x, %x, %p)\n", mem_node->base, mem_node->length, mem_node->next);
2255 }
2256
2257 if (resources->p_mem_head)
2258 p_mem_node = get_max_resource(&(resources->p_mem_head), 0x100000L);
2259 else {
2260 /*
2261 * In some platform implementation, MEM and PMEM are not
2262 * distinguished, and hence ACPI _CRS has only MEM entries
2263 * for both MEM and PMEM.
2264 */
2265 dbg("using MEM for PMEM\n");
2266 p_mem_node = get_max_resource(&(resources->mem_head), 0x100000L);
2267 }
2268 if (p_mem_node) {
2269 dbg("p_mem_node(base, len, next) (%x, %x, %p)\n", p_mem_node->base, p_mem_node->length, p_mem_node->next);
2270 }
2271
2272 /* set up the IRQ info */
2273 if (!resources->irqs) {
2274 irqs.barber_pole = 0;
2275 irqs.interrupt[0] = 0;
2276 irqs.interrupt[1] = 0;
2277 irqs.interrupt[2] = 0;
2278 irqs.interrupt[3] = 0;
2279 irqs.valid_INT = 0;
2280 } else {
2281 irqs.barber_pole = resources->irqs->barber_pole;
2282 irqs.interrupt[0] = resources->irqs->interrupt[0];
2283 irqs.interrupt[1] = resources->irqs->interrupt[1];
2284 irqs.interrupt[2] = resources->irqs->interrupt[2];
2285 irqs.interrupt[3] = resources->irqs->interrupt[3];
2286 irqs.valid_INT = resources->irqs->valid_INT;
2287 }
2288
2289 /* set up resource lists that are now aligned on top and bottom
2290 * for anything behind the bridge.
2291 */
2292 temp_resources.bus_head = bus_node;
2293 temp_resources.io_head = io_node;
2294 temp_resources.mem_head = mem_node;
2295 temp_resources.p_mem_head = p_mem_node;
2296 temp_resources.irqs = &irqs;
2297
2298 /* Make copies of the nodes we are going to pass down so that
2299 * if there is a problem,we can just use these to free resources
2300 */
2301 hold_bus_node = kmalloc(sizeof(*hold_bus_node), GFP_KERNEL);
2302 hold_IO_node = kmalloc(sizeof(*hold_IO_node), GFP_KERNEL);
2303 hold_mem_node = kmalloc(sizeof(*hold_mem_node), GFP_KERNEL);
2304 hold_p_mem_node = kmalloc(sizeof(*hold_p_mem_node), GFP_KERNEL);
2305
2306 if (!hold_bus_node || !hold_IO_node || !hold_mem_node || !hold_p_mem_node) {
2307 kfree(hold_bus_node);
2308 kfree(hold_IO_node);
2309 kfree(hold_mem_node);
2310 kfree(hold_p_mem_node);
2311
2312 return 1;
2313 }
2314
2315 memcpy(hold_bus_node, bus_node, sizeof(struct pci_resource));
2316
2317 bus_node->base += 1;
2318 bus_node->length -= 1;
2319 bus_node->next = NULL;
2320
2321 /* If we have IO resources copy them and fill in the bridge's
2322 * IO range registers
2323 */
2324 if (io_node) {
2325 memcpy(hold_IO_node, io_node, sizeof(struct pci_resource));
2326 io_node->next = NULL;
2327
2328 /* set IO base and Limit registers */
2329 RES_CHECK(io_node->base, 8);
2330 temp_byte = (u8)(io_node->base >> 8);
2331 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_IO_BASE, temp_byte);
2332
2333 RES_CHECK(io_node->base + io_node->length - 1, 8);
2334 temp_byte = (u8)((io_node->base + io_node->length - 1) >> 8);
2335 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
2336 } else {
2337 kfree(hold_IO_node);
2338 hold_IO_node = NULL;
2339 }
2340
2341 /* If we have memory resources copy them and fill in the bridge's
2342 * memory range registers. Otherwise, fill in the range
2343 * registers with values that disable them.
2344 */
2345 if (mem_node) {
2346 memcpy(hold_mem_node, mem_node, sizeof(struct pci_resource));
2347 mem_node->next = NULL;
2348
2349 /* set Mem base and Limit registers */
2350 RES_CHECK(mem_node->base, 16);
2351 temp_word = (u32)(mem_node->base >> 16);
2352 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_MEMORY_BASE, temp_word);
2353
2354 RES_CHECK(mem_node->base + mem_node->length - 1, 16);
2355 temp_word = (u32)((mem_node->base + mem_node->length - 1) >> 16);
2356 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, temp_word);
2357 } else {
2358 temp_word = 0xFFFF;
2359 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_MEMORY_BASE, temp_word);
2360
2361 temp_word = 0x0000;
2362 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, temp_word);
2363
2364 kfree(hold_mem_node);
2365 hold_mem_node = NULL;
2366 }
2367
2368 /* If we have prefetchable memory resources copy them and
2369 * fill in the bridge's memory range registers. Otherwise,
2370 * fill in the range registers with values that disable them.
2371 */
2372 if (p_mem_node) {
2373 memcpy(hold_p_mem_node, p_mem_node, sizeof(struct pci_resource));
2374 p_mem_node->next = NULL;
2375
2376 /* set Pre Mem base and Limit registers */
2377 RES_CHECK(p_mem_node->base, 16);
2378 temp_word = (u32)(p_mem_node->base >> 16);
2379 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, temp_word);
2380
2381 RES_CHECK(p_mem_node->base + p_mem_node->length - 1, 16);
2382 temp_word = (u32)((p_mem_node->base + p_mem_node->length - 1) >> 16);
2383 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
2384 } else {
2385 temp_word = 0xFFFF;
2386 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, temp_word);
2387
2388 temp_word = 0x0000;
2389 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
2390
2391 kfree(hold_p_mem_node);
2392 hold_p_mem_node = NULL;
2393 }
2394
2395 /* Adjust this to compensate for extra adjustment in first loop */
2396 irqs.barber_pole--;
2397
2398 rc = 0;
2399
2400 /* Here we actually find the devices and configure them */
2401 for (device = 0; (device <= 0x1F) && !rc; device++) {
2402 irqs.barber_pole = (irqs.barber_pole + 1) & 0x03;
2403
2404 ID = 0xFFFFFFFF;
2405 pci_bus->number = hold_bus_node->base;
2406 pci_bus_read_config_dword(pci_bus, PCI_DEVFN(device, 0),
2407 PCI_VENDOR_ID, &ID);
2408 pci_bus->number = func->bus;
2409
2410 if (ID != 0xFFFFFFFF) { /* device Present */
2411 /* Setup slot structure. */
2412 new_slot = shpchp_slot_create(hold_bus_node->base);
2413
2414 if (new_slot == NULL) {
2415 /* Out of memory */
2416 rc = -ENOMEM;
2417 continue;
2418 }
2419
2420 new_slot->bus = hold_bus_node->base;
2421 new_slot->device = device;
2422 new_slot->function = 0;
2423 new_slot->is_a_board = 1;
2424 new_slot->status = 0;
2425
2426 rc = configure_new_device(ctrl, new_slot, 1, &temp_resources, func->bus, func->device);
2427 dbg("configure_new_device rc=0x%x\n",rc);
2428 } /* End of IF (device in slot?) */
2429 } /* End of FOR loop */
2430
2431 if (rc) {
2432 shpchp_destroy_resource_list(&temp_resources);
2433
2434 return_resource(&(resources->bus_head), hold_bus_node);
2435 return_resource(&(resources->io_head), hold_IO_node);
2436 return_resource(&(resources->mem_head), hold_mem_node);
2437 return_resource(&(resources->p_mem_head), hold_p_mem_node);
2438 return(rc);
2439 }
2440
2441 /* save the interrupt routing information */
2442 if (resources->irqs) {
2443 resources->irqs->interrupt[0] = irqs.interrupt[0];
2444 resources->irqs->interrupt[1] = irqs.interrupt[1];
2445 resources->irqs->interrupt[2] = irqs.interrupt[2];
2446 resources->irqs->interrupt[3] = irqs.interrupt[3];
2447 resources->irqs->valid_INT = irqs.valid_INT;
2448 } else if (!behind_bridge) {
2449 /* We need to hook up the interrupts here */
2450 for (cloop = 0; cloop < 4; cloop++) {
2451 if (irqs.valid_INT & (0x01 << cloop)) {
2452 rc = shpchp_set_irq(func->bus, func->device,
2453 0x0A + cloop, irqs.interrupt[cloop]);
2454 if (rc) {
2455 shpchp_destroy_resource_list (&temp_resources);
2456 return_resource(&(resources->bus_head), hold_bus_node);
2457 return_resource(&(resources->io_head), hold_IO_node);
2458 return_resource(&(resources->mem_head), hold_mem_node);
2459 return_resource(&(resources->p_mem_head), hold_p_mem_node);
2460 return rc;
2461 }
2462 }
2463 } /* end of for loop */
2464 }
2465
2466 /* Return unused bus resources
2467 * First use the temporary node to store information for the board
2468 */
2469 if (hold_bus_node && bus_node && temp_resources.bus_head) {
2470 hold_bus_node->length = bus_node->base - hold_bus_node->base;
2471
2472 hold_bus_node->next = func->bus_head;
2473 func->bus_head = hold_bus_node;
2474
2475 temp_byte = (u8)(temp_resources.bus_head->base - 1);
2476
2477 /* set subordinate bus */
2478 dbg("re-set subordinate bus = 0x%x\n", temp_byte);
2479 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_SUBORDINATE_BUS, temp_byte);
2480
2481 if (temp_resources.bus_head->length == 0) {
2482 kfree(temp_resources.bus_head);
2483 temp_resources.bus_head = NULL;
2484 } else {
2485 dbg("return bus res of b:d(0x%x:%x) base:len(0x%x:%x)\n",
2486 func->bus, func->device, temp_resources.bus_head->base, temp_resources.bus_head->length);
2487 return_resource(&(resources->bus_head), temp_resources.bus_head);
2488 }
2489 }
2490
2491 /* If we have IO space available and there is some left,
2492 * return the unused portion
2493 */
2494 if (hold_IO_node && temp_resources.io_head) {
2495 io_node = do_pre_bridge_resource_split(&(temp_resources.io_head),
2496 &hold_IO_node, 0x1000);
2497
2498 /* Check if we were able to split something off */
2499 if (io_node) {
2500 hold_IO_node->base = io_node->base + io_node->length;
2501
2502 RES_CHECK(hold_IO_node->base, 8);
2503 temp_byte = (u8)((hold_IO_node->base) >> 8);
2504 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_IO_BASE, temp_byte);
2505
2506 return_resource(&(resources->io_head), io_node);
2507 }
2508
2509 io_node = do_bridge_resource_split(&(temp_resources.io_head), 0x1000);
2510
2511 /* Check if we were able to split something off */
2512 if (io_node) {
2513 /* First use the temporary node to store information for the board */
2514 hold_IO_node->length = io_node->base - hold_IO_node->base;
2515
2516 /* If we used any, add it to the board's list */
2517 if (hold_IO_node->length) {
2518 hold_IO_node->next = func->io_head;
2519 func->io_head = hold_IO_node;
2520
2521 RES_CHECK(io_node->base - 1, 8);
2522 temp_byte = (u8)((io_node->base - 1) >> 8);
2523 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
2524
2525 return_resource(&(resources->io_head), io_node);
2526 } else {
2527 /* it doesn't need any IO */
2528 temp_byte = 0x00;
2529 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
2530
2531 return_resource(&(resources->io_head), io_node);
2532 kfree(hold_IO_node);
2533 }
2534 } else {
2535 /* it used most of the range */
2536 hold_IO_node->next = func->io_head;
2537 func->io_head = hold_IO_node;
2538 }
2539 } else if (hold_IO_node) {
2540 /* it used the whole range */
2541 hold_IO_node->next = func->io_head;
2542 func->io_head = hold_IO_node;
2543 }
2544
2545 /* If we have memory space available and there is some left,
2546 * return the unused portion
2547 */
2548 if (hold_mem_node && temp_resources.mem_head) {
2549 mem_node = do_pre_bridge_resource_split(&(temp_resources.mem_head), &hold_mem_node, 0x100000L);
2550
2551 /* Check if we were able to split something off */
2552 if (mem_node) {
2553 hold_mem_node->base = mem_node->base + mem_node->length;
2554
2555 RES_CHECK(hold_mem_node->base, 16);
2556 temp_word = (u32)((hold_mem_node->base) >> 16);
2557 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_MEMORY_BASE, temp_word);
2558
2559 return_resource(&(resources->mem_head), mem_node);
2560 }
2561
2562 mem_node = do_bridge_resource_split(&(temp_resources.mem_head), 0x100000L);
2563
2564 /* Check if we were able to split something off */
2565 if (mem_node) {
2566 /* First use the temporary node to store information for the board */
2567 hold_mem_node->length = mem_node->base - hold_mem_node->base;
2568
2569 if (hold_mem_node->length) {
2570 hold_mem_node->next = func->mem_head;
2571 func->mem_head = hold_mem_node;
2572
2573 /* configure end address */
2574 RES_CHECK(mem_node->base - 1, 16);
2575 temp_word = (u32)((mem_node->base - 1) >> 16);
2576 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_MEMORY_LIMIT, temp_word);
2577
2578 /* Return unused resources to the pool */
2579 return_resource(&(resources->mem_head), mem_node);
2580 } else {
2581 /* it doesn't need any Mem */
2582 temp_word = 0x0000;
2583 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_MEMORY_LIMIT, temp_word);
2584
2585 return_resource(&(resources->mem_head), mem_node);
2586 kfree(hold_mem_node);
2587 }
2588 } else {
2589 /* it used most of the range */
2590 hold_mem_node->next = func->mem_head;
2591 func->mem_head = hold_mem_node;
2592 }
2593 } else if (hold_mem_node) {
2594 /* it used the whole range */
2595 hold_mem_node->next = func->mem_head;
2596 func->mem_head = hold_mem_node;
2597 }
2598
2599 /* If we have prefetchable memory space available and there is some
2600 * left at the end, return the unused portion
2601 */
2602 if (hold_p_mem_node && temp_resources.p_mem_head) {
2603 p_mem_node = do_pre_bridge_resource_split(&(temp_resources.p_mem_head),
2604 &hold_p_mem_node, 0x100000L);
2605
2606 /* Check if we were able to split something off */
2607 if (p_mem_node) {
2608 hold_p_mem_node->base = p_mem_node->base + p_mem_node->length;
2609
2610 RES_CHECK(hold_p_mem_node->base, 16);
2611 temp_word = (u32)((hold_p_mem_node->base) >> 16);
2612 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_PREF_MEMORY_BASE, temp_word);
2613
2614 return_resource(&(resources->p_mem_head), p_mem_node);
2615 }
2616
2617 p_mem_node = do_bridge_resource_split(&(temp_resources.p_mem_head), 0x100000L);
2618
2619 /* Check if we were able to split something off */
2620 if (p_mem_node) {
2621 /* First use the temporary node to store information for the board */
2622 hold_p_mem_node->length = p_mem_node->base - hold_p_mem_node->base;
2623
2624 /* If we used any, add it to the board's list */
2625 if (hold_p_mem_node->length) {
2626 hold_p_mem_node->next = func->p_mem_head;
2627 func->p_mem_head = hold_p_mem_node;
2628
2629 RES_CHECK(p_mem_node->base - 1, 16);
2630 temp_word = (u32)((p_mem_node->base - 1) >> 16);
2631 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
2632
2633 return_resource(&(resources->p_mem_head), p_mem_node);
2634 } else {
2635 /* it doesn't need any PMem */
2636 temp_word = 0x0000;
2637 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
2638
2639 return_resource(&(resources->p_mem_head), p_mem_node);
2640 kfree(hold_p_mem_node);
2641 }
2642 } else {
2643 /* it used the most of the range */
2644 hold_p_mem_node->next = func->p_mem_head;
2645 func->p_mem_head = hold_p_mem_node;
2646 }
2647 } else if (hold_p_mem_node) {
2648 /* it used the whole range */
2649 hold_p_mem_node->next = func->p_mem_head;
2650 func->p_mem_head = hold_p_mem_node;
2651 }
2652
2653 /* We should be configuring an IRQ and the bridge's base address
2654 * registers if it needs them. Although we have never seen such
2655 * a device
2656 */
2657
2658 shpchprm_enable_card(ctrl, func, PCI_HEADER_TYPE_BRIDGE);
2659
2660 dbg("PCI Bridge Hot-Added s:b:d:f(%02x:%02x:%02x:%02x)\n", ctrl->seg, func->bus, func->device, func->function);
2661 } else if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
2662 /* Standard device */
2663 u64 base64;
2664 rc = pci_bus_read_config_byte (pci_bus, devfn, 0x0B, &class_code);
2665
2666 if (class_code == PCI_BASE_CLASS_DISPLAY)
2667 return (DEVICE_TYPE_NOT_SUPPORTED);
2668
2669 /* Figure out IO and memory needs */
2670 for (cloop = PCI_BASE_ADDRESS_0; cloop <= PCI_BASE_ADDRESS_5; cloop += 4) {
2671 temp_register = 0xFFFFFFFF;
2672
2673 rc = pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
2674 rc = pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp_register);
2675 dbg("Bar[%x]=0x%x on bus:dev:func(0x%x:%x:%x)\n", cloop, temp_register, func->bus, func->device,
2676 func->function);
2677
2678 if (!temp_register)
2679 continue;
2680
2681 base64 = 0L;
2682 if (temp_register & PCI_BASE_ADDRESS_SPACE_IO) {
2683 /* Map IO */
2684
2685 /* set base = amount of IO space */
2686 base = temp_register & 0xFFFFFFFC;
2687 base = ~base + 1;
2688
2689 dbg("NEED IO length(0x%x)\n", base);
2690 io_node = get_io_resource(&(resources->io_head),(ulong)base);
2691
2692 /* allocate the resource to the board */
2693 if (io_node) {
2694 dbg("Got IO base=0x%x(length=0x%x)\n", io_node->base, io_node->length);
2695 base = (u32)io_node->base;
2696 io_node->next = func->io_head;
2697 func->io_head = io_node;
2698 } else {
2699 err("Got NO IO resource(length=0x%x)\n", base);
2700 return -ENOMEM;
2701 }
2702 } else { /* map MEM */
2703 int prefetchable = 1;
2704 struct pci_resource **res_node = &func->p_mem_head;
2705 char *res_type_str = "PMEM";
2706 u32 temp_register2;
2707
2708 if (!(temp_register & PCI_BASE_ADDRESS_MEM_PREFETCH)) {
2709 prefetchable = 0;
2710 res_node = &func->mem_head;
2711 res_type_str++;
2712 }
2713
2714 base = temp_register & 0xFFFFFFF0;
2715 base = ~base + 1;
2716
2717 switch (temp_register & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
2718 case PCI_BASE_ADDRESS_MEM_TYPE_32:
2719 dbg("NEED 32 %s bar=0x%x(length=0x%x)\n", res_type_str, temp_register, base);
2720
2721 if (prefetchable && resources->p_mem_head)
2722 mem_node=get_resource(&(resources->p_mem_head), (ulong)base);
2723 else {
2724 if (prefetchable)
2725 dbg("using MEM for PMEM\n");
2726 mem_node=get_resource(&(resources->mem_head), (ulong)base);
2727 }
2728
2729 /* allocate the resource to the board */
2730 if (mem_node) {
2731 base = (u32)mem_node->base;
2732 mem_node->next = *res_node;
2733 *res_node = mem_node;
2734 dbg("Got 32 %s base=0x%x(length=0x%x)\n", res_type_str, mem_node->base,
2735 mem_node->length);
2736 } else {
2737 err("Got NO 32 %s resource(length=0x%x)\n", res_type_str, base);
2738 return -ENOMEM;
2739 }
2740 break;
2741 case PCI_BASE_ADDRESS_MEM_TYPE_64:
2742 rc = pci_bus_read_config_dword(pci_bus, devfn, cloop+4, &temp_register2);
2743 dbg("NEED 64 %s bar=0x%x:%x(length=0x%x)\n", res_type_str, temp_register2,
2744 temp_register, base);
2745
2746 if (prefetchable && resources->p_mem_head)
2747 mem_node = get_resource(&(resources->p_mem_head), (ulong)base);
2748 else {
2749 if (prefetchable)
2750 dbg("using MEM for PMEM\n");
2751 mem_node = get_resource(&(resources->mem_head), (ulong)base);
2752 }
2753
2754 /* allocate the resource to the board */
2755 if (mem_node) {
2756 base64 = mem_node->base;
2757 mem_node->next = *res_node;
2758 *res_node = mem_node;
2759 dbg("Got 64 %s base=0x%x:%x(length=%x)\n", res_type_str, (u32)(base64 >> 32),
2760 (u32)base64, mem_node->length);
2761 } else {
2762 err("Got NO 64 %s resource(length=0x%x)\n", res_type_str, base);
2763 return -ENOMEM;
2764 }
2765 break;
2766 default:
2767 dbg("reserved BAR type=0x%x\n", temp_register);
2768 break;
2769 }
2770
2771 }
2772
2773 if (base64) {
2774 rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, (u32)base64);
2775 cloop += 4;
2776 base64 >>= 32;
2777
2778 if (base64) {
2779 dbg("%s: high dword of base64(0x%x) set to 0\n", __FUNCTION__, (u32)base64);
2780 base64 = 0x0L;
2781 }
2782
2783 rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, (u32)base64);
2784 } else {
2785 rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, base);
2786 }
2787 } /* End of base register loop */
2788
2789#if defined(CONFIG_X86_64)
2790 /* Figure out which interrupt pin this function uses */
2791 rc = pci_bus_read_config_byte (pci_bus, devfn, PCI_INTERRUPT_PIN, &temp_byte);
2792
2793 /* If this function needs an interrupt and we are behind a bridge
2794 and the pin is tied to something that's alread mapped,
2795 set this one the same
2796 */
2797 if (temp_byte && resources->irqs &&
2798 (resources->irqs->valid_INT &
2799 (0x01 << ((temp_byte + resources->irqs->barber_pole - 1) & 0x03)))) {
2800 /* We have to share with something already set up */
2801 IRQ = resources->irqs->interrupt[(temp_byte + resources->irqs->barber_pole - 1) & 0x03];
2802 } else {
2803 /* Program IRQ based on card type */
2804 rc = pci_bus_read_config_byte (pci_bus, devfn, 0x0B, &class_code);
2805
2806 if (class_code == PCI_BASE_CLASS_STORAGE) {
2807 IRQ = shpchp_disk_irq;
2808 } else {
2809 IRQ = shpchp_nic_irq;
2810 }
2811 }
2812
2813 /* IRQ Line */
2814 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_INTERRUPT_LINE, IRQ);
2815
2816 if (!behind_bridge) {
2817 rc = shpchp_set_irq(func->bus, func->device, temp_byte + 0x09, IRQ);
2818 if (rc)
2819 return(1);
2820 } else {
2821 /* TBD - this code may also belong in the other clause of this If statement */
2822 resources->irqs->interrupt[(temp_byte + resources->irqs->barber_pole - 1) & 0x03] = IRQ;
2823 resources->irqs->valid_INT |= 0x01 << (temp_byte + resources->irqs->barber_pole - 1) & 0x03;
2824 }
2825#endif
2826 /* Disable ROM base Address */
2827 rc = pci_bus_write_config_dword (pci_bus, devfn, PCI_ROM_ADDRESS, 0x00);
2828
2829 /* Set HP parameters (Cache Line Size, Latency Timer) */
2830 rc = shpchprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_NORMAL);
2831 if (rc)
2832 return rc;
2833
2834 shpchprm_enable_card(ctrl, func, PCI_HEADER_TYPE_NORMAL);
2835
2836 dbg("PCI function Hot-Added s:b:d:f(%02x:%02x:%02x:%02x)\n", ctrl->seg, func->bus, func->device, func->function);
2837 } /* End of Not-A-Bridge else */
2838 else {
2839 /* It's some strange type of PCI adapter (Cardbus?) */
2840 return(DEVICE_TYPE_NOT_SUPPORTED);
2841 }
2842
2843 func->configured = 1;
2844
2845 return 0;
2846} 980}
2847 981
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index 8d98410bf1c0..40905a6c8094 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -27,17 +27,10 @@
27 * 27 *
28 */ 28 */
29 29
30#include <linux/config.h>
31#include <linux/kernel.h> 30#include <linux/kernel.h>
32#include <linux/module.h> 31#include <linux/module.h>
33#include <linux/types.h> 32#include <linux/types.h>
34#include <linux/slab.h>
35#include <linux/vmalloc.h>
36#include <linux/interrupt.h>
37#include <linux/spinlock.h>
38#include <linux/delay.h>
39#include <linux/pci.h> 33#include <linux/pci.h>
40#include <asm/system.h>
41#include "shpchp.h" 34#include "shpchp.h"
42 35
43#ifdef DEBUG 36#ifdef DEBUG
@@ -282,7 +275,7 @@ static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
282 275
283static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 276static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
284{ 277{
285 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 278 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
286 u16 cmd_status; 279 u16 cmd_status;
287 int retval = 0; 280 int retval = 0;
288 u16 temp_word; 281 u16 temp_word;
@@ -320,7 +313,6 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
320 * command. 313 * command.
321 */ 314 */
322 writew(temp_word, php_ctlr->creg + CMD); 315 writew(temp_word, php_ctlr->creg + CMD);
323 dbg("%s: temp_word written %x\n", __FUNCTION__, temp_word);
324 316
325 DBG_LEAVE_ROUTINE 317 DBG_LEAVE_ROUTINE
326 return retval; 318 return retval;
@@ -328,7 +320,7 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
328 320
329static int hpc_check_cmd_status(struct controller *ctrl) 321static int hpc_check_cmd_status(struct controller *ctrl)
330{ 322{
331 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle; 323 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
332 u16 cmd_status; 324 u16 cmd_status;
333 int retval = 0; 325 int retval = 0;
334 326
@@ -368,7 +360,7 @@ static int hpc_check_cmd_status(struct controller *ctrl)
368 360
369static int hpc_get_attention_status(struct slot *slot, u8 *status) 361static int hpc_get_attention_status(struct slot *slot, u8 *status)
370{ 362{
371 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 363 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
372 u32 slot_reg; 364 u32 slot_reg;
373 u16 slot_status; 365 u16 slot_status;
374 u8 atten_led_state; 366 u8 atten_led_state;
@@ -408,7 +400,7 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status)
408 400
409static int hpc_get_power_status(struct slot * slot, u8 *status) 401static int hpc_get_power_status(struct slot * slot, u8 *status)
410{ 402{
411 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 403 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
412 u32 slot_reg; 404 u32 slot_reg;
413 u16 slot_status; 405 u16 slot_status;
414 u8 slot_state; 406 u8 slot_state;
@@ -450,7 +442,7 @@ static int hpc_get_power_status(struct slot * slot, u8 *status)
450 442
451static int hpc_get_latch_status(struct slot *slot, u8 *status) 443static int hpc_get_latch_status(struct slot *slot, u8 *status)
452{ 444{
453 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 445 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
454 u32 slot_reg; 446 u32 slot_reg;
455 u16 slot_status; 447 u16 slot_status;
456 448
@@ -473,7 +465,7 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status)
473 465
474static int hpc_get_adapter_status(struct slot *slot, u8 *status) 466static int hpc_get_adapter_status(struct slot *slot, u8 *status)
475{ 467{
476 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 468 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
477 u32 slot_reg; 469 u32 slot_reg;
478 u16 slot_status; 470 u16 slot_status;
479 u8 card_state; 471 u8 card_state;
@@ -496,7 +488,7 @@ static int hpc_get_adapter_status(struct slot *slot, u8 *status)
496 488
497static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 489static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
498{ 490{
499 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 491 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
500 492
501 DBG_ENTER_ROUTINE 493 DBG_ENTER_ROUTINE
502 494
@@ -513,7 +505,7 @@ static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
513 505
514static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 506static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
515{ 507{
516 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 508 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
517 u32 slot_reg; 509 u32 slot_reg;
518 u16 slot_status, sec_bus_status; 510 u16 slot_status, sec_bus_status;
519 u8 m66_cap, pcix_cap, pi; 511 u8 m66_cap, pcix_cap, pi;
@@ -594,7 +586,7 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
594 586
595static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) 587static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
596{ 588{
597 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 589 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
598 u16 sec_bus_status; 590 u16 sec_bus_status;
599 u8 pi; 591 u8 pi;
600 int retval = 0; 592 int retval = 0;
@@ -623,7 +615,7 @@ static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
623 615
624static int hpc_query_power_fault(struct slot * slot) 616static int hpc_query_power_fault(struct slot * slot)
625{ 617{
626 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 618 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
627 u32 slot_reg; 619 u32 slot_reg;
628 u16 slot_status; 620 u16 slot_status;
629 u8 pwr_fault_state, status; 621 u8 pwr_fault_state, status;
@@ -647,7 +639,7 @@ static int hpc_query_power_fault(struct slot * slot)
647 639
648static int hpc_set_attention_status(struct slot *slot, u8 value) 640static int hpc_set_attention_status(struct slot *slot, u8 value)
649{ 641{
650 struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 642 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
651 u8 slot_cmd = 0; 643 u8 slot_cmd = 0;
652 int rc = 0; 644 int rc = 0;
653 645
@@ -683,7 +675,7 @@ static int hpc_set_attention_status(struct slot *slot, u8 value)
683 675
684static void hpc_set_green_led_on(struct slot *slot) 676static void hpc_set_green_led_on(struct slot *slot)
685{ 677{
686 struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 678 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
687 u8 slot_cmd; 679 u8 slot_cmd;
688 680
689 if (!slot->ctrl->hpc_ctlr_handle) { 681 if (!slot->ctrl->hpc_ctlr_handle) {
@@ -705,7 +697,7 @@ static void hpc_set_green_led_on(struct slot *slot)
705 697
706static void hpc_set_green_led_off(struct slot *slot) 698static void hpc_set_green_led_off(struct slot *slot)
707{ 699{
708 struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 700 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
709 u8 slot_cmd; 701 u8 slot_cmd;
710 702
711 if (!slot->ctrl->hpc_ctlr_handle) { 703 if (!slot->ctrl->hpc_ctlr_handle) {
@@ -727,7 +719,7 @@ static void hpc_set_green_led_off(struct slot *slot)
727 719
728static void hpc_set_green_led_blink(struct slot *slot) 720static void hpc_set_green_led_blink(struct slot *slot)
729{ 721{
730 struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 722 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
731 u8 slot_cmd; 723 u8 slot_cmd;
732 724
733 if (!slot->ctrl->hpc_ctlr_handle) { 725 if (!slot->ctrl->hpc_ctlr_handle) {
@@ -754,7 +746,7 @@ int shpc_get_ctlr_slot_config(struct controller *ctrl,
754 int *updown, /* physical_slot_num increament: 1 or -1 */ 746 int *updown, /* physical_slot_num increament: 1 or -1 */
755 int *flags) 747 int *flags)
756{ 748{
757 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle; 749 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
758 750
759 DBG_ENTER_ROUTINE 751 DBG_ENTER_ROUTINE
760 752
@@ -776,7 +768,7 @@ int shpc_get_ctlr_slot_config(struct controller *ctrl,
776 768
777static void hpc_release_ctlr(struct controller *ctrl) 769static void hpc_release_ctlr(struct controller *ctrl)
778{ 770{
779 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle; 771 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
780 struct php_ctlr_state_s *p, *p_prev; 772 struct php_ctlr_state_s *p, *p_prev;
781 773
782 DBG_ENTER_ROUTINE 774 DBG_ENTER_ROUTINE
@@ -796,10 +788,8 @@ static void hpc_release_ctlr(struct controller *ctrl)
796 } 788 }
797 } 789 }
798 if (php_ctlr->pci_dev) { 790 if (php_ctlr->pci_dev) {
799 dbg("%s: before calling iounmap & release_mem_region\n", __FUNCTION__);
800 iounmap(php_ctlr->creg); 791 iounmap(php_ctlr->creg);
801 release_mem_region(pci_resource_start(php_ctlr->pci_dev, 0), pci_resource_len(php_ctlr->pci_dev, 0)); 792 release_mem_region(pci_resource_start(php_ctlr->pci_dev, 0), pci_resource_len(php_ctlr->pci_dev, 0));
802 dbg("%s: before calling iounmap & release_mem_region\n", __FUNCTION__);
803 php_ctlr->pci_dev = NULL; 793 php_ctlr->pci_dev = NULL;
804 } 794 }
805 795
@@ -828,7 +818,7 @@ DBG_LEAVE_ROUTINE
828 818
829static int hpc_power_on_slot(struct slot * slot) 819static int hpc_power_on_slot(struct slot * slot)
830{ 820{
831 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 821 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
832 u8 slot_cmd; 822 u8 slot_cmd;
833 int retval = 0; 823 int retval = 0;
834 824
@@ -859,7 +849,7 @@ static int hpc_power_on_slot(struct slot * slot)
859 849
860static int hpc_slot_enable(struct slot * slot) 850static int hpc_slot_enable(struct slot * slot)
861{ 851{
862 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 852 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
863 u8 slot_cmd; 853 u8 slot_cmd;
864 int retval = 0; 854 int retval = 0;
865 855
@@ -890,7 +880,7 @@ static int hpc_slot_enable(struct slot * slot)
890 880
891static int hpc_slot_disable(struct slot * slot) 881static int hpc_slot_disable(struct slot * slot)
892{ 882{
893 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 883 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
894 u8 slot_cmd; 884 u8 slot_cmd;
895 int retval = 0; 885 int retval = 0;
896 886
@@ -920,51 +910,12 @@ static int hpc_slot_disable(struct slot * slot)
920 return retval; 910 return retval;
921} 911}
922 912
923static int hpc_enable_all_slots( struct slot *slot )
924{
925 int retval = 0;
926
927 DBG_ENTER_ROUTINE
928
929 if (!slot->ctrl->hpc_ctlr_handle) {
930 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
931 return -1;
932 }
933
934 retval = shpc_write_cmd(slot, 0, SET_ENABLE_ALL);
935 if (retval) {
936 err("%s: Write command failed!\n", __FUNCTION__);
937 return -1;
938 }
939
940 DBG_LEAVE_ROUTINE
941
942 return retval;
943}
944
945static int hpc_pwr_on_all_slots(struct slot *slot)
946{
947 int retval = 0;
948
949 DBG_ENTER_ROUTINE
950
951 retval = shpc_write_cmd(slot, 0, SET_PWR_ON_ALL);
952
953 if (retval) {
954 err("%s: Write command failed!\n", __FUNCTION__);
955 return -1;
956 }
957
958 DBG_LEAVE_ROUTINE
959 return retval;
960}
961
962static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) 913static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
963{ 914{
964 u8 slot_cmd; 915 u8 slot_cmd;
965 u8 pi; 916 u8 pi;
966 int retval = 0; 917 int retval = 0;
967 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 918 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
968 919
969 DBG_ENTER_ROUTINE 920 DBG_ENTER_ROUTINE
970 921
@@ -1089,18 +1040,13 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1089 1040
1090 if (!intr_loc) 1041 if (!intr_loc)
1091 return IRQ_NONE; 1042 return IRQ_NONE;
1092 dbg("%s: shpc_isr proceeds\n", __FUNCTION__);
1093 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); 1043 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
1094 1044
1095 if(!shpchp_poll_mode) { 1045 if(!shpchp_poll_mode) {
1096 /* Mask Global Interrupt Mask - see implementation note on p. 139 */ 1046 /* Mask Global Interrupt Mask - see implementation note on p. 139 */
1097 /* of SHPC spec rev 1.0*/ 1047 /* of SHPC spec rev 1.0*/
1098 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1048 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1099 dbg("%s: Before masking global interrupt, temp_dword = %x\n",
1100 __FUNCTION__, temp_dword);
1101 temp_dword |= 0x00000001; 1049 temp_dword |= 0x00000001;
1102 dbg("%s: After masking global interrupt, temp_dword = %x\n",
1103 __FUNCTION__, temp_dword);
1104 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); 1050 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1105 1051
1106 intr_loc2 = readl(php_ctlr->creg + INTR_LOC); 1052 intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
@@ -1114,11 +1060,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1114 * Detect bit in Controller SERR-INT register 1060 * Detect bit in Controller SERR-INT register
1115 */ 1061 */
1116 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1062 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1117 dbg("%s: Before clearing CCIP, temp_dword = %x\n",
1118 __FUNCTION__, temp_dword);
1119 temp_dword &= 0xfffeffff; 1063 temp_dword &= 0xfffeffff;
1120 dbg("%s: After clearing CCIP, temp_dword = %x\n",
1121 __FUNCTION__, temp_dword);
1122 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); 1064 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1123 wake_up_interruptible(&ctrl->queue); 1065 wake_up_interruptible(&ctrl->queue);
1124 } 1066 }
@@ -1126,11 +1068,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1126 if ((intr_loc = (intr_loc >> 1)) == 0) { 1068 if ((intr_loc = (intr_loc >> 1)) == 0) {
1127 /* Unmask Global Interrupt Mask */ 1069 /* Unmask Global Interrupt Mask */
1128 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1070 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1129 dbg("%s: 1-Before unmasking global interrupt, temp_dword = %x\n",
1130 __FUNCTION__, temp_dword);
1131 temp_dword &= 0xfffffffe; 1071 temp_dword &= 0xfffffffe;
1132 dbg("%s: 1-After unmasking global interrupt, temp_dword = %x\n",
1133 __FUNCTION__, temp_dword);
1134 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); 1072 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1135 1073
1136 return IRQ_NONE; 1074 return IRQ_NONE;
@@ -1140,11 +1078,9 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1140 /* To find out which slot has interrupt pending */ 1078 /* To find out which slot has interrupt pending */
1141 if ((intr_loc >> hp_slot) & 0x01) { 1079 if ((intr_loc >> hp_slot) & 0x01) {
1142 temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot)); 1080 temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot));
1143 dbg("%s: Slot %x with intr, temp_dword = %x\n", 1081 dbg("%s: Slot %x with intr, slot register = %x\n",
1144 __FUNCTION__, hp_slot, temp_dword); 1082 __FUNCTION__, hp_slot, temp_dword);
1145 temp_byte = (temp_dword >> 16) & 0xFF; 1083 temp_byte = (temp_dword >> 16) & 0xFF;
1146 dbg("%s: Slot with intr, temp_byte = %x\n",
1147 __FUNCTION__, temp_byte);
1148 if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08)) 1084 if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08))
1149 schedule_flag += php_ctlr->switch_change_callback( 1085 schedule_flag += php_ctlr->switch_change_callback(
1150 hp_slot, php_ctlr->callback_instance_id); 1086 hp_slot, php_ctlr->callback_instance_id);
@@ -1160,8 +1096,6 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1160 1096
1161 /* Clear all slot events */ 1097 /* Clear all slot events */
1162 temp_dword = 0xe01f3fff; 1098 temp_dword = 0xe01f3fff;
1163 dbg("%s: Clearing slot events, temp_dword = %x\n",
1164 __FUNCTION__, temp_dword);
1165 writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot)); 1099 writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1166 1100
1167 intr_loc2 = readl(php_ctlr->creg + INTR_LOC); 1101 intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
@@ -1171,11 +1105,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1171 if (!shpchp_poll_mode) { 1105 if (!shpchp_poll_mode) {
1172 /* Unmask Global Interrupt Mask */ 1106 /* Unmask Global Interrupt Mask */
1173 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1107 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1174 dbg("%s: 2-Before unmasking global interrupt, temp_dword = %x\n",
1175 __FUNCTION__, temp_dword);
1176 temp_dword &= 0xfffffffe; 1108 temp_dword &= 0xfffffffe;
1177 dbg("%s: 2-After unmasking global interrupt, temp_dword = %x\n",
1178 __FUNCTION__, temp_dword);
1179 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); 1109 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1180 } 1110 }
1181 1111
@@ -1184,7 +1114,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1184 1114
1185static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) 1115static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1186{ 1116{
1187 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 1117 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1188 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 1118 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1189 int retval = 0; 1119 int retval = 0;
1190 u8 pi; 1120 u8 pi;
@@ -1253,7 +1183,7 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1253 1183
1254static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) 1184static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1255{ 1185{
1256 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; 1186 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1257 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 1187 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1258 u16 sec_bus_status; 1188 u16 sec_bus_status;
1259 int retval = 0; 1189 int retval = 0;
@@ -1367,8 +1297,6 @@ static struct hpc_ops shpchp_hpc_ops = {
1367 .power_on_slot = hpc_power_on_slot, 1297 .power_on_slot = hpc_power_on_slot,
1368 .slot_enable = hpc_slot_enable, 1298 .slot_enable = hpc_slot_enable,
1369 .slot_disable = hpc_slot_disable, 1299 .slot_disable = hpc_slot_disable,
1370 .enable_all_slots = hpc_enable_all_slots,
1371 .pwr_on_all_slots = hpc_pwr_on_all_slots,
1372 .set_bus_speed_mode = hpc_set_bus_speed_mode, 1300 .set_bus_speed_mode = hpc_set_bus_speed_mode,
1373 .set_attention_status = hpc_set_attention_status, 1301 .set_attention_status = hpc_set_attention_status,
1374 .get_power_status = hpc_get_power_status, 1302 .get_power_status = hpc_get_power_status,
@@ -1391,12 +1319,7 @@ static struct hpc_ops shpchp_hpc_ops = {
1391 .check_cmd_status = hpc_check_cmd_status, 1319 .check_cmd_status = hpc_check_cmd_status,
1392}; 1320};
1393 1321
1394int shpc_init(struct controller * ctrl, 1322int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
1395 struct pci_dev * pdev,
1396 php_intr_callback_t attention_button_callback,
1397 php_intr_callback_t switch_change_callback,
1398 php_intr_callback_t presence_change_callback,
1399 php_intr_callback_t power_fault_callback)
1400{ 1323{
1401 struct php_ctlr_state_s *php_ctlr, *p; 1324 struct php_ctlr_state_s *php_ctlr, *p;
1402 void *instance_id = ctrl; 1325 void *instance_id = ctrl;
@@ -1405,7 +1328,6 @@ int shpc_init(struct controller * ctrl,
1405 static int first = 1; 1328 static int first = 1;
1406 u32 shpc_cap_offset, shpc_base_offset; 1329 u32 shpc_cap_offset, shpc_base_offset;
1407 u32 tempdword, slot_reg; 1330 u32 tempdword, slot_reg;
1408 u16 vendor_id, device_id;
1409 u8 i; 1331 u8 i;
1410 1332
1411 DBG_ENTER_ROUTINE 1333 DBG_ENTER_ROUTINE
@@ -1422,21 +1344,8 @@ int shpc_init(struct controller * ctrl,
1422 1344
1423 php_ctlr->pci_dev = pdev; /* save pci_dev in context */ 1345 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1424 1346
1425 rc = pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor_id); 1347 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
1426 dbg("%s: Vendor ID: %x\n",__FUNCTION__, vendor_id); 1348 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1427 if (rc) {
1428 err("%s: unable to read PCI configuration data\n", __FUNCTION__);
1429 goto abort_free_ctlr;
1430 }
1431
1432 rc = pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
1433 dbg("%s: Device ID: %x\n",__FUNCTION__, device_id);
1434 if (rc) {
1435 err("%s: unable to read PCI configuration data\n", __FUNCTION__);
1436 goto abort_free_ctlr;
1437 }
1438
1439 if ((vendor_id == PCI_VENDOR_ID_AMD) || (device_id == PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1440 shpc_base_offset = 0; /* amd shpc driver doesn't use this; assume 0 */ 1349 shpc_base_offset = 0; /* amd shpc driver doesn't use this; assume 0 */
1441 } else { 1350 } else {
1442 if ((shpc_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC)) == 0) { 1351 if ((shpc_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC)) == 0) {
@@ -1469,7 +1378,8 @@ int shpc_init(struct controller * ctrl,
1469 err("%s : pci_read_config_dword failed\n", __FUNCTION__); 1378 err("%s : pci_read_config_dword failed\n", __FUNCTION__);
1470 goto abort_free_ctlr; 1379 goto abort_free_ctlr;
1471 } 1380 }
1472 dbg("%s: offset %d: tempdword %x\n", __FUNCTION__,i, tempdword); 1381 dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
1382 tempdword);
1473 } 1383 }
1474 } 1384 }
1475 1385
@@ -1478,13 +1388,6 @@ int shpc_init(struct controller * ctrl,
1478 first = 0; 1388 first = 0;
1479 } 1389 }
1480 1390
1481 dbg("pdev = %p: b:d:f:irq=0x%x:%x:%x:%x\n", pdev, pdev->bus->number, PCI_SLOT(pdev->devfn),
1482 PCI_FUNC(pdev->devfn), pdev->irq);
1483 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1484 if (pci_resource_len(pdev, rc) > 0)
1485 dbg("pci resource[%d] start=0x%lx(len=0x%lx), shpc_base_offset %x\n", rc,
1486 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc), shpc_base_offset);
1487
1488 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, 1391 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1489 pdev->subsystem_device); 1392 pdev->subsystem_device);
1490 1393
@@ -1504,7 +1407,6 @@ int shpc_init(struct controller * ctrl,
1504 goto abort_free_ctlr; 1407 goto abort_free_ctlr;
1505 } 1408 }
1506 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg); 1409 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
1507 dbg("%s: physical addr %p\n", __FUNCTION__, (void*)pci_resource_start(pdev, 0));
1508 1410
1509 init_MUTEX(&ctrl->crit_sect); 1411 init_MUTEX(&ctrl->crit_sect);
1510 /* Setup wait queue */ 1412 /* Setup wait queue */
@@ -1512,13 +1414,10 @@ int shpc_init(struct controller * ctrl,
1512 1414
1513 /* Find the IRQ */ 1415 /* Find the IRQ */
1514 php_ctlr->irq = pdev->irq; 1416 php_ctlr->irq = pdev->irq;
1515 dbg("HPC interrupt = %d\n", php_ctlr->irq); 1417 php_ctlr->attention_button_callback = shpchp_handle_attention_button,
1516 1418 php_ctlr->switch_change_callback = shpchp_handle_switch_change;
1517 /* Save interrupt callback info */ 1419 php_ctlr->presence_change_callback = shpchp_handle_presence_change;
1518 php_ctlr->attention_button_callback = attention_button_callback; 1420 php_ctlr->power_fault_callback = shpchp_handle_power_fault;
1519 php_ctlr->switch_change_callback = switch_change_callback;
1520 php_ctlr->presence_change_callback = presence_change_callback;
1521 php_ctlr->power_fault_callback = power_fault_callback;
1522 php_ctlr->callback_instance_id = instance_id; 1421 php_ctlr->callback_instance_id = instance_id;
1523 1422
1524 /* Return PCI Controller Info */ 1423 /* Return PCI Controller Info */
@@ -1556,7 +1455,6 @@ int shpc_init(struct controller * ctrl,
1556 if (rc) { 1455 if (rc) {
1557 info("Can't get msi for the hotplug controller\n"); 1456 info("Can't get msi for the hotplug controller\n");
1558 info("Use INTx for the hotplug controller\n"); 1457 info("Use INTx for the hotplug controller\n");
1559 dbg("%s: rc = %x\n", __FUNCTION__, rc);
1560 } else 1458 } else
1561 php_ctlr->irq = pdev->irq; 1459 php_ctlr->irq = pdev->irq;
1562 1460
@@ -1566,9 +1464,11 @@ int shpc_init(struct controller * ctrl,
1566 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); 1464 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1567 goto abort_free_ctlr; 1465 goto abort_free_ctlr;
1568 } 1466 }
1569 /* Execute OSHP method here */
1570 } 1467 }
1571 dbg("%s: Before adding HPC to HPC list\n", __FUNCTION__); 1468 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
1469 pdev->bus->number, PCI_SLOT(pdev->devfn),
1470 PCI_FUNC(pdev->devfn), pdev->irq);
1471 get_hp_hw_control_from_firmware(pdev);
1572 1472
1573 /* Add this HPC instance into the HPC list */ 1473 /* Add this HPC instance into the HPC list */
1574 spin_lock(&list_lock); 1474 spin_lock(&list_lock);
@@ -1607,7 +1507,6 @@ int shpc_init(struct controller * ctrl,
1607 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1507 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1608 } 1508 }
1609 1509
1610 dbg("%s: Leaving shpc_init\n", __FUNCTION__);
1611 DBG_LEAVE_ROUTINE 1510 DBG_LEAVE_ROUTINE
1612 return 0; 1511 return 0;
1613 1512
diff --git a/drivers/pci/hotplug/shpchp_pci.c b/drivers/pci/hotplug/shpchp_pci.c
index d867099114ec..b8e95acea3b6 100644
--- a/drivers/pci/hotplug/shpchp_pci.c
+++ b/drivers/pci/hotplug/shpchp_pci.c
@@ -27,784 +27,151 @@
27 * 27 *
28 */ 28 */
29 29
30#include <linux/config.h>
31#include <linux/module.h> 30#include <linux/module.h>
32#include <linux/kernel.h> 31#include <linux/kernel.h>
33#include <linux/types.h> 32#include <linux/types.h>
34#include <linux/slab.h>
35#include <linux/workqueue.h>
36#include <linux/proc_fs.h>
37#include <linux/pci.h> 33#include <linux/pci.h>
38#include "../pci.h" 34#include "../pci.h"
39#include "shpchp.h" 35#include "shpchp.h"
40#ifndef CONFIG_IA64
41#include "../../../arch/i386/pci/pci.h" /* horrible hack showing how processor dependant we are... */
42#endif
43 36
44int shpchp_configure_device (struct controller* ctrl, struct pci_func* func) 37void program_fw_provided_values(struct pci_dev *dev)
45{ 38{
46 unsigned char bus; 39 u16 pci_cmd, pci_bctl;
47 struct pci_bus *child; 40 struct pci_dev *cdev;
48 int num; 41 struct hotplug_params hpp = {0x8, 0x40, 0, 0}; /* defaults */
49 42
50 if (func->pci_dev == NULL) 43 /* Program hpp values for this device */
51 func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function)); 44 if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL ||
52 45 (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
53 /* Still NULL ? Well then scan for it ! */ 46 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
54 if (func->pci_dev == NULL) { 47 return;
55 num = pci_scan_slot(ctrl->pci_dev->subordinate, PCI_DEVFN(func->device, func->function)); 48
56 if (num) { 49 get_hp_params_from_firmware(dev, &hpp);
57 dbg("%s: subordiante %p number %x\n", __FUNCTION__, ctrl->pci_dev->subordinate, 50
58 ctrl->pci_dev->subordinate->number); 51 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp.cache_line_size);
59 pci_bus_add_devices(ctrl->pci_dev->subordinate); 52 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp.latency_timer);
60 } 53 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
61 54 if (hpp.enable_serr)
62 func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function)); 55 pci_cmd |= PCI_COMMAND_SERR;
63 if (func->pci_dev == NULL) { 56 else
64 dbg("ERROR: pci_dev still null\n"); 57 pci_cmd &= ~PCI_COMMAND_SERR;
65 return 0; 58 if (hpp.enable_perr)
59 pci_cmd |= PCI_COMMAND_PARITY;
60 else
61 pci_cmd &= ~PCI_COMMAND_PARITY;
62 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
63
64 /* Program bridge control value and child devices */
65 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
66 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
67 hpp.latency_timer);
68 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
69 if (hpp.enable_serr)
70 pci_bctl |= PCI_BRIDGE_CTL_SERR;
71 else
72 pci_bctl &= ~PCI_BRIDGE_CTL_SERR;
73 if (hpp.enable_perr)
74 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
75 else
76 pci_bctl &= ~PCI_BRIDGE_CTL_PARITY;
77 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
78 if (dev->subordinate) {
79 list_for_each_entry(cdev, &dev->subordinate->devices,
80 bus_list)
81 program_fw_provided_values(cdev);
66 } 82 }
67 } 83 }
68
69 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
70 pci_read_config_byte(func->pci_dev, PCI_SECONDARY_BUS, &bus);
71 child = pci_add_new_bus(func->pci_dev->bus, (func->pci_dev), bus);
72 pci_do_scan_bus(child);
73
74 }
75
76 return 0;
77} 84}
78 85
79 86int shpchp_configure_device(struct slot *p_slot)
80int shpchp_unconfigure_device(struct pci_func* func)
81{ 87{
82 int rc = 0; 88 struct pci_dev *dev;
83 int j; 89 struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
84 90 int num, fn;
85 dbg("%s: bus/dev/func = %x/%x/%x\n", __FUNCTION__, func->bus, 91
86 func->device, func->function); 92 dev = pci_find_slot(p_slot->bus, PCI_DEVFN(p_slot->device, 0));
87 93 if (dev) {
88 for (j=0; j<8 ; j++) { 94 err("Device %s already exists at %x:%x, cannot hot-add\n",
89 struct pci_dev* temp = pci_find_slot(func->bus, 95 pci_name(dev), p_slot->bus, p_slot->device);
90 (func->device << 3) | j); 96 return -EINVAL;
91 if (temp) {
92 pci_remove_bus_device(temp);
93 }
94 } 97 }
95 return rc;
96}
97
98/*
99 * shpchp_set_irq
100 *
101 * @bus_num: bus number of PCI device
102 * @dev_num: device number of PCI device
103 * @slot: pointer to u8 where slot number will be returned
104 */
105int shpchp_set_irq (u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
106{
107#if defined(CONFIG_X86) && !defined(CONFIG_X86_IO_APIC) && !defined(CONFIG_X86_64)
108 int rc;
109 u16 temp_word;
110 struct pci_dev fakedev;
111 struct pci_bus fakebus;
112 98
113 fakedev.devfn = dev_num << 3; 99 num = pci_scan_slot(parent, PCI_DEVFN(p_slot->device, 0));
114 fakedev.bus = &fakebus; 100 if (num == 0) {
115 fakebus.number = bus_num; 101 err("No new device found\n");
116 dbg("%s: dev %d, bus %d, pin %d, num %d\n", 102 return -ENODEV;
117 __FUNCTION__, dev_num, bus_num, int_pin, irq_num);
118 rc = pcibios_set_irq_routing(&fakedev, int_pin - 0x0a, irq_num);
119 dbg("%s: rc %d\n", __FUNCTION__, rc);
120 if (!rc)
121 return !rc;
122
123 /* set the Edge Level Control Register (ELCR) */
124 temp_word = inb(0x4d0);
125 temp_word |= inb(0x4d1) << 8;
126
127 temp_word |= 0x01 << irq_num;
128
129 /* This should only be for x86 as it sets the Edge Level Control Register */
130 outb((u8) (temp_word & 0xFF), 0x4d0);
131 outb((u8) ((temp_word & 0xFF00) >> 8), 0x4d1);
132#endif
133 return 0;
134}
135
136/* More PCI configuration routines; this time centered around hotplug controller */
137
138
139/*
140 * shpchp_save_config
141 *
142 * Reads configuration for all slots in a PCI bus and saves info.
143 *
144 * Note: For non-hot plug busses, the slot # saved is the device #
145 *
146 * returns 0 if success
147 */
148int shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num)
149{
150 int rc;
151 u8 class_code;
152 u8 header_type;
153 u32 ID;
154 u8 secondary_bus;
155 struct pci_func *new_slot;
156 int sub_bus;
157 int FirstSupported;
158 int LastSupported;
159 int max_functions;
160 int function;
161 u8 DevError;
162 int device = 0;
163 int cloop = 0;
164 int stop_it;
165 int index;
166 int is_hot_plug = num_ctlr_slots || first_device_num;
167 struct pci_bus lpci_bus, *pci_bus;
168
169 dbg("%s: num_ctlr_slots = %d, first_device_num = %d\n", __FUNCTION__,
170 num_ctlr_slots, first_device_num);
171
172 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
173 pci_bus = &lpci_bus;
174
175 dbg("%s: num_ctlr_slots = %d, first_device_num = %d\n", __FUNCTION__,
176 num_ctlr_slots, first_device_num);
177
178 /* Decide which slots are supported */
179 if (is_hot_plug) {
180 /*********************************
181 * is_hot_plug is the slot mask
182 *********************************/
183 FirstSupported = first_device_num;
184 LastSupported = FirstSupported + num_ctlr_slots - 1;
185 } else {
186 FirstSupported = 0;
187 LastSupported = 0x1F;
188 } 103 }
189 104
190 dbg("FirstSupported = %d, LastSupported = %d\n", FirstSupported, 105 for (fn = 0; fn < 8; fn++) {
191 LastSupported); 106 if (!(dev = pci_find_slot(p_slot->bus,
192 107 PCI_DEVFN(p_slot->device, fn))))
193 /* Save PCI configuration space for all devices in supported slots */ 108 continue;
194 pci_bus->number = busnumber; 109 if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
195 for (device = FirstSupported; device <= LastSupported; device++) { 110 err("Cannot hot-add display device %s\n",
196 ID = 0xFFFFFFFF; 111 pci_name(dev));
197 rc = pci_bus_read_config_dword(pci_bus, PCI_DEVFN(device, 0), 112 continue;
198 PCI_VENDOR_ID, &ID);
199
200 if (ID != 0xFFFFFFFF) { /* device in slot */
201 rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, 0),
202 0x0B, &class_code);
203 if (rc)
204 return rc;
205
206 rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, 0),
207 PCI_HEADER_TYPE, &header_type);
208 if (rc)
209 return rc;
210
211 dbg("class_code = %x, header_type = %x\n", class_code, header_type);
212
213 /* If multi-function device, set max_functions to 8 */
214 if (header_type & 0x80)
215 max_functions = 8;
216 else
217 max_functions = 1;
218
219 function = 0;
220
221 do {
222 DevError = 0;
223
224 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* P-P Bridge */
225 /* Recurse the subordinate bus
226 * get the subordinate bus number
227 */
228 rc = pci_bus_read_config_byte(pci_bus,
229 PCI_DEVFN(device, function),
230 PCI_SECONDARY_BUS, &secondary_bus);
231 if (rc) {
232 return rc;
233 } else {
234 sub_bus = (int) secondary_bus;
235
236 /* Save secondary bus cfg spc with this recursive call. */
237 rc = shpchp_save_config(ctrl, sub_bus, 0, 0);
238 if (rc)
239 return rc;
240 }
241 }
242
243 index = 0;
244 new_slot = shpchp_slot_find(busnumber, device, index++);
245
246 dbg("new_slot = %p\n", new_slot);
247
248 while (new_slot && (new_slot->function != (u8) function)) {
249 new_slot = shpchp_slot_find(busnumber, device, index++);
250 dbg("new_slot = %p\n", new_slot);
251 }
252 if (!new_slot) {
253 /* Setup slot structure. */
254 new_slot = shpchp_slot_create(busnumber);
255 dbg("new_slot = %p\n", new_slot);
256
257 if (new_slot == NULL)
258 return(1);
259 }
260
261 new_slot->bus = (u8) busnumber;
262 new_slot->device = (u8) device;
263 new_slot->function = (u8) function;
264 new_slot->is_a_board = 1;
265 new_slot->switch_save = 0x10;
266 new_slot->pwr_save = 1;
267 /* In case of unsupported board */
268 new_slot->status = DevError;
269 new_slot->pci_dev = pci_find_slot(new_slot->bus,
270 (new_slot->device << 3) | new_slot->function);
271 dbg("new_slot->pci_dev = %p\n", new_slot->pci_dev);
272
273 for (cloop = 0; cloop < 0x20; cloop++) {
274 rc = pci_bus_read_config_dword(pci_bus,
275 PCI_DEVFN(device, function),
276 cloop << 2,
277 (u32 *) &(new_slot->config_space [cloop]));
278 /* dbg("new_slot->config_space[%x] = %x\n",
279 cloop, new_slot->config_space[cloop]); */
280 if (rc)
281 return rc;
282 }
283
284 function++;
285
286 stop_it = 0;
287
288 /* this loop skips to the next present function
289 * reading in Class Code and Header type.
290 */
291
292 while ((function < max_functions)&&(!stop_it)) {
293 rc = pci_bus_read_config_dword(pci_bus,
294 PCI_DEVFN(device, function),
295 PCI_VENDOR_ID, &ID);
296
297 if (ID == 0xFFFFFFFF) { /* nothing there. */
298 function++;
299 dbg("Nothing there\n");
300 } else { /* Something there */
301 rc = pci_bus_read_config_byte(pci_bus,
302 PCI_DEVFN(device, function),
303 0x0B, &class_code);
304 if (rc)
305 return rc;
306
307 rc = pci_bus_read_config_byte(pci_bus,
308 PCI_DEVFN(device, function),
309 PCI_HEADER_TYPE, &header_type);
310 if (rc)
311 return rc;
312
313 dbg("class_code = %x, header_type = %x\n",
314 class_code, header_type);
315 stop_it++;
316 }
317 }
318
319 } while (function < max_functions);
320 /* End of IF (device in slot?) */
321 } else if (is_hot_plug) {
322 /* Setup slot structure with entry for empty slot */
323 new_slot = shpchp_slot_create(busnumber);
324
325 if (new_slot == NULL) {
326 return(1);
327 }
328 dbg("new_slot = %p\n", new_slot);
329
330 new_slot->bus = (u8) busnumber;
331 new_slot->device = (u8) device;
332 new_slot->function = 0;
333 new_slot->is_a_board = 0;
334 new_slot->presence_save = 0;
335 new_slot->switch_save = 0;
336 } 113 }
337 } /* End of FOR loop */ 114 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) ||
338 115 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) {
339 return(0); 116 /* Find an unused bus number for the new bridge */
340} 117 struct pci_bus *child;
341 118 unsigned char busnr, start = parent->secondary;
342 119 unsigned char end = parent->subordinate;
343/* 120 for (busnr = start; busnr <= end; busnr++) {
344 * shpchp_save_slot_config 121 if (!pci_find_bus(pci_domain_nr(parent),
345 * 122 busnr))
346 * Saves configuration info for all PCI devices in a given slot 123 break;
347 * including subordinate busses.
348 *
349 * returns 0 if success
350 */
351int shpchp_save_slot_config(struct controller *ctrl, struct pci_func * new_slot)
352{
353 int rc;
354 u8 class_code;
355 u8 header_type;
356 u32 ID;
357 u8 secondary_bus;
358 int sub_bus;
359 int max_functions;
360 int function;
361 int cloop = 0;
362 int stop_it;
363 struct pci_bus lpci_bus, *pci_bus;
364 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
365 pci_bus = &lpci_bus;
366 pci_bus->number = new_slot->bus;
367
368 ID = 0xFFFFFFFF;
369
370 pci_bus_read_config_dword(pci_bus, PCI_DEVFN(new_slot->device, 0),
371 PCI_VENDOR_ID, &ID);
372
373 if (ID != 0xFFFFFFFF) { /* device in slot */
374 pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, 0),
375 0x0B, &class_code);
376
377 pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, 0),
378 PCI_HEADER_TYPE, &header_type);
379
380 if (header_type & 0x80) /* Multi-function device */
381 max_functions = 8;
382 else
383 max_functions = 1;
384
385 function = 0;
386
387 do {
388 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */
389 /* Recurse the subordinate bus */
390 pci_bus_read_config_byte(pci_bus,
391 PCI_DEVFN(new_slot->device, function),
392 PCI_SECONDARY_BUS, &secondary_bus);
393
394 sub_bus = (int) secondary_bus;
395
396 /* Save the config headers for the secondary bus. */
397 rc = shpchp_save_config(ctrl, sub_bus, 0, 0);
398
399 if (rc)
400 return rc;
401
402 } /* End of IF */
403
404 new_slot->status = 0;
405
406 for (cloop = 0; cloop < 0x20; cloop++) {
407 pci_bus_read_config_dword(pci_bus,
408 PCI_DEVFN(new_slot->device, function),
409 cloop << 2,
410 (u32 *) &(new_slot->config_space [cloop]));
411 } 124 }
412 125 if (busnr >= end) {
413 function++; 126 err("No free bus for hot-added bridge\n");
414 127 continue;
415 stop_it = 0;
416
417 /* this loop skips to the next present function
418 * reading in the Class Code and the Header type.
419 */
420
421 while ((function < max_functions) && (!stop_it)) {
422 pci_bus_read_config_dword(pci_bus,
423 PCI_DEVFN(new_slot->device, function),
424 PCI_VENDOR_ID, &ID);
425
426 if (ID == 0xFFFFFFFF) { /* nothing there. */
427 function++;
428 } else { /* Something there */
429 pci_bus_read_config_byte(pci_bus,
430 PCI_DEVFN(new_slot->device, function),
431 0x0B, &class_code);
432
433 pci_bus_read_config_byte(pci_bus,
434 PCI_DEVFN(new_slot->device, function),
435 PCI_HEADER_TYPE, &header_type);
436
437 stop_it++;
438 }
439 } 128 }
440 129 child = pci_add_new_bus(parent, dev, busnr);
441 } while (function < max_functions); 130 if (!child) {
442 } /* End of IF (device in slot?) */ 131 err("Cannot add new bus for %s\n",
443 else { 132 pci_name(dev));
444 return 2; 133 continue;
134 }
135 child->subordinate = pci_do_scan_bus(child);
136 pci_bus_size_bridges(child);
137 }
138 program_fw_provided_values(dev);
445 } 139 }
446 140
141 pci_bus_assign_resources(parent);
142 pci_bus_add_devices(parent);
143 pci_enable_bridges(parent);
447 return 0; 144 return 0;
448} 145}
449 146
450 147int shpchp_unconfigure_device(struct slot *p_slot)
451/*
452 * shpchp_save_used_resources
453 *
454 * Stores used resource information for existing boards. this is
455 * for boards that were in the system when this driver was loaded.
456 * this function is for hot plug ADD
457 *
458 * returns 0 if success
459 * if disable == 1(DISABLE_CARD),
460 * it loops for all functions of the slot and disables them.
461 * else, it just get resources of the function and return.
462 */
463int shpchp_save_used_resources(struct controller *ctrl, struct pci_func *func, int disable)
464{ 148{
465 u8 cloop; 149 int rc = 0;
466 u8 header_type; 150 int j;
467 u8 secondary_bus; 151 u8 bctl = 0;
468 u8 temp_byte; 152
469 u16 command; 153 dbg("%s: bus/dev = %x/%x\n", __FUNCTION__, p_slot->bus, p_slot->device);
470 u16 save_command;
471 u16 w_base, w_length;
472 u32 temp_register;
473 u32 save_base;
474 u32 base, length;
475 u64 base64 = 0;
476 int index = 0;
477 unsigned int devfn;
478 struct pci_resource *mem_node = NULL;
479 struct pci_resource *p_mem_node = NULL;
480 struct pci_resource *t_mem_node;
481 struct pci_resource *io_node;
482 struct pci_resource *bus_node;
483 struct pci_bus lpci_bus, *pci_bus;
484 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
485 pci_bus = &lpci_bus;
486
487 if (disable)
488 func = shpchp_slot_find(func->bus, func->device, index++);
489
490 while ((func != NULL) && func->is_a_board) {
491 pci_bus->number = func->bus;
492 devfn = PCI_DEVFN(func->device, func->function);
493
494 /* Save the command register */
495 pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command);
496 154
497 if (disable) { 155 for (j=0; j<8 ; j++) {
498 /* disable card */ 156 struct pci_dev* temp = pci_find_slot(p_slot->bus,
499 command = 0x00; 157 (p_slot->device << 3) | j);
500 pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command); 158 if (!temp)
159 continue;
160 if ((temp->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
161 err("Cannot remove display device %s\n",
162 pci_name(temp));
163 continue;
501 } 164 }
502 165 if (temp->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
503 /* Check for Bridge */ 166 pci_read_config_byte(temp, PCI_BRIDGE_CONTROL, &bctl);
504 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 167 if (bctl & PCI_BRIDGE_CTL_VGA) {
505 168 err("Cannot remove display device %s\n",
506 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */ 169 pci_name(temp));
507 dbg("Save_used_res of PCI bridge b:d=0x%x:%x, sc=0x%x\n", 170 continue;
508 func->bus, func->device, save_command);
509 if (disable) {
510 /* Clear Bridge Control Register */
511 command = 0x00;
512 pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
513 } 171 }
514
515 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
516 pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
517
518 bus_node = kmalloc(sizeof(struct pci_resource),
519 GFP_KERNEL);
520 if (!bus_node)
521 return -ENOMEM;
522
523 bus_node->base = (ulong)secondary_bus;
524 bus_node->length = (ulong)(temp_byte - secondary_bus + 1);
525
526 bus_node->next = func->bus_head;
527 func->bus_head = bus_node;
528
529 /* Save IO base and Limit registers */
530 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &temp_byte);
531 base = temp_byte;
532 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &temp_byte);
533 length = temp_byte;
534
535 if ((base <= length) && (!disable || (save_command & PCI_COMMAND_IO))) {
536 io_node = kmalloc(sizeof(struct pci_resource),
537 GFP_KERNEL);
538 if (!io_node)
539 return -ENOMEM;
540
541 io_node->base = (ulong)(base & PCI_IO_RANGE_MASK) << 8;
542 io_node->length = (ulong)(length - base + 0x10) << 8;
543
544 io_node->next = func->io_head;
545 func->io_head = io_node;
546 }
547
548 /* Save memory base and Limit registers */
549 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
550 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
551
552 if ((w_base <= w_length) && (!disable || (save_command & PCI_COMMAND_MEMORY))) {
553 mem_node = kmalloc(sizeof(struct pci_resource),
554 GFP_KERNEL);
555 if (!mem_node)
556 return -ENOMEM;
557
558 mem_node->base = (ulong)w_base << 16;
559 mem_node->length = (ulong)(w_length - w_base + 0x10) << 16;
560
561 mem_node->next = func->mem_head;
562 func->mem_head = mem_node;
563 }
564 /* Save prefetchable memory base and Limit registers */
565 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
566 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
567
568 if ((w_base <= w_length) && (!disable || (save_command & PCI_COMMAND_MEMORY))) {
569 p_mem_node = kmalloc(sizeof(struct pci_resource),
570 GFP_KERNEL);
571 if (!p_mem_node)
572 return -ENOMEM;
573
574 p_mem_node->base = (ulong)w_base << 16;
575 p_mem_node->length = (ulong)(w_length - w_base + 0x10) << 16;
576
577 p_mem_node->next = func->p_mem_head;
578 func->p_mem_head = p_mem_node;
579 }
580 } else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
581 dbg("Save_used_res of PCI adapter b:d=0x%x:%x, sc=0x%x\n",
582 func->bus, func->device, save_command);
583
584 /* Figure out IO and memory base lengths */
585 for (cloop = PCI_BASE_ADDRESS_0; cloop <= PCI_BASE_ADDRESS_5; cloop += 4) {
586 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
587
588 temp_register = 0xFFFFFFFF;
589 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
590 pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp_register);
591
592 if (!disable)
593 pci_bus_write_config_dword(pci_bus, devfn, cloop, save_base);
594
595 if (!temp_register)
596 continue;
597
598 base = temp_register;
599
600 if ((base & PCI_BASE_ADDRESS_SPACE_IO) &&
601 (!disable || (save_command & PCI_COMMAND_IO))) {
602 /* IO base */
603 /* set temp_register = amount of IO space requested */
604 base = base & 0xFFFFFFFCL;
605 base = (~base) + 1;
606
607 io_node = kmalloc(sizeof (struct pci_resource),
608 GFP_KERNEL);
609 if (!io_node)
610 return -ENOMEM;
611
612 io_node->base = (ulong)save_base & PCI_BASE_ADDRESS_IO_MASK;
613 io_node->length = (ulong)base;
614 dbg("sur adapter: IO bar=0x%x(length=0x%x)\n",
615 io_node->base, io_node->length);
616
617 io_node->next = func->io_head;
618 func->io_head = io_node;
619 } else { /* map Memory */
620 int prefetchable = 1;
621 /* struct pci_resources **res_node; */
622 char *res_type_str = "PMEM";
623 u32 temp_register2;
624
625 t_mem_node = kmalloc(sizeof (struct pci_resource),
626 GFP_KERNEL);
627 if (!t_mem_node)
628 return -ENOMEM;
629
630 if (!(base & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
631 (!disable || (save_command & PCI_COMMAND_MEMORY))) {
632 prefetchable = 0;
633 mem_node = t_mem_node;
634 res_type_str++;
635 } else
636 p_mem_node = t_mem_node;
637
638 base = base & 0xFFFFFFF0L;
639 base = (~base) + 1;
640
641 switch (temp_register & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
642 case PCI_BASE_ADDRESS_MEM_TYPE_32:
643 if (prefetchable) {
644 p_mem_node->base = (ulong)save_base & PCI_BASE_ADDRESS_MEM_MASK;
645 p_mem_node->length = (ulong)base;
646 dbg("sur adapter: 32 %s bar=0x%x(length=0x%x)\n",
647 res_type_str,
648 p_mem_node->base,
649 p_mem_node->length);
650
651 p_mem_node->next = func->p_mem_head;
652 func->p_mem_head = p_mem_node;
653 } else {
654 mem_node->base = (ulong)save_base & PCI_BASE_ADDRESS_MEM_MASK;
655 mem_node->length = (ulong)base;
656 dbg("sur adapter: 32 %s bar=0x%x(length=0x%x)\n",
657 res_type_str,
658 mem_node->base,
659 mem_node->length);
660
661 mem_node->next = func->mem_head;
662 func->mem_head = mem_node;
663 }
664 break;
665 case PCI_BASE_ADDRESS_MEM_TYPE_64:
666 pci_bus_read_config_dword(pci_bus, devfn, cloop+4, &temp_register2);
667 base64 = temp_register2;
668 base64 = (base64 << 32) | save_base;
669
670 if (temp_register2) {
671 dbg("sur adapter: 64 %s high dword of base64(0x%x:%x) masked to 0\n",
672 res_type_str, temp_register2, (u32)base64);
673 base64 &= 0x00000000FFFFFFFFL;
674 }
675
676 if (prefetchable) {
677 p_mem_node->base = base64 & PCI_BASE_ADDRESS_MEM_MASK;
678 p_mem_node->length = base;
679 dbg("sur adapter: 64 %s base=0x%x(len=0x%x)\n",
680 res_type_str,
681 p_mem_node->base,
682 p_mem_node->length);
683
684 p_mem_node->next = func->p_mem_head;
685 func->p_mem_head = p_mem_node;
686 } else {
687 mem_node->base = base64 & PCI_BASE_ADDRESS_MEM_MASK;
688 mem_node->length = base;
689 dbg("sur adapter: 64 %s base=0x%x(len=0x%x)\n",
690 res_type_str,
691 mem_node->base,
692 mem_node->length);
693
694 mem_node->next = func->mem_head;
695 func->mem_head = mem_node;
696 }
697 cloop += 4;
698 break;
699 default:
700 dbg("asur: reserved BAR type=0x%x\n",
701 temp_register);
702 break;
703 }
704 }
705 } /* End of base register loop */
706 } else { /* Some other unknown header type */
707 dbg("Save_used_res of PCI unknown type b:d=0x%x:%x. skip.\n",
708 func->bus, func->device);
709 } 172 }
710 173 pci_remove_bus_device(temp);
711 /* find the next device in this slot */
712 if (!disable)
713 break;
714 func = shpchp_slot_find(func->bus, func->device, index++);
715 } 174 }
716
717 return 0;
718}
719
720/**
721 * kfree_resource_list: release memory of all list members
722 * @res: resource list to free
723 */
724static inline void
725return_resource_list(struct pci_resource **func, struct pci_resource **res)
726{
727 struct pci_resource *node;
728 struct pci_resource *t_node;
729
730 node = *func;
731 *func = NULL;
732 while (node) {
733 t_node = node->next;
734 return_resource(res, node);
735 node = t_node;
736 }
737}
738
739/*
740 * shpchp_return_board_resources
741 *
742 * this routine returns all resources allocated to a board to
743 * the available pool.
744 *
745 * returns 0 if success
746 */
747int shpchp_return_board_resources(struct pci_func * func,
748 struct resource_lists * resources)
749{
750 int rc;
751 dbg("%s\n", __FUNCTION__);
752
753 if (!func)
754 return 1;
755
756 return_resource_list(&(func->io_head),&(resources->io_head));
757 return_resource_list(&(func->mem_head),&(resources->mem_head));
758 return_resource_list(&(func->p_mem_head),&(resources->p_mem_head));
759 return_resource_list(&(func->bus_head),&(resources->bus_head));
760
761 rc = shpchp_resource_sort_and_combine(&(resources->mem_head));
762 rc |= shpchp_resource_sort_and_combine(&(resources->p_mem_head));
763 rc |= shpchp_resource_sort_and_combine(&(resources->io_head));
764 rc |= shpchp_resource_sort_and_combine(&(resources->bus_head));
765
766 return rc; 175 return rc;
767} 176}
768 177
769/**
770 * kfree_resource_list: release memory of all list members
771 * @res: resource list to free
772 */
773static inline void
774kfree_resource_list(struct pci_resource **r)
775{
776 struct pci_resource *res, *tres;
777
778 res = *r;
779 *r = NULL;
780
781 while (res) {
782 tres = res;
783 res = res->next;
784 kfree(tres);
785 }
786}
787
788/**
789 * shpchp_destroy_resource_list: put node back in the resource list
790 * @resources: list to put nodes back
791 */
792void shpchp_destroy_resource_list(struct resource_lists *resources)
793{
794 kfree_resource_list(&(resources->io_head));
795 kfree_resource_list(&(resources->mem_head));
796 kfree_resource_list(&(resources->p_mem_head));
797 kfree_resource_list(&(resources->bus_head));
798}
799
800/**
801 * shpchp_destroy_board_resources: put node back in the resource list
802 * @resources: list to put nodes back
803 */
804void shpchp_destroy_board_resources(struct pci_func * func)
805{
806 kfree_resource_list(&(func->io_head));
807 kfree_resource_list(&(func->mem_head));
808 kfree_resource_list(&(func->p_mem_head));
809 kfree_resource_list(&(func->bus_head));
810}
diff --git a/drivers/pci/hotplug/shpchp_sysfs.c b/drivers/pci/hotplug/shpchp_sysfs.c
index c9445ebda5c7..f5cfbf2c047c 100644
--- a/drivers/pci/hotplug/shpchp_sysfs.c
+++ b/drivers/pci/hotplug/shpchp_sysfs.c
@@ -26,12 +26,9 @@
26 * 26 *
27 */ 27 */
28 28
29#include <linux/config.h>
30#include <linux/module.h> 29#include <linux/module.h>
31#include <linux/kernel.h> 30#include <linux/kernel.h>
32#include <linux/types.h> 31#include <linux/types.h>
33#include <linux/proc_fs.h>
34#include <linux/workqueue.h>
35#include <linux/pci.h> 32#include <linux/pci.h>
36#include "shpchp.h" 33#include "shpchp.h"
37 34
@@ -40,104 +37,60 @@
40 37
41static ssize_t show_ctrl (struct device *dev, struct device_attribute *attr, char *buf) 38static ssize_t show_ctrl (struct device *dev, struct device_attribute *attr, char *buf)
42{ 39{
43 struct pci_dev *pci_dev; 40 struct pci_dev *pdev;
44 struct controller *ctrl;
45 char * out = buf; 41 char * out = buf;
46 int index; 42 int index, busnr;
47 struct pci_resource *res; 43 struct resource *res;
44 struct pci_bus *bus;
48 45
49 pci_dev = container_of (dev, struct pci_dev, dev); 46 pdev = container_of (dev, struct pci_dev, dev);
50 ctrl = pci_get_drvdata(pci_dev); 47 bus = pdev->subordinate;
51 48
52 out += sprintf(buf, "Free resources: memory\n"); 49 out += sprintf(buf, "Free resources: memory\n");
53 index = 11; 50 for (index = 0; index < PCI_BUS_NUM_RESOURCES; index++) {
54 res = ctrl->mem_head; 51 res = bus->resource[index];
55 while (res && index--) { 52 if (res && (res->flags & IORESOURCE_MEM) &&
56 out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length); 53 !(res->flags & IORESOURCE_PREFETCH)) {
57 res = res->next; 54 out += sprintf(out, "start = %8.8lx, length = %8.8lx\n",
55 res->start, (res->end - res->start));
56 }
58 } 57 }
59 out += sprintf(out, "Free resources: prefetchable memory\n"); 58 out += sprintf(out, "Free resources: prefetchable memory\n");
60 index = 11; 59 for (index = 0; index < PCI_BUS_NUM_RESOURCES; index++) {
61 res = ctrl->p_mem_head; 60 res = bus->resource[index];
62 while (res && index--) { 61 if (res && (res->flags & IORESOURCE_MEM) &&
63 out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length); 62 (res->flags & IORESOURCE_PREFETCH)) {
64 res = res->next; 63 out += sprintf(out, "start = %8.8lx, length = %8.8lx\n",
64 res->start, (res->end - res->start));
65 }
65 } 66 }
66 out += sprintf(out, "Free resources: IO\n"); 67 out += sprintf(out, "Free resources: IO\n");
67 index = 11; 68 for (index = 0; index < PCI_BUS_NUM_RESOURCES; index++) {
68 res = ctrl->io_head; 69 res = bus->resource[index];
69 while (res && index--) { 70 if (res && (res->flags & IORESOURCE_IO)) {
70 out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length); 71 out += sprintf(out, "start = %8.8lx, length = %8.8lx\n",
71 res = res->next; 72 res->start, (res->end - res->start));
73 }
72 } 74 }
73 out += sprintf(out, "Free resources: bus numbers\n"); 75 out += sprintf(out, "Free resources: bus numbers\n");
74 index = 11; 76 for (busnr = bus->secondary; busnr <= bus->subordinate; busnr++) {
75 res = ctrl->bus_head; 77 if (!pci_find_bus(pci_domain_nr(bus), busnr))
76 while (res && index--) { 78 break;
77 out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length);
78 res = res->next;
79 } 79 }
80 if (busnr < bus->subordinate)
81 out += sprintf(out, "start = %8.8x, length = %8.8x\n",
82 busnr, (bus->subordinate - busnr));
80 83
81 return out - buf; 84 return out - buf;
82} 85}
83static DEVICE_ATTR (ctrl, S_IRUGO, show_ctrl, NULL); 86static DEVICE_ATTR (ctrl, S_IRUGO, show_ctrl, NULL);
84 87
85static ssize_t show_dev (struct device *dev, struct device_attribute *attr, char *buf) 88void shpchp_create_ctrl_files (struct controller *ctrl)
86{ 89{
87 struct pci_dev *pci_dev; 90 device_create_file (&ctrl->pci_dev->dev, &dev_attr_ctrl);
88 struct controller *ctrl;
89 char * out = buf;
90 int index;
91 struct pci_resource *res;
92 struct pci_func *new_slot;
93 struct slot *slot;
94
95 pci_dev = container_of (dev, struct pci_dev, dev);
96 ctrl = pci_get_drvdata(pci_dev);
97
98 slot=ctrl->slot;
99
100 while (slot) {
101 new_slot = shpchp_slot_find(slot->bus, slot->device, 0);
102 if (!new_slot)
103 break;
104 out += sprintf(out, "assigned resources: memory\n");
105 index = 11;
106 res = new_slot->mem_head;
107 while (res && index--) {
108 out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length);
109 res = res->next;
110 }
111 out += sprintf(out, "assigned resources: prefetchable memory\n");
112 index = 11;
113 res = new_slot->p_mem_head;
114 while (res && index--) {
115 out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length);
116 res = res->next;
117 }
118 out += sprintf(out, "assigned resources: IO\n");
119 index = 11;
120 res = new_slot->io_head;
121 while (res && index--) {
122 out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length);
123 res = res->next;
124 }
125 out += sprintf(out, "assigned resources: bus numbers\n");
126 index = 11;
127 res = new_slot->bus_head;
128 while (res && index--) {
129 out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length);
130 res = res->next;
131 }
132 slot=slot->next;
133 }
134
135 return out - buf;
136} 91}
137static DEVICE_ATTR (dev, S_IRUGO, show_dev, NULL);
138 92
139void shpchp_create_ctrl_files (struct controller *ctrl) 93void shpchp_remove_ctrl_files(struct controller *ctrl)
140{ 94{
141 device_create_file (&ctrl->pci_dev->dev, &dev_attr_ctrl); 95 device_remove_file(&ctrl->pci_dev->dev, &dev_attr_ctrl);
142 device_create_file (&ctrl->pci_dev->dev, &dev_attr_dev);
143} 96}
diff --git a/drivers/pci/hotplug/shpchprm.h b/drivers/pci/hotplug/shpchprm.h
deleted file mode 100644
index 057b192ce589..000000000000
--- a/drivers/pci/hotplug/shpchprm.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * SHPCHPRM : SHPCHP Resource Manager for ACPI/non-ACPI platform
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
27 *
28 */
29
30#ifndef _SHPCHPRM_H_
31#define _SHPCHPRM_H_
32
33#ifdef CONFIG_HOTPLUG_PCI_SHPC_PHPRM_LEGACY
34#include "shpchprm_legacy.h"
35#else
36#include "shpchprm_nonacpi.h"
37#endif
38
39int shpchprm_init(enum php_ctlr_type ct);
40void shpchprm_cleanup(void);
41int shpchprm_print_pirt(void);
42int shpchprm_find_available_resources(struct controller *ctrl);
43int shpchprm_set_hpp(struct controller *ctrl, struct pci_func *func, u8 card_type);
44void shpchprm_enable_card(struct controller *ctrl, struct pci_func *func, u8 card_type);
45int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum);
46
47#ifdef DEBUG
48#define RES_CHECK(this, bits) \
49 { if (((this) & (bits - 1))) \
50 printk("%s:%d ERR: potential res loss!\n", __FUNCTION__, __LINE__); }
51#else
52#define RES_CHECK(this, bits)
53#endif
54
55#endif /* _SHPCHPRM_H_ */
diff --git a/drivers/pci/hotplug/shpchprm_acpi.c b/drivers/pci/hotplug/shpchprm_acpi.c
index d37b31658edf..17145e52223a 100644
--- a/drivers/pci/hotplug/shpchprm_acpi.c
+++ b/drivers/pci/hotplug/shpchprm_acpi.c
@@ -24,91 +24,19 @@
24 * 24 *
25 */ 25 */
26 26
27#include <linux/config.h>
28#include <linux/module.h> 27#include <linux/module.h>
29#include <linux/kernel.h> 28#include <linux/kernel.h>
30#include <linux/types.h> 29#include <linux/types.h>
31#include <linux/pci.h> 30#include <linux/pci.h>
32#include <linux/init.h>
33#include <linux/acpi.h>
34#include <linux/efi.h>
35#include <asm/uaccess.h>
36#include <asm/system.h>
37#ifdef CONFIG_IA64
38#include <asm/iosapic.h>
39#endif
40#include <acpi/acpi.h> 31#include <acpi/acpi.h>
41#include <acpi/acpi_bus.h> 32#include <acpi/acpi_bus.h>
42#include <acpi/actypes.h> 33#include <acpi/actypes.h>
43#include "shpchp.h" 34#include "shpchp.h"
44#include "shpchprm.h"
45
46#define PCI_MAX_BUS 0x100
47#define ACPI_STA_DEVICE_PRESENT 0x01
48 35
49#define METHOD_NAME__SUN "_SUN" 36#define METHOD_NAME__SUN "_SUN"
50#define METHOD_NAME__HPP "_HPP" 37#define METHOD_NAME__HPP "_HPP"
51#define METHOD_NAME_OSHP "OSHP" 38#define METHOD_NAME_OSHP "OSHP"
52 39
53#define PHP_RES_BUS 0xA0
54#define PHP_RES_IO 0xA1
55#define PHP_RES_MEM 0xA2
56#define PHP_RES_PMEM 0xA3
57
58#define BRIDGE_TYPE_P2P 0x00
59#define BRIDGE_TYPE_HOST 0x01
60
61/* this should go to drivers/acpi/include/ */
62struct acpi__hpp {
63 u8 cache_line_size;
64 u8 latency_timer;
65 u8 enable_serr;
66 u8 enable_perr;
67};
68
69struct acpi_php_slot {
70 struct acpi_php_slot *next;
71 struct acpi_bridge *bridge;
72 acpi_handle handle;
73 int seg;
74 int bus;
75 int dev;
76 int fun;
77 u32 sun;
78 struct pci_resource *mem_head;
79 struct pci_resource *p_mem_head;
80 struct pci_resource *io_head;
81 struct pci_resource *bus_head;
82 void *slot_ops; /* _STA, _EJx, etc */
83 struct slot *slot;
84}; /* per func */
85
86struct acpi_bridge {
87 struct acpi_bridge *parent;
88 struct acpi_bridge *next;
89 struct acpi_bridge *child;
90 acpi_handle handle;
91 int seg;
92 int pbus; /* pdev->bus->number */
93 int pdevice; /* PCI_SLOT(pdev->devfn) */
94 int pfunction; /* PCI_DEVFN(pdev->devfn) */
95 int bus; /* pdev->subordinate->number */
96 struct acpi__hpp *_hpp;
97 struct acpi_php_slot *slots;
98 struct pci_resource *tmem_head; /* total from crs */
99 struct pci_resource *tp_mem_head; /* total from crs */
100 struct pci_resource *tio_head; /* total from crs */
101 struct pci_resource *tbus_head; /* total from crs */
102 struct pci_resource *mem_head; /* available */
103 struct pci_resource *p_mem_head; /* available */
104 struct pci_resource *io_head; /* available */
105 struct pci_resource *bus_head; /* available */
106 int scanned;
107 int type;
108};
109
110static struct acpi_bridge *acpi_bridges_head;
111
112static u8 * acpi_path_name( acpi_handle handle) 40static u8 * acpi_path_name( acpi_handle handle)
113{ 41{
114 acpi_status status; 42 acpi_status status;
@@ -124,82 +52,43 @@ static u8 * acpi_path_name( acpi_handle handle)
124 return path_name; 52 return path_name;
125} 53}
126 54
127static void acpi_get__hpp ( struct acpi_bridge *ab); 55static acpi_status
128static void acpi_run_oshp ( struct acpi_bridge *ab); 56acpi_run_hpp(acpi_handle handle, struct hotplug_params *hpp)
129
130static int acpi_add_slot_to_php_slots(
131 struct acpi_bridge *ab,
132 int bus_num,
133 acpi_handle handle,
134 u32 adr,
135 u32 sun
136 )
137{
138 struct acpi_php_slot *aps;
139 static long samesun = -1;
140
141 aps = (struct acpi_php_slot *) kmalloc (sizeof(struct acpi_php_slot), GFP_KERNEL);
142 if (!aps) {
143 err ("acpi_shpchprm: alloc for aps fail\n");
144 return -1;
145 }
146 memset(aps, 0, sizeof(struct acpi_php_slot));
147
148 aps->handle = handle;
149 aps->bus = bus_num;
150 aps->dev = (adr >> 16) & 0xffff;
151 aps->fun = adr & 0xffff;
152 aps->sun = sun;
153
154 aps->next = ab->slots; /* cling to the bridge */
155 aps->bridge = ab;
156 ab->slots = aps;
157
158 ab->scanned += 1;
159 if (!ab->_hpp)
160 acpi_get__hpp(ab);
161
162 acpi_run_oshp(ab);
163
164 if (sun != samesun) {
165 info("acpi_shpchprm: Slot sun(%x) at s:b:d:f=0x%02x:%02x:%02x:%02x\n", aps->sun, ab->seg,
166 aps->bus, aps->dev, aps->fun);
167 samesun = sun;
168 }
169 return 0;
170}
171
172static void acpi_get__hpp ( struct acpi_bridge *ab)
173{ 57{
174 acpi_status status; 58 acpi_status status;
175 u8 nui[4]; 59 u8 nui[4];
176 struct acpi_buffer ret_buf = { 0, NULL}; 60 struct acpi_buffer ret_buf = { 0, NULL};
177 union acpi_object *ext_obj, *package; 61 union acpi_object *ext_obj, *package;
178 u8 *path_name = acpi_path_name(ab->handle); 62 u8 *path_name = acpi_path_name(handle);
179 int i, len = 0; 63 int i, len = 0;
180 64
181 /* get _hpp */ 65 /* get _hpp */
182 status = acpi_evaluate_object(ab->handle, METHOD_NAME__HPP, NULL, &ret_buf); 66 status = acpi_evaluate_object(handle, METHOD_NAME__HPP, NULL, &ret_buf);
183 switch (status) { 67 switch (status) {
184 case AE_BUFFER_OVERFLOW: 68 case AE_BUFFER_OVERFLOW:
185 ret_buf.pointer = kmalloc (ret_buf.length, GFP_KERNEL); 69 ret_buf.pointer = kmalloc (ret_buf.length, GFP_KERNEL);
186 if (!ret_buf.pointer) { 70 if (!ret_buf.pointer) {
187 err ("acpi_shpchprm:%s alloc for _HPP fail\n", path_name); 71 err ("%s:%s alloc for _HPP fail\n", __FUNCTION__,
188 return; 72 path_name);
73 return AE_NO_MEMORY;
189 } 74 }
190 status = acpi_evaluate_object(ab->handle, METHOD_NAME__HPP, NULL, &ret_buf); 75 status = acpi_evaluate_object(handle, METHOD_NAME__HPP,
76 NULL, &ret_buf);
191 if (ACPI_SUCCESS(status)) 77 if (ACPI_SUCCESS(status))
192 break; 78 break;
193 default: 79 default:
194 if (ACPI_FAILURE(status)) { 80 if (ACPI_FAILURE(status)) {
195 err("acpi_shpchprm:%s _HPP fail=0x%x\n", path_name, status); 81 dbg("%s:%s _HPP fail=0x%x\n", __FUNCTION__,
196 return; 82 path_name, status);
83 return status;
197 } 84 }
198 } 85 }
199 86
200 ext_obj = (union acpi_object *) ret_buf.pointer; 87 ext_obj = (union acpi_object *) ret_buf.pointer;
201 if (ext_obj->type != ACPI_TYPE_PACKAGE) { 88 if (ext_obj->type != ACPI_TYPE_PACKAGE) {
202 err ("acpi_shpchprm:%s _HPP obj not a package\n", path_name); 89 err ("%s:%s _HPP obj not a package\n", __FUNCTION__,
90 path_name);
91 status = AE_ERROR;
203 goto free_and_return; 92 goto free_and_return;
204 } 93 }
205 94
@@ -212,1353 +101,41 @@ static void acpi_get__hpp ( struct acpi_bridge *ab)
212 nui[i] = (u8)ext_obj->integer.value; 101 nui[i] = (u8)ext_obj->integer.value;
213 break; 102 break;
214 default: 103 default:
215 err ("acpi_shpchprm:%s _HPP obj type incorrect\n", path_name); 104 err ("%s:%s _HPP obj type incorrect\n", __FUNCTION__,
105 path_name);
106 status = AE_ERROR;
216 goto free_and_return; 107 goto free_and_return;
217 } 108 }
218 } 109 }
219 110
220 ab->_hpp = kmalloc (sizeof (struct acpi__hpp), GFP_KERNEL); 111 hpp->cache_line_size = nui[0];
221 if (!ab->_hpp) { 112 hpp->latency_timer = nui[1];
222 err ("acpi_shpchprm:%s alloc for _HPP failed\n", path_name); 113 hpp->enable_serr = nui[2];
223 goto free_and_return; 114 hpp->enable_perr = nui[3];
224 }
225 memset(ab->_hpp, 0, sizeof(struct acpi__hpp));
226 115
227 ab->_hpp->cache_line_size = nui[0]; 116 dbg(" _HPP: cache_line_size=0x%x\n", hpp->cache_line_size);
228 ab->_hpp->latency_timer = nui[1]; 117 dbg(" _HPP: latency timer =0x%x\n", hpp->latency_timer);
229 ab->_hpp->enable_serr = nui[2]; 118 dbg(" _HPP: enable SERR =0x%x\n", hpp->enable_serr);
230 ab->_hpp->enable_perr = nui[3]; 119 dbg(" _HPP: enable PERR =0x%x\n", hpp->enable_perr);
231
232 dbg(" _HPP: cache_line_size=0x%x\n", ab->_hpp->cache_line_size);
233 dbg(" _HPP: latency timer =0x%x\n", ab->_hpp->latency_timer);
234 dbg(" _HPP: enable SERR =0x%x\n", ab->_hpp->enable_serr);
235 dbg(" _HPP: enable PERR =0x%x\n", ab->_hpp->enable_perr);
236 120
237free_and_return: 121free_and_return:
238 kfree(ret_buf.pointer); 122 kfree(ret_buf.pointer);
239}
240
241static void acpi_run_oshp ( struct acpi_bridge *ab)
242{
243 acpi_status status;
244 u8 *path_name = acpi_path_name(ab->handle);
245
246 /* run OSHP */
247 status = acpi_evaluate_object(ab->handle, METHOD_NAME_OSHP, NULL, NULL);
248 if (ACPI_FAILURE(status)) {
249 err("acpi_pciehprm:%s OSHP fails=0x%x\n", path_name, status);
250 } else
251 dbg("acpi_pciehprm:%s OSHP passes =0x%x\n", path_name, status);
252 return;
253}
254
255static acpi_status acpi_evaluate_crs(
256 acpi_handle handle,
257 struct acpi_resource **retbuf
258 )
259{
260 acpi_status status;
261 struct acpi_buffer crsbuf;
262 u8 *path_name = acpi_path_name(handle);
263
264 crsbuf.length = 0;
265 crsbuf.pointer = NULL;
266
267 status = acpi_get_current_resources (handle, &crsbuf);
268
269 switch (status) {
270 case AE_BUFFER_OVERFLOW:
271 break; /* found */
272 case AE_NOT_FOUND:
273 dbg("acpi_shpchprm:%s _CRS not found\n", path_name);
274 return status;
275 default:
276 err ("acpi_shpchprm:%s _CRS fail=0x%x\n", path_name, status);
277 return status;
278 }
279
280 crsbuf.pointer = kmalloc (crsbuf.length, GFP_KERNEL);
281 if (!crsbuf.pointer) {
282 err ("acpi_shpchprm: alloc %ld bytes for %s _CRS fail\n", (ulong)crsbuf.length, path_name);
283 return AE_NO_MEMORY;
284 }
285
286 status = acpi_get_current_resources (handle, &crsbuf);
287 if (ACPI_FAILURE(status)) {
288 err("acpi_shpchprm: %s _CRS fail=0x%x.\n", path_name, status);
289 kfree(crsbuf.pointer);
290 return status;
291 }
292
293 *retbuf = crsbuf.pointer;
294
295 return status;
296}
297
298static void free_pci_resource ( struct pci_resource *aprh)
299{
300 struct pci_resource *res, *next;
301
302 for (res = aprh; res; res = next) {
303 next = res->next;
304 kfree(res);
305 }
306}
307
308static void print_pci_resource ( struct pci_resource *aprh)
309{
310 struct pci_resource *res;
311
312 for (res = aprh; res; res = res->next)
313 dbg(" base= 0x%x length= 0x%x\n", res->base, res->length);
314}
315
316static void print_slot_resources( struct acpi_php_slot *aps)
317{
318 if (aps->bus_head) {
319 dbg(" BUS Resources:\n");
320 print_pci_resource (aps->bus_head);
321 }
322
323 if (aps->io_head) {
324 dbg(" IO Resources:\n");
325 print_pci_resource (aps->io_head);
326 }
327
328 if (aps->mem_head) {
329 dbg(" MEM Resources:\n");
330 print_pci_resource (aps->mem_head);
331 }
332
333 if (aps->p_mem_head) {
334 dbg(" PMEM Resources:\n");
335 print_pci_resource (aps->p_mem_head);
336 }
337}
338
339static void print_pci_resources( struct acpi_bridge *ab)
340{
341 if (ab->tbus_head) {
342 dbg(" Total BUS Resources:\n");
343 print_pci_resource (ab->tbus_head);
344 }
345 if (ab->bus_head) {
346 dbg(" BUS Resources:\n");
347 print_pci_resource (ab->bus_head);
348 }
349
350 if (ab->tio_head) {
351 dbg(" Total IO Resources:\n");
352 print_pci_resource (ab->tio_head);
353 }
354 if (ab->io_head) {
355 dbg(" IO Resources:\n");
356 print_pci_resource (ab->io_head);
357 }
358
359 if (ab->tmem_head) {
360 dbg(" Total MEM Resources:\n");
361 print_pci_resource (ab->tmem_head);
362 }
363 if (ab->mem_head) {
364 dbg(" MEM Resources:\n");
365 print_pci_resource (ab->mem_head);
366 }
367
368 if (ab->tp_mem_head) {
369 dbg(" Total PMEM Resources:\n");
370 print_pci_resource (ab->tp_mem_head);
371 }
372 if (ab->p_mem_head) {
373 dbg(" PMEM Resources:\n");
374 print_pci_resource (ab->p_mem_head);
375 }
376 if (ab->_hpp) {
377 dbg(" _HPP: cache_line_size=0x%x\n", ab->_hpp->cache_line_size);
378 dbg(" _HPP: latency timer =0x%x\n", ab->_hpp->latency_timer);
379 dbg(" _HPP: enable SERR =0x%x\n", ab->_hpp->enable_serr);
380 dbg(" _HPP: enable PERR =0x%x\n", ab->_hpp->enable_perr);
381 }
382}
383
384static int shpchprm_delete_resource(
385 struct pci_resource **aprh,
386 ulong base,
387 ulong size)
388{
389 struct pci_resource *res;
390 struct pci_resource *prevnode;
391 struct pci_resource *split_node;
392 ulong tbase;
393
394 shpchp_resource_sort_and_combine(aprh);
395
396 for (res = *aprh; res; res = res->next) {
397 if (res->base > base)
398 continue;
399
400 if ((res->base + res->length) < (base + size))
401 continue;
402
403 if (res->base < base) {
404 tbase = base;
405
406 if ((res->length - (tbase - res->base)) < size)
407 continue;
408
409 split_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
410 if (!split_node)
411 return -ENOMEM;
412
413 split_node->base = res->base;
414 split_node->length = tbase - res->base;
415 res->base = tbase;
416 res->length -= split_node->length;
417
418 split_node->next = res->next;
419 res->next = split_node;
420 }
421
422 if (res->length >= size) {
423 split_node = (struct pci_resource*) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
424 if (!split_node)
425 return -ENOMEM;
426
427 split_node->base = res->base + size;
428 split_node->length = res->length - size;
429 res->length = size;
430
431 split_node->next = res->next;
432 res->next = split_node;
433 }
434
435 if (*aprh == res) {
436 *aprh = res->next;
437 } else {
438 prevnode = *aprh;
439 while (prevnode->next != res)
440 prevnode = prevnode->next;
441
442 prevnode->next = res->next;
443 }
444 res->next = NULL;
445 kfree(res);
446 break;
447 }
448
449 return 0;
450}
451
452static int shpchprm_delete_resources(
453 struct pci_resource **aprh,
454 struct pci_resource *this
455 )
456{
457 struct pci_resource *res;
458
459 for (res = this; res; res = res->next)
460 shpchprm_delete_resource(aprh, res->base, res->length);
461
462 return 0;
463}
464
465static int shpchprm_add_resource(
466 struct pci_resource **aprh,
467 ulong base,
468 ulong size)
469{
470 struct pci_resource *res;
471
472 for (res = *aprh; res; res = res->next) {
473 if ((res->base + res->length) == base) {
474 res->length += size;
475 size = 0L;
476 break;
477 }
478 if (res->next == *aprh)
479 break;
480 }
481
482 if (size) {
483 res = kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
484 if (!res) {
485 err ("acpi_shpchprm: alloc for res fail\n");
486 return -ENOMEM;
487 }
488 memset(res, 0, sizeof (struct pci_resource));
489
490 res->base = base;
491 res->length = size;
492 res->next = *aprh;
493 *aprh = res;
494 }
495
496 return 0;
497}
498
499static int shpchprm_add_resources(
500 struct pci_resource **aprh,
501 struct pci_resource *this
502 )
503{
504 struct pci_resource *res;
505 int rc = 0;
506
507 for (res = this; res && !rc; res = res->next)
508 rc = shpchprm_add_resource(aprh, res->base, res->length);
509
510 return rc;
511}
512
513static void acpi_parse_io (
514 struct acpi_bridge *ab,
515 union acpi_resource_data *data
516 )
517{
518 struct acpi_resource_io *dataio;
519 dataio = (struct acpi_resource_io *) data;
520
521 dbg("Io Resource\n");
522 dbg(" %d bit decode\n", ACPI_DECODE_16 == dataio->io_decode ? 16:10);
523 dbg(" Range minimum base: %08X\n", dataio->min_base_address);
524 dbg(" Range maximum base: %08X\n", dataio->max_base_address);
525 dbg(" Alignment: %08X\n", dataio->alignment);
526 dbg(" Range Length: %08X\n", dataio->range_length);
527}
528
529static void acpi_parse_fixed_io (
530 struct acpi_bridge *ab,
531 union acpi_resource_data *data
532 )
533{
534 struct acpi_resource_fixed_io *datafio;
535 datafio = (struct acpi_resource_fixed_io *) data;
536
537 dbg("Fixed Io Resource\n");
538 dbg(" Range base address: %08X", datafio->base_address);
539 dbg(" Range length: %08X", datafio->range_length);
540}
541
542static void acpi_parse_address16_32 (
543 struct acpi_bridge *ab,
544 union acpi_resource_data *data,
545 acpi_resource_type id
546 )
547{
548 /*
549 * acpi_resource_address16 == acpi_resource_address32
550 * acpi_resource_address16 *data16 = (acpi_resource_address16 *) data;
551 */
552 struct acpi_resource_address32 *data32 = (struct acpi_resource_address32 *) data;
553 struct pci_resource **aprh, **tprh;
554
555 if (id == ACPI_RSTYPE_ADDRESS16)
556 dbg("acpi_shpchprm:16-Bit Address Space Resource\n");
557 else
558 dbg("acpi_shpchprm:32-Bit Address Space Resource\n");
559
560 switch (data32->resource_type) {
561 case ACPI_MEMORY_RANGE:
562 dbg(" Resource Type: Memory Range\n");
563 aprh = &ab->mem_head;
564 tprh = &ab->tmem_head;
565
566 switch (data32->attribute.memory.cache_attribute) {
567 case ACPI_NON_CACHEABLE_MEMORY:
568 dbg(" Type Specific: Noncacheable memory\n");
569 break;
570 case ACPI_CACHABLE_MEMORY:
571 dbg(" Type Specific: Cacheable memory\n");
572 break;
573 case ACPI_WRITE_COMBINING_MEMORY:
574 dbg(" Type Specific: Write-combining memory\n");
575 break;
576 case ACPI_PREFETCHABLE_MEMORY:
577 aprh = &ab->p_mem_head;
578 dbg(" Type Specific: Prefetchable memory\n");
579 break;
580 default:
581 dbg(" Type Specific: Invalid cache attribute\n");
582 break;
583 }
584
585 dbg(" Type Specific: Read%s\n", ACPI_READ_WRITE_MEMORY == data32->attribute.memory.read_write_attribute ? "/Write":" Only");
586 break;
587
588 case ACPI_IO_RANGE:
589 dbg(" Resource Type: I/O Range\n");
590 aprh = &ab->io_head;
591 tprh = &ab->tio_head;
592
593 switch (data32->attribute.io.range_attribute) {
594 case ACPI_NON_ISA_ONLY_RANGES:
595 dbg(" Type Specific: Non-ISA Io Addresses\n");
596 break;
597 case ACPI_ISA_ONLY_RANGES:
598 dbg(" Type Specific: ISA Io Addresses\n");
599 break;
600 case ACPI_ENTIRE_RANGE:
601 dbg(" Type Specific: ISA and non-ISA Io Addresses\n");
602 break;
603 default:
604 dbg(" Type Specific: Invalid range attribute\n");
605 break;
606 }
607 break;
608
609 case ACPI_BUS_NUMBER_RANGE:
610 dbg(" Resource Type: Bus Number Range(fixed)\n");
611 /* fixup to be compatible with the rest of php driver */
612 data32->min_address_range++;
613 data32->address_length--;
614 aprh = &ab->bus_head;
615 tprh = &ab->tbus_head;
616 break;
617 default:
618 dbg(" Resource Type: Invalid resource type. Exiting.\n");
619 return;
620 }
621
622 dbg(" Resource %s\n", ACPI_CONSUMER == data32->producer_consumer ? "Consumer":"Producer");
623 dbg(" %s decode\n", ACPI_SUB_DECODE == data32->decode ? "Subtractive":"Positive");
624 dbg(" Min address is %s fixed\n", ACPI_ADDRESS_FIXED == data32->min_address_fixed ? "":"not");
625 dbg(" Max address is %s fixed\n", ACPI_ADDRESS_FIXED == data32->max_address_fixed ? "":"not");
626 dbg(" Granularity: %08X\n", data32->granularity);
627 dbg(" Address range min: %08X\n", data32->min_address_range);
628 dbg(" Address range max: %08X\n", data32->max_address_range);
629 dbg(" Address translation offset: %08X\n", data32->address_translation_offset);
630 dbg(" Address Length: %08X\n", data32->address_length);
631
632 if (0xFF != data32->resource_source.index) {
633 dbg(" Resource Source Index: %X\n", data32->resource_source.index);
634 /* dbg(" Resource Source: %s\n", data32->resource_source.string_ptr); */
635 }
636
637 shpchprm_add_resource(aprh, data32->min_address_range, data32->address_length);
638}
639
640static acpi_status acpi_parse_crs(
641 struct acpi_bridge *ab,
642 struct acpi_resource *crsbuf
643 )
644{
645 acpi_status status = AE_OK;
646 struct acpi_resource *resource = crsbuf;
647 u8 count = 0;
648 u8 done = 0;
649
650 while (!done) {
651 dbg("acpi_shpchprm: PCI bus 0x%x Resource structure %x.\n", ab->bus, count++);
652 switch (resource->id) {
653 case ACPI_RSTYPE_IRQ:
654 dbg("Irq -------- Resource\n");
655 break;
656 case ACPI_RSTYPE_DMA:
657 dbg("DMA -------- Resource\n");
658 break;
659 case ACPI_RSTYPE_START_DPF:
660 dbg("Start DPF -------- Resource\n");
661 break;
662 case ACPI_RSTYPE_END_DPF:
663 dbg("End DPF -------- Resource\n");
664 break;
665 case ACPI_RSTYPE_IO:
666 acpi_parse_io (ab, &resource->data);
667 break;
668 case ACPI_RSTYPE_FIXED_IO:
669 acpi_parse_fixed_io (ab, &resource->data);
670 break;
671 case ACPI_RSTYPE_VENDOR:
672 dbg("Vendor -------- Resource\n");
673 break;
674 case ACPI_RSTYPE_END_TAG:
675 dbg("End_tag -------- Resource\n");
676 done = 1;
677 break;
678 case ACPI_RSTYPE_MEM24:
679 dbg("Mem24 -------- Resource\n");
680 break;
681 case ACPI_RSTYPE_MEM32:
682 dbg("Mem32 -------- Resource\n");
683 break;
684 case ACPI_RSTYPE_FIXED_MEM32:
685 dbg("Fixed Mem32 -------- Resource\n");
686 break;
687 case ACPI_RSTYPE_ADDRESS16:
688 acpi_parse_address16_32(ab, &resource->data, ACPI_RSTYPE_ADDRESS16);
689 break;
690 case ACPI_RSTYPE_ADDRESS32:
691 acpi_parse_address16_32(ab, &resource->data, ACPI_RSTYPE_ADDRESS32);
692 break;
693 case ACPI_RSTYPE_ADDRESS64:
694 info("Address64 -------- Resource unparsed\n");
695 break;
696 case ACPI_RSTYPE_EXT_IRQ:
697 dbg("Ext Irq -------- Resource\n");
698 break;
699 default:
700 dbg("Invalid -------- resource type 0x%x\n", resource->id);
701 break;
702 }
703
704 resource = (struct acpi_resource *) ((char *)resource + resource->length);
705 }
706
707 return status; 123 return status;
708} 124}
709 125
710static acpi_status acpi_get_crs( struct acpi_bridge *ab) 126static void acpi_run_oshp(acpi_handle handle)
711{ 127{
712 acpi_status status; 128 acpi_status status;
713 struct acpi_resource *crsbuf;
714
715 status = acpi_evaluate_crs(ab->handle, &crsbuf);
716 if (ACPI_SUCCESS(status)) {
717 status = acpi_parse_crs(ab, crsbuf);
718 kfree(crsbuf);
719
720 shpchp_resource_sort_and_combine(&ab->bus_head);
721 shpchp_resource_sort_and_combine(&ab->io_head);
722 shpchp_resource_sort_and_combine(&ab->mem_head);
723 shpchp_resource_sort_and_combine(&ab->p_mem_head);
724
725 shpchprm_add_resources (&ab->tbus_head, ab->bus_head);
726 shpchprm_add_resources (&ab->tio_head, ab->io_head);
727 shpchprm_add_resources (&ab->tmem_head, ab->mem_head);
728 shpchprm_add_resources (&ab->tp_mem_head, ab->p_mem_head);
729 }
730
731 return status;
732}
733
734/* find acpi_bridge downword from ab. */
735static struct acpi_bridge *
736find_acpi_bridge_by_bus(
737 struct acpi_bridge *ab,
738 int seg,
739 int bus /* pdev->subordinate->number */
740 )
741{
742 struct acpi_bridge *lab = NULL;
743
744 if (!ab)
745 return NULL;
746
747 if ((ab->bus == bus) && (ab->seg == seg))
748 return ab;
749
750 if (ab->child)
751 lab = find_acpi_bridge_by_bus(ab->child, seg, bus);
752
753 if (!lab)
754 if (ab->next)
755 lab = find_acpi_bridge_by_bus(ab->next, seg, bus);
756
757 return lab;
758}
759
760/*
761 * Build a device tree of ACPI PCI Bridges
762 */
763static void shpchprm_acpi_register_a_bridge (
764 struct acpi_bridge **head,
765 struct acpi_bridge *pab, /* parent bridge to which child bridge is added */
766 struct acpi_bridge *cab /* child bridge to add */
767 )
768{
769 struct acpi_bridge *lpab;
770 struct acpi_bridge *lcab;
771
772 lpab = find_acpi_bridge_by_bus(*head, pab->seg, pab->bus);
773 if (!lpab) {
774 if (!(pab->type & BRIDGE_TYPE_HOST))
775 warn("PCI parent bridge s:b(%x:%x) not in list.\n", pab->seg, pab->bus);
776 pab->next = *head;
777 *head = pab;
778 lpab = pab;
779 }
780
781 if ((cab->type & BRIDGE_TYPE_HOST) && (pab == cab))
782 return;
783
784 lcab = find_acpi_bridge_by_bus(*head, cab->seg, cab->bus);
785 if (lcab) {
786 if ((pab->bus != lcab->parent->bus) || (lcab->bus != cab->bus))
787 err("PCI child bridge s:b(%x:%x) in list with diff parent.\n", cab->seg, cab->bus);
788 return;
789 } else
790 lcab = cab;
791
792 lcab->parent = lpab;
793 lcab->next = lpab->child;
794 lpab->child = lcab;
795}
796
797static acpi_status shpchprm_acpi_build_php_slots_callback(
798 acpi_handle handle,
799 u32 Level,
800 void *context,
801 void **retval
802 )
803{
804 ulong bus_num;
805 ulong seg_num;
806 ulong sun, adr;
807 ulong padr = 0;
808 acpi_handle phandle = NULL;
809 struct acpi_bridge *pab = (struct acpi_bridge *)context;
810 struct acpi_bridge *lab;
811 acpi_status status;
812 u8 *path_name = acpi_path_name(handle); 129 u8 *path_name = acpi_path_name(handle);
813 130
814 /* get _SUN */ 131 /* run OSHP */
815 status = acpi_evaluate_integer(handle, METHOD_NAME__SUN, NULL, &sun); 132 status = acpi_evaluate_object(handle, METHOD_NAME_OSHP, NULL, NULL);
816 switch(status) {
817 case AE_NOT_FOUND:
818 return AE_OK;
819 default:
820 if (ACPI_FAILURE(status)) {
821 err("acpi_shpchprm:%s _SUN fail=0x%x\n", path_name, status);
822 return status;
823 }
824 }
825
826 /* get _ADR. _ADR must exist if _SUN exists */
827 status = acpi_evaluate_integer(handle, METHOD_NAME__ADR, NULL, &adr);
828 if (ACPI_FAILURE(status)) {
829 err("acpi_shpchprm:%s _ADR fail=0x%x\n", path_name, status);
830 return status;
831 }
832
833 dbg("acpi_shpchprm:%s sun=0x%08x adr=0x%08x\n", path_name, (u32)sun, (u32)adr);
834
835 status = acpi_get_parent(handle, &phandle);
836 if (ACPI_FAILURE(status)) { 133 if (ACPI_FAILURE(status)) {
837 err("acpi_shpchprm:%s get_parent fail=0x%x\n", path_name, status); 134 err("%s:%s OSHP fails=0x%x\n", __FUNCTION__, path_name,
838 return (status); 135 status);
839 }
840
841 bus_num = pab->bus;
842 seg_num = pab->seg;
843
844 if (pab->bus == bus_num) {
845 lab = pab;
846 } else { 136 } else {
847 dbg("WARN: pab is not parent\n"); 137 dbg("%s:%s OSHP passes\n", __FUNCTION__, path_name);
848 lab = find_acpi_bridge_by_bus(pab, seg_num, bus_num);
849 if (!lab) {
850 dbg("acpi_shpchprm: alloc new P2P bridge(%x) for sun(%08x)\n", (u32)bus_num, (u32)sun);
851 lab = (struct acpi_bridge *)kmalloc(sizeof(struct acpi_bridge), GFP_KERNEL);
852 if (!lab) {
853 err("acpi_shpchprm: alloc for ab fail\n");
854 return AE_NO_MEMORY;
855 }
856 memset(lab, 0, sizeof(struct acpi_bridge));
857
858 lab->handle = phandle;
859 lab->pbus = pab->bus;
860 lab->pdevice = (int)(padr >> 16) & 0xffff;
861 lab->pfunction = (int)(padr & 0xffff);
862 lab->bus = (int)bus_num;
863 lab->scanned = 0;
864 lab->type = BRIDGE_TYPE_P2P;
865
866 shpchprm_acpi_register_a_bridge (&acpi_bridges_head, pab, lab);
867 } else
868 dbg("acpi_shpchprm: found P2P bridge(%x) for sun(%08x)\n", (u32)bus_num, (u32)sun);
869 } 138 }
870
871 acpi_add_slot_to_php_slots(lab, (int)bus_num, handle, (u32)adr, (u32)sun);
872 return (status);
873}
874
875static int shpchprm_acpi_build_php_slots(
876 struct acpi_bridge *ab,
877 u32 depth
878 )
879{
880 acpi_status status;
881 u8 *path_name = acpi_path_name(ab->handle);
882
883 /* Walk down this pci bridge to get _SUNs if any behind P2P */
884 status = acpi_walk_namespace ( ACPI_TYPE_DEVICE,
885 ab->handle,
886 depth,
887 shpchprm_acpi_build_php_slots_callback,
888 ab,
889 NULL );
890 if (ACPI_FAILURE(status)) {
891 dbg("acpi_shpchprm:%s walk for _SUN on pci bridge seg:bus(%x:%x) fail=0x%x\n", path_name, ab->seg, ab->bus, status);
892 return -1;
893 }
894
895 return 0;
896}
897
898static void build_a_bridge(
899 struct acpi_bridge *pab,
900 struct acpi_bridge *ab
901 )
902{
903 u8 *path_name = acpi_path_name(ab->handle);
904
905 shpchprm_acpi_register_a_bridge (&acpi_bridges_head, pab, ab);
906
907 switch (ab->type) {
908 case BRIDGE_TYPE_HOST:
909 dbg("acpi_shpchprm: Registered PCI HOST Bridge(%02x) on s:b:d:f(%02x:%02x:%02x:%02x) [%s]\n",
910 ab->bus, ab->seg, ab->pbus, ab->pdevice, ab->pfunction, path_name);
911 break;
912 case BRIDGE_TYPE_P2P:
913 dbg("acpi_shpchprm: Registered PCI P2P Bridge(%02x-%02x) on s:b:d:f(%02x:%02x:%02x:%02x) [%s]\n",
914 ab->pbus, ab->bus, ab->seg, ab->pbus, ab->pdevice, ab->pfunction, path_name);
915 break;
916 };
917
918 /* build any immediate PHP slots under this pci bridge */
919 shpchprm_acpi_build_php_slots(ab, 1);
920}
921
922static struct acpi_bridge * add_p2p_bridge(
923 acpi_handle handle,
924 struct acpi_bridge *pab, /* parent */
925 ulong adr
926 )
927{
928 struct acpi_bridge *ab;
929 struct pci_dev *pdev;
930 ulong devnum, funcnum;
931 u8 *path_name = acpi_path_name(handle);
932
933 ab = (struct acpi_bridge *) kmalloc (sizeof(struct acpi_bridge), GFP_KERNEL);
934 if (!ab) {
935 err("acpi_shpchprm: alloc for ab fail\n");
936 return NULL;
937 }
938 memset(ab, 0, sizeof(struct acpi_bridge));
939
940 devnum = (adr >> 16) & 0xffff;
941 funcnum = adr & 0xffff;
942
943 pdev = pci_find_slot(pab->bus, PCI_DEVFN(devnum, funcnum));
944 if (!pdev || !pdev->subordinate) {
945 err("acpi_shpchprm:%s is not a P2P Bridge\n", path_name);
946 kfree(ab);
947 return NULL;
948 }
949
950 ab->handle = handle;
951 ab->seg = pab->seg;
952 ab->pbus = pab->bus; /* or pdev->bus->number */
953 ab->pdevice = devnum; /* or PCI_SLOT(pdev->devfn) */
954 ab->pfunction = funcnum; /* or PCI_FUNC(pdev->devfn) */
955 ab->bus = pdev->subordinate->number;
956 ab->scanned = 0;
957 ab->type = BRIDGE_TYPE_P2P;
958
959 dbg("acpi_shpchprm: P2P(%x-%x) on pci=b:d:f(%x:%x:%x) acpi=b:d:f(%x:%x:%x) [%s]\n",
960 pab->bus, ab->bus, pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
961 pab->bus, (u32)devnum, (u32)funcnum, path_name);
962
963 build_a_bridge(pab, ab);
964
965 return ab;
966}
967
968static acpi_status scan_p2p_bridge(
969 acpi_handle handle,
970 u32 Level,
971 void *context,
972 void **retval
973 )
974{
975 struct acpi_bridge *pab = (struct acpi_bridge *)context;
976 struct acpi_bridge *ab;
977 acpi_status status;
978 ulong adr = 0;
979 u8 *path_name = acpi_path_name(handle);
980 ulong devnum, funcnum;
981 struct pci_dev *pdev;
982
983 /* get device, function */
984 status = acpi_evaluate_integer(handle, METHOD_NAME__ADR, NULL, &adr);
985 if (ACPI_FAILURE(status)) {
986 if (status != AE_NOT_FOUND)
987 err("acpi_shpchprm:%s _ADR fail=0x%x\n", path_name, status);
988 return AE_OK;
989 }
990
991 devnum = (adr >> 16) & 0xffff;
992 funcnum = adr & 0xffff;
993
994 pdev = pci_find_slot(pab->bus, PCI_DEVFN(devnum, funcnum));
995 if (!pdev)
996 return AE_OK;
997 if (!pdev->subordinate)
998 return AE_OK;
999
1000 ab = add_p2p_bridge(handle, pab, adr);
1001 if (ab) {
1002 status = acpi_walk_namespace ( ACPI_TYPE_DEVICE,
1003 handle,
1004 (u32)1,
1005 scan_p2p_bridge,
1006 ab,
1007 NULL);
1008 if (ACPI_FAILURE(status))
1009 dbg("acpi_shpchprm:%s find_p2p fail=0x%x\n", path_name, status);
1010 }
1011
1012 return AE_OK;
1013}
1014
1015static struct acpi_bridge * add_host_bridge(
1016 acpi_handle handle,
1017 ulong segnum,
1018 ulong busnum
1019 )
1020{
1021 ulong adr = 0;
1022 acpi_status status;
1023 struct acpi_bridge *ab;
1024 u8 *path_name = acpi_path_name(handle);
1025
1026 /* get device, function: host br adr is always 0000 though. */
1027 status = acpi_evaluate_integer(handle, METHOD_NAME__ADR, NULL, &adr);
1028 if (ACPI_FAILURE(status)) {
1029 err("acpi_shpchprm:%s _ADR fail=0x%x\n", path_name, status);
1030 return NULL;
1031 }
1032 dbg("acpi_shpchprm: ROOT PCI seg(0x%x)bus(0x%x)dev(0x%x)func(0x%x) [%s]\n", (u32)segnum, (u32)busnum,
1033 (u32)(adr >> 16) & 0xffff, (u32)adr & 0xffff, path_name);
1034
1035 ab = (struct acpi_bridge *) kmalloc (sizeof(struct acpi_bridge), GFP_KERNEL);
1036 if (!ab) {
1037 err("acpi_shpchprm: alloc for ab fail\n");
1038 return NULL;
1039 }
1040 memset(ab, 0, sizeof(struct acpi_bridge));
1041
1042 ab->handle = handle;
1043 ab->seg = (int)segnum;
1044 ab->bus = ab->pbus = (int)busnum;
1045 ab->pdevice = (int)(adr >> 16) & 0xffff;
1046 ab->pfunction = (int)(adr & 0xffff);
1047 ab->scanned = 0;
1048 ab->type = BRIDGE_TYPE_HOST;
1049
1050 /* get root pci bridge's current resources */
1051 status = acpi_get_crs(ab);
1052 if (ACPI_FAILURE(status)) {
1053 err("acpi_shpchprm:%s evaluate _CRS fail=0x%x\n", path_name, status);
1054 kfree(ab);
1055 return NULL;
1056 }
1057 build_a_bridge(ab, ab);
1058
1059 return ab;
1060}
1061
1062static acpi_status acpi_scan_from_root_pci_callback (
1063 acpi_handle handle,
1064 u32 Level,
1065 void *context,
1066 void **retval
1067 )
1068{
1069 ulong segnum = 0;
1070 ulong busnum = 0;
1071 acpi_status status;
1072 struct acpi_bridge *ab;
1073 u8 *path_name = acpi_path_name(handle);
1074
1075 /* get bus number of this pci root bridge */
1076 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL, &segnum);
1077 if (ACPI_FAILURE(status)) {
1078 if (status != AE_NOT_FOUND) {
1079 err("acpi_shpchprm:%s evaluate _SEG fail=0x%x\n", path_name, status);
1080 return status;
1081 }
1082 segnum = 0;
1083 }
1084
1085 /* get bus number of this pci root bridge */
1086 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN, NULL, &busnum);
1087 if (ACPI_FAILURE(status)) {
1088 err("acpi_shpchprm:%s evaluate _BBN fail=0x%x\n", path_name, status);
1089 return (status);
1090 }
1091
1092 ab = add_host_bridge(handle, segnum, busnum);
1093 if (ab) {
1094 status = acpi_walk_namespace ( ACPI_TYPE_DEVICE,
1095 handle,
1096 1,
1097 scan_p2p_bridge,
1098 ab,
1099 NULL);
1100 if (ACPI_FAILURE(status))
1101 dbg("acpi_shpchprm:%s find_p2p fail=0x%x\n", path_name, status);
1102 }
1103
1104 return AE_OK;
1105}
1106
1107static int shpchprm_acpi_scan_pci (void)
1108{
1109 acpi_status status;
1110
1111 /*
1112 * TBD: traverse LDM device tree with the help of
1113 * unified ACPI augmented for php device population.
1114 */
1115 status = acpi_get_devices ( PCI_ROOT_HID_STRING,
1116 acpi_scan_from_root_pci_callback,
1117 NULL,
1118 NULL );
1119 if (ACPI_FAILURE(status)) {
1120 err("acpi_shpchprm:get_device PCI ROOT HID fail=0x%x\n", status);
1121 return -1;
1122 }
1123
1124 return 0;
1125}
1126
1127int shpchprm_init(enum php_ctlr_type ctlr_type)
1128{
1129 int rc;
1130
1131 if (ctlr_type != PCI)
1132 return -ENODEV;
1133
1134 dbg("shpchprm ACPI init <enter>\n");
1135 acpi_bridges_head = NULL;
1136
1137 /* construct PCI bus:device tree of acpi_handles */
1138 rc = shpchprm_acpi_scan_pci();
1139 if (rc)
1140 return rc;
1141
1142 dbg("shpchprm ACPI init %s\n", (rc)?"fail":"success");
1143 return rc;
1144}
1145
1146static void free_a_slot(struct acpi_php_slot *aps)
1147{
1148 dbg(" free a php func of slot(0x%02x) on PCI b:d:f=0x%02x:%02x:%02x\n", aps->sun, aps->bus, aps->dev, aps->fun);
1149
1150 free_pci_resource (aps->io_head);
1151 free_pci_resource (aps->bus_head);
1152 free_pci_resource (aps->mem_head);
1153 free_pci_resource (aps->p_mem_head);
1154
1155 kfree(aps);
1156}
1157
1158static void free_a_bridge( struct acpi_bridge *ab)
1159{
1160 struct acpi_php_slot *aps, *next;
1161
1162 switch (ab->type) {
1163 case BRIDGE_TYPE_HOST:
1164 dbg("Free ACPI PCI HOST Bridge(%x) [%s] on s:b:d:f(%x:%x:%x:%x)\n",
1165 ab->bus, acpi_path_name(ab->handle), ab->seg, ab->pbus, ab->pdevice, ab->pfunction);
1166 break;
1167 case BRIDGE_TYPE_P2P:
1168 dbg("Free ACPI PCI P2P Bridge(%x-%x) [%s] on s:b:d:f(%x:%x:%x:%x)\n",
1169 ab->pbus, ab->bus, acpi_path_name(ab->handle), ab->seg, ab->pbus, ab->pdevice, ab->pfunction);
1170 break;
1171 };
1172
1173 /* free slots first */
1174 for (aps = ab->slots; aps; aps = next) {
1175 next = aps->next;
1176 free_a_slot(aps);
1177 }
1178
1179 free_pci_resource (ab->io_head);
1180 free_pci_resource (ab->tio_head);
1181 free_pci_resource (ab->bus_head);
1182 free_pci_resource (ab->tbus_head);
1183 free_pci_resource (ab->mem_head);
1184 free_pci_resource (ab->tmem_head);
1185 free_pci_resource (ab->p_mem_head);
1186 free_pci_resource (ab->tp_mem_head);
1187
1188 kfree(ab);
1189}
1190
1191static void shpchprm_free_bridges ( struct acpi_bridge *ab)
1192{
1193 if (!ab)
1194 return;
1195
1196 if (ab->child)
1197 shpchprm_free_bridges (ab->child);
1198
1199 if (ab->next)
1200 shpchprm_free_bridges (ab->next);
1201
1202 free_a_bridge(ab);
1203}
1204
1205void shpchprm_cleanup(void)
1206{
1207 shpchprm_free_bridges (acpi_bridges_head);
1208}
1209
1210static int get_number_of_slots (
1211 struct acpi_bridge *ab,
1212 int selfonly
1213 )
1214{
1215 struct acpi_php_slot *aps;
1216 int prev_slot = -1;
1217 int slot_num = 0;
1218
1219 for ( aps = ab->slots; aps; aps = aps->next)
1220 if (aps->dev != prev_slot) {
1221 prev_slot = aps->dev;
1222 slot_num++;
1223 }
1224
1225 if (ab->child)
1226 slot_num += get_number_of_slots (ab->child, 0);
1227
1228 if (selfonly)
1229 return slot_num;
1230
1231 if (ab->next)
1232 slot_num += get_number_of_slots (ab->next, 0);
1233
1234 return slot_num;
1235}
1236
1237static int print_acpi_resources (struct acpi_bridge *ab)
1238{
1239 struct acpi_php_slot *aps;
1240 int i;
1241
1242 switch (ab->type) {
1243 case BRIDGE_TYPE_HOST:
1244 dbg("PCI HOST Bridge (%x) [%s]\n", ab->bus, acpi_path_name(ab->handle));
1245 break;
1246 case BRIDGE_TYPE_P2P:
1247 dbg("PCI P2P Bridge (%x-%x) [%s]\n", ab->pbus, ab->bus, acpi_path_name(ab->handle));
1248 break;
1249 };
1250
1251 print_pci_resources (ab);
1252
1253 for ( i = -1, aps = ab->slots; aps; aps = aps->next) {
1254 if (aps->dev == i)
1255 continue;
1256 dbg(" Slot sun(%x) s:b:d:f(%02x:%02x:%02x:%02x)\n", aps->sun, aps->seg, aps->bus, aps->dev, aps->fun);
1257 print_slot_resources(aps);
1258 i = aps->dev;
1259 }
1260
1261 if (ab->child)
1262 print_acpi_resources (ab->child);
1263
1264 if (ab->next)
1265 print_acpi_resources (ab->next);
1266
1267 return 0;
1268}
1269
1270int shpchprm_print_pirt(void)
1271{
1272 dbg("SHPCHPRM ACPI Slots\n");
1273 if (acpi_bridges_head)
1274 print_acpi_resources (acpi_bridges_head);
1275 return 0;
1276}
1277
1278static struct acpi_php_slot * get_acpi_slot (
1279 struct acpi_bridge *ab,
1280 u32 sun
1281 )
1282{
1283 struct acpi_php_slot *aps = NULL;
1284
1285 for ( aps = ab->slots; aps; aps = aps->next)
1286 if (aps->sun == sun)
1287 return aps;
1288
1289 if (!aps && ab->child) {
1290 aps = (struct acpi_php_slot *)get_acpi_slot (ab->child, sun);
1291 if (aps)
1292 return aps;
1293 }
1294
1295 if (!aps && ab->next) {
1296 aps = (struct acpi_php_slot *)get_acpi_slot (ab->next, sun);
1297 if (aps)
1298 return aps;
1299 }
1300
1301 return aps;
1302
1303}
1304
1305#if 0
1306static void * shpchprm_get_slot(struct slot *slot)
1307{
1308 struct acpi_bridge *ab = acpi_bridges_head;
1309 struct acpi_php_slot *aps = get_acpi_slot (ab, slot->number);
1310
1311 aps->slot = slot;
1312
1313 dbg("Got acpi slot sun(%x): s:b:d:f(%x:%x:%x:%x)\n", aps->sun, aps->seg, aps->bus, aps->dev, aps->fun);
1314
1315 return (void *)aps;
1316}
1317#endif
1318
1319static void shpchprm_dump_func_res( struct pci_func *fun)
1320{
1321 struct pci_func *func = fun;
1322
1323 if (func->bus_head) {
1324 dbg(": BUS Resources:\n");
1325 print_pci_resource (func->bus_head);
1326 }
1327 if (func->io_head) {
1328 dbg(": IO Resources:\n");
1329 print_pci_resource (func->io_head);
1330 }
1331 if (func->mem_head) {
1332 dbg(": MEM Resources:\n");
1333 print_pci_resource (func->mem_head);
1334 }
1335 if (func->p_mem_head) {
1336 dbg(": PMEM Resources:\n");
1337 print_pci_resource (func->p_mem_head);
1338 }
1339}
1340
1341static void shpchprm_dump_ctrl_res( struct controller *ctlr)
1342{
1343 struct controller *ctrl = ctlr;
1344
1345 if (ctrl->bus_head) {
1346 dbg(": BUS Resources:\n");
1347 print_pci_resource (ctrl->bus_head);
1348 }
1349 if (ctrl->io_head) {
1350 dbg(": IO Resources:\n");
1351 print_pci_resource (ctrl->io_head);
1352 }
1353 if (ctrl->mem_head) {
1354 dbg(": MEM Resources:\n");
1355 print_pci_resource (ctrl->mem_head);
1356 }
1357 if (ctrl->p_mem_head) {
1358 dbg(": PMEM Resources:\n");
1359 print_pci_resource (ctrl->p_mem_head);
1360 }
1361}
1362
1363static int shpchprm_get_used_resources (
1364 struct controller *ctrl,
1365 struct pci_func *func
1366 )
1367{
1368 return shpchp_save_used_resources (ctrl, func, !DISABLE_CARD);
1369}
1370
1371static int configure_existing_function(
1372 struct controller *ctrl,
1373 struct pci_func *func
1374 )
1375{
1376 int rc;
1377
1378 /* see how much resources the func has used. */
1379 rc = shpchprm_get_used_resources (ctrl, func);
1380
1381 if (!rc) {
1382 /* subtract the resources used by the func from ctrl resources */
1383 rc = shpchprm_delete_resources (&ctrl->bus_head, func->bus_head);
1384 rc |= shpchprm_delete_resources (&ctrl->io_head, func->io_head);
1385 rc |= shpchprm_delete_resources (&ctrl->mem_head, func->mem_head);
1386 rc |= shpchprm_delete_resources (&ctrl->p_mem_head, func->p_mem_head);
1387 if (rc)
1388 warn("aCEF: cannot del used resources\n");
1389 } else
1390 err("aCEF: cannot get used resources\n");
1391
1392 return rc;
1393}
1394
1395static int bind_pci_resources_to_slots ( struct controller *ctrl)
1396{
1397 struct pci_func *func, new_func;
1398 int busn = ctrl->slot_bus;
1399 int devn, funn;
1400 u32 vid;
1401
1402 for (devn = 0; devn < 32; devn++) {
1403 for (funn = 0; funn < 8; funn++) {
1404 /*
1405 if (devn == ctrl->device && funn == ctrl->function)
1406 continue;
1407 */
1408 /* find out if this entry is for an occupied slot */
1409 vid = 0xFFFFFFFF;
1410 pci_bus_read_config_dword(ctrl->pci_dev->subordinate, PCI_DEVFN(devn, funn), PCI_VENDOR_ID, &vid);
1411
1412 if (vid != 0xFFFFFFFF) {
1413 func = shpchp_slot_find(busn, devn, funn);
1414 if (!func) {
1415 memset(&new_func, 0, sizeof(struct pci_func));
1416 new_func.bus = busn;
1417 new_func.device = devn;
1418 new_func.function = funn;
1419 new_func.is_a_board = 1;
1420 configure_existing_function(ctrl, &new_func);
1421 shpchprm_dump_func_res(&new_func);
1422 } else {
1423 configure_existing_function(ctrl, func);
1424 shpchprm_dump_func_res(func);
1425 }
1426 dbg("aCCF:existing PCI 0x%x Func ResourceDump\n", ctrl->bus);
1427 }
1428 }
1429 }
1430
1431 return 0;
1432}
1433
1434static int bind_pci_resources(
1435 struct controller *ctrl,
1436 struct acpi_bridge *ab
1437 )
1438{
1439 int status = 0;
1440
1441 if (ab->bus_head) {
1442 dbg("bapr: BUS Resources add on PCI 0x%x\n", ab->bus);
1443 status = shpchprm_add_resources (&ctrl->bus_head, ab->bus_head);
1444 if (shpchprm_delete_resources (&ab->bus_head, ctrl->bus_head))
1445 warn("bapr: cannot sub BUS Resource on PCI 0x%x\n", ab->bus);
1446 if (status) {
1447 err("bapr: BUS Resource add on PCI 0x%x: fail=0x%x\n", ab->bus, status);
1448 return status;
1449 }
1450 } else
1451 info("bapr: No BUS Resource on PCI 0x%x.\n", ab->bus);
1452
1453 if (ab->io_head) {
1454 dbg("bapr: IO Resources add on PCI 0x%x\n", ab->bus);
1455 status = shpchprm_add_resources (&ctrl->io_head, ab->io_head);
1456 if (shpchprm_delete_resources (&ab->io_head, ctrl->io_head))
1457 warn("bapr: cannot sub IO Resource on PCI 0x%x\n", ab->bus);
1458 if (status) {
1459 err("bapr: IO Resource add on PCI 0x%x: fail=0x%x\n", ab->bus, status);
1460 return status;
1461 }
1462 } else
1463 info("bapr: No IO Resource on PCI 0x%x.\n", ab->bus);
1464
1465 if (ab->mem_head) {
1466 dbg("bapr: MEM Resources add on PCI 0x%x\n", ab->bus);
1467 status = shpchprm_add_resources (&ctrl->mem_head, ab->mem_head);
1468 if (shpchprm_delete_resources (&ab->mem_head, ctrl->mem_head))
1469 warn("bapr: cannot sub MEM Resource on PCI 0x%x\n", ab->bus);
1470 if (status) {
1471 err("bapr: MEM Resource add on PCI 0x%x: fail=0x%x\n", ab->bus, status);
1472 return status;
1473 }
1474 } else
1475 info("bapr: No MEM Resource on PCI 0x%x.\n", ab->bus);
1476
1477 if (ab->p_mem_head) {
1478 dbg("bapr: PMEM Resources add on PCI 0x%x\n", ab->bus);
1479 status = shpchprm_add_resources (&ctrl->p_mem_head, ab->p_mem_head);
1480 if (shpchprm_delete_resources (&ab->p_mem_head, ctrl->p_mem_head))
1481 warn("bapr: cannot sub PMEM Resource on PCI 0x%x\n", ab->bus);
1482 if (status) {
1483 err("bapr: PMEM Resource add on PCI 0x%x: fail=0x%x\n", ab->bus, status);
1484 return status;
1485 }
1486 } else
1487 info("bapr: No PMEM Resource on PCI 0x%x.\n", ab->bus);
1488
1489 return status;
1490}
1491
1492static int no_pci_resources( struct acpi_bridge *ab)
1493{
1494 return !(ab->p_mem_head || ab->mem_head || ab->io_head || ab->bus_head);
1495}
1496
1497static int find_pci_bridge_resources (
1498 struct controller *ctrl,
1499 struct acpi_bridge *ab
1500 )
1501{
1502 int rc = 0;
1503 struct pci_func func;
1504
1505 memset(&func, 0, sizeof(struct pci_func));
1506
1507 func.bus = ab->pbus;
1508 func.device = ab->pdevice;
1509 func.function = ab->pfunction;
1510 func.is_a_board = 1;
1511
1512 /* Get used resources for this PCI bridge */
1513 rc = shpchp_save_used_resources (ctrl, &func, !DISABLE_CARD);
1514
1515 ab->io_head = func.io_head;
1516 ab->mem_head = func.mem_head;
1517 ab->p_mem_head = func.p_mem_head;
1518 ab->bus_head = func.bus_head;
1519 if (ab->bus_head)
1520 shpchprm_delete_resource(&ab->bus_head, ctrl->bus, 1);
1521
1522 return rc;
1523}
1524
1525static int get_pci_resources_from_bridge(
1526 struct controller *ctrl,
1527 struct acpi_bridge *ab
1528 )
1529{
1530 int rc = 0;
1531
1532 dbg("grfb: Get Resources for PCI 0x%x from actual PCI bridge 0x%x.\n", ctrl->bus, ab->bus);
1533
1534 rc = find_pci_bridge_resources (ctrl, ab);
1535
1536 shpchp_resource_sort_and_combine(&ab->bus_head);
1537 shpchp_resource_sort_and_combine(&ab->io_head);
1538 shpchp_resource_sort_and_combine(&ab->mem_head);
1539 shpchp_resource_sort_and_combine(&ab->p_mem_head);
1540
1541 shpchprm_add_resources (&ab->tbus_head, ab->bus_head);
1542 shpchprm_add_resources (&ab->tio_head, ab->io_head);
1543 shpchprm_add_resources (&ab->tmem_head, ab->mem_head);
1544 shpchprm_add_resources (&ab->tp_mem_head, ab->p_mem_head);
1545
1546 return rc;
1547}
1548
1549static int get_pci_resources(
1550 struct controller *ctrl,
1551 struct acpi_bridge *ab
1552 )
1553{
1554 int rc = 0;
1555
1556 if (no_pci_resources(ab)) {
1557 dbg("spbr:PCI 0x%x has no resources. Get parent resources.\n", ab->bus);
1558 rc = get_pci_resources_from_bridge(ctrl, ab);
1559 }
1560
1561 return rc;
1562} 139}
1563 140
1564int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum) 141int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
@@ -1570,144 +147,40 @@ int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busn
1570 return 0; 147 return 0;
1571} 148}
1572 149
1573/* 150void get_hp_hw_control_from_firmware(struct pci_dev *dev)
1574 * Get resources for this ctrl.
1575 * 1. get total resources from ACPI _CRS or bridge (this ctrl)
1576 * 2. find used resources of existing adapters
1577 * 3. subtract used resources from total resources
1578 */
1579int shpchprm_find_available_resources( struct controller *ctrl)
1580{ 151{
1581 int rc = 0; 152 /*
1582 struct acpi_bridge *ab; 153 * OSHP is an optional ACPI firmware control method. If present,
1583 154 * we need to run it to inform BIOS that we will control SHPC
1584 ab = find_acpi_bridge_by_bus(acpi_bridges_head, ctrl->seg, ctrl->pci_dev->subordinate->number); 155 * hardware from now on.
1585 if (!ab) { 156 */
1586 err("pfar:cannot locate acpi bridge of PCI 0x%x.\n", ctrl->pci_dev->subordinate->number); 157 acpi_handle handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1587 return -1; 158 if (!handle)
1588 } 159 return;
1589 if (no_pci_resources(ab)) { 160 acpi_run_oshp(handle);
1590 rc = get_pci_resources(ctrl, ab);
1591 if (rc) {
1592 err("pfar:cannot get pci resources of PCI 0x%x.\n",ctrl->pci_dev->subordinate->number);
1593 return -1;
1594 }
1595 }
1596
1597 rc = bind_pci_resources(ctrl, ab);
1598 dbg("pfar:pre-Bind PCI 0x%x Ctrl Resource Dump\n", ctrl->pci_dev->subordinate->number);
1599 shpchprm_dump_ctrl_res(ctrl);
1600
1601 bind_pci_resources_to_slots (ctrl);
1602
1603 dbg("pfar:post-Bind PCI 0x%x Ctrl Resource Dump\n", ctrl->pci_dev->subordinate->number);
1604 shpchprm_dump_ctrl_res(ctrl);
1605
1606 return rc;
1607}
1608
1609int shpchprm_set_hpp(
1610 struct controller *ctrl,
1611 struct pci_func *func,
1612 u8 card_type
1613 )
1614{
1615 struct acpi_bridge *ab;
1616 struct pci_bus lpci_bus, *pci_bus;
1617 int rc = 0;
1618 unsigned int devfn;
1619 u8 cls= 0x08; /* default cache line size */
1620 u8 lt = 0x40; /* default latency timer */
1621 u8 ep = 0;
1622 u8 es = 0;
1623
1624 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
1625 pci_bus = &lpci_bus;
1626 pci_bus->number = func->bus;
1627 devfn = PCI_DEVFN(func->device, func->function);
1628
1629 ab = find_acpi_bridge_by_bus(acpi_bridges_head, ctrl->seg, ctrl->slot_bus);
1630
1631 if (ab) {
1632 if (ab->_hpp) {
1633 lt = (u8)ab->_hpp->latency_timer;
1634 cls = (u8)ab->_hpp->cache_line_size;
1635 ep = (u8)ab->_hpp->enable_perr;
1636 es = (u8)ab->_hpp->enable_serr;
1637 } else
1638 dbg("_hpp: no _hpp for B/D/F=%#x/%#x/%#x. use default value\n", func->bus, func->device, func->function);
1639 } else
1640 dbg("_hpp: no acpi bridge for B/D/F = %#x/%#x/%#x. use default value\n", func->bus, func->device, func->function);
1641
1642
1643 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
1644 /* set subordinate Latency Timer */
1645 rc |= pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, lt);
1646 }
1647
1648 /* set base Latency Timer */
1649 rc |= pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, lt);
1650 dbg(" set latency timer =0x%02x: %x\n", lt, rc);
1651
1652 rc |= pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, cls);
1653 dbg(" set cache_line_size=0x%02x: %x\n", cls, rc);
1654
1655 return rc;
1656} 161}
1657 162
1658void shpchprm_enable_card( 163void get_hp_params_from_firmware(struct pci_dev *dev,
1659 struct controller *ctrl, 164 struct hotplug_params *hpp)
1660 struct pci_func *func,
1661 u8 card_type)
1662{ 165{
1663 u16 command, cmd, bcommand, bcmd; 166 acpi_status status = AE_NOT_FOUND;
1664 struct pci_bus lpci_bus, *pci_bus; 167 struct pci_dev *pdev = dev;
1665 struct acpi_bridge *ab;
1666 unsigned int devfn;
1667 int rc;
1668
1669 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
1670 pci_bus = &lpci_bus;
1671 pci_bus->number = func->bus;
1672 devfn = PCI_DEVFN(func->device, func->function);
1673
1674 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
1675
1676 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
1677 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
1678 }
1679 168
1680 cmd = command = command | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE 169 /*
1681 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; 170 * _HPP settings apply to all child buses, until another _HPP is
1682 bcmd = bcommand = bcommand | PCI_BRIDGE_CTL_NO_ISA; 171 * encountered. If we don't find an _HPP for the input pci dev,
1683 172 * look for it in the parent device scope since that would apply to
1684 ab = find_acpi_bridge_by_bus(acpi_bridges_head, ctrl->seg, ctrl->slot_bus); 173 * this pci dev. If we don't find any _HPP, use hardcoded defaults
1685 if (ab) { 174 */
1686 if (ab->_hpp) { 175 while (pdev && (ACPI_FAILURE(status))) {
1687 if (ab->_hpp->enable_perr) { 176 acpi_handle handle = DEVICE_ACPI_HANDLE(&(pdev->dev));
1688 command |= PCI_COMMAND_PARITY; 177 if (!handle)
1689 bcommand |= PCI_BRIDGE_CTL_PARITY; 178 break;
1690 } else { 179 status = acpi_run_hpp(handle, hpp);
1691 command &= ~PCI_COMMAND_PARITY; 180 if (!(pdev->bus->parent))
1692 bcommand &= ~PCI_BRIDGE_CTL_PARITY; 181 break;
1693 } 182 /* Check if a parent object supports _HPP */
1694 if (ab->_hpp->enable_serr) { 183 pdev = pdev->bus->parent->self;
1695 command |= PCI_COMMAND_SERR;
1696 bcommand |= PCI_BRIDGE_CTL_SERR;
1697 } else {
1698 command &= ~PCI_COMMAND_SERR;
1699 bcommand &= ~PCI_BRIDGE_CTL_SERR;
1700 }
1701 } else
1702 dbg("no _hpp for B/D/F = %#x/%#x/%#x.\n", func->bus, func->device, func->function);
1703 } else
1704 dbg("no acpi bridge for B/D/F = %#x/%#x/%#x.\n", func->bus, func->device, func->function);
1705
1706 if (command != cmd) {
1707 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
1708 }
1709 if ((card_type == PCI_HEADER_TYPE_BRIDGE) && (bcommand != bcmd)) {
1710 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
1711 } 184 }
1712} 185}
1713 186
diff --git a/drivers/pci/hotplug/shpchprm_legacy.c b/drivers/pci/hotplug/shpchprm_legacy.c
index ba6c549c9b9d..ed6c1254bf6f 100644
--- a/drivers/pci/hotplug/shpchprm_legacy.c
+++ b/drivers/pci/hotplug/shpchprm_legacy.c
@@ -27,33 +27,11 @@
27 * 27 *
28 */ 28 */
29 29
30#include <linux/config.h>
31#include <linux/module.h> 30#include <linux/module.h>
32#include <linux/kernel.h> 31#include <linux/kernel.h>
33#include <linux/types.h> 32#include <linux/types.h>
34#include <linux/pci.h> 33#include <linux/pci.h>
35#include <linux/init.h>
36#include <asm/uaccess.h>
37#ifdef CONFIG_IA64
38#include <asm/iosapic.h>
39#endif
40#include "shpchp.h" 34#include "shpchp.h"
41#include "shpchprm.h"
42#include "shpchprm_legacy.h"
43
44static void __iomem *shpchp_rom_start;
45static u16 unused_IRQ;
46
47void shpchprm_cleanup(void)
48{
49 if (shpchp_rom_start)
50 iounmap(shpchp_rom_start);
51}
52
53int shpchprm_print_pirt(void)
54{
55 return 0;
56}
57 35
58int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum) 36int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
59{ 37{
@@ -63,377 +41,14 @@ int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busn
63 return 0; 41 return 0;
64} 42}
65 43
66/* Find the Hot Plug Resource Table in the specified region of memory */ 44void get_hp_params_from_firmware(struct pci_dev *dev,
67static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iomem *end) 45 struct hotplug_params *hpp)
68{ 46{
69 void __iomem *fp; 47 return;
70 void __iomem *endp;
71 u8 temp1, temp2, temp3, temp4;
72 int status = 0;
73
74 endp = (end - sizeof(struct hrt) + 1);
75
76 for (fp = begin; fp <= endp; fp += 16) {
77 temp1 = readb(fp + SIG0);
78 temp2 = readb(fp + SIG1);
79 temp3 = readb(fp + SIG2);
80 temp4 = readb(fp + SIG3);
81 if (temp1 == '$' && temp2 == 'H' && temp3 == 'R' && temp4 == 'T') {
82 status = 1;
83 break;
84 }
85 }
86
87 if (!status)
88 fp = NULL;
89
90 dbg("Discovered Hotplug Resource Table at %p\n", fp);
91 return fp;
92} 48}
93 49
94/* 50void get_hp_hw_control_from_firmware(struct pci_dev *dev)
95 * shpchprm_find_available_resources
96 *
97 * Finds available memory, IO, and IRQ resources for programming
98 * devices which may be added to the system
99 * this function is for hot plug ADD!
100 *
101 * returns 0 if success
102 */
103int shpchprm_find_available_resources(struct controller *ctrl)
104{ 51{
105 u8 populated_slot; 52 return;
106 u8 bridged_slot;
107 void __iomem *one_slot;
108 struct pci_func *func = NULL;
109 int i = 10, index = 0;
110 u32 temp_dword, rc;
111 ulong temp_ulong;
112 struct pci_resource *mem_node;
113 struct pci_resource *p_mem_node;
114 struct pci_resource *io_node;
115 struct pci_resource *bus_node;
116 void __iomem *rom_resource_table;
117 struct pci_bus lpci_bus, *pci_bus;
118 u8 cfgspc_irq, temp;
119
120 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
121 pci_bus = &lpci_bus;
122 rom_resource_table = detect_HRT_floating_pointer(shpchp_rom_start, shpchp_rom_start + 0xffff);
123 dbg("rom_resource_table = %p\n", rom_resource_table);
124 if (rom_resource_table == NULL)
125 return -ENODEV;
126
127 /* Sum all resources and setup resource maps */
128 unused_IRQ = readl(rom_resource_table + UNUSED_IRQ);
129 dbg("unused_IRQ = %x\n", unused_IRQ);
130
131 temp = 0;
132 while (unused_IRQ) {
133 if (unused_IRQ & 1) {
134 shpchp_disk_irq = temp;
135 break;
136 }
137 unused_IRQ = unused_IRQ >> 1;
138 temp++;
139 }
140
141 dbg("shpchp_disk_irq= %d\n", shpchp_disk_irq);
142 unused_IRQ = unused_IRQ >> 1;
143 temp++;
144
145 while (unused_IRQ) {
146 if (unused_IRQ & 1) {
147 shpchp_nic_irq = temp;
148 break;
149 }
150 unused_IRQ = unused_IRQ >> 1;
151 temp++;
152 }
153
154 dbg("shpchp_nic_irq= %d\n", shpchp_nic_irq);
155 unused_IRQ = readl(rom_resource_table + PCIIRQ);
156
157 temp = 0;
158
159 pci_read_config_byte(ctrl->pci_dev, PCI_INTERRUPT_LINE, &cfgspc_irq);
160
161 if (!shpchp_nic_irq) {
162 shpchp_nic_irq = cfgspc_irq;
163 }
164
165 if (!shpchp_disk_irq) {
166 shpchp_disk_irq = cfgspc_irq;
167 }
168
169 dbg("shpchp_disk_irq, shpchp_nic_irq= %d, %d\n", shpchp_disk_irq, shpchp_nic_irq);
170
171 one_slot = rom_resource_table + sizeof(struct hrt);
172
173 i = readb(rom_resource_table + NUMBER_OF_ENTRIES);
174 dbg("number_of_entries = %d\n", i);
175
176 if (!readb(one_slot + SECONDARY_BUS))
177 return (1);
178
179 dbg("dev|IO base|length|MEMbase|length|PM base|length|PB SB MB\n");
180
181 while (i && readb(one_slot + SECONDARY_BUS)) {
182 u8 dev_func = readb(one_slot + DEV_FUNC);
183 u8 primary_bus = readb(one_slot + PRIMARY_BUS);
184 u8 secondary_bus = readb(one_slot + SECONDARY_BUS);
185 u8 max_bus = readb(one_slot + MAX_BUS);
186 u16 io_base = readw(one_slot + IO_BASE);
187 u16 io_length = readw(one_slot + IO_LENGTH);
188 u16 mem_base = readw(one_slot + MEM_BASE);
189 u16 mem_length = readw(one_slot + MEM_LENGTH);
190 u16 pre_mem_base = readw(one_slot + PRE_MEM_BASE);
191 u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH);
192
193 dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n",
194 dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
195 primary_bus, secondary_bus, max_bus);
196
197 /* If this entry isn't for our controller's bus, ignore it */
198 if (primary_bus != ctrl->slot_bus) {
199 i--;
200 one_slot += sizeof(struct slot_rt);
201 continue;
202 }
203 /* find out if this entry is for an occupied slot */
204 temp_dword = 0xFFFFFFFF;
205 pci_bus->number = primary_bus;
206 pci_bus_read_config_dword(pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword);
207
208 dbg("temp_D_word = %x\n", temp_dword);
209
210 if (temp_dword != 0xFFFFFFFF) {
211 index = 0;
212 func = shpchp_slot_find(primary_bus, dev_func >> 3, 0);
213
214 while (func && (func->function != (dev_func & 0x07))) {
215 dbg("func = %p b:d:f(%x:%x:%x)\n", func, primary_bus, dev_func >> 3, index);
216 func = shpchp_slot_find(primary_bus, dev_func >> 3, index++);
217 }
218
219 /* If we can't find a match, skip this table entry */
220 if (!func) {
221 i--;
222 one_slot += sizeof(struct slot_rt);
223 continue;
224 }
225 /* this may not work and shouldn't be used */
226 if (secondary_bus != primary_bus)
227 bridged_slot = 1;
228 else
229 bridged_slot = 0;
230
231 populated_slot = 1;
232 } else {
233 populated_slot = 0;
234 bridged_slot = 0;
235 }
236 dbg("slot populated =%s \n", populated_slot?"yes":"no");
237
238 /* If we've got a valid IO base, use it */
239
240 temp_ulong = io_base + io_length;
241
242 if ((io_base) && (temp_ulong <= 0x10000)) {
243 io_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
244 if (!io_node)
245 return -ENOMEM;
246
247 io_node->base = (ulong)io_base;
248 io_node->length = (ulong)io_length;
249 dbg("found io_node(base, length) = %x, %x\n", io_node->base, io_node->length);
250
251 if (!populated_slot) {
252 io_node->next = ctrl->io_head;
253 ctrl->io_head = io_node;
254 } else {
255 io_node->next = func->io_head;
256 func->io_head = io_node;
257 }
258 }
259
260 /* If we've got a valid memory base, use it */
261 temp_ulong = mem_base + mem_length;
262 if ((mem_base) && (temp_ulong <= 0x10000)) {
263 mem_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
264 if (!mem_node)
265 return -ENOMEM;
266
267 mem_node->base = (ulong)mem_base << 16;
268 mem_node->length = (ulong)(mem_length << 16);
269 dbg("found mem_node(base, length) = %x, %x\n", mem_node->base, mem_node->length);
270
271 if (!populated_slot) {
272 mem_node->next = ctrl->mem_head;
273 ctrl->mem_head = mem_node;
274 } else {
275 mem_node->next = func->mem_head;
276 func->mem_head = mem_node;
277 }
278 }
279
280 /*
281 * If we've got a valid prefetchable memory base, and
282 * the base + length isn't greater than 0xFFFF
283 */
284 temp_ulong = pre_mem_base + pre_mem_length;
285 if ((pre_mem_base) && (temp_ulong <= 0x10000)) {
286 p_mem_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
287 if (!p_mem_node)
288 return -ENOMEM;
289
290 p_mem_node->base = (ulong)pre_mem_base << 16;
291 p_mem_node->length = (ulong)pre_mem_length << 16;
292 dbg("found p_mem_node(base, length) = %x, %x\n", p_mem_node->base, p_mem_node->length);
293
294 if (!populated_slot) {
295 p_mem_node->next = ctrl->p_mem_head;
296 ctrl->p_mem_head = p_mem_node;
297 } else {
298 p_mem_node->next = func->p_mem_head;
299 func->p_mem_head = p_mem_node;
300 }
301 }
302
303 /*
304 * If we've got a valid bus number, use it
305 * The second condition is to ignore bus numbers on
306 * populated slots that don't have PCI-PCI bridges
307 */
308 if (secondary_bus && (secondary_bus != primary_bus)) {
309 bus_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
310 if (!bus_node)
311 return -ENOMEM;
312
313 bus_node->base = (ulong)secondary_bus;
314 bus_node->length = (ulong)(max_bus - secondary_bus + 1);
315 dbg("found bus_node(base, length) = %x, %x\n", bus_node->base, bus_node->length);
316
317 if (!populated_slot) {
318 bus_node->next = ctrl->bus_head;
319 ctrl->bus_head = bus_node;
320 } else {
321 bus_node->next = func->bus_head;
322 func->bus_head = bus_node;
323 }
324 }
325
326 i--;
327 one_slot += sizeof(struct slot_rt);
328 }
329
330 /* If all of the following fail, we don't have any resources for hot plug add */
331 rc = 1;
332 rc &= shpchp_resource_sort_and_combine(&(ctrl->mem_head));
333 rc &= shpchp_resource_sort_and_combine(&(ctrl->p_mem_head));
334 rc &= shpchp_resource_sort_and_combine(&(ctrl->io_head));
335 rc &= shpchp_resource_sort_and_combine(&(ctrl->bus_head));
336
337 return (rc);
338} 53}
339 54
340int shpchprm_set_hpp(
341 struct controller *ctrl,
342 struct pci_func *func,
343 u8 card_type)
344{
345 u32 rc;
346 u8 temp_byte;
347 struct pci_bus lpci_bus, *pci_bus;
348 unsigned int devfn;
349 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
350 pci_bus = &lpci_bus;
351 pci_bus->number = func->bus;
352 devfn = PCI_DEVFN(func->device, func->function);
353
354 temp_byte = 0x40; /* hard coded value for LT */
355 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
356 /* set subordinate Latency Timer */
357 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
358 if (rc) {
359 dbg("%s: set secondary LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus,
360 func->device, func->function);
361 return rc;
362 }
363 }
364
365 /* set base Latency Timer */
366 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
367 if (rc) {
368 dbg("%s: set LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
369 return rc;
370 }
371
372 /* set Cache Line size */
373 temp_byte = 0x08; /* hard coded value for CLS */
374 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
375 if (rc) {
376 dbg("%s: set CLS error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
377 }
378
379 /* set enable_perr */
380 /* set enable_serr */
381
382 return rc;
383}
384
385void shpchprm_enable_card(
386 struct controller *ctrl,
387 struct pci_func *func,
388 u8 card_type)
389{
390 u16 command, bcommand;
391 struct pci_bus lpci_bus, *pci_bus;
392 unsigned int devfn;
393 int rc;
394
395 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
396 pci_bus = &lpci_bus;
397 pci_bus->number = func->bus;
398 devfn = PCI_DEVFN(func->device, func->function);
399
400 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
401 command |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR
402 | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
403 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
404 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
405
406 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
407 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
408 bcommand |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR
409 | PCI_BRIDGE_CTL_NO_ISA;
410 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
411 }
412}
413
414static int legacy_shpchprm_init_pci(void)
415{
416 shpchp_rom_start = ioremap(ROM_PHY_ADDR, ROM_PHY_LEN);
417 if (!shpchp_rom_start) {
418 err("Could not ioremap memory region for ROM\n");
419 return -EIO;
420 }
421
422 return 0;
423}
424
425int shpchprm_init(enum php_ctlr_type ctrl_type)
426{
427 int retval;
428
429 switch (ctrl_type) {
430 case PCI:
431 retval = legacy_shpchprm_init_pci();
432 break;
433 default:
434 retval = -ENODEV;
435 break;
436 }
437
438 return retval;
439}
diff --git a/drivers/pci/hotplug/shpchprm_legacy.h b/drivers/pci/hotplug/shpchprm_legacy.h
deleted file mode 100644
index 21bda74ddfa5..000000000000
--- a/drivers/pci/hotplug/shpchprm_legacy.h
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * SHPCHPRM Legacy: PHP Resource Manager for Non-ACPI/Legacy platform using HRT
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
27 *
28 */
29
30#ifndef _SHPCHPRM_LEGACY_H_
31#define _SHPCHPRM_LEGACY_H_
32
33#define ROM_PHY_ADDR 0x0F0000
34#define ROM_PHY_LEN 0x00FFFF
35
36struct slot_rt {
37 u8 dev_func;
38 u8 primary_bus;
39 u8 secondary_bus;
40 u8 max_bus;
41 u16 io_base;
42 u16 io_length;
43 u16 mem_base;
44 u16 mem_length;
45 u16 pre_mem_base;
46 u16 pre_mem_length;
47} __attribute__ ((packed));
48
49/* offsets to the hotplug slot resource table registers based on the above structure layout */
50enum slot_rt_offsets {
51 DEV_FUNC = offsetof(struct slot_rt, dev_func),
52 PRIMARY_BUS = offsetof(struct slot_rt, primary_bus),
53 SECONDARY_BUS = offsetof(struct slot_rt, secondary_bus),
54 MAX_BUS = offsetof(struct slot_rt, max_bus),
55 IO_BASE = offsetof(struct slot_rt, io_base),
56 IO_LENGTH = offsetof(struct slot_rt, io_length),
57 MEM_BASE = offsetof(struct slot_rt, mem_base),
58 MEM_LENGTH = offsetof(struct slot_rt, mem_length),
59 PRE_MEM_BASE = offsetof(struct slot_rt, pre_mem_base),
60 PRE_MEM_LENGTH = offsetof(struct slot_rt, pre_mem_length),
61};
62
63struct hrt {
64 char sig0;
65 char sig1;
66 char sig2;
67 char sig3;
68 u16 unused_IRQ;
69 u16 PCIIRQ;
70 u8 number_of_entries;
71 u8 revision;
72 u16 reserved1;
73 u32 reserved2;
74} __attribute__ ((packed));
75
76/* offsets to the hotplug resource table registers based on the above structure layout */
77enum hrt_offsets {
78 SIG0 = offsetof(struct hrt, sig0),
79 SIG1 = offsetof(struct hrt, sig1),
80 SIG2 = offsetof(struct hrt, sig2),
81 SIG3 = offsetof(struct hrt, sig3),
82 UNUSED_IRQ = offsetof(struct hrt, unused_IRQ),
83 PCIIRQ = offsetof(struct hrt, PCIIRQ),
84 NUMBER_OF_ENTRIES = offsetof(struct hrt, number_of_entries),
85 REVISION = offsetof(struct hrt, revision),
86 HRT_RESERVED1 = offsetof(struct hrt, reserved1),
87 HRT_RESERVED2 = offsetof(struct hrt, reserved2),
88};
89
90struct irq_info {
91 u8 bus, devfn; /* bus, device and function */
92 struct {
93 u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
94 u16 bitmap; /* Available IRQs */
95 } __attribute__ ((packed)) irq[4];
96 u8 slot; /* slot number, 0=onboard */
97 u8 rfu;
98} __attribute__ ((packed));
99
100struct irq_routing_table {
101 u32 signature; /* PIRQ_SIGNATURE should be here */
102 u16 version; /* PIRQ_VERSION */
103 u16 size; /* Table size in bytes */
104 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
105 u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
106 u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
107 u32 miniport_data; /* Crap */
108 u8 rfu[11];
109 u8 checksum; /* Modulo 256 checksum must give zero */
110 struct irq_info slots[0];
111} __attribute__ ((packed));
112
113#endif /* _SHPCHPRM_LEGACY_H_ */
diff --git a/drivers/pci/hotplug/shpchprm_nonacpi.c b/drivers/pci/hotplug/shpchprm_nonacpi.c
index 5f75ef7f3df2..d70fe5408417 100644
--- a/drivers/pci/hotplug/shpchprm_nonacpi.c
+++ b/drivers/pci/hotplug/shpchprm_nonacpi.c
@@ -32,24 +32,7 @@
32#include <linux/kernel.h> 32#include <linux/kernel.h>
33#include <linux/types.h> 33#include <linux/types.h>
34#include <linux/pci.h> 34#include <linux/pci.h>
35#include <linux/init.h>
36#include <asm/uaccess.h>
37#ifdef CONFIG_IA64
38#include <asm/iosapic.h>
39#endif
40#include "shpchp.h" 35#include "shpchp.h"
41#include "shpchprm.h"
42#include "shpchprm_nonacpi.h"
43
44void shpchprm_cleanup(void)
45{
46 return;
47}
48
49int shpchprm_print_pirt(void)
50{
51 return 0;
52}
53 36
54int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum) 37int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
55{ 38{
@@ -60,375 +43,13 @@ int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busn
60 return 0; 43 return 0;
61} 44}
62 45
63static void print_pci_resource ( struct pci_resource *aprh) 46void get_hp_params_from_firmware(struct pci_dev *dev,
64{ 47 struct hotplug_params *hpp)
65 struct pci_resource *res;
66
67 for (res = aprh; res; res = res->next)
68 dbg(" base= 0x%x length= 0x%x\n", res->base, res->length);
69}
70
71
72static void phprm_dump_func_res( struct pci_func *fun)
73{
74 struct pci_func *func = fun;
75
76 if (func->bus_head) {
77 dbg(": BUS Resources:\n");
78 print_pci_resource (func->bus_head);
79 }
80 if (func->io_head) {
81 dbg(": IO Resources:\n");
82 print_pci_resource (func->io_head);
83 }
84 if (func->mem_head) {
85 dbg(": MEM Resources:\n");
86 print_pci_resource (func->mem_head);
87 }
88 if (func->p_mem_head) {
89 dbg(": PMEM Resources:\n");
90 print_pci_resource (func->p_mem_head);
91 }
92}
93
94static int phprm_get_used_resources (
95 struct controller *ctrl,
96 struct pci_func *func
97 )
98{
99 return shpchp_save_used_resources (ctrl, func, !DISABLE_CARD);
100}
101
102static int phprm_delete_resource(
103 struct pci_resource **aprh,
104 ulong base,
105 ulong size)
106{
107 struct pci_resource *res;
108 struct pci_resource *prevnode;
109 struct pci_resource *split_node;
110 ulong tbase;
111
112 shpchp_resource_sort_and_combine(aprh);
113
114 for (res = *aprh; res; res = res->next) {
115 if (res->base > base)
116 continue;
117
118 if ((res->base + res->length) < (base + size))
119 continue;
120
121 if (res->base < base) {
122 tbase = base;
123
124 if ((res->length - (tbase - res->base)) < size)
125 continue;
126
127 split_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
128 if (!split_node)
129 return -ENOMEM;
130
131 split_node->base = res->base;
132 split_node->length = tbase - res->base;
133 res->base = tbase;
134 res->length -= split_node->length;
135
136 split_node->next = res->next;
137 res->next = split_node;
138 }
139
140 if (res->length >= size) {
141 split_node = (struct pci_resource*) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
142 if (!split_node)
143 return -ENOMEM;
144
145 split_node->base = res->base + size;
146 split_node->length = res->length - size;
147 res->length = size;
148
149 split_node->next = res->next;
150 res->next = split_node;
151 }
152
153 if (*aprh == res) {
154 *aprh = res->next;
155 } else {
156 prevnode = *aprh;
157 while (prevnode->next != res)
158 prevnode = prevnode->next;
159
160 prevnode->next = res->next;
161 }
162 res->next = NULL;
163 kfree(res);
164 break;
165 }
166
167 return 0;
168}
169
170
171static int phprm_delete_resources(
172 struct pci_resource **aprh,
173 struct pci_resource *this
174 )
175{
176 struct pci_resource *res;
177
178 for (res = this; res; res = res->next)
179 phprm_delete_resource(aprh, res->base, res->length);
180
181 return 0;
182}
183
184
185static int configure_existing_function(
186 struct controller *ctrl,
187 struct pci_func *func
188 )
189{
190 int rc;
191
192 /* see how much resources the func has used. */
193 rc = phprm_get_used_resources (ctrl, func);
194
195 if (!rc) {
196 /* subtract the resources used by the func from ctrl resources */
197 rc = phprm_delete_resources (&ctrl->bus_head, func->bus_head);
198 rc |= phprm_delete_resources (&ctrl->io_head, func->io_head);
199 rc |= phprm_delete_resources (&ctrl->mem_head, func->mem_head);
200 rc |= phprm_delete_resources (&ctrl->p_mem_head, func->p_mem_head);
201 if (rc)
202 warn("aCEF: cannot del used resources\n");
203 } else
204 err("aCEF: cannot get used resources\n");
205
206 return rc;
207}
208
209static int bind_pci_resources_to_slots ( struct controller *ctrl)
210{ 48{
211 struct pci_func *func, new_func; 49 return;
212 int busn = ctrl->slot_bus;
213 int devn, funn;
214 u32 vid;
215
216 for (devn = 0; devn < 32; devn++) {
217 for (funn = 0; funn < 8; funn++) {
218 /*
219 if (devn == ctrl->device && funn == ctrl->function)
220 continue;
221 */
222 /* find out if this entry is for an occupied slot */
223 vid = 0xFFFFFFFF;
224
225 pci_bus_read_config_dword(ctrl->pci_dev->subordinate, PCI_DEVFN(devn, funn), PCI_VENDOR_ID, &vid);
226
227 if (vid != 0xFFFFFFFF) {
228 func = shpchp_slot_find(busn, devn, funn);
229 if (!func) {
230 memset(&new_func, 0, sizeof(struct pci_func));
231 new_func.bus = busn;
232 new_func.device = devn;
233 new_func.function = funn;
234 new_func.is_a_board = 1;
235 configure_existing_function(ctrl, &new_func);
236 phprm_dump_func_res(&new_func);
237 } else {
238 configure_existing_function(ctrl, func);
239 phprm_dump_func_res(func);
240 }
241 dbg("aCCF:existing PCI 0x%x Func ResourceDump\n", ctrl->bus);
242 }
243 }
244 }
245
246 return 0;
247}
248
249static void phprm_dump_ctrl_res( struct controller *ctlr)
250{
251 struct controller *ctrl = ctlr;
252
253 if (ctrl->bus_head) {
254 dbg(": BUS Resources:\n");
255 print_pci_resource (ctrl->bus_head);
256 }
257 if (ctrl->io_head) {
258 dbg(": IO Resources:\n");
259 print_pci_resource (ctrl->io_head);
260 }
261 if (ctrl->mem_head) {
262 dbg(": MEM Resources:\n");
263 print_pci_resource (ctrl->mem_head);
264 }
265 if (ctrl->p_mem_head) {
266 dbg(": PMEM Resources:\n");
267 print_pci_resource (ctrl->p_mem_head);
268 }
269}
270
271/*
272 * phprm_find_available_resources
273 *
274 * Finds available memory, IO, and IRQ resources for programming
275 * devices which may be added to the system
276 * this function is for hot plug ADD!
277 *
278 * returns 0 if success
279 */
280int shpchprm_find_available_resources(struct controller *ctrl)
281{
282 struct pci_func func;
283 u32 rc;
284
285 memset(&func, 0, sizeof(struct pci_func));
286
287 func.bus = ctrl->bus;
288 func.device = ctrl->device;
289 func.function = ctrl->function;
290 func.is_a_board = 1;
291
292 /* Get resources for this PCI bridge */
293 rc = shpchp_save_used_resources (ctrl, &func, !DISABLE_CARD);
294 dbg("%s: shpchp_save_used_resources rc = %d\n", __FUNCTION__, rc);
295
296 if (func.mem_head)
297 func.mem_head->next = ctrl->mem_head;
298 ctrl->mem_head = func.mem_head;
299
300 if (func.p_mem_head)
301 func.p_mem_head->next = ctrl->p_mem_head;
302 ctrl->p_mem_head = func.p_mem_head;
303
304 if (func.io_head)
305 func.io_head->next = ctrl->io_head;
306 ctrl->io_head = func.io_head;
307
308 if(func.bus_head)
309 func.bus_head->next = ctrl->bus_head;
310 ctrl->bus_head = func.bus_head;
311 if (ctrl->bus_head)
312 phprm_delete_resource(&ctrl->bus_head, ctrl->pci_dev->subordinate->number, 1);
313
314 dbg("%s:pre-Bind PCI 0x%x Ctrl Resource Dump\n", __FUNCTION__, ctrl->bus);
315 phprm_dump_ctrl_res(ctrl);
316 bind_pci_resources_to_slots (ctrl);
317
318 dbg("%s:post-Bind PCI 0x%x Ctrl Resource Dump\n", __FUNCTION__, ctrl->bus);
319 phprm_dump_ctrl_res(ctrl);
320
321
322 /* If all of the following fail, we don't have any resources for hot plug add */
323 rc = 1;
324 rc &= shpchp_resource_sort_and_combine(&(ctrl->mem_head));
325 rc &= shpchp_resource_sort_and_combine(&(ctrl->p_mem_head));
326 rc &= shpchp_resource_sort_and_combine(&(ctrl->io_head));
327 rc &= shpchp_resource_sort_and_combine(&(ctrl->bus_head));
328
329 return (rc);
330}
331
332int shpchprm_set_hpp(
333 struct controller *ctrl,
334 struct pci_func *func,
335 u8 card_type)
336{
337 u32 rc;
338 u8 temp_byte;
339 struct pci_bus lpci_bus, *pci_bus;
340 unsigned int devfn;
341 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
342 pci_bus = &lpci_bus;
343 pci_bus->number = func->bus;
344 devfn = PCI_DEVFN(func->device, func->function);
345
346 temp_byte = 0x40; /* hard coded value for LT */
347 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
348 /* set subordinate Latency Timer */
349 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
350
351 if (rc) {
352 dbg("%s: set secondary LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus,
353 func->device, func->function);
354 return rc;
355 }
356 }
357
358 /* set base Latency Timer */
359 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
360
361 if (rc) {
362 dbg("%s: set LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
363 return rc;
364 }
365
366 /* set Cache Line size */
367 temp_byte = 0x08; /* hard coded value for CLS */
368
369 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
370
371 if (rc) {
372 dbg("%s: set CLS error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
373 }
374
375 /* set enable_perr */
376 /* set enable_serr */
377
378 return rc;
379}
380
381void shpchprm_enable_card(
382 struct controller *ctrl,
383 struct pci_func *func,
384 u8 card_type)
385{
386 u16 command, bcommand;
387 struct pci_bus lpci_bus, *pci_bus;
388 unsigned int devfn;
389 int rc;
390
391 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
392 pci_bus = &lpci_bus;
393 pci_bus->number = func->bus;
394 devfn = PCI_DEVFN(func->device, func->function);
395
396 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
397
398 command |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR
399 | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
400 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
401
402 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
403
404 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
405
406 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
407
408 bcommand |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR
409 | PCI_BRIDGE_CTL_NO_ISA;
410
411 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
412 }
413}
414
415static int legacy_shpchprm_init_pci(void)
416{
417 return 0;
418} 50}
419 51
420int shpchprm_init(enum php_ctlr_type ctrl_type) 52void get_hp_hw_control_from_firmware(struct pci_dev *dev)
421{ 53{
422 int retval; 54 return;
423
424 switch (ctrl_type) {
425 case PCI:
426 retval = legacy_shpchprm_init_pci();
427 break;
428 default:
429 retval = -ENODEV;
430 break;
431 }
432
433 return retval;
434} 55}
diff --git a/drivers/pci/hotplug/shpchprm_nonacpi.h b/drivers/pci/hotplug/shpchprm_nonacpi.h
deleted file mode 100644
index cddaaa5ee1b3..000000000000
--- a/drivers/pci/hotplug/shpchprm_nonacpi.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * SHPCHPRM NONACPI: PHP Resource Manager for Non-ACPI/Legacy platform
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
27 *
28 */
29
30#ifndef _SHPCHPRM_NONACPI_H_
31#define _SHPCHPRM_NONACPI_H_
32
33struct irq_info {
34 u8 bus, devfn; /* bus, device and function */
35 struct {
36 u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
37 u16 bitmap; /* Available IRQs */
38 } __attribute__ ((packed)) irq[4];
39 u8 slot; /* slot number, 0=onboard */
40 u8 rfu;
41} __attribute__ ((packed));
42
43struct irq_routing_table {
44 u32 signature; /* PIRQ_SIGNATURE should be here */
45 u16 version; /* PIRQ_VERSION */
46 u16 size; /* Table size in bytes */
47 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
48 u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
49 u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
50 u32 miniport_data; /* Crap */
51 u8 rfu[11];
52 u8 checksum; /* Modulo 256 checksum must give zero */
53 struct irq_info slots[0];
54} __attribute__ ((packed));
55
56#endif /* _SHPCHPRM_NONACPI_H_ */
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index ee8677bda950..a2033552423c 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -575,6 +575,8 @@ static int msi_capability_init(struct pci_dev *dev)
575/** 575/**
576 * msix_capability_init - configure device's MSI-X capability 576 * msix_capability_init - configure device's MSI-X capability
577 * @dev: pointer to the pci_dev data structure of MSI-X device function 577 * @dev: pointer to the pci_dev data structure of MSI-X device function
578 * @entries: pointer to an array of struct msix_entry entries
579 * @nvec: number of @entries
578 * 580 *
579 * Setup the MSI-X capability structure of device function with a 581 * Setup the MSI-X capability structure of device function with a
580 * single MSI-X vector. A return of zero indicates the successful setup of 582 * single MSI-X vector. A return of zero indicates the successful setup of
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 0d0d533894e0..8972e6a3aac0 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -26,7 +26,10 @@ struct pci_dynid {
26#ifdef CONFIG_HOTPLUG 26#ifdef CONFIG_HOTPLUG
27 27
28/** 28/**
29 * store_new_id 29 * store_new_id - add a new PCI device ID to this driver and re-probe devices
30 * @driver: target device driver
31 * @buf: buffer for scanning device ID data
32 * @count: input size
30 * 33 *
31 * Adds a new dynamic pci device ID to this driver, 34 * Adds a new dynamic pci device ID to this driver,
32 * and causes the driver to probe for all devices again. 35 * and causes the driver to probe for all devices again.
@@ -194,8 +197,10 @@ static int pci_call_probe(struct pci_driver *drv, struct pci_dev *dev,
194 197
195/** 198/**
196 * __pci_device_probe() 199 * __pci_device_probe()
200 * @drv: driver to call to check if it wants the PCI device
201 * @pci_dev: PCI device being probed
197 * 202 *
198 * returns 0 on success, else error. 203 * returns 0 on success, else error.
199 * side-effect: pci_dev->driver is set to drv when drv claims pci_dev. 204 * side-effect: pci_dev->driver is set to drv when drv claims pci_dev.
200 */ 205 */
201static int 206static int
@@ -377,6 +382,10 @@ int pci_register_driver(struct pci_driver *drv)
377 * the pci shutdown function, this test can go away. */ 382 * the pci shutdown function, this test can go away. */
378 if (!drv->driver.shutdown) 383 if (!drv->driver.shutdown)
379 drv->driver.shutdown = pci_device_shutdown; 384 drv->driver.shutdown = pci_device_shutdown;
385 else
386 printk(KERN_WARNING "Warning: PCI driver %s has a struct "
387 "device_driver shutdown method, please update!\n",
388 drv->name);
380 drv->driver.owner = drv->owner; 389 drv->driver.owner = drv->owner;
381 drv->driver.kobj.ktype = &pci_driver_kobj_type; 390 drv->driver.kobj.ktype = &pci_driver_kobj_type;
382 391
@@ -436,11 +445,11 @@ pci_dev_driver(const struct pci_dev *dev)
436 445
437/** 446/**
438 * pci_bus_match - Tell if a PCI device structure has a matching PCI device id structure 447 * pci_bus_match - Tell if a PCI device structure has a matching PCI device id structure
439 * @ids: array of PCI device id structures to search in
440 * @dev: the PCI device structure to match against 448 * @dev: the PCI device structure to match against
449 * @drv: the device driver to search for matching PCI device id structures
441 * 450 *
442 * Used by a driver to check whether a PCI device present in the 451 * Used by a driver to check whether a PCI device present in the
443 * system is in its list of supported devices.Returns the matching 452 * system is in its list of supported devices. Returns the matching
444 * pci_device_id structure or %NULL if there is no match. 453 * pci_device_id structure or %NULL if there is no match.
445 */ 454 */
446static int pci_bus_match(struct device *dev, struct device_driver *drv) 455static int pci_bus_match(struct device *dev, struct device_driver *drv)
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 2898830c496f..965a5934623a 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -130,7 +130,7 @@ pci_read_config(struct kobject *kobj, char *buf, loff_t off, size_t count)
130 130
131 if ((off & 1) && size) { 131 if ((off & 1) && size) {
132 u8 val; 132 u8 val;
133 pci_read_config_byte(dev, off, &val); 133 pci_user_read_config_byte(dev, off, &val);
134 data[off - init_off] = val; 134 data[off - init_off] = val;
135 off++; 135 off++;
136 size--; 136 size--;
@@ -138,7 +138,7 @@ pci_read_config(struct kobject *kobj, char *buf, loff_t off, size_t count)
138 138
139 if ((off & 3) && size > 2) { 139 if ((off & 3) && size > 2) {
140 u16 val; 140 u16 val;
141 pci_read_config_word(dev, off, &val); 141 pci_user_read_config_word(dev, off, &val);
142 data[off - init_off] = val & 0xff; 142 data[off - init_off] = val & 0xff;
143 data[off - init_off + 1] = (val >> 8) & 0xff; 143 data[off - init_off + 1] = (val >> 8) & 0xff;
144 off += 2; 144 off += 2;
@@ -147,7 +147,7 @@ pci_read_config(struct kobject *kobj, char *buf, loff_t off, size_t count)
147 147
148 while (size > 3) { 148 while (size > 3) {
149 u32 val; 149 u32 val;
150 pci_read_config_dword(dev, off, &val); 150 pci_user_read_config_dword(dev, off, &val);
151 data[off - init_off] = val & 0xff; 151 data[off - init_off] = val & 0xff;
152 data[off - init_off + 1] = (val >> 8) & 0xff; 152 data[off - init_off + 1] = (val >> 8) & 0xff;
153 data[off - init_off + 2] = (val >> 16) & 0xff; 153 data[off - init_off + 2] = (val >> 16) & 0xff;
@@ -158,7 +158,7 @@ pci_read_config(struct kobject *kobj, char *buf, loff_t off, size_t count)
158 158
159 if (size >= 2) { 159 if (size >= 2) {
160 u16 val; 160 u16 val;
161 pci_read_config_word(dev, off, &val); 161 pci_user_read_config_word(dev, off, &val);
162 data[off - init_off] = val & 0xff; 162 data[off - init_off] = val & 0xff;
163 data[off - init_off + 1] = (val >> 8) & 0xff; 163 data[off - init_off + 1] = (val >> 8) & 0xff;
164 off += 2; 164 off += 2;
@@ -167,7 +167,7 @@ pci_read_config(struct kobject *kobj, char *buf, loff_t off, size_t count)
167 167
168 if (size > 0) { 168 if (size > 0) {
169 u8 val; 169 u8 val;
170 pci_read_config_byte(dev, off, &val); 170 pci_user_read_config_byte(dev, off, &val);
171 data[off - init_off] = val; 171 data[off - init_off] = val;
172 off++; 172 off++;
173 --size; 173 --size;
@@ -192,7 +192,7 @@ pci_write_config(struct kobject *kobj, char *buf, loff_t off, size_t count)
192 } 192 }
193 193
194 if ((off & 1) && size) { 194 if ((off & 1) && size) {
195 pci_write_config_byte(dev, off, data[off - init_off]); 195 pci_user_write_config_byte(dev, off, data[off - init_off]);
196 off++; 196 off++;
197 size--; 197 size--;
198 } 198 }
@@ -200,7 +200,7 @@ pci_write_config(struct kobject *kobj, char *buf, loff_t off, size_t count)
200 if ((off & 3) && size > 2) { 200 if ((off & 3) && size > 2) {
201 u16 val = data[off - init_off]; 201 u16 val = data[off - init_off];
202 val |= (u16) data[off - init_off + 1] << 8; 202 val |= (u16) data[off - init_off + 1] << 8;
203 pci_write_config_word(dev, off, val); 203 pci_user_write_config_word(dev, off, val);
204 off += 2; 204 off += 2;
205 size -= 2; 205 size -= 2;
206 } 206 }
@@ -210,7 +210,7 @@ pci_write_config(struct kobject *kobj, char *buf, loff_t off, size_t count)
210 val |= (u32) data[off - init_off + 1] << 8; 210 val |= (u32) data[off - init_off + 1] << 8;
211 val |= (u32) data[off - init_off + 2] << 16; 211 val |= (u32) data[off - init_off + 2] << 16;
212 val |= (u32) data[off - init_off + 3] << 24; 212 val |= (u32) data[off - init_off + 3] << 24;
213 pci_write_config_dword(dev, off, val); 213 pci_user_write_config_dword(dev, off, val);
214 off += 4; 214 off += 4;
215 size -= 4; 215 size -= 4;
216 } 216 }
@@ -218,13 +218,13 @@ pci_write_config(struct kobject *kobj, char *buf, loff_t off, size_t count)
218 if (size >= 2) { 218 if (size >= 2) {
219 u16 val = data[off - init_off]; 219 u16 val = data[off - init_off];
220 val |= (u16) data[off - init_off + 1] << 8; 220 val |= (u16) data[off - init_off + 1] << 8;
221 pci_write_config_word(dev, off, val); 221 pci_user_write_config_word(dev, off, val);
222 off += 2; 222 off += 2;
223 size -= 2; 223 size -= 2;
224 } 224 }
225 225
226 if (size) { 226 if (size) {
227 pci_write_config_byte(dev, off, data[off - init_off]); 227 pci_user_write_config_byte(dev, off, data[off - init_off]);
228 off++; 228 off++;
229 --size; 229 --size;
230 } 230 }
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 259d247b7551..61b855c99e39 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -252,6 +252,8 @@ pci_restore_bars(struct pci_dev *dev)
252 pci_update_resource(dev, &dev->resource[i], i); 252 pci_update_resource(dev, &dev->resource[i], i);
253} 253}
254 254
255int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
256
255/** 257/**
256 * pci_set_power_state - Set the power state of a PCI device 258 * pci_set_power_state - Set the power state of a PCI device
257 * @dev: PCI device to be suspended 259 * @dev: PCI device to be suspended
@@ -266,7 +268,6 @@ pci_restore_bars(struct pci_dev *dev)
266 * -EIO if device does not support PCI PM. 268 * -EIO if device does not support PCI PM.
267 * 0 if we can successfully change the power state. 269 * 0 if we can successfully change the power state.
268 */ 270 */
269int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
270int 271int
271pci_set_power_state(struct pci_dev *dev, pci_power_t state) 272pci_set_power_state(struct pci_dev *dev, pci_power_t state)
272{ 273{
@@ -314,19 +315,19 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
314 * sets PowerState to 0. 315 * sets PowerState to 0.
315 */ 316 */
316 switch (dev->current_state) { 317 switch (dev->current_state) {
318 case PCI_D0:
319 case PCI_D1:
320 case PCI_D2:
321 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
322 pmcsr |= state;
323 break;
317 case PCI_UNKNOWN: /* Boot-up */ 324 case PCI_UNKNOWN: /* Boot-up */
318 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 325 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
319 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 326 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
320 need_restore = 1; 327 need_restore = 1;
321 /* Fall-through: force to D0 */ 328 /* Fall-through: force to D0 */
322 case PCI_D3hot:
323 case PCI_D3cold:
324 case PCI_POWER_ERROR:
325 pmcsr = 0;
326 break;
327 default: 329 default:
328 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 330 pmcsr = 0;
329 pmcsr |= state;
330 break; 331 break;
331 } 332 }
332 333
@@ -808,8 +809,8 @@ pci_clear_mwi(struct pci_dev *dev)
808 809
809/** 810/**
810 * pci_intx - enables/disables PCI INTx for device dev 811 * pci_intx - enables/disables PCI INTx for device dev
811 * @dev: the PCI device to operate on 812 * @pdev: the PCI device to operate on
812 * @enable: boolean 813 * @enable: boolean: whether to enable or disable PCI INTx
813 * 814 *
814 * Enables/disables PCI INTx for device dev 815 * Enables/disables PCI INTx for device dev
815 */ 816 */
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index d3f3dd42240d..6527b36c9a61 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -15,6 +15,13 @@ extern int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
15extern int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); 15extern int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
16extern int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t state); 16extern int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t state);
17 17
18extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
19extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
20extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
21extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
22extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
23extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
24
18/* PCI /proc functions */ 25/* PCI /proc functions */
19#ifdef CONFIG_PROC_FS 26#ifdef CONFIG_PROC_FS
20extern int pci_proc_attach_device(struct pci_dev *dev); 27extern int pci_proc_attach_device(struct pci_dev *dev);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 005786416bb5..fce2cb2112d8 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -669,6 +669,7 @@ static void pci_release_dev(struct device *dev)
669 669
670/** 670/**
671 * pci_cfg_space_size - get the configuration space size of the PCI device. 671 * pci_cfg_space_size - get the configuration space size of the PCI device.
672 * @dev: PCI device
672 * 673 *
673 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 674 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
674 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 675 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
diff --git a/drivers/pci/proc.c b/drivers/pci/proc.c
index 9613f666c110..9eb465727fce 100644
--- a/drivers/pci/proc.c
+++ b/drivers/pci/proc.c
@@ -80,7 +80,7 @@ proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *pp
80 80
81 if ((pos & 1) && cnt) { 81 if ((pos & 1) && cnt) {
82 unsigned char val; 82 unsigned char val;
83 pci_read_config_byte(dev, pos, &val); 83 pci_user_read_config_byte(dev, pos, &val);
84 __put_user(val, buf); 84 __put_user(val, buf);
85 buf++; 85 buf++;
86 pos++; 86 pos++;
@@ -89,7 +89,7 @@ proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *pp
89 89
90 if ((pos & 3) && cnt > 2) { 90 if ((pos & 3) && cnt > 2) {
91 unsigned short val; 91 unsigned short val;
92 pci_read_config_word(dev, pos, &val); 92 pci_user_read_config_word(dev, pos, &val);
93 __put_user(cpu_to_le16(val), (unsigned short __user *) buf); 93 __put_user(cpu_to_le16(val), (unsigned short __user *) buf);
94 buf += 2; 94 buf += 2;
95 pos += 2; 95 pos += 2;
@@ -98,7 +98,7 @@ proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *pp
98 98
99 while (cnt >= 4) { 99 while (cnt >= 4) {
100 unsigned int val; 100 unsigned int val;
101 pci_read_config_dword(dev, pos, &val); 101 pci_user_read_config_dword(dev, pos, &val);
102 __put_user(cpu_to_le32(val), (unsigned int __user *) buf); 102 __put_user(cpu_to_le32(val), (unsigned int __user *) buf);
103 buf += 4; 103 buf += 4;
104 pos += 4; 104 pos += 4;
@@ -107,7 +107,7 @@ proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *pp
107 107
108 if (cnt >= 2) { 108 if (cnt >= 2) {
109 unsigned short val; 109 unsigned short val;
110 pci_read_config_word(dev, pos, &val); 110 pci_user_read_config_word(dev, pos, &val);
111 __put_user(cpu_to_le16(val), (unsigned short __user *) buf); 111 __put_user(cpu_to_le16(val), (unsigned short __user *) buf);
112 buf += 2; 112 buf += 2;
113 pos += 2; 113 pos += 2;
@@ -116,7 +116,7 @@ proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *pp
116 116
117 if (cnt) { 117 if (cnt) {
118 unsigned char val; 118 unsigned char val;
119 pci_read_config_byte(dev, pos, &val); 119 pci_user_read_config_byte(dev, pos, &val);
120 __put_user(val, buf); 120 __put_user(val, buf);
121 buf++; 121 buf++;
122 pos++; 122 pos++;
@@ -151,7 +151,7 @@ proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, lof
151 if ((pos & 1) && cnt) { 151 if ((pos & 1) && cnt) {
152 unsigned char val; 152 unsigned char val;
153 __get_user(val, buf); 153 __get_user(val, buf);
154 pci_write_config_byte(dev, pos, val); 154 pci_user_write_config_byte(dev, pos, val);
155 buf++; 155 buf++;
156 pos++; 156 pos++;
157 cnt--; 157 cnt--;
@@ -160,7 +160,7 @@ proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, lof
160 if ((pos & 3) && cnt > 2) { 160 if ((pos & 3) && cnt > 2) {
161 unsigned short val; 161 unsigned short val;
162 __get_user(val, (unsigned short __user *) buf); 162 __get_user(val, (unsigned short __user *) buf);
163 pci_write_config_word(dev, pos, le16_to_cpu(val)); 163 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
164 buf += 2; 164 buf += 2;
165 pos += 2; 165 pos += 2;
166 cnt -= 2; 166 cnt -= 2;
@@ -169,7 +169,7 @@ proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, lof
169 while (cnt >= 4) { 169 while (cnt >= 4) {
170 unsigned int val; 170 unsigned int val;
171 __get_user(val, (unsigned int __user *) buf); 171 __get_user(val, (unsigned int __user *) buf);
172 pci_write_config_dword(dev, pos, le32_to_cpu(val)); 172 pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
173 buf += 4; 173 buf += 4;
174 pos += 4; 174 pos += 4;
175 cnt -= 4; 175 cnt -= 4;
@@ -178,7 +178,7 @@ proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, lof
178 if (cnt >= 2) { 178 if (cnt >= 2) {
179 unsigned short val; 179 unsigned short val;
180 __get_user(val, (unsigned short __user *) buf); 180 __get_user(val, (unsigned short __user *) buf);
181 pci_write_config_word(dev, pos, le16_to_cpu(val)); 181 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
182 buf += 2; 182 buf += 2;
183 pos += 2; 183 pos += 2;
184 cnt -= 2; 184 cnt -= 2;
@@ -187,7 +187,7 @@ proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, lof
187 if (cnt) { 187 if (cnt) {
188 unsigned char val; 188 unsigned char val;
189 __get_user(val, buf); 189 __get_user(val, buf);
190 pci_write_config_byte(dev, pos, val); 190 pci_user_write_config_byte(dev, pos, val);
191 buf++; 191 buf++;
192 pos++; 192 pos++;
193 cnt--; 193 cnt--;
@@ -484,10 +484,10 @@ static int show_dev_config(struct seq_file *m, void *v)
484 484
485 drv = pci_dev_driver(dev); 485 drv = pci_dev_driver(dev);
486 486
487 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 487 pci_user_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
488 pci_read_config_byte (dev, PCI_LATENCY_TIMER, &latency); 488 pci_user_read_config_byte (dev, PCI_LATENCY_TIMER, &latency);
489 pci_read_config_byte (dev, PCI_MIN_GNT, &min_gnt); 489 pci_user_read_config_byte (dev, PCI_MIN_GNT, &min_gnt);
490 pci_read_config_byte (dev, PCI_MAX_LAT, &max_lat); 490 pci_user_read_config_byte (dev, PCI_MAX_LAT, &max_lat);
491 seq_printf(m, " Bus %2d, device %3d, function %2d:\n", 491 seq_printf(m, " Bus %2d, device %3d, function %2d:\n",
492 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 492 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
493 seq_printf(m, " Class %04x", class_rev >> 16); 493 seq_printf(m, " Class %04x", class_rev >> 16);
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 7992bc8cc6a4..ee1605906a3e 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -414,6 +414,18 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
414DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); 414DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
415DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); 415DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
416 416
417static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
418{
419 u32 region;
420
421 pci_read_config_dword(dev, 0x40, &region);
422 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
423
424 pci_read_config_dword(dev, 0x48, &region);
425 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
426}
427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
428
417/* 429/*
418 * VIA ACPI: One IO region pointed to by longword at 430 * VIA ACPI: One IO region pointed to by longword at
419 * 0x48 or 0x20 (256 bytes of ACPI registers) 431 * 0x48 or 0x20 (256 bytes of ACPI registers)
@@ -922,6 +934,12 @@ static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
922 case 0x186a: /* M6Ne notebook */ 934 case 0x186a: /* M6Ne notebook */
923 asus_hides_smbus = 1; 935 asus_hides_smbus = 1;
924 } 936 }
937 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
938 switch (dev->subsystem_device) {
939 case 0x1882: /* M6V notebook */
940 asus_hides_smbus = 1;
941 }
942 }
925 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 943 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
926 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 944 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
927 switch(dev->subsystem_device) { 945 switch(dev->subsystem_device) {
@@ -932,6 +950,7 @@ static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
932 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 950 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
933 switch (dev->subsystem_device) { 951 switch (dev->subsystem_device) {
934 case 0x12bc: /* HP D330L */ 952 case 0x12bc: /* HP D330L */
953 case 0x12bd: /* HP D530 */
935 asus_hides_smbus = 1; 954 asus_hides_smbus = 1;
936 } 955 }
937 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) { 956 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
@@ -966,6 +985,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus
966DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 985DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
967DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 986DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
968DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 987DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
988DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
969 989
970static void __init asus_hides_smbus_lpc(struct pci_dev *dev) 990static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
971{ 991{
@@ -990,6 +1010,23 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, as
990DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 1010DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
991DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 1011DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
992 1012
1013static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1014{
1015 u32 val, rcba;
1016 void __iomem *base;
1017
1018 if (likely(!asus_hides_smbus))
1019 return;
1020 pci_read_config_dword(dev, 0xF0, &rcba);
1021 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1022 if (base == NULL) return;
1023 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1024 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1025 iounmap(base);
1026 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1027}
1028DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1029
993/* 1030/*
994 * SiS 96x south bridge: BIOS typically hides SMBus device... 1031 * SiS 96x south bridge: BIOS typically hides SMBus device...
995 */ 1032 */
diff --git a/drivers/pci/syscall.c b/drivers/pci/syscall.c
index c071790cc983..87fafc08cb9d 100644
--- a/drivers/pci/syscall.c
+++ b/drivers/pci/syscall.c
@@ -13,7 +13,7 @@
13#include <linux/smp_lock.h> 13#include <linux/smp_lock.h>
14#include <linux/syscalls.h> 14#include <linux/syscalls.h>
15#include <asm/uaccess.h> 15#include <asm/uaccess.h>
16 16#include "pci.h"
17 17
18asmlinkage long 18asmlinkage long
19sys_pciconfig_read(unsigned long bus, unsigned long dfn, 19sys_pciconfig_read(unsigned long bus, unsigned long dfn,
@@ -38,13 +38,13 @@ sys_pciconfig_read(unsigned long bus, unsigned long dfn,
38 lock_kernel(); 38 lock_kernel();
39 switch (len) { 39 switch (len) {
40 case 1: 40 case 1:
41 cfg_ret = pci_read_config_byte(dev, off, &byte); 41 cfg_ret = pci_user_read_config_byte(dev, off, &byte);
42 break; 42 break;
43 case 2: 43 case 2:
44 cfg_ret = pci_read_config_word(dev, off, &word); 44 cfg_ret = pci_user_read_config_word(dev, off, &word);
45 break; 45 break;
46 case 4: 46 case 4:
47 cfg_ret = pci_read_config_dword(dev, off, &dword); 47 cfg_ret = pci_user_read_config_dword(dev, off, &dword);
48 break; 48 break;
49 default: 49 default:
50 err = -EINVAL; 50 err = -EINVAL;
@@ -112,7 +112,7 @@ sys_pciconfig_write(unsigned long bus, unsigned long dfn,
112 err = get_user(byte, (u8 __user *)buf); 112 err = get_user(byte, (u8 __user *)buf);
113 if (err) 113 if (err)
114 break; 114 break;
115 err = pci_write_config_byte(dev, off, byte); 115 err = pci_user_write_config_byte(dev, off, byte);
116 if (err != PCIBIOS_SUCCESSFUL) 116 if (err != PCIBIOS_SUCCESSFUL)
117 err = -EIO; 117 err = -EIO;
118 break; 118 break;
@@ -121,7 +121,7 @@ sys_pciconfig_write(unsigned long bus, unsigned long dfn,
121 err = get_user(word, (u16 __user *)buf); 121 err = get_user(word, (u16 __user *)buf);
122 if (err) 122 if (err)
123 break; 123 break;
124 err = pci_write_config_word(dev, off, word); 124 err = pci_user_write_config_word(dev, off, word);
125 if (err != PCIBIOS_SUCCESSFUL) 125 if (err != PCIBIOS_SUCCESSFUL)
126 err = -EIO; 126 err = -EIO;
127 break; 127 break;
@@ -130,7 +130,7 @@ sys_pciconfig_write(unsigned long bus, unsigned long dfn,
130 err = get_user(dword, (u32 __user *)buf); 130 err = get_user(dword, (u32 __user *)buf);
131 if (err) 131 if (err)
132 break; 132 break;
133 err = pci_write_config_dword(dev, off, dword); 133 err = pci_user_write_config_dword(dev, off, dword);
134 if (err != PCIBIOS_SUCCESSFUL) 134 if (err != PCIBIOS_SUCCESSFUL)
135 err = -EIO; 135 err = -EIO;
136 break; 136 break;
diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c
index babd48363402..e0039dfae8e5 100644
--- a/drivers/scsi/ipr.c
+++ b/drivers/scsi/ipr.c
@@ -4944,6 +4944,7 @@ static int ipr_reset_restore_cfg_space(struct ipr_cmnd *ipr_cmd)
4944 int rc; 4944 int rc;
4945 4945
4946 ENTER; 4946 ENTER;
4947 pci_unblock_user_cfg_access(ioa_cfg->pdev);
4947 rc = pci_restore_state(ioa_cfg->pdev); 4948 rc = pci_restore_state(ioa_cfg->pdev);
4948 4949
4949 if (rc != PCIBIOS_SUCCESSFUL) { 4950 if (rc != PCIBIOS_SUCCESSFUL) {
@@ -4998,6 +4999,7 @@ static int ipr_reset_start_bist(struct ipr_cmnd *ipr_cmd)
4998 int rc; 4999 int rc;
4999 5000
5000 ENTER; 5001 ENTER;
5002 pci_block_user_cfg_access(ioa_cfg->pdev);
5001 rc = pci_write_config_byte(ioa_cfg->pdev, PCI_BIST, PCI_BIST_START); 5003 rc = pci_write_config_byte(ioa_cfg->pdev, PCI_BIST, PCI_BIST_START);
5002 5004
5003 if (rc != PCIBIOS_SUCCESSFUL) { 5005 if (rc != PCIBIOS_SUCCESSFUL) {
diff --git a/drivers/scsi/megaraid/megaraid_mbox.c b/drivers/scsi/megaraid/megaraid_mbox.c
index d47be8e0ea3a..c9e743ba09ec 100644
--- a/drivers/scsi/megaraid/megaraid_mbox.c
+++ b/drivers/scsi/megaraid/megaraid_mbox.c
@@ -76,7 +76,7 @@ static void megaraid_exit(void);
76 76
77static int megaraid_probe_one(struct pci_dev*, const struct pci_device_id *); 77static int megaraid_probe_one(struct pci_dev*, const struct pci_device_id *);
78static void megaraid_detach_one(struct pci_dev *); 78static void megaraid_detach_one(struct pci_dev *);
79static void megaraid_mbox_shutdown(struct device *); 79static void megaraid_mbox_shutdown(struct pci_dev *);
80 80
81static int megaraid_io_attach(adapter_t *); 81static int megaraid_io_attach(adapter_t *);
82static void megaraid_io_detach(adapter_t *); 82static void megaraid_io_detach(adapter_t *);
@@ -369,9 +369,7 @@ static struct pci_driver megaraid_pci_driver_g = {
369 .id_table = pci_id_table_g, 369 .id_table = pci_id_table_g,
370 .probe = megaraid_probe_one, 370 .probe = megaraid_probe_one,
371 .remove = __devexit_p(megaraid_detach_one), 371 .remove = __devexit_p(megaraid_detach_one),
372 .driver = { 372 .shutdown = megaraid_mbox_shutdown,
373 .shutdown = megaraid_mbox_shutdown,
374 }
375}; 373};
376 374
377 375
@@ -673,9 +671,9 @@ megaraid_detach_one(struct pci_dev *pdev)
673 * Shutdown notification, perform flush cache 671 * Shutdown notification, perform flush cache
674 */ 672 */
675static void 673static void
676megaraid_mbox_shutdown(struct device *device) 674megaraid_mbox_shutdown(struct pci_dev *pdev)
677{ 675{
678 adapter_t *adapter = pci_get_drvdata(to_pci_dev(device)); 676 adapter_t *adapter = pci_get_drvdata(pdev);
679 static int counter; 677 static int counter;
680 678
681 if (!adapter) { 679 if (!adapter) {
diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c
index a3040429c27b..3a26f9cc8585 100644
--- a/drivers/video/cirrusfb.c
+++ b/drivers/video/cirrusfb.c
@@ -275,20 +275,20 @@ static const struct cirrusfb_board_info_rec {
275 275
276#ifdef CONFIG_PCI 276#ifdef CONFIG_PCI
277#define CHIP(id, btype) \ 277#define CHIP(id, btype) \
278 { PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_##id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) } 278 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
279 279
280static struct pci_device_id cirrusfb_pci_table[] = { 280static struct pci_device_id cirrusfb_pci_table[] = {
281 CHIP( CIRRUS_5436, BT_ALPINE ), 281 CHIP( PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE ),
282 CHIP( CIRRUS_5434_8, BT_ALPINE ), 282 CHIP( PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE ),
283 CHIP( CIRRUS_5434_4, BT_ALPINE ), 283 CHIP( PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE ),
284 CHIP( CIRRUS_5430, BT_ALPINE ), /* GD-5440 has identical id */ 284 CHIP( PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE ), /* GD-5440 is same id */
285 CHIP( CIRRUS_7543, BT_ALPINE ), 285 CHIP( PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE ),
286 CHIP( CIRRUS_7548, BT_ALPINE ), 286 CHIP( PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE ),
287 CHIP( CIRRUS_5480, BT_GD5480 ), /* MacPicasso probably */ 287 CHIP( PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480 ), /* MacPicasso likely */
288 CHIP( CIRRUS_5446, BT_PICASSO4 ), /* Picasso 4 is a GD5446 */ 288 CHIP( PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4 ), /* Picasso 4 is 5446 */
289 CHIP( CIRRUS_5462, BT_LAGUNA ), /* CL Laguna */ 289 CHIP( PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA ), /* CL Laguna */
290 CHIP( CIRRUS_5464, BT_LAGUNA ), /* CL Laguna 3D */ 290 CHIP( PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA ), /* CL Laguna 3D */
291 CHIP( CIRRUS_5465, BT_LAGUNA ), /* CL Laguna 3DA*/ 291 CHIP( PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA ), /* CL Laguna 3DA*/
292 { 0, } 292 { 0, }
293}; 293};
294MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table); 294MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 7349058ed778..3596ac94ecff 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -132,6 +132,7 @@ struct pci_dev {
132 unsigned int is_enabled:1; /* pci_enable_device has been called */ 132 unsigned int is_enabled:1; /* pci_enable_device has been called */
133 unsigned int is_busmaster:1; /* device is busmaster */ 133 unsigned int is_busmaster:1; /* device is busmaster */
134 unsigned int no_msi:1; /* device may not use msi */ 134 unsigned int no_msi:1; /* device may not use msi */
135 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
135 136
136 u32 saved_config_space[16]; /* config space saved at suspend time */ 137 u32 saved_config_space[16]; /* config space saved at suspend time */
137 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 138 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
@@ -490,6 +491,9 @@ extern void pci_disable_msix(struct pci_dev *dev);
490extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); 491extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
491#endif 492#endif
492 493
494extern void pci_block_user_cfg_access(struct pci_dev *dev);
495extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
496
493/* 497/*
494 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 498 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
495 * a PCI domain is defined to be a set of PCI busses which share 499 * a PCI domain is defined to be a set of PCI busses which share
@@ -560,6 +564,9 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int en
560 564
561#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 565#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
562 566
567static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
568static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
569
563#endif /* CONFIG_PCI */ 570#endif /* CONFIG_PCI */
564 571
565/* Include architecture-dependent settings and functions */ 572/* Include architecture-dependent settings and functions */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 71834f05504f..7d300f7469e3 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -132,9 +132,6 @@
132 132
133#define PCI_VENDOR_ID_COMPAQ 0x0e11 133#define PCI_VENDOR_ID_COMPAQ 0x0e11
134#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 134#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508
135#define PCI_DEVICE_ID_COMPAQ_1280 0x3033
136#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000
137#define PCI_DEVICE_ID_COMPAQ_6010 0x6010
138#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc 135#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc
139#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 136#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10
140#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 137#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32
@@ -274,7 +271,6 @@
274#define PCI_DEVICE_ID_ATI_RAGE128_PP 0x5050 271#define PCI_DEVICE_ID_ATI_RAGE128_PP 0x5050
275#define PCI_DEVICE_ID_ATI_RAGE128_PQ 0x5051 272#define PCI_DEVICE_ID_ATI_RAGE128_PQ 0x5051
276#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052 273#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052
277#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452
278#define PCI_DEVICE_ID_ATI_RAGE128_PS 0x5053 274#define PCI_DEVICE_ID_ATI_RAGE128_PS 0x5053
279#define PCI_DEVICE_ID_ATI_RAGE128_PT 0x5054 275#define PCI_DEVICE_ID_ATI_RAGE128_PT 0x5054
280#define PCI_DEVICE_ID_ATI_RAGE128_PU 0x5055 276#define PCI_DEVICE_ID_ATI_RAGE128_PU 0x5055
@@ -282,8 +278,6 @@
282#define PCI_DEVICE_ID_ATI_RAGE128_PW 0x5057 278#define PCI_DEVICE_ID_ATI_RAGE128_PW 0x5057
283#define PCI_DEVICE_ID_ATI_RAGE128_PX 0x5058 279#define PCI_DEVICE_ID_ATI_RAGE128_PX 0x5058
284/* Rage128 M4 */ 280/* Rage128 M4 */
285#define PCI_DEVICE_ID_ATI_RADEON_LE 0x4d45
286#define PCI_DEVICE_ID_ATI_RADEON_LF 0x4d46
287/* Radeon R100 */ 281/* Radeon R100 */
288#define PCI_DEVICE_ID_ATI_RADEON_QD 0x5144 282#define PCI_DEVICE_ID_ATI_RADEON_QD 0x5144
289#define PCI_DEVICE_ID_ATI_RADEON_QE 0x5145 283#define PCI_DEVICE_ID_ATI_RADEON_QE 0x5145
@@ -304,32 +298,22 @@
304#define PCI_DEVICE_ID_ATI_RADEON_QW 0x5157 298#define PCI_DEVICE_ID_ATI_RADEON_QW 0x5157
305#define PCI_DEVICE_ID_ATI_RADEON_QX 0x5158 299#define PCI_DEVICE_ID_ATI_RADEON_QX 0x5158
306/* Radeon NV-100 */ 300/* Radeon NV-100 */
307#define PCI_DEVICE_ID_ATI_RADEON_N1 0x5159
308#define PCI_DEVICE_ID_ATI_RADEON_N2 0x515a
309/* Radeon RV250 (9000) */ 301/* Radeon RV250 (9000) */
310#define PCI_DEVICE_ID_ATI_RADEON_Id 0x4964 302#define PCI_DEVICE_ID_ATI_RADEON_Id 0x4964
311#define PCI_DEVICE_ID_ATI_RADEON_Ie 0x4965 303#define PCI_DEVICE_ID_ATI_RADEON_Ie 0x4965
312#define PCI_DEVICE_ID_ATI_RADEON_If 0x4966 304#define PCI_DEVICE_ID_ATI_RADEON_If 0x4966
313#define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967 305#define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967
314/* Radeon RV280 (9200) */ 306/* Radeon RV280 (9200) */
315#define PCI_DEVICE_ID_ATI_RADEON_Y_ 0x5960
316#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961 307#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961
317#define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964 308#define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964
318/* Radeon R300 (9500) */ 309/* Radeon R300 (9500) */
319#define PCI_DEVICE_ID_ATI_RADEON_AD 0x4144
320/* Radeon R300 (9700) */ 310/* Radeon R300 (9700) */
321#define PCI_DEVICE_ID_ATI_RADEON_ND 0x4e44 311#define PCI_DEVICE_ID_ATI_RADEON_ND 0x4e44
322#define PCI_DEVICE_ID_ATI_RADEON_NE 0x4e45 312#define PCI_DEVICE_ID_ATI_RADEON_NE 0x4e45
323#define PCI_DEVICE_ID_ATI_RADEON_NF 0x4e46 313#define PCI_DEVICE_ID_ATI_RADEON_NF 0x4e46
324#define PCI_DEVICE_ID_ATI_RADEON_NG 0x4e47 314#define PCI_DEVICE_ID_ATI_RADEON_NG 0x4e47
325#define PCI_DEVICE_ID_ATI_RADEON_AE 0x4145
326#define PCI_DEVICE_ID_ATI_RADEON_AF 0x4146
327/* Radeon R350 (9800) */ 315/* Radeon R350 (9800) */
328#define PCI_DEVICE_ID_ATI_RADEON_NH 0x4e48
329#define PCI_DEVICE_ID_ATI_RADEON_NI 0x4e49
330/* Radeon RV350 (9600) */ 316/* Radeon RV350 (9600) */
331#define PCI_DEVICE_ID_ATI_RADEON_AP 0x4150
332#define PCI_DEVICE_ID_ATI_RADEON_AR 0x4152
333/* Radeon M6 */ 317/* Radeon M6 */
334#define PCI_DEVICE_ID_ATI_RADEON_LY 0x4c59 318#define PCI_DEVICE_ID_ATI_RADEON_LY 0x4c59
335#define PCI_DEVICE_ID_ATI_RADEON_LZ 0x4c5a 319#define PCI_DEVICE_ID_ATI_RADEON_LZ 0x4c5a
@@ -342,10 +326,6 @@
342#define PCI_DEVICE_ID_ATI_RADEON_Lf 0x4c66 326#define PCI_DEVICE_ID_ATI_RADEON_Lf 0x4c66
343#define PCI_DEVICE_ID_ATI_RADEON_Lg 0x4c67 327#define PCI_DEVICE_ID_ATI_RADEON_Lg 0x4c67
344/* Radeon */ 328/* Radeon */
345#define PCI_DEVICE_ID_ATI_RADEON_RA 0x5144
346#define PCI_DEVICE_ID_ATI_RADEON_RB 0x5145
347#define PCI_DEVICE_ID_ATI_RADEON_RC 0x5146
348#define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147
349/* RadeonIGP */ 329/* RadeonIGP */
350#define PCI_DEVICE_ID_ATI_RS100 0xcab0 330#define PCI_DEVICE_ID_ATI_RS100 0xcab0
351#define PCI_DEVICE_ID_ATI_RS200 0xcab2 331#define PCI_DEVICE_ID_ATI_RS200 0xcab2
@@ -446,45 +426,28 @@
446#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 426#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6
447#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 427#define PCI_DEVICE_ID_CIRRUS_6729 0x1100
448#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 428#define PCI_DEVICE_ID_CIRRUS_6832 0x1110
449#define PCI_DEVICE_ID_CIRRUS_7542 0x1200
450#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 429#define PCI_DEVICE_ID_CIRRUS_7543 0x1202
451#define PCI_DEVICE_ID_CIRRUS_7541 0x1204
452#define PCI_DEVICE_ID_CIRRUS_4610 0x6001 430#define PCI_DEVICE_ID_CIRRUS_4610 0x6001
453#define PCI_DEVICE_ID_CIRRUS_4612 0x6003 431#define PCI_DEVICE_ID_CIRRUS_4612 0x6003
454#define PCI_DEVICE_ID_CIRRUS_4615 0x6004 432#define PCI_DEVICE_ID_CIRRUS_4615 0x6004
455#define PCI_DEVICE_ID_CIRRUS_4281 0x6005
456 433
457#define PCI_VENDOR_ID_IBM 0x1014 434#define PCI_VENDOR_ID_IBM 0x1014
458#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a
459#define PCI_DEVICE_ID_IBM_TR 0x0018 435#define PCI_DEVICE_ID_IBM_TR 0x0018
460#define PCI_DEVICE_ID_IBM_82G2675 0x001d
461#define PCI_DEVICE_ID_IBM_MCA 0x0020
462#define PCI_DEVICE_ID_IBM_82351 0x0022
463#define PCI_DEVICE_ID_IBM_PYTHON 0x002d
464#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e
465#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e 436#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e
466#define PCI_DEVICE_ID_IBM_MPIC 0x0046
467#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d
468#define PCI_DEVICE_ID_IBM_CHUKAR 0x0096
469#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc 437#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc
470#define PCI_DEVICE_ID_IBM_CPC710_PCI32 0x0105
471#define PCI_DEVICE_ID_IBM_405GP 0x0156
472#define PCI_DEVICE_ID_IBM_SNIPE 0x0180 438#define PCI_DEVICE_ID_IBM_SNIPE 0x0180
473#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd
474#define PCI_DEVICE_ID_IBM_CITRINE 0x028C 439#define PCI_DEVICE_ID_IBM_CITRINE 0x028C
475#define PCI_DEVICE_ID_IBM_GEMSTONE 0xB166 440#define PCI_DEVICE_ID_IBM_GEMSTONE 0xB166
476#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff
477#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1 0x0031 441#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1 0x0031
478#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2 0x0219 442#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2 0x0219
479#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX 0x021A 443#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX 0x021A
480#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM 0x0251 444#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM 0x0251
481#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252 445#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252
482 446
483#define PCI_VENDOR_ID_COMPEX2 0x101a // pci.ids says "AT&T GIS (NCR)" 447#define PCI_VENDOR_ID_COMPEX2 0x101a /* pci.ids says "AT&T GIS (NCR)" */
484#define PCI_DEVICE_ID_COMPEX2_100VG 0x0005 448#define PCI_DEVICE_ID_COMPEX2_100VG 0x0005
485 449
486#define PCI_VENDOR_ID_WD 0x101c 450#define PCI_VENDOR_ID_WD 0x101c
487#define PCI_DEVICE_ID_WD_7197 0x3296
488#define PCI_DEVICE_ID_WD_90C 0xc24a 451#define PCI_DEVICE_ID_WD_90C 0xc24a
489 452
490#define PCI_VENDOR_ID_AMI 0x101e 453#define PCI_VENDOR_ID_AMI 0x101e
@@ -501,33 +464,18 @@
501#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 464#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006
502#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007 465#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007
503#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C 466#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C
504#define PCI_DEVICE_ID_AMD_FE_GATE_700D 0x700D
505#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E 467#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E
506#define PCI_DEVICE_ID_AMD_FE_GATE_700F 0x700F
507#define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400
508#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401 468#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401
509#define PCI_DEVICE_ID_AMD_COBRA_7403 0x7403
510#define PCI_DEVICE_ID_AMD_COBRA_7404 0x7404
511#define PCI_DEVICE_ID_AMD_VIPER_7408 0x7408
512#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409 469#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409
513#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B 470#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B
514#define PCI_DEVICE_ID_AMD_VIPER_740C 0x740C
515#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410 471#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410
516#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411 472#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411
517#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413 473#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413
518#define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414 474#define PCI_DEVICE_ID_AMD_VIPER_7440 0x7440
519#define PCI_DEVICE_ID_AMD_OPUS_7440 0x7440
520# define PCI_DEVICE_ID_AMD_VIPER_7440 PCI_DEVICE_ID_AMD_OPUS_7440
521#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441 475#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441
522# define PCI_DEVICE_ID_AMD_VIPER_7441 PCI_DEVICE_ID_AMD_OPUS_7441
523#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443 476#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443
524# define PCI_DEVICE_ID_AMD_VIPER_7443 PCI_DEVICE_ID_AMD_OPUS_7443 477#define PCI_DEVICE_ID_AMD_VIPER_7443 0x7443
525#define PCI_DEVICE_ID_AMD_OPUS_7445 0x7445 478#define PCI_DEVICE_ID_AMD_OPUS_7445 0x7445
526#define PCI_DEVICE_ID_AMD_OPUS_7448 0x7448
527# define PCI_DEVICE_ID_AMD_VIPER_7448 PCI_DEVICE_ID_AMD_OPUS_7448
528#define PCI_DEVICE_ID_AMD_OPUS_7449 0x7449
529# define PCI_DEVICE_ID_AMD_VIPER_7449 PCI_DEVICE_ID_AMD_OPUS_7449
530#define PCI_DEVICE_ID_AMD_8111_LAN 0x7462
531#define PCI_DEVICE_ID_AMD_8111_LPC 0x7468 479#define PCI_DEVICE_ID_AMD_8111_LPC 0x7468
532#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 480#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469
533#define PCI_DEVICE_ID_AMD_8111_SMBUS2 0x746a 481#define PCI_DEVICE_ID_AMD_8111_SMBUS2 0x746a
@@ -585,7 +533,6 @@
585#define PCI_DEVICE_ID_CT_65550 0x00e0 533#define PCI_DEVICE_ID_CT_65550 0x00e0
586#define PCI_DEVICE_ID_CT_65554 0x00e4 534#define PCI_DEVICE_ID_CT_65554 0x00e4
587#define PCI_DEVICE_ID_CT_65555 0x00e5 535#define PCI_DEVICE_ID_CT_65555 0x00e5
588#define PCI_DEVICE_ID_CT_69000 0x00c0
589 536
590#define PCI_VENDOR_ID_MIRO 0x1031 537#define PCI_VENDOR_ID_MIRO 0x1031
591#define PCI_DEVICE_ID_MIRO_36050 0x5601 538#define PCI_DEVICE_ID_MIRO_36050 0x5601
@@ -639,7 +586,6 @@
639#define PCI_DEVICE_ID_SI_550 0x0550 586#define PCI_DEVICE_ID_SI_550 0x0550
640#define PCI_DEVICE_ID_SI_540_VGA 0x5300 587#define PCI_DEVICE_ID_SI_540_VGA 0x5300
641#define PCI_DEVICE_ID_SI_550_VGA 0x5315 588#define PCI_DEVICE_ID_SI_550_VGA 0x5315
642#define PCI_DEVICE_ID_SI_601 0x0601
643#define PCI_DEVICE_ID_SI_620 0x0620 589#define PCI_DEVICE_ID_SI_620 0x0620
644#define PCI_DEVICE_ID_SI_630 0x0630 590#define PCI_DEVICE_ID_SI_630 0x0630
645#define PCI_DEVICE_ID_SI_633 0x0633 591#define PCI_DEVICE_ID_SI_633 0x0633
@@ -650,30 +596,22 @@
650#define PCI_DEVICE_ID_SI_648 0x0648 596#define PCI_DEVICE_ID_SI_648 0x0648
651#define PCI_DEVICE_ID_SI_650 0x0650 597#define PCI_DEVICE_ID_SI_650 0x0650
652#define PCI_DEVICE_ID_SI_651 0x0651 598#define PCI_DEVICE_ID_SI_651 0x0651
653#define PCI_DEVICE_ID_SI_652 0x0652
654#define PCI_DEVICE_ID_SI_655 0x0655 599#define PCI_DEVICE_ID_SI_655 0x0655
655#define PCI_DEVICE_ID_SI_661 0x0661 600#define PCI_DEVICE_ID_SI_661 0x0661
656#define PCI_DEVICE_ID_SI_730 0x0730 601#define PCI_DEVICE_ID_SI_730 0x0730
657#define PCI_DEVICE_ID_SI_733 0x0733 602#define PCI_DEVICE_ID_SI_733 0x0733
658#define PCI_DEVICE_ID_SI_630_VGA 0x6300 603#define PCI_DEVICE_ID_SI_630_VGA 0x6300
659#define PCI_DEVICE_ID_SI_730_VGA 0x7300
660#define PCI_DEVICE_ID_SI_735 0x0735 604#define PCI_DEVICE_ID_SI_735 0x0735
661#define PCI_DEVICE_ID_SI_740 0x0740 605#define PCI_DEVICE_ID_SI_740 0x0740
662#define PCI_DEVICE_ID_SI_741 0x0741 606#define PCI_DEVICE_ID_SI_741 0x0741
663#define PCI_DEVICE_ID_SI_745 0x0745 607#define PCI_DEVICE_ID_SI_745 0x0745
664#define PCI_DEVICE_ID_SI_746 0x0746 608#define PCI_DEVICE_ID_SI_746 0x0746
665#define PCI_DEVICE_ID_SI_748 0x0748
666#define PCI_DEVICE_ID_SI_750 0x0750
667#define PCI_DEVICE_ID_SI_751 0x0751
668#define PCI_DEVICE_ID_SI_752 0x0752
669#define PCI_DEVICE_ID_SI_755 0x0755 609#define PCI_DEVICE_ID_SI_755 0x0755
670#define PCI_DEVICE_ID_SI_760 0x0760 610#define PCI_DEVICE_ID_SI_760 0x0760
671#define PCI_DEVICE_ID_SI_900 0x0900 611#define PCI_DEVICE_ID_SI_900 0x0900
672#define PCI_DEVICE_ID_SI_961 0x0961 612#define PCI_DEVICE_ID_SI_961 0x0961
673#define PCI_DEVICE_ID_SI_962 0x0962 613#define PCI_DEVICE_ID_SI_962 0x0962
674#define PCI_DEVICE_ID_SI_963 0x0963 614#define PCI_DEVICE_ID_SI_963 0x0963
675#define PCI_DEVICE_ID_SI_5107 0x5107
676#define PCI_DEVICE_ID_SI_5300 0x5300
677#define PCI_DEVICE_ID_SI_5511 0x5511 615#define PCI_DEVICE_ID_SI_5511 0x5511
678#define PCI_DEVICE_ID_SI_5513 0x5513 616#define PCI_DEVICE_ID_SI_5513 0x5513
679#define PCI_DEVICE_ID_SI_5518 0x5518 617#define PCI_DEVICE_ID_SI_5518 0x5518
@@ -685,10 +623,6 @@
685#define PCI_DEVICE_ID_SI_5597 0x5597 623#define PCI_DEVICE_ID_SI_5597 0x5597
686#define PCI_DEVICE_ID_SI_5598 0x5598 624#define PCI_DEVICE_ID_SI_5598 0x5598
687#define PCI_DEVICE_ID_SI_5600 0x5600 625#define PCI_DEVICE_ID_SI_5600 0x5600
688#define PCI_DEVICE_ID_SI_6300 0x6300
689#define PCI_DEVICE_ID_SI_6306 0x6306
690#define PCI_DEVICE_ID_SI_6326 0x6326
691#define PCI_DEVICE_ID_SI_7001 0x7001
692#define PCI_DEVICE_ID_SI_7012 0x7012 626#define PCI_DEVICE_ID_SI_7012 0x7012
693#define PCI_DEVICE_ID_SI_7013 0x7013 627#define PCI_DEVICE_ID_SI_7013 0x7013
694#define PCI_DEVICE_ID_SI_7016 0x7016 628#define PCI_DEVICE_ID_SI_7016 0x7016
@@ -709,14 +643,11 @@
709#define PCI_DEVICE_ID_HP_DIVA_TOSCA1 0x1049 643#define PCI_DEVICE_ID_HP_DIVA_TOSCA1 0x1049
710#define PCI_DEVICE_ID_HP_DIVA_TOSCA2 0x104A 644#define PCI_DEVICE_ID_HP_DIVA_TOSCA2 0x104A
711#define PCI_DEVICE_ID_HP_DIVA_MAESTRO 0x104B 645#define PCI_DEVICE_ID_HP_DIVA_MAESTRO 0x104B
712#define PCI_DEVICE_ID_HP_PCI_LBA 0x1054
713#define PCI_DEVICE_ID_HP_REO_SBA 0x10f0
714#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1 646#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1
715#define PCI_DEVICE_ID_HP_VISUALIZE_FXE 0x108b 647#define PCI_DEVICE_ID_HP_VISUALIZE_FXE 0x108b
716#define PCI_DEVICE_ID_HP_DIVA_HALFDOME 0x1223 648#define PCI_DEVICE_ID_HP_DIVA_HALFDOME 0x1223
717#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE 0x1226 649#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE 0x1226
718#define PCI_DEVICE_ID_HP_DIVA_POWERBAR 0x1227 650#define PCI_DEVICE_ID_HP_DIVA_POWERBAR 0x1227
719#define PCI_DEVICE_ID_HP_ZX1_SBA 0x1229
720#define PCI_DEVICE_ID_HP_ZX1_IOC 0x122a 651#define PCI_DEVICE_ID_HP_ZX1_IOC 0x122a
721#define PCI_DEVICE_ID_HP_PCIX_LBA 0x122e 652#define PCI_DEVICE_ID_HP_PCIX_LBA 0x122e
722#define PCI_DEVICE_ID_HP_SX1000_IOC 0x127c 653#define PCI_DEVICE_ID_HP_SX1000_IOC 0x127c
@@ -724,9 +655,7 @@
724#define PCI_DEVICE_ID_HP_DIVA_AUX 0x1290 655#define PCI_DEVICE_ID_HP_DIVA_AUX 0x1290
725#define PCI_DEVICE_ID_HP_DIVA_RMP3 0x1301 656#define PCI_DEVICE_ID_HP_DIVA_RMP3 0x1301
726#define PCI_DEVICE_ID_HP_DIVA_HURRICANE 0x132a 657#define PCI_DEVICE_ID_HP_DIVA_HURRICANE 0x132a
727#define PCI_DEVICE_ID_HP_CISS 0x3210
728#define PCI_DEVICE_ID_HP_CISSA 0x3220 658#define PCI_DEVICE_ID_HP_CISSA 0x3220
729#define PCI_DEVICE_ID_HP_CISSB 0x3222
730#define PCI_DEVICE_ID_HP_CISSC 0x3230 659#define PCI_DEVICE_ID_HP_CISSC 0x3230
731#define PCI_DEVICE_ID_HP_CISSD 0x3238 660#define PCI_DEVICE_ID_HP_CISSD 0x3238
732#define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031 661#define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031
@@ -734,8 +663,6 @@
734#define PCI_VENDOR_ID_PCTECH 0x1042 663#define PCI_VENDOR_ID_PCTECH 0x1042
735#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 664#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000
736#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 665#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001
737#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000
738#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010
739#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 666#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
740 667
741#define PCI_VENDOR_ID_ASUSTEK 0x1043 668#define PCI_VENDOR_ID_ASUSTEK 0x1043
@@ -745,24 +672,15 @@
745#define PCI_DEVICE_ID_DPT 0xa400 672#define PCI_DEVICE_ID_DPT 0xa400
746 673
747#define PCI_VENDOR_ID_OPTI 0x1045 674#define PCI_VENDOR_ID_OPTI 0x1045
748#define PCI_DEVICE_ID_OPTI_92C178 0xc178
749#define PCI_DEVICE_ID_OPTI_82C557 0xc557
750#define PCI_DEVICE_ID_OPTI_82C558 0xc558 675#define PCI_DEVICE_ID_OPTI_82C558 0xc558
751#define PCI_DEVICE_ID_OPTI_82C621 0xc621 676#define PCI_DEVICE_ID_OPTI_82C621 0xc621
752#define PCI_DEVICE_ID_OPTI_82C700 0xc700 677#define PCI_DEVICE_ID_OPTI_82C700 0xc700
753#define PCI_DEVICE_ID_OPTI_82C701 0xc701
754#define PCI_DEVICE_ID_OPTI_82C814 0xc814
755#define PCI_DEVICE_ID_OPTI_82C822 0xc822
756#define PCI_DEVICE_ID_OPTI_82C861 0xc861
757#define PCI_DEVICE_ID_OPTI_82C825 0xd568 678#define PCI_DEVICE_ID_OPTI_82C825 0xd568
758 679
759#define PCI_VENDOR_ID_ELSA 0x1048 680#define PCI_VENDOR_ID_ELSA 0x1048
760#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 681#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000
761#define PCI_DEVICE_ID_ELSA_QS3000 0x3000 682#define PCI_DEVICE_ID_ELSA_QS3000 0x3000
762 683
763#define PCI_VENDOR_ID_SGS 0x104a
764#define PCI_DEVICE_ID_SGS_2000 0x0008
765#define PCI_DEVICE_ID_SGS_1764 0x0009
766 684
767#define PCI_VENDOR_ID_BUSLOGIC 0x104B 685#define PCI_VENDOR_ID_BUSLOGIC 0x104B
768#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 686#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
@@ -770,7 +688,6 @@
770#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 688#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130
771 689
772#define PCI_VENDOR_ID_TI 0x104c 690#define PCI_VENDOR_ID_TI 0x104c
773#define PCI_DEVICE_ID_TI_TVP4010 0x3d04
774#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 691#define PCI_DEVICE_ID_TI_TVP4020 0x3d07
775#define PCI_DEVICE_ID_TI_4450 0x8011 692#define PCI_DEVICE_ID_TI_4450 0x8011
776#define PCI_DEVICE_ID_TI_XX21_XX11 0x8031 693#define PCI_DEVICE_ID_TI_XX21_XX11 0x8031
@@ -804,14 +721,10 @@
804#define PCI_DEVICE_ID_TI_X420 0xac8e 721#define PCI_DEVICE_ID_TI_X420 0xac8e
805 722
806#define PCI_VENDOR_ID_SONY 0x104d 723#define PCI_VENDOR_ID_SONY 0x104d
807#define PCI_DEVICE_ID_SONY_CXD3222 0x8039
808 724
809#define PCI_VENDOR_ID_OAK 0x104e
810#define PCI_DEVICE_ID_OAK_OTI107 0x0107
811 725
812/* Winbond have two vendor IDs! See 0x10ad as well */ 726/* Winbond have two vendor IDs! See 0x10ad as well */
813#define PCI_VENDOR_ID_WINBOND2 0x1050 727#define PCI_VENDOR_ID_WINBOND2 0x1050
814#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940
815#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a 728#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a
816#define PCI_DEVICE_ID_WINBOND2_6692 0x6692 729#define PCI_DEVICE_ID_WINBOND2_6692 0x6692
817 730
@@ -820,19 +733,15 @@
820 733
821#define PCI_VENDOR_ID_EFAR 0x1055 734#define PCI_VENDOR_ID_EFAR 0x1055
822#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130 735#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130
823#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
824#define PCI_DEVICE_ID_EFAR_SLC90E66_2 0x9462
825#define PCI_DEVICE_ID_EFAR_SLC90E66_3 0x9463 736#define PCI_DEVICE_ID_EFAR_SLC90E66_3 0x9463
826 737
827#define PCI_VENDOR_ID_MOTOROLA 0x1057 738#define PCI_VENDOR_ID_MOTOROLA 0x1057
828#define PCI_VENDOR_ID_MOTOROLA_OOPS 0x1507
829#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 739#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001
830#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 740#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002
831#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004 741#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004
832#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 742#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801
833#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802 743#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802
834#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803 744#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803
835#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806
836#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b 745#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b
837#define PCI_DEVICE_ID_MOTOROLA_MPC5200 0x5803 746#define PCI_DEVICE_ID_MOTOROLA_MPC5200 0x5803
838 747
@@ -843,33 +752,19 @@
843#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 752#define PCI_DEVICE_ID_PROMISE_20262 0x4d38
844#define PCI_DEVICE_ID_PROMISE_20263 0x0D38 753#define PCI_DEVICE_ID_PROMISE_20263 0x0D38
845#define PCI_DEVICE_ID_PROMISE_20268 0x4d68 754#define PCI_DEVICE_ID_PROMISE_20268 0x4d68
846#define PCI_DEVICE_ID_PROMISE_20268R 0x6268
847#define PCI_DEVICE_ID_PROMISE_20269 0x4d69 755#define PCI_DEVICE_ID_PROMISE_20269 0x4d69
848#define PCI_DEVICE_ID_PROMISE_20270 0x6268 756#define PCI_DEVICE_ID_PROMISE_20270 0x6268
849#define PCI_DEVICE_ID_PROMISE_20271 0x6269 757#define PCI_DEVICE_ID_PROMISE_20271 0x6269
850#define PCI_DEVICE_ID_PROMISE_20275 0x1275 758#define PCI_DEVICE_ID_PROMISE_20275 0x1275
851#define PCI_DEVICE_ID_PROMISE_20276 0x5275 759#define PCI_DEVICE_ID_PROMISE_20276 0x5275
852#define PCI_DEVICE_ID_PROMISE_20277 0x7275 760#define PCI_DEVICE_ID_PROMISE_20277 0x7275
853#define PCI_DEVICE_ID_PROMISE_5300 0x5300
854 761
855#define PCI_VENDOR_ID_N9 0x105d
856#define PCI_DEVICE_ID_N9_I128 0x2309
857#define PCI_DEVICE_ID_N9_I128_2 0x2339
858#define PCI_DEVICE_ID_N9_I128_T2R 0x493d
859 762
860#define PCI_VENDOR_ID_UMC 0x1060 763#define PCI_VENDOR_ID_UMC 0x1060
861#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 764#define PCI_DEVICE_ID_UMC_UM8673F 0x0101
862#define PCI_DEVICE_ID_UMC_UM8891A 0x0891
863#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a 765#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a
864#define PCI_DEVICE_ID_UMC_UM8886A 0x886a 766#define PCI_DEVICE_ID_UMC_UM8886A 0x886a
865#define PCI_DEVICE_ID_UMC_UM8881F 0x8881
866#define PCI_DEVICE_ID_UMC_UM8886F 0x8886
867#define PCI_DEVICE_ID_UMC_UM9017F 0x9017
868#define PCI_DEVICE_ID_UMC_UM8886N 0xe886
869#define PCI_DEVICE_ID_UMC_UM8891N 0xe891
870 767
871#define PCI_VENDOR_ID_X 0x1061
872#define PCI_DEVICE_ID_X_AGX016 0x0001
873 768
874#define PCI_VENDOR_ID_MYLEX 0x1069 769#define PCI_VENDOR_ID_MYLEX 0x1069
875#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 770#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001
@@ -880,37 +775,26 @@
880#define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 775#define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56
881#define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166 776#define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166
882 777
883#define PCI_VENDOR_ID_PICOP 0x1066
884#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001
885#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002
886 778
887#define PCI_VENDOR_ID_APPLE 0x106b 779#define PCI_VENDOR_ID_APPLE 0x106b
888#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 780#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001
889#define PCI_DEVICE_ID_APPLE_GC 0x0002
890#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e 781#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e
891#define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018 782#define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018
892#define PCI_DEVICE_ID_APPLE_KL_USB 0x0019
893#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 783#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020
894#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021 784#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021
895#define PCI_DEVICE_ID_APPLE_KEYLARGO 0x0022
896#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024 785#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024
897#define PCI_DEVICE_ID_APPLE_KEYLARGO_P 0x0025
898#define PCI_DEVICE_ID_APPLE_KL_USB_P 0x0026
899#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027 786#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027
900#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d 787#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d
901#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e 788#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e
902#define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030
903#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032 789#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032
904#define PCI_DEVICE_ID_APPLE_UNI_N_ATA 0x0033 790#define PCI_DEVICE_ID_APPLE_UNI_N_ATA 0x0033
905#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034 791#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034
906#define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b 792#define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b
907#define PCI_DEVICE_ID_APPLE_KEYLARGO_I 0x003e
908#define PCI_DEVICE_ID_APPLE_K2_ATA100 0x0043 793#define PCI_DEVICE_ID_APPLE_K2_ATA100 0x0043
909#define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b 794#define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b
910#define PCI_DEVICE_ID_APPLE_K2_GMAC 0x004c 795#define PCI_DEVICE_ID_APPLE_K2_GMAC 0x004c
911#define PCI_DEVICE_ID_APPLE_SH_ATA 0x0050 796#define PCI_DEVICE_ID_APPLE_SH_ATA 0x0050
912#define PCI_DEVICE_ID_APPLE_SH_SUNGEM 0x0051 797#define PCI_DEVICE_ID_APPLE_SH_SUNGEM 0x0051
913#define PCI_DEVICE_ID_APPLE_SH_FW 0x0052
914#define PCI_DEVICE_ID_APPLE_U3L_AGP 0x0058 798#define PCI_DEVICE_ID_APPLE_U3L_AGP 0x0058
915#define PCI_DEVICE_ID_APPLE_U3H_AGP 0x0059 799#define PCI_DEVICE_ID_APPLE_U3H_AGP 0x0059
916#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645 800#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645
@@ -923,12 +807,9 @@
923#define PCI_DEVICE_ID_YAMAHA_744 0x0010 807#define PCI_DEVICE_ID_YAMAHA_744 0x0010
924#define PCI_DEVICE_ID_YAMAHA_754 0x0012 808#define PCI_DEVICE_ID_YAMAHA_754 0x0012
925 809
926#define PCI_VENDOR_ID_NEXGEN 0x1074
927#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78
928 810
929#define PCI_VENDOR_ID_QLOGIC 0x1077 811#define PCI_VENDOR_ID_QLOGIC 0x1077
930#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 812#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020
931#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022
932#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 813#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100
933#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 814#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200
934#define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300 815#define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300
@@ -946,32 +827,20 @@
946#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 827#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001
947#define PCI_DEVICE_ID_CYRIX_5520 0x0002 828#define PCI_DEVICE_ID_CYRIX_5520 0x0002
948#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 829#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100
949#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101
950#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 830#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102
951#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 831#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103
952#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 832#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104
953 833
954#define PCI_VENDOR_ID_LEADTEK 0x107d
955#define PCI_DEVICE_ID_LEADTEK_805 0x0000
956 834
957#define PCI_VENDOR_ID_INTERPHASE 0x107e
958#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004
959#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005
960#define PCI_DEVICE_ID_INTERPHASE_5575 0x0008
961 835
962#define PCI_VENDOR_ID_CONTAQ 0x1080 836#define PCI_VENDOR_ID_CONTAQ 0x1080
963#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600
964#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 837#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693
965 838
966#define PCI_VENDOR_ID_FOREX 0x1083
967 839
968#define PCI_VENDOR_ID_OLICOM 0x108d 840#define PCI_VENDOR_ID_OLICOM 0x108d
969#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001
970#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011
971#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 841#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012
972#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 842#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
973#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 843#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
974#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021
975 844
976#define PCI_VENDOR_ID_SUN 0x108e 845#define PCI_VENDOR_ID_SUN 0x108e
977#define PCI_DEVICE_ID_SUN_EBUS 0x1000 846#define PCI_DEVICE_ID_SUN_EBUS 0x1000
@@ -990,49 +859,31 @@
990#define PCI_DEVICE_ID_SUN_CASSINI 0xabba 859#define PCI_DEVICE_ID_SUN_CASSINI 0xabba
991 860
992#define PCI_VENDOR_ID_CMD 0x1095 861#define PCI_VENDOR_ID_CMD 0x1095
993#define PCI_DEVICE_ID_CMD_640 0x0640
994#define PCI_DEVICE_ID_CMD_643 0x0643 862#define PCI_DEVICE_ID_CMD_643 0x0643
995#define PCI_DEVICE_ID_CMD_646 0x0646 863#define PCI_DEVICE_ID_CMD_646 0x0646
996#define PCI_DEVICE_ID_CMD_647 0x0647
997#define PCI_DEVICE_ID_CMD_648 0x0648 864#define PCI_DEVICE_ID_CMD_648 0x0648
998#define PCI_DEVICE_ID_CMD_649 0x0649 865#define PCI_DEVICE_ID_CMD_649 0x0649
999#define PCI_DEVICE_ID_CMD_670 0x0670
1000#define PCI_DEVICE_ID_CMD_680 0x0680
1001 866
1002#define PCI_DEVICE_ID_SII_680 0x0680 867#define PCI_DEVICE_ID_SII_680 0x0680
1003#define PCI_DEVICE_ID_SII_3112 0x3112 868#define PCI_DEVICE_ID_SII_3112 0x3112
1004#define PCI_DEVICE_ID_SII_1210SA 0x0240 869#define PCI_DEVICE_ID_SII_1210SA 0x0240
1005 870
1006#define PCI_VENDOR_ID_VISION 0x1098
1007#define PCI_DEVICE_ID_VISION_QD8500 0x0001
1008#define PCI_DEVICE_ID_VISION_QD8580 0x0002
1009 871
1010#define PCI_VENDOR_ID_BROOKTREE 0x109e 872#define PCI_VENDOR_ID_BROOKTREE 0x109e
1011#define PCI_DEVICE_ID_BROOKTREE_848 0x0350
1012#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351
1013#define PCI_DEVICE_ID_BROOKTREE_878_1 0x036e
1014#define PCI_DEVICE_ID_BROOKTREE_878 0x0878 873#define PCI_DEVICE_ID_BROOKTREE_878 0x0878
1015#define PCI_DEVICE_ID_BROOKTREE_879 0x0879 874#define PCI_DEVICE_ID_BROOKTREE_879 0x0879
1016#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474
1017 875
1018#define PCI_VENDOR_ID_SIERRA 0x10a8
1019#define PCI_DEVICE_ID_SIERRA_STB 0x0000
1020 876
1021#define PCI_VENDOR_ID_SGI 0x10a9 877#define PCI_VENDOR_ID_SGI 0x10a9
1022#define PCI_DEVICE_ID_SGI_IOC3 0x0003 878#define PCI_DEVICE_ID_SGI_IOC3 0x0003
1023#define PCI_DEVICE_ID_SGI_IOC4 0x100a 879#define PCI_DEVICE_ID_SGI_IOC4 0x100a
1024#define PCI_VENDOR_ID_SGI_LITHIUM 0x1002 880#define PCI_VENDOR_ID_SGI_LITHIUM 0x1002
1025 881
1026#define PCI_VENDOR_ID_ACC 0x10aa
1027#define PCI_DEVICE_ID_ACC_2056 0x0000
1028 882
1029#define PCI_VENDOR_ID_WINBOND 0x10ad 883#define PCI_VENDOR_ID_WINBOND 0x10ad
1030#define PCI_DEVICE_ID_WINBOND_83769 0x0001
1031#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 884#define PCI_DEVICE_ID_WINBOND_82C105 0x0105
1032#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 885#define PCI_DEVICE_ID_WINBOND_83C553 0x0565
1033 886
1034#define PCI_VENDOR_ID_DATABOOK 0x10b3
1035#define PCI_DEVICE_ID_DATABOOK_87144 0xb106
1036 887
1037#define PCI_VENDOR_ID_PLX 0x10b5 888#define PCI_VENDOR_ID_PLX 0x10b5
1038#define PCI_DEVICE_ID_PLX_R685 0x1030 889#define PCI_DEVICE_ID_PLX_R685 0x1030
@@ -1043,33 +894,19 @@
1043#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 894#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151
1044#define PCI_DEVICE_ID_PLX_R753 0x1152 895#define PCI_DEVICE_ID_PLX_R753 0x1152
1045#define PCI_DEVICE_ID_PLX_OLITEC 0x1187 896#define PCI_DEVICE_ID_PLX_OLITEC 0x1187
1046#define PCI_DEVICE_ID_PLX_9030 0x9030
1047#define PCI_DEVICE_ID_PLX_9050 0x9050 897#define PCI_DEVICE_ID_PLX_9050 0x9050
1048#define PCI_DEVICE_ID_PLX_9060 0x9060
1049#define PCI_DEVICE_ID_PLX_9060ES 0x906E
1050#define PCI_DEVICE_ID_PLX_9060SD 0x906D
1051#define PCI_DEVICE_ID_PLX_9080 0x9080 898#define PCI_DEVICE_ID_PLX_9080 0x9080
1052#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 899#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001
1053 900
1054#define PCI_VENDOR_ID_MADGE 0x10b6 901#define PCI_VENDOR_ID_MADGE 0x10b6
1055#define PCI_DEVICE_ID_MADGE_MK2 0x0002 902#define PCI_DEVICE_ID_MADGE_MK2 0x0002
1056#define PCI_DEVICE_ID_MADGE_C155S 0x1001
1057 903
1058#define PCI_VENDOR_ID_3COM 0x10b7 904#define PCI_VENDOR_ID_3COM 0x10b7
1059#define PCI_DEVICE_ID_3COM_3C985 0x0001 905#define PCI_DEVICE_ID_3COM_3C985 0x0001
1060#define PCI_DEVICE_ID_3COM_3C940 0x1700 906#define PCI_DEVICE_ID_3COM_3C940 0x1700
1061#define PCI_DEVICE_ID_3COM_3C339 0x3390 907#define PCI_DEVICE_ID_3COM_3C339 0x3390
1062#define PCI_DEVICE_ID_3COM_3C359 0x3590 908#define PCI_DEVICE_ID_3COM_3C359 0x3590
1063#define PCI_DEVICE_ID_3COM_3C590 0x5900
1064#define PCI_DEVICE_ID_3COM_3C595TX 0x5950
1065#define PCI_DEVICE_ID_3COM_3C595T4 0x5951
1066#define PCI_DEVICE_ID_3COM_3C595MII 0x5952
1067#define PCI_DEVICE_ID_3COM_3C940B 0x80eb 909#define PCI_DEVICE_ID_3COM_3C940B 0x80eb
1068#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000
1069#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001
1070#define PCI_DEVICE_ID_3COM_3C905TX 0x9050
1071#define PCI_DEVICE_ID_3COM_3C905T4 0x9051
1072#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055
1073#define PCI_DEVICE_ID_3COM_3CR990 0x9900 910#define PCI_DEVICE_ID_3COM_3CR990 0x9900
1074#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902 911#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902
1075#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903 912#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903
@@ -1079,24 +916,11 @@
1079#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909 916#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909
1080#define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a 917#define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a
1081 918
1082#define PCI_VENDOR_ID_SMC 0x10b8
1083#define PCI_DEVICE_ID_SMC_EPIC100 0x0005
1084 919
1085#define PCI_VENDOR_ID_AL 0x10b9 920#define PCI_VENDOR_ID_AL 0x10b9
1086#define PCI_DEVICE_ID_AL_M1445 0x1445
1087#define PCI_DEVICE_ID_AL_M1449 0x1449
1088#define PCI_DEVICE_ID_AL_M1451 0x1451
1089#define PCI_DEVICE_ID_AL_M1461 0x1461
1090#define PCI_DEVICE_ID_AL_M1489 0x1489
1091#define PCI_DEVICE_ID_AL_M1511 0x1511
1092#define PCI_DEVICE_ID_AL_M1513 0x1513
1093#define PCI_DEVICE_ID_AL_M1521 0x1521
1094#define PCI_DEVICE_ID_AL_M1523 0x1523
1095#define PCI_DEVICE_ID_AL_M1531 0x1531
1096#define PCI_DEVICE_ID_AL_M1533 0x1533 921#define PCI_DEVICE_ID_AL_M1533 0x1533
1097#define PCI_DEVICE_ID_AL_M1535 0x1535 922#define PCI_DEVICE_ID_AL_M1535 0x1535
1098#define PCI_DEVICE_ID_AL_M1541 0x1541 923#define PCI_DEVICE_ID_AL_M1541 0x1541
1099#define PCI_DEVICE_ID_AL_M1543 0x1543
1100#define PCI_DEVICE_ID_AL_M1563 0x1563 924#define PCI_DEVICE_ID_AL_M1563 0x1563
1101#define PCI_DEVICE_ID_AL_M1621 0x1621 925#define PCI_DEVICE_ID_AL_M1621 0x1621
1102#define PCI_DEVICE_ID_AL_M1631 0x1631 926#define PCI_DEVICE_ID_AL_M1631 0x1631
@@ -1109,49 +933,23 @@
1109#define PCI_DEVICE_ID_AL_M1681 0x1681 933#define PCI_DEVICE_ID_AL_M1681 0x1681
1110#define PCI_DEVICE_ID_AL_M1683 0x1683 934#define PCI_DEVICE_ID_AL_M1683 0x1683
1111#define PCI_DEVICE_ID_AL_M1689 0x1689 935#define PCI_DEVICE_ID_AL_M1689 0x1689
1112#define PCI_DEVICE_ID_AL_M3307 0x3307
1113#define PCI_DEVICE_ID_AL_M4803 0x5215
1114#define PCI_DEVICE_ID_AL_M5219 0x5219 936#define PCI_DEVICE_ID_AL_M5219 0x5219
1115#define PCI_DEVICE_ID_AL_M5228 0x5228 937#define PCI_DEVICE_ID_AL_M5228 0x5228
1116#define PCI_DEVICE_ID_AL_M5229 0x5229 938#define PCI_DEVICE_ID_AL_M5229 0x5229
1117#define PCI_DEVICE_ID_AL_M5237 0x5237
1118#define PCI_DEVICE_ID_AL_M5243 0x5243
1119#define PCI_DEVICE_ID_AL_M5451 0x5451 939#define PCI_DEVICE_ID_AL_M5451 0x5451
1120#define PCI_DEVICE_ID_AL_M7101 0x7101 940#define PCI_DEVICE_ID_AL_M7101 0x7101
1121 941
1122#define PCI_VENDOR_ID_MITSUBISHI 0x10ba
1123 942
1124#define PCI_VENDOR_ID_SURECOM 0x10bd
1125#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34
1126 943
1127#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 944#define PCI_VENDOR_ID_NEOMAGIC 0x10c8
1128#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001
1129#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002
1130#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003
1131#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004
1132#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005
1133#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083
1134#define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005 945#define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005
1135#define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006 946#define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006
1136#define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016 947#define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016
1137 948
1138#define PCI_VENDOR_ID_ASP 0x10cd
1139#define PCI_DEVICE_ID_ASP_ABP940 0x1200
1140#define PCI_DEVICE_ID_ASP_ABP940U 0x1300
1141#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
1142
1143#define PCI_VENDOR_ID_MACRONIX 0x10d9
1144#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512
1145#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531
1146 949
1147#define PCI_VENDOR_ID_TCONRAD 0x10da 950#define PCI_VENDOR_ID_TCONRAD 0x10da
1148#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508 951#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
1149 952
1150#define PCI_VENDOR_ID_CERN 0x10dc
1151#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001
1152#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002
1153#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021
1154#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022
1155 953
1156#define PCI_VENDOR_ID_NVIDIA 0x10de 954#define PCI_VENDOR_ID_NVIDIA 0x10de
1157#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 955#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020
@@ -1197,7 +995,6 @@
1197#define PCI_DEVICE_ID_QUADRO_FX_GO1400 0x00cc 995#define PCI_DEVICE_ID_QUADRO_FX_GO1400 0x00cc
1198#define PCI_DEVICE_ID_QUADRO_FX_1400 0x00ce 996#define PCI_DEVICE_ID_QUADRO_FX_1400 0x00ce
1199#define PCI_DEVICE_ID_NVIDIA_NFORCE3 0x00d1 997#define PCI_DEVICE_ID_NVIDIA_NFORCE3 0x00d1
1200#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
1201#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS 0x00d4 998#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS 0x00d4
1202#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE 0x00d5 999#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE 0x00d5
1203#define PCI_DEVICE_ID_NVIDIA_NVENET_3 0x00d6 1000#define PCI_DEVICE_ID_NVIDIA_NVENET_3 0x00d6
@@ -1284,7 +1081,6 @@
1284#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2 0x037F 1081#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2 0x037F
1285#define PCI_DEVICE_ID_NVIDIA_NVENET_12 0x0268 1082#define PCI_DEVICE_ID_NVIDIA_NVENET_12 0x0268
1286#define PCI_DEVICE_ID_NVIDIA_NVENET_13 0x0269 1083#define PCI_DEVICE_ID_NVIDIA_NVENET_13 0x0269
1287#define PCI_DEVICE_ID_NVIDIA_MCP51_AUDIO 0x026B
1288#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800 0x0280 1084#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800 0x0280
1289#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X 0x0281 1085#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X 0x0281
1290#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE 0x0282 1086#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE 0x0282
@@ -1335,24 +1131,13 @@
1335#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373 1131#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373
1336 1132
1337#define PCI_VENDOR_ID_IMS 0x10e0 1133#define PCI_VENDOR_ID_IMS 0x10e0
1338#define PCI_DEVICE_ID_IMS_8849 0x8849
1339#define PCI_DEVICE_ID_IMS_TT128 0x9128 1134#define PCI_DEVICE_ID_IMS_TT128 0x9128
1340#define PCI_DEVICE_ID_IMS_TT3D 0x9135 1135#define PCI_DEVICE_ID_IMS_TT3D 0x9135
1341 1136
1342#define PCI_VENDOR_ID_TEKRAM2 0x10e1
1343#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c
1344 1137
1345#define PCI_VENDOR_ID_TUNDRA 0x10e3
1346#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000
1347 1138
1348#define PCI_VENDOR_ID_AMCC 0x10e8
1349#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043
1350#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062
1351#define PCI_DEVICE_ID_AMCC_S5933 0x807d
1352#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c
1353 1139
1354#define PCI_VENDOR_ID_INTERG 0x10ea 1140#define PCI_VENDOR_ID_INTERG 0x10ea
1355#define PCI_DEVICE_ID_INTERG_1680 0x1680
1356#define PCI_DEVICE_ID_INTERG_1682 0x1682 1141#define PCI_DEVICE_ID_INTERG_1682 0x1682
1357#define PCI_DEVICE_ID_INTERG_2000 0x2000 1142#define PCI_DEVICE_ID_INTERG_2000 0x2000
1358#define PCI_DEVICE_ID_INTERG_2010 0x2010 1143#define PCI_DEVICE_ID_INTERG_2010 0x2010
@@ -1360,32 +1145,23 @@
1360#define PCI_DEVICE_ID_INTERG_5050 0x5050 1145#define PCI_DEVICE_ID_INTERG_5050 0x5050
1361 1146
1362#define PCI_VENDOR_ID_REALTEK 0x10ec 1147#define PCI_VENDOR_ID_REALTEK 0x10ec
1363#define PCI_DEVICE_ID_REALTEK_8029 0x8029
1364#define PCI_DEVICE_ID_REALTEK_8129 0x8129
1365#define PCI_DEVICE_ID_REALTEK_8139 0x8139 1148#define PCI_DEVICE_ID_REALTEK_8139 0x8139
1366#define PCI_DEVICE_ID_REALTEK_8169 0x8169
1367 1149
1368#define PCI_VENDOR_ID_XILINX 0x10ee 1150#define PCI_VENDOR_ID_XILINX 0x10ee
1369#define PCI_DEVICE_ID_RME_DIGI96 0x3fc0 1151#define PCI_DEVICE_ID_RME_DIGI96 0x3fc0
1370#define PCI_DEVICE_ID_RME_DIGI96_8 0x3fc1 1152#define PCI_DEVICE_ID_RME_DIGI96_8 0x3fc1
1371#define PCI_DEVICE_ID_RME_DIGI96_8_PRO 0x3fc2 1153#define PCI_DEVICE_ID_RME_DIGI96_8_PRO 0x3fc2
1372#define PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST 0x3fc3 1154#define PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST 0x3fc3
1373#define PCI_DEVICE_ID_XILINX_HAMMERFALL 0x3fc4
1374#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5 1155#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
1375#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6 1156#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6
1376#define PCI_DEVICE_ID_TURBOPAM 0x4020
1377 1157
1378#define PCI_VENDOR_ID_TRUEVISION 0x10fa
1379#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c
1380 1158
1381#define PCI_VENDOR_ID_INIT 0x1101 1159#define PCI_VENDOR_ID_INIT 0x1101
1382#define PCI_DEVICE_ID_INIT_320P 0x9100
1383#define PCI_DEVICE_ID_INIT_360P 0x9500
1384 1160
1385#define PCI_VENDOR_ID_CREATIVE 0x1102 // duplicate: ECTIVA 1161#define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */
1386#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002 1162#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002
1387 1163
1388#define PCI_VENDOR_ID_ECTIVA 0x1102 // duplicate: CREATIVE 1164#define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */
1389#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938 1165#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
1390 1166
1391#define PCI_VENDOR_ID_TTI 0x1103 1167#define PCI_VENDOR_ID_TTI 0x1103
@@ -1395,7 +1171,7 @@
1395#define PCI_DEVICE_ID_TTI_HPT302 0x0006 1171#define PCI_DEVICE_ID_TTI_HPT302 0x0006
1396#define PCI_DEVICE_ID_TTI_HPT371 0x0007 1172#define PCI_DEVICE_ID_TTI_HPT371 0x0007
1397#define PCI_DEVICE_ID_TTI_HPT374 0x0008 1173#define PCI_DEVICE_ID_TTI_HPT374 0x0008
1398#define PCI_DEVICE_ID_TTI_HPT372N 0x0009 // apparently a 372N variant? 1174#define PCI_DEVICE_ID_TTI_HPT372N 0x0009 /* apparently a 372N variant? */
1399 1175
1400#define PCI_VENDOR_ID_VIA 0x1106 1176#define PCI_VENDOR_ID_VIA 0x1106
1401#define PCI_DEVICE_ID_VIA_8763_0 0x0198 1177#define PCI_DEVICE_ID_VIA_8763_0 0x0198
@@ -1408,36 +1184,25 @@
1408#define PCI_DEVICE_ID_VIA_8363_0 0x0305 1184#define PCI_DEVICE_ID_VIA_8363_0 0x0305
1409#define PCI_DEVICE_ID_VIA_8371_0 0x0391 1185#define PCI_DEVICE_ID_VIA_8371_0 0x0391
1410#define PCI_DEVICE_ID_VIA_8501_0 0x0501 1186#define PCI_DEVICE_ID_VIA_8501_0 0x0501
1411#define PCI_DEVICE_ID_VIA_82C505 0x0505
1412#define PCI_DEVICE_ID_VIA_82C561 0x0561 1187#define PCI_DEVICE_ID_VIA_82C561 0x0561
1413#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 1188#define PCI_DEVICE_ID_VIA_82C586_1 0x0571
1414#define PCI_DEVICE_ID_VIA_82C576 0x0576 1189#define PCI_DEVICE_ID_VIA_82C576 0x0576
1415#define PCI_DEVICE_ID_VIA_82C585 0x0585
1416#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 1190#define PCI_DEVICE_ID_VIA_82C586_0 0x0586
1417#define PCI_DEVICE_ID_VIA_82C595 0x0595
1418#define PCI_DEVICE_ID_VIA_82C596 0x0596 1191#define PCI_DEVICE_ID_VIA_82C596 0x0596
1419#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 1192#define PCI_DEVICE_ID_VIA_82C597_0 0x0597
1420#define PCI_DEVICE_ID_VIA_82C598_0 0x0598 1193#define PCI_DEVICE_ID_VIA_82C598_0 0x0598
1421#define PCI_DEVICE_ID_VIA_8601_0 0x0601 1194#define PCI_DEVICE_ID_VIA_8601_0 0x0601
1422#define PCI_DEVICE_ID_VIA_8605_0 0x0605 1195#define PCI_DEVICE_ID_VIA_8605_0 0x0605
1423#define PCI_DEVICE_ID_VIA_82C680 0x0680
1424#define PCI_DEVICE_ID_VIA_82C686 0x0686 1196#define PCI_DEVICE_ID_VIA_82C686 0x0686
1425#define PCI_DEVICE_ID_VIA_82C691_0 0x0691 1197#define PCI_DEVICE_ID_VIA_82C691_0 0x0691
1426#define PCI_DEVICE_ID_VIA_82C693 0x0693
1427#define PCI_DEVICE_ID_VIA_82C693_1 0x0698
1428#define PCI_DEVICE_ID_VIA_82C926 0x0926
1429#define PCI_DEVICE_ID_VIA_82C576_1 0x1571 1198#define PCI_DEVICE_ID_VIA_82C576_1 0x1571
1430#define PCI_DEVICE_ID_VIA_82C595_97 0x1595
1431#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 1199#define PCI_DEVICE_ID_VIA_82C586_2 0x3038
1432#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 1200#define PCI_DEVICE_ID_VIA_82C586_3 0x3040
1433#define PCI_DEVICE_ID_VIA_6305 0x3044
1434#define PCI_DEVICE_ID_VIA_82C596_3 0x3050 1201#define PCI_DEVICE_ID_VIA_82C596_3 0x3050
1435#define PCI_DEVICE_ID_VIA_82C596B_3 0x3051 1202#define PCI_DEVICE_ID_VIA_82C596B_3 0x3051
1436#define PCI_DEVICE_ID_VIA_82C686_4 0x3057 1203#define PCI_DEVICE_ID_VIA_82C686_4 0x3057
1437#define PCI_DEVICE_ID_VIA_82C686_5 0x3058 1204#define PCI_DEVICE_ID_VIA_82C686_5 0x3058
1438#define PCI_DEVICE_ID_VIA_8233_5 0x3059 1205#define PCI_DEVICE_ID_VIA_8233_5 0x3059
1439#define PCI_DEVICE_ID_VIA_8233_7 0x3065
1440#define PCI_DEVICE_ID_VIA_82C686_6 0x3068
1441#define PCI_DEVICE_ID_VIA_8233_0 0x3074 1206#define PCI_DEVICE_ID_VIA_8233_0 0x3074
1442#define PCI_DEVICE_ID_VIA_8633_0 0x3091 1207#define PCI_DEVICE_ID_VIA_8633_0 0x3091
1443#define PCI_DEVICE_ID_VIA_8367_0 0x3099 1208#define PCI_DEVICE_ID_VIA_8367_0 0x3099
@@ -1455,38 +1220,23 @@
1455#define PCI_DEVICE_ID_VIA_XN266 0x3156 1220#define PCI_DEVICE_ID_VIA_XN266 0x3156
1456#define PCI_DEVICE_ID_VIA_8754C_0 0x3168 1221#define PCI_DEVICE_ID_VIA_8754C_0 0x3168
1457#define PCI_DEVICE_ID_VIA_8235 0x3177 1222#define PCI_DEVICE_ID_VIA_8235 0x3177
1458#define PCI_DEVICE_ID_VIA_P4N333 0x3178
1459#define PCI_DEVICE_ID_VIA_8385_0 0x3188 1223#define PCI_DEVICE_ID_VIA_8385_0 0x3188
1460#define PCI_DEVICE_ID_VIA_8377_0 0x3189 1224#define PCI_DEVICE_ID_VIA_8377_0 0x3189
1461#define PCI_DEVICE_ID_VIA_8378_0 0x3205 1225#define PCI_DEVICE_ID_VIA_8378_0 0x3205
1462#define PCI_DEVICE_ID_VIA_8783_0 0x3208 1226#define PCI_DEVICE_ID_VIA_8783_0 0x3208
1463#define PCI_DEVICE_ID_VIA_P4M400 0x3209
1464#define PCI_DEVICE_ID_VIA_8237 0x3227 1227#define PCI_DEVICE_ID_VIA_8237 0x3227
1465#define PCI_DEVICE_ID_VIA_3296_0 0x0296 1228#define PCI_DEVICE_ID_VIA_3296_0 0x0296
1466#define PCI_DEVICE_ID_VIA_86C100A 0x6100
1467#define PCI_DEVICE_ID_VIA_8231 0x8231 1229#define PCI_DEVICE_ID_VIA_8231 0x8231
1468#define PCI_DEVICE_ID_VIA_8231_4 0x8235 1230#define PCI_DEVICE_ID_VIA_8231_4 0x8235
1469#define PCI_DEVICE_ID_VIA_8365_1 0x8305 1231#define PCI_DEVICE_ID_VIA_8365_1 0x8305
1470#define PCI_DEVICE_ID_VIA_8371_1 0x8391 1232#define PCI_DEVICE_ID_VIA_8371_1 0x8391
1471#define PCI_DEVICE_ID_VIA_8501_1 0x8501
1472#define PCI_DEVICE_ID_VIA_82C597_1 0x8597
1473#define PCI_DEVICE_ID_VIA_82C598_1 0x8598 1233#define PCI_DEVICE_ID_VIA_82C598_1 0x8598
1474#define PCI_DEVICE_ID_VIA_8601_1 0x8601
1475#define PCI_DEVICE_ID_VIA_8505_1 0x8605
1476#define PCI_DEVICE_ID_VIA_8633_1 0xB091
1477#define PCI_DEVICE_ID_VIA_8367_1 0xB099
1478#define PCI_DEVICE_ID_VIA_P4X266_1 0xB101
1479#define PCI_DEVICE_ID_VIA_8615_1 0xB103
1480#define PCI_DEVICE_ID_VIA_8361_1 0xB112
1481#define PCI_DEVICE_ID_VIA_8235_1 0xB168
1482#define PCI_DEVICE_ID_VIA_838X_1 0xB188 1234#define PCI_DEVICE_ID_VIA_838X_1 0xB188
1483#define PCI_DEVICE_ID_VIA_83_87XX_1 0xB198 1235#define PCI_DEVICE_ID_VIA_83_87XX_1 0xB198
1484 1236
1485#define PCI_VENDOR_ID_SIEMENS 0x110A 1237#define PCI_VENDOR_ID_SIEMENS 0x110A
1486#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 1238#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102
1487 1239
1488#define PCI_VENDOR_ID_SMC2 0x1113
1489#define PCI_DEVICE_ID_SMC2_1211TX 0x1211
1490 1240
1491#define PCI_VENDOR_ID_VORTEX 0x1119 1241#define PCI_VENDOR_ID_VORTEX 0x1119
1492#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 1242#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000
@@ -1509,18 +1259,6 @@
1509#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 1259#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103
1510#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 1260#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104
1511#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 1261#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105
1512#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110
1513#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111
1514#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112
1515#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113
1516#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114
1517#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115
1518#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120
1519#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121
1520#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122
1521#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123
1522#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124
1523#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125
1524 1262
1525#define PCI_VENDOR_ID_EF 0x111a 1263#define PCI_VENDOR_ID_EF 0x111a
1526#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 1264#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000
@@ -1532,21 +1270,15 @@
1532#define PCI_DEVICE_ID_IDT_IDT77201 0x0001 1270#define PCI_DEVICE_ID_IDT_IDT77201 0x0001
1533 1271
1534#define PCI_VENDOR_ID_FORE 0x1127 1272#define PCI_VENDOR_ID_FORE 0x1127
1535#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210
1536#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 1273#define PCI_DEVICE_ID_FORE_PCA200E 0x0300
1537 1274
1538#define PCI_VENDOR_ID_IMAGINGTECH 0x112f
1539#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000
1540 1275
1541#define PCI_VENDOR_ID_PHILIPS 0x1131 1276#define PCI_VENDOR_ID_PHILIPS 0x1131
1542#define PCI_DEVICE_ID_PHILIPS_SAA7145 0x7145
1543#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 1277#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146
1544#define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730 1278#define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730
1545 1279
1546#define PCI_VENDOR_ID_EICON 0x1133 1280#define PCI_VENDOR_ID_EICON 0x1133
1547#define PCI_DEVICE_ID_EICON_DIVA20PRO 0xe001
1548#define PCI_DEVICE_ID_EICON_DIVA20 0xe002 1281#define PCI_DEVICE_ID_EICON_DIVA20 0xe002
1549#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003
1550#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004 1282#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004
1551#define PCI_DEVICE_ID_EICON_DIVA201 0xe005 1283#define PCI_DEVICE_ID_EICON_DIVA201 0xe005
1552#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b 1284#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b
@@ -1558,35 +1290,17 @@
1558#define PCI_VENDOR_ID_ZIATECH 0x1138 1290#define PCI_VENDOR_ID_ZIATECH 0x1138
1559#define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550 1291#define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550
1560 1292
1561#define PCI_VENDOR_ID_CYCLONE 0x113c
1562#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001
1563 1293
1564#define PCI_VENDOR_ID_ALLIANCE 0x1142
1565#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210
1566#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422
1567#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424
1568#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d
1569 1294
1570#define PCI_VENDOR_ID_SYSKONNECT 0x1148 1295#define PCI_VENDOR_ID_SYSKONNECT 0x1148
1571#define PCI_DEVICE_ID_SYSKONNECT_FP 0x4000
1572#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 1296#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200
1573#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 1297#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300
1574#define PCI_DEVICE_ID_SYSKONNECT_YU 0x4320 1298#define PCI_DEVICE_ID_SYSKONNECT_YU 0x4320
1575#define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400 1299#define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400
1576#define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500 1300#define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500
1577 1301
1578#define PCI_VENDOR_ID_VMIC 0x114a
1579#define PCI_DEVICE_ID_VMIC_VME 0x7587
1580 1302
1581#define PCI_VENDOR_ID_DIGI 0x114f 1303#define PCI_VENDOR_ID_DIGI 0x114f
1582#define PCI_DEVICE_ID_DIGI_EPC 0x0002
1583#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003
1584#define PCI_DEVICE_ID_DIGI_XEM 0x0004
1585#define PCI_DEVICE_ID_DIGI_XR 0x0005
1586#define PCI_DEVICE_ID_DIGI_CX 0x0006
1587#define PCI_DEVICE_ID_DIGI_XRJ 0x0009
1588#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a
1589#define PCI_DEVICE_ID_DIGI_XR_920 0x0027
1590#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070 1304#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070
1591#define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071 1305#define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071
1592#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072 1306#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072
@@ -1596,23 +1310,15 @@
1596#define PCI_DEVICE_ID_NEO_2RJ45 0x00CA 1310#define PCI_DEVICE_ID_NEO_2RJ45 0x00CA
1597#define PCI_DEVICE_ID_NEO_2RJ45PRI 0x00CB 1311#define PCI_DEVICE_ID_NEO_2RJ45PRI 0x00CB
1598 1312
1599#define PCI_VENDOR_ID_MUTECH 0x1159
1600#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001
1601 1313
1602#define PCI_VENDOR_ID_XIRCOM 0x115d 1314#define PCI_VENDOR_ID_XIRCOM 0x115d
1603#define PCI_DEVICE_ID_XIRCOM_X3201_ETH 0x0003
1604#define PCI_DEVICE_ID_XIRCOM_RBM56G 0x0101 1315#define PCI_DEVICE_ID_XIRCOM_RBM56G 0x0101
1605#define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103 1316#define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103
1606 1317
1607#define PCI_VENDOR_ID_RENDITION 0x1163
1608#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001
1609#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000
1610 1318
1611#define PCI_VENDOR_ID_SERVERWORKS 0x1166 1319#define PCI_VENDOR_ID_SERVERWORKS 0x1166
1612#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 1320#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008
1613#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 1321#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009
1614#define PCI_DEVICE_ID_SERVERWORKS_CIOB30 0x0010
1615#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011
1616#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017 1322#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
1617#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 1323#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200
1618#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 1324#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201
@@ -1622,13 +1328,7 @@
1622#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 1328#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
1623#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214 1329#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214
1624#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217 1330#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
1625#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220
1626#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB
1627#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221
1628#define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227 1331#define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
1629#define PCI_DEVICE_ID_SERVERWORKS_GCLE 0x0225
1630#define PCI_DEVICE_ID_SERVERWORKS_GCLE2 0x0227
1631#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230
1632 1332
1633#define PCI_VENDOR_ID_SBE 0x1176 1333#define PCI_VENDOR_ID_SBE 0x1176
1634#define PCI_DEVICE_ID_SBE_WANXL100 0x0301 1334#define PCI_DEVICE_ID_SBE_WANXL100 0x0301
@@ -1639,17 +1339,12 @@
1639#define PCI_DEVICE_ID_TOSHIBA_PICCOLO 0x0102 1339#define PCI_DEVICE_ID_TOSHIBA_PICCOLO 0x0102
1640#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1 0x0103 1340#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1 0x0103
1641#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2 0x0105 1341#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2 0x0105
1642#define PCI_DEVICE_ID_TOSHIBA_601 0x0601
1643#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a 1342#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a
1644#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_A 0x0603
1645#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_B 0x060a
1646#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f 1343#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f
1647#define PCI_DEVICE_ID_TOSHIBA_TOPIC100 0x0617 1344#define PCI_DEVICE_ID_TOSHIBA_TOPIC100 0x0617
1648 1345
1649#define PCI_VENDOR_ID_TOSHIBA_2 0x102f 1346#define PCI_VENDOR_ID_TOSHIBA_2 0x102f
1650#define PCI_DEVICE_ID_TOSHIBA_TX3927 0x000a
1651#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030 1347#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030
1652#define PCI_DEVICE_ID_TOSHIBA_TX4927 0x0180
1653#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC 0x0108 1348#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC 0x0108
1654#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3 1349#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3
1655 1350
@@ -1664,7 +1359,6 @@
1664#define PCI_DEVICE_ID_DLINK_DGE510T 0x4c00 1359#define PCI_DEVICE_ID_DLINK_DGE510T 0x4c00
1665 1360
1666#define PCI_VENDOR_ID_ARTOP 0x1191 1361#define PCI_VENDOR_ID_ARTOP 0x1191
1667#define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004
1668#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 1362#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005
1669#define PCI_DEVICE_ID_ARTOP_ATP860 0x0006 1363#define PCI_DEVICE_ID_ARTOP_ATP860 0x0006
1670#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007 1364#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007
@@ -1677,16 +1371,11 @@
1677#define PCI_DEVICE_ID_ARTOP_AEC7612D 0x8040 1371#define PCI_DEVICE_ID_ARTOP_AEC7612D 0x8040
1678#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050 1372#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050
1679#define PCI_DEVICE_ID_ARTOP_8060 0x8060 1373#define PCI_DEVICE_ID_ARTOP_8060 0x8060
1680#define PCI_DEVICE_ID_ARTOP_AEC67160 0x8080
1681#define PCI_DEVICE_ID_ARTOP_AEC67160_2 0x8081
1682#define PCI_DEVICE_ID_ARTOP_AEC67162 0x808a
1683 1374
1684#define PCI_VENDOR_ID_ZEITNET 0x1193 1375#define PCI_VENDOR_ID_ZEITNET 0x1193
1685#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 1376#define PCI_DEVICE_ID_ZEITNET_1221 0x0001
1686#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 1377#define PCI_DEVICE_ID_ZEITNET_1225 0x0002
1687 1378
1688#define PCI_VENDOR_ID_OMEGA 0x119b
1689#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221
1690 1379
1691#define PCI_VENDOR_ID_FUJITSU_ME 0x119e 1380#define PCI_VENDOR_ID_FUJITSU_ME 0x119e
1692#define PCI_DEVICE_ID_FUJITSU_FS155 0x0001 1381#define PCI_DEVICE_ID_FUJITSU_FS155 0x0001
@@ -1696,61 +1385,41 @@
1696#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 1385#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334
1697 1386
1698#define PCI_VENDOR_ID_MARVELL 0x11ab 1387#define PCI_VENDOR_ID_MARVELL 0x11ab
1699#define PCI_DEVICE_ID_MARVELL_GT64011 0x4146
1700#define PCI_DEVICE_ID_MARVELL_GT64111 0x4146
1701#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430 1388#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430
1702#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460 1389#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460
1703#define PCI_DEVICE_ID_MARVELL_MV64460 0x6480 1390#define PCI_DEVICE_ID_MARVELL_MV64460 0x6480
1704#define PCI_DEVICE_ID_MARVELL_GT96100 0x9652 1391#define PCI_DEVICE_ID_MARVELL_GT96100 0x9652
1705#define PCI_DEVICE_ID_MARVELL_GT96100A 0x9653 1392#define PCI_DEVICE_ID_MARVELL_GT96100A 0x9653
1706 1393
1707#define PCI_VENDOR_ID_LITEON 0x11ad
1708#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002
1709 1394
1710#define PCI_VENDOR_ID_V3 0x11b0 1395#define PCI_VENDOR_ID_V3 0x11b0
1711#define PCI_DEVICE_ID_V3_V960 0x0001 1396#define PCI_DEVICE_ID_V3_V960 0x0001
1712#define PCI_DEVICE_ID_V3_V350 0x0001
1713#define PCI_DEVICE_ID_V3_V961 0x0002
1714#define PCI_DEVICE_ID_V3_V351 0x0002 1397#define PCI_DEVICE_ID_V3_V351 0x0002
1715 1398
1716#define PCI_VENDOR_ID_NP 0x11bc
1717#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001
1718 1399
1719#define PCI_VENDOR_ID_ATT 0x11c1 1400#define PCI_VENDOR_ID_ATT 0x11c1
1720#define PCI_DEVICE_ID_ATT_L56XMF 0x0440
1721#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 1401#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480
1722 1402
1723#define PCI_VENDOR_ID_NEC2 0x11c3 /* NEC (2nd) */
1724 1403
1725#define PCI_VENDOR_ID_SPECIALIX 0x11cb 1404#define PCI_VENDOR_ID_SPECIALIX 0x11cb
1726#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 1405#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000
1727#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000
1728#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 1406#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000
1729#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004 1407#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
1730 1408
1731#define PCI_VENDOR_ID_AURAVISION 0x11d1
1732#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7
1733 1409
1734#define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 1410#define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4
1735#define PCI_DEVICE_ID_AD1889JS 0x1889 1411#define PCI_DEVICE_ID_AD1889JS 0x1889
1736 1412
1737#define PCI_VENDOR_ID_IKON 0x11d5
1738#define PCI_DEVICE_ID_IKON_10115 0x0115
1739#define PCI_DEVICE_ID_IKON_10117 0x0117
1740 1413
1741#define PCI_VENDOR_ID_SEGA 0x11db
1742#define PCI_DEVICE_ID_SEGA_BBA 0x1234 1414#define PCI_DEVICE_ID_SEGA_BBA 0x1234
1743 1415
1744#define PCI_VENDOR_ID_ZORAN 0x11de 1416#define PCI_VENDOR_ID_ZORAN 0x11de
1745#define PCI_DEVICE_ID_ZORAN_36057 0x6057 1417#define PCI_DEVICE_ID_ZORAN_36057 0x6057
1746#define PCI_DEVICE_ID_ZORAN_36120 0x6120 1418#define PCI_DEVICE_ID_ZORAN_36120 0x6120
1747 1419
1748#define PCI_VENDOR_ID_KINETIC 0x11f4
1749#define PCI_DEVICE_ID_KINETIC_2915 0x2915
1750 1420
1751#define PCI_VENDOR_ID_COMPEX 0x11f6 1421#define PCI_VENDOR_ID_COMPEX 0x11f6
1752#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 1422#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112
1753#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401
1754 1423
1755#define PCI_VENDOR_ID_RP 0x11fe 1424#define PCI_VENDOR_ID_RP 0x11fe
1756#define PCI_DEVICE_ID_RP32INTF 0x0001 1425#define PCI_DEVICE_ID_RP32INTF 0x0001
@@ -1764,7 +1433,6 @@
1764#define PCI_DEVICE_ID_RP16SNI 0x0009 1433#define PCI_DEVICE_ID_RP16SNI 0x0009
1765#define PCI_DEVICE_ID_RPP4 0x000A 1434#define PCI_DEVICE_ID_RPP4 0x000A
1766#define PCI_DEVICE_ID_RPP8 0x000B 1435#define PCI_DEVICE_ID_RPP8 0x000B
1767#define PCI_DEVICE_ID_RP8M 0x000C
1768#define PCI_DEVICE_ID_RP4M 0x000D 1436#define PCI_DEVICE_ID_RP4M 0x000D
1769#define PCI_DEVICE_ID_RP2_232 0x000E 1437#define PCI_DEVICE_ID_RP2_232 0x000E
1770#define PCI_DEVICE_ID_RP2_422 0x000F 1438#define PCI_DEVICE_ID_RP2_422 0x000F
@@ -1792,10 +1460,6 @@
1792#define PCI_DEVICE_ID_PC300_TE_M_2 0x0320 1460#define PCI_DEVICE_ID_PC300_TE_M_2 0x0320
1793#define PCI_DEVICE_ID_PC300_TE_M_1 0x0321 1461#define PCI_DEVICE_ID_PC300_TE_M_1 0x0321
1794 1462
1795/* Allied Telesyn */
1796#define PCI_VENDOR_ID_AT 0x1259
1797#define PCI_SUBDEVICE_ID_AT_2701FX 0x2703
1798
1799#define PCI_VENDOR_ID_ESSENTIAL 0x120f 1463#define PCI_VENDOR_ID_ESSENTIAL 0x120f
1800#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 1464#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001
1801 1465
@@ -1812,10 +1476,7 @@
1812#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 1476#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005
1813#define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009 1477#define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009
1814 1478
1815#define PCI_VENDOR_ID_SIGMADES 0x1236
1816#define PCI_DEVICE_ID_SIGMADES_6425 0x6401
1817 1479
1818#define PCI_VENDOR_ID_CCUBE 0x123f
1819 1480
1820#define PCI_VENDOR_ID_AVM 0x1244 1481#define PCI_VENDOR_ID_AVM 0x1244
1821#define PCI_DEVICE_ID_AVM_B1 0x0700 1482#define PCI_DEVICE_ID_AVM_B1 0x0700
@@ -1825,19 +1486,8 @@
1825#define PCI_DEVICE_ID_AVM_C2 0x1100 1486#define PCI_DEVICE_ID_AVM_C2 0x1100
1826#define PCI_DEVICE_ID_AVM_T1 0x1200 1487#define PCI_DEVICE_ID_AVM_T1 0x1200
1827 1488
1828#define PCI_VENDOR_ID_DIPIX 0x1246
1829 1489
1830#define PCI_VENDOR_ID_STALLION 0x124d 1490#define PCI_VENDOR_ID_STALLION 0x124d
1831#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000
1832#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002
1833#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003
1834
1835#define PCI_VENDOR_ID_OPTIBASE 0x1255
1836#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110
1837#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210
1838#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110
1839#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120
1840#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130
1841 1491
1842/* Allied Telesyn */ 1492/* Allied Telesyn */
1843#define PCI_VENDOR_ID_AT 0x1259 1493#define PCI_VENDOR_ID_AT 0x1259
@@ -1846,7 +1496,6 @@
1846 1496
1847#define PCI_VENDOR_ID_ESS 0x125d 1497#define PCI_VENDOR_ID_ESS 0x125d
1848#define PCI_DEVICE_ID_ESS_ESS1968 0x1968 1498#define PCI_DEVICE_ID_ESS_ESS1968 0x1968
1849#define PCI_DEVICE_ID_ESS_AUDIOPCI 0x1969
1850#define PCI_DEVICE_ID_ESS_ESS1978 0x1978 1499#define PCI_DEVICE_ID_ESS_ESS1978 0x1978
1851#define PCI_DEVICE_ID_ESS_ALLEGRO_1 0x1988 1500#define PCI_DEVICE_ID_ESS_ALLEGRO_1 0x1988
1852#define PCI_DEVICE_ID_ESS_ALLEGRO 0x1989 1501#define PCI_DEVICE_ID_ESS_ALLEGRO 0x1989
@@ -1859,11 +1508,7 @@
1859 1508
1860#define PCI_VENDOR_ID_SATSAGEM 0x1267 1509#define PCI_VENDOR_ID_SATSAGEM 0x1267
1861#define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 1510#define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016
1862#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352
1863#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b
1864 1511
1865#define PCI_VENDOR_ID_HUGHES 0x1273
1866#define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002
1867 1512
1868#define PCI_VENDOR_ID_ENSONIQ 0x1274 1513#define PCI_VENDOR_ID_ENSONIQ 0x1274
1869#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 1514#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
@@ -1884,13 +1529,10 @@
1884#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 1529#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886
1885 1530
1886/* formerly Platform Tech */ 1531/* formerly Platform Tech */
1887#define PCI_VENDOR_ID_ESS_OLD 0x1285
1888#define PCI_DEVICE_ID_ESS_ESS0100 0x0100 1532#define PCI_DEVICE_ID_ESS_ESS0100 0x0100
1889 1533
1890#define PCI_VENDOR_ID_ALTEON 0x12ae 1534#define PCI_VENDOR_ID_ALTEON 0x12ae
1891#define PCI_DEVICE_ID_ALTEON_ACENIC 0x0001
1892 1535
1893#define PCI_VENDOR_ID_USR 0x12B9
1894 1536
1895#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 1537#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4
1896#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 1538#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001
@@ -1905,8 +1547,6 @@
1905#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A 1547#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A
1906#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B 1548#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B
1907 1549
1908#define PCI_VENDOR_ID_PICTUREL 0x12c5
1909#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081
1910 1550
1911#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 1551#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2
1912#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 1552#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
@@ -1928,8 +1568,6 @@
1928#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8 1568#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8
1929#define PCI_DEVICE_ID_LML_33R10 0x8a02 1569#define PCI_DEVICE_ID_LML_33R10 0x8a02
1930 1570
1931#define PCI_VENDOR_ID_CBOARDS 0x1307
1932#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001
1933 1571
1934#define PCI_VENDOR_ID_SIIG 0x131f 1572#define PCI_VENDOR_ID_SIIG 0x131f
1935#define PCI_SUBVENDOR_ID_SIIG 0x131f 1573#define PCI_SUBVENDOR_ID_SIIG 0x131f
@@ -1973,7 +1611,6 @@
1973#define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL 0x2050 1611#define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL 0x2050
1974 1612
1975#define PCI_VENDOR_ID_RADISYS 0x1331 1613#define PCI_VENDOR_ID_RADISYS 0x1331
1976#define PCI_DEVICE_ID_RADISYS_ENP2611 0x0030
1977 1614
1978#define PCI_VENDOR_ID_DOMEX 0x134a 1615#define PCI_VENDOR_ID_DOMEX 0x134a
1979#define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001 1616#define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001
@@ -1981,8 +1618,6 @@
1981#define PCI_VENDOR_ID_QUATECH 0x135C 1618#define PCI_VENDOR_ID_QUATECH 0x135C
1982#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 1619#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010
1983#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 1620#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020
1984#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030
1985#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040
1986#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 1621#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050
1987#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 1622#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060
1988 1623
@@ -2001,7 +1636,6 @@
2001#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO 0x0106 1636#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO 0x0106
2002#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO 0x0107 1637#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO 0x0107
2003#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2 0x0108 1638#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2 0x0108
2004#define PCI_SUBDEVICE_ID_HYPERCOPE_PLEXUS 0x0109
2005 1639
2006#define PCI_VENDOR_ID_KAWASAKI 0x136b 1640#define PCI_VENDOR_ID_KAWASAKI 0x136b
2007#define PCI_DEVICE_ID_MCHIP_KL5A72002 0xff01 1641#define PCI_DEVICE_ID_MCHIP_KL5A72002 0xff01
@@ -2015,12 +1649,9 @@
2015#define PCI_DEVICE_ID_LMC_SSI 0x0005 1649#define PCI_DEVICE_ID_LMC_SSI 0x0005
2016#define PCI_DEVICE_ID_LMC_T1 0x0006 1650#define PCI_DEVICE_ID_LMC_T1 0x0006
2017 1651
2018#define PCI_VENDOR_ID_MARIAN 0x1382
2019#define PCI_DEVICE_ID_MARIAN_PRODIF_PLUS 0x2048
2020 1652
2021#define PCI_VENDOR_ID_NETGEAR 0x1385 1653#define PCI_VENDOR_ID_NETGEAR 0x1385
2022#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a 1654#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
2023#define PCI_DEVICE_ID_NETGEAR_GA622 0x622a
2024 1655
2025#define PCI_VENDOR_ID_APPLICOM 0x1389 1656#define PCI_VENDOR_ID_APPLICOM 0x1389
2026#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001 1657#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
@@ -2043,9 +1674,6 @@
2043#define PCI_DEVICE_ID_MOXA_CP134U 0x1340 1674#define PCI_DEVICE_ID_MOXA_CP134U 0x1340
2044#define PCI_DEVICE_ID_MOXA_C168 0x1680 1675#define PCI_DEVICE_ID_MOXA_C168 0x1680
2045#define PCI_DEVICE_ID_MOXA_CP168U 0x1681 1676#define PCI_DEVICE_ID_MOXA_CP168U 0x1681
2046#define PCI_DEVICE_ID_MOXA_CP204J 0x2040
2047#define PCI_DEVICE_ID_MOXA_C218 0x2180
2048#define PCI_DEVICE_ID_MOXA_C320 0x3200
2049 1677
2050#define PCI_VENDOR_ID_CCD 0x1397 1678#define PCI_VENDOR_ID_CCD 0x1397
2051#define PCI_DEVICE_ID_CCD_2BD0 0x2bd0 1679#define PCI_DEVICE_ID_CCD_2BD0 0x2bd0
@@ -2066,9 +1694,7 @@
2066 1694
2067#define PCI_VENDOR_ID_MICROGATE 0x13c0 1695#define PCI_VENDOR_ID_MICROGATE 0x13c0
2068#define PCI_DEVICE_ID_MICROGATE_USC 0x0010 1696#define PCI_DEVICE_ID_MICROGATE_USC 0x0010
2069#define PCI_DEVICE_ID_MICROGATE_SCC 0x0020
2070#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 1697#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030
2071#define PCI_DEVICE_ID_MICROGATE_USC2 0x0210
2072 1698
2073#define PCI_VENDOR_ID_3WARE 0x13C1 1699#define PCI_VENDOR_ID_3WARE 0x13C1
2074#define PCI_DEVICE_ID_3WARE_1000 0x1000 1700#define PCI_DEVICE_ID_3WARE_1000 0x1000
@@ -2119,10 +1745,6 @@
2119 1745
2120#define PCI_VENDOR_ID_SAMSUNG 0x144d 1746#define PCI_VENDOR_ID_SAMSUNG 0x144d
2121 1747
2122#define PCI_VENDOR_ID_AIRONET 0x14b9
2123#define PCI_DEVICE_ID_AIRONET_4800_1 0x0001
2124#define PCI_DEVICE_ID_AIRONET_4800 0x4500 // values switched? see
2125#define PCI_DEVICE_ID_AIRONET_4500 0x4800 // drivers/net/aironet4500_card.c
2126 1748
2127#define PCI_VENDOR_ID_TITAN 0x14D2 1749#define PCI_VENDOR_ID_TITAN 0x14D2
2128#define PCI_DEVICE_ID_TITAN_010L 0x8001 1750#define PCI_DEVICE_ID_TITAN_010L 0x8001
@@ -2141,8 +1763,6 @@
2141#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 1763#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400
2142#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 1764#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402
2143 1765
2144#define PCI_VENDOR_ID_SIPACKETS 0x14d9
2145#define PCI_DEVICE_ID_SP_HT 0x0010
2146 1766
2147#define PCI_VENDOR_ID_AFAVLAB 0x14db 1767#define PCI_VENDOR_ID_AFAVLAB 0x14db
2148#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 1768#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180
@@ -2207,8 +1827,6 @@
2207 1827
2208#define PCI_VENDOR_ID_CHELSIO 0x1425 1828#define PCI_VENDOR_ID_CHELSIO 0x1425
2209 1829
2210#define PCI_VENDOR_ID_MIPS 0x153f
2211#define PCI_DEVICE_ID_SOC_IT 0x0001
2212 1830
2213#define PCI_VENDOR_ID_SYBA 0x1592 1831#define PCI_VENDOR_ID_SYBA 0x1592
2214#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 1832#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782
@@ -2228,15 +1846,7 @@
2228#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 1846#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274
2229 1847
2230#define PCI_VENDOR_ID_PDC 0x15e9 1848#define PCI_VENDOR_ID_PDC 0x15e9
2231#define PCI_DEVICE_ID_PDC_1841 0x1841
2232 1849
2233#define PCI_VENDOR_ID_MACROLINK 0x15ed
2234#define PCI_DEVICE_ID_MACROLINK_MCCS8 0x1000
2235#define PCI_DEVICE_ID_MACROLINK_MCCS 0x1001
2236#define PCI_DEVICE_ID_MACROLINK_MCCS8H 0x1002
2237#define PCI_DEVICE_ID_MACROLINK_MCCSH 0x1003
2238#define PCI_DEVICE_ID_MACROLINK_MCCR8 0x2000
2239#define PCI_DEVICE_ID_MACROLINK_MCCR 0x2001
2240 1850
2241#define PCI_VENDOR_ID_FARSITE 0x1619 1851#define PCI_VENDOR_ID_FARSITE 0x1619
2242#define PCI_DEVICE_ID_FARSITE_T2P 0x0400 1852#define PCI_DEVICE_ID_FARSITE_T2P 0x0400
@@ -2254,7 +1864,6 @@
2254#define PCI_DEVICE_ID_REVOLUTION 0x0044 1864#define PCI_DEVICE_ID_REVOLUTION 0x0044
2255 1865
2256#define PCI_VENDOR_ID_LINKSYS 0x1737 1866#define PCI_VENDOR_ID_LINKSYS 0x1737
2257#define PCI_DEVICE_ID_LINKSYS_EG1032 0x1032
2258#define PCI_DEVICE_ID_LINKSYS_EG1064 0x1064 1867#define PCI_DEVICE_ID_LINKSYS_EG1064 0x1064
2259 1868
2260#define PCI_VENDOR_ID_ALTIMA 0x173b 1869#define PCI_VENDOR_ID_ALTIMA 0x173b
@@ -2269,7 +1878,6 @@
2269#define PCI_DEVICE_ID_HERC_WIN 0x5732 1878#define PCI_DEVICE_ID_HERC_WIN 0x5732
2270#define PCI_DEVICE_ID_HERC_UNI 0x5832 1879#define PCI_DEVICE_ID_HERC_UNI 0x5832
2271 1880
2272#define PCI_VENDOR_ID_INFINICON 0x1820
2273 1881
2274#define PCI_VENDOR_ID_SITECOM 0x182d 1882#define PCI_VENDOR_ID_SITECOM 0x182d
2275#define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069 1883#define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069
@@ -2279,8 +1887,6 @@
2279#define PCI_VENDOR_ID_TDI 0x192E 1887#define PCI_VENDOR_ID_TDI 0x192E
2280#define PCI_DEVICE_ID_TDI_EHCI 0x0101 1888#define PCI_DEVICE_ID_TDI_EHCI 0x0101
2281 1889
2282#define PCI_VENDOR_ID_SYMPHONY 0x1c1c
2283#define PCI_DEVICE_ID_SYMPHONY_101 0x0001
2284 1890
2285#define PCI_VENDOR_ID_TEKRAM 0x1de1 1891#define PCI_VENDOR_ID_TEKRAM 0x1de1
2286#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 1892#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
@@ -2289,70 +1895,33 @@
2289#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 1895#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013
2290 1896
2291#define PCI_VENDOR_ID_3DLABS 0x3d3d 1897#define PCI_VENDOR_ID_3DLABS 0x3d3d
2292#define PCI_DEVICE_ID_3DLABS_300SX 0x0001
2293#define PCI_DEVICE_ID_3DLABS_500TX 0x0002
2294#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003
2295#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004
2296#define PCI_DEVICE_ID_3DLABS_MX 0x0006
2297#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007 1898#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007
2298#define PCI_DEVICE_ID_3DLABS_GAMMA 0x0008
2299#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009 1899#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009
2300 1900
2301#define PCI_VENDOR_ID_AVANCE 0x4005
2302#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064
2303#define PCI_DEVICE_ID_AVANCE_2302 0x2302
2304 1901
2305#define PCI_VENDOR_ID_AKS 0x416c 1902#define PCI_VENDOR_ID_AKS 0x416c
2306#define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100 1903#define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100
2307#define PCI_DEVICE_ID_AKS_CPC 0x0200
2308 1904
2309#define PCI_VENDOR_ID_REDCREEK 0x4916
2310#define PCI_DEVICE_ID_RC45 0x1960
2311 1905
2312#define PCI_VENDOR_ID_NETVIN 0x4a14
2313#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000
2314 1906
2315#define PCI_VENDOR_ID_S3 0x5333 1907#define PCI_VENDOR_ID_S3 0x5333
2316#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551
2317#define PCI_DEVICE_ID_S3_ViRGE 0x5631
2318#define PCI_DEVICE_ID_S3_TRIO 0x8811 1908#define PCI_DEVICE_ID_S3_TRIO 0x8811
2319#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812
2320#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814
2321#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d
2322#define PCI_DEVICE_ID_S3_868 0x8880 1909#define PCI_DEVICE_ID_S3_868 0x8880
2323#define PCI_DEVICE_ID_S3_928 0x88b0
2324#define PCI_DEVICE_ID_S3_864_1 0x88c0
2325#define PCI_DEVICE_ID_S3_864_2 0x88c1
2326#define PCI_DEVICE_ID_S3_964_1 0x88d0
2327#define PCI_DEVICE_ID_S3_964_2 0x88d1
2328#define PCI_DEVICE_ID_S3_968 0x88f0 1910#define PCI_DEVICE_ID_S3_968 0x88f0
2329#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901
2330#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902
2331#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01
2332#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10
2333#define PCI_DEVICE_ID_S3_SAVAGE4 0x8a25 1911#define PCI_DEVICE_ID_S3_SAVAGE4 0x8a25
2334#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01
2335#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02
2336#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03
2337#define PCI_DEVICE_ID_S3_PROSAVAGE8 0x8d04 1912#define PCI_DEVICE_ID_S3_PROSAVAGE8 0x8d04
2338#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 1913#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00
2339 1914
2340#define PCI_VENDOR_ID_DUNORD 0x5544 1915#define PCI_VENDOR_ID_DUNORD 0x5544
2341#define PCI_DEVICE_ID_DUNORD_I3000 0x0001 1916#define PCI_DEVICE_ID_DUNORD_I3000 0x0001
2342 1917
1918
2343#define PCI_VENDOR_ID_DCI 0x6666 1919#define PCI_VENDOR_ID_DCI 0x6666
2344#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 1920#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001
2345#define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 1921#define PCI_DEVICE_ID_DCI_PCCOM8 0x0002
2346 1922
2347#define PCI_VENDOR_ID_DUNORD 0x5544
2348#define PCI_DEVICE_ID_DUNORD_I3000 0x0001
2349
2350#define PCI_VENDOR_ID_GENROCO 0x5555
2351#define PCI_DEVICE_ID_GENROCO_HFP832 0x0003
2352
2353#define PCI_VENDOR_ID_INTEL 0x8086 1923#define PCI_VENDOR_ID_INTEL 0x8086
2354#define PCI_DEVICE_ID_INTEL_EESSC 0x0008 1924#define PCI_DEVICE_ID_INTEL_EESSC 0x0008
2355#define PCI_DEVICE_ID_INTEL_21145 0x0039
2356#define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320 1925#define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320
2357#define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321 1926#define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321
2358#define PCI_DEVICE_ID_INTEL_PXH_0 0x0329 1927#define PCI_DEVICE_ID_INTEL_PXH_0 0x0329
@@ -2361,30 +1930,17 @@
2361#define PCI_DEVICE_ID_INTEL_82375 0x0482 1930#define PCI_DEVICE_ID_INTEL_82375 0x0482
2362#define PCI_DEVICE_ID_INTEL_82424 0x0483 1931#define PCI_DEVICE_ID_INTEL_82424 0x0483
2363#define PCI_DEVICE_ID_INTEL_82378 0x0484 1932#define PCI_DEVICE_ID_INTEL_82378 0x0484
2364#define PCI_DEVICE_ID_INTEL_82430 0x0486
2365#define PCI_DEVICE_ID_INTEL_82434 0x04a3
2366#define PCI_DEVICE_ID_INTEL_I960 0x0960 1933#define PCI_DEVICE_ID_INTEL_I960 0x0960
2367#define PCI_DEVICE_ID_INTEL_I960RM 0x0962 1934#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
2368#define PCI_DEVICE_ID_INTEL_82562ET 0x1031
2369#define PCI_DEVICE_ID_INTEL_82801CAM 0x1038
2370#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130 1935#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130
2371#define PCI_DEVICE_ID_INTEL_82815_AB 0x1131
2372#define PCI_DEVICE_ID_INTEL_82815_CGC 0x1132 1936#define PCI_DEVICE_ID_INTEL_82815_CGC 0x1132
2373#define PCI_DEVICE_ID_INTEL_82559ER 0x1209
2374#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 1937#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221
2375#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222
2376#define PCI_DEVICE_ID_INTEL_7116 0x1223
2377#define PCI_DEVICE_ID_INTEL_7505_0 0x2550 1938#define PCI_DEVICE_ID_INTEL_7505_0 0x2550
2378#define PCI_DEVICE_ID_INTEL_7505_1 0x2552
2379#define PCI_DEVICE_ID_INTEL_7205_0 0x255d 1939#define PCI_DEVICE_ID_INTEL_7205_0 0x255d
2380#define PCI_DEVICE_ID_INTEL_82596 0x1226
2381#define PCI_DEVICE_ID_INTEL_82865 0x1227
2382#define PCI_DEVICE_ID_INTEL_82557 0x1229
2383#define PCI_DEVICE_ID_INTEL_82437 0x122d 1940#define PCI_DEVICE_ID_INTEL_82437 0x122d
2384#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e 1941#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e
2385#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 1942#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230
2386#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 1943#define PCI_DEVICE_ID_INTEL_82371MX 0x1234
2387#define PCI_DEVICE_ID_INTEL_82437MX 0x1235
2388#define PCI_DEVICE_ID_INTEL_82441 0x1237 1944#define PCI_DEVICE_ID_INTEL_82441 0x1237
2389#define PCI_DEVICE_ID_INTEL_82380FB 0x124b 1945#define PCI_DEVICE_ID_INTEL_82380FB 0x124b
2390#define PCI_DEVICE_ID_INTEL_82439 0x1250 1946#define PCI_DEVICE_ID_INTEL_82439 0x1250
@@ -2393,83 +1949,53 @@
2393#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 1949#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30
2394#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 1950#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
2395#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 1951#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411
2396#define PCI_DEVICE_ID_INTEL_82801AA_2 0x2412
2397#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 1952#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413
2398#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 1953#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415
2399#define PCI_DEVICE_ID_INTEL_82801AA_6 0x2416 1954#define PCI_DEVICE_ID_INTEL_82801AA_6 0x2416
2400#define PCI_DEVICE_ID_INTEL_82801AA_8 0x2418 1955#define PCI_DEVICE_ID_INTEL_82801AA_8 0x2418
2401#define PCI_DEVICE_ID_INTEL_82801AB_0 0x2420 1956#define PCI_DEVICE_ID_INTEL_82801AB_0 0x2420
2402#define PCI_DEVICE_ID_INTEL_82801AB_1 0x2421 1957#define PCI_DEVICE_ID_INTEL_82801AB_1 0x2421
2403#define PCI_DEVICE_ID_INTEL_82801AB_2 0x2422
2404#define PCI_DEVICE_ID_INTEL_82801AB_3 0x2423 1958#define PCI_DEVICE_ID_INTEL_82801AB_3 0x2423
2405#define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425 1959#define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425
2406#define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426 1960#define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426
2407#define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428 1961#define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428
2408#define PCI_DEVICE_ID_INTEL_82801BA_0 0x2440 1962#define PCI_DEVICE_ID_INTEL_82801BA_0 0x2440
2409#define PCI_DEVICE_ID_INTEL_82801BA_1 0x2442
2410#define PCI_DEVICE_ID_INTEL_82801BA_2 0x2443 1963#define PCI_DEVICE_ID_INTEL_82801BA_2 0x2443
2411#define PCI_DEVICE_ID_INTEL_82801BA_3 0x2444
2412#define PCI_DEVICE_ID_INTEL_82801BA_4 0x2445 1964#define PCI_DEVICE_ID_INTEL_82801BA_4 0x2445
2413#define PCI_DEVICE_ID_INTEL_82801BA_5 0x2446
2414#define PCI_DEVICE_ID_INTEL_82801BA_6 0x2448 1965#define PCI_DEVICE_ID_INTEL_82801BA_6 0x2448
2415#define PCI_DEVICE_ID_INTEL_82801BA_7 0x2449
2416#define PCI_DEVICE_ID_INTEL_82801BA_8 0x244a 1966#define PCI_DEVICE_ID_INTEL_82801BA_8 0x244a
2417#define PCI_DEVICE_ID_INTEL_82801BA_9 0x244b 1967#define PCI_DEVICE_ID_INTEL_82801BA_9 0x244b
2418#define PCI_DEVICE_ID_INTEL_82801BA_10 0x244c 1968#define PCI_DEVICE_ID_INTEL_82801BA_10 0x244c
2419#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e 1969#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e
2420#define PCI_DEVICE_ID_INTEL_82801E_0 0x2450 1970#define PCI_DEVICE_ID_INTEL_82801E_0 0x2450
2421#define PCI_DEVICE_ID_INTEL_82801E_2 0x2452
2422#define PCI_DEVICE_ID_INTEL_82801E_3 0x2453
2423#define PCI_DEVICE_ID_INTEL_82801E_9 0x2459
2424#define PCI_DEVICE_ID_INTEL_82801E_11 0x245b 1971#define PCI_DEVICE_ID_INTEL_82801E_11 0x245b
2425#define PCI_DEVICE_ID_INTEL_82801E_13 0x245d
2426#define PCI_DEVICE_ID_INTEL_82801E_14 0x245e
2427#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480 1972#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480
2428#define PCI_DEVICE_ID_INTEL_82801CA_2 0x2482
2429#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483 1973#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483
2430#define PCI_DEVICE_ID_INTEL_82801CA_4 0x2484
2431#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485 1974#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485
2432#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486 1975#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486
2433#define PCI_DEVICE_ID_INTEL_82801CA_7 0x2487
2434#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a 1976#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a
2435#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b 1977#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b
2436#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c 1978#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c
2437#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0 1979#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0
2438#define PCI_DEVICE_ID_INTEL_82801DB_1 0x24c1 1980#define PCI_DEVICE_ID_INTEL_82801DB_1 0x24c1
2439#define PCI_DEVICE_ID_INTEL_82801DB_2 0x24c2
2440#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3 1981#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
2441#define PCI_DEVICE_ID_INTEL_82801DB_4 0x24c4
2442#define PCI_DEVICE_ID_INTEL_82801DB_5 0x24c5 1982#define PCI_DEVICE_ID_INTEL_82801DB_5 0x24c5
2443#define PCI_DEVICE_ID_INTEL_82801DB_6 0x24c6 1983#define PCI_DEVICE_ID_INTEL_82801DB_6 0x24c6
2444#define PCI_DEVICE_ID_INTEL_82801DB_7 0x24c7
2445#define PCI_DEVICE_ID_INTEL_82801DB_9 0x24c9 1984#define PCI_DEVICE_ID_INTEL_82801DB_9 0x24c9
2446#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca 1985#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca
2447#define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb 1986#define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb
2448#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc 1987#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc
2449#define PCI_DEVICE_ID_INTEL_82801DB_13 0x24cd
2450#define PCI_DEVICE_ID_INTEL_82801EB_0 0x24d0 1988#define PCI_DEVICE_ID_INTEL_82801EB_0 0x24d0
2451#define PCI_DEVICE_ID_INTEL_82801EB_1 0x24d1 1989#define PCI_DEVICE_ID_INTEL_82801EB_1 0x24d1
2452#define PCI_DEVICE_ID_INTEL_82801EB_2 0x24d2
2453#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3 1990#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3
2454#define PCI_DEVICE_ID_INTEL_82801EB_4 0x24d4
2455#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5 1991#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5
2456#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6 1992#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6
2457#define PCI_DEVICE_ID_INTEL_82801EB_7 0x24d7
2458#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db 1993#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db
2459#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd
2460#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1 1994#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1
2461#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2 1995#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2
2462#define PCI_DEVICE_ID_INTEL_ESB_3 0x25a3
2463#define PCI_DEVICE_ID_INTEL_ESB_31 0x25b0
2464#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4 1996#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4
2465#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6 1997#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
2466#define PCI_DEVICE_ID_INTEL_ESB_6 0x25a7
2467#define PCI_DEVICE_ID_INTEL_ESB_7 0x25a9
2468#define PCI_DEVICE_ID_INTEL_ESB_8 0x25aa
2469#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab 1998#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
2470#define PCI_DEVICE_ID_INTEL_ESB_11 0x25ac
2471#define PCI_DEVICE_ID_INTEL_ESB_12 0x25ad
2472#define PCI_DEVICE_ID_INTEL_ESB_13 0x25ae
2473#define PCI_DEVICE_ID_INTEL_82820_HB 0x2500 1999#define PCI_DEVICE_ID_INTEL_82820_HB 0x2500
2474#define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501 2000#define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501
2475#define PCI_DEVICE_ID_INTEL_82850_HB 0x2530 2001#define PCI_DEVICE_ID_INTEL_82850_HB 0x2530
@@ -2479,7 +2005,6 @@
2479#define PCI_DEVICE_ID_INTEL_82865_HB 0x2570 2005#define PCI_DEVICE_ID_INTEL_82865_HB 0x2570
2480#define PCI_DEVICE_ID_INTEL_82865_IG 0x2572 2006#define PCI_DEVICE_ID_INTEL_82865_IG 0x2572
2481#define PCI_DEVICE_ID_INTEL_82875_HB 0x2578 2007#define PCI_DEVICE_ID_INTEL_82875_HB 0x2578
2482#define PCI_DEVICE_ID_INTEL_82875_IG 0x257b
2483#define PCI_DEVICE_ID_INTEL_82915G_HB 0x2580 2008#define PCI_DEVICE_ID_INTEL_82915G_HB 0x2580
2484#define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582 2009#define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582
2485#define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590 2010#define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590
@@ -2489,80 +2014,23 @@
2489#define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640 2014#define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640
2490#define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641 2015#define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641
2491#define PCI_DEVICE_ID_INTEL_ICH6_2 0x2642 2016#define PCI_DEVICE_ID_INTEL_ICH6_2 0x2642
2492#define PCI_DEVICE_ID_INTEL_ICH6_3 0x2651
2493#define PCI_DEVICE_ID_INTEL_ICH6_4 0x2652
2494#define PCI_DEVICE_ID_INTEL_ICH6_5 0x2653
2495#define PCI_DEVICE_ID_INTEL_ICH6_6 0x2658
2496#define PCI_DEVICE_ID_INTEL_ICH6_7 0x2659
2497#define PCI_DEVICE_ID_INTEL_ICH6_8 0x265a
2498#define PCI_DEVICE_ID_INTEL_ICH6_9 0x265b
2499#define PCI_DEVICE_ID_INTEL_ICH6_10 0x265c
2500#define PCI_DEVICE_ID_INTEL_ICH6_11 0x2660
2501#define PCI_DEVICE_ID_INTEL_ICH6_12 0x2662
2502#define PCI_DEVICE_ID_INTEL_ICH6_13 0x2664
2503#define PCI_DEVICE_ID_INTEL_ICH6_14 0x2666
2504#define PCI_DEVICE_ID_INTEL_ICH6_15 0x2668
2505#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a 2017#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a
2506#define PCI_DEVICE_ID_INTEL_ICH6_17 0x266d 2018#define PCI_DEVICE_ID_INTEL_ICH6_17 0x266d
2507#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e 2019#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e
2508#define PCI_DEVICE_ID_INTEL_ICH6_19 0x266f 2020#define PCI_DEVICE_ID_INTEL_ICH6_19 0x266f
2509#define PCI_DEVICE_ID_INTEL_ESB2_0 0x2670 2021#define PCI_DEVICE_ID_INTEL_ESB2_0 0x2670
2510#define PCI_DEVICE_ID_INTEL_ESB2_1 0x2680
2511#define PCI_DEVICE_ID_INTEL_ESB2_2 0x2681
2512#define PCI_DEVICE_ID_INTEL_ESB2_3 0x2682
2513#define PCI_DEVICE_ID_INTEL_ESB2_4 0x2683
2514#define PCI_DEVICE_ID_INTEL_ESB2_5 0x2688
2515#define PCI_DEVICE_ID_INTEL_ESB2_6 0x2689
2516#define PCI_DEVICE_ID_INTEL_ESB2_7 0x268a
2517#define PCI_DEVICE_ID_INTEL_ESB2_8 0x268b
2518#define PCI_DEVICE_ID_INTEL_ESB2_9 0x268c
2519#define PCI_DEVICE_ID_INTEL_ESB2_10 0x2690
2520#define PCI_DEVICE_ID_INTEL_ESB2_11 0x2692
2521#define PCI_DEVICE_ID_INTEL_ESB2_12 0x2694
2522#define PCI_DEVICE_ID_INTEL_ESB2_13 0x2696
2523#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698 2022#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698
2524#define PCI_DEVICE_ID_INTEL_ESB2_15 0x2699
2525#define PCI_DEVICE_ID_INTEL_ESB2_16 0x269a
2526#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b 2023#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b
2527#define PCI_DEVICE_ID_INTEL_ESB2_18 0x269e 2024#define PCI_DEVICE_ID_INTEL_ESB2_18 0x269e
2528#define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b8 2025#define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b8
2529#define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9 2026#define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9
2530#define PCI_DEVICE_ID_INTEL_ICH7_2 0x27c0
2531#define PCI_DEVICE_ID_INTEL_ICH7_3 0x27c1
2532#define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0 2027#define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0
2533#define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd 2028#define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd
2534#define PCI_DEVICE_ID_INTEL_ICH7_5 0x27c4
2535#define PCI_DEVICE_ID_INTEL_ICH7_6 0x27c5
2536#define PCI_DEVICE_ID_INTEL_ICH7_7 0x27c8
2537#define PCI_DEVICE_ID_INTEL_ICH7_8 0x27c9
2538#define PCI_DEVICE_ID_INTEL_ICH7_9 0x27ca
2539#define PCI_DEVICE_ID_INTEL_ICH7_10 0x27cb
2540#define PCI_DEVICE_ID_INTEL_ICH7_11 0x27cc
2541#define PCI_DEVICE_ID_INTEL_ICH7_12 0x27d0
2542#define PCI_DEVICE_ID_INTEL_ICH7_13 0x27d2
2543#define PCI_DEVICE_ID_INTEL_ICH7_14 0x27d4
2544#define PCI_DEVICE_ID_INTEL_ICH7_15 0x27d6
2545#define PCI_DEVICE_ID_INTEL_ICH7_16 0x27d8
2546#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da 2029#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da
2547#define PCI_DEVICE_ID_INTEL_ICH7_18 0x27dc
2548#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd 2030#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd
2549#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de 2031#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
2550#define PCI_DEVICE_ID_INTEL_ICH7_21 0x27df 2032#define PCI_DEVICE_ID_INTEL_ICH7_21 0x27df
2551#define PCI_DEVICE_ID_INTEL_ICH7_22 0x27e0
2552#define PCI_DEVICE_ID_INTEL_ICH7_23 0x27e2
2553#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340 2033#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340
2554#define PCI_DEVICE_ID_INTEL_ESB2_19 0x3500
2555#define PCI_DEVICE_ID_INTEL_ESB2_20 0x3501
2556#define PCI_DEVICE_ID_INTEL_ESB2_21 0x3504
2557#define PCI_DEVICE_ID_INTEL_ESB2_22 0x3505
2558#define PCI_DEVICE_ID_INTEL_ESB2_23 0x350c
2559#define PCI_DEVICE_ID_INTEL_ESB2_24 0x350d
2560#define PCI_DEVICE_ID_INTEL_ESB2_25 0x3510
2561#define PCI_DEVICE_ID_INTEL_ESB2_26 0x3511
2562#define PCI_DEVICE_ID_INTEL_ESB2_27 0x3514
2563#define PCI_DEVICE_ID_INTEL_ESB2_28 0x3515
2564#define PCI_DEVICE_ID_INTEL_ESB2_29 0x3518
2565#define PCI_DEVICE_ID_INTEL_ESB2_30 0x3519
2566#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575 2034#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575
2567#define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 2035#define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577
2568#define PCI_DEVICE_ID_INTEL_82855GM_HB 0x3580 2036#define PCI_DEVICE_ID_INTEL_82855GM_HB 0x3580
@@ -2576,7 +2044,6 @@
2576#define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599 2044#define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599
2577#define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a 2045#define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a
2578#define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e 2046#define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e
2579#define PCI_DEVICE_ID_INTEL_80310 0x530d
2580#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 2047#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
2581#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 2048#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
2582#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 2049#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
@@ -2601,22 +2068,15 @@
2601#define PCI_DEVICE_ID_INTEL_440MX_6 0x7196 2068#define PCI_DEVICE_ID_INTEL_440MX_6 0x7196
2602#define PCI_DEVICE_ID_INTEL_82443MX_0 0x7198 2069#define PCI_DEVICE_ID_INTEL_82443MX_0 0x7198
2603#define PCI_DEVICE_ID_INTEL_82443MX_1 0x7199 2070#define PCI_DEVICE_ID_INTEL_82443MX_1 0x7199
2604#define PCI_DEVICE_ID_INTEL_82443MX_2 0x719a
2605#define PCI_DEVICE_ID_INTEL_82443MX_3 0x719b 2071#define PCI_DEVICE_ID_INTEL_82443MX_3 0x719b
2606#define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0 2072#define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0
2607#define PCI_DEVICE_ID_INTEL_82443GX_1 0x71a1
2608#define PCI_DEVICE_ID_INTEL_82443GX_2 0x71a2 2073#define PCI_DEVICE_ID_INTEL_82443GX_2 0x71a2
2609#define PCI_DEVICE_ID_INTEL_82372FB_0 0x7600
2610#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 2074#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601
2611#define PCI_DEVICE_ID_INTEL_82372FB_2 0x7602
2612#define PCI_DEVICE_ID_INTEL_82372FB_3 0x7603
2613#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 2075#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4
2614#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5
2615#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca 2076#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca
2616#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb 2077#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb
2617#define PCI_DEVICE_ID_INTEL_84460GX 0x84ea 2078#define PCI_DEVICE_ID_INTEL_84460GX 0x84ea
2618#define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500 2079#define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500
2619#define PCI_DEVICE_ID_INTEL_IXP2400 0x9001
2620#define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 2080#define PCI_DEVICE_ID_INTEL_IXP2800 0x9004
2621#define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 2081#define PCI_DEVICE_ID_INTEL_S21152BB 0xb152
2622 2082
@@ -2629,7 +2089,6 @@
2629#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003 2089#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003
2630 2090
2631#define PCI_VENDOR_ID_KTI 0x8e2e 2091#define PCI_VENDOR_ID_KTI 0x8e2e
2632#define PCI_DEVICE_ID_KTI_ET32P2 0x3000
2633 2092
2634#define PCI_VENDOR_ID_ADAPTEC 0x9004 2093#define PCI_VENDOR_ID_ADAPTEC 0x9004
2635#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 2094#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078
@@ -2637,7 +2096,6 @@
2637#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860 2096#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860
2638#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 2097#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078
2639#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 2098#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578
2640#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800
2641#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038 2099#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038
2642#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 2100#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075
2643#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 2101#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078
@@ -2657,7 +2115,6 @@
2657#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678 2115#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678
2658#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 2116#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778
2659#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 2117#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878
2660#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78
2661 2118
2662#define PCI_VENDOR_ID_ADAPTEC2 0x9005 2119#define PCI_VENDOR_ID_ADAPTEC2 0x9005
2663#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 2120#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010
@@ -2677,8 +2134,6 @@
2677#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf 2134#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf
2678#define PCI_DEVICE_ID_ADAPTEC2_SCAMP 0x0503 2135#define PCI_DEVICE_ID_ADAPTEC2_SCAMP 0x0503
2679 2136
2680#define PCI_VENDOR_ID_ATRONICS 0x907f
2681#define PCI_DEVICE_ID_ATRONICS_2015 0x2015
2682 2137
2683#define PCI_VENDOR_ID_HOLTEK 0x9412 2138#define PCI_VENDOR_ID_HOLTEK 0x9412
2684#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 2139#define PCI_DEVICE_ID_HOLTEK_6565 0x6565
@@ -2711,7 +2166,3 @@
2711#define PCI_DEVICE_ID_RME_DIGI32_PRO 0x9897 2166#define PCI_DEVICE_ID_RME_DIGI32_PRO 0x9897
2712#define PCI_DEVICE_ID_RME_DIGI32_8 0x9898 2167#define PCI_DEVICE_ID_RME_DIGI32_8 0x9898
2713 2168
2714#define PCI_VENDOR_ID_ARK 0xedd8
2715#define PCI_DEVICE_ID_ARK_STING 0xa091
2716#define PCI_DEVICE_ID_ARK_STINGARK 0xa099
2717#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1
diff --git a/sound/oss/ymfpci.c b/sound/oss/ymfpci.c
index 05203ad523f7..8dae59bd05a2 100644
--- a/sound/oss/ymfpci.c
+++ b/sound/oss/ymfpci.c
@@ -107,14 +107,15 @@ static LIST_HEAD(ymf_devs);
107 */ 107 */
108 108
109static struct pci_device_id ymf_id_tbl[] = { 109static struct pci_device_id ymf_id_tbl[] = {
110#define DEV(v, d, data) \ 110#define DEV(dev, data) \
111 { PCI_VENDOR_ID_##v, PCI_DEVICE_ID_##v##_##d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long)data } 111 { PCI_VENDOR_ID_YAMAHA, dev, PCI_ANY_ID, PCI_ANY_ID, 0, 0, \
112 DEV (YAMAHA, 724, "YMF724"), 112 (unsigned long)data }
113 DEV (YAMAHA, 724F, "YMF724F"), 113 DEV (PCI_DEVICE_ID_YAMAHA_724, "YMF724"),
114 DEV (YAMAHA, 740, "YMF740"), 114 DEV (PCI_DEVICE_ID_YAMAHA_724F, "YMF724F"),
115 DEV (YAMAHA, 740C, "YMF740C"), 115 DEV (PCI_DEVICE_ID_YAMAHA_740, "YMF740"),
116 DEV (YAMAHA, 744, "YMF744"), 116 DEV (PCI_DEVICE_ID_YAMAHA_740C, "YMF740C"),
117 DEV (YAMAHA, 754, "YMF754"), 117 DEV (PCI_DEVICE_ID_YAMAHA_744, "YMF744"),
118 DEV (PCI_DEVICE_ID_YAMAHA_754, "YMF754"),
118#undef DEV 119#undef DEV
119 { } 120 { }
120}; 121};
diff --git a/sound/pci/bt87x.c b/sound/pci/bt87x.c
index 2236c958aec0..01d98eeb242e 100644
--- a/sound/pci/bt87x.c
+++ b/sound/pci/bt87x.c
@@ -761,15 +761,18 @@ static int __devinit snd_bt87x_create(snd_card_t *card,
761 761
762#define BT_DEVICE(chip, subvend, subdev, rate) \ 762#define BT_DEVICE(chip, subvend, subdev, rate) \
763 { .vendor = PCI_VENDOR_ID_BROOKTREE, \ 763 { .vendor = PCI_VENDOR_ID_BROOKTREE, \
764 .device = PCI_DEVICE_ID_BROOKTREE_##chip, \ 764 .device = chip, \
765 .subvendor = subvend, .subdevice = subdev, \ 765 .subvendor = subvend, .subdevice = subdev, \
766 .driver_data = rate } 766 .driver_data = rate }
767 767
768/* driver_data is the default digital_rate value for that device */ 768/* driver_data is the default digital_rate value for that device */
769static struct pci_device_id snd_bt87x_ids[] = { 769static struct pci_device_id snd_bt87x_ids[] = {
770 BT_DEVICE(878, 0x0070, 0x13eb, 32000), /* Hauppauge WinTV series */ 770 /* Hauppauge WinTV series */
771 BT_DEVICE(879, 0x0070, 0x13eb, 32000), /* Hauppauge WinTV series */ 771 BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x0070, 0x13eb, 32000),
772 BT_DEVICE(878, 0x0070, 0xff01, 44100), /* Viewcast Osprey 200 */ 772 /* Hauppauge WinTV series */
773 BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_879, 0x0070, 0x13eb, 32000),
774 /* Viewcast Osprey 200 */
775 BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x0070, 0xff01, 44100),
773 { } 776 { }
774}; 777};
775MODULE_DEVICE_TABLE(pci, snd_bt87x_ids); 778MODULE_DEVICE_TABLE(pci, snd_bt87x_ids);
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-30 23:51:32 -0400