diff options
| -rw-r--r-- | arch/arm/mach-omap2/memory.c | 40 |
1 files changed, 5 insertions, 35 deletions
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index f173aa8d896f..3e5d8cd4ea4f 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c | |||
| @@ -30,37 +30,6 @@ | |||
| 30 | #include "prcm-regs.h" | 30 | #include "prcm-regs.h" |
| 31 | #include "memory.h" | 31 | #include "memory.h" |
| 32 | 32 | ||
| 33 | #define SMS_BASE 0x68008000 | ||
| 34 | #define SMS_SYSCONFIG 0x010 | ||
| 35 | |||
| 36 | #define SDRC_BASE 0x68009000 | ||
| 37 | #define SDRC_SYSCONFIG 0x010 | ||
| 38 | #define SDRC_SYSSTATUS 0x014 | ||
| 39 | |||
| 40 | static const u32 sms_base = IO_ADDRESS(SMS_BASE); | ||
| 41 | static const u32 sdrc_base = IO_ADDRESS(SDRC_BASE); | ||
| 42 | |||
| 43 | |||
| 44 | static inline void sms_write_reg(int idx, u32 val) | ||
| 45 | { | ||
| 46 | __raw_writel(val, sms_base + idx); | ||
| 47 | } | ||
| 48 | |||
| 49 | static inline u32 sms_read_reg(int idx) | ||
| 50 | { | ||
| 51 | return __raw_readl(sms_base + idx); | ||
| 52 | } | ||
| 53 | |||
| 54 | static inline void sdrc_write_reg(int idx, u32 val) | ||
| 55 | { | ||
| 56 | __raw_writel(val, sdrc_base + idx); | ||
| 57 | } | ||
| 58 | |||
| 59 | static inline u32 sdrc_read_reg(int idx) | ||
| 60 | { | ||
| 61 | return __raw_readl(sdrc_base + idx); | ||
| 62 | } | ||
| 63 | |||
| 64 | 33 | ||
| 65 | static struct memory_timings mem_timings; | 34 | static struct memory_timings mem_timings; |
| 66 | 35 | ||
| @@ -132,18 +101,19 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) | |||
| 132 | mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); | 101 | mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); |
| 133 | } | 102 | } |
| 134 | 103 | ||
| 104 | /* turn on smart idle modes for SDRAM scheduler and controller */ | ||
| 135 | void __init omap2_init_memory(void) | 105 | void __init omap2_init_memory(void) |
| 136 | { | 106 | { |
| 137 | u32 l; | 107 | u32 l; |
| 138 | 108 | ||
| 139 | l = sms_read_reg(SMS_SYSCONFIG); | 109 | l = SMS_SYSCONFIG; |
| 140 | l &= ~(0x3 << 3); | 110 | l &= ~(0x3 << 3); |
| 141 | l |= (0x2 << 3); | 111 | l |= (0x2 << 3); |
| 142 | sms_write_reg(SMS_SYSCONFIG, l); | 112 | SMS_SYSCONFIG = l; |
| 143 | 113 | ||
| 144 | l = sdrc_read_reg(SDRC_SYSCONFIG); | 114 | l = SDRC_SYSCONFIG; |
| 145 | l &= ~(0x3 << 3); | 115 | l &= ~(0x3 << 3); |
| 146 | l |= (0x2 << 3); | 116 | l |= (0x2 << 3); |
| 147 | sdrc_write_reg(SDRC_SYSCONFIG, l); | 117 | SDRC_SYSCONFIG = l; |
| 148 | 118 | ||
| 149 | } | 119 | } |
