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-rw-r--r--arch/sh/include/asm/clkdev.h35
-rw-r--r--arch/sh/include/asm/clock.h7
-rw-r--r--arch/sh/include/asm/dmaengine.h63
-rw-r--r--arch/sh/include/asm/siu.h8
-rw-r--r--arch/sh/kernel/Makefile2
-rw-r--r--arch/sh/kernel/clkdev.c169
-rw-r--r--arch/sh/kernel/cpu/clock-cpg.c5
-rw-r--r--arch/sh/kernel/cpu/clock.c55
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c9
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c9
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c12
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c15
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c9
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c9
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c9
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c24
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c9
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c15
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c9
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7343.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c58
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c56
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c51
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c80
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c16
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c13
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c15
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c27
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c27
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c18
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c27
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c18
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c24
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c36
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c18
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c9
-rw-r--r--drivers/base/platform.c20
-rw-r--r--drivers/clocksource/sh_cmt.c42
-rw-r--r--drivers/clocksource/sh_mtu2.c34
-rw-r--r--drivers/clocksource/sh_tmu.c38
-rw-r--r--drivers/dma/shdma.c13
-rw-r--r--drivers/dma/shdma.h4
-rw-r--r--drivers/serial/sh-sci.c189
-rw-r--r--drivers/sh/intc.c95
-rw-r--r--include/linux/device.h4
-rw-r--r--include/linux/serial_sci.h4
-rw-r--r--include/linux/sh_dma.h101
-rw-r--r--include/linux/sh_intc.h6
52 files changed, 863 insertions, 697 deletions
diff --git a/arch/sh/include/asm/clkdev.h b/arch/sh/include/asm/clkdev.h
new file mode 100644
index 000000000000..5645f358128b
--- /dev/null
+++ b/arch/sh/include/asm/clkdev.h
@@ -0,0 +1,35 @@
1/*
2 * arch/sh/include/asm/clkdev.h
3 *
4 * Cloned from arch/arm/include/asm/clkdev.h:
5 *
6 * Copyright (C) 2008 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Helper for the clk API to assist looking up a struct clk.
13 */
14#ifndef __ASM_CLKDEV_H
15#define __ASM_CLKDEV_H
16
17struct clk;
18
19struct clk_lookup {
20 struct list_head node;
21 const char *dev_id;
22 const char *con_id;
23 struct clk *clk;
24};
25
26struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
27 const char *dev_fmt, ...);
28
29void clkdev_add(struct clk_lookup *cl);
30void clkdev_drop(struct clk_lookup *cl);
31
32void clkdev_add_table(struct clk_lookup *, size_t);
33int clk_add_alias(const char *, const char *, char *, struct device *);
34
35#endif
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 11da4c5beb68..4b19179230fe 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -45,13 +45,6 @@ struct clk {
45 struct cpufreq_frequency_table *freq_table; 45 struct cpufreq_frequency_table *freq_table;
46}; 46};
47 47
48struct clk_lookup {
49 struct list_head node;
50 const char *dev_id;
51 const char *con_id;
52 struct clk *clk;
53};
54
55#define CLK_ENABLE_ON_INIT (1 << 0) 48#define CLK_ENABLE_ON_INIT (1 << 0)
56 49
57/* Should be defined by processor-specific code */ 50/* Should be defined by processor-specific code */
diff --git a/arch/sh/include/asm/dmaengine.h b/arch/sh/include/asm/dmaengine.h
index bf2f30cf0a27..2a02b611a9ad 100644
--- a/arch/sh/include/asm/dmaengine.h
+++ b/arch/sh/include/asm/dmaengine.h
@@ -10,14 +10,9 @@
10#ifndef ASM_DMAENGINE_H 10#ifndef ASM_DMAENGINE_H
11#define ASM_DMAENGINE_H 11#define ASM_DMAENGINE_H
12 12
13#include <linux/dmaengine.h> 13#include <linux/sh_dma.h>
14#include <linux/list.h>
15 14
16#include <asm/dma-register.h> 15enum {
17
18#define SH_DMAC_MAX_CHANNELS 6
19
20enum sh_dmae_slave_chan_id {
21 SHDMA_SLAVE_SCIF0_TX, 16 SHDMA_SLAVE_SCIF0_TX,
22 SHDMA_SLAVE_SCIF0_RX, 17 SHDMA_SLAVE_SCIF0_RX,
23 SHDMA_SLAVE_SCIF1_TX, 18 SHDMA_SLAVE_SCIF1_TX,
@@ -34,60 +29,6 @@ enum sh_dmae_slave_chan_id {
34 SHDMA_SLAVE_SIUA_RX, 29 SHDMA_SLAVE_SIUA_RX,
35 SHDMA_SLAVE_SIUB_TX, 30 SHDMA_SLAVE_SIUB_TX,
36 SHDMA_SLAVE_SIUB_RX, 31 SHDMA_SLAVE_SIUB_RX,
37 SHDMA_SLAVE_NUMBER, /* Must stay last */
38};
39
40struct sh_dmae_slave_config {
41 enum sh_dmae_slave_chan_id slave_id;
42 dma_addr_t addr;
43 u32 chcr;
44 char mid_rid;
45};
46
47struct sh_dmae_channel {
48 unsigned int offset;
49 unsigned int dmars;
50 unsigned int dmars_bit;
51};
52
53struct sh_dmae_pdata {
54 struct sh_dmae_slave_config *slave;
55 int slave_num;
56 struct sh_dmae_channel *channel;
57 int channel_num;
58 unsigned int ts_low_shift;
59 unsigned int ts_low_mask;
60 unsigned int ts_high_shift;
61 unsigned int ts_high_mask;
62 unsigned int *ts_shift;
63 int ts_shift_num;
64 u16 dmaor_init;
65};
66
67struct device;
68
69/* Used by slave DMA clients to request DMA to/from a specific peripheral */
70struct sh_dmae_slave {
71 enum sh_dmae_slave_chan_id slave_id; /* Set by the platform */
72 struct device *dma_dev; /* Set by the platform */
73 struct sh_dmae_slave_config *config; /* Set by the driver */
74};
75
76struct sh_dmae_regs {
77 u32 sar; /* SAR / source address */
78 u32 dar; /* DAR / destination address */
79 u32 tcr; /* TCR / transfer count */
80};
81
82struct sh_desc {
83 struct sh_dmae_regs hw;
84 struct list_head node;
85 struct dma_async_tx_descriptor async_tx;
86 enum dma_data_direction direction;
87 dma_cookie_t cookie;
88 size_t partial;
89 int chunks;
90 int mark;
91}; 32};
92 33
93#endif 34#endif
diff --git a/arch/sh/include/asm/siu.h b/arch/sh/include/asm/siu.h
index f1b1e6944a5f..e8d4142baf59 100644
--- a/arch/sh/include/asm/siu.h
+++ b/arch/sh/include/asm/siu.h
@@ -17,10 +17,10 @@ struct device;
17 17
18struct siu_platform { 18struct siu_platform {
19 struct device *dma_dev; 19 struct device *dma_dev;
20 enum sh_dmae_slave_chan_id dma_slave_tx_a; 20 unsigned int dma_slave_tx_a;
21 enum sh_dmae_slave_chan_id dma_slave_rx_a; 21 unsigned int dma_slave_rx_a;
22 enum sh_dmae_slave_chan_id dma_slave_tx_b; 22 unsigned int dma_slave_tx_b;
23 enum sh_dmae_slave_chan_id dma_slave_rx_b; 23 unsigned int dma_slave_rx_b;
24}; 24};
25 25
26#endif /* ASM_SIU_H */ 26#endif /* ASM_SIU_H */
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index 02fd3ae8b0ee..650b92f00ee5 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -11,7 +11,7 @@ endif
11 11
12CFLAGS_REMOVE_return_address.o = -pg 12CFLAGS_REMOVE_return_address.o = -pg
13 13
14obj-y := debugtraps.o dma-nommu.o dumpstack.o \ 14obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \
15 idle.o io.o io_generic.o irq.o \ 15 idle.o io.o io_generic.o irq.o \
16 irq_$(BITS).o machvec.o nmi_debug.o process.o \ 16 irq_$(BITS).o machvec.o nmi_debug.o process.o \
17 process_$(BITS).o ptrace_$(BITS).o \ 17 process_$(BITS).o ptrace_$(BITS).o \
diff --git a/arch/sh/kernel/clkdev.c b/arch/sh/kernel/clkdev.c
new file mode 100644
index 000000000000..defdd6e30908
--- /dev/null
+++ b/arch/sh/kernel/clkdev.c
@@ -0,0 +1,169 @@
1/*
2 * arch/sh/kernel/clkdev.c
3 *
4 * Cloned from arch/arm/common/clkdev.c:
5 *
6 * Copyright (C) 2008 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Helper for the clk API to assist looking up a struct clk.
13 */
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/device.h>
17#include <linux/list.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/string.h>
21#include <linux/mutex.h>
22#include <linux/clk.h>
23#include <linux/slab.h>
24#include <linux/bootmem.h>
25#include <linux/mm.h>
26#include <asm/clock.h>
27#include <asm/clkdev.h>
28
29static LIST_HEAD(clocks);
30static DEFINE_MUTEX(clocks_mutex);
31
32/*
33 * Find the correct struct clk for the device and connection ID.
34 * We do slightly fuzzy matching here:
35 * An entry with a NULL ID is assumed to be a wildcard.
36 * If an entry has a device ID, it must match
37 * If an entry has a connection ID, it must match
38 * Then we take the most specific entry - with the following
39 * order of precidence: dev+con > dev only > con only.
40 */
41static struct clk *clk_find(const char *dev_id, const char *con_id)
42{
43 struct clk_lookup *p;
44 struct clk *clk = NULL;
45 int match, best = 0;
46
47 list_for_each_entry(p, &clocks, node) {
48 match = 0;
49 if (p->dev_id) {
50 if (!dev_id || strcmp(p->dev_id, dev_id))
51 continue;
52 match += 2;
53 }
54 if (p->con_id) {
55 if (!con_id || strcmp(p->con_id, con_id))
56 continue;
57 match += 1;
58 }
59 if (match == 0)
60 continue;
61
62 if (match > best) {
63 clk = p->clk;
64 best = match;
65 }
66 }
67 return clk;
68}
69
70struct clk *clk_get_sys(const char *dev_id, const char *con_id)
71{
72 struct clk *clk;
73
74 mutex_lock(&clocks_mutex);
75 clk = clk_find(dev_id, con_id);
76 mutex_unlock(&clocks_mutex);
77
78 return clk ? clk : ERR_PTR(-ENOENT);
79}
80EXPORT_SYMBOL(clk_get_sys);
81
82void clkdev_add(struct clk_lookup *cl)
83{
84 mutex_lock(&clocks_mutex);
85 list_add_tail(&cl->node, &clocks);
86 mutex_unlock(&clocks_mutex);
87}
88EXPORT_SYMBOL(clkdev_add);
89
90void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
91{
92 mutex_lock(&clocks_mutex);
93 while (num--) {
94 list_add_tail(&cl->node, &clocks);
95 cl++;
96 }
97 mutex_unlock(&clocks_mutex);
98}
99
100#define MAX_DEV_ID 20
101#define MAX_CON_ID 16
102
103struct clk_lookup_alloc {
104 struct clk_lookup cl;
105 char dev_id[MAX_DEV_ID];
106 char con_id[MAX_CON_ID];
107};
108
109struct clk_lookup * __init_refok
110clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
111{
112 struct clk_lookup_alloc *cla;
113
114 if (!slab_is_available())
115 cla = alloc_bootmem_low_pages(sizeof(*cla));
116 else
117 cla = kzalloc(sizeof(*cla), GFP_KERNEL);
118
119 if (!cla)
120 return NULL;
121
122 cla->cl.clk = clk;
123 if (con_id) {
124 strlcpy(cla->con_id, con_id, sizeof(cla->con_id));
125 cla->cl.con_id = cla->con_id;
126 }
127
128 if (dev_fmt) {
129 va_list ap;
130
131 va_start(ap, dev_fmt);
132 vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
133 cla->cl.dev_id = cla->dev_id;
134 va_end(ap);
135 }
136
137 return &cla->cl;
138}
139EXPORT_SYMBOL(clkdev_alloc);
140
141int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
142 struct device *dev)
143{
144 struct clk *r = clk_get(dev, id);
145 struct clk_lookup *l;
146
147 if (IS_ERR(r))
148 return PTR_ERR(r);
149
150 l = clkdev_alloc(r, alias, alias_dev_name);
151 clk_put(r);
152 if (!l)
153 return -ENODEV;
154 clkdev_add(l);
155 return 0;
156}
157EXPORT_SYMBOL(clk_add_alias);
158
159/*
160 * clkdev_drop - remove a clock dynamically allocated
161 */
162void clkdev_drop(struct clk_lookup *cl)
163{
164 mutex_lock(&clocks_mutex);
165 list_del(&cl->node);
166 mutex_unlock(&clocks_mutex);
167 kfree(cl);
168}
169EXPORT_SYMBOL(clkdev_drop);
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index eed5eaff96ba..17a73ad7a20d 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -338,6 +338,11 @@ int __init __deprecated cpg_clk_init(void)
338 ret |= clk_register(clk); 338 ret |= clk_register(clk);
339 } 339 }
340 340
341 clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL);
342 clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL);
343 clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL);
344 clk_add_alias("sci_ick", NULL, "peripheral_clk", NULL);
345
341 return ret; 346 return ret;
342} 347}
343 348
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index e9fa1bfed53e..9ded1bc29260 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -10,10 +10,6 @@
10 * 10 *
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> 11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
12 * 12 *
13 * With clkdev bits:
14 *
15 * Copyright (C) 2008 Russell King.
16 *
17 * This file is subject to the terms and conditions of the GNU General Public 13 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive 14 * License. See the file "COPYING" in the main directory of this archive
19 * for more details. 15 * for more details.
@@ -30,6 +26,7 @@
30#include <linux/platform_device.h> 26#include <linux/platform_device.h>
31#include <linux/debugfs.h> 27#include <linux/debugfs.h>
32#include <linux/cpufreq.h> 28#include <linux/cpufreq.h>
29#include <linux/clk.h>
33#include <asm/clock.h> 30#include <asm/clock.h>
34#include <asm/machvec.h> 31#include <asm/machvec.h>
35 32
@@ -398,56 +395,6 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
398EXPORT_SYMBOL_GPL(clk_round_rate); 395EXPORT_SYMBOL_GPL(clk_round_rate);
399 396
400/* 397/*
401 * Find the correct struct clk for the device and connection ID.
402 * We do slightly fuzzy matching here:
403 * An entry with a NULL ID is assumed to be a wildcard.
404 * If an entry has a device ID, it must match
405 * If an entry has a connection ID, it must match
406 * Then we take the most specific entry - with the following
407 * order of precedence: dev+con > dev only > con only.
408 */
409static struct clk *clk_find(const char *dev_id, const char *con_id)
410{
411 struct clk_lookup *p;
412 struct clk *clk = NULL;
413 int match, best = 0;
414
415 list_for_each_entry(p, &clock_list, node) {
416 match = 0;
417 if (p->dev_id) {
418 if (!dev_id || strcmp(p->dev_id, dev_id))
419 continue;
420 match += 2;
421 }
422 if (p->con_id) {
423 if (!con_id || strcmp(p->con_id, con_id))
424 continue;
425 match += 1;
426 }
427 if (match == 0)
428 continue;
429
430 if (match > best) {
431 clk = p->clk;
432 best = match;
433 }
434 }
435 return clk;
436}
437
438struct clk *clk_get_sys(const char *dev_id, const char *con_id)
439{
440 struct clk *clk;
441
442 mutex_lock(&clock_list_sem);
443 clk = clk_find(dev_id, con_id);
444 mutex_unlock(&clock_list_sem);
445
446 return clk ? clk : ERR_PTR(-ENOENT);
447}
448EXPORT_SYMBOL_GPL(clk_get_sys);
449
450/*
451 * Returns a clock. Note that we first try to use device id on the bus 398 * Returns a clock. Note that we first try to use device id on the bus
452 * and clock name. If this fails, we try to use clock name only. 399 * and clock name. If this fails, we try to use clock name only.
453 */ 400 */
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 114c7cee7184..c3638516bffc 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -128,17 +128,14 @@ static struct platform_device eth_device = {
128}; 128};
129 129
130static struct sh_timer_config cmt0_platform_data = { 130static struct sh_timer_config cmt0_platform_data = {
131 .name = "CMT0",
132 .channel_offset = 0x02, 131 .channel_offset = 0x02,
133 .timer_bit = 0, 132 .timer_bit = 0,
134 .clk = "peripheral_clk",
135 .clockevent_rating = 125, 133 .clockevent_rating = 125,
136 .clocksource_rating = 0, /* disabled due to code generation issues */ 134 .clocksource_rating = 0, /* disabled due to code generation issues */
137}; 135};
138 136
139static struct resource cmt0_resources[] = { 137static struct resource cmt0_resources[] = {
140 [0] = { 138 [0] = {
141 .name = "CMT0",
142 .start = 0xf84a0072, 139 .start = 0xf84a0072,
143 .end = 0xf84a0077, 140 .end = 0xf84a0077,
144 .flags = IORESOURCE_MEM, 141 .flags = IORESOURCE_MEM,
@@ -160,17 +157,14 @@ static struct platform_device cmt0_device = {
160}; 157};
161 158
162static struct sh_timer_config cmt1_platform_data = { 159static struct sh_timer_config cmt1_platform_data = {
163 .name = "CMT1",
164 .channel_offset = 0x08, 160 .channel_offset = 0x08,
165 .timer_bit = 1, 161 .timer_bit = 1,
166 .clk = "peripheral_clk",
167 .clockevent_rating = 125, 162 .clockevent_rating = 125,
168 .clocksource_rating = 0, /* disabled due to code generation issues */ 163 .clocksource_rating = 0, /* disabled due to code generation issues */
169}; 164};
170 165
171static struct resource cmt1_resources[] = { 166static struct resource cmt1_resources[] = {
172 [0] = { 167 [0] = {
173 .name = "CMT1",
174 .start = 0xf84a0078, 168 .start = 0xf84a0078,
175 .end = 0xf84a007d, 169 .end = 0xf84a007d,
176 .flags = IORESOURCE_MEM, 170 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index 8f669dc9b0da..6c96ea02bf8d 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -115,16 +115,13 @@ static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
115 mask_registers, prio_registers, NULL); 115 mask_registers, prio_registers, NULL);
116 116
117static struct sh_timer_config mtu2_0_platform_data = { 117static struct sh_timer_config mtu2_0_platform_data = {
118 .name = "MTU2_0",
119 .channel_offset = -0x80, 118 .channel_offset = -0x80,
120 .timer_bit = 0, 119 .timer_bit = 0,
121 .clk = "peripheral_clk",
122 .clockevent_rating = 200, 120 .clockevent_rating = 200,
123}; 121};
124 122
125static struct resource mtu2_0_resources[] = { 123static struct resource mtu2_0_resources[] = {
126 [0] = { 124 [0] = {
127 .name = "MTU2_0",
128 .start = 0xff801300, 125 .start = 0xff801300,
129 .end = 0xff801326, 126 .end = 0xff801326,
130 .flags = IORESOURCE_MEM, 127 .flags = IORESOURCE_MEM,
@@ -146,16 +143,13 @@ static struct platform_device mtu2_0_device = {
146}; 143};
147 144
148static struct sh_timer_config mtu2_1_platform_data = { 145static struct sh_timer_config mtu2_1_platform_data = {
149 .name = "MTU2_1",
150 .channel_offset = -0x100, 146 .channel_offset = -0x100,
151 .timer_bit = 1, 147 .timer_bit = 1,
152 .clk = "peripheral_clk",
153 .clockevent_rating = 200, 148 .clockevent_rating = 200,
154}; 149};
155 150
156static struct resource mtu2_1_resources[] = { 151static struct resource mtu2_1_resources[] = {
157 [0] = { 152 [0] = {
158 .name = "MTU2_1",
159 .start = 0xff801380, 153 .start = 0xff801380,
160 .end = 0xff801390, 154 .end = 0xff801390,
161 .flags = IORESOURCE_MEM, 155 .flags = IORESOURCE_MEM,
@@ -177,16 +171,13 @@ static struct platform_device mtu2_1_device = {
177}; 171};
178 172
179static struct sh_timer_config mtu2_2_platform_data = { 173static struct sh_timer_config mtu2_2_platform_data = {
180 .name = "MTU2_2",
181 .channel_offset = 0x80, 174 .channel_offset = 0x80,
182 .timer_bit = 2, 175 .timer_bit = 2,
183 .clk = "peripheral_clk",
184 .clockevent_rating = 200, 176 .clockevent_rating = 200,
185}; 177};
186 178
187static struct resource mtu2_2_resources[] = { 179static struct resource mtu2_2_resources[] = {
188 [0] = { 180 [0] = {
189 .name = "MTU2_2",
190 .start = 0xff801000, 181 .start = 0xff801000,
191 .end = 0xff80100a, 182 .end = 0xff80100a,
192 .flags = IORESOURCE_MEM, 183 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 4ccfeb59eb1a..d08bf4c07d60 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -318,16 +318,13 @@ static struct platform_device rtc_device = {
318}; 318};
319 319
320static struct sh_timer_config mtu2_0_platform_data = { 320static struct sh_timer_config mtu2_0_platform_data = {
321 .name = "MTU2_0",
322 .channel_offset = -0x80, 321 .channel_offset = -0x80,
323 .timer_bit = 0, 322 .timer_bit = 0,
324 .clk = "peripheral_clk",
325 .clockevent_rating = 200, 323 .clockevent_rating = 200,
326}; 324};
327 325
328static struct resource mtu2_0_resources[] = { 326static struct resource mtu2_0_resources[] = {
329 [0] = { 327 [0] = {
330 .name = "MTU2_0",
331 .start = 0xfffe4300, 328 .start = 0xfffe4300,
332 .end = 0xfffe4326, 329 .end = 0xfffe4326,
333 .flags = IORESOURCE_MEM, 330 .flags = IORESOURCE_MEM,
@@ -349,16 +346,13 @@ static struct platform_device mtu2_0_device = {
349}; 346};
350 347
351static struct sh_timer_config mtu2_1_platform_data = { 348static struct sh_timer_config mtu2_1_platform_data = {
352 .name = "MTU2_1",
353 .channel_offset = -0x100, 349 .channel_offset = -0x100,
354 .timer_bit = 1, 350 .timer_bit = 1,
355 .clk = "peripheral_clk",
356 .clockevent_rating = 200, 351 .clockevent_rating = 200,
357}; 352};
358 353
359static struct resource mtu2_1_resources[] = { 354static struct resource mtu2_1_resources[] = {
360 [0] = { 355 [0] = {
361 .name = "MTU2_1",
362 .start = 0xfffe4380, 356 .start = 0xfffe4380,
363 .end = 0xfffe4390, 357 .end = 0xfffe4390,
364 .flags = IORESOURCE_MEM, 358 .flags = IORESOURCE_MEM,
@@ -380,16 +374,13 @@ static struct platform_device mtu2_1_device = {
380}; 374};
381 375
382static struct sh_timer_config mtu2_2_platform_data = { 376static struct sh_timer_config mtu2_2_platform_data = {
383 .name = "MTU2_2",
384 .channel_offset = 0x80, 377 .channel_offset = 0x80,
385 .timer_bit = 2, 378 .timer_bit = 2,
386 .clk = "peripheral_clk",
387 .clockevent_rating = 200, 379 .clockevent_rating = 200,
388}; 380};
389 381
390static struct resource mtu2_2_resources[] = { 382static struct resource mtu2_2_resources[] = {
391 [0] = { 383 [0] = {
392 .name = "MTU2_2",
393 .start = 0xfffe4000, 384 .start = 0xfffe4000,
394 .end = 0xfffe400a, 385 .end = 0xfffe400a,
395 .flags = IORESOURCE_MEM, 386 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index 3136966cc9b3..832f401b5860 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -234,17 +234,14 @@ static struct platform_device scif3_device = {
234}; 234};
235 235
236static struct sh_timer_config cmt0_platform_data = { 236static struct sh_timer_config cmt0_platform_data = {
237 .name = "CMT0",
238 .channel_offset = 0x02, 237 .channel_offset = 0x02,
239 .timer_bit = 0, 238 .timer_bit = 0,
240 .clk = "peripheral_clk",
241 .clockevent_rating = 125, 239 .clockevent_rating = 125,
242 .clocksource_rating = 0, /* disabled due to code generation issues */ 240 .clocksource_rating = 0, /* disabled due to code generation issues */
243}; 241};
244 242
245static struct resource cmt0_resources[] = { 243static struct resource cmt0_resources[] = {
246 [0] = { 244 [0] = {
247 .name = "CMT0",
248 .start = 0xfffec002, 245 .start = 0xfffec002,
249 .end = 0xfffec007, 246 .end = 0xfffec007,
250 .flags = IORESOURCE_MEM, 247 .flags = IORESOURCE_MEM,
@@ -266,17 +263,14 @@ static struct platform_device cmt0_device = {
266}; 263};
267 264
268static struct sh_timer_config cmt1_platform_data = { 265static struct sh_timer_config cmt1_platform_data = {
269 .name = "CMT1",
270 .channel_offset = 0x08, 266 .channel_offset = 0x08,
271 .timer_bit = 1, 267 .timer_bit = 1,
272 .clk = "peripheral_clk",
273 .clockevent_rating = 125, 268 .clockevent_rating = 125,
274 .clocksource_rating = 0, /* disabled due to code generation issues */ 269 .clocksource_rating = 0, /* disabled due to code generation issues */
275}; 270};
276 271
277static struct resource cmt1_resources[] = { 272static struct resource cmt1_resources[] = {
278 [0] = { 273 [0] = {
279 .name = "CMT1",
280 .start = 0xfffec008, 274 .start = 0xfffec008,
281 .end = 0xfffec00d, 275 .end = 0xfffec00d,
282 .flags = IORESOURCE_MEM, 276 .flags = IORESOURCE_MEM,
@@ -298,16 +292,13 @@ static struct platform_device cmt1_device = {
298}; 292};
299 293
300static struct sh_timer_config mtu2_0_platform_data = { 294static struct sh_timer_config mtu2_0_platform_data = {
301 .name = "MTU2_0",
302 .channel_offset = -0x80, 295 .channel_offset = -0x80,
303 .timer_bit = 0, 296 .timer_bit = 0,
304 .clk = "peripheral_clk",
305 .clockevent_rating = 200, 297 .clockevent_rating = 200,
306}; 298};
307 299
308static struct resource mtu2_0_resources[] = { 300static struct resource mtu2_0_resources[] = {
309 [0] = { 301 [0] = {
310 .name = "MTU2_0",
311 .start = 0xfffe4300, 302 .start = 0xfffe4300,
312 .end = 0xfffe4326, 303 .end = 0xfffe4326,
313 .flags = IORESOURCE_MEM, 304 .flags = IORESOURCE_MEM,
@@ -329,16 +320,13 @@ static struct platform_device mtu2_0_device = {
329}; 320};
330 321
331static struct sh_timer_config mtu2_1_platform_data = { 322static struct sh_timer_config mtu2_1_platform_data = {
332 .name = "MTU2_1",
333 .channel_offset = -0x100, 323 .channel_offset = -0x100,
334 .timer_bit = 1, 324 .timer_bit = 1,
335 .clk = "peripheral_clk",
336 .clockevent_rating = 200, 325 .clockevent_rating = 200,
337}; 326};
338 327
339static struct resource mtu2_1_resources[] = { 328static struct resource mtu2_1_resources[] = {
340 [0] = { 329 [0] = {
341 .name = "MTU2_1",
342 .start = 0xfffe4380, 330 .start = 0xfffe4380,
343 .end = 0xfffe4390, 331 .end = 0xfffe4390,
344 .flags = IORESOURCE_MEM, 332 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index 064873585a8b..dc47b04e1049 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -194,17 +194,14 @@ static struct platform_device scif3_device = {
194}; 194};
195 195
196static struct sh_timer_config cmt0_platform_data = { 196static struct sh_timer_config cmt0_platform_data = {
197 .name = "CMT0",
198 .channel_offset = 0x02, 197 .channel_offset = 0x02,
199 .timer_bit = 0, 198 .timer_bit = 0,
200 .clk = "peripheral_clk",
201 .clockevent_rating = 125, 199 .clockevent_rating = 125,
202 .clocksource_rating = 0, /* disabled due to code generation issues */ 200 .clocksource_rating = 0, /* disabled due to code generation issues */
203}; 201};
204 202
205static struct resource cmt0_resources[] = { 203static struct resource cmt0_resources[] = {
206 [0] = { 204 [0] = {
207 .name = "CMT0",
208 .start = 0xfffec002, 205 .start = 0xfffec002,
209 .end = 0xfffec007, 206 .end = 0xfffec007,
210 .flags = IORESOURCE_MEM, 207 .flags = IORESOURCE_MEM,
@@ -226,17 +223,14 @@ static struct platform_device cmt0_device = {
226}; 223};
227 224
228static struct sh_timer_config cmt1_platform_data = { 225static struct sh_timer_config cmt1_platform_data = {
229 .name = "CMT1",
230 .channel_offset = 0x08, 226 .channel_offset = 0x08,
231 .timer_bit = 1, 227 .timer_bit = 1,
232 .clk = "peripheral_clk",
233 .clockevent_rating = 125, 228 .clockevent_rating = 125,
234 .clocksource_rating = 0, /* disabled due to code generation issues */ 229 .clocksource_rating = 0, /* disabled due to code generation issues */
235}; 230};
236 231
237static struct resource cmt1_resources[] = { 232static struct resource cmt1_resources[] = {
238 [0] = { 233 [0] = {
239 .name = "CMT1",
240 .start = 0xfffec008, 234 .start = 0xfffec008,
241 .end = 0xfffec00d, 235 .end = 0xfffec00d,
242 .flags = IORESOURCE_MEM, 236 .flags = IORESOURCE_MEM,
@@ -258,16 +252,13 @@ static struct platform_device cmt1_device = {
258}; 252};
259 253
260static struct sh_timer_config mtu2_0_platform_data = { 254static struct sh_timer_config mtu2_0_platform_data = {
261 .name = "MTU2_0",
262 .channel_offset = -0x80, 255 .channel_offset = -0x80,
263 .timer_bit = 0, 256 .timer_bit = 0,
264 .clk = "peripheral_clk",
265 .clockevent_rating = 200, 257 .clockevent_rating = 200,
266}; 258};
267 259
268static struct resource mtu2_0_resources[] = { 260static struct resource mtu2_0_resources[] = {
269 [0] = { 261 [0] = {
270 .name = "MTU2_0",
271 .start = 0xfffe4300, 262 .start = 0xfffe4300,
272 .end = 0xfffe4326, 263 .end = 0xfffe4326,
273 .flags = IORESOURCE_MEM, 264 .flags = IORESOURCE_MEM,
@@ -289,16 +280,13 @@ static struct platform_device mtu2_0_device = {
289}; 280};
290 281
291static struct sh_timer_config mtu2_1_platform_data = { 282static struct sh_timer_config mtu2_1_platform_data = {
292 .name = "MTU2_1",
293 .channel_offset = -0x100, 283 .channel_offset = -0x100,
294 .timer_bit = 1, 284 .timer_bit = 1,
295 .clk = "peripheral_clk",
296 .clockevent_rating = 200, 285 .clockevent_rating = 200,
297}; 286};
298 287
299static struct resource mtu2_1_resources[] = { 288static struct resource mtu2_1_resources[] = {
300 [0] = { 289 [0] = {
301 .name = "MTU2_1",
302 .start = 0xfffe4380, 290 .start = 0xfffe4380,
303 .end = 0xfffe4390, 291 .end = 0xfffe4390,
304 .flags = IORESOURCE_MEM, 292 .flags = IORESOURCE_MEM,
@@ -320,16 +308,13 @@ static struct platform_device mtu2_1_device = {
320}; 308};
321 309
322static struct sh_timer_config mtu2_2_platform_data = { 310static struct sh_timer_config mtu2_2_platform_data = {
323 .name = "MTU2_2",
324 .channel_offset = 0x80, 311 .channel_offset = 0x80,
325 .timer_bit = 2, 312 .timer_bit = 2,
326 .clk = "peripheral_clk",
327 .clockevent_rating = 200, 313 .clockevent_rating = 200,
328}; 314};
329 315
330static struct resource mtu2_2_resources[] = { 316static struct resource mtu2_2_resources[] = {
331 [0] = { 317 [0] = {
332 .name = "MTU2_2",
333 .start = 0xfffe4000, 318 .start = 0xfffe4000,
334 .end = 0xfffe400a, 319 .end = 0xfffe400a,
335 .flags = IORESOURCE_MEM, 320 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 7b892d60e3a0..baadd7f54d94 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -124,16 +124,13 @@ static struct platform_device rtc_device = {
124}; 124};
125 125
126static struct sh_timer_config tmu0_platform_data = { 126static struct sh_timer_config tmu0_platform_data = {
127 .name = "TMU0",
128 .channel_offset = 0x02, 127 .channel_offset = 0x02,
129 .timer_bit = 0, 128 .timer_bit = 0,
130 .clk = "peripheral_clk",
131 .clockevent_rating = 200, 129 .clockevent_rating = 200,
132}; 130};
133 131
134static struct resource tmu0_resources[] = { 132static struct resource tmu0_resources[] = {
135 [0] = { 133 [0] = {
136 .name = "TMU0",
137 .start = 0xfffffe94, 134 .start = 0xfffffe94,
138 .end = 0xfffffe9f, 135 .end = 0xfffffe9f,
139 .flags = IORESOURCE_MEM, 136 .flags = IORESOURCE_MEM,
@@ -155,16 +152,13 @@ static struct platform_device tmu0_device = {
155}; 152};
156 153
157static struct sh_timer_config tmu1_platform_data = { 154static struct sh_timer_config tmu1_platform_data = {
158 .name = "TMU1",
159 .channel_offset = 0xe, 155 .channel_offset = 0xe,
160 .timer_bit = 1, 156 .timer_bit = 1,
161 .clk = "peripheral_clk",
162 .clocksource_rating = 200, 157 .clocksource_rating = 200,
163}; 158};
164 159
165static struct resource tmu1_resources[] = { 160static struct resource tmu1_resources[] = {
166 [0] = { 161 [0] = {
167 .name = "TMU1",
168 .start = 0xfffffea0, 162 .start = 0xfffffea0,
169 .end = 0xfffffeab, 163 .end = 0xfffffeab,
170 .flags = IORESOURCE_MEM, 164 .flags = IORESOURCE_MEM,
@@ -186,15 +180,12 @@ static struct platform_device tmu1_device = {
186}; 180};
187 181
188static struct sh_timer_config tmu2_platform_data = { 182static struct sh_timer_config tmu2_platform_data = {
189 .name = "TMU2",
190 .channel_offset = 0x1a, 183 .channel_offset = 0x1a,
191 .timer_bit = 2, 184 .timer_bit = 2,
192 .clk = "peripheral_clk",
193}; 185};
194 186
195static struct resource tmu2_resources[] = { 187static struct resource tmu2_resources[] = {
196 [0] = { 188 [0] = {
197 .name = "TMU2",
198 .start = 0xfffffeac, 189 .start = 0xfffffeac,
199 .end = 0xfffffebb, 190 .end = 0xfffffebb,
200 .flags = IORESOURCE_MEM, 191 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index bc0c4f68c7c7..3cf8c8ef7b32 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -157,16 +157,13 @@ static struct platform_device scif2_device = {
157#endif 157#endif
158 158
159static struct sh_timer_config tmu0_platform_data = { 159static struct sh_timer_config tmu0_platform_data = {
160 .name = "TMU0",
161 .channel_offset = 0x02, 160 .channel_offset = 0x02,
162 .timer_bit = 0, 161 .timer_bit = 0,
163 .clk = "peripheral_clk",
164 .clockevent_rating = 200, 162 .clockevent_rating = 200,
165}; 163};
166 164
167static struct resource tmu0_resources[] = { 165static struct resource tmu0_resources[] = {
168 [0] = { 166 [0] = {
169 .name = "TMU0",
170 .start = 0xfffffe94, 167 .start = 0xfffffe94,
171 .end = 0xfffffe9f, 168 .end = 0xfffffe9f,
172 .flags = IORESOURCE_MEM, 169 .flags = IORESOURCE_MEM,
@@ -188,16 +185,13 @@ static struct platform_device tmu0_device = {
188}; 185};
189 186
190static struct sh_timer_config tmu1_platform_data = { 187static struct sh_timer_config tmu1_platform_data = {
191 .name = "TMU1",
192 .channel_offset = 0xe, 188 .channel_offset = 0xe,
193 .timer_bit = 1, 189 .timer_bit = 1,
194 .clk = "peripheral_clk",
195 .clocksource_rating = 200, 190 .clocksource_rating = 200,
196}; 191};
197 192
198static struct resource tmu1_resources[] = { 193static struct resource tmu1_resources[] = {
199 [0] = { 194 [0] = {
200 .name = "TMU1",
201 .start = 0xfffffea0, 195 .start = 0xfffffea0,
202 .end = 0xfffffeab, 196 .end = 0xfffffeab,
203 .flags = IORESOURCE_MEM, 197 .flags = IORESOURCE_MEM,
@@ -219,15 +213,12 @@ static struct platform_device tmu1_device = {
219}; 213};
220 214
221static struct sh_timer_config tmu2_platform_data = { 215static struct sh_timer_config tmu2_platform_data = {
222 .name = "TMU2",
223 .channel_offset = 0x1a, 216 .channel_offset = 0x1a,
224 .timer_bit = 2, 217 .timer_bit = 2,
225 .clk = "peripheral_clk",
226}; 218};
227 219
228static struct resource tmu2_resources[] = { 220static struct resource tmu2_resources[] = {
229 [0] = { 221 [0] = {
230 .name = "TMU2",
231 .start = 0xfffffeac, 222 .start = 0xfffffeac,
232 .end = 0xfffffebb, 223 .end = 0xfffffebb,
233 .flags = IORESOURCE_MEM, 224 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 0845a3ad006d..b0c2fb4ab479 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -127,16 +127,13 @@ static struct platform_device scif1_device = {
127}; 127};
128 128
129static struct sh_timer_config tmu0_platform_data = { 129static struct sh_timer_config tmu0_platform_data = {
130 .name = "TMU0",
131 .channel_offset = 0x02, 130 .channel_offset = 0x02,
132 .timer_bit = 0, 131 .timer_bit = 0,
133 .clk = "peripheral_clk",
134 .clockevent_rating = 200, 132 .clockevent_rating = 200,
135}; 133};
136 134
137static struct resource tmu0_resources[] = { 135static struct resource tmu0_resources[] = {
138 [0] = { 136 [0] = {
139 .name = "TMU0",
140 .start = 0xa412fe94, 137 .start = 0xa412fe94,
141 .end = 0xa412fe9f, 138 .end = 0xa412fe9f,
142 .flags = IORESOURCE_MEM, 139 .flags = IORESOURCE_MEM,
@@ -158,16 +155,13 @@ static struct platform_device tmu0_device = {
158}; 155};
159 156
160static struct sh_timer_config tmu1_platform_data = { 157static struct sh_timer_config tmu1_platform_data = {
161 .name = "TMU1",
162 .channel_offset = 0xe, 158 .channel_offset = 0xe,
163 .timer_bit = 1, 159 .timer_bit = 1,
164 .clk = "peripheral_clk",
165 .clocksource_rating = 200, 160 .clocksource_rating = 200,
166}; 161};
167 162
168static struct resource tmu1_resources[] = { 163static struct resource tmu1_resources[] = {
169 [0] = { 164 [0] = {
170 .name = "TMU1",
171 .start = 0xa412fea0, 165 .start = 0xa412fea0,
172 .end = 0xa412feab, 166 .end = 0xa412feab,
173 .flags = IORESOURCE_MEM, 167 .flags = IORESOURCE_MEM,
@@ -189,15 +183,12 @@ static struct platform_device tmu1_device = {
189}; 183};
190 184
191static struct sh_timer_config tmu2_platform_data = { 185static struct sh_timer_config tmu2_platform_data = {
192 .name = "TMU2",
193 .channel_offset = 0x1a, 186 .channel_offset = 0x1a,
194 .timer_bit = 2, 187 .timer_bit = 2,
195 .clk = "peripheral_clk",
196}; 188};
197 189
198static struct resource tmu2_resources[] = { 190static struct resource tmu2_resources[] = {
199 [0] = { 191 [0] = {
200 .name = "TMU2",
201 .start = 0xa412feac, 192 .start = 0xa412feac,
202 .end = 0xa412feb5, 193 .end = 0xa412feb5,
203 .flags = IORESOURCE_MEM, 194 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index a718a6231091..24b17135d5d2 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -130,17 +130,14 @@ static struct platform_device usbf_device = {
130}; 130};
131 131
132static struct sh_timer_config cmt0_platform_data = { 132static struct sh_timer_config cmt0_platform_data = {
133 .name = "CMT0",
134 .channel_offset = 0x10, 133 .channel_offset = 0x10,
135 .timer_bit = 0, 134 .timer_bit = 0,
136 .clk = "peripheral_clk",
137 .clockevent_rating = 125, 135 .clockevent_rating = 125,
138 .clocksource_rating = 125, 136 .clocksource_rating = 125,
139}; 137};
140 138
141static struct resource cmt0_resources[] = { 139static struct resource cmt0_resources[] = {
142 [0] = { 140 [0] = {
143 .name = "CMT0",
144 .start = 0x044a0010, 141 .start = 0x044a0010,
145 .end = 0x044a001b, 142 .end = 0x044a001b,
146 .flags = IORESOURCE_MEM, 143 .flags = IORESOURCE_MEM,
@@ -162,15 +159,12 @@ static struct platform_device cmt0_device = {
162}; 159};
163 160
164static struct sh_timer_config cmt1_platform_data = { 161static struct sh_timer_config cmt1_platform_data = {
165 .name = "CMT1",
166 .channel_offset = 0x20, 162 .channel_offset = 0x20,
167 .timer_bit = 1, 163 .timer_bit = 1,
168 .clk = "peripheral_clk",
169}; 164};
170 165
171static struct resource cmt1_resources[] = { 166static struct resource cmt1_resources[] = {
172 [0] = { 167 [0] = {
173 .name = "CMT1",
174 .start = 0x044a0020, 168 .start = 0x044a0020,
175 .end = 0x044a002b, 169 .end = 0x044a002b,
176 .flags = IORESOURCE_MEM, 170 .flags = IORESOURCE_MEM,
@@ -192,15 +186,12 @@ static struct platform_device cmt1_device = {
192}; 186};
193 187
194static struct sh_timer_config cmt2_platform_data = { 188static struct sh_timer_config cmt2_platform_data = {
195 .name = "CMT2",
196 .channel_offset = 0x30, 189 .channel_offset = 0x30,
197 .timer_bit = 2, 190 .timer_bit = 2,
198 .clk = "peripheral_clk",
199}; 191};
200 192
201static struct resource cmt2_resources[] = { 193static struct resource cmt2_resources[] = {
202 [0] = { 194 [0] = {
203 .name = "CMT2",
204 .start = 0x044a0030, 195 .start = 0x044a0030,
205 .end = 0x044a003b, 196 .end = 0x044a003b,
206 .flags = IORESOURCE_MEM, 197 .flags = IORESOURCE_MEM,
@@ -222,15 +213,12 @@ static struct platform_device cmt2_device = {
222}; 213};
223 214
224static struct sh_timer_config cmt3_platform_data = { 215static struct sh_timer_config cmt3_platform_data = {
225 .name = "CMT3",
226 .channel_offset = 0x40, 216 .channel_offset = 0x40,
227 .timer_bit = 3, 217 .timer_bit = 3,
228 .clk = "peripheral_clk",
229}; 218};
230 219
231static struct resource cmt3_resources[] = { 220static struct resource cmt3_resources[] = {
232 [0] = { 221 [0] = {
233 .name = "CMT3",
234 .start = 0x044a0040, 222 .start = 0x044a0040,
235 .end = 0x044a004b, 223 .end = 0x044a004b,
236 .flags = IORESOURCE_MEM, 224 .flags = IORESOURCE_MEM,
@@ -252,15 +240,12 @@ static struct platform_device cmt3_device = {
252}; 240};
253 241
254static struct sh_timer_config cmt4_platform_data = { 242static struct sh_timer_config cmt4_platform_data = {
255 .name = "CMT4",
256 .channel_offset = 0x50, 243 .channel_offset = 0x50,
257 .timer_bit = 4, 244 .timer_bit = 4,
258 .clk = "peripheral_clk",
259}; 245};
260 246
261static struct resource cmt4_resources[] = { 247static struct resource cmt4_resources[] = {
262 [0] = { 248 [0] = {
263 .name = "CMT4",
264 .start = 0x044a0050, 249 .start = 0x044a0050,
265 .end = 0x044a005b, 250 .end = 0x044a005b,
266 .flags = IORESOURCE_MEM, 251 .flags = IORESOURCE_MEM,
@@ -282,16 +267,13 @@ static struct platform_device cmt4_device = {
282}; 267};
283 268
284static struct sh_timer_config tmu0_platform_data = { 269static struct sh_timer_config tmu0_platform_data = {
285 .name = "TMU0",
286 .channel_offset = 0x02, 270 .channel_offset = 0x02,
287 .timer_bit = 0, 271 .timer_bit = 0,
288 .clk = "peripheral_clk",
289 .clockevent_rating = 200, 272 .clockevent_rating = 200,
290}; 273};
291 274
292static struct resource tmu0_resources[] = { 275static struct resource tmu0_resources[] = {
293 [0] = { 276 [0] = {
294 .name = "TMU0",
295 .start = 0xa412fe94, 277 .start = 0xa412fe94,
296 .end = 0xa412fe9f, 278 .end = 0xa412fe9f,
297 .flags = IORESOURCE_MEM, 279 .flags = IORESOURCE_MEM,
@@ -313,16 +295,13 @@ static struct platform_device tmu0_device = {
313}; 295};
314 296
315static struct sh_timer_config tmu1_platform_data = { 297static struct sh_timer_config tmu1_platform_data = {
316 .name = "TMU1",
317 .channel_offset = 0xe, 298 .channel_offset = 0xe,
318 .timer_bit = 1, 299 .timer_bit = 1,
319 .clk = "peripheral_clk",
320 .clocksource_rating = 200, 300 .clocksource_rating = 200,
321}; 301};
322 302
323static struct resource tmu1_resources[] = { 303static struct resource tmu1_resources[] = {
324 [0] = { 304 [0] = {
325 .name = "TMU1",
326 .start = 0xa412fea0, 305 .start = 0xa412fea0,
327 .end = 0xa412feab, 306 .end = 0xa412feab,
328 .flags = IORESOURCE_MEM, 307 .flags = IORESOURCE_MEM,
@@ -344,15 +323,12 @@ static struct platform_device tmu1_device = {
344}; 323};
345 324
346static struct sh_timer_config tmu2_platform_data = { 325static struct sh_timer_config tmu2_platform_data = {
347 .name = "TMU2",
348 .channel_offset = 0x1a, 326 .channel_offset = 0x1a,
349 .timer_bit = 2, 327 .timer_bit = 2,
350 .clk = "peripheral_clk",
351}; 328};
352 329
353static struct resource tmu2_resources[] = { 330static struct resource tmu2_resources[] = {
354 [0] = { 331 [0] = {
355 .name = "TMU2",
356 .start = 0xa412feac, 332 .start = 0xa412feac,
357 .end = 0xa412feb5, 333 .end = 0xa412feb5,
358 .flags = IORESOURCE_MEM, 334 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index b9b7e10ad68f..e916b18e1f7c 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -31,16 +31,13 @@ static struct platform_device scif0_device = {
31}; 31};
32 32
33static struct sh_timer_config tmu0_platform_data = { 33static struct sh_timer_config tmu0_platform_data = {
34 .name = "TMU0",
35 .channel_offset = 0x04, 34 .channel_offset = 0x04,
36 .timer_bit = 0, 35 .timer_bit = 0,
37 .clk = "peripheral_clk",
38 .clockevent_rating = 200, 36 .clockevent_rating = 200,
39}; 37};
40 38
41static struct resource tmu0_resources[] = { 39static struct resource tmu0_resources[] = {
42 [0] = { 40 [0] = {
43 .name = "TMU0",
44 .start = 0xffd80008, 41 .start = 0xffd80008,
45 .end = 0xffd80013, 42 .end = 0xffd80013,
46 .flags = IORESOURCE_MEM, 43 .flags = IORESOURCE_MEM,
@@ -62,16 +59,13 @@ static struct platform_device tmu0_device = {
62}; 59};
63 60
64static struct sh_timer_config tmu1_platform_data = { 61static struct sh_timer_config tmu1_platform_data = {
65 .name = "TMU1",
66 .channel_offset = 0x10, 62 .channel_offset = 0x10,
67 .timer_bit = 1, 63 .timer_bit = 1,
68 .clk = "peripheral_clk",
69 .clocksource_rating = 200, 64 .clocksource_rating = 200,
70}; 65};
71 66
72static struct resource tmu1_resources[] = { 67static struct resource tmu1_resources[] = {
73 [0] = { 68 [0] = {
74 .name = "TMU1",
75 .start = 0xffd80014, 69 .start = 0xffd80014,
76 .end = 0xffd8001f, 70 .end = 0xffd8001f,
77 .flags = IORESOURCE_MEM, 71 .flags = IORESOURCE_MEM,
@@ -93,15 +87,12 @@ static struct platform_device tmu1_device = {
93}; 87};
94 88
95static struct sh_timer_config tmu2_platform_data = { 89static struct sh_timer_config tmu2_platform_data = {
96 .name = "TMU2",
97 .channel_offset = 0x1c, 90 .channel_offset = 0x1c,
98 .timer_bit = 2, 91 .timer_bit = 2,
99 .clk = "peripheral_clk",
100}; 92};
101 93
102static struct resource tmu2_resources[] = { 94static struct resource tmu2_resources[] = {
103 [0] = { 95 [0] = {
104 .name = "TMU2",
105 .start = 0xffd80020, 96 .start = 0xffd80020,
106 .end = 0xffd8002f, 97 .end = 0xffd8002f,
107 .flags = IORESOURCE_MEM, 98 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index ffd79e57254f..911d196e86b5 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -66,16 +66,13 @@ static struct platform_device scif1_device = {
66}; 66};
67 67
68static struct sh_timer_config tmu0_platform_data = { 68static struct sh_timer_config tmu0_platform_data = {
69 .name = "TMU0",
70 .channel_offset = 0x04, 69 .channel_offset = 0x04,
71 .timer_bit = 0, 70 .timer_bit = 0,
72 .clk = "peripheral_clk",
73 .clockevent_rating = 200, 71 .clockevent_rating = 200,
74}; 72};
75 73
76static struct resource tmu0_resources[] = { 74static struct resource tmu0_resources[] = {
77 [0] = { 75 [0] = {
78 .name = "TMU0",
79 .start = 0xffd80008, 76 .start = 0xffd80008,
80 .end = 0xffd80013, 77 .end = 0xffd80013,
81 .flags = IORESOURCE_MEM, 78 .flags = IORESOURCE_MEM,
@@ -97,16 +94,13 @@ static struct platform_device tmu0_device = {
97}; 94};
98 95
99static struct sh_timer_config tmu1_platform_data = { 96static struct sh_timer_config tmu1_platform_data = {
100 .name = "TMU1",
101 .channel_offset = 0x10, 97 .channel_offset = 0x10,
102 .timer_bit = 1, 98 .timer_bit = 1,
103 .clk = "peripheral_clk",
104 .clocksource_rating = 200, 99 .clocksource_rating = 200,
105}; 100};
106 101
107static struct resource tmu1_resources[] = { 102static struct resource tmu1_resources[] = {
108 [0] = { 103 [0] = {
109 .name = "TMU1",
110 .start = 0xffd80014, 104 .start = 0xffd80014,
111 .end = 0xffd8001f, 105 .end = 0xffd8001f,
112 .flags = IORESOURCE_MEM, 106 .flags = IORESOURCE_MEM,
@@ -128,15 +122,12 @@ static struct platform_device tmu1_device = {
128}; 122};
129 123
130static struct sh_timer_config tmu2_platform_data = { 124static struct sh_timer_config tmu2_platform_data = {
131 .name = "TMU2",
132 .channel_offset = 0x1c, 125 .channel_offset = 0x1c,
133 .timer_bit = 2, 126 .timer_bit = 2,
134 .clk = "peripheral_clk",
135}; 127};
136 128
137static struct resource tmu2_resources[] = { 129static struct resource tmu2_resources[] = {
138 [0] = { 130 [0] = {
139 .name = "TMU2",
140 .start = 0xffd80020, 131 .start = 0xffd80020,
141 .end = 0xffd8002f, 132 .end = 0xffd8002f,
142 .flags = IORESOURCE_MEM, 133 .flags = IORESOURCE_MEM,
@@ -163,15 +154,12 @@ static struct platform_device tmu2_device = {
163 defined(CONFIG_CPU_SUBTYPE_SH7751R) 154 defined(CONFIG_CPU_SUBTYPE_SH7751R)
164 155
165static struct sh_timer_config tmu3_platform_data = { 156static struct sh_timer_config tmu3_platform_data = {
166 .name = "TMU3",
167 .channel_offset = 0x04, 157 .channel_offset = 0x04,
168 .timer_bit = 0, 158 .timer_bit = 0,
169 .clk = "peripheral_clk",
170}; 159};
171 160
172static struct resource tmu3_resources[] = { 161static struct resource tmu3_resources[] = {
173 [0] = { 162 [0] = {
174 .name = "TMU3",
175 .start = 0xfe100008, 163 .start = 0xfe100008,
176 .end = 0xfe100013, 164 .end = 0xfe100013,
177 .flags = IORESOURCE_MEM, 165 .flags = IORESOURCE_MEM,
@@ -193,15 +181,12 @@ static struct platform_device tmu3_device = {
193}; 181};
194 182
195static struct sh_timer_config tmu4_platform_data = { 183static struct sh_timer_config tmu4_platform_data = {
196 .name = "TMU4",
197 .channel_offset = 0x10, 184 .channel_offset = 0x10,
198 .timer_bit = 1, 185 .timer_bit = 1,
199 .clk = "peripheral_clk",
200}; 186};
201 187
202static struct resource tmu4_resources[] = { 188static struct resource tmu4_resources[] = {
203 [0] = { 189 [0] = {
204 .name = "TMU4",
205 .start = 0xfe100014, 190 .start = 0xfe100014,
206 .end = 0xfe10001f, 191 .end = 0xfe10001f,
207 .flags = IORESOURCE_MEM, 192 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index a16eb3656f4b..48ea8fe85dc5 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -187,16 +187,13 @@ static struct platform_device scif3_device = {
187}; 187};
188 188
189static struct sh_timer_config tmu0_platform_data = { 189static struct sh_timer_config tmu0_platform_data = {
190 .name = "TMU0",
191 .channel_offset = 0x04, 190 .channel_offset = 0x04,
192 .timer_bit = 0, 191 .timer_bit = 0,
193 .clk = "peripheral_clk",
194 .clockevent_rating = 200, 192 .clockevent_rating = 200,
195}; 193};
196 194
197static struct resource tmu0_resources[] = { 195static struct resource tmu0_resources[] = {
198 [0] = { 196 [0] = {
199 .name = "TMU0",
200 .start = 0xffd80008, 197 .start = 0xffd80008,
201 .end = 0xffd80013, 198 .end = 0xffd80013,
202 .flags = IORESOURCE_MEM, 199 .flags = IORESOURCE_MEM,
@@ -218,16 +215,13 @@ static struct platform_device tmu0_device = {
218}; 215};
219 216
220static struct sh_timer_config tmu1_platform_data = { 217static struct sh_timer_config tmu1_platform_data = {
221 .name = "TMU1",
222 .channel_offset = 0x10, 218 .channel_offset = 0x10,
223 .timer_bit = 1, 219 .timer_bit = 1,
224 .clk = "peripheral_clk",
225 .clocksource_rating = 200, 220 .clocksource_rating = 200,
226}; 221};
227 222
228static struct resource tmu1_resources[] = { 223static struct resource tmu1_resources[] = {
229 [0] = { 224 [0] = {
230 .name = "TMU1",
231 .start = 0xffd80014, 225 .start = 0xffd80014,
232 .end = 0xffd8001f, 226 .end = 0xffd8001f,
233 .flags = IORESOURCE_MEM, 227 .flags = IORESOURCE_MEM,
@@ -249,15 +243,12 @@ static struct platform_device tmu1_device = {
249}; 243};
250 244
251static struct sh_timer_config tmu2_platform_data = { 245static struct sh_timer_config tmu2_platform_data = {
252 .name = "TMU2",
253 .channel_offset = 0x1c, 246 .channel_offset = 0x1c,
254 .timer_bit = 2, 247 .timer_bit = 2,
255 .clk = "peripheral_clk",
256}; 248};
257 249
258static struct resource tmu2_resources[] = { 250static struct resource tmu2_resources[] = {
259 [0] = { 251 [0] = {
260 .name = "TMU2",
261 .start = 0xffd80020, 252 .start = 0xffd80020,
262 .end = 0xffd8002f, 253 .end = 0xffd8002f,
263 .flags = IORESOURCE_MEM, 254 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 2c16df37eda6..a63cdcaee0b2 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -154,15 +154,15 @@ static struct clk mstp_clks[] = {
154 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 154 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
155 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 155 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
156 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 156 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
157 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 157 MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
158 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 158 MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
159 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 159 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
160 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 160 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
161 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 161 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
162 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), 162 SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
163 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), 163 SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
164 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), 164 SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
165 MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0), 165 SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
166 MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0), 166 MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
167 MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 167 MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
168 MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 168 MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 91588d280cd8..f99db94cf8fb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -158,14 +158,14 @@ static struct clk mstp_clks[] = {
158 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 158 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
159 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 159 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
160 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 160 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
161 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 161 MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
162 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 162 MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
163 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 163 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
164 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 164 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
165 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 165 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
166 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), 166 SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
167 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), 167 SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
168 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), 168 SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
169 MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 169 MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
170 MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 170 MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
171 171
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 15db6d521c5c..107b200e78bd 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -160,13 +160,13 @@ struct clk div6_clks[] = {
160static struct clk mstp_clks[] = { 160static struct clk mstp_clks[] = {
161 SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT), 161 SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT),
162 SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT), 162 SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT),
163 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU, 0), 163 SH_HWBLK_CLK("tmu_fck", -1, P_CLK, HWBLK_TMU, 0),
164 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), 164 SH_HWBLK_CLK("cmt_fck", -1, R_CLK, HWBLK_CMT, 0),
165 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), 165 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
166 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0), 166 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
167 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), 167 SH_HWBLK_CLK("sci_fck", 0, P_CLK, HWBLK_SCIF0, 0),
168 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), 168 SH_HWBLK_CLK("sci_fck", 1, P_CLK, HWBLK_SCIF1, 0),
169 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), 169 SH_HWBLK_CLK("sci_fck", 2, P_CLK, HWBLK_SCIF2, 0),
170 170
171 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0), 171 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
172 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), 172 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 50babe01fe44..fc86c88223f4 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -21,6 +21,8 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h>
25#include <asm/clkdev.h>
24#include <asm/clock.h> 26#include <asm/clock.h>
25#include <asm/hwblk.h> 27#include <asm/hwblk.h>
26#include <cpu/sh7723.h> 28#include <cpu/sh7723.h>
@@ -171,18 +173,18 @@ static struct clk mstp_clks[] = {
171 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT), 173 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
172 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0), 174 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
173 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0), 175 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
174 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0), 176 SH_HWBLK_CLK("tmu012_fck", -1, P_CLK, HWBLK_TMU0, 0),
175 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), 177 SH_HWBLK_CLK("cmt_fck", -1, R_CLK, HWBLK_CMT, 0),
176 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), 178 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
177 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), 179 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
178 SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), 180 SH_HWBLK_CLK("tmu345_fck", -1, P_CLK, HWBLK_TMU1, 0),
179 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0), 181 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
180 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), 182 SH_HWBLK_CLK("sci_fck", 0, P_CLK, HWBLK_SCIF0, 0),
181 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), 183 SH_HWBLK_CLK("sci_fck", 1, P_CLK, HWBLK_SCIF1, 0),
182 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), 184 SH_HWBLK_CLK("sci_fck", 2, P_CLK, HWBLK_SCIF2, 0),
183 SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), 185 SH_HWBLK_CLK("sci_fck", 3, B_CLK, HWBLK_SCIF3, 0),
184 SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), 186 SH_HWBLK_CLK("sci_fck", 4, B_CLK, HWBLK_SCIF4, 0),
185 SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), 187 SH_HWBLK_CLK("sci_fck", 5, B_CLK, HWBLK_SCIF5, 0),
186 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), 188 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
187 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), 189 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
188 SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0), 190 SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0),
@@ -211,6 +213,40 @@ static struct clk mstp_clks[] = {
211 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0), 213 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
212}; 214};
213 215
216static struct clk_lookup lookups[] = {
217 {
218 /* TMU0 */
219 .dev_id = "sh_tmu.0",
220 .con_id = "tmu_fck",
221 .clk = &mstp_clks[11], /* tmu012_fck */
222 }, {
223 /* TMU1 */
224 .dev_id = "sh_tmu.1",
225 .con_id = "tmu_fck",
226 .clk = &mstp_clks[11],
227 }, {
228 /* TMU2 */
229 .dev_id = "sh_tmu.2",
230 .con_id = "tmu_fck",
231 .clk = &mstp_clks[11],
232 }, {
233 /* TMU3 */
234 .dev_id = "sh_tmu.3",
235 .con_id = "tmu_fck",
236 .clk = &mstp_clks[15], /* tmu345_fck */
237 }, {
238 /* TMU4 */
239 .dev_id = "sh_tmu.4",
240 .con_id = "tmu_fck",
241 .clk = &mstp_clks[15],
242 }, {
243 /* TMU5 */
244 .dev_id = "sh_tmu.5",
245 .con_id = "tmu_fck",
246 .clk = &mstp_clks[15],
247 },
248};
249
214int __init arch_clk_init(void) 250int __init arch_clk_init(void)
215{ 251{
216 int k, ret = 0; 252 int k, ret = 0;
@@ -222,7 +258,9 @@ int __init arch_clk_init(void)
222 pll_clk.parent = &extal_clk; 258 pll_clk.parent = &extal_clk;
223 259
224 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 260 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
225 ret = clk_register(main_clks[k]); 261 ret |= clk_register(main_clks[k]);
262
263 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
226 264
227 if (!ret) 265 if (!ret)
228 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 266 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 6707061fbf54..f1583a23b3a5 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -21,6 +21,8 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h>
25#include <asm/clkdev.h>
24#include <asm/clock.h> 26#include <asm/clock.h>
25#include <asm/hwblk.h> 27#include <asm/hwblk.h>
26#include <cpu/sh7724.h> 28#include <cpu/sh7724.h>
@@ -189,17 +191,17 @@ static struct clk mstp_clks[] = {
189 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT), 191 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
190 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0), 192 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
191 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0), 193 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
192 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0), 194 SH_HWBLK_CLK("tmu012_fck", -1, P_CLK, HWBLK_TMU0, 0),
193 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), 195 SH_HWBLK_CLK("cmt_fck", -1, R_CLK, HWBLK_CMT, 0),
194 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), 196 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
195 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), 197 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
196 SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), 198 SH_HWBLK_CLK("tmu345_fck", -1, P_CLK, HWBLK_TMU1, 0),
197 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), 199 SH_HWBLK_CLK("sci_fck", 0, P_CLK, HWBLK_SCIF0, 0),
198 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), 200 SH_HWBLK_CLK("sci_fck", 1, P_CLK, HWBLK_SCIF1, 0),
199 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), 201 SH_HWBLK_CLK("sci_fck", 2, P_CLK, HWBLK_SCIF2, 0),
200 SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), 202 SH_HWBLK_CLK("sci_fck", 3, B_CLK, HWBLK_SCIF3, 0),
201 SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), 203 SH_HWBLK_CLK("sci_fck", 4, B_CLK, HWBLK_SCIF4, 0),
202 SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), 204 SH_HWBLK_CLK("sci_fck", 5, B_CLK, HWBLK_SCIF5, 0),
203 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), 205 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
204 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), 206 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
205 207
@@ -233,6 +235,40 @@ static struct clk mstp_clks[] = {
233 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0), 235 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
234}; 236};
235 237
238static struct clk_lookup lookups[] = {
239 {
240 /* TMU0 */
241 .dev_id = "sh_tmu.0",
242 .con_id = "tmu_fck",
243 .clk = &mstp_clks[12], /* tmu012_fck */
244 }, {
245 /* TMU1 */
246 .dev_id = "sh_tmu.1",
247 .con_id = "tmu_fck",
248 .clk = &mstp_clks[12],
249 }, {
250 /* TMU2 */
251 .dev_id = "sh_tmu.2",
252 .con_id = "tmu_fck",
253 .clk = &mstp_clks[12],
254 }, {
255 /* TMU3 */
256 .dev_id = "sh_tmu.3",
257 .con_id = "tmu_fck",
258 .clk = &mstp_clks[16], /* tmu345_fck */
259 }, {
260 /* TMU4 */
261 .dev_id = "sh_tmu.4",
262 .con_id = "tmu_fck",
263 .clk = &mstp_clks[16],
264 }, {
265 /* TMU5 */
266 .dev_id = "sh_tmu.5",
267 .con_id = "tmu_fck",
268 .clk = &mstp_clks[16],
269 },
270};
271
236int __init arch_clk_init(void) 272int __init arch_clk_init(void)
237{ 273{
238 int k, ret = 0; 274 int k, ret = 0;
@@ -246,6 +282,8 @@ int __init arch_clk_init(void)
246 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 282 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
247 ret = clk_register(main_clks[k]); 283 ret = clk_register(main_clks[k]);
248 284
285 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
286
249 if (!ret) 287 if (!ret)
250 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 288 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
251 289
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index d997f0a25b10..28de049a59b1 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SH7785 support for the clock framework 4 * SH7785 support for the clock framework
5 * 5 *
6 * Copyright (C) 2007 - 2009 Paul Mundt 6 * Copyright (C) 2007 - 2010 Paul Mundt
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -14,6 +14,7 @@
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/cpufreq.h> 16#include <linux/cpufreq.h>
17#include <asm/clkdev.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18#include <asm/freq.h> 19#include <asm/freq.h>
19#include <cpu/sh7785.h> 20#include <cpu/sh7785.h>
@@ -88,12 +89,12 @@ struct clk div4_clks[DIV4_NR] = {
88 89
89static struct clk mstp_clks[] = { 90static struct clk mstp_clks[] = {
90 /* MSTPCR0 */ 91 /* MSTPCR0 */
91 SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 92 SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
92 SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 93 SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
93 SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 94 SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
94 SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 95 SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
95 SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 96 SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
96 SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 97 SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
97 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 98 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
98 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 99 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
99 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 100 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
@@ -113,12 +114,48 @@ static struct clk mstp_clks[] = {
113 SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0), 114 SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
114}; 115};
115 116
117static struct clk_lookup lookups[] = {
118 {
119 /* TMU0 */
120 .dev_id = "sh_tmu.0",
121 .con_id = "tmu_fck",
122 .clk = &mstp_clks[13], /* tmu012_fck */
123 }, {
124 /* TMU1 */
125 .dev_id = "sh_tmu.1",
126 .con_id = "tmu_fck",
127 .clk = &mstp_clks[13],
128 }, {
129 /* TMU2 */
130 .dev_id = "sh_tmu.2",
131 .con_id = "tmu_fck",
132 .clk = &mstp_clks[13],
133 }, {
134 /* TMU3 */
135 .dev_id = "sh_tmu.3",
136 .con_id = "tmu_fck",
137 .clk = &mstp_clks[12], /* tmu345_fck */
138 }, {
139 /* TMU4 */
140 .dev_id = "sh_tmu.4",
141 .con_id = "tmu_fck",
142 .clk = &mstp_clks[12],
143 }, {
144 /* TMU5 */
145 .dev_id = "sh_tmu.5",
146 .con_id = "tmu_fck",
147 .clk = &mstp_clks[12],
148 },
149};
150
116int __init arch_clk_init(void) 151int __init arch_clk_init(void)
117{ 152{
118 int i, ret = 0; 153 int i, ret = 0;
119 154
120 for (i = 0; i < ARRAY_SIZE(clks); i++) 155 for (i = 0; i < ARRAY_SIZE(clks); i++)
121 ret |= clk_register(clks[i]); 156 ret |= clk_register(clks[i]);
157 for (i = 0; i < ARRAY_SIZE(lookups); i++)
158 clkdev_add(&lookups[i]);
122 159
123 if (!ret) 160 if (!ret)
124 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 161 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index af69fd468703..c4a84bb2f3d9 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -13,6 +13,8 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/clk.h>
17#include <asm/clkdev.h>
16#include <asm/clock.h> 18#include <asm/clock.h>
17#include <asm/freq.h> 19#include <asm/freq.h>
18 20
@@ -87,12 +89,12 @@ struct clk div4_clks[DIV4_NR] = {
87 89
88static struct clk mstp_clks[] = { 90static struct clk mstp_clks[] = {
89 /* MSTPCR0 */ 91 /* MSTPCR0 */
90 SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 92 SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
91 SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 93 SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
92 SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 94 SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
93 SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 95 SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
94 SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 96 SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
95 SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 97 SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
96 SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0), 98 SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
97 SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0), 99 SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
98 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 100 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
@@ -120,12 +122,78 @@ static struct clk mstp_clks[] = {
120 SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0), 122 SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
121}; 123};
122 124
125static struct clk_lookup lookups[] = {
126 {
127 /* TMU0 */
128 .dev_id = "sh_tmu.0",
129 .con_id = "tmu_fck",
130 .clk = &mstp_clks[17], /* tmu012_fck */
131 }, {
132 /* TMU1 */
133 .dev_id = "sh_tmu.1",
134 .con_id = "tmu_fck",
135 .clk = &mstp_clks[17],
136 }, {
137 /* TMU2 */
138 .dev_id = "sh_tmu.2",
139 .con_id = "tmu_fck",
140 .clk = &mstp_clks[17],
141 }, {
142 /* TMU3 */
143 .dev_id = "sh_tmu.3",
144 .con_id = "tmu_fck",
145 .clk = &mstp_clks[16], /* tmu345_fck */
146 }, {
147 /* TMU4 */
148 .dev_id = "sh_tmu.4",
149 .con_id = "tmu_fck",
150 .clk = &mstp_clks[16],
151 }, {
152 /* TMU5 */
153 .dev_id = "sh_tmu.5",
154 .con_id = "tmu_fck",
155 .clk = &mstp_clks[16],
156 }, {
157 /* TMU6 */
158 .dev_id = "sh_tmu.6",
159 .con_id = "tmu_fck",
160 .clk = &mstp_clks[15], /* tmu678_fck */
161 }, {
162 /* TMU7 */
163 .dev_id = "sh_tmu.7",
164 .con_id = "tmu_fck",
165 .clk = &mstp_clks[15],
166 }, {
167 /* TMU8 */
168 .dev_id = "sh_tmu.8",
169 .con_id = "tmu_fck",
170 .clk = &mstp_clks[15],
171 }, {
172 /* TMU9 */
173 .dev_id = "sh_tmu.9",
174 .con_id = "tmu_fck",
175 .clk = &mstp_clks[14], /* tmu9_11_fck */
176 }, {
177 /* TMU10 */
178 .dev_id = "sh_tmu.10",
179 .con_id = "tmu_fck",
180 .clk = &mstp_clks[14],
181 }, {
182 /* TMU11 */
183 .dev_id = "sh_tmu.11",
184 .con_id = "tmu_fck",
185 .clk = &mstp_clks[14],
186 }
187};
188
123int __init arch_clk_init(void) 189int __init arch_clk_init(void)
124{ 190{
125 int i, ret = 0; 191 int i, ret = 0;
126 192
127 for (i = 0; i < ARRAY_SIZE(clks); i++) 193 for (i = 0; i < ARRAY_SIZE(clks); i++)
128 ret |= clk_register(clks[i]); 194 ret |= clk_register(clks[i]);
195 for (i = 0; i < ARRAY_SIZE(lookups); i++)
196 clkdev_add(&lookups[i]);
129 197
130 if (!ret) 198 if (!ret)
131 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 199 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 45eb1bfd42c9..3681cafdb4af 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -21,7 +21,6 @@ static struct plat_sci_port scif0_platform_data = {
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .type = PORT_SCIF, 22 .type = PORT_SCIF,
23 .irqs = { 80, 80, 80, 80 }, 23 .irqs = { 80, 80, 80, 80 },
24 .clk = "scif0",
25}; 24};
26 25
27static struct platform_device scif0_device = { 26static struct platform_device scif0_device = {
@@ -37,7 +36,6 @@ static struct plat_sci_port scif1_platform_data = {
37 .flags = UPF_BOOT_AUTOCONF, 36 .flags = UPF_BOOT_AUTOCONF,
38 .type = PORT_SCIF, 37 .type = PORT_SCIF,
39 .irqs = { 81, 81, 81, 81 }, 38 .irqs = { 81, 81, 81, 81 },
40 .clk = "scif1",
41}; 39};
42 40
43static struct platform_device scif1_device = { 41static struct platform_device scif1_device = {
@@ -53,7 +51,6 @@ static struct plat_sci_port scif2_platform_data = {
53 .flags = UPF_BOOT_AUTOCONF, 51 .flags = UPF_BOOT_AUTOCONF,
54 .type = PORT_SCIF, 52 .type = PORT_SCIF,
55 .irqs = { 82, 82, 82, 82 }, 53 .irqs = { 82, 82, 82, 82 },
56 .clk = "scif2",
57}; 54};
58 55
59static struct platform_device scif2_device = { 56static struct platform_device scif2_device = {
@@ -69,7 +66,6 @@ static struct plat_sci_port scif3_platform_data = {
69 .flags = UPF_BOOT_AUTOCONF, 66 .flags = UPF_BOOT_AUTOCONF,
70 .type = PORT_SCIF, 67 .type = PORT_SCIF,
71 .irqs = { 83, 83, 83, 83 }, 68 .irqs = { 83, 83, 83, 83 },
72 .clk = "scif3",
73}; 69};
74 70
75static struct platform_device scif3_device = { 71static struct platform_device scif3_device = {
@@ -207,17 +203,14 @@ static struct platform_device jpu_device = {
207}; 203};
208 204
209static struct sh_timer_config cmt_platform_data = { 205static struct sh_timer_config cmt_platform_data = {
210 .name = "CMT",
211 .channel_offset = 0x60, 206 .channel_offset = 0x60,
212 .timer_bit = 5, 207 .timer_bit = 5,
213 .clk = "cmt0",
214 .clockevent_rating = 125, 208 .clockevent_rating = 125,
215 .clocksource_rating = 200, 209 .clocksource_rating = 200,
216}; 210};
217 211
218static struct resource cmt_resources[] = { 212static struct resource cmt_resources[] = {
219 [0] = { 213 [0] = {
220 .name = "CMT",
221 .start = 0x044a0060, 214 .start = 0x044a0060,
222 .end = 0x044a006b, 215 .end = 0x044a006b,
223 .flags = IORESOURCE_MEM, 216 .flags = IORESOURCE_MEM,
@@ -239,16 +232,13 @@ static struct platform_device cmt_device = {
239}; 232};
240 233
241static struct sh_timer_config tmu0_platform_data = { 234static struct sh_timer_config tmu0_platform_data = {
242 .name = "TMU0",
243 .channel_offset = 0x04, 235 .channel_offset = 0x04,
244 .timer_bit = 0, 236 .timer_bit = 0,
245 .clk = "tmu0",
246 .clockevent_rating = 200, 237 .clockevent_rating = 200,
247}; 238};
248 239
249static struct resource tmu0_resources[] = { 240static struct resource tmu0_resources[] = {
250 [0] = { 241 [0] = {
251 .name = "TMU0",
252 .start = 0xffd80008, 242 .start = 0xffd80008,
253 .end = 0xffd80013, 243 .end = 0xffd80013,
254 .flags = IORESOURCE_MEM, 244 .flags = IORESOURCE_MEM,
@@ -270,16 +260,13 @@ static struct platform_device tmu0_device = {
270}; 260};
271 261
272static struct sh_timer_config tmu1_platform_data = { 262static struct sh_timer_config tmu1_platform_data = {
273 .name = "TMU1",
274 .channel_offset = 0x10, 263 .channel_offset = 0x10,
275 .timer_bit = 1, 264 .timer_bit = 1,
276 .clk = "tmu0",
277 .clocksource_rating = 200, 265 .clocksource_rating = 200,
278}; 266};
279 267
280static struct resource tmu1_resources[] = { 268static struct resource tmu1_resources[] = {
281 [0] = { 269 [0] = {
282 .name = "TMU1",
283 .start = 0xffd80014, 270 .start = 0xffd80014,
284 .end = 0xffd8001f, 271 .end = 0xffd8001f,
285 .flags = IORESOURCE_MEM, 272 .flags = IORESOURCE_MEM,
@@ -301,15 +288,12 @@ static struct platform_device tmu1_device = {
301}; 288};
302 289
303static struct sh_timer_config tmu2_platform_data = { 290static struct sh_timer_config tmu2_platform_data = {
304 .name = "TMU2",
305 .channel_offset = 0x1c, 291 .channel_offset = 0x1c,
306 .timer_bit = 2, 292 .timer_bit = 2,
307 .clk = "tmu0",
308}; 293};
309 294
310static struct resource tmu2_resources[] = { 295static struct resource tmu2_resources[] = {
311 [0] = { 296 [0] = {
312 .name = "TMU2",
313 .start = 0xffd80020, 297 .start = 0xffd80020,
314 .end = 0xffd8002b, 298 .end = 0xffd8002b,
315 .flags = IORESOURCE_MEM, 299 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index c494c193e3b6..8dab9e1bbd89 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -23,7 +23,6 @@ static struct plat_sci_port scif0_platform_data = {
23 .flags = UPF_BOOT_AUTOCONF, 23 .flags = UPF_BOOT_AUTOCONF,
24 .type = PORT_SCIF, 24 .type = PORT_SCIF,
25 .irqs = { 80, 80, 80, 80 }, 25 .irqs = { 80, 80, 80, 80 },
26 .clk = "scif0",
27}; 26};
28 27
29static struct platform_device scif0_device = { 28static struct platform_device scif0_device = {
@@ -169,17 +168,14 @@ static struct platform_device veu1_device = {
169}; 168};
170 169
171static struct sh_timer_config cmt_platform_data = { 170static struct sh_timer_config cmt_platform_data = {
172 .name = "CMT",
173 .channel_offset = 0x60, 171 .channel_offset = 0x60,
174 .timer_bit = 5, 172 .timer_bit = 5,
175 .clk = "cmt0",
176 .clockevent_rating = 125, 173 .clockevent_rating = 125,
177 .clocksource_rating = 200, 174 .clocksource_rating = 200,
178}; 175};
179 176
180static struct resource cmt_resources[] = { 177static struct resource cmt_resources[] = {
181 [0] = { 178 [0] = {
182 .name = "CMT",
183 .start = 0x044a0060, 179 .start = 0x044a0060,
184 .end = 0x044a006b, 180 .end = 0x044a006b,
185 .flags = IORESOURCE_MEM, 181 .flags = IORESOURCE_MEM,
@@ -201,16 +197,13 @@ static struct platform_device cmt_device = {
201}; 197};
202 198
203static struct sh_timer_config tmu0_platform_data = { 199static struct sh_timer_config tmu0_platform_data = {
204 .name = "TMU0",
205 .channel_offset = 0x04, 200 .channel_offset = 0x04,
206 .timer_bit = 0, 201 .timer_bit = 0,
207 .clk = "tmu0",
208 .clockevent_rating = 200, 202 .clockevent_rating = 200,
209}; 203};
210 204
211static struct resource tmu0_resources[] = { 205static struct resource tmu0_resources[] = {
212 [0] = { 206 [0] = {
213 .name = "TMU0",
214 .start = 0xffd80008, 207 .start = 0xffd80008,
215 .end = 0xffd80013, 208 .end = 0xffd80013,
216 .flags = IORESOURCE_MEM, 209 .flags = IORESOURCE_MEM,
@@ -232,16 +225,13 @@ static struct platform_device tmu0_device = {
232}; 225};
233 226
234static struct sh_timer_config tmu1_platform_data = { 227static struct sh_timer_config tmu1_platform_data = {
235 .name = "TMU1",
236 .channel_offset = 0x10, 228 .channel_offset = 0x10,
237 .timer_bit = 1, 229 .timer_bit = 1,
238 .clk = "tmu0",
239 .clocksource_rating = 200, 230 .clocksource_rating = 200,
240}; 231};
241 232
242static struct resource tmu1_resources[] = { 233static struct resource tmu1_resources[] = {
243 [0] = { 234 [0] = {
244 .name = "TMU1",
245 .start = 0xffd80014, 235 .start = 0xffd80014,
246 .end = 0xffd8001f, 236 .end = 0xffd8001f,
247 .flags = IORESOURCE_MEM, 237 .flags = IORESOURCE_MEM,
@@ -263,15 +253,12 @@ static struct platform_device tmu1_device = {
263}; 253};
264 254
265static struct sh_timer_config tmu2_platform_data = { 255static struct sh_timer_config tmu2_platform_data = {
266 .name = "TMU2",
267 .channel_offset = 0x1c, 256 .channel_offset = 0x1c,
268 .timer_bit = 2, 257 .timer_bit = 2,
269 .clk = "tmu0",
270}; 258};
271 259
272static struct resource tmu2_resources[] = { 260static struct resource tmu2_resources[] = {
273 [0] = { 261 [0] = {
274 .name = "TMU2",
275 .start = 0xffd80020, 262 .start = 0xffd80020,
276 .end = 0xffd8002b, 263 .end = 0xffd8002b,
277 .flags = IORESOURCE_MEM, 264 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index fd7e3639e845..dc9b30d086a4 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -174,7 +174,6 @@ static struct plat_sci_port scif0_platform_data = {
174 .flags = UPF_BOOT_AUTOCONF, 174 .flags = UPF_BOOT_AUTOCONF,
175 .type = PORT_SCIF, 175 .type = PORT_SCIF,
176 .irqs = { 80, 80, 80, 80 }, 176 .irqs = { 80, 80, 80, 80 },
177 .clk = "scif0",
178}; 177};
179 178
180static struct platform_device scif0_device = { 179static struct platform_device scif0_device = {
@@ -190,7 +189,6 @@ static struct plat_sci_port scif1_platform_data = {
190 .flags = UPF_BOOT_AUTOCONF, 189 .flags = UPF_BOOT_AUTOCONF,
191 .type = PORT_SCIF, 190 .type = PORT_SCIF,
192 .irqs = { 81, 81, 81, 81 }, 191 .irqs = { 81, 81, 81, 81 },
193 .clk = "scif1",
194}; 192};
195 193
196static struct platform_device scif1_device = { 194static struct platform_device scif1_device = {
@@ -206,7 +204,6 @@ static struct plat_sci_port scif2_platform_data = {
206 .flags = UPF_BOOT_AUTOCONF, 204 .flags = UPF_BOOT_AUTOCONF,
207 .type = PORT_SCIF, 205 .type = PORT_SCIF,
208 .irqs = { 82, 82, 82, 82 }, 206 .irqs = { 82, 82, 82, 82 },
209 .clk = "scif2",
210}; 207};
211 208
212static struct platform_device scif2_device = { 209static struct platform_device scif2_device = {
@@ -401,17 +398,14 @@ static struct platform_device jpu_device = {
401}; 398};
402 399
403static struct sh_timer_config cmt_platform_data = { 400static struct sh_timer_config cmt_platform_data = {
404 .name = "CMT",
405 .channel_offset = 0x60, 401 .channel_offset = 0x60,
406 .timer_bit = 5, 402 .timer_bit = 5,
407 .clk = "cmt0",
408 .clockevent_rating = 125, 403 .clockevent_rating = 125,
409 .clocksource_rating = 125, 404 .clocksource_rating = 125,
410}; 405};
411 406
412static struct resource cmt_resources[] = { 407static struct resource cmt_resources[] = {
413 [0] = { 408 [0] = {
414 .name = "CMT",
415 .start = 0x044a0060, 409 .start = 0x044a0060,
416 .end = 0x044a006b, 410 .end = 0x044a006b,
417 .flags = IORESOURCE_MEM, 411 .flags = IORESOURCE_MEM,
@@ -436,16 +430,13 @@ static struct platform_device cmt_device = {
436}; 430};
437 431
438static struct sh_timer_config tmu0_platform_data = { 432static struct sh_timer_config tmu0_platform_data = {
439 .name = "TMU0",
440 .channel_offset = 0x04, 433 .channel_offset = 0x04,
441 .timer_bit = 0, 434 .timer_bit = 0,
442 .clk = "tmu0",
443 .clockevent_rating = 200, 435 .clockevent_rating = 200,
444}; 436};
445 437
446static struct resource tmu0_resources[] = { 438static struct resource tmu0_resources[] = {
447 [0] = { 439 [0] = {
448 .name = "TMU0",
449 .start = 0xffd80008, 440 .start = 0xffd80008,
450 .end = 0xffd80013, 441 .end = 0xffd80013,
451 .flags = IORESOURCE_MEM, 442 .flags = IORESOURCE_MEM,
@@ -470,16 +461,13 @@ static struct platform_device tmu0_device = {
470}; 461};
471 462
472static struct sh_timer_config tmu1_platform_data = { 463static struct sh_timer_config tmu1_platform_data = {
473 .name = "TMU1",
474 .channel_offset = 0x10, 464 .channel_offset = 0x10,
475 .timer_bit = 1, 465 .timer_bit = 1,
476 .clk = "tmu0",
477 .clocksource_rating = 200, 466 .clocksource_rating = 200,
478}; 467};
479 468
480static struct resource tmu1_resources[] = { 469static struct resource tmu1_resources[] = {
481 [0] = { 470 [0] = {
482 .name = "TMU1",
483 .start = 0xffd80014, 471 .start = 0xffd80014,
484 .end = 0xffd8001f, 472 .end = 0xffd8001f,
485 .flags = IORESOURCE_MEM, 473 .flags = IORESOURCE_MEM,
@@ -504,15 +492,12 @@ static struct platform_device tmu1_device = {
504}; 492};
505 493
506static struct sh_timer_config tmu2_platform_data = { 494static struct sh_timer_config tmu2_platform_data = {
507 .name = "TMU2",
508 .channel_offset = 0x1c, 495 .channel_offset = 0x1c,
509 .timer_bit = 2, 496 .timer_bit = 2,
510 .clk = "tmu0",
511}; 497};
512 498
513static struct resource tmu2_resources[] = { 499static struct resource tmu2_resources[] = {
514 [0] = { 500 [0] = {
515 .name = "TMU2",
516 .start = 0xffd80020, 501 .start = 0xffd80020,
517 .end = 0xffd8002b, 502 .end = 0xffd8002b,
518 .flags = IORESOURCE_MEM, 503 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 85c61f624702..0eadefdbbba1 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -26,7 +26,6 @@ static struct plat_sci_port scif0_platform_data = {
26 .flags = UPF_BOOT_AUTOCONF, 26 .flags = UPF_BOOT_AUTOCONF,
27 .type = PORT_SCIF, 27 .type = PORT_SCIF,
28 .irqs = { 80, 80, 80, 80 }, 28 .irqs = { 80, 80, 80, 80 },
29 .clk = "scif0",
30}; 29};
31 30
32static struct platform_device scif0_device = { 31static struct platform_device scif0_device = {
@@ -42,7 +41,6 @@ static struct plat_sci_port scif1_platform_data = {
42 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
43 .type = PORT_SCIF, 42 .type = PORT_SCIF,
44 .irqs = { 81, 81, 81, 81 }, 43 .irqs = { 81, 81, 81, 81 },
45 .clk = "scif1",
46}; 44};
47 45
48static struct platform_device scif1_device = { 46static struct platform_device scif1_device = {
@@ -58,7 +56,6 @@ static struct plat_sci_port scif2_platform_data = {
58 .flags = UPF_BOOT_AUTOCONF, 56 .flags = UPF_BOOT_AUTOCONF,
59 .type = PORT_SCIF, 57 .type = PORT_SCIF,
60 .irqs = { 82, 82, 82, 82 }, 58 .irqs = { 82, 82, 82, 82 },
61 .clk = "scif2",
62}; 59};
63 60
64static struct platform_device scif2_device = { 61static struct platform_device scif2_device = {
@@ -74,7 +71,6 @@ static struct plat_sci_port scif3_platform_data = {
74 .flags = UPF_BOOT_AUTOCONF, 71 .flags = UPF_BOOT_AUTOCONF,
75 .type = PORT_SCIFA, 72 .type = PORT_SCIFA,
76 .irqs = { 56, 56, 56, 56 }, 73 .irqs = { 56, 56, 56, 56 },
77 .clk = "scif3",
78}; 74};
79 75
80static struct platform_device scif3_device = { 76static struct platform_device scif3_device = {
@@ -90,7 +86,6 @@ static struct plat_sci_port scif4_platform_data = {
90 .flags = UPF_BOOT_AUTOCONF, 86 .flags = UPF_BOOT_AUTOCONF,
91 .type = PORT_SCIFA, 87 .type = PORT_SCIFA,
92 .irqs = { 88, 88, 88, 88 }, 88 .irqs = { 88, 88, 88, 88 },
93 .clk = "scif4",
94}; 89};
95 90
96static struct platform_device scif4_device = { 91static struct platform_device scif4_device = {
@@ -106,7 +101,6 @@ static struct plat_sci_port scif5_platform_data = {
106 .flags = UPF_BOOT_AUTOCONF, 101 .flags = UPF_BOOT_AUTOCONF,
107 .type = PORT_SCIFA, 102 .type = PORT_SCIFA,
108 .irqs = { 109, 109, 109, 109 }, 103 .irqs = { 109, 109, 109, 109 },
109 .clk = "scif5",
110}; 104};
111 105
112static struct platform_device scif5_device = { 106static struct platform_device scif5_device = {
@@ -211,17 +205,14 @@ static struct platform_device veu1_device = {
211}; 205};
212 206
213static struct sh_timer_config cmt_platform_data = { 207static struct sh_timer_config cmt_platform_data = {
214 .name = "CMT",
215 .channel_offset = 0x60, 208 .channel_offset = 0x60,
216 .timer_bit = 5, 209 .timer_bit = 5,
217 .clk = "cmt0",
218 .clockevent_rating = 125, 210 .clockevent_rating = 125,
219 .clocksource_rating = 125, 211 .clocksource_rating = 125,
220}; 212};
221 213
222static struct resource cmt_resources[] = { 214static struct resource cmt_resources[] = {
223 [0] = { 215 [0] = {
224 .name = "CMT",
225 .start = 0x044a0060, 216 .start = 0x044a0060,
226 .end = 0x044a006b, 217 .end = 0x044a006b,
227 .flags = IORESOURCE_MEM, 218 .flags = IORESOURCE_MEM,
@@ -246,16 +237,13 @@ static struct platform_device cmt_device = {
246}; 237};
247 238
248static struct sh_timer_config tmu0_platform_data = { 239static struct sh_timer_config tmu0_platform_data = {
249 .name = "TMU0",
250 .channel_offset = 0x04, 240 .channel_offset = 0x04,
251 .timer_bit = 0, 241 .timer_bit = 0,
252 .clk = "tmu0",
253 .clockevent_rating = 200, 242 .clockevent_rating = 200,
254}; 243};
255 244
256static struct resource tmu0_resources[] = { 245static struct resource tmu0_resources[] = {
257 [0] = { 246 [0] = {
258 .name = "TMU0",
259 .start = 0xffd80008, 247 .start = 0xffd80008,
260 .end = 0xffd80013, 248 .end = 0xffd80013,
261 .flags = IORESOURCE_MEM, 249 .flags = IORESOURCE_MEM,
@@ -280,16 +268,13 @@ static struct platform_device tmu0_device = {
280}; 268};
281 269
282static struct sh_timer_config tmu1_platform_data = { 270static struct sh_timer_config tmu1_platform_data = {
283 .name = "TMU1",
284 .channel_offset = 0x10, 271 .channel_offset = 0x10,
285 .timer_bit = 1, 272 .timer_bit = 1,
286 .clk = "tmu0",
287 .clocksource_rating = 200, 273 .clocksource_rating = 200,
288}; 274};
289 275
290static struct resource tmu1_resources[] = { 276static struct resource tmu1_resources[] = {
291 [0] = { 277 [0] = {
292 .name = "TMU1",
293 .start = 0xffd80014, 278 .start = 0xffd80014,
294 .end = 0xffd8001f, 279 .end = 0xffd8001f,
295 .flags = IORESOURCE_MEM, 280 .flags = IORESOURCE_MEM,
@@ -314,15 +299,12 @@ static struct platform_device tmu1_device = {
314}; 299};
315 300
316static struct sh_timer_config tmu2_platform_data = { 301static struct sh_timer_config tmu2_platform_data = {
317 .name = "TMU2",
318 .channel_offset = 0x1c, 302 .channel_offset = 0x1c,
319 .timer_bit = 2, 303 .timer_bit = 2,
320 .clk = "tmu0",
321}; 304};
322 305
323static struct resource tmu2_resources[] = { 306static struct resource tmu2_resources[] = {
324 [0] = { 307 [0] = {
325 .name = "TMU2",
326 .start = 0xffd80020, 308 .start = 0xffd80020,
327 .end = 0xffd8002b, 309 .end = 0xffd8002b,
328 .flags = IORESOURCE_MEM, 310 .flags = IORESOURCE_MEM,
@@ -347,15 +329,12 @@ static struct platform_device tmu2_device = {
347}; 329};
348 330
349static struct sh_timer_config tmu3_platform_data = { 331static struct sh_timer_config tmu3_platform_data = {
350 .name = "TMU3",
351 .channel_offset = 0x04, 332 .channel_offset = 0x04,
352 .timer_bit = 0, 333 .timer_bit = 0,
353 .clk = "tmu1",
354}; 334};
355 335
356static struct resource tmu3_resources[] = { 336static struct resource tmu3_resources[] = {
357 [0] = { 337 [0] = {
358 .name = "TMU3",
359 .start = 0xffd90008, 338 .start = 0xffd90008,
360 .end = 0xffd90013, 339 .end = 0xffd90013,
361 .flags = IORESOURCE_MEM, 340 .flags = IORESOURCE_MEM,
@@ -380,15 +359,12 @@ static struct platform_device tmu3_device = {
380}; 359};
381 360
382static struct sh_timer_config tmu4_platform_data = { 361static struct sh_timer_config tmu4_platform_data = {
383 .name = "TMU4",
384 .channel_offset = 0x10, 362 .channel_offset = 0x10,
385 .timer_bit = 1, 363 .timer_bit = 1,
386 .clk = "tmu1",
387}; 364};
388 365
389static struct resource tmu4_resources[] = { 366static struct resource tmu4_resources[] = {
390 [0] = { 367 [0] = {
391 .name = "TMU4",
392 .start = 0xffd90014, 368 .start = 0xffd90014,
393 .end = 0xffd9001f, 369 .end = 0xffd9001f,
394 .flags = IORESOURCE_MEM, 370 .flags = IORESOURCE_MEM,
@@ -413,15 +389,12 @@ static struct platform_device tmu4_device = {
413}; 389};
414 390
415static struct sh_timer_config tmu5_platform_data = { 391static struct sh_timer_config tmu5_platform_data = {
416 .name = "TMU5",
417 .channel_offset = 0x1c, 392 .channel_offset = 0x1c,
418 .timer_bit = 2, 393 .timer_bit = 2,
419 .clk = "tmu1",
420}; 394};
421 395
422static struct resource tmu5_resources[] = { 396static struct resource tmu5_resources[] = {
423 [0] = { 397 [0] = {
424 .name = "TMU5",
425 .start = 0xffd90020, 398 .start = 0xffd90020,
426 .end = 0xffd9002b, 399 .end = 0xffd9002b,
427 .flags = IORESOURCE_MEM, 400 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index e7fa2a92fc1f..8a0a4a99f86b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -213,7 +213,6 @@ static struct plat_sci_port scif0_platform_data = {
213 .flags = UPF_BOOT_AUTOCONF, 213 .flags = UPF_BOOT_AUTOCONF,
214 .type = PORT_SCIF, 214 .type = PORT_SCIF,
215 .irqs = { 80, 80, 80, 80 }, 215 .irqs = { 80, 80, 80, 80 },
216 .clk = "scif0",
217}; 216};
218 217
219static struct platform_device scif0_device = { 218static struct platform_device scif0_device = {
@@ -229,7 +228,6 @@ static struct plat_sci_port scif1_platform_data = {
229 .flags = UPF_BOOT_AUTOCONF, 228 .flags = UPF_BOOT_AUTOCONF,
230 .type = PORT_SCIF, 229 .type = PORT_SCIF,
231 .irqs = { 81, 81, 81, 81 }, 230 .irqs = { 81, 81, 81, 81 },
232 .clk = "scif1",
233}; 231};
234 232
235static struct platform_device scif1_device = { 233static struct platform_device scif1_device = {
@@ -245,7 +243,6 @@ static struct plat_sci_port scif2_platform_data = {
245 .flags = UPF_BOOT_AUTOCONF, 243 .flags = UPF_BOOT_AUTOCONF,
246 .type = PORT_SCIF, 244 .type = PORT_SCIF,
247 .irqs = { 82, 82, 82, 82 }, 245 .irqs = { 82, 82, 82, 82 },
248 .clk = "scif2",
249}; 246};
250 247
251static struct platform_device scif2_device = { 248static struct platform_device scif2_device = {
@@ -261,7 +258,6 @@ static struct plat_sci_port scif3_platform_data = {
261 .flags = UPF_BOOT_AUTOCONF, 258 .flags = UPF_BOOT_AUTOCONF,
262 .type = PORT_SCIFA, 259 .type = PORT_SCIFA,
263 .irqs = { 56, 56, 56, 56 }, 260 .irqs = { 56, 56, 56, 56 },
264 .clk = "scif3",
265}; 261};
266 262
267static struct platform_device scif3_device = { 263static struct platform_device scif3_device = {
@@ -277,7 +273,6 @@ static struct plat_sci_port scif4_platform_data = {
277 .flags = UPF_BOOT_AUTOCONF, 273 .flags = UPF_BOOT_AUTOCONF,
278 .type = PORT_SCIFA, 274 .type = PORT_SCIFA,
279 .irqs = { 88, 88, 88, 88 }, 275 .irqs = { 88, 88, 88, 88 },
280 .clk = "scif4",
281}; 276};
282 277
283static struct platform_device scif4_device = { 278static struct platform_device scif4_device = {
@@ -293,7 +288,6 @@ static struct plat_sci_port scif5_platform_data = {
293 .flags = UPF_BOOT_AUTOCONF, 288 .flags = UPF_BOOT_AUTOCONF,
294 .type = PORT_SCIFA, 289 .type = PORT_SCIFA,
295 .irqs = { 109, 109, 109, 109 }, 290 .irqs = { 109, 109, 109, 109 },
296 .clk = "scif5",
297}; 291};
298 292
299static struct platform_device scif5_device = { 293static struct platform_device scif5_device = {
@@ -485,17 +479,14 @@ static struct platform_device veu1_device = {
485}; 479};
486 480
487static struct sh_timer_config cmt_platform_data = { 481static struct sh_timer_config cmt_platform_data = {
488 .name = "CMT",
489 .channel_offset = 0x60, 482 .channel_offset = 0x60,
490 .timer_bit = 5, 483 .timer_bit = 5,
491 .clk = "cmt0",
492 .clockevent_rating = 125, 484 .clockevent_rating = 125,
493 .clocksource_rating = 200, 485 .clocksource_rating = 200,
494}; 486};
495 487
496static struct resource cmt_resources[] = { 488static struct resource cmt_resources[] = {
497 [0] = { 489 [0] = {
498 .name = "CMT",
499 .start = 0x044a0060, 490 .start = 0x044a0060,
500 .end = 0x044a006b, 491 .end = 0x044a006b,
501 .flags = IORESOURCE_MEM, 492 .flags = IORESOURCE_MEM,
@@ -520,16 +511,13 @@ static struct platform_device cmt_device = {
520}; 511};
521 512
522static struct sh_timer_config tmu0_platform_data = { 513static struct sh_timer_config tmu0_platform_data = {
523 .name = "TMU0",
524 .channel_offset = 0x04, 514 .channel_offset = 0x04,
525 .timer_bit = 0, 515 .timer_bit = 0,
526 .clk = "tmu0",
527 .clockevent_rating = 200, 516 .clockevent_rating = 200,
528}; 517};
529 518
530static struct resource tmu0_resources[] = { 519static struct resource tmu0_resources[] = {
531 [0] = { 520 [0] = {
532 .name = "TMU0",
533 .start = 0xffd80008, 521 .start = 0xffd80008,
534 .end = 0xffd80013, 522 .end = 0xffd80013,
535 .flags = IORESOURCE_MEM, 523 .flags = IORESOURCE_MEM,
@@ -554,16 +542,13 @@ static struct platform_device tmu0_device = {
554}; 542};
555 543
556static struct sh_timer_config tmu1_platform_data = { 544static struct sh_timer_config tmu1_platform_data = {
557 .name = "TMU1",
558 .channel_offset = 0x10, 545 .channel_offset = 0x10,
559 .timer_bit = 1, 546 .timer_bit = 1,
560 .clk = "tmu0",
561 .clocksource_rating = 200, 547 .clocksource_rating = 200,
562}; 548};
563 549
564static struct resource tmu1_resources[] = { 550static struct resource tmu1_resources[] = {
565 [0] = { 551 [0] = {
566 .name = "TMU1",
567 .start = 0xffd80014, 552 .start = 0xffd80014,
568 .end = 0xffd8001f, 553 .end = 0xffd8001f,
569 .flags = IORESOURCE_MEM, 554 .flags = IORESOURCE_MEM,
@@ -588,15 +573,12 @@ static struct platform_device tmu1_device = {
588}; 573};
589 574
590static struct sh_timer_config tmu2_platform_data = { 575static struct sh_timer_config tmu2_platform_data = {
591 .name = "TMU2",
592 .channel_offset = 0x1c, 576 .channel_offset = 0x1c,
593 .timer_bit = 2, 577 .timer_bit = 2,
594 .clk = "tmu0",
595}; 578};
596 579
597static struct resource tmu2_resources[] = { 580static struct resource tmu2_resources[] = {
598 [0] = { 581 [0] = {
599 .name = "TMU2",
600 .start = 0xffd80020, 582 .start = 0xffd80020,
601 .end = 0xffd8002b, 583 .end = 0xffd8002b,
602 .flags = IORESOURCE_MEM, 584 .flags = IORESOURCE_MEM,
@@ -622,15 +604,12 @@ static struct platform_device tmu2_device = {
622 604
623 605
624static struct sh_timer_config tmu3_platform_data = { 606static struct sh_timer_config tmu3_platform_data = {
625 .name = "TMU3",
626 .channel_offset = 0x04, 607 .channel_offset = 0x04,
627 .timer_bit = 0, 608 .timer_bit = 0,
628 .clk = "tmu1",
629}; 609};
630 610
631static struct resource tmu3_resources[] = { 611static struct resource tmu3_resources[] = {
632 [0] = { 612 [0] = {
633 .name = "TMU3",
634 .start = 0xffd90008, 613 .start = 0xffd90008,
635 .end = 0xffd90013, 614 .end = 0xffd90013,
636 .flags = IORESOURCE_MEM, 615 .flags = IORESOURCE_MEM,
@@ -655,15 +634,12 @@ static struct platform_device tmu3_device = {
655}; 634};
656 635
657static struct sh_timer_config tmu4_platform_data = { 636static struct sh_timer_config tmu4_platform_data = {
658 .name = "TMU4",
659 .channel_offset = 0x10, 637 .channel_offset = 0x10,
660 .timer_bit = 1, 638 .timer_bit = 1,
661 .clk = "tmu1",
662}; 639};
663 640
664static struct resource tmu4_resources[] = { 641static struct resource tmu4_resources[] = {
665 [0] = { 642 [0] = {
666 .name = "TMU4",
667 .start = 0xffd90014, 643 .start = 0xffd90014,
668 .end = 0xffd9001f, 644 .end = 0xffd9001f,
669 .flags = IORESOURCE_MEM, 645 .flags = IORESOURCE_MEM,
@@ -688,15 +664,12 @@ static struct platform_device tmu4_device = {
688}; 664};
689 665
690static struct sh_timer_config tmu5_platform_data = { 666static struct sh_timer_config tmu5_platform_data = {
691 .name = "TMU5",
692 .channel_offset = 0x1c, 667 .channel_offset = 0x1c,
693 .timer_bit = 2, 668 .timer_bit = 2,
694 .clk = "tmu1",
695}; 669};
696 670
697static struct resource tmu5_resources[] = { 671static struct resource tmu5_resources[] = {
698 [0] = { 672 [0] = {
699 .name = "TMU5",
700 .start = 0xffd90020, 673 .start = 0xffd90020,
701 .end = 0xffd9002b, 674 .end = 0xffd9002b,
702 .flags = IORESOURCE_MEM, 675 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index e75edf58796a..444aca95b20d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -63,16 +63,13 @@ static struct platform_device scif4_device = {
63}; 63};
64 64
65static struct sh_timer_config tmu0_platform_data = { 65static struct sh_timer_config tmu0_platform_data = {
66 .name = "TMU0",
67 .channel_offset = 0x04, 66 .channel_offset = 0x04,
68 .timer_bit = 0, 67 .timer_bit = 0,
69 .clk = "peripheral_clk",
70 .clockevent_rating = 200, 68 .clockevent_rating = 200,
71}; 69};
72 70
73static struct resource tmu0_resources[] = { 71static struct resource tmu0_resources[] = {
74 [0] = { 72 [0] = {
75 .name = "TMU0",
76 .start = 0xfe430008, 73 .start = 0xfe430008,
77 .end = 0xfe430013, 74 .end = 0xfe430013,
78 .flags = IORESOURCE_MEM, 75 .flags = IORESOURCE_MEM,
@@ -94,16 +91,13 @@ static struct platform_device tmu0_device = {
94}; 91};
95 92
96static struct sh_timer_config tmu1_platform_data = { 93static struct sh_timer_config tmu1_platform_data = {
97 .name = "TMU1",
98 .channel_offset = 0x10, 94 .channel_offset = 0x10,
99 .timer_bit = 1, 95 .timer_bit = 1,
100 .clk = "peripheral_clk",
101 .clocksource_rating = 200, 96 .clocksource_rating = 200,
102}; 97};
103 98
104static struct resource tmu1_resources[] = { 99static struct resource tmu1_resources[] = {
105 [0] = { 100 [0] = {
106 .name = "TMU1",
107 .start = 0xfe430014, 101 .start = 0xfe430014,
108 .end = 0xfe43001f, 102 .end = 0xfe43001f,
109 .flags = IORESOURCE_MEM, 103 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 7f6b0a5f7f82..5b5f6b005fc5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -131,16 +131,13 @@ static struct platform_device usbf_device = {
131}; 131};
132 132
133static struct sh_timer_config tmu0_platform_data = { 133static struct sh_timer_config tmu0_platform_data = {
134 .name = "TMU0",
135 .channel_offset = 0x04, 134 .channel_offset = 0x04,
136 .timer_bit = 0, 135 .timer_bit = 0,
137 .clk = "peripheral_clk",
138 .clockevent_rating = 200, 136 .clockevent_rating = 200,
139}; 137};
140 138
141static struct resource tmu0_resources[] = { 139static struct resource tmu0_resources[] = {
142 [0] = { 140 [0] = {
143 .name = "TMU0",
144 .start = 0xffd80008, 141 .start = 0xffd80008,
145 .end = 0xffd80013, 142 .end = 0xffd80013,
146 .flags = IORESOURCE_MEM, 143 .flags = IORESOURCE_MEM,
@@ -162,16 +159,13 @@ static struct platform_device tmu0_device = {
162}; 159};
163 160
164static struct sh_timer_config tmu1_platform_data = { 161static struct sh_timer_config tmu1_platform_data = {
165 .name = "TMU1",
166 .channel_offset = 0x10, 162 .channel_offset = 0x10,
167 .timer_bit = 1, 163 .timer_bit = 1,
168 .clk = "peripheral_clk",
169 .clocksource_rating = 200, 164 .clocksource_rating = 200,
170}; 165};
171 166
172static struct resource tmu1_resources[] = { 167static struct resource tmu1_resources[] = {
173 [0] = { 168 [0] = {
174 .name = "TMU1",
175 .start = 0xffd80014, 169 .start = 0xffd80014,
176 .end = 0xffd8001f, 170 .end = 0xffd8001f,
177 .flags = IORESOURCE_MEM, 171 .flags = IORESOURCE_MEM,
@@ -193,15 +187,12 @@ static struct platform_device tmu1_device = {
193}; 187};
194 188
195static struct sh_timer_config tmu2_platform_data = { 189static struct sh_timer_config tmu2_platform_data = {
196 .name = "TMU2",
197 .channel_offset = 0x1c, 190 .channel_offset = 0x1c,
198 .timer_bit = 2, 191 .timer_bit = 2,
199 .clk = "peripheral_clk",
200}; 192};
201 193
202static struct resource tmu2_resources[] = { 194static struct resource tmu2_resources[] = {
203 [0] = { 195 [0] = {
204 .name = "TMU2",
205 .start = 0xffd80020, 196 .start = 0xffd80020,
206 .end = 0xffd8002f, 197 .end = 0xffd8002f,
207 .flags = IORESOURCE_MEM, 198 .flags = IORESOURCE_MEM,
@@ -223,15 +214,12 @@ static struct platform_device tmu2_device = {
223}; 214};
224 215
225static struct sh_timer_config tmu3_platform_data = { 216static struct sh_timer_config tmu3_platform_data = {
226 .name = "TMU3",
227 .channel_offset = 0x04, 217 .channel_offset = 0x04,
228 .timer_bit = 0, 218 .timer_bit = 0,
229 .clk = "peripheral_clk",
230}; 219};
231 220
232static struct resource tmu3_resources[] = { 221static struct resource tmu3_resources[] = {
233 [0] = { 222 [0] = {
234 .name = "TMU3",
235 .start = 0xffd88008, 223 .start = 0xffd88008,
236 .end = 0xffd88013, 224 .end = 0xffd88013,
237 .flags = IORESOURCE_MEM, 225 .flags = IORESOURCE_MEM,
@@ -253,15 +241,12 @@ static struct platform_device tmu3_device = {
253}; 241};
254 242
255static struct sh_timer_config tmu4_platform_data = { 243static struct sh_timer_config tmu4_platform_data = {
256 .name = "TMU4",
257 .channel_offset = 0x10, 244 .channel_offset = 0x10,
258 .timer_bit = 1, 245 .timer_bit = 1,
259 .clk = "peripheral_clk",
260}; 246};
261 247
262static struct resource tmu4_resources[] = { 248static struct resource tmu4_resources[] = {
263 [0] = { 249 [0] = {
264 .name = "TMU4",
265 .start = 0xffd88014, 250 .start = 0xffd88014,
266 .end = 0xffd8801f, 251 .end = 0xffd8801f,
267 .flags = IORESOURCE_MEM, 252 .flags = IORESOURCE_MEM,
@@ -283,15 +268,12 @@ static struct platform_device tmu4_device = {
283}; 268};
284 269
285static struct sh_timer_config tmu5_platform_data = { 270static struct sh_timer_config tmu5_platform_data = {
286 .name = "TMU5",
287 .channel_offset = 0x1c, 271 .channel_offset = 0x1c,
288 .timer_bit = 2, 272 .timer_bit = 2,
289 .clk = "peripheral_clk",
290}; 273};
291 274
292static struct resource tmu5_resources[] = { 275static struct resource tmu5_resources[] = {
293 [0] = { 276 [0] = {
294 .name = "TMU5",
295 .start = 0xffd88020, 277 .start = 0xffd88020,
296 .end = 0xffd8802b, 278 .end = 0xffd8802b,
297 .flags = IORESOURCE_MEM, 279 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 86d681ecf90e..7270d7fd6761 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -165,16 +165,13 @@ static struct platform_device scif9_device = {
165}; 165};
166 166
167static struct sh_timer_config tmu0_platform_data = { 167static struct sh_timer_config tmu0_platform_data = {
168 .name = "TMU0",
169 .channel_offset = 0x04, 168 .channel_offset = 0x04,
170 .timer_bit = 0, 169 .timer_bit = 0,
171 .clk = "peripheral_clk",
172 .clockevent_rating = 200, 170 .clockevent_rating = 200,
173}; 171};
174 172
175static struct resource tmu0_resources[] = { 173static struct resource tmu0_resources[] = {
176 [0] = { 174 [0] = {
177 .name = "TMU0",
178 .start = 0xffd80008, 175 .start = 0xffd80008,
179 .end = 0xffd80013, 176 .end = 0xffd80013,
180 .flags = IORESOURCE_MEM, 177 .flags = IORESOURCE_MEM,
@@ -196,16 +193,13 @@ static struct platform_device tmu0_device = {
196}; 193};
197 194
198static struct sh_timer_config tmu1_platform_data = { 195static struct sh_timer_config tmu1_platform_data = {
199 .name = "TMU1",
200 .channel_offset = 0x10, 196 .channel_offset = 0x10,
201 .timer_bit = 1, 197 .timer_bit = 1,
202 .clk = "peripheral_clk",
203 .clocksource_rating = 200, 198 .clocksource_rating = 200,
204}; 199};
205 200
206static struct resource tmu1_resources[] = { 201static struct resource tmu1_resources[] = {
207 [0] = { 202 [0] = {
208 .name = "TMU1",
209 .start = 0xffd80014, 203 .start = 0xffd80014,
210 .end = 0xffd8001f, 204 .end = 0xffd8001f,
211 .flags = IORESOURCE_MEM, 205 .flags = IORESOURCE_MEM,
@@ -227,15 +221,12 @@ static struct platform_device tmu1_device = {
227}; 221};
228 222
229static struct sh_timer_config tmu2_platform_data = { 223static struct sh_timer_config tmu2_platform_data = {
230 .name = "TMU2",
231 .channel_offset = 0x1c, 224 .channel_offset = 0x1c,
232 .timer_bit = 2, 225 .timer_bit = 2,
233 .clk = "peripheral_clk",
234}; 226};
235 227
236static struct resource tmu2_resources[] = { 228static struct resource tmu2_resources[] = {
237 [0] = { 229 [0] = {
238 .name = "TMU2",
239 .start = 0xffd80020, 230 .start = 0xffd80020,
240 .end = 0xffd8002f, 231 .end = 0xffd8002f,
241 .flags = IORESOURCE_MEM, 232 .flags = IORESOURCE_MEM,
@@ -257,15 +248,12 @@ static struct platform_device tmu2_device = {
257}; 248};
258 249
259static struct sh_timer_config tmu3_platform_data = { 250static struct sh_timer_config tmu3_platform_data = {
260 .name = "TMU3",
261 .channel_offset = 0x04, 251 .channel_offset = 0x04,
262 .timer_bit = 0, 252 .timer_bit = 0,
263 .clk = "peripheral_clk",
264}; 253};
265 254
266static struct resource tmu3_resources[] = { 255static struct resource tmu3_resources[] = {
267 [0] = { 256 [0] = {
268 .name = "TMU3",
269 .start = 0xffd81008, 257 .start = 0xffd81008,
270 .end = 0xffd81013, 258 .end = 0xffd81013,
271 .flags = IORESOURCE_MEM, 259 .flags = IORESOURCE_MEM,
@@ -287,15 +275,12 @@ static struct platform_device tmu3_device = {
287}; 275};
288 276
289static struct sh_timer_config tmu4_platform_data = { 277static struct sh_timer_config tmu4_platform_data = {
290 .name = "TMU4",
291 .channel_offset = 0x10, 278 .channel_offset = 0x10,
292 .timer_bit = 1, 279 .timer_bit = 1,
293 .clk = "peripheral_clk",
294}; 280};
295 281
296static struct resource tmu4_resources[] = { 282static struct resource tmu4_resources[] = {
297 [0] = { 283 [0] = {
298 .name = "TMU4",
299 .start = 0xffd81014, 284 .start = 0xffd81014,
300 .end = 0xffd8101f, 285 .end = 0xffd8101f,
301 .flags = IORESOURCE_MEM, 286 .flags = IORESOURCE_MEM,
@@ -317,15 +302,12 @@ static struct platform_device tmu4_device = {
317}; 302};
318 303
319static struct sh_timer_config tmu5_platform_data = { 304static struct sh_timer_config tmu5_platform_data = {
320 .name = "TMU5",
321 .channel_offset = 0x1c, 305 .channel_offset = 0x1c,
322 .timer_bit = 2, 306 .timer_bit = 2,
323 .clk = "peripheral_clk",
324}; 307};
325 308
326static struct resource tmu5_resources[] = { 309static struct resource tmu5_resources[] = {
327 [0] = { 310 [0] = {
328 .name = "TMU5",
329 .start = 0xffd81020, 311 .start = 0xffd81020,
330 .end = 0xffd8102f, 312 .end = 0xffd8102f,
331 .flags = IORESOURCE_MEM, 313 .flags = IORESOURCE_MEM,
@@ -347,15 +329,12 @@ static struct platform_device tmu5_device = {
347}; 329};
348 330
349static struct sh_timer_config tmu6_platform_data = { 331static struct sh_timer_config tmu6_platform_data = {
350 .name = "TMU6",
351 .channel_offset = 0x04, 332 .channel_offset = 0x04,
352 .timer_bit = 0, 333 .timer_bit = 0,
353 .clk = "peripheral_clk",
354}; 334};
355 335
356static struct resource tmu6_resources[] = { 336static struct resource tmu6_resources[] = {
357 [0] = { 337 [0] = {
358 .name = "TMU6",
359 .start = 0xffd82008, 338 .start = 0xffd82008,
360 .end = 0xffd82013, 339 .end = 0xffd82013,
361 .flags = IORESOURCE_MEM, 340 .flags = IORESOURCE_MEM,
@@ -377,15 +356,12 @@ static struct platform_device tmu6_device = {
377}; 356};
378 357
379static struct sh_timer_config tmu7_platform_data = { 358static struct sh_timer_config tmu7_platform_data = {
380 .name = "TMU7",
381 .channel_offset = 0x10, 359 .channel_offset = 0x10,
382 .timer_bit = 1, 360 .timer_bit = 1,
383 .clk = "peripheral_clk",
384}; 361};
385 362
386static struct resource tmu7_resources[] = { 363static struct resource tmu7_resources[] = {
387 [0] = { 364 [0] = {
388 .name = "TMU7",
389 .start = 0xffd82014, 365 .start = 0xffd82014,
390 .end = 0xffd8201f, 366 .end = 0xffd8201f,
391 .flags = IORESOURCE_MEM, 367 .flags = IORESOURCE_MEM,
@@ -407,15 +383,12 @@ static struct platform_device tmu7_device = {
407}; 383};
408 384
409static struct sh_timer_config tmu8_platform_data = { 385static struct sh_timer_config tmu8_platform_data = {
410 .name = "TMU8",
411 .channel_offset = 0x1c, 386 .channel_offset = 0x1c,
412 .timer_bit = 2, 387 .timer_bit = 2,
413 .clk = "peripheral_clk",
414}; 388};
415 389
416static struct resource tmu8_resources[] = { 390static struct resource tmu8_resources[] = {
417 [0] = { 391 [0] = {
418 .name = "TMU8",
419 .start = 0xffd82020, 392 .start = 0xffd82020,
420 .end = 0xffd8202b, 393 .end = 0xffd8202b,
421 .flags = IORESOURCE_MEM, 394 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 02e792c90de6..05fc38df1582 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -49,16 +49,13 @@ static struct platform_device scif1_device = {
49}; 49};
50 50
51static struct sh_timer_config tmu0_platform_data = { 51static struct sh_timer_config tmu0_platform_data = {
52 .name = "TMU0",
53 .channel_offset = 0x04, 52 .channel_offset = 0x04,
54 .timer_bit = 0, 53 .timer_bit = 0,
55 .clk = "peripheral_clk",
56 .clockevent_rating = 200, 54 .clockevent_rating = 200,
57}; 55};
58 56
59static struct resource tmu0_resources[] = { 57static struct resource tmu0_resources[] = {
60 [0] = { 58 [0] = {
61 .name = "TMU0",
62 .start = 0xffd80008, 59 .start = 0xffd80008,
63 .end = 0xffd80013, 60 .end = 0xffd80013,
64 .flags = IORESOURCE_MEM, 61 .flags = IORESOURCE_MEM,
@@ -80,16 +77,13 @@ static struct platform_device tmu0_device = {
80}; 77};
81 78
82static struct sh_timer_config tmu1_platform_data = { 79static struct sh_timer_config tmu1_platform_data = {
83 .name = "TMU1",
84 .channel_offset = 0x10, 80 .channel_offset = 0x10,
85 .timer_bit = 1, 81 .timer_bit = 1,
86 .clk = "peripheral_clk",
87 .clocksource_rating = 200, 82 .clocksource_rating = 200,
88}; 83};
89 84
90static struct resource tmu1_resources[] = { 85static struct resource tmu1_resources[] = {
91 [0] = { 86 [0] = {
92 .name = "TMU1",
93 .start = 0xffd80014, 87 .start = 0xffd80014,
94 .end = 0xffd8001f, 88 .end = 0xffd8001f,
95 .flags = IORESOURCE_MEM, 89 .flags = IORESOURCE_MEM,
@@ -111,15 +105,12 @@ static struct platform_device tmu1_device = {
111}; 105};
112 106
113static struct sh_timer_config tmu2_platform_data = { 107static struct sh_timer_config tmu2_platform_data = {
114 .name = "TMU2",
115 .channel_offset = 0x1c, 108 .channel_offset = 0x1c,
116 .timer_bit = 2, 109 .timer_bit = 2,
117 .clk = "peripheral_clk",
118}; 110};
119 111
120static struct resource tmu2_resources[] = { 112static struct resource tmu2_resources[] = {
121 [0] = { 113 [0] = {
122 .name = "TMU2",
123 .start = 0xffd80020, 114 .start = 0xffd80020,
124 .end = 0xffd8002f, 115 .end = 0xffd8002f,
125 .flags = IORESOURCE_MEM, 116 .flags = IORESOURCE_MEM,
@@ -141,15 +132,12 @@ static struct platform_device tmu2_device = {
141}; 132};
142 133
143static struct sh_timer_config tmu3_platform_data = { 134static struct sh_timer_config tmu3_platform_data = {
144 .name = "TMU3",
145 .channel_offset = 0x04, 135 .channel_offset = 0x04,
146 .timer_bit = 0, 136 .timer_bit = 0,
147 .clk = "peripheral_clk",
148}; 137};
149 138
150static struct resource tmu3_resources[] = { 139static struct resource tmu3_resources[] = {
151 [0] = { 140 [0] = {
152 .name = "TMU3",
153 .start = 0xffdc0008, 141 .start = 0xffdc0008,
154 .end = 0xffdc0013, 142 .end = 0xffdc0013,
155 .flags = IORESOURCE_MEM, 143 .flags = IORESOURCE_MEM,
@@ -171,15 +159,12 @@ static struct platform_device tmu3_device = {
171}; 159};
172 160
173static struct sh_timer_config tmu4_platform_data = { 161static struct sh_timer_config tmu4_platform_data = {
174 .name = "TMU4",
175 .channel_offset = 0x10, 162 .channel_offset = 0x10,
176 .timer_bit = 1, 163 .timer_bit = 1,
177 .clk = "peripheral_clk",
178}; 164};
179 165
180static struct resource tmu4_resources[] = { 166static struct resource tmu4_resources[] = {
181 [0] = { 167 [0] = {
182 .name = "TMU4",
183 .start = 0xffdc0014, 168 .start = 0xffdc0014,
184 .end = 0xffdc001f, 169 .end = 0xffdc001f,
185 .flags = IORESOURCE_MEM, 170 .flags = IORESOURCE_MEM,
@@ -201,15 +186,12 @@ static struct platform_device tmu4_device = {
201}; 186};
202 187
203static struct sh_timer_config tmu5_platform_data = { 188static struct sh_timer_config tmu5_platform_data = {
204 .name = "TMU5",
205 .channel_offset = 0x1c, 189 .channel_offset = 0x1c,
206 .timer_bit = 2, 190 .timer_bit = 2,
207 .clk = "peripheral_clk",
208}; 191};
209 192
210static struct resource tmu5_resources[] = { 193static struct resource tmu5_resources[] = {
211 [0] = { 194 [0] = {
212 .name = "TMU5",
213 .start = 0xffdc0020, 195 .start = 0xffdc0020,
214 .end = 0xffdc002b, 196 .end = 0xffdc002b,
215 .flags = IORESOURCE_MEM, 197 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 1fcd88b1671e..07bb2d4619f8 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -25,7 +25,6 @@ static struct plat_sci_port scif0_platform_data = {
25 .flags = UPF_BOOT_AUTOCONF, 25 .flags = UPF_BOOT_AUTOCONF,
26 .type = PORT_SCIF, 26 .type = PORT_SCIF,
27 .irqs = { 40, 40, 40, 40 }, 27 .irqs = { 40, 40, 40, 40 },
28 .clk = "scif_fck",
29}; 28};
30 29
31static struct platform_device scif0_device = { 30static struct platform_device scif0_device = {
@@ -41,7 +40,6 @@ static struct plat_sci_port scif1_platform_data = {
41 .flags = UPF_BOOT_AUTOCONF, 40 .flags = UPF_BOOT_AUTOCONF,
42 .type = PORT_SCIF, 41 .type = PORT_SCIF,
43 .irqs = { 44, 44, 44, 44 }, 42 .irqs = { 44, 44, 44, 44 },
44 .clk = "scif_fck",
45}; 43};
46 44
47static struct platform_device scif1_device = { 45static struct platform_device scif1_device = {
@@ -57,7 +55,6 @@ static struct plat_sci_port scif2_platform_data = {
57 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
58 .type = PORT_SCIF, 56 .type = PORT_SCIF,
59 .irqs = { 60, 60, 60, 60 }, 57 .irqs = { 60, 60, 60, 60 },
60 .clk = "scif_fck",
61}; 58};
62 59
63static struct platform_device scif2_device = { 60static struct platform_device scif2_device = {
@@ -73,7 +70,6 @@ static struct plat_sci_port scif3_platform_data = {
73 .flags = UPF_BOOT_AUTOCONF, 70 .flags = UPF_BOOT_AUTOCONF,
74 .type = PORT_SCIF, 71 .type = PORT_SCIF,
75 .irqs = { 61, 61, 61, 61 }, 72 .irqs = { 61, 61, 61, 61 },
76 .clk = "scif_fck",
77}; 73};
78 74
79static struct platform_device scif3_device = { 75static struct platform_device scif3_device = {
@@ -89,7 +85,6 @@ static struct plat_sci_port scif4_platform_data = {
89 .flags = UPF_BOOT_AUTOCONF, 85 .flags = UPF_BOOT_AUTOCONF,
90 .type = PORT_SCIF, 86 .type = PORT_SCIF,
91 .irqs = { 62, 62, 62, 62 }, 87 .irqs = { 62, 62, 62, 62 },
92 .clk = "scif_fck",
93}; 88};
94 89
95static struct platform_device scif4_device = { 90static struct platform_device scif4_device = {
@@ -105,7 +100,6 @@ static struct plat_sci_port scif5_platform_data = {
105 .flags = UPF_BOOT_AUTOCONF, 100 .flags = UPF_BOOT_AUTOCONF,
106 .type = PORT_SCIF, 101 .type = PORT_SCIF,
107 .irqs = { 63, 63, 63, 63 }, 102 .irqs = { 63, 63, 63, 63 },
108 .clk = "scif_fck",
109}; 103};
110 104
111static struct platform_device scif5_device = { 105static struct platform_device scif5_device = {
@@ -117,16 +111,13 @@ static struct platform_device scif5_device = {
117}; 111};
118 112
119static struct sh_timer_config tmu0_platform_data = { 113static struct sh_timer_config tmu0_platform_data = {
120 .name = "TMU0",
121 .channel_offset = 0x04, 114 .channel_offset = 0x04,
122 .timer_bit = 0, 115 .timer_bit = 0,
123 .clk = "tmu012_fck",
124 .clockevent_rating = 200, 116 .clockevent_rating = 200,
125}; 117};
126 118
127static struct resource tmu0_resources[] = { 119static struct resource tmu0_resources[] = {
128 [0] = { 120 [0] = {
129 .name = "TMU0",
130 .start = 0xffd80008, 121 .start = 0xffd80008,
131 .end = 0xffd80013, 122 .end = 0xffd80013,
132 .flags = IORESOURCE_MEM, 123 .flags = IORESOURCE_MEM,
@@ -148,16 +139,13 @@ static struct platform_device tmu0_device = {
148}; 139};
149 140
150static struct sh_timer_config tmu1_platform_data = { 141static struct sh_timer_config tmu1_platform_data = {
151 .name = "TMU1",
152 .channel_offset = 0x10, 142 .channel_offset = 0x10,
153 .timer_bit = 1, 143 .timer_bit = 1,
154 .clk = "tmu012_fck",
155 .clocksource_rating = 200, 144 .clocksource_rating = 200,
156}; 145};
157 146
158static struct resource tmu1_resources[] = { 147static struct resource tmu1_resources[] = {
159 [0] = { 148 [0] = {
160 .name = "TMU1",
161 .start = 0xffd80014, 149 .start = 0xffd80014,
162 .end = 0xffd8001f, 150 .end = 0xffd8001f,
163 .flags = IORESOURCE_MEM, 151 .flags = IORESOURCE_MEM,
@@ -179,15 +167,12 @@ static struct platform_device tmu1_device = {
179}; 167};
180 168
181static struct sh_timer_config tmu2_platform_data = { 169static struct sh_timer_config tmu2_platform_data = {
182 .name = "TMU2",
183 .channel_offset = 0x1c, 170 .channel_offset = 0x1c,
184 .timer_bit = 2, 171 .timer_bit = 2,
185 .clk = "tmu012_fck",
186}; 172};
187 173
188static struct resource tmu2_resources[] = { 174static struct resource tmu2_resources[] = {
189 [0] = { 175 [0] = {
190 .name = "TMU2",
191 .start = 0xffd80020, 176 .start = 0xffd80020,
192 .end = 0xffd8002f, 177 .end = 0xffd8002f,
193 .flags = IORESOURCE_MEM, 178 .flags = IORESOURCE_MEM,
@@ -209,15 +194,12 @@ static struct platform_device tmu2_device = {
209}; 194};
210 195
211static struct sh_timer_config tmu3_platform_data = { 196static struct sh_timer_config tmu3_platform_data = {
212 .name = "TMU3",
213 .channel_offset = 0x04, 197 .channel_offset = 0x04,
214 .timer_bit = 0, 198 .timer_bit = 0,
215 .clk = "tmu345_fck",
216}; 199};
217 200
218static struct resource tmu3_resources[] = { 201static struct resource tmu3_resources[] = {
219 [0] = { 202 [0] = {
220 .name = "TMU3",
221 .start = 0xffdc0008, 203 .start = 0xffdc0008,
222 .end = 0xffdc0013, 204 .end = 0xffdc0013,
223 .flags = IORESOURCE_MEM, 205 .flags = IORESOURCE_MEM,
@@ -239,15 +221,12 @@ static struct platform_device tmu3_device = {
239}; 221};
240 222
241static struct sh_timer_config tmu4_platform_data = { 223static struct sh_timer_config tmu4_platform_data = {
242 .name = "TMU4",
243 .channel_offset = 0x10, 224 .channel_offset = 0x10,
244 .timer_bit = 1, 225 .timer_bit = 1,
245 .clk = "tmu345_fck",
246}; 226};
247 227
248static struct resource tmu4_resources[] = { 228static struct resource tmu4_resources[] = {
249 [0] = { 229 [0] = {
250 .name = "TMU4",
251 .start = 0xffdc0014, 230 .start = 0xffdc0014,
252 .end = 0xffdc001f, 231 .end = 0xffdc001f,
253 .flags = IORESOURCE_MEM, 232 .flags = IORESOURCE_MEM,
@@ -269,15 +248,12 @@ static struct platform_device tmu4_device = {
269}; 248};
270 249
271static struct sh_timer_config tmu5_platform_data = { 250static struct sh_timer_config tmu5_platform_data = {
272 .name = "TMU5",
273 .channel_offset = 0x1c, 251 .channel_offset = 0x1c,
274 .timer_bit = 2, 252 .timer_bit = 2,
275 .clk = "tmu345_fck",
276}; 253};
277 254
278static struct resource tmu5_resources[] = { 255static struct resource tmu5_resources[] = {
279 [0] = { 256 [0] = {
280 .name = "TMU5",
281 .start = 0xffdc0020, 257 .start = 0xffdc0020,
282 .end = 0xffdc002b, 258 .end = 0xffdc002b,
283 .flags = IORESOURCE_MEM, 259 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 7e585320710a..f5599907ac3d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -117,16 +117,13 @@ static struct platform_device scif5_device = {
117}; 117};
118 118
119static struct sh_timer_config tmu0_platform_data = { 119static struct sh_timer_config tmu0_platform_data = {
120 .name = "TMU0",
121 .channel_offset = 0x04, 120 .channel_offset = 0x04,
122 .timer_bit = 0, 121 .timer_bit = 0,
123 .clk = "peripheral_clk",
124 .clockevent_rating = 200, 122 .clockevent_rating = 200,
125}; 123};
126 124
127static struct resource tmu0_resources[] = { 125static struct resource tmu0_resources[] = {
128 [0] = { 126 [0] = {
129 .name = "TMU0",
130 .start = 0xffd80008, 127 .start = 0xffd80008,
131 .end = 0xffd80013, 128 .end = 0xffd80013,
132 .flags = IORESOURCE_MEM, 129 .flags = IORESOURCE_MEM,
@@ -148,16 +145,13 @@ static struct platform_device tmu0_device = {
148}; 145};
149 146
150static struct sh_timer_config tmu1_platform_data = { 147static struct sh_timer_config tmu1_platform_data = {
151 .name = "TMU1",
152 .channel_offset = 0x10, 148 .channel_offset = 0x10,
153 .timer_bit = 1, 149 .timer_bit = 1,
154 .clk = "peripheral_clk",
155 .clocksource_rating = 200, 150 .clocksource_rating = 200,
156}; 151};
157 152
158static struct resource tmu1_resources[] = { 153static struct resource tmu1_resources[] = {
159 [0] = { 154 [0] = {
160 .name = "TMU1",
161 .start = 0xffd80014, 155 .start = 0xffd80014,
162 .end = 0xffd8001f, 156 .end = 0xffd8001f,
163 .flags = IORESOURCE_MEM, 157 .flags = IORESOURCE_MEM,
@@ -179,15 +173,12 @@ static struct platform_device tmu1_device = {
179}; 173};
180 174
181static struct sh_timer_config tmu2_platform_data = { 175static struct sh_timer_config tmu2_platform_data = {
182 .name = "TMU2",
183 .channel_offset = 0x1c, 176 .channel_offset = 0x1c,
184 .timer_bit = 2, 177 .timer_bit = 2,
185 .clk = "peripheral_clk",
186}; 178};
187 179
188static struct resource tmu2_resources[] = { 180static struct resource tmu2_resources[] = {
189 [0] = { 181 [0] = {
190 .name = "TMU2",
191 .start = 0xffd80020, 182 .start = 0xffd80020,
192 .end = 0xffd8002f, 183 .end = 0xffd8002f,
193 .flags = IORESOURCE_MEM, 184 .flags = IORESOURCE_MEM,
@@ -209,15 +200,12 @@ static struct platform_device tmu2_device = {
209}; 200};
210 201
211static struct sh_timer_config tmu3_platform_data = { 202static struct sh_timer_config tmu3_platform_data = {
212 .name = "TMU3",
213 .channel_offset = 0x04, 203 .channel_offset = 0x04,
214 .timer_bit = 0, 204 .timer_bit = 0,
215 .clk = "peripheral_clk",
216}; 205};
217 206
218static struct resource tmu3_resources[] = { 207static struct resource tmu3_resources[] = {
219 [0] = { 208 [0] = {
220 .name = "TMU3",
221 .start = 0xffda0008, 209 .start = 0xffda0008,
222 .end = 0xffda0013, 210 .end = 0xffda0013,
223 .flags = IORESOURCE_MEM, 211 .flags = IORESOURCE_MEM,
@@ -239,15 +227,12 @@ static struct platform_device tmu3_device = {
239}; 227};
240 228
241static struct sh_timer_config tmu4_platform_data = { 229static struct sh_timer_config tmu4_platform_data = {
242 .name = "TMU4",
243 .channel_offset = 0x10, 230 .channel_offset = 0x10,
244 .timer_bit = 1, 231 .timer_bit = 1,
245 .clk = "peripheral_clk",
246}; 232};
247 233
248static struct resource tmu4_resources[] = { 234static struct resource tmu4_resources[] = {
249 [0] = { 235 [0] = {
250 .name = "TMU4",
251 .start = 0xffda0014, 236 .start = 0xffda0014,
252 .end = 0xffda001f, 237 .end = 0xffda001f,
253 .flags = IORESOURCE_MEM, 238 .flags = IORESOURCE_MEM,
@@ -269,15 +254,12 @@ static struct platform_device tmu4_device = {
269}; 254};
270 255
271static struct sh_timer_config tmu5_platform_data = { 256static struct sh_timer_config tmu5_platform_data = {
272 .name = "TMU5",
273 .channel_offset = 0x1c, 257 .channel_offset = 0x1c,
274 .timer_bit = 2, 258 .timer_bit = 2,
275 .clk = "peripheral_clk",
276}; 259};
277 260
278static struct resource tmu5_resources[] = { 261static struct resource tmu5_resources[] = {
279 [0] = { 262 [0] = {
280 .name = "TMU5",
281 .start = 0xffda0020, 263 .start = 0xffda0020,
282 .end = 0xffda002b, 264 .end = 0xffda002b,
283 .flags = IORESOURCE_MEM, 265 .flags = IORESOURCE_MEM,
@@ -299,15 +281,12 @@ static struct platform_device tmu5_device = {
299}; 281};
300 282
301static struct sh_timer_config tmu6_platform_data = { 283static struct sh_timer_config tmu6_platform_data = {
302 .name = "TMU6",
303 .channel_offset = 0x04, 284 .channel_offset = 0x04,
304 .timer_bit = 0, 285 .timer_bit = 0,
305 .clk = "peripheral_clk",
306}; 286};
307 287
308static struct resource tmu6_resources[] = { 288static struct resource tmu6_resources[] = {
309 [0] = { 289 [0] = {
310 .name = "TMU6",
311 .start = 0xffdc0008, 290 .start = 0xffdc0008,
312 .end = 0xffdc0013, 291 .end = 0xffdc0013,
313 .flags = IORESOURCE_MEM, 292 .flags = IORESOURCE_MEM,
@@ -329,15 +308,12 @@ static struct platform_device tmu6_device = {
329}; 308};
330 309
331static struct sh_timer_config tmu7_platform_data = { 310static struct sh_timer_config tmu7_platform_data = {
332 .name = "TMU7",
333 .channel_offset = 0x10, 311 .channel_offset = 0x10,
334 .timer_bit = 1, 312 .timer_bit = 1,
335 .clk = "peripheral_clk",
336}; 313};
337 314
338static struct resource tmu7_resources[] = { 315static struct resource tmu7_resources[] = {
339 [0] = { 316 [0] = {
340 .name = "TMU7",
341 .start = 0xffdc0014, 317 .start = 0xffdc0014,
342 .end = 0xffdc001f, 318 .end = 0xffdc001f,
343 .flags = IORESOURCE_MEM, 319 .flags = IORESOURCE_MEM,
@@ -359,15 +335,12 @@ static struct platform_device tmu7_device = {
359}; 335};
360 336
361static struct sh_timer_config tmu8_platform_data = { 337static struct sh_timer_config tmu8_platform_data = {
362 .name = "TMU8",
363 .channel_offset = 0x1c, 338 .channel_offset = 0x1c,
364 .timer_bit = 2, 339 .timer_bit = 2,
365 .clk = "peripheral_clk",
366}; 340};
367 341
368static struct resource tmu8_resources[] = { 342static struct resource tmu8_resources[] = {
369 [0] = { 343 [0] = {
370 .name = "TMU8",
371 .start = 0xffdc0020, 344 .start = 0xffdc0020,
372 .end = 0xffdc002b, 345 .end = 0xffdc002b,
373 .flags = IORESOURCE_MEM, 346 .flags = IORESOURCE_MEM,
@@ -389,15 +362,12 @@ static struct platform_device tmu8_device = {
389}; 362};
390 363
391static struct sh_timer_config tmu9_platform_data = { 364static struct sh_timer_config tmu9_platform_data = {
392 .name = "TMU9",
393 .channel_offset = 0x04, 365 .channel_offset = 0x04,
394 .timer_bit = 0, 366 .timer_bit = 0,
395 .clk = "peripheral_clk",
396}; 367};
397 368
398static struct resource tmu9_resources[] = { 369static struct resource tmu9_resources[] = {
399 [0] = { 370 [0] = {
400 .name = "TMU9",
401 .start = 0xffde0008, 371 .start = 0xffde0008,
402 .end = 0xffde0013, 372 .end = 0xffde0013,
403 .flags = IORESOURCE_MEM, 373 .flags = IORESOURCE_MEM,
@@ -419,15 +389,12 @@ static struct platform_device tmu9_device = {
419}; 389};
420 390
421static struct sh_timer_config tmu10_platform_data = { 391static struct sh_timer_config tmu10_platform_data = {
422 .name = "TMU10",
423 .channel_offset = 0x10, 392 .channel_offset = 0x10,
424 .timer_bit = 1, 393 .timer_bit = 1,
425 .clk = "peripheral_clk",
426}; 394};
427 395
428static struct resource tmu10_resources[] = { 396static struct resource tmu10_resources[] = {
429 [0] = { 397 [0] = {
430 .name = "TMU10",
431 .start = 0xffde0014, 398 .start = 0xffde0014,
432 .end = 0xffde001f, 399 .end = 0xffde001f,
433 .flags = IORESOURCE_MEM, 400 .flags = IORESOURCE_MEM,
@@ -449,15 +416,12 @@ static struct platform_device tmu10_device = {
449}; 416};
450 417
451static struct sh_timer_config tmu11_platform_data = { 418static struct sh_timer_config tmu11_platform_data = {
452 .name = "TMU11",
453 .channel_offset = 0x1c, 419 .channel_offset = 0x1c,
454 .timer_bit = 2, 420 .timer_bit = 2,
455 .clk = "peripheral_clk",
456}; 421};
457 422
458static struct resource tmu11_resources[] = { 423static struct resource tmu11_resources[] = {
459 [0] = { 424 [0] = {
460 .name = "TMU11",
461 .start = 0xffde0020, 425 .start = 0xffde0020,
462 .end = 0xffde002b, 426 .end = 0xffde002b,
463 .flags = IORESOURCE_MEM, 427 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 780ba17a5599..9158bc5ea38b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -70,16 +70,13 @@ static struct platform_device scif2_device = {
70}; 70};
71 71
72static struct sh_timer_config tmu0_platform_data = { 72static struct sh_timer_config tmu0_platform_data = {
73 .name = "TMU0",
74 .channel_offset = 0x04, 73 .channel_offset = 0x04,
75 .timer_bit = 0, 74 .timer_bit = 0,
76 .clk = "peripheral_clk",
77 .clockevent_rating = 200, 75 .clockevent_rating = 200,
78}; 76};
79 77
80static struct resource tmu0_resources[] = { 78static struct resource tmu0_resources[] = {
81 [0] = { 79 [0] = {
82 .name = "TMU0",
83 .start = 0xffc10008, 80 .start = 0xffc10008,
84 .end = 0xffc10013, 81 .end = 0xffc10013,
85 .flags = IORESOURCE_MEM, 82 .flags = IORESOURCE_MEM,
@@ -101,16 +98,13 @@ static struct platform_device tmu0_device = {
101}; 98};
102 99
103static struct sh_timer_config tmu1_platform_data = { 100static struct sh_timer_config tmu1_platform_data = {
104 .name = "TMU1",
105 .channel_offset = 0x10, 101 .channel_offset = 0x10,
106 .timer_bit = 1, 102 .timer_bit = 1,
107 .clk = "peripheral_clk",
108 .clocksource_rating = 200, 103 .clocksource_rating = 200,
109}; 104};
110 105
111static struct resource tmu1_resources[] = { 106static struct resource tmu1_resources[] = {
112 [0] = { 107 [0] = {
113 .name = "TMU1",
114 .start = 0xffc10014, 108 .start = 0xffc10014,
115 .end = 0xffc1001f, 109 .end = 0xffc1001f,
116 .flags = IORESOURCE_MEM, 110 .flags = IORESOURCE_MEM,
@@ -132,15 +126,12 @@ static struct platform_device tmu1_device = {
132}; 126};
133 127
134static struct sh_timer_config tmu2_platform_data = { 128static struct sh_timer_config tmu2_platform_data = {
135 .name = "TMU2",
136 .channel_offset = 0x1c, 129 .channel_offset = 0x1c,
137 .timer_bit = 2, 130 .timer_bit = 2,
138 .clk = "peripheral_clk",
139}; 131};
140 132
141static struct resource tmu2_resources[] = { 133static struct resource tmu2_resources[] = {
142 [0] = { 134 [0] = {
143 .name = "TMU2",
144 .start = 0xffc10020, 135 .start = 0xffc10020,
145 .end = 0xffc1002f, 136 .end = 0xffc1002f,
146 .flags = IORESOURCE_MEM, 137 .flags = IORESOURCE_MEM,
@@ -162,15 +153,12 @@ static struct platform_device tmu2_device = {
162}; 153};
163 154
164static struct sh_timer_config tmu3_platform_data = { 155static struct sh_timer_config tmu3_platform_data = {
165 .name = "TMU3",
166 .channel_offset = 0x04, 156 .channel_offset = 0x04,
167 .timer_bit = 0, 157 .timer_bit = 0,
168 .clk = "peripheral_clk",
169}; 158};
170 159
171static struct resource tmu3_resources[] = { 160static struct resource tmu3_resources[] = {
172 [0] = { 161 [0] = {
173 .name = "TMU3",
174 .start = 0xffc20008, 162 .start = 0xffc20008,
175 .end = 0xffc20013, 163 .end = 0xffc20013,
176 .flags = IORESOURCE_MEM, 164 .flags = IORESOURCE_MEM,
@@ -192,15 +180,12 @@ static struct platform_device tmu3_device = {
192}; 180};
193 181
194static struct sh_timer_config tmu4_platform_data = { 182static struct sh_timer_config tmu4_platform_data = {
195 .name = "TMU4",
196 .channel_offset = 0x10, 183 .channel_offset = 0x10,
197 .timer_bit = 1, 184 .timer_bit = 1,
198 .clk = "peripheral_clk",
199}; 185};
200 186
201static struct resource tmu4_resources[] = { 187static struct resource tmu4_resources[] = {
202 [0] = { 188 [0] = {
203 .name = "TMU4",
204 .start = 0xffc20014, 189 .start = 0xffc20014,
205 .end = 0xffc2001f, 190 .end = 0xffc2001f,
206 .flags = IORESOURCE_MEM, 191 .flags = IORESOURCE_MEM,
@@ -222,15 +207,12 @@ static struct platform_device tmu4_device = {
222}; 207};
223 208
224static struct sh_timer_config tmu5_platform_data = { 209static struct sh_timer_config tmu5_platform_data = {
225 .name = "TMU5",
226 .channel_offset = 0x1c, 210 .channel_offset = 0x1c,
227 .timer_bit = 2, 211 .timer_bit = 2,
228 .clk = "peripheral_clk",
229}; 212};
230 213
231static struct resource tmu5_resources[] = { 214static struct resource tmu5_resources[] = {
232 [0] = { 215 [0] = {
233 .name = "TMU5",
234 .start = 0xffc20020, 216 .start = 0xffc20020,
235 .end = 0xffc2002b, 217 .end = 0xffc2002b,
236 .flags = IORESOURCE_MEM, 218 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index e7a3c1e4b604..d910666142b1 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -68,16 +68,13 @@ static struct platform_device rtc_device = {
68#define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2)) 68#define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2))
69 69
70static struct sh_timer_config tmu0_platform_data = { 70static struct sh_timer_config tmu0_platform_data = {
71 .name = "TMU0",
72 .channel_offset = 0x04, 71 .channel_offset = 0x04,
73 .timer_bit = 0, 72 .timer_bit = 0,
74 .clk = "peripheral_clk",
75 .clockevent_rating = 200, 73 .clockevent_rating = 200,
76}; 74};
77 75
78static struct resource tmu0_resources[] = { 76static struct resource tmu0_resources[] = {
79 [0] = { 77 [0] = {
80 .name = "TMU0",
81 .start = TMU0_BASE, 78 .start = TMU0_BASE,
82 .end = TMU0_BASE + 0xc - 1, 79 .end = TMU0_BASE + 0xc - 1,
83 .flags = IORESOURCE_MEM, 80 .flags = IORESOURCE_MEM,
@@ -99,16 +96,13 @@ static struct platform_device tmu0_device = {
99}; 96};
100 97
101static struct sh_timer_config tmu1_platform_data = { 98static struct sh_timer_config tmu1_platform_data = {
102 .name = "TMU1",
103 .channel_offset = 0x10, 99 .channel_offset = 0x10,
104 .timer_bit = 1, 100 .timer_bit = 1,
105 .clk = "peripheral_clk",
106 .clocksource_rating = 200, 101 .clocksource_rating = 200,
107}; 102};
108 103
109static struct resource tmu1_resources[] = { 104static struct resource tmu1_resources[] = {
110 [0] = { 105 [0] = {
111 .name = "TMU1",
112 .start = TMU1_BASE, 106 .start = TMU1_BASE,
113 .end = TMU1_BASE + 0xc - 1, 107 .end = TMU1_BASE + 0xc - 1,
114 .flags = IORESOURCE_MEM, 108 .flags = IORESOURCE_MEM,
@@ -130,15 +124,12 @@ static struct platform_device tmu1_device = {
130}; 124};
131 125
132static struct sh_timer_config tmu2_platform_data = { 126static struct sh_timer_config tmu2_platform_data = {
133 .name = "TMU2",
134 .channel_offset = 0x1c, 127 .channel_offset = 0x1c,
135 .timer_bit = 2, 128 .timer_bit = 2,
136 .clk = "peripheral_clk",
137}; 129};
138 130
139static struct resource tmu2_resources[] = { 131static struct resource tmu2_resources[] = {
140 [0] = { 132 [0] = {
141 .name = "TMU2",
142 .start = TMU2_BASE, 133 .start = TMU2_BASE,
143 .end = TMU2_BASE + 0xc - 1, 134 .end = TMU2_BASE + 0xc - 1,
144 .flags = IORESOURCE_MEM, 135 .flags = IORESOURCE_MEM,
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index 4b4b565c835f..d10230adeb36 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -1254,6 +1254,26 @@ static int __init early_platform_driver_probe_id(char *class_str,
1254 } 1254 }
1255 1255
1256 if (match) { 1256 if (match) {
1257 /*
1258 * Set up a sensible init_name to enable
1259 * dev_name() and others to be used before the
1260 * rest of the driver core is initialized.
1261 */
1262 if (!match->dev.init_name) {
1263 if (match->id != -1)
1264 match->dev.init_name =
1265 kasprintf(GFP_KERNEL, "%s.%d",
1266 match->name,
1267 match->id);
1268 else
1269 match->dev.init_name =
1270 kasprintf(GFP_KERNEL, "%s",
1271 match->name);
1272
1273 if (!match->dev.init_name)
1274 return -ENOMEM;
1275 }
1276
1257 if (epdrv->pdrv->probe(match)) 1277 if (epdrv->pdrv->probe(match))
1258 pr_warning("%s: unable to probe %s early.\n", 1278 pr_warning("%s: unable to probe %s early.\n",
1259 class_str, match->name); 1279 class_str, match->name);
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 578595c4425d..c5f66171a713 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -149,13 +149,12 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
149 149
150static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate) 150static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
151{ 151{
152 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
153 int ret; 152 int ret;
154 153
155 /* enable clock */ 154 /* enable clock */
156 ret = clk_enable(p->clk); 155 ret = clk_enable(p->clk);
157 if (ret) { 156 if (ret) {
158 pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk); 157 dev_err(&p->pdev->dev, "cannot enable clock\n");
159 return ret; 158 return ret;
160 } 159 }
161 160
@@ -278,7 +277,7 @@ static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
278 delay = 1; 277 delay = 1;
279 278
280 if (!delay) 279 if (!delay)
281 pr_warning("sh_cmt: too long delay\n"); 280 dev_warn(&p->pdev->dev, "too long delay\n");
282 281
283 } while (delay); 282 } while (delay);
284} 283}
@@ -288,7 +287,7 @@ static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
288 unsigned long flags; 287 unsigned long flags;
289 288
290 if (delta > p->max_match_value) 289 if (delta > p->max_match_value)
291 pr_warning("sh_cmt: delta out of range\n"); 290 dev_warn(&p->pdev->dev, "delta out of range\n");
292 291
293 spin_lock_irqsave(&p->lock, flags); 292 spin_lock_irqsave(&p->lock, flags);
294 p->next_match_value = delta; 293 p->next_match_value = delta;
@@ -450,7 +449,7 @@ static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
450 cs->resume = sh_cmt_clocksource_resume; 449 cs->resume = sh_cmt_clocksource_resume;
451 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); 450 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
452 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 451 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
453 pr_info("sh_cmt: %s used as clock source\n", cs->name); 452 dev_info(&p->pdev->dev, "used as clock source\n");
454 clocksource_register(cs); 453 clocksource_register(cs);
455 return 0; 454 return 0;
456} 455}
@@ -496,13 +495,11 @@ static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
496 495
497 switch (mode) { 496 switch (mode) {
498 case CLOCK_EVT_MODE_PERIODIC: 497 case CLOCK_EVT_MODE_PERIODIC:
499 pr_info("sh_cmt: %s used for periodic clock events\n", 498 dev_info(&p->pdev->dev, "used for periodic clock events\n");
500 ced->name);
501 sh_cmt_clock_event_start(p, 1); 499 sh_cmt_clock_event_start(p, 1);
502 break; 500 break;
503 case CLOCK_EVT_MODE_ONESHOT: 501 case CLOCK_EVT_MODE_ONESHOT:
504 pr_info("sh_cmt: %s used for oneshot clock events\n", 502 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
505 ced->name);
506 sh_cmt_clock_event_start(p, 0); 503 sh_cmt_clock_event_start(p, 0);
507 break; 504 break;
508 case CLOCK_EVT_MODE_SHUTDOWN: 505 case CLOCK_EVT_MODE_SHUTDOWN:
@@ -543,7 +540,7 @@ static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
543 ced->set_next_event = sh_cmt_clock_event_next; 540 ced->set_next_event = sh_cmt_clock_event_next;
544 ced->set_mode = sh_cmt_clock_event_mode; 541 ced->set_mode = sh_cmt_clock_event_mode;
545 542
546 pr_info("sh_cmt: %s used for clock events\n", ced->name); 543 dev_info(&p->pdev->dev, "used for clock events\n");
547 clockevents_register_device(ced); 544 clockevents_register_device(ced);
548} 545}
549 546
@@ -600,22 +597,26 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
600 /* map memory, let mapbase point to our channel */ 597 /* map memory, let mapbase point to our channel */
601 p->mapbase = ioremap_nocache(res->start, resource_size(res)); 598 p->mapbase = ioremap_nocache(res->start, resource_size(res));
602 if (p->mapbase == NULL) { 599 if (p->mapbase == NULL) {
603 pr_err("sh_cmt: failed to remap I/O memory\n"); 600 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
604 goto err0; 601 goto err0;
605 } 602 }
606 603
607 /* request irq using setup_irq() (too early for request_irq()) */ 604 /* request irq using setup_irq() (too early for request_irq()) */
608 p->irqaction.name = cfg->name; 605 p->irqaction.name = dev_name(&p->pdev->dev);
609 p->irqaction.handler = sh_cmt_interrupt; 606 p->irqaction.handler = sh_cmt_interrupt;
610 p->irqaction.dev_id = p; 607 p->irqaction.dev_id = p;
611 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL; 608 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
612 609
613 /* get hold of clock */ 610 /* get hold of clock */
614 p->clk = clk_get(&p->pdev->dev, cfg->clk); 611 p->clk = clk_get(&p->pdev->dev, "cmt_fck");
615 if (IS_ERR(p->clk)) { 612 if (IS_ERR(p->clk)) {
616 pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk); 613 dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
617 ret = PTR_ERR(p->clk); 614 p->clk = clk_get(&p->pdev->dev, cfg->clk);
618 goto err1; 615 if (IS_ERR(p->clk)) {
616 dev_err(&p->pdev->dev, "cannot get clock\n");
617 ret = PTR_ERR(p->clk);
618 goto err1;
619 }
619 } 620 }
620 621
621 if (resource_size(res) == 6) { 622 if (resource_size(res) == 6) {
@@ -628,17 +629,17 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
628 p->clear_bits = ~0xc000; 629 p->clear_bits = ~0xc000;
629 } 630 }
630 631
631 ret = sh_cmt_register(p, cfg->name, 632 ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
632 cfg->clockevent_rating, 633 cfg->clockevent_rating,
633 cfg->clocksource_rating); 634 cfg->clocksource_rating);
634 if (ret) { 635 if (ret) {
635 pr_err("sh_cmt: registration failed\n"); 636 dev_err(&p->pdev->dev, "registration failed\n");
636 goto err1; 637 goto err1;
637 } 638 }
638 639
639 ret = setup_irq(irq, &p->irqaction); 640 ret = setup_irq(irq, &p->irqaction);
640 if (ret) { 641 if (ret) {
641 pr_err("sh_cmt: failed to request irq %d\n", irq); 642 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
642 goto err1; 643 goto err1;
643 } 644 }
644 645
@@ -653,11 +654,10 @@ err0:
653static int __devinit sh_cmt_probe(struct platform_device *pdev) 654static int __devinit sh_cmt_probe(struct platform_device *pdev)
654{ 655{
655 struct sh_cmt_priv *p = platform_get_drvdata(pdev); 656 struct sh_cmt_priv *p = platform_get_drvdata(pdev);
656 struct sh_timer_config *cfg = pdev->dev.platform_data;
657 int ret; 657 int ret;
658 658
659 if (p) { 659 if (p) {
660 pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name); 660 dev_info(&pdev->dev, "kept as earlytimer\n");
661 return 0; 661 return 0;
662 } 662 }
663 663
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c
index 4c8a759e60cd..b11882e0f1bd 100644
--- a/drivers/clocksource/sh_mtu2.c
+++ b/drivers/clocksource/sh_mtu2.c
@@ -118,13 +118,12 @@ static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
118 118
119static int sh_mtu2_enable(struct sh_mtu2_priv *p) 119static int sh_mtu2_enable(struct sh_mtu2_priv *p)
120{ 120{
121 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
122 int ret; 121 int ret;
123 122
124 /* enable clock */ 123 /* enable clock */
125 ret = clk_enable(p->clk); 124 ret = clk_enable(p->clk);
126 if (ret) { 125 if (ret) {
127 pr_err("sh_mtu2: cannot enable clock \"%s\"\n", cfg->clk); 126 dev_err(&p->pdev->dev, "cannot enable clock\n");
128 return ret; 127 return ret;
129 } 128 }
130 129
@@ -193,8 +192,7 @@ static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
193 192
194 switch (mode) { 193 switch (mode) {
195 case CLOCK_EVT_MODE_PERIODIC: 194 case CLOCK_EVT_MODE_PERIODIC:
196 pr_info("sh_mtu2: %s used for periodic clock events\n", 195 dev_info(&p->pdev->dev, "used for periodic clock events\n");
197 ced->name);
198 sh_mtu2_enable(p); 196 sh_mtu2_enable(p);
199 break; 197 break;
200 case CLOCK_EVT_MODE_UNUSED: 198 case CLOCK_EVT_MODE_UNUSED:
@@ -221,13 +219,13 @@ static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
221 ced->cpumask = cpumask_of(0); 219 ced->cpumask = cpumask_of(0);
222 ced->set_mode = sh_mtu2_clock_event_mode; 220 ced->set_mode = sh_mtu2_clock_event_mode;
223 221
224 pr_info("sh_mtu2: %s used for clock events\n", ced->name); 222 dev_info(&p->pdev->dev, "used for clock events\n");
225 clockevents_register_device(ced); 223 clockevents_register_device(ced);
226 224
227 ret = setup_irq(p->irqaction.irq, &p->irqaction); 225 ret = setup_irq(p->irqaction.irq, &p->irqaction);
228 if (ret) { 226 if (ret) {
229 pr_err("sh_mtu2: failed to request irq %d\n", 227 dev_err(&p->pdev->dev, "failed to request irq %d\n",
230 p->irqaction.irq); 228 p->irqaction.irq);
231 return; 229 return;
232 } 230 }
233} 231}
@@ -273,26 +271,31 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
273 /* map memory, let mapbase point to our channel */ 271 /* map memory, let mapbase point to our channel */
274 p->mapbase = ioremap_nocache(res->start, resource_size(res)); 272 p->mapbase = ioremap_nocache(res->start, resource_size(res));
275 if (p->mapbase == NULL) { 273 if (p->mapbase == NULL) {
276 pr_err("sh_mtu2: failed to remap I/O memory\n"); 274 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
277 goto err0; 275 goto err0;
278 } 276 }
279 277
280 /* setup data for setup_irq() (too early for request_irq()) */ 278 /* setup data for setup_irq() (too early for request_irq()) */
281 p->irqaction.name = cfg->name; 279 p->irqaction.name = dev_name(&p->pdev->dev);
282 p->irqaction.handler = sh_mtu2_interrupt; 280 p->irqaction.handler = sh_mtu2_interrupt;
283 p->irqaction.dev_id = p; 281 p->irqaction.dev_id = p;
284 p->irqaction.irq = irq; 282 p->irqaction.irq = irq;
285 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL; 283 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
286 284
287 /* get hold of clock */ 285 /* get hold of clock */
288 p->clk = clk_get(&p->pdev->dev, cfg->clk); 286 p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
289 if (IS_ERR(p->clk)) { 287 if (IS_ERR(p->clk)) {
290 pr_err("sh_mtu2: cannot get clock \"%s\"\n", cfg->clk); 288 dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
291 ret = PTR_ERR(p->clk); 289 p->clk = clk_get(&p->pdev->dev, cfg->clk);
292 goto err1; 290 if (IS_ERR(p->clk)) {
291 dev_err(&p->pdev->dev, "cannot get clock\n");
292 ret = PTR_ERR(p->clk);
293 goto err1;
294 }
293 } 295 }
294 296
295 return sh_mtu2_register(p, cfg->name, cfg->clockevent_rating); 297 return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
298 cfg->clockevent_rating);
296 err1: 299 err1:
297 iounmap(p->mapbase); 300 iounmap(p->mapbase);
298 err0: 301 err0:
@@ -302,11 +305,10 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
302static int __devinit sh_mtu2_probe(struct platform_device *pdev) 305static int __devinit sh_mtu2_probe(struct platform_device *pdev)
303{ 306{
304 struct sh_mtu2_priv *p = platform_get_drvdata(pdev); 307 struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
305 struct sh_timer_config *cfg = pdev->dev.platform_data;
306 int ret; 308 int ret;
307 309
308 if (p) { 310 if (p) {
309 pr_info("sh_mtu2: %s kept as earlytimer\n", cfg->name); 311 dev_info(&pdev->dev, "kept as earlytimer\n");
310 return 0; 312 return 0;
311 } 313 }
312 314
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index 961f5b5ef6a3..6b62283c1aba 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -106,13 +106,12 @@ static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
106 106
107static int sh_tmu_enable(struct sh_tmu_priv *p) 107static int sh_tmu_enable(struct sh_tmu_priv *p)
108{ 108{
109 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
110 int ret; 109 int ret;
111 110
112 /* enable clock */ 111 /* enable clock */
113 ret = clk_enable(p->clk); 112 ret = clk_enable(p->clk);
114 if (ret) { 113 if (ret) {
115 pr_err("sh_tmu: cannot enable clock \"%s\"\n", cfg->clk); 114 dev_err(&p->pdev->dev, "cannot enable clock\n");
116 return ret; 115 return ret;
117 } 116 }
118 117
@@ -228,7 +227,7 @@ static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
228 cs->disable = sh_tmu_clocksource_disable; 227 cs->disable = sh_tmu_clocksource_disable;
229 cs->mask = CLOCKSOURCE_MASK(32); 228 cs->mask = CLOCKSOURCE_MASK(32);
230 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 229 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
231 pr_info("sh_tmu: %s used as clock source\n", cs->name); 230 dev_info(&p->pdev->dev, "used as clock source\n");
232 clocksource_register(cs); 231 clocksource_register(cs);
233 return 0; 232 return 0;
234} 233}
@@ -276,13 +275,11 @@ static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
276 275
277 switch (mode) { 276 switch (mode) {
278 case CLOCK_EVT_MODE_PERIODIC: 277 case CLOCK_EVT_MODE_PERIODIC:
279 pr_info("sh_tmu: %s used for periodic clock events\n", 278 dev_info(&p->pdev->dev, "used for periodic clock events\n");
280 ced->name);
281 sh_tmu_clock_event_start(p, 1); 279 sh_tmu_clock_event_start(p, 1);
282 break; 280 break;
283 case CLOCK_EVT_MODE_ONESHOT: 281 case CLOCK_EVT_MODE_ONESHOT:
284 pr_info("sh_tmu: %s used for oneshot clock events\n", 282 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
285 ced->name);
286 sh_tmu_clock_event_start(p, 0); 283 sh_tmu_clock_event_start(p, 0);
287 break; 284 break;
288 case CLOCK_EVT_MODE_UNUSED: 285 case CLOCK_EVT_MODE_UNUSED:
@@ -323,13 +320,13 @@ static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
323 ced->set_next_event = sh_tmu_clock_event_next; 320 ced->set_next_event = sh_tmu_clock_event_next;
324 ced->set_mode = sh_tmu_clock_event_mode; 321 ced->set_mode = sh_tmu_clock_event_mode;
325 322
326 pr_info("sh_tmu: %s used for clock events\n", ced->name); 323 dev_info(&p->pdev->dev, "used for clock events\n");
327 clockevents_register_device(ced); 324 clockevents_register_device(ced);
328 325
329 ret = setup_irq(p->irqaction.irq, &p->irqaction); 326 ret = setup_irq(p->irqaction.irq, &p->irqaction);
330 if (ret) { 327 if (ret) {
331 pr_err("sh_tmu: failed to request irq %d\n", 328 dev_err(&p->pdev->dev, "failed to request irq %d\n",
332 p->irqaction.irq); 329 p->irqaction.irq);
333 return; 330 return;
334 } 331 }
335} 332}
@@ -378,26 +375,30 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
378 /* map memory, let mapbase point to our channel */ 375 /* map memory, let mapbase point to our channel */
379 p->mapbase = ioremap_nocache(res->start, resource_size(res)); 376 p->mapbase = ioremap_nocache(res->start, resource_size(res));
380 if (p->mapbase == NULL) { 377 if (p->mapbase == NULL) {
381 pr_err("sh_tmu: failed to remap I/O memory\n"); 378 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
382 goto err0; 379 goto err0;
383 } 380 }
384 381
385 /* setup data for setup_irq() (too early for request_irq()) */ 382 /* setup data for setup_irq() (too early for request_irq()) */
386 p->irqaction.name = cfg->name; 383 p->irqaction.name = dev_name(&p->pdev->dev);
387 p->irqaction.handler = sh_tmu_interrupt; 384 p->irqaction.handler = sh_tmu_interrupt;
388 p->irqaction.dev_id = p; 385 p->irqaction.dev_id = p;
389 p->irqaction.irq = irq; 386 p->irqaction.irq = irq;
390 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL; 387 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
391 388
392 /* get hold of clock */ 389 /* get hold of clock */
393 p->clk = clk_get(&p->pdev->dev, cfg->clk); 390 p->clk = clk_get(&p->pdev->dev, "tmu_fck");
394 if (IS_ERR(p->clk)) { 391 if (IS_ERR(p->clk)) {
395 pr_err("sh_tmu: cannot get clock \"%s\"\n", cfg->clk); 392 dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
396 ret = PTR_ERR(p->clk); 393 p->clk = clk_get(&p->pdev->dev, cfg->clk);
397 goto err1; 394 if (IS_ERR(p->clk)) {
395 dev_err(&p->pdev->dev, "cannot get clock\n");
396 ret = PTR_ERR(p->clk);
397 goto err1;
398 }
398 } 399 }
399 400
400 return sh_tmu_register(p, cfg->name, 401 return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
401 cfg->clockevent_rating, 402 cfg->clockevent_rating,
402 cfg->clocksource_rating); 403 cfg->clocksource_rating);
403 err1: 404 err1:
@@ -409,11 +410,10 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
409static int __devinit sh_tmu_probe(struct platform_device *pdev) 410static int __devinit sh_tmu_probe(struct platform_device *pdev)
410{ 411{
411 struct sh_tmu_priv *p = platform_get_drvdata(pdev); 412 struct sh_tmu_priv *p = platform_get_drvdata(pdev);
412 struct sh_timer_config *cfg = pdev->dev.platform_data;
413 int ret; 413 int ret;
414 414
415 if (p) { 415 if (p) {
416 pr_info("sh_tmu: %s kept as earlytimer\n", cfg->name); 416 dev_info(&pdev->dev, "kept as earlytimer\n");
417 return 0; 417 return 0;
418 } 418 }
419 419
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index 5d17e09cb625..7a18b580f626 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -25,8 +25,7 @@
25#include <linux/dma-mapping.h> 25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/pm_runtime.h> 27#include <linux/pm_runtime.h>
28 28#include <linux/sh_dma.h>
29#include <asm/dmaengine.h>
30 29
31#include "shdma.h" 30#include "shdma.h"
32 31
@@ -44,7 +43,7 @@ enum sh_dmae_desc_status {
44#define LOG2_DEFAULT_XFER_SIZE 2 43#define LOG2_DEFAULT_XFER_SIZE 2
45 44
46/* A bitmask with bits enough for enum sh_dmae_slave_chan_id */ 45/* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
47static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)]; 46static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)];
48 47
49static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all); 48static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
50 49
@@ -266,7 +265,7 @@ static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
266} 265}
267 266
268static struct sh_dmae_slave_config *sh_dmae_find_slave( 267static struct sh_dmae_slave_config *sh_dmae_find_slave(
269 struct sh_dmae_chan *sh_chan, enum sh_dmae_slave_chan_id slave_id) 268 struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param)
270{ 269{
271 struct dma_device *dma_dev = sh_chan->common.device; 270 struct dma_device *dma_dev = sh_chan->common.device;
272 struct sh_dmae_device *shdev = container_of(dma_dev, 271 struct sh_dmae_device *shdev = container_of(dma_dev,
@@ -274,11 +273,11 @@ static struct sh_dmae_slave_config *sh_dmae_find_slave(
274 struct sh_dmae_pdata *pdata = shdev->pdata; 273 struct sh_dmae_pdata *pdata = shdev->pdata;
275 int i; 274 int i;
276 275
277 if ((unsigned)slave_id >= SHDMA_SLAVE_NUMBER) 276 if (param->slave_id >= SH_DMA_SLAVE_NUMBER)
278 return NULL; 277 return NULL;
279 278
280 for (i = 0; i < pdata->slave_num; i++) 279 for (i = 0; i < pdata->slave_num; i++)
281 if (pdata->slave[i].slave_id == slave_id) 280 if (pdata->slave[i].slave_id == param->slave_id)
282 return pdata->slave + i; 281 return pdata->slave + i;
283 282
284 return NULL; 283 return NULL;
@@ -299,7 +298,7 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
299 if (param) { 298 if (param) {
300 struct sh_dmae_slave_config *cfg; 299 struct sh_dmae_slave_config *cfg;
301 300
302 cfg = sh_dmae_find_slave(sh_chan, param->slave_id); 301 cfg = sh_dmae_find_slave(sh_chan, param);
303 if (!cfg) 302 if (!cfg)
304 return -EINVAL; 303 return -EINVAL;
305 304
diff --git a/drivers/dma/shdma.h b/drivers/dma/shdma.h
index 153609a1e96c..4021275a0a43 100644
--- a/drivers/dma/shdma.h
+++ b/drivers/dma/shdma.h
@@ -17,8 +17,8 @@
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/list.h> 18#include <linux/list.h>
19 19
20#include <asm/dmaengine.h> 20#define SH_DMAC_MAX_CHANNELS 6
21 21#define SH_DMA_SLAVE_NUMBER 256
22#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */ 22#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
23 23
24struct device; 24struct device;
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 309de6be8204..291bc08e2e84 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -82,16 +82,16 @@ struct sci_port {
82 82
83 /* Interface clock */ 83 /* Interface clock */
84 struct clk *iclk; 84 struct clk *iclk;
85 /* Data clock */ 85 /* Function clock */
86 struct clk *dclk; 86 struct clk *fclk;
87 87
88 struct list_head node; 88 struct list_head node;
89 struct dma_chan *chan_tx; 89 struct dma_chan *chan_tx;
90 struct dma_chan *chan_rx; 90 struct dma_chan *chan_rx;
91#ifdef CONFIG_SERIAL_SH_SCI_DMA 91#ifdef CONFIG_SERIAL_SH_SCI_DMA
92 struct device *dma_dev; 92 struct device *dma_dev;
93 enum sh_dmae_slave_chan_id slave_tx; 93 unsigned int slave_tx;
94 enum sh_dmae_slave_chan_id slave_rx; 94 unsigned int slave_rx;
95 struct dma_async_tx_descriptor *desc_tx; 95 struct dma_async_tx_descriptor *desc_tx;
96 struct dma_async_tx_descriptor *desc_rx[2]; 96 struct dma_async_tx_descriptor *desc_rx[2];
97 dma_cookie_t cookie_tx; 97 dma_cookie_t cookie_tx;
@@ -106,6 +106,7 @@ struct sci_port {
106 struct work_struct work_tx; 106 struct work_struct work_tx;
107 struct work_struct work_rx; 107 struct work_struct work_rx;
108 struct timer_list rx_timer; 108 struct timer_list rx_timer;
109 unsigned int rx_timeout;
109#endif 110#endif
110}; 111};
111 112
@@ -673,22 +674,22 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
673 struct sci_port *s = to_sci_port(port); 674 struct sci_port *s = to_sci_port(port);
674 675
675 if (s->chan_rx) { 676 if (s->chan_rx) {
676 unsigned long tout;
677 u16 scr = sci_in(port, SCSCR); 677 u16 scr = sci_in(port, SCSCR);
678 u16 ssr = sci_in(port, SCxSR); 678 u16 ssr = sci_in(port, SCxSR);
679 679
680 /* Disable future Rx interrupts */ 680 /* Disable future Rx interrupts */
681 sci_out(port, SCSCR, scr & ~SCI_CTRL_FLAGS_RIE); 681 if (port->type == PORT_SCIFA) {
682 disable_irq_nosync(irq);
683 scr |= 0x4000;
684 } else {
685 scr &= ~SCI_CTRL_FLAGS_RIE;
686 }
687 sci_out(port, SCSCR, scr);
682 /* Clear current interrupt */ 688 /* Clear current interrupt */
683 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); 689 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
684 /* Calculate delay for 1.5 DMA buffers */ 690 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
685 tout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / 691 jiffies, s->rx_timeout);
686 port->fifosize / 2; 692 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
687 dev_dbg(port->dev, "Rx IRQ: setup timeout in %lu ms\n",
688 tout * 1000 / HZ);
689 if (tout < 2)
690 tout = 2;
691 mod_timer(&s->rx_timer, jiffies + tout);
692 693
693 return IRQ_HANDLED; 694 return IRQ_HANDLED;
694 } 695 }
@@ -798,7 +799,7 @@ static int sci_notifier(struct notifier_block *self,
798 (phase == CPUFREQ_RESUMECHANGE)) { 799 (phase == CPUFREQ_RESUMECHANGE)) {
799 spin_lock_irqsave(&priv->lock, flags); 800 spin_lock_irqsave(&priv->lock, flags);
800 list_for_each_entry(sci_port, &priv->ports, node) 801 list_for_each_entry(sci_port, &priv->ports, node)
801 sci_port->port.uartclk = clk_get_rate(sci_port->dclk); 802 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
802 spin_unlock_irqrestore(&priv->lock, flags); 803 spin_unlock_irqrestore(&priv->lock, flags);
803 } 804 }
804 805
@@ -809,21 +810,17 @@ static void sci_clk_enable(struct uart_port *port)
809{ 810{
810 struct sci_port *sci_port = to_sci_port(port); 811 struct sci_port *sci_port = to_sci_port(port);
811 812
812 clk_enable(sci_port->dclk); 813 clk_enable(sci_port->iclk);
813 sci_port->port.uartclk = clk_get_rate(sci_port->dclk); 814 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
814 815 clk_enable(sci_port->fclk);
815 if (sci_port->iclk)
816 clk_enable(sci_port->iclk);
817} 816}
818 817
819static void sci_clk_disable(struct uart_port *port) 818static void sci_clk_disable(struct uart_port *port)
820{ 819{
821 struct sci_port *sci_port = to_sci_port(port); 820 struct sci_port *sci_port = to_sci_port(port);
822 821
823 if (sci_port->iclk) 822 clk_disable(sci_port->fclk);
824 clk_disable(sci_port->iclk); 823 clk_disable(sci_port->iclk);
825
826 clk_disable(sci_port->dclk);
827} 824}
828 825
829static int sci_request_irq(struct sci_port *port) 826static int sci_request_irq(struct sci_port *port)
@@ -912,22 +909,26 @@ static void sci_dma_tx_complete(void *arg)
912 909
913 spin_lock_irqsave(&port->lock, flags); 910 spin_lock_irqsave(&port->lock, flags);
914 911
915 xmit->tail += s->sg_tx.length; 912 xmit->tail += sg_dma_len(&s->sg_tx);
916 xmit->tail &= UART_XMIT_SIZE - 1; 913 xmit->tail &= UART_XMIT_SIZE - 1;
917 914
918 port->icount.tx += s->sg_tx.length; 915 port->icount.tx += sg_dma_len(&s->sg_tx);
919 916
920 async_tx_ack(s->desc_tx); 917 async_tx_ack(s->desc_tx);
921 s->cookie_tx = -EINVAL; 918 s->cookie_tx = -EINVAL;
922 s->desc_tx = NULL; 919 s->desc_tx = NULL;
923 920
924 spin_unlock_irqrestore(&port->lock, flags);
925
926 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 921 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
927 uart_write_wakeup(port); 922 uart_write_wakeup(port);
928 923
929 if (uart_circ_chars_pending(xmit)) 924 if (!uart_circ_empty(xmit)) {
930 schedule_work(&s->work_tx); 925 schedule_work(&s->work_tx);
926 } else if (port->type == PORT_SCIFA) {
927 u16 ctrl = sci_in(port, SCSCR);
928 sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE);
929 }
930
931 spin_unlock_irqrestore(&port->lock, flags);
931} 932}
932 933
933/* Locking: called with port lock held */ 934/* Locking: called with port lock held */
@@ -971,13 +972,13 @@ static void sci_dma_rx_complete(void *arg)
971 unsigned long flags; 972 unsigned long flags;
972 int count; 973 int count;
973 974
974 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 975 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
975 976
976 spin_lock_irqsave(&port->lock, flags); 977 spin_lock_irqsave(&port->lock, flags);
977 978
978 count = sci_dma_rx_push(s, tty, s->buf_len_rx); 979 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
979 980
980 mod_timer(&s->rx_timer, jiffies + msecs_to_jiffies(5)); 981 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
981 982
982 spin_unlock_irqrestore(&port->lock, flags); 983 spin_unlock_irqrestore(&port->lock, flags);
983 984
@@ -1049,6 +1050,8 @@ static void sci_submit_rx(struct sci_port *s)
1049 sci_rx_dma_release(s, true); 1050 sci_rx_dma_release(s, true);
1050 return; 1051 return;
1051 } 1052 }
1053 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1054 s->cookie_rx[i], i);
1052 } 1055 }
1053 1056
1054 s->active_rx = s->cookie_rx[0]; 1057 s->active_rx = s->cookie_rx[0];
@@ -1106,10 +1109,10 @@ static void work_fn_rx(struct work_struct *work)
1106 return; 1109 return;
1107 } 1110 }
1108 1111
1109 dev_dbg(port->dev, "%s: cookie %d #%d\n", __func__,
1110 s->cookie_rx[new], new);
1111
1112 s->active_rx = s->cookie_rx[!new]; 1112 s->active_rx = s->cookie_rx[!new];
1113
1114 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1115 s->cookie_rx[new], new, s->active_rx);
1113} 1116}
1114 1117
1115static void work_fn_tx(struct work_struct *work) 1118static void work_fn_tx(struct work_struct *work)
@@ -1130,14 +1133,13 @@ static void work_fn_tx(struct work_struct *work)
1130 */ 1133 */
1131 spin_lock_irq(&port->lock); 1134 spin_lock_irq(&port->lock);
1132 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 1135 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1133 sg->dma_address = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + 1136 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1134 sg->offset; 1137 sg->offset;
1135 sg->length = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1138 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1136 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1139 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1137 sg->dma_length = sg->length;
1138 spin_unlock_irq(&port->lock); 1140 spin_unlock_irq(&port->lock);
1139 1141
1140 BUG_ON(!sg->length); 1142 BUG_ON(!sg_dma_len(sg));
1141 1143
1142 desc = chan->device->device_prep_slave_sg(chan, 1144 desc = chan->device->device_prep_slave_sg(chan,
1143 sg, s->sg_len_tx, DMA_TO_DEVICE, 1145 sg, s->sg_len_tx, DMA_TO_DEVICE,
@@ -1172,23 +1174,28 @@ static void work_fn_tx(struct work_struct *work)
1172 1174
1173static void sci_start_tx(struct uart_port *port) 1175static void sci_start_tx(struct uart_port *port)
1174{ 1176{
1177 struct sci_port *s = to_sci_port(port);
1175 unsigned short ctrl; 1178 unsigned short ctrl;
1176 1179
1177#ifdef CONFIG_SERIAL_SH_SCI_DMA 1180#ifdef CONFIG_SERIAL_SH_SCI_DMA
1178 struct sci_port *s = to_sci_port(port); 1181 if (port->type == PORT_SCIFA) {
1179 1182 u16 new, scr = sci_in(port, SCSCR);
1180 if (s->chan_tx) { 1183 if (s->chan_tx)
1181 if (!uart_circ_empty(&s->port.state->xmit) && s->cookie_tx < 0) 1184 new = scr | 0x8000;
1182 schedule_work(&s->work_tx); 1185 else
1183 1186 new = scr & ~0x8000;
1184 return; 1187 if (new != scr)
1188 sci_out(port, SCSCR, new);
1185 } 1189 }
1190 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1191 s->cookie_tx < 0)
1192 schedule_work(&s->work_tx);
1186#endif 1193#endif
1187 1194 if (!s->chan_tx || port->type == PORT_SCIFA) {
1188 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1195 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1189 ctrl = sci_in(port, SCSCR); 1196 ctrl = sci_in(port, SCSCR);
1190 ctrl |= SCI_CTRL_FLAGS_TIE; 1197 sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE);
1191 sci_out(port, SCSCR, ctrl); 1198 }
1192} 1199}
1193 1200
1194static void sci_stop_tx(struct uart_port *port) 1201static void sci_stop_tx(struct uart_port *port)
@@ -1197,6 +1204,8 @@ static void sci_stop_tx(struct uart_port *port)
1197 1204
1198 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1205 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1199 ctrl = sci_in(port, SCSCR); 1206 ctrl = sci_in(port, SCSCR);
1207 if (port->type == PORT_SCIFA)
1208 ctrl &= ~0x8000;
1200 ctrl &= ~SCI_CTRL_FLAGS_TIE; 1209 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1201 sci_out(port, SCSCR, ctrl); 1210 sci_out(port, SCSCR, ctrl);
1202} 1211}
@@ -1207,6 +1216,8 @@ static void sci_start_rx(struct uart_port *port)
1207 1216
1208 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ 1217 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1209 ctrl |= sci_in(port, SCSCR); 1218 ctrl |= sci_in(port, SCSCR);
1219 if (port->type == PORT_SCIFA)
1220 ctrl &= ~0x4000;
1210 sci_out(port, SCSCR, ctrl); 1221 sci_out(port, SCSCR, ctrl);
1211} 1222}
1212 1223
@@ -1216,6 +1227,8 @@ static void sci_stop_rx(struct uart_port *port)
1216 1227
1217 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ 1228 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1218 ctrl = sci_in(port, SCSCR); 1229 ctrl = sci_in(port, SCSCR);
1230 if (port->type == PORT_SCIFA)
1231 ctrl &= ~0x4000;
1219 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); 1232 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1220 sci_out(port, SCSCR, ctrl); 1233 sci_out(port, SCSCR, ctrl);
1221} 1234}
@@ -1250,8 +1263,12 @@ static void rx_timer_fn(unsigned long arg)
1250{ 1263{
1251 struct sci_port *s = (struct sci_port *)arg; 1264 struct sci_port *s = (struct sci_port *)arg;
1252 struct uart_port *port = &s->port; 1265 struct uart_port *port = &s->port;
1253
1254 u16 scr = sci_in(port, SCSCR); 1266 u16 scr = sci_in(port, SCSCR);
1267
1268 if (port->type == PORT_SCIFA) {
1269 scr &= ~0x4000;
1270 enable_irq(s->irqs[1]);
1271 }
1255 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE); 1272 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
1256 dev_dbg(port->dev, "DMA Rx timed out\n"); 1273 dev_dbg(port->dev, "DMA Rx timed out\n");
1257 schedule_work(&s->work_rx); 1274 schedule_work(&s->work_rx);
@@ -1338,8 +1355,7 @@ static void sci_request_dma(struct uart_port *port)
1338 sg_init_table(sg, 1); 1355 sg_init_table(sg, 1);
1339 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, 1356 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1340 (int)buf[i] & ~PAGE_MASK); 1357 (int)buf[i] & ~PAGE_MASK);
1341 sg->dma_address = dma[i]; 1358 sg_dma_address(sg) = dma[i];
1342 sg->dma_length = sg->length;
1343 } 1359 }
1344 1360
1345 INIT_WORK(&s->work_rx, work_fn_rx); 1361 INIT_WORK(&s->work_rx, work_fn_rx);
@@ -1402,8 +1418,12 @@ static void sci_shutdown(struct uart_port *port)
1402static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1418static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1403 struct ktermios *old) 1419 struct ktermios *old)
1404{ 1420{
1421#ifdef CONFIG_SERIAL_SH_SCI_DMA
1422 struct sci_port *s = to_sci_port(port);
1423#endif
1405 unsigned int status, baud, smr_val, max_baud; 1424 unsigned int status, baud, smr_val, max_baud;
1406 int t = -1; 1425 int t = -1;
1426 u16 scfcr = 0;
1407 1427
1408 /* 1428 /*
1409 * earlyprintk comes here early on with port->uartclk set to zero. 1429 * earlyprintk comes here early on with port->uartclk set to zero.
@@ -1426,7 +1446,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1426 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1446 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1427 1447
1428 if (port->type != PORT_SCI) 1448 if (port->type != PORT_SCI)
1429 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1449 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1430 1450
1431 smr_val = sci_in(port, SCSMR) & 3; 1451 smr_val = sci_in(port, SCSMR) & 3;
1432 if ((termios->c_cflag & CSIZE) == CS7) 1452 if ((termios->c_cflag & CSIZE) == CS7)
@@ -1457,10 +1477,32 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1457 } 1477 }
1458 1478
1459 sci_init_pins(port, termios->c_cflag); 1479 sci_init_pins(port, termios->c_cflag);
1460 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0); 1480 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
1461 1481
1462 sci_out(port, SCSCR, SCSCR_INIT(port)); 1482 sci_out(port, SCSCR, SCSCR_INIT(port));
1463 1483
1484#ifdef CONFIG_SERIAL_SH_SCI_DMA
1485 /*
1486 * Calculate delay for 1.5 DMA buffers: see
1487 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1488 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1489 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1490 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1491 * sizes), but it has been found out experimentally, that this is not
1492 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1493 * as a minimum seem to work perfectly.
1494 */
1495 if (s->chan_rx) {
1496 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1497 port->fifosize / 2;
1498 dev_dbg(port->dev,
1499 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1500 s->rx_timeout * 1000 / HZ, port->timeout);
1501 if (s->rx_timeout < msecs_to_jiffies(20))
1502 s->rx_timeout = msecs_to_jiffies(20);
1503 }
1504#endif
1505
1464 if ((termios->c_cflag & CREAD) != 0) 1506 if ((termios->c_cflag & CREAD) != 0)
1465 sci_start_rx(port); 1507 sci_start_rx(port);
1466} 1508}
@@ -1552,10 +1594,10 @@ static struct uart_ops sci_uart_ops = {
1552#endif 1594#endif
1553}; 1595};
1554 1596
1555static void __devinit sci_init_single(struct platform_device *dev, 1597static int __devinit sci_init_single(struct platform_device *dev,
1556 struct sci_port *sci_port, 1598 struct sci_port *sci_port,
1557 unsigned int index, 1599 unsigned int index,
1558 struct plat_sci_port *p) 1600 struct plat_sci_port *p)
1559{ 1601{
1560 struct uart_port *port = &sci_port->port; 1602 struct uart_port *port = &sci_port->port;
1561 1603
@@ -1576,8 +1618,23 @@ static void __devinit sci_init_single(struct platform_device *dev,
1576 } 1618 }
1577 1619
1578 if (dev) { 1620 if (dev) {
1579 sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL; 1621 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1580 sci_port->dclk = clk_get(&dev->dev, "peripheral_clk"); 1622 if (IS_ERR(sci_port->iclk)) {
1623 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1624 if (IS_ERR(sci_port->iclk)) {
1625 dev_err(&dev->dev, "can't get iclk\n");
1626 return PTR_ERR(sci_port->iclk);
1627 }
1628 }
1629
1630 /*
1631 * The function clock is optional, ignore it if we can't
1632 * find it.
1633 */
1634 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1635 if (IS_ERR(sci_port->fclk))
1636 sci_port->fclk = NULL;
1637
1581 sci_port->enable = sci_clk_enable; 1638 sci_port->enable = sci_clk_enable;
1582 sci_port->disable = sci_clk_disable; 1639 sci_port->disable = sci_clk_disable;
1583 port->dev = &dev->dev; 1640 port->dev = &dev->dev;
@@ -1604,6 +1661,7 @@ static void __devinit sci_init_single(struct platform_device *dev,
1604#endif 1661#endif
1605 1662
1606 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs)); 1663 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
1664 return 0;
1607} 1665}
1608 1666
1609#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1667#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
@@ -1753,8 +1811,11 @@ static int sci_remove(struct platform_device *dev)
1753 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); 1811 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1754 1812
1755 spin_lock_irqsave(&priv->lock, flags); 1813 spin_lock_irqsave(&priv->lock, flags);
1756 list_for_each_entry(p, &priv->ports, node) 1814 list_for_each_entry(p, &priv->ports, node) {
1757 uart_remove_one_port(&sci_uart_driver, &p->port); 1815 uart_remove_one_port(&sci_uart_driver, &p->port);
1816 clk_put(p->iclk);
1817 clk_put(p->fclk);
1818 }
1758 spin_unlock_irqrestore(&priv->lock, flags); 1819 spin_unlock_irqrestore(&priv->lock, flags);
1759 1820
1760 kfree(priv); 1821 kfree(priv);
@@ -1780,7 +1841,9 @@ static int __devinit sci_probe_single(struct platform_device *dev,
1780 return 0; 1841 return 0;
1781 } 1842 }
1782 1843
1783 sci_init_single(dev, sciport, index, p); 1844 ret = sci_init_single(dev, sciport, index, p);
1845 if (ret)
1846 return ret;
1784 1847
1785 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 1848 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
1786 if (ret) 1849 if (ret)
diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c
index a3d8677af6a5..f43850527645 100644
--- a/drivers/sh/intc.c
+++ b/drivers/sh/intc.c
@@ -44,6 +44,12 @@ struct intc_handle_int {
44 unsigned long handle; 44 unsigned long handle;
45}; 45};
46 46
47struct intc_window {
48 phys_addr_t phys;
49 void __iomem *virt;
50 unsigned long size;
51};
52
47struct intc_desc_int { 53struct intc_desc_int {
48 struct list_head list; 54 struct list_head list;
49 struct sys_device sysdev; 55 struct sys_device sysdev;
@@ -57,6 +63,8 @@ struct intc_desc_int {
57 unsigned int nr_prio; 63 unsigned int nr_prio;
58 struct intc_handle_int *sense; 64 struct intc_handle_int *sense;
59 unsigned int nr_sense; 65 unsigned int nr_sense;
66 struct intc_window *window;
67 unsigned int nr_windows;
60 struct irq_chip chip; 68 struct irq_chip chip;
61}; 69};
62 70
@@ -446,11 +454,39 @@ static int intc_set_sense(unsigned int irq, unsigned int type)
446 return 0; 454 return 0;
447} 455}
448 456
457static unsigned long intc_phys_to_virt(struct intc_desc_int *d,
458 unsigned long address)
459{
460 struct intc_window *window;
461 int k;
462
463 /* scan through physical windows and convert address */
464 for (k = 0; k < d->nr_windows; k++) {
465 window = d->window + k;
466
467 if (address < window->phys)
468 continue;
469
470 if (address >= (window->phys + window->size))
471 continue;
472
473 address -= window->phys;
474 address += (unsigned long)window->virt;
475
476 return address;
477 }
478
479 /* no windows defined, register must be 1:1 mapped virt:phys */
480 return address;
481}
482
449static unsigned int __init intc_get_reg(struct intc_desc_int *d, 483static unsigned int __init intc_get_reg(struct intc_desc_int *d,
450 unsigned long address) 484 unsigned long address)
451{ 485{
452 unsigned int k; 486 unsigned int k;
453 487
488 address = intc_phys_to_virt(d, address);
489
454 for (k = 0; k < d->nr_reg; k++) { 490 for (k = 0; k < d->nr_reg; k++) {
455 if (d->reg[k] == address) 491 if (d->reg[k] == address)
456 return k; 492 return k;
@@ -800,6 +836,8 @@ static unsigned int __init save_reg(struct intc_desc_int *d,
800 unsigned int smp) 836 unsigned int smp)
801{ 837{
802 if (value) { 838 if (value) {
839 value = intc_phys_to_virt(d, value);
840
803 d->reg[cnt] = value; 841 d->reg[cnt] = value;
804#ifdef CONFIG_SMP 842#ifdef CONFIG_SMP
805 d->smp[cnt] = smp; 843 d->smp[cnt] = smp;
@@ -815,25 +853,52 @@ static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
815 generic_handle_irq((unsigned int)get_irq_data(irq)); 853 generic_handle_irq((unsigned int)get_irq_data(irq));
816} 854}
817 855
818void __init register_intc_controller(struct intc_desc *desc) 856int __init register_intc_controller(struct intc_desc *desc)
819{ 857{
820 unsigned int i, k, smp; 858 unsigned int i, k, smp;
821 struct intc_hw_desc *hw = &desc->hw; 859 struct intc_hw_desc *hw = &desc->hw;
822 struct intc_desc_int *d; 860 struct intc_desc_int *d;
861 struct resource *res;
823 862
824 d = kzalloc(sizeof(*d), GFP_NOWAIT); 863 d = kzalloc(sizeof(*d), GFP_NOWAIT);
864 if (!d)
865 goto err0;
825 866
826 INIT_LIST_HEAD(&d->list); 867 INIT_LIST_HEAD(&d->list);
827 list_add(&d->list, &intc_list); 868 list_add(&d->list, &intc_list);
828 869
870 if (desc->num_resources) {
871 d->nr_windows = desc->num_resources;
872 d->window = kzalloc(d->nr_windows * sizeof(*d->window),
873 GFP_NOWAIT);
874 if (!d->window)
875 goto err1;
876
877 for (k = 0; k < d->nr_windows; k++) {
878 res = desc->resource + k;
879 WARN_ON(resource_type(res) != IORESOURCE_MEM);
880 d->window[k].phys = res->start;
881 d->window[k].size = resource_size(res);
882 d->window[k].virt = ioremap_nocache(res->start,
883 resource_size(res));
884 if (!d->window[k].virt)
885 goto err2;
886 }
887 }
888
829 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; 889 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
830 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0; 890 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
831 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0; 891 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
832 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0; 892 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
833 893
834 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT); 894 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
895 if (!d->reg)
896 goto err2;
897
835#ifdef CONFIG_SMP 898#ifdef CONFIG_SMP
836 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT); 899 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
900 if (!d->smp)
901 goto err3;
837#endif 902#endif
838 k = 0; 903 k = 0;
839 904
@@ -848,6 +913,8 @@ void __init register_intc_controller(struct intc_desc *desc)
848 if (hw->prio_regs) { 913 if (hw->prio_regs) {
849 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio), 914 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
850 GFP_NOWAIT); 915 GFP_NOWAIT);
916 if (!d->prio)
917 goto err4;
851 918
852 for (i = 0; i < hw->nr_prio_regs; i++) { 919 for (i = 0; i < hw->nr_prio_regs; i++) {
853 smp = IS_SMP(hw->prio_regs[i]); 920 smp = IS_SMP(hw->prio_regs[i]);
@@ -859,6 +926,8 @@ void __init register_intc_controller(struct intc_desc *desc)
859 if (hw->sense_regs) { 926 if (hw->sense_regs) {
860 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense), 927 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
861 GFP_NOWAIT); 928 GFP_NOWAIT);
929 if (!d->sense)
930 goto err5;
862 931
863 for (i = 0; i < hw->nr_sense_regs; i++) 932 for (i = 0; i < hw->nr_sense_regs; i++)
864 k += save_reg(d, k, hw->sense_regs[i].reg, 0); 933 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
@@ -941,6 +1010,28 @@ void __init register_intc_controller(struct intc_desc *desc)
941 /* enable bits matching force_enable after registering irqs */ 1010 /* enable bits matching force_enable after registering irqs */
942 if (desc->force_enable) 1011 if (desc->force_enable)
943 intc_enable_disable_enum(desc, d, desc->force_enable, 1); 1012 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
1013
1014 return 0;
1015err5:
1016 kfree(d->prio);
1017err4:
1018#ifdef CONFIG_SMP
1019 kfree(d->smp);
1020err3:
1021#endif
1022 kfree(d->reg);
1023err2:
1024 for (k = 0; k < d->nr_windows; k++)
1025 if (d->window[k].virt)
1026 iounmap(d->window[k].virt);
1027
1028 kfree(d->window);
1029err1:
1030 kfree(d);
1031err0:
1032 pr_err("unable to allocate INTC memory\n");
1033
1034 return -ENOMEM;
944} 1035}
945 1036
946static int intc_suspend(struct sys_device *dev, pm_message_t state) 1037static int intc_suspend(struct sys_device *dev, pm_message_t state)
diff --git a/include/linux/device.h b/include/linux/device.h
index 182192892d45..241b96bcd7ad 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -451,6 +451,10 @@ struct device {
451 451
452static inline const char *dev_name(const struct device *dev) 452static inline const char *dev_name(const struct device *dev)
453{ 453{
454 /* Use the init name until the kobject becomes available */
455 if (dev->init_name)
456 return dev->init_name;
457
454 return kobject_name(&dev->kobj); 458 return kobject_name(&dev->kobj);
455} 459}
456 460
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index 193d4bfe42ff..f5364a1de68b 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -33,8 +33,8 @@ struct plat_sci_port {
33 char *clk; /* clock string */ 33 char *clk; /* clock string */
34 struct device *dma_dev; 34 struct device *dma_dev;
35#ifdef CONFIG_SERIAL_SH_SCI_DMA 35#ifdef CONFIG_SERIAL_SH_SCI_DMA
36 enum sh_dmae_slave_chan_id dma_slave_tx; 36 unsigned int dma_slave_tx;
37 enum sh_dmae_slave_chan_id dma_slave_rx; 37 unsigned int dma_slave_rx;
38#endif 38#endif
39}; 39};
40 40
diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
new file mode 100644
index 000000000000..cdaaff424211
--- /dev/null
+++ b/include/linux/sh_dma.h
@@ -0,0 +1,101 @@
1/*
2 * Header for the new SH dmaengine driver
3 *
4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef SH_DMA_H
11#define SH_DMA_H
12
13#include <linux/list.h>
14#include <linux/dmaengine.h>
15
16/* Used by slave DMA clients to request DMA to/from a specific peripheral */
17struct sh_dmae_slave {
18 unsigned int slave_id; /* Set by the platform */
19 struct device *dma_dev; /* Set by the platform */
20 struct sh_dmae_slave_config *config; /* Set by the driver */
21};
22
23struct sh_dmae_regs {
24 u32 sar; /* SAR / source address */
25 u32 dar; /* DAR / destination address */
26 u32 tcr; /* TCR / transfer count */
27};
28
29struct sh_desc {
30 struct sh_dmae_regs hw;
31 struct list_head node;
32 struct dma_async_tx_descriptor async_tx;
33 enum dma_data_direction direction;
34 dma_cookie_t cookie;
35 size_t partial;
36 int chunks;
37 int mark;
38};
39struct sh_dmae_slave_config {
40 unsigned int slave_id;
41 dma_addr_t addr;
42 u32 chcr;
43 char mid_rid;
44};
45
46struct sh_dmae_channel {
47 unsigned int offset;
48 unsigned int dmars;
49 unsigned int dmars_bit;
50};
51
52struct sh_dmae_pdata {
53 struct sh_dmae_slave_config *slave;
54 int slave_num;
55 struct sh_dmae_channel *channel;
56 int channel_num;
57 unsigned int ts_low_shift;
58 unsigned int ts_low_mask;
59 unsigned int ts_high_shift;
60 unsigned int ts_high_mask;
61 unsigned int *ts_shift;
62 int ts_shift_num;
63 u16 dmaor_init;
64};
65
66/* DMA register */
67#define SAR 0x00
68#define DAR 0x04
69#define TCR 0x08
70#define CHCR 0x0C
71#define DMAOR 0x40
72
73/* DMAOR definitions */
74#define DMAOR_AE 0x00000004
75#define DMAOR_NMIF 0x00000002
76#define DMAOR_DME 0x00000001
77
78/* Definitions for the SuperH DMAC */
79#define REQ_L 0x00000000
80#define REQ_E 0x00080000
81#define RACK_H 0x00000000
82#define RACK_L 0x00040000
83#define ACK_R 0x00000000
84#define ACK_W 0x00020000
85#define ACK_H 0x00000000
86#define ACK_L 0x00010000
87#define DM_INC 0x00004000
88#define DM_DEC 0x00008000
89#define DM_FIX 0x0000c000
90#define SM_INC 0x00001000
91#define SM_DEC 0x00002000
92#define SM_FIX 0x00003000
93#define RS_IN 0x00000200
94#define RS_OUT 0x00000300
95#define TS_BLK 0x00000040
96#define TM_BUR 0x00000020
97#define CHCR_DE 0x00000001
98#define CHCR_TE 0x00000002
99#define CHCR_IE 0x00000004
100
101#endif
diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h
index 51d288d8ac88..01d8168c5a1b 100644
--- a/include/linux/sh_intc.h
+++ b/include/linux/sh_intc.h
@@ -1,6 +1,8 @@
1#ifndef __SH_INTC_H 1#ifndef __SH_INTC_H
2#define __SH_INTC_H 2#define __SH_INTC_H
3 3
4#include <linux/ioport.h>
5
4typedef unsigned char intc_enum; 6typedef unsigned char intc_enum;
5 7
6struct intc_vect { 8struct intc_vect {
@@ -71,6 +73,8 @@ struct intc_hw_desc {
71 73
72struct intc_desc { 74struct intc_desc {
73 char *name; 75 char *name;
76 struct resource *resource;
77 unsigned int num_resources;
74 intc_enum force_enable; 78 intc_enum force_enable;
75 intc_enum force_disable; 79 intc_enum force_disable;
76 struct intc_hw_desc hw; 80 struct intc_hw_desc hw;
@@ -92,7 +96,7 @@ struct intc_desc symbol __initdata = { \
92 prio_regs, sense_regs, ack_regs), \ 96 prio_regs, sense_regs, ack_regs), \
93} 97}
94 98
95void __init register_intc_controller(struct intc_desc *desc); 99int __init register_intc_controller(struct intc_desc *desc);
96int intc_set_priority(unsigned int irq, unsigned int prio); 100int intc_set_priority(unsigned int irq, unsigned int prio);
97 101
98int reserve_irq_vector(unsigned int irq); 102int reserve_irq_vector(unsigned int irq);
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-03 01:13:48 -0400