diff options
| -rw-r--r-- | drivers/infiniband/hw/qib/qib_iba7322.c | 189 |
1 files changed, 0 insertions, 189 deletions
diff --git a/drivers/infiniband/hw/qib/qib_iba7322.c b/drivers/infiniband/hw/qib/qib_iba7322.c index 23fb9efe20a4..503992d9c5ce 100644 --- a/drivers/infiniband/hw/qib/qib_iba7322.c +++ b/drivers/infiniband/hw/qib/qib_iba7322.c | |||
| @@ -42,9 +42,6 @@ | |||
| 42 | #include <linux/jiffies.h> | 42 | #include <linux/jiffies.h> |
| 43 | #include <rdma/ib_verbs.h> | 43 | #include <rdma/ib_verbs.h> |
| 44 | #include <rdma/ib_smi.h> | 44 | #include <rdma/ib_smi.h> |
| 45 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 46 | #include <linux/dca.h> | ||
| 47 | #endif | ||
| 48 | 45 | ||
| 49 | #include "qib.h" | 46 | #include "qib.h" |
| 50 | #include "qib_7322_regs.h" | 47 | #include "qib_7322_regs.h" |
| @@ -518,12 +515,6 @@ struct qib_chip_specific { | |||
| 518 | u32 lastbuf_for_pio; | 515 | u32 lastbuf_for_pio; |
| 519 | u32 stay_in_freeze; | 516 | u32 stay_in_freeze; |
| 520 | u32 recovery_ports_initted; | 517 | u32 recovery_ports_initted; |
| 521 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 522 | u32 dca_ctrl; | ||
| 523 | int rhdr_cpu[18]; | ||
| 524 | int sdma_cpu[2]; | ||
| 525 | u64 dca_rcvhdr_ctrl[5]; /* B, C, D, E, F */ | ||
| 526 | #endif | ||
| 527 | struct msix_entry *msix_entries; | 518 | struct msix_entry *msix_entries; |
| 528 | void **msix_arg; | 519 | void **msix_arg; |
| 529 | unsigned long *sendchkenable; | 520 | unsigned long *sendchkenable; |
| @@ -642,52 +633,6 @@ static struct { | |||
| 642 | SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 }, | 633 | SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 }, |
| 643 | }; | 634 | }; |
| 644 | 635 | ||
| 645 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 646 | static const struct dca_reg_map { | ||
| 647 | int shadow_inx; | ||
| 648 | int lsb; | ||
| 649 | u64 mask; | ||
| 650 | u16 regno; | ||
| 651 | } dca_rcvhdr_reg_map[] = { | ||
| 652 | { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH), | ||
| 653 | ~SYM_MASK(DCACtrlB, RcvHdrq0DCAOPH) , KREG_IDX(DCACtrlB) }, | ||
| 654 | { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH), | ||
| 655 | ~SYM_MASK(DCACtrlB, RcvHdrq1DCAOPH) , KREG_IDX(DCACtrlB) }, | ||
| 656 | { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH), | ||
| 657 | ~SYM_MASK(DCACtrlB, RcvHdrq2DCAOPH) , KREG_IDX(DCACtrlB) }, | ||
| 658 | { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH), | ||
| 659 | ~SYM_MASK(DCACtrlB, RcvHdrq3DCAOPH) , KREG_IDX(DCACtrlB) }, | ||
| 660 | { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH), | ||
| 661 | ~SYM_MASK(DCACtrlC, RcvHdrq4DCAOPH) , KREG_IDX(DCACtrlC) }, | ||
| 662 | { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH), | ||
| 663 | ~SYM_MASK(DCACtrlC, RcvHdrq5DCAOPH) , KREG_IDX(DCACtrlC) }, | ||
| 664 | { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH), | ||
| 665 | ~SYM_MASK(DCACtrlC, RcvHdrq6DCAOPH) , KREG_IDX(DCACtrlC) }, | ||
| 666 | { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH), | ||
| 667 | ~SYM_MASK(DCACtrlC, RcvHdrq7DCAOPH) , KREG_IDX(DCACtrlC) }, | ||
| 668 | { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH), | ||
| 669 | ~SYM_MASK(DCACtrlD, RcvHdrq8DCAOPH) , KREG_IDX(DCACtrlD) }, | ||
| 670 | { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH), | ||
| 671 | ~SYM_MASK(DCACtrlD, RcvHdrq9DCAOPH) , KREG_IDX(DCACtrlD) }, | ||
| 672 | { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH), | ||
| 673 | ~SYM_MASK(DCACtrlD, RcvHdrq10DCAOPH) , KREG_IDX(DCACtrlD) }, | ||
| 674 | { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH), | ||
| 675 | ~SYM_MASK(DCACtrlD, RcvHdrq11DCAOPH) , KREG_IDX(DCACtrlD) }, | ||
| 676 | { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH), | ||
| 677 | ~SYM_MASK(DCACtrlE, RcvHdrq12DCAOPH) , KREG_IDX(DCACtrlE) }, | ||
| 678 | { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH), | ||
| 679 | ~SYM_MASK(DCACtrlE, RcvHdrq13DCAOPH) , KREG_IDX(DCACtrlE) }, | ||
| 680 | { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH), | ||
| 681 | ~SYM_MASK(DCACtrlE, RcvHdrq14DCAOPH) , KREG_IDX(DCACtrlE) }, | ||
| 682 | { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH), | ||
| 683 | ~SYM_MASK(DCACtrlE, RcvHdrq15DCAOPH) , KREG_IDX(DCACtrlE) }, | ||
| 684 | { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH), | ||
| 685 | ~SYM_MASK(DCACtrlF, RcvHdrq16DCAOPH) , KREG_IDX(DCACtrlF) }, | ||
| 686 | { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH), | ||
| 687 | ~SYM_MASK(DCACtrlF, RcvHdrq17DCAOPH) , KREG_IDX(DCACtrlF) }, | ||
| 688 | }; | ||
| 689 | #endif | ||
| 690 | |||
| 691 | /* ibcctrl bits */ | 636 | /* ibcctrl bits */ |
| 692 | #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1 | 637 | #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1 |
| 693 | /* cycle through TS1/TS2 till OK */ | 638 | /* cycle through TS1/TS2 till OK */ |
| @@ -2538,95 +2483,6 @@ static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on) | |||
| 2538 | qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink); | 2483 | qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink); |
| 2539 | } | 2484 | } |
| 2540 | 2485 | ||
| 2541 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 2542 | static void qib_update_rhdrq_dca(struct qib_ctxtdata *rcd) | ||
| 2543 | { | ||
| 2544 | struct qib_devdata *dd = rcd->dd; | ||
| 2545 | struct qib_chip_specific *cspec = dd->cspec; | ||
| 2546 | int cpu = get_cpu(); | ||
| 2547 | |||
| 2548 | if (cspec->rhdr_cpu[rcd->ctxt] != cpu) { | ||
| 2549 | const struct dca_reg_map *rmp; | ||
| 2550 | |||
| 2551 | cspec->rhdr_cpu[rcd->ctxt] = cpu; | ||
| 2552 | rmp = &dca_rcvhdr_reg_map[rcd->ctxt]; | ||
| 2553 | cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask; | ||
| 2554 | cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |= | ||
| 2555 | (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << rmp->lsb; | ||
| 2556 | qib_write_kreg(dd, rmp->regno, | ||
| 2557 | cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); | ||
| 2558 | cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable); | ||
| 2559 | qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); | ||
| 2560 | } | ||
| 2561 | put_cpu(); | ||
| 2562 | } | ||
| 2563 | |||
| 2564 | static void qib_update_sdma_dca(struct qib_pportdata *ppd) | ||
| 2565 | { | ||
| 2566 | struct qib_devdata *dd = ppd->dd; | ||
| 2567 | struct qib_chip_specific *cspec = dd->cspec; | ||
| 2568 | int cpu = get_cpu(); | ||
| 2569 | unsigned pidx = ppd->port - 1; | ||
| 2570 | |||
| 2571 | if (cspec->sdma_cpu[pidx] != cpu) { | ||
| 2572 | cspec->sdma_cpu[pidx] = cpu; | ||
| 2573 | cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ? | ||
| 2574 | SYM_MASK(DCACtrlF, SendDma1DCAOPH) : | ||
| 2575 | SYM_MASK(DCACtrlF, SendDma0DCAOPH)); | ||
| 2576 | cspec->dca_rcvhdr_ctrl[4] |= | ||
| 2577 | (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << | ||
| 2578 | (ppd->hw_pidx ? | ||
| 2579 | SYM_LSB(DCACtrlF, SendDma1DCAOPH) : | ||
| 2580 | SYM_LSB(DCACtrlF, SendDma0DCAOPH)); | ||
| 2581 | qib_write_kreg(dd, KREG_IDX(DCACtrlF), | ||
| 2582 | cspec->dca_rcvhdr_ctrl[4]); | ||
| 2583 | cspec->dca_ctrl |= ppd->hw_pidx ? | ||
| 2584 | SYM_MASK(DCACtrlA, SendDMAHead1DCAEnable) : | ||
| 2585 | SYM_MASK(DCACtrlA, SendDMAHead0DCAEnable); | ||
| 2586 | qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); | ||
| 2587 | } | ||
| 2588 | put_cpu(); | ||
| 2589 | } | ||
| 2590 | |||
| 2591 | static void qib_setup_dca(struct qib_devdata *dd) | ||
| 2592 | { | ||
| 2593 | struct qib_chip_specific *cspec = dd->cspec; | ||
| 2594 | int i; | ||
| 2595 | |||
| 2596 | for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++) | ||
| 2597 | cspec->rhdr_cpu[i] = -1; | ||
| 2598 | for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) | ||
| 2599 | cspec->sdma_cpu[i] = -1; | ||
| 2600 | cspec->dca_rcvhdr_ctrl[0] = | ||
| 2601 | (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) | | ||
| 2602 | (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) | | ||
| 2603 | (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) | | ||
| 2604 | (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt)); | ||
| 2605 | cspec->dca_rcvhdr_ctrl[1] = | ||
| 2606 | (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) | | ||
| 2607 | (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) | | ||
| 2608 | (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) | | ||
| 2609 | (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt)); | ||
| 2610 | cspec->dca_rcvhdr_ctrl[2] = | ||
| 2611 | (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) | | ||
| 2612 | (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) | | ||
| 2613 | (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) | | ||
| 2614 | (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt)); | ||
| 2615 | cspec->dca_rcvhdr_ctrl[3] = | ||
| 2616 | (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) | | ||
| 2617 | (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) | | ||
| 2618 | (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) | | ||
| 2619 | (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt)); | ||
| 2620 | cspec->dca_rcvhdr_ctrl[4] = | ||
| 2621 | (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) | | ||
| 2622 | (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt)); | ||
| 2623 | for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) | ||
| 2624 | qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i, | ||
| 2625 | cspec->dca_rcvhdr_ctrl[i]); | ||
| 2626 | } | ||
| 2627 | |||
| 2628 | #endif | ||
| 2629 | |||
| 2630 | /* | 2486 | /* |
| 2631 | * Disable MSIx interrupt if enabled, call generic MSIx code | 2487 | * Disable MSIx interrupt if enabled, call generic MSIx code |
| 2632 | * to cleanup, and clear pending MSIx interrupts. | 2488 | * to cleanup, and clear pending MSIx interrupts. |
| @@ -2667,15 +2523,6 @@ static void qib_setup_7322_cleanup(struct qib_devdata *dd) | |||
| 2667 | { | 2523 | { |
| 2668 | int i; | 2524 | int i; |
| 2669 | 2525 | ||
| 2670 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 2671 | if (dd->flags & QIB_DCA_ENABLED) { | ||
| 2672 | dca_remove_requester(&dd->pcidev->dev); | ||
| 2673 | dd->flags &= ~QIB_DCA_ENABLED; | ||
| 2674 | dd->cspec->dca_ctrl = 0; | ||
| 2675 | qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl); | ||
| 2676 | } | ||
| 2677 | #endif | ||
| 2678 | |||
| 2679 | qib_7322_free_irq(dd); | 2526 | qib_7322_free_irq(dd); |
| 2680 | kfree(dd->cspec->cntrs); | 2527 | kfree(dd->cspec->cntrs); |
| 2681 | kfree(dd->cspec->sendchkenable); | 2528 | kfree(dd->cspec->sendchkenable); |
| @@ -2983,11 +2830,6 @@ static irqreturn_t qib_7322pintr(int irq, void *data) | |||
| 2983 | if (dd->int_counter != (u32) -1) | 2830 | if (dd->int_counter != (u32) -1) |
| 2984 | dd->int_counter++; | 2831 | dd->int_counter++; |
| 2985 | 2832 | ||
| 2986 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 2987 | if (dd->flags & QIB_DCA_ENABLED) | ||
| 2988 | qib_update_rhdrq_dca(rcd); | ||
| 2989 | #endif | ||
| 2990 | |||
| 2991 | /* Clear the interrupt bit we expect to be set. */ | 2833 | /* Clear the interrupt bit we expect to be set. */ |
| 2992 | qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) | | 2834 | qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) | |
| 2993 | (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt); | 2835 | (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt); |
| @@ -3051,11 +2893,6 @@ static irqreturn_t sdma_intr(int irq, void *data) | |||
| 3051 | if (dd->int_counter != (u32) -1) | 2893 | if (dd->int_counter != (u32) -1) |
| 3052 | dd->int_counter++; | 2894 | dd->int_counter++; |
| 3053 | 2895 | ||
| 3054 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 3055 | if (dd->flags & QIB_DCA_ENABLED) | ||
| 3056 | qib_update_sdma_dca(ppd); | ||
| 3057 | #endif | ||
| 3058 | |||
| 3059 | /* Clear the interrupt bit we expect to be set. */ | 2896 | /* Clear the interrupt bit we expect to be set. */ |
| 3060 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? | 2897 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? |
| 3061 | INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0)); | 2898 | INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0)); |
| @@ -3085,11 +2922,6 @@ static irqreturn_t sdma_idle_intr(int irq, void *data) | |||
| 3085 | if (dd->int_counter != (u32) -1) | 2922 | if (dd->int_counter != (u32) -1) |
| 3086 | dd->int_counter++; | 2923 | dd->int_counter++; |
| 3087 | 2924 | ||
| 3088 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 3089 | if (dd->flags & QIB_DCA_ENABLED) | ||
| 3090 | qib_update_sdma_dca(ppd); | ||
| 3091 | #endif | ||
| 3092 | |||
| 3093 | /* Clear the interrupt bit we expect to be set. */ | 2925 | /* Clear the interrupt bit we expect to be set. */ |
| 3094 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? | 2926 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? |
| 3095 | INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0)); | 2927 | INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0)); |
| @@ -3119,11 +2951,6 @@ static irqreturn_t sdma_progress_intr(int irq, void *data) | |||
| 3119 | if (dd->int_counter != (u32) -1) | 2951 | if (dd->int_counter != (u32) -1) |
| 3120 | dd->int_counter++; | 2952 | dd->int_counter++; |
| 3121 | 2953 | ||
| 3122 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 3123 | if (dd->flags & QIB_DCA_ENABLED) | ||
| 3124 | qib_update_sdma_dca(ppd); | ||
| 3125 | #endif | ||
| 3126 | |||
| 3127 | /* Clear the interrupt bit we expect to be set. */ | 2954 | /* Clear the interrupt bit we expect to be set. */ |
| 3128 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? | 2955 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? |
| 3129 | INT_MASK_P(SDmaProgress, 1) : | 2956 | INT_MASK_P(SDmaProgress, 1) : |
| @@ -3154,11 +2981,6 @@ static irqreturn_t sdma_cleanup_intr(int irq, void *data) | |||
| 3154 | if (dd->int_counter != (u32) -1) | 2981 | if (dd->int_counter != (u32) -1) |
| 3155 | dd->int_counter++; | 2982 | dd->int_counter++; |
| 3156 | 2983 | ||
| 3157 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 3158 | if (dd->flags & QIB_DCA_ENABLED) | ||
| 3159 | qib_update_sdma_dca(ppd); | ||
| 3160 | #endif | ||
| 3161 | |||
| 3162 | /* Clear the interrupt bit we expect to be set. */ | 2984 | /* Clear the interrupt bit we expect to be set. */ |
| 3163 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? | 2985 | qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? |
| 3164 | INT_MASK_PM(SDmaCleanupDone, 1) : | 2986 | INT_MASK_PM(SDmaCleanupDone, 1) : |
| @@ -4265,10 +4087,6 @@ static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op, | |||
| 4265 | qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, | 4087 | qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, |
| 4266 | rcd->rcvhdrq_phys); | 4088 | rcd->rcvhdrq_phys); |
| 4267 | rcd->seq_cnt = 1; | 4089 | rcd->seq_cnt = 1; |
| 4268 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 4269 | if (dd->flags & QIB_DCA_ENABLED) | ||
| 4270 | qib_update_rhdrq_dca(rcd); | ||
| 4271 | #endif | ||
| 4272 | } | 4090 | } |
| 4273 | if (op & QIB_RCVCTRL_CTXT_DIS) | 4091 | if (op & QIB_RCVCTRL_CTXT_DIS) |
| 4274 | ppd->p_rcvctrl &= | 4092 | ppd->p_rcvctrl &= |
| @@ -6893,13 +6711,6 @@ struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev, | |||
| 6893 | /* clear diagctrl register, in case diags were running and crashed */ | 6711 | /* clear diagctrl register, in case diags were running and crashed */ |
| 6894 | qib_write_kreg(dd, kr_hwdiagctrl, 0); | 6712 | qib_write_kreg(dd, kr_hwdiagctrl, 0); |
| 6895 | 6713 | ||
| 6896 | #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE) | ||
| 6897 | ret = dca_add_requester(&pdev->dev); | ||
| 6898 | if (!ret) { | ||
| 6899 | dd->flags |= QIB_DCA_ENABLED; | ||
| 6900 | qib_setup_dca(dd); | ||
| 6901 | } | ||
| 6902 | #endif | ||
| 6903 | goto bail; | 6714 | goto bail; |
| 6904 | 6715 | ||
| 6905 | bail_cleanup: | 6716 | bail_cleanup: |
