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-rw-r--r--drivers/staging/Kconfig2
-rw-r--r--drivers/staging/Makefile1
-rw-r--r--drivers/staging/sxg/Kconfig10
-rw-r--r--drivers/staging/sxg/Makefile1
-rw-r--r--drivers/staging/sxg/README13
-rw-r--r--drivers/staging/sxg/saharadbgdownload.h4854
-rw-r--r--drivers/staging/sxg/sxg.c3608
-rw-r--r--drivers/staging/sxg/sxg.h773
-rw-r--r--drivers/staging/sxg/sxg_os.h154
-rw-r--r--drivers/staging/sxg/sxgdbg.h190
-rw-r--r--drivers/staging/sxg/sxghif.h861
-rw-r--r--drivers/staging/sxg/sxghw.h734
-rw-r--r--drivers/staging/sxg/sxgphycode.h349
13 files changed, 11550 insertions, 0 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index e18aecc6daf3..6da76622191c 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -27,4 +27,6 @@ source "drivers/staging/et131x/Kconfig"
27 27
28source "drivers/staging/slicoss/Kconfig" 28source "drivers/staging/slicoss/Kconfig"
29 29
30source "drivers/staging/sxg/Kconfig"
31
30endif # STAGING 32endif # STAGING
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index e5e4a0ee77a6..cd6d6a52751a 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -2,3 +2,4 @@
2 2
3obj-$(CONFIG_ET131X) += et131x/ 3obj-$(CONFIG_ET131X) += et131x/
4obj-$(CONFIG_SLICOSS) += slicoss/ 4obj-$(CONFIG_SLICOSS) += slicoss/
5obj-$(CONFIG_SXG) += sxg/
diff --git a/drivers/staging/sxg/Kconfig b/drivers/staging/sxg/Kconfig
new file mode 100644
index 000000000000..1ae350806600
--- /dev/null
+++ b/drivers/staging/sxg/Kconfig
@@ -0,0 +1,10 @@
1config SXG
2 tristate "Alacritech SLIC Technology Non-Accelerated 10Gbe support"
3 depends on PCI && NETDEV_10000
4 default n
5 help
6 This driver supports the Alacritech SLIC Technology Non-Accelerated
7 10Gbe network cards.
8
9 To compile this driver as a module, choose
10 M here: the module will be called sxg.
diff --git a/drivers/staging/sxg/Makefile b/drivers/staging/sxg/Makefile
new file mode 100644
index 000000000000..ec48faa7b3e3
--- /dev/null
+++ b/drivers/staging/sxg/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_SXG) += sxg.o
diff --git a/drivers/staging/sxg/README b/drivers/staging/sxg/README
new file mode 100644
index 000000000000..4d1ddbe4c335
--- /dev/null
+++ b/drivers/staging/sxg/README
@@ -0,0 +1,13 @@
1This is the rough cut at a driver for the Alacritech SLIC Technology
2Non-Accelerated 10Gbe network driver.
3
4TODO:
5 - lindent the code
6 - remove typedefs
7 - remove wrappers
8 - checkpatch.pl cleanups
9 - new functionality that the card needs
10
11Please send patches to:
12 Greg Kroah-Hartman <gregkh@suse.de>
13for any cleanups that you do to this driver.
diff --git a/drivers/staging/sxg/saharadbgdownload.h b/drivers/staging/sxg/saharadbgdownload.h
new file mode 100644
index 000000000000..d8865ba05047
--- /dev/null
+++ b/drivers/staging/sxg/saharadbgdownload.h
@@ -0,0 +1,4854 @@
1#define SAHARA_UCODE_VERS_STRING "$Revision: 1.1 $"
2#define SAHARA_UCODE_VERS_DATE "$Date: 2008/06/27 12:58:27 $"
3#define SAHARA_UCODE_HOSTIF_ID 3
4
5static u32 SNumSections = 0x2;
6static u32 SSectionSize[] =
7{
8 0x0000e274, 0x0000000c,
9};
10
11static u32 SSectionStart[] =
12{
13 0x00000000, 0x00001fff,
14};
15
16static unsigned char SaharaUCode[2][57972] =
17{
18{
19 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x82, 0x4d, 0x29, 0x3a,
20 0x00, 0x00, 0xb2, 0x03, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
21 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
22 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
23 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
24 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
25 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
26 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
27 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
28 0xfe, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0x02, 0x00, 0x36, 0x32,
29 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x02, 0x00, 0x00, 0x92,
30 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
31 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
32 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
33 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
34 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
35 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
36 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
37 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
38 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x40, 0x2b, 0x92,
39 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
40 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
41 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
42 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
43 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
44 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
45 0x00, 0x00, 0x2a, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
46 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x98, 0x1e, 0x80, 0xe9, 0x9a,
47 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
48 0x00, 0x00, 0x2d, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
49 0x00, 0x00, 0x2e, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
50 0x00, 0x00, 0x2f, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x0f, 0x80, 0x28, 0x92,
51 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x00, 0x00, 0x92,
52 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x40, 0x00, 0x92,
53 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x80, 0x00, 0x92,
54 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0xc0, 0x00, 0x92,
55 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x00, 0x01, 0x92,
56 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x40, 0x01, 0x92,
57 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x80, 0x01, 0x92,
58 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0xc0, 0x01, 0x92,
59 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x00, 0x02, 0x92,
60 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x40, 0x02, 0x92,
61 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x80, 0x02, 0x92,
62 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
63 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x00, 0x03, 0x92,
64 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x40, 0x03, 0x92,
65 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0x80, 0x03, 0x92,
66 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0f, 0xc0, 0x03, 0x92,
67 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0x5f, 0x3f, 0x00, 0x34,
68 0x00, 0x00, 0x8a, 0x11, 0x04, 0x00, 0x00, 0x80, 0x42, 0xff, 0xfc, 0xb0,
69 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x12, 0x80, 0xfd, 0x3a,
70 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
71 0x8a, 0x11, 0x8a, 0x11, 0x02, 0x01, 0x00, 0x80, 0x82, 0x8d, 0xfd, 0xbc,
72 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x12, 0x80, 0xfd, 0x3a,
73 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0xc0, 0x01, 0x32,
74 0x38, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x84, 0x82, 0x4d, 0x28, 0x1a,
75 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x60, 0x5f, 0x0a, 0xf6, 0x94,
76 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00, 0x00, 0xb0, 0x02, 0x00, 0x00, 0x92,
77 0x00, 0x00, 0x62, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x02, 0x00, 0x00, 0x92,
78 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x00, 0x90, 0x0e, 0x80, 0x18, 0x92,
79 0x00, 0x00, 0xd2, 0x02, 0x00, 0x00, 0x00, 0x00, 0x08, 0xc0, 0x20, 0x92,
80 0x00, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x21, 0x92,
81 0x00, 0x00, 0xd0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x08, 0x40, 0x21, 0x92,
82 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x85, 0x21, 0x90,
83 0x00, 0x00, 0x4b, 0x03, 0x00, 0x00, 0x00, 0xec, 0x02, 0xc0, 0x22, 0x92,
84 0x00, 0x00, 0x43, 0x04, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
85 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x00, 0xb0, 0x02, 0x40, 0x18, 0x9d,
86 0x00, 0x00, 0x4d, 0x00, 0x00, 0x00, 0x00, 0xd0, 0x02, 0x00, 0x00, 0x92,
87 0x00, 0x00, 0x8b, 0x03, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
88 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
89 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x80, 0x02, 0x00, 0x00, 0x70,
90 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xc0, 0x21, 0x92,
91 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0xe8, 0x02, 0x00, 0x90, 0x72,
92 0x00, 0x00, 0x8a, 0x11, 0x80, 0x01, 0x00, 0x80, 0xb2, 0x00, 0xe9, 0xb6,
93 0x00, 0x00, 0xb0, 0x03, 0x00, 0x00, 0x00, 0x7c, 0x1e, 0xc0, 0xe7, 0x9a,
94 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x13, 0x40, 0x01, 0x39,
95 0x00, 0x00, 0xa4, 0x03, 0x00, 0x00, 0x00, 0x08, 0xb8, 0x01, 0x00, 0x94,
96 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xb3, 0x40, 0x01, 0x39,
97 0x00, 0x00, 0xb0, 0x03, 0xb2, 0x00, 0x00, 0xd8, 0x02, 0x00, 0x00, 0xb2,
98 0x00, 0x00, 0x8a, 0x11, 0x17, 0x01, 0x00, 0x80, 0x02, 0x00, 0x00, 0xb0,
99 0x00, 0x00, 0x69, 0x05, 0x00, 0x10, 0x01, 0xf8, 0x02, 0x00, 0x6e, 0x92,
100 0x00, 0x00, 0x8a, 0x11, 0x0a, 0x00, 0x00, 0xcc, 0x02, 0x00, 0x00, 0xb2,
101 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x09, 0x00, 0x36, 0x32,
102 0x00, 0x00, 0xe2, 0x10, 0x00, 0x00, 0x00, 0x14, 0x09, 0x40, 0x18, 0xd2,
103 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x2b, 0x32,
104 0x00, 0x00, 0x57, 0x00, 0x80, 0x01, 0x00, 0x80, 0x12, 0x81, 0xfc, 0xb6,
105 0x00, 0x00, 0x8a, 0x11, 0x04, 0x01, 0x00, 0x80, 0x02, 0x00, 0x2b, 0xbc,
106 0x02, 0x00, 0x57, 0x00, 0xb0, 0x00, 0x00, 0xa0, 0xc2, 0x0a, 0x00, 0xb9,
107 0x00, 0x00, 0x5a, 0x00, 0x04, 0x01, 0x00, 0x80, 0x02, 0xc0, 0xb0, 0xbc,
108 0x00, 0x00, 0x60, 0x00, 0xa0, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
109 0x00, 0x00, 0x5c, 0x00, 0x80, 0x01, 0x00, 0x80, 0xc2, 0x4a, 0xd0, 0xb6,
110 0x00, 0x00, 0x60, 0x00, 0xa0, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
111 0x00, 0x00, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x04, 0xcd, 0x4a, 0xd0, 0x34,
112 0x00, 0x00, 0xfa, 0x0f, 0x00, 0x00, 0x00, 0xd8, 0x02, 0x00, 0x00, 0xd2,
113 0x00, 0x00, 0x8a, 0x11, 0x04, 0x00, 0x00, 0x80, 0x02, 0x80, 0x92, 0xbc,
114 0x18, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x0a, 0x03, 0xf9,
115 0x00, 0x00, 0x54, 0x00, 0x03, 0x01, 0x00, 0xb0, 0x02, 0x40, 0x18, 0xbd,
116 0x08, 0x00, 0xb0, 0x03, 0x00, 0x00, 0x00, 0xf8, 0xa3, 0x40, 0x01, 0x99,
117 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x00, 0x16, 0x32,
118 0x00, 0x00, 0x67, 0x00, 0x03, 0x01, 0x00, 0xd8, 0x02, 0x80, 0x80, 0xbd,
119 0x00, 0x00, 0x76, 0x00, 0x12, 0x01, 0x00, 0xe8, 0x02, 0xc0, 0x21, 0xb2,
120 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x0a, 0x03, 0x39,
121 0x76, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x02, 0x00, 0x36, 0x92,
122 0x00, 0x00, 0x6b, 0x00, 0x12, 0x01, 0x00, 0x5c, 0x08, 0x80, 0x22, 0xb2,
123 0x00, 0x00, 0x65, 0x00, 0x04, 0x01, 0x00, 0x80, 0x82, 0x85, 0x80, 0xbc,
124 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x8a, 0x03, 0x39,
125 0x63, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x02, 0x00, 0x36, 0x92,
126 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x68, 0x8b, 0x80, 0x35,
127 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0xb8, 0xff, 0x85, 0x30,
128 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x21, 0xff, 0x38,
129 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x87, 0x4d, 0x80, 0x3a,
130 0x2c, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x87, 0x0d, 0x80, 0x3a,
131 0x00, 0xc4, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x07, 0x00, 0x36, 0x32,
132 0x00, 0x00, 0x8a, 0x11, 0x12, 0x00, 0x00, 0x54, 0xf2, 0xc1, 0x38, 0xb4,
133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x12, 0x80, 0x2d, 0x37,
134 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c, 0x48, 0x41, 0x80, 0x3a,
135 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x86, 0x98, 0x67, 0xc0, 0x82, 0x3a,
136 0x00, 0x00, 0x63, 0x00, 0x12, 0x00, 0x00, 0xe8, 0x02, 0xc0, 0x21, 0xb2,
137 0x00, 0x00, 0x8a, 0x11, 0x80, 0x00, 0x00, 0x80, 0x62, 0x8b, 0x80, 0xb6,
138 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x12, 0x80, 0x2d, 0x37,
139 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c, 0x08, 0x80, 0x70, 0x32,
140 0x00, 0x00, 0x7c, 0x00, 0x90, 0x99, 0x86, 0x2c, 0x28, 0xde, 0x82, 0xba,
141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c, 0x18, 0xc0, 0x82, 0x3a,
142 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c, 0x08, 0xc5, 0x82, 0x30,
143 0x00, 0x00, 0x8a, 0x11, 0x04, 0x01, 0x00, 0x80, 0x02, 0xc5, 0x82, 0xbc,
144 0x00, 0x00, 0x63, 0x00, 0x00, 0x00, 0x00, 0x08, 0x68, 0x8b, 0x80, 0x94,
145 0x08, 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x40, 0x01, 0x99,
146 0x08, 0x00, 0x38, 0x03, 0x0c, 0x00, 0x00, 0xf8, 0x53, 0x40, 0x01, 0xb9,
147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x05, 0x80, 0x30,
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922 0x00, 0x00, 0x8a, 0x03, 0x04, 0x20, 0x01, 0x80, 0x52, 0x20, 0x6e, 0xbc,
923 0x00, 0x00, 0x8a, 0x11, 0x09, 0x01, 0x00, 0x80, 0x02, 0x00, 0x00, 0xb0,
924 0x25, 0x00, 0x9d, 0x05, 0x00, 0x00, 0x00, 0x1c, 0x08, 0x00, 0x36, 0x92,
925 0x24, 0x00, 0x9d, 0x05, 0x00, 0x00, 0x00, 0x1c, 0x08, 0x00, 0x36, 0x92,
926 0x00, 0x00, 0x93, 0x03, 0x04, 0x01, 0x00, 0xd8, 0x1e, 0x80, 0xed, 0xbc,
927 0x00, 0x00, 0x8c, 0x03, 0xb7, 0x00, 0x00, 0xd8, 0x0e, 0xc0, 0xed, 0xb2,
928 0x00, 0x00, 0x8f, 0x03, 0x04, 0x01, 0x00, 0x80, 0x42, 0x3b, 0xee, 0xbc,
929 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1e, 0x00, 0xee, 0x3a,
930 0x00, 0x00, 0x00, 0x00, 0xa7, 0x00, 0x00, 0xd0, 0x0e, 0x00, 0xee, 0x32,
931 0x00, 0x00, 0x93, 0x03, 0x80, 0x01, 0x00, 0x80, 0x92, 0x80, 0xfc, 0xb6,
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935 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x36, 0x32,
936 0x00, 0x00, 0x97, 0x03, 0x80, 0x01, 0x80, 0x80, 0x32, 0x0b, 0x6a, 0xb6,
937 0x35, 0x00, 0x8a, 0x11, 0x12, 0x00, 0x00, 0x2c, 0x82, 0xcd, 0x2e, 0xb2,
938 0x00, 0x00, 0x99, 0x03, 0x04, 0x01, 0x00, 0x80, 0x42, 0xc5, 0x2c, 0xbc,
939 0x00, 0x00, 0x9a, 0x03, 0x00, 0x00, 0x00, 0xcc, 0x02, 0x00, 0x00, 0x92,
940 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcc, 0x12, 0xc0, 0x2c, 0x3a,
941 0x00, 0x00, 0x95, 0x03, 0x04, 0x01, 0x00, 0x00, 0x19, 0x00, 0x90, 0xbc,
942 0x00, 0x00, 0x00, 0x00, 0x00, 0x74, 0x86, 0xc8, 0x06, 0xc0, 0x2c, 0x32,
943 0x08, 0x00, 0xb0, 0x03, 0x00, 0x00, 0x00, 0xf8, 0xc3, 0x40, 0x01, 0x99,
944 0x00, 0x00, 0x9f, 0x03, 0x04, 0x00, 0x00, 0x80, 0x02, 0x80, 0x80, 0xbc,
945 0x00, 0x00, 0x8a, 0x11, 0x04, 0x55, 0x01, 0x80, 0xb2, 0x1b, 0x2b, 0xbc,
946 0x00, 0x00, 0xc6, 0x0e, 0x00, 0x00, 0x00, 0x2c, 0x09, 0x00, 0x00, 0xf2,
947 0x00, 0x00, 0xa4, 0x03, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
948 0x00, 0x00, 0xa3, 0x03, 0x04, 0x00, 0x00, 0x80, 0x02, 0x80, 0x80, 0xbc,
949 0x00, 0x00, 0x8a, 0x11, 0x04, 0x55, 0x01, 0x80, 0xb2, 0x1b, 0x2b, 0xbc,
950 0x00, 0x00, 0xc6, 0x0e, 0x00, 0x00, 0x00, 0x2c, 0xf9, 0x01, 0x00, 0xf4,
951 0x00, 0x00, 0xad, 0x03, 0x04, 0x00, 0x00, 0x28, 0x09, 0x80, 0x80, 0xb2,
952 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x02, 0x00, 0x00, 0x32,
953 0x00, 0x00, 0xef, 0x0f, 0x00, 0x00, 0x00, 0x08, 0x08, 0x00, 0x00, 0xd2,
954 0x00, 0x00, 0xad, 0x03, 0x04, 0x00, 0x00, 0x80, 0x02, 0x80, 0x92, 0xbc,
955 0x18, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x0a, 0x03, 0xf9,
956 0x00, 0x00, 0xb0, 0x03, 0x80, 0x01, 0x00, 0x80, 0xa2, 0x80, 0x2f, 0xb6,
957 0x00, 0x00, 0xb0, 0x03, 0x12, 0x01, 0x00, 0x00, 0x09, 0xc0, 0x21, 0xb2,
958 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x0a, 0x03, 0x39,
959 0xb0, 0x03, 0x36, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x02, 0x00, 0x36, 0x92,
960 0x00, 0x00, 0xb0, 0x03, 0x80, 0x01, 0x00, 0x80, 0xa2, 0x80, 0x2f, 0xb6,
961 0x00, 0x00, 0xb0, 0x03, 0x12, 0x01, 0x00, 0x00, 0x09, 0xc0, 0x21, 0xb2,
962 0x18, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x0a, 0x03, 0xf9,
963 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x02, 0x00, 0x00, 0x32,
964 0x18, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x8a, 0x02, 0x99,
965 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
966 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
967 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
968 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
969 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
970 0x09, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
971 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcc, 0x0f, 0x00, 0x00, 0x32,
972 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
973 0x06, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
974 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
975 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
976 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
977 0x05, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
978 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
979 0x07, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
980 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x02, 0x00, 0x00, 0x32,
981 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x32,
982 0x00, 0x00, 0xc2, 0x03, 0x8b, 0x01, 0x00, 0xa0, 0x12, 0x00, 0x2a, 0xba,
983 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x02, 0x00, 0x00, 0x32,
984 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x32,
985 0x00, 0x00, 0xc5, 0x03, 0x06, 0x01, 0x00, 0x80, 0x02, 0x80, 0x2a, 0xbc,
986 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x02, 0x00, 0x00, 0x32,
987 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x02, 0x00, 0x00, 0x32,
988 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcc, 0x02, 0x00, 0x00, 0x32,
989 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x02, 0x00, 0x00, 0x32,
990 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0x02, 0x00, 0x00, 0x32,
991 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xdc, 0x02, 0x00, 0x00, 0x32,
992 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x02, 0x00, 0x00, 0x32,
993 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x02, 0x00, 0x00, 0x32,
994 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc4, 0x02, 0x00, 0x00, 0x32,
995 0x00, 0x00, 0xc8, 0x03, 0x85, 0x01, 0x00, 0x9c, 0x12, 0xc0, 0x29, 0xba,
996 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
997 0x0b, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
998 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
999 0x13, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1000 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1001 0x0c, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1002 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x06, 0x32,
1003 0x0f, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1004 0x00, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1005 0x0d, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1006 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1007 0x14, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1008 0xb7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1009 0x15, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1010 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1011 0x18, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1012 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1013 0x1d, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1014 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x04, 0x32,
1015 0x1e, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1016 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1017 0x1f, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1018 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x00, 0x32,
1019 0x20, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1020 0xe0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1021 0x17, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1022 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1023 0x1b, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1024 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1025 0x1c, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1026 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x40, 0x00, 0x32,
1027 0x16, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1028 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1029 0x1a, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1030 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1031 0x19, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1032 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1033 0x0b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1034 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1035 0x0c, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1036 0xfe, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0x02, 0x00, 0x36, 0x32,
1037 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x32,
1038 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x64, 0x02, 0x39,
1039 0x00, 0x00, 0xfb, 0x03, 0x85, 0x01, 0x00, 0x00, 0x19, 0x00, 0x90, 0xba,
1040 0x25, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1041 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1042 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, 0x00, 0x00, 0x32,
1043 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xf3, 0x40, 0x01, 0x39,
1044 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xe3, 0x40, 0x01, 0x39,
1045 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xc3, 0x40, 0x01, 0x39,
1046 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xb3, 0x40, 0x01, 0x39,
1047 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xa3, 0x40, 0x01, 0x39,
1048 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x93, 0x40, 0x01, 0x39,
1049 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x83, 0x40, 0x01, 0x39,
1050 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x40, 0x01, 0x39,
1051 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x63, 0x40, 0x01, 0x39,
1052 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x53, 0x40, 0x01, 0x39,
1053 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x43, 0x40, 0x01, 0x39,
1054 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x33, 0x40, 0x01, 0x39,
1055 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x13, 0x40, 0x01, 0x39,
1056 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x23, 0x40, 0x01, 0x39,
1057 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x80, 0x00, 0x32,
1058 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x3f, 0x80, 0xfc, 0x35,
1059 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x02, 0x00, 0x00, 0x32,
1060 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x32,
1061 0x4c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0x02, 0x00, 0x36, 0x32,
1062 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x03, 0x40, 0x38, 0x32,
1063 0x00, 0x00, 0x8a, 0x11, 0x04, 0x01, 0x00, 0x80, 0xd2, 0x01, 0x30, 0xb6,
1064 0x00, 0x00, 0x13, 0x04, 0x04, 0x01, 0x00, 0xd0, 0x12, 0x00, 0x2d, 0xbc,
1065 0x50, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x03, 0x00, 0x36, 0x32,
1066 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x37, 0x32,
1067 0x00, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0xd0, 0x02, 0x00, 0x00, 0x32,
1068 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xe0, 0x06, 0x00, 0x00, 0x32,
1069 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0xe4, 0x06, 0x00, 0x00, 0x32,
1070 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x01, 0xec, 0x06, 0x00, 0x00, 0x32,
1071 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0xe0, 0x06, 0x00, 0x00, 0x32,
1072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0x12, 0x00, 0x2d, 0x3a,
1073 0x4c, 0x00, 0x1a, 0x04, 0x02, 0x01, 0x00, 0x80, 0x82, 0x0d, 0x2d, 0xbc,
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1864 0x00, 0x00, 0x2a, 0x0c, 0x00, 0x00, 0x00, 0x10, 0x08, 0xc0, 0x01, 0x92,
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1872 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1873 0x00, 0x00, 0x34, 0x0c, 0x00, 0x00, 0x00, 0x10, 0x08, 0xc0, 0x01, 0x92,
1874 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
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1877 0x00, 0x00, 0xa2, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1878 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1879 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
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1882 0x00, 0x00, 0x34, 0x0c, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1883 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1884 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1885 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1886 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1887 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1888 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1889 0x00, 0x00, 0x31, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x08, 0x40, 0x01, 0x92,
1890 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1891 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1892 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1893 0x00, 0x00, 0xab, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x40, 0x00, 0x92,
1894 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1895 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1896 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1897 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1898 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1899 0x00, 0x00, 0xf3, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1900 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1901 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1902 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1903 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1904 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1905 0x00, 0x00, 0xb6, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1906 0x00, 0x00, 0xb6, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1907 0x00, 0x00, 0xb6, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1908 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1909 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1910 0x00, 0x00, 0x0a, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1911 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1912 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1913 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1914 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1915 0x00, 0x00, 0x1a, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1916 0x00, 0x00, 0xb4, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1917 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1918 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1919 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1920 0x00, 0x00, 0xc3, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1921 0x00, 0x00, 0xc3, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0xc0, 0x00, 0x92,
1922 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1923 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1924 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1925 0x00, 0x00, 0xe5, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0xc0, 0x00, 0x92,
1926 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1927 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1928 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1929 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1930 0x00, 0x00, 0xe8, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1931 0x00, 0x00, 0xe8, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1932 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1933 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1934 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1935 0x00, 0x00, 0xea, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1936 0x00, 0x00, 0xea, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0xc0, 0x00, 0x92,
1937 0x00, 0x00, 0xea, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1938 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1939 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x40, 0x00, 0x92,
1940 0x00, 0x00, 0xc2, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1941 0x00, 0x00, 0xc2, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0xc0, 0x00, 0x92,
1942 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1943 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x00, 0x92,
1944 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x40, 0x00, 0x92,
1945 0x00, 0x00, 0xf8, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1946 0x00, 0x00, 0xf8, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0xc0, 0x00, 0x92,
1947 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1948 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1949 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1950 0x00, 0x00, 0x2e, 0x09, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1951 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0xc0, 0x00, 0x92,
1952 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1953 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1954 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1955 0x00, 0x00, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1956 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1957 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1958 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1959 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1960 0x00, 0x00, 0x07, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1961 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1962 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1963 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1964 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1965 0x00, 0x00, 0x22, 0x09, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1966 0x00, 0x00, 0x22, 0x09, 0x00, 0x00, 0x00, 0x10, 0x08, 0xc0, 0x00, 0x92,
1967 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1968 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1969 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
1970 0x00, 0x00, 0xef, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x80, 0x00, 0x92,
1971 0x00, 0x00, 0xef, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0xc0, 0x00, 0x92,
1972 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x01, 0x92,
1973 0x08, 0x00, 0xa1, 0x03, 0x00, 0x18, 0x01, 0xe8, 0x76, 0x20, 0x81, 0x99,
1974 0x08, 0x00, 0x9d, 0x03, 0x00, 0x18, 0x01, 0xe8, 0x76, 0x20, 0x81, 0x99,
1975 0x00, 0x00, 0xb0, 0x10, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0xf0,
1976 0x08, 0x00, 0xa7, 0x07, 0x1d, 0x19, 0x01, 0xe8, 0x76, 0x20, 0x81, 0xb9,
1977 0x00, 0x00, 0xa1, 0x03, 0x00, 0x00, 0x00, 0xf8, 0x62, 0x81, 0x2f, 0x95,
1978 0x00, 0x00, 0xa1, 0x03, 0x80, 0x00, 0x00, 0x80, 0x02, 0x81, 0x2f, 0xb6,
1979 0x29, 0x00, 0x8a, 0x11, 0x12, 0x00, 0x00, 0x2c, 0x82, 0xcd, 0x2e, 0xb2,
1980 0x00, 0x00, 0xa1, 0x03, 0x00, 0x00, 0x00, 0xf8, 0x02, 0x81, 0x2f, 0x94,
1981 0x08, 0x00, 0xa1, 0x03, 0x00, 0x1c, 0x01, 0xe8, 0x76, 0x20, 0x81, 0x99,
1982 0x00, 0x00, 0x8a, 0x11, 0x80, 0x0f, 0x01, 0x80, 0x02, 0xc0, 0x6e, 0xb6,
1983 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x02, 0x00, 0x00, 0x32,
1984 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x01, 0xec, 0x06, 0xc0, 0x6e, 0x35,
1985 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x36, 0x32,
1986 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0xa9, 0x00, 0x2d, 0x37,
1987 0xb4, 0xcc, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x87, 0x8d, 0x97, 0x3a,
1988 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x99, 0xc0, 0x2c, 0x37,
1989 0xb4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x89, 0x8d, 0x97, 0x3a,
1990 0x00, 0x00, 0x8a, 0x11, 0x02, 0x10, 0x00, 0x00, 0x87, 0xbf, 0x97, 0xba,
1991 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x40, 0xfe, 0x32,
1992 0x00, 0x00, 0x8a, 0x11, 0x12, 0x00, 0x00, 0x40, 0xf2, 0xc1, 0x38, 0xb4,
1993 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 0x78, 0x09, 0x00, 0x6e, 0x32,
1994 0x00, 0x00, 0xb7, 0x07, 0xb7, 0x10, 0x02, 0xe0, 0x06, 0x80, 0x97, 0xb2,
1995 0x00, 0x00, 0xba, 0x07, 0x80, 0x00, 0x00, 0x80, 0xf2, 0x80, 0xfc, 0xb6,
1996 0x00, 0x00, 0xbb, 0x07, 0x00, 0x00, 0x00, 0xc8, 0xff, 0x80, 0xfc, 0x94,
1997 0x00, 0x00, 0xbc, 0x07, 0x9f, 0x99, 0x00, 0x80, 0x82, 0x1b, 0xee, 0xbc,
1998 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x00, 0xe0, 0x0e, 0x00, 0x6e, 0x32,
1999 0x00, 0x00, 0x00, 0x00, 0xa7, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x30,
2000 0x18, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x0a, 0x03, 0xf9,
2001 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x02, 0x1c, 0x09, 0x00, 0x6e, 0x32,
2002 0x40, 0x00, 0xc1, 0x07, 0x06, 0x01, 0x00, 0x80, 0x82, 0xcd, 0x91, 0xbc,
2003 0x00, 0x40, 0xc2, 0x07, 0x00, 0x18, 0x02, 0xe0, 0xa6, 0xcd, 0x2c, 0x92,
2004 0x00, 0x60, 0x00, 0x00, 0x00, 0x18, 0x02, 0xe0, 0xa6, 0xcd, 0x2c, 0x32,
2005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x09, 0x80, 0x03, 0x32,
2006 0x00, 0x00, 0xc5, 0x07, 0x80, 0xd7, 0x01, 0x80, 0x32, 0xc0, 0x6e, 0xb6,
2007 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x49, 0x00, 0x92, 0x3a,
2008 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x01, 0x18, 0x09, 0x00, 0x6e, 0x32,
2009 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x02, 0x24, 0x09, 0xc0, 0x6e, 0x32,
2010 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x28, 0x09, 0x80, 0x6e, 0x32,
2011 0x00, 0x00, 0xd3, 0x07, 0x80, 0x0e, 0x01, 0x80, 0x12, 0xc0, 0x6e, 0xb6,
2012 0x02, 0x00, 0x00, 0x00, 0x00, 0x34, 0x02, 0xec, 0x06, 0x00, 0x36, 0x32,
2013 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0x01, 0x92, 0x3a,
2014 0x00, 0x00, 0xcf, 0x07, 0x80, 0xd6, 0x01, 0x80, 0x42, 0xc0, 0x6e, 0xb6,
2015 0x00, 0x82, 0x00, 0x00, 0x00, 0x10, 0x02, 0xe0, 0xa6, 0xcd, 0x91, 0x32,
2016 0x00, 0xa0, 0x00, 0x00, 0x00, 0x2c, 0x02, 0xe8, 0x06, 0x00, 0x36, 0x32,
2017 0x28, 0x00, 0xdd, 0x07, 0x00, 0x32, 0x02, 0xec, 0x06, 0x00, 0x36, 0x92,
2018 0x00, 0x00, 0x00, 0x00, 0xd3, 0x01, 0x00, 0x1c, 0xd9, 0xc1, 0x91, 0x34,
2019 0x00, 0x82, 0x00, 0x00, 0x00, 0x10, 0x02, 0xe0, 0xa6, 0xcd, 0x91, 0x32,
2020 0x00, 0xa0, 0x00, 0x00, 0x00, 0x2c, 0x02, 0xe8, 0x06, 0x00, 0x36, 0x32,
2021 0x34, 0x00, 0xdd, 0x07, 0x00, 0x32, 0x02, 0xec, 0x06, 0x00, 0x36, 0x92,
2022 0x04, 0x00, 0x00, 0x00, 0x00, 0x34, 0x02, 0xec, 0x06, 0x00, 0x36, 0x32,
2023 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x0d, 0x92, 0x3a,
2024 0x00, 0x00, 0xd9, 0x07, 0x80, 0xd6, 0x01, 0x80, 0x42, 0xc0, 0x6e, 0xb6,
2025 0x00, 0x86, 0x00, 0x00, 0x00, 0x10, 0x02, 0xe0, 0xa6, 0xcd, 0x91, 0x32,
2026 0x04, 0xa0, 0x00, 0x00, 0x00, 0x2c, 0x02, 0xe8, 0x06, 0x00, 0x36, 0x32,
2027 0x14, 0x00, 0xdd, 0x07, 0x00, 0x32, 0x02, 0xec, 0x06, 0x00, 0x36, 0x92,
2028 0x00, 0x00, 0x00, 0x00, 0xd3, 0x01, 0x00, 0x1c, 0xd9, 0xc1, 0x91, 0x34,
2029 0x00, 0x86, 0x00, 0x00, 0x00, 0x10, 0x02, 0xe0, 0xa6, 0xcd, 0x91, 0x32,
2030 0x04, 0xa0, 0x00, 0x00, 0x00, 0x2c, 0x02, 0xe8, 0x06, 0x00, 0x36, 0x32,
2031 0x20, 0x00, 0xdd, 0x07, 0x00, 0x32, 0x02, 0xec, 0x06, 0x00, 0x36, 0x92,
2032 0x12, 0x00, 0x00, 0x00, 0x00, 0x30, 0x02, 0xec, 0x86, 0xcd, 0x91, 0x3a,
2033 0x08, 0x00, 0x00, 0x00, 0x00, 0x28, 0x02, 0xe8, 0x86, 0x24, 0x90, 0x39,
2034 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x02, 0xe0, 0x96, 0x24, 0x14, 0x37,
2035 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01, 0xe0, 0x06, 0x80, 0x91, 0x32,
2036 0x00, 0x00, 0xe3, 0x07, 0x04, 0x01, 0x00, 0x80, 0x02, 0x80, 0x92, 0xbc,
2037 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x01, 0xe0, 0x06, 0x00, 0x00, 0x32,
2038 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0xe0, 0x06, 0x00, 0x00, 0x32,
2039 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0, 0x00, 0xe0, 0x06, 0x00, 0x00, 0x32,
2040 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x36, 0x32,
2041 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0xa9, 0x00, 0x2d, 0x37,
2042 0x00, 0xcd, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x87, 0x8d, 0x97, 0x3a,
2043 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x99, 0xc0, 0x2c, 0x37,
2044 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x89, 0x8d, 0x97, 0x3a,
2045 0x00, 0x00, 0x8a, 0x11, 0x02, 0x10, 0x00, 0x00, 0x87, 0xbf, 0x97, 0xba,
2046 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x40, 0xfe, 0x32,
2047 0x00, 0x00, 0x8a, 0x11, 0x12, 0x00, 0x00, 0x48, 0xf2, 0xc1, 0x38, 0xb4,
2048 0x18, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x0a, 0x03, 0xf9,
2049 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x01, 0x38, 0x08, 0xc0, 0x6e, 0x32,
2050 0x00, 0x00, 0x8a, 0x11, 0x04, 0xc9, 0x01, 0x80, 0x02, 0x80, 0x6e, 0xbc,
2051 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 0xec, 0x06, 0x80, 0x83, 0x32,
2052 0x01, 0x00, 0xaa, 0x07, 0x12, 0x01, 0x00, 0x2c, 0x82, 0xcd, 0x2e, 0xb2,
2053 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
2054 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x01, 0xb0, 0x02, 0xc0, 0x6e, 0x32,
2055 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x02, 0x80, 0x01, 0x32,
2056 0x00, 0xc0, 0xf9, 0x07, 0x18, 0x01, 0x00, 0x0c, 0xa8, 0xcd, 0x3e, 0xb2,
2057 0x20, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x80, 0x36, 0x32,
2058 0x2c, 0x00, 0x9d, 0x03, 0x12, 0x01, 0x00, 0x2c, 0x82, 0xcd, 0x2e, 0xb2,
2059 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
2060 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 0x38, 0x08, 0xc0, 0x6e, 0x32,
2061 0x00, 0x08, 0x00, 0x80, 0x00, 0x00, 0x00, 0x28, 0x09, 0x00, 0x37, 0x32,
2062 0x00, 0x00, 0x50, 0x10, 0x00, 0x00, 0x00, 0x08, 0xe8, 0x01, 0x00, 0xf4,
2063 0x00, 0x00, 0xff, 0x07, 0x80, 0xd7, 0x01, 0x2c, 0x09, 0xc0, 0x6e, 0xb2,
2064 0x00, 0x00, 0x00, 0x00, 0xda, 0xd7, 0x01, 0xec, 0x06, 0xc0, 0x6e, 0x35,
2065 0x00, 0x00, 0x00, 0x00, 0x00, 0x5a, 0x01, 0xec, 0x06, 0x40, 0xed, 0x32,
2066 0x00, 0x00, 0x00, 0x00, 0x00, 0x5c, 0x01, 0xec, 0x06, 0x80, 0xee, 0x32,
2067 0x00, 0x00, 0x02, 0x08, 0x80, 0x01, 0x00, 0x80, 0x62, 0xc0, 0x92, 0xb6,
2068 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x82, 0x81, 0x2f, 0x34,
2069 0x00, 0x00, 0xaa, 0x07, 0x04, 0x06, 0x01, 0xec, 0x16, 0xc0, 0x6e, 0xbc,
2070 0x00, 0x00, 0xaa, 0x07, 0x80, 0x00, 0x00, 0x80, 0x72, 0x81, 0x2f, 0xb6,
2071 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x72, 0x81, 0x2f, 0x34,
2072 0x3b, 0x00, 0xaa, 0x07, 0x12, 0x01, 0x00, 0x2c, 0x82, 0xcd, 0x2e, 0xb2,
2073 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
2074 0x00, 0x00, 0x8a, 0x11, 0x04, 0x07, 0x01, 0x80, 0x12, 0xc0, 0x6e, 0xbc,
2075 0x00, 0x00, 0x8a, 0x11, 0x80, 0x00, 0x00, 0x80, 0xb2, 0x81, 0x2f, 0xb6,
2076 0x00, 0x00, 0x0a, 0x08, 0x00, 0x00, 0x00, 0xf8, 0xb2, 0x81, 0x2f, 0x94,
2077 0x00, 0x00, 0x8a, 0x11, 0x04, 0xa0, 0x00, 0x18, 0x08, 0x00, 0x6e, 0xb2,
2078 0x00, 0x00, 0x01, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0xf0,
2079 0x00, 0x00, 0x60, 0x11, 0x00, 0x78, 0x01, 0x60, 0x08, 0x00, 0x6e, 0xf2,
2080 0x00, 0x00, 0x0f, 0x08, 0x12, 0x01, 0x00, 0xc8, 0x02, 0x00, 0x20, 0xb2,
2081 0x00, 0x00, 0x12, 0x08, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
2082 0x00, 0x00, 0x1e, 0x08, 0x12, 0x01, 0x00, 0x5c, 0x08, 0x80, 0x20, 0xb2,
2083 0x00, 0x00, 0x12, 0x08, 0x12, 0x01, 0x00, 0x60, 0x02, 0x80, 0x2c, 0xb2,
2084 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
2085 0x00, 0x00, 0x14, 0x08, 0x04, 0x00, 0x00, 0x80, 0x02, 0x40, 0x80, 0xbc,
2086 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x80, 0xff, 0x3a,
2087 0x00, 0x00, 0x17, 0x08, 0x80, 0x01, 0x00, 0x80, 0xa2, 0x80, 0x2f, 0xb6,
2088 0x18, 0x00, 0x36, 0x00, 0xca, 0x00, 0x00, 0xf8, 0x73, 0x0a, 0x03, 0xf9,
2089 0x00, 0x00, 0x8a, 0x11, 0x04, 0x01, 0x00, 0x80, 0x02, 0x80, 0x2d, 0xbc,
2090 0x00, 0x00, 0xaa, 0x07, 0x80, 0x00, 0x00, 0x80, 0x72, 0x81, 0x2f, 0xb6,
2091 0x3b, 0x00, 0x8a, 0x11, 0x12, 0x00, 0x00, 0x2c, 0x82, 0xcd, 0x2e, 0xb2,
2092 0x00, 0x00, 0xaa, 0x07, 0x00, 0x00, 0x00, 0xf8, 0x72, 0x81, 0x2f, 0x94,
2093 0x00, 0x00, 0x00, 0x00, 0x00, 0xbc, 0x00, 0x14, 0x08, 0x80, 0x6e, 0x32,
2094 0x00, 0x00, 0x12, 0x08, 0x12, 0x00, 0x00, 0xc8, 0x02, 0x00, 0x20, 0xb2,
2095 0x00, 0x00, 0x10, 0x08, 0x12, 0x00, 0x00, 0x5c, 0x08, 0x80, 0x20, 0xb2,
2096 0x00, 0x00, 0x8a, 0x11, 0x04, 0xa0, 0x00, 0x18, 0x08, 0x00, 0x6e, 0xb2,
2097 0x00, 0x00, 0x8a, 0x11, 0x04, 0x01, 0x00, 0x80, 0x02, 0x40, 0x2d, 0xbc,
2098 0x08, 0x00, 0x00, 0x00, 0x00, 0x10, 0x02, 0x00, 0x78, 0xe1, 0x6e, 0x39,
2099 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x20, 0x07, 0x00, 0x00, 0x32,
2100 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x78, 0xca, 0xe9, 0x39,
2101 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x08, 0x40, 0x80, 0x32,
2102 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x79, 0x21, 0x2f, 0x39,
2103 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x02, 0x44, 0xe2, 0x25, 0x6e, 0x32,
2104 0x00, 0x00, 0x8a, 0x11, 0x04, 0x90, 0x00, 0x6c, 0x08, 0x00, 0x6e, 0xb2,
2105 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x00, 0x4c, 0x08, 0x00, 0x6e, 0x32,
2106 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x02, 0x00, 0x00, 0x32,
2107 0x00, 0x00, 0x00, 0x00, 0x4d, 0x00, 0x00, 0x00, 0x67, 0xe0, 0x83, 0x3e,
2108 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x07, 0x00, 0x80, 0x32,
2109 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x07, 0xc0, 0x86, 0x32,
2110 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0xc0, 0x84, 0x32,
2111 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0xd8, 0xa0, 0x81, 0x3c,
2112 0x00, 0x00, 0x82, 0x08, 0x04, 0xb0, 0x00, 0xe0, 0xd6, 0x20, 0x6e, 0xbc,
2113 0x00, 0x00, 0x8a, 0x11, 0x09, 0x01, 0x00, 0x80, 0x02, 0x00, 0x00, 0xb0,
2114 0x00, 0x00, 0x50, 0x08, 0x04, 0x00, 0x00, 0x3c, 0xd8, 0xe0, 0x83, 0xbc,
2115 0x00, 0x00, 0x8a, 0x11, 0x04, 0x01, 0x00, 0x80, 0x02, 0x80, 0x81, 0xbc,
2116 0x00, 0x00, 0x34, 0x08, 0x04, 0x00, 0x00, 0x80, 0x72, 0x80, 0x2d, 0xbc,
2117 0x00, 0x00, 0x8a, 0x11, 0x12, 0x00, 0x00, 0x44, 0xe2, 0xe0, 0x38, 0xb2,
2118 0x00, 0x00, 0x41, 0x08, 0x51, 0x00, 0x00, 0xd8, 0x12, 0x80, 0x2d, 0x9a,
2119 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0xf9, 0x81, 0x83, 0x34,
2120 0x00, 0x00, 0x8a, 0x11, 0x12, 0x00, 0x00, 0x44, 0xe2, 0xe5, 0x38, 0xb2,
2121 0x00, 0x00, 0x39, 0x08, 0x80, 0x00, 0x00, 0x80, 0x82, 0x80, 0x2f, 0xb6,
2122 0x00, 0x00, 0x5c, 0x10, 0x00, 0xa0, 0x01, 0x50, 0x08, 0x00, 0x6e, 0xf2,
2123 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 0xe0, 0x06, 0x00, 0x85, 0x32,
2124 0x00, 0x00, 0x3b, 0x08, 0x12, 0x01, 0x00, 0xe8, 0x02, 0xc0, 0x21, 0xb2,
2125 0x18, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x0a, 0x03, 0xf9,
2126 0x00, 0x00, 0x3f, 0x08, 0x04, 0x01, 0x00, 0x80, 0x02, 0x80, 0x2d, 0xbc,
2127 0x00, 0x00, 0x8a, 0x11, 0x80, 0x01, 0x00, 0x80, 0xa2, 0x80, 0x2f, 0xb6,
2128 0x00, 0x00, 0x3a, 0x08, 0x67, 0x00, 0x00, 0xf8, 0xa2, 0x80, 0x2f, 0xb5,
2129 0x00, 0x00, 0x8a, 0x11, 0x12, 0x00, 0x00, 0xe8, 0x02, 0xc0, 0x21, 0xb2,
2130 0x00, 0x00, 0x8a, 0x11, 0x04, 0x01, 0x00, 0x80, 0x72, 0x80, 0x2d, 0xbc,
2131 0x00, 0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0xd8, 0x02, 0x00, 0x00, 0x32,
2132 0x00, 0x00, 0x46, 0x08, 0x2a, 0x01, 0x00, 0x00, 0xd8, 0x20, 0x80, 0xba,
2133 0x00, 0x00, 0x45, 0x08, 0x12, 0x01, 0x00, 0x00, 0x09, 0xc0, 0x21, 0xb2,
2134 0x18, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x0a, 0x03, 0xf9,
2135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x02, 0x40, 0x84, 0x32,
2136 0x1d, 0x00, 0x8a, 0x11, 0x04, 0x00, 0x00, 0x80, 0x02, 0xa4, 0x17, 0xb8,
2137 0x00, 0x00, 0x00, 0x00, 0xca, 0xe0, 0x00, 0x6c, 0x08, 0x00, 0x6e, 0x32,
2138 0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0x00, 0x4c, 0x08, 0x00, 0x6e, 0x32,
2139 0x00, 0x00, 0x8a, 0x11, 0x04, 0xf0, 0x00, 0x18, 0x08, 0x00, 0x6e, 0xb2,
2140 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x18, 0x81, 0x83, 0x35,
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4718 0x26, 0x00, 0x57, 0x12, 0x04, 0x01, 0x00, 0x80, 0x82, 0xcd, 0xfa, 0xbc,
4719 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x80, 0x02, 0x00, 0x00, 0x50,
4720 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x0f, 0x40, 0x29, 0x32,
4721 0x00, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x02, 0x00, 0x36, 0x32,
4722 0x00, 0x00, 0x4c, 0x12, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0xd0,
4723 0x00, 0x00, 0x56, 0x12, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0xd0,
4724 0x00, 0x00, 0x29, 0x12, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0xd0,
4725 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x80, 0x18, 0x32,
4726 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x0f, 0x00, 0x00, 0x32,
4727 0xa2, 0x60, 0x03, 0x00, 0x00, 0x00, 0x00, 0x58, 0x03, 0x00, 0x37, 0x32,
4728 0x6b, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5c, 0x03, 0x00, 0x36, 0x32,
4729 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x0f, 0x80, 0x2a, 0x32,
4730 0x00, 0x00, 0x6b, 0x12, 0x04, 0x00, 0x00, 0x80, 0x02, 0x40, 0x29, 0xb2,
4731 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x83, 0x3e, 0x00, 0x34,
4732 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x83, 0x3e, 0x00, 0x34,
4733 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x53, 0x0a, 0x00, 0x34,
4734 0x00, 0x00, 0x6c, 0x12, 0x00, 0x00, 0x00, 0x88, 0x0f, 0x40, 0x2b, 0x92,
4735 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x0f, 0x00, 0x28, 0x32,
4736 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x0f, 0x00, 0x29, 0x32,
4737 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x0f, 0x80, 0x2a, 0x32,
4738 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x02, 0xc0, 0xf9, 0x32,
4739 0x71, 0x12, 0x97, 0x12, 0x00, 0x00, 0x00, 0xb0, 0x0f, 0x00, 0x36, 0x92,
4740 0x07, 0x00, 0x74, 0x12, 0x04, 0x00, 0x00, 0x80, 0x82, 0x4d, 0x29, 0xbc,
4741 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x1f, 0x00, 0xfa, 0x3a,
4742 0x00, 0x00, 0x68, 0x12, 0x00, 0x00, 0x00, 0x9c, 0x0f, 0x80, 0x2a, 0x92,
4743 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0x0f, 0x00, 0x36, 0x32,
4744 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x02, 0x00, 0x36, 0x32,
4745 0x00, 0x00, 0x84, 0x12, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0xd0,
4746 0x1f, 0x00, 0x7a, 0x12, 0x04, 0x00, 0x00, 0x80, 0x82, 0xcd, 0x29, 0xbc,
4747 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0x8f, 0xcd, 0xfa, 0x3a,
4748 0x00, 0x00, 0x76, 0x12, 0x00, 0x00, 0x00, 0x9c, 0x12, 0xc0, 0x29, 0x9a,
4749 0x00, 0x00, 0x3a, 0x12, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0xd0,
4750 0x00, 0x00, 0x30, 0x12, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0xd0,
4751 0x00, 0x00, 0x82, 0x12, 0x04, 0x00, 0x00, 0x80, 0x52, 0x8a, 0xfa, 0xbc,
4752 0xa2, 0x60, 0x03, 0x00, 0x00, 0x00, 0x00, 0x58, 0x03, 0x00, 0x37, 0x32,
4753 0x82, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5c, 0x03, 0x00, 0x36, 0x32,
4754 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0xa3, 0x3e, 0x00, 0x34,
4755 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0xa3, 0x3e, 0x00, 0x34,
4756 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x53, 0x0a, 0x00, 0x34,
4757 0x00, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x0f, 0x00, 0x36, 0x32,
4758 0x00, 0x00, 0xf7, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
4759 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc4, 0x02, 0xc0, 0xfa, 0x32,
4760 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x0f, 0x00, 0x36, 0x32,
4761 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xbc, 0x0f, 0x40, 0x2f, 0x32,
4762 0x00, 0x00, 0x8b, 0x12, 0x04, 0x00, 0x00, 0x9c, 0x1f, 0xc0, 0xf9, 0xbc,
4763 0x00, 0x00, 0x8a, 0x12, 0x04, 0x00, 0x00, 0x80, 0x02, 0x40, 0x2f, 0xb2,
4764 0x00, 0x00, 0x87, 0x12, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x2c, 0x92,
4765 0x00, 0x00, 0x87, 0x12, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x36, 0x92,
4766 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x40, 0x2c, 0x32,
4767 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x80, 0x2c, 0x32,
4768 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0xc0, 0x2c, 0x32,
4769 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x2d, 0x32,
4770 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x40, 0x2d, 0x32,
4771 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x80, 0x2d, 0x32,
4772 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0xc0, 0x2d, 0x32,
4773 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0xc0, 0xfb, 0x32,
4774 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x80, 0x2f, 0x32,
4775 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x73, 0x0a, 0x02, 0x39,
4776 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0xe0, 0x07, 0x80, 0x3f, 0x52,
4777 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x03, 0x00, 0x36, 0x32,
4778 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0xf9, 0x32,
4779 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x40, 0x28, 0x32,
4780 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x80, 0xf8, 0x32,
4781 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x0f, 0x00, 0x36, 0x32,
4782 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xbc, 0x0f, 0xc0, 0x2b, 0x32,
4783 0x00, 0x00, 0xa0, 0x12, 0x04, 0x00, 0x00, 0x9c, 0x1f, 0xc0, 0xf9, 0xbc,
4784 0x00, 0x00, 0x9f, 0x12, 0x04, 0x00, 0x00, 0x80, 0x02, 0xc0, 0x2b, 0xb2,
4785 0x00, 0x00, 0x9c, 0x12, 0x00, 0x00, 0x00, 0xe0, 0x07, 0xc0, 0x28, 0x92,
4786 0x00, 0x00, 0x9c, 0x12, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x36, 0x92,
4787 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x40, 0xf9, 0x32,
4788 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x40, 0x29, 0x32,
4789 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x80, 0x29, 0x32,
4790 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0xc0, 0x29, 0x32,
4791 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x2a, 0x32,
4792 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x40, 0x2a, 0x32,
4793 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x80, 0xf9, 0x32,
4794 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0xc0, 0x2a, 0x32,
4795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x2b, 0x32,
4796 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x40, 0x2b, 0x32,
4797 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x80, 0x2b, 0x32,
4798 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0xc0, 0xfb, 0x32,
4799 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x02, 0x00, 0xfb, 0x32,
4800 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x02, 0x00, 0x00, 0x32,
4801 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x02, 0x00, 0x00, 0x32,
4802 0x00, 0x00, 0xb1, 0x12, 0x9f, 0x00, 0x00, 0x80, 0x02, 0x00, 0x90, 0xb2,
4803 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x07, 0x40, 0x90, 0x52,
4804 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x07, 0x80, 0x90, 0x32,
4805 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x07, 0x40, 0x90, 0x52,
4806 0x00, 0x00, 0xb3, 0x12, 0x12, 0x00, 0x00, 0x48, 0xf2, 0x01, 0x00, 0xb4,
4807 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x90, 0x32,
4808 0x00, 0x00, 0xb5, 0x12, 0x12, 0x00, 0x00, 0x9c, 0x0f, 0xc0, 0x21, 0xb2,
4809 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x80, 0x02, 0x00, 0x00, 0x50,
4810 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb4, 0x0f, 0x40, 0xfb, 0x35,
4811 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x02, 0x00, 0x00, 0x32,
4812 0x4c, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x02, 0x00, 0x36, 0x32,
4813 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x07, 0x80, 0x2a, 0x32,
4814 0x00, 0x00, 0xad, 0x12, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0xd0,
4815 0x00, 0x00, 0xb3, 0x12, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0xd0,
4816 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0xcb, 0xc1, 0xb0, 0x34,
4817 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x02, 0x00, 0x00, 0x32,
4818 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x02, 0x00, 0x00, 0x32,
4819 0x00, 0x00, 0xc4, 0x12, 0x00, 0x00, 0x00, 0x28, 0x09, 0xc0, 0xb0, 0xd2,
4820 0x00, 0x00, 0xbe, 0x12, 0x04, 0x00, 0x00, 0x80, 0x02, 0x80, 0x92, 0xb2,
4821 0x00, 0x00, 0xc2, 0x12, 0x12, 0x00, 0x00, 0x9c, 0x0f, 0xc0, 0x21, 0xb2,
4822 0x00, 0x00, 0xc4, 0x11, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
4823 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0, 0x02, 0x00, 0x00, 0x32,
4824 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xc2, 0x0a, 0x00, 0x39,
4825 0x00, 0x00, 0xc8, 0x12, 0x04, 0x01, 0x00, 0x28, 0x09, 0x34, 0xb0, 0xba,
4826 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x28, 0x09, 0x00, 0x00, 0x52,
4827 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x22, 0x00, 0x2b, 0x37,
4828 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0xc0, 0x37, 0xac, 0xb0, 0x32,
4829 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0b, 0x00, 0x00, 0x32,
4830 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0xa9, 0x4d, 0xb0, 0x30,
4831 0x00, 0x00, 0xd8, 0x12, 0x80, 0x00, 0x00, 0x80, 0x02, 0x40, 0xb0, 0xb6,
4832 0x00, 0x00, 0xcd, 0x12, 0x12, 0x00, 0x00, 0x00, 0x09, 0x40, 0x20, 0xb2,
4833 0x00, 0x00, 0xce, 0x12, 0x12, 0x00, 0x00, 0x04, 0x09, 0x40, 0x20, 0xb2,
4834 0x00, 0x00, 0xd1, 0x12, 0x9f, 0x01, 0x00, 0x80, 0x02, 0x00, 0x90, 0xb2,
4835 0x00, 0x00, 0xd0, 0x12, 0x12, 0x00, 0x00, 0x08, 0x09, 0x40, 0x20, 0xb2,
4836 0x0d, 0x00, 0xcd, 0x12, 0x04, 0x01, 0x00, 0x80, 0x02, 0xe4, 0x16, 0xb8,
4837 0x02, 0x00, 0xcd, 0x12, 0x04, 0x01, 0x00, 0xbc, 0x0f, 0x24, 0x17, 0xb8,
4838 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xbc, 0x0f, 0x64, 0x16, 0x38,
4839 0x00, 0x00, 0xcd, 0x12, 0x04, 0x01, 0x00, 0x80, 0x22, 0xc0, 0xfb, 0xbc,
4840 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xc2, 0x0a, 0x00, 0x39,
4841 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x3b, 0x40, 0xb0, 0x33,
4842 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0xcd, 0x4a, 0xd0, 0x35,
4843 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe7, 0x25, 0x01, 0x32,
4844 0x00, 0x42, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x87, 0x8d, 0x2a, 0x3a,
4845 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x07, 0x00, 0xb0, 0x32,
4846 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00, 0xd0, 0x32,
4847 0x00, 0x00, 0x00, 0x00, 0x12, 0x01, 0x00, 0x48, 0xf2, 0xc1, 0x38, 0x54,
4848 0x00, 0x00, 0xdc, 0x12, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
4849 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
4850},
4851{
4852 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x90,
4853},
4854};
diff --git a/drivers/staging/sxg/sxg.c b/drivers/staging/sxg/sxg.c
new file mode 100644
index 000000000000..a91c9f397270
--- /dev/null
+++ b/drivers/staging/sxg/sxg.c
@@ -0,0 +1,3608 @@
1/**************************************************************************
2 *
3 * Copyright (C) 2000-2008 Alacritech, Inc. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above
12 * copyright notice, this list of conditions and the following
13 * disclaimer in the documentation and/or other materials provided
14 * with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
17 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * The views and conclusions contained in the software and documentation
30 * are those of the authors and should not be interpreted as representing
31 * official policies, either expressed or implied, of Alacritech, Inc.
32 *
33 **************************************************************************/
34
35/*
36 * FILENAME: sxg.c
37 *
38 * The SXG driver for Alacritech's 10Gbe products.
39 *
40 * NOTE: This is the standard, non-accelerated version of Alacritech's
41 * IS-NIC driver.
42 */
43
44#include <linux/kernel.h>
45#include <linux/string.h>
46#include <linux/errno.h>
47#include <linux/module.h>
48#include <linux/moduleparam.h>
49#include <linux/ioport.h>
50#include <linux/slab.h>
51#include <linux/interrupt.h>
52#include <linux/timer.h>
53#include <linux/pci.h>
54#include <linux/spinlock.h>
55#include <linux/init.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/ethtool.h>
59#include <linux/skbuff.h>
60#include <linux/delay.h>
61#include <linux/types.h>
62#include <linux/dma-mapping.h>
63#include <linux/mii.h>
64
65#define SLIC_DUMP_ENABLED 0
66#define SLIC_GET_STATS_ENABLED 0
67#define LINUX_FREES_ADAPTER_RESOURCES 1
68#define SXG_OFFLOAD_IP_CHECKSUM 0
69#define SXG_POWER_MANAGEMENT_ENABLED 0
70#define VPCI 0
71#define DBG 1
72#define ATK_DEBUG 1
73
74#include "sxg_os.h"
75#include "sxghw.h"
76#include "sxghif.h"
77#include "sxg.h"
78#include "sxgdbg.h"
79
80#include "sxgphycode.h"
81#include "saharadbgdownload.h"
82
83static int sxg_allocate_buffer_memory(p_adapter_t adapter, u32 Size, SXG_BUFFER_TYPE BufferType);
84static void sxg_allocate_rcvblock_complete(p_adapter_t adapter, void * RcvBlock, dma_addr_t PhysicalAddress, u32 Length);
85static void sxg_allocate_sgl_buffer_complete(p_adapter_t adapter, PSXG_SCATTER_GATHER SxgSgl, dma_addr_t PhysicalAddress, u32 Length);
86
87static void sxg_mcast_init_crc32(void);
88
89static int sxg_entry_open(p_net_device dev);
90static int sxg_entry_halt(p_net_device dev);
91static int sxg_ioctl(p_net_device dev, struct ifreq *rq, int cmd);
92static int sxg_send_packets(struct sk_buff *skb, p_net_device dev);
93static int sxg_transmit_packet(p_adapter_t adapter, struct sk_buff *skb);
94static void sxg_dumb_sgl(PSCATTER_GATHER_LIST pSgl, PSXG_SCATTER_GATHER SxgSgl);
95
96static void sxg_handle_interrupt(p_adapter_t adapter);
97static int sxg_process_isr(p_adapter_t adapter, u32 MessageId);
98static u32 sxg_process_event_queue(p_adapter_t adapter, u32 RssId);
99static void sxg_complete_slow_send(p_adapter_t adapter);
100static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event);
101static void sxg_process_rcv_error(p_adapter_t adapter, u32 ErrorStatus);
102static bool sxg_mac_filter(p_adapter_t adapter,
103 p_ether_header EtherHdr, ushort length);
104
105#if SLIC_GET_STATS_ENABLED
106static struct net_device_stats *sxg_get_stats(p_net_device dev);
107#endif
108
109static int sxg_mac_set_address(p_net_device dev, void * ptr);
110
111static void sxg_adapter_set_hwaddr(p_adapter_t adapter);
112
113static void sxg_unmap_mmio_space(p_adapter_t adapter);
114static void sxg_mcast_set_mask(p_adapter_t adapter);
115
116static int sxg_initialize_adapter(p_adapter_t adapter);
117static void sxg_stock_rcv_buffers(p_adapter_t adapter);
118static void sxg_complete_descriptor_blocks(p_adapter_t adapter, unsigned char Index);
119static int sxg_initialize_link(p_adapter_t adapter);
120static int sxg_phy_init(p_adapter_t adapter);
121static void sxg_link_event(p_adapter_t adapter);
122static SXG_LINK_STATE sxg_get_link_state(p_adapter_t adapter);
123static void sxg_link_state(p_adapter_t adapter, SXG_LINK_STATE LinkState);
124static int sxg_write_mdio_reg(p_adapter_t adapter,
125 u32 DevAddr, u32 RegAddr, u32 Value);
126static int sxg_read_mdio_reg(p_adapter_t adapter,
127 u32 DevAddr, u32 RegAddr, u32 * pValue);
128static void sxg_mcast_set_list(p_net_device dev);
129
130
131
132#define XXXTODO 0
133
134static unsigned int sxg_first_init = 1;
135static char *sxg_banner =
136 "Alacritech SLIC Technology(tm) Server and Storage 10Gbe Accelerator (Non-Accelerated)\n";
137
138static int sxg_debug = 1;
139static int debug = -1;
140static p_net_device head_netdevice = NULL;
141
142static sxgbase_driver_t sxg_global = {
143 .dynamic_intagg = 1,
144};
145static int intagg_delay = 100;
146static u32 dynamic_intagg = 0;
147
148#define DRV_NAME "sxg"
149#define DRV_VERSION "1.0.1"
150#define DRV_AUTHOR "Alacritech, Inc. Engineering"
151#define DRV_DESCRIPTION "Alacritech SLIC Techonology(tm) Non-Accelerated 10Gbe Driver"
152#define DRV_COPYRIGHT "Copyright 2000-2008 Alacritech, Inc. All rights reserved."
153
154MODULE_AUTHOR(DRV_AUTHOR);
155MODULE_DESCRIPTION(DRV_DESCRIPTION);
156MODULE_LICENSE("GPL");
157
158module_param(dynamic_intagg, int, 0);
159MODULE_PARM_DESC(dynamic_intagg, "Dynamic Interrupt Aggregation Setting");
160module_param(intagg_delay, int, 0);
161MODULE_PARM_DESC(intagg_delay, "uSec Interrupt Aggregation Delay");
162
163static struct pci_device_id sxg_pci_tbl[] __devinitdata = {
164 {PCI_DEVICE(SXG_VENDOR_ID, SXG_DEVICE_ID)},
165 {0,}
166};
167MODULE_DEVICE_TABLE(pci, sxg_pci_tbl);
168
169/***********************************************************************
170************************************************************************
171************************************************************************
172************************************************************************
173************************************************************************/
174
175static inline void sxg_reg32_write(void __iomem *reg, u32 value, bool flush)
176{
177 writel(value, reg);
178 if (flush)
179 mb();
180}
181
182static inline void sxg_reg64_write(p_adapter_t adapter, void __iomem *reg,
183 u64 value, u32 cpu)
184{
185 u32 value_high = (u32) (value >> 32);
186 u32 value_low = (u32) (value & 0x00000000FFFFFFFF);
187 unsigned long flags;
188
189 spin_lock_irqsave(&adapter->Bit64RegLock, flags);
190 writel(value_high, (void __iomem *)(&adapter->UcodeRegs[cpu].Upper));
191 writel(value_low, reg);
192 spin_unlock_irqrestore(&adapter->Bit64RegLock, flags);
193}
194
195static void sxg_init_driver(void)
196{
197 if (sxg_first_init) {
198 DBG_ERROR("sxg: %s sxg_first_init set jiffies[%lx]\n",
199 __FUNCTION__, jiffies);
200 sxg_first_init = 0;
201 spin_lock_init(&sxg_global.driver_lock);
202 }
203}
204
205static void sxg_dbg_macaddrs(p_adapter_t adapter)
206{
207 DBG_ERROR(" (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
208 adapter->netdev->name, adapter->currmacaddr[0],
209 adapter->currmacaddr[1], adapter->currmacaddr[2],
210 adapter->currmacaddr[3], adapter->currmacaddr[4],
211 adapter->currmacaddr[5]);
212 DBG_ERROR(" (%s) mac %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
213 adapter->netdev->name, adapter->macaddr[0],
214 adapter->macaddr[1], adapter->macaddr[2],
215 adapter->macaddr[3], adapter->macaddr[4],
216 adapter->macaddr[5]);
217 return;
218}
219
220// SXG Globals
221static SXG_DRIVER SxgDriver;
222
223#ifdef ATKDBG
224static sxg_trace_buffer_t LSxgTraceBuffer;
225#endif /* ATKDBG */
226static sxg_trace_buffer_t *SxgTraceBuffer = NULL;
227
228/*
229 * sxg_download_microcode
230 *
231 * Download Microcode to Sahara adapter
232 *
233 * Arguments -
234 * adapter - A pointer to our adapter structure
235 * UcodeSel - microcode file selection
236 *
237 * Return
238 * int
239 */
240static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
241{
242 PSXG_HW_REGS HwRegs = adapter->HwRegs;
243 u32 Section;
244 u32 ThisSectionSize;
245 u32 * Instruction = NULL;
246 u32 BaseAddress, AddressOffset, Address;
247// u32 Failure;
248 u32 ValueRead;
249 u32 i;
250 u32 numSections = 0;
251 u32 sectionSize[16];
252 u32 sectionStart[16];
253
254 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DnldUcod",
255 adapter, 0, 0, 0);
256 DBG_ERROR("sxg: %s ENTER\n", __FUNCTION__);
257
258 switch (UcodeSel) {
259 case SXG_UCODE_SAHARA: // Sahara operational ucode
260 numSections = SNumSections;
261 for (i = 0; i < numSections; i++) {
262 sectionSize[i] = SSectionSize[i];
263 sectionStart[i] = SSectionStart[i];
264 }
265 break;
266 default:
267 printk(KERN_ERR KBUILD_MODNAME
268 ": Woah, big error with the microcode!\n");
269 break;
270 }
271
272 DBG_ERROR("sxg: RESET THE CARD\n");
273 // First, reset the card
274 WRITE_REG(HwRegs->Reset, 0xDEAD, FLUSH);
275
276 // Download each section of the microcode as specified in
277 // its download file. The *download.c file is generated using
278 // the saharaobjtoc facility which converts the metastep .obj
279 // file to a .c file which contains a two dimentional array.
280 for (Section = 0; Section < numSections; Section++) {
281 DBG_ERROR("sxg: SECTION # %d\n", Section);
282 switch (UcodeSel) {
283 case SXG_UCODE_SAHARA:
284 Instruction = (u32 *) & SaharaUCode[Section][0];
285 break;
286 default:
287 ASSERT(0);
288 break;
289 }
290 BaseAddress = sectionStart[Section];
291 ThisSectionSize = sectionSize[Section] / 12; // Size in instructions
292 for (AddressOffset = 0; AddressOffset < ThisSectionSize;
293 AddressOffset++) {
294 Address = BaseAddress + AddressOffset;
295 ASSERT((Address & ~MICROCODE_ADDRESS_MASK) == 0);
296 // Write instruction bits 31 - 0
297 WRITE_REG(HwRegs->UcodeDataLow, *Instruction, FLUSH);
298 // Write instruction bits 63-32
299 WRITE_REG(HwRegs->UcodeDataMiddle, *(Instruction + 1),
300 FLUSH);
301 // Write instruction bits 95-64
302 WRITE_REG(HwRegs->UcodeDataHigh, *(Instruction + 2),
303 FLUSH);
304 // Write instruction address with the WRITE bit set
305 WRITE_REG(HwRegs->UcodeAddr,
306 (Address | MICROCODE_ADDRESS_WRITE), FLUSH);
307 // Sahara bug in the ucode download logic - the write to DataLow
308 // for the next instruction could get corrupted. To avoid this,
309 // write to DataLow again for this instruction (which may get
310 // corrupted, but it doesn't matter), then increment the address
311 // and write the data for the next instruction to DataLow. That
312 // write should succeed.
313 WRITE_REG(HwRegs->UcodeDataLow, *Instruction, TRUE);
314 // Advance 3 u32S to start of next instruction
315 Instruction += 3;
316 }
317 }
318 // Now repeat the entire operation reading the instruction back and
319 // checking for parity errors
320 for (Section = 0; Section < numSections; Section++) {
321 DBG_ERROR("sxg: check SECTION # %d\n", Section);
322 switch (UcodeSel) {
323 case SXG_UCODE_SAHARA:
324 Instruction = (u32 *) & SaharaUCode[Section][0];
325 break;
326 default:
327 ASSERT(0);
328 break;
329 }
330 BaseAddress = sectionStart[Section];
331 ThisSectionSize = sectionSize[Section] / 12; // Size in instructions
332 for (AddressOffset = 0; AddressOffset < ThisSectionSize;
333 AddressOffset++) {
334 Address = BaseAddress + AddressOffset;
335 // Write the address with the READ bit set
336 WRITE_REG(HwRegs->UcodeAddr,
337 (Address | MICROCODE_ADDRESS_READ), FLUSH);
338 // Read it back and check parity bit.
339 READ_REG(HwRegs->UcodeAddr, ValueRead);
340 if (ValueRead & MICROCODE_ADDRESS_PARITY) {
341 DBG_ERROR("sxg: %s PARITY ERROR\n",
342 __FUNCTION__);
343
344 return (FALSE); // Parity error
345 }
346 ASSERT((ValueRead & MICROCODE_ADDRESS_MASK) == Address);
347 // Read the instruction back and compare
348 READ_REG(HwRegs->UcodeDataLow, ValueRead);
349 if (ValueRead != *Instruction) {
350 DBG_ERROR("sxg: %s MISCOMPARE LOW\n",
351 __FUNCTION__);
352 return (FALSE); // Miscompare
353 }
354 READ_REG(HwRegs->UcodeDataMiddle, ValueRead);
355 if (ValueRead != *(Instruction + 1)) {
356 DBG_ERROR("sxg: %s MISCOMPARE MIDDLE\n",
357 __FUNCTION__);
358 return (FALSE); // Miscompare
359 }
360 READ_REG(HwRegs->UcodeDataHigh, ValueRead);
361 if (ValueRead != *(Instruction + 2)) {
362 DBG_ERROR("sxg: %s MISCOMPARE HIGH\n",
363 __FUNCTION__);
364 return (FALSE); // Miscompare
365 }
366 // Advance 3 u32S to start of next instruction
367 Instruction += 3;
368 }
369 }
370
371 // Everything OK, Go.
372 WRITE_REG(HwRegs->UcodeAddr, MICROCODE_ADDRESS_GO, FLUSH);
373
374 // Poll the CardUp register to wait for microcode to initialize
375 // Give up after 10,000 attemps (500ms).
376 for (i = 0; i < 10000; i++) {
377 udelay(50);
378 READ_REG(adapter->UcodeRegs[0].CardUp, ValueRead);
379 if (ValueRead == 0xCAFE) {
380 DBG_ERROR("sxg: %s BOO YA 0xCAFE\n", __FUNCTION__);
381 break;
382 }
383 }
384 if (i == 10000) {
385 DBG_ERROR("sxg: %s TIMEOUT\n", __FUNCTION__);
386
387 return (FALSE); // Timeout
388 }
389 // Now write the LoadSync register. This is used to
390 // synchronize with the card so it can scribble on the memory
391 // that contained 0xCAFE from the "CardUp" step above
392 if (UcodeSel == SXG_UCODE_SAHARA) {
393 WRITE_REG(adapter->UcodeRegs[0].LoadSync, 0, FLUSH);
394 }
395
396 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDnldUcd",
397 adapter, 0, 0, 0);
398 DBG_ERROR("sxg: %s EXIT\n", __FUNCTION__);
399
400 return (TRUE);
401}
402
403/*
404 * sxg_allocate_resources - Allocate memory and locks
405 *
406 * Arguments -
407 * adapter - A pointer to our adapter structure
408 *
409 * Return
410 * int
411 */
412static int sxg_allocate_resources(p_adapter_t adapter)
413{
414 int status;
415 u32 i;
416 u32 RssIds, IsrCount;
417// PSXG_XMT_RING XmtRing;
418// PSXG_RCV_RING RcvRing;
419
420 DBG_ERROR("%s ENTER\n", __FUNCTION__);
421
422 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocRes",
423 adapter, 0, 0, 0);
424
425 // Windows tells us how many CPUs it plans to use for
426 // RSS
427 RssIds = SXG_RSS_CPU_COUNT(adapter);
428 IsrCount = adapter->MsiEnabled ? RssIds : 1;
429
430 DBG_ERROR("%s Setup the spinlocks\n", __FUNCTION__);
431
432 // Allocate spinlocks and initialize listheads first.
433 spin_lock_init(&adapter->RcvQLock);
434 spin_lock_init(&adapter->SglQLock);
435 spin_lock_init(&adapter->XmtZeroLock);
436 spin_lock_init(&adapter->Bit64RegLock);
437 spin_lock_init(&adapter->AdapterLock);
438
439 DBG_ERROR("%s Setup the lists\n", __FUNCTION__);
440
441 InitializeListHead(&adapter->FreeRcvBuffers);
442 InitializeListHead(&adapter->FreeRcvBlocks);
443 InitializeListHead(&adapter->AllRcvBlocks);
444 InitializeListHead(&adapter->FreeSglBuffers);
445 InitializeListHead(&adapter->AllSglBuffers);
446
447 // Mark these basic allocations done. This flags essentially
448 // tells the SxgFreeResources routine that it can grab spinlocks
449 // and reference listheads.
450 adapter->BasicAllocations = TRUE;
451 // Main allocation loop. Start with the maximum supported by
452 // the microcode and back off if memory allocation
453 // fails. If we hit a minimum, fail.
454
455 for (;;) {
456 DBG_ERROR("%s Allocate XmtRings size[%x]\n", __FUNCTION__,
457 (sizeof(SXG_XMT_RING) * 1));
458
459 // Start with big items first - receive and transmit rings. At the moment
460 // I'm going to keep the ring size fixed and adjust the number of
461 // TCBs if we fail. Later we might consider reducing the ring size as well..
462 adapter->XmtRings = pci_alloc_consistent(adapter->pcidev,
463 sizeof(SXG_XMT_RING) *
464 1,
465 &adapter->PXmtRings);
466 DBG_ERROR("%s XmtRings[%p]\n", __FUNCTION__, adapter->XmtRings);
467
468 if (!adapter->XmtRings) {
469 goto per_tcb_allocation_failed;
470 }
471 memset(adapter->XmtRings, 0, sizeof(SXG_XMT_RING) * 1);
472
473 DBG_ERROR("%s Allocate RcvRings size[%x]\n", __FUNCTION__,
474 (sizeof(SXG_RCV_RING) * 1));
475 adapter->RcvRings =
476 pci_alloc_consistent(adapter->pcidev,
477 sizeof(SXG_RCV_RING) * 1,
478 &adapter->PRcvRings);
479 DBG_ERROR("%s RcvRings[%p]\n", __FUNCTION__, adapter->RcvRings);
480 if (!adapter->RcvRings) {
481 goto per_tcb_allocation_failed;
482 }
483 memset(adapter->RcvRings, 0, sizeof(SXG_RCV_RING) * 1);
484 break;
485
486 per_tcb_allocation_failed:
487 // an allocation failed. Free any successful allocations.
488 if (adapter->XmtRings) {
489 pci_free_consistent(adapter->pcidev,
490 sizeof(SXG_XMT_RING) * 4096,
491 adapter->XmtRings,
492 adapter->PXmtRings);
493 adapter->XmtRings = NULL;
494 }
495 if (adapter->RcvRings) {
496 pci_free_consistent(adapter->pcidev,
497 sizeof(SXG_RCV_RING) * 4096,
498 adapter->RcvRings,
499 adapter->PRcvRings);
500 adapter->RcvRings = NULL;
501 }
502 // Loop around and try again....
503 }
504
505 DBG_ERROR("%s Initialize RCV ZERO and XMT ZERO rings\n", __FUNCTION__);
506 // Initialize rcv zero and xmt zero rings
507 SXG_INITIALIZE_RING(adapter->RcvRingZeroInfo, SXG_RCV_RING_SIZE);
508 SXG_INITIALIZE_RING(adapter->XmtRingZeroInfo, SXG_XMT_RING_SIZE);
509
510 // Sanity check receive data structure format
511 ASSERT((adapter->ReceiveBufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
512 (adapter->ReceiveBufferSize == SXG_RCV_JUMBO_BUFFER_SIZE));
513 ASSERT(sizeof(SXG_RCV_DESCRIPTOR_BLOCK) ==
514 SXG_RCV_DESCRIPTOR_BLOCK_SIZE);
515
516 // Allocate receive data buffers. We allocate a block of buffers and
517 // a corresponding descriptor block at once. See sxghw.h:SXG_RCV_BLOCK
518 for (i = 0; i < SXG_INITIAL_RCV_DATA_BUFFERS;
519 i += SXG_RCV_DESCRIPTORS_PER_BLOCK) {
520 sxg_allocate_buffer_memory(adapter,
521 SXG_RCV_BLOCK_SIZE(adapter->
522 ReceiveBufferSize),
523 SXG_BUFFER_TYPE_RCV);
524 }
525 // NBL resource allocation can fail in the 'AllocateComplete' routine, which
526 // doesn't return status. Make sure we got the number of buffers we requested
527 if (adapter->FreeRcvBufferCount < SXG_INITIAL_RCV_DATA_BUFFERS) {
528 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF6",
529 adapter, adapter->FreeRcvBufferCount, SXG_MAX_ENTRIES,
530 0);
531 return (STATUS_RESOURCES);
532 }
533
534 DBG_ERROR("%s Allocate EventRings size[%x]\n", __FUNCTION__,
535 (sizeof(SXG_EVENT_RING) * RssIds));
536
537 // Allocate event queues.
538 adapter->EventRings = pci_alloc_consistent(adapter->pcidev,
539 sizeof(SXG_EVENT_RING) *
540 RssIds,
541 &adapter->PEventRings);
542
543 if (!adapter->EventRings) {
544 // Caller will call SxgFreeAdapter to clean up above allocations
545 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF8",
546 adapter, SXG_MAX_ENTRIES, 0, 0);
547 status = STATUS_RESOURCES;
548 goto per_tcb_allocation_failed;
549 }
550 memset(adapter->EventRings, 0, sizeof(SXG_EVENT_RING) * RssIds);
551
552 DBG_ERROR("%s Allocate ISR size[%x]\n", __FUNCTION__, IsrCount);
553 // Allocate ISR
554 adapter->Isr = pci_alloc_consistent(adapter->pcidev,
555 IsrCount, &adapter->PIsr);
556 if (!adapter->Isr) {
557 // Caller will call SxgFreeAdapter to clean up above allocations
558 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF9",
559 adapter, SXG_MAX_ENTRIES, 0, 0);
560 status = STATUS_RESOURCES;
561 goto per_tcb_allocation_failed;
562 }
563 memset(adapter->Isr, 0, sizeof(u32) * IsrCount);
564
565 DBG_ERROR("%s Allocate shared XMT ring zero index location size[%x]\n",
566 __FUNCTION__, sizeof(u32));
567
568 // Allocate shared XMT ring zero index location
569 adapter->XmtRingZeroIndex = pci_alloc_consistent(adapter->pcidev,
570 sizeof(u32),
571 &adapter->
572 PXmtRingZeroIndex);
573 if (!adapter->XmtRingZeroIndex) {
574 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF10",
575 adapter, SXG_MAX_ENTRIES, 0, 0);
576 status = STATUS_RESOURCES;
577 goto per_tcb_allocation_failed;
578 }
579 memset(adapter->XmtRingZeroIndex, 0, sizeof(u32));
580
581 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlcResS",
582 adapter, SXG_MAX_ENTRIES, 0, 0);
583
584 DBG_ERROR("%s EXIT\n", __FUNCTION__);
585 return (STATUS_SUCCESS);
586}
587
588/*
589 * sxg_config_pci -
590 *
591 * Set up PCI Configuration space
592 *
593 * Arguments -
594 * pcidev - A pointer to our adapter structure
595 *
596 */
597static void sxg_config_pci(struct pci_dev *pcidev)
598{
599 u16 pci_command;
600 u16 new_command;
601
602 pci_read_config_word(pcidev, PCI_COMMAND, &pci_command);
603 DBG_ERROR("sxg: %s PCI command[%4.4x]\n", __FUNCTION__, pci_command);
604 // Set the command register
605 new_command = pci_command | (PCI_COMMAND_MEMORY | // Memory Space Enable
606 PCI_COMMAND_MASTER | // Bus master enable
607 PCI_COMMAND_INVALIDATE | // Memory write and invalidate
608 PCI_COMMAND_PARITY | // Parity error response
609 PCI_COMMAND_SERR | // System ERR
610 PCI_COMMAND_FAST_BACK); // Fast back-to-back
611 if (pci_command != new_command) {
612 DBG_ERROR("%s -- Updating PCI COMMAND register %4.4x->%4.4x.\n",
613 __FUNCTION__, pci_command, new_command);
614 pci_write_config_word(pcidev, PCI_COMMAND, new_command);
615 }
616}
617
618static int sxg_entry_probe(struct pci_dev *pcidev,
619 const struct pci_device_id *pci_tbl_entry)
620{
621 static int did_version = 0;
622 int err;
623 struct net_device *netdev;
624 p_adapter_t adapter;
625 void __iomem *memmapped_ioaddr;
626 u32 status = 0;
627 ulong mmio_start = 0;
628 ulong mmio_len = 0;
629
630 DBG_ERROR("sxg: %s 2.6 VERSION ENTER jiffies[%lx] cpu %d\n",
631 __FUNCTION__, jiffies, smp_processor_id());
632
633 // Initialize trace buffer
634#ifdef ATKDBG
635 SxgTraceBuffer = &LSxgTraceBuffer;
636 SXG_TRACE_INIT(SxgTraceBuffer, TRACE_NOISY);
637#endif
638
639 sxg_global.dynamic_intagg = dynamic_intagg;
640
641 err = pci_enable_device(pcidev);
642
643 DBG_ERROR("Call pci_enable_device(%p) status[%x]\n", pcidev, err);
644 if (err) {
645 return err;
646 }
647
648 if (sxg_debug > 0 && did_version++ == 0) {
649 printk(KERN_INFO "%s\n", sxg_banner);
650 printk(KERN_INFO "%s\n", DRV_VERSION);
651 }
652
653 if (!(err = pci_set_dma_mask(pcidev, DMA_64BIT_MASK))) {
654 DBG_ERROR("pci_set_dma_mask(DMA_64BIT_MASK) successful\n");
655 } else {
656 if ((err = pci_set_dma_mask(pcidev, DMA_32BIT_MASK))) {
657 DBG_ERROR
658 ("No usable DMA configuration, aborting err[%x]\n",
659 err);
660 return err;
661 }
662 DBG_ERROR("pci_set_dma_mask(DMA_32BIT_MASK) successful\n");
663 }
664
665 DBG_ERROR("Call pci_request_regions\n");
666
667 err = pci_request_regions(pcidev, DRV_NAME);
668 if (err) {
669 DBG_ERROR("pci_request_regions FAILED err[%x]\n", err);
670 return err;
671 }
672
673 DBG_ERROR("call pci_set_master\n");
674 pci_set_master(pcidev);
675
676 DBG_ERROR("call alloc_etherdev\n");
677 netdev = alloc_etherdev(sizeof(adapter_t));
678 if (!netdev) {
679 err = -ENOMEM;
680 goto err_out_exit_sxg_probe;
681 }
682 DBG_ERROR("alloc_etherdev for slic netdev[%p]\n", netdev);
683
684 SET_NETDEV_DEV(netdev, &pcidev->dev);
685
686 pci_set_drvdata(pcidev, netdev);
687 adapter = netdev_priv(netdev);
688 adapter->netdev = netdev;
689 adapter->pcidev = pcidev;
690
691 mmio_start = pci_resource_start(pcidev, 0);
692 mmio_len = pci_resource_len(pcidev, 0);
693
694 DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n",
695 mmio_start, mmio_len);
696
697 memmapped_ioaddr = ioremap(mmio_start, mmio_len);
698 DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __FUNCTION__, memmapped_ioaddr);
699 if (!memmapped_ioaddr) {
700 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
701 __FUNCTION__, mmio_len, mmio_start);
702 goto err_out_free_mmio_region;
703 }
704
705 DBG_ERROR("sxg: %s found Alacritech SXG PCI, MMIO at %p, start[%lx] len[%lx], IRQ %d.\n",
706 __func__, memmapped_ioaddr, mmio_start, mmio_len, pcidev->irq);
707
708 adapter->HwRegs = (void *) memmapped_ioaddr;
709 adapter->base_addr = memmapped_ioaddr;
710
711 mmio_start = pci_resource_start(pcidev, 2);
712 mmio_len = pci_resource_len(pcidev, 2);
713
714 DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n",
715 mmio_start, mmio_len);
716
717 memmapped_ioaddr = ioremap(mmio_start, mmio_len);
718 DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__, memmapped_ioaddr);
719 if (!memmapped_ioaddr) {
720 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
721 __FUNCTION__, mmio_len, mmio_start);
722 goto err_out_free_mmio_region;
723 }
724
725 DBG_ERROR("sxg: %s found Alacritech SXG PCI, MMIO at %p, "
726 "start[%lx] len[%lx], IRQ %d.\n", __func__,
727 memmapped_ioaddr, mmio_start, mmio_len, pcidev->irq);
728
729 adapter->UcodeRegs = (void *)memmapped_ioaddr;
730
731 adapter->State = SXG_STATE_INITIALIZING;
732 // Maintain a list of all adapters anchored by
733 // the global SxgDriver structure.
734 adapter->Next = SxgDriver.Adapters;
735 SxgDriver.Adapters = adapter;
736 adapter->AdapterID = ++SxgDriver.AdapterID;
737
738 // Initialize CRC table used to determine multicast hash
739 sxg_mcast_init_crc32();
740
741 adapter->JumboEnabled = FALSE;
742 adapter->RssEnabled = FALSE;
743 if (adapter->JumboEnabled) {
744 adapter->FrameSize = JUMBOMAXFRAME;
745 adapter->ReceiveBufferSize = SXG_RCV_JUMBO_BUFFER_SIZE;
746 } else {
747 adapter->FrameSize = ETHERMAXFRAME;
748 adapter->ReceiveBufferSize = SXG_RCV_DATA_BUFFER_SIZE;
749 }
750
751// status = SXG_READ_EEPROM(adapter);
752// if (!status) {
753// goto sxg_init_bad;
754// }
755
756 DBG_ERROR("sxg: %s ENTER sxg_config_pci\n", __FUNCTION__);
757 sxg_config_pci(pcidev);
758 DBG_ERROR("sxg: %s EXIT sxg_config_pci\n", __FUNCTION__);
759
760 DBG_ERROR("sxg: %s ENTER sxg_init_driver\n", __FUNCTION__);
761 sxg_init_driver();
762 DBG_ERROR("sxg: %s EXIT sxg_init_driver\n", __FUNCTION__);
763
764 adapter->vendid = pci_tbl_entry->vendor;
765 adapter->devid = pci_tbl_entry->device;
766 adapter->subsysid = pci_tbl_entry->subdevice;
767 adapter->busnumber = pcidev->bus->number;
768 adapter->slotnumber = ((pcidev->devfn >> 3) & 0x1F);
769 adapter->functionnumber = (pcidev->devfn & 0x7);
770 adapter->memorylength = pci_resource_len(pcidev, 0);
771 adapter->irq = pcidev->irq;
772 adapter->next_netdevice = head_netdevice;
773 head_netdevice = netdev;
774// adapter->chipid = chip_idx;
775 adapter->port = 0; //adapter->functionnumber;
776 adapter->cardindex = adapter->port;
777
778 // Allocate memory and other resources
779 DBG_ERROR("sxg: %s ENTER sxg_allocate_resources\n", __FUNCTION__);
780 status = sxg_allocate_resources(adapter);
781 DBG_ERROR("sxg: %s EXIT sxg_allocate_resources status %x\n",
782 __FUNCTION__, status);
783 if (status != STATUS_SUCCESS) {
784 goto err_out_unmap;
785 }
786
787 DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __FUNCTION__);
788 if (sxg_download_microcode(adapter, SXG_UCODE_SAHARA)) {
789 DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n",
790 __FUNCTION__);
791 sxg_adapter_set_hwaddr(adapter);
792 } else {
793 adapter->state = ADAPT_FAIL;
794 adapter->linkstate = LINK_DOWN;
795 DBG_ERROR("sxg_download_microcode FAILED status[%x]\n", status);
796 }
797
798 netdev->base_addr = (unsigned long)adapter->base_addr;
799 netdev->irq = adapter->irq;
800 netdev->open = sxg_entry_open;
801 netdev->stop = sxg_entry_halt;
802 netdev->hard_start_xmit = sxg_send_packets;
803 netdev->do_ioctl = sxg_ioctl;
804#if XXXTODO
805 netdev->set_mac_address = sxg_mac_set_address;
806#if SLIC_GET_STATS_ENABLED
807 netdev->get_stats = sxg_get_stats;
808#endif
809 netdev->set_multicast_list = sxg_mcast_set_list;
810#endif
811
812 strcpy(netdev->name, "eth%d");
813// strcpy(netdev->name, pci_name(pcidev));
814 if ((err = register_netdev(netdev))) {
815 DBG_ERROR("Cannot register net device, aborting. %s\n",
816 netdev->name);
817 goto err_out_unmap;
818 }
819
820 DBG_ERROR
821 ("sxg: %s addr 0x%lx, irq %d, MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
822 netdev->name, netdev->base_addr, pcidev->irq, netdev->dev_addr[0],
823 netdev->dev_addr[1], netdev->dev_addr[2], netdev->dev_addr[3],
824 netdev->dev_addr[4], netdev->dev_addr[5]);
825
826//sxg_init_bad:
827 ASSERT(status == FALSE);
828// sxg_free_adapter(adapter);
829
830 DBG_ERROR("sxg: %s EXIT status[%x] jiffies[%lx] cpu %d\n", __FUNCTION__,
831 status, jiffies, smp_processor_id());
832 return status;
833
834 err_out_unmap:
835 iounmap((void *)memmapped_ioaddr);
836
837 err_out_free_mmio_region:
838 release_mem_region(mmio_start, mmio_len);
839
840 err_out_exit_sxg_probe:
841
842 DBG_ERROR("%s EXIT jiffies[%lx] cpu %d\n", __FUNCTION__, jiffies,
843 smp_processor_id());
844
845 return -ENODEV;
846}
847
848
849/***********************************************************************
850 * LINE BASE Interrupt routines..
851 ***********************************************************************/
852/*
853 *
854 * sxg_disable_interrupt
855 *
856 * DisableInterrupt Handler
857 *
858 * Arguments:
859 *
860 * adapter: Our adapter structure
861 *
862 * Return Value:
863 * None.
864 */
865static void sxg_disable_interrupt(p_adapter_t adapter)
866{
867 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DisIntr",
868 adapter, adapter->InterruptsEnabled, 0, 0);
869 // For now, RSS is disabled with line based interrupts
870 ASSERT(adapter->RssEnabled == FALSE);
871 ASSERT(adapter->MsiEnabled == FALSE);
872 //
873 // Turn off interrupts by writing to the icr register.
874 //
875 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_DISABLE), TRUE);
876
877 adapter->InterruptsEnabled = 0;
878
879 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDisIntr",
880 adapter, adapter->InterruptsEnabled, 0, 0);
881}
882
883/*
884 *
885 * sxg_enable_interrupt
886 *
887 * EnableInterrupt Handler
888 *
889 * Arguments:
890 *
891 * adapter: Our adapter structure
892 *
893 * Return Value:
894 * None.
895 */
896static void sxg_enable_interrupt(p_adapter_t adapter)
897{
898 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "EnIntr",
899 adapter, adapter->InterruptsEnabled, 0, 0);
900 // For now, RSS is disabled with line based interrupts
901 ASSERT(adapter->RssEnabled == FALSE);
902 ASSERT(adapter->MsiEnabled == FALSE);
903 //
904 // Turn on interrupts by writing to the icr register.
905 //
906 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_ENABLE), TRUE);
907
908 adapter->InterruptsEnabled = 1;
909
910 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XEnIntr",
911 adapter, 0, 0, 0);
912}
913
914/*
915 *
916 * sxg_isr - Process an line-based interrupt
917 *
918 * Arguments:
919 * Context - Our adapter structure
920 * QueueDefault - Output parameter to queue to default CPU
921 * TargetCpus - Output bitmap to schedule DPC's
922 *
923 * Return Value:
924 * TRUE if our interrupt
925 */
926static irqreturn_t sxg_isr(int irq, void *dev_id)
927{
928 p_net_device dev = (p_net_device) dev_id;
929 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
930// u32 CpuMask = 0, i;
931
932 adapter->Stats.NumInts++;
933 if (adapter->Isr[0] == 0) {
934 // The SLIC driver used to experience a number of spurious interrupts
935 // due to the delay associated with the masking of the interrupt
936 // (we'd bounce back in here). If we see that again with Sahara,
937 // add a READ_REG of the Icr register after the WRITE_REG below.
938 adapter->Stats.FalseInts++;
939 return IRQ_NONE;
940 }
941 //
942 // Move the Isr contents and clear the value in
943 // shared memory, and mask interrupts
944 //
945 adapter->IsrCopy[0] = adapter->Isr[0];
946 adapter->Isr[0] = 0;
947 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_MASK), TRUE);
948// ASSERT(adapter->IsrDpcsPending == 0);
949#if XXXTODO // RSS Stuff
950 // If RSS is enabled and the ISR specifies
951 // SXG_ISR_EVENT, then schedule DPC's
952 // based on event queues.
953 if (adapter->RssEnabled && (adapter->IsrCopy[0] & SXG_ISR_EVENT)) {
954 for (i = 0;
955 i < adapter->RssSystemInfo->ProcessorInfo.RssCpuCount;
956 i++) {
957 PSXG_EVENT_RING EventRing = &adapter->EventRings[i];
958 PSXG_EVENT Event =
959 &EventRing->Ring[adapter->NextEvent[i]];
960 unsigned char Cpu = adapter->RssSystemInfo->RssIdToCpu[i];
961 if (Event->Status & EVENT_STATUS_VALID) {
962 adapter->IsrDpcsPending++;
963 CpuMask |= (1 << Cpu);
964 }
965 }
966 }
967 // Now, either schedule the CPUs specified by the CpuMask,
968 // or queue default
969 if (CpuMask) {
970 *QueueDefault = FALSE;
971 } else {
972 adapter->IsrDpcsPending = 1;
973 *QueueDefault = TRUE;
974 }
975 *TargetCpus = CpuMask;
976#endif
977 //
978 // There are no DPCs in Linux, so call the handler now
979 //
980 sxg_handle_interrupt(adapter);
981
982 return IRQ_HANDLED;
983}
984
985static void sxg_handle_interrupt(p_adapter_t adapter)
986{
987// unsigned char RssId = 0;
988 u32 NewIsr;
989
990 if (adapter->Stats.RcvNoBuffer < 5) {
991 DBG_ERROR("Enter sxg_handle_interrupt ISR[%x]\n",
992 adapter->IsrCopy[0]);
993 }
994 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "HndlIntr",
995 adapter, adapter->IsrCopy[0], 0, 0);
996 // For now, RSS is disabled with line based interrupts
997 ASSERT(adapter->RssEnabled == FALSE);
998 ASSERT(adapter->MsiEnabled == FALSE);
999 ASSERT(adapter->IsrCopy[0]);
1000/////////////////////////////
1001
1002 // Always process the event queue.
1003 sxg_process_event_queue(adapter,
1004 (adapter->RssEnabled ? /*RssId */ 0 : 0));
1005
1006#if XXXTODO // RSS stuff
1007 if (--adapter->IsrDpcsPending) {
1008 // We're done.
1009 ASSERT(adapter->RssEnabled);
1010 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DPCsPend",
1011 adapter, 0, 0, 0);
1012 return;
1013 }
1014#endif
1015 //
1016 // Last (or only) DPC processes the ISR and clears the interrupt.
1017 //
1018 NewIsr = sxg_process_isr(adapter, 0);
1019 //
1020 // Reenable interrupts
1021 //
1022 adapter->IsrCopy[0] = 0;
1023 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ClearIsr",
1024 adapter, NewIsr, 0, 0);
1025
1026 if (adapter->Stats.RcvNoBuffer < 5) {
1027 DBG_ERROR
1028 ("Exit sxg_handle_interrupt2 after enabling interrupt\n");
1029 }
1030
1031 WRITE_REG(adapter->UcodeRegs[0].Isr, NewIsr, TRUE);
1032
1033 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XHndlInt",
1034 adapter, 0, 0, 0);
1035}
1036
1037/*
1038 *
1039 * sxg_process_isr - Process an interrupt. Called from the line-based and
1040 * message based interrupt DPC routines
1041 *
1042 * Arguments:
1043 * adapter - Our adapter structure
1044 * Queue - The ISR that needs processing
1045 *
1046 * Return Value:
1047 * None
1048 */
1049static int sxg_process_isr(p_adapter_t adapter, u32 MessageId)
1050{
1051 u32 Isr = adapter->IsrCopy[MessageId];
1052 u32 NewIsr = 0;
1053
1054 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ProcIsr",
1055 adapter, Isr, 0, 0);
1056
1057 // Error
1058 if (Isr & SXG_ISR_ERR) {
1059 if (Isr & SXG_ISR_PDQF) {
1060 adapter->Stats.PdqFull++;
1061 DBG_ERROR("%s: SXG_ISR_ERR PDQF!!\n", __FUNCTION__);
1062 }
1063 // No host buffer
1064 if (Isr & SXG_ISR_RMISS) {
1065 // There is a bunch of code in the SLIC driver which
1066 // attempts to process more receive events per DPC
1067 // if we start to fall behind. We'll probably
1068 // need to do something similar here, but hold
1069 // off for now. I don't want to make the code more
1070 // complicated than strictly needed.
1071 adapter->Stats.RcvNoBuffer++;
1072 if (adapter->Stats.RcvNoBuffer < 5) {
1073 DBG_ERROR("%s: SXG_ISR_ERR RMISS!!\n",
1074 __FUNCTION__);
1075 }
1076 }
1077 // Card crash
1078 if (Isr & SXG_ISR_DEAD) {
1079 // Set aside the crash info and set the adapter state to RESET
1080 adapter->CrashCpu =
1081 (unsigned char) ((Isr & SXG_ISR_CPU) >> SXG_ISR_CPU_SHIFT);
1082 adapter->CrashLocation = (ushort) (Isr & SXG_ISR_CRASH);
1083 adapter->Dead = TRUE;
1084 DBG_ERROR("%s: ISR_DEAD %x, CPU: %d\n", __FUNCTION__,
1085 adapter->CrashLocation, adapter->CrashCpu);
1086 }
1087 // Event ring full
1088 if (Isr & SXG_ISR_ERFULL) {
1089 // Same issue as RMISS, really. This means the
1090 // host is falling behind the card. Need to increase
1091 // event ring size, process more events per interrupt,
1092 // and/or reduce/remove interrupt aggregation.
1093 adapter->Stats.EventRingFull++;
1094 DBG_ERROR("%s: SXG_ISR_ERR EVENT RING FULL!!\n",
1095 __FUNCTION__);
1096 }
1097 // Transmit drop - no DRAM buffers or XMT error
1098 if (Isr & SXG_ISR_XDROP) {
1099 adapter->Stats.XmtDrops++;
1100 adapter->Stats.XmtErrors++;
1101 DBG_ERROR("%s: SXG_ISR_ERR XDROP!!\n", __FUNCTION__);
1102 }
1103 }
1104 // Slowpath send completions
1105 if (Isr & SXG_ISR_SPSEND) {
1106 sxg_complete_slow_send(adapter);
1107 }
1108 // Dump
1109 if (Isr & SXG_ISR_UPC) {
1110 ASSERT(adapter->DumpCmdRunning); // Maybe change when debug is added..
1111 adapter->DumpCmdRunning = FALSE;
1112 }
1113 // Link event
1114 if (Isr & SXG_ISR_LINK) {
1115 sxg_link_event(adapter);
1116 }
1117 // Debug - breakpoint hit
1118 if (Isr & SXG_ISR_BREAK) {
1119 // At the moment AGDB isn't written to support interactive
1120 // debug sessions. When it is, this interrupt will be used
1121 // to signal AGDB that it has hit a breakpoint. For now, ASSERT.
1122 ASSERT(0);
1123 }
1124 // Heartbeat response
1125 if (Isr & SXG_ISR_PING) {
1126 adapter->PingOutstanding = FALSE;
1127 }
1128 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XProcIsr",
1129 adapter, Isr, NewIsr, 0);
1130
1131 return (NewIsr);
1132}
1133
1134/*
1135 *
1136 * sxg_process_event_queue - Process our event queue
1137 *
1138 * Arguments:
1139 * - adapter - Adapter structure
1140 * - RssId - The event queue requiring processing
1141 *
1142 * Return Value:
1143 * None.
1144 */
1145static u32 sxg_process_event_queue(p_adapter_t adapter, u32 RssId)
1146{
1147 PSXG_EVENT_RING EventRing = &adapter->EventRings[RssId];
1148 PSXG_EVENT Event = &EventRing->Ring[adapter->NextEvent[RssId]];
1149 u32 EventsProcessed = 0, Batches = 0;
1150 u32 num_skbs = 0;
1151 struct sk_buff *skb;
1152#ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1153 struct sk_buff *prev_skb = NULL;
1154 struct sk_buff *IndicationList[SXG_RCV_ARRAYSIZE];
1155 u32 Index;
1156 PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr;
1157#endif
1158 u32 ReturnStatus = 0;
1159
1160 ASSERT((adapter->State == SXG_STATE_RUNNING) ||
1161 (adapter->State == SXG_STATE_PAUSING) ||
1162 (adapter->State == SXG_STATE_PAUSED) ||
1163 (adapter->State == SXG_STATE_HALTING));
1164 // We may still have unprocessed events on the queue if
1165 // the card crashed. Don't process them.
1166 if (adapter->Dead) {
1167 return (0);
1168 }
1169 // In theory there should only be a single processor that
1170 // accesses this queue, and only at interrupt-DPC time. So
1171 // we shouldn't need a lock for any of this.
1172 while (Event->Status & EVENT_STATUS_VALID) {
1173 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "Event",
1174 Event, Event->Code, Event->Status,
1175 adapter->NextEvent);
1176 switch (Event->Code) {
1177 case EVENT_CODE_BUFFERS:
1178 ASSERT(!(Event->CommandIndex & 0xFF00)); // SXG_RING_INFO Head & Tail == unsigned char
1179 //
1180 sxg_complete_descriptor_blocks(adapter,
1181 Event->CommandIndex);
1182 //
1183 break;
1184 case EVENT_CODE_SLOWRCV:
1185 --adapter->RcvBuffersOnCard;
1186 if ((skb = sxg_slow_receive(adapter, Event))) {
1187 u32 rx_bytes;
1188#ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1189 // Add it to our indication list
1190 SXG_ADD_RCV_PACKET(adapter, skb, prev_skb,
1191 IndicationList, num_skbs);
1192 // In Linux, we just pass up each skb to the protocol above at this point,
1193 // there is no capability of an indication list.
1194#else
1195// CHECK skb_pull(skb, INIC_RCVBUF_HEADSIZE);
1196 rx_bytes = Event->Length; // (rcvbuf->length & IRHDDR_FLEN_MSK);
1197 skb_put(skb, rx_bytes);
1198 adapter->stats.rx_packets++;
1199 adapter->stats.rx_bytes += rx_bytes;
1200#if SXG_OFFLOAD_IP_CHECKSUM
1201 skb->ip_summed = CHECKSUM_UNNECESSARY;
1202#endif
1203 skb->dev = adapter->netdev;
1204 skb->protocol = eth_type_trans(skb, skb->dev);
1205 netif_rx(skb);
1206#endif
1207 }
1208 break;
1209 default:
1210 DBG_ERROR("%s: ERROR Invalid EventCode %d\n",
1211 __FUNCTION__, Event->Code);
1212// ASSERT(0);
1213 }
1214 // See if we need to restock card receive buffers.
1215 // There are two things to note here:
1216 // First - This test is not SMP safe. The
1217 // adapter->BuffersOnCard field is protected via atomic interlocked calls, but
1218 // we do not protect it with respect to these tests. The only way to do that
1219 // is with a lock, and I don't want to grab a lock every time we adjust the
1220 // BuffersOnCard count. Instead, we allow the buffer replenishment to be off
1221 // once in a while. The worst that can happen is the card is given one
1222 // more-or-less descriptor block than the arbitrary value we've chosen.
1223 // No big deal
1224 // In short DO NOT ADD A LOCK HERE, OR WHERE RcvBuffersOnCard is adjusted.
1225 // Second - We expect this test to rarely evaluate to true. We attempt to
1226 // refill descriptor blocks as they are returned to us
1227 // (sxg_complete_descriptor_blocks), so The only time this should evaluate
1228 // to true is when sxg_complete_descriptor_blocks failed to allocate
1229 // receive buffers.
1230 if (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) {
1231 sxg_stock_rcv_buffers(adapter);
1232 }
1233 // It's more efficient to just set this to zero.
1234 // But clearing the top bit saves potential debug info...
1235 Event->Status &= ~EVENT_STATUS_VALID;
1236 // Advanct to the next event
1237 SXG_ADVANCE_INDEX(adapter->NextEvent[RssId], EVENT_RING_SIZE);
1238 Event = &EventRing->Ring[adapter->NextEvent[RssId]];
1239 EventsProcessed++;
1240 if (EventsProcessed == EVENT_RING_BATCH) {
1241 // Release a batch of events back to the card
1242 WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
1243 EVENT_RING_BATCH, FALSE);
1244 EventsProcessed = 0;
1245 // If we've processed our batch limit, break out of the
1246 // loop and return SXG_ISR_EVENT to arrange for us to
1247 // be called again
1248 if (Batches++ == EVENT_BATCH_LIMIT) {
1249 SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
1250 TRACE_NOISY, "EvtLimit", Batches,
1251 adapter->NextEvent, 0, 0);
1252 ReturnStatus = SXG_ISR_EVENT;
1253 break;
1254 }
1255 }
1256 }
1257#ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1258 //
1259 // Indicate any received dumb-nic frames
1260 //
1261 SXG_INDICATE_PACKETS(adapter, IndicationList, num_skbs);
1262#endif
1263 //
1264 // Release events back to the card.
1265 //
1266 if (EventsProcessed) {
1267 WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
1268 EventsProcessed, FALSE);
1269 }
1270 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XPrcEvnt",
1271 Batches, EventsProcessed, adapter->NextEvent, num_skbs);
1272
1273 return (ReturnStatus);
1274}
1275
1276/*
1277 * sxg_complete_slow_send - Complete slowpath or dumb-nic sends
1278 *
1279 * Arguments -
1280 * adapter - A pointer to our adapter structure
1281
1282 * Return
1283 * None
1284 */
1285static void sxg_complete_slow_send(p_adapter_t adapter)
1286{
1287 PSXG_XMT_RING XmtRing = &adapter->XmtRings[0];
1288 PSXG_RING_INFO XmtRingInfo = &adapter->XmtRingZeroInfo;
1289 u32 * ContextType;
1290 PSXG_CMD XmtCmd;
1291
1292 // NOTE - This lock is dropped and regrabbed in this loop.
1293 // This means two different processors can both be running
1294 // through this loop. Be *very* careful.
1295 spin_lock(&adapter->XmtZeroLock);
1296 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnds",
1297 adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
1298
1299 while (XmtRingInfo->Tail != *adapter->XmtRingZeroIndex) {
1300 // Locate the current Cmd (ring descriptor entry), and
1301 // associated SGL, and advance the tail
1302 SXG_RETURN_CMD(XmtRing, XmtRingInfo, XmtCmd, ContextType);
1303 ASSERT(ContextType);
1304 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd",
1305 XmtRingInfo->Head, XmtRingInfo->Tail, XmtCmd, 0);
1306 // Clear the SGL field.
1307 XmtCmd->Sgl = 0;
1308
1309 switch (*ContextType) {
1310 case SXG_SGL_DUMB:
1311 {
1312 struct sk_buff *skb;
1313 // Dumb-nic send. Command context is the dumb-nic SGL
1314 skb = (struct sk_buff *)ContextType;
1315 // Complete the send
1316 SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
1317 TRACE_IMPORTANT, "DmSndCmp", skb, 0,
1318 0, 0);
1319 ASSERT(adapter->Stats.XmtQLen);
1320 adapter->Stats.XmtQLen--; // within XmtZeroLock
1321 adapter->Stats.XmtOk++;
1322 // Now drop the lock and complete the send back to
1323 // Microsoft. We need to drop the lock because
1324 // Microsoft can come back with a chimney send, which
1325 // results in a double trip in SxgTcpOuput
1326 spin_unlock(&adapter->XmtZeroLock);
1327 SXG_COMPLETE_DUMB_SEND(adapter, skb);
1328 // and reacquire..
1329 spin_lock(&adapter->XmtZeroLock);
1330 }
1331 break;
1332 default:
1333 ASSERT(0);
1334 }
1335 }
1336 spin_unlock(&adapter->XmtZeroLock);
1337 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd",
1338 adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
1339}
1340
1341/*
1342 * sxg_slow_receive
1343 *
1344 * Arguments -
1345 * adapter - A pointer to our adapter structure
1346 * Event - Receive event
1347 *
1348 * Return
1349 * skb
1350 */
1351static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event)
1352{
1353 PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr;
1354 struct sk_buff *Packet;
1355
1356 RcvDataBufferHdr = (PSXG_RCV_DATA_BUFFER_HDR) Event->HostHandle;
1357 ASSERT(RcvDataBufferHdr);
1358 ASSERT(RcvDataBufferHdr->State == SXG_BUFFER_ONCARD);
1359 ASSERT(SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr) ==
1360 RcvDataBufferHdr->VirtualAddress);
1361 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "SlowRcv", Event,
1362 RcvDataBufferHdr, RcvDataBufferHdr->State,
1363 RcvDataBufferHdr->VirtualAddress);
1364 // Drop rcv frames in non-running state
1365 switch (adapter->State) {
1366 case SXG_STATE_RUNNING:
1367 break;
1368 case SXG_STATE_PAUSING:
1369 case SXG_STATE_PAUSED:
1370 case SXG_STATE_HALTING:
1371 goto drop;
1372 default:
1373 ASSERT(0);
1374 goto drop;
1375 }
1376
1377 // Change buffer state to UPSTREAM
1378 RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM;
1379 if (Event->Status & EVENT_STATUS_RCVERR) {
1380 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvError",
1381 Event, Event->Status, Event->HostHandle, 0);
1382 // XXXTODO - Remove this print later
1383 DBG_ERROR("SXG: Receive error %x\n",
1384 *(u32 *)
1385 SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr));
1386 sxg_process_rcv_error(adapter,
1387 *(u32 *)
1388 SXG_RECEIVE_DATA_LOCATION
1389 (RcvDataBufferHdr));
1390 goto drop;
1391 }
1392#if XXXTODO // VLAN stuff
1393 // If there's a VLAN tag, extract it and validate it
1394 if (((p_ether_header) (SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr)))->
1395 EtherType == ETHERTYPE_VLAN) {
1396 if (SxgExtractVlanHeader(adapter, RcvDataBufferHdr, Event) !=
1397 STATUS_SUCCESS) {
1398 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY,
1399 "BadVlan", Event,
1400 SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
1401 Event->Length, 0);
1402 goto drop;
1403 }
1404 }
1405#endif
1406 //
1407 // Dumb-nic frame. See if it passes our mac filter and update stats
1408 //
1409 if (!sxg_mac_filter(adapter,
1410 (p_ether_header)
1411 SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
1412 Event->Length)) {
1413 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvFiltr",
1414 Event, SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
1415 Event->Length, 0);
1416 goto drop;
1417 }
1418
1419 Packet = RcvDataBufferHdr->SxgDumbRcvPacket;
1420
1421 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumbRcv",
1422 RcvDataBufferHdr, Packet, Event->Length, 0);
1423 //
1424 // Lastly adjust the receive packet length.
1425 //
1426 SXG_ADJUST_RCV_PACKET(Packet, RcvDataBufferHdr, Event);
1427
1428 return (Packet);
1429
1430 drop:
1431 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DropRcv",
1432 RcvDataBufferHdr, Event->Length, 0, 0);
1433 adapter->Stats.RcvDiscards++;
1434 spin_lock(&adapter->RcvQLock);
1435 SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
1436 spin_unlock(&adapter->RcvQLock);
1437 return (NULL);
1438}
1439
1440/*
1441 * sxg_process_rcv_error - process receive error and update
1442 * stats
1443 *
1444 * Arguments:
1445 * adapter - Adapter structure
1446 * ErrorStatus - 4-byte receive error status
1447 *
1448 * Return Value:
1449 * None
1450 */
1451static void sxg_process_rcv_error(p_adapter_t adapter, u32 ErrorStatus)
1452{
1453 u32 Error;
1454
1455 adapter->Stats.RcvErrors++;
1456
1457 if (ErrorStatus & SXG_RCV_STATUS_TRANSPORT_ERROR) {
1458 Error = ErrorStatus & SXG_RCV_STATUS_TRANSPORT_MASK;
1459 switch (Error) {
1460 case SXG_RCV_STATUS_TRANSPORT_CSUM:
1461 adapter->Stats.TransportCsum++;
1462 break;
1463 case SXG_RCV_STATUS_TRANSPORT_UFLOW:
1464 adapter->Stats.TransportUflow++;
1465 break;
1466 case SXG_RCV_STATUS_TRANSPORT_HDRLEN:
1467 adapter->Stats.TransportHdrLen++;
1468 break;
1469 }
1470 }
1471 if (ErrorStatus & SXG_RCV_STATUS_NETWORK_ERROR) {
1472 Error = ErrorStatus & SXG_RCV_STATUS_NETWORK_MASK;
1473 switch (Error) {
1474 case SXG_RCV_STATUS_NETWORK_CSUM:
1475 adapter->Stats.NetworkCsum++;
1476 break;
1477 case SXG_RCV_STATUS_NETWORK_UFLOW:
1478 adapter->Stats.NetworkUflow++;
1479 break;
1480 case SXG_RCV_STATUS_NETWORK_HDRLEN:
1481 adapter->Stats.NetworkHdrLen++;
1482 break;
1483 }
1484 }
1485 if (ErrorStatus & SXG_RCV_STATUS_PARITY) {
1486 adapter->Stats.Parity++;
1487 }
1488 if (ErrorStatus & SXG_RCV_STATUS_LINK_ERROR) {
1489 Error = ErrorStatus & SXG_RCV_STATUS_LINK_MASK;
1490 switch (Error) {
1491 case SXG_RCV_STATUS_LINK_PARITY:
1492 adapter->Stats.LinkParity++;
1493 break;
1494 case SXG_RCV_STATUS_LINK_EARLY:
1495 adapter->Stats.LinkEarly++;
1496 break;
1497 case SXG_RCV_STATUS_LINK_BUFOFLOW:
1498 adapter->Stats.LinkBufOflow++;
1499 break;
1500 case SXG_RCV_STATUS_LINK_CODE:
1501 adapter->Stats.LinkCode++;
1502 break;
1503 case SXG_RCV_STATUS_LINK_DRIBBLE:
1504 adapter->Stats.LinkDribble++;
1505 break;
1506 case SXG_RCV_STATUS_LINK_CRC:
1507 adapter->Stats.LinkCrc++;
1508 break;
1509 case SXG_RCV_STATUS_LINK_OFLOW:
1510 adapter->Stats.LinkOflow++;
1511 break;
1512 case SXG_RCV_STATUS_LINK_UFLOW:
1513 adapter->Stats.LinkUflow++;
1514 break;
1515 }
1516 }
1517}
1518
1519/*
1520 * sxg_mac_filter
1521 *
1522 * Arguments:
1523 * adapter - Adapter structure
1524 * pether - Ethernet header
1525 * length - Frame length
1526 *
1527 * Return Value:
1528 * TRUE if the frame is to be allowed
1529 */
1530static bool sxg_mac_filter(p_adapter_t adapter, p_ether_header EtherHdr, ushort length)
1531{
1532 bool EqualAddr;
1533
1534 if (SXG_MULTICAST_PACKET(EtherHdr)) {
1535 if (SXG_BROADCAST_PACKET(EtherHdr)) {
1536 // broadcast
1537 if (adapter->MacFilter & MAC_BCAST) {
1538 adapter->Stats.DumbRcvBcastPkts++;
1539 adapter->Stats.DumbRcvBcastBytes += length;
1540 adapter->Stats.DumbRcvPkts++;
1541 adapter->Stats.DumbRcvBytes += length;
1542 return (TRUE);
1543 }
1544 } else {
1545 // multicast
1546 if (adapter->MacFilter & MAC_ALLMCAST) {
1547 adapter->Stats.DumbRcvMcastPkts++;
1548 adapter->Stats.DumbRcvMcastBytes += length;
1549 adapter->Stats.DumbRcvPkts++;
1550 adapter->Stats.DumbRcvBytes += length;
1551 return (TRUE);
1552 }
1553 if (adapter->MacFilter & MAC_MCAST) {
1554 PSXG_MULTICAST_ADDRESS MulticastAddrs =
1555 adapter->MulticastAddrs;
1556 while (MulticastAddrs) {
1557 ETHER_EQ_ADDR(MulticastAddrs->Address,
1558 EtherHdr->ether_dhost,
1559 EqualAddr);
1560 if (EqualAddr) {
1561 adapter->Stats.
1562 DumbRcvMcastPkts++;
1563 adapter->Stats.
1564 DumbRcvMcastBytes += length;
1565 adapter->Stats.DumbRcvPkts++;
1566 adapter->Stats.DumbRcvBytes +=
1567 length;
1568 return (TRUE);
1569 }
1570 MulticastAddrs = MulticastAddrs->Next;
1571 }
1572 }
1573 }
1574 } else if (adapter->MacFilter & MAC_DIRECTED) {
1575 // Not broadcast or multicast. Must be directed at us or
1576 // the card is in promiscuous mode. Either way, consider it
1577 // ours if MAC_DIRECTED is set
1578 adapter->Stats.DumbRcvUcastPkts++;
1579 adapter->Stats.DumbRcvUcastBytes += length;
1580 adapter->Stats.DumbRcvPkts++;
1581 adapter->Stats.DumbRcvBytes += length;
1582 return (TRUE);
1583 }
1584 if (adapter->MacFilter & MAC_PROMISC) {
1585 // Whatever it is, keep it.
1586 adapter->Stats.DumbRcvPkts++;
1587 adapter->Stats.DumbRcvBytes += length;
1588 return (TRUE);
1589 }
1590 adapter->Stats.RcvDiscards++;
1591 return (FALSE);
1592}
1593
1594static int sxg_register_interrupt(p_adapter_t adapter)
1595{
1596 if (!adapter->intrregistered) {
1597 int retval;
1598
1599 DBG_ERROR
1600 ("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x] %x\n",
1601 __FUNCTION__, adapter, adapter->netdev->irq, NR_IRQS);
1602
1603 spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
1604
1605 retval = request_irq(adapter->netdev->irq,
1606 &sxg_isr,
1607 IRQF_SHARED,
1608 adapter->netdev->name, adapter->netdev);
1609
1610 spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
1611
1612 if (retval) {
1613 DBG_ERROR("sxg: request_irq (%s) FAILED [%x]\n",
1614 adapter->netdev->name, retval);
1615 return (retval);
1616 }
1617 adapter->intrregistered = 1;
1618 adapter->IntRegistered = TRUE;
1619 // Disable RSS with line-based interrupts
1620 adapter->MsiEnabled = FALSE;
1621 adapter->RssEnabled = FALSE;
1622 DBG_ERROR("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x]\n",
1623 __FUNCTION__, adapter, adapter->netdev->irq);
1624 }
1625 return (STATUS_SUCCESS);
1626}
1627
1628static void sxg_deregister_interrupt(p_adapter_t adapter)
1629{
1630 DBG_ERROR("sxg: %s ENTER adapter[%p]\n", __FUNCTION__, adapter);
1631#if XXXTODO
1632 slic_init_cleanup(adapter);
1633#endif
1634 memset(&adapter->stats, 0, sizeof(struct net_device_stats));
1635 adapter->error_interrupts = 0;
1636 adapter->rcv_interrupts = 0;
1637 adapter->xmit_interrupts = 0;
1638 adapter->linkevent_interrupts = 0;
1639 adapter->upr_interrupts = 0;
1640 adapter->num_isrs = 0;
1641 adapter->xmit_completes = 0;
1642 adapter->rcv_broadcasts = 0;
1643 adapter->rcv_multicasts = 0;
1644 adapter->rcv_unicasts = 0;
1645 DBG_ERROR("sxg: %s EXIT\n", __FUNCTION__);
1646}
1647
1648/*
1649 * sxg_if_init
1650 *
1651 * Perform initialization of our slic interface.
1652 *
1653 */
1654static int sxg_if_init(p_adapter_t adapter)
1655{
1656 p_net_device dev = adapter->netdev;
1657 int status = 0;
1658
1659 DBG_ERROR("sxg: %s (%s) ENTER states[%d:%d:%d] flags[%x]\n",
1660 __FUNCTION__, adapter->netdev->name,
1661 adapter->queues_initialized, adapter->state,
1662 adapter->linkstate, dev->flags);
1663
1664 /* adapter should be down at this point */
1665 if (adapter->state != ADAPT_DOWN) {
1666 DBG_ERROR("sxg_if_init adapter->state != ADAPT_DOWN\n");
1667 return (-EIO);
1668 }
1669 ASSERT(adapter->linkstate == LINK_DOWN);
1670
1671 adapter->devflags_prev = dev->flags;
1672 adapter->macopts = MAC_DIRECTED;
1673 if (dev->flags) {
1674 DBG_ERROR("sxg: %s (%s) Set MAC options: ", __FUNCTION__,
1675 adapter->netdev->name);
1676 if (dev->flags & IFF_BROADCAST) {
1677 adapter->macopts |= MAC_BCAST;
1678 DBG_ERROR("BCAST ");
1679 }
1680 if (dev->flags & IFF_PROMISC) {
1681 adapter->macopts |= MAC_PROMISC;
1682 DBG_ERROR("PROMISC ");
1683 }
1684 if (dev->flags & IFF_ALLMULTI) {
1685 adapter->macopts |= MAC_ALLMCAST;
1686 DBG_ERROR("ALL_MCAST ");
1687 }
1688 if (dev->flags & IFF_MULTICAST) {
1689 adapter->macopts |= MAC_MCAST;
1690 DBG_ERROR("MCAST ");
1691 }
1692 DBG_ERROR("\n");
1693 }
1694 status = sxg_register_interrupt(adapter);
1695 if (status != STATUS_SUCCESS) {
1696 DBG_ERROR("sxg_if_init: sxg_register_interrupt FAILED %x\n",
1697 status);
1698 sxg_deregister_interrupt(adapter);
1699 return (status);
1700 }
1701
1702 adapter->state = ADAPT_UP;
1703
1704 /*
1705 * clear any pending events, then enable interrupts
1706 */
1707 DBG_ERROR("sxg: %s ENABLE interrupts(slic)\n", __FUNCTION__);
1708
1709 return (STATUS_SUCCESS);
1710}
1711
1712static int sxg_entry_open(p_net_device dev)
1713{
1714 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
1715 int status;
1716
1717 ASSERT(adapter);
1718 DBG_ERROR("sxg: %s adapter->activated[%d]\n", __FUNCTION__,
1719 adapter->activated);
1720 DBG_ERROR
1721 ("sxg: %s (%s): [jiffies[%lx] cpu %d] dev[%p] adapt[%p] port[%d]\n",
1722 __FUNCTION__, adapter->netdev->name, jiffies, smp_processor_id(),
1723 adapter->netdev, adapter, adapter->port);
1724
1725 netif_stop_queue(adapter->netdev);
1726
1727 spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
1728 if (!adapter->activated) {
1729 sxg_global.num_sxg_ports_active++;
1730 adapter->activated = 1;
1731 }
1732
1733 // Initialize the adapter
1734 DBG_ERROR("sxg: %s ENTER sxg_initialize_adapter\n", __FUNCTION__);
1735 status = sxg_initialize_adapter(adapter);
1736 DBG_ERROR("sxg: %s EXIT sxg_initialize_adapter status[%x]\n",
1737 __FUNCTION__, status);
1738
1739 if (status == STATUS_SUCCESS) {
1740 DBG_ERROR("sxg: %s ENTER sxg_if_init\n", __FUNCTION__);
1741 status = sxg_if_init(adapter);
1742 DBG_ERROR("sxg: %s EXIT sxg_if_init status[%x]\n", __FUNCTION__,
1743 status);
1744 }
1745
1746 if (status != STATUS_SUCCESS) {
1747 if (adapter->activated) {
1748 sxg_global.num_sxg_ports_active--;
1749 adapter->activated = 0;
1750 }
1751 spin_unlock_irqrestore(&sxg_global.driver_lock,
1752 sxg_global.flags);
1753 return (status);
1754 }
1755 DBG_ERROR("sxg: %s ENABLE ALL INTERRUPTS\n", __FUNCTION__);
1756
1757 // Enable interrupts
1758 SXG_ENABLE_ALL_INTERRUPTS(adapter);
1759
1760 DBG_ERROR("sxg: %s EXIT\n", __FUNCTION__);
1761
1762 spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
1763 return STATUS_SUCCESS;
1764}
1765
1766static void __devexit sxg_entry_remove(struct pci_dev *pcidev)
1767{
1768 p_net_device dev = pci_get_drvdata(pcidev);
1769 u32 mmio_start = 0;
1770 unsigned int mmio_len = 0;
1771 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
1772
1773 ASSERT(adapter);
1774 DBG_ERROR("sxg: %s ENTER dev[%p] adapter[%p]\n", __FUNCTION__, dev,
1775 adapter);
1776 sxg_deregister_interrupt(adapter);
1777 sxg_unmap_mmio_space(adapter);
1778 DBG_ERROR("sxg: %s unregister_netdev\n", __FUNCTION__);
1779 unregister_netdev(dev);
1780
1781 mmio_start = pci_resource_start(pcidev, 0);
1782 mmio_len = pci_resource_len(pcidev, 0);
1783
1784 DBG_ERROR("sxg: %s rel_region(0) start[%x] len[%x]\n", __FUNCTION__,
1785 mmio_start, mmio_len);
1786 release_mem_region(mmio_start, mmio_len);
1787
1788 DBG_ERROR("sxg: %s iounmap dev->base_addr[%x]\n", __FUNCTION__,
1789 (unsigned int) dev->base_addr);
1790 iounmap((char *)dev->base_addr);
1791
1792 DBG_ERROR("sxg: %s deallocate device\n", __FUNCTION__);
1793 kfree(dev);
1794 DBG_ERROR("sxg: %s EXIT\n", __FUNCTION__);
1795}
1796
1797static int sxg_entry_halt(p_net_device dev)
1798{
1799 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
1800
1801 spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
1802 DBG_ERROR("sxg: %s (%s) ENTER\n", __FUNCTION__, dev->name);
1803
1804 netif_stop_queue(adapter->netdev);
1805 adapter->state = ADAPT_DOWN;
1806 adapter->linkstate = LINK_DOWN;
1807 adapter->devflags_prev = 0;
1808 DBG_ERROR("sxg: %s (%s) set adapter[%p] state to ADAPT_DOWN(%d)\n",
1809 __FUNCTION__, dev->name, adapter, adapter->state);
1810
1811 DBG_ERROR("sxg: %s (%s) EXIT\n", __FUNCTION__, dev->name);
1812 DBG_ERROR("sxg: %s EXIT\n", __FUNCTION__);
1813 spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
1814 return (STATUS_SUCCESS);
1815}
1816
1817static int sxg_ioctl(p_net_device dev, struct ifreq *rq, int cmd)
1818{
1819 ASSERT(rq);
1820// DBG_ERROR("sxg: %s cmd[%x] rq[%p] dev[%p]\n", __FUNCTION__, cmd, rq, dev);
1821 switch (cmd) {
1822 case SIOCSLICSETINTAGG:
1823 {
1824// p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
1825 u32 data[7];
1826 u32 intagg;
1827
1828 if (copy_from_user(data, rq->ifr_data, 28)) {
1829 DBG_ERROR
1830 ("copy_from_user FAILED getting initial params\n");
1831 return -EFAULT;
1832 }
1833 intagg = data[0];
1834 printk(KERN_EMERG
1835 "%s: set interrupt aggregation to %d\n",
1836 __FUNCTION__, intagg);
1837 return 0;
1838 }
1839
1840 default:
1841// DBG_ERROR("sxg: %s UNSUPPORTED[%x]\n", __FUNCTION__, cmd);
1842 return -EOPNOTSUPP;
1843 }
1844 return 0;
1845}
1846
1847#define NORMAL_ETHFRAME 0
1848
1849/*
1850 *
1851 * sxg_send_packets - Send a skb packet
1852 *
1853 * Arguments:
1854 * skb - The packet to send
1855 * dev - Our linux net device that refs our adapter
1856 *
1857 * Return:
1858 * 0 regardless of outcome XXXTODO refer to e1000 driver
1859 */
1860static int sxg_send_packets(struct sk_buff *skb, p_net_device dev)
1861{
1862 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
1863 u32 status = STATUS_SUCCESS;
1864
1865 DBG_ERROR("sxg: %s ENTER sxg_send_packets skb[%p]\n", __FUNCTION__,
1866 skb);
1867 // Check the adapter state
1868 switch (adapter->State) {
1869 case SXG_STATE_INITIALIZING:
1870 case SXG_STATE_HALTED:
1871 case SXG_STATE_SHUTDOWN:
1872 ASSERT(0); // unexpected
1873 // fall through
1874 case SXG_STATE_RESETTING:
1875 case SXG_STATE_SLEEP:
1876 case SXG_STATE_BOOTDIAG:
1877 case SXG_STATE_DIAG:
1878 case SXG_STATE_HALTING:
1879 status = STATUS_FAILURE;
1880 break;
1881 case SXG_STATE_RUNNING:
1882 if (adapter->LinkState != SXG_LINK_UP) {
1883 status = STATUS_FAILURE;
1884 }
1885 break;
1886 default:
1887 ASSERT(0);
1888 status = STATUS_FAILURE;
1889 }
1890 if (status != STATUS_SUCCESS) {
1891 goto xmit_fail;
1892 }
1893 // send a packet
1894 status = sxg_transmit_packet(adapter, skb);
1895 if (status == STATUS_SUCCESS) {
1896 goto xmit_done;
1897 }
1898
1899 xmit_fail:
1900 // reject & complete all the packets if they cant be sent
1901 if (status != STATUS_SUCCESS) {
1902#if XXXTODO
1903// sxg_send_packets_fail(adapter, skb, status);
1904#else
1905 SXG_DROP_DUMB_SEND(adapter, skb);
1906 adapter->stats.tx_dropped++;
1907#endif
1908 }
1909 DBG_ERROR("sxg: %s EXIT sxg_send_packets status[%x]\n", __FUNCTION__,
1910 status);
1911
1912 xmit_done:
1913 return 0;
1914}
1915
1916/*
1917 * sxg_transmit_packet
1918 *
1919 * This function transmits a single packet.
1920 *
1921 * Arguments -
1922 * adapter - Pointer to our adapter structure
1923 * skb - The packet to be sent
1924 *
1925 * Return -
1926 * STATUS of send
1927 */
1928static int sxg_transmit_packet(p_adapter_t adapter, struct sk_buff *skb)
1929{
1930 PSCATTER_GATHER_LIST pSgl;
1931 PSXG_SCATTER_GATHER SxgSgl;
1932 void * SglBuffer;
1933 u32 SglBufferLength;
1934
1935 // The vast majority of work is done in the shared
1936 // sxg_dumb_sgl routine.
1937 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSend",
1938 adapter, skb, 0, 0);
1939
1940 // Allocate a SGL buffer
1941 SXG_GET_SGL_BUFFER(adapter, SxgSgl);
1942 if (!SxgSgl) {
1943 adapter->Stats.NoSglBuf++;
1944 adapter->Stats.XmtErrors++;
1945 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "SndPktF1",
1946 adapter, skb, 0, 0);
1947 return (STATUS_RESOURCES);
1948 }
1949 ASSERT(SxgSgl->adapter == adapter);
1950 SglBuffer = SXG_SGL_BUFFER(SxgSgl);
1951 SglBufferLength = SXG_SGL_BUF_SIZE;
1952 SxgSgl->VlanTag.VlanTci = 0;
1953 SxgSgl->VlanTag.VlanTpid = 0;
1954 SxgSgl->Type = SXG_SGL_DUMB;
1955 SxgSgl->DumbPacket = skb;
1956 pSgl = NULL;
1957
1958 // Call the common sxg_dumb_sgl routine to complete the send.
1959 sxg_dumb_sgl(pSgl, SxgSgl);
1960 // Return success sxg_dumb_sgl (or something later) will complete it.
1961 return (STATUS_SUCCESS);
1962}
1963
1964/*
1965 * sxg_dumb_sgl
1966 *
1967 * Arguments:
1968 * pSgl -
1969 * SxgSgl - SXG_SCATTER_GATHER
1970 *
1971 * Return Value:
1972 * None.
1973 */
1974static void sxg_dumb_sgl(PSCATTER_GATHER_LIST pSgl, PSXG_SCATTER_GATHER SxgSgl)
1975{
1976 p_adapter_t adapter = SxgSgl->adapter;
1977 struct sk_buff *skb = SxgSgl->DumbPacket;
1978 // For now, all dumb-nic sends go on RSS queue zero
1979 PSXG_XMT_RING XmtRing = &adapter->XmtRings[0];
1980 PSXG_RING_INFO XmtRingInfo = &adapter->XmtRingZeroInfo;
1981 PSXG_CMD XmtCmd = NULL;
1982// u32 Index = 0;
1983 u32 DataLength = skb->len;
1984// unsigned int BufLen;
1985// u32 SglOffset;
1986 u64 phys_addr;
1987
1988 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSgl",
1989 pSgl, SxgSgl, 0, 0);
1990
1991 // Set aside a pointer to the sgl
1992 SxgSgl->pSgl = pSgl;
1993
1994 // Sanity check that our SGL format is as we expect.
1995 ASSERT(sizeof(SXG_X64_SGE) == sizeof(SCATTER_GATHER_ELEMENT));
1996 // Shouldn't be a vlan tag on this frame
1997 ASSERT(SxgSgl->VlanTag.VlanTci == 0);
1998 ASSERT(SxgSgl->VlanTag.VlanTpid == 0);
1999
2000 // From here below we work with the SGL placed in our
2001 // buffer.
2002
2003 SxgSgl->Sgl.NumberOfElements = 1;
2004
2005 // Grab the spinlock and acquire a command
2006 spin_lock(&adapter->XmtZeroLock);
2007 SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl);
2008 if (XmtCmd == NULL) {
2009 // Call sxg_complete_slow_send to see if we can
2010 // free up any XmtRingZero entries and then try again
2011 spin_unlock(&adapter->XmtZeroLock);
2012 sxg_complete_slow_send(adapter);
2013 spin_lock(&adapter->XmtZeroLock);
2014 SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl);
2015 if (XmtCmd == NULL) {
2016 adapter->Stats.XmtZeroFull++;
2017 goto abortcmd;
2018 }
2019 }
2020 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbCmd",
2021 XmtCmd, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
2022 // Update stats
2023 adapter->Stats.DumbXmtPkts++;
2024 adapter->Stats.DumbXmtBytes += DataLength;
2025#if XXXTODO // Stats stuff
2026 if (SXG_MULTICAST_PACKET(EtherHdr)) {
2027 if (SXG_BROADCAST_PACKET(EtherHdr)) {
2028 adapter->Stats.DumbXmtBcastPkts++;
2029 adapter->Stats.DumbXmtBcastBytes += DataLength;
2030 } else {
2031 adapter->Stats.DumbXmtMcastPkts++;
2032 adapter->Stats.DumbXmtMcastBytes += DataLength;
2033 }
2034 } else {
2035 adapter->Stats.DumbXmtUcastPkts++;
2036 adapter->Stats.DumbXmtUcastBytes += DataLength;
2037 }
2038#endif
2039 // Fill in the command
2040 // Copy out the first SGE to the command and adjust for offset
2041 phys_addr = pci_map_single(adapter->pcidev, skb->data, skb->len, PCI_DMA_TODEVICE);
2042 XmtCmd->Buffer.FirstSgeAddress = SXG_GET_ADDR_HIGH(phys_addr);
2043 XmtCmd->Buffer.FirstSgeAddress = XmtCmd->Buffer.FirstSgeAddress << 32;
2044 XmtCmd->Buffer.FirstSgeAddress =
2045 XmtCmd->Buffer.FirstSgeAddress | SXG_GET_ADDR_LOW(phys_addr);
2046// XmtCmd->Buffer.FirstSgeAddress = SxgSgl->Sgl.Elements[Index].Address;
2047// XmtCmd->Buffer.FirstSgeAddress.LowPart += MdlOffset;
2048 XmtCmd->Buffer.FirstSgeLength = DataLength;
2049 // Set a pointer to the remaining SGL entries
2050// XmtCmd->Sgl = SxgSgl->PhysicalAddress;
2051 // Advance the physical address of the SxgSgl structure to
2052 // the second SGE
2053// SglOffset = (u32)((u32 *)(&SxgSgl->Sgl.Elements[Index+1]) -
2054// (u32 *)SxgSgl);
2055// XmtCmd->Sgl.LowPart += SglOffset;
2056 XmtCmd->Buffer.SgeOffset = 0;
2057 // Note - TotalLength might be overwritten with MSS below..
2058 XmtCmd->Buffer.TotalLength = DataLength;
2059 XmtCmd->SgEntries = 1; //(ushort)(SxgSgl->Sgl.NumberOfElements - Index);
2060 XmtCmd->Flags = 0;
2061 //
2062 // Advance transmit cmd descripter by 1.
2063 // NOTE - See comments in SxgTcpOutput where we write
2064 // to the XmtCmd register regarding CPU ID values and/or
2065 // multiple commands.
2066 //
2067 //
2068 WRITE_REG(adapter->UcodeRegs[0].XmtCmd, 1, TRUE);
2069 //
2070 //
2071 adapter->Stats.XmtQLen++; // Stats within lock
2072 spin_unlock(&adapter->XmtZeroLock);
2073 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDumSgl2",
2074 XmtCmd, pSgl, SxgSgl, 0);
2075 return;
2076
2077 abortcmd:
2078 // NOTE - Only jump to this label AFTER grabbing the
2079 // XmtZeroLock, and DO NOT DROP IT between the
2080 // command allocation and the following abort.
2081 if (XmtCmd) {
2082 SXG_ABORT_CMD(XmtRingInfo);
2083 }
2084 spin_unlock(&adapter->XmtZeroLock);
2085
2086// failsgl:
2087 // Jump to this label if failure occurs before the
2088 // XmtZeroLock is grabbed
2089 adapter->Stats.XmtErrors++;
2090 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumSGFal",
2091 pSgl, SxgSgl, XmtRingInfo->Head, XmtRingInfo->Tail);
2092
2093 SXG_COMPLETE_DUMB_SEND(adapter, SxgSgl->DumbPacket); // SxgSgl->DumbPacket is the skb
2094}
2095
2096/***************************************************************
2097 * Link management functions
2098 ***************************************************************/
2099
2100/*
2101 * sxg_initialize_link - Initialize the link stuff
2102 *
2103 * Arguments -
2104 * adapter - A pointer to our adapter structure
2105 *
2106 * Return
2107 * status
2108 */
2109static int sxg_initialize_link(p_adapter_t adapter)
2110{
2111 PSXG_HW_REGS HwRegs = adapter->HwRegs;
2112 u32 Value;
2113 u32 ConfigData;
2114 u32 MaxFrame;
2115 int status;
2116
2117 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitLink",
2118 adapter, 0, 0, 0);
2119
2120 // Reset PHY and XGXS module
2121 WRITE_REG(HwRegs->LinkStatus, LS_SERDES_POWER_DOWN, TRUE);
2122
2123 // Reset transmit configuration register
2124 WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_RESET, TRUE);
2125
2126 // Reset receive configuration register
2127 WRITE_REG(HwRegs->RcvConfig, RCV_CONFIG_RESET, TRUE);
2128
2129 // Reset all MAC modules
2130 WRITE_REG(HwRegs->MacConfig0, AXGMAC_CFG0_SUB_RESET, TRUE);
2131
2132 // Link address 0
2133 // XXXTODO - This assumes the MAC address (0a:0b:0c:0d:0e:0f)
2134 // is stored with the first nibble (0a) in the byte 0
2135 // of the Mac address. Possibly reverse?
2136 Value = *(u32 *) adapter->MacAddr;
2137 WRITE_REG(HwRegs->LinkAddress0Low, Value, TRUE);
2138 // also write the MAC address to the MAC. Endian is reversed.
2139 WRITE_REG(HwRegs->MacAddressLow, ntohl(Value), TRUE);
2140 Value = (*(u16 *) & adapter->MacAddr[4] & 0x0000FFFF);
2141 WRITE_REG(HwRegs->LinkAddress0High, Value | LINK_ADDRESS_ENABLE, TRUE);
2142 // endian swap for the MAC (put high bytes in bits [31:16], swapped)
2143 Value = ntohl(Value);
2144 WRITE_REG(HwRegs->MacAddressHigh, Value, TRUE);
2145 // Link address 1
2146 WRITE_REG(HwRegs->LinkAddress1Low, 0, TRUE);
2147 WRITE_REG(HwRegs->LinkAddress1High, 0, TRUE);
2148 // Link address 2
2149 WRITE_REG(HwRegs->LinkAddress2Low, 0, TRUE);
2150 WRITE_REG(HwRegs->LinkAddress2High, 0, TRUE);
2151 // Link address 3
2152 WRITE_REG(HwRegs->LinkAddress3Low, 0, TRUE);
2153 WRITE_REG(HwRegs->LinkAddress3High, 0, TRUE);
2154
2155 // Enable MAC modules
2156 WRITE_REG(HwRegs->MacConfig0, 0, TRUE);
2157
2158 // Configure MAC
2159 WRITE_REG(HwRegs->MacConfig1, (AXGMAC_CFG1_XMT_PAUSE | // Allow sending of pause
2160 AXGMAC_CFG1_XMT_EN | // Enable XMT
2161 AXGMAC_CFG1_RCV_PAUSE | // Enable detection of pause
2162 AXGMAC_CFG1_RCV_EN | // Enable receive
2163 AXGMAC_CFG1_SHORT_ASSERT | // short frame detection
2164 AXGMAC_CFG1_CHECK_LEN | // Verify frame length
2165 AXGMAC_CFG1_GEN_FCS | // Generate FCS
2166 AXGMAC_CFG1_PAD_64), // Pad frames to 64 bytes
2167 TRUE);
2168
2169 // Set AXGMAC max frame length if jumbo. Not needed for standard MTU
2170 if (adapter->JumboEnabled) {
2171 WRITE_REG(HwRegs->MacMaxFrameLen, AXGMAC_MAXFRAME_JUMBO, TRUE);
2172 }
2173 // AMIIM Configuration Register -
2174 // The value placed in the AXGMAC_AMIIM_CFG_HALF_CLOCK portion
2175 // (bottom bits) of this register is used to determine the
2176 // MDC frequency as specified in the A-XGMAC Design Document.
2177 // This value must not be zero. The following value (62 or 0x3E)
2178 // is based on our MAC transmit clock frequency (MTCLK) of 312.5 MHz.
2179 // Given a maximum MDIO clock frequency of 2.5 MHz (see the PHY spec),
2180 // we get: 312.5/(2*(X+1)) < 2.5 ==> X = 62.
2181 // This value happens to be the default value for this register,
2182 // so we really don't have to do this.
2183 WRITE_REG(HwRegs->MacAmiimConfig, 0x0000003E, TRUE);
2184
2185 // Power up and enable PHY and XAUI/XGXS/Serdes logic
2186 WRITE_REG(HwRegs->LinkStatus,
2187 (LS_PHY_CLR_RESET |
2188 LS_XGXS_ENABLE |
2189 LS_XGXS_CTL | LS_PHY_CLK_EN | LS_ATTN_ALARM), TRUE);
2190 DBG_ERROR("After Power Up and enable PHY in sxg_initialize_link\n");
2191
2192 // Per information given by Aeluros, wait 100 ms after removing reset.
2193 // It's not enough to wait for the self-clearing reset bit in reg 0 to clear.
2194 mdelay(100);
2195
2196 // Verify the PHY has come up by checking that the Reset bit has cleared.
2197 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module
2198 PHY_PMA_CONTROL1, // PMA/PMD control register
2199 &Value);
2200 if (status != STATUS_SUCCESS)
2201 return (STATUS_FAILURE);
2202 if (Value & PMA_CONTROL1_RESET) // reset complete if bit is 0
2203 return (STATUS_FAILURE);
2204
2205 // The SERDES should be initialized by now - confirm
2206 READ_REG(HwRegs->LinkStatus, Value);
2207 if (Value & LS_SERDES_DOWN) // verify SERDES is initialized
2208 return (STATUS_FAILURE);
2209
2210 // The XAUI link should also be up - confirm
2211 if (!(Value & LS_XAUI_LINK_UP)) // verify XAUI link is up
2212 return (STATUS_FAILURE);
2213
2214 // Initialize the PHY
2215 status = sxg_phy_init(adapter);
2216 if (status != STATUS_SUCCESS)
2217 return (STATUS_FAILURE);
2218
2219 // Enable the Link Alarm
2220 status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module
2221 LASI_CONTROL, // LASI control register
2222 LASI_CTL_LS_ALARM_ENABLE); // enable link alarm bit
2223 if (status != STATUS_SUCCESS)
2224 return (STATUS_FAILURE);
2225
2226 // XXXTODO - temporary - verify bit is set
2227 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module
2228 LASI_CONTROL, // LASI control register
2229 &Value);
2230 if (status != STATUS_SUCCESS)
2231 return (STATUS_FAILURE);
2232 if (!(Value & LASI_CTL_LS_ALARM_ENABLE)) {
2233 DBG_ERROR("Error! LASI Control Alarm Enable bit not set!\n");
2234 }
2235 // Enable receive
2236 MaxFrame = adapter->JumboEnabled ? JUMBOMAXFRAME : ETHERMAXFRAME;
2237 ConfigData = (RCV_CONFIG_ENABLE |
2238 RCV_CONFIG_ENPARSE |
2239 RCV_CONFIG_RCVBAD |
2240 RCV_CONFIG_RCVPAUSE |
2241 RCV_CONFIG_TZIPV6 |
2242 RCV_CONFIG_TZIPV4 |
2243 RCV_CONFIG_HASH_16 |
2244 RCV_CONFIG_SOCKET | RCV_CONFIG_BUFSIZE(MaxFrame));
2245 WRITE_REG(HwRegs->RcvConfig, ConfigData, TRUE);
2246
2247 WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_ENABLE, TRUE);
2248
2249 // Mark the link as down. We'll get a link event when it comes up.
2250 sxg_link_state(adapter, SXG_LINK_DOWN);
2251
2252 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInitLnk",
2253 adapter, 0, 0, 0);
2254 return (STATUS_SUCCESS);
2255}
2256
2257/*
2258 * sxg_phy_init - Initialize the PHY
2259 *
2260 * Arguments -
2261 * adapter - A pointer to our adapter structure
2262 *
2263 * Return
2264 * status
2265 */
2266static int sxg_phy_init(p_adapter_t adapter)
2267{
2268 u32 Value;
2269 PPHY_UCODE p;
2270 int status;
2271
2272 DBG_ERROR("ENTER %s\n", __FUNCTION__);
2273
2274 // Read a register to identify the PHY type
2275 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module
2276 0xC205, // PHY ID register (?)
2277 &Value); // XXXTODO - add def
2278 if (status != STATUS_SUCCESS)
2279 return (STATUS_FAILURE);
2280
2281 if (Value == 0x0012) { // 0x0012 == AEL2005C PHY(?) - XXXTODO - add def
2282 DBG_ERROR
2283 ("AEL2005C PHY detected. Downloading PHY microcode.\n");
2284
2285 // Initialize AEL2005C PHY and download PHY microcode
2286 for (p = PhyUcode; p->Addr != 0xFFFF; p++) {
2287 if (p->Addr == 0) {
2288 // if address == 0, data == sleep time in ms
2289 mdelay(p->Data);
2290 } else {
2291 // write the given data to the specified address
2292 status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module
2293 p->Addr, // PHY address
2294 p->Data); // PHY data
2295 if (status != STATUS_SUCCESS)
2296 return (STATUS_FAILURE);
2297 }
2298 }
2299 }
2300 DBG_ERROR("EXIT %s\n", __FUNCTION__);
2301
2302 return (STATUS_SUCCESS);
2303}
2304
2305/*
2306 * sxg_link_event - Process a link event notification from the card
2307 *
2308 * Arguments -
2309 * adapter - A pointer to our adapter structure
2310 *
2311 * Return
2312 * None
2313 */
2314static void sxg_link_event(p_adapter_t adapter)
2315{
2316 PSXG_HW_REGS HwRegs = adapter->HwRegs;
2317 SXG_LINK_STATE LinkState;
2318 int status;
2319 u32 Value;
2320
2321 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "LinkEvnt",
2322 adapter, 0, 0, 0);
2323 DBG_ERROR("ENTER %s\n", __FUNCTION__);
2324
2325 // Check the Link Status register. We should have a Link Alarm.
2326 READ_REG(HwRegs->LinkStatus, Value);
2327 if (Value & LS_LINK_ALARM) {
2328 // We got a Link Status alarm. First, pause to let the
2329 // link state settle (it can bounce a number of times)
2330 mdelay(10);
2331
2332 // Now clear the alarm by reading the LASI status register.
2333 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module
2334 LASI_STATUS, // LASI status register
2335 &Value);
2336 if (status != STATUS_SUCCESS) {
2337 DBG_ERROR("Error reading LASI Status MDIO register!\n");
2338 sxg_link_state(adapter, SXG_LINK_DOWN);
2339// ASSERT(0);
2340 }
2341 ASSERT(Value & LASI_STATUS_LS_ALARM);
2342
2343 // Now get and set the link state
2344 LinkState = sxg_get_link_state(adapter);
2345 sxg_link_state(adapter, LinkState);
2346 DBG_ERROR("SXG: Link Alarm occurred. Link is %s\n",
2347 ((LinkState == SXG_LINK_UP) ? "UP" : "DOWN"));
2348 } else {
2349 // XXXTODO - Assuming Link Attention is only being generated for the
2350 // Link Alarm pin (and not for a XAUI Link Status change), then it's
2351 // impossible to get here. Yet we've gotten here twice (under extreme
2352 // conditions - bouncing the link up and down many times a second).
2353 // Needs further investigation.
2354 DBG_ERROR("SXG: sxg_link_event: Can't get here!\n");
2355 DBG_ERROR("SXG: Link Status == 0x%08X.\n", Value);
2356// ASSERT(0);
2357 }
2358 DBG_ERROR("EXIT %s\n", __FUNCTION__);
2359
2360}
2361
2362/*
2363 * sxg_get_link_state - Determine if the link is up or down
2364 *
2365 * Arguments -
2366 * adapter - A pointer to our adapter structure
2367 *
2368 * Return
2369 * Link State
2370 */
2371static SXG_LINK_STATE sxg_get_link_state(p_adapter_t adapter)
2372{
2373 int status;
2374 u32 Value;
2375
2376 DBG_ERROR("ENTER %s\n", __FUNCTION__);
2377
2378 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "GetLink",
2379 adapter, 0, 0, 0);
2380
2381 // Per the Xenpak spec (and the IEEE 10Gb spec?), the link is up if
2382 // the following 3 bits (from 3 different MDIO registers) are all true.
2383 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module
2384 PHY_PMA_RCV_DET, // PMA/PMD Receive Signal Detect register
2385 &Value);
2386 if (status != STATUS_SUCCESS)
2387 goto bad;
2388
2389 // If PMA/PMD receive signal detect is 0, then the link is down
2390 if (!(Value & PMA_RCV_DETECT))
2391 return (SXG_LINK_DOWN);
2392
2393 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PCS, // PHY PCS module
2394 PHY_PCS_10G_STATUS1, // PCS 10GBASE-R Status 1 register
2395 &Value);
2396 if (status != STATUS_SUCCESS)
2397 goto bad;
2398
2399 // If PCS is not locked to receive blocks, then the link is down
2400 if (!(Value & PCS_10B_BLOCK_LOCK))
2401 return (SXG_LINK_DOWN);
2402
2403 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_XS, // PHY XS module
2404 PHY_XS_LANE_STATUS, // XS Lane Status register
2405 &Value);
2406 if (status != STATUS_SUCCESS)
2407 goto bad;
2408
2409 // If XS transmit lanes are not aligned, then the link is down
2410 if (!(Value & XS_LANE_ALIGN))
2411 return (SXG_LINK_DOWN);
2412
2413 // All 3 bits are true, so the link is up
2414 DBG_ERROR("EXIT %s\n", __FUNCTION__);
2415
2416 return (SXG_LINK_UP);
2417
2418 bad:
2419 // An error occurred reading an MDIO register. This shouldn't happen.
2420 DBG_ERROR("Error reading an MDIO register!\n");
2421 ASSERT(0);
2422 return (SXG_LINK_DOWN);
2423}
2424
2425static void sxg_indicate_link_state(p_adapter_t adapter, SXG_LINK_STATE LinkState)
2426{
2427 if (adapter->LinkState == SXG_LINK_UP) {
2428 DBG_ERROR("%s: LINK now UP, call netif_start_queue\n",
2429 __FUNCTION__);
2430 netif_start_queue(adapter->netdev);
2431 } else {
2432 DBG_ERROR("%s: LINK now DOWN, call netif_stop_queue\n",
2433 __FUNCTION__);
2434 netif_stop_queue(adapter->netdev);
2435 }
2436}
2437
2438/*
2439 * sxg_link_state - Set the link state and if necessary, indicate.
2440 * This routine the central point of processing for all link state changes.
2441 * Nothing else in the driver should alter the link state or perform
2442 * link state indications
2443 *
2444 * Arguments -
2445 * adapter - A pointer to our adapter structure
2446 * LinkState - The link state
2447 *
2448 * Return
2449 * None
2450 */
2451static void sxg_link_state(p_adapter_t adapter, SXG_LINK_STATE LinkState)
2452{
2453 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "LnkINDCT",
2454 adapter, LinkState, adapter->LinkState, adapter->State);
2455
2456 DBG_ERROR("ENTER %s\n", __FUNCTION__);
2457
2458 // Hold the adapter lock during this routine. Maybe move
2459 // the lock to the caller.
2460 spin_lock(&adapter->AdapterLock);
2461 if (LinkState == adapter->LinkState) {
2462 // Nothing changed..
2463 spin_unlock(&adapter->AdapterLock);
2464 DBG_ERROR("EXIT #0 %s\n", __FUNCTION__);
2465 return;
2466 }
2467 // Save the adapter state
2468 adapter->LinkState = LinkState;
2469
2470 // Drop the lock and indicate link state
2471 spin_unlock(&adapter->AdapterLock);
2472 DBG_ERROR("EXIT #1 %s\n", __FUNCTION__);
2473
2474 sxg_indicate_link_state(adapter, LinkState);
2475}
2476
2477/*
2478 * sxg_write_mdio_reg - Write to a register on the MDIO bus
2479 *
2480 * Arguments -
2481 * adapter - A pointer to our adapter structure
2482 * DevAddr - MDIO device number being addressed
2483 * RegAddr - register address for the specified MDIO device
2484 * Value - value to write to the MDIO register
2485 *
2486 * Return
2487 * status
2488 */
2489static int sxg_write_mdio_reg(p_adapter_t adapter,
2490 u32 DevAddr, u32 RegAddr, u32 Value)
2491{
2492 PSXG_HW_REGS HwRegs = adapter->HwRegs;
2493 u32 AddrOp; // Address operation (written to MIIM field reg)
2494 u32 WriteOp; // Write operation (written to MIIM field reg)
2495 u32 Cmd; // Command (written to MIIM command reg)
2496 u32 ValueRead;
2497 u32 Timeout;
2498
2499// DBG_ERROR("ENTER %s\n", __FUNCTION__);
2500
2501 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO",
2502 adapter, 0, 0, 0);
2503
2504 // Ensure values don't exceed field width
2505 DevAddr &= 0x001F; // 5-bit field
2506 RegAddr &= 0xFFFF; // 16-bit field
2507 Value &= 0xFFFF; // 16-bit field
2508
2509 // Set MIIM field register bits for an MIIM address operation
2510 AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2511 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2512 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2513 (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr;
2514
2515 // Set MIIM field register bits for an MIIM write operation
2516 WriteOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2517 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2518 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2519 (MIIM_OP_WRITE << AXGMAC_AMIIM_FIELD_OP_SHIFT) | Value;
2520
2521 // Set MIIM command register bits to execute an MIIM command
2522 Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION;
2523
2524 // Reset the command register command bit (in case it's not 0)
2525 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2526
2527 // MIIM write to set the address of the specified MDIO register
2528 WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE);
2529
2530 // Write to MIIM Command Register to execute to address operation
2531 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2532
2533 // Poll AMIIM Indicator register to wait for completion
2534 Timeout = SXG_LINK_TIMEOUT;
2535 do {
2536 udelay(100); // Timeout in 100us units
2537 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2538 if (--Timeout == 0) {
2539 return (STATUS_FAILURE);
2540 }
2541 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2542
2543 // Reset the command register command bit
2544 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2545
2546 // MIIM write to set up an MDIO write operation
2547 WRITE_REG(HwRegs->MacAmiimField, WriteOp, TRUE);
2548
2549 // Write to MIIM Command Register to execute the write operation
2550 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2551
2552 // Poll AMIIM Indicator register to wait for completion
2553 Timeout = SXG_LINK_TIMEOUT;
2554 do {
2555 udelay(100); // Timeout in 100us units
2556 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2557 if (--Timeout == 0) {
2558 return (STATUS_FAILURE);
2559 }
2560 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2561
2562// DBG_ERROR("EXIT %s\n", __FUNCTION__);
2563
2564 return (STATUS_SUCCESS);
2565}
2566
2567/*
2568 * sxg_read_mdio_reg - Read a register on the MDIO bus
2569 *
2570 * Arguments -
2571 * adapter - A pointer to our adapter structure
2572 * DevAddr - MDIO device number being addressed
2573 * RegAddr - register address for the specified MDIO device
2574 * pValue - pointer to where to put data read from the MDIO register
2575 *
2576 * Return
2577 * status
2578 */
2579static int sxg_read_mdio_reg(p_adapter_t adapter,
2580 u32 DevAddr, u32 RegAddr, u32 * pValue)
2581{
2582 PSXG_HW_REGS HwRegs = adapter->HwRegs;
2583 u32 AddrOp; // Address operation (written to MIIM field reg)
2584 u32 ReadOp; // Read operation (written to MIIM field reg)
2585 u32 Cmd; // Command (written to MIIM command reg)
2586 u32 ValueRead;
2587 u32 Timeout;
2588
2589 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO",
2590 adapter, 0, 0, 0);
2591// DBG_ERROR("ENTER %s\n", __FUNCTION__);
2592
2593 // Ensure values don't exceed field width
2594 DevAddr &= 0x001F; // 5-bit field
2595 RegAddr &= 0xFFFF; // 16-bit field
2596
2597 // Set MIIM field register bits for an MIIM address operation
2598 AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2599 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2600 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2601 (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr;
2602
2603 // Set MIIM field register bits for an MIIM read operation
2604 ReadOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2605 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2606 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2607 (MIIM_OP_READ << AXGMAC_AMIIM_FIELD_OP_SHIFT);
2608
2609 // Set MIIM command register bits to execute an MIIM command
2610 Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION;
2611
2612 // Reset the command register command bit (in case it's not 0)
2613 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2614
2615 // MIIM write to set the address of the specified MDIO register
2616 WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE);
2617
2618 // Write to MIIM Command Register to execute to address operation
2619 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2620
2621 // Poll AMIIM Indicator register to wait for completion
2622 Timeout = SXG_LINK_TIMEOUT;
2623 do {
2624 udelay(100); // Timeout in 100us units
2625 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2626 if (--Timeout == 0) {
2627 return (STATUS_FAILURE);
2628 }
2629 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2630
2631 // Reset the command register command bit
2632 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2633
2634 // MIIM write to set up an MDIO register read operation
2635 WRITE_REG(HwRegs->MacAmiimField, ReadOp, TRUE);
2636
2637 // Write to MIIM Command Register to execute the read operation
2638 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2639
2640 // Poll AMIIM Indicator register to wait for completion
2641 Timeout = SXG_LINK_TIMEOUT;
2642 do {
2643 udelay(100); // Timeout in 100us units
2644 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2645 if (--Timeout == 0) {
2646 return (STATUS_FAILURE);
2647 }
2648 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2649
2650 // Read the MDIO register data back from the field register
2651 READ_REG(HwRegs->MacAmiimField, *pValue);
2652 *pValue &= 0xFFFF; // data is in the lower 16 bits
2653
2654// DBG_ERROR("EXIT %s\n", __FUNCTION__);
2655
2656 return (STATUS_SUCCESS);
2657}
2658
2659/*
2660 * Allocate a mcast_address structure to hold the multicast address.
2661 * Link it in.
2662 */
2663static int sxg_mcast_add_list(p_adapter_t adapter, char *address)
2664{
2665 p_mcast_address_t mcaddr, mlist;
2666 bool equaladdr;
2667
2668 /* Check to see if it already exists */
2669 mlist = adapter->mcastaddrs;
2670 while (mlist) {
2671 ETHER_EQ_ADDR(mlist->address, address, equaladdr);
2672 if (equaladdr) {
2673 return (STATUS_SUCCESS);
2674 }
2675 mlist = mlist->next;
2676 }
2677
2678 /* Doesn't already exist. Allocate a structure to hold it */
2679 mcaddr = kmalloc(sizeof(mcast_address_t), GFP_ATOMIC);
2680 if (mcaddr == NULL)
2681 return 1;
2682
2683 memcpy(mcaddr->address, address, 6);
2684
2685 mcaddr->next = adapter->mcastaddrs;
2686 adapter->mcastaddrs = mcaddr;
2687
2688 return (STATUS_SUCCESS);
2689}
2690
2691/*
2692 * Functions to obtain the CRC corresponding to the destination mac address.
2693 * This is a standard ethernet CRC in that it is a 32-bit, reflected CRC using
2694 * the polynomial:
2695 * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1.
2696 *
2697 * After the CRC for the 6 bytes is generated (but before the value is complemented),
2698 * we must then transpose the value and return bits 30-23.
2699 *
2700 */
2701static u32 sxg_crc_table[256]; /* Table of CRC's for all possible byte values */
2702static u32 sxg_crc_init; /* Is table initialized */
2703
2704/*
2705 * Contruct the CRC32 table
2706 */
2707static void sxg_mcast_init_crc32(void)
2708{
2709 u32 c; /* CRC shit reg */
2710 u32 e = 0; /* Poly X-or pattern */
2711 int i; /* counter */
2712 int k; /* byte being shifted into crc */
2713
2714 static int p[] = { 0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26 };
2715
2716 for (i = 0; i < sizeof(p) / sizeof(int); i++) {
2717 e |= 1L << (31 - p[i]);
2718 }
2719
2720 for (i = 1; i < 256; i++) {
2721 c = i;
2722 for (k = 8; k; k--) {
2723 c = c & 1 ? (c >> 1) ^ e : c >> 1;
2724 }
2725 sxg_crc_table[i] = c;
2726 }
2727}
2728
2729/*
2730 * Return the MAC hast as described above.
2731 */
2732static unsigned char sxg_mcast_get_mac_hash(char *macaddr)
2733{
2734 u32 crc;
2735 char *p;
2736 int i;
2737 unsigned char machash = 0;
2738
2739 if (!sxg_crc_init) {
2740 sxg_mcast_init_crc32();
2741 sxg_crc_init = 1;
2742 }
2743
2744 crc = 0xFFFFFFFF; /* Preload shift register, per crc-32 spec */
2745 for (i = 0, p = macaddr; i < 6; ++p, ++i) {
2746 crc = (crc >> 8) ^ sxg_crc_table[(crc ^ *p) & 0xFF];
2747 }
2748
2749 /* Return bits 1-8, transposed */
2750 for (i = 1; i < 9; i++) {
2751 machash |= (((crc >> i) & 1) << (8 - i));
2752 }
2753
2754 return (machash);
2755}
2756
2757static void sxg_mcast_set_bit(p_adapter_t adapter, char *address)
2758{
2759 unsigned char crcpoly;
2760
2761 /* Get the CRC polynomial for the mac address */
2762 crcpoly = sxg_mcast_get_mac_hash(address);
2763
2764 /* We only have space on the SLIC for 64 entries. Lop
2765 * off the top two bits. (2^6 = 64)
2766 */
2767 crcpoly &= 0x3F;
2768
2769 /* OR in the new bit into our 64 bit mask. */
2770 adapter->MulticastMask |= (u64) 1 << crcpoly;
2771}
2772
2773static void sxg_mcast_set_list(p_net_device dev)
2774{
2775#if XXXTODO
2776 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
2777 int status = STATUS_SUCCESS;
2778 int i;
2779 char *addresses;
2780 struct dev_mc_list *mc_list = dev->mc_list;
2781 int mc_count = dev->mc_count;
2782
2783 ASSERT(adapter);
2784
2785 for (i = 1; i <= mc_count; i++) {
2786 addresses = (char *) & mc_list->dmi_addr;
2787 if (mc_list->dmi_addrlen == 6) {
2788 status = sxg_mcast_add_list(adapter, addresses);
2789 if (status != STATUS_SUCCESS) {
2790 break;
2791 }
2792 } else {
2793 status = -EINVAL;
2794 break;
2795 }
2796 sxg_mcast_set_bit(adapter, addresses);
2797 mc_list = mc_list->next;
2798 }
2799
2800 DBG_ERROR("%s a->devflags_prev[%x] dev->flags[%x] status[%x]\n",
2801 __FUNCTION__, adapter->devflags_prev, dev->flags, status);
2802 if (adapter->devflags_prev != dev->flags) {
2803 adapter->macopts = MAC_DIRECTED;
2804 if (dev->flags) {
2805 if (dev->flags & IFF_BROADCAST) {
2806 adapter->macopts |= MAC_BCAST;
2807 }
2808 if (dev->flags & IFF_PROMISC) {
2809 adapter->macopts |= MAC_PROMISC;
2810 }
2811 if (dev->flags & IFF_ALLMULTI) {
2812 adapter->macopts |= MAC_ALLMCAST;
2813 }
2814 if (dev->flags & IFF_MULTICAST) {
2815 adapter->macopts |= MAC_MCAST;
2816 }
2817 }
2818 adapter->devflags_prev = dev->flags;
2819 DBG_ERROR("%s call sxg_config_set adapter->macopts[%x]\n",
2820 __FUNCTION__, adapter->macopts);
2821 sxg_config_set(adapter, TRUE);
2822 } else {
2823 if (status == STATUS_SUCCESS) {
2824 sxg_mcast_set_mask(adapter);
2825 }
2826 }
2827#endif
2828 return;
2829}
2830
2831static void sxg_mcast_set_mask(p_adapter_t adapter)
2832{
2833 PSXG_UCODE_REGS sxg_regs = adapter->UcodeRegs;
2834
2835 DBG_ERROR("%s ENTER (%s) macopts[%x] mask[%llx]\n", __FUNCTION__,
2836 adapter->netdev->name, (unsigned int) adapter->MacFilter,
2837 adapter->MulticastMask);
2838
2839 if (adapter->MacFilter & (MAC_ALLMCAST | MAC_PROMISC)) {
2840 /* Turn on all multicast addresses. We have to do this for promiscuous
2841 * mode as well as ALLMCAST mode. It saves the Microcode from having
2842 * to keep state about the MAC configuration.
2843 */
2844// DBG_ERROR("sxg: %s macopts = MAC_ALLMCAST | MAC_PROMISC\n SLUT MODE!!!\n",__FUNCTION__);
2845 WRITE_REG(sxg_regs->McastLow, 0xFFFFFFFF, FLUSH);
2846 WRITE_REG(sxg_regs->McastHigh, 0xFFFFFFFF, FLUSH);
2847// DBG_ERROR("%s (%s) WRITE to slic_regs slic_mcastlow&high 0xFFFFFFFF\n",__FUNCTION__, adapter->netdev->name);
2848
2849 } else {
2850 /* Commit our multicast mast to the SLIC by writing to the multicast
2851 * address mask registers
2852 */
2853 DBG_ERROR("%s (%s) WRITE mcastlow[%lx] mcasthigh[%lx]\n",
2854 __FUNCTION__, adapter->netdev->name,
2855 ((ulong) (adapter->MulticastMask & 0xFFFFFFFF)),
2856 ((ulong)
2857 ((adapter->MulticastMask >> 32) & 0xFFFFFFFF)));
2858
2859 WRITE_REG(sxg_regs->McastLow,
2860 (u32) (adapter->MulticastMask & 0xFFFFFFFF),
2861 FLUSH);
2862 WRITE_REG(sxg_regs->McastHigh,
2863 (u32) ((adapter->
2864 MulticastMask >> 32) & 0xFFFFFFFF),
2865 FLUSH);
2866 }
2867}
2868
2869static void sxg_unmap_mmio_space(p_adapter_t adapter)
2870{
2871#if LINUX_FREES_ADAPTER_RESOURCES
2872// if (adapter->Regs) {
2873// iounmap(adapter->Regs);
2874// }
2875// adapter->slic_regs = NULL;
2876#endif
2877}
2878
2879#if XXXTODO
2880/*
2881 * SxgFreeResources - Free everything allocated in SxgAllocateResources
2882 *
2883 * Arguments -
2884 * adapter - A pointer to our adapter structure
2885 *
2886 * Return
2887 * none
2888 */
2889void SxgFreeResources(p_adapter_t adapter)
2890{
2891 u32 RssIds, IsrCount;
2892 PTCP_OBJECT TcpObject;
2893 u32 i;
2894 BOOLEAN TimerCancelled;
2895
2896 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "FreeRes",
2897 adapter, adapter->MaxTcbs, 0, 0);
2898
2899 RssIds = SXG_RSS_CPU_COUNT(adapter);
2900 IsrCount = adapter->MsiEnabled ? RssIds : 1;
2901
2902 if (adapter->BasicAllocations == FALSE) {
2903 // No allocations have been made, including spinlocks,
2904 // or listhead initializations. Return.
2905 return;
2906 }
2907
2908 if (!(IsListEmpty(&adapter->AllRcvBlocks))) {
2909 SxgFreeRcvBlocks(adapter);
2910 }
2911 if (!(IsListEmpty(&adapter->AllSglBuffers))) {
2912 SxgFreeSglBuffers(adapter);
2913 }
2914 // Free event queues.
2915 if (adapter->EventRings) {
2916 pci_free_consistent(adapter->pcidev,
2917 sizeof(SXG_EVENT_RING) * RssIds,
2918 adapter->EventRings, adapter->PEventRings);
2919 }
2920 if (adapter->Isr) {
2921 pci_free_consistent(adapter->pcidev,
2922 sizeof(u32) * IsrCount,
2923 adapter->Isr, adapter->PIsr);
2924 }
2925 if (adapter->XmtRingZeroIndex) {
2926 pci_free_consistent(adapter->pcidev,
2927 sizeof(u32),
2928 adapter->XmtRingZeroIndex,
2929 adapter->PXmtRingZeroIndex);
2930 }
2931 if (adapter->IndirectionTable) {
2932 pci_free_consistent(adapter->pcidev,
2933 SXG_MAX_RSS_TABLE_SIZE,
2934 adapter->IndirectionTable,
2935 adapter->PIndirectionTable);
2936 }
2937
2938 SXG_FREE_PACKET_POOL(adapter->PacketPoolHandle);
2939 SXG_FREE_BUFFER_POOL(adapter->BufferPoolHandle);
2940
2941 // Unmap register spaces
2942 SxgUnmapResources(adapter);
2943
2944 // Deregister DMA
2945 if (adapter->DmaHandle) {
2946 SXG_DEREGISTER_DMA(adapter->DmaHandle);
2947 }
2948 // Deregister interrupt
2949 SxgDeregisterInterrupt(adapter);
2950
2951 // Possibly free system info (5.2 only)
2952 SXG_RELEASE_SYSTEM_INFO(adapter);
2953
2954 SxgDiagFreeResources(adapter);
2955
2956 SxgFreeMCastAddrs(adapter);
2957
2958 if (SXG_TIMER_ALLOCATED(adapter->ResetTimer)) {
2959 SXG_CANCEL_TIMER(adapter->ResetTimer, TimerCancelled);
2960 SXG_FREE_TIMER(adapter->ResetTimer);
2961 }
2962 if (SXG_TIMER_ALLOCATED(adapter->RssTimer)) {
2963 SXG_CANCEL_TIMER(adapter->RssTimer, TimerCancelled);
2964 SXG_FREE_TIMER(adapter->RssTimer);
2965 }
2966 if (SXG_TIMER_ALLOCATED(adapter->OffloadTimer)) {
2967 SXG_CANCEL_TIMER(adapter->OffloadTimer, TimerCancelled);
2968 SXG_FREE_TIMER(adapter->OffloadTimer);
2969 }
2970
2971 adapter->BasicAllocations = FALSE;
2972
2973 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFreeRes",
2974 adapter, adapter->MaxTcbs, 0, 0);
2975}
2976#endif
2977
2978/*
2979 * sxg_allocate_complete -
2980 *
2981 * This routine is called when a memory allocation has completed.
2982 *
2983 * Arguments -
2984 * p_adapter_t - Our adapter structure
2985 * VirtualAddress - Memory virtual address
2986 * PhysicalAddress - Memory physical address
2987 * Length - Length of memory allocated (or 0)
2988 * Context - The type of buffer allocated
2989 *
2990 * Return
2991 * None.
2992 */
2993static void sxg_allocate_complete(p_adapter_t adapter,
2994 void *VirtualAddress,
2995 dma_addr_t PhysicalAddress,
2996 u32 Length, SXG_BUFFER_TYPE Context)
2997{
2998 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocCmp",
2999 adapter, VirtualAddress, Length, Context);
3000 ASSERT(adapter->AllocationsPending);
3001 --adapter->AllocationsPending;
3002
3003 switch (Context) {
3004
3005 case SXG_BUFFER_TYPE_RCV:
3006 sxg_allocate_rcvblock_complete(adapter,
3007 VirtualAddress,
3008 PhysicalAddress, Length);
3009 break;
3010 case SXG_BUFFER_TYPE_SGL:
3011 sxg_allocate_sgl_buffer_complete(adapter,
3012 (PSXG_SCATTER_GATHER)
3013 VirtualAddress,
3014 PhysicalAddress, Length);
3015 break;
3016 }
3017 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlocCmp",
3018 adapter, VirtualAddress, Length, Context);
3019}
3020
3021/*
3022 * sxg_allocate_buffer_memory - Shared memory allocation routine used for
3023 * synchronous and asynchronous buffer allocations
3024 *
3025 * Arguments -
3026 * adapter - A pointer to our adapter structure
3027 * Size - block size to allocate
3028 * BufferType - Type of buffer to allocate
3029 *
3030 * Return
3031 * int
3032 */
3033static int sxg_allocate_buffer_memory(p_adapter_t adapter,
3034 u32 Size, SXG_BUFFER_TYPE BufferType)
3035{
3036 int status;
3037 void * Buffer;
3038 dma_addr_t pBuffer;
3039
3040 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocMem",
3041 adapter, Size, BufferType, 0);
3042 // Grab the adapter lock and check the state.
3043 // If we're in anything other than INITIALIZING or
3044 // RUNNING state, fail. This is to prevent
3045 // allocations in an improper driver state
3046 spin_lock(&adapter->AdapterLock);
3047
3048 // Increment the AllocationsPending count while holding
3049 // the lock. Pause processing relies on this
3050 ++adapter->AllocationsPending;
3051 spin_unlock(&adapter->AdapterLock);
3052
3053 // At initialization time allocate resources synchronously.
3054 Buffer = pci_alloc_consistent(adapter->pcidev, Size, &pBuffer);
3055 if (Buffer == NULL) {
3056 spin_lock(&adapter->AdapterLock);
3057 // Decrement the AllocationsPending count while holding
3058 // the lock. Pause processing relies on this
3059 --adapter->AllocationsPending;
3060 spin_unlock(&adapter->AdapterLock);
3061 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlcMemF1",
3062 adapter, Size, BufferType, 0);
3063 return (STATUS_RESOURCES);
3064 }
3065 sxg_allocate_complete(adapter, Buffer, pBuffer, Size, BufferType);
3066 status = STATUS_SUCCESS;
3067
3068 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlocMem",
3069 adapter, Size, BufferType, status);
3070 return (status);
3071}
3072
3073/*
3074 * sxg_allocate_rcvblock_complete - Complete a receive descriptor block allocation
3075 *
3076 * Arguments -
3077 * adapter - A pointer to our adapter structure
3078 * RcvBlock - receive block virtual address
3079 * PhysicalAddress - Physical address
3080 * Length - Memory length
3081 *
3082 * Return
3083 *
3084 */
3085static void sxg_allocate_rcvblock_complete(p_adapter_t adapter,
3086 void * RcvBlock,
3087 dma_addr_t PhysicalAddress, u32 Length)
3088{
3089 u32 i;
3090 u32 BufferSize = adapter->ReceiveBufferSize;
3091 u64 Paddr;
3092 PSXG_RCV_BLOCK_HDR RcvBlockHdr;
3093 unsigned char *RcvDataBuffer;
3094 PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr;
3095 PSXG_RCV_DESCRIPTOR_BLOCK RcvDescriptorBlock;
3096 PSXG_RCV_DESCRIPTOR_BLOCK_HDR RcvDescriptorBlockHdr;
3097
3098 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlRcvBlk",
3099 adapter, RcvBlock, Length, 0);
3100 if (RcvBlock == NULL) {
3101 goto fail;
3102 }
3103 memset(RcvBlock, 0, Length);
3104 ASSERT((BufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
3105 (BufferSize == SXG_RCV_JUMBO_BUFFER_SIZE));
3106 ASSERT(Length == SXG_RCV_BLOCK_SIZE(BufferSize));
3107 // First, initialize the contained pool of receive data
3108 // buffers. This initialization requires NBL/NB/MDL allocations,
3109 // If any of them fail, free the block and return without
3110 // queueing the shared memory
3111 RcvDataBuffer = RcvBlock;
3112#if 0
3113 for (i = 0, Paddr = *PhysicalAddress;
3114 i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3115 i++, Paddr.LowPart += BufferSize, RcvDataBuffer += BufferSize)
3116#endif
3117 for (i = 0, Paddr = PhysicalAddress;
3118 i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3119 i++, Paddr += BufferSize, RcvDataBuffer += BufferSize) {
3120 //
3121 RcvDataBufferHdr =
3122 (PSXG_RCV_DATA_BUFFER_HDR) (RcvDataBuffer +
3123 SXG_RCV_DATA_BUFFER_HDR_OFFSET
3124 (BufferSize));
3125 RcvDataBufferHdr->VirtualAddress = RcvDataBuffer;
3126 RcvDataBufferHdr->PhysicalAddress = Paddr;
3127 RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM; // For FREE macro assertion
3128 RcvDataBufferHdr->Size =
3129 SXG_RCV_BUFFER_DATA_SIZE(BufferSize);
3130
3131 SXG_ALLOCATE_RCV_PACKET(adapter, RcvDataBufferHdr);
3132 if (RcvDataBufferHdr->SxgDumbRcvPacket == NULL)
3133 goto fail;
3134
3135 }
3136
3137 // Place this entire block of memory on the AllRcvBlocks queue so it can be
3138 // free later
3139 RcvBlockHdr =
3140 (PSXG_RCV_BLOCK_HDR) ((unsigned char *)RcvBlock +
3141 SXG_RCV_BLOCK_HDR_OFFSET(BufferSize));
3142 RcvBlockHdr->VirtualAddress = RcvBlock;
3143 RcvBlockHdr->PhysicalAddress = PhysicalAddress;
3144 spin_lock(&adapter->RcvQLock);
3145 adapter->AllRcvBlockCount++;
3146 InsertTailList(&adapter->AllRcvBlocks, &RcvBlockHdr->AllList);
3147 spin_unlock(&adapter->RcvQLock);
3148
3149 // Now free the contained receive data buffers that we initialized above
3150 RcvDataBuffer = RcvBlock;
3151 for (i = 0, Paddr = PhysicalAddress;
3152 i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3153 i++, Paddr += BufferSize, RcvDataBuffer += BufferSize) {
3154 RcvDataBufferHdr = (PSXG_RCV_DATA_BUFFER_HDR) (RcvDataBuffer +
3155 SXG_RCV_DATA_BUFFER_HDR_OFFSET
3156 (BufferSize));
3157 spin_lock(&adapter->RcvQLock);
3158 SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
3159 spin_unlock(&adapter->RcvQLock);
3160 }
3161
3162 // Locate the descriptor block and put it on a separate free queue
3163 RcvDescriptorBlock = (PSXG_RCV_DESCRIPTOR_BLOCK) ((unsigned char *)RcvBlock +
3164 SXG_RCV_DESCRIPTOR_BLOCK_OFFSET
3165 (BufferSize));
3166 RcvDescriptorBlockHdr =
3167 (PSXG_RCV_DESCRIPTOR_BLOCK_HDR) ((unsigned char *)RcvBlock +
3168 SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET
3169 (BufferSize));
3170 RcvDescriptorBlockHdr->VirtualAddress = RcvDescriptorBlock;
3171 RcvDescriptorBlockHdr->PhysicalAddress = Paddr;
3172 spin_lock(&adapter->RcvQLock);
3173 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter, RcvDescriptorBlockHdr);
3174 spin_unlock(&adapter->RcvQLock);
3175 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlRBlk",
3176 adapter, RcvBlock, Length, 0);
3177 return;
3178 fail:
3179 // Free any allocated resources
3180 if (RcvBlock) {
3181 RcvDataBuffer = RcvBlock;
3182 for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3183 i++, RcvDataBuffer += BufferSize) {
3184 RcvDataBufferHdr =
3185 (PSXG_RCV_DATA_BUFFER_HDR) (RcvDataBuffer +
3186 SXG_RCV_DATA_BUFFER_HDR_OFFSET
3187 (BufferSize));
3188 SXG_FREE_RCV_PACKET(RcvDataBufferHdr);
3189 }
3190 pci_free_consistent(adapter->pcidev,
3191 Length, RcvBlock, PhysicalAddress);
3192 }
3193 DBG_ERROR("%s: OUT OF RESOURCES\n", __FUNCTION__);
3194 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "RcvAFail",
3195 adapter, adapter->FreeRcvBufferCount,
3196 adapter->FreeRcvBlockCount, adapter->AllRcvBlockCount);
3197 adapter->Stats.NoMem++;
3198}
3199
3200/*
3201 * sxg_allocate_sgl_buffer_complete - Complete a SGL buffer allocation
3202 *
3203 * Arguments -
3204 * adapter - A pointer to our adapter structure
3205 * SxgSgl - SXG_SCATTER_GATHER buffer
3206 * PhysicalAddress - Physical address
3207 * Length - Memory length
3208 *
3209 * Return
3210 *
3211 */
3212static void sxg_allocate_sgl_buffer_complete(p_adapter_t adapter,
3213 PSXG_SCATTER_GATHER SxgSgl,
3214 dma_addr_t PhysicalAddress, u32 Length)
3215{
3216 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlSglCmp",
3217 adapter, SxgSgl, Length, 0);
3218 spin_lock(&adapter->SglQLock);
3219 adapter->AllSglBufferCount++;
3220 memset(SxgSgl, 0, sizeof(SXG_SCATTER_GATHER));
3221 SxgSgl->PhysicalAddress = PhysicalAddress; /* *PhysicalAddress; */
3222 SxgSgl->adapter = adapter; // Initialize backpointer once
3223 InsertTailList(&adapter->AllSglBuffers, &SxgSgl->AllList);
3224 spin_unlock(&adapter->SglQLock);
3225 SxgSgl->State = SXG_BUFFER_BUSY;
3226 SXG_FREE_SGL_BUFFER(adapter, SxgSgl, NULL);
3227 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlSgl",
3228 adapter, SxgSgl, Length, 0);
3229}
3230
3231static unsigned char temp_mac_address[6] = { 0x00, 0xab, 0xcd, 0xef, 0x12, 0x69 };
3232
3233static void sxg_adapter_set_hwaddr(p_adapter_t adapter)
3234{
3235// DBG_ERROR ("%s ENTER card->config_set[%x] port[%d] physport[%d] funct#[%d]\n", __FUNCTION__,
3236// card->config_set, adapter->port, adapter->physport, adapter->functionnumber);
3237//
3238// sxg_dbg_macaddrs(adapter);
3239
3240 memcpy(adapter->macaddr, temp_mac_address, sizeof(SXG_CONFIG_MAC));
3241// DBG_ERROR ("%s AFTER copying from config.macinfo into currmacaddr\n", __FUNCTION__);
3242// sxg_dbg_macaddrs(adapter);
3243 if (!(adapter->currmacaddr[0] ||
3244 adapter->currmacaddr[1] ||
3245 adapter->currmacaddr[2] ||
3246 adapter->currmacaddr[3] ||
3247 adapter->currmacaddr[4] || adapter->currmacaddr[5])) {
3248 memcpy(adapter->currmacaddr, adapter->macaddr, 6);
3249 }
3250 if (adapter->netdev) {
3251 memcpy(adapter->netdev->dev_addr, adapter->currmacaddr, 6);
3252 }
3253// DBG_ERROR ("%s EXIT port %d\n", __FUNCTION__, adapter->port);
3254 sxg_dbg_macaddrs(adapter);
3255
3256}
3257
3258static int sxg_mac_set_address(p_net_device dev, void * ptr)
3259{
3260#if XXXTODO
3261 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
3262 struct sockaddr *addr = ptr;
3263
3264 DBG_ERROR("%s ENTER (%s)\n", __FUNCTION__, adapter->netdev->name);
3265
3266 if (netif_running(dev)) {
3267 return -EBUSY;
3268 }
3269 if (!adapter) {
3270 return -EBUSY;
3271 }
3272 DBG_ERROR("sxg: %s (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
3273 __FUNCTION__, adapter->netdev->name, adapter->currmacaddr[0],
3274 adapter->currmacaddr[1], adapter->currmacaddr[2],
3275 adapter->currmacaddr[3], adapter->currmacaddr[4],
3276 adapter->currmacaddr[5]);
3277 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3278 memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len);
3279 DBG_ERROR("sxg: %s (%s) new %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
3280 __FUNCTION__, adapter->netdev->name, adapter->currmacaddr[0],
3281 adapter->currmacaddr[1], adapter->currmacaddr[2],
3282 adapter->currmacaddr[3], adapter->currmacaddr[4],
3283 adapter->currmacaddr[5]);
3284
3285 sxg_config_set(adapter, TRUE);
3286#endif
3287 return 0;
3288}
3289
3290/*****************************************************************************/
3291/************* SXG DRIVER FUNCTIONS (below) ********************************/
3292/*****************************************************************************/
3293
3294/*
3295 * sxg_initialize_adapter - Initialize adapter
3296 *
3297 * Arguments -
3298 * adapter - A pointer to our adapter structure
3299 *
3300 * Return
3301 * int
3302 */
3303static int sxg_initialize_adapter(p_adapter_t adapter)
3304{
3305 u32 RssIds, IsrCount;
3306 u32 i;
3307 int status;
3308
3309 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitAdpt",
3310 adapter, 0, 0, 0);
3311
3312 RssIds = 1; // XXXTODO SXG_RSS_CPU_COUNT(adapter);
3313 IsrCount = adapter->MsiEnabled ? RssIds : 1;
3314
3315 // Sanity check SXG_UCODE_REGS structure definition to
3316 // make sure the length is correct
3317 ASSERT(sizeof(SXG_UCODE_REGS) == SXG_REGISTER_SIZE_PER_CPU);
3318
3319 // Disable interrupts
3320 SXG_DISABLE_ALL_INTERRUPTS(adapter);
3321
3322 // Set MTU
3323 ASSERT((adapter->FrameSize == ETHERMAXFRAME) ||
3324 (adapter->FrameSize == JUMBOMAXFRAME));
3325 WRITE_REG(adapter->UcodeRegs[0].LinkMtu, adapter->FrameSize, TRUE);
3326
3327 // Set event ring base address and size
3328 WRITE_REG64(adapter,
3329 adapter->UcodeRegs[0].EventBase, adapter->PEventRings, 0);
3330 WRITE_REG(adapter->UcodeRegs[0].EventSize, EVENT_RING_SIZE, TRUE);
3331
3332 // Per-ISR initialization
3333 for (i = 0; i < IsrCount; i++) {
3334 u64 Addr;
3335 // Set interrupt status pointer
3336 Addr = adapter->PIsr + (i * sizeof(u32));
3337 WRITE_REG64(adapter, adapter->UcodeRegs[i].Isp, Addr, i);
3338 }
3339
3340 // XMT ring zero index
3341 WRITE_REG64(adapter,
3342 adapter->UcodeRegs[0].SPSendIndex,
3343 adapter->PXmtRingZeroIndex, 0);
3344
3345 // Per-RSS initialization
3346 for (i = 0; i < RssIds; i++) {
3347 // Release all event ring entries to the Microcode
3348 WRITE_REG(adapter->UcodeRegs[i].EventRelease, EVENT_RING_SIZE,
3349 TRUE);
3350 }
3351
3352 // Transmit ring base and size
3353 WRITE_REG64(adapter,
3354 adapter->UcodeRegs[0].XmtBase, adapter->PXmtRings, 0);
3355 WRITE_REG(adapter->UcodeRegs[0].XmtSize, SXG_XMT_RING_SIZE, TRUE);
3356
3357 // Receive ring base and size
3358 WRITE_REG64(adapter,
3359 adapter->UcodeRegs[0].RcvBase, adapter->PRcvRings, 0);
3360 WRITE_REG(adapter->UcodeRegs[0].RcvSize, SXG_RCV_RING_SIZE, TRUE);
3361
3362 // Populate the card with receive buffers
3363 sxg_stock_rcv_buffers(adapter);
3364
3365 // Initialize checksum offload capabilities. At the moment
3366 // we always enable IP and TCP receive checksums on the card.
3367 // Depending on the checksum configuration specified by the
3368 // user, we can choose to report or ignore the checksum
3369 // information provided by the card.
3370 WRITE_REG(adapter->UcodeRegs[0].ReceiveChecksum,
3371 SXG_RCV_TCP_CSUM_ENABLED | SXG_RCV_IP_CSUM_ENABLED, TRUE);
3372
3373 // Initialize the MAC, XAUI
3374 DBG_ERROR("sxg: %s ENTER sxg_initialize_link\n", __FUNCTION__);
3375 status = sxg_initialize_link(adapter);
3376 DBG_ERROR("sxg: %s EXIT sxg_initialize_link status[%x]\n", __FUNCTION__,
3377 status);
3378 if (status != STATUS_SUCCESS) {
3379 return (status);
3380 }
3381 // Initialize Dead to FALSE.
3382 // SlicCheckForHang or SlicDumpThread will take it from here.
3383 adapter->Dead = FALSE;
3384 adapter->PingOutstanding = FALSE;
3385
3386 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInit",
3387 adapter, 0, 0, 0);
3388 return (STATUS_SUCCESS);
3389}
3390
3391/*
3392 * sxg_fill_descriptor_block - Populate a descriptor block and give it to
3393 * the card. The caller should hold the RcvQLock
3394 *
3395 * Arguments -
3396 * adapter - A pointer to our adapter structure
3397 * RcvDescriptorBlockHdr - Descriptor block to fill
3398 *
3399 * Return
3400 * status
3401 */
3402static int sxg_fill_descriptor_block(p_adapter_t adapter,
3403 PSXG_RCV_DESCRIPTOR_BLOCK_HDR RcvDescriptorBlockHdr)
3404{
3405 u32 i;
3406 PSXG_RING_INFO RcvRingInfo = &adapter->RcvRingZeroInfo;
3407 PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr;
3408 PSXG_RCV_DESCRIPTOR_BLOCK RcvDescriptorBlock;
3409 PSXG_CMD RingDescriptorCmd;
3410 PSXG_RCV_RING RingZero = &adapter->RcvRings[0];
3411
3412 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "FilBlk",
3413 adapter, adapter->RcvBuffersOnCard,
3414 adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
3415
3416 ASSERT(RcvDescriptorBlockHdr);
3417
3418 // If we don't have the resources to fill the descriptor block,
3419 // return failure
3420 if ((adapter->FreeRcvBufferCount < SXG_RCV_DESCRIPTORS_PER_BLOCK) ||
3421 SXG_RING_FULL(RcvRingInfo)) {
3422 adapter->Stats.NoMem++;
3423 return (STATUS_FAILURE);
3424 }
3425 // Get a ring descriptor command
3426 SXG_GET_CMD(RingZero,
3427 RcvRingInfo, RingDescriptorCmd, RcvDescriptorBlockHdr);
3428 ASSERT(RingDescriptorCmd);
3429 RcvDescriptorBlockHdr->State = SXG_BUFFER_ONCARD;
3430 RcvDescriptorBlock =
3431 (PSXG_RCV_DESCRIPTOR_BLOCK) RcvDescriptorBlockHdr->VirtualAddress;
3432
3433 // Fill in the descriptor block
3434 for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK; i++) {
3435 SXG_GET_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
3436 ASSERT(RcvDataBufferHdr);
3437 SXG_REINIATIALIZE_PACKET(RcvDataBufferHdr->SxgDumbRcvPacket);
3438 RcvDataBufferHdr->State = SXG_BUFFER_ONCARD;
3439 RcvDescriptorBlock->Descriptors[i].VirtualAddress = (void *)RcvDataBufferHdr;
3440 RcvDescriptorBlock->Descriptors[i].PhysicalAddress =
3441 RcvDataBufferHdr->PhysicalAddress;
3442 }
3443 // Add the descriptor block to receive descriptor ring 0
3444 RingDescriptorCmd->Sgl = RcvDescriptorBlockHdr->PhysicalAddress;
3445
3446 // RcvBuffersOnCard is not protected via the receive lock (see
3447 // sxg_process_event_queue) We don't want to grap a lock every time a
3448 // buffer is returned to us, so we use atomic interlocked functions
3449 // instead.
3450 adapter->RcvBuffersOnCard += SXG_RCV_DESCRIPTORS_PER_BLOCK;
3451
3452 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DscBlk",
3453 RcvDescriptorBlockHdr,
3454 RingDescriptorCmd, RcvRingInfo->Head, RcvRingInfo->Tail);
3455
3456 WRITE_REG(adapter->UcodeRegs[0].RcvCmd, 1, true);
3457 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFilBlk",
3458 adapter, adapter->RcvBuffersOnCard,
3459 adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
3460 return (STATUS_SUCCESS);
3461}
3462
3463/*
3464 * sxg_stock_rcv_buffers - Stock the card with receive buffers
3465 *
3466 * Arguments -
3467 * adapter - A pointer to our adapter structure
3468 *
3469 * Return
3470 * None
3471 */
3472static void sxg_stock_rcv_buffers(p_adapter_t adapter)
3473{
3474 PSXG_RCV_DESCRIPTOR_BLOCK_HDR RcvDescriptorBlockHdr;
3475
3476 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "StockBuf",
3477 adapter, adapter->RcvBuffersOnCard,
3478 adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
3479 // First, see if we've got less than our minimum threshold of
3480 // receive buffers, there isn't an allocation in progress, and
3481 // we haven't exceeded our maximum.. get another block of buffers
3482 // None of this needs to be SMP safe. It's round numbers.
3483 if ((adapter->FreeRcvBufferCount < SXG_MIN_RCV_DATA_BUFFERS) &&
3484 (adapter->AllRcvBlockCount < SXG_MAX_RCV_BLOCKS) &&
3485 (adapter->AllocationsPending == 0)) {
3486 sxg_allocate_buffer_memory(adapter,
3487 SXG_RCV_BLOCK_SIZE(adapter->
3488 ReceiveBufferSize),
3489 SXG_BUFFER_TYPE_RCV);
3490 }
3491 // Now grab the RcvQLock lock and proceed
3492 spin_lock(&adapter->RcvQLock);
3493 while (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) {
3494 PLIST_ENTRY _ple;
3495
3496 // Get a descriptor block
3497 RcvDescriptorBlockHdr = NULL;
3498 if (adapter->FreeRcvBlockCount) {
3499 _ple = RemoveHeadList(&adapter->FreeRcvBlocks);
3500 RcvDescriptorBlockHdr = container_of(_ple, SXG_RCV_DESCRIPTOR_BLOCK_HDR, FreeList);
3501 adapter->FreeRcvBlockCount--;
3502 RcvDescriptorBlockHdr->State = SXG_BUFFER_BUSY;
3503 }
3504
3505 if (RcvDescriptorBlockHdr == NULL) {
3506 // Bail out..
3507 adapter->Stats.NoMem++;
3508 break;
3509 }
3510 // Fill in the descriptor block and give it to the card
3511 if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) ==
3512 STATUS_FAILURE) {
3513 // Free the descriptor block
3514 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter,
3515 RcvDescriptorBlockHdr);
3516 break;
3517 }
3518 }
3519 spin_unlock(&adapter->RcvQLock);
3520 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFilBlks",
3521 adapter, adapter->RcvBuffersOnCard,
3522 adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
3523}
3524
3525/*
3526 * sxg_complete_descriptor_blocks - Return descriptor blocks that have been
3527 * completed by the microcode
3528 *
3529 * Arguments -
3530 * adapter - A pointer to our adapter structure
3531 * Index - Where the microcode is up to
3532 *
3533 * Return
3534 * None
3535 */
3536static void sxg_complete_descriptor_blocks(p_adapter_t adapter, unsigned char Index)
3537{
3538 PSXG_RCV_RING RingZero = &adapter->RcvRings[0];
3539 PSXG_RING_INFO RcvRingInfo = &adapter->RcvRingZeroInfo;
3540 PSXG_RCV_DESCRIPTOR_BLOCK_HDR RcvDescriptorBlockHdr;
3541 PSXG_CMD RingDescriptorCmd;
3542
3543 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlks",
3544 adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail);
3545
3546 // Now grab the RcvQLock lock and proceed
3547 spin_lock(&adapter->RcvQLock);
3548 ASSERT(Index != RcvRingInfo->Tail);
3549 while (RcvRingInfo->Tail != Index) {
3550 //
3551 // Locate the current Cmd (ring descriptor entry), and
3552 // associated receive descriptor block, and advance
3553 // the tail
3554 //
3555 SXG_RETURN_CMD(RingZero,
3556 RcvRingInfo,
3557 RingDescriptorCmd, RcvDescriptorBlockHdr);
3558 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlk",
3559 RcvRingInfo->Head, RcvRingInfo->Tail,
3560 RingDescriptorCmd, RcvDescriptorBlockHdr);
3561
3562 // Clear the SGL field
3563 RingDescriptorCmd->Sgl = 0;
3564 // Attempt to refill it and hand it right back to the
3565 // card. If we fail to refill it, free the descriptor block
3566 // header. The card will be restocked later via the
3567 // RcvBuffersOnCard test
3568 if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) ==
3569 STATUS_FAILURE) {
3570 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter,
3571 RcvDescriptorBlockHdr);
3572 }
3573 }
3574 spin_unlock(&adapter->RcvQLock);
3575 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XCRBlks",
3576 adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail);
3577}
3578
3579
3580static struct pci_driver sxg_driver = {
3581 .name = DRV_NAME,
3582 .id_table = sxg_pci_tbl,
3583 .probe = sxg_entry_probe,
3584 .remove = sxg_entry_remove,
3585#if SXG_POWER_MANAGEMENT_ENABLED
3586 .suspend = sxgpm_suspend,
3587 .resume = sxgpm_resume,
3588#endif
3589/* .shutdown = slic_shutdown, MOOK_INVESTIGATE */
3590};
3591
3592static int __init sxg_module_init(void)
3593{
3594 sxg_init_driver();
3595
3596 if (debug >= 0)
3597 sxg_debug = debug;
3598
3599 return pci_register_driver(&sxg_driver);
3600}
3601
3602static void __exit sxg_module_cleanup(void)
3603{
3604 pci_unregister_driver(&sxg_driver);
3605}
3606
3607module_init(sxg_module_init);
3608module_exit(sxg_module_cleanup);
diff --git a/drivers/staging/sxg/sxg.h b/drivers/staging/sxg/sxg.h
new file mode 100644
index 000000000000..844ca56f2800
--- /dev/null
+++ b/drivers/staging/sxg/sxg.h
@@ -0,0 +1,773 @@
1/**************************************************************************
2 *
3 * Copyright © 2000-2008 Alacritech, Inc. All rights reserved.
4 *
5 * $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
22 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * The views and conclusions contained in the software and documentation
32 * are those of the authors and should not be interpreted as representing
33 * official policies, either expressed or implied, of Alacritech, Inc.
34 *
35 **************************************************************************/
36
37/*
38 * FILENAME: sxg.h
39 *
40 * This is the base set of header definitions for the SXG driver.
41 */
42#ifndef __SXG_DRIVER_H__
43#define __SXG_DRIVER_H__
44
45#define p_net_device struct net_device *
46// SXG_STATS - Probably move these to someplace where
47// the slicstat (sxgstat?) program can get them.
48typedef struct _SXG_STATS {
49 // Xmt
50 u32 XmtNBL; // Offload send NBL count
51 u64 DumbXmtBytes; // Dumbnic send bytes
52 u64 SlowXmtBytes; // Slowpath send bytes
53 u64 FastXmtBytes; // Fastpath send bytes
54 u64 DumbXmtPkts; // Dumbnic send packets
55 u64 SlowXmtPkts; // Slowpath send packets
56 u64 FastXmtPkts; // Fastpath send packets
57 u64 DumbXmtUcastPkts; // directed packets
58 u64 DumbXmtMcastPkts; // Multicast packets
59 u64 DumbXmtBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV
60 u64 DumbXmtUcastBytes; // OID_GEN_DIRECTED_BYTES_XMIT
61 u64 DumbXmtMcastBytes; // OID_GEN_MULTICAST_BYTES_XMIT
62 u64 DumbXmtBcastBytes; // OID_GEN_BROADCAST_BYTES_XMIT
63 u64 XmtErrors; // OID_GEN_XMIT_ERROR
64 u64 XmtDiscards; // OID_GEN_XMIT_DISCARDS
65 u64 XmtOk; // OID_GEN_XMIT_OK
66 u64 XmtQLen; // OID_GEN_TRANSMIT_QUEUE_LENGTH
67 u64 XmtZeroFull; // Transmit ring zero full
68 // Rcv
69 u32 RcvNBL; // Offload recieve NBL count
70 u64 DumbRcvBytes; // dumbnic recv bytes
71 u64 DumbRcvUcastBytes; // OID_GEN_DIRECTED_BYTES_RCV
72 u64 DumbRcvMcastBytes; // OID_GEN_MULTICAST_BYTES_RCV
73 u64 DumbRcvBcastBytes; // OID_GEN_BROADCAST_BYTES_RCV
74 u64 SlowRcvBytes; // Slowpath recv bytes
75 u64 FastRcvBytes; // Fastpath recv bytes
76 u64 DumbRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV
77 u64 DumbRcvTcpPkts; // See SxgCollectStats
78 u64 DumbRcvUcastPkts; // directed packets
79 u64 DumbRcvMcastPkts; // Multicast packets
80 u64 DumbRcvBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV
81 u64 SlowRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV
82 u64 RcvErrors; // OID_GEN_RCV_ERROR
83 u64 RcvDiscards; // OID_GEN_RCV_DISCARDS
84 u64 RcvNoBuffer; // OID_GEN_RCV_NO_BUFFER
85 u64 PdqFull; // Processed Data Queue Full
86 u64 EventRingFull; // Event ring full
87 // Verbose stats
88 u64 MaxSends; // Max sends outstanding
89 u64 NoSglBuf; // SGL buffer allocation failure
90 u64 SglFail; // NDIS SGL failure
91 u64 SglAsync; // NDIS SGL failure
92 u64 NoMem; // Memory allocation failure
93 u64 NumInts; // Interrupts
94 u64 FalseInts; // Interrupt with ISR == 0
95 u64 XmtDrops; // No sahara DRAM buffer for xmt
96 // Sahara receive status
97 u64 TransportCsum; // SXG_RCV_STATUS_TRANSPORT_CSUM
98 u64 TransportUflow; // SXG_RCV_STATUS_TRANSPORT_UFLOW
99 u64 TransportHdrLen; // SXG_RCV_STATUS_TRANSPORT_HDRLEN
100 u64 NetworkCsum; // SXG_RCV_STATUS_NETWORK_CSUM:
101 u64 NetworkUflow; // SXG_RCV_STATUS_NETWORK_UFLOW:
102 u64 NetworkHdrLen; // SXG_RCV_STATUS_NETWORK_HDRLEN:
103 u64 Parity; // SXG_RCV_STATUS_PARITY
104 u64 LinkParity; // SXG_RCV_STATUS_LINK_PARITY:
105 u64 LinkEarly; // SXG_RCV_STATUS_LINK_EARLY:
106 u64 LinkBufOflow; // SXG_RCV_STATUS_LINK_BUFOFLOW:
107 u64 LinkCode; // SXG_RCV_STATUS_LINK_CODE:
108 u64 LinkDribble; // SXG_RCV_STATUS_LINK_DRIBBLE:
109 u64 LinkCrc; // SXG_RCV_STATUS_LINK_CRC:
110 u64 LinkOflow; // SXG_RCV_STATUS_LINK_OFLOW:
111 u64 LinkUflow; // SXG_RCV_STATUS_LINK_UFLOW:
112} SXG_STATS, *PSXG_STATS;
113
114
115/****************************************************************************
116 * DUMB-NIC Send path definitions
117 ****************************************************************************/
118
119#define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb) { \
120 ASSERT(_skb); \
121 dev_kfree_skb_irq(_skb); \
122}
123
124#define SXG_DROP_DUMB_SEND(_pAdapt, _skb) { \
125 ASSERT(_skb); \
126 dev_kfree_skb(_skb); \
127}
128
129// Locate current receive header buffer location. Use this
130// instead of RcvDataHdr->VirtualAddress since the data
131// may have been offset by SXG_ADVANCE_MDL_OFFSET
132#define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr) (_RcvDataHdr)->skb->data
133
134/************************************************************************
135 * Dumb-NIC receive processing
136 ************************************************************************/
137// Define an SXG_PACKET as an NDIS_PACKET
138#define PSXG_PACKET struct sk_buff *
139// Indications array size
140#define SXG_RCV_ARRAYSIZE 64
141
142#define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr) { \
143 struct sk_buff * skb; \
144 skb = alloc_skb(2048, GFP_ATOMIC); \
145 if (skb) { \
146 (_RcvDataBufferHdr)->skb = skb; \
147 skb->next = NULL; \
148 } else { \
149 (_RcvDataBufferHdr)->skb = NULL; \
150 } \
151}
152
153#define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) { \
154 if((_RcvDataBufferHdr)->skb) { \
155 dev_kfree_skb((_RcvDataBufferHdr)->skb); \
156 } \
157}
158
159// Macro to add a NDIS_PACKET to an indication array
160// If we fill up our array of packet pointers, then indicate this
161// block up now and start on a new one.
162#define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, _NumPackets) { \
163 (_IndicationList)[_NumPackets] = (_Packet); \
164 (_NumPackets)++; \
165 if((_NumPackets) == SXG_RCV_ARRAYSIZE) { \
166 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
167 (_NumPackets), 0, 0, 0); \
168 netif_rx((_IndicationList),(_NumPackets)); \
169 (_NumPackets) = 0; \
170 } \
171}
172
173#define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) { \
174 if(_NumPackets) { \
175 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
176 (_NumPackets), 0, 0, 0); \
177 netif_rx((_IndicationList),(_NumPackets)); \
178 (_NumPackets) = 0; \
179 } \
180}
181
182#define SXG_REINIATIALIZE_PACKET(_Packet) \
183 {} /*_NdisReinitializePacket(_Packet)*/ /* this is not necessary with an skb */
184
185// Definitions to initialize Dumb-nic Receive NBLs
186#define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((PSXG_RCV_NBL_RESERVED)((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
187
188#define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \
189 NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
190
191#define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) { \
192 NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz)); \
193 NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type)); \
194 NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function)); \
195}
196
197#define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) { \
198 NDIS_PACKET_8021Q_INFO _Packet8021qInfo; \
199 _Packet8021qInfo.TagHeader.VlanId = (_VlanId); \
200 _Packet8021qInfo.TagHeader.UserPriority = (_Priority); \
201 NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) = \
202 _Packet8021qInfo.Value; \
203}
204
205#define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) { \
206 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv", \
207 (_RcvDataBufferHdr), (_Packet), \
208 (_Event)->Status, 0); \
209 ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size); \
210 Packet->len = (_Event)->Length; \
211}
212
213///////////////////////////////////////////////////////////////////////////////
214// Macros to free a receive data buffer and receive data descriptor block
215///////////////////////////////////////////////////////////////////////////////
216// NOTE - Lock must be held with RCV macros
217#define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
218 PLIST_ENTRY _ple; \
219 _Hdr = NULL; \
220 if((_pAdapt)->FreeRcvBufferCount) { \
221 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers))); \
222 _ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers); \
223 (_Hdr) = container_of(_ple, SXG_RCV_DATA_BUFFER_HDR, FreeList); \
224 (_pAdapt)->FreeRcvBufferCount--; \
225 ASSERT((_Hdr)->State == SXG_BUFFER_FREE); \
226 } \
227}
228
229#define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
230 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr", \
231 (_Hdr), (_pAdapt)->FreeRcvBufferCount, \
232 (_Hdr)->State, (_Hdr)->VirtualAddress); \
233/* SXG_RESTORE_MDL_OFFSET(_Hdr); */ \
234 (_pAdapt)->FreeRcvBufferCount++; \
235 ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) >= (_pAdapt)->FreeRcvBufferCount); \
236 ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
237 (_Hdr)->State = SXG_BUFFER_FREE; \
238 InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList)); \
239}
240
241#define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) { \
242 ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
243 (_Hdr)->State = SXG_BUFFER_FREE; \
244 (_pAdapt)->FreeRcvBlockCount++; \
245 ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount); \
246 InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList); \
247}
248
249// SGL macros
250#define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) { \
251 spin_lock(&(_pAdapt)->SglQLock); \
252 (_pAdapt)->FreeSglBufferCount++; \
253 ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount);\
254 ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE)); \
255 (_Sgl)->State = SXG_BUFFER_FREE; \
256 InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList); \
257 spin_unlock(&(_pAdapt)->SglQLock); \
258}
259
260// Get an SGL buffer from the free queue. The first part of this macro
261// attempts to keep ahead of buffer depletion by allocating more when
262// we hit a minimum threshold. Note that we don't grab the lock
263// until after that. We're dealing with round numbers here, so we don't need to,
264// and not grabbing it avoids a possible double-trip.
265#define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl) { \
266 PLIST_ENTRY _ple; \
267 if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \
268 (_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) && \
269 (_pAdapt->AllocationsPending == 0)) { \
270 sxg_allocate_buffer_memory(_pAdapt, \
271 (sizeof(SXG_SCATTER_GATHER) + SXG_SGL_BUF_SIZE),\
272 SXG_BUFFER_TYPE_SGL); \
273 } \
274 _Sgl = NULL; \
275 spin_lock(&(_pAdapt)->SglQLock); \
276 if((_pAdapt)->FreeSglBufferCount) { \
277 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers))); \
278 _ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers); \
279 (_Sgl) = container_of(_ple, SXG_SCATTER_GATHER, FreeList); \
280 (_pAdapt)->FreeSglBufferCount--; \
281 ASSERT((_Sgl)->State == SXG_BUFFER_FREE); \
282 (_Sgl)->State = SXG_BUFFER_BUSY; \
283 (_Sgl)->pSgl = NULL; \
284 } \
285 spin_unlock(&(_pAdapt)->SglQLock); \
286}
287
288//
289// SXG_MULTICAST_ADDRESS
290//
291// Linked list of multicast addresses.
292typedef struct _SXG_MULTICAST_ADDRESS {
293 unsigned char Address[6];
294 struct _SXG_MULTICAST_ADDRESS *Next;
295} SXG_MULTICAST_ADDRESS, *PSXG_MULTICAST_ADDRESS;
296
297// Structure to maintain chimney send and receive buffer queues.
298// This structure maintains NET_BUFFER_LIST queues that are
299// given to us via the Chimney MiniportTcpOffloadSend and
300// MiniportTcpOffloadReceive routines. This structure DOES NOT
301// manage our data buffer queue
302typedef struct _SXG_BUFFER_QUEUE {
303 u32 Type; // Slow or fast - See below
304 u32 Direction; // Xmt or Rcv
305 u32 Bytes; // Byte count
306 u32 * Head; // Send queue head
307 u32 * Tail; // Send queue tail
308// PNET_BUFFER_LIST NextNBL; // Short cut - next NBL
309// PNET_BUFFER NextNB; // Short cut - next NB
310} SXG_BUFFER_QUEUE, *PSXG_BUFFER_QUEUE;
311
312#define SXG_SLOW_SEND_BUFFER 0
313#define SXG_FAST_SEND_BUFFER 1
314#define SXG_RECEIVE_BUFFER 2
315
316#define SXG_INIT_BUFFER(_Buffer, _Type) { \
317 (_Buffer)->Type = (_Type); \
318 if((_Type) == SXG_RECEIVE_BUFFER) { \
319 (_Buffer)->Direction = 0; \
320 } else { \
321 (_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE; \
322 } \
323 (_Buffer)->Bytes = 0; \
324 (_Buffer)->Head = NULL; \
325 (_Buffer)->Tail = NULL; \
326}
327
328
329#define SXG_RSS_CPU_COUNT(_pAdapt) \
330 ((_pAdapt)->RssEnabled ? NR_CPUS : 1)
331
332/****************************************************************************
333 * DRIVER and ADAPTER structures
334 ****************************************************************************/
335
336// Adapter states - These states closely match the adapter states
337// documented in the DDK (with a few exceptions).
338typedef enum _SXG_STATE {
339 SXG_STATE_INITIALIZING, // Initializing
340 SXG_STATE_BOOTDIAG, // Boot-Diagnostic mode
341 SXG_STATE_PAUSING, // Pausing
342 SXG_STATE_PAUSED, // Paused
343 SXG_STATE_RUNNING, // Running
344 SXG_STATE_RESETTING, // Reset in progress
345 SXG_STATE_SLEEP, // Sleeping
346 SXG_STATE_DIAG, // Diagnostic mode
347 SXG_STATE_HALTING, // Halting
348 SXG_STATE_HALTED, // Down or not-initialized
349 SXG_STATE_SHUTDOWN // shutdown
350} SXG_STATE, *PSXG_STATE;
351
352// Link state
353typedef enum _SXG_LINK_STATE {
354 SXG_LINK_DOWN,
355 SXG_LINK_UP
356} SXG_LINK_STATE, *PSXG_LINK_STATE;
357
358// Link initialization timeout in 100us units
359#define SXG_LINK_TIMEOUT 100000 // 10 Seconds - REDUCE!
360
361
362// Microcode file selection codes
363typedef enum _SXG_UCODE_SEL {
364 SXG_UCODE_SAHARA, // Sahara ucode
365 SXG_UCODE_SDIAGCPU, // Sahara CPU diagnostic ucode
366 SXG_UCODE_SDIAGSYS // Sahara system diagnostic ucode
367} SXG_UCODE_SEL;
368
369
370#define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
371#define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
372
373// This probably lives in a proto.h file. Move later
374#define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
375#define SXG_BROADCAST_PACKET(_pether) ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
376 (*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
377
378// For DbgPrints
379#define SXG_ID DPFLTR_IHVNETWORK_ID
380#define SXG_ERROR DPFLTR_ERROR_LEVEL
381
382//
383// SXG_DRIVER structure -
384//
385// contains information about the sxg driver. There is only
386// one of these, and it is defined as a global.
387typedef struct _SXG_DRIVER {
388 struct _adapter_t *Adapters; // Linked list of adapters
389 ushort AdapterID; // Maintain unique adapter ID
390} SXG_DRIVER, *PSXG_DRIVER;
391
392#ifdef STATUS_SUCCESS
393#undef STATUS_SUCCESS
394#endif
395
396#define STATUS_SUCCESS 0
397#define STATUS_PENDING 0
398#define STATUS_FAILURE -1
399#define STATUS_ERROR -2
400#define STATUS_NOT_SUPPORTED -3
401#define STATUS_BUFFER_TOO_SHORT -4
402#define STATUS_RESOURCES -5
403
404#define SLIC_MAX_CARDS 32
405#define SLIC_MAX_PORTS 4 /* Max # of ports per card */
406#if SLIC_DUMP_ENABLED
407// Dump buffer size
408//
409// This cannot be bigger than the max DMA size the card supports,
410// given the current code structure in the host and ucode.
411// Mojave supports 16K, Oasis supports 16K-1, so
412// just set this at 15K, shouldnt make that much of a diff.
413#define DUMP_BUF_SIZE 0x3C00
414#endif
415
416#define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
417#define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
418
419typedef struct _mcast_address_t
420{
421 unsigned char address[6];
422 struct _mcast_address_t *next;
423} mcast_address_t, *p_mcast_address_t;
424
425#define CARD_DOWN 0x00000000
426#define CARD_UP 0x00000001
427#define CARD_FAIL 0x00000002
428#define CARD_DIAG 0x00000003
429#define CARD_SLEEP 0x00000004
430
431#define ADAPT_DOWN 0x00
432#define ADAPT_UP 0x01
433#define ADAPT_FAIL 0x02
434#define ADAPT_RESET 0x03
435#define ADAPT_SLEEP 0x04
436
437#define ADAPT_FLAGS_BOOTTIME 0x0001
438#define ADAPT_FLAGS_IS64BIT 0x0002
439#define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004
440#define ADAPT_FLAGS_FIBERMEDIA 0x0008
441#define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010
442#define ADAPT_FLAGS_INT_REGISTERED 0x0020
443#define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040
444#define ADAPT_FLAGS_STATS_TIMER_SET 0x0080
445#define ADAPT_FLAGS_RESET_TIMER_SET 0x0100
446
447#define LINK_DOWN 0x00
448#define LINK_CONFIG 0x01
449#define LINK_UP 0x02
450
451#define LINK_10MB 0x00
452#define LINK_100MB 0x01
453#define LINK_AUTOSPEED 0x02
454#define LINK_1000MB 0x03
455#define LINK_10000MB 0x04
456
457#define LINK_HALFD 0x00
458#define LINK_FULLD 0x01
459#define LINK_AUTOD 0x02
460
461#define MAC_DIRECTED 0x00000001
462#define MAC_BCAST 0x00000002
463#define MAC_MCAST 0x00000004
464#define MAC_PROMISC 0x00000008
465#define MAC_LOOPBACK 0x00000010
466#define MAC_ALLMCAST 0x00000020
467
468#define SLIC_DUPLEX(x) ((x==LINK_FULLD) ? "FDX" : "HDX")
469#define SLIC_SPEED(x) ((x==LINK_100MB) ? "100Mb" : ((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
470#define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up ")
471#define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
472#define SLIC_CARD_STATE(x) ((x==CARD_UP) ? "UP" : "Down")
473
474
475typedef struct _ether_header
476{
477 unsigned char ether_dhost[6];
478 unsigned char ether_shost[6];
479 ushort ether_type;
480} ether_header, *p_ether_header;
481
482
483#define NUM_CFG_SPACES 2
484#define NUM_CFG_REGS 64
485
486typedef struct _physcard_t
487{
488 struct _adapter_t *adapter[SLIC_MAX_PORTS];
489 struct _physcard_t *next;
490 unsigned int adapters_allocd;
491} physcard_t, *p_physcard_t;
492
493typedef struct _sxgbase_driver
494{
495 spinlock_t driver_lock;
496 unsigned long flags; /* irqsave for spinlock */
497 u32 num_sxg_cards;
498 u32 num_sxg_ports;
499 u32 num_sxg_ports_active;
500 u32 dynamic_intagg;
501 p_physcard_t phys_card;
502} sxgbase_driver_t;
503
504
505typedef struct _adapter_t
506{
507 void * ifp;
508 unsigned int port;
509 p_physcard_t physcard;
510 unsigned int physport;
511 unsigned int cardindex;
512 unsigned int card_size;
513 unsigned int chipid;
514 unsigned int busnumber;
515 unsigned int slotnumber;
516 unsigned int functionnumber;
517 ushort vendid;
518 ushort devid;
519 ushort subsysid;
520 u32 irq;
521
522 void * sxg_adapter;
523 u32 nBusySend;
524
525 void __iomem * base_addr;
526 u32 memorylength;
527 u32 drambase;
528 u32 dramlength;
529 unsigned int queues_initialized;
530 unsigned int allocated;
531 unsigned int activated;
532 u32 intrregistered;
533 unsigned int isp_initialized;
534 unsigned int gennumber;
535 u32 curaddrupper;
536 u32 isrcopy;
537 unsigned char state;
538 unsigned char linkstate;
539 unsigned char linkspeed;
540 unsigned char linkduplex;
541 unsigned int flags;
542 unsigned char macaddr[6];
543 unsigned char currmacaddr[6];
544 u32 macopts;
545 ushort devflags_prev;
546 u64 mcastmask;
547 p_mcast_address_t mcastaddrs;
548 struct timer_list pingtimer;
549 u32 pingtimerset;
550 struct timer_list statstimer;
551 u32 statstimerset;
552 struct timer_list vpci_timer;
553 u32 vpci_timerset;
554 struct timer_list loadtimer;
555 u32 loadtimerset;
556
557 u32 xmitq_full;
558 u32 all_reg_writes;
559 u32 icr_reg_writes;
560 u32 isr_reg_writes;
561 u32 error_interrupts;
562 u32 error_rmiss_interrupts;
563 u32 rx_errors;
564 u32 rcv_drops;
565 u32 rcv_interrupts;
566 u32 xmit_interrupts;
567 u32 linkevent_interrupts;
568 u32 upr_interrupts;
569 u32 num_isrs;
570 u32 false_interrupts;
571 u32 tx_packets;
572 u32 xmit_completes;
573 u32 tx_drops;
574 u32 rcv_broadcasts;
575 u32 rcv_multicasts;
576 u32 rcv_unicasts;
577 u32 max_isr_rcvs;
578 u32 max_isr_xmits;
579 u32 rcv_interrupt_yields;
580 u32 intagg_period;
581 struct net_device_stats stats;
582 u32 * MiniportHandle; // Our miniport handle
583 SXG_STATE State; // Adapter state
584 SXG_LINK_STATE LinkState; // Link state
585 u64 LinkSpeed; // Link Speed
586 u32 PowerState; // NDIS power state
587 struct _adapter_t *Next; // Linked list
588 ushort AdapterID; // 1..n
589 unsigned char MacAddr[6]; // Our permanent HW mac address
590 unsigned char CurrMacAddr[6]; // Our Current mac address
591 p_net_device netdev;
592 p_net_device next_netdevice;
593 struct pci_dev * pcidev;
594
595 PSXG_MULTICAST_ADDRESS MulticastAddrs; // Multicast list
596 u64 MulticastMask; // Multicast mask
597 u32 * InterruptHandle; // Register Interrupt handle
598 u32 InterruptLevel; // From Resource list
599 u32 InterruptVector; // From Resource list
600 spinlock_t AdapterLock; /* Serialize access adapter routines */
601 spinlock_t Bit64RegLock; /* For writing 64-bit addresses */
602 PSXG_HW_REGS HwRegs; // Sahara HW Register Memory (BAR0/1)
603 PSXG_UCODE_REGS UcodeRegs; // Microcode Register Memory (BAR2/3)
604 PSXG_TCB_REGS TcbRegs; // Same as Ucode regs - See sxghw.h
605 ushort ResetDpcCount; // For timeout
606 ushort RssDpcCount; // For timeout
607 ushort VendorID; // Vendor ID
608 ushort DeviceID; // Device ID
609 ushort SubSystemID; // Sub-System ID
610 ushort FrameSize; // Maximum frame size
611 u32 * DmaHandle; // NDIS DMA handle
612 u32 * PacketPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out
613 u32 * BufferPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out
614 u32 MacFilter; // NDIS MAC Filter
615 ushort IpId; // For slowpath
616 PSXG_EVENT_RING EventRings; // Host event rings. 1/CPU to 16 max
617 dma_addr_t PEventRings; // Physical address
618 u32 NextEvent[SXG_MAX_RSS]; // Current location in ring
619 dma_addr_t PTcbBuffers; // TCB Buffers - physical address
620 dma_addr_t PTcbCompBuffers; // TCB Composite Buffers - phys addr
621 PSXG_XMT_RING XmtRings; // Transmit rings
622 dma_addr_t PXmtRings; // Transmit rings - physical address
623 SXG_RING_INFO XmtRingZeroInfo; // Transmit ring 0 info
624 spinlock_t XmtZeroLock; /* Transmit ring 0 lock */
625 u32 * XmtRingZeroIndex; // Shared XMT ring 0 index
626 dma_addr_t PXmtRingZeroIndex; // Shared XMT ring 0 index - physical
627 LIST_ENTRY FreeProtocolHeaders;// Free protocol headers
628 u32 FreeProtoHdrCount; // Count
629 void * ProtocolHeaders; // Block of protocol header
630 dma_addr_t PProtocolHeaders; // Block of protocol headers - phys
631
632 PSXG_RCV_RING RcvRings; // Receive rings
633 dma_addr_t PRcvRings; // Receive rings - physical address
634 SXG_RING_INFO RcvRingZeroInfo; // Receive ring 0 info
635
636 u32 * Isr; // Interrupt status register
637 dma_addr_t PIsr; // ISR - physical address
638 u32 IsrCopy[SXG_MAX_RSS]; // Copy of ISR
639 ushort InterruptsEnabled; // Bitmask of enabled vectors
640 unsigned char * IndirectionTable; // RSS indirection table
641 dma_addr_t PIndirectionTable; // Physical address
642 ushort RssTableSize; // From NDIS_RECEIVE_SCALE_PARAMETERS
643 ushort HashKeySize; // From NDIS_RECEIVE_SCALE_PARAMETERS
644 unsigned char HashSecretKey[40]; // rss key
645 u32 HashInformation;
646 // Receive buffer queues
647 spinlock_t RcvQLock; /* Receive Queue Lock */
648 LIST_ENTRY FreeRcvBuffers; // Free SXG_DATA_BUFFER queue
649 LIST_ENTRY FreeRcvBlocks; // Free SXG_RCV_DESCRIPTOR_BLOCK Q
650 LIST_ENTRY AllRcvBlocks; // All SXG_RCV_BLOCKs
651 ushort FreeRcvBufferCount; // Number of free rcv data buffers
652 ushort FreeRcvBlockCount; // # of free rcv descriptor blocks
653 ushort AllRcvBlockCount; // Number of total receive blocks
654 ushort ReceiveBufferSize; // SXG_RCV_DATA/JUMBO_BUFFER_SIZE only
655 u32 AllocationsPending; // Receive allocation pending
656 u32 RcvBuffersOnCard; // SXG_DATA_BUFFERS owned by card
657 // SGL buffers
658 spinlock_t SglQLock; /* SGL Queue Lock */
659 LIST_ENTRY FreeSglBuffers; // Free SXG_SCATTER_GATHER
660 LIST_ENTRY AllSglBuffers; // All SXG_SCATTER_GATHER
661 ushort FreeSglBufferCount; // Number of free SGL buffers
662 ushort AllSglBufferCount; // Number of total SGL buffers
663 u32 CurrentTime; // Tick count
664 u32 FastpathConnections;// # of fastpath connections
665 // Various single-bit flags:
666 u32 BasicAllocations:1; // Locks and listheads
667 u32 IntRegistered:1; // Interrupt registered
668 u32 PingOutstanding:1; // Ping outstanding to card
669 u32 Dead:1; // Card dead
670 u32 DumpDriver:1; // OID_SLIC_DRIVER_DUMP request
671 u32 DumpCard:1; // OID_SLIC_CARD_DUMP request
672 u32 DumpCmdRunning:1; // Dump command in progress
673 u32 DebugRunning:1; // AGDB debug in progress
674 u32 JumboEnabled:1; // Jumbo frames enabled
675 u32 MsiEnabled:1; // MSI interrupt enabled
676 u32 RssEnabled:1; // RSS Enabled
677 u32 FailOnBadEeprom:1; // Fail on Bad Eeprom
678 u32 DiagStart:1; // Init adapter for diagnostic start
679 // Stats
680 u32 PendingRcvCount; // Outstanding rcv indications
681 u32 PendingXmtCount; // Outstanding send requests
682 SXG_STATS Stats; // Statistics
683 u32 ReassBufs; // Number of reassembly buffers
684 // Card Crash Info
685 ushort CrashLocation; // Microcode crash location
686 unsigned char CrashCpu; // Sahara CPU ID
687 // Diagnostics
688 // PDIAG_CMD DiagCmds; // List of free diagnostic commands
689 // PDIAG_BUFFER DiagBuffers; // List of free diagnostic buffers
690 // PDIAG_REQ DiagReqQ; // List of outstanding (asynchronous) diag requests
691 // u32 DiagCmdTimeout; // Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var?
692 // unsigned char DiagDmaDesc[DMA_CPU_CTXS]; // Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx)
693
694 /////////////////////////////////////////////////////////////////////
695 // Put preprocessor-conditional fields at the end so we don't
696 // have to recompile sxgdbg everytime we reconfigure the driver
697 /////////////////////////////////////////////////////////////////////
698 void * PendingSetRss; // Pending RSS parameter change
699 u32 IPv4HdrSize; // Shared 5.2/6.0 encap param
700 unsigned char * InterruptInfo; // Allocated by us during AddDevice
701#if defined(CONFIG_X86)
702 u32 AddrUpper; // Upper 32 bits of 64-bit register
703#endif
704 //#if SXG_FAILURE_DUMP
705 // NDIS_EVENT DumpThreadEvent; // syncronize dump thread
706 // BOOLEAN DumpThreadRunning; // termination flag
707 // PSXG_DUMP_CMD DumpBuffer; // 68k - Cmd and Buffer
708 // dma_addr_t PDumpBuffer; // Physical address
709 //#endif // SXG_FAILURE_DUMP
710
711} adapter_t, *p_adapter_t;
712
713#if SLIC_DUMP_ENABLED
714#define SLIC_DUMP_REQUESTED 1
715#define SLIC_DUMP_IN_PROGRESS 2
716#define SLIC_DUMP_DONE 3
717
718/****************************************************************************
719 *
720 * Microcode crash information structure. This
721 * structure is written out to the card's SRAM when the microcode panic's.
722 *
723 ****************************************************************************/
724typedef struct _slic_crash_info {
725 ushort cpu_id;
726 ushort crash_pc;
727} slic_crash_info, *p_slic_crash_info;
728
729#define CRASH_INFO_OFFSET 0x155C
730
731#endif
732
733#define UPDATE_STATS(largestat, newstat, oldstat) \
734{ \
735 if ((newstat) < (oldstat)) \
736 (largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1)); \
737 else \
738 (largestat) += ((newstat) - (oldstat)); \
739}
740
741#define UPDATE_STATS_GB(largestat, newstat, oldstat) \
742{ \
743 (largestat) += ((newstat) - (oldstat)); \
744}
745
746#define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result) \
747{ \
748 _Result = TRUE; \
749 if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB)) \
750 _Result = FALSE; \
751 if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4]))) \
752 _Result = FALSE; \
753}
754
755#define ETHERMAXFRAME 1514
756#define JUMBOMAXFRAME 9014
757
758#if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
759#define SXG_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
760#define SXG_GET_ADDR_HIGH(_addr) (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
761#else
762#define SXG_GET_ADDR_LOW(_addr) (u32)_addr
763#define SXG_GET_ADDR_HIGH(_addr) (u32)0
764#endif
765
766#define FLUSH TRUE
767#define DONT_FLUSH FALSE
768
769#define SIOCSLICDUMPCARD SIOCDEVPRIVATE+9
770#define SIOCSLICSETINTAGG SIOCDEVPRIVATE+10
771#define SIOCSLICTRACEDUMP SIOCDEVPRIVATE+11
772
773#endif /* __SXG_DRIVER_H__ */
diff --git a/drivers/staging/sxg/sxg_os.h b/drivers/staging/sxg/sxg_os.h
new file mode 100644
index 000000000000..26fb0ffafa5c
--- /dev/null
+++ b/drivers/staging/sxg/sxg_os.h
@@ -0,0 +1,154 @@
1/**************************************************************************
2 *
3 * Copyright (C) 2000-2008 Alacritech, Inc. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above
12 * copyright notice, this list of conditions and the following
13 * disclaimer in the documentation and/or other materials provided
14 * with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
17 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * The views and conclusions contained in the software and documentation
30 * are those of the authors and should not be interpreted as representing
31 * official policies, either expressed or implied, of Alacritech, Inc.
32 *
33 **************************************************************************/
34
35/*
36 * FILENAME: sxg_os.h
37 *
38 * These are the Linux-specific definitions required for the SLICOSS
39 * driver, which should allow for greater portability to other OSes.
40 */
41#ifndef _SLIC_OS_SPECIFIC_H_
42#define _SLIC_OS_SPECIFIC_H_
43
44#define FALSE (0)
45#define TRUE (1)
46
47
48typedef struct _LIST_ENTRY {
49 struct _LIST_ENTRY *nle_flink;
50 struct _LIST_ENTRY *nle_blink;
51} list_entry, LIST_ENTRY, *PLIST_ENTRY;
52
53#define InitializeListHead(l) \
54 (l)->nle_flink = (l)->nle_blink = (l)
55
56#define IsListEmpty(h) \
57 ((h)->nle_flink == (h))
58
59#define RemoveEntryList(e) \
60 do { \
61 list_entry *b; \
62 list_entry *f; \
63 \
64 f = (e)->nle_flink; \
65 b = (e)->nle_blink; \
66 b->nle_flink = f; \
67 f->nle_blink = b; \
68 } while (0)
69
70/* These two have to be inlined since they return things. */
71
72static __inline PLIST_ENTRY
73RemoveHeadList(list_entry *l)
74{
75 list_entry *f;
76 list_entry *e;
77
78 e = l->nle_flink;
79 f = e->nle_flink;
80 l->nle_flink = f;
81 f->nle_blink = l;
82
83 return (e);
84}
85
86static __inline PLIST_ENTRY
87RemoveTailList(list_entry *l)
88{
89 list_entry *b;
90 list_entry *e;
91
92 e = l->nle_blink;
93 b = e->nle_blink;
94 l->nle_blink = b;
95 b->nle_flink = l;
96
97 return (e);
98}
99
100
101#define InsertTailList(l, e) \
102 do { \
103 list_entry *b; \
104 \
105 b = (l)->nle_blink; \
106 (e)->nle_flink = (l); \
107 (e)->nle_blink = b; \
108 b->nle_flink = (e); \
109 (l)->nle_blink = (e); \
110 } while (0)
111
112#define InsertHeadList(l, e) \
113 do { \
114 list_entry *f; \
115 \
116 f = (l)->nle_flink; \
117 (e)->nle_flink = f; \
118 (e)->nle_blink = l; \
119 f->nle_blink = (e); \
120 (l)->nle_flink = (e); \
121 } while (0)
122
123
124#define ATK_DEBUG 1
125
126#if ATK_DEBUG
127#define SLIC_TIMESTAMP(value) { \
128 struct timeval timev; \
129 do_gettimeofday(&timev); \
130 value = timev.tv_sec*1000000 + timev.tv_usec; \
131}
132#else
133#define SLIC_TIMESTAMP(value)
134#endif
135
136
137/****************** SXG DEFINES *****************************************/
138
139#ifdef ATKDBG
140#define SXG_TIMESTAMP(value) { \
141 struct timeval timev; \
142 do_gettimeofday(&timev); \
143 value = timev.tv_sec*1000000 + timev.tv_usec; \
144}
145#else
146#define SXG_TIMESTAMP(value)
147#endif
148
149#define WRITE_REG(reg,value,flush) sxg_reg32_write((&reg), (value), (flush))
150#define WRITE_REG64(a,reg,value,cpu) sxg_reg64_write((a),(&reg),(value),(cpu))
151#define READ_REG(reg,value) (value) = readl((void __iomem *)(&reg))
152
153#endif /* _SLIC_OS_SPECIFIC_H_ */
154
diff --git a/drivers/staging/sxg/sxgdbg.h b/drivers/staging/sxg/sxgdbg.h
new file mode 100644
index 000000000000..cfb6c7c77a9e
--- /dev/null
+++ b/drivers/staging/sxg/sxgdbg.h
@@ -0,0 +1,190 @@
1/**************************************************************************
2 *
3 * Copyright © 2000-2008 Alacritech, Inc. All rights reserved.
4 *
5 * $Id: sxgdbg.h,v 1.1 2008/06/27 12:49:28 mook Exp $
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
22 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * The views and conclusions contained in the software and documentation
32 * are those of the authors and should not be interpreted as representing
33 * official policies, either expressed or implied, of Alacritech, Inc.
34 *
35 **************************************************************************/
36
37/*
38 * FILENAME: sxgdbg.h
39 *
40 * All debug and assertion-based definitions and macros are included
41 * in this file for the SXGOSS driver.
42 */
43#ifndef _SXG_DEBUG_H_
44#define _SXG_DEBUG_H_
45
46#define ATKDBG 1
47#define ATK_TRACE_ENABLED 1
48
49#define DBG_ERROR(n, args...) printk(KERN_EMERG n, ##args)
50
51#ifdef ASSERT
52#undef ASSERT
53#endif
54
55#ifdef SXG_ASSERT_ENABLED
56#ifndef ASSERT
57#define ASSERT(a) \
58 { \
59 if (!(a)) { \
60 DBG_ERROR("ASSERT() Failure: file %s, function %s line %d\n",\
61 __FILE__, __FUNCTION__, __LINE__); \
62 } \
63 }
64#endif
65#else
66#ifndef ASSERT
67#define ASSERT(a)
68#endif
69#endif /* SXG_ASSERT_ENABLED */
70
71
72#ifdef ATKDBG
73/*
74 * Global for timer granularity; every driver must have an instance
75 * of this initialized to 0
76 */
77
78extern ulong ATKTimerDiv;
79
80/*
81 * trace_entry_t -
82 *
83 * This structure defines an entry in the trace buffer. The
84 * first few fields mean the same from entry to entry, while
85 * the meaning of last several fields change to suit the
86 * needs of the trace entry. Typically they are function call
87 * parameters.
88 */
89typedef struct _trace_entry_s {
90 char name[8]; /* 8 character name - like 's'i'm'b'a'r'c'v' */
91 u32 time; /* Current clock tic */
92 unsigned char cpu; /* Current CPU */
93 unsigned char irql; /* Current IRQL */
94 unsigned char driver; /* The driver which added the trace call */
95 unsigned char pad2; /* pad to 4 byte boundary - will probably get used */
96 u32 arg1; /* Caller arg1 */
97 u32 arg2; /* Caller arg2 */
98 u32 arg3; /* Caller arg3 */
99 u32 arg4; /* Caller arg4 */
100} trace_entry_t, *ptrace_entry_t;
101
102/*
103 * Driver types for driver field in trace_entry_t
104 */
105#define TRACE_SXG 1
106#define TRACE_VPCI 2
107#define TRACE_SLIC 3
108
109#define TRACE_ENTRIES 1024
110
111typedef struct _sxg_trace_buffer_t
112{
113 unsigned int size; /* aid for windbg extension */
114 unsigned int in; /* Where to add */
115 unsigned int level; /* Current Trace level */
116 spinlock_t lock; /* For MP tracing */
117 trace_entry_t entries[TRACE_ENTRIES];/* The circular buffer */
118} sxg_trace_buffer_t;
119
120/*
121 * The trace levels
122 *
123 * XXX At the moment I am only defining critical, important, and noisy.
124 * I am leaving room for more if anyone wants them.
125 */
126#define TRACE_NONE 0 /* For trace level - if no tracing wanted */
127#define TRACE_CRITICAL 1 /* minimal tracing - only critical stuff */
128#define TRACE_IMPORTANT 5 /* more tracing - anything important */
129#define TRACE_NOISY 10 /* Everything in the world */
130
131
132/**********************************************************************
133 *
134 * The macros themselves -
135 *
136 *********************************************************************/
137#if ATK_TRACE_ENABLED
138#define SXG_TRACE_INIT(buffer, tlevel) \
139{ \
140 memset((buffer), 0, sizeof(sxg_trace_buffer_t)); \
141 (buffer)->level = (tlevel); \
142 (buffer)->size = TRACE_ENTRIES; \
143 spin_lock_init(&(buffer)->lock); \
144}
145#else
146#define SXG_TRACE_INIT(buffer, tlevel)
147#endif
148
149/*
150 * The trace macro. This is active only if ATK_TRACE_ENABLED is set.
151 */
152#if ATK_TRACE_ENABLED
153#define SXG_TRACE(tdriver, buffer, tlevel, tname, a1, a2, a3, a4) { \
154 if ((buffer) && ((buffer)->level >= (tlevel))) { \
155 unsigned int trace_irql = 0; /* ?????? FIX THIS */ \
156 unsigned int trace_len; \
157 ptrace_entry_t trace_entry; \
158 struct timeval timev; \
159 \
160 spin_lock(&(buffer)->lock); \
161 trace_entry = &(buffer)->entries[(buffer)->in]; \
162 do_gettimeofday(&timev); \
163 \
164 memset(trace_entry->name, 0, 8); \
165 trace_len = strlen(tname); \
166 trace_len = trace_len > 8 ? 8 : trace_len; \
167 memcpy(trace_entry->name, (tname), trace_len); \
168 trace_entry->time = timev.tv_usec; \
169 trace_entry->cpu = (unsigned char)(smp_processor_id() & 0xFF); \
170 trace_entry->driver = (tdriver); \
171 trace_entry->irql = trace_irql; \
172 trace_entry->arg1 = (ulong)(a1); \
173 trace_entry->arg2 = (ulong)(a2); \
174 trace_entry->arg3 = (ulong)(a3); \
175 trace_entry->arg4 = (ulong)(a4); \
176 \
177 (buffer)->in++; \
178 if ((buffer)->in == TRACE_ENTRIES) \
179 (buffer)->in = 0; \
180 \
181 spin_unlock(&(buffer)->lock); \
182 } \
183}
184#else
185#define SXG_TRACE(tdriver, buffer, tlevel, tname, a1, a2, a3, a4)
186#endif
187
188#endif
189
190#endif /* _SXG_DEBUG_H_ */
diff --git a/drivers/staging/sxg/sxghif.h b/drivers/staging/sxg/sxghif.h
new file mode 100644
index 000000000000..ed26ceaa1315
--- /dev/null
+++ b/drivers/staging/sxg/sxghif.h
@@ -0,0 +1,861 @@
1/*
2 * Copyright © 1997-2007 Alacritech, Inc. All rights reserved
3 *
4 * $Id: sxghif.h,v 1.5 2008/07/24 19:18:22 chris Exp $
5 *
6 * sxghif.h:
7 *
8 * This file contains structures and definitions for the
9 * Alacritech Sahara host interface
10 */
11
12/*******************************************************************************
13 * UCODE Registers
14 *******************************************************************************/
15typedef struct _SXG_UCODE_REGS {
16 // Address 0 - 0x3F = Command codes 0-15 for TCB 0. Excode 0
17 u32 Icr; // Code = 0 (extended), ExCode = 0 - Int control
18 u32 RsvdReg1; // Code = 1 - TOE -NA
19 u32 RsvdReg2; // Code = 2 - TOE -NA
20 u32 RsvdReg3; // Code = 3 - TOE -NA
21 u32 RsvdReg4; // Code = 4 - TOE -NA
22 u32 RsvdReg5; // Code = 5 - TOE -NA
23 u32 CardUp; // Code = 6 - Microcode initialized when 1
24 u32 RsvdReg7; // Code = 7 - TOE -NA
25 u32 CodeNotUsed[8]; // Codes 8-15 not used. ExCode = 0
26 // This brings us to ExCode 1 at address 0x40 = Interrupt status pointer
27 u32 Isp; // Code = 0 (extended), ExCode = 1
28 u32 PadEx1[15]; // Codes 1-15 not used with extended codes
29 // ExCode 2 = Interrupt Status Register
30 u32 Isr; // Code = 0 (extended), ExCode = 2
31 u32 PadEx2[15];
32 // ExCode 3 = Event base register. Location of event rings
33 u32 EventBase; // Code = 0 (extended), ExCode = 3
34 u32 PadEx3[15];
35 // ExCode 4 = Event ring size
36 u32 EventSize; // Code = 0 (extended), ExCode = 4
37 u32 PadEx4[15];
38 // ExCode 5 = TCB Buffers base address
39 u32 TcbBase; // Code = 0 (extended), ExCode = 5
40 u32 PadEx5[15];
41 // ExCode 6 = TCB Composite Buffers base address
42 u32 TcbCompBase; // Code = 0 (extended), ExCode = 6
43 u32 PadEx6[15];
44 // ExCode 7 = Transmit ring base address
45 u32 XmtBase; // Code = 0 (extended), ExCode = 7
46 u32 PadEx7[15];
47 // ExCode 8 = Transmit ring size
48 u32 XmtSize; // Code = 0 (extended), ExCode = 8
49 u32 PadEx8[15];
50 // ExCode 9 = Receive ring base address
51 u32 RcvBase; // Code = 0 (extended), ExCode = 9
52 u32 PadEx9[15];
53 // ExCode 10 = Receive ring size
54 u32 RcvSize; // Code = 0 (extended), ExCode = 10
55 u32 PadEx10[15];
56 // ExCode 11 = Read EEPROM Config
57 u32 Config; // Code = 0 (extended), ExCode = 11
58 u32 PadEx11[15];
59 // ExCode 12 = Multicast bits 31:0
60 u32 McastLow; // Code = 0 (extended), ExCode = 12
61 u32 PadEx12[15];
62 // ExCode 13 = Multicast bits 63:32
63 u32 McastHigh; // Code = 0 (extended), ExCode = 13
64 u32 PadEx13[15];
65 // ExCode 14 = Ping
66 u32 Ping; // Code = 0 (extended), ExCode = 14
67 u32 PadEx14[15];
68 // ExCode 15 = Link MTU
69 u32 LinkMtu; // Code = 0 (extended), ExCode = 15
70 u32 PadEx15[15];
71 // ExCode 16 = Download synchronization
72 u32 LoadSync; // Code = 0 (extended), ExCode = 16
73 u32 PadEx16[15];
74 // ExCode 17 = Upper DRAM address bits on 32-bit systems
75 u32 Upper; // Code = 0 (extended), ExCode = 17
76 u32 PadEx17[15];
77 // ExCode 18 = Slowpath Send Index Address
78 u32 SPSendIndex; // Code = 0 (extended), ExCode = 18
79 u32 PadEx18[15];
80 u32 RsvdXF; // Code = 0 (extended), ExCode = 19
81 u32 PadEx19[15];
82 // ExCode 20 = Aggregation
83 u32 Aggregation; // Code = 0 (extended), ExCode = 20
84 u32 PadEx20[15];
85 // ExCode 21 = Receive MDL push timer
86 u32 PushTicks; // Code = 0 (extended), ExCode = 21
87 u32 PadEx21[15];
88 // ExCode 22 = TOE NA
89 u32 AckFrequency; // Code = 0 (extended), ExCode = 22
90 u32 PadEx22[15];
91 // ExCode 23 = TOE NA
92 u32 RsvdReg23;
93 u32 PadEx23[15];
94 // ExCode 24 = TOE NA
95 u32 RsvdReg24;
96 u32 PadEx24[15];
97 // ExCode 25 = TOE NA
98 u32 RsvdReg25; // Code = 0 (extended), ExCode = 25
99 u32 PadEx25[15];
100 // ExCode 26 = Receive checksum requirements
101 u32 ReceiveChecksum; // Code = 0 (extended), ExCode = 26
102 u32 PadEx26[15];
103 // ExCode 27 = RSS Requirements
104 u32 Rss; // Code = 0 (extended), ExCode = 27
105 u32 PadEx27[15];
106 // ExCode 28 = RSS Table
107 u32 RssTable; // Code = 0 (extended), ExCode = 28
108 u32 PadEx28[15];
109 // ExCode 29 = Event ring release entries
110 u32 EventRelease; // Code = 0 (extended), ExCode = 29
111 u32 PadEx29[15];
112 // ExCode 30 = Number of receive bufferlist commands on ring 0
113 u32 RcvCmd; // Code = 0 (extended), ExCode = 30
114 u32 PadEx30[15];
115 // ExCode 31 = slowpath transmit command - Data[31:0] = 1
116 u32 XmtCmd; // Code = 0 (extended), ExCode = 31
117 u32 PadEx31[15];
118 // ExCode 32 = Dump command
119 u32 DumpCmd; // Code = 0 (extended), ExCode = 32
120 u32 PadEx32[15];
121 // ExCode 33 = Debug command
122 u32 DebugCmd; // Code = 0 (extended), ExCode = 33
123 u32 PadEx33[15];
124 // There are 128 possible extended commands - each of account for 16
125 // words (including the non-relevent base command codes 1-15).
126 // Pad for the remainder of these here to bring us to the next CPU
127 // base. As extended codes are added, reduce the first array value in
128 // the following field
129 u32 PadToNextCpu[94][16]; // 94 = 128 - 34 (34 = Excodes 0 - 33)
130} SXG_UCODE_REGS, *PSXG_UCODE_REGS;
131
132// Interrupt control register (0) values
133#define SXG_ICR_DISABLE 0x00000000
134#define SXG_ICR_ENABLE 0x00000001
135#define SXG_ICR_MASK 0x00000002
136#define SXG_ICR_MSGID_MASK 0xFFFF0000
137#define SXG_ICR_MSGID_SHIFT 16
138#define SXG_ICR(_MessageId, _Data) \
139 ((((_MessageId) << SXG_ICR_MSGID_SHIFT) & \
140 SXG_ICR_MSGID_MASK) | (_Data))
141
142// The Microcode supports up to 16 RSS queues
143#define SXG_MAX_RSS 16
144#define SXG_MAX_RSS_TABLE_SIZE 256 // 256-byte max
145
146#define SXG_RSS_TCP6 0x00000001 // RSS TCP over IPv6
147#define SXG_RSS_TCP4 0x00000002 // RSS TCP over IPv4
148#define SXG_RSS_LEGACY 0x00000004 // Line-base interrupts
149#define SXG_RSS_TABLE_SIZE 0x0000FF00 // Table size mask
150#define SXG_RSS_TABLE_SHIFT 8
151#define SXG_RSS_BASE_CPU 0x00FF0000 // Base CPU (not used)
152#define SXG_RSS_BASE_SHIFT 16
153
154#define SXG_RCV_IP_CSUM_ENABLED 0x00000001 // ExCode 26 (ReceiveChecksum)
155#define SXG_RCV_TCP_CSUM_ENABLED 0x00000002 // ExCode 26 (ReceiveChecksum)
156
157#define SXG_XMT_CPUID_SHIFT 16
158
159#if VPCI
160#define SXG_CHECK_FOR_HANG_TIME 3000
161#else
162#define SXG_CHECK_FOR_HANG_TIME 5
163#endif
164
165/*
166 * TCB registers - This is really the same register memory area as UCODE_REGS
167 * above, but defined differently. Bits 17:06 of the address define the TCB,
168 * which means each TCB area occupies 0x40 (64) bytes, or 16 u32S. What really
169 * is happening is that these registers occupy the "PadEx[15]" areas in the
170 * SXG_UCODE_REGS definition above
171 */
172typedef struct _SXG_TCB_REGS {
173 u32 ExCode; /* Extended codes - see SXG_UCODE_REGS */
174 u32 Xmt; /* Code = 1 - # of Xmt descriptors added to ring */
175 u32 Rcv; /* Code = 2 - # of Rcv descriptors added to ring */
176 u32 Rsvd1; /* Code = 3 - TOE NA */
177 u32 Rsvd2; /* Code = 4 - TOE NA */
178 u32 Rsvd3; /* Code = 5 - TOE NA */
179 u32 Invalid; /* Code = 6 - Reserved for "CardUp" see above */
180 u32 Rsvd4; /* Code = 7 - TOE NA */
181 u32 Rsvd5; /* Code = 8 - TOE NA */
182 u32 Pad[7]; /* Codes 8-15 - Not used. */
183} SXG_TCB_REGS, *PSXG_TCB_REGS;
184
185/***************************************************************************
186 * ISR Format
187 * 31 0
188 * _______________________________________
189 * | | | | | | | | |
190 * |____|____|____|____|____|____|____|____|
191 * ^^^^ ^^^^ ^^^^ ^^^^ \ /
192 * ERR --|||| |||| |||| |||| -----------------
193 * EVENT ---||| |||| |||| |||| |
194 * ----|| |||| |||| |||| |-- Crash Address
195 * UPC -----| |||| |||| ||||
196 * LEVENT -------|||| |||| ||||
197 * PDQF --------||| |||| ||||
198 * RMISS ---------|| |||| ||||
199 * BREAK ----------| |||| ||||
200 * HBEATOK ------------|||| ||||
201 * NOHBEAT -------------||| ||||
202 * ERFULL --------------|| ||||
203 * XDROP ---------------| ||||
204 * -----------------||||
205 * -----------------||||--\
206 * ||---|-CpuId of crash
207 * |----/
208 ***************************************************************************/
209#define SXG_ISR_ERR 0x80000000 // Error
210#define SXG_ISR_EVENT 0x40000000 // Event ring event
211#define SXG_ISR_NONE1 0x20000000 // Not used
212#define SXG_ISR_UPC 0x10000000 // Dump/debug command complete
213#define SXG_ISR_LINK 0x08000000 // Link event
214#define SXG_ISR_PDQF 0x04000000 // Processed data queue full
215#define SXG_ISR_RMISS 0x02000000 // Drop - no host buf
216#define SXG_ISR_BREAK 0x01000000 // Breakpoint hit
217#define SXG_ISR_PING 0x00800000 // Heartbeat response
218#define SXG_ISR_DEAD 0x00400000 // Card crash
219#define SXG_ISR_ERFULL 0x00200000 // Event ring full
220#define SXG_ISR_XDROP 0x00100000 // XMT Drop - no DRAM bufs or XMT err
221#define SXG_ISR_SPSEND 0x00080000 // Slow send complete
222#define SXG_ISR_CPU 0x00070000 // Dead CPU mask
223#define SXG_ISR_CPU_SHIFT 16 // Dead CPU shift
224#define SXG_ISR_CRASH 0x0000FFFF // Crash address mask
225
226/***************************************************************************
227 *
228 * Event Ring entry
229 *
230 ***************************************************************************/
231/*
232 * 31 15 0
233 * .___________________.___________________.
234 * |<------------ Pad 0 ------------>|
235 * |_________|_________|_________|_________|0 0x00
236 * |<------------ Pad 1 ------------>|
237 * |_________|_________|_________|_________|4 0x04
238 * |<------------ Pad 2 ------------>|
239 * |_________|_________|_________|_________|8 0x08
240 * |<----------- Event Word 0 ------------>|
241 * |_________|_________|_________|_________|12 0x0c
242 * |<----------- Event Word 1 ------------>|
243 * |_________|_________|_________|_________|16 0x10
244 * |<------------- Toeplitz ------------>|
245 * |_________|_________|_________|_________|20 0x14
246 * |<----- Length ---->|<------ TCB Id --->|
247 * |_________|_________|_________|_________|24 0x18
248 * |<----- Status ---->|Evnt Code|Flsh Code|
249 * |_________|_________|_________|_________|28 0x1c
250 * ^ ^^^^ ^^^^
251 * |- VALID |||| ||||- RBUFC
252 * |||| |||-- SLOWR
253 * |||| ||--- UNUSED
254 * |||| |---- FASTC
255 * ||||------ FASTR
256 * |||-------
257 * ||--------
258 * |---------
259 *
260 * Slowpath status:
261 * _______________________________________
262 * |<----- Status ---->|Evnt Code|Flsh Code|
263 * |_________|Cmd Index|_________|_________|28 0x1c
264 * ^^^ ^^^^
265 * ||| ||||- ISTCPIP6
266 * ||| |||-- IPONLY
267 * ||| ||--- RCVERR
268 * ||| |---- IPCBAD
269 * |||------ TCPCBAD
270 * ||------- ISTCPIP
271 * |-------- SCERR
272 *
273 */
274#pragma pack(push, 1)
275typedef struct _SXG_EVENT {
276 u32 Pad[1]; // not used
277 u32 SndUna; // SndUna value
278 u32 Resid; // receive MDL resid
279 union {
280 void * HostHandle; // Receive host handle
281 u32 Rsvd1; // TOE NA
282 struct {
283 u32 NotUsed;
284 u32 Rsvd2; // TOE NA
285 } Flush;
286 };
287 u32 Toeplitz; // RSS Toeplitz hash
288 union {
289 ushort Rsvd3; // TOE NA
290 ushort HdrOffset; // Slowpath
291 };
292 ushort Length; //
293 unsigned char Rsvd4; // TOE NA
294 unsigned char Code; // Event code
295 unsigned char CommandIndex; // New ring index
296 unsigned char Status; // Event status
297} SXG_EVENT, *PSXG_EVENT;
298#pragma pack(pop)
299
300// Event code definitions
301#define EVENT_CODE_BUFFERS 0x01 // Receive buffer list command (ring 0)
302#define EVENT_CODE_SLOWRCV 0x02 // Slowpath receive
303#define EVENT_CODE_UNUSED 0x04 // Was slowpath commands complete
304
305// Status values
306#define EVENT_STATUS_VALID 0x80 // Entry valid
307
308// Slowpath status
309#define EVENT_STATUS_ERROR 0x40 // Completed with error. Index in next byte
310#define EVENT_STATUS_TCPIP4 0x20 // TCPIPv4 frame
311#define EVENT_STATUS_TCPBAD 0x10 // Bad TCP checksum
312#define EVENT_STATUS_IPBAD 0x08 // Bad IP checksum
313#define EVENT_STATUS_RCVERR 0x04 // Slowpath receive error
314#define EVENT_STATUS_IPONLY 0x02 // IP frame
315#define EVENT_STATUS_TCPIP6 0x01 // TCPIPv6 frame
316#define EVENT_STATUS_TCPIP 0x21 // Combination of v4 and v6
317
318// Event ring
319// Size must be power of 2, between 128 and 16k
320#define EVENT_RING_SIZE 4096 // ??
321#define EVENT_RING_BATCH 16 // Hand entries back 16 at a time.
322#define EVENT_BATCH_LIMIT 256 // Stop processing events after 256 (16 * 16)
323
324typedef struct _SXG_EVENT_RING {
325 SXG_EVENT Ring[EVENT_RING_SIZE];
326}SXG_EVENT_RING, *PSXG_EVENT_RING;
327
328/***************************************************************************
329 *
330 * TCB Buffers
331 *
332 ***************************************************************************/
333// Maximum number of TCBS supported by hardware/microcode
334#define SXG_MAX_TCB 4096
335// Minimum TCBs before we fail initialization
336#define SXG_MIN_TCB 512
337// TCB Hash
338// The bucket is determined by bits 11:4 of the toeplitz if we support 4k
339// offloaded connections, 10:4 if we support 2k and so on.
340#define SXG_TCB_BUCKET_SHIFT 4
341#define SXG_TCB_PER_BUCKET 16
342#define SXG_TCB_BUCKET_MASK 0xFF0 // Bucket portion of TCB ID
343#define SXG_TCB_ELEMENT_MASK 0x00F // Element within bucket
344#define SXG_TCB_BUCKETS 256 // 256 * 16 = 4k
345
346#define SXG_TCB_BUFFER_SIZE 512 // ASSERT format is correct
347
348#define SXG_TCB_RCVQ_SIZE 736
349
350#define SXG_TCB_COMPOSITE_BUFFER_SIZE 1024
351
352#define SXG_LOCATE_TCP_FRAME_HDR(_TcpObject, _IPv6) \
353 (((_TcpObject)->VlanId) ? \
354 ((_IPv6) ? /* Vlan frame header = yes */ \
355 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.SxgTcp : \
356 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.SxgTcp) : \
357 ((_IPv6) ? /* Vlan frame header = No */ \
358 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.SxgTcp : \
359 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.SxgTcp))
360
361#define SXG_LOCATE_IP_FRAME_HDR(_TcpObject) \
362 (_TcpObject)->VlanId ? \
363 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.Ip : \
364 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.Ip
365
366#define SXG_LOCATE_IP6_FRAME_HDR(_TcpObject) \
367 (_TcpObject)->VlanId ? \
368 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip : \
369 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.Ip
370
371
372#if DBG
373// Horrible kludge to distinguish dumb-nic, slowpath, and
374// fastpath traffic. Decrement the HopLimit by one
375// for slowpath, two for fastpath. This assumes the limit is measurably
376// greater than two, which I think is reasonable.
377// Obviously this is DBG only. Maybe remove later, or #if 0 so we
378// can set it when needed
379#define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath) { \
380 PIPV6_HDR _Ip6FrameHdr; \
381 if((_TcpObject)->IPv6) { \
382 _Ip6FrameHdr = SXG_LOCATE_IP6_FRAME_HDR((_TcpObject)); \
383 if(_FastPath) { \
384 _Ip6FrameHdr->HopLimit = (_TcpObject)->Cached.TtlOrHopLimit - 2; \
385 } else { \
386 _Ip6FrameHdr->HopLimit = (_TcpObject)->Cached.TtlOrHopLimit - 1; \
387 } \
388 } \
389}
390#else
391// Do nothing with free build
392#define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath)
393#endif
394
395/***************************************************************************
396 * Receive and transmit rings
397 ***************************************************************************/
398#define SXG_MAX_RING_SIZE 256
399#define SXG_XMT_RING_SIZE 128 // Start with 128
400#define SXG_RCV_RING_SIZE 128 // Start with 128
401#define SXG_MAX_ENTRIES 4096
402
403// Structure and macros to manage a ring
404typedef struct _SXG_RING_INFO {
405 unsigned char Head; // Where we add entries - Note unsigned char:RING_SIZE
406 unsigned char Tail; // Where we pull off completed entries
407 ushort Size; // Ring size - Must be multiple of 2
408 void * Context[SXG_MAX_RING_SIZE]; // Shadow ring
409} SXG_RING_INFO, *PSXG_RING_INFO;
410
411#define SXG_INITIALIZE_RING(_ring, _size) { \
412 (_ring).Head = 0; \
413 (_ring).Tail = 0; \
414 (_ring).Size = (_size); \
415}
416#define SXG_ADVANCE_INDEX(_index, _size) ((_index) = ((_index) + 1) & ((_size) - 1))
417#define SXG_PREVIOUS_INDEX(_index, _size) (((_index) - 1) &((_size) - 1))
418#define SXG_RING_EMPTY(_ring) ((_ring)->Head == (_ring)->Tail)
419#define SXG_RING_FULL(_ring) ((((_ring)->Head + 1) & ((_ring)->Size - 1)) == (_ring)->Tail)
420#define SXG_RING_ADVANCE_HEAD(_ring) SXG_ADVANCE_INDEX((_ring)->Head, ((_ring)->Size))
421#define SXG_RING_RETREAT_HEAD(_ring) ((_ring)->Head = \
422 SXG_PREVIOUS_INDEX((_ring)->Head, (_ring)->Size))
423#define SXG_RING_ADVANCE_TAIL(_ring) { \
424 ASSERT((_ring)->Tail != (_ring)->Head); \
425 SXG_ADVANCE_INDEX((_ring)->Tail, ((_ring)->Size)); \
426}
427// Set cmd to the next available ring entry, set the shadow context
428// entry and advance the ring.
429// The appropriate lock must be held when calling this macro
430#define SXG_GET_CMD(_ring, _ringinfo, _cmd, _context) { \
431 if(SXG_RING_FULL(_ringinfo)) { \
432 (_cmd) = NULL; \
433 } else { \
434 (_cmd) = &(_ring)->Descriptors[(_ringinfo)->Head]; \
435 (_ringinfo)->Context[(_ringinfo)->Head] = (void *)(_context);\
436 SXG_RING_ADVANCE_HEAD(_ringinfo); \
437 } \
438}
439
440// Abort the previously allocated command by retreating the head.
441// NOTE - The appopriate lock MUST NOT BE DROPPED between the SXG_GET_CMD
442// and SXG_ABORT_CMD calls.
443#define SXG_ABORT_CMD(_ringinfo) { \
444 ASSERT(!(SXG_RING_EMPTY(_ringinfo))); \
445 SXG_RING_RETREAT_HEAD(_ringinfo); \
446 (_ringinfo)->Context[(_ringinfo)->Head] = NULL; \
447}
448
449// For the given ring, return a pointer to the tail cmd and context,
450// clear the context and advance the tail
451#define SXG_RETURN_CMD(_ring, _ringinfo, _cmd, _context) { \
452 (_cmd) = &(_ring)->Descriptors[(_ringinfo)->Tail]; \
453 (_context) = (_ringinfo)->Context[(_ringinfo)->Tail]; \
454 (_ringinfo)->Context[(_ringinfo)->Tail] = NULL; \
455 SXG_RING_ADVANCE_TAIL(_ringinfo); \
456}
457
458/***************************************************************************
459 *
460 * Host Command Buffer - commands to INIC via the Cmd Rings
461 *
462 ***************************************************************************/
463/*
464 * 31 15 0
465 * .___________________.___________________.
466 * |<-------------- Sgl Low -------------->|
467 * |_________|_________|_________|_________|0 0x00
468 * |<-------------- Sgl High ------------->|
469 * |_________|_________|_________|_________|4 0x04
470 * |<------------- Sge 0 Low ----------->|
471 * |_________|_________|_________|_________|8 0x08
472 * |<------------- Sge 0 High ----------->|
473 * |_________|_________|_________|_________|12 0x0c
474 * |<------------ Sge 0 Length ---------->|
475 * |_________|_________|_________|_________|16 0x10
476 * |<----------- Window Update ----------->|
477 * |<-------- SP 1st SGE offset ---------->|
478 * |_________|_________|_________|_________|20 0x14
479 * |<----------- Total Length ------------>|
480 * |_________|_________|_________|_________|24 0x18
481 * |<----- LCnt ------>|<----- Flags ----->|
482 * |_________|_________|_________|_________|28 0x1c
483 */
484#pragma pack(push, 1)
485typedef struct _SXG_CMD {
486 dma_addr_t Sgl; // Physical address of SGL
487 union {
488 struct {
489 dma64_addr_t FirstSgeAddress;// Address of first SGE
490 u32 FirstSgeLength; // Length of first SGE
491 union {
492 u32 Rsvd1; // TOE NA
493 u32 SgeOffset; // Slowpath - 2nd SGE offset
494 u32 Resid; // MDL completion - clobbers update
495 };
496 union {
497 u32 TotalLength; // Total transfer length
498 u32 Mss; // LSO MSS
499 };
500 } Buffer;
501 };
502 union {
503 struct {
504 unsigned char Flags:4; // slowpath flags
505 unsigned char IpHl:4; // Ip header length (>>2)
506 unsigned char MacLen; // Mac header len
507 } CsumFlags;
508 struct {
509 ushort Flags:4; // slowpath flags
510 ushort TcpHdrOff:7; // TCP
511 ushort MacLen:5; // Mac header len
512 } LsoFlags;
513 ushort Flags; // flags
514 };
515 union {
516 ushort SgEntries; // SG entry count including first sge
517 struct {
518 unsigned char Status; // Copied from event status
519 unsigned char NotUsed;
520 } Status;
521 };
522} SXG_CMD, *PSXG_CMD;
523#pragma pack(pop)
524
525#pragma pack(push, 1)
526typedef struct _VLAN_HDR {
527 ushort VlanTci;
528 ushort VlanTpid;
529} VLAN_HDR, *PVLAN_HDR;
530#pragma pack(pop)
531
532/*
533 * Slowpath Flags:
534 *
535 *
536 * LSS Flags:
537 * .---
538 * /.--- TCP Large segment send
539 * //.---
540 * ///.---
541 * 3 1 1 ////
542 * 1 5 0 ||||
543 * .___________________.____________vvvv.
544 * | |MAC | TCP | |
545 * | LCnt |hlen|hdroff|Flgs|
546 * |___________________|||||||||||||____|
547 *
548 *
549 * Checksum Flags
550 *
551 * .---
552 * /.---
553 * //.--- Checksum TCP
554 * ///.--- Checksum IP
555 * 3 1 //// No bits - normal send
556 * 1 5 7 ||||
557 * .___________________._______________vvvv.
558 * | | Offload | IP | |
559 * | LCnt |MAC hlen |Hlen|Flgs|
560 * |___________________|____|____|____|____|
561 *
562 */
563// Slowpath CMD flags
564#define SXG_SLOWCMD_CSUM_IP 0x01 // Checksum IP
565#define SXG_SLOWCMD_CSUM_TCP 0x02 // Checksum TCP
566#define SXG_SLOWCMD_LSO 0x04 // Large segment send
567
568typedef struct _SXG_XMT_RING {
569 SXG_CMD Descriptors[SXG_XMT_RING_SIZE];
570} SXG_XMT_RING, *PSXG_XMT_RING;
571
572typedef struct _SXG_RCV_RING {
573 SXG_CMD Descriptors[SXG_RCV_RING_SIZE];
574} SXG_RCV_RING, *PSXG_RCV_RING;
575
576/***************************************************************************
577 * Share memory buffer types - Used to identify asynchronous
578 * shared memory allocation
579 ***************************************************************************/
580typedef enum {
581 SXG_BUFFER_TYPE_RCV, // Receive buffer
582 SXG_BUFFER_TYPE_SGL // SGL buffer
583} SXG_BUFFER_TYPE;
584
585// State for SXG buffers
586#define SXG_BUFFER_FREE 0x01
587#define SXG_BUFFER_BUSY 0x02
588#define SXG_BUFFER_ONCARD 0x04
589#define SXG_BUFFER_UPSTREAM 0x08
590
591/***************************************************************************
592 * Receive data buffers
593 *
594 * Receive data buffers are given to the Sahara card 128 at a time.
595 * This is accomplished by filling in a "receive descriptor block"
596 * with 128 "receive descriptors". Each descriptor consists of
597 * a physical address, which the card uses as the address to
598 * DMA data into, and a virtual address, which is given back
599 * to the host in the "HostHandle" portion of an event.
600 * The receive descriptor data structure is defined below
601 * as SXG_RCV_DATA_DESCRIPTOR, and the corresponding block
602 * is defined as SXG_RCV_DESCRIPTOR_BLOCK.
603 *
604 * This receive descriptor block is given to the card by filling
605 * in the Sgl field of a SXG_CMD entry from pAdapt->RcvRings[0]
606 * with the physical address of the receive descriptor block.
607 *
608 * Both the receive buffers and the receive descriptor blocks
609 * require additional data structures to maintain them
610 * on a free queue and contain other information associated with them.
611 * Those data structures are defined as the SXG_RCV_DATA_BUFFER_HDR
612 * and SXG_RCV_DESCRIPTOR_BLOCK_HDR respectively.
613 *
614 * Since both the receive buffers and the receive descriptor block
615 * must be accessible by the card, both must be allocated out of
616 * shared memory. To ensure that we always have a descriptor
617 * block available for every 128 buffers, we allocate all of
618 * these resources together in a single block. This entire
619 * block is managed by a SXG_RCV_BLOCK_HDR, who's sole purpose
620 * is to maintain address information so that the entire block
621 * can be free later.
622 *
623 * Further complicating matters is the fact that the receive
624 * buffers must be variable in length in order to accomodate
625 * jumbo frame configurations. We configure the buffer
626 * length so that the buffer and it's corresponding SXG_RCV_DATA_BUFFER_HDR
627 * structure add up to an even boundary. Then we place the
628 * remaining data structures after 128 of them as shown in
629 * the following diagram:
630 *
631 * _________________________________________
632 * | |
633 * | Variable length receive buffer #1 |
634 * |_________________________________________|
635 * | |
636 * | SXG_RCV_DATA_BUFFER_HDR #1 |
637 * |_________________________________________| <== Even 2k or 10k boundary
638 * | |
639 * | ... repeat 2-128 .. |
640 * |_________________________________________|
641 * | |
642 * | SXG_RCV_DESCRIPTOR_BLOCK |
643 * | Contains SXG_RCV_DATA_DESCRIPTOR * 128 |
644 * |_________________________________________|
645 * | |
646 * | SXG_RCV_DESCRIPTOR_BLOCK_HDR |
647 * |_________________________________________|
648 * | |
649 * | SXG_RCV_BLOCK_HDR |
650 * |_________________________________________|
651 *
652 * Memory consumption:
653 * Non-jumbo:
654 * Buffers and SXG_RCV_DATA_BUFFER_HDR = 2k * 128 = 256k
655 * + SXG_RCV_DESCRIPTOR_BLOCK = 2k
656 * + SXG_RCV_DESCRIPTOR_BLOCK_HDR = ~32
657 * + SXG_RCV_BLOCK_HDR = ~32
658 * => Total = ~258k/block
659 *
660 * Jumbo:
661 * Buffers and SXG_RCV_DATA_BUFFER_HDR = 10k * 128 = 1280k
662 * + SXG_RCV_DESCRIPTOR_BLOCK = 2k
663 * + SXG_RCV_DESCRIPTOR_BLOCK_HDR = ~32
664 * + SXG_RCV_BLOCK_HDR = ~32
665 * => Total = ~1282k/block
666 *
667 ***************************************************************************/
668#define SXG_RCV_DATA_BUFFERS 4096 // Amount to give to the card
669#define SXG_INITIAL_RCV_DATA_BUFFERS 8192 // Initial pool of buffers
670#define SXG_MIN_RCV_DATA_BUFFERS 2048 // Minimum amount and when to get more
671#define SXG_MAX_RCV_BLOCKS 128 // = 16384 receive buffers
672
673// Receive buffer header
674typedef struct _SXG_RCV_DATA_BUFFER_HDR {
675 dma_addr_t PhysicalAddress; // Buffer physical address
676 // Note - DO NOT USE the VirtualAddress field to locate data.
677 // Use the sxg.h:SXG_RECEIVE_DATA_LOCATION macro instead.
678 void *VirtualAddress; // Start of buffer
679 LIST_ENTRY FreeList; // Free queue of buffers
680 struct _SXG_RCV_DATA_BUFFER_HDR *Next; // Fastpath data buffer queue
681 u32 Size; // Buffer size
682 u32 ByteOffset; // See SXG_RESTORE_MDL_OFFSET
683 unsigned char State; // See SXG_BUFFER state above
684 unsigned char Status; // Event status (to log PUSH)
685 struct sk_buff * skb; // Double mapped (nbl and pkt)
686} SXG_RCV_DATA_BUFFER_HDR, *PSXG_RCV_DATA_BUFFER_HDR;
687
688// SxgSlowReceive uses the PACKET (skb) contained
689// in the SXG_RCV_DATA_BUFFER_HDR when indicating dumb-nic data
690#define SxgDumbRcvPacket skb
691
692#define SXG_RCV_DATA_HDR_SIZE 256 // Space for SXG_RCV_DATA_BUFFER_HDR
693#define SXG_RCV_DATA_BUFFER_SIZE 2048 // Non jumbo = 2k including HDR
694#define SXG_RCV_JUMBO_BUFFER_SIZE 10240 // jumbo = 10k including HDR
695
696// Receive data descriptor
697typedef struct _SXG_RCV_DATA_DESCRIPTOR {
698 union {
699 struct sk_buff * VirtualAddress; // Host handle
700 u64 ForceTo8Bytes; // Force x86 to 8-byte boundary
701 };
702 dma_addr_t PhysicalAddress;
703} SXG_RCV_DATA_DESCRIPTOR, *PSXG_RCV_DATA_DESCRIPTOR;
704
705// Receive descriptor block
706#define SXG_RCV_DESCRIPTORS_PER_BLOCK 128
707#define SXG_RCV_DESCRIPTOR_BLOCK_SIZE 2048 // For sanity check
708typedef struct _SXG_RCV_DESCRIPTOR_BLOCK {
709 SXG_RCV_DATA_DESCRIPTOR Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK];
710} SXG_RCV_DESCRIPTOR_BLOCK, *PSXG_RCV_DESCRIPTOR_BLOCK;
711
712// Receive descriptor block header
713typedef struct _SXG_RCV_DESCRIPTOR_BLOCK_HDR {
714 void * VirtualAddress; // Start of 2k buffer
715 dma_addr_t PhysicalAddress; // ..and it's physical address
716 LIST_ENTRY FreeList; // Free queue of descriptor blocks
717 unsigned char State; // See SXG_BUFFER state above
718} SXG_RCV_DESCRIPTOR_BLOCK_HDR, *PSXG_RCV_DESCRIPTOR_BLOCK_HDR;
719
720// Receive block header
721typedef struct _SXG_RCV_BLOCK_HDR {
722 void * VirtualAddress; // Start of virtual memory
723 dma_addr_t PhysicalAddress; // ..and it's physical address
724 LIST_ENTRY AllList; // Queue of all SXG_RCV_BLOCKS
725} SXG_RCV_BLOCK_HDR, *PSXG_RCV_BLOCK_HDR;
726
727// Macros to determine data structure offsets into receive block
728#define SXG_RCV_BLOCK_SIZE(_Buffersize) \
729 (((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
730 (sizeof(SXG_RCV_DESCRIPTOR_BLOCK)) + \
731 (sizeof(SXG_RCV_DESCRIPTOR_BLOCK_HDR)) + \
732 (sizeof(SXG_RCV_BLOCK_HDR)))
733#define SXG_RCV_BUFFER_DATA_SIZE(_Buffersize) \
734 ((_Buffersize) - SXG_RCV_DATA_HDR_SIZE)
735#define SXG_RCV_DATA_BUFFER_HDR_OFFSET(_Buffersize) \
736 ((_Buffersize) - SXG_RCV_DATA_HDR_SIZE)
737#define SXG_RCV_DESCRIPTOR_BLOCK_OFFSET(_Buffersize) \
738 ((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK)
739#define SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET(_Buffersize) \
740 (((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
741 (sizeof(SXG_RCV_DESCRIPTOR_BLOCK)))
742#define SXG_RCV_BLOCK_HDR_OFFSET(_Buffersize) \
743 (((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
744 (sizeof(SXG_RCV_DESCRIPTOR_BLOCK)) + \
745 (sizeof(SXG_RCV_DESCRIPTOR_BLOCK_HDR)))
746
747// Use the miniport reserved portion of the NBL to locate
748// our SXG_RCV_DATA_BUFFER_HDR structure.
749typedef struct _SXG_RCV_NBL_RESERVED {
750 PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr;
751 void * Available;
752} SXG_RCV_NBL_RESERVED, *PSXG_RCV_NBL_RESERVED;
753
754#define SXG_RCV_NBL_BUFFER_HDR(_NBL) (((PSXG_RCV_NBL_RESERVED)NET_BUFFER_LIST_MINIPORT_RESERVED(_NBL))->RcvDataBufferHdr)
755
756/***************************************************************************
757 * Scatter gather list buffer
758 ***************************************************************************/
759#define SXG_INITIAL_SGL_BUFFERS 8192 // Initial pool of SGL buffers
760#define SXG_MIN_SGL_BUFFERS 2048 // Minimum amount and when to get more
761#define SXG_MAX_SGL_BUFFERS 16384 // Maximum to allocate (note ADAPT:ushort)
762
763
764// Self identifying structure type
765typedef enum _SXG_SGL_TYPE {
766 SXG_SGL_DUMB, // Dumb NIC SGL
767 SXG_SGL_SLOW, // Slowpath protocol header - see below
768 SXG_SGL_CHIMNEY // Chimney offload SGL
769} SXG_SGL_TYPE, PSXG_SGL_TYPE;
770
771// Note - the description below is Microsoft specific
772//
773// The following definition specifies the amount of shared memory to allocate
774// for the SCATTER_GATHER_LIST portion of the SXG_SCATTER_GATHER data structure.
775// The following considerations apply when setting this value:
776// - First, the Sahara card is designed to read the Microsoft SGL structure
777// straight out of host memory. This means that the SGL must reside in
778// shared memory. If the length here is smaller than the SGL for the
779// NET_BUFFER, then NDIS will allocate its own buffer. The buffer
780// that NDIS allocates is not in shared memory, so when this happens,
781// the SGL will need to be copied to a set of SXG_SCATTER_GATHER buffers.
782// In other words.. we don't want this value to be too small.
783// - On the other hand.. we're allocating up to 16k of these things. If
784// we make this too big, we start to consume a ton of memory..
785// At the moment, I'm going to limit the number of SG entries to 150.
786// If each entry maps roughly 4k, then this should cover roughly 600kB
787// NET_BUFFERs. Furthermore, since each entry is 24 bytes, the total
788// SGE portion of the structure consumes 3600 bytes, which should allow
789// the entire SXG_SCATTER_GATHER structure to reside comfortably within
790// a 4k block, providing the remaining fields stay under 500 bytes.
791//
792// So with 150 entries, the SXG_SCATTER_GATHER structure becomes roughly
793// 4k. At 16k of them, that amounts to 64M of shared memory. A ton, but
794// manageable.
795#define SXG_SGL_ENTRIES 150
796
797// The ucode expects an NDIS SGL structure that
798// is formatted for an x64 system. When running
799// on an x64 system, we can simply hand the NDIS SGL
800// to the card directly. For x86 systems we must reconstruct
801// the SGL. The following structure defines an x64
802// formatted SGL entry
803typedef struct _SXG_X64_SGE {
804 dma64_addr_t Address; // same as wdm.h
805 u32 Length; // same as wdm.h
806 u32 CompilerPad;// The compiler pads to 8-bytes
807 u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
808} SXG_X64_SGE, *PSXG_X64_SGE;
809
810typedef struct _SCATTER_GATHER_ELEMENT {
811 dma64_addr_t Address; // same as wdm.h
812 u32 Length; // same as wdm.h
813 u32 CompilerPad;// The compiler pads to 8-bytes
814 u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
815} SCATTER_GATHER_ELEMENT, *PSCATTER_GATHER_ELEMENT;
816
817
818typedef struct _SCATTER_GATHER_LIST {
819 u32 NumberOfElements;
820 u32 * Reserved;
821 SCATTER_GATHER_ELEMENT Elements[];
822} SCATTER_GATHER_LIST, *PSCATTER_GATHER_LIST;
823
824// The card doesn't care about anything except elements, so
825// we can leave the u32 * reserved field alone in the following
826// SGL structure. But redefine from wdm.h:SCATTER_GATHER_LIST so
827// we can specify SXG_X64_SGE and define a fixed number of elements
828typedef struct _SXG_X64_SGL {
829 u32 NumberOfElements;
830 u32 * Reserved;
831 SXG_X64_SGE Elements[SXG_SGL_ENTRIES];
832} SXG_X64_SGL, *PSXG_X64_SGL;
833
834typedef struct _SXG_SCATTER_GATHER {
835 SXG_SGL_TYPE Type; // FIRST! Dumb-nic or offload
836 void * adapter; // Back pointer to adapter
837 LIST_ENTRY FreeList; // Free SXG_SCATTER_GATHER blocks
838 LIST_ENTRY AllList; // All SXG_SCATTER_GATHER blocks
839 dma_addr_t PhysicalAddress;// physical address
840 unsigned char State; // See SXG_BUFFER state above
841 unsigned char CmdIndex; // Command ring index
842 struct sk_buff * DumbPacket; // Associated Packet
843 u32 Direction; // For asynchronous completions
844 u32 CurOffset; // Current SGL offset
845 u32 SglRef; // SGL reference count
846 VLAN_HDR VlanTag; // VLAN tag to be inserted into SGL
847 PSCATTER_GATHER_LIST pSgl; // SGL Addr. Possibly &Sgl
848 SXG_X64_SGL Sgl; // SGL handed to card
849} SXG_SCATTER_GATHER, *PSXG_SCATTER_GATHER;
850
851#if defined(CONFIG_X86_64)
852#define SXG_SGL_BUFFER(_SxgSgl) (&_SxgSgl->Sgl)
853#define SXG_SGL_BUF_SIZE sizeof(SXG_X64_SGL)
854#elif defined(CONFIG_X86)
855// Force NDIS to give us it's own buffer so we can reformat to our own
856#define SXG_SGL_BUFFER(_SxgSgl) NULL
857#define SXG_SGL_BUF_SIZE 0
858#else
859 Stop Compilation;
860#endif
861
diff --git a/drivers/staging/sxg/sxghw.h b/drivers/staging/sxg/sxghw.h
new file mode 100644
index 000000000000..8f4f6effdd98
--- /dev/null
+++ b/drivers/staging/sxg/sxghw.h
@@ -0,0 +1,734 @@
1/*
2 * Copyright © 1997-2007 Alacritech, Inc. All rights reserved
3 *
4 * $Id: sxghw.h,v 1.2 2008/07/24 17:24:23 chris Exp $
5 *
6 * sxghw.h:
7 *
8 * This file contains structures and definitions for the
9 * Alacritech Sahara hardware
10 */
11
12
13/*******************************************************************************
14 * Configuration space
15 *******************************************************************************/
16// PCI Vendor ID
17#define SXG_VENDOR_ID 0x139A // Alacritech's Vendor ID
18
19// PCI Device ID
20#define SXG_DEVICE_ID 0x0009 // Sahara Device ID
21
22//
23// Subsystem IDs.
24//
25// The subsystem ID value is broken into bit fields as follows:
26// Bits [15:12] - Function
27// Bits [11:8] - OEM and/or operating system.
28// Bits [7:0] - Base SID.
29//
30// SSID field (bit) masks
31#define SSID_BASE_MASK 0x00FF // Base subsystem ID mask
32#define SSID_OEM_MASK 0x0F00 // Subsystem OEM mask
33#define SSID_FUNC_MASK 0xF000 // Subsystem function mask
34
35// Base SSID's
36#define SSID_SAHARA_PROTO 0x0018 // 100022 Sahara prototype (XenPak) board
37#define SSID_SAHARA_FIBER 0x0019 // 100023 Sahara 1-port fiber board
38#define SSID_SAHARA_COPPER 0x001A // 100024 Sahara 1-port copper board
39
40// Useful SSID macros
41#define SSID_BASE(ssid) ((ssid) & SSID_BASE_MASK) // isolate base SSID bits
42#define SSID_OEM(ssid) ((ssid) & SSID_OEM_MASK) // isolate SSID OEM bits
43#define SSID_FUNC(ssid) ((ssid) & SSID_FUNC_MASK) // isolate SSID function bits
44
45/*******************************************************************************
46 * HW Register Space
47 *******************************************************************************/
48#define SXG_HWREG_MEMSIZE 0x4000 // 16k
49
50#pragma pack(push, 1)
51typedef struct _SXG_HW_REGS {
52 u32 Reset; // Write 0xdead to invoke soft reset
53 u32 Pad1; // No register defined at offset 4
54 u32 InterruptMask0; // Deassert legacy interrupt on function 0
55 u32 InterruptMask1; // Deassert legacy interrupt on function 1
56 u32 UcodeDataLow; // Store microcode instruction bits 31-0
57 u32 UcodeDataMiddle; // Store microcode instruction bits 63-32
58 u32 UcodeDataHigh; // Store microcode instruction bits 95-64
59 u32 UcodeAddr; // Store microcode address - See flags below
60 u32 PadTo0x80[24]; // Pad to Xcv configuration registers
61 u32 MacConfig0; // 0x80 - AXGMAC Configuration Register 0
62 u32 MacConfig1; // 0x84 - AXGMAC Configuration Register 1
63 u32 MacConfig2; // 0x88 - AXGMAC Configuration Register 2
64 u32 MacConfig3; // 0x8C - AXGMAC Configuration Register 3
65 u32 MacAddressLow; // 0x90 - AXGMAC MAC Station Address - octets 1-4
66 u32 MacAddressHigh; // 0x94 - AXGMAC MAC Station Address - octets 5-6
67 u32 MacReserved1[2]; // 0x98 - AXGMAC Reserved
68 u32 MacMaxFrameLen; // 0xA0 - AXGMAC Maximum Frame Length
69 u32 MacReserved2[2]; // 0xA4 - AXGMAC Reserved
70 u32 MacRevision; // 0xAC - AXGMAC Revision Level Register
71 u32 MacReserved3[4]; // 0xB0 - AXGMAC Reserved
72 u32 MacAmiimCmd; // 0xC0 - AXGMAC AMIIM Command Register
73 u32 MacAmiimField; // 0xC4 - AXGMAC AMIIM Field Register
74 u32 MacAmiimConfig; // 0xC8 - AXGMAC AMIIM Configuration Register
75 u32 MacAmiimLink; // 0xCC - AXGMAC AMIIM Link Fail Vector Register
76 u32 MacAmiimIndicator; // 0xD0 - AXGMAC AMIIM Indicator Registor
77 u32 PadTo0x100[11]; // 0xD4 - 0x100 - Pad
78 u32 XmtConfig; // 0x100 - Transmit Configuration Register
79 u32 RcvConfig; // 0x104 - Receive Configuration Register 1
80 u32 LinkAddress0Low; // 0x108 - Link address 0
81 u32 LinkAddress0High; // 0x10C - Link address 0
82 u32 LinkAddress1Low; // 0x110 - Link address 1
83 u32 LinkAddress1High; // 0x114 - Link address 1
84 u32 LinkAddress2Low; // 0x118 - Link address 2
85 u32 LinkAddress2High; // 0x11C - Link address 2
86 u32 LinkAddress3Low; // 0x120 - Link address 3
87 u32 LinkAddress3High; // 0x124 - Link address 3
88 u32 ToeplitzKey[10]; // 0x128 - 0x150 - Toeplitz key
89 u32 SocketKey[10]; // 0x150 - 0x178 - Socket Key
90 u32 LinkStatus; // 0x178 - Link status
91 u32 ClearStats; // 0x17C - Clear Stats
92 u32 XmtErrorsLow; // 0x180 - Transmit stats - errors
93 u32 XmtErrorsHigh; // 0x184 - Transmit stats - errors
94 u32 XmtFramesLow; // 0x188 - Transmit stats - frame count
95 u32 XmtFramesHigh; // 0x18C - Transmit stats - frame count
96 u32 XmtBytesLow; // 0x190 - Transmit stats - byte count
97 u32 XmtBytesHigh; // 0x194 - Transmit stats - byte count
98 u32 XmtTcpSegmentsLow; // 0x198 - Transmit stats - TCP segments
99 u32 XmtTcpSegmentsHigh; // 0x19C - Transmit stats - TCP segments
100 u32 XmtTcpBytesLow; // 0x1A0 - Transmit stats - TCP bytes
101 u32 XmtTcpBytesHigh; // 0x1A4 - Transmit stats - TCP bytes
102 u32 RcvErrorsLow; // 0x1A8 - Receive stats - errors
103 u32 RcvErrorsHigh; // 0x1AC - Receive stats - errors
104 u32 RcvFramesLow; // 0x1B0 - Receive stats - frame count
105 u32 RcvFramesHigh; // 0x1B4 - Receive stats - frame count
106 u32 RcvBytesLow; // 0x1B8 - Receive stats - byte count
107 u32 RcvBytesHigh; // 0x1BC - Receive stats - byte count
108 u32 RcvTcpSegmentsLow; // 0x1C0 - Receive stats - TCP segments
109 u32 RcvTcpSegmentsHigh; // 0x1C4 - Receive stats - TCP segments
110 u32 RcvTcpBytesLow; // 0x1C8 - Receive stats - TCP bytes
111 u32 RcvTcpBytesHigh; // 0x1CC - Receive stats - TCP bytes
112 u32 PadTo0x200[12]; // 0x1D0 - 0x200 - Pad
113 u32 Software[1920]; // 0x200 - 0x2000 - Software defined (not used)
114 u32 MsixTable[1024]; // 0x2000 - 0x3000 - MSIX Table
115 u32 MsixBitArray[1024]; // 0x3000 - 0x4000 - MSIX Pending Bit Array
116} SXG_HW_REGS, *PSXG_HW_REGS;
117#pragma pack(pop)
118
119// Microcode Address Flags
120#define MICROCODE_ADDRESS_GO 0x80000000 // Start microcode
121#define MICROCODE_ADDRESS_WRITE 0x40000000 // Store microcode
122#define MICROCODE_ADDRESS_READ 0x20000000 // Read microcode
123#define MICROCODE_ADDRESS_PARITY 0x10000000 // Parity error detected
124#define MICROCODE_ADDRESS_MASK 0x00001FFF // Address bits
125
126// Link Address Registers
127#define LINK_ADDRESS_ENABLE 0x80000000 // Applied to link address high
128
129// Microsoft register space size
130#define SXG_UCODEREG_MEMSIZE 0x40000 // 256k
131
132// Sahara microcode register address format. The command code,
133// extended command code, and associated processor are encoded in
134// the address bits as follows
135#define SXG_ADDRESS_CODE_SHIFT 2 // Base command code
136#define SXG_ADDRESS_CODE_MASK 0x0000003C
137#define SXG_ADDRESS_EXCODE_SHIFT 6 // Extended (or sub) command code
138#define SXG_ADDRESS_EXCODE_MASK 0x00001FC0
139#define SXG_ADDRESS_CPUID_SHIFT 13 // CPU
140#define SXG_ADDRESS_CPUID_MASK 0x0003E000
141#define SXG_REGISTER_SIZE_PER_CPU 0x00002000 // Used to sanity check UCODE_REGS structure
142
143// Sahara receive sequencer status values
144#define SXG_RCV_STATUS_ATTN 0x80000000 // Attention
145#define SXG_RCV_STATUS_TRANSPORT_MASK 0x3F000000 // Transport mask
146#define SXG_RCV_STATUS_TRANSPORT_ERROR 0x20000000 // Transport error
147#define SXG_RCV_STATUS_TRANSPORT_CSUM 0x23000000 // Transport cksum error
148#define SXG_RCV_STATUS_TRANSPORT_UFLOW 0x22000000 // Transport underflow
149#define SXG_RCV_STATUS_TRANSPORT_HDRLEN 0x20000000 // Transport header length
150#define SXG_RCV_STATUS_TRANSPORT_FLAGS 0x10000000 // Transport flags detected
151#define SXG_RCV_STATUS_TRANSPORT_OPTS 0x08000000 // Transport options detected
152#define SXG_RCV_STATUS_TRANSPORT_SESS_MASK 0x07000000 // Transport DDP
153#define SXG_RCV_STATUS_TRANSPORT_DDP 0x06000000 // Transport DDP
154#define SXG_RCV_STATUS_TRANSPORT_iSCSI 0x05000000 // Transport iSCSI
155#define SXG_RCV_STATUS_TRANSPORT_NFS 0x04000000 // Transport NFS
156#define SXG_RCV_STATUS_TRANSPORT_FTP 0x03000000 // Transport FTP
157#define SXG_RCV_STATUS_TRANSPORT_HTTP 0x02000000 // Transport HTTP
158#define SXG_RCV_STATUS_TRANSPORT_SMB 0x01000000 // Transport SMB
159#define SXG_RCV_STATUS_NETWORK_MASK 0x00FF0000 // Network mask
160#define SXG_RCV_STATUS_NETWORK_ERROR 0x00800000 // Network error
161#define SXG_RCV_STATUS_NETWORK_CSUM 0x00830000 // Network cksum error
162#define SXG_RCV_STATUS_NETWORK_UFLOW 0x00820000 // Network underflow error
163#define SXG_RCV_STATUS_NETWORK_HDRLEN 0x00800000 // Network header length
164#define SXG_RCV_STATUS_NETWORK_OFLOW 0x00400000 // Network overflow detected
165#define SXG_RCV_STATUS_NETWORK_MCAST 0x00200000 // Network multicast detected
166#define SXG_RCV_STATUS_NETWORK_OPTIONS 0x00100000 // Network options detected
167#define SXG_RCV_STATUS_NETWORK_OFFSET 0x00080000 // Network offset detected
168#define SXG_RCV_STATUS_NETWORK_FRAGMENT 0x00040000 // Network fragment detected
169#define SXG_RCV_STATUS_NETWORK_TRANS_MASK 0x00030000 // Network transport type mask
170#define SXG_RCV_STATUS_NETWORK_UDP 0x00020000 // UDP
171#define SXG_RCV_STATUS_NETWORK_TCP 0x00010000 // TCP
172#define SXG_RCV_STATUS_IPONLY 0x00008000 // IP-only not TCP
173#define SXG_RCV_STATUS_PKT_PRI 0x00006000 // Receive priority
174#define SXG_RCV_STATUS_PKT_PRI_SHFT 13 // Receive priority shift
175#define SXG_RCV_STATUS_PARITY 0x00001000 // MAC Receive RAM parity error
176#define SXG_RCV_STATUS_ADDRESS_MASK 0x00000F00 // Link address detection mask
177#define SXG_RCV_STATUS_ADDRESS_D 0x00000B00 // Link address D
178#define SXG_RCV_STATUS_ADDRESS_C 0x00000A00 // Link address C
179#define SXG_RCV_STATUS_ADDRESS_B 0x00000900 // Link address B
180#define SXG_RCV_STATUS_ADDRESS_A 0x00000800 // Link address A
181#define SXG_RCV_STATUS_ADDRESS_BCAST 0x00000300 // Link address broadcast
182#define SXG_RCV_STATUS_ADDRESS_MCAST 0x00000200 // Link address multicast
183#define SXG_RCV_STATUS_ADDRESS_CMCAST 0x00000100 // Link control multicast
184#define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask
185#define SXG_RCV_STATUS_LINK_ERROR 0x00000080 // Link error
186#define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask
187#define SXG_RCV_STATUS_LINK_PARITY 0x00000087 // RcvMacQ parity error
188#define SXG_RCV_STATUS_LINK_EARLY 0x00000086 // Data early
189#define SXG_RCV_STATUS_LINK_BUFOFLOW 0x00000085 // Buffer overflow
190#define SXG_RCV_STATUS_LINK_CODE 0x00000084 // Link code error
191#define SXG_RCV_STATUS_LINK_DRIBBLE 0x00000083 // Dribble nibble
192#define SXG_RCV_STATUS_LINK_CRC 0x00000082 // CRC error
193#define SXG_RCV_STATUS_LINK_OFLOW 0x00000081 // Link overflow
194#define SXG_RCV_STATUS_LINK_UFLOW 0x00000080 // Link underflow
195#define SXG_RCV_STATUS_LINK_8023 0x00000020 // 802.3
196#define SXG_RCV_STATUS_LINK_SNAP 0x00000010 // Snap
197#define SXG_RCV_STATUS_LINK_VLAN 0x00000008 // VLAN
198#define SXG_RCV_STATUS_LINK_TYPE_MASK 0x00000007 // Network type mask
199#define SXG_RCV_STATUS_LINK_CONTROL 0x00000003 // Control packet
200#define SXG_RCV_STATUS_LINK_IPV6 0x00000002 // IPv6 packet
201#define SXG_RCV_STATUS_LINK_IPV4 0x00000001 // IPv4 packet
202
203/***************************************************************************
204 * Sahara receive and transmit configuration registers
205 ***************************************************************************/
206#define RCV_CONFIG_RESET 0x80000000 // RcvConfig register reset
207#define RCV_CONFIG_ENABLE 0x40000000 // Enable the receive logic
208#define RCV_CONFIG_ENPARSE 0x20000000 // Enable the receive parser
209#define RCV_CONFIG_SOCKET 0x10000000 // Enable the socket detector
210#define RCV_CONFIG_RCVBAD 0x08000000 // Receive all bad frames
211#define RCV_CONFIG_CONTROL 0x04000000 // Receive all control frames
212#define RCV_CONFIG_RCVPAUSE 0x02000000 // Enable pause transmit when attn
213#define RCV_CONFIG_TZIPV6 0x01000000 // Include TCP port w/ IPv6 toeplitz
214#define RCV_CONFIG_TZIPV4 0x00800000 // Include TCP port w/ IPv4 toeplitz
215#define RCV_CONFIG_FLUSH 0x00400000 // Flush buffers
216#define RCV_CONFIG_PRIORITY_MASK 0x00300000 // Priority level
217#define RCV_CONFIG_HASH_MASK 0x00030000 // Hash depth
218#define RCV_CONFIG_HASH_8 0x00000000 // Hash depth 8
219#define RCV_CONFIG_HASH_16 0x00010000 // Hash depth 16
220#define RCV_CONFIG_HASH_4 0x00020000 // Hash depth 4
221#define RCV_CONFIG_HASH_2 0x00030000 // Hash depth 2
222#define RCV_CONFIG_BUFLEN_MASK 0x0000FFF0 // Buffer length bits 15:4. ie multiple of 16.
223#define RCV_CONFIG_SKT_DIS 0x00000008 // Disable socket detection on attn
224// Macro to determine RCV_CONFIG_BUFLEN based on maximum frame size.
225// We add 18 bytes for Sahara receive status and padding, plus 4 bytes for CRC,
226// and round up to nearest 16 byte boundary
227#define RCV_CONFIG_BUFSIZE(_MaxFrame) ((((_MaxFrame) + 22) + 15) & RCV_CONFIG_BUFLEN_MASK)
228
229#define XMT_CONFIG_RESET 0x80000000 // XmtConfig register reset
230#define XMT_CONFIG_ENABLE 0x40000000 // Enable transmit logic
231#define XMT_CONFIG_MAC_PARITY 0x20000000 // Inhibit MAC RAM parity error
232#define XMT_CONFIG_BUF_PARITY 0x10000000 // Inhibit D2F buffer parity error
233#define XMT_CONFIG_MEM_PARITY 0x08000000 // Inhibit 1T SRAM parity error
234#define XMT_CONFIG_INVERT_PARITY 0x04000000 // Invert MAC RAM parity
235#define XMT_CONFIG_INITIAL_IPID 0x0000FFFF // Initial IPID
236
237/***************************************************************************
238 * A-XGMAC Registers - Occupy 0x80 - 0xD4 of the SXG_HW_REGS
239 *
240 * Full register descriptions can be found in axgmac.pdf
241 ***************************************************************************/
242// A-XGMAC Configuration Register 0
243#define AXGMAC_CFG0_SUB_RESET 0x80000000 // Sub module reset
244#define AXGMAC_CFG0_RCNTRL_RESET 0x00400000 // Receive control reset
245#define AXGMAC_CFG0_RFUNC_RESET 0x00200000 // Receive function reset
246#define AXGMAC_CFG0_TCNTRL_RESET 0x00040000 // Transmit control reset
247#define AXGMAC_CFG0_TFUNC_RESET 0x00020000 // Transmit function reset
248#define AXGMAC_CFG0_MII_RESET 0x00010000 // MII Management reset
249
250// A-XGMAC Configuration Register 1
251#define AXGMAC_CFG1_XMT_PAUSE 0x80000000 // Allow the sending of Pause frames
252#define AXGMAC_CFG1_XMT_EN 0x40000000 // Enable transmit
253#define AXGMAC_CFG1_RCV_PAUSE 0x20000000 // Allow the detection of Pause frames
254#define AXGMAC_CFG1_RCV_EN 0x10000000 // Enable receive
255#define AXGMAC_CFG1_XMT_STATE 0x04000000 // Current transmit state - READ ONLY
256#define AXGMAC_CFG1_RCV_STATE 0x01000000 // Current receive state - READ ONLY
257#define AXGMAC_CFG1_XOFF_SHORT 0x00001000 // Only pause for 64 slot on XOFF
258#define AXGMAC_CFG1_XMG_FCS1 0x00000400 // Delay transmit FCS 1 4-byte word
259#define AXGMAC_CFG1_XMG_FCS2 0x00000800 // Delay transmit FCS 2 4-byte words
260#define AXGMAC_CFG1_XMG_FCS3 0x00000C00 // Delay transmit FCS 3 4-byte words
261#define AXGMAC_CFG1_RCV_FCS1 0x00000100 // Delay receive FCS 1 4-byte word
262#define AXGMAC_CFG1_RCV_FCS2 0x00000200 // Delay receive FCS 2 4-byte words
263#define AXGMAC_CFG1_RCV_FCS3 0x00000300 // Delay receive FCS 3 4-byte words
264#define AXGMAC_CFG1_PKT_OVERRIDE 0x00000080 // Per-packet override enable
265#define AXGMAC_CFG1_SWAP 0x00000040 // Byte swap enable
266#define AXGMAC_CFG1_SHORT_ASSERT 0x00000020 // ASSERT srdrpfrm on short frame (<64)
267#define AXGMAC_CFG1_RCV_STRICT 0x00000010 // RCV only 802.3AE when CLEAR
268#define AXGMAC_CFG1_CHECK_LEN 0x00000008 // Verify frame length
269#define AXGMAC_CFG1_GEN_FCS 0x00000004 // Generate FCS
270#define AXGMAC_CFG1_PAD_MASK 0x00000003 // Mask for pad bits
271#define AXGMAC_CFG1_PAD_64 0x00000001 // Pad frames to 64 bytes
272#define AXGMAC_CFG1_PAD_VLAN 0x00000002 // Detect VLAN and pad to 68 bytes
273#define AXGMAC_CFG1_PAD_68 0x00000003 // Pad to 68 bytes
274
275// A-XGMAC Configuration Register 2
276#define AXGMAC_CFG2_GEN_PAUSE 0x80000000 // Generate single pause frame (test)
277#define AXGMAC_CFG2_LF_MANUAL 0x08000000 // Manual link fault sequence
278#define AXGMAC_CFG2_LF_AUTO 0x04000000 // Auto link fault sequence
279#define AXGMAC_CFG2_LF_REMOTE 0x02000000 // Remote link fault (READ ONLY)
280#define AXGMAC_CFG2_LF_LOCAL 0x01000000 // Local link fault (READ ONLY)
281#define AXGMAC_CFG2_IPG_MASK 0x001F0000 // Inter packet gap
282#define AXGMAC_CFG2_IPG_SHIFT 16
283#define AXGMAC_CFG2_PAUSE_XMT 0x00008000 // Pause transmit module
284#define AXGMAC_CFG2_IPG_EXTEN 0x00000020 // Enable IPG extension algorithm
285#define AXGMAC_CFG2_IPGEX_MASK 0x0000001F // IPG extension
286
287// A-XGMAC Configuration Register 3
288#define AXGMAC_CFG3_RCV_DROP 0xFFFF0000 // Receive frame drop filter
289#define AXGMAC_CFG3_RCV_DONT_CARE 0x0000FFFF // Receive frame don't care filter
290
291// A-XGMAC Station Address Register - Octets 1-4
292#define AXGMAC_SARLOW_OCTET_ONE 0xFF000000 // First octet
293#define AXGMAC_SARLOW_OCTET_TWO 0x00FF0000 // Second octet
294#define AXGMAC_SARLOW_OCTET_THREE 0x0000FF00 // Third octet
295#define AXGMAC_SARLOW_OCTET_FOUR 0x000000FF // Fourth octet
296
297// A-XGMAC Station Address Register - Octets 5-6
298#define AXGMAC_SARHIGH_OCTET_FIVE 0xFF000000 // Fifth octet
299#define AXGMAC_SARHIGH_OCTET_SIX 0x00FF0000 // Sixth octet
300
301// A-XGMAC Maximum frame length register
302#define AXGMAC_MAXFRAME_XMT 0x3FFF0000 // Maximum transmit frame length
303#define AXGMAC_MAXFRAME_XMT_SHIFT 16
304#define AXGMAC_MAXFRAME_RCV 0x0000FFFF // Maximum receive frame length
305// This register doesn't need to be written for standard MTU.
306// For jumbo, I'll just statically define the value here. This
307// value sets the receive byte count to 9036 (0x234C) and the
308// transmit WORD count to 2259 (0x8D3). These values include 22
309// bytes of padding beyond the jumbo MTU of 9014
310#define AXGMAC_MAXFRAME_JUMBO 0x08D3234C
311
312// A-XGMAC Revision level
313#define AXGMAC_REVISION_MASK 0x0000FFFF // Revision level
314
315// A-XGMAC AMIIM Command Register
316#define AXGMAC_AMIIM_CMD_START 0x00000008 // Command start
317#define AXGMAC_AMIIM_CMD_MASK 0x00000007 // Command
318#define AXGMAC_AMIIM_CMD_LEGACY_WRITE 1 // 10/100/1000 Mbps Phy Write
319#define AXGMAC_AMIIM_CMD_LEGACY_READ 2 // 10/100/1000 Mbps Phy Read
320#define AXGMAC_AMIIM_CMD_MONITOR_SINGLE 3 // Monitor single PHY
321#define AXGMAC_AMIIM_CMD_MONITOR_MULTIPLE 4 // Monitor multiple contiguous PHYs
322#define AXGMAC_AMIIM_CMD_10G_OPERATION 5 // Present AMIIM Field Reg
323#define AXGMAC_AMIIM_CMD_CLEAR_LINK_FAIL 6 // Clear Link Fail Bit in MIIM
324
325// A-XGMAC AMIIM Field Register
326#define AXGMAC_AMIIM_FIELD_ST 0xC0000000 // 2-bit ST field
327#define AXGMAC_AMIIM_FIELD_ST_SHIFT 30
328#define AXGMAC_AMIIM_FIELD_OP 0x30000000 // 2-bit OP field
329#define AXGMAC_AMIIM_FIELD_OP_SHIFT 28
330#define AXGMAC_AMIIM_FIELD_PORT_ADDR 0x0F800000 // Port address field (hstphyadx in spec)
331#define AXGMAC_AMIIM_FIELD_PORT_SHIFT 23
332#define AXGMAC_AMIIM_FIELD_DEV_ADDR 0x007C0000 // Device address field (hstregadx in spec)
333#define AXGMAC_AMIIM_FIELD_DEV_SHIFT 18
334#define AXGMAC_AMIIM_FIELD_TA 0x00030000 // 2-bit TA field
335#define AXGMAC_AMIIM_FIELD_TA_SHIFT 16
336#define AXGMAC_AMIIM_FIELD_DATA 0x0000FFFF // Data field
337
338// Values for the AXGMAC_AMIIM_FIELD_OP field in the A-XGMAC AMIIM Field Register
339#define MIIM_OP_ADDR 0 // MIIM Address set operation
340#define MIIM_OP_WRITE 1 // MIIM Write register operation
341#define MIIM_OP_READ 2 // MIIM Read register operation
342#define MIIM_OP_ADDR_SHIFT (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT)
343
344// Values for the AXGMAC_AMIIM_FIELD_PORT_ADDR field in the A-XGMAC AMIIM Field Register
345#define MIIM_PORT_NUM 1 // All Sahara MIIM modules use port 1
346
347// Values for the AXGMAC_AMIIM_FIELD_DEV_ADDR field in the A-XGMAC AMIIM Field Register
348#define MIIM_DEV_PHY_PMA 1 // PHY PMA/PMD module MIIM device number
349#define MIIM_DEV_PHY_PCS 3 // PHY PCS module MIIM device number
350#define MIIM_DEV_PHY_XS 4 // PHY XS module MIIM device number
351#define MIIM_DEV_XGXS 5 // XGXS MIIM device number
352
353// Values for the AXGMAC_AMIIM_FIELD_TA field in the A-XGMAC AMIIM Field Register
354#define MIIM_TA_10GB 2 // set to 2 for 10 GB operation
355
356// A-XGMAC AMIIM Configuration Register
357#define AXGMAC_AMIIM_CFG_NOPREAM 0x00000080 // Bypass preamble of mngmt frame
358#define AXGMAC_AMIIM_CFG_HALF_CLOCK 0x0000007F // half-clock duration of MDC output
359
360// A-XGMAC AMIIM Indicator Register
361#define AXGMAC_AMIIM_INDC_LINK 0x00000010 // Link status from legacy PHY or MMD
362#define AXGMAC_AMIIM_INDC_MPHY 0x00000008 // Multiple phy operation in progress
363#define AXGMAC_AMIIM_INDC_SPHY 0x00000004 // Single phy operation in progress
364#define AXGMAC_AMIIM_INDC_MON 0x00000002 // Single or multiple monitor cmd
365#define AXGMAC_AMIIM_INDC_BUSY 0x00000001 // Set until cmd operation complete
366
367// Link Status and Control Register
368#define LS_PHY_CLR_RESET 0x80000000 // Clear reset signal to PHY
369#define LS_SERDES_POWER_DOWN 0x40000000 // Power down the Sahara Serdes
370#define LS_XGXS_ENABLE 0x20000000 // Enable the XAUI XGXS logic
371#define LS_XGXS_CTL 0x10000000 // Hold XAUI XGXS logic reset until Serdes is up
372#define LS_SERDES_DOWN 0x08000000 // When 0, XAUI Serdes is up and initialization is complete
373#define LS_TRACE_DOWN 0x04000000 // When 0, Trace Serdes is up and initialization is complete
374#define LS_PHY_CLK_25MHZ 0x02000000 // Set PHY clock to 25 MHz (else 156.125 MHz)
375#define LS_PHY_CLK_EN 0x01000000 // Enable clock to PHY
376#define LS_XAUI_LINK_UP 0x00000010 // XAUI link is up
377#define LS_XAUI_LINK_CHNG 0x00000008 // XAUI link status has changed
378#define LS_LINK_ALARM 0x00000004 // Link alarm pin
379#define LS_ATTN_CTRL_MASK 0x00000003 // Mask link attention control bits
380#define LS_ATTN_ALARM 0x00000000 // 00 => Attn on link alarm
381#define LS_ATTN_ALARM_OR_STAT_CHNG 0x00000001 // 01 => Attn on link alarm or status change
382#define LS_ATTN_STAT_CHNG 0x00000002 // 10 => Attn on link status change
383#define LS_ATTN_NONE 0x00000003 // 11 => no Attn
384
385// Link Address High Registers
386#define LINK_ADDR_ENABLE 0x80000000 // Enable this link address
387
388
389/***************************************************************************
390 * XGXS XAUI XGMII Extender registers
391 *
392 * Full register descriptions can be found in mxgxs.pdf
393 ***************************************************************************/
394// XGXS Register Map
395#define XGXS_ADDRESS_CONTROL1 0x0000 // XS Control 1
396#define XGXS_ADDRESS_STATUS1 0x0001 // XS Status 1
397#define XGXS_ADDRESS_DEVID_LOW 0x0002 // XS Device ID (low)
398#define XGXS_ADDRESS_DEVID_HIGH 0x0003 // XS Device ID (high)
399#define XGXS_ADDRESS_SPEED 0x0004 // XS Speed ability
400#define XGXS_ADDRESS_DEV_LOW 0x0005 // XS Devices in package
401#define XGXS_ADDRESS_DEV_HIGH 0x0006 // XS Devices in package
402#define XGXS_ADDRESS_STATUS2 0x0008 // XS Status 2
403#define XGXS_ADDRESS_PKGID_lOW 0x000E // XS Package Identifier
404#define XGXS_ADDRESS_PKGID_HIGH 0x000F // XS Package Identifier
405#define XGXS_ADDRESS_LANE_STATUS 0x0018 // 10G XGXS Lane Status
406#define XGXS_ADDRESS_TEST_CTRL 0x0019 // 10G XGXS Test Control
407#define XGXS_ADDRESS_RESET_LO1 0x8000 // Vendor-Specific Reset Lo 1
408#define XGXS_ADDRESS_RESET_LO2 0x8001 // Vendor-Specific Reset Lo 2
409#define XGXS_ADDRESS_RESET_HI1 0x8002 // Vendor-Specific Reset Hi 1
410#define XGXS_ADDRESS_RESET_HI2 0x8003 // Vendor-Specific Reset Hi 2
411
412// XS Control 1 register bit definitions
413#define XGXS_CONTROL1_RESET 0x8000 // Reset - self clearing
414#define XGXS_CONTROL1_LOOPBACK 0x4000 // Enable loopback
415#define XGXS_CONTROL1_SPEED1 0x2000 // 0 = unspecified, 1 = 10Gb+
416#define XGXS_CONTROL1_LOWPOWER 0x0400 // 1 = Low power mode
417#define XGXS_CONTROL1_SPEED2 0x0040 // Same as SPEED1 (?)
418#define XGXS_CONTROL1_SPEED 0x003C // Everything reserved except zero (?)
419
420// XS Status 1 register bit definitions
421#define XGXS_STATUS1_FAULT 0x0080 // Fault detected
422#define XGXS_STATUS1_LINK 0x0004 // 1 = Link up
423#define XGXS_STATUS1_LOWPOWER 0x0002 // 1 = Low power supported
424
425// XS Speed register bit definitions
426#define XGXS_SPEED_10G 0x0001 // 1 = 10G capable
427
428// XS Devices register bit definitions
429#define XGXS_DEVICES_DTE 0x0020 // DTE XS Present
430#define XGXS_DEVICES_PHY 0x0010 // PHY XS Present
431#define XGXS_DEVICES_PCS 0x0008 // PCS Present
432#define XGXS_DEVICES_WIS 0x0004 // WIS Present
433#define XGXS_DEVICES_PMD 0x0002 // PMD/PMA Present
434#define XGXS_DEVICES_CLAUSE22 0x0001 // Clause 22 registers present
435
436// XS Devices High register bit definitions
437#define XGXS_DEVICES_VENDOR2 0x8000 // Vendor specific device 2
438#define XGXS_DEVICES_VENDOR1 0x4000 // Vendor specific device 1
439
440// XS Status 2 register bit definitions
441#define XGXS_STATUS2_DEV_MASK 0xC000 // Device present mask
442#define XGXS_STATUS2_DEV_RESPOND 0x8000 // Device responding
443#define XGXS_STATUS2_XMT_FAULT 0x0800 // Transmit fault
444#define XGXS_STATUS2_RCV_FAULT 0x0400 // Receive fault
445
446// XS Package ID High register bit definitions
447#define XGXS_PKGID_HIGH_ORG 0xFC00 // Organizationally Unique
448#define XGXS_PKGID_HIGH_MFG 0x03F0 // Manufacturer Model
449#define XGXS_PKGID_HIGH_REV 0x000F // Revision Number
450
451// XS Lane Status register bit definitions
452#define XGXS_LANE_PHY 0x1000 // PHY/DTE lane alignment status
453#define XGXS_LANE_PATTERN 0x0800 // Pattern testing ability
454#define XGXS_LANE_LOOPBACK 0x0400 // PHY loopback ability
455#define XGXS_LANE_SYNC3 0x0008 // Lane 3 sync
456#define XGXS_LANE_SYNC2 0x0004 // Lane 2 sync
457#define XGXS_LANE_SYNC1 0x0002 // Lane 1 sync
458#define XGXS_LANE_SYNC0 0x0001 // Lane 0 sync
459
460// XS Test Control register bit definitions
461#define XGXS_TEST_PATTERN_ENABLE 0x0004 // Test pattern enabled
462#define XGXS_TEST_PATTERN_MASK 0x0003 // Test patterns
463#define XGXS_TEST_PATTERN_RSVD 0x0003 // Test pattern - reserved
464#define XGXS_TEST_PATTERN_MIX 0x0002 // Test pattern - mixed
465#define XGXS_TEST_PATTERN_LOW 0x0001 // Test pattern - low
466#define XGXS_TEST_PATTERN_HIGH 0x0001 // Test pattern - high
467
468/***************************************************************************
469 * External MDIO Bus Registers
470 *
471 * Full register descriptions can be found in PHY/XENPAK/IEEE specs
472 ***************************************************************************/
473// LASI (Link Alarm Status Interrupt) Registers (located in MIIM_DEV_PHY_PMA device)
474#define LASI_RX_ALARM_CONTROL 0x9000 // LASI RX_ALARM Control
475#define LASI_TX_ALARM_CONTROL 0x9001 // LASI TX_ALARM Control
476#define LASI_CONTROL 0x9002 // LASI Control
477#define LASI_RX_ALARM_STATUS 0x9003 // LASI RX_ALARM Status
478#define LASI_TX_ALARM_STATUS 0x9004 // LASI TX_ALARM Status
479#define LASI_STATUS 0x9005 // LASI Status
480
481// LASI_CONTROL bit definitions
482#define LASI_CTL_RX_ALARM_ENABLE 0x0004 // Enable RX_ALARM interrupts
483#define LASI_CTL_TX_ALARM_ENABLE 0x0002 // Enable TX_ALARM interrupts
484#define LASI_CTL_LS_ALARM_ENABLE 0x0001 // Enable Link Status interrupts
485
486// LASI_STATUS bit definitions
487#define LASI_STATUS_RX_ALARM 0x0004 // RX_ALARM status
488#define LASI_STATUS_TX_ALARM 0x0002 // TX_ALARM status
489#define LASI_STATUS_LS_ALARM 0x0001 // Link Status
490
491// PHY registers - PMA/PMD (device 1)
492#define PHY_PMA_CONTROL1 0x0000 // PMA/PMD Control 1
493#define PHY_PMA_STATUS1 0x0001 // PMA/PMD Status 1
494#define PHY_PMA_RCV_DET 0x000A // PMA/PMD Receive Signal Detect
495 // other PMA/PMD registers exist and can be defined as needed
496
497// PHY registers - PCS (device 3)
498#define PHY_PCS_CONTROL1 0x0000 // PCS Control 1
499#define PHY_PCS_STATUS1 0x0001 // PCS Status 1
500#define PHY_PCS_10G_STATUS1 0x0020 // PCS 10GBASE-R Status 1
501 // other PCS registers exist and can be defined as needed
502
503// PHY registers - XS (device 4)
504#define PHY_XS_CONTROL1 0x0000 // XS Control 1
505#define PHY_XS_STATUS1 0x0001 // XS Status 1
506#define PHY_XS_LANE_STATUS 0x0018 // XS Lane Status
507 // other XS registers exist and can be defined as needed
508
509// PHY_PMA_CONTROL1 register bit definitions
510#define PMA_CONTROL1_RESET 0x8000 // PMA/PMD reset
511
512// PHY_PMA_RCV_DET register bit definitions
513#define PMA_RCV_DETECT 0x0001 // PMA/PMD receive signal detect
514
515// PHY_PCS_10G_STATUS1 register bit definitions
516#define PCS_10B_BLOCK_LOCK 0x0001 // PCS 10GBASE-R locked to receive blocks
517
518// PHY_XS_LANE_STATUS register bit definitions
519#define XS_LANE_ALIGN 0x1000 // XS transmit lanes aligned
520
521// PHY Microcode download data structure
522typedef struct _PHY_UCODE {
523 ushort Addr;
524 ushort Data;
525} PHY_UCODE, *PPHY_UCODE;
526
527
528/*****************************************************************************
529 * Transmit Sequencer Command Descriptor definitions
530 *****************************************************************************/
531
532// This descriptor must be placed in GRAM. The address of this descriptor
533// (along with a couple of control bits) is pushed onto the PxhCmdQ or PxlCmdQ
534// (Proxy high or low command queue). This data is read by the Proxy Sequencer,
535// which pushes it onto the XmtCmdQ, which is (eventually) read by the Transmit
536// Sequencer, causing a packet to be transmitted. Not all fields are valid for
537// all commands - see the Sahara spec for details. Note that this structure is
538// only valid when compiled on a little endian machine.
539#pragma pack(push, 1)
540typedef struct _XMT_DESC {
541 ushort XmtLen; // word 0, bits [15:0] - transmit length
542 unsigned char XmtCtl; // word 0, bits [23:16] - transmit control byte
543 unsigned char Cmd; // word 0, bits [31:24] - transmit command plus misc.
544 u32 XmtBufId; // word 1, bits [31:0] - transmit buffer ID
545 unsigned char TcpStrt; // word 2, bits [7:0] - byte address of TCP header
546 unsigned char IpStrt; // word 2, bits [15:8] - byte address of IP header
547 ushort IpCkSum; // word 2, bits [31:16] - partial IP checksum
548 ushort TcpCkSum; // word 3, bits [15:0] - partial TCP checksum
549 ushort Rsvd1; // word 3, bits [31:16] - PAD
550 u32 Rsvd2; // word 4, bits [31:0] - PAD
551 u32 Rsvd3; // word 5, bits [31:0] - PAD
552 u32 Rsvd4; // word 6, bits [31:0] - PAD
553 u32 Rsvd5; // word 7, bits [31:0] - PAD
554} XMT_DESC, *PXMT_DESC;
555#pragma pack(pop)
556
557// XMT_DESC Cmd byte definitions
558 // command codes
559#define XMT_DESC_CMD_RAW_SEND 0 // raw send descriptor
560#define XMT_DESC_CMD_CSUM_INSERT 1 // checksum insert descriptor
561#define XMT_DESC_CMD_FORMAT 2 // format descriptor
562#define XMT_DESC_CMD_PRIME 3 // prime descriptor
563#define XMT_DESC_CMD_CODE_SHFT 6 // comand code shift (shift to bits [31:30] in word 0)
564 // shifted command codes
565#define XMT_RAW_SEND (XMT_DESC_CMD_RAW_SEND << XMT_DESC_CMD_CODE_SHFT)
566#define XMT_CSUM_INSERT (XMT_DESC_CMD_CSUM_INSERT << XMT_DESC_CMD_CODE_SHFT)
567#define XMT_FORMAT (XMT_DESC_CMD_FORMAT << XMT_DESC_CMD_CODE_SHFT)
568#define XMT_PRIME (XMT_DESC_CMD_PRIME << XMT_DESC_CMD_CODE_SHFT)
569
570// XMT_DESC Control Byte (XmtCtl) definitions
571// NOTE: These bits do not work on Sahara (Rev A)!
572#define XMT_CTL_PAUSE_FRAME 0x80 // current frame is a pause control frame (for statistics)
573#define XMT_CTL_CONTROL_FRAME 0x40 // current frame is a control frame (for statistics)
574#define XMT_CTL_PER_PKT_QUAL 0x20 // per packet qualifier
575#define XMT_CTL_PAD_MODE_NONE 0x00 // do not pad frame
576#define XMT_CTL_PAD_MODE_64 0x08 // pad frame to 64 bytes
577#define XMT_CTL_PAD_MODE_VLAN_68 0x10 // pad frame to 64 bytes, and VLAN frames to 68 bytes
578#define XMT_CTL_PAD_MODE_68 0x18 // pad frame to 68 bytes
579#define XMT_CTL_GEN_FCS 0x04 // generate FCS (CRC) for this frame
580#define XMT_CTL_DELAY_FCS_0 0x00 // do not delay FCS calcution
581#define XMT_CTL_DELAY_FCS_1 0x01 // delay FCS calculation by 1 (4-byte) word
582#define XMT_CTL_DELAY_FCS_2 0x02 // delay FCS calculation by 2 (4-byte) words
583#define XMT_CTL_DELAY_FCS_3 0x03 // delay FCS calculation by 3 (4-byte) words
584
585// XMT_DESC XmtBufId definition
586#define XMT_BUF_ID_SHFT 8 // The Xmt buffer ID is formed by dividing
587 // the buffer (DRAM) address by 256 (or << 8)
588
589/*****************************************************************************
590 * Receiver Sequencer Definitions
591 *****************************************************************************/
592
593// Receive Event Queue (queues 3 - 6) bit definitions
594#define RCV_EVTQ_RBFID_MASK 0x0000FFFF // bit mask for the Receive Buffer ID
595
596// Receive Buffer ID definition
597#define RCV_BUF_ID_SHFT 5 // The Rcv buffer ID is formed by dividing
598 // the buffer (DRAM) address by 32 (or << 5)
599
600// Format of the 18 byte Receive Buffer returned by the
601// Receive Sequencer for received packets
602#pragma pack(push, 1)
603typedef struct _RCV_BUF_HDR {
604 u32 Status; // Status word from Rcv Seq Parser
605 ushort Length; // Rcv packet byte count
606 union {
607 ushort TcpCsum; // TCP checksum
608 struct {
609 unsigned char TcpCsumL; // lower 8 bits of the TCP checksum
610 unsigned char LinkHash; // Link hash (multicast frames only)
611 };
612 };
613 ushort SktHash; // Socket hash
614 unsigned char TcpHdrOffset; // TCP header offset into packet
615 unsigned char IpHdrOffset; // IP header offset into packet
616 u32 TpzHash; // Toeplitz hash
617 ushort Reserved; // Reserved
618} RCV_BUF_HDR, *PRCV_BUF_HDR;
619#pragma pack(pop)
620
621
622/*****************************************************************************
623 * Queue definitions
624 *****************************************************************************/
625
626// Ingress (read only) queue numbers
627#define PXY_BUF_Q 0 // Proxy Buffer Queue
628#define HST_EVT_Q 1 // Host Event Queue
629#define XMT_BUF_Q 2 // Transmit Buffer Queue
630#define SKT_EVL_Q 3 // RcvSqr Socket Event Low Priority Queue
631#define RCV_EVL_Q 4 // RcvSqr Rcv Event Low Priority Queue
632#define SKT_EVH_Q 5 // RcvSqr Socket Event High Priority Queue
633#define RCV_EVH_Q 6 // RcvSqr Rcv Event High Priority Queue
634#define DMA_RSP_Q 7 // Dma Response Queue - one per CPU context
635// Local (read/write) queue numbers
636#define LOCAL_A_Q 8 // Spare local Queue
637#define LOCAL_B_Q 9 // Spare local Queue
638#define LOCAL_C_Q 10 // Spare local Queue
639#define FSM_EVT_Q 11 // Finite-State-Machine Event Queue
640#define SBF_PAL_Q 12 // System Buffer Physical Address (low) Queue
641#define SBF_PAH_Q 13 // System Buffer Physical Address (high) Queue
642#define SBF_VAL_Q 14 // System Buffer Virtual Address (low) Queue
643#define SBF_VAH_Q 15 // System Buffer Virtual Address (high) Queue
644// Egress (write only) queue numbers
645#define H2G_CMD_Q 16 // Host to GlbRam DMA Command Queue
646#define H2D_CMD_Q 17 // Host to DRAM DMA Command Queue
647#define G2H_CMD_Q 18 // GlbRam to Host DMA Command Queue
648#define G2D_CMD_Q 19 // GlbRam to DRAM DMA Command Queue
649#define D2H_CMD_Q 20 // DRAM to Host DMA Command Queue
650#define D2G_CMD_Q 21 // DRAM to GlbRam DMA Command Queue
651#define D2D_CMD_Q 22 // DRAM to DRAM DMA Command Queue
652#define PXL_CMD_Q 23 // Low Priority Proxy Command Queue
653#define PXH_CMD_Q 24 // High Priority Proxy Command Queue
654#define RSQ_CMD_Q 25 // Receive Sequencer Command Queue
655#define RCV_BUF_Q 26 // Receive Buffer Queue
656
657// Bit definitions for the Proxy Command queues (PXL_CMD_Q and PXH_CMD_Q)
658#define PXY_COPY_EN 0x00200000 // enable copy of xmt descriptor to xmt command queue
659#define PXY_SIZE_16 0x00000000 // copy 16 bytes
660#define PXY_SIZE_32 0x00100000 // copy 32 bytes
661
662/*****************************************************************************
663 * SXG EEPROM/Flash Configuration Definitions
664 *****************************************************************************/
665#pragma pack(push, 1)
666
667//
668typedef struct _HW_CFG_DATA {
669 ushort Addr;
670 union {
671 ushort Data;
672 ushort Checksum;
673 };
674} HW_CFG_DATA, *PHW_CFG_DATA;
675
676//
677#define NUM_HW_CFG_ENTRIES ((128/sizeof(HW_CFG_DATA)) - 4)
678
679// MAC address
680typedef struct _SXG_CONFIG_MAC {
681 unsigned char MacAddr[6]; // MAC Address
682} SXG_CONFIG_MAC, *PSXG_CONFIG_MAC;
683
684//
685typedef struct _ATK_FRU {
686 unsigned char PartNum[6];
687 unsigned char Revision[2];
688 unsigned char Serial[14];
689} ATK_FRU, *PATK_FRU;
690
691// OEM FRU Format types
692#define ATK_FRU_FORMAT 0x0000
693#define CPQ_FRU_FORMAT 0x0001
694#define DELL_FRU_FORMAT 0x0002
695#define HP_FRU_FORMAT 0x0003
696#define IBM_FRU_FORMAT 0x0004
697#define EMC_FRU_FORMAT 0x0005
698#define NO_FRU_FORMAT 0xFFFF
699
700// EEPROM/Flash Format
701typedef struct _SXG_CONFIG {
702 //
703 // Section 1 (128 bytes)
704 //
705 ushort MagicWord; // EEPROM/FLASH Magic code 'A5A5'
706 ushort SpiClks; // SPI bus clock dividers
707 HW_CFG_DATA HwCfg[NUM_HW_CFG_ENTRIES];
708 //
709 //
710 //
711 ushort Version; // EEPROM format version
712 SXG_CONFIG_MAC MacAddr[4]; // space for 4 MAC addresses
713 ATK_FRU AtkFru; // FRU information
714 ushort OemFruFormat; // OEM FRU format type
715 unsigned char OemFru[76]; // OEM FRU information (optional)
716 ushort Checksum; // Checksum of section 2
717 // CS info XXXTODO
718} SXG_CONFIG, *PSXG_CONFIG;
719#pragma pack(pop)
720
721/*****************************************************************************
722 * Miscellaneous Hardware definitions
723 *****************************************************************************/
724
725// Sahara (ASIC level) defines
726#define SAHARA_GRAM_SIZE 0x020000 // GRAM size - 128 KB
727#define SAHARA_DRAM_SIZE 0x200000 // DRAM size - 2 MB
728#define SAHARA_QRAM_SIZE 0x004000 // QRAM size - 16K entries (64 KB)
729#define SAHARA_WCS_SIZE 0x002000 // WCS - 8K instructions (x 108 bits)
730
731// Arabia (board level) defines
732#define FLASH_SIZE 0x080000 // 512 KB (4 Mb)
733#define EEPROM_SIZE_XFMR 512 // true EEPROM size (bytes), including xfmr area
734#define EEPROM_SIZE_NO_XFMR 256 // EEPROM size excluding xfmr area
diff --git a/drivers/staging/sxg/sxgphycode.h b/drivers/staging/sxg/sxgphycode.h
new file mode 100644
index 000000000000..26b36c81eb1a
--- /dev/null
+++ b/drivers/staging/sxg/sxgphycode.h
@@ -0,0 +1,349 @@
1/*
2 * Copyright (C) 1997-2008 Alacritech, Inc. All rights reserved
3 *
4 * sxgphycode.h:
5 *
6 * This file PHY microcode and register initialization data.
7 */
8
9/**********************************************************************
10 * PHY Microcode
11 *
12 * The following contains both PHY microcode and PHY register
13 * initialization data. It is specific to both the PHY and the
14 * type of transceiver.
15 *
16 **********************************************************************/
17
18/*
19 * Download for AEL2005C PHY with SR/LR transceiver (10GBASE-SR or 10GBASE-LR)
20 */
21static PHY_UCODE PhyUcode[] = {
22 /*
23 * NOTE: An address of 0 is a special case. When the download routine
24 * sees an address of 0, it does not write to the PHY. Instead, it
25 * delays the download. The length of the delay (in ms) is given in
26 * the data field.
27 *
28 * Delays are required at certain points.
29 */
30
31 /*
32 * Platform-specific MDIO Patches:
33 * (include patches for 10G RX polarity flip, 50Mhz Synth, etc)
34 */
35 /* Addr, Data */
36 {0xc017, 0xfeb0}, /* flip RX_LOS polarity (mandatory */
37 /* patch for SFP+ applications) */
38 {0xC001, 0x0428}, /* flip RX serial polarity */
39
40 {0xc013, 0xf341}, /* invert lxmit clock (mandatory patch) */
41 {0xc210, 0x8000}, /* reset datapath (mandatory patch) */
42 {0xc210, 0x8100}, /* reset datapath (mandatory patch) */
43 {0xc210, 0x8000}, /* reset datapath (mandatory patch) */
44 {0xc210, 0x0000}, /* reset datapath (mandatory patch) */
45 {0x0000, 0x0032}, /* wait for 50ms for datapath reset to */
46 /* complete. (mandatory patch) */
47
48 /* Configure the LED's */
49 {0xc214, 0x0099}, /* configure the LED drivers */
50 {0xc216, 0x5f5f}, /* configure the Activity LED */
51 {0xc217, 0x33ff}, /* configure the Link LED */
52
53 /* Transceiver-specific MDIO Patches: */
54 {0xc010, 0x448a}, /* (bit 14) mask out high BER input from the */
55 /* LOS signal in 1.000A */
56 /* (mandatory patch for SR code)*/
57 {0xc003, 0x0181}, /* (bit 7) enable the CDR inc setting in */
58 /* 1.C005 (mandatory patch for SR code) */
59
60 /* Transceiver-specific Microcontroller Initialization: */
61 {0xc04a, 0x5200}, /* activate microcontroller and pause */
62 {0x0000, 0x0032}, /* wait 50ms for microcontroller before */
63 /* writing in code. */
64
65 /* code block starts here: */
66 {0xcc00, 0x2009},
67 {0xcc01, 0x3009},
68 {0xcc02, 0x27ff},
69 {0xcc03, 0x300f},
70 {0xcc04, 0x200c},
71 {0xcc05, 0x300c},
72 {0xcc06, 0x20c4},
73 {0xcc07, 0x3c04},
74 {0xcc08, 0x6437},
75 {0xcc09, 0x20c4},
76 {0xcc0a, 0x3c04},
77 {0xcc0b, 0x6437},
78 {0xcc0c, 0x25c4},
79 {0xcc0d, 0x3c54},
80 {0xcc0e, 0x6724},
81 {0xcc0f, 0x25c4},
82 {0xcc10, 0x3c54},
83 {0xcc11, 0x6724},
84 {0xcc12, 0x2042},
85 {0xcc13, 0x3012},
86 {0xcc14, 0x1002},
87 {0xcc15, 0x2482},
88 {0xcc16, 0x3012},
89 {0xcc17, 0x1002},
90 {0xcc18, 0x2a32},
91 {0xcc19, 0x3002},
92 {0xcc1a, 0x1002},
93 {0xcc1b, 0x200d},
94 {0xcc1c, 0x304d},
95 {0xcc1d, 0x2862},
96 {0xcc1e, 0x3012},
97 {0xcc1f, 0x1002},
98 {0xcc20, 0x2982},
99 {0xcc21, 0x3002},
100 {0xcc22, 0x1002},
101 {0xcc23, 0x628f},
102 {0xcc24, 0x20a4},
103 {0xcc25, 0x3004},
104 {0xcc26, 0x6438},
105 {0xcc27, 0x20a4},
106 {0xcc28, 0x3004},
107 {0xcc29, 0x6438},
108 {0xcc2a, 0x2015},
109 {0xcc2b, 0x3005},
110 {0xcc2c, 0x5853},
111 {0xcc2d, 0x2bd2},
112 {0xcc2e, 0x3002},
113 {0xcc2f, 0x1342},
114 {0xcc30, 0x200c},
115 {0xcc31, 0x300c},
116 {0xcc32, 0x2ff7},
117 {0xcc33, 0x30f7},
118 {0xcc34, 0x20c4},
119 {0xcc35, 0x3c04},
120 {0xcc36, 0x6724},
121 {0xcc37, 0x20c4},
122 {0xcc38, 0x3c04},
123 {0xcc39, 0x6724},
124 {0xcc3a, 0x2d32},
125 {0xcc3b, 0x3002},
126 {0xcc3c, 0x1002},
127 {0xcc3d, 0x2008},
128 {0xcc3e, 0x3008},
129 {0xcc3f, 0x5c83},
130 {0xcc40, 0x2d52},
131 {0xcc41, 0x3002},
132 {0xcc42, 0x1352},
133 {0xcc43, 0x2008},
134 {0xcc44, 0x3008},
135 {0xcc45, 0x5c83},
136 {0xcc46, 0x2d32},
137 {0xcc47, 0x3002},
138 {0xcc48, 0x1352},
139 {0xcc49, 0x201c},
140 {0xcc4a, 0x300c},
141 {0xcc4b, 0x200d},
142 {0xcc4c, 0x310d},
143 {0xcc4d, 0x2862},
144 {0xcc4e, 0x3012},
145 {0xcc4f, 0x1002},
146 {0xcc50, 0x2ed2},
147 {0xcc51, 0x3002},
148 {0xcc52, 0x1342},
149 {0xcc53, 0x6f72},
150 {0xcc54, 0x1002},
151 {0xcc55, 0x628f},
152 {0xcc56, 0x2514},
153 {0xcc57, 0x3c64},
154 {0xcc58, 0x6436},
155 {0xcc59, 0x2514},
156 {0xcc5a, 0x3c64},
157 {0xcc5b, 0x6436},
158 {0xcc5c, 0x2fa4},
159 {0xcc5d, 0x3cd4},
160 {0xcc5e, 0x6624},
161 {0xcc5f, 0x2fa4},
162 {0xcc60, 0x3cd4},
163 {0xcc61, 0x6624},
164 {0xcc62, 0x2f45},
165 {0xcc63, 0x3015},
166 {0xcc64, 0x5653},
167 {0xcc65, 0x2eb2},
168 {0xcc66, 0x3002},
169 {0xcc67, 0x13d2},
170 {0xcc68, 0x2ed2},
171 {0xcc69, 0x3002},
172 {0xcc6a, 0x1002},
173 {0xcc6b, 0x6f72},
174 {0xcc6c, 0x1002},
175 {0xcc6d, 0x628f},
176 {0xcc6e, 0x2602},
177 {0xcc6f, 0x3012},
178 {0xcc70, 0x1002},
179 {0xcc71, 0x200d},
180 {0xcc72, 0x320d},
181 {0xcc73, 0x2862},
182 {0xcc74, 0x3012},
183 {0xcc75, 0x1002},
184 {0xcc76, 0x25c4},
185 {0xcc77, 0x3c54},
186 {0xcc78, 0x6437},
187 {0xcc79, 0x25c4},
188 {0xcc7a, 0x3c54},
189 {0xcc7b, 0x6437},
190 {0xcc7c, 0x20c4},
191 {0xcc7d, 0x3c04},
192 {0xcc7e, 0x6724},
193 {0xcc7f, 0x20c4},
194 {0xcc80, 0x3c04},
195 {0xcc81, 0x6724},
196 {0xcc82, 0x6f72},
197 {0xcc83, 0x1002},
198 {0xcc84, 0x628f},
199 {0xcc85, 0x26f2},
200 {0xcc86, 0x3012},
201 {0xcc87, 0x1002},
202 {0xcc88, 0xc503},
203 {0xcc89, 0xd5d5},
204 {0xcc8a, 0xc600},
205 {0xcc8b, 0x2a6d},
206 {0xcc8c, 0xc601},
207 {0xcc8d, 0x2a4c},
208 {0xcc8e, 0xc602},
209 {0xcc8f, 0x0111},
210 {0xcc90, 0xc60c},
211 {0xcc91, 0x5900},
212 {0xcc92, 0xc710},
213 {0xcc93, 0x0700},
214 {0xcc94, 0xc718},
215 {0xcc95, 0x0700},
216 {0xcc96, 0xc720},
217 {0xcc97, 0x4700},
218 {0xcc98, 0xc801},
219 {0xcc99, 0x7f50},
220 {0xcc9a, 0xc802},
221 {0xcc9b, 0x7760},
222 {0xcc9c, 0xc803},
223 {0xcc9d, 0x7fce},
224 {0xcc9e, 0xc804},
225 {0xcc9f, 0x5700},
226 {0xcca0, 0xc805},
227 {0xcca1, 0x5f11},
228 {0xcca2, 0xc806},
229 {0xcca3, 0x4751},
230 {0xcca4, 0xc807},
231 {0xcca5, 0x57e1},
232 {0xcca6, 0xc808},
233 {0xcca7, 0x2700},
234 {0xcca8, 0xc809},
235 {0xcca9, 0x0000},
236 {0xccaa, 0xc821},
237 {0xccab, 0x0002},
238 {0xccac, 0xc822},
239 {0xccad, 0x0014},
240 {0xccae, 0xc832},
241 {0xccaf, 0x1186},
242 {0xccb0, 0xc847},
243 {0xccb1, 0x1e02},
244 {0xccb2, 0xc013},
245 {0xccb3, 0xf341},
246 {0xccb4, 0xc01a},
247 {0xccb5, 0x0446},
248 {0xccb6, 0xc024},
249 {0xccb7, 0x1000},
250 {0xccb8, 0xc025},
251 {0xccb9, 0x0a00},
252 {0xccba, 0xc026},
253 {0xccbb, 0x0c0c},
254 {0xccbc, 0xc027},
255 {0xccbd, 0x0c0c},
256 {0xccbe, 0xc029},
257 {0xccbf, 0x00a0},
258 {0xccc0, 0xc030},
259 {0xccc1, 0x0a00},
260 {0xccc2, 0xc03c},
261 {0xccc3, 0x001c},
262 {0xccc4, 0xc005},
263 {0xccc5, 0x7a06},
264 {0xccc6, 0x0000},
265 {0xccc7, 0x0000},
266 {0xccc8, 0x628f},
267 {0xccc9, 0x26f2},
268 {0xccca, 0x3012},
269 {0xcccb, 0x1002},
270 {0xcccc, 0xc620},
271 {0xcccd, 0x0000},
272 {0xccce, 0xc621},
273 {0xcccf, 0x003f},
274 {0xccd0, 0xc622},
275 {0xccd1, 0x0000},
276 {0xccd2, 0xc623},
277 {0xccd3, 0x0000},
278 {0xccd4, 0xc624},
279 {0xccd5, 0x0000},
280 {0xccd6, 0xc625},
281 {0xccd7, 0x0000},
282 {0xccd8, 0xc627},
283 {0xccd9, 0x0000},
284 {0xccda, 0xc628},
285 {0xccdb, 0x0000},
286 {0xccdc, 0xc62c},
287 {0xccdd, 0x0000},
288 {0xccde, 0x0000},
289 {0xccdf, 0x0000},
290 {0xcce0, 0x628f},
291 {0xcce1, 0xd019},
292 {0xcce2, 0x26f2},
293 {0xcce3, 0x3012},
294 {0xcce4, 0x1002},
295 {0xcce5, 0xc210},
296 {0xcce6, 0x8000},
297 {0xcce7, 0xc210},
298 {0xcce8, 0x8010},
299 {0xcce9, 0xc210},
300 {0xccea, 0x8000},
301 {0xcceb, 0xc210},
302 {0xccec, 0x0000},
303 {0xcced, 0x0000},
304 {0xccee, 0x0000},
305 {0xccef, 0x8221},
306 {0xccf0, 0x2752},
307 {0xccf1, 0x3012},
308 {0xccf2, 0x1002},
309 {0xccf3, 0x6f72},
310 {0xccf4, 0x1002},
311 {0xccf5, 0x2806},
312 {0xccf6, 0x3006},
313 {0xccf7, 0x2007},
314 {0xccf8, 0x3cc7},
315 {0xccf9, 0xe161},
316 {0xccfa, 0xc171},
317 {0xccfb, 0x6134},
318 {0xccfc, 0x6135},
319 {0xccfd, 0x5453},
320 {0xccfe, 0x2858},
321 {0xccff, 0x3018},
322 {0xcd00, 0x1348},
323 {0xcd01, 0x6524},
324 {0xcd02, 0x27b8},
325 {0xcd03, 0x3018},
326 {0xcd04, 0x1008},
327 {0xcd05, 0x1002},
328 {0xcd06, 0x628f},
329 {0xcd07, 0x5dd3},
330 {0xcd08, 0x2906},
331 {0xcd09, 0x3016},
332 {0xcd0a, 0x1306},
333 {0xcd0b, 0x2ff7},
334 {0xcd0c, 0x30f7},
335 {0xcd0d, 0x60b7},
336 {0xcd0e, 0xdffd},
337 {0xcd0f, 0x0008},
338 {0xcd10, 0x6f72},
339 {0xcd11, 0x1002},
340 {0xcd12, 0x0000},
341 {0xcdff, 0x0a01},
342 /* end of code block */
343
344 /* Unpause the microcontroller to start program */
345 {0xca00, 0x0080},
346 {0xca12, 0x0000},
347 {0x0000, 0x000A}, /* wait 10ms just to be safe */
348 {0xffff, 0xffff} /* table terminator */
349};
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 15:15:55 -0500