diff options
| -rw-r--r-- | arch/powerpc/boot/dts/glacier.dts | 76 |
1 files changed, 67 insertions, 9 deletions
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts index f6f618939293..d62a4fb6f93c 100644 --- a/arch/powerpc/boot/dts/glacier.dts +++ b/arch/powerpc/boot/dts/glacier.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Device Tree Source for AMCC Glacier (460GT) | 2 | * Device Tree Source for AMCC Glacier (460GT) |
| 3 | * | 3 | * |
| 4 | * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> | 4 | * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de> |
| 5 | * | 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public | 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without | 7 | * License version 2. This program is licensed "as is" without |
| @@ -42,6 +42,7 @@ | |||
| 42 | d-cache-size = <32768>; | 42 | d-cache-size = <32768>; |
| 43 | dcr-controller; | 43 | dcr-controller; |
| 44 | dcr-access-method = "native"; | 44 | dcr-access-method = "native"; |
| 45 | next-level-cache = <&L2C0>; | ||
| 45 | }; | 46 | }; |
| 46 | }; | 47 | }; |
| 47 | 48 | ||
| @@ -106,6 +107,16 @@ | |||
| 106 | dcr-reg = <0x00c 0x002>; | 107 | dcr-reg = <0x00c 0x002>; |
| 107 | }; | 108 | }; |
| 108 | 109 | ||
| 110 | L2C0: l2c { | ||
| 111 | compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; | ||
| 112 | dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ | ||
| 113 | 0x030 0x008>; /* L2 cache DCR's */ | ||
| 114 | cache-line-size = <32>; /* 32 bytes */ | ||
| 115 | cache-size = <262144>; /* L2, 256K */ | ||
| 116 | interrupt-parent = <&UIC1>; | ||
| 117 | interrupts = <11 1>; | ||
| 118 | }; | ||
| 119 | |||
| 109 | plb { | 120 | plb { |
| 110 | compatible = "ibm,plb-460gt", "ibm,plb4"; | 121 | compatible = "ibm,plb-460gt", "ibm,plb4"; |
| 111 | #address-cells = <2>; | 122 | #address-cells = <2>; |
| @@ -118,6 +129,13 @@ | |||
| 118 | dcr-reg = <0x010 0x002>; | 129 | dcr-reg = <0x010 0x002>; |
| 119 | }; | 130 | }; |
| 120 | 131 | ||
| 132 | CRYPTO: crypto@180000 { | ||
| 133 | compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto"; | ||
| 134 | reg = <4 0x00180000 0x80400>; | ||
| 135 | interrupt-parent = <&UIC0>; | ||
| 136 | interrupts = <0x1d 0x4>; | ||
| 137 | }; | ||
| 138 | |||
| 121 | MAL0: mcmal { | 139 | MAL0: mcmal { |
| 122 | compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; | 140 | compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; |
| 123 | dcr-reg = <0x180 0x062>; | 141 | dcr-reg = <0x180 0x062>; |
| @@ -186,6 +204,29 @@ | |||
| 186 | reg = <0x03fa0000 0x00060000>; | 204 | reg = <0x03fa0000 0x00060000>; |
| 187 | }; | 205 | }; |
| 188 | }; | 206 | }; |
| 207 | |||
| 208 | ndfc@3,0 { | ||
| 209 | compatible = "ibm,ndfc"; | ||
| 210 | reg = <0x00000003 0x00000000 0x00002000>; | ||
| 211 | ccr = <0x00001000>; | ||
| 212 | bank-settings = <0x80002222>; | ||
| 213 | #address-cells = <1>; | ||
| 214 | #size-cells = <1>; | ||
| 215 | |||
| 216 | nand { | ||
| 217 | #address-cells = <1>; | ||
| 218 | #size-cells = <1>; | ||
| 219 | |||
| 220 | partition@0 { | ||
| 221 | label = "u-boot"; | ||
| 222 | reg = <0x00000000 0x00100000>; | ||
| 223 | }; | ||
| 224 | partition@100000 { | ||
| 225 | label = "user"; | ||
| 226 | reg = <0x00000000 0x03f00000>; | ||
| 227 | }; | ||
| 228 | }; | ||
| 229 | }; | ||
| 189 | }; | 230 | }; |
| 190 | 231 | ||
| 191 | UART0: serial@ef600300 { | 232 | UART0: serial@ef600300 { |
| @@ -237,6 +278,20 @@ | |||
| 237 | reg = <0xef600700 0x00000014>; | 278 | reg = <0xef600700 0x00000014>; |
| 238 | interrupt-parent = <&UIC0>; | 279 | interrupt-parent = <&UIC0>; |
| 239 | interrupts = <0x2 0x4>; | 280 | interrupts = <0x2 0x4>; |
| 281 | #address-cells = <1>; | ||
| 282 | #size-cells = <0>; | ||
| 283 | rtc@68 { | ||
| 284 | compatible = "stm,m41t80"; | ||
| 285 | reg = <0x68>; | ||
| 286 | interrupt-parent = <&UIC2>; | ||
| 287 | interrupts = <0x19 0x8>; | ||
| 288 | }; | ||
| 289 | sttm@48 { | ||
| 290 | compatible = "ad,ad7414"; | ||
| 291 | reg = <0x48>; | ||
| 292 | interrupt-parent = <&UIC1>; | ||
| 293 | interrupts = <0x14 0x8>; | ||
| 294 | }; | ||
| 240 | }; | 295 | }; |
| 241 | 296 | ||
| 242 | IIC1: i2c@ef600800 { | 297 | IIC1: i2c@ef600800 { |
| @@ -275,7 +330,7 @@ | |||
| 275 | 330 | ||
| 276 | EMAC0: ethernet@ef600e00 { | 331 | EMAC0: ethernet@ef600e00 { |
| 277 | device_type = "network"; | 332 | device_type = "network"; |
| 278 | compatible = "ibm,emac-460gt", "ibm,emac4"; | 333 | compatible = "ibm,emac-460gt", "ibm,emac4sync"; |
| 279 | interrupt-parent = <&EMAC0>; | 334 | interrupt-parent = <&EMAC0>; |
| 280 | interrupts = <0x0 0x1>; | 335 | interrupts = <0x0 0x1>; |
| 281 | #interrupt-cells = <1>; | 336 | #interrupt-cells = <1>; |
| @@ -283,7 +338,7 @@ | |||
| 283 | #size-cells = <0>; | 338 | #size-cells = <0>; |
| 284 | interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 | 339 | interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 |
| 285 | /*Wake*/ 0x1 &UIC2 0x14 0x4>; | 340 | /*Wake*/ 0x1 &UIC2 0x14 0x4>; |
| 286 | reg = <0xef600e00 0x00000074>; | 341 | reg = <0xef600e00 0x000000c4>; |
| 287 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ | 342 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
| 288 | mal-device = <&MAL0>; | 343 | mal-device = <&MAL0>; |
| 289 | mal-tx-channel = <0>; | 344 | mal-tx-channel = <0>; |
| @@ -305,7 +360,7 @@ | |||
| 305 | 360 | ||
| 306 | EMAC1: ethernet@ef600f00 { | 361 | EMAC1: ethernet@ef600f00 { |
| 307 | device_type = "network"; | 362 | device_type = "network"; |
| 308 | compatible = "ibm,emac-460gt", "ibm,emac4"; | 363 | compatible = "ibm,emac-460gt", "ibm,emac4sync"; |
| 309 | interrupt-parent = <&EMAC1>; | 364 | interrupt-parent = <&EMAC1>; |
| 310 | interrupts = <0x0 0x1>; | 365 | interrupts = <0x0 0x1>; |
| 311 | #interrupt-cells = <1>; | 366 | #interrupt-cells = <1>; |
| @@ -313,7 +368,7 @@ | |||
| 313 | #size-cells = <0>; | 368 | #size-cells = <0>; |
| 314 | interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 | 369 | interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 |
| 315 | /*Wake*/ 0x1 &UIC2 0x15 0x4>; | 370 | /*Wake*/ 0x1 &UIC2 0x15 0x4>; |
| 316 | reg = <0xef600f00 0x00000074>; | 371 | reg = <0xef600f00 0x000000c4>; |
| 317 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ | 372 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
| 318 | mal-device = <&MAL0>; | 373 | mal-device = <&MAL0>; |
| 319 | mal-tx-channel = <1>; | 374 | mal-tx-channel = <1>; |
| @@ -336,7 +391,7 @@ | |||
| 336 | 391 | ||
| 337 | EMAC2: ethernet@ef601100 { | 392 | EMAC2: ethernet@ef601100 { |
| 338 | device_type = "network"; | 393 | device_type = "network"; |
| 339 | compatible = "ibm,emac-460gt", "ibm,emac4"; | 394 | compatible = "ibm,emac-460gt", "ibm,emac4sync"; |
| 340 | interrupt-parent = <&EMAC2>; | 395 | interrupt-parent = <&EMAC2>; |
| 341 | interrupts = <0x0 0x1>; | 396 | interrupts = <0x0 0x1>; |
| 342 | #interrupt-cells = <1>; | 397 | #interrupt-cells = <1>; |
| @@ -344,7 +399,7 @@ | |||
| 344 | #size-cells = <0>; | 399 | #size-cells = <0>; |
| 345 | interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 | 400 | interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 |
| 346 | /*Wake*/ 0x1 &UIC2 0x16 0x4>; | 401 | /*Wake*/ 0x1 &UIC2 0x16 0x4>; |
| 347 | reg = <0xef601100 0x00000074>; | 402 | reg = <0xef601100 0x000000c4>; |
| 348 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ | 403 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
| 349 | mal-device = <&MAL0>; | 404 | mal-device = <&MAL0>; |
| 350 | mal-tx-channel = <2>; | 405 | mal-tx-channel = <2>; |
| @@ -366,7 +421,7 @@ | |||
| 366 | 421 | ||
| 367 | EMAC3: ethernet@ef601200 { | 422 | EMAC3: ethernet@ef601200 { |
| 368 | device_type = "network"; | 423 | device_type = "network"; |
| 369 | compatible = "ibm,emac-460gt", "ibm,emac4"; | 424 | compatible = "ibm,emac-460gt", "ibm,emac4sync"; |
| 370 | interrupt-parent = <&EMAC3>; | 425 | interrupt-parent = <&EMAC3>; |
| 371 | interrupts = <0x0 0x1>; | 426 | interrupts = <0x0 0x1>; |
| 372 | #interrupt-cells = <1>; | 427 | #interrupt-cells = <1>; |
| @@ -374,7 +429,7 @@ | |||
| 374 | #size-cells = <0>; | 429 | #size-cells = <0>; |
| 375 | interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4 | 430 | interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4 |
| 376 | /*Wake*/ 0x1 &UIC2 0x17 0x4>; | 431 | /*Wake*/ 0x1 &UIC2 0x17 0x4>; |
| 377 | reg = <0xef601200 0x00000074>; | 432 | reg = <0xef601200 0x000000c4>; |
| 378 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ | 433 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
| 379 | mal-device = <&MAL0>; | 434 | mal-device = <&MAL0>; |
| 380 | mal-tx-channel = <3>; | 435 | mal-tx-channel = <3>; |
| @@ -414,6 +469,7 @@ | |||
| 414 | * later cannot be changed | 469 | * later cannot be changed |
| 415 | */ | 470 | */ |
| 416 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 | 471 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 |
| 472 | 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 | ||
| 417 | 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; | 473 | 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; |
| 418 | 474 | ||
| 419 | /* Inbound 2GB range starting at 0 */ | 475 | /* Inbound 2GB range starting at 0 */ |
| @@ -444,6 +500,7 @@ | |||
| 444 | * later cannot be changed | 500 | * later cannot be changed |
| 445 | */ | 501 | */ |
| 446 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 | 502 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 |
| 503 | 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 | ||
| 447 | 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; | 504 | 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; |
| 448 | 505 | ||
| 449 | /* Inbound 2GB range starting at 0 */ | 506 | /* Inbound 2GB range starting at 0 */ |
| @@ -485,6 +542,7 @@ | |||
| 485 | * later cannot be changed | 542 | * later cannot be changed |
| 486 | */ | 543 | */ |
| 487 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 | 544 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 |
| 545 | 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 | ||
| 488 | 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; | 546 | 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; |
| 489 | 547 | ||
| 490 | /* Inbound 2GB range starting at 0 */ | 548 | /* Inbound 2GB range starting at 0 */ |
