diff options
| -rw-r--r-- | arch/arm/mach-mx5/cpu.c | 53 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx51.h | 13 |
2 files changed, 60 insertions, 6 deletions
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 41c769f08c4d..2d37785e3857 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c | |||
| @@ -14,9 +14,62 @@ | |||
| 14 | #include <linux/types.h> | 14 | #include <linux/types.h> |
| 15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
| 16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 17 | #include <linux/module.h> | ||
| 17 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
| 18 | #include <asm/io.h> | 19 | #include <asm/io.h> |
| 19 | 20 | ||
| 21 | static int cpu_silicon_rev = -1; | ||
| 22 | |||
| 23 | #define SI_REV 0x48 | ||
| 24 | |||
| 25 | static void query_silicon_parameter(void) | ||
| 26 | { | ||
| 27 | void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE); | ||
| 28 | u32 rev; | ||
| 29 | |||
| 30 | if (!rom) { | ||
| 31 | cpu_silicon_rev = -EINVAL; | ||
| 32 | return; | ||
| 33 | } | ||
| 34 | |||
| 35 | rev = readl(rom + SI_REV); | ||
| 36 | switch (rev) { | ||
| 37 | case 0x1: | ||
| 38 | cpu_silicon_rev = MX51_CHIP_REV_1_0; | ||
| 39 | break; | ||
| 40 | case 0x2: | ||
| 41 | cpu_silicon_rev = MX51_CHIP_REV_1_1; | ||
| 42 | break; | ||
| 43 | case 0x10: | ||
| 44 | cpu_silicon_rev = MX51_CHIP_REV_2_0; | ||
| 45 | break; | ||
| 46 | case 0x20: | ||
| 47 | cpu_silicon_rev = MX51_CHIP_REV_3_0; | ||
| 48 | break; | ||
| 49 | default: | ||
| 50 | cpu_silicon_rev = 0; | ||
| 51 | } | ||
| 52 | |||
| 53 | iounmap(rom); | ||
| 54 | } | ||
| 55 | |||
| 56 | /* | ||
| 57 | * Returns: | ||
| 58 | * the silicon revision of the cpu | ||
| 59 | * -EINVAL - not a mx51 | ||
| 60 | */ | ||
| 61 | int mx51_revision(void) | ||
| 62 | { | ||
| 63 | if (!cpu_is_mx51()) | ||
| 64 | return -EINVAL; | ||
| 65 | |||
| 66 | if (cpu_silicon_rev == -1) | ||
| 67 | query_silicon_parameter(); | ||
| 68 | |||
| 69 | return cpu_silicon_rev; | ||
| 70 | } | ||
| 71 | EXPORT_SYMBOL(mx51_revision); | ||
| 72 | |||
| 20 | static int __init post_cpu_init(void) | 73 | static int __init post_cpu_init(void) |
| 21 | { | 74 | { |
| 22 | unsigned int reg; | 75 | unsigned int reg; |
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index f1396bd5621f..fd255a9dbcdc 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h | |||
| @@ -28,6 +28,12 @@ | |||
| 28 | */ | 28 | */ |
| 29 | 29 | ||
| 30 | /* | 30 | /* |
| 31 | * IROM | ||
| 32 | */ | ||
| 33 | #define MX51_IROM_BASE_ADDR 0x0 | ||
| 34 | #define MX51_IROM_SIZE SZ_64K | ||
| 35 | |||
| 36 | /* | ||
| 31 | * IRAM | 37 | * IRAM |
| 32 | */ | 38 | */ |
| 33 | #define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ | 39 | #define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ |
| @@ -438,12 +444,7 @@ | |||
| 438 | 444 | ||
| 439 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | 445 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) |
| 440 | 446 | ||
| 441 | extern unsigned int system_rev; | 447 | extern int mx51_revision(void); |
| 442 | |||
| 443 | static inline unsigned int mx51_revision(void) | ||
| 444 | { | ||
| 445 | return system_rev; | ||
| 446 | } | ||
| 447 | #endif | 448 | #endif |
| 448 | 449 | ||
| 449 | #endif /* __ASM_ARCH_MXC_MX51_H__ */ | 450 | #endif /* __ASM_ARCH_MXC_MX51_H__ */ |
