diff options
| -rw-r--r-- | arch/arm/mach-omap2/clock44xx_data.c | 11 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/clock.h | 1 |
2 files changed, 0 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 022f1a75286a..6deca1e01608 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c | |||
| @@ -39,42 +39,36 @@ static struct clk extalt_clkin_ck = { | |||
| 39 | .name = "extalt_clkin_ck", | 39 | .name = "extalt_clkin_ck", |
| 40 | .rate = 59000000, | 40 | .rate = 59000000, |
| 41 | .ops = &clkops_null, | 41 | .ops = &clkops_null, |
| 42 | .flags = ALWAYS_ENABLED, | ||
| 43 | }; | 42 | }; |
| 44 | 43 | ||
| 45 | static struct clk pad_clks_ck = { | 44 | static struct clk pad_clks_ck = { |
| 46 | .name = "pad_clks_ck", | 45 | .name = "pad_clks_ck", |
| 47 | .rate = 12000000, | 46 | .rate = 12000000, |
| 48 | .ops = &clkops_null, | 47 | .ops = &clkops_null, |
| 49 | .flags = ALWAYS_ENABLED, | ||
| 50 | }; | 48 | }; |
| 51 | 49 | ||
| 52 | static struct clk pad_slimbus_core_clks_ck = { | 50 | static struct clk pad_slimbus_core_clks_ck = { |
| 53 | .name = "pad_slimbus_core_clks_ck", | 51 | .name = "pad_slimbus_core_clks_ck", |
| 54 | .rate = 12000000, | 52 | .rate = 12000000, |
| 55 | .ops = &clkops_null, | 53 | .ops = &clkops_null, |
| 56 | .flags = ALWAYS_ENABLED, | ||
| 57 | }; | 54 | }; |
| 58 | 55 | ||
| 59 | static struct clk secure_32k_clk_src_ck = { | 56 | static struct clk secure_32k_clk_src_ck = { |
| 60 | .name = "secure_32k_clk_src_ck", | 57 | .name = "secure_32k_clk_src_ck", |
| 61 | .rate = 32768, | 58 | .rate = 32768, |
| 62 | .ops = &clkops_null, | 59 | .ops = &clkops_null, |
| 63 | .flags = ALWAYS_ENABLED, | ||
| 64 | }; | 60 | }; |
| 65 | 61 | ||
| 66 | static struct clk slimbus_clk = { | 62 | static struct clk slimbus_clk = { |
| 67 | .name = "slimbus_clk", | 63 | .name = "slimbus_clk", |
| 68 | .rate = 12000000, | 64 | .rate = 12000000, |
| 69 | .ops = &clkops_null, | 65 | .ops = &clkops_null, |
| 70 | .flags = ALWAYS_ENABLED, | ||
| 71 | }; | 66 | }; |
| 72 | 67 | ||
| 73 | static struct clk sys_32k_ck = { | 68 | static struct clk sys_32k_ck = { |
| 74 | .name = "sys_32k_ck", | 69 | .name = "sys_32k_ck", |
| 75 | .rate = 32768, | 70 | .rate = 32768, |
| 76 | .ops = &clkops_null, | 71 | .ops = &clkops_null, |
| 77 | .flags = ALWAYS_ENABLED, | ||
| 78 | }; | 72 | }; |
| 79 | 73 | ||
| 80 | static struct clk virt_12000000_ck = { | 74 | static struct clk virt_12000000_ck = { |
| @@ -179,35 +173,30 @@ static struct clk sys_clkin_ck = { | |||
| 179 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, | 173 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, |
| 180 | .ops = &clkops_null, | 174 | .ops = &clkops_null, |
| 181 | .recalc = &omap2_clksel_recalc, | 175 | .recalc = &omap2_clksel_recalc, |
| 182 | .flags = ALWAYS_ENABLED, | ||
| 183 | }; | 176 | }; |
| 184 | 177 | ||
| 185 | static struct clk utmi_phy_clkout_ck = { | 178 | static struct clk utmi_phy_clkout_ck = { |
| 186 | .name = "utmi_phy_clkout_ck", | 179 | .name = "utmi_phy_clkout_ck", |
| 187 | .rate = 12000000, | 180 | .rate = 12000000, |
| 188 | .ops = &clkops_null, | 181 | .ops = &clkops_null, |
| 189 | .flags = ALWAYS_ENABLED, | ||
| 190 | }; | 182 | }; |
| 191 | 183 | ||
| 192 | static struct clk xclk60mhsp1_ck = { | 184 | static struct clk xclk60mhsp1_ck = { |
| 193 | .name = "xclk60mhsp1_ck", | 185 | .name = "xclk60mhsp1_ck", |
| 194 | .rate = 12000000, | 186 | .rate = 12000000, |
| 195 | .ops = &clkops_null, | 187 | .ops = &clkops_null, |
| 196 | .flags = ALWAYS_ENABLED, | ||
| 197 | }; | 188 | }; |
| 198 | 189 | ||
| 199 | static struct clk xclk60mhsp2_ck = { | 190 | static struct clk xclk60mhsp2_ck = { |
| 200 | .name = "xclk60mhsp2_ck", | 191 | .name = "xclk60mhsp2_ck", |
| 201 | .rate = 12000000, | 192 | .rate = 12000000, |
| 202 | .ops = &clkops_null, | 193 | .ops = &clkops_null, |
| 203 | .flags = ALWAYS_ENABLED, | ||
| 204 | }; | 194 | }; |
| 205 | 195 | ||
| 206 | static struct clk xclk60motg_ck = { | 196 | static struct clk xclk60motg_ck = { |
| 207 | .name = "xclk60motg_ck", | 197 | .name = "xclk60motg_ck", |
| 208 | .rate = 60000000, | 198 | .rate = 60000000, |
| 209 | .ops = &clkops_null, | 199 | .ops = &clkops_null, |
| 210 | .flags = ALWAYS_ENABLED, | ||
| 211 | }; | 200 | }; |
| 212 | 201 | ||
| 213 | /* Module clocks and DPLL outputs */ | 202 | /* Module clocks and DPLL outputs */ |
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 47de911b0a15..de078afc65df 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h | |||
| @@ -191,7 +191,6 @@ extern const struct clkops clkops_null; | |||
| 191 | #define CLOCK_NO_IDLE_PARENT (1 << 2) | 191 | #define CLOCK_NO_IDLE_PARENT (1 << 2) |
| 192 | #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ | 192 | #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ |
| 193 | #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ | 193 | #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ |
| 194 | #define ALWAYS_ENABLED (1 << 5) | ||
| 195 | 194 | ||
| 196 | /* Clksel_rate flags */ | 195 | /* Clksel_rate flags */ |
| 197 | #define DEFAULT_RATE (1 << 0) | 196 | #define DEFAULT_RATE (1 << 0) |
