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| -rw-r--r-- | Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt | 70 |
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diff --git a/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt b/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt new file mode 100644 index 000000000000..8832e8798912 --- /dev/null +++ b/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt | |||
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| 1 | MPC5121 PSC Device Tree Bindings | ||
| 2 | |||
| 3 | PSC in UART mode | ||
| 4 | ---------------- | ||
| 5 | |||
| 6 | For PSC in UART mode the needed PSC serial devices | ||
| 7 | are specified by fsl,mpc5121-psc-uart nodes in the | ||
| 8 | fsl,mpc5121-immr SoC node. Additionally the PSC FIFO | ||
| 9 | Controller node fsl,mpc5121-psc-fifo is requered there: | ||
| 10 | |||
| 11 | fsl,mpc5121-psc-uart nodes | ||
| 12 | -------------------------- | ||
| 13 | |||
| 14 | Required properties : | ||
| 15 | - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc" | ||
| 16 | - cell-index : Index of the PSC in hardware | ||
| 17 | - reg : Offset and length of the register set for the PSC device | ||
| 18 | - interrupts : <a b> where a is the interrupt number of the | ||
| 19 | PSC FIFO Controller and b is a field that represents an | ||
| 20 | encoding of the sense and level information for the interrupt. | ||
| 21 | - interrupt-parent : the phandle for the interrupt controller that | ||
| 22 | services interrupts for this device. | ||
| 23 | |||
| 24 | Recommended properties : | ||
| 25 | - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4) | ||
| 26 | - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4) | ||
| 27 | |||
| 28 | |||
| 29 | fsl,mpc5121-psc-fifo node | ||
| 30 | ------------------------- | ||
| 31 | |||
| 32 | Required properties : | ||
| 33 | - compatible : Should be "fsl,mpc5121-psc-fifo" | ||
| 34 | - reg : Offset and length of the register set for the PSC | ||
| 35 | FIFO Controller | ||
| 36 | - interrupts : <a b> where a is the interrupt number of the | ||
| 37 | PSC FIFO Controller and b is a field that represents an | ||
| 38 | encoding of the sense and level information for the interrupt. | ||
| 39 | - interrupt-parent : the phandle for the interrupt controller that | ||
| 40 | services interrupts for this device. | ||
| 41 | |||
| 42 | |||
| 43 | Example for a board using PSC0 and PSC1 devices in serial mode: | ||
| 44 | |||
| 45 | serial@11000 { | ||
| 46 | compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; | ||
| 47 | cell-index = <0>; | ||
| 48 | reg = <0x11000 0x100>; | ||
| 49 | interrupts = <40 0x8>; | ||
| 50 | interrupt-parent = < &ipic >; | ||
| 51 | fsl,rx-fifo-size = <16>; | ||
| 52 | fsl,tx-fifo-size = <16>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | serial@11100 { | ||
| 56 | compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; | ||
| 57 | cell-index = <1>; | ||
| 58 | reg = <0x11100 0x100>; | ||
| 59 | interrupts = <40 0x8>; | ||
| 60 | interrupt-parent = < &ipic >; | ||
| 61 | fsl,rx-fifo-size = <16>; | ||
| 62 | fsl,tx-fifo-size = <16>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | pscfifo@11f00 { | ||
| 66 | compatible = "fsl,mpc5121-psc-fifo"; | ||
| 67 | reg = <0x11f00 0x100>; | ||
| 68 | interrupts = <40 0x8>; | ||
| 69 | interrupt-parent = < &ipic >; | ||
| 70 | }; | ||
