aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--include/linux/pci.h488
-rw-r--r--include/linux/pci_regs.h447
2 files changed, 477 insertions, 458 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h
index e7a228f2fdde..830c1bae56cc 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -19,436 +19,10 @@
19 19
20#include <linux/mod_devicetable.h> 20#include <linux/mod_devicetable.h>
21 21
22/* 22/* Include the pci register defines */
23 * Under PCI, each device has 256 bytes of configuration address space, 23#include <linux/pci_regs.h>
24 * of which the first 64 bytes are standardized as follows:
25 */
26#define PCI_VENDOR_ID 0x00 /* 16 bits */
27#define PCI_DEVICE_ID 0x02 /* 16 bits */
28#define PCI_COMMAND 0x04 /* 16 bits */
29#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
30#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
31#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
32#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
33#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
34#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
35#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
36#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
37#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
38#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
39#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
40
41#define PCI_STATUS 0x06 /* 16 bits */
42#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
43#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
44#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
45#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
46#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
47#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
48#define PCI_STATUS_DEVSEL_FAST 0x000
49#define PCI_STATUS_DEVSEL_MEDIUM 0x200
50#define PCI_STATUS_DEVSEL_SLOW 0x400
51#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
52#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
53#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
54#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
55#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
56
57#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
58 revision */
59#define PCI_REVISION_ID 0x08 /* Revision ID */
60#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
61#define PCI_CLASS_DEVICE 0x0a /* Device class */
62
63#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
64#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
65#define PCI_HEADER_TYPE 0x0e /* 8 bits */
66#define PCI_HEADER_TYPE_NORMAL 0
67#define PCI_HEADER_TYPE_BRIDGE 1
68#define PCI_HEADER_TYPE_CARDBUS 2
69
70#define PCI_BIST 0x0f /* 8 bits */
71#define PCI_BIST_CODE_MASK 0x0f /* Return result */
72#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
73#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
74
75/*
76 * Base addresses specify locations in memory or I/O space.
77 * Decoded size can be determined by writing a value of
78 * 0xffffffff to the register, and reading it back. Only
79 * 1 bits are decoded.
80 */
81#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
82#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
83#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
84#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
85#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
86#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
87#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
88#define PCI_BASE_ADDRESS_SPACE_IO 0x01
89#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
90#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
91#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
92#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
93#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
94#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
95#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
96#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
97/* bit 1 is reserved if address_space = 1 */
98
99/* Header type 0 (normal devices) */
100#define PCI_CARDBUS_CIS 0x28
101#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
102#define PCI_SUBSYSTEM_ID 0x2e
103#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
104#define PCI_ROM_ADDRESS_ENABLE 0x01
105#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
106
107#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
108
109/* 0x35-0x3b are reserved */
110#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
111#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
112#define PCI_MIN_GNT 0x3e /* 8 bits */
113#define PCI_MAX_LAT 0x3f /* 8 bits */
114
115/* Header type 1 (PCI-to-PCI bridges) */
116#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
117#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
118#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
119#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
120#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
121#define PCI_IO_LIMIT 0x1d
122#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
123#define PCI_IO_RANGE_TYPE_16 0x00
124#define PCI_IO_RANGE_TYPE_32 0x01
125#define PCI_IO_RANGE_MASK (~0x0fUL)
126#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
127#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
128#define PCI_MEMORY_LIMIT 0x22
129#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
130#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
131#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
132#define PCI_PREF_MEMORY_LIMIT 0x26
133#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
134#define PCI_PREF_RANGE_TYPE_32 0x00
135#define PCI_PREF_RANGE_TYPE_64 0x01
136#define PCI_PREF_RANGE_MASK (~0x0fUL)
137#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
138#define PCI_PREF_LIMIT_UPPER32 0x2c
139#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
140#define PCI_IO_LIMIT_UPPER16 0x32
141/* 0x34 same as for htype 0 */
142/* 0x35-0x3b is reserved */
143#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
144/* 0x3c-0x3d are same as for htype 0 */
145#define PCI_BRIDGE_CONTROL 0x3e
146#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
147#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
148#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
149#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
150#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
151#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
152#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
153
154/* Header type 2 (CardBus bridges) */
155#define PCI_CB_CAPABILITY_LIST 0x14
156/* 0x15 reserved */
157#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
158#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
159#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
160#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
161#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
162#define PCI_CB_MEMORY_BASE_0 0x1c
163#define PCI_CB_MEMORY_LIMIT_0 0x20
164#define PCI_CB_MEMORY_BASE_1 0x24
165#define PCI_CB_MEMORY_LIMIT_1 0x28
166#define PCI_CB_IO_BASE_0 0x2c
167#define PCI_CB_IO_BASE_0_HI 0x2e
168#define PCI_CB_IO_LIMIT_0 0x30
169#define PCI_CB_IO_LIMIT_0_HI 0x32
170#define PCI_CB_IO_BASE_1 0x34
171#define PCI_CB_IO_BASE_1_HI 0x36
172#define PCI_CB_IO_LIMIT_1 0x38
173#define PCI_CB_IO_LIMIT_1_HI 0x3a
174#define PCI_CB_IO_RANGE_MASK (~0x03UL)
175/* 0x3c-0x3d are same as for htype 0 */
176#define PCI_CB_BRIDGE_CONTROL 0x3e
177#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
178#define PCI_CB_BRIDGE_CTL_SERR 0x02
179#define PCI_CB_BRIDGE_CTL_ISA 0x04
180#define PCI_CB_BRIDGE_CTL_VGA 0x08
181#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
182#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
183#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
184#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
185#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
186#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
187#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
188#define PCI_CB_SUBSYSTEM_ID 0x42
189#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
190/* 0x48-0x7f reserved */
191
192/* Capability lists */
193
194#define PCI_CAP_LIST_ID 0 /* Capability ID */
195#define PCI_CAP_ID_PM 0x01 /* Power Management */
196#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
197#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
198#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
199#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
200#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
201#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
202#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
203#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
204#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
205#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
206#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
207#define PCI_CAP_SIZEOF 4
208
209/* Power Management Registers */
210
211#define PCI_PM_PMC 2 /* PM Capabilities Register */
212#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
213#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
214#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
215#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
216#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
217#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
218#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
219#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
220#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
221#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
222#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
223#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
224#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
225#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
226#define PCI_PM_CTRL 4 /* PM control and status register */
227#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
228#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
229#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
230#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
231#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
232#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
233#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
234#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
235#define PCI_PM_DATA_REGISTER 7 /* (??) */
236#define PCI_PM_SIZEOF 8
237
238/* AGP registers */
239
240#define PCI_AGP_VERSION 2 /* BCD version number */
241#define PCI_AGP_RFU 3 /* Rest of capability flags */
242#define PCI_AGP_STATUS 4 /* Status register */
243#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
244#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
245#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
246#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
247#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
248#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
249#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
250#define PCI_AGP_COMMAND 8 /* Control register */
251#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
252#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
253#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
254#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
255#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
256#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
257#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
258#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
259#define PCI_AGP_SIZEOF 12
260
261/* Vital Product Data */
262
263#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
264#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
265#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
266#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
267
268/* Slot Identification */
269
270#define PCI_SID_ESR 2 /* Expansion Slot Register */
271#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
272#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
273#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
274
275/* Message Signalled Interrupts registers */
276
277#define PCI_MSI_FLAGS 2 /* Various flags */
278#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
279#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
280#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
281#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
282#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
283#define PCI_MSI_RFU 3 /* Rest of capability flags */
284#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
285#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
286#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
287#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
288#define PCI_MSI_MASK_BIT 16 /* Mask bits register */
289
290/* CompactPCI Hotswap Register */
291
292#define PCI_CHSWP_CSR 2 /* Control and Status Register */
293#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
294#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
295#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
296#define PCI_CHSWP_LOO 0x08 /* LED On / Off */
297#define PCI_CHSWP_PI 0x30 /* Programming Interface */
298#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
299#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
300
301/* PCI-X registers */
302
303#define PCI_X_CMD 2 /* Modes & Features */
304#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
305#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
306#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
307#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
308#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
309#define PCI_X_STATUS 4 /* PCI-X capabilities */
310#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
311#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
312#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
313#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
314#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
315#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
316#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
317#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
318#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
319#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
320#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
321#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
322#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
323
324/* PCI Express capability registers */
325
326#define PCI_EXP_FLAGS 2 /* Capabilities register */
327#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
328#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
329#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
330#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
331#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
332#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
333#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
334#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
335#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
336#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
337#define PCI_EXP_DEVCAP 4 /* Device capabilities */
338#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
339#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
340#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
341#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
342#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
343#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
344#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
345#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
346#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
347#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
348#define PCI_EXP_DEVCTL 8 /* Device Control */
349#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
350#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
351#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
352#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
353#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
354#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
355#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
356#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
357#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
358#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
359#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
360#define PCI_EXP_DEVSTA 10 /* Device Status */
361#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
362#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
363#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
364#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
365#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
366#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
367#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
368#define PCI_EXP_LNKCTL 16 /* Link Control */
369#define PCI_EXP_LNKSTA 18 /* Link Status */
370#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
371#define PCI_EXP_SLTCTL 24 /* Slot Control */
372#define PCI_EXP_SLTSTA 26 /* Slot Status */
373#define PCI_EXP_RTCTL 28 /* Root Control */
374#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
375#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
376#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
377#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
378#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
379#define PCI_EXP_RTCAP 30 /* Root Capabilities */
380#define PCI_EXP_RTSTA 32 /* Root Status */
381
382/* Extended Capabilities (PCI-X 2.0 and Express) */
383#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
384#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
385#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
386
387#define PCI_EXT_CAP_ID_ERR 1
388#define PCI_EXT_CAP_ID_VC 2
389#define PCI_EXT_CAP_ID_DSN 3
390#define PCI_EXT_CAP_ID_PWR 4
391
392/* Advanced Error Reporting */
393#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
394#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
395#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
396#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
397#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
398#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
399#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
400#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
401#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
402#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
403#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
404#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
405#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
406 /* Same bits as above */
407#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
408 /* Same bits as above */
409#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
410#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
411#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
412#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
413#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
414#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
415#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
416 /* Same bits as above */
417#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
418#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
419#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
420#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
421#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
422#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
423#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
424#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
425#define PCI_ERR_ROOT_STATUS 48
426#define PCI_ERR_ROOT_COR_SRC 52
427#define PCI_ERR_ROOT_SRC 54
428
429/* Virtual Channel */
430#define PCI_VC_PORT_REG1 4
431#define PCI_VC_PORT_REG2 8
432#define PCI_VC_PORT_CTRL 12
433#define PCI_VC_PORT_STATUS 14
434#define PCI_VC_RES_CAP 16
435#define PCI_VC_RES_CTRL 20
436#define PCI_VC_RES_STATUS 26
437
438/* Power Budgeting */
439#define PCI_PWR_DSR 4 /* Data Select Register */
440#define PCI_PWR_DATA 8 /* Data Register */
441#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
442#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
443#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
444#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
445#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
446#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
447#define PCI_PWR_CAP 12 /* Capability */
448#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
449 24
450/* Include the ID list */ 25/* Include the ID list */
451
452#include <linux/pci_ids.h> 26#include <linux/pci_ids.h>
453 27
454/* 28/*
@@ -496,9 +70,9 @@ enum pci_mmap_state {
496 70
497typedef int __bitwise pci_power_t; 71typedef int __bitwise pci_power_t;
498 72
499#define PCI_D0 ((pci_power_t __force) 0) 73#define PCI_D0 ((pci_power_t __force) 0)
500#define PCI_D1 ((pci_power_t __force) 1) 74#define PCI_D1 ((pci_power_t __force) 1)
501#define PCI_D2 ((pci_power_t __force) 2) 75#define PCI_D2 ((pci_power_t __force) 2)
502#define PCI_D3hot ((pci_power_t __force) 3) 76#define PCI_D3hot ((pci_power_t __force) 3)
503#define PCI_D3cold ((pci_power_t __force) 4) 77#define PCI_D3cold ((pci_power_t __force) 4)
504#define PCI_POWER_ERROR ((pci_power_t __force) -1) 78#define PCI_POWER_ERROR ((pci_power_t __force) -1)
@@ -577,15 +151,15 @@ struct pci_dev {
577 * 7-10 bridges: address space assigned to buses behind the bridge 151 * 7-10 bridges: address space assigned to buses behind the bridge
578 */ 152 */
579 153
580#define PCI_ROM_RESOURCE 6 154#define PCI_ROM_RESOURCE 6
581#define PCI_BRIDGE_RESOURCES 7 155#define PCI_BRIDGE_RESOURCES 7
582#define PCI_NUM_RESOURCES 11 156#define PCI_NUM_RESOURCES 11
583 157
584#ifndef PCI_BUS_NUM_RESOURCES 158#ifndef PCI_BUS_NUM_RESOURCES
585#define PCI_BUS_NUM_RESOURCES 8 159#define PCI_BUS_NUM_RESOURCES 8
586#endif 160#endif
587 161
588#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 162#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
589 163
590struct pci_bus { 164struct pci_bus {
591 struct list_head node; /* node in list of buses */ 165 struct list_head node; /* node in list of buses */
@@ -694,7 +268,7 @@ struct pci_driver {
694 * @dev_class_mask: the class mask for this device 268 * @dev_class_mask: the class mask for this device
695 * 269 *
696 * This macro is used to create a struct pci_device_id that matches a 270 * This macro is used to create a struct pci_device_id that matches a
697 * specific PCI class. The vendor, device, subvendor, and subdevice 271 * specific PCI class. The vendor, device, subvendor, and subdevice
698 * fields will be set to PCI_ANY_ID. 272 * fields will be set to PCI_ANY_ID.
699 */ 273 */
700#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 274#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
@@ -702,7 +276,7 @@ struct pci_driver {
702 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 276 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
703 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 277 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
704 278
705/* 279/*
706 * pci_module_init is obsolete, this stays here till we fix up all usages of it 280 * pci_module_init is obsolete, this stays here till we fix up all usages of it
707 * in the tree. 281 * in the tree.
708 */ 282 */
@@ -905,18 +479,26 @@ extern void pci_disable_msix(struct pci_dev *dev);
905extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); 479extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
906#endif 480#endif
907 481
908#endif /* CONFIG_PCI */ 482/*
909 483 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
910/* Include architecture-dependent settings and functions */ 484 * a PCI domain is defined to be a set of PCI busses which share
485 * configuration space.
486 */
487#ifndef CONFIG_PCI_DOMAINS
488static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
489static inline int pci_proc_domain(struct pci_bus *bus)
490{
491 return 0;
492}
493#endif
911 494
912#include <asm/pci.h> 495#else /* CONFIG_PCI is not enabled */
913 496
914/* 497/*
915 * If the system does not have PCI, clearly these return errors. Define 498 * If the system does not have PCI, clearly these return errors. Define
916 * these as simple inline functions to avoid hair in drivers. 499 * these as simple inline functions to avoid hair in drivers.
917 */ 500 */
918 501
919#ifndef CONFIG_PCI
920#define _PCI_NOP(o,s,t) \ 502#define _PCI_NOP(o,s,t) \
921 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \ 503 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
922 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 504 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
@@ -967,21 +549,11 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int en
967 549
968#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 550#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
969 551
970#else 552#endif /* CONFIG_PCI */
971 553
972/* 554/* Include architecture-dependent settings and functions */
973 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 555
974 * a PCI domain is defined to be a set of PCI busses which share 556#include <asm/pci.h>
975 * configuration space.
976 */
977#ifndef CONFIG_PCI_DOMAINS
978static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
979static inline int pci_proc_domain(struct pci_bus *bus)
980{
981 return 0;
982}
983#endif
984#endif /* !CONFIG_PCI */
985 557
986/* these helpers provide future and backwards compatibility 558/* these helpers provide future and backwards compatibility
987 * for accessing popular PCI BAR info */ 559 * for accessing popular PCI BAR info */
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
new file mode 100644
index 000000000000..7dc391cad10d
--- /dev/null
+++ b/include/linux/pci_regs.h
@@ -0,0 +1,447 @@
1/*
2 * pci_regs.h
3 *
4 * PCI standard defines
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_REGS_H
18#define LINUX_PCI_REGS_H
19
20/*
21 * Under PCI, each device has 256 bytes of configuration address space,
22 * of which the first 64 bytes are standardized as follows:
23 */
24#define PCI_VENDOR_ID 0x00 /* 16 bits */
25#define PCI_DEVICE_ID 0x02 /* 16 bits */
26#define PCI_COMMAND 0x04 /* 16 bits */
27#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
28#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
29#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
30#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
31#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
32#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
33#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
34#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
35#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
36#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
37#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
38
39#define PCI_STATUS 0x06 /* 16 bits */
40#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
41#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
42#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
43#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
44#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
45#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
46#define PCI_STATUS_DEVSEL_FAST 0x000
47#define PCI_STATUS_DEVSEL_MEDIUM 0x200
48#define PCI_STATUS_DEVSEL_SLOW 0x400
49#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
50#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
51#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
52#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
53#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
54
55#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
56#define PCI_REVISION_ID 0x08 /* Revision ID */
57#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
58#define PCI_CLASS_DEVICE 0x0a /* Device class */
59
60#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
61#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
62#define PCI_HEADER_TYPE 0x0e /* 8 bits */
63#define PCI_HEADER_TYPE_NORMAL 0
64#define PCI_HEADER_TYPE_BRIDGE 1
65#define PCI_HEADER_TYPE_CARDBUS 2
66
67#define PCI_BIST 0x0f /* 8 bits */
68#define PCI_BIST_CODE_MASK 0x0f /* Return result */
69#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
70#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
71
72/*
73 * Base addresses specify locations in memory or I/O space.
74 * Decoded size can be determined by writing a value of
75 * 0xffffffff to the register, and reading it back. Only
76 * 1 bits are decoded.
77 */
78#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
79#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
80#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
81#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
82#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
83#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
84#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
85#define PCI_BASE_ADDRESS_SPACE_IO 0x01
86#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
87#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
88#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
89#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
90#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
91#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
92#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
93#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
94/* bit 1 is reserved if address_space = 1 */
95
96/* Header type 0 (normal devices) */
97#define PCI_CARDBUS_CIS 0x28
98#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
99#define PCI_SUBSYSTEM_ID 0x2e
100#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
101#define PCI_ROM_ADDRESS_ENABLE 0x01
102#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
103
104#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
105
106/* 0x35-0x3b are reserved */
107#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
108#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
109#define PCI_MIN_GNT 0x3e /* 8 bits */
110#define PCI_MAX_LAT 0x3f /* 8 bits */
111
112/* Header type 1 (PCI-to-PCI bridges) */
113#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
114#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
115#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
116#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
117#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
118#define PCI_IO_LIMIT 0x1d
119#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
120#define PCI_IO_RANGE_TYPE_16 0x00
121#define PCI_IO_RANGE_TYPE_32 0x01
122#define PCI_IO_RANGE_MASK (~0x0fUL)
123#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
124#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
125#define PCI_MEMORY_LIMIT 0x22
126#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
127#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
128#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
129#define PCI_PREF_MEMORY_LIMIT 0x26
130#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
131#define PCI_PREF_RANGE_TYPE_32 0x00
132#define PCI_PREF_RANGE_TYPE_64 0x01
133#define PCI_PREF_RANGE_MASK (~0x0fUL)
134#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
135#define PCI_PREF_LIMIT_UPPER32 0x2c
136#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
137#define PCI_IO_LIMIT_UPPER16 0x32
138/* 0x34 same as for htype 0 */
139/* 0x35-0x3b is reserved */
140#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
141/* 0x3c-0x3d are same as for htype 0 */
142#define PCI_BRIDGE_CONTROL 0x3e
143#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
144#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
145#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
146#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
147#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
148#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
149#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
150
151/* Header type 2 (CardBus bridges) */
152#define PCI_CB_CAPABILITY_LIST 0x14
153/* 0x15 reserved */
154#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
155#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
156#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
157#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
158#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
159#define PCI_CB_MEMORY_BASE_0 0x1c
160#define PCI_CB_MEMORY_LIMIT_0 0x20
161#define PCI_CB_MEMORY_BASE_1 0x24
162#define PCI_CB_MEMORY_LIMIT_1 0x28
163#define PCI_CB_IO_BASE_0 0x2c
164#define PCI_CB_IO_BASE_0_HI 0x2e
165#define PCI_CB_IO_LIMIT_0 0x30
166#define PCI_CB_IO_LIMIT_0_HI 0x32
167#define PCI_CB_IO_BASE_1 0x34
168#define PCI_CB_IO_BASE_1_HI 0x36
169#define PCI_CB_IO_LIMIT_1 0x38
170#define PCI_CB_IO_LIMIT_1_HI 0x3a
171#define PCI_CB_IO_RANGE_MASK (~0x03UL)
172/* 0x3c-0x3d are same as for htype 0 */
173#define PCI_CB_BRIDGE_CONTROL 0x3e
174#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
175#define PCI_CB_BRIDGE_CTL_SERR 0x02
176#define PCI_CB_BRIDGE_CTL_ISA 0x04
177#define PCI_CB_BRIDGE_CTL_VGA 0x08
178#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
179#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
180#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
181#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
182#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
183#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
184#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
185#define PCI_CB_SUBSYSTEM_ID 0x42
186#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
187/* 0x48-0x7f reserved */
188
189/* Capability lists */
190
191#define PCI_CAP_LIST_ID 0 /* Capability ID */
192#define PCI_CAP_ID_PM 0x01 /* Power Management */
193#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
194#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
195#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
196#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
197#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
198#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
199#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
200#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
201#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
202#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
203#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
204#define PCI_CAP_SIZEOF 4
205
206/* Power Management Registers */
207
208#define PCI_PM_PMC 2 /* PM Capabilities Register */
209#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
210#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
211#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
212#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
213#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
214#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
215#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
216#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
217#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
218#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
219#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
220#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
221#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
222#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
223#define PCI_PM_CTRL 4 /* PM control and status register */
224#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
225#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
226#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
227#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
228#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
229#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
230#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
231#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
232#define PCI_PM_DATA_REGISTER 7 /* (??) */
233#define PCI_PM_SIZEOF 8
234
235/* AGP registers */
236
237#define PCI_AGP_VERSION 2 /* BCD version number */
238#define PCI_AGP_RFU 3 /* Rest of capability flags */
239#define PCI_AGP_STATUS 4 /* Status register */
240#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
241#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
242#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
243#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
244#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
245#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
246#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
247#define PCI_AGP_COMMAND 8 /* Control register */
248#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
249#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
250#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
251#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
252#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
253#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
254#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
255#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
256#define PCI_AGP_SIZEOF 12
257
258/* Vital Product Data */
259
260#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
261#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
262#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
263#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
264
265/* Slot Identification */
266
267#define PCI_SID_ESR 2 /* Expansion Slot Register */
268#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
269#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
270#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
271
272/* Message Signalled Interrupts registers */
273
274#define PCI_MSI_FLAGS 2 /* Various flags */
275#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
276#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
277#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
278#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
279#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
280#define PCI_MSI_RFU 3 /* Rest of capability flags */
281#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
282#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
283#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
284#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
285#define PCI_MSI_MASK_BIT 16 /* Mask bits register */
286
287/* CompactPCI Hotswap Register */
288
289#define PCI_CHSWP_CSR 2 /* Control and Status Register */
290#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
291#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
292#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
293#define PCI_CHSWP_LOO 0x08 /* LED On / Off */
294#define PCI_CHSWP_PI 0x30 /* Programming Interface */
295#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
296#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
297
298/* PCI-X registers */
299
300#define PCI_X_CMD 2 /* Modes & Features */
301#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
302#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
303#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
304#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
305#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
306#define PCI_X_STATUS 4 /* PCI-X capabilities */
307#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
308#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
309#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
310#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
311#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
312#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
313#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
314#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
315#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
316#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
317#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
318#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
319#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
320
321/* PCI Express capability registers */
322
323#define PCI_EXP_FLAGS 2 /* Capabilities register */
324#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
325#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
326#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
327#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
328#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
329#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
330#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
331#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
332#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
333#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
334#define PCI_EXP_DEVCAP 4 /* Device capabilities */
335#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
336#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
337#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
338#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
339#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
340#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
341#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
342#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
343#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
344#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
345#define PCI_EXP_DEVCTL 8 /* Device Control */
346#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
347#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
348#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
349#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
350#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
351#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
352#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
353#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
354#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
355#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
356#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
357#define PCI_EXP_DEVSTA 10 /* Device Status */
358#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
359#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
360#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
361#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
362#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
363#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
364#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
365#define PCI_EXP_LNKCTL 16 /* Link Control */
366#define PCI_EXP_LNKSTA 18 /* Link Status */
367#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
368#define PCI_EXP_SLTCTL 24 /* Slot Control */
369#define PCI_EXP_SLTSTA 26 /* Slot Status */
370#define PCI_EXP_RTCTL 28 /* Root Control */
371#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
372#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
373#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
374#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
375#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
376#define PCI_EXP_RTCAP 30 /* Root Capabilities */
377#define PCI_EXP_RTSTA 32 /* Root Status */
378
379/* Extended Capabilities (PCI-X 2.0 and Express) */
380#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
381#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
382#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
383
384#define PCI_EXT_CAP_ID_ERR 1
385#define PCI_EXT_CAP_ID_VC 2
386#define PCI_EXT_CAP_ID_DSN 3
387#define PCI_EXT_CAP_ID_PWR 4
388
389/* Advanced Error Reporting */
390#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
391#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
392#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
393#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
394#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
395#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
396#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
397#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
398#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
399#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
400#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
401#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
402#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
403 /* Same bits as above */
404#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
405 /* Same bits as above */
406#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
407#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
408#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
409#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
410#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
411#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
412#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
413 /* Same bits as above */
414#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
415#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
416#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
417#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
418#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
419#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
420#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
421#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
422#define PCI_ERR_ROOT_STATUS 48
423#define PCI_ERR_ROOT_COR_SRC 52
424#define PCI_ERR_ROOT_SRC 54
425
426/* Virtual Channel */
427#define PCI_VC_PORT_REG1 4
428#define PCI_VC_PORT_REG2 8
429#define PCI_VC_PORT_CTRL 12
430#define PCI_VC_PORT_STATUS 14
431#define PCI_VC_RES_CAP 16
432#define PCI_VC_RES_CTRL 20
433#define PCI_VC_RES_STATUS 26
434
435/* Power Budgeting */
436#define PCI_PWR_DSR 4 /* Data Select Register */
437#define PCI_PWR_DATA 8 /* Data Register */
438#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
439#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
440#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
441#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
442#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
443#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
444#define PCI_PWR_CAP 12 /* Capability */
445#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
446
447#endif /* LINUX_PCI_REGS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-23 20:32:47 -0400