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-rw-r--r--arch/powerpc/boot/dts/uc101.dts284
-rw-r--r--arch/powerpc/platforms/52xx/mpc5200_simple.c1
2 files changed, 285 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts
new file mode 100644
index 000000000000..019264c62904
--- /dev/null
+++ b/arch/powerpc/boot/dts/uc101.dts
@@ -0,0 +1,284 @@
1/*
2 * Manroland uc101 board Device Tree Source
3 *
4 * Copyright (C) 2009 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 * Copyright 2006-2007 Secret Lab Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "manroland,uc101";
18 compatible = "manroland,uc101";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44
45 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 gpt0: timer@600 { // General Purpose Timer in GPIO mode
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 gpio-controller;
72 #gpio-cells = <2>;
73 };
74
75 gpt1: timer@610 { // General Purpose Timer in GPIO mode
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 reg = <0x610 0x10>;
78 interrupts = <1 10 0>;
79 gpio-controller;
80 #gpio-cells = <2>;
81 };
82
83 gpt2: timer@620 { // General Purpose Timer in GPIO mode
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x620 0x10>;
86 interrupts = <1 11 0>;
87 gpio-controller;
88 #gpio-cells = <2>;
89 };
90
91 gpt3: timer@630 { // General Purpose Timer in GPIO mode
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x630 0x10>;
94 interrupts = <1 12 0>;
95 gpio-controller;
96 #gpio-cells = <2>;
97 };
98
99 gpt4: timer@640 { // General Purpose Timer in GPIO mode
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 reg = <0x640 0x10>;
102 interrupts = <1 13 0>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 };
106
107 gpt5: timer@650 { // General Purpose Timer in GPIO mode
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 reg = <0x650 0x10>;
110 interrupts = <1 14 0>;
111 gpio-controller;
112 #gpio-cells = <2>;
113 };
114
115 gpt6: timer@660 { // General Purpose Timer in GPIO mode
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 reg = <0x660 0x10>;
118 interrupts = <1 15 0>;
119 gpio-controller;
120 #gpio-cells = <2>;
121 };
122
123 gpt7: timer@670 { // General Purpose Timer in GPIO mode
124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
125 reg = <0x670 0x10>;
126 interrupts = <1 16 0>;
127 gpio-controller;
128 #gpio-cells = <2>;
129 };
130
131 gpio_simple: gpio@b00 {
132 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
133 reg = <0xb00 0x40>;
134 interrupts = <1 7 0>;
135 gpio-controller;
136 #gpio-cells = <2>;
137 };
138
139 gpio_wkup: gpio@c00 {
140 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
141 reg = <0xc00 0x40>;
142 interrupts = <1 8 0 0 3 0>;
143 gpio-controller;
144 #gpio-cells = <2>;
145 };
146
147 dma-controller@1200 {
148 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
149 reg = <0x1200 0x80>;
150 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
151 3 4 0 3 5 0 3 6 0 3 7 0
152 3 8 0 3 9 0 3 10 0 3 11 0
153 3 12 0 3 13 0 3 14 0 3 15 0>;
154 };
155
156 xlb@1f00 {
157 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
158 reg = <0x1f00 0x100>;
159 };
160
161 serial@2000 { /* PSC1 in UART mode */
162 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
163 reg = <0x2000 0x100>;
164 interrupts = <2 1 0>;
165 };
166
167 serial@2200 { /* PSC2 in UART mode */
168 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
169 reg = <0x2200 0x100>;
170 interrupts = <2 2 0>;
171 };
172
173 serial@2c00 { /* PSC6 in UART mode */
174 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
175 reg = <0x2c00 0x100>;
176 interrupts = <2 4 0>;
177 };
178
179 ethernet@3000 {
180 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
181 reg = <0x3000 0x400>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <2 5 0>;
184 phy-handle = <&phy0>;
185 };
186
187 mdio@3000 {
188 #address-cells = <1>;
189 #size-cells = <0>;
190 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
191 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
192 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
193
194 phy0: ethernet-phy@0 {
195 compatible = "intel,lxt971";
196 reg = <0>;
197 };
198 };
199
200 ata@3a00 {
201 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
202 reg = <0x3a00 0x100>;
203 interrupts = <2 7 0>;
204 };
205
206 i2c@3d40 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
210 reg = <0x3d40 0x40>;
211 interrupts = <2 16 0>;
212 fsl,preserve-clocking;
213 clock-frequency = <400000>;
214
215 hwmon@2c {
216 compatible = "ad,adm9240";
217 reg = <0x2c>;
218 };
219 rtc@51 {
220 compatible = "nxp,pcf8563";
221 reg = <0x51>;
222 };
223 };
224
225 sram@8000 {
226 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
227 reg = <0x8000 0x4000>;
228 };
229 };
230
231 localbus {
232 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
233
234 #address-cells = <2>;
235 #size-cells = <1>;
236
237 ranges = <0 0 0xff800000 0x00800000
238 1 0 0x80000000 0x00800000
239 3 0 0x80000000 0x00800000>;
240
241 flash@0,0 {
242 compatible = "cfi-flash";
243 reg = <0 0 0x00800000>;
244 bank-width = <2>;
245 device-width = <2>;
246 #size-cells = <1>;
247 #address-cells = <1>;
248
249 partition@0 {
250 label = "DTS";
251 reg = <0x0 0x00100000>;
252 };
253 partition@100000 {
254 label = "Kernel";
255 reg = <0x100000 0x00200000>;
256 };
257 partition@300000 {
258 label = "RootFS";
259 reg = <0x00300000 0x00200000>;
260 };
261 partition@500000 {
262 label = "user";
263 reg = <0x00500000 0x00200000>;
264 };
265 partition@700000 {
266 label = "U-Boot";
267 reg = <0x00700000 0x00040000>;
268 };
269 partition@740000 {
270 label = "Env";
271 reg = <0x00740000 0x00010000>;
272 };
273 partition@750000 {
274 label = "red. Env";
275 reg = <0x00750000 0x00010000>;
276 };
277 partition@760000 {
278 label = "reserve";
279 reg = <0x00760000 0x000a0000>;
280 };
281 };
282
283 };
284};
diff --git a/arch/powerpc/platforms/52xx/mpc5200_simple.c b/arch/powerpc/platforms/52xx/mpc5200_simple.c
index c31e5b534f0a..caf6d92a4b83 100644
--- a/arch/powerpc/platforms/52xx/mpc5200_simple.c
+++ b/arch/powerpc/platforms/52xx/mpc5200_simple.c
@@ -51,6 +51,7 @@ static void __init mpc5200_simple_setup_arch(void)
51/* list of the supported boards */ 51/* list of the supported boards */
52static char *board[] __initdata = { 52static char *board[] __initdata = {
53 "intercontrol,digsy-mtc", 53 "intercontrol,digsy-mtc",
54 "manroland,uc101",
54 "phytec,pcm030", 55 "phytec,pcm030",
55 "phytec,pcm032", 56 "phytec,pcm032",
56 "promess,motionpro", 57 "promess,motionpro",
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 15:24:49 -0500