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-rw-r--r--arch/ppc64/kernel/entry.S9
-rw-r--r--arch/ppc64/kernel/head.S10
-rw-r--r--arch/ppc64/kernel/iSeries_setup.c22
-rw-r--r--arch/ppc64/kernel/idle.c8
-rw-r--r--arch/ppc64/kernel/process.c3
-rw-r--r--arch/ppc64/kernel/setup.c56
-rw-r--r--arch/ppc64/kernel/smp.c3
-rw-r--r--arch/ppc64/kernel/sysfs.c8
-rw-r--r--drivers/net/hamradio/baycom_epp.c126
-rw-r--r--fs/jbd/checkpoint.c5
-rw-r--r--include/asm-ppc64/processor.h186
-rw-r--r--include/asm-ppc64/thread_info.h4
12 files changed, 97 insertions, 343 deletions
diff --git a/arch/ppc64/kernel/entry.S b/arch/ppc64/kernel/entry.S
index d3604056e1a9..b61572eb2a71 100644
--- a/arch/ppc64/kernel/entry.S
+++ b/arch/ppc64/kernel/entry.S
@@ -436,15 +436,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
436 REST_8GPRS(14, r1) 436 REST_8GPRS(14, r1)
437 REST_10GPRS(22, r1) 437 REST_10GPRS(22, r1)
438 438
439#ifdef CONFIG_PPC_ISERIES
440 clrrdi r7,r1,THREAD_SHIFT /* get current_thread_info() */
441 ld r7,TI_FLAGS(r7) /* Get run light flag */
442 mfspr r9,CTRLF
443 srdi r7,r7,TIF_RUN_LIGHT
444 insrdi r9,r7,1,63 /* Insert run light into CTRL */
445 mtspr CTRLT,r9
446#endif
447
448 /* convert old thread to its task_struct for return value */ 439 /* convert old thread to its task_struct for return value */
449 addi r3,r3,-THREAD 440 addi r3,r3,-THREAD
450 ld r7,_NIP(r1) /* Return to _switch caller in new task */ 441 ld r7,_NIP(r1) /* Return to _switch caller in new task */
diff --git a/arch/ppc64/kernel/head.S b/arch/ppc64/kernel/head.S
index 92a744c31ab1..346dbf606b5d 100644
--- a/arch/ppc64/kernel/head.S
+++ b/arch/ppc64/kernel/head.S
@@ -626,10 +626,10 @@ system_reset_iSeries:
626 lhz r24,PACAPACAINDEX(r13) /* Get processor # */ 626 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
627 cmpwi 0,r24,0 /* Are we processor 0? */ 627 cmpwi 0,r24,0 /* Are we processor 0? */
628 beq .__start_initialization_iSeries /* Start up the first processor */ 628 beq .__start_initialization_iSeries /* Start up the first processor */
629 mfspr r4,CTRLF 629 mfspr r4,SPRN_CTRLF
630 li r5,RUNLATCH /* Turn off the run light */ 630 li r5,CTRL_RUNLATCH /* Turn off the run light */
631 andc r4,r4,r5 631 andc r4,r4,r5
632 mtspr CTRLT,r4 632 mtspr SPRN_CTRLT,r4
633 633
6341: 6341:
635 HMT_LOW 635 HMT_LOW
@@ -2082,9 +2082,9 @@ _GLOBAL(hmt_start_secondary)
2082 mfspr r4, HID0 2082 mfspr r4, HID0
2083 ori r4, r4, 0x1 2083 ori r4, r4, 0x1
2084 mtspr HID0, r4 2084 mtspr HID0, r4
2085 mfspr r4, CTRLF 2085 mfspr r4, SPRN_CTRLF
2086 oris r4, r4, 0x40 2086 oris r4, r4, 0x40
2087 mtspr CTRLT, r4 2087 mtspr SPRN_CTRLT, r4
2088 blr 2088 blr
2089#endif 2089#endif
2090 2090
diff --git a/arch/ppc64/kernel/iSeries_setup.c b/arch/ppc64/kernel/iSeries_setup.c
index da20120f2261..6d06eb550a3f 100644
--- a/arch/ppc64/kernel/iSeries_setup.c
+++ b/arch/ppc64/kernel/iSeries_setup.c
@@ -852,6 +852,28 @@ static int __init iSeries_src_init(void)
852 852
853late_initcall(iSeries_src_init); 853late_initcall(iSeries_src_init);
854 854
855static int set_spread_lpevents(char *str)
856{
857 unsigned long i;
858 unsigned long val = simple_strtoul(str, NULL, 0);
859
860 /*
861 * The parameter is the number of processors to share in processing
862 * lp events.
863 */
864 if (( val > 0) && (val <= NR_CPUS)) {
865 for (i = 1; i < val; ++i)
866 paca[i].lpqueue_ptr = paca[0].lpqueue_ptr;
867
868 printk("lpevent processing spread over %ld processors\n", val);
869 } else {
870 printk("invalid spread_lpevents %ld\n", val);
871 }
872
873 return 1;
874}
875__setup("spread_lpevents=", set_spread_lpevents);
876
855void __init iSeries_early_setup(void) 877void __init iSeries_early_setup(void)
856{ 878{
857 iSeries_fixup_klimit(); 879 iSeries_fixup_klimit();
diff --git a/arch/ppc64/kernel/idle.c b/arch/ppc64/kernel/idle.c
index 6abc621d3ba0..f24ce2b87200 100644
--- a/arch/ppc64/kernel/idle.c
+++ b/arch/ppc64/kernel/idle.c
@@ -75,13 +75,9 @@ static int iSeries_idle(void)
75{ 75{
76 struct paca_struct *lpaca; 76 struct paca_struct *lpaca;
77 long oldval; 77 long oldval;
78 unsigned long CTRL;
79 78
80 /* ensure iSeries run light will be out when idle */ 79 /* ensure iSeries run light will be out when idle */
81 clear_thread_flag(TIF_RUN_LIGHT); 80 ppc64_runlatch_off();
82 CTRL = mfspr(CTRLF);
83 CTRL &= ~RUNLATCH;
84 mtspr(CTRLT, CTRL);
85 81
86 lpaca = get_paca(); 82 lpaca = get_paca();
87 83
@@ -111,7 +107,9 @@ static int iSeries_idle(void)
111 } 107 }
112 } 108 }
113 109
110 ppc64_runlatch_on();
114 schedule(); 111 schedule();
112 ppc64_runlatch_off();
115 } 113 }
116 114
117 return 0; 115 return 0;
diff --git a/arch/ppc64/kernel/process.c b/arch/ppc64/kernel/process.c
index 8b0686122738..cdfecbeb331f 100644
--- a/arch/ppc64/kernel/process.c
+++ b/arch/ppc64/kernel/process.c
@@ -378,9 +378,6 @@ copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
378 childregs->gpr[1] = sp + sizeof(struct pt_regs); 378 childregs->gpr[1] = sp + sizeof(struct pt_regs);
379 p->thread.regs = NULL; /* no user register state */ 379 p->thread.regs = NULL; /* no user register state */
380 clear_ti_thread_flag(p->thread_info, TIF_32BIT); 380 clear_ti_thread_flag(p->thread_info, TIF_32BIT);
381#ifdef CONFIG_PPC_ISERIES
382 set_ti_thread_flag(p->thread_info, TIF_RUN_LIGHT);
383#endif
384 } else { 381 } else {
385 childregs->gpr[1] = usp; 382 childregs->gpr[1] = usp;
386 p->thread.regs = childregs; 383 p->thread.regs = childregs;
diff --git a/arch/ppc64/kernel/setup.c b/arch/ppc64/kernel/setup.c
index 21c57f539c29..dce198d39328 100644
--- a/arch/ppc64/kernel/setup.c
+++ b/arch/ppc64/kernel/setup.c
@@ -103,11 +103,6 @@ extern void unflatten_device_tree(void);
103 103
104extern void smp_release_cpus(void); 104extern void smp_release_cpus(void);
105 105
106unsigned long decr_overclock = 1;
107unsigned long decr_overclock_proc0 = 1;
108unsigned long decr_overclock_set = 0;
109unsigned long decr_overclock_proc0_set = 0;
110
111int have_of = 1; 106int have_of = 1;
112int boot_cpuid = 0; 107int boot_cpuid = 0;
113int boot_cpuid_phys = 0; 108int boot_cpuid_phys = 0;
@@ -1120,64 +1115,15 @@ void ppc64_dump_msg(unsigned int src, const char *msg)
1120 printk("[dump]%04x %s\n", src, msg); 1115 printk("[dump]%04x %s\n", src, msg);
1121} 1116}
1122 1117
1123int set_spread_lpevents( char * str )
1124{
1125 /* The parameter is the number of processors to share in processing lp events */
1126 unsigned long i;
1127 unsigned long val = simple_strtoul( str, NULL, 0 );
1128 if ( ( val > 0 ) && ( val <= NR_CPUS ) ) {
1129 for ( i=1; i<val; ++i )
1130 paca[i].lpqueue_ptr = paca[0].lpqueue_ptr;
1131 printk("lpevent processing spread over %ld processors\n", val);
1132 }
1133 else
1134 printk("invalid spreaqd_lpevents %ld\n", val);
1135 return 1;
1136}
1137
1138/* This should only be called on processor 0 during calibrate decr */ 1118/* This should only be called on processor 0 during calibrate decr */
1139void setup_default_decr(void) 1119void setup_default_decr(void)
1140{ 1120{
1141 struct paca_struct *lpaca = get_paca(); 1121 struct paca_struct *lpaca = get_paca();
1142 1122
1143 if ( decr_overclock_set && !decr_overclock_proc0_set ) 1123 lpaca->default_decr = tb_ticks_per_jiffy;
1144 decr_overclock_proc0 = decr_overclock;
1145
1146 lpaca->default_decr = tb_ticks_per_jiffy / decr_overclock_proc0;
1147 lpaca->next_jiffy_update_tb = get_tb() + tb_ticks_per_jiffy; 1124 lpaca->next_jiffy_update_tb = get_tb() + tb_ticks_per_jiffy;
1148} 1125}
1149 1126
1150int set_decr_overclock_proc0( char * str )
1151{
1152 unsigned long val = simple_strtoul( str, NULL, 0 );
1153 if ( ( val >= 1 ) && ( val <= 48 ) ) {
1154 decr_overclock_proc0_set = 1;
1155 decr_overclock_proc0 = val;
1156 printk("proc 0 decrementer overclock factor of %ld\n", val);
1157 }
1158 else
1159 printk("invalid proc 0 decrementer overclock factor of %ld\n", val);
1160 return 1;
1161}
1162
1163int set_decr_overclock( char * str )
1164{
1165 unsigned long val = simple_strtoul( str, NULL, 0 );
1166 if ( ( val >= 1 ) && ( val <= 48 ) ) {
1167 decr_overclock_set = 1;
1168 decr_overclock = val;
1169 printk("decrementer overclock factor of %ld\n", val);
1170 }
1171 else
1172 printk("invalid decrementer overclock factor of %ld\n", val);
1173 return 1;
1174
1175}
1176
1177__setup("spread_lpevents=", set_spread_lpevents );
1178__setup("decr_overclock_proc0=", set_decr_overclock_proc0 );
1179__setup("decr_overclock=", set_decr_overclock );
1180
1181#ifndef CONFIG_PPC_ISERIES 1127#ifndef CONFIG_PPC_ISERIES
1182/* 1128/*
1183 * This function can be used by platforms to "find" legacy serial ports. 1129 * This function can be used by platforms to "find" legacy serial ports.
diff --git a/arch/ppc64/kernel/smp.c b/arch/ppc64/kernel/smp.c
index 3b906cd94037..9ef5d36d6b25 100644
--- a/arch/ppc64/kernel/smp.c
+++ b/arch/ppc64/kernel/smp.c
@@ -334,7 +334,6 @@ void smp_call_function_interrupt(void)
334 } 334 }
335} 335}
336 336
337extern unsigned long decr_overclock;
338extern struct gettimeofday_struct do_gtod; 337extern struct gettimeofday_struct do_gtod;
339 338
340struct thread_info *current_set[NR_CPUS]; 339struct thread_info *current_set[NR_CPUS];
@@ -491,7 +490,7 @@ int __devinit __cpu_up(unsigned int cpu)
491 if (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu)) 490 if (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))
492 return -EINVAL; 491 return -EINVAL;
493 492
494 paca[cpu].default_decr = tb_ticks_per_jiffy / decr_overclock; 493 paca[cpu].default_decr = tb_ticks_per_jiffy;
495 494
496 if (!cpu_has_feature(CPU_FTR_SLB)) { 495 if (!cpu_has_feature(CPU_FTR_SLB)) {
497 void *tmp; 496 void *tmp;
diff --git a/arch/ppc64/kernel/sysfs.c b/arch/ppc64/kernel/sysfs.c
index 0925694c3ce5..c8fa6569b2fd 100644
--- a/arch/ppc64/kernel/sysfs.c
+++ b/arch/ppc64/kernel/sysfs.c
@@ -113,7 +113,6 @@ void ppc64_enable_pmcs(void)
113#ifdef CONFIG_PPC_PSERIES 113#ifdef CONFIG_PPC_PSERIES
114 unsigned long set, reset; 114 unsigned long set, reset;
115 int ret; 115 int ret;
116 unsigned int ctrl;
117#endif /* CONFIG_PPC_PSERIES */ 116#endif /* CONFIG_PPC_PSERIES */
118 117
119 /* Only need to enable them once */ 118 /* Only need to enable them once */
@@ -167,11 +166,8 @@ void ppc64_enable_pmcs(void)
167 * On SMT machines we have to set the run latch in the ctrl register 166 * On SMT machines we have to set the run latch in the ctrl register
168 * in order to make PMC6 spin. 167 * in order to make PMC6 spin.
169 */ 168 */
170 if (cpu_has_feature(CPU_FTR_SMT)) { 169 if (cpu_has_feature(CPU_FTR_SMT))
171 ctrl = mfspr(CTRLF); 170 ppc64_runlatch_on();
172 ctrl |= RUNLATCH;
173 mtspr(CTRLT, ctrl);
174 }
175#endif /* CONFIG_PPC_PSERIES */ 171#endif /* CONFIG_PPC_PSERIES */
176} 172}
177 173
diff --git a/drivers/net/hamradio/baycom_epp.c b/drivers/net/hamradio/baycom_epp.c
index 1c563f905a59..a7f15d9f13e5 100644
--- a/drivers/net/hamradio/baycom_epp.c
+++ b/drivers/net/hamradio/baycom_epp.c
@@ -374,29 +374,6 @@ static inline void do_kiss_params(struct baycom_state *bc,
374} 374}
375 375
376/* --------------------------------------------------------------------- */ 376/* --------------------------------------------------------------------- */
377/*
378 * high performance HDLC encoder
379 * yes, it's ugly, but generates pretty good code
380 */
381
382#define ENCODEITERA(j) \
383({ \
384 if (!(notbitstream & (0x1f0 << j))) \
385 goto stuff##j; \
386 encodeend##j: ; \
387})
388
389#define ENCODEITERB(j) \
390({ \
391 stuff##j: \
392 bitstream &= ~(0x100 << j); \
393 bitbuf = (bitbuf & (((2 << j) << numbit) - 1)) | \
394 ((bitbuf & ~(((2 << j) << numbit) - 1)) << 1); \
395 numbit++; \
396 notbitstream = ~bitstream; \
397 goto encodeend##j; \
398})
399
400 377
401static void encode_hdlc(struct baycom_state *bc) 378static void encode_hdlc(struct baycom_state *bc)
402{ 379{
@@ -405,6 +382,7 @@ static void encode_hdlc(struct baycom_state *bc)
405 int pkt_len; 382 int pkt_len;
406 unsigned bitstream, notbitstream, bitbuf, numbit, crc; 383 unsigned bitstream, notbitstream, bitbuf, numbit, crc;
407 unsigned char crcarr[2]; 384 unsigned char crcarr[2];
385 int j;
408 386
409 if (bc->hdlctx.bufcnt > 0) 387 if (bc->hdlctx.bufcnt > 0)
410 return; 388 return;
@@ -429,24 +407,14 @@ static void encode_hdlc(struct baycom_state *bc)
429 pkt_len--; 407 pkt_len--;
430 if (!pkt_len) 408 if (!pkt_len)
431 bp = crcarr; 409 bp = crcarr;
432 ENCODEITERA(0); 410 for (j = 0; j < 8; j++)
433 ENCODEITERA(1); 411 if (unlikely(!(notbitstream & (0x1f0 << j)))) {
434 ENCODEITERA(2); 412 bitstream &= ~(0x100 << j);
435 ENCODEITERA(3); 413 bitbuf = (bitbuf & (((2 << j) << numbit) - 1)) |
436 ENCODEITERA(4); 414 ((bitbuf & ~(((2 << j) << numbit) - 1)) << 1);
437 ENCODEITERA(5); 415 numbit++;
438 ENCODEITERA(6); 416 notbitstream = ~bitstream;
439 ENCODEITERA(7); 417 }
440 goto enditer;
441 ENCODEITERB(0);
442 ENCODEITERB(1);
443 ENCODEITERB(2);
444 ENCODEITERB(3);
445 ENCODEITERB(4);
446 ENCODEITERB(5);
447 ENCODEITERB(6);
448 ENCODEITERB(7);
449 enditer:
450 numbit += 8; 418 numbit += 8;
451 while (numbit >= 8) { 419 while (numbit >= 8) {
452 *wp++ = bitbuf; 420 *wp++ = bitbuf;
@@ -610,37 +578,6 @@ static void do_rxpacket(struct net_device *dev)
610 bc->stats.rx_packets++; 578 bc->stats.rx_packets++;
611} 579}
612 580
613#define DECODEITERA(j) \
614({ \
615 if (!(notbitstream & (0x0fc << j))) /* flag or abort */ \
616 goto flgabrt##j; \
617 if ((bitstream & (0x1f8 << j)) == (0xf8 << j)) /* stuffed bit */ \
618 goto stuff##j; \
619 enditer##j: ; \
620})
621
622#define DECODEITERB(j) \
623({ \
624 flgabrt##j: \
625 if (!(notbitstream & (0x1fc << j))) { /* abort received */ \
626 state = 0; \
627 goto enditer##j; \
628 } \
629 if ((bitstream & (0x1fe << j)) != (0x0fc << j)) /* flag received */ \
630 goto enditer##j; \
631 if (state) \
632 do_rxpacket(dev); \
633 bc->hdlcrx.bufcnt = 0; \
634 bc->hdlcrx.bufptr = bc->hdlcrx.buf; \
635 state = 1; \
636 numbits = 7-j; \
637 goto enditer##j; \
638 stuff##j: \
639 numbits--; \
640 bitbuf = (bitbuf & ((~0xff) << j)) | ((bitbuf & ~((~0xff) << j)) << 1); \
641 goto enditer##j; \
642})
643
644static int receive(struct net_device *dev, int cnt) 581static int receive(struct net_device *dev, int cnt)
645{ 582{
646 struct baycom_state *bc = netdev_priv(dev); 583 struct baycom_state *bc = netdev_priv(dev);
@@ -649,6 +586,7 @@ static int receive(struct net_device *dev, int cnt)
649 unsigned char tmp[128]; 586 unsigned char tmp[128];
650 unsigned char *cp; 587 unsigned char *cp;
651 int cnt2, ret = 0; 588 int cnt2, ret = 0;
589 int j;
652 590
653 numbits = bc->hdlcrx.numbits; 591 numbits = bc->hdlcrx.numbits;
654 state = bc->hdlcrx.state; 592 state = bc->hdlcrx.state;
@@ -669,24 +607,32 @@ static int receive(struct net_device *dev, int cnt)
669 bitbuf |= (*cp) << 8; 607 bitbuf |= (*cp) << 8;
670 numbits += 8; 608 numbits += 8;
671 notbitstream = ~bitstream; 609 notbitstream = ~bitstream;
672 DECODEITERA(0); 610 for (j = 0; j < 8; j++) {
673 DECODEITERA(1); 611
674 DECODEITERA(2); 612 /* flag or abort */
675 DECODEITERA(3); 613 if (unlikely(!(notbitstream & (0x0fc << j)))) {
676 DECODEITERA(4); 614
677 DECODEITERA(5); 615 /* abort received */
678 DECODEITERA(6); 616 if (!(notbitstream & (0x1fc << j)))
679 DECODEITERA(7); 617 state = 0;
680 goto enddec; 618
681 DECODEITERB(0); 619 /* not flag received */
682 DECODEITERB(1); 620 else if (!(bitstream & (0x1fe << j)) != (0x0fc << j)) {
683 DECODEITERB(2); 621 if (state)
684 DECODEITERB(3); 622 do_rxpacket(dev);
685 DECODEITERB(4); 623 bc->hdlcrx.bufcnt = 0;
686 DECODEITERB(5); 624 bc->hdlcrx.bufptr = bc->hdlcrx.buf;
687 DECODEITERB(6); 625 state = 1;
688 DECODEITERB(7); 626 numbits = 7-j;
689 enddec: 627 }
628 }
629
630 /* stuffed bit */
631 else if (unlikely((bitstream & (0x1f8 << j)) == (0xf8 << j))) {
632 numbits--;
633 bitbuf = (bitbuf & ((~0xff) << j)) | ((bitbuf & ~((~0xff) << j)) << 1);
634 }
635 }
690 while (state && numbits >= 8) { 636 while (state && numbits >= 8) {
691 if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) { 637 if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) {
692 state = 0; 638 state = 0;
diff --git a/fs/jbd/checkpoint.c b/fs/jbd/checkpoint.c
index 98d830401c56..5a97e346bd95 100644
--- a/fs/jbd/checkpoint.c
+++ b/fs/jbd/checkpoint.c
@@ -188,7 +188,6 @@ static int __cleanup_transaction(journal_t *journal, transaction_t *transaction)
188 } else { 188 } else {
189 jbd_unlock_bh_state(bh); 189 jbd_unlock_bh_state(bh);
190 } 190 }
191 jh = next_jh;
192 } while (jh != last_jh); 191 } while (jh != last_jh);
193 192
194 return ret; 193 return ret;
@@ -339,8 +338,10 @@ int log_do_checkpoint(journal_t *journal)
339 } 338 }
340 } while (jh != last_jh && !retry); 339 } while (jh != last_jh && !retry);
341 340
342 if (batch_count) 341 if (batch_count) {
343 __flush_batch(journal, bhs, &batch_count); 342 __flush_batch(journal, bhs, &batch_count);
343 retry = 1;
344 }
344 345
345 /* 346 /*
346 * If someone cleaned up this transaction while we slept, we're 347 * If someone cleaned up this transaction while we slept, we're
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
index 0035efe2db2b..809c634ba1df 100644
--- a/include/asm-ppc64/processor.h
+++ b/include/asm-ppc64/processor.h
@@ -120,103 +120,18 @@
120 120
121/* Special Purpose Registers (SPRNs)*/ 121/* Special Purpose Registers (SPRNs)*/
122 122
123#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
124#define SPRN_CTR 0x009 /* Count Register */ 123#define SPRN_CTR 0x009 /* Count Register */
125#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 124#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
126#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ 125#define DABR_TRANSLATION (1UL << 2)
127#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
128#define SPRN_DAR 0x013 /* Data Address Register */ 126#define SPRN_DAR 0x013 /* Data Address Register */
129#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
130#define DBCR_EDM 0x80000000
131#define DBCR_IDM 0x40000000
132#define DBCR_RST(x) (((x) & 0x3) << 28)
133#define DBCR_RST_NONE 0
134#define DBCR_RST_CORE 1
135#define DBCR_RST_CHIP 2
136#define DBCR_RST_SYSTEM 3
137#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
138#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
139#define DBCR_EDE 0x02000000 /* Exception Debug Event */
140#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
141#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
142#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
143#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
144#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
145#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
146#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
147#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
148#define DAC_BYTE 0
149#define DAC_HALF 1
150#define DAC_WORD 2
151#define DAC_QUAD 3
152#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
153#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
154#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
155#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
156#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
157#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
158#define DBCR_SIA 0x00000008 /* Second IAC Enable */
159#define DBCR_SDA 0x00000004 /* Second DAC Enable */
160#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
161#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
162#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
163#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
164#define SPRN_DBSR 0x3F0 /* Debug Status Register */
165#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
166#define DCCR_NOCACHE 0 /* Noncacheable */
167#define DCCR_CACHE 1 /* Cacheable */
168#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
169#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
170#define DCWR_COPY 0 /* Copy-back */
171#define DCWR_WRITE 1 /* Write-through */
172#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
173#define SPRN_DEC 0x016 /* Decrement Register */ 127#define SPRN_DEC 0x016 /* Decrement Register */
174#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
175#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 128#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
176#define DSISR_NOHPTE 0x40000000 /* no translation found */ 129#define DSISR_NOHPTE 0x40000000 /* no translation found */
177#define DSISR_PROTFAULT 0x08000000 /* protection fault */ 130#define DSISR_PROTFAULT 0x08000000 /* protection fault */
178#define DSISR_ISSTORE 0x02000000 /* access was a store */ 131#define DSISR_ISSTORE 0x02000000 /* access was a store */
179#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ 132#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
180#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */ 133#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
181#define SPRN_EAR 0x11A /* External Address Register */
182#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
183#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
184#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
185#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
186#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
187#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
188#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
189#define ESR_PTR 0x02000000 /* Program Exception - Trap */
190#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
191#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
192#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
193#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
194#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
195#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ 134#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
196#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
197#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
198#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
199#define HID0_SBCLK (1<<27)
200#define HID0_EICE (1<<26)
201#define HID0_ECLK (1<<25)
202#define HID0_PAR (1<<24)
203#define HID0_DOZE (1<<23)
204#define HID0_NAP (1<<22)
205#define HID0_SLEEP (1<<21)
206#define HID0_DPM (1<<20)
207#define HID0_ICE (1<<15) /* Instruction Cache Enable */
208#define HID0_DCE (1<<14) /* Data Cache Enable */
209#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
210#define HID0_DLOCK (1<<12) /* Data Cache Lock */
211#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
212#define HID0_DCI (1<<10) /* Data Cache Invalidate */
213#define HID0_SPD (1<<9) /* Speculative disable */
214#define HID0_SGE (1<<7) /* Store Gathering Enable */
215#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
216#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
217#define HID0_ABE (1<<3) /* Address Broadcast Enable */
218#define HID0_BHTE (1<<2) /* Branch History Table Enable */
219#define HID0_BTCD (1<<1) /* Branch target cache disable */
220#define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */ 135#define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */
221#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ 136#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
222#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 137#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
@@ -225,23 +140,8 @@
225#define SPRN_HID5 0x3F6 /* 970 HID5 */ 140#define SPRN_HID5 0x3F6 /* 970 HID5 */
226#define SPRN_TSC 0x3FD /* Thread switch control */ 141#define SPRN_TSC 0x3FD /* Thread switch control */
227#define SPRN_TST 0x3FC /* Thread switch timeout */ 142#define SPRN_TST 0x3FC /* Thread switch timeout */
228#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
229#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
230#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
231#define ICCR_NOCACHE 0 /* Noncacheable */
232#define ICCR_CACHE 1 /* Cacheable */
233#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
234#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
235#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
236#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
237#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
238#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ 143#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
239#define SPRN_LR 0x008 /* Link Register */ 144#define SPRN_LR 0x008 /* Link Register */
240#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
241#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
242#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
243#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
244#define SPRN_PID 0x3B1 /* Process ID */
245#define SPRN_PIR 0x3FF /* Processor Identification Register */ 145#define SPRN_PIR 0x3FF /* Processor Identification Register */
246#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 146#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
247#define SPRN_PURR 0x135 /* Processor Utilization of Resources Register */ 147#define SPRN_PURR 0x135 /* Processor Utilization of Resources Register */
@@ -249,9 +149,6 @@
249#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 149#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
250#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ 150#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
251#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 151#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
252#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
253#define SGR_NORMAL 0
254#define SGR_GUARDED 1
255#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 152#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
256#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 153#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
257#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 154#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
@@ -264,50 +161,12 @@
264#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, W/O) */ 161#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, W/O) */
265#define SPRN_TBWU 0x11D /* Time Base Write Upper Register (super, W/O) */ 162#define SPRN_TBWU 0x11D /* Time Base Write Upper Register (super, W/O) */
266#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 163#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
267#define SPRN_TCR 0x3DA /* Timer Control Register */
268#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
269#define WP_2_17 0 /* 2^17 clocks */
270#define WP_2_21 1 /* 2^21 clocks */
271#define WP_2_25 2 /* 2^25 clocks */
272#define WP_2_29 3 /* 2^29 clocks */
273#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
274#define WRC_NONE 0 /* No reset will occur */
275#define WRC_CORE 1 /* Core reset will occur */
276#define WRC_CHIP 2 /* Chip reset will occur */
277#define WRC_SYSTEM 3 /* System reset will occur */
278#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
279#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
280#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
281#define FP_2_9 0 /* 2^9 clocks */
282#define FP_2_13 1 /* 2^13 clocks */
283#define FP_2_17 2 /* 2^17 clocks */
284#define FP_2_21 3 /* 2^21 clocks */
285#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
286#define TCR_ARE 0x00400000 /* Auto Reload Enable */
287#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
288#define THRM1_TIN (1<<0)
289#define THRM1_TIV (1<<1)
290#define THRM1_THRES (0x7f<<2)
291#define THRM1_TID (1<<29)
292#define THRM1_TIE (1<<30)
293#define THRM1_V (1<<31)
294#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
295#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
296#define THRM3_E (1<<31)
297#define SPRN_TSR 0x3D8 /* Timer Status Register */
298#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
299#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
300#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
301#define WRS_NONE 0 /* No WDT reset occurred */
302#define WRS_CORE 1 /* WDT forced core reset */
303#define WRS_CHIP 2 /* WDT forced chip reset */
304#define WRS_SYSTEM 3 /* WDT forced system reset */
305#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
306#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
307#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ 164#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
308#define SPRN_XER 0x001 /* Fixed Point Exception Register */ 165#define SPRN_XER 0x001 /* Fixed Point Exception Register */
309#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
310#define SPRN_VRSAVE 0x100 /* Vector save */ 166#define SPRN_VRSAVE 0x100 /* Vector save */
167#define SPRN_CTRLF 0x088
168#define SPRN_CTRLT 0x098
169#define CTRL_RUNLATCH 0x1
311 170
312/* Performance monitor SPRs */ 171/* Performance monitor SPRs */
313#define SPRN_SIAR 780 172#define SPRN_SIAR 780
@@ -352,28 +211,19 @@
352#define CTR SPRN_CTR /* Counter Register */ 211#define CTR SPRN_CTR /* Counter Register */
353#define DAR SPRN_DAR /* Data Address Register */ 212#define DAR SPRN_DAR /* Data Address Register */
354#define DABR SPRN_DABR /* Data Address Breakpoint Register */ 213#define DABR SPRN_DABR /* Data Address Breakpoint Register */
355#define DCMP SPRN_DCMP /* Data TLB Compare Register */
356#define DEC SPRN_DEC /* Decrement Register */ 214#define DEC SPRN_DEC /* Decrement Register */
357#define DMISS SPRN_DMISS /* Data TLB Miss Register */
358#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ 215#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
359#define EAR SPRN_EAR /* External Address Register */
360#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
361#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
362#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ 216#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
363#define MSRDORM SPRN_MSRDORM /* MSR Dormant Register */ 217#define MSRDORM SPRN_MSRDORM /* MSR Dormant Register */
364#define NIADORM SPRN_NIADORM /* NIA Dormant Register */ 218#define NIADORM SPRN_NIADORM /* NIA Dormant Register */
365#define TSC SPRN_TSC /* Thread switch control */ 219#define TSC SPRN_TSC /* Thread switch control */
366#define TST SPRN_TST /* Thread switch timeout */ 220#define TST SPRN_TST /* Thread switch timeout */
367#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ 221#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
368#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
369#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
370#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
371#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ 222#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
372#define __LR SPRN_LR 223#define __LR SPRN_LR
373#define PVR SPRN_PVR /* Processor Version */ 224#define PVR SPRN_PVR /* Processor Version */
374#define PIR SPRN_PIR /* Processor ID */ 225#define PIR SPRN_PIR /* Processor ID */
375#define PURR SPRN_PURR /* Processor Utilization of Resource Register */ 226#define PURR SPRN_PURR /* Processor Utilization of Resource Register */
376//#define RPA SPRN_RPA /* Required Physical Address Register */
377#define SDR1 SPRN_SDR1 /* MMU hash base register */ 227#define SDR1 SPRN_SDR1 /* MMU hash base register */
378#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ 228#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
379#define SPR1 SPRN_SPRG1 229#define SPR1 SPRN_SPRG1
@@ -389,10 +239,6 @@
389#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ 239#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
390#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ 240#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
391#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ 241#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
392#define ICTC 1019
393#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
394#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
395#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
396#define XER SPRN_XER 242#define XER SPRN_XER
397 243
398/* Processor Version Register (PVR) field extraction */ 244/* Processor Version Register (PVR) field extraction */
@@ -436,12 +282,6 @@
436#define XGLUE(a,b) a##b 282#define XGLUE(a,b) a##b
437#define GLUE(a,b) XGLUE(a,b) 283#define GLUE(a,b) XGLUE(a,b)
438 284
439/* iSeries CTRL register (for runlatch) */
440
441#define CTRLT 0x098
442#define CTRLF 0x088
443#define RUNLATCH 0x0001
444
445#ifdef __ASSEMBLY__ 285#ifdef __ASSEMBLY__
446 286
447#define _GLOBAL(name) \ 287#define _GLOBAL(name) \
@@ -656,6 +496,24 @@ static inline void prefetchw(const void *x)
656 496
657#define HAVE_ARCH_PICK_MMAP_LAYOUT 497#define HAVE_ARCH_PICK_MMAP_LAYOUT
658 498
499static inline void ppc64_runlatch_on(void)
500{
501 unsigned long ctrl;
502
503 ctrl = mfspr(SPRN_CTRLF);
504 ctrl |= CTRL_RUNLATCH;
505 mtspr(SPRN_CTRLT, ctrl);
506}
507
508static inline void ppc64_runlatch_off(void)
509{
510 unsigned long ctrl;
511
512 ctrl = mfspr(SPRN_CTRLF);
513 ctrl &= ~CTRL_RUNLATCH;
514 mtspr(SPRN_CTRLT, ctrl);
515}
516
659#endif /* __KERNEL__ */ 517#endif /* __KERNEL__ */
660 518
661#endif /* __ASSEMBLY__ */ 519#endif /* __ASSEMBLY__ */
diff --git a/include/asm-ppc64/thread_info.h b/include/asm-ppc64/thread_info.h
index 037b5e06083c..48b7900e90ec 100644
--- a/include/asm-ppc64/thread_info.h
+++ b/include/asm-ppc64/thread_info.h
@@ -96,7 +96,7 @@ static inline struct thread_info *current_thread_info(void)
96#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling 96#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling
97 TIF_NEED_RESCHED */ 97 TIF_NEED_RESCHED */
98#define TIF_32BIT 5 /* 32 bit binary */ 98#define TIF_32BIT 5 /* 32 bit binary */
99#define TIF_RUN_LIGHT 6 /* iSeries run light */ 99/* #define SPARE 6 */
100#define TIF_ABI_PENDING 7 /* 32/64 bit switch needed */ 100#define TIF_ABI_PENDING 7 /* 32/64 bit switch needed */
101#define TIF_SYSCALL_AUDIT 8 /* syscall auditing active */ 101#define TIF_SYSCALL_AUDIT 8 /* syscall auditing active */
102#define TIF_SINGLESTEP 9 /* singlestepping active */ 102#define TIF_SINGLESTEP 9 /* singlestepping active */
@@ -110,7 +110,7 @@ static inline struct thread_info *current_thread_info(void)
110#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 110#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
111#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 111#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
112#define _TIF_32BIT (1<<TIF_32BIT) 112#define _TIF_32BIT (1<<TIF_32BIT)
113#define _TIF_RUN_LIGHT (1<<TIF_RUN_LIGHT) 113/* #define _SPARE (1<<SPARE) */
114#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING) 114#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
115#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) 115#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
116#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) 116#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-02 15:22:49 -0500