diff options
| -rw-r--r-- | arch/x86/kvm/vmx.h | 15 | ||||
| -rw-r--r-- | include/asm-x86/msr-index.h | 16 |
2 files changed, 16 insertions, 15 deletions
diff --git a/arch/x86/kvm/vmx.h b/arch/x86/kvm/vmx.h index 425a13436b3f..b32d4e5b123d 100644 --- a/arch/x86/kvm/vmx.h +++ b/arch/x86/kvm/vmx.h | |||
| @@ -331,21 +331,6 @@ enum vmcs_field { | |||
| 331 | 331 | ||
| 332 | #define AR_RESERVD_MASK 0xfffe0f00 | 332 | #define AR_RESERVD_MASK 0xfffe0f00 |
| 333 | 333 | ||
| 334 | #define MSR_IA32_VMX_BASIC 0x480 | ||
| 335 | #define MSR_IA32_VMX_PINBASED_CTLS 0x481 | ||
| 336 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 | ||
| 337 | #define MSR_IA32_VMX_EXIT_CTLS 0x483 | ||
| 338 | #define MSR_IA32_VMX_ENTRY_CTLS 0x484 | ||
| 339 | #define MSR_IA32_VMX_MISC 0x485 | ||
| 340 | #define MSR_IA32_VMX_CR0_FIXED0 0x486 | ||
| 341 | #define MSR_IA32_VMX_CR0_FIXED1 0x487 | ||
| 342 | #define MSR_IA32_VMX_CR4_FIXED0 0x488 | ||
| 343 | #define MSR_IA32_VMX_CR4_FIXED1 0x489 | ||
| 344 | #define MSR_IA32_VMX_VMCS_ENUM 0x48a | ||
| 345 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b | ||
| 346 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c | ||
| 347 | |||
| 348 | #define MSR_IA32_FEATURE_CONTROL 0x3a | ||
| 349 | #define MSR_IA32_FEATURE_CONTROL_LOCKED 0x1 | 334 | #define MSR_IA32_FEATURE_CONTROL_LOCKED 0x1 |
| 350 | #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED 0x4 | 335 | #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED 0x4 |
| 351 | 336 | ||
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h index 3052f058ab06..0bb43301a202 100644 --- a/include/asm-x86/msr-index.h +++ b/include/asm-x86/msr-index.h | |||
| @@ -176,6 +176,7 @@ | |||
| 176 | #define MSR_IA32_TSC 0x00000010 | 176 | #define MSR_IA32_TSC 0x00000010 |
| 177 | #define MSR_IA32_PLATFORM_ID 0x00000017 | 177 | #define MSR_IA32_PLATFORM_ID 0x00000017 |
| 178 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a | 178 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a |
| 179 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a | ||
| 179 | 180 | ||
| 180 | #define MSR_IA32_APICBASE 0x0000001b | 181 | #define MSR_IA32_APICBASE 0x0000001b |
| 181 | #define MSR_IA32_APICBASE_BSP (1<<8) | 182 | #define MSR_IA32_APICBASE_BSP (1<<8) |
| @@ -310,4 +311,19 @@ | |||
| 310 | /* Geode defined MSRs */ | 311 | /* Geode defined MSRs */ |
| 311 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 | 312 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 |
| 312 | 313 | ||
| 314 | /* Intel VT MSRs */ | ||
| 315 | #define MSR_IA32_VMX_BASIC 0x00000480 | ||
| 316 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 | ||
| 317 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 | ||
| 318 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 | ||
| 319 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 | ||
| 320 | #define MSR_IA32_VMX_MISC 0x00000485 | ||
| 321 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 | ||
| 322 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 | ||
| 323 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 | ||
| 324 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 | ||
| 325 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a | ||
| 326 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b | ||
| 327 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c | ||
| 328 | |||
| 313 | #endif /* ASM_X86__MSR_INDEX_H */ | 329 | #endif /* ASM_X86__MSR_INDEX_H */ |
