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-rw-r--r--arch/powerpc/kernel/misc_32.S23
-rw-r--r--arch/ppc/kernel/misc.S4
-rw-r--r--arch/ppc/kernel/ppc_ksyms.c1
-rw-r--r--arch/ppc/platforms/prep_setup.c9
-rw-r--r--include/asm-powerpc/cache.h40
-rw-r--r--include/asm-powerpc/cacheflush.h (renamed from include/asm-ppc64/cacheflush.h)52
-rw-r--r--include/asm-powerpc/reg.h6
-rw-r--r--include/asm-powerpc/reg_8xx.h (renamed from include/asm-ppc/cache.h)50
-rw-r--r--include/asm-ppc/cacheflush.h49
-rw-r--r--include/asm-ppc64/cache.h36
10 files changed, 98 insertions, 172 deletions
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 3bedb532aed9..f6d84a75ed26 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -519,7 +519,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
519 * 519 *
520 * flush_icache_range(unsigned long start, unsigned long stop) 520 * flush_icache_range(unsigned long start, unsigned long stop)
521 */ 521 */
522_GLOBAL(flush_icache_range) 522_GLOBAL(__flush_icache_range)
523BEGIN_FTR_SECTION 523BEGIN_FTR_SECTION
524 blr /* for 601, do nothing */ 524 blr /* for 601, do nothing */
525END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) 525END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
@@ -607,27 +607,6 @@ _GLOBAL(invalidate_dcache_range)
607 sync /* wait for dcbi's to get to ram */ 607 sync /* wait for dcbi's to get to ram */
608 blr 608 blr
609 609
610#ifdef CONFIG_NOT_COHERENT_CACHE
611/*
612 * 40x cores have 8K or 16K dcache and 32 byte line size.
613 * 44x has a 32K dcache and 32 byte line size.
614 * 8xx has 1, 2, 4, 8K variants.
615 * For now, cover the worst case of the 44x.
616 * Must be called with external interrupts disabled.
617 */
618#define CACHE_NWAYS 64
619#define CACHE_NLINES 16
620
621_GLOBAL(flush_dcache_all)
622 li r4, (2 * CACHE_NWAYS * CACHE_NLINES)
623 mtctr r4
624 lis r5, KERNELBASE@h
6251: lwz r3, 0(r5) /* Load one word from every line */
626 addi r5, r5, L1_CACHE_BYTES
627 bdnz 1b
628 blr
629#endif /* CONFIG_NOT_COHERENT_CACHE */
630
631/* 610/*
632 * Flush a particular page from the data cache to RAM. 611 * Flush a particular page from the data cache to RAM.
633 * Note: this is necessary because the instruction cache does *not* 612 * Note: this is necessary because the instruction cache does *not*
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index ae6af29938a1..5e61124581d0 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -497,9 +497,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
497 * and invalidate the corresponding instruction cache blocks. 497 * and invalidate the corresponding instruction cache blocks.
498 * This is a no-op on the 601. 498 * This is a no-op on the 601.
499 * 499 *
500 * flush_icache_range(unsigned long start, unsigned long stop) 500 * __flush_icache_range(unsigned long start, unsigned long stop)
501 */ 501 */
502_GLOBAL(flush_icache_range) 502_GLOBAL(__flush_icache_range)
503BEGIN_FTR_SECTION 503BEGIN_FTR_SECTION
504 blr /* for 601, do nothing */ 504 blr /* for 601, do nothing */
505END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) 505END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
diff --git a/arch/ppc/kernel/ppc_ksyms.c b/arch/ppc/kernel/ppc_ksyms.c
index 6550de73a855..307077f14936 100644
--- a/arch/ppc/kernel/ppc_ksyms.c
+++ b/arch/ppc/kernel/ppc_ksyms.c
@@ -175,6 +175,7 @@ EXPORT_SYMBOL(pci_bus_to_phys);
175#endif /* CONFIG_PCI */ 175#endif /* CONFIG_PCI */
176 176
177#ifdef CONFIG_NOT_COHERENT_CACHE 177#ifdef CONFIG_NOT_COHERENT_CACHE
178extern void flush_dcache_all(void);
178EXPORT_SYMBOL(flush_dcache_all); 179EXPORT_SYMBOL(flush_dcache_all);
179#endif 180#endif
180 181
diff --git a/arch/ppc/platforms/prep_setup.c b/arch/ppc/platforms/prep_setup.c
index 067d7d53b81e..4415748071dc 100644
--- a/arch/ppc/platforms/prep_setup.c
+++ b/arch/ppc/platforms/prep_setup.c
@@ -61,6 +61,15 @@
61#include <asm/pci-bridge.h> 61#include <asm/pci-bridge.h>
62#include <asm/todc.h> 62#include <asm/todc.h>
63 63
64/* prep registers for L2 */
65#define CACHECRBA 0x80000823 /* Cache configuration register address */
66#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
67#define L2CACHE_512KB 0x00 /* 512KB */
68#define L2CACHE_256KB 0x01 /* 256KB */
69#define L2CACHE_1MB 0x02 /* 1MB */
70#define L2CACHE_NONE 0x03 /* NONE */
71#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
72
64TODC_ALLOC(); 73TODC_ALLOC();
65 74
66unsigned char ucSystemType; 75unsigned char ucSystemType;
diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h
new file mode 100644
index 000000000000..26ce502e76e8
--- /dev/null
+++ b/include/asm-powerpc/cache.h
@@ -0,0 +1,40 @@
1#ifndef _ASM_POWERPC_CACHE_H
2#define _ASM_POWERPC_CACHE_H
3
4#ifdef __KERNEL__
5
6#include <linux/config.h>
7
8/* bytes per L1 cache line */
9#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
10#define L1_CACHE_SHIFT 4
11#define MAX_COPY_PREFETCH 1
12#elif defined(CONFIG_PPC32)
13#define L1_CACHE_SHIFT 5
14#define MAX_COPY_PREFETCH 4
15#else /* CONFIG_PPC64 */
16#define L1_CACHE_SHIFT 7
17#endif
18
19#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
20
21#define SMP_CACHE_BYTES L1_CACHE_BYTES
22#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
23
24#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
25struct ppc64_caches {
26 u32 dsize; /* L1 d-cache size */
27 u32 dline_size; /* L1 d-cache line size */
28 u32 log_dline_size;
29 u32 dlines_per_page;
30 u32 isize; /* L1 i-cache size */
31 u32 iline_size; /* L1 i-cache line size */
32 u32 log_iline_size;
33 u32 ilines_per_page;
34};
35
36extern struct ppc64_caches ppc64_caches;
37#endif /* __powerpc64__ && ! __ASSEMBLY__ */
38
39#endif /* __KERNEL__ */
40#endif /* _ASM_POWERPC_CACHE_H */
diff --git a/include/asm-ppc64/cacheflush.h b/include/asm-powerpc/cacheflush.h
index ffbc08be8e52..8a740c88d93d 100644
--- a/include/asm-ppc64/cacheflush.h
+++ b/include/asm-powerpc/cacheflush.h
@@ -1,13 +1,20 @@
1#ifndef _PPC64_CACHEFLUSH_H 1/*
2#define _PPC64_CACHEFLUSH_H 2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 */
7#ifndef _ASM_POWERPC_CACHEFLUSH_H
8#define _ASM_POWERPC_CACHEFLUSH_H
9
10#ifdef __KERNEL__
3 11
4#include <linux/mm.h> 12#include <linux/mm.h>
5#include <asm/cputable.h> 13#include <asm/cputable.h>
6 14
7/* 15/*
8 * No cache flushing is required when address mappings are 16 * No cache flushing is required when address mappings are changed,
9 * changed, because the caches on PowerPCs are physically 17 * because the caches on PowerPCs are physically addressed.
10 * addressed.
11 */ 18 */
12#define flush_cache_all() do { } while (0) 19#define flush_cache_all() do { } while (0)
13#define flush_cache_mm(mm) do { } while (0) 20#define flush_cache_mm(mm) do { } while (0)
@@ -22,27 +29,40 @@ extern void flush_dcache_page(struct page *page);
22#define flush_dcache_mmap_unlock(mapping) do { } while (0) 29#define flush_dcache_mmap_unlock(mapping) do { } while (0)
23 30
24extern void __flush_icache_range(unsigned long, unsigned long); 31extern void __flush_icache_range(unsigned long, unsigned long);
32static inline void flush_icache_range(unsigned long start, unsigned long stop)
33{
34 if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
35 __flush_icache_range(start, stop);
36}
37
25extern void flush_icache_user_range(struct vm_area_struct *vma, 38extern void flush_icache_user_range(struct vm_area_struct *vma,
26 struct page *page, unsigned long addr, 39 struct page *page, unsigned long addr,
27 int len); 40 int len);
41extern void __flush_dcache_icache(void *page_va);
42extern void flush_dcache_icache_page(struct page *page);
43#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
44extern void __flush_dcache_icache_phys(unsigned long physaddr);
45#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
28 46
29extern void flush_dcache_range(unsigned long start, unsigned long stop); 47extern void flush_dcache_range(unsigned long start, unsigned long stop);
30extern void flush_dcache_phys_range(unsigned long start, unsigned long stop); 48#ifdef CONFIG_PPC32
49extern void clean_dcache_range(unsigned long start, unsigned long stop);
50extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
51#endif /* CONFIG_PPC32 */
52#ifdef CONFIG_PPC64
31extern void flush_inval_dcache_range(unsigned long start, unsigned long stop); 53extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
54extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
55#endif
32 56
33#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 57#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
34do { memcpy(dst, src, len); \ 58 do { \
35 flush_icache_user_range(vma, page, vaddr, len); \ 59 memcpy(dst, src, len); \
36} while (0) 60 flush_icache_user_range(vma, page, vaddr, len); \
61 } while (0)
37#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 62#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
38 memcpy(dst, src, len) 63 memcpy(dst, src, len)
39 64
40extern void __flush_dcache_icache(void *page_va);
41 65
42static inline void flush_icache_range(unsigned long start, unsigned long stop) 66#endif /* __KERNEL__ */
43{
44 if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
45 __flush_icache_range(start, stop);
46}
47 67
48#endif /* _PPC64_CACHEFLUSH_H */ 68#endif /* _ASM_POWERPC_CACHEFLUSH_H */
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 489cf4c99c21..ef121f4f0bab 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -16,7 +16,11 @@
16/* Pickup Book E specific registers. */ 16/* Pickup Book E specific registers. */
17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
18#include <asm/reg_booke.h> 18#include <asm/reg_booke.h>
19#endif 19#endif /* CONFIG_BOOKE || CONFIG_40x */
20
21#ifdef CONFIG_8xx
22#include <asm/reg_8xx.h>
23#endif /* CONFIG_8xx */
20 24
21#define MSR_SF_LG 63 /* Enable 64 bit mode */ 25#define MSR_SF_LG 63 /* Enable 64 bit mode */
22#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ 26#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
diff --git a/include/asm-ppc/cache.h b/include/asm-powerpc/reg_8xx.h
index 7a157d0f4b5f..e8ea346b21d3 100644
--- a/include/asm-ppc/cache.h
+++ b/include/asm-powerpc/reg_8xx.h
@@ -1,49 +1,9 @@
1/* 1/*
2 * include/asm-ppc/cache.h 2 * Contains register definitions common to PowerPC 8xx CPUs. Notice
3 */ 3 */
4#ifdef __KERNEL__ 4#ifndef _ASM_POWERPC_REG_8xx_H
5#ifndef __ARCH_PPC_CACHE_H 5#define _ASM_POWERPC_REG_8xx_H
6#define __ARCH_PPC_CACHE_H
7 6
8#include <linux/config.h>
9
10/* bytes per L1 cache line */
11#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
12#define L1_CACHE_SHIFT 4
13#define MAX_COPY_PREFETCH 1
14#elif defined(CONFIG_PPC64BRIDGE)
15#define L1_CACHE_SHIFT 7
16#define MAX_COPY_PREFETCH 1
17#else
18#define L1_CACHE_SHIFT 5
19#define MAX_COPY_PREFETCH 4
20#endif
21
22#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
23
24#define SMP_CACHE_BYTES L1_CACHE_BYTES
25#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
26
27#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
28#define L1_CACHE_PAGES 8
29
30#ifndef __ASSEMBLY__
31extern void clean_dcache_range(unsigned long start, unsigned long stop);
32extern void flush_dcache_range(unsigned long start, unsigned long stop);
33extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
34extern void flush_dcache_all(void);
35#endif /* __ASSEMBLY__ */
36
37/* prep registers for L2 */
38#define CACHECRBA 0x80000823 /* Cache configuration register address */
39#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
40#define L2CACHE_512KB 0x00 /* 512KB */
41#define L2CACHE_256KB 0x01 /* 256KB */
42#define L2CACHE_1MB 0x02 /* 1MB */
43#define L2CACHE_NONE 0x03 /* NONE */
44#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
45
46#ifdef CONFIG_8xx
47/* Cache control on the MPC8xx is provided through some additional 7/* Cache control on the MPC8xx is provided through some additional
48 * special purpose registers. 8 * special purpose registers.
49 */ 9 */
@@ -78,7 +38,5 @@ extern void flush_dcache_all(void);
78 38
79#define DC_DFWT 0x40000000 /* Data cache is forced write through */ 39#define DC_DFWT 0x40000000 /* Data cache is forced write through */
80#define DC_LES 0x20000000 /* Caches are little endian mode */ 40#define DC_LES 0x20000000 /* Caches are little endian mode */
81#endif /* CONFIG_8xx */
82 41
83#endif 42#endif /* _ASM_POWERPC_REG_8xx_H */
84#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/cacheflush.h b/include/asm-ppc/cacheflush.h
deleted file mode 100644
index 6a243efb3317..000000000000
--- a/include/asm-ppc/cacheflush.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * include/asm-ppc/cacheflush.h
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifdef __KERNEL__
10#ifndef _PPC_CACHEFLUSH_H
11#define _PPC_CACHEFLUSH_H
12
13#include <linux/mm.h>
14
15/*
16 * No cache flushing is required when address mappings are
17 * changed, because the caches on PowerPCs are physically
18 * addressed. -- paulus
19 * Also, when SMP we use the coherency (M) bit of the
20 * BATs and PTEs. -- Cort
21 */
22#define flush_cache_all() do { } while (0)
23#define flush_cache_mm(mm) do { } while (0)
24#define flush_cache_range(vma, a, b) do { } while (0)
25#define flush_cache_page(vma, p, pfn) do { } while (0)
26#define flush_icache_page(vma, page) do { } while (0)
27#define flush_cache_vmap(start, end) do { } while (0)
28#define flush_cache_vunmap(start, end) do { } while (0)
29
30extern void flush_dcache_page(struct page *page);
31#define flush_dcache_mmap_lock(mapping) do { } while (0)
32#define flush_dcache_mmap_unlock(mapping) do { } while (0)
33
34extern void flush_icache_range(unsigned long, unsigned long);
35extern void flush_icache_user_range(struct vm_area_struct *vma,
36 struct page *page, unsigned long addr, int len);
37
38#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
39do { memcpy(dst, src, len); \
40 flush_icache_user_range(vma, page, vaddr, len); \
41} while (0)
42#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
43 memcpy(dst, src, len)
44
45extern void __flush_dcache_icache(void *page_va);
46extern void __flush_dcache_icache_phys(unsigned long physaddr);
47extern void flush_dcache_icache_page(struct page *page);
48#endif /* _PPC_CACHEFLUSH_H */
49#endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/cache.h b/include/asm-ppc64/cache.h
deleted file mode 100644
index 92140a7efbd1..000000000000
--- a/include/asm-ppc64/cache.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 */
7#ifndef __ARCH_PPC64_CACHE_H
8#define __ARCH_PPC64_CACHE_H
9
10#include <asm/types.h>
11
12/* bytes per L1 cache line */
13#define L1_CACHE_SHIFT 7
14#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
15
16#define SMP_CACHE_BYTES L1_CACHE_BYTES
17#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
18
19#ifndef __ASSEMBLY__
20
21struct ppc64_caches {
22 u32 dsize; /* L1 d-cache size */
23 u32 dline_size; /* L1 d-cache line size */
24 u32 log_dline_size;
25 u32 dlines_per_page;
26 u32 isize; /* L1 i-cache size */
27 u32 iline_size; /* L1 i-cache line size */
28 u32 log_iline_size;
29 u32 ilines_per_page;
30};
31
32extern struct ppc64_caches ppc64_caches;
33
34#endif
35
36#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-05 14:20:24 -0500