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-rw-r--r--arch/arm/plat-mxc/irq.c67
-rw-r--r--include/asm-arm/arch-mxc/irqs.h13
-rw-r--r--include/asm-arm/arch-mxc/mx31.h2
-rw-r--r--include/asm-arm/arch-mxc/mxc.h38
4 files changed, 53 insertions, 67 deletions
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 88f0cfababda..1fbe01da6925 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -1,24 +1,59 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
3 */ 18 */
4 19
5/* 20#include <linux/irq.h>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <asm/hardware.h>
17#include <asm/io.h> 21#include <asm/io.h>
18#include <asm/irq.h>
19#include <asm/mach/irq.h>
20#include <asm/arch/common.h> 22#include <asm/arch/common.h>
21 23
24#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
25#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
26#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
27#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
28#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
29#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
30#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
31#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
32#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
33#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
34#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
35#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
36#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
37#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
38#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
39#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
40#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
41#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
42#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
43#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
44#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
45#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
46#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
47#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
48#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
49#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
50#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
51
52#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
53#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
54#define IIM_PROD_REV_SH 3
55#define IIM_PROD_REV_LEN 5
56
22/* Disable interrupt number "irq" in the AVIC */ 57/* Disable interrupt number "irq" in the AVIC */
23static void mxc_mask_irq(unsigned int irq) 58static void mxc_mask_irq(unsigned int irq)
24{ 59{
@@ -32,7 +67,7 @@ static void mxc_unmask_irq(unsigned int irq)
32} 67}
33 68
34static struct irq_chip mxc_avic_chip = { 69static struct irq_chip mxc_avic_chip = {
35 .mask_ack = mxc_mask_irq, 70 .ack = mxc_mask_irq,
36 .mask = mxc_mask_irq, 71 .mask = mxc_mask_irq,
37 .unmask = mxc_unmask_irq, 72 .unmask = mxc_unmask_irq,
38}; 73};
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index b2c5205e1962..f416130718cf 100644
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -13,17 +13,4 @@
13 13
14#include <asm/hardware.h> 14#include <asm/hardware.h>
15 15
16#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
17
18#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
19#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
20
21/* Number of normal interrupts */
22#define NR_IRQS (MXC_MAX_INT_LINES + \
23 MXC_MAX_GPIO_LINES + \
24 MXC_MAX_VIRTUAL_INTS)
25
26/* Number of fast interrupts */
27#define NR_FIQS MXC_MAX_INTS
28
29#endif /* __ASM_ARCH_MXC_IRQS_H__ */ 16#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
index 98e6a4cd1ea9..a7373e4a56cb 100644
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -320,6 +320,8 @@
320#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) 320#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
321#define MXC_MAX_VIRTUAL_INTS 16 321#define MXC_MAX_VIRTUAL_INTS 16
322 322
323#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
324
323/*! 325/*!
324 * Number of GPIO port as defined in the IC Spec 326 * Number of GPIO port as defined in the IC Spec
325 */ 327 */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 1df4e2f24920..3e1c4ded18e2 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -29,42 +29,4 @@
29# define cpu_is_mx31() (0) 29# define cpu_is_mx31() (0)
30#endif 30#endif
31 31
32/*
33 *****************************************
34 * AVIC Registers *
35 *****************************************
36 */
37#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
38#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
39#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
40#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
41#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
42#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
43#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
44#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
45#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
46#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
47#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
48#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
49#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
50#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
51#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
52#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
53#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
54#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
55#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
56#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
57#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
58#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
59#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
60#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
61#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
62#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
63#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
64
65#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
66#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
67#define IIM_PROD_REV_SH 3
68#define IIM_PROD_REV_LEN 5
69
70#endif /* __ASM_ARCH_MXC_H__ */ 32#endif /* __ASM_ARCH_MXC_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-20 12:01:40 -0500