aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/net/r8169.c189
-rw-r--r--drivers/net/skge.c75
-rw-r--r--drivers/net/skge.h1
-rw-r--r--drivers/net/sky2.c173
-rw-r--r--drivers/net/sky2.h83
5 files changed, 368 insertions, 153 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 6e1018448eea..8cc0d0bbdf50 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -287,6 +287,20 @@ enum RTL8169_register_content {
287 TxInterFrameGapShift = 24, 287 TxInterFrameGapShift = 24,
288 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 288 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
289 289
290 /* Config1 register p.24 */
291 PMEnable = (1 << 0), /* Power Management Enable */
292
293 /* Config3 register p.25 */
294 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
295 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
296
297 /* Config5 register p.27 */
298 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
299 MWF = (1 << 5), /* Accept Multicast wakeup frame */
300 UWF = (1 << 4), /* Accept Unicast wakeup frame */
301 LanWake = (1 << 1), /* LanWake enable/disable */
302 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
303
290 /* TBICSR p.28 */ 304 /* TBICSR p.28 */
291 TBIReset = 0x80000000, 305 TBIReset = 0x80000000,
292 TBILoopback = 0x40000000, 306 TBILoopback = 0x40000000,
@@ -433,6 +447,7 @@ struct rtl8169_private {
433 unsigned int (*phy_reset_pending)(void __iomem *); 447 unsigned int (*phy_reset_pending)(void __iomem *);
434 unsigned int (*link_ok)(void __iomem *); 448 unsigned int (*link_ok)(void __iomem *);
435 struct work_struct task; 449 struct work_struct task;
450 unsigned wol_enabled : 1;
436}; 451};
437 452
438MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 453MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
@@ -607,6 +622,80 @@ static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
607 *duplex = p->duplex; 622 *duplex = p->duplex;
608} 623}
609 624
625static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
626{
627 struct rtl8169_private *tp = netdev_priv(dev);
628 void __iomem *ioaddr = tp->mmio_addr;
629 u8 options;
630
631 wol->wolopts = 0;
632
633#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
634 wol->supported = WAKE_ANY;
635
636 spin_lock_irq(&tp->lock);
637
638 options = RTL_R8(Config1);
639 if (!(options & PMEnable))
640 goto out_unlock;
641
642 options = RTL_R8(Config3);
643 if (options & LinkUp)
644 wol->wolopts |= WAKE_PHY;
645 if (options & MagicPacket)
646 wol->wolopts |= WAKE_MAGIC;
647
648 options = RTL_R8(Config5);
649 if (options & UWF)
650 wol->wolopts |= WAKE_UCAST;
651 if (options & BWF)
652 wol->wolopts |= WAKE_BCAST;
653 if (options & MWF)
654 wol->wolopts |= WAKE_MCAST;
655
656out_unlock:
657 spin_unlock_irq(&tp->lock);
658}
659
660static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
661{
662 struct rtl8169_private *tp = netdev_priv(dev);
663 void __iomem *ioaddr = tp->mmio_addr;
664 int i;
665 static struct {
666 u32 opt;
667 u16 reg;
668 u8 mask;
669 } cfg[] = {
670 { WAKE_ANY, Config1, PMEnable },
671 { WAKE_PHY, Config3, LinkUp },
672 { WAKE_MAGIC, Config3, MagicPacket },
673 { WAKE_UCAST, Config5, UWF },
674 { WAKE_BCAST, Config5, BWF },
675 { WAKE_MCAST, Config5, MWF },
676 { WAKE_ANY, Config5, LanWake }
677 };
678
679 spin_lock_irq(&tp->lock);
680
681 RTL_W8(Cfg9346, Cfg9346_Unlock);
682
683 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
684 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
685 if (wol->wolopts & cfg[i].opt)
686 options |= cfg[i].mask;
687 RTL_W8(cfg[i].reg, options);
688 }
689
690 RTL_W8(Cfg9346, Cfg9346_Lock);
691
692 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
693
694 spin_unlock_irq(&tp->lock);
695
696 return 0;
697}
698
610static void rtl8169_get_drvinfo(struct net_device *dev, 699static void rtl8169_get_drvinfo(struct net_device *dev,
611 struct ethtool_drvinfo *info) 700 struct ethtool_drvinfo *info)
612{ 701{
@@ -1025,6 +1114,8 @@ static struct ethtool_ops rtl8169_ethtool_ops = {
1025 .get_tso = ethtool_op_get_tso, 1114 .get_tso = ethtool_op_get_tso,
1026 .set_tso = ethtool_op_set_tso, 1115 .set_tso = ethtool_op_set_tso,
1027 .get_regs = rtl8169_get_regs, 1116 .get_regs = rtl8169_get_regs,
1117 .get_wol = rtl8169_get_wol,
1118 .set_wol = rtl8169_set_wol,
1028 .get_strings = rtl8169_get_strings, 1119 .get_strings = rtl8169_get_strings,
1029 .get_stats_count = rtl8169_get_stats_count, 1120 .get_stats_count = rtl8169_get_stats_count,
1030 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1121 .get_ethtool_stats = rtl8169_get_ethtool_stats,
@@ -1442,6 +1533,11 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1442 } 1533 }
1443 tp->chipset = i; 1534 tp->chipset = i;
1444 1535
1536 RTL_W8(Cfg9346, Cfg9346_Unlock);
1537 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1538 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1539 RTL_W8(Cfg9346, Cfg9346_Lock);
1540
1445 *ioaddr_out = ioaddr; 1541 *ioaddr_out = ioaddr;
1446 *dev_out = dev; 1542 *dev_out = dev;
1447out: 1543out:
@@ -1612,49 +1708,6 @@ rtl8169_remove_one(struct pci_dev *pdev)
1612 pci_set_drvdata(pdev, NULL); 1708 pci_set_drvdata(pdev, NULL);
1613} 1709}
1614 1710
1615#ifdef CONFIG_PM
1616
1617static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
1618{
1619 struct net_device *dev = pci_get_drvdata(pdev);
1620 struct rtl8169_private *tp = netdev_priv(dev);
1621 void __iomem *ioaddr = tp->mmio_addr;
1622 unsigned long flags;
1623
1624 if (!netif_running(dev))
1625 return 0;
1626
1627 netif_device_detach(dev);
1628 netif_stop_queue(dev);
1629 spin_lock_irqsave(&tp->lock, flags);
1630
1631 /* Disable interrupts, stop Rx and Tx */
1632 RTL_W16(IntrMask, 0);
1633 RTL_W8(ChipCmd, 0);
1634
1635 /* Update the error counts. */
1636 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1637 RTL_W32(RxMissed, 0);
1638 spin_unlock_irqrestore(&tp->lock, flags);
1639
1640 return 0;
1641}
1642
1643static int rtl8169_resume(struct pci_dev *pdev)
1644{
1645 struct net_device *dev = pci_get_drvdata(pdev);
1646
1647 if (!netif_running(dev))
1648 return 0;
1649
1650 netif_device_attach(dev);
1651 rtl8169_hw_start(dev);
1652
1653 return 0;
1654}
1655
1656#endif /* CONFIG_PM */
1657
1658static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, 1711static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1659 struct net_device *dev) 1712 struct net_device *dev)
1660{ 1713{
@@ -2700,6 +2753,56 @@ static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2700 return &tp->stats; 2753 return &tp->stats;
2701} 2754}
2702 2755
2756#ifdef CONFIG_PM
2757
2758static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2759{
2760 struct net_device *dev = pci_get_drvdata(pdev);
2761 struct rtl8169_private *tp = netdev_priv(dev);
2762 void __iomem *ioaddr = tp->mmio_addr;
2763
2764 if (!netif_running(dev))
2765 goto out;
2766
2767 netif_device_detach(dev);
2768 netif_stop_queue(dev);
2769
2770 spin_lock_irq(&tp->lock);
2771
2772 rtl8169_asic_down(ioaddr);
2773
2774 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2775 RTL_W32(RxMissed, 0);
2776
2777 spin_unlock_irq(&tp->lock);
2778
2779 pci_save_state(pdev);
2780 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
2781 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2782out:
2783 return 0;
2784}
2785
2786static int rtl8169_resume(struct pci_dev *pdev)
2787{
2788 struct net_device *dev = pci_get_drvdata(pdev);
2789
2790 if (!netif_running(dev))
2791 goto out;
2792
2793 netif_device_attach(dev);
2794
2795 pci_set_power_state(pdev, PCI_D0);
2796 pci_restore_state(pdev);
2797 pci_enable_wake(pdev, PCI_D0, 0);
2798
2799 rtl8169_schedule_work(dev, rtl8169_reset_task);
2800out:
2801 return 0;
2802}
2803
2804#endif /* CONFIG_PM */
2805
2703static struct pci_driver rtl8169_pci_driver = { 2806static struct pci_driver rtl8169_pci_driver = {
2704 .name = MODULENAME, 2807 .name = MODULENAME,
2705 .id_table = rtl8169_pci_tbl, 2808 .id_table = rtl8169_pci_tbl,
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 67fb19b8fde9..25e028b7ce48 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -879,13 +879,12 @@ static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
879 int i; 879 int i;
880 880
881 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 881 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
882 xm_read16(hw, port, XM_PHY_DATA); 882 *val = xm_read16(hw, port, XM_PHY_DATA);
883 883
884 /* Need to wait for external PHY */
885 for (i = 0; i < PHY_RETRIES; i++) { 884 for (i = 0; i < PHY_RETRIES; i++) {
886 udelay(1);
887 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) 885 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
888 goto ready; 886 goto ready;
887 udelay(1);
889 } 888 }
890 889
891 return -ETIMEDOUT; 890 return -ETIMEDOUT;
@@ -918,7 +917,12 @@ static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
918 917
919 ready: 918 ready:
920 xm_write16(hw, port, XM_PHY_DATA, val); 919 xm_write16(hw, port, XM_PHY_DATA, val);
921 return 0; 920 for (i = 0; i < PHY_RETRIES; i++) {
921 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
922 return 0;
923 udelay(1);
924 }
925 return -ETIMEDOUT;
922} 926}
923 927
924static void genesis_init(struct skge_hw *hw) 928static void genesis_init(struct skge_hw *hw)
@@ -1168,13 +1172,17 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1168 u32 r; 1172 u32 r;
1169 const u8 zero[6] = { 0 }; 1173 const u8 zero[6] = { 0 };
1170 1174
1171 /* Clear MIB counters */ 1175 for (i = 0; i < 10; i++) {
1172 xm_write16(hw, port, XM_STAT_CMD, 1176 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1173 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 1177 MFF_SET_MAC_RST);
1174 /* Clear two times according to Errata #3 */ 1178 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1175 xm_write16(hw, port, XM_STAT_CMD, 1179 goto reset_ok;
1176 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 1180 udelay(1);
1181 }
1182
1183 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1177 1184
1185 reset_ok:
1178 /* Unreset the XMAC. */ 1186 /* Unreset the XMAC. */
1179 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); 1187 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1180 1188
@@ -1191,7 +1199,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1191 r |= GP_DIR_2|GP_IO_2; 1199 r |= GP_DIR_2|GP_IO_2;
1192 1200
1193 skge_write32(hw, B2_GP_IO, r); 1201 skge_write32(hw, B2_GP_IO, r);
1194 skge_read32(hw, B2_GP_IO); 1202
1195 1203
1196 /* Enable GMII interface */ 1204 /* Enable GMII interface */
1197 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); 1205 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
@@ -1205,6 +1213,13 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1205 for (i = 1; i < 16; i++) 1213 for (i = 1; i < 16; i++)
1206 xm_outaddr(hw, port, XM_EXM(i), zero); 1214 xm_outaddr(hw, port, XM_EXM(i), zero);
1207 1215
1216 /* Clear MIB counters */
1217 xm_write16(hw, port, XM_STAT_CMD,
1218 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1219 /* Clear two times according to Errata #3 */
1220 xm_write16(hw, port, XM_STAT_CMD,
1221 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1222
1208 /* configure Rx High Water Mark (XM_RX_HI_WM) */ 1223 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1209 xm_write16(hw, port, XM_RX_HI_WM, 1450); 1224 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1210 1225
@@ -2170,8 +2185,10 @@ static int skge_up(struct net_device *dev)
2170 skge->tx_avail = skge->tx_ring.count - 1; 2185 skge->tx_avail = skge->tx_ring.count - 1;
2171 2186
2172 /* Enable IRQ from port */ 2187 /* Enable IRQ from port */
2188 spin_lock_irq(&hw->hw_lock);
2173 hw->intr_mask |= portirqmask[port]; 2189 hw->intr_mask |= portirqmask[port];
2174 skge_write32(hw, B0_IMSK, hw->intr_mask); 2190 skge_write32(hw, B0_IMSK, hw->intr_mask);
2191 spin_unlock_irq(&hw->hw_lock);
2175 2192
2176 /* Initialize MAC */ 2193 /* Initialize MAC */
2177 spin_lock_bh(&hw->phy_lock); 2194 spin_lock_bh(&hw->phy_lock);
@@ -2229,8 +2246,10 @@ static int skge_down(struct net_device *dev)
2229 else 2246 else
2230 yukon_stop(skge); 2247 yukon_stop(skge);
2231 2248
2249 spin_lock_irq(&hw->hw_lock);
2232 hw->intr_mask &= ~portirqmask[skge->port]; 2250 hw->intr_mask &= ~portirqmask[skge->port];
2233 skge_write32(hw, B0_IMSK, hw->intr_mask); 2251 skge_write32(hw, B0_IMSK, hw->intr_mask);
2252 spin_unlock_irq(&hw->hw_lock);
2234 2253
2235 /* Stop transmitter */ 2254 /* Stop transmitter */
2236 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); 2255 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
@@ -2678,8 +2697,7 @@ static int skge_poll(struct net_device *dev, int *budget)
2678 2697
2679 /* restart receiver */ 2698 /* restart receiver */
2680 wmb(); 2699 wmb();
2681 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), 2700 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
2682 CSR_START | CSR_IRQ_CL_F);
2683 2701
2684 *budget -= work_done; 2702 *budget -= work_done;
2685 dev->quota -= work_done; 2703 dev->quota -= work_done;
@@ -2687,10 +2705,11 @@ static int skge_poll(struct net_device *dev, int *budget)
2687 if (work_done >= to_do) 2705 if (work_done >= to_do)
2688 return 1; /* not done */ 2706 return 1; /* not done */
2689 2707
2690 netif_rx_complete(dev); 2708 spin_lock_irq(&hw->hw_lock);
2691 hw->intr_mask |= portirqmask[skge->port]; 2709 __netif_rx_complete(dev);
2692 skge_write32(hw, B0_IMSK, hw->intr_mask); 2710 hw->intr_mask |= portirqmask[skge->port];
2693 skge_read32(hw, B0_IMSK); 2711 skge_write32(hw, B0_IMSK, hw->intr_mask);
2712 spin_unlock_irq(&hw->hw_lock);
2694 2713
2695 return 0; 2714 return 0;
2696} 2715}
@@ -2850,18 +2869,10 @@ static void skge_extirq(unsigned long data)
2850 } 2869 }
2851 spin_unlock(&hw->phy_lock); 2870 spin_unlock(&hw->phy_lock);
2852 2871
2853 local_irq_disable(); 2872 spin_lock_irq(&hw->hw_lock);
2854 hw->intr_mask |= IS_EXT_REG; 2873 hw->intr_mask |= IS_EXT_REG;
2855 skge_write32(hw, B0_IMSK, hw->intr_mask); 2874 skge_write32(hw, B0_IMSK, hw->intr_mask);
2856 local_irq_enable(); 2875 spin_unlock_irq(&hw->hw_lock);
2857}
2858
2859static inline void skge_wakeup(struct net_device *dev)
2860{
2861 struct skge_port *skge = netdev_priv(dev);
2862
2863 prefetch(skge->rx_ring.to_clean);
2864 netif_rx_schedule(dev);
2865} 2876}
2866 2877
2867static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs) 2878static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
@@ -2872,15 +2883,17 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2872 if (status == 0 || status == ~0) /* hotplug or shared irq */ 2883 if (status == 0 || status == ~0) /* hotplug or shared irq */
2873 return IRQ_NONE; 2884 return IRQ_NONE;
2874 2885
2875 status &= hw->intr_mask; 2886 spin_lock(&hw->hw_lock);
2876 if (status & IS_R1_F) { 2887 if (status & IS_R1_F) {
2888 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2877 hw->intr_mask &= ~IS_R1_F; 2889 hw->intr_mask &= ~IS_R1_F;
2878 skge_wakeup(hw->dev[0]); 2890 netif_rx_schedule(hw->dev[0]);
2879 } 2891 }
2880 2892
2881 if (status & IS_R2_F) { 2893 if (status & IS_R2_F) {
2894 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2882 hw->intr_mask &= ~IS_R2_F; 2895 hw->intr_mask &= ~IS_R2_F;
2883 skge_wakeup(hw->dev[1]); 2896 netif_rx_schedule(hw->dev[1]);
2884 } 2897 }
2885 2898
2886 if (status & IS_XA1_F) 2899 if (status & IS_XA1_F)
@@ -2922,6 +2935,7 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2922 } 2935 }
2923 2936
2924 skge_write32(hw, B0_IMSK, hw->intr_mask); 2937 skge_write32(hw, B0_IMSK, hw->intr_mask);
2938 spin_unlock(&hw->hw_lock);
2925 2939
2926 return IRQ_HANDLED; 2940 return IRQ_HANDLED;
2927} 2941}
@@ -3290,6 +3304,7 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3290 3304
3291 hw->pdev = pdev; 3305 hw->pdev = pdev;
3292 spin_lock_init(&hw->phy_lock); 3306 spin_lock_init(&hw->phy_lock);
3307 spin_lock_init(&hw->hw_lock);
3293 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw); 3308 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3294 3309
3295 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 3310 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index 2efdacc290e5..941f12a333b6 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -2402,6 +2402,7 @@ struct skge_hw {
2402 2402
2403 struct tasklet_struct ext_tasklet; 2403 struct tasklet_struct ext_tasklet;
2404 spinlock_t phy_lock; 2404 spinlock_t phy_lock;
2405 spinlock_t hw_lock;
2405}; 2406};
2406 2407
2407enum { 2408enum {
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index bfeba5b9cd7a..ca8160d68229 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -195,11 +195,11 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
195 pr_debug("sky2_set_power_state %d\n", state); 195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
197 197
198 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control); 198 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
199 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) && 199 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
200 (power_control & PCI_PM_CAP_PME_D3cold); 200 (power_control & PCI_PM_CAP_PME_D3cold);
201 201
202 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control); 202 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
203 203
204 power_control |= PCI_PM_CTRL_PME_STATUS; 204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK); 205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
@@ -223,7 +223,7 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224 224
225 /* Turn off phy power saving */ 225 /* Turn off phy power saving */
226 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1); 226 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
228 228
229 /* looks like this XL is back asswards .. */ 229 /* looks like this XL is back asswards .. */
@@ -232,18 +232,28 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
232 if (hw->ports > 1) 232 if (hw->ports > 1)
233 reg1 |= PCI_Y2_PHY2_COMA; 233 reg1 |= PCI_Y2_PHY2_COMA;
234 } 234 }
235 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); 235
236 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
237 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
238 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
239 reg1 &= P_ASPM_CONTROL_MSK;
240 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
241 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
242 }
243
244 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
245
236 break; 246 break;
237 247
238 case PCI_D3hot: 248 case PCI_D3hot:
239 case PCI_D3cold: 249 case PCI_D3cold:
240 /* Turn on phy power saving */ 250 /* Turn on phy power saving */
241 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1); 251 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
242 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
243 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 253 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
244 else 254 else
245 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 255 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); 256 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
247 257
248 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 258 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
249 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 259 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
@@ -265,7 +275,7 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
265 ret = -1; 275 ret = -1;
266 } 276 }
267 277
268 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control); 278 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
269 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 279 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
270 return ret; 280 return ret;
271} 281}
@@ -463,16 +473,31 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
463 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 473 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
464 } 474 }
465 475
466 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 476 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
477 /* apply fixes in PHY AFE */
478 gm_phy_write(hw, port, 22, 255);
479 /* increase differential signal amplitude in 10BASE-T */
480 gm_phy_write(hw, port, 24, 0xaa99);
481 gm_phy_write(hw, port, 23, 0x2011);
467 482
468 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { 483 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
469 /* turn on 100 Mbps LED (LED_LINK100) */ 484 gm_phy_write(hw, port, 24, 0xa204);
470 ledover |= PHY_M_LED_MO_100(MO_LED_ON); 485 gm_phy_write(hw, port, 23, 0x2002);
471 }
472 486
473 if (ledover) 487 /* set page register to 0 */
474 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 488 gm_phy_write(hw, port, 22, 0);
489 } else {
490 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
475 491
492 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
493 /* turn on 100 Mbps LED (LED_LINK100) */
494 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
495 }
496
497 if (ledover)
498 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
499
500 }
476 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 501 /* Enable phy interrupt on auto-negotiation complete (or link up) */
477 if (sky2->autoneg == AUTONEG_ENABLE) 502 if (sky2->autoneg == AUTONEG_ENABLE)
478 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 503 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
@@ -953,6 +978,12 @@ static int sky2_rx_start(struct sky2_port *sky2)
953 978
954 sky2->rx_put = sky2->rx_next = 0; 979 sky2->rx_put = sky2->rx_next = 0;
955 sky2_qset(hw, rxq); 980 sky2_qset(hw, rxq);
981
982 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
983 /* MAC Rx RAM Read is controlled by hardware */
984 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
985 }
986
956 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 987 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
957 988
958 rx_set_checksum(sky2); 989 rx_set_checksum(sky2);
@@ -1035,9 +1066,10 @@ static int sky2_up(struct net_device *dev)
1035 RB_RST_SET); 1066 RB_RST_SET);
1036 1067
1037 sky2_qset(hw, txqaddr[port]); 1068 sky2_qset(hw, txqaddr[port]);
1038 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1039 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1040 1069
1070 /* Set almost empty threshold */
1071 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1072 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1041 1073
1042 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 1074 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1043 TX_RING_SIZE - 1); 1075 TX_RING_SIZE - 1);
@@ -1047,8 +1079,10 @@ static int sky2_up(struct net_device *dev)
1047 goto err_out; 1079 goto err_out;
1048 1080
1049 /* Enable interrupts from phy/mac for port */ 1081 /* Enable interrupts from phy/mac for port */
1082 spin_lock_irq(&hw->hw_lock);
1050 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; 1083 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1051 sky2_write32(hw, B0_IMSK, hw->intr_mask); 1084 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1085 spin_unlock_irq(&hw->hw_lock);
1052 return 0; 1086 return 0;
1053 1087
1054err_out: 1088err_out:
@@ -1348,10 +1382,10 @@ static int sky2_down(struct net_device *dev)
1348 netif_stop_queue(dev); 1382 netif_stop_queue(dev);
1349 1383
1350 /* Disable port IRQ */ 1384 /* Disable port IRQ */
1351 local_irq_disable(); 1385 spin_lock_irq(&hw->hw_lock);
1352 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); 1386 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1353 sky2_write32(hw, B0_IMSK, hw->intr_mask); 1387 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1354 local_irq_enable(); 1388 spin_unlock_irq(&hw->hw_lock);
1355 1389
1356 flush_scheduled_work(); 1390 flush_scheduled_work();
1357 1391
@@ -1633,10 +1667,10 @@ static void sky2_phy_task(void *arg)
1633out: 1667out:
1634 up(&sky2->phy_sema); 1668 up(&sky2->phy_sema);
1635 1669
1636 local_irq_disable(); 1670 spin_lock_irq(&hw->hw_lock);
1637 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2; 1671 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1638 sky2_write32(hw, B0_IMSK, hw->intr_mask); 1672 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1639 local_irq_enable(); 1673 spin_unlock_irq(&hw->hw_lock);
1640} 1674}
1641 1675
1642 1676
@@ -1863,6 +1897,17 @@ static int sky2_poll(struct net_device *dev0, int *budget)
1863 1897
1864 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 1898 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1865 1899
1900 /*
1901 * Kick the STAT_LEV_TIMER_CTRL timer.
1902 * This fixes my hangs on Yukon-EC (0xb6) rev 1.
1903 * The if clause is there to start the timer only if it has been
1904 * configured correctly and not been disabled via ethtool.
1905 */
1906 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) {
1907 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
1908 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
1909 }
1910
1866 hwidx = sky2_read16(hw, STAT_PUT_IDX); 1911 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1867 BUG_ON(hwidx >= STATUS_RING_SIZE); 1912 BUG_ON(hwidx >= STATUS_RING_SIZE);
1868 rmb(); 1913 rmb();
@@ -1945,16 +1990,19 @@ exit_loop:
1945 sky2_tx_check(hw, 0, tx_done[0]); 1990 sky2_tx_check(hw, 0, tx_done[0]);
1946 sky2_tx_check(hw, 1, tx_done[1]); 1991 sky2_tx_check(hw, 1, tx_done[1]);
1947 1992
1993 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
1994 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1995 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1996 }
1997
1948 if (likely(work_done < to_do)) { 1998 if (likely(work_done < to_do)) {
1949 /* need to restart TX timer */ 1999 spin_lock_irq(&hw->hw_lock);
1950 if (is_ec_a1(hw)) { 2000 __netif_rx_complete(dev0);
1951 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1952 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1953 }
1954 2001
1955 netif_rx_complete(dev0);
1956 hw->intr_mask |= Y2_IS_STAT_BMU; 2002 hw->intr_mask |= Y2_IS_STAT_BMU;
1957 sky2_write32(hw, B0_IMSK, hw->intr_mask); 2003 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2004 spin_unlock_irq(&hw->hw_lock);
2005
1958 return 0; 2006 return 0;
1959 } else { 2007 } else {
1960 *budget -= work_done; 2008 *budget -= work_done;
@@ -2017,13 +2065,13 @@ static void sky2_hw_intr(struct sky2_hw *hw)
2017 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 2065 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2018 u16 pci_err; 2066 u16 pci_err;
2019 2067
2020 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err); 2068 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2021 if (net_ratelimit()) 2069 if (net_ratelimit())
2022 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", 2070 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2023 pci_name(hw->pdev), pci_err); 2071 pci_name(hw->pdev), pci_err);
2024 2072
2025 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2073 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2026 pci_write_config_word(hw->pdev, PCI_STATUS, 2074 sky2_pci_write16(hw, PCI_STATUS,
2027 pci_err | PCI_STATUS_ERROR_BITS); 2075 pci_err | PCI_STATUS_ERROR_BITS);
2028 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2076 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2029 } 2077 }
@@ -2032,7 +2080,7 @@ static void sky2_hw_intr(struct sky2_hw *hw)
2032 /* PCI-Express uncorrectable Error occurred */ 2080 /* PCI-Express uncorrectable Error occurred */
2033 u32 pex_err; 2081 u32 pex_err;
2034 2082
2035 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err); 2083 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2036 2084
2037 if (net_ratelimit()) 2085 if (net_ratelimit())
2038 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", 2086 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
@@ -2040,7 +2088,7 @@ static void sky2_hw_intr(struct sky2_hw *hw)
2040 2088
2041 /* clear the interrupt */ 2089 /* clear the interrupt */
2042 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2090 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2043 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, 2091 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2044 0xffffffffUL); 2092 0xffffffffUL);
2045 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2093 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2046 2094
@@ -2086,6 +2134,7 @@ static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2086 2134
2087 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); 2135 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2088 sky2_write32(hw, B0_IMSK, hw->intr_mask); 2136 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2137
2089 schedule_work(&sky2->phy_task); 2138 schedule_work(&sky2->phy_task);
2090} 2139}
2091 2140
@@ -2099,6 +2148,7 @@ static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2099 if (status == 0 || status == ~0) 2148 if (status == 0 || status == ~0)
2100 return IRQ_NONE; 2149 return IRQ_NONE;
2101 2150
2151 spin_lock(&hw->hw_lock);
2102 if (status & Y2_IS_HW_ERR) 2152 if (status & Y2_IS_HW_ERR)
2103 sky2_hw_intr(hw); 2153 sky2_hw_intr(hw);
2104 2154
@@ -2127,7 +2177,7 @@ static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2127 2177
2128 sky2_write32(hw, B0_Y2_SP_ICR, 2); 2178 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2129 2179
2130 sky2_read32(hw, B0_IMSK); 2180 spin_unlock(&hw->hw_lock);
2131 2181
2132 return IRQ_HANDLED; 2182 return IRQ_HANDLED;
2133} 2183}
@@ -2170,7 +2220,7 @@ static int sky2_reset(struct sky2_hw *hw)
2170{ 2220{
2171 u16 status; 2221 u16 status;
2172 u8 t8, pmd_type; 2222 u8 t8, pmd_type;
2173 int i, err; 2223 int i;
2174 2224
2175 sky2_write8(hw, B0_CTST, CS_RST_CLR); 2225 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2176 2226
@@ -2192,25 +2242,18 @@ static int sky2_reset(struct sky2_hw *hw)
2192 sky2_write8(hw, B0_CTST, CS_RST_CLR); 2242 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2193 2243
2194 /* clear PCI errors, if any */ 2244 /* clear PCI errors, if any */
2195 err = pci_read_config_word(hw->pdev, PCI_STATUS, &status); 2245 status = sky2_pci_read16(hw, PCI_STATUS);
2196 if (err)
2197 goto pci_err;
2198 2246
2199 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2247 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2200 err = pci_write_config_word(hw->pdev, PCI_STATUS, 2248 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2201 status | PCI_STATUS_ERROR_BITS); 2249
2202 if (err)
2203 goto pci_err;
2204 2250
2205 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 2251 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2206 2252
2207 /* clear any PEX errors */ 2253 /* clear any PEX errors */
2208 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) { 2254 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2209 err = pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, 2255 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2210 0xffffffffUL); 2256
2211 if (err)
2212 goto pci_err;
2213 }
2214 2257
2215 pmd_type = sky2_read8(hw, B2_PMD_TYP); 2258 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2216 hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); 2259 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
@@ -2309,8 +2352,7 @@ static int sky2_reset(struct sky2_hw *hw)
2309 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 2352 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2310 2353
2311 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 2354 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2312 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); 2355 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));
2313 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2314 } 2356 }
2315 2357
2316 /* enable status unit */ 2358 /* enable status unit */
@@ -2321,14 +2363,6 @@ static int sky2_reset(struct sky2_hw *hw)
2321 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 2363 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2322 2364
2323 return 0; 2365 return 0;
2324
2325pci_err:
2326 /* This is to catch a BIOS bug workaround where
2327 * mmconfig table doesn't have other buses.
2328 */
2329 printk(KERN_ERR PFX "%s: can't access PCI config space\n",
2330 pci_name(hw->pdev));
2331 return err;
2332} 2366}
2333 2367
2334static u32 sky2_supported_modes(const struct sky2_hw *hw) 2368static u32 sky2_supported_modes(const struct sky2_hw *hw)
@@ -2852,11 +2886,11 @@ static int sky2_set_coalesce(struct net_device *dev,
2852 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax)) 2886 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2853 return -EINVAL; 2887 return -EINVAL;
2854 2888
2855 if (ecmd->tx_max_coalesced_frames > 0xffff) 2889 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2856 return -EINVAL; 2890 return -EINVAL;
2857 if (ecmd->rx_max_coalesced_frames > 0xff) 2891 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2858 return -EINVAL; 2892 return -EINVAL;
2859 if (ecmd->rx_max_coalesced_frames_irq > 0xff) 2893 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2860 return -EINVAL; 2894 return -EINVAL;
2861 2895
2862 if (ecmd->tx_coalesce_usecs == 0) 2896 if (ecmd->tx_coalesce_usecs == 0)
@@ -3198,17 +3232,6 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
3198 } 3232 }
3199 } 3233 }
3200 3234
3201#ifdef __BIG_ENDIAN
3202 /* byte swap descriptors in hardware */
3203 {
3204 u32 reg;
3205
3206 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3207 reg |= PCI_REV_DESC;
3208 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3209 }
3210#endif
3211
3212 err = -ENOMEM; 3235 err = -ENOMEM;
3213 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 3236 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3214 if (!hw) { 3237 if (!hw) {
@@ -3226,6 +3249,18 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
3226 goto err_out_free_hw; 3249 goto err_out_free_hw;
3227 } 3250 }
3228 hw->pm_cap = pm_cap; 3251 hw->pm_cap = pm_cap;
3252 spin_lock_init(&hw->hw_lock);
3253
3254#ifdef __BIG_ENDIAN
3255 /* byte swap descriptors in hardware */
3256 {
3257 u32 reg;
3258
3259 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3260 reg |= PCI_REV_DESC;
3261 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3262 }
3263#endif
3229 3264
3230 /* ring for status responses */ 3265 /* ring for status responses */
3231 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, 3266 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index fd12c289a238..3edb98075e0a 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -5,14 +5,22 @@
5#define _SKY2_H 5#define _SKY2_H
6 6
7/* PCI config registers */ 7/* PCI config registers */
8#define PCI_DEV_REG1 0x40 8enum {
9#define PCI_DEV_REG2 0x44 9 PCI_DEV_REG1 = 0x40,
10#define PCI_DEV_STATUS 0x7c 10 PCI_DEV_REG2 = 0x44,
11#define PCI_OS_PCI_X (1<<26) 11 PCI_DEV_STATUS = 0x7c,
12 PCI_DEV_REG3 = 0x80,
13 PCI_DEV_REG4 = 0x84,
14 PCI_DEV_REG5 = 0x88,
15};
12 16
13#define PEX_LNK_STAT 0xf2 17enum {
14#define PEX_UNC_ERR_STAT 0x104 18 PEX_DEV_CAP = 0xe4,
15#define PEX_DEV_CTRL 0xe8 19 PEX_DEV_CTRL = 0xe8,
20 PEX_DEV_STA = 0xea,
21 PEX_LNK_STAT = 0xf2,
22 PEX_UNC_ERR_STAT= 0x104,
23};
16 24
17/* Yukon-2 */ 25/* Yukon-2 */
18enum pci_dev_reg_1 { 26enum pci_dev_reg_1 {
@@ -37,6 +45,25 @@ enum pci_dev_reg_2 {
37 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */ 45 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
38}; 46};
39 47
48/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
49enum pci_dev_reg_4 {
50 /* (Link Training & Status State Machine) */
51 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
52 /* (Active State Power Management) */
53 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
54 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
55 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
56 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
57
58 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
59 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
60 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
61 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
62 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
63 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
64 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
65};
66
40 67
41#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 68#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
42 PCI_STATUS_SIG_SYSTEM_ERROR | \ 69 PCI_STATUS_SIG_SYSTEM_ERROR | \
@@ -507,6 +534,16 @@ enum {
507}; 534};
508#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) 535#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
509 536
537/* Q_F 32 bit Flag Register */
538enum {
539 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
540 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
541 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
542 F_WM_REACHED = 1<<25, /* Watermark reached */
543 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
544 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
545 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
546};
510 547
511/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ 548/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
512enum { 549enum {
@@ -909,10 +946,12 @@ enum {
909 PHY_BCOM_ID1_C0 = 0x6044, 946 PHY_BCOM_ID1_C0 = 0x6044,
910 PHY_BCOM_ID1_C5 = 0x6047, 947 PHY_BCOM_ID1_C5 = 0x6047,
911 948
912 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ 949 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
913 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */ 950 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
914 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ 951 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
915 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ 952 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
953 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
954 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
916}; 955};
917 956
918/* Advertisement register bits */ 957/* Advertisement register bits */
@@ -1837,8 +1876,9 @@ struct sky2_port {
1837struct sky2_hw { 1876struct sky2_hw {
1838 void __iomem *regs; 1877 void __iomem *regs;
1839 struct pci_dev *pdev; 1878 struct pci_dev *pdev;
1840 u32 intr_mask;
1841 struct net_device *dev[2]; 1879 struct net_device *dev[2];
1880 spinlock_t hw_lock;
1881 u32 intr_mask;
1842 1882
1843 int pm_cap; 1883 int pm_cap;
1844 int msi; 1884 int msi;
@@ -1912,4 +1952,25 @@ static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
1912 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); 1952 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
1913 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); 1953 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
1914} 1954}
1955
1956/* PCI config space access */
1957static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
1958{
1959 return sky2_read32(hw, Y2_CFG_SPC + reg);
1960}
1961
1962static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
1963{
1964 return sky2_read16(hw, Y2_CFG_SPC + reg);
1965}
1966
1967static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
1968{
1969 sky2_write32(hw, Y2_CFG_SPC + reg, val);
1970}
1971
1972static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
1973{
1974 sky2_write16(hw, Y2_CFG_SPC + reg, val);
1975}
1915#endif 1976#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-12 08:04:02 -0500