diff options
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 6497c1ad02d3..12c7d78d9240 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
| @@ -2730,14 +2730,21 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |||
| 2730 | DRM_ERROR("Failure to bind: %d\n", ret); | 2730 | DRM_ERROR("Failure to bind: %d\n", ret); |
| 2731 | return ret; | 2731 | return ret; |
| 2732 | } | 2732 | } |
| 2733 | /* | 2733 | } |
| 2734 | * Pre-965 chips need a fence register set up in order to | 2734 | /* |
| 2735 | * properly handle tiled surfaces. | 2735 | * Pre-965 chips need a fence register set up in order to |
| 2736 | */ | 2736 | * properly handle tiled surfaces. |
| 2737 | if (!IS_I965G(dev) && | 2737 | */ |
| 2738 | obj_priv->fence_reg == I915_FENCE_REG_NONE && | 2738 | if (!IS_I965G(dev) && |
| 2739 | obj_priv->tiling_mode != I915_TILING_NONE) | 2739 | obj_priv->fence_reg == I915_FENCE_REG_NONE && |
| 2740 | i915_gem_object_get_fence_reg(obj, true); | 2740 | obj_priv->tiling_mode != I915_TILING_NONE) { |
| 2741 | ret = i915_gem_object_get_fence_reg(obj, true); | ||
| 2742 | if (ret != 0) { | ||
| 2743 | if (ret != -EBUSY && ret != -ERESTARTSYS) | ||
| 2744 | DRM_ERROR("Failure to install fence: %d\n", | ||
| 2745 | ret); | ||
| 2746 | return ret; | ||
| 2747 | } | ||
| 2741 | } | 2748 | } |
| 2742 | obj_priv->pin_count++; | 2749 | obj_priv->pin_count++; |
| 2743 | 2750 | ||
