2 files changed, 11 insertions, 5 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 58109ae34709..76a3ba668e2e 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -599,7 +599,7 @@ config CPU_DCACHE_SIZE
 
 config CPU_DCACHE_WRITETHROUGH
         bool "Force write through D-cache"
-        depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
+        depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
         default y if CPU_ARM925T
         help
           Say Y here to use the data cache in writethrough mode. Unless you
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 3b5e47dc0c97..e5d61ee3d4a1 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -114,6 +114,10 @@ static void __init early_cachepolicy(char **p)
         }
         if (i == ARRAY_SIZE(cache_policies))
                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
+        if (cpu_architecture() >= CPU_ARCH_ARMv6) {
+                printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
+                cachepolicy = CPOLICY_WRITEBACK;
+        }
         flush_cache_all();
         set_cr(cr_alignment);
 }
@@ -252,13 +256,15 @@ static void __init build_mem_type_table(void)
         int cpu_arch = cpu_architecture();
         int i;
 
+        if (cpu_arch < CPU_ARCH_ARMv6) {
 #if defined(CONFIG_CPU_DCACHE_DISABLE)
-        if (cachepolicy > CPOLICY_BUFFERED)
-                cachepolicy = CPOLICY_BUFFERED;
+                if (cachepolicy > CPOLICY_BUFFERED)
+                        cachepolicy = CPOLICY_BUFFERED;
 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
-        if (cachepolicy > CPOLICY_WRITETHROUGH)
-                cachepolicy = CPOLICY_WRITETHROUGH;
+                if (cachepolicy > CPOLICY_WRITETHROUGH)
+                        cachepolicy = CPOLICY_WRITETHROUGH;
 #endif
+        }
         if (cpu_arch < CPU_ARCH_ARMv5) {
                 if (cachepolicy >= CPOLICY_WRITEALLOC)
                         cachepolicy = CPOLICY_WRITEBACK;