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-rw-r--r--arch/powerpc/Kconfig9
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts211
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts250
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts54
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts8
-rw-r--r--arch/powerpc/configs/mpc8544_ds_defconfig333
-rw-r--r--arch/powerpc/configs/mpc8568mds_defconfig292
-rw-r--r--arch/powerpc/kernel/pci_32.c25
-rw-r--r--arch/powerpc/platforms/82xx/mpc82xx_ads.c3
-rw-r--r--arch/powerpc/platforms/83xx/pci.c4
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig6
-rw-r--r--arch/powerpc/platforms/85xx/Makefile2
-rw-r--r--arch/powerpc/platforms/85xx/mpc8544_ds.c241
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx.h1
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ads.c3
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_cds.c125
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c7
-rw-r--r--arch/powerpc/platforms/85xx/pci.c91
-rw-r--r--arch/powerpc/platforms/86xx/Kconfig3
-rw-r--r--arch/powerpc/platforms/86xx/Makefile1
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx.h5
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c13
-rw-r--r--arch/powerpc/platforms/86xx/pci.c238
-rw-r--r--arch/powerpc/platforms/chrp/pci.c7
-rw-r--r--arch/powerpc/platforms/embedded6xx/linkstation.c2
-rw-r--r--arch/powerpc/sysdev/Makefile1
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c257
-rw-r--r--arch/powerpc/sysdev/fsl_pci.h88
-rw-r--r--arch/powerpc/sysdev/fsl_pcie.h94
-rw-r--r--arch/powerpc/sysdev/grackle.c2
-rw-r--r--arch/powerpc/sysdev/indirect_pci.c59
-rw-r--r--arch/powerpc/sysdev/mv64x60_pci.c2
-rw-r--r--include/asm-powerpc/pci-bridge.h16
-rw-r--r--include/linux/pci_ids.h17
45 files changed, 1660 insertions, 840 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 853c282da22e..00099efe0e9f 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -411,11 +411,6 @@ config PPC_INDIRECT_PCI
411 default y if 40x || 44x 411 default y if 40x || 44x
412 default n 412 default n
413 413
414config PPC_INDIRECT_PCI_BE
415 bool
416 depends PPC_INDIRECT_PCI
417 default n
418
419config EISA 414config EISA
420 bool 415 bool
421 416
@@ -425,6 +420,10 @@ config SBUS
425config FSL_SOC 420config FSL_SOC
426 bool 421 bool
427 422
423config FSL_PCI
424 bool
425 select PPC_INDIRECT_PCI
426
428# Yes MCA RS/6000s exist but Linux-PPC does not currently support any 427# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
429config MCA 428config MCA
430 bool 429 bool
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index a1533cc07d09..c5adbe40364e 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -178,7 +178,7 @@
178 #size-cells = <2>; 178 #size-cells = <2>;
179 #address-cells = <3>; 179 #address-cells = <3>;
180 reg = <8500 100>; 180 reg = <8500 100>;
181 compatible = "83xx"; 181 compatible = "fsl,mpc8349-pci";
182 device_type = "pci"; 182 device_type = "pci";
183 }; 183 };
184 184
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 4fc0c4d34aa8..f158ed781ba8 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -154,7 +154,7 @@
154 #size-cells = <2>; 154 #size-cells = <2>;
155 #address-cells = <3>; 155 #address-cells = <3>;
156 reg = <8500 100>; 156 reg = <8500 100>;
157 compatible = "83xx"; 157 compatible = "fsl,mpc8349-pci";
158 device_type = "pci"; 158 device_type = "pci";
159 }; 159 };
160 160
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 447c03ffabbc..7c4beff3e200 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -123,7 +123,7 @@
123 #size-cells = <2>; 123 #size-cells = <2>;
124 #address-cells = <3>; 124 #address-cells = <3>;
125 reg = <8500 100>; 125 reg = <8500 100>;
126 compatible = "83xx"; 126 compatible = "fsl,mpc8349-pci";
127 device_type = "pci"; 127 device_type = "pci";
128 }; 128 };
129 129
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index ae9bca575453..502f47c01797 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -197,7 +197,7 @@
197 #size-cells = <2>; 197 #size-cells = <2>;
198 #address-cells = <3>; 198 #address-cells = <3>;
199 reg = <8500 100>; 199 reg = <8500 100>;
200 compatible = "83xx"; 200 compatible = "fsl,mpc8349-pci";
201 device_type = "pci"; 201 device_type = "pci";
202 }; 202 };
203 203
@@ -222,7 +222,7 @@
222 #size-cells = <2>; 222 #size-cells = <2>;
223 #address-cells = <3>; 223 #address-cells = <3>;
224 reg = <8600 100>; 224 reg = <8600 100>;
225 compatible = "83xx"; 225 compatible = "fsl,mpc8349-pci";
226 device_type = "pci"; 226 device_type = "pci";
227 }; 227 };
228 228
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index f636528a3c72..0b8387141d88 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -154,7 +154,7 @@
154 #size-cells = <2>; 154 #size-cells = <2>;
155 #address-cells = <3>; 155 #address-cells = <3>;
156 reg = <8600 100>; 156 reg = <8600 100>;
157 compatible = "83xx"; 157 compatible = "fsl,mpc8349-pci";
158 device_type = "pci"; 158 device_type = "pci";
159 }; 159 };
160 160
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 310e877826b4..481099756e44 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -241,7 +241,7 @@
241 #size-cells = <2>; 241 #size-cells = <2>;
242 #address-cells = <3>; 242 #address-cells = <3>;
243 reg = <8500 100>; 243 reg = <8500 100>;
244 compatible = "83xx"; 244 compatible = "fsl,mpc8349-pci";
245 device_type = "pci"; 245 device_type = "pci";
246 }; 246 };
247 247
@@ -301,7 +301,7 @@
301 #size-cells = <2>; 301 #size-cells = <2>;
302 #address-cells = <3>; 302 #address-cells = <3>;
303 reg = <8600 100>; 303 reg = <8600 100>;
304 compatible = "83xx"; 304 compatible = "fsl,mpc8349-pci";
305 device_type = "pci"; 305 device_type = "pci";
306 }; 306 };
307 307
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 1e914f31dd92..e3f7c1282068 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -169,7 +169,7 @@
169 #size-cells = <2>; 169 #size-cells = <2>;
170 #address-cells = <3>; 170 #address-cells = <3>;
171 reg = <8500 100>; 171 reg = <8500 100>;
172 compatible = "83xx"; 172 compatible = "fsl,mpc8349-pci";
173 device_type = "pci"; 173 device_type = "pci";
174 }; 174 };
175 175
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 364a969f5c2f..fc8dff9f6201 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -258,7 +258,7 @@
258 #size-cells = <2>; 258 #size-cells = <2>;
259 #address-cells = <3>; 259 #address-cells = <3>;
260 reg = <8000 1000>; 260 reg = <8000 1000>;
261 compatible = "85xx"; 261 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
262 device_type = "pci"; 262 device_type = "pci";
263 }; 263 };
264 264
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 070206fffe88..fb0b647f8c2a 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -193,7 +193,7 @@
193 #size-cells = <2>; 193 #size-cells = <2>;
194 #address-cells = <3>; 194 #address-cells = <3>;
195 reg = <8000 1000>; 195 reg = <8000 1000>;
196 compatible = "85xx"; 196 compatible = "fsl,mpc8540-pci";
197 device_type = "pci"; 197 device_type = "pci";
198 198
199 i8259@19000 { 199 i8259@19000 {
@@ -230,7 +230,7 @@
230 #size-cells = <2>; 230 #size-cells = <2>;
231 #address-cells = <3>; 231 #address-cells = <3>;
232 reg = <9000 1000>; 232 reg = <9000 1000>;
233 compatible = "85xx"; 233 compatible = "fsl,mpc8540-pci";
234 device_type = "pci"; 234 device_type = "pci";
235 }; 235 };
236 236
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 828592592460..4a900c6df762 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -137,6 +137,217 @@
137 interrupt-parent = <&mpic>; 137 interrupt-parent = <&mpic>;
138 }; 138 };
139 139
140 pci@8000 {
141 compatible = "fsl,mpc8540-pci";
142 device_type = "pci";
143 interrupt-map-mask = <f800 0 0 7>;
144 interrupt-map = <
145
146 /* IDSEL 0x11 J17 Slot 1 */
147 8800 0 0 1 &mpic 2 1
148 8800 0 0 2 &mpic 3 1
149 8800 0 0 3 &mpic 4 1
150 8800 0 0 4 &mpic 1 1
151
152 /* IDSEL 0x12 J16 Slot 2 */
153
154 9000 0 0 1 &mpic 3 1
155 9000 0 0 2 &mpic 4 1
156 9000 0 0 3 &mpic 2 1
157 9000 0 0 4 &mpic 1 1>;
158
159 interrupt-parent = <&mpic>;
160 interrupts = <18 2>;
161 bus-range = <0 ff>;
162 ranges = <02000000 0 80000000 80000000 0 10000000
163 01000000 0 00000000 e2000000 0 00800000>;
164 clock-frequency = <3f940aa>;
165 #interrupt-cells = <1>;
166 #size-cells = <2>;
167 #address-cells = <3>;
168 reg = <8000 1000>;
169 };
170
171 pcie@9000 {
172 compatible = "fsl,mpc8548-pcie";
173 device_type = "pci";
174 #interrupt-cells = <1>;
175 #size-cells = <2>;
176 #address-cells = <3>;
177 reg = <9000 1000>;
178 bus-range = <0 ff>;
179 ranges = <02000000 0 90000000 90000000 0 10000000
180 01000000 0 00000000 e3000000 0 00800000>;
181 clock-frequency = <1fca055>;
182 interrupt-parent = <&mpic>;
183 interrupts = <1a 2>;
184 interrupt-map-mask = <f800 0 0 7>;
185 interrupt-map = <
186 /* IDSEL 0x0 */
187 0000 0 0 1 &mpic 4 1
188 0000 0 0 2 &mpic 5 1
189 0000 0 0 3 &mpic 6 1
190 0000 0 0 4 &mpic 7 1
191 >;
192 };
193
194 pcie@a000 {
195 compatible = "fsl,mpc8548-pcie";
196 device_type = "pci";
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 reg = <a000 1000>;
201 bus-range = <0 ff>;
202 ranges = <02000000 0 a0000000 a0000000 0 10000000
203 01000000 0 00000000 e2800000 0 00800000>;
204 clock-frequency = <1fca055>;
205 interrupt-parent = <&mpic>;
206 interrupts = <19 2>;
207 interrupt-map-mask = <f800 0 0 7>;
208 interrupt-map = <
209 /* IDSEL 0x0 */
210 0000 0 0 1 &mpic 0 1
211 0000 0 0 2 &mpic 1 1
212 0000 0 0 3 &mpic 2 1
213 0000 0 0 4 &mpic 3 1
214 >;
215 };
216
217 pcie@b000 {
218 compatible = "fsl,mpc8548-pcie";
219 device_type = "pci";
220 #interrupt-cells = <1>;
221 #size-cells = <2>;
222 #address-cells = <3>;
223 reg = <b000 1000>;
224 bus-range = <0 ff>;
225 ranges = <02000000 0 b0000000 b0000000 0 10000000
226 01000000 0 00000000 e3800000 0 00800000>;
227 clock-frequency = <1fca055>;
228 interrupt-parent = <&mpic>;
229 interrupts = <1b 2>;
230 interrupt-map-mask = <f800 0 0 7>;
231 interrupt-map = <
232
233 // IDSEL 0x1a
234 d000 0 0 1 &i8259 6 2
235 d000 0 0 2 &i8259 3 2
236 d000 0 0 3 &i8259 4 2
237 d000 0 0 4 &i8259 5 2
238
239 // IDSEL 0x1b
240 d800 0 0 1 &i8259 5 2
241 d800 0 0 2 &i8259 0 0
242 d800 0 0 3 &i8259 0 0
243 d800 0 0 4 &i8259 0 0
244
245 // IDSEL 0x1c USB
246 e000 0 0 1 &i8259 9 2
247 e000 0 0 2 &i8259 a 2
248 e000 0 0 3 &i8259 c 2
249 e000 0 0 4 &i8259 7 2
250
251 // IDSEL 0x1d Audio
252 e800 0 0 1 &i8259 9 2
253 e800 0 0 2 &i8259 a 2
254 e800 0 0 3 &i8259 b 2
255 e800 0 0 4 &i8259 0 0
256
257 // IDSEL 0x1e Legacy
258 f000 0 0 1 &i8259 c 2
259 f000 0 0 2 &i8259 0 0
260 f000 0 0 3 &i8259 0 0
261 f000 0 0 4 &i8259 0 0
262
263 // IDSEL 0x1f IDE/SATA
264 f800 0 0 1 &i8259 6 2
265 f800 0 0 2 &i8259 0 0
266 f800 0 0 3 &i8259 0 0
267 f800 0 0 4 &i8259 0 0
268 >;
269 uli1575@0 {
270 reg = <0 0 0 0 0>;
271 #size-cells = <2>;
272 #address-cells = <3>;
273 ranges = <02000000 0 b0000000
274 02000000 0 b0000000
275 0 10000000
276 01000000 0 00000000
277 01000000 0 00000000
278 0 00080000>;
279
280 pci_bridge@0 {
281 reg = <0 0 0 0 0>;
282 #size-cells = <2>;
283 #address-cells = <3>;
284 ranges = <02000000 0 b0000000
285 02000000 0 b0000000
286 0 20000000
287 01000000 0 00000000
288 01000000 0 00000000
289 0 00100000>;
290
291 isa@1e {
292 device_type = "isa";
293 #interrupt-cells = <2>;
294 #size-cells = <1>;
295 #address-cells = <2>;
296 reg = <f000 0 0 0 0>;
297 ranges = <1 0 01000000 0 0
298 00001000>;
299 interrupt-parent = <&i8259>;
300
301 i8259: interrupt-controller@20 {
302 reg = <1 20 2
303 1 a0 2
304 1 4d0 2>;
305 clock-frequency = <0>;
306 interrupt-controller;
307 device_type = "interrupt-controller";
308 #address-cells = <0>;
309 #interrupt-cells = <2>;
310 built-in;
311 compatible = "chrp,iic";
312 interrupts = <9 2>;
313 interrupt-parent =
314 <&mpic>;
315 };
316
317 i8042@60 {
318 #size-cells = <0>;
319 #address-cells = <1>;
320 reg = <1 60 1 1 64 1>;
321 interrupts = <1 3 c 3>;
322 interrupt-parent =
323 <&i8259>;
324
325 keyboard@0 {
326 reg = <0>;
327 compatible = "pnpPNP,303";
328 };
329
330 mouse@1 {
331 reg = <1>;
332 compatible = "pnpPNP,f03";
333 };
334 };
335
336 rtc@70 {
337 compatible =
338 "pnpPNP,b00";
339 reg = <1 70 2>;
340 };
341
342 gpio@400 {
343 reg = <1 400 80>;
344 };
345 };
346 };
347 };
348
349 };
350
140 mpic: pic@40000 { 351 mpic: pic@40000 {
141 clock-frequency = <0>; 352 clock-frequency = <0>;
142 interrupt-controller; 353 interrupt-controller;
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 9d0b84b66cd4..d215d21fff42 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * MPC8555 CDS Device Tree Source 2 * MPC8548 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006 Freescale Semiconductor Inc.
5 * 5 *
@@ -44,8 +44,14 @@
44 #size-cells = <1>; 44 #size-cells = <1>;
45 #interrupt-cells = <2>; 45 #interrupt-cells = <2>;
46 device_type = "soc"; 46 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 47 ranges = <00001000 e0001000 000ff000
48 reg = <e0000000 00100000>; // CCSRBAR 1M 48 80000000 80000000 10000000
49 e2000000 e2000000 00800000
50 90000000 90000000 10000000
51 e2800000 e2800000 00800000
52 a0000000 a0000000 20000000
53 e3000000 e3000000 01000000>;
54 reg = <e0000000 00001000>; // CCSRBAR
49 bus-frequency = <0>; 55 bus-frequency = <0>;
50 56
51 memory-controller@2000 { 57 memory-controller@2000 {
@@ -162,8 +168,8 @@
162 serial@4500 { 168 serial@4500 {
163 device_type = "serial"; 169 device_type = "serial";
164 compatible = "ns16550"; 170 compatible = "ns16550";
165 reg = <4500 100>; // reg base, size 171 reg = <4500 100>; // reg base, size
166 clock-frequency = <0>; // should we fill in in uboot? 172 clock-frequency = <0>; // should we fill in in uboot?
167 interrupts = <2a 2>; 173 interrupts = <2a 2>;
168 interrupt-parent = <&mpic>; 174 interrupt-parent = <&mpic>;
169 }; 175 };
@@ -172,7 +178,7 @@
172 device_type = "serial"; 178 device_type = "serial";
173 compatible = "ns16550"; 179 compatible = "ns16550";
174 reg = <4600 100>; // reg base, size 180 reg = <4600 100>; // reg base, size
175 clock-frequency = <0>; // should we fill in in uboot? 181 clock-frequency = <0>; // should we fill in in uboot?
176 interrupts = <2a 2>; 182 interrupts = <2a 2>;
177 interrupt-parent = <&mpic>; 183 interrupt-parent = <&mpic>;
178 }; 184 };
@@ -183,77 +189,154 @@
183 fsl,has-rstcr; 189 fsl,has-rstcr;
184 }; 190 };
185 191
186 pci1: pci@8000 { 192 pci@8000 {
187 interrupt-map-mask = <1f800 0 0 7>; 193 interrupt-map-mask = <f800 0 0 7>;
188 interrupt-map = < 194 interrupt-map = <
195 /* IDSEL 0x4 (PCIX Slot 2) */
196 02000 0 0 1 &mpic 0 1
197 02000 0 0 2 &mpic 1 1
198 02000 0 0 3 &mpic 2 1
199 02000 0 0 4 &mpic 3 1
200
201 /* IDSEL 0x5 (PCIX Slot 3) */
202 02800 0 0 1 &mpic 1 1
203 02800 0 0 2 &mpic 2 1
204 02800 0 0 3 &mpic 3 1
205 02800 0 0 4 &mpic 0 1
206
207 /* IDSEL 0x6 (PCIX Slot 4) */
208 03000 0 0 1 &mpic 2 1
209 03000 0 0 2 &mpic 3 1
210 03000 0 0 3 &mpic 0 1
211 03000 0 0 4 &mpic 1 1
212
213 /* IDSEL 0x8 (PCIX Slot 5) */
214 04000 0 0 1 &mpic 0 1
215 04000 0 0 2 &mpic 1 1
216 04000 0 0 3 &mpic 2 1
217 04000 0 0 4 &mpic 3 1
218
219 /* IDSEL 0xC (Tsi310 bridge) */
220 06000 0 0 1 &mpic 0 1
221 06000 0 0 2 &mpic 1 1
222 06000 0 0 3 &mpic 2 1
223 06000 0 0 4 &mpic 3 1
224
225 /* IDSEL 0x14 (Slot 2) */
226 0a000 0 0 1 &mpic 0 1
227 0a000 0 0 2 &mpic 1 1
228 0a000 0 0 3 &mpic 2 1
229 0a000 0 0 4 &mpic 3 1
230
231 /* IDSEL 0x15 (Slot 3) */
232 0a800 0 0 1 &mpic 1 1
233 0a800 0 0 2 &mpic 2 1
234 0a800 0 0 3 &mpic 3 1
235 0a800 0 0 4 &mpic 0 1
236
237 /* IDSEL 0x16 (Slot 4) */
238 0b000 0 0 1 &mpic 2 1
239 0b000 0 0 2 &mpic 3 1
240 0b000 0 0 3 &mpic 0 1
241 0b000 0 0 4 &mpic 1 1
242
243 /* IDSEL 0x18 (Slot 5) */
244 0c000 0 0 1 &mpic 0 1
245 0c000 0 0 2 &mpic 1 1
246 0c000 0 0 3 &mpic 2 1
247 0c000 0 0 4 &mpic 3 1
248
249 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
250 0E000 0 0 1 &mpic 0 1
251 0E000 0 0 2 &mpic 1 1
252 0E000 0 0 3 &mpic 2 1
253 0E000 0 0 4 &mpic 3 1>;
189 254
190 /* IDSEL 0x10 */
191 08000 0 0 1 &mpic 0 1
192 08000 0 0 2 &mpic 1 1
193 08000 0 0 3 &mpic 2 1
194 08000 0 0 4 &mpic 3 1
195
196 /* IDSEL 0x11 */
197 08800 0 0 1 &mpic 0 1
198 08800 0 0 2 &mpic 1 1
199 08800 0 0 3 &mpic 2 1
200 08800 0 0 4 &mpic 3 1
201
202 /* IDSEL 0x12 (Slot 1) */
203 09000 0 0 1 &mpic 0 1
204 09000 0 0 2 &mpic 1 1
205 09000 0 0 3 &mpic 2 1
206 09000 0 0 4 &mpic 3 1
207
208 /* IDSEL 0x13 (Slot 2) */
209 09800 0 0 1 &mpic 1 1
210 09800 0 0 2 &mpic 2 1
211 09800 0 0 3 &mpic 3 1
212 09800 0 0 4 &mpic 0 1
213
214 /* IDSEL 0x14 (Slot 3) */
215 0a000 0 0 1 &mpic 2 1
216 0a000 0 0 2 &mpic 3 1
217 0a000 0 0 3 &mpic 0 1
218 0a000 0 0 4 &mpic 1 1
219
220 /* IDSEL 0x15 (Slot 4) */
221 0a800 0 0 1 &mpic 3 1
222 0a800 0 0 2 &mpic 0 1
223 0a800 0 0 3 &mpic 1 1
224 0a800 0 0 4 &mpic 2 1
225
226 /* Bus 1 (Tundra Bridge) */
227 /* IDSEL 0x12 (ISA bridge) */
228 19000 0 0 1 &mpic 0 1
229 19000 0 0 2 &mpic 1 1
230 19000 0 0 3 &mpic 2 1
231 19000 0 0 4 &mpic 3 1>;
232 interrupt-parent = <&mpic>; 255 interrupt-parent = <&mpic>;
233 interrupts = <18 2>; 256 interrupts = <18 2>;
234 bus-range = <0 0>; 257 bus-range = <0 0>;
235 ranges = <02000000 0 80000000 80000000 0 20000000 258 ranges = <02000000 0 80000000 80000000 0 10000000
236 01000000 0 00000000 e2000000 0 00100000>; 259 01000000 0 00000000 e2000000 0 00800000>;
237 clock-frequency = <3f940aa>; 260 clock-frequency = <3f940aa>;
238 #interrupt-cells = <1>; 261 #interrupt-cells = <1>;
239 #size-cells = <2>; 262 #size-cells = <2>;
240 #address-cells = <3>; 263 #address-cells = <3>;
241 reg = <8000 1000>; 264 reg = <8000 1000>;
242 compatible = "85xx"; 265 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
243 device_type = "pci"; 266 device_type = "pci";
244 267
245 i8259@19000 { 268 pci_bridge@1c {
246 clock-frequency = <0>; 269 interrupt-map-mask = <f800 0 0 7>;
247 interrupt-controller; 270 interrupt-map = <
248 device_type = "interrupt-controller"; 271
249 reg = <19000 0 0 0 1>; 272 /* IDSEL 0x00 (PrPMC Site) */
250 #address-cells = <0>; 273 0000 0 0 1 &mpic 0 1
251 #interrupt-cells = <2>; 274 0000 0 0 2 &mpic 1 1
252 built-in; 275 0000 0 0 3 &mpic 2 1
253 compatible = "chrp,iic"; 276 0000 0 0 4 &mpic 3 1
254 big-endian; 277
255 interrupts = <1>; 278 /* IDSEL 0x04 (VIA chip) */
256 interrupt-parent = <&pci1>; 279 2000 0 0 1 &mpic 0 1
280 2000 0 0 2 &mpic 1 1
281 2000 0 0 3 &mpic 2 1
282 2000 0 0 4 &mpic 3 1
283
284 /* IDSEL 0x05 (8139) */
285 2800 0 0 1 &mpic 1 1
286
287 /* IDSEL 0x06 (Slot 6) */
288 3000 0 0 1 &mpic 2 1
289 3000 0 0 2 &mpic 3 1
290 3000 0 0 3 &mpic 0 1
291 3000 0 0 4 &mpic 1 1
292
293 /* IDESL 0x07 (Slot 7) */
294 3800 0 0 1 &mpic 3 1
295 3800 0 0 2 &mpic 0 1
296 3800 0 0 3 &mpic 1 1
297 3800 0 0 4 &mpic 2 1>;
298
299 reg = <e000 0 0 0 0>;
300 #interrupt-cells = <1>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 ranges = <02000000 0 80000000
304 02000000 0 80000000
305 0 20000000
306 01000000 0 00000000
307 01000000 0 00000000
308 0 00080000>;
309 clock-frequency = <1fca055>;
310
311 isa@4 {
312 device_type = "isa";
313 #interrupt-cells = <2>;
314 #size-cells = <1>;
315 #address-cells = <2>;
316 reg = <2000 0 0 0 0>;
317 ranges = <1 0 01000000 0 0 00001000>;
318 interrupt-parent = <&i8259>;
319
320 i8259: interrupt-controller@20 {
321 clock-frequency = <0>;
322 interrupt-controller;
323 device_type = "interrupt-controller";
324 reg = <1 20 2
325 1 a0 2
326 1 4d0 2>;
327 #address-cells = <0>;
328 #interrupt-cells = <2>;
329 built-in;
330 compatible = "chrp,iic";
331 interrupts = <0 1>;
332 interrupt-parent = <&mpic>;
333 };
334
335 rtc@70 {
336 compatible = "pnpPNP,b00";
337 reg = <1 70 2>;
338 };
339 };
257 }; 340 };
258 }; 341 };
259 342
@@ -263,20 +346,45 @@
263 346
264 /* IDSEL 0x15 */ 347 /* IDSEL 0x15 */
265 a800 0 0 1 &mpic b 1 348 a800 0 0 1 &mpic b 1
266 a800 0 0 2 &mpic b 1 349 a800 0 0 2 &mpic 1 1
267 a800 0 0 3 &mpic b 1 350 a800 0 0 3 &mpic 2 1
268 a800 0 0 4 &mpic b 1>; 351 a800 0 0 4 &mpic 3 1>;
352
269 interrupt-parent = <&mpic>; 353 interrupt-parent = <&mpic>;
270 interrupts = <19 2>; 354 interrupts = <19 2>;
271 bus-range = <0 0>; 355 bus-range = <0 0>;
272 ranges = <02000000 0 a0000000 a0000000 0 20000000 356 ranges = <02000000 0 90000000 90000000 0 10000000
273 01000000 0 00000000 e3000000 0 00100000>; 357 01000000 0 00000000 e2800000 0 00800000>;
274 clock-frequency = <3f940aa>; 358 clock-frequency = <3f940aa>;
275 #interrupt-cells = <1>; 359 #interrupt-cells = <1>;
276 #size-cells = <2>; 360 #size-cells = <2>;
277 #address-cells = <3>; 361 #address-cells = <3>;
278 reg = <9000 1000>; 362 reg = <9000 1000>;
279 compatible = "85xx"; 363 compatible = "fsl,mpc8540-pci";
364 device_type = "pci";
365 };
366 /* PCI Express */
367 pcie@a000 {
368 interrupt-map-mask = <f800 0 0 7>;
369 interrupt-map = <
370
371 /* IDSEL 0x0 (PEX) */
372 00000 0 0 1 &mpic 0 1
373 00000 0 0 2 &mpic 1 1
374 00000 0 0 3 &mpic 2 1
375 00000 0 0 4 &mpic 3 1>;
376
377 interrupt-parent = <&mpic>;
378 interrupts = <1a 2>;
379 bus-range = <0 ff>;
380 ranges = <02000000 0 a0000000 a0000000 0 20000000
381 01000000 0 00000000 e3000000 0 08000000>;
382 clock-frequency = <1fca055>;
383 #interrupt-cells = <1>;
384 #size-cells = <2>;
385 #address-cells = <3>;
386 reg = <a000 1000>;
387 compatible = "fsl,mpc8548-pcie";
280 device_type = "pci"; 388 device_type = "pci";
281 }; 389 };
282 390
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 17e45d9a382a..c3c888252121 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -193,7 +193,7 @@
193 #size-cells = <2>; 193 #size-cells = <2>;
194 #address-cells = <3>; 194 #address-cells = <3>;
195 reg = <8000 1000>; 195 reg = <8000 1000>;
196 compatible = "85xx"; 196 compatible = "fsl,mpc8540-pci";
197 device_type = "pci"; 197 device_type = "pci";
198 198
199 i8259@19000 { 199 i8259@19000 {
@@ -230,7 +230,7 @@
230 #size-cells = <2>; 230 #size-cells = <2>;
231 #address-cells = <3>; 231 #address-cells = <3>;
232 reg = <9000 1000>; 232 reg = <9000 1000>;
233 compatible = "85xx"; 233 compatible = "fsl,mpc8540-pci";
234 device_type = "pci"; 234 device_type = "pci";
235 }; 235 };
236 236
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 21ccaaa27993..16dbe848cecf 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -136,7 +136,7 @@
136 #interrupt-cells = <1>; 136 #interrupt-cells = <1>;
137 #size-cells = <2>; 137 #size-cells = <2>;
138 #address-cells = <3>; 138 #address-cells = <3>;
139 compatible = "85xx"; 139 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
140 device_type = "pci"; 140 device_type = "pci";
141 reg = <8000 1000>; 141 reg = <8000 1000>;
142 clock-frequency = <3f940aa>; 142 clock-frequency = <3f940aa>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 6bb18f2807a8..99fa5a0ea425 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -170,6 +170,60 @@
170 interrupt-parent = <&mpic>; 170 interrupt-parent = <&mpic>;
171 }; 171 };
172 172
173 pci@8000 {
174 interrupt-map-mask = <f800 0 0 7>;
175 interrupt-map = <
176 /* IDSEL 0x12 AD18 */
177 9000 0 0 1 &mpic 5 1
178 9000 0 0 2 &mpic 6 1
179 9000 0 0 3 &mpic 7 1
180 9000 0 0 4 &mpic 4 1
181
182 /* IDSEL 0x13 AD19 */
183 9800 0 0 1 &mpic 6 1
184 9800 0 0 2 &mpic 7 1
185 9800 0 0 3 &mpic 4 1
186 9800 0 0 4 &mpic 5 1>;
187
188 interrupt-parent = <&mpic>;
189 interrupts = <18 2>;
190 bus-range = <0 ff>;
191 ranges = <02000000 0 80000000 80000000 0 20000000
192 01000000 0 00000000 e2000000 0 00800000>;
193 clock-frequency = <3f940aa>;
194 #interrupt-cells = <1>;
195 #size-cells = <2>;
196 #address-cells = <3>;
197 reg = <8000 1000>;
198 compatible = "fsl,mpc8540-pci";
199 device_type = "pci";
200 };
201
202 /* PCI Express */
203 pcie@a000 {
204 interrupt-map-mask = <f800 0 0 7>;
205 interrupt-map = <
206
207 /* IDSEL 0x0 (PEX) */
208 00000 0 0 1 &mpic 0 1
209 00000 0 0 2 &mpic 1 1
210 00000 0 0 3 &mpic 2 1
211 00000 0 0 4 &mpic 3 1>;
212
213 interrupt-parent = <&mpic>;
214 interrupts = <1a 2>;
215 bus-range = <0 ff>;
216 ranges = <02000000 0 a0000000 a0000000 0 20000000
217 01000000 0 00000000 e3000000 0 08000000>;
218 clock-frequency = <1fca055>;
219 #interrupt-cells = <1>;
220 #size-cells = <2>;
221 #address-cells = <3>;
222 reg = <a000 1000>;
223 compatible = "fsl,mpc8548-pcie";
224 device_type = "pci";
225 };
226
173 serial@4600 { 227 serial@4600 {
174 device_type = "serial"; 228 device_type = "serial";
175 compatible = "ns16550"; 229 compatible = "ns16550";
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 6a78a2b37c08..5d82709cfcbb 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -211,8 +211,8 @@
211 interrupt-parent = <&mpic>; 211 interrupt-parent = <&mpic>;
212 }; 212 };
213 213
214 pci@8000 { 214 pcie@8000 {
215 compatible = "86xx"; 215 compatible = "fsl,mpc8641-pcie";
216 device_type = "pci"; 216 device_type = "pci";
217 #interrupt-cells = <1>; 217 #interrupt-cells = <1>;
218 #size-cells = <2>; 218 #size-cells = <2>;
@@ -399,8 +399,8 @@
399 399
400 }; 400 };
401 401
402 pci@9000 { 402 pcie@9000 {
403 compatible = "86xx"; 403 compatible = "fsl,mpc8641-pcie";
404 device_type = "pci"; 404 device_type = "pci";
405 #interrupt-cells = <1>; 405 #interrupt-cells = <1>;
406 #size-cells = <2>; 406 #size-cells = <2>;
diff --git a/arch/powerpc/configs/mpc8544_ds_defconfig b/arch/powerpc/configs/mpc8544_ds_defconfig
index c40a25a79cbb..7995231def26 100644
--- a/arch/powerpc/configs/mpc8544_ds_defconfig
+++ b/arch/powerpc/configs/mpc8544_ds_defconfig
@@ -1,9 +1,26 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22-rc7 3# Linux kernel version: 2.6.22
4# Sun Jul 1 23:56:58 2007 4# Fri Jul 20 14:09:13 2007
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7
8#
9# Processor support
10#
11# CONFIG_6xx is not set
12CONFIG_PPC_85xx=y
13# CONFIG_PPC_8xx is not set
14# CONFIG_40x is not set
15# CONFIG_44x is not set
16# CONFIG_E200 is not set
17CONFIG_85xx=y
18CONFIG_E500=y
19CONFIG_BOOKE=y
20CONFIG_FSL_BOOKE=y
21# CONFIG_PHYS_64BIT is not set
22# CONFIG_SPE is not set
23# CONFIG_PPC_MM_SLICES is not set
7CONFIG_PPC32=y 24CONFIG_PPC32=y
8CONFIG_PPC_MERGE=y 25CONFIG_PPC_MERGE=y
9CONFIG_MMU=y 26CONFIG_MMU=y
@@ -14,6 +31,7 @@ CONFIG_ARCH_HAS_ILOG2_U32=y
14CONFIG_GENERIC_HWEIGHT=y 31CONFIG_GENERIC_HWEIGHT=y
15CONFIG_GENERIC_CALIBRATE_DELAY=y 32CONFIG_GENERIC_CALIBRATE_DELAY=y
16CONFIG_GENERIC_FIND_NEXT_BIT=y 33CONFIG_GENERIC_FIND_NEXT_BIT=y
34# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
17CONFIG_PPC=y 35CONFIG_PPC=y
18CONFIG_EARLY_PRINTK=y 36CONFIG_EARLY_PRINTK=y
19CONFIG_GENERIC_NVRAM=y 37CONFIG_GENERIC_NVRAM=y
@@ -25,28 +43,8 @@ CONFIG_PPC_UDBG_16550=y
25CONFIG_AUDIT_ARCH=y 43CONFIG_AUDIT_ARCH=y
26CONFIG_GENERIC_BUG=y 44CONFIG_GENERIC_BUG=y
27CONFIG_DEFAULT_UIMAGE=y 45CONFIG_DEFAULT_UIMAGE=y
28
29#
30# Processor support
31#
32# CONFIG_CLASSIC32 is not set
33# CONFIG_PPC_82xx is not set
34# CONFIG_PPC_83xx is not set
35CONFIG_PPC_85xx=y
36# CONFIG_PPC_86xx is not set
37# CONFIG_PPC_8xx is not set
38# CONFIG_40x is not set
39# CONFIG_44x is not set
40# CONFIG_E200 is not set
41CONFIG_85xx=y
42CONFIG_E500=y
43# CONFIG_PPC_DCR_NATIVE is not set 46# CONFIG_PPC_DCR_NATIVE is not set
44# CONFIG_PPC_DCR_MMIO is not set 47# CONFIG_PPC_DCR_MMIO is not set
45CONFIG_BOOKE=y
46CONFIG_FSL_BOOKE=y
47# CONFIG_PHYS_64BIT is not set
48# CONFIG_SPE is not set
49# CONFIG_PPC_MM_SLICES is not set
50CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 48CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
51 49
52# 50#
@@ -63,13 +61,12 @@ CONFIG_LOCALVERSION=""
63CONFIG_LOCALVERSION_AUTO=y 61CONFIG_LOCALVERSION_AUTO=y
64CONFIG_SWAP=y 62CONFIG_SWAP=y
65CONFIG_SYSVIPC=y 63CONFIG_SYSVIPC=y
66CONFIG_IPC_NS=y
67CONFIG_SYSVIPC_SYSCTL=y 64CONFIG_SYSVIPC_SYSCTL=y
68CONFIG_POSIX_MQUEUE=y 65CONFIG_POSIX_MQUEUE=y
69CONFIG_BSD_PROCESS_ACCT=y 66CONFIG_BSD_PROCESS_ACCT=y
70# CONFIG_BSD_PROCESS_ACCT_V3 is not set 67# CONFIG_BSD_PROCESS_ACCT_V3 is not set
71# CONFIG_TASKSTATS is not set 68# CONFIG_TASKSTATS is not set
72# CONFIG_UTS_NS is not set 69# CONFIG_USER_NS is not set
73CONFIG_AUDIT=y 70CONFIG_AUDIT=y
74# CONFIG_AUDITSYSCALL is not set 71# CONFIG_AUDITSYSCALL is not set
75CONFIG_IKCONFIG=y 72CONFIG_IKCONFIG=y
@@ -86,7 +83,7 @@ CONFIG_SYSCTL_SYSCALL=y
86CONFIG_KALLSYMS=y 83CONFIG_KALLSYMS=y
87CONFIG_KALLSYMS_ALL=y 84CONFIG_KALLSYMS_ALL=y
88# CONFIG_KALLSYMS_EXTRA_PASS is not set 85# CONFIG_KALLSYMS_EXTRA_PASS is not set
89# CONFIG_HOTPLUG is not set 86CONFIG_HOTPLUG=y
90CONFIG_PRINTK=y 87CONFIG_PRINTK=y
91CONFIG_BUG=y 88CONFIG_BUG=y
92CONFIG_ELF_CORE=y 89CONFIG_ELF_CORE=y
@@ -105,24 +102,17 @@ CONFIG_SLAB=y
105CONFIG_RT_MUTEXES=y 102CONFIG_RT_MUTEXES=y
106# CONFIG_TINY_SHMEM is not set 103# CONFIG_TINY_SHMEM is not set
107CONFIG_BASE_SMALL=0 104CONFIG_BASE_SMALL=0
108
109#
110# Loadable module support
111#
112CONFIG_MODULES=y 105CONFIG_MODULES=y
113CONFIG_MODULE_UNLOAD=y 106CONFIG_MODULE_UNLOAD=y
114CONFIG_MODULE_FORCE_UNLOAD=y 107CONFIG_MODULE_FORCE_UNLOAD=y
115CONFIG_MODVERSIONS=y 108CONFIG_MODVERSIONS=y
116# CONFIG_MODULE_SRCVERSION_ALL is not set 109# CONFIG_MODULE_SRCVERSION_ALL is not set
117CONFIG_KMOD=y 110CONFIG_KMOD=y
118
119#
120# Block layer
121#
122CONFIG_BLOCK=y 111CONFIG_BLOCK=y
123CONFIG_LBD=y 112CONFIG_LBD=y
124# CONFIG_BLK_DEV_IO_TRACE is not set 113# CONFIG_BLK_DEV_IO_TRACE is not set
125# CONFIG_LSF is not set 114# CONFIG_LSF is not set
115# CONFIG_BLK_DEV_BSG is not set
126 116
127# 117#
128# IO Schedulers 118# IO Schedulers
@@ -153,7 +143,7 @@ CONFIG_MPC8544_DS=y
153CONFIG_MPC85xx=y 143CONFIG_MPC85xx=y
154CONFIG_MPIC=y 144CONFIG_MPIC=y
155# CONFIG_MPIC_WEIRD is not set 145# CONFIG_MPIC_WEIRD is not set
156# CONFIG_PPC_I8259 is not set 146CONFIG_PPC_I8259=y
157# CONFIG_PPC_RTAS is not set 147# CONFIG_PPC_RTAS is not set
158# CONFIG_MMIO_NVRAM is not set 148# CONFIG_MMIO_NVRAM is not set
159# CONFIG_PPC_MPC106 is not set 149# CONFIG_PPC_MPC106 is not set
@@ -191,6 +181,8 @@ CONFIG_FLAT_NODE_MEM_MAP=y
191CONFIG_SPLIT_PTLOCK_CPUS=4 181CONFIG_SPLIT_PTLOCK_CPUS=4
192# CONFIG_RESOURCES_64BIT is not set 182# CONFIG_RESOURCES_64BIT is not set
193CONFIG_ZONE_DMA_FLAG=1 183CONFIG_ZONE_DMA_FLAG=1
184CONFIG_BOUNCE=y
185CONFIG_VIRT_TO_BUS=y
194CONFIG_PROC_DEVICETREE=y 186CONFIG_PROC_DEVICETREE=y
195CONFIG_CMDLINE_BOOL=y 187CONFIG_CMDLINE_BOOL=y
196CONFIG_CMDLINE="root=/dev/sda3 rw console=ttyS0,115200" 188CONFIG_CMDLINE="root=/dev/sda3 rw console=ttyS0,115200"
@@ -205,15 +197,21 @@ CONFIG_ISA_DMA_API=y
205# 197#
206CONFIG_ZONE_DMA=y 198CONFIG_ZONE_DMA=y
207CONFIG_PPC_INDIRECT_PCI=y 199CONFIG_PPC_INDIRECT_PCI=y
208CONFIG_PPC_INDIRECT_PCI_BE=y
209CONFIG_FSL_SOC=y 200CONFIG_FSL_SOC=y
210# CONFIG_PCI is not set 201CONFIG_FSL_PCI=y
211# CONFIG_PCI_DOMAINS is not set 202CONFIG_PCI=y
212# CONFIG_ARCH_SUPPORTS_MSI is not set 203CONFIG_PCI_DOMAINS=y
204CONFIG_PCI_SYSCALL=y
205# CONFIG_PCIEPORTBUS is not set
206CONFIG_ARCH_SUPPORTS_MSI=y
207# CONFIG_PCI_MSI is not set
208# CONFIG_PCI_DEBUG is not set
213 209
214# 210#
215# PCCARD (PCMCIA/CardBus) support 211# PCCARD (PCMCIA/CardBus) support
216# 212#
213# CONFIG_PCCARD is not set
214# CONFIG_HOTPLUG_PCI is not set
217 215
218# 216#
219# Advanced setup 217# Advanced setup
@@ -254,7 +252,6 @@ CONFIG_ASK_IP_FIB_HASH=y
254CONFIG_IP_FIB_HASH=y 252CONFIG_IP_FIB_HASH=y
255CONFIG_IP_MULTIPLE_TABLES=y 253CONFIG_IP_MULTIPLE_TABLES=y
256CONFIG_IP_ROUTE_MULTIPATH=y 254CONFIG_IP_ROUTE_MULTIPATH=y
257# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
258CONFIG_IP_ROUTE_VERBOSE=y 255CONFIG_IP_ROUTE_VERBOSE=y
259CONFIG_IP_PNP=y 256CONFIG_IP_PNP=y
260CONFIG_IP_PNP_DHCP=y 257CONFIG_IP_PNP_DHCP=y
@@ -330,6 +327,7 @@ CONFIG_FIB_RULES=y
330# CONFIG_MAC80211 is not set 327# CONFIG_MAC80211 is not set
331# CONFIG_IEEE80211 is not set 328# CONFIG_IEEE80211 is not set
332# CONFIG_RFKILL is not set 329# CONFIG_RFKILL is not set
330# CONFIG_NET_9P is not set
333 331
334# 332#
335# Device Drivers 333# Device Drivers
@@ -340,45 +338,35 @@ CONFIG_FIB_RULES=y
340# 338#
341CONFIG_STANDALONE=y 339CONFIG_STANDALONE=y
342CONFIG_PREVENT_FIRMWARE_BUILD=y 340CONFIG_PREVENT_FIRMWARE_BUILD=y
341# CONFIG_FW_LOADER is not set
343# CONFIG_DEBUG_DRIVER is not set 342# CONFIG_DEBUG_DRIVER is not set
344# CONFIG_DEBUG_DEVRES is not set 343# CONFIG_DEBUG_DEVRES is not set
345# CONFIG_SYS_HYPERVISOR is not set 344# CONFIG_SYS_HYPERVISOR is not set
346
347#
348# Connector - unified userspace <-> kernelspace linker
349#
350# CONFIG_CONNECTOR is not set 345# CONFIG_CONNECTOR is not set
351# CONFIG_MTD is not set 346# CONFIG_MTD is not set
352
353#
354# Parallel port support
355#
356# CONFIG_PARPORT is not set 347# CONFIG_PARPORT is not set
357 348CONFIG_BLK_DEV=y
358#
359# Plug and Play support
360#
361# CONFIG_PNPACPI is not set
362
363#
364# Block devices
365#
366# CONFIG_BLK_DEV_FD is not set 349# CONFIG_BLK_DEV_FD is not set
350# CONFIG_BLK_CPQ_DA is not set
351# CONFIG_BLK_CPQ_CISS_DA is not set
352# CONFIG_BLK_DEV_DAC960 is not set
353# CONFIG_BLK_DEV_UMEM is not set
367# CONFIG_BLK_DEV_COW_COMMON is not set 354# CONFIG_BLK_DEV_COW_COMMON is not set
368CONFIG_BLK_DEV_LOOP=y 355CONFIG_BLK_DEV_LOOP=y
369# CONFIG_BLK_DEV_CRYPTOLOOP is not set 356# CONFIG_BLK_DEV_CRYPTOLOOP is not set
370CONFIG_BLK_DEV_NBD=y 357CONFIG_BLK_DEV_NBD=y
358# CONFIG_BLK_DEV_SX8 is not set
371CONFIG_BLK_DEV_RAM=y 359CONFIG_BLK_DEV_RAM=y
372CONFIG_BLK_DEV_RAM_COUNT=2 360CONFIG_BLK_DEV_RAM_COUNT=2
373CONFIG_BLK_DEV_RAM_SIZE=16384 361CONFIG_BLK_DEV_RAM_SIZE=16384
374CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 362CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
375# CONFIG_CDROM_PKTCDVD is not set 363# CONFIG_CDROM_PKTCDVD is not set
376# CONFIG_ATA_OVER_ETH is not set 364# CONFIG_ATA_OVER_ETH is not set
377 365CONFIG_MISC_DEVICES=y
378# 366# CONFIG_PHANTOM is not set
379# Misc devices 367# CONFIG_EEPROM_93CX6 is not set
380# 368# CONFIG_SGI_IOC4 is not set
381# CONFIG_BLINK is not set 369# CONFIG_TIFM_CORE is not set
382# CONFIG_IDE is not set 370# CONFIG_IDE is not set
383 371
384# 372#
@@ -386,6 +374,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
386# 374#
387# CONFIG_RAID_ATTRS is not set 375# CONFIG_RAID_ATTRS is not set
388CONFIG_SCSI=y 376CONFIG_SCSI=y
377CONFIG_SCSI_DMA=y
389# CONFIG_SCSI_TGT is not set 378# CONFIG_SCSI_TGT is not set
390# CONFIG_SCSI_NETLINK is not set 379# CONFIG_SCSI_NETLINK is not set
391CONFIG_SCSI_PROC_FS=y 380CONFIG_SCSI_PROC_FS=y
@@ -422,25 +411,120 @@ CONFIG_SCSI_WAIT_SCAN=m
422# SCSI low-level drivers 411# SCSI low-level drivers
423# 412#
424# CONFIG_ISCSI_TCP is not set 413# CONFIG_ISCSI_TCP is not set
414# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
415# CONFIG_SCSI_3W_9XXX is not set
416# CONFIG_SCSI_ACARD is not set
417# CONFIG_SCSI_AACRAID is not set
418# CONFIG_SCSI_AIC7XXX is not set
419# CONFIG_SCSI_AIC7XXX_OLD is not set
420# CONFIG_SCSI_AIC79XX is not set
421# CONFIG_SCSI_AIC94XX is not set
422# CONFIG_SCSI_DPT_I2O is not set
423# CONFIG_SCSI_ARCMSR is not set
424# CONFIG_MEGARAID_NEWGEN is not set
425# CONFIG_MEGARAID_LEGACY is not set
426# CONFIG_MEGARAID_SAS is not set
427# CONFIG_SCSI_HPTIOP is not set
428# CONFIG_SCSI_BUSLOGIC is not set
429# CONFIG_SCSI_DMX3191D is not set
430# CONFIG_SCSI_EATA is not set
431# CONFIG_SCSI_FUTURE_DOMAIN is not set
432# CONFIG_SCSI_GDTH is not set
433# CONFIG_SCSI_IPS is not set
434# CONFIG_SCSI_INITIO is not set
435# CONFIG_SCSI_INIA100 is not set
436# CONFIG_SCSI_STEX is not set
437# CONFIG_SCSI_SYM53C8XX_2 is not set
438# CONFIG_SCSI_IPR is not set
439# CONFIG_SCSI_QLOGIC_1280 is not set
440# CONFIG_SCSI_QLA_FC is not set
441# CONFIG_SCSI_QLA_ISCSI is not set
442# CONFIG_SCSI_LPFC is not set
443# CONFIG_SCSI_DC395x is not set
444# CONFIG_SCSI_DC390T is not set
445# CONFIG_SCSI_NSP32 is not set
425# CONFIG_SCSI_DEBUG is not set 446# CONFIG_SCSI_DEBUG is not set
447# CONFIG_SCSI_SRP is not set
426CONFIG_ATA=y 448CONFIG_ATA=y
427# CONFIG_ATA_NONSTANDARD is not set 449# CONFIG_ATA_NONSTANDARD is not set
450# CONFIG_SATA_AHCI is not set
451# CONFIG_SATA_SVW is not set
452# CONFIG_ATA_PIIX is not set
453# CONFIG_SATA_MV is not set
454# CONFIG_SATA_NV is not set
455# CONFIG_PDC_ADMA is not set
456# CONFIG_SATA_QSTOR is not set
457# CONFIG_SATA_PROMISE is not set
458# CONFIG_SATA_SX4 is not set
459# CONFIG_SATA_SIL is not set
460# CONFIG_SATA_SIL24 is not set
461# CONFIG_SATA_SIS is not set
462# CONFIG_SATA_ULI is not set
463# CONFIG_SATA_VIA is not set
464# CONFIG_SATA_VITESSE is not set
465# CONFIG_SATA_INIC162X is not set
466# CONFIG_PATA_ALI is not set
467# CONFIG_PATA_AMD is not set
468# CONFIG_PATA_ARTOP is not set
469# CONFIG_PATA_ATIIXP is not set
470# CONFIG_PATA_CMD640_PCI is not set
471# CONFIG_PATA_CMD64X is not set
472# CONFIG_PATA_CS5520 is not set
473# CONFIG_PATA_CS5530 is not set
474# CONFIG_PATA_CYPRESS is not set
475# CONFIG_PATA_EFAR is not set
476# CONFIG_ATA_GENERIC is not set
477# CONFIG_PATA_HPT366 is not set
478# CONFIG_PATA_HPT37X is not set
479# CONFIG_PATA_HPT3X2N is not set
480# CONFIG_PATA_HPT3X3 is not set
481# CONFIG_PATA_IT821X is not set
482# CONFIG_PATA_IT8213 is not set
483# CONFIG_PATA_JMICRON is not set
484# CONFIG_PATA_TRIFLEX is not set
485# CONFIG_PATA_MARVELL is not set
486# CONFIG_PATA_MPIIX is not set
487# CONFIG_PATA_OLDPIIX is not set
488# CONFIG_PATA_NETCELL is not set
489# CONFIG_PATA_NS87410 is not set
490# CONFIG_PATA_OPTI is not set
491# CONFIG_PATA_OPTIDMA is not set
492# CONFIG_PATA_PDC_OLD is not set
493# CONFIG_PATA_RADISYS is not set
494# CONFIG_PATA_RZ1000 is not set
495# CONFIG_PATA_SC1200 is not set
496# CONFIG_PATA_SERVERWORKS is not set
497# CONFIG_PATA_PDC2027X is not set
498# CONFIG_PATA_SIL680 is not set
499# CONFIG_PATA_SIS is not set
500# CONFIG_PATA_VIA is not set
501# CONFIG_PATA_WINBOND is not set
428# CONFIG_PATA_PLATFORM is not set 502# CONFIG_PATA_PLATFORM is not set
503# CONFIG_MD is not set
429 504
430# 505#
431# Multi-device support (RAID and LVM) 506# Fusion MPT device support
432# 507#
433# CONFIG_MD is not set 508# CONFIG_FUSION is not set
434# CONFIG_MACINTOSH_DRIVERS is not set 509# CONFIG_FUSION_SPI is not set
510# CONFIG_FUSION_FC is not set
511# CONFIG_FUSION_SAS is not set
435 512
436# 513#
437# Network device support 514# IEEE 1394 (FireWire) support
438# 515#
516# CONFIG_FIREWIRE is not set
517# CONFIG_IEEE1394 is not set
518# CONFIG_I2O is not set
519# CONFIG_MACINTOSH_DRIVERS is not set
439CONFIG_NETDEVICES=y 520CONFIG_NETDEVICES=y
521# CONFIG_NETDEVICES_MULTIQUEUE is not set
440# CONFIG_DUMMY is not set 522# CONFIG_DUMMY is not set
441# CONFIG_BONDING is not set 523# CONFIG_BONDING is not set
524# CONFIG_MACVLAN is not set
442# CONFIG_EQUALIZER is not set 525# CONFIG_EQUALIZER is not set
443# CONFIG_TUN is not set 526# CONFIG_TUN is not set
527# CONFIG_ARCNET is not set
444CONFIG_PHYLIB=y 528CONFIG_PHYLIB=y
445 529
446# 530#
@@ -454,17 +538,44 @@ CONFIG_PHYLIB=y
454CONFIG_VITESSE_PHY=y 538CONFIG_VITESSE_PHY=y
455# CONFIG_SMSC_PHY is not set 539# CONFIG_SMSC_PHY is not set
456# CONFIG_BROADCOM_PHY is not set 540# CONFIG_BROADCOM_PHY is not set
541# CONFIG_ICPLUS_PHY is not set
457# CONFIG_FIXED_PHY is not set 542# CONFIG_FIXED_PHY is not set
458
459#
460# Ethernet (10 or 100Mbit)
461#
462CONFIG_NET_ETHERNET=y 543CONFIG_NET_ETHERNET=y
463CONFIG_MII=y 544CONFIG_MII=y
545# CONFIG_HAPPYMEAL is not set
546# CONFIG_SUNGEM is not set
547# CONFIG_CASSINI is not set
548# CONFIG_NET_VENDOR_3COM is not set
549# CONFIG_NET_TULIP is not set
550# CONFIG_HP100 is not set
551# CONFIG_NET_PCI is not set
464CONFIG_NETDEV_1000=y 552CONFIG_NETDEV_1000=y
553# CONFIG_ACENIC is not set
554# CONFIG_DL2K is not set
555# CONFIG_E1000 is not set
556# CONFIG_NS83820 is not set
557# CONFIG_HAMACHI is not set
558# CONFIG_YELLOWFIN is not set
559# CONFIG_R8169 is not set
560# CONFIG_SIS190 is not set
561# CONFIG_SKGE is not set
562# CONFIG_SKY2 is not set
563# CONFIG_VIA_VELOCITY is not set
564# CONFIG_TIGON3 is not set
565# CONFIG_BNX2 is not set
465CONFIG_GIANFAR=y 566CONFIG_GIANFAR=y
466CONFIG_GFAR_NAPI=y 567CONFIG_GFAR_NAPI=y
568# CONFIG_QLA3XXX is not set
569# CONFIG_ATL1 is not set
467CONFIG_NETDEV_10000=y 570CONFIG_NETDEV_10000=y
571# CONFIG_CHELSIO_T1 is not set
572# CONFIG_CHELSIO_T3 is not set
573# CONFIG_IXGB is not set
574# CONFIG_S2IO is not set
575# CONFIG_MYRI10GE is not set
576# CONFIG_NETXEN_NIC is not set
577# CONFIG_MLX4_CORE is not set
578# CONFIG_TR is not set
468 579
469# 580#
470# Wireless LAN 581# Wireless LAN
@@ -472,21 +583,16 @@ CONFIG_NETDEV_10000=y
472# CONFIG_WLAN_PRE80211 is not set 583# CONFIG_WLAN_PRE80211 is not set
473# CONFIG_WLAN_80211 is not set 584# CONFIG_WLAN_80211 is not set
474# CONFIG_WAN is not set 585# CONFIG_WAN is not set
586# CONFIG_FDDI is not set
587# CONFIG_HIPPI is not set
475# CONFIG_PPP is not set 588# CONFIG_PPP is not set
476# CONFIG_SLIP is not set 589# CONFIG_SLIP is not set
590# CONFIG_NET_FC is not set
477# CONFIG_SHAPER is not set 591# CONFIG_SHAPER is not set
478# CONFIG_NETCONSOLE is not set 592# CONFIG_NETCONSOLE is not set
479# CONFIG_NETPOLL is not set 593# CONFIG_NETPOLL is not set
480# CONFIG_NET_POLL_CONTROLLER is not set 594# CONFIG_NET_POLL_CONTROLLER is not set
481
482#
483# ISDN subsystem
484#
485# CONFIG_ISDN is not set 595# CONFIG_ISDN is not set
486
487#
488# Telephony Support
489#
490# CONFIG_PHONE is not set 596# CONFIG_PHONE is not set
491 597
492# 598#
@@ -521,6 +627,7 @@ CONFIG_INPUT=y
521CONFIG_SERIO=y 627CONFIG_SERIO=y
522CONFIG_SERIO_I8042=y 628CONFIG_SERIO_I8042=y
523CONFIG_SERIO_SERPORT=y 629CONFIG_SERIO_SERPORT=y
630# CONFIG_SERIO_PCIPS2 is not set
524CONFIG_SERIO_LIBPS2=y 631CONFIG_SERIO_LIBPS2=y
525# CONFIG_SERIO_RAW is not set 632# CONFIG_SERIO_RAW is not set
526# CONFIG_GAMEPORT is not set 633# CONFIG_GAMEPORT is not set
@@ -539,6 +646,7 @@ CONFIG_HW_CONSOLE=y
539# 646#
540CONFIG_SERIAL_8250=y 647CONFIG_SERIAL_8250=y
541CONFIG_SERIAL_8250_CONSOLE=y 648CONFIG_SERIAL_8250_CONSOLE=y
649CONFIG_SERIAL_8250_PCI=y
542CONFIG_SERIAL_8250_NR_UARTS=4 650CONFIG_SERIAL_8250_NR_UARTS=4
543CONFIG_SERIAL_8250_RUNTIME_UARTS=4 651CONFIG_SERIAL_8250_RUNTIME_UARTS=4
544# CONFIG_SERIAL_8250_EXTENDED is not set 652# CONFIG_SERIAL_8250_EXTENDED is not set
@@ -550,14 +658,11 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
550# CONFIG_SERIAL_UARTLITE is not set 658# CONFIG_SERIAL_UARTLITE is not set
551CONFIG_SERIAL_CORE=y 659CONFIG_SERIAL_CORE=y
552CONFIG_SERIAL_CORE_CONSOLE=y 660CONFIG_SERIAL_CORE_CONSOLE=y
661# CONFIG_SERIAL_JSM is not set
553# CONFIG_SERIAL_OF_PLATFORM is not set 662# CONFIG_SERIAL_OF_PLATFORM is not set
554CONFIG_UNIX98_PTYS=y 663CONFIG_UNIX98_PTYS=y
555CONFIG_LEGACY_PTYS=y 664CONFIG_LEGACY_PTYS=y
556CONFIG_LEGACY_PTY_COUNT=256 665CONFIG_LEGACY_PTY_COUNT=256
557
558#
559# IPMI
560#
561# CONFIG_IPMI_HANDLER is not set 666# CONFIG_IPMI_HANDLER is not set
562# CONFIG_WATCHDOG is not set 667# CONFIG_WATCHDOG is not set
563# CONFIG_HW_RANDOM is not set 668# CONFIG_HW_RANDOM is not set
@@ -565,12 +670,12 @@ CONFIG_NVRAM=y
565CONFIG_GEN_RTC=y 670CONFIG_GEN_RTC=y
566CONFIG_GEN_RTC_X=y 671CONFIG_GEN_RTC_X=y
567# CONFIG_R3964 is not set 672# CONFIG_R3964 is not set
673# CONFIG_APPLICOM is not set
674# CONFIG_AGP is not set
675# CONFIG_DRM is not set
568# CONFIG_RAW_DRIVER is not set 676# CONFIG_RAW_DRIVER is not set
569
570#
571# TPM devices
572#
573# CONFIG_TCG_TPM is not set 677# CONFIG_TCG_TPM is not set
678CONFIG_DEVPORT=y
574# CONFIG_I2C is not set 679# CONFIG_I2C is not set
575 680
576# 681#
@@ -578,11 +683,8 @@ CONFIG_GEN_RTC_X=y
578# 683#
579# CONFIG_SPI is not set 684# CONFIG_SPI is not set
580# CONFIG_SPI_MASTER is not set 685# CONFIG_SPI_MASTER is not set
581
582#
583# Dallas's 1-wire bus
584#
585# CONFIG_W1 is not set 686# CONFIG_W1 is not set
687# CONFIG_POWER_SUPPLY is not set
586# CONFIG_HWMON is not set 688# CONFIG_HWMON is not set
587 689
588# 690#
@@ -655,19 +757,14 @@ CONFIG_DUMMY_CONSOLE=y
655# Sound 757# Sound
656# 758#
657# CONFIG_SOUND is not set 759# CONFIG_SOUND is not set
658 760CONFIG_HID_SUPPORT=y
659#
660# HID Devices
661#
662CONFIG_HID=y 761CONFIG_HID=y
663# CONFIG_HID_DEBUG is not set 762# CONFIG_HID_DEBUG is not set
664 763CONFIG_USB_SUPPORT=y
665# 764CONFIG_USB_ARCH_HAS_HCD=y
666# USB support 765CONFIG_USB_ARCH_HAS_OHCI=y
667# 766CONFIG_USB_ARCH_HAS_EHCI=y
668# CONFIG_USB_ARCH_HAS_HCD is not set 767# CONFIG_USB is not set
669# CONFIG_USB_ARCH_HAS_OHCI is not set
670# CONFIG_USB_ARCH_HAS_EHCI is not set
671 768
672# 769#
673# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 770# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -691,14 +788,7 @@ CONFIG_HID=y
691# 788#
692# LED Triggers 789# LED Triggers
693# 790#
694 791# CONFIG_INFINIBAND is not set
695#
696# InfiniBand support
697#
698
699#
700# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
701#
702 792
703# 793#
704# Real Time Clock 794# Real Time Clock
@@ -719,19 +809,13 @@ CONFIG_RTC_INTF_DEV=y
719# CONFIG_RTC_DRV_TEST is not set 809# CONFIG_RTC_DRV_TEST is not set
720 810
721# 811#
722# I2C RTC drivers
723#
724
725#
726# SPI RTC drivers
727#
728
729#
730# Platform RTC drivers 812# Platform RTC drivers
731# 813#
814# CONFIG_RTC_DRV_CMOS is not set
732# CONFIG_RTC_DRV_DS1553 is not set 815# CONFIG_RTC_DRV_DS1553 is not set
733# CONFIG_RTC_DRV_DS1742 is not set 816# CONFIG_RTC_DRV_DS1742 is not set
734# CONFIG_RTC_DRV_M48T86 is not set 817# CONFIG_RTC_DRV_M48T86 is not set
818# CONFIG_RTC_DRV_M48T59 is not set
735# CONFIG_RTC_DRV_V3020 is not set 819# CONFIG_RTC_DRV_V3020 is not set
736 820
737# 821#
@@ -752,6 +836,11 @@ CONFIG_RTC_INTF_DEV=y
752# 836#
753 837
754# 838#
839# Userspace I/O
840#
841# CONFIG_UIO is not set
842
843#
755# File systems 844# File systems
756# 845#
757CONFIG_EXT2_FS=y 846CONFIG_EXT2_FS=y
@@ -859,7 +948,6 @@ CONFIG_RPCSEC_GSS_KRB5=y
859# CONFIG_NCP_FS is not set 948# CONFIG_NCP_FS is not set
860# CONFIG_CODA_FS is not set 949# CONFIG_CODA_FS is not set
861# CONFIG_AFS_FS is not set 950# CONFIG_AFS_FS is not set
862# CONFIG_9P_FS is not set
863 951
864# 952#
865# Partition Types 953# Partition Types
@@ -941,6 +1029,7 @@ CONFIG_BITREVERSE=y
941# CONFIG_CRC16 is not set 1029# CONFIG_CRC16 is not set
942# CONFIG_CRC_ITU_T is not set 1030# CONFIG_CRC_ITU_T is not set
943CONFIG_CRC32=y 1031CONFIG_CRC32=y
1032# CONFIG_CRC7 is not set
944CONFIG_LIBCRC32C=m 1033CONFIG_LIBCRC32C=m
945CONFIG_ZLIB_INFLATE=y 1034CONFIG_ZLIB_INFLATE=y
946CONFIG_PLIST=y 1035CONFIG_PLIST=y
@@ -965,6 +1054,7 @@ CONFIG_ENABLE_MUST_CHECK=y
965CONFIG_DEBUG_KERNEL=y 1054CONFIG_DEBUG_KERNEL=y
966# CONFIG_DEBUG_SHIRQ is not set 1055# CONFIG_DEBUG_SHIRQ is not set
967CONFIG_DETECT_SOFTLOCKUP=y 1056CONFIG_DETECT_SOFTLOCKUP=y
1057CONFIG_SCHED_DEBUG=y
968# CONFIG_SCHEDSTATS is not set 1058# CONFIG_SCHEDSTATS is not set
969# CONFIG_TIMER_STATS is not set 1059# CONFIG_TIMER_STATS is not set
970# CONFIG_DEBUG_SLAB is not set 1060# CONFIG_DEBUG_SLAB is not set
@@ -996,10 +1086,6 @@ CONFIG_FORCED_INLINING=y
996# 1086#
997# CONFIG_KEYS is not set 1087# CONFIG_KEYS is not set
998# CONFIG_SECURITY is not set 1088# CONFIG_SECURITY is not set
999
1000#
1001# Cryptographic options
1002#
1003CONFIG_CRYPTO=y 1089CONFIG_CRYPTO=y
1004CONFIG_CRYPTO_ALGAPI=y 1090CONFIG_CRYPTO_ALGAPI=y
1005CONFIG_CRYPTO_BLKCIPHER=y 1091CONFIG_CRYPTO_BLKCIPHER=y
@@ -1038,7 +1124,4 @@ CONFIG_CRYPTO_DES=y
1038# CONFIG_CRYPTO_CRC32C is not set 1124# CONFIG_CRYPTO_CRC32C is not set
1039# CONFIG_CRYPTO_CAMELLIA is not set 1125# CONFIG_CRYPTO_CAMELLIA is not set
1040# CONFIG_CRYPTO_TEST is not set 1126# CONFIG_CRYPTO_TEST is not set
1041 1127CONFIG_CRYPTO_HW=y
1042#
1043# Hardware crypto devices
1044#
diff --git a/arch/powerpc/configs/mpc8568mds_defconfig b/arch/powerpc/configs/mpc8568mds_defconfig
index 6451d4dd28a0..417d3e6abcdf 100644
--- a/arch/powerpc/configs/mpc8568mds_defconfig
+++ b/arch/powerpc/configs/mpc8568mds_defconfig
@@ -1,9 +1,26 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22-rc7 3# Linux kernel version: 2.6.22
4# Sun Jul 1 23:56:59 2007 4# Fri Jul 20 13:55:04 2007
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7
8#
9# Processor support
10#
11# CONFIG_6xx is not set
12CONFIG_PPC_85xx=y
13# CONFIG_PPC_8xx is not set
14# CONFIG_40x is not set
15# CONFIG_44x is not set
16# CONFIG_E200 is not set
17CONFIG_85xx=y
18CONFIG_E500=y
19CONFIG_BOOKE=y
20CONFIG_FSL_BOOKE=y
21# CONFIG_PHYS_64BIT is not set
22CONFIG_SPE=y
23# CONFIG_PPC_MM_SLICES is not set
7CONFIG_PPC32=y 24CONFIG_PPC32=y
8CONFIG_PPC_MERGE=y 25CONFIG_PPC_MERGE=y
9CONFIG_MMU=y 26CONFIG_MMU=y
@@ -14,6 +31,7 @@ CONFIG_ARCH_HAS_ILOG2_U32=y
14CONFIG_GENERIC_HWEIGHT=y 31CONFIG_GENERIC_HWEIGHT=y
15CONFIG_GENERIC_CALIBRATE_DELAY=y 32CONFIG_GENERIC_CALIBRATE_DELAY=y
16CONFIG_GENERIC_FIND_NEXT_BIT=y 33CONFIG_GENERIC_FIND_NEXT_BIT=y
34# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
17CONFIG_PPC=y 35CONFIG_PPC=y
18CONFIG_EARLY_PRINTK=y 36CONFIG_EARLY_PRINTK=y
19CONFIG_GENERIC_NVRAM=y 37CONFIG_GENERIC_NVRAM=y
@@ -25,28 +43,8 @@ CONFIG_PPC_UDBG_16550=y
25CONFIG_AUDIT_ARCH=y 43CONFIG_AUDIT_ARCH=y
26CONFIG_GENERIC_BUG=y 44CONFIG_GENERIC_BUG=y
27CONFIG_DEFAULT_UIMAGE=y 45CONFIG_DEFAULT_UIMAGE=y
28
29#
30# Processor support
31#
32# CONFIG_CLASSIC32 is not set
33# CONFIG_PPC_82xx is not set
34# CONFIG_PPC_83xx is not set
35CONFIG_PPC_85xx=y
36# CONFIG_PPC_86xx is not set
37# CONFIG_PPC_8xx is not set
38# CONFIG_40x is not set
39# CONFIG_44x is not set
40# CONFIG_E200 is not set
41CONFIG_85xx=y
42CONFIG_E500=y
43# CONFIG_PPC_DCR_NATIVE is not set 46# CONFIG_PPC_DCR_NATIVE is not set
44# CONFIG_PPC_DCR_MMIO is not set 47# CONFIG_PPC_DCR_MMIO is not set
45CONFIG_BOOKE=y
46CONFIG_FSL_BOOKE=y
47# CONFIG_PHYS_64BIT is not set
48CONFIG_SPE=y
49# CONFIG_PPC_MM_SLICES is not set
50CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 48CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
51 49
52# 50#
@@ -63,12 +61,11 @@ CONFIG_LOCALVERSION=""
63CONFIG_LOCALVERSION_AUTO=y 61CONFIG_LOCALVERSION_AUTO=y
64CONFIG_SWAP=y 62CONFIG_SWAP=y
65CONFIG_SYSVIPC=y 63CONFIG_SYSVIPC=y
66# CONFIG_IPC_NS is not set
67CONFIG_SYSVIPC_SYSCTL=y 64CONFIG_SYSVIPC_SYSCTL=y
68# CONFIG_POSIX_MQUEUE is not set 65# CONFIG_POSIX_MQUEUE is not set
69# CONFIG_BSD_PROCESS_ACCT is not set 66# CONFIG_BSD_PROCESS_ACCT is not set
70# CONFIG_TASKSTATS is not set 67# CONFIG_TASKSTATS is not set
71# CONFIG_UTS_NS is not set 68# CONFIG_USER_NS is not set
72# CONFIG_AUDIT is not set 69# CONFIG_AUDIT is not set
73# CONFIG_IKCONFIG is not set 70# CONFIG_IKCONFIG is not set
74CONFIG_LOG_BUF_SHIFT=14 71CONFIG_LOG_BUF_SHIFT=14
@@ -100,24 +97,17 @@ CONFIG_SLAB=y
100CONFIG_RT_MUTEXES=y 97CONFIG_RT_MUTEXES=y
101# CONFIG_TINY_SHMEM is not set 98# CONFIG_TINY_SHMEM is not set
102CONFIG_BASE_SMALL=0 99CONFIG_BASE_SMALL=0
103
104#
105# Loadable module support
106#
107CONFIG_MODULES=y 100CONFIG_MODULES=y
108CONFIG_MODULE_UNLOAD=y 101CONFIG_MODULE_UNLOAD=y
109# CONFIG_MODULE_FORCE_UNLOAD is not set 102# CONFIG_MODULE_FORCE_UNLOAD is not set
110# CONFIG_MODVERSIONS is not set 103# CONFIG_MODVERSIONS is not set
111# CONFIG_MODULE_SRCVERSION_ALL is not set 104# CONFIG_MODULE_SRCVERSION_ALL is not set
112# CONFIG_KMOD is not set 105# CONFIG_KMOD is not set
113
114#
115# Block layer
116#
117CONFIG_BLOCK=y 106CONFIG_BLOCK=y
118# CONFIG_LBD is not set 107# CONFIG_LBD is not set
119# CONFIG_BLK_DEV_IO_TRACE is not set 108# CONFIG_BLK_DEV_IO_TRACE is not set
120# CONFIG_LSF is not set 109# CONFIG_LSF is not set
110# CONFIG_BLK_DEV_BSG is not set
121 111
122# 112#
123# IO Schedulers 113# IO Schedulers
@@ -186,6 +176,8 @@ CONFIG_FLAT_NODE_MEM_MAP=y
186CONFIG_SPLIT_PTLOCK_CPUS=4 176CONFIG_SPLIT_PTLOCK_CPUS=4
187# CONFIG_RESOURCES_64BIT is not set 177# CONFIG_RESOURCES_64BIT is not set
188CONFIG_ZONE_DMA_FLAG=1 178CONFIG_ZONE_DMA_FLAG=1
179CONFIG_BOUNCE=y
180CONFIG_VIRT_TO_BUS=y
189CONFIG_PROC_DEVICETREE=y 181CONFIG_PROC_DEVICETREE=y
190# CONFIG_CMDLINE_BOOL is not set 182# CONFIG_CMDLINE_BOOL is not set
191# CONFIG_PM is not set 183# CONFIG_PM is not set
@@ -201,14 +193,20 @@ CONFIG_ZONE_DMA=y
201CONFIG_PPC_INDIRECT_PCI=y 193CONFIG_PPC_INDIRECT_PCI=y
202CONFIG_PPC_INDIRECT_PCI_BE=y 194CONFIG_PPC_INDIRECT_PCI_BE=y
203CONFIG_FSL_SOC=y 195CONFIG_FSL_SOC=y
204# CONFIG_PCI is not set 196CONFIG_FSL_PCI=y
205# CONFIG_PCI_DOMAINS is not set 197CONFIG_PCI=y
206# CONFIG_ARCH_SUPPORTS_MSI is not set 198CONFIG_PCI_DOMAINS=y
199CONFIG_PCI_SYSCALL=y
200# CONFIG_PCIEPORTBUS is not set
201CONFIG_ARCH_SUPPORTS_MSI=y
202# CONFIG_PCI_MSI is not set
203# CONFIG_PCI_DEBUG is not set
207 204
208# 205#
209# PCCARD (PCMCIA/CardBus) support 206# PCCARD (PCMCIA/CardBus) support
210# 207#
211# CONFIG_PCCARD is not set 208# CONFIG_PCCARD is not set
209# CONFIG_HOTPLUG_PCI is not set
212 210
213# 211#
214# Advanced setup 212# Advanced setup
@@ -309,6 +307,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
309# CONFIG_MAC80211 is not set 307# CONFIG_MAC80211 is not set
310# CONFIG_IEEE80211 is not set 308# CONFIG_IEEE80211 is not set
311# CONFIG_RFKILL is not set 309# CONFIG_RFKILL is not set
310# CONFIG_NET_9P is not set
312 311
313# 312#
314# Device Drivers 313# Device Drivers
@@ -323,42 +322,31 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
323# CONFIG_DEBUG_DRIVER is not set 322# CONFIG_DEBUG_DRIVER is not set
324# CONFIG_DEBUG_DEVRES is not set 323# CONFIG_DEBUG_DEVRES is not set
325# CONFIG_SYS_HYPERVISOR is not set 324# CONFIG_SYS_HYPERVISOR is not set
326
327#
328# Connector - unified userspace <-> kernelspace linker
329#
330# CONFIG_CONNECTOR is not set 325# CONFIG_CONNECTOR is not set
331# CONFIG_MTD is not set 326# CONFIG_MTD is not set
332
333#
334# Parallel port support
335#
336# CONFIG_PARPORT is not set 327# CONFIG_PARPORT is not set
337 328CONFIG_BLK_DEV=y
338#
339# Plug and Play support
340#
341# CONFIG_PNPACPI is not set
342
343#
344# Block devices
345#
346# CONFIG_BLK_DEV_FD is not set 329# CONFIG_BLK_DEV_FD is not set
330# CONFIG_BLK_CPQ_DA is not set
331# CONFIG_BLK_CPQ_CISS_DA is not set
332# CONFIG_BLK_DEV_DAC960 is not set
333# CONFIG_BLK_DEV_UMEM is not set
347# CONFIG_BLK_DEV_COW_COMMON is not set 334# CONFIG_BLK_DEV_COW_COMMON is not set
348CONFIG_BLK_DEV_LOOP=y 335CONFIG_BLK_DEV_LOOP=y
349# CONFIG_BLK_DEV_CRYPTOLOOP is not set 336# CONFIG_BLK_DEV_CRYPTOLOOP is not set
350# CONFIG_BLK_DEV_NBD is not set 337# CONFIG_BLK_DEV_NBD is not set
338# CONFIG_BLK_DEV_SX8 is not set
351CONFIG_BLK_DEV_RAM=y 339CONFIG_BLK_DEV_RAM=y
352CONFIG_BLK_DEV_RAM_COUNT=16 340CONFIG_BLK_DEV_RAM_COUNT=16
353CONFIG_BLK_DEV_RAM_SIZE=32768 341CONFIG_BLK_DEV_RAM_SIZE=32768
354CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 342CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
355# CONFIG_CDROM_PKTCDVD is not set 343# CONFIG_CDROM_PKTCDVD is not set
356# CONFIG_ATA_OVER_ETH is not set 344# CONFIG_ATA_OVER_ETH is not set
357 345CONFIG_MISC_DEVICES=y
358# 346# CONFIG_PHANTOM is not set
359# Misc devices 347# CONFIG_EEPROM_93CX6 is not set
360# 348# CONFIG_SGI_IOC4 is not set
361# CONFIG_BLINK is not set 349# CONFIG_TIFM_CORE is not set
362# CONFIG_IDE is not set 350# CONFIG_IDE is not set
363 351
364# 352#
@@ -366,6 +354,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
366# 354#
367# CONFIG_RAID_ATTRS is not set 355# CONFIG_RAID_ATTRS is not set
368CONFIG_SCSI=y 356CONFIG_SCSI=y
357CONFIG_SCSI_DMA=y
369# CONFIG_SCSI_TGT is not set 358# CONFIG_SCSI_TGT is not set
370# CONFIG_SCSI_NETLINK is not set 359# CONFIG_SCSI_NETLINK is not set
371CONFIG_SCSI_PROC_FS=y 360CONFIG_SCSI_PROC_FS=y
@@ -402,23 +391,65 @@ CONFIG_SCSI_WAIT_SCAN=m
402# SCSI low-level drivers 391# SCSI low-level drivers
403# 392#
404# CONFIG_ISCSI_TCP is not set 393# CONFIG_ISCSI_TCP is not set
394# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
395# CONFIG_SCSI_3W_9XXX is not set
396# CONFIG_SCSI_ACARD is not set
397# CONFIG_SCSI_AACRAID is not set
398# CONFIG_SCSI_AIC7XXX is not set
399# CONFIG_SCSI_AIC7XXX_OLD is not set
400# CONFIG_SCSI_AIC79XX is not set
401# CONFIG_SCSI_AIC94XX is not set
402# CONFIG_SCSI_DPT_I2O is not set
403# CONFIG_SCSI_ARCMSR is not set
404# CONFIG_MEGARAID_NEWGEN is not set
405# CONFIG_MEGARAID_LEGACY is not set
406# CONFIG_MEGARAID_SAS is not set
407# CONFIG_SCSI_HPTIOP is not set
408# CONFIG_SCSI_BUSLOGIC is not set
409# CONFIG_SCSI_DMX3191D is not set
410# CONFIG_SCSI_EATA is not set
411# CONFIG_SCSI_FUTURE_DOMAIN is not set
412# CONFIG_SCSI_GDTH is not set
413# CONFIG_SCSI_IPS is not set
414# CONFIG_SCSI_INITIO is not set
415# CONFIG_SCSI_INIA100 is not set
416# CONFIG_SCSI_STEX is not set
417# CONFIG_SCSI_SYM53C8XX_2 is not set
418# CONFIG_SCSI_QLOGIC_1280 is not set
419# CONFIG_SCSI_QLA_FC is not set
420# CONFIG_SCSI_QLA_ISCSI is not set
421# CONFIG_SCSI_LPFC is not set
422# CONFIG_SCSI_DC395x is not set
423# CONFIG_SCSI_DC390T is not set
424# CONFIG_SCSI_NSP32 is not set
405# CONFIG_SCSI_DEBUG is not set 425# CONFIG_SCSI_DEBUG is not set
426# CONFIG_SCSI_SRP is not set
406# CONFIG_ATA is not set 427# CONFIG_ATA is not set
428# CONFIG_MD is not set
407 429
408# 430#
409# Multi-device support (RAID and LVM) 431# Fusion MPT device support
410# 432#
411# CONFIG_MD is not set 433# CONFIG_FUSION is not set
412# CONFIG_MACINTOSH_DRIVERS is not set 434# CONFIG_FUSION_SPI is not set
435# CONFIG_FUSION_FC is not set
436# CONFIG_FUSION_SAS is not set
413 437
414# 438#
415# Network device support 439# IEEE 1394 (FireWire) support
416# 440#
441# CONFIG_FIREWIRE is not set
442# CONFIG_IEEE1394 is not set
443# CONFIG_I2O is not set
444# CONFIG_MACINTOSH_DRIVERS is not set
417CONFIG_NETDEVICES=y 445CONFIG_NETDEVICES=y
446# CONFIG_NETDEVICES_MULTIQUEUE is not set
418# CONFIG_DUMMY is not set 447# CONFIG_DUMMY is not set
419# CONFIG_BONDING is not set 448# CONFIG_BONDING is not set
449# CONFIG_MACVLAN is not set
420# CONFIG_EQUALIZER is not set 450# CONFIG_EQUALIZER is not set
421# CONFIG_TUN is not set 451# CONFIG_TUN is not set
452# CONFIG_ARCNET is not set
422CONFIG_PHYLIB=y 453CONFIG_PHYLIB=y
423 454
424# 455#
@@ -432,17 +463,44 @@ CONFIG_MARVELL_PHY=y
432# CONFIG_VITESSE_PHY is not set 463# CONFIG_VITESSE_PHY is not set
433# CONFIG_SMSC_PHY is not set 464# CONFIG_SMSC_PHY is not set
434# CONFIG_BROADCOM_PHY is not set 465# CONFIG_BROADCOM_PHY is not set
466# CONFIG_ICPLUS_PHY is not set
435# CONFIG_FIXED_PHY is not set 467# CONFIG_FIXED_PHY is not set
436
437#
438# Ethernet (10 or 100Mbit)
439#
440CONFIG_NET_ETHERNET=y 468CONFIG_NET_ETHERNET=y
441CONFIG_MII=y 469CONFIG_MII=y
470# CONFIG_HAPPYMEAL is not set
471# CONFIG_SUNGEM is not set
472# CONFIG_CASSINI is not set
473# CONFIG_NET_VENDOR_3COM is not set
474# CONFIG_NET_TULIP is not set
475# CONFIG_HP100 is not set
476# CONFIG_NET_PCI is not set
442CONFIG_NETDEV_1000=y 477CONFIG_NETDEV_1000=y
478# CONFIG_ACENIC is not set
479# CONFIG_DL2K is not set
480# CONFIG_E1000 is not set
481# CONFIG_NS83820 is not set
482# CONFIG_HAMACHI is not set
483# CONFIG_YELLOWFIN is not set
484# CONFIG_R8169 is not set
485# CONFIG_SIS190 is not set
486# CONFIG_SKGE is not set
487# CONFIG_SKY2 is not set
488# CONFIG_VIA_VELOCITY is not set
489# CONFIG_TIGON3 is not set
490# CONFIG_BNX2 is not set
443CONFIG_GIANFAR=y 491CONFIG_GIANFAR=y
444CONFIG_GFAR_NAPI=y 492CONFIG_GFAR_NAPI=y
493# CONFIG_QLA3XXX is not set
494# CONFIG_ATL1 is not set
445CONFIG_NETDEV_10000=y 495CONFIG_NETDEV_10000=y
496# CONFIG_CHELSIO_T1 is not set
497# CONFIG_CHELSIO_T3 is not set
498# CONFIG_IXGB is not set
499# CONFIG_S2IO is not set
500# CONFIG_MYRI10GE is not set
501# CONFIG_NETXEN_NIC is not set
502# CONFIG_MLX4_CORE is not set
503# CONFIG_TR is not set
446 504
447# 505#
448# Wireless LAN 506# Wireless LAN
@@ -450,21 +508,16 @@ CONFIG_NETDEV_10000=y
450# CONFIG_WLAN_PRE80211 is not set 508# CONFIG_WLAN_PRE80211 is not set
451# CONFIG_WLAN_80211 is not set 509# CONFIG_WLAN_80211 is not set
452# CONFIG_WAN is not set 510# CONFIG_WAN is not set
511# CONFIG_FDDI is not set
512# CONFIG_HIPPI is not set
453# CONFIG_PPP is not set 513# CONFIG_PPP is not set
454# CONFIG_SLIP is not set 514# CONFIG_SLIP is not set
515# CONFIG_NET_FC is not set
455# CONFIG_SHAPER is not set 516# CONFIG_SHAPER is not set
456# CONFIG_NETCONSOLE is not set 517# CONFIG_NETCONSOLE is not set
457# CONFIG_NETPOLL is not set 518# CONFIG_NETPOLL is not set
458# CONFIG_NET_POLL_CONTROLLER is not set 519# CONFIG_NET_POLL_CONTROLLER is not set
459
460#
461# ISDN subsystem
462#
463# CONFIG_ISDN is not set 520# CONFIG_ISDN is not set
464
465#
466# Telephony Support
467#
468# CONFIG_PHONE is not set 521# CONFIG_PHONE is not set
469 522
470# 523#
@@ -510,6 +563,7 @@ CONFIG_INPUT=y
510# 563#
511CONFIG_SERIAL_8250=y 564CONFIG_SERIAL_8250=y
512CONFIG_SERIAL_8250_CONSOLE=y 565CONFIG_SERIAL_8250_CONSOLE=y
566CONFIG_SERIAL_8250_PCI=y
513CONFIG_SERIAL_8250_NR_UARTS=4 567CONFIG_SERIAL_8250_NR_UARTS=4
514CONFIG_SERIAL_8250_RUNTIME_UARTS=4 568CONFIG_SERIAL_8250_RUNTIME_UARTS=4
515# CONFIG_SERIAL_8250_EXTENDED is not set 569# CONFIG_SERIAL_8250_EXTENDED is not set
@@ -521,14 +575,11 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
521# CONFIG_SERIAL_UARTLITE is not set 575# CONFIG_SERIAL_UARTLITE is not set
522CONFIG_SERIAL_CORE=y 576CONFIG_SERIAL_CORE=y
523CONFIG_SERIAL_CORE_CONSOLE=y 577CONFIG_SERIAL_CORE_CONSOLE=y
578# CONFIG_SERIAL_JSM is not set
524# CONFIG_SERIAL_OF_PLATFORM is not set 579# CONFIG_SERIAL_OF_PLATFORM is not set
525CONFIG_UNIX98_PTYS=y 580CONFIG_UNIX98_PTYS=y
526CONFIG_LEGACY_PTYS=y 581CONFIG_LEGACY_PTYS=y
527CONFIG_LEGACY_PTY_COUNT=256 582CONFIG_LEGACY_PTY_COUNT=256
528
529#
530# IPMI
531#
532# CONFIG_IPMI_HANDLER is not set 583# CONFIG_IPMI_HANDLER is not set
533CONFIG_WATCHDOG=y 584CONFIG_WATCHDOG=y
534# CONFIG_WATCHDOG_NOWAYOUT is not set 585# CONFIG_WATCHDOG_NOWAYOUT is not set
@@ -538,17 +589,23 @@ CONFIG_WATCHDOG=y
538# 589#
539# CONFIG_SOFT_WATCHDOG is not set 590# CONFIG_SOFT_WATCHDOG is not set
540# CONFIG_BOOKE_WDT is not set 591# CONFIG_BOOKE_WDT is not set
592
593#
594# PCI-based Watchdog Cards
595#
596# CONFIG_PCIPCWATCHDOG is not set
597# CONFIG_WDTPCI is not set
541CONFIG_HW_RANDOM=y 598CONFIG_HW_RANDOM=y
542# CONFIG_NVRAM is not set 599# CONFIG_NVRAM is not set
543CONFIG_GEN_RTC=y 600CONFIG_GEN_RTC=y
544# CONFIG_GEN_RTC_X is not set 601# CONFIG_GEN_RTC_X is not set
545# CONFIG_R3964 is not set 602# CONFIG_R3964 is not set
603# CONFIG_APPLICOM is not set
604# CONFIG_AGP is not set
605# CONFIG_DRM is not set
546# CONFIG_RAW_DRIVER is not set 606# CONFIG_RAW_DRIVER is not set
547
548#
549# TPM devices
550#
551# CONFIG_TCG_TPM is not set 607# CONFIG_TCG_TPM is not set
608CONFIG_DEVPORT=y
552CONFIG_I2C=y 609CONFIG_I2C=y
553CONFIG_I2C_BOARDINFO=y 610CONFIG_I2C_BOARDINFO=y
554CONFIG_I2C_CHARDEV=y 611CONFIG_I2C_CHARDEV=y
@@ -563,23 +620,43 @@ CONFIG_I2C_CHARDEV=y
563# 620#
564# I2C Hardware Bus support 621# I2C Hardware Bus support
565# 622#
623# CONFIG_I2C_ALI1535 is not set
624# CONFIG_I2C_ALI1563 is not set
625# CONFIG_I2C_ALI15X3 is not set
626# CONFIG_I2C_AMD756 is not set
627# CONFIG_I2C_AMD8111 is not set
628# CONFIG_I2C_I801 is not set
629# CONFIG_I2C_I810 is not set
630# CONFIG_I2C_PIIX4 is not set
566CONFIG_I2C_MPC=y 631CONFIG_I2C_MPC=y
632# CONFIG_I2C_NFORCE2 is not set
567# CONFIG_I2C_OCORES is not set 633# CONFIG_I2C_OCORES is not set
568# CONFIG_I2C_PARPORT_LIGHT is not set 634# CONFIG_I2C_PARPORT_LIGHT is not set
635# CONFIG_I2C_PROSAVAGE is not set
636# CONFIG_I2C_SAVAGE4 is not set
569# CONFIG_I2C_SIMTEC is not set 637# CONFIG_I2C_SIMTEC is not set
638# CONFIG_I2C_SIS5595 is not set
639# CONFIG_I2C_SIS630 is not set
640# CONFIG_I2C_SIS96X is not set
641# CONFIG_I2C_TAOS_EVM is not set
570# CONFIG_I2C_STUB is not set 642# CONFIG_I2C_STUB is not set
643# CONFIG_I2C_VIA is not set
644# CONFIG_I2C_VIAPRO is not set
645# CONFIG_I2C_VOODOO3 is not set
571 646
572# 647#
573# Miscellaneous I2C Chip support 648# Miscellaneous I2C Chip support
574# 649#
575# CONFIG_SENSORS_DS1337 is not set 650# CONFIG_SENSORS_DS1337 is not set
576# CONFIG_SENSORS_DS1374 is not set 651# CONFIG_SENSORS_DS1374 is not set
652# CONFIG_DS1682 is not set
577# CONFIG_SENSORS_EEPROM is not set 653# CONFIG_SENSORS_EEPROM is not set
578# CONFIG_SENSORS_PCF8574 is not set 654# CONFIG_SENSORS_PCF8574 is not set
579# CONFIG_SENSORS_PCA9539 is not set 655# CONFIG_SENSORS_PCA9539 is not set
580# CONFIG_SENSORS_PCF8591 is not set 656# CONFIG_SENSORS_PCF8591 is not set
581# CONFIG_SENSORS_M41T00 is not set 657# CONFIG_SENSORS_M41T00 is not set
582# CONFIG_SENSORS_MAX6875 is not set 658# CONFIG_SENSORS_MAX6875 is not set
659# CONFIG_SENSORS_TSL2550 is not set
583# CONFIG_I2C_DEBUG_CORE is not set 660# CONFIG_I2C_DEBUG_CORE is not set
584# CONFIG_I2C_DEBUG_ALGO is not set 661# CONFIG_I2C_DEBUG_ALGO is not set
585# CONFIG_I2C_DEBUG_BUS is not set 662# CONFIG_I2C_DEBUG_BUS is not set
@@ -590,11 +667,8 @@ CONFIG_I2C_MPC=y
590# 667#
591# CONFIG_SPI is not set 668# CONFIG_SPI is not set
592# CONFIG_SPI_MASTER is not set 669# CONFIG_SPI_MASTER is not set
593
594#
595# Dallas's 1-wire bus
596#
597# CONFIG_W1 is not set 670# CONFIG_W1 is not set
671# CONFIG_POWER_SUPPLY is not set
598CONFIG_HWMON=y 672CONFIG_HWMON=y
599# CONFIG_HWMON_VID is not set 673# CONFIG_HWMON_VID is not set
600# CONFIG_SENSORS_ABITUGURU is not set 674# CONFIG_SENSORS_ABITUGURU is not set
@@ -628,10 +702,13 @@ CONFIG_HWMON=y
628# CONFIG_SENSORS_MAX6650 is not set 702# CONFIG_SENSORS_MAX6650 is not set
629# CONFIG_SENSORS_PC87360 is not set 703# CONFIG_SENSORS_PC87360 is not set
630# CONFIG_SENSORS_PC87427 is not set 704# CONFIG_SENSORS_PC87427 is not set
705# CONFIG_SENSORS_SIS5595 is not set
631# CONFIG_SENSORS_SMSC47M1 is not set 706# CONFIG_SENSORS_SMSC47M1 is not set
632# CONFIG_SENSORS_SMSC47M192 is not set 707# CONFIG_SENSORS_SMSC47M192 is not set
633# CONFIG_SENSORS_SMSC47B397 is not set 708# CONFIG_SENSORS_SMSC47B397 is not set
709# CONFIG_SENSORS_VIA686A is not set
634# CONFIG_SENSORS_VT1211 is not set 710# CONFIG_SENSORS_VT1211 is not set
711# CONFIG_SENSORS_VT8231 is not set
635# CONFIG_SENSORS_W83781D is not set 712# CONFIG_SENSORS_W83781D is not set
636# CONFIG_SENSORS_W83791D is not set 713# CONFIG_SENSORS_W83791D is not set
637# CONFIG_SENSORS_W83792D is not set 714# CONFIG_SENSORS_W83792D is not set
@@ -670,19 +747,14 @@ CONFIG_DAB=y
670# Sound 747# Sound
671# 748#
672# CONFIG_SOUND is not set 749# CONFIG_SOUND is not set
673 750CONFIG_HID_SUPPORT=y
674#
675# HID Devices
676#
677CONFIG_HID=y 751CONFIG_HID=y
678# CONFIG_HID_DEBUG is not set 752# CONFIG_HID_DEBUG is not set
679 753CONFIG_USB_SUPPORT=y
680# 754CONFIG_USB_ARCH_HAS_HCD=y
681# USB support 755CONFIG_USB_ARCH_HAS_OHCI=y
682# 756CONFIG_USB_ARCH_HAS_EHCI=y
683# CONFIG_USB_ARCH_HAS_HCD is not set 757# CONFIG_USB is not set
684# CONFIG_USB_ARCH_HAS_OHCI is not set
685# CONFIG_USB_ARCH_HAS_EHCI is not set
686 758
687# 759#
688# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 760# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -706,14 +778,7 @@ CONFIG_HID=y
706# 778#
707# LED Triggers 779# LED Triggers
708# 780#
709 781# CONFIG_INFINIBAND is not set
710#
711# InfiniBand support
712#
713
714#
715# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
716#
717 782
718# 783#
719# Real Time Clock 784# Real Time Clock
@@ -734,6 +799,11 @@ CONFIG_HID=y
734# 799#
735 800
736# 801#
802# Userspace I/O
803#
804# CONFIG_UIO is not set
805
806#
737# File systems 807# File systems
738# 808#
739CONFIG_EXT2_FS=y 809CONFIG_EXT2_FS=y
@@ -829,7 +899,6 @@ CONFIG_RPCSEC_GSS_KRB5=y
829# CONFIG_NCP_FS is not set 899# CONFIG_NCP_FS is not set
830# CONFIG_CODA_FS is not set 900# CONFIG_CODA_FS is not set
831# CONFIG_AFS_FS is not set 901# CONFIG_AFS_FS is not set
832# CONFIG_9P_FS is not set
833 902
834# 903#
835# Partition Types 904# Partition Types
@@ -868,6 +937,7 @@ CONFIG_BITREVERSE=y
868# CONFIG_CRC16 is not set 937# CONFIG_CRC16 is not set
869# CONFIG_CRC_ITU_T is not set 938# CONFIG_CRC_ITU_T is not set
870CONFIG_CRC32=y 939CONFIG_CRC32=y
940# CONFIG_CRC7 is not set
871# CONFIG_LIBCRC32C is not set 941# CONFIG_LIBCRC32C is not set
872CONFIG_PLIST=y 942CONFIG_PLIST=y
873CONFIG_HAS_IOMEM=y 943CONFIG_HAS_IOMEM=y
@@ -892,6 +962,7 @@ CONFIG_ENABLE_MUST_CHECK=y
892CONFIG_DEBUG_KERNEL=y 962CONFIG_DEBUG_KERNEL=y
893# CONFIG_DEBUG_SHIRQ is not set 963# CONFIG_DEBUG_SHIRQ is not set
894CONFIG_DETECT_SOFTLOCKUP=y 964CONFIG_DETECT_SOFTLOCKUP=y
965CONFIG_SCHED_DEBUG=y
895# CONFIG_SCHEDSTATS is not set 966# CONFIG_SCHEDSTATS is not set
896# CONFIG_TIMER_STATS is not set 967# CONFIG_TIMER_STATS is not set
897# CONFIG_DEBUG_SLAB is not set 968# CONFIG_DEBUG_SLAB is not set
@@ -915,7 +986,7 @@ CONFIG_FORCED_INLINING=y
915CONFIG_DEBUGGER=y 986CONFIG_DEBUGGER=y
916# CONFIG_XMON is not set 987# CONFIG_XMON is not set
917# CONFIG_BDI_SWITCH is not set 988# CONFIG_BDI_SWITCH is not set
918CONFIG_BOOTX_TEXT=y 989# CONFIG_BOOTX_TEXT is not set
919CONFIG_PPC_EARLY_DEBUG=y 990CONFIG_PPC_EARLY_DEBUG=y
920# CONFIG_PPC_EARLY_DEBUG_LPAR is not set 991# CONFIG_PPC_EARLY_DEBUG_LPAR is not set
921# CONFIG_PPC_EARLY_DEBUG_G5 is not set 992# CONFIG_PPC_EARLY_DEBUG_G5 is not set
@@ -932,10 +1003,6 @@ CONFIG_PPC_EARLY_DEBUG=y
932# 1003#
933# CONFIG_KEYS is not set 1004# CONFIG_KEYS is not set
934# CONFIG_SECURITY is not set 1005# CONFIG_SECURITY is not set
935
936#
937# Cryptographic options
938#
939CONFIG_CRYPTO=y 1006CONFIG_CRYPTO=y
940CONFIG_CRYPTO_ALGAPI=y 1007CONFIG_CRYPTO_ALGAPI=y
941CONFIG_CRYPTO_BLKCIPHER=y 1008CONFIG_CRYPTO_BLKCIPHER=y
@@ -973,7 +1040,4 @@ CONFIG_CRYPTO_DES=y
973# CONFIG_CRYPTO_CRC32C is not set 1040# CONFIG_CRYPTO_CRC32C is not set
974# CONFIG_CRYPTO_CAMELLIA is not set 1041# CONFIG_CRYPTO_CAMELLIA is not set
975# CONFIG_CRYPTO_TEST is not set 1042# CONFIG_CRYPTO_TEST is not set
976 1043CONFIG_CRYPTO_HW=y
977#
978# Hardware crypto devices
979#
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c
index 0adf077f3f3a..721a69400d65 100644
--- a/arch/powerpc/kernel/pci_32.c
+++ b/arch/powerpc/kernel/pci_32.c
@@ -415,15 +415,13 @@ probe_resource(struct pci_bus *parent, struct resource *pr,
415 return 0; 415 return 0;
416} 416}
417 417
418static void __init 418void __init
419update_bridge_base(struct pci_bus *bus, int i) 419update_bridge_resource(struct pci_dev *dev, struct resource *res)
420{ 420{
421 struct resource *res = bus->resource[i];
422 u8 io_base_lo, io_limit_lo; 421 u8 io_base_lo, io_limit_lo;
423 u16 mem_base, mem_limit; 422 u16 mem_base, mem_limit;
424 u16 cmd; 423 u16 cmd;
425 unsigned long start, end, off; 424 unsigned long start, end, off;
426 struct pci_dev *dev = bus->self;
427 struct pci_controller *hose = dev->sysdata; 425 struct pci_controller *hose = dev->sysdata;
428 426
429 if (!hose) { 427 if (!hose) {
@@ -467,12 +465,20 @@ update_bridge_base(struct pci_bus *bus, int i)
467 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit); 465 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
468 466
469 } else { 467 } else {
470 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n", 468 DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n",
471 pci_name(dev), i, res->flags); 469 pci_name(dev), res->flags);
472 } 470 }
473 pci_write_config_word(dev, PCI_COMMAND, cmd); 471 pci_write_config_word(dev, PCI_COMMAND, cmd);
474} 472}
475 473
474static void __init
475update_bridge_base(struct pci_bus *bus, int i)
476{
477 struct resource *res = bus->resource[i];
478 struct pci_dev *dev = bus->self;
479 update_bridge_resource(dev, res);
480}
481
476static inline void alloc_resource(struct pci_dev *dev, int idx) 482static inline void alloc_resource(struct pci_dev *dev, int idx)
477{ 483{
478 struct resource *pr, *r = &dev->resource[idx]; 484 struct resource *pr, *r = &dev->resource[idx];
@@ -1468,3 +1474,10 @@ EARLY_PCI_OP(read, dword, u32 *)
1468EARLY_PCI_OP(write, byte, u8) 1474EARLY_PCI_OP(write, byte, u8)
1469EARLY_PCI_OP(write, word, u16) 1475EARLY_PCI_OP(write, word, u16)
1470EARLY_PCI_OP(write, dword, u32) 1476EARLY_PCI_OP(write, dword, u32)
1477
1478extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1479int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1480 int cap)
1481{
1482 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1483}
diff --git a/arch/powerpc/platforms/82xx/mpc82xx_ads.c b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
index da20832b27f1..2d1b05b9f8ef 100644
--- a/arch/powerpc/platforms/82xx/mpc82xx_ads.c
+++ b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
@@ -553,7 +553,8 @@ static void __init mpc82xx_add_bridge(struct device_node *np)
553 553
554 setup_indirect_pci(hose, 554 setup_indirect_pci(hose,
555 r.start + offsetof(pci_cpm2_t, pci_cfg_addr), 555 r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
556 r.start + offsetof(pci_cpm2_t, pci_cfg_data)); 556 r.start + offsetof(pci_cpm2_t, pci_cfg_data),
557 0);
557 558
558 pci_process_bridge_OF_ranges(hose, np, 1); 559 pci_process_bridge_OF_ranges(hose, np, 1);
559} 560}
diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/platforms/83xx/pci.c
index c0e2b89154e5..92069469de20 100644
--- a/arch/powerpc/platforms/83xx/pci.c
+++ b/arch/powerpc/platforms/83xx/pci.c
@@ -74,11 +74,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
74 */ 74 */
75 /* PCI 1 */ 75 /* PCI 1 */
76 if ((rsrc.start & 0xfffff) == 0x8500) { 76 if ((rsrc.start & 0xfffff) == 0x8500) {
77 setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304); 77 setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0);
78 } 78 }
79 /* PCI 2 */ 79 /* PCI 2 */
80 if ((rsrc.start & 0xfffff) == 0x8600) { 80 if ((rsrc.start & 0xfffff) == 0x8600) {
81 setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384); 81 setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0);
82 primary = 0; 82 primary = 0;
83 } 83 }
84 84
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 629926e01e90..f58184086c8c 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -18,6 +18,7 @@ config MPC8560_ADS
18config MPC85xx_CDS 18config MPC85xx_CDS
19 bool "Freescale MPC85xx CDS" 19 bool "Freescale MPC85xx CDS"
20 select DEFAULT_UIMAGE 20 select DEFAULT_UIMAGE
21 select PPC_I8259
21 help 22 help
22 This option enables support for the MPC85xx CDS board 23 This option enables support for the MPC85xx CDS board
23 24
@@ -30,6 +31,7 @@ config MPC85xx_MDS
30 31
31config MPC8544_DS 32config MPC8544_DS
32 bool "Freescale MPC8544 DS" 33 bool "Freescale MPC8544 DS"
34 select PPC_I8259
33 select DEFAULT_UIMAGE 35 select DEFAULT_UIMAGE
34 help 36 help
35 This option enables support for the MPC8544 DS board 37 This option enables support for the MPC8544 DS board
@@ -50,9 +52,9 @@ config MPC8560
50config MPC85xx 52config MPC85xx
51 bool 53 bool
52 select PPC_UDBG_16550 54 select PPC_UDBG_16550
53 select PPC_INDIRECT_PCI 55 select PPC_INDIRECT_PCI if PCI
54 select PPC_INDIRECT_PCI_BE
55 select MPIC 56 select MPIC
57 select FSL_PCI if PCI
56 select SERIAL_8250_SHARE_IRQ if SERIAL_8250 58 select SERIAL_8250_SHARE_IRQ if SERIAL_8250
57 default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \ 59 default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \
58 || MPC85xx_MDS || MPC8544_DS 60 || MPC85xx_MDS || MPC8544_DS
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 4e02cbb14cf7..d70f2d0f9d36 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -1,7 +1,7 @@
1# 1#
2# Makefile for the PowerPC 85xx linux kernel. 2# Makefile for the PowerPC 85xx linux kernel.
3# 3#
4obj-$(CONFIG_PPC_85xx) += misc.o pci.o 4obj-$(CONFIG_PPC_85xx) += misc.o
5obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o 5obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
6obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o 6obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
7obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o 7obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
diff --git a/arch/powerpc/platforms/85xx/mpc8544_ds.c b/arch/powerpc/platforms/85xx/mpc8544_ds.c
index 6fb90aab879f..4905f6f8903b 100644
--- a/arch/powerpc/platforms/85xx/mpc8544_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8544_ds.c
@@ -2,6 +2,8 @@
2 * MPC8544 DS Board Setup 2 * MPC8544 DS Board Setup
3 * 3 *
4 * Author Xianghua Xiao (x.xiao@freescale.com) 4 * Author Xianghua Xiao (x.xiao@freescale.com)
5 * Roy Zang <tie-fei.zang@freescale.com>
6 * - Add PCI/PCI Exprees support
5 * Copyright 2007 Freescale Semiconductor Inc. 7 * Copyright 2007 Freescale Semiconductor Inc.
6 * 8 *
7 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
@@ -12,13 +14,16 @@
12 14
13#include <linux/stddef.h> 15#include <linux/stddef.h>
14#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/pci.h>
15#include <linux/kdev_t.h> 18#include <linux/kdev_t.h>
16#include <linux/delay.h> 19#include <linux/delay.h>
17#include <linux/seq_file.h> 20#include <linux/seq_file.h>
21#include <linux/interrupt.h>
18 22
19#include <asm/system.h> 23#include <asm/system.h>
20#include <asm/time.h> 24#include <asm/time.h>
21#include <asm/machdep.h> 25#include <asm/machdep.h>
26#include <asm/pci-bridge.h>
22#include <asm/mpc85xx.h> 27#include <asm/mpc85xx.h>
23#include <mm/mmu_decl.h> 28#include <mm/mmu_decl.h>
24#include <asm/prom.h> 29#include <asm/prom.h>
@@ -27,6 +32,7 @@
27#include <asm/i8259.h> 32#include <asm/i8259.h>
28 33
29#include <sysdev/fsl_soc.h> 34#include <sysdev/fsl_soc.h>
35#include <sysdev/fsl_pci.h>
30#include "mpc85xx.h" 36#include "mpc85xx.h"
31 37
32#undef DEBUG 38#undef DEBUG
@@ -37,6 +43,17 @@
37#define DBG(fmt, args...) 43#define DBG(fmt, args...)
38#endif 44#endif
39 45
46#ifdef CONFIG_PPC_I8259
47static void mpc8544_8259_cascade(unsigned int irq, struct irq_desc *desc)
48{
49 unsigned int cascade_irq = i8259_irq();
50
51 if (cascade_irq != NO_IRQ) {
52 generic_handle_irq(cascade_irq);
53 }
54 desc->chip->eoi(irq);
55}
56#endif /* CONFIG_PPC_I8259 */
40 57
41void __init mpc8544_ds_pic_init(void) 58void __init mpc8544_ds_pic_init(void)
42{ 59{
@@ -96,19 +113,240 @@ void __init mpc8544_ds_pic_init(void)
96#endif /* CONFIG_PPC_I8259 */ 113#endif /* CONFIG_PPC_I8259 */
97} 114}
98 115
116#ifdef CONFIG_PCI
117enum pirq { PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH };
118
119/*
120 * Value in table -- IRQ number
121 */
122const unsigned char uli1575_irq_route_table[16] = {
123 0, /* 0: Reserved */
124 0x8,
125 0, /* 2: Reserved */
126 0x2,
127 0x4,
128 0x5,
129 0x7,
130 0x6,
131 0, /* 8: Reserved */
132 0x1,
133 0x3,
134 0x9,
135 0xb,
136 0, /* 13: Reserved */
137 0xd,
138 0xf,
139};
140
141static int __devinit
142get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
143{
144 struct of_irq oirq;
145 u32 laddr[3];
146 struct device_node *hosenode = hose ? hose->arch_data : NULL;
147
148 if (!hosenode)
149 return -EINVAL;
150
151 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
152 laddr[1] = laddr[2] = 0;
153 of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
154 DBG("mpc8544_ds: pci irq addr %x, slot %d, pin %d, irq %d\n",
155 laddr[0], slot, pin, oirq.specifier[0]);
156 return oirq.specifier[0];
157}
158
159/*8259*/
160static void __devinit quirk_uli1575(struct pci_dev *dev)
161{
162 unsigned short temp;
163 struct pci_controller *hose = pci_bus_to_host(dev->bus);
164 unsigned char irq2pin[16];
165 unsigned long pirq_map_word = 0;
166 u32 irq;
167 int i;
168
169 /*
170 * ULI1575 interrupts route setup
171 */
172 memset(irq2pin, 0, 16); /* Initialize default value 0 */
173
174 irq2pin[6]=PIRQA+3; /* enabled mapping for IRQ6 to PIRQD, used by SATA */
175
176 /*
177 * PIRQE -> PIRQF mapping set manually
178 *
179 * IRQ pin IRQ#
180 * PIRQE ---- 9
181 * PIRQF ---- 10
182 * PIRQG ---- 11
183 * PIRQH ---- 12
184 */
185 for (i = 0; i < 4; i++)
186 irq2pin[i + 9] = PIRQE + i;
187
188 /* Set IRQ-PIRQ Mapping to ULI1575 */
189 for (i = 0; i < 16; i++)
190 if (irq2pin[i])
191 pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
192 << ((irq2pin[i] - PIRQA) * 4);
193
194 pirq_map_word |= 1<<26; /* disable INTx in EP mode*/
195
196 /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
197 DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
198 (int)pirq_map_word);
199 pci_write_config_dword(dev, 0x48, pirq_map_word);
200
201#define ULI1575_SET_DEV_IRQ(slot, pin, reg) \
202 do { \
203 int irq; \
204 irq = get_pci_irq_from_of(hose, slot, pin); \
205 if (irq > 0 && irq < 16) \
206 pci_write_config_byte(dev, reg, irq2pin[irq]); \
207 else \
208 printk(KERN_WARNING "ULI1575 device" \
209 "(slot %d, pin %d) irq %d is invalid.\n", \
210 slot, pin, irq); \
211 } while(0)
212
213 /* USB 1.1 OHCI controller 1, slot 28, pin 1 */
214 ULI1575_SET_DEV_IRQ(28, 1, 0x86);
215
216 /* USB 1.1 OHCI controller 2, slot 28, pin 2 */
217 ULI1575_SET_DEV_IRQ(28, 2, 0x87);
218
219 /* USB 1.1 OHCI controller 3, slot 28, pin 3 */
220 ULI1575_SET_DEV_IRQ(28, 3, 0x88);
221
222 /* USB 2.0 controller, slot 28, pin 4 */
223 irq = get_pci_irq_from_of(hose, 28, 4);
224 if (irq >= 0 && irq <= 15)
225 pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
226
227 /* Audio controller, slot 29, pin 1 */
228 ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
229
230 /* Modem controller, slot 29, pin 2 */
231 ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
232
233 /* HD audio controller, slot 29, pin 3 */
234 ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
235
236 /* SMB interrupt: slot 30, pin 1 */
237 ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
238
239 /* PMU ACPI SCI interrupt: slot 30, pin 2 */
240 ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
241
242 /* Serial ATA interrupt: slot 31, pin 1 */
243 ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
244
245 /* Primary PATA IDE IRQ: 14
246 * Secondary PATA IDE IRQ: 15
247 */
248 pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
249 pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
250
251 /* Set IRQ14 and IRQ15 to legacy IRQs */
252 pci_read_config_word(dev, 0x46, &temp);
253 temp |= 0xc000;
254 pci_write_config_word(dev, 0x46, temp);
255
256 /* Set i8259 interrupt trigger
257 * IRQ 3: Level
258 * IRQ 4: Level
259 * IRQ 5: Level
260 * IRQ 6: Level
261 * IRQ 7: Level
262 * IRQ 9: Level
263 * IRQ 10: Level
264 * IRQ 11: Level
265 * IRQ 12: Level
266 * IRQ 14: Edge
267 * IRQ 15: Edge
268 */
269 outb(0xfa, 0x4d0);
270 outb(0x1e, 0x4d1);
271
272#undef ULI1575_SET_DEV_IRQ
273}
274
275/* SATA */
276static void __devinit quirk_uli5288(struct pci_dev *dev)
277{
278 unsigned char c;
279
280 pci_read_config_byte(dev, 0x83, &c);
281 c |= 0x80; /* read/write lock */
282 pci_write_config_byte(dev, 0x83, c);
283
284 pci_write_config_byte(dev, 0x09, 0x01); /* Base class code: storage */
285 pci_write_config_byte(dev, 0x0a, 0x06); /* IDE disk */
286
287 pci_read_config_byte(dev, 0x83, &c);
288 c &= 0x7f;
289 pci_write_config_byte(dev, 0x83, c);
290
291 pci_read_config_byte(dev, 0x84, &c);
292 c |= 0x01; /* emulated PATA mode enabled */
293 pci_write_config_byte(dev, 0x84, c);
294}
295
296/* PATA */
297static void __devinit quirk_uli5229(struct pci_dev *dev)
298{
299 unsigned short temp;
300 pci_write_config_word(dev, 0x04, 0x0405); /* MEM IO MSI */
301 pci_read_config_word(dev, 0x4a, &temp);
302 temp |= 0x1000; /* Enable Native IRQ 14/15 */
303 pci_write_config_word(dev, 0x4a, temp);
304}
305
306/*Bridge*/
307static void __devinit early_uli5249(struct pci_dev *dev)
308{
309 unsigned char temp;
310 pci_write_config_word(dev, 0x04, 0x0007); /* mem access */
311 pci_read_config_byte(dev, 0x7c, &temp);
312 pci_write_config_byte(dev, 0x7c, 0x80); /* R/W lock control */
313 pci_write_config_byte(dev, 0x09, 0x01); /* set as pci-pci bridge */
314 pci_write_config_byte(dev, 0x7c, temp); /* restore pci bus debug control */
315 dev->class |= 0x1;
316}
317
318DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
321DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
322#endif /* CONFIG_PCI */
99 323
100/* 324/*
101 * Setup the architecture 325 * Setup the architecture
102 */ 326 */
103static void __init mpc8544_ds_setup_arch(void) 327static void __init mpc8544_ds_setup_arch(void)
104{ 328{
329#ifdef CONFIG_PCI
330 struct device_node *np;
331#endif
332
105 if (ppc_md.progress) 333 if (ppc_md.progress)
106 ppc_md.progress("mpc8544_ds_setup_arch()", 0); 334 ppc_md.progress("mpc8544_ds_setup_arch()", 0);
107 335
336#ifdef CONFIG_PCI
337 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
338 struct resource rsrc;
339 of_address_to_resource(np, 0, &rsrc);
340 if ((rsrc.start & 0xfffff) == 0xb000)
341 fsl_add_bridge(np, 1);
342 else
343 fsl_add_bridge(np, 0);
344 }
345#endif
346
108 printk("MPC8544 DS board from Freescale Semiconductor\n"); 347 printk("MPC8544 DS board from Freescale Semiconductor\n");
109} 348}
110 349
111
112/* 350/*
113 * Called very early, device-tree isn't unflattened 351 * Called very early, device-tree isn't unflattened
114 */ 352 */
@@ -124,6 +362,7 @@ define_machine(mpc8544_ds) {
124 .probe = mpc8544_ds_probe, 362 .probe = mpc8544_ds_probe,
125 .setup_arch = mpc8544_ds_setup_arch, 363 .setup_arch = mpc8544_ds_setup_arch,
126 .init_IRQ = mpc8544_ds_pic_init, 364 .init_IRQ = mpc8544_ds_pic_init,
365 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
127 .get_irq = mpic_get_irq, 366 .get_irq = mpic_get_irq,
128 .restart = mpc85xx_restart, 367 .restart = mpc85xx_restart,
129 .calibrate_decr = generic_calibrate_decr, 368 .calibrate_decr = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
index 7286ffac2c1d..5b34deef12b5 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -15,4 +15,3 @@
15 */ 15 */
16 16
17extern void mpc85xx_restart(char *); 17extern void mpc85xx_restart(char *);
18extern int mpc85xx_add_bridge(struct device_node *dev);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 7235f702394c..40a828675c7b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -29,6 +29,7 @@
29#include <asm/udbg.h> 29#include <asm/udbg.h>
30 30
31#include <sysdev/fsl_soc.h> 31#include <sysdev/fsl_soc.h>
32#include <sysdev/fsl_pci.h>
32#include "mpc85xx.h" 33#include "mpc85xx.h"
33 34
34#ifdef CONFIG_CPM2 35#ifdef CONFIG_CPM2
@@ -217,7 +218,7 @@ static void __init mpc85xx_ads_setup_arch(void)
217 218
218#ifdef CONFIG_PCI 219#ifdef CONFIG_PCI
219 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 220 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
220 mpc85xx_add_bridge(np); 221 fsl_add_bridge(np, 1);
221 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 222 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
222#endif 223#endif
223} 224}
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 50c8d6458362..6a171e9abf7d 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -24,6 +24,7 @@
24#include <linux/seq_file.h> 24#include <linux/seq_file.h>
25#include <linux/initrd.h> 25#include <linux/initrd.h>
26#include <linux/module.h> 26#include <linux/module.h>
27#include <linux/interrupt.h>
27#include <linux/fsl_devices.h> 28#include <linux/fsl_devices.h>
28 29
29#include <asm/system.h> 30#include <asm/system.h>
@@ -45,6 +46,7 @@
45#include <asm/i8259.h> 46#include <asm/i8259.h>
46 47
47#include <sysdev/fsl_soc.h> 48#include <sysdev/fsl_soc.h>
49#include <sysdev/fsl_pci.h>
48#include "mpc85xx.h" 50#include "mpc85xx.h"
49 51
50static int cds_pci_slot = 2; 52static int cds_pci_slot = 2;
@@ -58,8 +60,6 @@ static volatile u8 *cadmus;
58static int mpc85xx_exclude_device(struct pci_controller *hose, 60static int mpc85xx_exclude_device(struct pci_controller *hose,
59 u_char bus, u_char devfn) 61 u_char bus, u_char devfn)
60{ 62{
61 if ((bus == hose->first_busno) && PCI_SLOT(devfn) == 0)
62 return PCIBIOS_DEVICE_NOT_FOUND;
63 /* We explicitly do not go past the Tundra 320 Bridge */ 63 /* We explicitly do not go past the Tundra 320 Bridge */
64 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL)) 64 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
65 return PCIBIOS_DEVICE_NOT_FOUND; 65 return PCIBIOS_DEVICE_NOT_FOUND;
@@ -69,6 +69,37 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
69 return PCIBIOS_SUCCESSFUL; 69 return PCIBIOS_SUCCESSFUL;
70} 70}
71 71
72static void mpc85xx_cds_restart(char *cmd)
73{
74 struct pci_dev *dev;
75 u_char tmp;
76
77 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
78 NULL))) {
79
80 /* Use the VIA Super Southbridge to force a PCI reset */
81 pci_read_config_byte(dev, 0x47, &tmp);
82 pci_write_config_byte(dev, 0x47, tmp | 1);
83
84 /* Flush the outbound PCI write queues */
85 pci_read_config_byte(dev, 0x47, &tmp);
86
87 /*
88 * At this point, the harware reset should have triggered.
89 * However, if it doesn't work for some mysterious reason,
90 * just fall through to the default reset below.
91 */
92
93 pci_dev_put(dev);
94 }
95
96 /*
97 * If we can't find the VIA chip (maybe the P2P bridge is disabled)
98 * or the VIA chip reset didn't work, just use the default reset.
99 */
100 mpc85xx_restart(NULL);
101}
102
72static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev) 103static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
73{ 104{
74 u_char c; 105 u_char c;
@@ -98,7 +129,7 @@ static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
98 /* There are two USB controllers. 129 /* There are two USB controllers.
99 * Identify them by functon number 130 * Identify them by functon number
100 */ 131 */
101 if (PCI_FUNC(dev->devfn)) 132 if (PCI_FUNC(dev->devfn) == 3)
102 dev->irq = 11; 133 dev->irq = 11;
103 else 134 else
104 dev->irq = 10; 135 dev->irq = 10;
@@ -109,17 +140,41 @@ static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
109 } 140 }
110} 141}
111 142
143static void __devinit skip_fake_bridge(struct pci_dev *dev)
144{
145 /* Make it an error to skip the fake bridge
146 * in pci_setup_device() in probe.c */
147 dev->hdr_type = 0x7f;
148}
149DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
150DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
151DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
152
112#ifdef CONFIG_PPC_I8259 153#ifdef CONFIG_PPC_I8259
113#warning The i8259 PIC support is currently broken 154static void mpc85xx_8259_cascade_handler(unsigned int irq,
114static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) 155 struct irq_desc *desc)
115{ 156{
116 unsigned int cascade_irq = i8259_irq(); 157 unsigned int cascade_irq = i8259_irq();
117 158
118 if (cascade_irq != NO_IRQ) 159 if (cascade_irq != NO_IRQ)
160 /* handle an interrupt from the 8259 */
119 generic_handle_irq(cascade_irq); 161 generic_handle_irq(cascade_irq);
120 162
121 desc->chip->eoi(irq); 163 /* check for any interrupts from the shared IRQ line */
164 handle_fasteoi_irq(irq, desc);
165}
166
167static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
168{
169 return IRQ_HANDLED;
122} 170}
171
172static struct irqaction mpc85xxcds_8259_irqaction = {
173 .handler = mpc85xx_8259_cascade_action,
174 .flags = IRQF_SHARED,
175 .mask = CPU_MASK_NONE,
176 .name = "8259 cascade",
177};
123#endif /* PPC_I8259 */ 178#endif /* PPC_I8259 */
124#endif /* CONFIG_PCI */ 179#endif /* CONFIG_PCI */
125 180
@@ -128,10 +183,6 @@ static void __init mpc85xx_cds_pic_init(void)
128 struct mpic *mpic; 183 struct mpic *mpic;
129 struct resource r; 184 struct resource r;
130 struct device_node *np = NULL; 185 struct device_node *np = NULL;
131#ifdef CONFIG_PPC_I8259
132 struct device_node *cascade_node = NULL;
133 int cascade_irq;
134#endif
135 186
136 np = of_find_node_by_type(np, "open-pic"); 187 np = of_find_node_by_type(np, "open-pic");
137 188
@@ -155,8 +206,19 @@ static void __init mpc85xx_cds_pic_init(void)
155 of_node_put(np); 206 of_node_put(np);
156 207
157 mpic_init(mpic); 208 mpic_init(mpic);
209}
210
211#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
212static int mpc85xx_cds_8259_attach(void)
213{
214 int ret;
215 struct device_node *np = NULL;
216 struct device_node *cascade_node = NULL;
217 int cascade_irq;
218
219 if (!machine_is(mpc85xx_cds))
220 return 0;
158 221
159#ifdef CONFIG_PPC_I8259
160 /* Initialize the i8259 controller */ 222 /* Initialize the i8259 controller */
161 for_each_node_by_type(np, "interrupt-controller") 223 for_each_node_by_type(np, "interrupt-controller")
162 if (of_device_is_compatible(np, "chrp,iic")) { 224 if (of_device_is_compatible(np, "chrp,iic")) {
@@ -166,22 +228,39 @@ static void __init mpc85xx_cds_pic_init(void)
166 228
167 if (cascade_node == NULL) { 229 if (cascade_node == NULL) {
168 printk(KERN_DEBUG "Could not find i8259 PIC\n"); 230 printk(KERN_DEBUG "Could not find i8259 PIC\n");
169 return; 231 return -ENODEV;
170 } 232 }
171 233
172 cascade_irq = irq_of_parse_and_map(cascade_node, 0); 234 cascade_irq = irq_of_parse_and_map(cascade_node, 0);
173 if (cascade_irq == NO_IRQ) { 235 if (cascade_irq == NO_IRQ) {
174 printk(KERN_ERR "Failed to map cascade interrupt\n"); 236 printk(KERN_ERR "Failed to map cascade interrupt\n");
175 return; 237 return -ENXIO;
176 } 238 }
177 239
178 i8259_init(cascade_node, 0); 240 i8259_init(cascade_node, 0);
179 of_node_put(cascade_node); 241 of_node_put(cascade_node);
180 242
181 set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade); 243 /*
182#endif /* CONFIG_PPC_I8259 */ 244 * Hook the interrupt to make sure desc->action is never NULL.
245 * This is required to ensure that the interrupt does not get
246 * disabled when the last user of the shared IRQ line frees their
247 * interrupt.
248 */
249 if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
250 printk(KERN_ERR "Failed to setup cascade interrupt\n");
251 return ret;
252 }
253
254 /* Success. Connect our low-level cascade handler. */
255 set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler);
256
257 return 0;
183} 258}
184 259
260device_initcall(mpc85xx_cds_8259_attach);
261
262#endif /* CONFIG_PPC_I8259 */
263
185/* 264/*
186 * Setup the architecture 265 * Setup the architecture
187 */ 266 */
@@ -218,9 +297,14 @@ static void __init mpc85xx_cds_setup_arch(void)
218 } 297 }
219 298
220#ifdef CONFIG_PCI 299#ifdef CONFIG_PCI
221 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 300 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
222 mpc85xx_add_bridge(np); 301 struct resource rsrc;
223 302 of_address_to_resource(np, 0, &rsrc);
303 if ((rsrc.start & 0xfffff) == 0x8000)
304 fsl_add_bridge(np, 1);
305 else
306 fsl_add_bridge(np, 0);
307 }
224 ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup; 308 ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
225 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 309 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
226#endif 310#endif
@@ -265,7 +349,12 @@ define_machine(mpc85xx_cds) {
265 .init_IRQ = mpc85xx_cds_pic_init, 349 .init_IRQ = mpc85xx_cds_pic_init,
266 .show_cpuinfo = mpc85xx_cds_show_cpuinfo, 350 .show_cpuinfo = mpc85xx_cds_show_cpuinfo,
267 .get_irq = mpic_get_irq, 351 .get_irq = mpic_get_irq,
352#ifdef CONFIG_PCI
353 .restart = mpc85xx_cds_restart,
354#else
268 .restart = mpc85xx_restart, 355 .restart = mpc85xx_restart,
356#endif
269 .calibrate_decr = generic_calibrate_decr, 357 .calibrate_decr = generic_calibrate_decr,
270 .progress = udbg_progress, 358 .progress = udbg_progress,
359 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
271}; 360};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 004b80bd0b84..e8003bf00c9a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -46,6 +46,7 @@
46#include <asm/prom.h> 46#include <asm/prom.h>
47#include <asm/udbg.h> 47#include <asm/udbg.h>
48#include <sysdev/fsl_soc.h> 48#include <sysdev/fsl_soc.h>
49#include <sysdev/fsl_pci.h>
49#include <asm/qe.h> 50#include <asm/qe.h>
50#include <asm/qe_ic.h> 51#include <asm/qe_ic.h>
51#include <asm/mpic.h> 52#include <asm/mpic.h>
@@ -94,9 +95,8 @@ static void __init mpc85xx_mds_setup_arch(void)
94 } 95 }
95 96
96#ifdef CONFIG_PCI 97#ifdef CONFIG_PCI
97 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { 98 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
98 mpc85xx_add_bridge(np); 99 fsl_add_bridge(np, 1);
99 }
100 of_node_put(np); 100 of_node_put(np);
101#endif 101#endif
102 102
@@ -208,4 +208,5 @@ define_machine(mpc85xx_mds) {
208 .restart = mpc85xx_restart, 208 .restart = mpc85xx_restart,
209 .calibrate_decr = generic_calibrate_decr, 209 .calibrate_decr = generic_calibrate_decr,
210 .progress = udbg_progress, 210 .progress = udbg_progress,
211 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
211}; 212};
diff --git a/arch/powerpc/platforms/85xx/pci.c b/arch/powerpc/platforms/85xx/pci.c
deleted file mode 100644
index 8118417b7364..000000000000
--- a/arch/powerpc/platforms/85xx/pci.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * FSL SoC setup code
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/stddef.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/irq.h>
19#include <linux/module.h>
20
21#include <asm/system.h>
22#include <asm/atomic.h>
23#include <asm/io.h>
24#include <asm/pci-bridge.h>
25#include <asm/prom.h>
26#include <sysdev/fsl_soc.h>
27
28#undef DEBUG
29
30#ifdef DEBUG
31#define DBG(x...) printk(x)
32#else
33#define DBG(x...)
34#endif
35
36#ifdef CONFIG_PCI
37int __init mpc85xx_add_bridge(struct device_node *dev)
38{
39 int len;
40 struct pci_controller *hose;
41 struct resource rsrc;
42 const int *bus_range;
43 int primary = 1, has_address = 0;
44 phys_addr_t immr = get_immrbase();
45
46 DBG("Adding PCI host bridge %s\n", dev->full_name);
47
48 /* Fetch host bridge registers address */
49 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
50
51 /* Get bus range if any */
52 bus_range = of_get_property(dev, "bus-range", &len);
53 if (bus_range == NULL || len < 2 * sizeof(int)) {
54 printk(KERN_WARNING "Can't get bus-range for %s, assume"
55 " bus 0\n", dev->full_name);
56 }
57
58 pci_assign_all_buses = 1;
59 hose = pcibios_alloc_controller(dev);
60 if (!hose)
61 return -ENOMEM;
62
63 hose->first_busno = bus_range ? bus_range[0] : 0;
64 hose->last_busno = bus_range ? bus_range[1] : 0xff;
65
66 /* PCI 1 */
67 if ((rsrc.start & 0xfffff) == 0x8000) {
68 setup_indirect_pci(hose, immr + 0x8000, immr + 0x8004);
69 }
70 /* PCI 2 */
71 if ((rsrc.start & 0xfffff) == 0x9000) {
72 setup_indirect_pci(hose, immr + 0x9000, immr + 0x9004);
73 primary = 0;
74 }
75
76 printk(KERN_INFO "Found MPC85xx PCI host bridge at 0x%016llx. "
77 "Firmware bus number: %d->%d\n",
78 (unsigned long long)rsrc.start, hose->first_busno,
79 hose->last_busno);
80
81 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
82 hose, hose->cfg_addr, hose->cfg_data);
83
84 /* Interpret the "ranges" property */
85 /* This also maps the I/O region and sets isa_io/mem_base */
86 pci_process_bridge_OF_ranges(hose, dev, primary);
87
88 return 0;
89}
90
91#endif
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 0faebfdc1596..343b76d0d793 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -14,8 +14,7 @@ endchoice
14 14
15config MPC8641 15config MPC8641
16 bool 16 bool
17 select PPC_INDIRECT_PCI 17 select FSL_PCI if PCI
18 select PPC_INDIRECT_PCI_BE
19 select PPC_UDBG_16550 18 select PPC_UDBG_16550
20 select MPIC 19 select MPIC
21 default y if MPC8641_HPCN 20 default y if MPC8641_HPCN
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index 418fd8f4d268..3376c7767f2d 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -4,4 +4,3 @@
4 4
5obj-$(CONFIG_SMP) += mpc86xx_smp.o 5obj-$(CONFIG_SMP) += mpc86xx_smp.o
6obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o 6obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
7obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h b/arch/powerpc/platforms/86xx/mpc86xx.h
index 23f7ed2a7f88..525ffa1904f9 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx.h
+++ b/arch/powerpc/platforms/86xx/mpc86xx.h
@@ -15,11 +15,6 @@
15 * mpc86xx_* files. Mostly for use by mpc86xx_setup(). 15 * mpc86xx_* files. Mostly for use by mpc86xx_setup().
16 */ 16 */
17 17
18extern int mpc86xx_add_bridge(struct device_node *dev);
19
20extern int mpc86xx_exclude_device(struct pci_controller *hose,
21 u_char bus, u_char devfn);
22
23extern void __init mpc86xx_smp_init(void); 18extern void __init mpc86xx_smp_init(void);
24 19
25#endif /* __MPC86XX_H__ */ 20#endif /* __MPC86XX_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 5b01ec7c13dc..e9eaa0749ae6 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -31,6 +31,7 @@
31 31
32#include <asm/mpic.h> 32#include <asm/mpic.h>
33 33
34#include <sysdev/fsl_pci.h>
34#include <sysdev/fsl_soc.h> 35#include <sysdev/fsl_soc.h>
35 36
36#include "mpc86xx.h" 37#include "mpc86xx.h"
@@ -344,8 +345,14 @@ mpc86xx_hpcn_setup_arch(void)
344 } 345 }
345 346
346#ifdef CONFIG_PCI 347#ifdef CONFIG_PCI
347 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 348 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
348 mpc86xx_add_bridge(np); 349 struct resource rsrc;
350 of_address_to_resource(np, 0, &rsrc);
351 if ((rsrc.start & 0xfffff) == 0x8000)
352 fsl_add_bridge(np, 1);
353 else
354 fsl_add_bridge(np, 0);
355 }
349#endif 356#endif
350 357
351 printk("MPC86xx HPCN board from Freescale Semiconductor\n"); 358 printk("MPC86xx HPCN board from Freescale Semiconductor\n");
@@ -424,7 +431,6 @@ mpc86xx_time_init(void)
424 return 0; 431 return 0;
425} 432}
426 433
427
428define_machine(mpc86xx_hpcn) { 434define_machine(mpc86xx_hpcn) {
429 .name = "MPC86xx HPCN", 435 .name = "MPC86xx HPCN",
430 .probe = mpc86xx_hpcn_probe, 436 .probe = mpc86xx_hpcn_probe,
@@ -436,4 +442,5 @@ define_machine(mpc86xx_hpcn) {
436 .time_init = mpc86xx_time_init, 442 .time_init = mpc86xx_time_init,
437 .calibrate_decr = generic_calibrate_decr, 443 .calibrate_decr = generic_calibrate_decr,
438 .progress = udbg_progress, 444 .progress = udbg_progress,
445 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
439}; 446};
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
deleted file mode 100644
index 73cd5b05a84e..000000000000
--- a/arch/powerpc/platforms/86xx/pci.c
+++ /dev/null
@@ -1,238 +0,0 @@
1/*
2 * MPC86XX pci setup code
3 *
4 * Recode: ZHANG WEI <wei.zhang@freescale.com>
5 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
6 *
7 * Copyright 2006 Freescale Semiconductor Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/types.h>
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include <linux/serial.h>
20
21#include <asm/system.h>
22#include <asm/atomic.h>
23#include <asm/io.h>
24#include <asm/prom.h>
25#include <asm/pci-bridge.h>
26#include <sysdev/fsl_soc.h>
27#include <sysdev/fsl_pcie.h>
28
29#include "mpc86xx.h"
30
31#undef DEBUG
32
33#ifdef DEBUG
34#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
35#else
36#define DBG(fmt, args...)
37#endif
38
39struct pcie_outbound_window_regs {
40 uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
41 uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
42 uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
43 char res1[4];
44 uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
45 char res2[12];
46};
47
48struct pcie_inbound_window_regs {
49 uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
50 char res1[4];
51 uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
52 uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
53 uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
54 char res2[12];
55};
56
57static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
58{
59 volatile struct ccsr_pex *pcie;
60 volatile struct pcie_outbound_window_regs *pcieow;
61 volatile struct pcie_inbound_window_regs *pcieiw;
62 int i = 0;
63
64 DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
65 rsrc->end - rsrc->start + 1);
66 pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
67
68 /* Disable all windows (except pexowar0 since its ignored) */
69 pcie->pexowar1 = 0;
70 pcie->pexowar2 = 0;
71 pcie->pexowar3 = 0;
72 pcie->pexowar4 = 0;
73 pcie->pexiwar1 = 0;
74 pcie->pexiwar2 = 0;
75 pcie->pexiwar3 = 0;
76
77 pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
78 pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
79
80 /* Setup outbound MEM window */
81 for(i = 0; i < 3; i++)
82 if (hose->mem_resources[i].flags & IORESOURCE_MEM){
83 DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
84 hose->mem_resources[i].start,
85 hose->mem_resources[i].end
86 - hose->mem_resources[i].start + 1);
87 pcieow->pexotar = (hose->mem_resources[i].start) >> 12
88 & 0x000fffff;
89 pcieow->pexotear = 0;
90 pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
91 & 0x000fffff;
92 /* Enable, Mem R/W */
93 pcieow->pexowar = 0x80044000 |
94 (__ilog2(hose->mem_resources[i].end
95 - hose->mem_resources[i].start + 1)
96 - 1);
97 pcieow++;
98 }
99
100 /* Setup outbound IO window */
101 if (hose->io_resource.flags & IORESOURCE_IO){
102 DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
103 hose->io_resource.start,
104 hose->io_resource.end - hose->io_resource.start + 1,
105 hose->io_base_phys);
106 pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
107 pcieow->pexotear = 0;
108 pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
109 /* Enable, IO R/W */
110 pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
111 - hose->io_resource.start + 1) - 1);
112 }
113
114 /* Setup 2G inbound Memory Window @ 0 */
115 pcieiw->pexitar = 0x00000000;
116 pcieiw->pexiwbar = 0x00000000;
117 /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
118 pcieiw->pexiwar = 0xa0f5501e;
119}
120
121static void __init
122mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
123{
124 u16 cmd;
125
126 DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
127 pcie_offset, pcie_size);
128
129 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
130 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
131 | PCI_COMMAND_IO;
132 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
133
134 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
135}
136
137static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
138{
139 struct resource *res;
140 int i, res_idx = PCI_BRIDGE_RESOURCES;
141 struct pci_controller *hose;
142
143 /*
144 * Make the bridge be transparent.
145 */
146 dev->transparent = 1;
147
148 hose = pci_bus_to_host(dev->bus);
149 if (!hose) {
150 printk(KERN_ERR "Can't find hose for bus %d\n",
151 dev->bus->number);
152 return;
153 }
154
155 if (hose->io_resource.flags) {
156 res = &dev->resource[res_idx++];
157 res->start = hose->io_resource.start;
158 res->end = hose->io_resource.end;
159 res->flags = hose->io_resource.flags;
160 }
161
162 for (i = 0; i < 3; i++) {
163 res = &dev->resource[res_idx + i];
164 res->start = hose->mem_resources[i].start;
165 res->end = hose->mem_resources[i].end;
166 res->flags = hose->mem_resources[i].flags;
167 }
168}
169
170
171DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
172DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
173
174#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
175#define PCIE_LTSSM_L0 0x16 /* L0 state */
176
177int __init mpc86xx_add_bridge(struct device_node *dev)
178{
179 int len;
180 struct pci_controller *hose;
181 struct resource rsrc;
182 const int *bus_range;
183 int has_address = 0;
184 int primary = 0;
185 u16 val;
186
187 DBG("Adding PCIE host bridge %s\n", dev->full_name);
188
189 /* Fetch host bridge registers address */
190 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
191
192 /* Get bus range if any */
193 bus_range = of_get_property(dev, "bus-range", &len);
194 if (bus_range == NULL || len < 2 * sizeof(int))
195 printk(KERN_WARNING "Can't get bus-range for %s, assume"
196 " bus 0\n", dev->full_name);
197
198 pci_assign_all_buses = 1;
199 hose = pcibios_alloc_controller(dev);
200 if (!hose)
201 return -ENOMEM;
202
203 hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
204 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
205
206 hose->first_busno = bus_range ? bus_range[0] : 0x0;
207 hose->last_busno = bus_range ? bus_range[1] : 0xff;
208
209 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
210
211 /* Probe the hose link training status */
212 early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
213 if (val < PCIE_LTSSM_L0)
214 return -ENXIO;
215
216 /* Setup the PCIE host controller. */
217 mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
218
219 if ((rsrc.start & 0xfffff) == 0x8000)
220 primary = 1;
221
222 printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
223 "Firmware bus number: %d->%d\n",
224 (unsigned long) rsrc.start,
225 hose->first_busno, hose->last_busno);
226
227 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
228 hose, hose->cfg_addr, hose->cfg_data);
229
230 /* Interpret the "ranges" property */
231 /* This also maps the I/O region and sets isa_io/mem_base */
232 pci_process_bridge_OF_ranges(hose, dev, primary);
233
234 /* Setup PEX window registers */
235 setup_pcie_atmu(hose, &rsrc);
236
237 return 0;
238}
diff --git a/arch/powerpc/platforms/chrp/pci.c b/arch/powerpc/platforms/chrp/pci.c
index 3690624e49d4..28d1647b204e 100644
--- a/arch/powerpc/platforms/chrp/pci.c
+++ b/arch/powerpc/platforms/chrp/pci.c
@@ -181,7 +181,7 @@ setup_python(struct pci_controller *hose, struct device_node *dev)
181 } 181 }
182 iounmap(reg); 182 iounmap(reg);
183 183
184 setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); 184 setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0);
185} 185}
186 186
187/* Marvell Discovery II based Pegasos 2 */ 187/* Marvell Discovery II based Pegasos 2 */
@@ -277,13 +277,14 @@ chrp_find_bridges(void)
277 hose->cfg_data = p; 277 hose->cfg_data = p;
278 gg2_pci_config_base = p; 278 gg2_pci_config_base = p;
279 } else if (is_pegasos == 1) { 279 } else if (is_pegasos == 1) {
280 setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); 280 setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0);
281 } else if (is_pegasos == 2) { 281 } else if (is_pegasos == 2) {
282 setup_peg2(hose, dev); 282 setup_peg2(hose, dev);
283 } else if (!strncmp(model, "IBM,CPC710", 10)) { 283 } else if (!strncmp(model, "IBM,CPC710", 10)) {
284 setup_indirect_pci(hose, 284 setup_indirect_pci(hose,
285 r.start + 0x000f8000, 285 r.start + 0x000f8000,
286 r.start + 0x000f8010); 286 r.start + 0x000f8010,
287 0);
287 if (index == 0) { 288 if (index == 0) {
288 dma = of_get_property(dev, "system-dma-base", 289 dma = of_get_property(dev, "system-dma-base",
289 &len); 290 &len);
diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c
index f4d0a7a603f5..bd5ca58345a1 100644
--- a/arch/powerpc/platforms/embedded6xx/linkstation.c
+++ b/arch/powerpc/platforms/embedded6xx/linkstation.c
@@ -73,7 +73,7 @@ static int __init linkstation_add_bridge(struct device_node *dev)
73 return -ENOMEM; 73 return -ENOMEM;
74 hose->first_busno = bus_range ? bus_range[0] : 0; 74 hose->first_busno = bus_range ? bus_range[0] : 0;
75 hose->last_busno = bus_range ? bus_range[1] : 0xff; 75 hose->last_busno = bus_range ? bus_range[1] : 0xff;
76 setup_indirect_pci(hose, 0xfec00000, 0xfee00000); 76 setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
77 77
78 /* Interpret the "ranges" property */ 78 /* Interpret the "ranges" property */
79 /* This also maps the I/O region and sets isa_io/mem_base */ 79 /* This also maps the I/O region and sets isa_io/mem_base */
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 484eb4e0e9db..08ce31e612c2 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PPC_PMI) += pmi.o
12obj-$(CONFIG_U3_DART) += dart_iommu.o 12obj-$(CONFIG_U3_DART) += dart_iommu.o
13obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o 13obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
14obj-$(CONFIG_FSL_SOC) += fsl_soc.o 14obj-$(CONFIG_FSL_SOC) += fsl_soc.o
15obj-$(CONFIG_FSL_PCI) += fsl_pci.o
15obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 16obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
16obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 17obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
17mv64x60-$(CONFIG_PCI) += mv64x60_pci.o 18mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
new file mode 100644
index 000000000000..51c223385feb
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -0,0 +1,257 @@
1/*
2 * MPC85xx/86xx PCI/PCIE support routing.
3 *
4 * Copyright 2007 Freescale Semiconductor, Inc
5 *
6 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
7 * Recode: ZHANG WEI <wei.zhang@freescale.com>
8 * Rewrite the routing for Frescale PCI and PCI Express
9 * Roy Zang <tie-fei.zang@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <linux/kernel.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/bootmem.h>
22
23#include <asm/io.h>
24#include <asm/prom.h>
25#include <asm/pci-bridge.h>
26#include <asm/machdep.h>
27#include <sysdev/fsl_soc.h>
28#include <sysdev/fsl_pci.h>
29
30/* atmu setup for fsl pci/pcie controller */
31void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
32{
33 struct ccsr_pci __iomem *pci;
34 int i;
35
36 pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start,
37 rsrc->end - rsrc->start + 1);
38 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
39
40 /* Disable all windows (except powar0 since its ignored) */
41 for(i = 1; i < 5; i++)
42 out_be32(&pci->pow[i].powar, 0);
43 for(i = 0; i < 3; i++)
44 out_be32(&pci->piw[i].piwar, 0);
45
46 /* Setup outbound MEM window */
47 for(i = 0; i < 3; i++)
48 if (hose->mem_resources[i].flags & IORESOURCE_MEM){
49 pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
50 hose->mem_resources[i].start,
51 hose->mem_resources[i].end
52 - hose->mem_resources[i].start + 1);
53 out_be32(&pci->pow[i+1].potar,
54 (hose->mem_resources[i].start >> 12)
55 & 0x000fffff);
56 out_be32(&pci->pow[i+1].potear, 0);
57 out_be32(&pci->pow[i+1].powbar,
58 (hose->mem_resources[i].start >> 12)
59 & 0x000fffff);
60 /* Enable, Mem R/W */
61 out_be32(&pci->pow[i+1].powar, 0x80044000
62 | (__ilog2(hose->mem_resources[i].end
63 - hose->mem_resources[i].start + 1) - 1));
64 }
65
66 /* Setup outbound IO window */
67 if (hose->io_resource.flags & IORESOURCE_IO){
68 pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
69 hose->io_resource.start,
70 hose->io_resource.end - hose->io_resource.start + 1,
71 hose->io_base_phys);
72 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)
73 & 0x000fffff);
74 out_be32(&pci->pow[i+1].potear, 0);
75 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)
76 & 0x000fffff);
77 /* Enable, IO R/W */
78 out_be32(&pci->pow[i+1].powar, 0x80088000
79 | (__ilog2(hose->io_resource.end
80 - hose->io_resource.start + 1) - 1));
81 }
82
83 /* Setup 2G inbound Memory Window @ 1 */
84 out_be32(&pci->piw[2].pitar, 0x00000000);
85 out_be32(&pci->piw[2].piwbar,0x00000000);
86 out_be32(&pci->piw[2].piwar, PIWAR_2G);
87}
88
89void __init setup_pci_cmd(struct pci_controller *hose)
90{
91 u16 cmd;
92 int cap_x;
93
94 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
95 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
96 | PCI_COMMAND_IO;
97 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
98
99 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
100 if (cap_x) {
101 int pci_x_cmd = cap_x + PCI_X_CMD;
102 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
103 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
104 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
105 } else {
106 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
107 }
108}
109
110static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
111{
112 struct resource *res;
113 int i, res_idx = PCI_BRIDGE_RESOURCES;
114 struct pci_controller *hose;
115
116 /* if we aren't a PCIe don't bother */
117 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
118 return ;
119
120 /*
121 * Make the bridge be transparent.
122 */
123 dev->transparent = 1;
124
125 hose = pci_bus_to_host(dev->bus);
126 if (!hose) {
127 printk(KERN_ERR "Can't find hose for bus %d\n",
128 dev->bus->number);
129 return;
130 }
131
132 /* Clear out any of the virtual P2P bridge registers */
133 pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0);
134 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0);
135 pci_write_config_byte(dev, PCI_IO_BASE, 0x10);
136 pci_write_config_byte(dev, PCI_IO_LIMIT, 0);
137 pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10);
138 pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
139 pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0);
140 pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
141 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
142 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
143
144 if (hose->io_resource.flags) {
145 res = &dev->resource[res_idx++];
146 res->start = hose->io_resource.start;
147 res->end = hose->io_resource.end;
148 res->flags = hose->io_resource.flags;
149 update_bridge_resource(dev, res);
150 }
151
152 for (i = 0; i < 3; i++) {
153 res = &dev->resource[res_idx + i];
154 res->start = hose->mem_resources[i].start;
155 res->end = hose->mem_resources[i].end;
156 res->flags = hose->mem_resources[i].flags;
157 update_bridge_resource(dev, res);
158 }
159}
160
161int __init fsl_pcie_check_link(struct pci_controller *hose)
162{
163 u16 val;
164 early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
165 if (val < PCIE_LTSSM_L0)
166 return 1;
167 return 0;
168}
169
170void fsl_pcibios_fixup_bus(struct pci_bus *bus)
171{
172 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
173 int i;
174
175 /* deal with bogus pci_bus when we don't have anything connected on PCIe */
176 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
177 if (bus->parent) {
178 for (i = 0; i < 4; ++i)
179 bus->resource[i] = bus->parent->resource[i];
180 }
181 }
182}
183
184int __init fsl_add_bridge(struct device_node *dev, int is_primary)
185{
186 int len;
187 struct pci_controller *hose;
188 struct resource rsrc;
189 const int *bus_range;
190
191 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
192
193 /* Fetch host bridge registers address */
194 if (of_address_to_resource(dev, 0, &rsrc)) {
195 printk(KERN_WARNING "Can't get pci register base!");
196 return -ENOMEM;
197 }
198
199 /* Get bus range if any */
200 bus_range = of_get_property(dev, "bus-range", &len);
201 if (bus_range == NULL || len < 2 * sizeof(int))
202 printk(KERN_WARNING "Can't get bus-range for %s, assume"
203 " bus 0\n", dev->full_name);
204
205 pci_assign_all_buses = 1;
206 hose = pcibios_alloc_controller(dev);
207 if (!hose)
208 return -ENOMEM;
209
210 hose->first_busno = bus_range ? bus_range[0] : 0x0;
211 hose->last_busno = bus_range ? bus_range[1] : 0xff;
212
213 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
214 PPC_INDIRECT_TYPE_BIG_ENDIAN);
215 setup_pci_cmd(hose);
216
217 /* check PCI express link status */
218 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
219 hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
220 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
221 if (fsl_pcie_check_link(hose))
222 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
223 }
224
225 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx."
226 "Firmware bus number: %d->%d\n",
227 (unsigned long long)rsrc.start, hose->first_busno,
228 hose->last_busno);
229
230 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
231 hose, hose->cfg_addr, hose->cfg_data);
232
233 /* Interpret the "ranges" property */
234 /* This also maps the I/O region and sets isa_io/mem_base */
235 pci_process_bridge_OF_ranges(hose, dev, is_primary);
236
237 /* Setup PEX window registers */
238 setup_pci_atmu(hose, &rsrc);
239
240 return 0;
241}
242
243DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_transparent);
244DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_transparent);
245DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_transparent);
246DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_transparent);
247DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_transparent);
248DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_transparent);
249DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_transparent);
250DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_transparent);
251DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_transparent);
252DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_transparent);
253DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_transparent);
254DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent);
255DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent);
256DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent);
257DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent);
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
new file mode 100644
index 000000000000..37b04ad26571
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -0,0 +1,88 @@
1/*
2 * MPC85xx/86xx PCI Express structure define
3 *
4 * Copyright 2007 Freescale Semiconductor, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifdef __KERNEL__
14#ifndef __POWERPC_FSL_PCI_H
15#define __POWERPC_FSL_PCI_H
16
17#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
18#define PCIE_LTSSM_L0 0x16 /* L0 state */
19#define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
20
21/* PCI/PCI Express outbound window reg */
22struct pci_outbound_window_regs {
23 __be32 potar; /* 0x.0 - Outbound translation address register */
24 __be32 potear; /* 0x.4 - Outbound translation extended address register */
25 __be32 powbar; /* 0x.8 - Outbound window base address register */
26 u8 res1[4];
27 __be32 powar; /* 0x.10 - Outbound window attributes register */
28 u8 res2[12];
29};
30
31/* PCI/PCI Express inbound window reg */
32struct pci_inbound_window_regs {
33 __be32 pitar; /* 0x.0 - Inbound translation address register */
34 u8 res1[4];
35 __be32 piwbar; /* 0x.8 - Inbound window base address register */
36 __be32 piwbear; /* 0x.c - Inbound window base extended address register */
37 __be32 piwar; /* 0x.10 - Inbound window attributes register */
38 u8 res2[12];
39};
40
41/* PCI/PCI Express IO block registers for 85xx/86xx */
42struct ccsr_pci {
43 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
44 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
45 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
46 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
47 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
48 u8 res2[12];
49 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
50 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
51 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
52 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
53 u8 res3[3024];
54
55/* PCI/PCI Express outbound window 0-4
56 * Window 0 is the default window and is the only window enabled upon reset.
57 * The default outbound register set is used when a transaction misses
58 * in all of the other outbound windows.
59 */
60 struct pci_outbound_window_regs pow[5];
61
62 u8 res14[256];
63
64/* PCI/PCI Express inbound window 3-1
65 * inbound window 1 supports only a 32-bit base address and does not
66 * define an inbound window base extended address register.
67 */
68 struct pci_inbound_window_regs piw[3];
69
70 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
71 u8 res21[4];
72 __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
73 u8 res22[4];
74 __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
75 u8 res23[12];
76 __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
77 u8 res24[4];
78 __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
79 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
80 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
81 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
82};
83
84extern int fsl_add_bridge(struct device_node *dev, int is_primary);
85extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
86
87#endif /* __POWERPC_FSL_PCI_H */
88#endif /* __KERNEL__ */
diff --git a/arch/powerpc/sysdev/fsl_pcie.h b/arch/powerpc/sysdev/fsl_pcie.h
deleted file mode 100644
index 8d9779c84bea..000000000000
--- a/arch/powerpc/sysdev/fsl_pcie.h
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * MPC85xx/86xx PCI Express structure define
3 *
4 * Copyright 2007 Freescale Semiconductor, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifdef __KERNEL__
14#ifndef __POWERPC_FSL_PCIE_H
15#define __POWERPC_FSL_PCIE_H
16
17/* PCIE Express IO block registers in 85xx/86xx */
18
19struct ccsr_pex {
20 __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
21 __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
22 u8 __iomem res1[4];
23 __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
24 __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
25 u8 __iomem res2[12];
26 __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
27 __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
28 __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
29 __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */
30 u8 __iomem res3[3024];
31 __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
32 __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
33 u8 __iomem res4[8];
34 __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
35 u8 __iomem res5[12];
36 __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
37 __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
38 __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
39 u8 __iomem res6[4];
40 __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
41 u8 __iomem res7[12];
42 __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
43 __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
44 __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
45 u8 __iomem res8[4];
46 __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
47 u8 __iomem res9[12];
48 __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
49 __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
50 __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
51 u8 __iomem res10[4];
52 __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
53 u8 __iomem res11[12];
54 __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
55 __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
56 __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
57 u8 __iomem res12[4];
58 __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
59 u8 __iomem res13[12];
60 u8 __iomem res14[256];
61 __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
62 u8 __iomem res15[4];
63 __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
64 __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
65 __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
66 u8 __iomem res16[12];
67 __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
68 u8 __iomem res17[4];
69 __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
70 __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
71 __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
72 u8 __iomem res18[12];
73 __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
74 u8 __iomem res19[4];
75 __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
76 __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
77 __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
78 u8 __iomem res20[12];
79 __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */
80 u8 __iomem res21[4];
81 __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
82 u8 __iomem res22[4];
83 __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */
84 u8 __iomem res23[12];
85 __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
86 u8 __iomem res24[4];
87 __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
88 __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
89 __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
90 __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
91};
92
93#endif /* __POWERPC_FSL_PCIE_H */
94#endif /* __KERNEL__ */
diff --git a/arch/powerpc/sysdev/grackle.c b/arch/powerpc/sysdev/grackle.c
index 42053625f498..11ad5622eb76 100644
--- a/arch/powerpc/sysdev/grackle.c
+++ b/arch/powerpc/sysdev/grackle.c
@@ -55,7 +55,7 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
55 55
56void __init setup_grackle(struct pci_controller *hose) 56void __init setup_grackle(struct pci_controller *hose)
57{ 57{
58 setup_indirect_pci(hose, 0xfec00000, 0xfee00000); 58 setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
59 if (machine_is_compatible("PowerMac1,1")) 59 if (machine_is_compatible("PowerMac1,1"))
60 pci_assign_all_buses = 1; 60 pci_assign_all_buses = 1;
61 if (machine_is_compatible("AAPL,PowerBook1998")) 61 if (machine_is_compatible("AAPL,PowerBook1998"))
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index c7e6e859b393..a8ac2dfdd3d4 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -20,12 +20,6 @@
20#include <asm/pci-bridge.h> 20#include <asm/pci-bridge.h>
21#include <asm/machdep.h> 21#include <asm/machdep.h>
22 22
23#ifdef CONFIG_PPC_INDIRECT_PCI_BE
24#define PCI_CFG_OUT out_be32
25#else
26#define PCI_CFG_OUT out_le32
27#endif
28
29static int 23static int
30indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 24indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
31 int len, u32 *val) 25 int len, u32 *val)
@@ -35,10 +29,17 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
35 u8 cfg_type = 0; 29 u8 cfg_type = 0;
36 u32 bus_no, reg; 30 u32 bus_no, reg;
37 31
32 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
33 if (bus->number != hose->first_busno)
34 return PCIBIOS_DEVICE_NOT_FOUND;
35 if (devfn != 0)
36 return PCIBIOS_DEVICE_NOT_FOUND;
37 }
38
38 if (ppc_md.pci_exclude_device) 39 if (ppc_md.pci_exclude_device)
39 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 40 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
40 return PCIBIOS_DEVICE_NOT_FOUND; 41 return PCIBIOS_DEVICE_NOT_FOUND;
41 42
42 if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE) 43 if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
43 if (bus->number != hose->first_busno) 44 if (bus->number != hose->first_busno)
44 cfg_type = 1; 45 cfg_type = 1;
@@ -51,9 +52,12 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
51 else 52 else
52 reg = offset & 0xfc; 53 reg = offset & 0xfc;
53 54
54 PCI_CFG_OUT(hose->cfg_addr, 55 if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
55 (0x80000000 | (bus_no << 16) 56 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
56 | (devfn << 8) | reg | cfg_type)); 57 (devfn << 8) | reg | cfg_type));
58 else
59 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
60 (devfn << 8) | reg | cfg_type));
57 61
58 /* 62 /*
59 * Note: the caller has already checked that offset is 63 * Note: the caller has already checked that offset is
@@ -83,6 +87,13 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
83 u8 cfg_type = 0; 87 u8 cfg_type = 0;
84 u32 bus_no, reg; 88 u32 bus_no, reg;
85 89
90 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
91 if (bus->number != hose->first_busno)
92 return PCIBIOS_DEVICE_NOT_FOUND;
93 if (devfn != 0)
94 return PCIBIOS_DEVICE_NOT_FOUND;
95 }
96
86 if (ppc_md.pci_exclude_device) 97 if (ppc_md.pci_exclude_device)
87 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 98 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
88 return PCIBIOS_DEVICE_NOT_FOUND; 99 return PCIBIOS_DEVICE_NOT_FOUND;
@@ -99,9 +110,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
99 else 110 else
100 reg = offset & 0xfc; 111 reg = offset & 0xfc;
101 112
102 PCI_CFG_OUT(hose->cfg_addr, 113 if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
103 (0x80000000 | (bus_no << 16) 114 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
104 | (devfn << 8) | reg | cfg_type)); 115 (devfn << 8) | reg | cfg_type));
116 else
117 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
118 (devfn << 8) | reg | cfg_type));
105 119
106 /* surpress setting of PCI_PRIMARY_BUS */ 120 /* surpress setting of PCI_PRIMARY_BUS */
107 if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS) 121 if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
@@ -135,24 +149,15 @@ static struct pci_ops indirect_pci_ops =
135}; 149};
136 150
137void __init 151void __init
138setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem * cfg_addr, 152setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data, u32 flags)
139 void __iomem * cfg_data)
140{
141 hose->cfg_addr = cfg_addr;
142 hose->cfg_data = cfg_data;
143 hose->ops = &indirect_pci_ops;
144}
145
146void __init
147setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
148{ 153{
149 unsigned long base = cfg_addr & PAGE_MASK; 154 unsigned long base = cfg_addr & PAGE_MASK;
150 void __iomem *mbase, *addr, *data; 155 void __iomem *mbase;
151 156
152 mbase = ioremap(base, PAGE_SIZE); 157 mbase = ioremap(base, PAGE_SIZE);
153 addr = mbase + (cfg_addr & ~PAGE_MASK); 158 hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
154 if ((cfg_data & PAGE_MASK) != base) 159 if ((cfg_data & PAGE_MASK) != base)
155 mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); 160 mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
156 data = mbase + (cfg_data & ~PAGE_MASK); 161 hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
157 setup_indirect_pci_nomap(hose, addr, data); 162 hose->ops = &indirect_pci_ops;
158} 163}
diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c
index 45db86c2363c..9b3baa7317d7 100644
--- a/arch/powerpc/sysdev/mv64x60_pci.c
+++ b/arch/powerpc/sysdev/mv64x60_pci.c
@@ -144,7 +144,7 @@ static int __init mv64x60_add_bridge(struct device_node *dev)
144 hose->first_busno = bus_range ? bus_range[0] : 0; 144 hose->first_busno = bus_range ? bus_range[0] : 0;
145 hose->last_busno = bus_range ? bus_range[1] : 0xff; 145 hose->last_busno = bus_range ? bus_range[1] : 0xff;
146 146
147 setup_indirect_pci(hose, rsrc.start, rsrc.start + 4); 147 setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0);
148 hose->self_busno = hose->first_busno; 148 hose->self_busno = hose->first_busno;
149 149
150 printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. " 150 printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index e72c2a60853c..d53e0eb1de16 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -45,10 +45,17 @@ struct pci_controller {
45 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS 45 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
46 * to determine which bus number to match on when generating type0 46 * to determine which bus number to match on when generating type0
47 * config cycles 47 * config cycles
48 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
49 * hanging if we don't have link and try to do config cycles to
50 * anything but the PHB. Only allow talking to the PHB if this is
51 * set.
52 * BIG_ENDIAN - cfg_addr is a big endian register
48 */ 53 */
49#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) 54#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
50#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) 55#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
51#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) 56#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
57#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008)
58#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010)
52 u32 indirect_type; 59 u32 indirect_type;
53 60
54 /* Currently, we limit ourselves to 1 IO range and 3 mem 61 /* Currently, we limit ourselves to 1 IO range and 3 mem
@@ -79,11 +86,14 @@ int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
79int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, 86int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
80 int where, u32 val); 87 int where, u32 val);
81 88
82extern void setup_indirect_pci_nomap(struct pci_controller* hose, 89extern int early_find_capability(struct pci_controller *hose, int bus,
83 void __iomem *cfg_addr, void __iomem *cfg_data); 90 int dev_fn, int cap);
91
84extern void setup_indirect_pci(struct pci_controller* hose, 92extern void setup_indirect_pci(struct pci_controller* hose,
85 u32 cfg_addr, u32 cfg_data); 93 u32 cfg_addr, u32 cfg_data, u32 flags);
86extern void setup_grackle(struct pci_controller *hose); 94extern void setup_grackle(struct pci_controller *hose);
95extern void __init update_bridge_resource(struct pci_dev *dev,
96 struct resource *res);
87 97
88#else 98#else
89 99
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 42d3278c6b56..dc41ad4203b8 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2079,6 +2079,23 @@
2079#define PCI_VENDOR_ID_TDI 0x192E 2079#define PCI_VENDOR_ID_TDI 0x192E
2080#define PCI_DEVICE_ID_TDI_EHCI 0x0101 2080#define PCI_DEVICE_ID_TDI_EHCI 0x0101
2081 2081
2082#define PCI_VENDOR_ID_FREESCALE 0x1957
2083#define PCI_DEVICE_ID_MPC8548E 0x0012
2084#define PCI_DEVICE_ID_MPC8548 0x0013
2085#define PCI_DEVICE_ID_MPC8543E 0x0014
2086#define PCI_DEVICE_ID_MPC8543 0x0015
2087#define PCI_DEVICE_ID_MPC8547E 0x0018
2088#define PCI_DEVICE_ID_MPC8545E 0x0019
2089#define PCI_DEVICE_ID_MPC8545 0x001a
2090#define PCI_DEVICE_ID_MPC8568E 0x0020
2091#define PCI_DEVICE_ID_MPC8568 0x0021
2092#define PCI_DEVICE_ID_MPC8567E 0x0022
2093#define PCI_DEVICE_ID_MPC8567 0x0023
2094#define PCI_DEVICE_ID_MPC8544E 0x0030
2095#define PCI_DEVICE_ID_MPC8544 0x0031
2096#define PCI_DEVICE_ID_MPC8641 0x7010
2097#define PCI_DEVICE_ID_MPC8641D 0x7011
2098
2082#define PCI_VENDOR_ID_PASEMI 0x1959 2099#define PCI_VENDOR_ID_PASEMI 0x1959
2083 2100
2084#define PCI_VENDOR_ID_ATTANSIC 0x1969 2101#define PCI_VENDOR_ID_ATTANSIC 0x1969
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 10:56:14 -0500