diff options
-rw-r--r-- | arch/sh/include/asm/dma-sh.h | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h index e873ecaa5065..0c8f8e14622a 100644 --- a/arch/sh/include/asm/dma-sh.h +++ b/arch/sh/include/asm/dma-sh.h | |||
@@ -11,6 +11,7 @@ | |||
11 | #ifndef __DMA_SH_H | 11 | #ifndef __DMA_SH_H |
12 | #define __DMA_SH_H | 12 | #define __DMA_SH_H |
13 | 13 | ||
14 | #include <asm/dma.h> | ||
14 | #include <cpu/dma.h> | 15 | #include <cpu/dma.h> |
15 | 16 | ||
16 | /* DMAOR contorl: The DMAOR access size is different by CPU.*/ | 17 | /* DMAOR contorl: The DMAOR access size is different by CPU.*/ |
@@ -29,21 +30,21 @@ | |||
29 | #endif | 30 | #endif |
30 | 31 | ||
31 | static int dmte_irq_map[] __maybe_unused = { | 32 | static int dmte_irq_map[] __maybe_unused = { |
32 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4) | 33 | #if (MAX_DMA_CHANNELS >= 4) |
33 | DMTE0_IRQ, | 34 | DMTE0_IRQ, |
34 | DMTE0_IRQ + 1, | 35 | DMTE0_IRQ + 1, |
35 | DMTE0_IRQ + 2, | 36 | DMTE0_IRQ + 2, |
36 | DMTE0_IRQ + 3, | 37 | DMTE0_IRQ + 3, |
37 | #endif | 38 | #endif |
38 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6) | 39 | #if (MAX_DMA_CHANNELS >= 6) |
39 | DMTE4_IRQ, | 40 | DMTE4_IRQ, |
40 | DMTE4_IRQ + 1, | 41 | DMTE4_IRQ + 1, |
41 | #endif | 42 | #endif |
42 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8) | 43 | #if (MAX_DMA_CHANNELS >= 8) |
43 | DMTE6_IRQ, | 44 | DMTE6_IRQ, |
44 | DMTE6_IRQ + 1, | 45 | DMTE6_IRQ + 1, |
45 | #endif | 46 | #endif |
46 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12) | 47 | #if (MAX_DMA_CHANNELS >= 12) |
47 | DMTE8_IRQ, | 48 | DMTE8_IRQ, |
48 | DMTE9_IRQ, | 49 | DMTE9_IRQ, |
49 | DMTE10_IRQ, | 50 | DMTE10_IRQ, |
@@ -85,21 +86,21 @@ static int dmte_irq_map[] __maybe_unused = { | |||
85 | 86 | ||
86 | /* DMA base address */ | 87 | /* DMA base address */ |
87 | static u32 dma_base_addr[] __maybe_unused = { | 88 | static u32 dma_base_addr[] __maybe_unused = { |
88 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4) | 89 | #if (MAX_DMA_CHANNELS >= 4) |
89 | SH_DMAC_BASE0 + 0x00, /* channel 0 */ | 90 | SH_DMAC_BASE0 + 0x00, /* channel 0 */ |
90 | SH_DMAC_BASE0 + 0x10, | 91 | SH_DMAC_BASE0 + 0x10, |
91 | SH_DMAC_BASE0 + 0x20, | 92 | SH_DMAC_BASE0 + 0x20, |
92 | SH_DMAC_BASE0 + 0x30, | 93 | SH_DMAC_BASE0 + 0x30, |
93 | #endif | 94 | #endif |
94 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6) | 95 | #if (MAX_DMA_CHANNELS >= 6) |
95 | SH_DMAC_BASE0 + 0x50, | 96 | SH_DMAC_BASE0 + 0x50, |
96 | SH_DMAC_BASE0 + 0x60, | 97 | SH_DMAC_BASE0 + 0x60, |
97 | #endif | 98 | #endif |
98 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8) | 99 | #if (MAX_DMA_CHANNELS >= 8) |
99 | SH_DMAC_BASE1 + 0x00, | 100 | SH_DMAC_BASE1 + 0x00, |
100 | SH_DMAC_BASE1 + 0x10, | 101 | SH_DMAC_BASE1 + 0x10, |
101 | #endif | 102 | #endif |
102 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12) | 103 | #if (MAX_DMA_CHANNELS >= 12) |
103 | SH_DMAC_BASE1 + 0x20, | 104 | SH_DMAC_BASE1 + 0x20, |
104 | SH_DMAC_BASE1 + 0x30, | 105 | SH_DMAC_BASE1 + 0x30, |
105 | SH_DMAC_BASE1 + 0x50, | 106 | SH_DMAC_BASE1 + 0x50, |