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-rw-r--r--drivers/net/s2io-regs.h116
-rw-r--r--drivers/net/s2io.c246
-rw-r--r--drivers/net/s2io.h1
3 files changed, 278 insertions, 85 deletions
diff --git a/drivers/net/s2io-regs.h b/drivers/net/s2io-regs.h
index 83e3e47a9e3d..aef66e2d98d2 100644
--- a/drivers/net/s2io-regs.h
+++ b/drivers/net/s2io-regs.h
@@ -325,33 +325,66 @@ struct XENA_dev_config {
325#define TXDMA_TPA_INT BIT(5) 325#define TXDMA_TPA_INT BIT(5)
326#define TXDMA_SM_INT BIT(6) 326#define TXDMA_SM_INT BIT(6)
327 u64 pfc_err_reg; 327 u64 pfc_err_reg;
328#define PFC_ECC_SG_ERR BIT(7)
329#define PFC_ECC_DB_ERR BIT(15)
330#define PFC_SM_ERR_ALARM BIT(23)
331#define PFC_MISC_0_ERR BIT(31)
332#define PFC_MISC_1_ERR BIT(32)
333#define PFC_PCIX_ERR BIT(39)
328 u64 pfc_err_mask; 334 u64 pfc_err_mask;
329 u64 pfc_err_alarm; 335 u64 pfc_err_alarm;
330 336
331 u64 tda_err_reg; 337 u64 tda_err_reg;
338#define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8)
339#define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8)
340#define TDA_SM0_ERR_ALARM BIT(22)
341#define TDA_SM1_ERR_ALARM BIT(23)
342#define TDA_PCIX_ERR BIT(39)
332 u64 tda_err_mask; 343 u64 tda_err_mask;
333 u64 tda_err_alarm; 344 u64 tda_err_alarm;
334 345
335 u64 pcc_err_reg; 346 u64 pcc_err_reg;
336#define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8) 347#define PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8)
348#define PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8)
349#define PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8)
350#define PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8)
351#define PCC_SM_ERR_ALARM vBIT(0xff,32,8)
352#define PCC_WR_ERR_ALARM vBIT(0xff,40,8)
353#define PCC_N_SERR vBIT(0xff,48,8)
354#define PCC_6_COF_OV_ERR BIT(56)
355#define PCC_7_COF_OV_ERR BIT(57)
356#define PCC_6_LSO_OV_ERR BIT(58)
357#define PCC_7_LSO_OV_ERR BIT(59)
337#define PCC_ENABLE_FOUR vBIT(0x0F,0,8) 358#define PCC_ENABLE_FOUR vBIT(0x0F,0,8)
338
339 u64 pcc_err_mask; 359 u64 pcc_err_mask;
340 u64 pcc_err_alarm; 360 u64 pcc_err_alarm;
341 361
342 u64 tti_err_reg; 362 u64 tti_err_reg;
363#define TTI_ECC_SG_ERR BIT(7)
364#define TTI_ECC_DB_ERR BIT(15)
365#define TTI_SM_ERR_ALARM BIT(23)
343 u64 tti_err_mask; 366 u64 tti_err_mask;
344 u64 tti_err_alarm; 367 u64 tti_err_alarm;
345 368
346 u64 lso_err_reg; 369 u64 lso_err_reg;
370#define LSO6_SEND_OFLOW BIT(12)
371#define LSO7_SEND_OFLOW BIT(13)
372#define LSO6_ABORT BIT(14)
373#define LSO7_ABORT BIT(15)
374#define LSO6_SM_ERR_ALARM BIT(22)
375#define LSO7_SM_ERR_ALARM BIT(23)
347 u64 lso_err_mask; 376 u64 lso_err_mask;
348 u64 lso_err_alarm; 377 u64 lso_err_alarm;
349 378
350 u64 tpa_err_reg; 379 u64 tpa_err_reg;
380#define TPA_TX_FRM_DROP BIT(7)
381#define TPA_SM_ERR_ALARM BIT(23)
382
351 u64 tpa_err_mask; 383 u64 tpa_err_mask;
352 u64 tpa_err_alarm; 384 u64 tpa_err_alarm;
353 385
354 u64 sm_err_reg; 386 u64 sm_err_reg;
387#define SM_SM_ERR_ALARM BIT(15)
355 u64 sm_err_mask; 388 u64 sm_err_mask;
356 u64 sm_err_alarm; 389 u64 sm_err_alarm;
357 390
@@ -450,22 +483,52 @@ struct XENA_dev_config {
450#define RXDMA_INT_RTI_INT_M BIT(3) 483#define RXDMA_INT_RTI_INT_M BIT(3)
451 484
452 u64 rda_err_reg; 485 u64 rda_err_reg;
486#define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8)
487#define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8)
488#define RDA_FRM_ECC_SG_ERR BIT(23)
489#define RDA_FRM_ECC_DB_N_AERR BIT(31)
490#define RDA_SM1_ERR_ALARM BIT(38)
491#define RDA_SM0_ERR_ALARM BIT(39)
492#define RDA_MISC_ERR BIT(47)
493#define RDA_PCIX_ERR BIT(55)
494#define RDA_RXD_ECC_DB_SERR BIT(63)
453 u64 rda_err_mask; 495 u64 rda_err_mask;
454 u64 rda_err_alarm; 496 u64 rda_err_alarm;
455 497
456 u64 rc_err_reg; 498 u64 rc_err_reg;
499#define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8)
500#define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8)
501#define RC_FTC_ECC_SG_ERR BIT(23)
502#define RC_FTC_ECC_DB_ERR BIT(31)
503#define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8)
504#define RC_FTC_SM_ERR_ALARM BIT(47)
505#define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8)
457 u64 rc_err_mask; 506 u64 rc_err_mask;
458 u64 rc_err_alarm; 507 u64 rc_err_alarm;
459 508
460 u64 prc_pcix_err_reg; 509 u64 prc_pcix_err_reg;
510#define PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8)
511#define PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8)
512#define PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8)
513#define PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8)
514#define PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8)
515#define PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8)
461 u64 prc_pcix_err_mask; 516 u64 prc_pcix_err_mask;
462 u64 prc_pcix_err_alarm; 517 u64 prc_pcix_err_alarm;
463 518
464 u64 rpa_err_reg; 519 u64 rpa_err_reg;
520#define RPA_ECC_SG_ERR BIT(7)
521#define RPA_ECC_DB_ERR BIT(15)
522#define RPA_FLUSH_REQUEST BIT(22)
523#define RPA_SM_ERR_ALARM BIT(23)
524#define RPA_CREDIT_ERR BIT(31)
465 u64 rpa_err_mask; 525 u64 rpa_err_mask;
466 u64 rpa_err_alarm; 526 u64 rpa_err_alarm;
467 527
468 u64 rti_err_reg; 528 u64 rti_err_reg;
529#define RTI_ECC_SG_ERR BIT(7)
530#define RTI_ECC_DB_ERR BIT(15)
531#define RTI_SM_ERR_ALARM BIT(23)
469 u64 rti_err_mask; 532 u64 rti_err_mask;
470 u64 rti_err_alarm; 533 u64 rti_err_alarm;
471 534
@@ -582,17 +645,43 @@ struct XENA_dev_config {
582#define MAC_INT_STATUS_RMAC_INT BIT(1) 645#define MAC_INT_STATUS_RMAC_INT BIT(1)
583 646
584 u64 mac_tmac_err_reg; 647 u64 mac_tmac_err_reg;
585#define TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15) 648#define TMAC_ECC_SG_ERR BIT(7)
586#define TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23) 649#define TMAC_ECC_DB_ERR BIT(15)
587#define TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31) 650#define TMAC_TX_BUF_OVRN BIT(23)
651#define TMAC_TX_CRI_ERR BIT(31)
652#define TMAC_TX_SM_ERR BIT(39)
653#define TMAC_DESC_ECC_SG_ERR BIT(47)
654#define TMAC_DESC_ECC_DB_ERR BIT(55)
655
588 u64 mac_tmac_err_mask; 656 u64 mac_tmac_err_mask;
589 u64 mac_tmac_err_alarm; 657 u64 mac_tmac_err_alarm;
590 658
591 u64 mac_rmac_err_reg; 659 u64 mac_rmac_err_reg;
592#define RMAC_ERR_REG_RX_BUFF_OVRN BIT(0) 660#define RMAC_RX_BUFF_OVRN BIT(0)
593#define RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14) 661#define RMAC_FRM_RCVD_INT BIT(1)
594#define RMAC_ERR_REG_ECC_DB_ERR BIT(15) 662#define RMAC_UNUSED_INT BIT(2)
595#define RMAC_LINK_STATE_CHANGE_INT BIT(31) 663#define RMAC_RTS_PNUM_ECC_SG_ERR BIT(5)
664#define RMAC_RTS_DS_ECC_SG_ERR BIT(6)
665#define RMAC_RD_BUF_ECC_SG_ERR BIT(7)
666#define RMAC_RTH_MAP_ECC_SG_ERR BIT(8)
667#define RMAC_RTH_SPDM_ECC_SG_ERR BIT(9)
668#define RMAC_RTS_VID_ECC_SG_ERR BIT(10)
669#define RMAC_DA_SHADOW_ECC_SG_ERR BIT(11)
670#define RMAC_RTS_PNUM_ECC_DB_ERR BIT(13)
671#define RMAC_RTS_DS_ECC_DB_ERR BIT(14)
672#define RMAC_RD_BUF_ECC_DB_ERR BIT(15)
673#define RMAC_RTH_MAP_ECC_DB_ERR BIT(16)
674#define RMAC_RTH_SPDM_ECC_DB_ERR BIT(17)
675#define RMAC_RTS_VID_ECC_DB_ERR BIT(18)
676#define RMAC_DA_SHADOW_ECC_DB_ERR BIT(19)
677#define RMAC_LINK_STATE_CHANGE_INT BIT(31)
678#define RMAC_RX_SM_ERR BIT(39)
679#define RMAC_SINGLE_ECC_ERR (BIT(5) | BIT(6) | BIT(7) |\
680 BIT(8) | BIT(9) | BIT(10)|\
681 BIT(11))
682#define RMAC_DOUBLE_ECC_ERR (BIT(13) | BIT(14) | BIT(15) |\
683 BIT(16) | BIT(17) | BIT(18)|\
684 BIT(19))
596 u64 mac_rmac_err_mask; 685 u64 mac_rmac_err_mask;
597 u64 mac_rmac_err_alarm; 686 u64 mac_rmac_err_alarm;
598 687
@@ -750,6 +839,7 @@ struct XENA_dev_config {
750 BIT(17) | BIT(19)) 839 BIT(17) | BIT(19))
751#define MC_ERR_REG_ECC_ALL_DBL (BIT(10) | BIT(11) | BIT(12) |\ 840#define MC_ERR_REG_ECC_ALL_DBL (BIT(10) | BIT(11) | BIT(12) |\
752 BIT(13) | BIT(18) | BIT(20)) 841 BIT(13) | BIT(18) | BIT(20))
842#define PLL_LOCK_N BIT(39)
753 u64 mc_err_mask; 843 u64 mc_err_mask;
754 u64 mc_err_alarm; 844 u64 mc_err_alarm;
755 845
@@ -823,11 +913,17 @@ struct XENA_dev_config {
823#define XGXS_INT_MASK_RXGXS BIT(1) 913#define XGXS_INT_MASK_RXGXS BIT(1)
824 914
825 u64 xgxs_txgxs_err_reg; 915 u64 xgxs_txgxs_err_reg;
826#define TXGXS_ECC_DB_ERR BIT(15) 916#define TXGXS_ECC_SG_ERR BIT(7)
917#define TXGXS_ECC_DB_ERR BIT(15)
918#define TXGXS_ESTORE_UFLOW BIT(31)
919#define TXGXS_TX_SM_ERR BIT(39)
920
827 u64 xgxs_txgxs_err_mask; 921 u64 xgxs_txgxs_err_mask;
828 u64 xgxs_txgxs_err_alarm; 922 u64 xgxs_txgxs_err_alarm;
829 923
830 u64 xgxs_rxgxs_err_reg; 924 u64 xgxs_rxgxs_err_reg;
925#define RXGXS_ESTORE_OFLOW BIT(7)
926#define RXGXS_RX_SM_ERR BIT(39)
831 u64 xgxs_rxgxs_err_mask; 927 u64 xgxs_rxgxs_err_mask;
832 u64 xgxs_rxgxs_err_alarm; 928 u64 xgxs_rxgxs_err_alarm;
833 929
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index e7431c58da49..63473027b463 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -892,8 +892,9 @@ static void free_shared_mem(struct s2io_nic *nic)
892 k++; 892 k++;
893 } 893 }
894 kfree(mac_control->rings[i].ba[j]); 894 kfree(mac_control->rings[i].ba[j]);
895 nic->mac_control.stats_info->sw_stat.mem_freed += (sizeof(struct buffAdd) * 895 nic->mac_control.stats_info->sw_stat.mem_freed +=
896 (rxd_count[nic->rxd_mode] + 1)); 896 (sizeof(struct buffAdd) *
897 (rxd_count[nic->rxd_mode] + 1));
897 } 898 }
898 kfree(mac_control->rings[i].ba); 899 kfree(mac_control->rings[i].ba);
899 nic->mac_control.stats_info->sw_stat.mem_freed += 900 nic->mac_control.stats_info->sw_stat.mem_freed +=
@@ -1731,7 +1732,150 @@ static int s2io_link_fault_indication(struct s2io_nic *nic)
1731 else 1732 else
1732 return MAC_RMAC_ERR_TIMER; 1733 return MAC_RMAC_ERR_TIMER;
1733} 1734}
1735/**
1736 * do_s2io_write_bits - update alarm bits in alarm register
1737 * @value: alarm bits
1738 * @flag: interrupt status
1739 * @addr: address value
1740 * Description: update alarm bits in alarm register
1741 * Return Value:
1742 * NONE.
1743 */
1744static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1745{
1746 u64 temp64;
1747
1748 temp64 = readq(addr);
1749
1750 if(flag == ENABLE_INTRS)
1751 temp64 &= ~((u64) value);
1752 else
1753 temp64 |= ((u64) value);
1754 writeq(temp64, addr);
1755}
1734 1756
1757void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1758{
1759 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1760 register u64 gen_int_mask = 0;
1761
1762 if (mask & TX_DMA_INTR) {
1763
1764 gen_int_mask |= TXDMA_INT_M;
1765
1766 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1767 TXDMA_PCC_INT | TXDMA_TTI_INT |
1768 TXDMA_LSO_INT | TXDMA_TPA_INT |
1769 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1770
1771 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1772 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1773 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1774 &bar0->pfc_err_mask);
1775
1776 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1777 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1778 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1779
1780 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1781 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1782 PCC_N_SERR | PCC_6_COF_OV_ERR |
1783 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1784 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1785 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1786
1787 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1788 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1789
1790 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1791 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1792 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1793 flag, &bar0->lso_err_mask);
1794
1795 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1796 flag, &bar0->tpa_err_mask);
1797
1798 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1799
1800 }
1801
1802 if (mask & TX_MAC_INTR) {
1803 gen_int_mask |= TXMAC_INT_M;
1804 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1805 &bar0->mac_int_mask);
1806 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1807 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1808 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1809 flag, &bar0->mac_tmac_err_mask);
1810 }
1811
1812 if (mask & TX_XGXS_INTR) {
1813 gen_int_mask |= TXXGXS_INT_M;
1814 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1815 &bar0->xgxs_int_mask);
1816 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1817 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1818 flag, &bar0->xgxs_txgxs_err_mask);
1819 }
1820
1821 if (mask & RX_DMA_INTR) {
1822 gen_int_mask |= RXDMA_INT_M;
1823 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1824 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1825 flag, &bar0->rxdma_int_mask);
1826 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1827 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1828 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1829 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1830 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1831 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1832 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1833 &bar0->prc_pcix_err_mask);
1834 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1835 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1836 &bar0->rpa_err_mask);
1837 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1838 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1839 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1840 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1841 flag, &bar0->rda_err_mask);
1842 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1843 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1844 flag, &bar0->rti_err_mask);
1845 }
1846
1847 if (mask & RX_MAC_INTR) {
1848 gen_int_mask |= RXMAC_INT_M;
1849 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1850 &bar0->mac_int_mask);
1851 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1852 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1853 RMAC_DOUBLE_ECC_ERR |
1854 RMAC_LINK_STATE_CHANGE_INT,
1855 flag, &bar0->mac_rmac_err_mask);
1856 }
1857
1858 if (mask & RX_XGXS_INTR)
1859 {
1860 gen_int_mask |= RXXGXS_INT_M;
1861 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1862 &bar0->xgxs_int_mask);
1863 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1864 &bar0->xgxs_rxgxs_err_mask);
1865 }
1866
1867 if (mask & MC_INTR) {
1868 gen_int_mask |= MC_INT_M;
1869 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
1870 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1871 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1872 &bar0->mc_err_mask);
1873 }
1874 nic->general_int_mask = gen_int_mask;
1875
1876 /* Remove this line when alarm interrupts are enabled */
1877 nic->general_int_mask = 0;
1878}
1735/** 1879/**
1736 * en_dis_able_nic_intrs - Enable or Disable the interrupts 1880 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1737 * @nic: device private variable, 1881 * @nic: device private variable,
@@ -1746,17 +1890,16 @@ static int s2io_link_fault_indication(struct s2io_nic *nic)
1746static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag) 1890static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1747{ 1891{
1748 struct XENA_dev_config __iomem *bar0 = nic->bar0; 1892 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1749 register u64 val64 = 0, temp64 = 0; 1893 register u64 temp64 = 0, intr_mask = 0;
1894
1895 intr_mask = nic->general_int_mask;
1750 1896
1751 /* Top level interrupt classification */ 1897 /* Top level interrupt classification */
1752 /* PIC Interrupts */ 1898 /* PIC Interrupts */
1753 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) { 1899 if (mask & TX_PIC_INTR) {
1754 /* Enable PIC Intrs in the general intr mask register */ 1900 /* Enable PIC Intrs in the general intr mask register */
1755 val64 = TXPIC_INT_M; 1901 intr_mask |= TXPIC_INT_M;
1756 if (flag == ENABLE_INTRS) { 1902 if (flag == ENABLE_INTRS) {
1757 temp64 = readq(&bar0->general_int_mask);
1758 temp64 &= ~((u64) val64);
1759 writeq(temp64, &bar0->general_int_mask);
1760 /* 1903 /*
1761 * If Hercules adapter enable GPIO otherwise 1904 * If Hercules adapter enable GPIO otherwise
1762 * disable all PCIX, Flash, MDIO, IIC and GPIO 1905 * disable all PCIX, Flash, MDIO, IIC and GPIO
@@ -1765,64 +1908,25 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1765 */ 1908 */
1766 if (s2io_link_fault_indication(nic) == 1909 if (s2io_link_fault_indication(nic) ==
1767 LINK_UP_DOWN_INTERRUPT ) { 1910 LINK_UP_DOWN_INTERRUPT ) {
1768 temp64 = readq(&bar0->pic_int_mask); 1911 do_s2io_write_bits(PIC_INT_GPIO, flag,
1769 temp64 &= ~((u64) PIC_INT_GPIO); 1912 &bar0->pic_int_mask);
1770 writeq(temp64, &bar0->pic_int_mask); 1913 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
1771 temp64 = readq(&bar0->gpio_int_mask); 1914 &bar0->gpio_int_mask);
1772 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP); 1915 } else
1773 writeq(temp64, &bar0->gpio_int_mask);
1774 } else {
1775 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); 1916 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1776 }
1777 /*
1778 * No MSI Support is available presently, so TTI and
1779 * RTI interrupts are also disabled.
1780 */
1781 } else if (flag == DISABLE_INTRS) { 1917 } else if (flag == DISABLE_INTRS) {
1782 /* 1918 /*
1783 * Disable PIC Intrs in the general 1919 * Disable PIC Intrs in the general
1784 * intr mask register 1920 * intr mask register
1785 */ 1921 */
1786 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); 1922 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1787 temp64 = readq(&bar0->general_int_mask);
1788 val64 |= temp64;
1789 writeq(val64, &bar0->general_int_mask);
1790 }
1791 }
1792
1793 /* MAC Interrupts */
1794 /* Enabling/Disabling MAC interrupts */
1795 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1796 val64 = TXMAC_INT_M | RXMAC_INT_M;
1797 if (flag == ENABLE_INTRS) {
1798 temp64 = readq(&bar0->general_int_mask);
1799 temp64 &= ~((u64) val64);
1800 writeq(temp64, &bar0->general_int_mask);
1801 /*
1802 * All MAC block error interrupts are disabled for now
1803 * TODO
1804 */
1805 } else if (flag == DISABLE_INTRS) {
1806 /*
1807 * Disable MAC Intrs in the general intr mask register
1808 */
1809 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1810 writeq(DISABLE_ALL_INTRS,
1811 &bar0->mac_rmac_err_mask);
1812
1813 temp64 = readq(&bar0->general_int_mask);
1814 val64 |= temp64;
1815 writeq(val64, &bar0->general_int_mask);
1816 } 1923 }
1817 } 1924 }
1818 1925
1819 /* Tx traffic interrupts */ 1926 /* Tx traffic interrupts */
1820 if (mask & TX_TRAFFIC_INTR) { 1927 if (mask & TX_TRAFFIC_INTR) {
1821 val64 = TXTRAFFIC_INT_M; 1928 intr_mask |= TXTRAFFIC_INT_M;
1822 if (flag == ENABLE_INTRS) { 1929 if (flag == ENABLE_INTRS) {
1823 temp64 = readq(&bar0->general_int_mask);
1824 temp64 &= ~((u64) val64);
1825 writeq(temp64, &bar0->general_int_mask);
1826 /* 1930 /*
1827 * Enable all the Tx side interrupts 1931 * Enable all the Tx side interrupts
1828 * writing 0 Enables all 64 TX interrupt levels 1932 * writing 0 Enables all 64 TX interrupt levels
@@ -1834,19 +1938,13 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1834 * register. 1938 * register.
1835 */ 1939 */
1836 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); 1940 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1837 temp64 = readq(&bar0->general_int_mask);
1838 val64 |= temp64;
1839 writeq(val64, &bar0->general_int_mask);
1840 } 1941 }
1841 } 1942 }
1842 1943
1843 /* Rx traffic interrupts */ 1944 /* Rx traffic interrupts */
1844 if (mask & RX_TRAFFIC_INTR) { 1945 if (mask & RX_TRAFFIC_INTR) {
1845 val64 = RXTRAFFIC_INT_M; 1946 intr_mask |= RXTRAFFIC_INT_M;
1846 if (flag == ENABLE_INTRS) { 1947 if (flag == ENABLE_INTRS) {
1847 temp64 = readq(&bar0->general_int_mask);
1848 temp64 &= ~((u64) val64);
1849 writeq(temp64, &bar0->general_int_mask);
1850 /* writing 0 Enables all 8 RX interrupt levels */ 1948 /* writing 0 Enables all 8 RX interrupt levels */
1851 writeq(0x0, &bar0->rx_traffic_mask); 1949 writeq(0x0, &bar0->rx_traffic_mask);
1852 } else if (flag == DISABLE_INTRS) { 1950 } else if (flag == DISABLE_INTRS) {
@@ -1855,11 +1953,17 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1855 * register. 1953 * register.
1856 */ 1954 */
1857 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); 1955 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1858 temp64 = readq(&bar0->general_int_mask);
1859 val64 |= temp64;
1860 writeq(val64, &bar0->general_int_mask);
1861 } 1956 }
1862 } 1957 }
1958
1959 temp64 = readq(&bar0->general_int_mask);
1960 if (flag == ENABLE_INTRS)
1961 temp64 &= ~((u64) intr_mask);
1962 else
1963 temp64 = DISABLE_ALL_INTRS;
1964 writeq(temp64, &bar0->general_int_mask);
1965
1966 nic->general_int_mask = readq(&bar0->general_int_mask);
1863} 1967}
1864 1968
1865/** 1969/**
@@ -2063,14 +2167,6 @@ static int start_nic(struct s2io_nic *nic)
2063 writeq(val64, &bar0->adapter_control); 2167 writeq(val64, &bar0->adapter_control);
2064 2168
2065 /* 2169 /*
2066 * Clearing any possible Link state change interrupts that
2067 * could have popped up just before Enabling the card.
2068 */
2069 val64 = readq(&bar0->mac_rmac_err_reg);
2070 if (val64)
2071 writeq(val64, &bar0->mac_rmac_err_reg);
2072
2073 /*
2074 * Verify if the device is ready to be enabled, if so enable 2170 * Verify if the device is ready to be enabled, if so enable
2075 * it. 2171 * it.
2076 */ 2172 */
@@ -2223,9 +2319,9 @@ static void stop_nic(struct s2io_nic *nic)
2223 config = &nic->config; 2319 config = &nic->config;
2224 2320
2225 /* Disable all interrupts */ 2321 /* Disable all interrupts */
2322 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2226 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR; 2323 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2227 interruptible |= TX_PIC_INTR | RX_PIC_INTR; 2324 interruptible |= TX_PIC_INTR;
2228 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2229 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS); 2325 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2230 2326
2231 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */ 2327 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
@@ -6666,12 +6762,12 @@ static int s2io_card_up(struct s2io_nic * sp)
6666 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev); 6762 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6667 6763
6668 /* Enable select interrupts */ 6764 /* Enable select interrupts */
6765 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
6669 if (sp->intr_type != INTA) 6766 if (sp->intr_type != INTA)
6670 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS); 6767 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6671 else { 6768 else {
6672 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR; 6769 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6673 interruptible |= TX_PIC_INTR | RX_PIC_INTR; 6770 interruptible |= TX_PIC_INTR;
6674 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6675 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS); 6771 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6676 } 6772 }
6677 6773
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index 724948d217b6..b9654dfeb877 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -893,6 +893,7 @@ struct s2io_nic {
893 893
894 spinlock_t rx_lock; 894 spinlock_t rx_lock;
895 atomic_t isr_cnt; 895 atomic_t isr_cnt;
896 u64 general_int_mask;
896 u64 *ufo_in_band_v; 897 u64 *ufo_in_band_v;
897#define VPD_STRING_LEN 80 898#define VPD_STRING_LEN 80
898 u8 product_name[VPD_STRING_LEN]; 899 u8 product_name[VPD_STRING_LEN];
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 11:12:48 -0500