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-rw-r--r--arch/mips/Kconfig6
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c83
-rw-r--r--arch/mips/kernel/Makefile1
-rw-r--r--arch/mips/kernel/cevt-txx9.c171
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c17
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c19
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h9
-rw-r--r--include/asm-mips/jmr3927/tx3927.h4
-rw-r--r--include/asm-mips/jmr3927/txx927.h37
-rw-r--r--include/asm-mips/tx4927/tx4927_pci.h3
-rw-r--r--include/asm-mips/tx4938/tx4938.h1
-rw-r--r--include/asm-mips/txx9tmr.h67
12 files changed, 273 insertions, 145 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 61262c5f9c62..97da953eb5d0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -583,6 +583,7 @@ config SNI_RM
583 583
584config TOSHIBA_JMR3927 584config TOSHIBA_JMR3927
585 bool "Toshiba JMR-TX3927 board" 585 bool "Toshiba JMR-TX3927 board"
586 select CEVT_TXX9
586 select DMA_NONCOHERENT 587 select DMA_NONCOHERENT
587 select HW_HAS_PCI 588 select HW_HAS_PCI
588 select MIPS_TX3927 589 select MIPS_TX3927
@@ -597,6 +598,7 @@ config TOSHIBA_JMR3927
597config TOSHIBA_RBTX4927 598config TOSHIBA_RBTX4927
598 bool "Toshiba RBTX49[23]7 board" 599 bool "Toshiba RBTX49[23]7 board"
599 select CEVT_R4K 600 select CEVT_R4K
601 select CEVT_TXX9
600 select DMA_NONCOHERENT 602 select DMA_NONCOHERENT
601 select HAS_TXX9_SERIAL 603 select HAS_TXX9_SERIAL
602 select HW_HAS_PCI 604 select HW_HAS_PCI
@@ -618,6 +620,7 @@ config TOSHIBA_RBTX4927
618config TOSHIBA_RBTX4938 620config TOSHIBA_RBTX4938
619 bool "Toshiba RBTX4938 board" 621 bool "Toshiba RBTX4938 board"
620 select CEVT_R4K 622 select CEVT_R4K
623 select CEVT_TXX9
621 select DMA_NONCOHERENT 624 select DMA_NONCOHERENT
622 select HAS_TXX9_SERIAL 625 select HAS_TXX9_SERIAL
623 select HW_HAS_PCI 626 select HW_HAS_PCI
@@ -736,6 +739,9 @@ config CEVT_GT641XX
736config CEVT_R4K 739config CEVT_R4K
737 bool 740 bool
738 741
742config CEVT_TXX9
743 bool
744
739config CFE 745config CFE
740 bool 746 bool
741 747
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index edb9e59248ec..06e01c8f4e3a 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -27,17 +27,13 @@
27 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) 27 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
28 */ 28 */
29 29
30#include <linux/clockchips.h>
31#include <linux/init.h> 30#include <linux/init.h>
32#include <linux/kernel.h> 31#include <linux/kernel.h>
33#include <linux/kdev_t.h> 32#include <linux/kdev_t.h>
34#include <linux/types.h> 33#include <linux/types.h>
35#include <linux/sched.h>
36#include <linux/pci.h> 34#include <linux/pci.h>
37#include <linux/ide.h> 35#include <linux/ide.h>
38#include <linux/irq.h>
39#include <linux/ioport.h> 36#include <linux/ioport.h>
40#include <linux/param.h> /* for HZ */
41#include <linux/delay.h> 37#include <linux/delay.h>
42#include <linux/pm.h> 38#include <linux/pm.h>
43#include <linux/platform_device.h> 39#include <linux/platform_device.h>
@@ -48,17 +44,13 @@
48#endif 44#endif
49 45
50#include <asm/addrspace.h> 46#include <asm/addrspace.h>
51#include <asm/time.h> 47#include <asm/txx9tmr.h>
52#include <asm/reboot.h> 48#include <asm/reboot.h>
53#include <asm/jmr3927/jmr3927.h> 49#include <asm/jmr3927/jmr3927.h>
54#include <asm/mipsregs.h> 50#include <asm/mipsregs.h>
55 51
56extern void puts(const char *cp); 52extern void puts(const char *cp);
57 53
58/* Tick Timer divider */
59#define JMR3927_TIMER_CCD 0 /* 1/2 */
60#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
61
62/* don't enable - see errata */ 54/* don't enable - see errata */
63static int jmr3927_ccfg_toeon; 55static int jmr3927_ccfg_toeon;
64 56
@@ -93,66 +85,12 @@ static void jmr3927_machine_power_off(void)
93 while (1); 85 while (1);
94} 86}
95 87
96static cycle_t jmr3927_hpt_read(void)
97{
98 /* We assume this function is called xtime_lock held. */
99 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
100}
101
102static void jmr3927_set_mode(enum clock_event_mode mode,
103 struct clock_event_device *evt)
104{
105 /* Nothing to do here */
106}
107
108struct clock_event_device jmr3927_clock_event_device = {
109 .name = "MIPS",
110 .features = CLOCK_EVT_FEAT_PERIODIC,
111 .shift = 32,
112 .rating = 300,
113 .cpumask = CPU_MASK_CPU0,
114 .irq = JMR3927_IRQ_TICK,
115 .set_mode = jmr3927_set_mode,
116};
117
118static irqreturn_t jmr3927_timer_interrupt(int irq, void *dev_id)
119{
120 struct clock_event_device *cd = &jmr3927_clock_event_device;
121
122 jmr3927_tmrptr->tisr = 0; /* ack interrupt */
123
124 cd->event_handler(cd);
125
126 return IRQ_HANDLED;
127}
128
129static struct irqaction jmr3927_timer_irqaction = {
130 .handler = jmr3927_timer_interrupt,
131 .flags = IRQF_DISABLED | IRQF_PERCPU,
132 .name = "jmr3927-timer",
133};
134
135void __init plat_time_init(void) 88void __init plat_time_init(void)
136{ 89{
137 struct clock_event_device *cd; 90 txx9_clockevent_init(TX3927_TMR_REG(0),
138 91 TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0),
139 clocksource_mips.read = jmr3927_hpt_read; 92 JMR3927_IMCLK);
140 mips_hpt_frequency = JMR3927_TIMER_CLK; 93 txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
141
142 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
143 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
144 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
145 jmr3927_tmrptr->tcr =
146 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
147
148 cd = &jmr3927_clock_event_device;
149 /* Calculate the min / max delta */
150 cd->mult = div_sc((unsigned long) JMR3927_IMCLK, NSEC_PER_SEC, 32);
151 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
152 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
153 clockevents_register_device(cd);
154
155 setup_irq(JMR3927_IRQ_TICK, &jmr3927_timer_irqaction);
156} 94}
157 95
158#define DO_WRITE_THROUGH 96#define DO_WRITE_THROUGH
@@ -317,15 +255,8 @@ static void __init tx3927_setup(void)
317 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); 255 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
318 256
319 /* TMR */ 257 /* TMR */
320 /* disable all timers */ 258 for (i = 0; i < TX3927_NR_TMR; i++)
321 for (i = 0; i < TX3927_NR_TMR; i++) { 259 txx9_tmr_init(TX3927_TMR_REG(i));
322 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
323 tx3927_tmrptr(i)->tisr = 0;
324 tx3927_tmrptr(i)->cpra = 0xffffffff;
325 tx3927_tmrptr(i)->itmr = 0;
326 tx3927_tmrptr(i)->ccdr = 0;
327 tx3927_tmrptr(i)->pgmr = 0;
328 }
329 260
330 /* DMA */ 261 /* DMA */
331 tx3927_dmaptr->mcr = 0; 262 tx3927_dmaptr->mcr = 0;
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index d7745c8976f6..3196509a28d5 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -10,6 +10,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
10 10
11obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o 11obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
12obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o 12obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
13obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
13 14
14binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ 15binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
15 irix5sys.o sysirix.o 16 irix5sys.o sysirix.o
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
new file mode 100644
index 000000000000..795cb8fb0d74
--- /dev/null
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -0,0 +1,171 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Based on linux/arch/mips/kernel/cevt-r4k.c,
7 * linux/arch/mips/jmr3927/rbhma3100/setup.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 * Copyright (C) 2000-2001 Toshiba Corporation
11 * Copyright (C) 2007 MIPS Technologies, Inc.
12 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
13 */
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <asm/time.h>
17#include <asm/txx9tmr.h>
18
19#define TCR_BASE (TXx9_TMTCR_CCDE | TXx9_TMTCR_CRE | TXx9_TMTCR_TMODE_ITVL)
20#define TIMER_CCD 0 /* 1/2 */
21#define TIMER_CLK(imclk) ((imclk) / (2 << TIMER_CCD))
22
23static struct txx9_tmr_reg __iomem *txx9_cs_tmrptr;
24
25static cycle_t txx9_cs_read(void)
26{
27 return __raw_readl(&txx9_cs_tmrptr->trr);
28}
29
30/* Use 1 bit smaller width to use full bits in that width */
31#define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1)
32
33static struct clocksource txx9_clocksource = {
34 .name = "TXx9",
35 .rating = 200,
36 .read = txx9_cs_read,
37 .mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
38 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
39};
40
41void __init txx9_clocksource_init(unsigned long baseaddr,
42 unsigned int imbusclk)
43{
44 struct txx9_tmr_reg __iomem *tmrptr;
45
46 clocksource_set_clock(&txx9_clocksource, TIMER_CLK(imbusclk));
47 clocksource_register(&txx9_clocksource);
48
49 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
50 __raw_writel(TCR_BASE, &tmrptr->tcr);
51 __raw_writel(0, &tmrptr->tisr);
52 __raw_writel(TIMER_CCD, &tmrptr->ccdr);
53 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
54 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
55 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
56 txx9_cs_tmrptr = tmrptr;
57}
58
59static struct txx9_tmr_reg __iomem *txx9_tmrptr;
60
61static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
62{
63 /* stop and reset counter */
64 __raw_writel(TCR_BASE, &tmrptr->tcr);
65 /* clear pending interrupt */
66 __raw_writel(0, &tmrptr->tisr);
67}
68
69static void txx9tmr_set_mode(enum clock_event_mode mode,
70 struct clock_event_device *evt)
71{
72 struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
73
74 txx9tmr_stop_and_clear(tmrptr);
75 switch (mode) {
76 case CLOCK_EVT_MODE_PERIODIC:
77 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE,
78 &tmrptr->itmr);
79 /* start timer */
80 __raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >>
81 evt->shift,
82 &tmrptr->cpra);
83 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
84 break;
85 case CLOCK_EVT_MODE_SHUTDOWN:
86 case CLOCK_EVT_MODE_UNUSED:
87 __raw_writel(0, &tmrptr->itmr);
88 break;
89 case CLOCK_EVT_MODE_ONESHOT:
90 __raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);
91 break;
92 case CLOCK_EVT_MODE_RESUME:
93 __raw_writel(TIMER_CCD, &tmrptr->ccdr);
94 __raw_writel(0, &tmrptr->itmr);
95 break;
96 }
97}
98
99static int txx9tmr_set_next_event(unsigned long delta,
100 struct clock_event_device *evt)
101{
102 struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
103
104 txx9tmr_stop_and_clear(tmrptr);
105 /* start timer */
106 __raw_writel(delta, &tmrptr->cpra);
107 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
108 return 0;
109}
110
111static struct clock_event_device txx9tmr_clock_event_device = {
112 .name = "TXx9",
113 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
114 .rating = 200,
115 .cpumask = CPU_MASK_CPU0,
116 .set_mode = txx9tmr_set_mode,
117 .set_next_event = txx9tmr_set_next_event,
118};
119
120static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
121{
122 struct clock_event_device *cd = &txx9tmr_clock_event_device;
123 struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
124
125 __raw_writel(0, &tmrptr->tisr); /* ack interrupt */
126 cd->event_handler(cd);
127 return IRQ_HANDLED;
128}
129
130static struct irqaction txx9tmr_irq = {
131 .handler = txx9tmr_interrupt,
132 .flags = IRQF_DISABLED | IRQF_PERCPU,
133 .name = "txx9tmr",
134};
135
136void __init txx9_clockevent_init(unsigned long baseaddr, int irq,
137 unsigned int imbusclk)
138{
139 struct clock_event_device *cd = &txx9tmr_clock_event_device;
140 struct txx9_tmr_reg __iomem *tmrptr;
141
142 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
143 txx9tmr_stop_and_clear(tmrptr);
144 __raw_writel(TIMER_CCD, &tmrptr->ccdr);
145 __raw_writel(0, &tmrptr->itmr);
146 txx9_tmrptr = tmrptr;
147
148 clockevent_set_clock(cd, TIMER_CLK(imbusclk));
149 cd->max_delta_ns =
150 clockevent_delta2ns(0xffffffff >> (32 - TXX9_TIMER_BITS), cd);
151 cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
152 cd->irq = irq;
153 clockevents_register_device(cd);
154 setup_irq(irq, &txx9tmr_irq);
155 printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n",
156 baseaddr, irq);
157}
158
159void __init txx9_tmr_init(unsigned long baseaddr)
160{
161 struct txx9_tmr_reg __iomem *tmrptr;
162
163 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
164 __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
165 __raw_writel(0, &tmrptr->tisr);
166 __raw_writel(0xffffffff, &tmrptr->cpra);
167 __raw_writel(0, &tmrptr->itmr);
168 __raw_writel(0, &tmrptr->ccdr);
169 __raw_writel(0, &tmrptr->pgmr);
170 iounmap(tmrptr);
171}
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index c7470fba6180..0299595ce1c4 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -63,6 +63,7 @@
63#include <asm/processor.h> 63#include <asm/processor.h>
64#include <asm/reboot.h> 64#include <asm/reboot.h>
65#include <asm/time.h> 65#include <asm/time.h>
66#include <asm/txx9tmr.h>
66#include <linux/bootmem.h> 67#include <linux/bootmem.h>
67#include <linux/blkdev.h> 68#include <linux/blkdev.h>
68#ifdef CONFIG_TOSHIBA_FPCIB0 69#ifdef CONFIG_TOSHIBA_FPCIB0
@@ -93,7 +94,6 @@
93 94
94#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 ) 95#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
95#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 ) 96#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
96#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
97#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 ) 97#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
98#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 ) 98#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
99#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 ) 99#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
@@ -130,7 +130,6 @@ extern void toshiba_rbtx4927_power_off(void);
130 130
131int tx4927_using_backplane = 0; 131int tx4927_using_backplane = 0;
132 132
133extern void gt64120_time_init(void);
134extern void toshiba_rbtx4927_irq_setup(void); 133extern void toshiba_rbtx4927_irq_setup(void);
135 134
136char *prom_getcmdline(void); 135char *prom_getcmdline(void);
@@ -721,6 +720,7 @@ void toshiba_rbtx4927_power_off(void)
721 720
722void __init toshiba_rbtx4927_setup(void) 721void __init toshiba_rbtx4927_setup(void)
723{ 722{
723 int i;
724 u32 cp0_config; 724 u32 cp0_config;
725 char *argptr; 725 char *argptr;
726 726
@@ -764,6 +764,9 @@ void __init toshiba_rbtx4927_setup(void)
764 _machine_halt = toshiba_rbtx4927_halt; 764 _machine_halt = toshiba_rbtx4927_halt;
765 pm_power_off = toshiba_rbtx4927_power_off; 765 pm_power_off = toshiba_rbtx4927_power_off;
766 766
767 for (i = 0; i < TX4927_NR_TMR; i++)
768 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
769
767#ifdef CONFIG_PCI 770#ifdef CONFIG_PCI
768 771
769 /* PCIC */ 772 /* PCIC */
@@ -892,7 +895,6 @@ void __init toshiba_rbtx4927_setup(void)
892#ifdef CONFIG_SERIAL_TXX9 895#ifdef CONFIG_SERIAL_TXX9
893 { 896 {
894 extern int early_serial_txx9_setup(struct uart_port *port); 897 extern int early_serial_txx9_setup(struct uart_port *port);
895 int i;
896 struct uart_port req; 898 struct uart_port req;
897 for(i = 0; i < 2; i++) { 899 for(i = 0; i < 2; i++) {
898 memset(&req, 0, sizeof(req)); 900 memset(&req, 0, sizeof(req));
@@ -937,12 +939,11 @@ void __init toshiba_rbtx4927_setup(void)
937void __init 939void __init
938toshiba_rbtx4927_time_init(void) 940toshiba_rbtx4927_time_init(void)
939{ 941{
940 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
941
942 mips_hpt_frequency = tx4927_cpu_clock / 2; 942 mips_hpt_frequency = tx4927_cpu_clock / 2;
943 943 if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
944 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n"); 944 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
945 945 TXX9_IRQ_BASE + 17,
946 50000000);
946} 947}
947 948
948static int __init toshiba_rbtx4927_rtc_init(void) 949static int __init toshiba_rbtx4927_rtc_init(void)
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
index ceecaf498957..4a8152375efe 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -26,6 +26,7 @@
26#include <asm/reboot.h> 26#include <asm/reboot.h>
27#include <asm/irq.h> 27#include <asm/irq.h>
28#include <asm/time.h> 28#include <asm/time.h>
29#include <asm/txx9tmr.h>
29#include <asm/uaccess.h> 30#include <asm/uaccess.h>
30#include <asm/io.h> 31#include <asm/io.h>
31#include <asm/bootinfo.h> 32#include <asm/bootinfo.h>
@@ -773,15 +774,8 @@ void __init tx4938_board_setup(void)
773 } 774 }
774 775
775 /* TMR */ 776 /* TMR */
776 /* disable all timers */ 777 for (i = 0; i < TX4938_NR_TMR; i++)
777 for (i = 0; i < TX4938_NR_TMR; i++) { 778 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
778 tx4938_tmrptr(i)->tcr = 0x00000020;
779 tx4938_tmrptr(i)->tisr = 0;
780 tx4938_tmrptr(i)->cpra = 0xffffffff;
781 tx4938_tmrptr(i)->itmr = 0;
782 tx4938_tmrptr(i)->ccdr = 0;
783 tx4938_tmrptr(i)->pgmr = 0;
784 }
785 779
786 /* enable DMA */ 780 /* enable DMA */
787 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN); 781 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
@@ -852,12 +846,13 @@ void tx4938_report_pcic_status(void)
852 846
853#endif /* CONFIG_PCI */ 847#endif /* CONFIG_PCI */
854 848
855/* We use onchip r4k counter or TMR timer as our system wide timer
856 * interrupt running at 100HZ. */
857
858void __init plat_time_init(void) 849void __init plat_time_init(void)
859{ 850{
860 mips_hpt_frequency = txx9_cpu_clock / 2; 851 mips_hpt_frequency = txx9_cpu_clock / 2;
852 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS)
853 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
854 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
855 txx9_gbus_clock / 2);
861} 856}
862 857
863void __init toshiba_rbtx4938_setup(void) 858void __init toshiba_rbtx4938_setup(void)
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index b2dc35f56181..81602c8047eb 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -132,9 +132,7 @@
132#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) 132#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
133#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) 133#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
134#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) 134#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
135#define JMR3927_IRQ_IRC_TMR0 (JMR3927_IRQ_IRC + TX3927_IR_TMR0) 135#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
136#define JMR3927_IRQ_IRC_TMR1 (JMR3927_IRQ_IRC + TX3927_IR_TMR1)
137#define JMR3927_IRQ_IRC_TMR2 (JMR3927_IRQ_IRC + TX3927_IR_TMR2)
138#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) 136#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
139#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) 137#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
140#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) 138#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
@@ -148,17 +146,12 @@
148#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 146#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
149/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ 147/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
150#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 148#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
151/* Clock Tick (10ms) */
152#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
153 149
154/* Clocks */ 150/* Clocks */
155#define JMR3927_CORECLK 132710400 /* 132.7MHz */ 151#define JMR3927_CORECLK 132710400 /* 132.7MHz */
156#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ 152#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
157#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ 153#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
158 154
159#define jmr3927_tmrptr tx3927_tmrptr(0) /* TMR0 */
160
161
162/* 155/*
163 * TX3927 Pin Configuration: 156 * TX3927 Pin Configuration:
164 * 157 *
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 211bcf47fffb..338f99882a39 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -222,9 +222,7 @@ struct tx3927_ccfg_reg {
222#define TX3927_IR_DMA 8 222#define TX3927_IR_DMA 8
223#define TX3927_IR_PIO 9 223#define TX3927_IR_PIO 9
224#define TX3927_IR_PCI 10 224#define TX3927_IR_PCI 10
225#define TX3927_IR_TMR0 13 225#define TX3927_IR_TMR(ch) (13 + (ch))
226#define TX3927_IR_TMR1 14
227#define TX3927_IR_TMR2 15
228#define TX3927_NUM_IR 16 226#define TX3927_NUM_IR 16
229 227
230/* 228/*
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h
index 58a8ff6be815..0474fe8dac3f 100644
--- a/include/asm-mips/jmr3927/txx927.h
+++ b/include/asm-mips/jmr3927/txx927.h
@@ -10,22 +10,6 @@
10#ifndef __ASM_TXX927_H 10#ifndef __ASM_TXX927_H
11#define __ASM_TXX927_H 11#define __ASM_TXX927_H
12 12
13struct txx927_tmr_reg {
14 volatile unsigned long tcr;
15 volatile unsigned long tisr;
16 volatile unsigned long cpra;
17 volatile unsigned long cprb;
18 volatile unsigned long itmr;
19 volatile unsigned long unused0[3];
20 volatile unsigned long ccdr;
21 volatile unsigned long unused1[3];
22 volatile unsigned long pgmr;
23 volatile unsigned long unused2[3];
24 volatile unsigned long wtmr;
25 volatile unsigned long unused3[43];
26 volatile unsigned long trr;
27};
28
29struct txx927_sio_reg { 13struct txx927_sio_reg {
30 volatile unsigned long lcr; 14 volatile unsigned long lcr;
31 volatile unsigned long dicr; 15 volatile unsigned long dicr;
@@ -51,27 +35,6 @@ struct txx927_pio_reg {
51}; 35};
52 36
53/* 37/*
54 * TMR
55 */
56/* TMTCR : Timer Control */
57#define TXx927_TMTCR_TCE 0x00000080
58#define TXx927_TMTCR_CCDE 0x00000040
59#define TXx927_TMTCR_CRE 0x00000020
60#define TXx927_TMTCR_ECES 0x00000008
61#define TXx927_TMTCR_CCS 0x00000004
62#define TXx927_TMTCR_TMODE_MASK 0x00000003
63#define TXx927_TMTCR_TMODE_ITVL 0x00000000
64
65/* TMTISR : Timer Int. Status */
66#define TXx927_TMTISR_TPIBS 0x00000004
67#define TXx927_TMTISR_TPIAS 0x00000002
68#define TXx927_TMTISR_TIIS 0x00000001
69
70/* TMTITMR : Interval Timer Mode */
71#define TXx927_TMTITMR_TIIE 0x00008000
72#define TXx927_TMTITMR_TZCE 0x00000001
73
74/*
75 * SIO 38 * SIO
76 */ 39 */
77/* SILCR : Line Control */ 40/* SILCR : Line Control */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index f98b2bb719d5..3f1e470192e3 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -9,6 +9,7 @@
9#define __ASM_TX4927_TX4927_PCI_H 9#define __ASM_TX4927_TX4927_PCI_H
10 10
11#define TX4927_CCFG_TOE 0x00004000 11#define TX4927_CCFG_TOE 0x00004000
12#define TX4927_CCFG_TINTDIS 0x01000000
12 13
13#define TX4927_PCIMEM 0x08000000 14#define TX4927_PCIMEM 0x08000000
14#define TX4927_PCIMEM_SIZE 0x08000000 15#define TX4927_PCIMEM_SIZE 0x08000000
@@ -20,6 +21,8 @@
20#define TX4927_PCIC_REG 0xff1fd000 21#define TX4927_PCIC_REG 0xff1fd000
21#define TX4927_CCFG_REG 0xff1fe000 22#define TX4927_CCFG_REG 0xff1fe000
22#define TX4927_IRC_REG 0xff1ff600 23#define TX4927_IRC_REG 0xff1ff600
24#define TX4927_NR_TMR 3
25#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
23#define TX4927_CE3 0x17f00000 /* 1M */ 26#define TX4927_CE3 0x17f00000 /* 1M */
24#define TX4927_PCIRESET_ADDR 0xbc00f006 27#define TX4927_PCIRESET_ADDR 0xbc00f006
25#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020) 28#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index 650b010761f9..f7c448b90578 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -641,7 +641,6 @@ struct tx4938_ccfg_reg {
641#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) 641#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
642#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) 642#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
643#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) 643#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
644#define tx4938_tmrptr(ch) ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch))
645#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) 644#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
646#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG) 645#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG)
647#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) 646#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
diff --git a/include/asm-mips/txx9tmr.h b/include/asm-mips/txx9tmr.h
new file mode 100644
index 000000000000..67f70a8f09bd
--- /dev/null
+++ b/include/asm-mips/txx9tmr.h
@@ -0,0 +1,67 @@
1/*
2 * include/asm-mips/txx9tmr.h
3 * TX39/TX49 timer controller definitions.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#ifndef __ASM_TXX9TMR_H
10#define __ASM_TXX9TMR_H
11
12#include <linux/types.h>
13
14struct txx9_tmr_reg {
15 u32 tcr;
16 u32 tisr;
17 u32 cpra;
18 u32 cprb;
19 u32 itmr;
20 u32 unused0[3];
21 u32 ccdr;
22 u32 unused1[3];
23 u32 pgmr;
24 u32 unused2[3];
25 u32 wtmr;
26 u32 unused3[43];
27 u32 trr;
28};
29
30/* TMTCR : Timer Control */
31#define TXx9_TMTCR_TCE 0x00000080
32#define TXx9_TMTCR_CCDE 0x00000040
33#define TXx9_TMTCR_CRE 0x00000020
34#define TXx9_TMTCR_ECES 0x00000008
35#define TXx9_TMTCR_CCS 0x00000004
36#define TXx9_TMTCR_TMODE_MASK 0x00000003
37#define TXx9_TMTCR_TMODE_ITVL 0x00000000
38#define TXx9_TMTCR_TMODE_PGEN 0x00000001
39#define TXx9_TMTCR_TMODE_WDOG 0x00000002
40
41/* TMTISR : Timer Int. Status */
42#define TXx9_TMTISR_TPIBS 0x00000004
43#define TXx9_TMTISR_TPIAS 0x00000002
44#define TXx9_TMTISR_TIIS 0x00000001
45
46/* TMITMR : Interval Timer Mode */
47#define TXx9_TMITMR_TIIE 0x00008000
48#define TXx9_TMITMR_TZCE 0x00000001
49
50/* TMWTMR : Watchdog Timer Mode */
51#define TXx9_TMWTMR_TWIE 0x00008000
52#define TXx9_TMWTMR_WDIS 0x00000080
53#define TXx9_TMWTMR_TWC 0x00000001
54
55void txx9_clocksource_init(unsigned long baseaddr,
56 unsigned int imbusclk);
57void txx9_clockevent_init(unsigned long baseaddr, int irq,
58 unsigned int imbusclk);
59void txx9_tmr_init(unsigned long baseaddr);
60
61#ifdef CONFIG_CPU_TX39XX
62#define TXX9_TIMER_BITS 24
63#else
64#define TXX9_TIMER_BITS 32
65#endif
66
67#endif /* __ASM_TXX9TMR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 01:46:27 -0500