2 files changed, 149 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index eaefb5b066db..417d9c24fcdb 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -931,3 +931,95 @@ static void cayman_gpu_init(struct radeon_device *rdev)
        udelay(50);
 }
+/*
+ * GART
+ */
+void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
+{
+        /* flush hdp cache */
+        WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+        /* bits 0-7 are the VM contexts0-7 */
+        WREG32(VM_INVALIDATE_REQUEST, 1);
+}
+int cayman_pcie_gart_enable(struct radeon_device *rdev)
+{
+        int r;
+        if (rdev->gart.table.vram.robj == NULL) {
+                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
+                return -EINVAL;
+        }
+        r = radeon_gart_table_vram_pin(rdev);
+        if (r)
+                return r;
+        radeon_gart_restore(rdev);
+        /* Setup TLB control */
+        WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB |
+               ENABLE_L1_FRAGMENT_PROCESSING |
+               SYSTEM_ACCESS_MODE_NOT_IN_SYS |
+               SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
+        /* Setup L2 cache */
+        WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
+               ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
+               ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
+               EFFECTIVE_L2_QUEUE_SIZE(7) |
+               CONTEXT1_IDENTITY_ACCESS_MODE(1));
+        WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
+        WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
+               L2_CACHE_BIGK_FRAGMENT_SIZE(6));
+        /* setup context0 */
+        WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
+        WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
+        WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
+        WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+                        (u32)(rdev->dummy_page.addr >> 12));
+        WREG32(VM_CONTEXT0_CNTL2, 0);
+        WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
+                                RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
+        /* disable context1-7 */
+        WREG32(VM_CONTEXT1_CNTL2, 0);
+        WREG32(VM_CONTEXT1_CNTL, 0);
+        cayman_pcie_gart_tlb_flush(rdev);
+        rdev->gart.ready = true;
+        return 0;
+}
+void cayman_pcie_gart_disable(struct radeon_device *rdev)
+{
+        int r;
+        /* Disable all tables */
+        WREG32(VM_CONTEXT0_CNTL, 0);
+        WREG32(VM_CONTEXT1_CNTL, 0);
+        /* Setup TLB control */
+        WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
+               SYSTEM_ACCESS_MODE_NOT_IN_SYS |
+               SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
+        /* Setup L2 cache */
+        WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
+               ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
+               EFFECTIVE_L2_QUEUE_SIZE(7) |
+               CONTEXT1_IDENTITY_ACCESS_MODE(1));
+        WREG32(VM_L2_CNTL2, 0);
+        WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
+               L2_CACHE_BIGK_FRAGMENT_SIZE(6));
+        if (rdev->gart.table.vram.robj) {
+                r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
+                if (likely(r == 0)) {
+                        radeon_bo_kunmap(rdev->gart.table.vram.robj);
+                        radeon_bo_unpin(rdev->gart.table.vram.robj);
+                        radeon_bo_unreserve(rdev->gart.table.vram.robj);
+                }
+        }
+}
+void cayman_pcie_gart_fini(struct radeon_device *rdev)
+{
+        cayman_pcie_gart_disable(rdev);
+        radeon_gart_table_vram_free(rdev);
+        radeon_gart_fini(rdev);
+}
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index b4ba1b013ccb..9dc2b3429c3f 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -43,10 +43,66 @@
 #define DMIF_ADDR_CONFIG                                0xBD4
+#define VM_CONTEXT0_REQUEST_RESPONSE                    0x1470
+#define         REQUEST_TYPE(x)                                 (((x) & 0xf) << 0)
+#define         RESPONSE_TYPE_MASK                              0x000000F0
+#define         RESPONSE_TYPE_SHIFT                             4
+#define VM_L2_CNTL                                      0x1400
+#define         ENABLE_L2_CACHE                                 (1 << 0)
+#define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
+#define         ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE         (1 << 9)
+#define         ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE        (1 << 10)
+#define         EFFECTIVE_L2_QUEUE_SIZE(x)                      (((x) & 7) << 14)
+#define         CONTEXT1_IDENTITY_ACCESS_MODE(x)                (((x) & 3) << 18)
+/* CONTEXT1_IDENTITY_ACCESS_MODE
+ * 0 physical = logical
+ * 1 logical via context1 page table
+ * 2 inside identity aperture use translation, outside physical = logical
+ * 3 inside identity aperture physical = logical, outside use translation
+ */
+#define VM_L2_CNTL2                                     0x1404
+#define         INVALIDATE_ALL_L1_TLBS                          (1 << 0)
+#define         INVALIDATE_L2_CACHE                             (1 << 1)
+#define VM_L2_CNTL3                                     0x1408
+#define         BANK_SELECT(x)                                  ((x) << 0)
+#define         CACHE_UPDATE_MODE(x)                            ((x) << 6)
+#define         L2_CACHE_BIGK_ASSOCIATIVITY                     (1 << 20)
+#define         L2_CACHE_BIGK_FRAGMENT_SIZE(x)                  ((x) << 15)
+#define VM_L2_STATUS                                    0x140C
+#define         L2_BUSY                                         (1 << 0)
+#define VM_CONTEXT0_CNTL                                0x1410
+#define         ENABLE_CONTEXT                                  (1 << 0)
+#define         PAGE_TABLE_DEPTH(x)                             (((x) & 3) << 1)
+#define         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 4)
+#define VM_CONTEXT1_CNTL                                0x1414
+#define VM_CONTEXT0_CNTL2                               0x1430
+#define VM_CONTEXT1_CNTL2                               0x1434
+#define VM_INVALIDATE_REQUEST                           0x1478
+#define VM_INVALIDATE_RESPONSE                          0x147c
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR       0x1518
+#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR       0x151c
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                0x153C
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR               0x155C
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x157C
 #define MC_SHARED_CHMAP                                         0x2004
 #define         NOOFCHAN_SHIFT                                  12
 #define         NOOFCHAN_MASK                                   0x00003000
 #define MC_SHARED_CHREMAP                                       0x2008
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
+#define MC_VM_MX_L1_TLB_CNTL                            0x2064
+#define         ENABLE_L1_TLB                                   (1 << 0)
+#define         ENABLE_L1_FRAGMENT_PROCESSING                   (1 << 1)
+#define         SYSTEM_ACCESS_MODE_PA_ONLY                      (0 << 3)
+#define         SYSTEM_ACCESS_MODE_USE_SYS_MAP                  (1 << 3)
+#define         SYSTEM_ACCESS_MODE_IN_SYS                       (2 << 3)
+#define         SYSTEM_ACCESS_MODE_NOT_IN_SYS                   (3 << 3)
+#define         SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU       (0 << 5)
+#define         ENABLE_ADVANCED_DRIVER_MODEL                    (1 << 6)
 #define MC_SHARED_BLACKOUT_CNTL                         0x20ac
 #define MC_ARB_RAMCFG                                   0x2760
 #define         NOOFBANK_SHIFT                                  0
@@ -87,6 +143,7 @@
 #define CONFIG_MEMSIZE                                  0x5428
+#define HDP_MEM_COHERENCY_FLUSH_CNTL                    0x5480
 #define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
 #define GRBM_CNTL                                       0x8000

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index eaefb5b066db..417d9c24fcdb 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c
@@ -931,3 +931,95 @@ static void cayman_gpu_init(struct radeon_device *rdev)
931	udelay(50);	931	udelay(50);
932	}	932	}
933		933
		934	/*
		935	* GART
		936	*/
		937	void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
		938	{
		939	/* flush hdp cache */
		940	WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
		941
		942	/* bits 0-7 are the VM contexts0-7 */
		943	WREG32(VM_INVALIDATE_REQUEST, 1);
		944	}
		945
		946	int cayman_pcie_gart_enable(struct radeon_device *rdev)
		947	{
		948	int r;
		949
		950	if (rdev->gart.table.vram.robj == NULL) {
		951	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		952	return -EINVAL;
		953	}
		954	r = radeon_gart_table_vram_pin(rdev);
		955	if (r)
		956	return r;
		957	radeon_gart_restore(rdev);
		958	/* Setup TLB control */
		959	WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB \|
		960	ENABLE_L1_FRAGMENT_PROCESSING \|
		961	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|
		962	SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
		963	/* Setup L2 cache */
		964	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \|
		965	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|
		966	ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE \|
		967	EFFECTIVE_L2_QUEUE_SIZE(7) \|
		968	CONTEXT1_IDENTITY_ACCESS_MODE(1));
		969	WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS \| INVALIDATE_L2_CACHE);
		970	WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY \|
		971	L2_CACHE_BIGK_FRAGMENT_SIZE(6));
		972	/* setup context0 */
		973	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
		974	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
		975	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
		976	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
		977	(u32)(rdev->dummy_page.addr >> 12));
		978	WREG32(VM_CONTEXT0_CNTL2, 0);
		979	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \|
		980	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
		981	/* disable context1-7 */
		982	WREG32(VM_CONTEXT1_CNTL2, 0);
		983	WREG32(VM_CONTEXT1_CNTL, 0);
		984
		985	cayman_pcie_gart_tlb_flush(rdev);
		986	rdev->gart.ready = true;
		987	return 0;
		988	}
		989
		990	void cayman_pcie_gart_disable(struct radeon_device *rdev)
		991	{
		992	int r;
		993
		994	/* Disable all tables */
		995	WREG32(VM_CONTEXT0_CNTL, 0);
		996	WREG32(VM_CONTEXT1_CNTL, 0);
		997	/* Setup TLB control */
		998	WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING \|
		999	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|
		1000	SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
		1001	/* Setup L2 cache */
		1002	WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|
		1003	ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE \|
		1004	EFFECTIVE_L2_QUEUE_SIZE(7) \|
		1005	CONTEXT1_IDENTITY_ACCESS_MODE(1));
		1006	WREG32(VM_L2_CNTL2, 0);
		1007	WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY \|
		1008	L2_CACHE_BIGK_FRAGMENT_SIZE(6));
		1009	if (rdev->gart.table.vram.robj) {
		1010	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
		1011	if (likely(r == 0)) {
		1012	radeon_bo_kunmap(rdev->gart.table.vram.robj);
		1013	radeon_bo_unpin(rdev->gart.table.vram.robj);
		1014	radeon_bo_unreserve(rdev->gart.table.vram.robj);
		1015	}
		1016	}
		1017	}
		1018
		1019	void cayman_pcie_gart_fini(struct radeon_device *rdev)
		1020	{
		1021	cayman_pcie_gart_disable(rdev);
		1022	radeon_gart_table_vram_free(rdev);
		1023	radeon_gart_fini(rdev);
		1024	}
		1025


diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h index b4ba1b013ccb..9dc2b3429c3f 100644 --- a/drivers/gpu/drm/radeon/nid.h +++ b/drivers/gpu/drm/radeon/nid.h
@@ -43,10 +43,66 @@
43		43
44	#define DMIF_ADDR_CONFIG 0xBD4	44	#define DMIF_ADDR_CONFIG 0xBD4
45		45
		46	#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
		47	#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
		48	#define RESPONSE_TYPE_MASK 0x000000F0
		49	#define RESPONSE_TYPE_SHIFT 4
		50	#define VM_L2_CNTL 0x1400
		51	#define ENABLE_L2_CACHE (1 << 0)
		52	#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
		53	#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
		54	#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
		55	#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
		56	#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18)
		57	/* CONTEXT1_IDENTITY_ACCESS_MODE
		58	* 0 physical = logical
		59	* 1 logical via context1 page table
		60	* 2 inside identity aperture use translation, outside physical = logical
		61	* 3 inside identity aperture physical = logical, outside use translation
		62	*/
		63	#define VM_L2_CNTL2 0x1404
		64	#define INVALIDATE_ALL_L1_TLBS (1 << 0)
		65	#define INVALIDATE_L2_CACHE (1 << 1)
		66	#define VM_L2_CNTL3 0x1408
		67	#define BANK_SELECT(x) ((x) << 0)
		68	#define CACHE_UPDATE_MODE(x) ((x) << 6)
		69	#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
		70	#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
		71	#define VM_L2_STATUS 0x140C
		72	#define L2_BUSY (1 << 0)
		73	#define VM_CONTEXT0_CNTL 0x1410
		74	#define ENABLE_CONTEXT (1 << 0)
		75	#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
		76	#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
		77	#define VM_CONTEXT1_CNTL 0x1414
		78	#define VM_CONTEXT0_CNTL2 0x1430
		79	#define VM_CONTEXT1_CNTL2 0x1434
		80	#define VM_INVALIDATE_REQUEST 0x1478
		81	#define VM_INVALIDATE_RESPONSE 0x147c
		82	#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
		83	#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
		84	#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
		85	#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
		86	#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
		87
46	#define MC_SHARED_CHMAP 0x2004	88	#define MC_SHARED_CHMAP 0x2004
47	#define NOOFCHAN_SHIFT 12	89	#define NOOFCHAN_SHIFT 12
48	#define NOOFCHAN_MASK 0x00003000	90	#define NOOFCHAN_MASK 0x00003000
49	#define MC_SHARED_CHREMAP 0x2008	91	#define MC_SHARED_CHREMAP 0x2008
		92
		93	#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
		94	#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
		95	#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
		96	#define MC_VM_MX_L1_TLB_CNTL 0x2064
		97	#define ENABLE_L1_TLB (1 << 0)
		98	#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
		99	#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
		100	#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
		101	#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
		102	#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
		103	#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
		104	#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
		105
50	#define MC_SHARED_BLACKOUT_CNTL 0x20ac	106	#define MC_SHARED_BLACKOUT_CNTL 0x20ac
51	#define MC_ARB_RAMCFG 0x2760	107	#define MC_ARB_RAMCFG 0x2760
52	#define NOOFBANK_SHIFT 0	108	#define NOOFBANK_SHIFT 0
@@ -87,6 +143,7 @@
87		143
88	#define CONFIG_MEMSIZE 0x5428	144	#define CONFIG_MEMSIZE 0x5428
89		145
		146	#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
90	#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0	147	#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
91		148
92	#define GRBM_CNTL 0x8000	149	#define GRBM_CNTL 0x8000