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-rw-r--r--arch/sh/drivers/pci/Makefile4
-rw-r--r--arch/sh/drivers/pci/fixups-se7780.c62
-rw-r--r--arch/sh/drivers/pci/fixups-sh7785lcr.c47
3 files changed, 2 insertions, 111 deletions
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index 847e90894d1b..67d710a04de1 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -21,6 +21,6 @@ obj-$(CONFIG_SH_SDK7780) += ops-sdk7780.o fixups-sdk7780.o
21obj-$(CONFIG_SH_TITAN) += ops-titan.o 21obj-$(CONFIG_SH_TITAN) += ops-titan.o
22obj-$(CONFIG_SH_LANDISK) += ops-landisk.o 22obj-$(CONFIG_SH_LANDISK) += ops-landisk.o
23obj-$(CONFIG_SH_LBOX_RE2) += ops-lboxre2.o fixups-lboxre2.o 23obj-$(CONFIG_SH_LBOX_RE2) += ops-lboxre2.o fixups-lboxre2.o
24obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += ops-se7780.o fixups-se7780.o 24obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += ops-se7780.o fixups-sdk7780.o
25obj-$(CONFIG_SH_CAYMAN) += ops-cayman.o 25obj-$(CONFIG_SH_CAYMAN) += ops-cayman.o
26obj-$(CONFIG_SH_SH7785LCR) += ops-sh7785lcr.o fixups-sh7785lcr.o 26obj-$(CONFIG_SH_SH7785LCR) += ops-sh7785lcr.o fixups-r7780rp.o
diff --git a/arch/sh/drivers/pci/fixups-se7780.c b/arch/sh/drivers/pci/fixups-se7780.c
deleted file mode 100644
index a968af7d6f70..000000000000
--- a/arch/sh/drivers/pci/fixups-se7780.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * arch/sh/drivers/pci/fixups-se7780.c
3 *
4 * HITACHI UL Solution Engine 7780 PCI fixups
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 - 2006 Paul Mundt
8 * Copyright (C) 2006 Nobuhiro Iwamatsu
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/pci.h>
15#include "pci-sh4.h"
16#include <asm/io.h>
17
18int pci_fixup_pcic(struct pci_channel *chan)
19{
20 ctrl_outl(0x00000001, SH7780_PCI_VCR2);
21
22 /* Enable all interrupts, so we know what to fix */
23 pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
24 pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);
25
26 /* Set up standard PCI config registers */
27 ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));
28 ctrl_outw(0x0047, PCI_REG(SH7780_PCICMD));
29 ctrl_outb( 0x00, PCI_REG(SH7780_PCIPIF));
30 ctrl_outb( 0x00, PCI_REG(SH7780_PCISUB));
31 ctrl_outb( 0x06, PCI_REG(SH7780_PCIBCC));
32 ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));
33 ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));
34
35 pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
36 pci_write_reg(chan, 0x08000000, SH7780_PCILAR0); /* SHwy */
37 pci_write_reg(chan, 0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
38
39 pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
40 pci_write_reg(chan, 0x00000000, SH7780_PCILAR1);
41 pci_write_reg(chan, 0x00000000, SH7780_PCILSR1);
42
43 pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
44
45 /*
46 * Set the MBR so PCI address is one-to-one with window,
47 * meaning all calls go straight through... use ifdef to
48 * catch erroneous assumption.
49 */
50 pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0);
51 pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
52
53 /* Set IOBR for window containing area specified in pci.h */
54 pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
55 SH7780_PCIIOBR);
56 pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),
57 SH7780_PCIIOBMR);
58
59 pci_write_reg(chan, 0xA5000C01, SH7780_PCICR);
60
61 return 0;
62}
diff --git a/arch/sh/drivers/pci/fixups-sh7785lcr.c b/arch/sh/drivers/pci/fixups-sh7785lcr.c
deleted file mode 100644
index 9e7dc79037e7..000000000000
--- a/arch/sh/drivers/pci/fixups-sh7785lcr.c
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * arch/sh/drivers/pci/fixups-sh7785lcr.c
3 *
4 * R0P7785LC0011RL PCI fixups
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * Based on arch/sh/drivers/pci/fixups-r7780rp.c
8 * Copyright (C) 2003 Lineo uSolutions, Inc.
9 * Copyright (C) 2004 - 2006 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/pci.h>
16#include "pci-sh4.h"
17
18int pci_fixup_pcic(struct pci_channel *chan)
19{
20 pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
21 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
22
23 pci_write_reg(chan, 0xfbb00047, SH7780_PCICMD);
24 pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
25
26 pci_write_reg(chan, 0x00011912, SH7780_PCISVID);
27 pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
28 pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
29 pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
30 pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
31
32 pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
33 pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
34
35#ifdef CONFIG_32BIT
36 pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
37 pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
38#endif
39
40 /* Set IOBR for windows containing area specified in pci.h */
41 pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE - 1),
42 SH7780_PCIIOBR);
43 pci_write_reg(chan, ((SH7780_PCI_IO_SIZE - 1) & (7 << 18)),
44 SH7780_PCIIOBMR);
45
46 return 0;
47}