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-rw-r--r--drivers/net/wireless/ath/ath5k/dma.c4
-rw-r--r--drivers/net/wireless/ath/ath5k/phy.c4
-rw-r--r--drivers/net/wireless/ath/ath5k/reg.h29
3 files changed, 18 insertions, 19 deletions
diff --git a/drivers/net/wireless/ath/ath5k/dma.c b/drivers/net/wireless/ath/ath5k/dma.c
index 58bb6c5dda7b..923c9ca5c4f0 100644
--- a/drivers/net/wireless/ath/ath5k/dma.c
+++ b/drivers/net/wireless/ath/ath5k/dma.c
@@ -244,7 +244,7 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
244 244
245 /* Force channel idle high */ 245 /* Force channel idle high */
246 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, 246 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
247 AR5K_DIAG_SW_CHANEL_IDLE_HIGH); 247 AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
248 248
249 /* Wait a while and disable mechanism */ 249 /* Wait a while and disable mechanism */
250 udelay(200); 250 udelay(200);
@@ -261,7 +261,7 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
261 } while (--i && pending); 261 } while (--i && pending);
262 262
263 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211, 263 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211,
264 AR5K_DIAG_SW_CHANEL_IDLE_HIGH); 264 AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
265 } 265 }
266 266
267 /* Clear register */ 267 /* Clear register */
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index 4932bf2f35eb..61da913e7c8f 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -1257,7 +1257,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1257 * Disable beacons and RX/TX queues, wait 1257 * Disable beacons and RX/TX queues, wait
1258 */ 1258 */
1259 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1259 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1260 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1260 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1261 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1261 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1262 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1262 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1263 1263
@@ -1336,7 +1336,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1336 * Re-enable RX/TX and beacons 1336 * Re-enable RX/TX and beacons
1337 */ 1337 */
1338 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1338 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1339 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1339 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1340 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1340 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1341 1341
1342 return 0; 1342 return 0;
diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h
index 67d63081705a..a34929f06533 100644
--- a/drivers/net/wireless/ath/ath5k/reg.h
+++ b/drivers/net/wireless/ath/ath5k/reg.h
@@ -1387,10 +1387,9 @@
1387 1387
1388 1388
1389/* 1389/*
1390 * PCU control register 1390 * PCU Diagnostic register
1391 * 1391 *
1392 * Only DIS_RX is used in the code, the rest i guess are 1392 * Used for tweaking/diagnostics.
1393 * for tweaking/diagnostics.
1394 */ 1393 */
1395#define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */ 1394#define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */
1396#define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ 1395#define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */
@@ -1399,22 +1398,22 @@
1399#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 /* Disable ACKs if WEP key is invalid */ 1398#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 /* Disable ACKs if WEP key is invalid */
1400#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs */ 1399#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs */
1401#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs */ 1400#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs */
1402#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption */ 1401#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable HW encryption */
1403#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption */ 1402#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable HW decryption */
1404#define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */ 1403#define AR5K_DIAG_SW_DIS_TX_5210 0x00000020 /* Disable transmit [5210] */
1405#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */ 1404#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable receive */
1406#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 1405#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020
1407#define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \ 1406#define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \
1408 AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) 1407 AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)
1409#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* Loopback (i guess it goes with DIS_TX) [5210] */ 1408#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* TX Data Loopback (i guess it goes with DIS_TX) [5210] */
1410#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 1409#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040
1411#define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \ 1410#define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \
1412 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) 1411 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
1413#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Corrupted FCS */ 1412#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Generate invalid TX FCS */
1414#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 1413#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080
1415#define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \ 1414#define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \
1416 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) 1415 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
1417#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Dump channel info */ 1416#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Add 56 bytes of channel info before the frame data in the RX buffer */
1418#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 1417#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100
1419#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ 1418#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
1420 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) 1419 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
@@ -1426,17 +1425,17 @@
1426#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ 1425#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */
1427#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */ 1426#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */
1428#define AR5K_DIAG_SW_SCRAM_SEED_S 10 1427#define AR5K_DIAG_SW_SCRAM_SEED_S 10
1429#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ 1428#define AR5K_DIAG_SW_DIS_SEQ_INC_5210 0x00040000 /* Disable seqnum increment (?)[5210] */
1430#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 1429#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000
1431#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */ 1430#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */
1432#define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \ 1431#define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \
1433 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) 1432 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
1434#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 /* Observation point select (?) */ 1433#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 /* Observation point select (?) */
1435#define AR5K_DIAG_SW_OBSPT_S 18 1434#define AR5K_DIAG_SW_OBSPT_S 18
1436#define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000 /* Force RX Clear high */ 1435#define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x00100000 /* Ignore carrier sense */
1437#define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000 /* Ignore virtual carrier sense */ 1436#define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x00200000 /* Ignore virtual carrier sense */
1438#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000 /* Force channel idle high */ 1437#define AR5K_DIAG_SW_CHANNEL_IDLE_HIGH 0x00400000 /* Force channel idle high */
1439#define AR5K_DIAG_SW_PHEAR_ME 0x0080000 /* ??? */ 1438#define AR5K_DIAG_SW_PHEAR_ME 0x00800000 /* ??? */
1440 1439
1441/* 1440/*
1442 * TSF (clock) register (lower 32 bits) 1441 * TSF (clock) register (lower 32 bits)