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-rw-r--r--Documentation/mips/AU1xxx_IDE.README168
-rw-r--r--MAINTAINERS2
-rw-r--r--arch/mips/Kconfig1510
-rw-r--r--arch/mips/Makefile118
-rw-r--r--arch/mips/arc/Makefile2
-rw-r--r--arch/mips/arc/identify.c5
-rw-r--r--arch/mips/au1000/common/Makefile2
-rw-r--r--arch/mips/au1000/common/au1xxx_irqmap.c32
-rw-r--r--arch/mips/au1000/common/cputable.c3
-rw-r--r--arch/mips/au1000/common/dbdma.c319
-rw-r--r--arch/mips/au1000/common/dma.c1
-rw-r--r--arch/mips/au1000/common/gpio.c119
-rw-r--r--arch/mips/au1000/common/irq.c105
-rw-r--r--arch/mips/au1000/common/platform.c248
-rw-r--r--arch/mips/au1000/common/power.c19
-rw-r--r--arch/mips/au1000/common/prom.c3
-rw-r--r--arch/mips/au1000/common/puts.c77
-rw-r--r--arch/mips/au1000/common/setup.c12
-rw-r--r--arch/mips/au1000/common/time.c26
-rw-r--r--arch/mips/au1000/common/usbdev.c12
-rw-r--r--arch/mips/au1000/csb250/init.c1
-rw-r--r--arch/mips/au1000/db1x00/irqmap.c32
-rw-r--r--arch/mips/au1000/db1x00/mirage_ts.c16
-rw-r--r--arch/mips/au1000/hydrogen3/init.c1
-rw-r--r--arch/mips/au1000/mtx-1/init.c1
-rw-r--r--arch/mips/au1000/mtx-1/irqmap.c11
-rw-r--r--arch/mips/au1000/pb1000/init.c1
-rw-r--r--arch/mips/au1000/pb1200/Makefile5
-rw-r--r--arch/mips/au1000/pb1200/board_setup.c193
-rw-r--r--arch/mips/au1000/pb1200/init.c69
-rw-r--r--arch/mips/au1000/pb1200/irqmap.c182
-rw-r--r--arch/mips/au1000/pb1500/irqmap.c5
-rw-r--r--arch/mips/au1000/pb1550/irqmap.c5
-rw-r--r--arch/mips/boot/Makefile4
-rw-r--r--arch/mips/cobalt/Makefile2
-rw-r--r--arch/mips/cobalt/int-handler.S4
-rw-r--r--arch/mips/cobalt/irq.c111
-rw-r--r--arch/mips/cobalt/promcon.c87
-rw-r--r--arch/mips/cobalt/reset.c59
-rw-r--r--arch/mips/cobalt/setup.c104
-rw-r--r--arch/mips/configs/atlas_defconfig660
-rw-r--r--arch/mips/configs/bigsur_defconfig881
-rw-r--r--arch/mips/configs/capcella_defconfig450
-rw-r--r--arch/mips/configs/cobalt_defconfig367
-rw-r--r--arch/mips/configs/db1000_defconfig498
-rw-r--r--arch/mips/configs/db1100_defconfig558
-rw-r--r--arch/mips/configs/db1200_defconfig987
-rw-r--r--arch/mips/configs/db1500_defconfig459
-rw-r--r--arch/mips/configs/db1550_defconfig441
-rw-r--r--arch/mips/configs/ddb5476_defconfig389
-rw-r--r--arch/mips/configs/ddb5477_defconfig377
-rw-r--r--arch/mips/configs/decstation_defconfig463
-rw-r--r--arch/mips/configs/e55_defconfig403
-rw-r--r--arch/mips/configs/ev64120_defconfig376
-rw-r--r--arch/mips/configs/ev96100_defconfig359
-rw-r--r--arch/mips/configs/ip22_defconfig479
-rw-r--r--arch/mips/configs/ip27_defconfig466
-rw-r--r--arch/mips/configs/ip32_defconfig390
-rw-r--r--arch/mips/configs/it8172_defconfig372
-rw-r--r--arch/mips/configs/ivr_defconfig376
-rw-r--r--arch/mips/configs/jaguar-atx_defconfig339
-rw-r--r--arch/mips/configs/jmr3927_defconfig388
-rw-r--r--arch/mips/configs/lasat200_defconfig378
-rw-r--r--arch/mips/configs/malta_defconfig724
-rw-r--r--arch/mips/configs/mipssim_defconfig775
-rw-r--r--arch/mips/configs/mpc30x_defconfig607
-rw-r--r--arch/mips/configs/ocelot_3_defconfig457
-rw-r--r--arch/mips/configs/ocelot_c_defconfig372
-rw-r--r--arch/mips/configs/ocelot_defconfig359
-rw-r--r--arch/mips/configs/ocelot_g_defconfig372
-rw-r--r--arch/mips/configs/pb1100_defconfig434
-rw-r--r--arch/mips/configs/pb1500_defconfig512
-rw-r--r--arch/mips/configs/pb1550_defconfig508
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig1069
-rw-r--r--arch/mips/configs/pnx8550-v2pci_defconfig1251
-rw-r--r--arch/mips/configs/qemu_defconfig106
-rw-r--r--arch/mips/configs/rbhma4500_defconfig1259
-rw-r--r--arch/mips/configs/rm200_defconfig801
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig397
-rw-r--r--arch/mips/configs/sead_defconfig234
-rw-r--r--arch/mips/configs/tb0226_defconfig684
-rw-r--r--arch/mips/configs/tb0229_defconfig541
-rw-r--r--arch/mips/configs/tb0287_defconfig170
-rw-r--r--arch/mips/configs/workpad_defconfig416
-rw-r--r--arch/mips/configs/yosemite_defconfig346
-rw-r--r--arch/mips/ddb5xxx/Kconfig4
-rw-r--r--arch/mips/ddb5xxx/ddb5074/nile4_pic.c15
-rw-r--r--arch/mips/ddb5xxx/ddb5074/setup.c4
-rw-r--r--arch/mips/ddb5xxx/ddb5476/setup.c4
-rw-r--r--arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c15
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq_5477.c15
-rw-r--r--arch/mips/ddb5xxx/ddb5477/setup.c6
-rw-r--r--arch/mips/dec/Makefile4
-rw-r--r--arch/mips/dec/ecc-berr.c48
-rw-r--r--arch/mips/dec/int-handler.S18
-rw-r--r--arch/mips/dec/kn01-berr.c201
-rw-r--r--arch/mips/dec/kn02-irq.c13
-rw-r--r--arch/mips/dec/kn02xa-berr.c139
-rw-r--r--arch/mips/dec/prom/identify.c28
-rw-r--r--arch/mips/dec/prom/init.c16
-rw-r--r--arch/mips/dec/prom/memory.c14
-rw-r--r--arch/mips/dec/reset.c2
-rw-r--r--arch/mips/dec/setup.c57
-rw-r--r--arch/mips/defconfig479
-rw-r--r--arch/mips/galileo-boards/ev96100/setup.c4
-rw-r--r--arch/mips/gt64120/ev64120/Kconfig3
-rw-r--r--arch/mips/gt64120/ev64120/setup.c4
-rw-r--r--arch/mips/gt64120/momenco_ocelot/setup.c4
-rw-r--r--arch/mips/ite-boards/Kconfig8
-rw-r--r--arch/mips/ite-boards/generic/irq.c30
-rw-r--r--arch/mips/ite-boards/generic/it8172_setup.c4
-rw-r--r--arch/mips/jazz/Kconfig33
-rw-r--r--arch/mips/jazz/irq.c15
-rw-r--r--arch/mips/jazz/setup.c4
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c14
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c38
-rw-r--r--arch/mips/kernel/Makefile14
-rw-r--r--arch/mips/kernel/asm-offsets.c25
-rw-r--r--arch/mips/kernel/binfmt_elfn32.c4
-rw-r--r--arch/mips/kernel/binfmt_elfo32.c35
-rw-r--r--arch/mips/kernel/branch.c29
-rw-r--r--arch/mips/kernel/cpu-probe.c256
-rw-r--r--arch/mips/kernel/dma-no-isa.c28
-rw-r--r--arch/mips/kernel/entry.S54
-rw-r--r--arch/mips/kernel/gdb-low.S5
-rw-r--r--arch/mips/kernel/gdb-stub.c23
-rw-r--r--arch/mips/kernel/genex.S44
-rw-r--r--arch/mips/kernel/genrtc.c64
-rw-r--r--arch/mips/kernel/head.S70
-rw-r--r--arch/mips/kernel/i8259.c21
-rw-r--r--arch/mips/kernel/ioctl32.c6
-rw-r--r--arch/mips/kernel/irixelf.c236
-rw-r--r--arch/mips/kernel/irixinv.c7
-rw-r--r--arch/mips/kernel/irixioctl.c63
-rw-r--r--arch/mips/kernel/irixsig.c408
-rw-r--r--arch/mips/kernel/irq-msc01.c38
-rw-r--r--arch/mips/kernel/irq-mv6434x.c15
-rw-r--r--arch/mips/kernel/irq-rm7000.c14
-rw-r--r--arch/mips/kernel/irq-rm9000.c28
-rw-r--r--arch/mips/kernel/irq_cpu.c91
-rw-r--r--arch/mips/kernel/linux32.c164
-rw-r--r--arch/mips/kernel/module-elf32.c250
-rw-r--r--arch/mips/kernel/module-elf64.c274
-rw-r--r--arch/mips/kernel/module.c336
-rw-r--r--arch/mips/kernel/proc.c135
-rw-r--r--arch/mips/kernel/process.c213
-rw-r--r--arch/mips/kernel/ptrace.c242
-rw-r--r--arch/mips/kernel/ptrace32.c150
-rw-r--r--arch/mips/kernel/r4k_fpu.S5
-rw-r--r--arch/mips/kernel/rtlx.c341
-rw-r--r--arch/mips/kernel/scall32-o32.S13
-rw-r--r--arch/mips/kernel/scall64-64.S4
-rw-r--r--arch/mips/kernel/scall64-n32.S32
-rw-r--r--arch/mips/kernel/scall64-o32.S14
-rw-r--r--arch/mips/kernel/semaphore.c12
-rw-r--r--arch/mips/kernel/setup.c46
-rw-r--r--arch/mips/kernel/signal-common.h90
-rw-r--r--arch/mips/kernel/signal.c143
-rw-r--r--arch/mips/kernel/signal32.c114
-rw-r--r--arch/mips/kernel/signal_n32.c37
-rw-r--r--arch/mips/kernel/smp.c51
-rw-r--r--arch/mips/kernel/smp_mt.c366
-rw-r--r--arch/mips/kernel/syscall.c34
-rw-r--r--arch/mips/kernel/sysirix.c539
-rw-r--r--arch/mips/kernel/time.c12
-rw-r--r--arch/mips/kernel/traps.c499
-rw-r--r--arch/mips/kernel/unaligned.c10
-rw-r--r--arch/mips/kernel/vmlinux.lds.S13
-rw-r--r--arch/mips/kernel/vpe.c1296
-rw-r--r--arch/mips/lasat/Kconfig15
-rw-r--r--arch/mips/lasat/interrupt.c15
-rw-r--r--arch/mips/lasat/setup.c6
-rw-r--r--arch/mips/lib-32/dump_tlb.c106
-rw-r--r--arch/mips/lib-32/r3k_dump_tlb.c10
-rw-r--r--arch/mips/lib-64/dump_tlb.c10
-rw-r--r--arch/mips/lib/Makefile4
-rw-r--r--arch/mips/lib/csum_partial_copy.c8
-rw-r--r--arch/mips/lib/memcpy.S15
-rw-r--r--arch/mips/lib/uncached.c76
-rw-r--r--arch/mips/math-emu/cp1emu.c229
-rw-r--r--arch/mips/math-emu/dp_sqrt.c2
-rw-r--r--arch/mips/math-emu/dsemul.c17
-rw-r--r--arch/mips/math-emu/dsemul.h10
-rw-r--r--arch/mips/math-emu/ieee754.c16
-rw-r--r--arch/mips/math-emu/ieee754.h180
-rw-r--r--arch/mips/math-emu/kernel_linkage.c6
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c15
-rw-r--r--arch/mips/mips-boards/atlas/atlas_setup.c8
-rw-r--r--arch/mips/mips-boards/generic/init.c91
-rw-r--r--arch/mips/mips-boards/generic/memory.c29
-rw-r--r--arch/mips/mips-boards/generic/mipsIRQ.S110
-rw-r--r--arch/mips/mips-boards/generic/pci.c167
-rw-r--r--arch/mips/mips-boards/generic/time.c88
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c153
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c8
-rw-r--r--arch/mips/mips-boards/sead/sead_int.c12
-rw-r--r--arch/mips/mips-boards/sead/sead_setup.c2
-rw-r--r--arch/mips/mips-boards/sim/Makefile20
-rw-r--r--arch/mips/mips-boards/sim/cmdline.c59
-rw-r--r--arch/mips/mips-boards/sim/sim_IRQ.c148
-rw-r--r--arch/mips/mips-boards/sim/sim_cmdline.c33
-rw-r--r--arch/mips/mips-boards/sim/sim_int.c41
-rw-r--r--arch/mips/mips-boards/sim/sim_irq.S99
-rw-r--r--arch/mips/mips-boards/sim/sim_mem.c129
-rw-r--r--arch/mips/mips-boards/sim/sim_printf.c74
-rw-r--r--arch/mips/mips-boards/sim/sim_setup.c101
-rw-r--r--arch/mips/mips-boards/sim/sim_smp.c151
-rw-r--r--arch/mips/mips-boards/sim/sim_time.c215
-rw-r--r--arch/mips/mm/Makefile2
-rw-r--r--arch/mips/mm/c-r3k.c6
-rw-r--r--arch/mips/mm/c-r4k.c145
-rw-r--r--arch/mips/mm/c-sb1.c10
-rw-r--r--arch/mips/mm/c-tx39.c16
-rw-r--r--arch/mips/mm/cache.c106
-rw-r--r--arch/mips/mm/cerr-sb1.c54
-rw-r--r--arch/mips/mm/cex-sb1.S5
-rw-r--r--arch/mips/mm/dma-coherent.c2
-rw-r--r--arch/mips/mm/dma-noncoherent.c46
-rw-r--r--arch/mips/mm/fault.c17
-rw-r--r--arch/mips/mm/highmem.c19
-rw-r--r--arch/mips/mm/init.c34
-rw-r--r--arch/mips/mm/ioremap.c28
-rw-r--r--arch/mips/mm/pg-r4k.c21
-rw-r--r--arch/mips/mm/pg-sb1.c65
-rw-r--r--arch/mips/mm/pgtable-32.c36
-rw-r--r--arch/mips/mm/sc-rm7k.c39
-rw-r--r--arch/mips/mm/tlb-andes.c4
-rw-r--r--arch/mips/mm/tlb-r4k.c70
-rw-r--r--arch/mips/mm/tlb-sb1.c376
-rw-r--r--arch/mips/mm/tlbex.c245
-rw-r--r--arch/mips/momentum/Kconfig6
-rw-r--r--arch/mips/momentum/jaguar_atx/prom.c3
-rw-r--r--arch/mips/momentum/jaguar_atx/setup.c6
-rw-r--r--arch/mips/momentum/ocelot_3/prom.c3
-rw-r--r--arch/mips/momentum/ocelot_3/setup.c6
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c15
-rw-r--r--arch/mips/momentum/ocelot_c/setup.c4
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c15
-rw-r--r--arch/mips/momentum/ocelot_g/setup.c6
-rw-r--r--arch/mips/oprofile/Kconfig2
-rw-r--r--arch/mips/oprofile/common.c28
-rw-r--r--arch/mips/oprofile/op_impl.h5
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c215
-rw-r--r--arch/mips/oprofile/op_model_rm9000.c3
-rw-r--r--arch/mips/pci/Makefile3
-rw-r--r--arch/mips/pci/fixup-atlas.c41
-rw-r--r--arch/mips/pci/fixup-au1000.c78
-rw-r--r--arch/mips/pci/fixup-cobalt.c55
-rw-r--r--arch/mips/pci/fixup-pnx8550.c57
-rw-r--r--arch/mips/pci/fixup-tx4938.c92
-rw-r--r--arch/mips/pci/ops-au1000.c14
-rw-r--r--arch/mips/pci/ops-bonito64.c14
-rw-r--r--arch/mips/pci/ops-gt64111.c10
-rw-r--r--arch/mips/pci/ops-gt64120.c10
-rw-r--r--arch/mips/pci/ops-msc.c31
-rw-r--r--arch/mips/pci/ops-nile4.c2
-rw-r--r--arch/mips/pci/ops-pnx8550.c284
-rw-r--r--arch/mips/pci/ops-tx4938.c198
-rw-r--r--arch/mips/pci/pci-bcm1480.c265
-rw-r--r--arch/mips/pci/pci-bcm1480ht.c224
-rw-r--r--arch/mips/pci/pci-ip27.c7
-rw-r--r--arch/mips/pci/pci-ip32.c4
-rw-r--r--arch/mips/pci/pci-lasat.c56
-rw-r--r--arch/mips/pci/pci.c19
-rw-r--r--arch/mips/philips/pnx8550/common/Kconfig1
-rw-r--r--arch/mips/philips/pnx8550/common/Makefile27
-rw-r--r--arch/mips/philips/pnx8550/common/gdb_hook.c109
-rw-r--r--arch/mips/philips/pnx8550/common/int.c293
-rw-r--r--arch/mips/philips/pnx8550/common/mipsIRQ.S76
-rw-r--r--arch/mips/philips/pnx8550/common/pci.c133
-rw-r--r--arch/mips/philips/pnx8550/common/platform.c135
-rw-r--r--arch/mips/philips/pnx8550/common/proc.c113
-rw-r--r--arch/mips/philips/pnx8550/common/prom.c138
-rw-r--r--arch/mips/philips/pnx8550/common/reset.c49
-rw-r--r--arch/mips/philips/pnx8550/common/setup.c149
-rw-r--r--arch/mips/philips/pnx8550/common/time.c105
-rw-r--r--arch/mips/philips/pnx8550/jbs/Makefile4
-rw-r--r--arch/mips/philips/pnx8550/jbs/board_setup.c65
-rw-r--r--arch/mips/philips/pnx8550/jbs/init.c57
-rw-r--r--arch/mips/philips/pnx8550/jbs/irqmap.c36
-rw-r--r--arch/mips/pmc-sierra/Kconfig3
-rw-r--r--arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h1
-rw-r--r--arch/mips/pmc-sierra/yosemite/ht-irq.c1
-rw-r--r--arch/mips/pmc-sierra/yosemite/ht.c1
-rw-r--r--arch/mips/pmc-sierra/yosemite/prom.c3
-rw-r--r--arch/mips/pmc-sierra/yosemite/setup.c6
-rw-r--r--arch/mips/pmc-sierra/yosemite/smp.c2
-rw-r--r--arch/mips/qemu/q-setup.c5
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c148
-rw-r--r--arch/mips/sgi-ip22/ip22-setup.c6
-rw-r--r--arch/mips/sgi-ip27/Kconfig54
-rw-r--r--arch/mips/sgi-ip27/ip27-console.c4
-rw-r--r--arch/mips/sgi-ip27/ip27-init.c50
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c66
-rw-r--r--arch/mips/sgi-ip27/ip27-smp.c25
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c75
-rw-r--r--arch/mips/sgi-ip32/ip32-memory.c4
-rw-r--r--arch/mips/sgi-ip32/ip32-setup.c6
-rw-r--r--arch/mips/sibyte/Kconfig161
-rw-r--r--arch/mips/sibyte/bcm1480/Makefile5
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c476
-rw-r--r--arch/mips/sibyte/bcm1480/irq_handler.S165
-rw-r--r--arch/mips/sibyte/bcm1480/setup.c136
-rw-r--r--arch/mips/sibyte/bcm1480/smp.c110
-rw-r--r--arch/mips/sibyte/bcm1480/time.c138
-rw-r--r--arch/mips/sibyte/cfe/smp.c14
-rw-r--r--arch/mips/sibyte/sb1250/bcm1250_tbprof.c154
-rw-r--r--arch/mips/sibyte/sb1250/bus_watcher.c2
-rw-r--r--arch/mips/sibyte/sb1250/irq.c121
-rw-r--r--arch/mips/sibyte/sb1250/setup.c4
-rw-r--r--arch/mips/sibyte/sb1250/smp.c18
-rw-r--r--arch/mips/sibyte/sb1250/time.c44
-rw-r--r--arch/mips/sibyte/swarm/rtc_m41t81.c47
-rw-r--r--arch/mips/sibyte/swarm/rtc_xicor1241.c42
-rw-r--r--arch/mips/sibyte/swarm/setup.c41
-rw-r--r--arch/mips/sibyte/swarm/time.c44
-rw-r--r--arch/mips/sni/irq.c15
-rw-r--r--arch/mips/sni/setup.c6
-rw-r--r--arch/mips/tx4927/Kconfig3
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c6
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c23
-rw-r--r--arch/mips/tx4938/Kconfig24
-rw-r--r--arch/mips/tx4938/common/Makefile11
-rw-r--r--arch/mips/tx4938/common/dbgio.c50
-rw-r--r--arch/mips/tx4938/common/irq.c424
-rw-r--r--arch/mips/tx4938/common/irq_handler.S84
-rw-r--r--arch/mips/tx4938/common/prom.c129
-rw-r--r--arch/mips/tx4938/common/rtc_rx5c348.c202
-rw-r--r--arch/mips/tx4938/common/setup.c91
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/Makefile9
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/irq.c244
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/prom.c78
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c1035
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c219
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c159
-rw-r--r--arch/mips/vr41xx/Kconfig88
-rw-r--r--arch/mips/vr41xx/common/cmu.c2
-rw-r--r--arch/mips/vr41xx/common/init.c14
-rw-r--r--arch/mips/vr41xx/common/vrc4173.c4
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/setup.c5
-rw-r--r--drivers/char/lcd.c4
-rw-r--r--drivers/char/lcd.h2
-rw-r--r--drivers/char/qtronix.c5
-rw-r--r--drivers/ide/Kconfig31
-rw-r--r--drivers/ide/ide-proc.c1
-rw-r--r--drivers/ide/mips/au1xxx-ide.c1250
-rw-r--r--drivers/media/video/indycam.c10
-rw-r--r--drivers/media/video/saa7191.c14
-rw-r--r--drivers/media/video/vino.c7
-rw-r--r--drivers/mmc/Kconfig9
-rw-r--r--drivers/mmc/Makefile1
-rw-r--r--drivers/mmc/au1xmmc.c1026
-rw-r--r--drivers/mmc/au1xmmc.h96
-rw-r--r--drivers/pcmcia/Makefile2
-rw-r--r--drivers/pcmcia/au1000_db1x00.c21
-rw-r--r--drivers/pcmcia/au1000_generic.c8
-rw-r--r--drivers/pcmcia/au1000_generic.h4
-rw-r--r--drivers/scsi/dec_esp.c2
-rw-r--r--drivers/tc/tc.c89
-rw-r--r--drivers/tc/zs.c32
-rw-r--r--drivers/video/Kconfig8
-rw-r--r--drivers/video/Makefile2
-rw-r--r--drivers/video/au1100fb.c971
-rw-r--r--drivers/video/au1100fb.h614
-rw-r--r--drivers/video/console/newport_con.c1
-rw-r--r--drivers/video/gbefb.c20
-rw-r--r--include/asm-mips/abi.h25
-rw-r--r--include/asm-mips/addrspace.h90
-rw-r--r--include/asm-mips/asm.h4
-rw-r--r--include/asm-mips/atomic.h40
-rw-r--r--include/asm-mips/bitops.h209
-rw-r--r--include/asm-mips/bootinfo.h5
-rw-r--r--include/asm-mips/break.h1
-rw-r--r--include/asm-mips/bug.h11
-rw-r--r--include/asm-mips/bugs.h6
-rw-r--r--include/asm-mips/cache.h3
-rw-r--r--include/asm-mips/cacheflush.h31
-rw-r--r--include/asm-mips/checksum.h159
-rw-r--r--include/asm-mips/cobalt/cobalt.h52
-rw-r--r--include/asm-mips/cobalt/mach-gt64120.h1
-rw-r--r--include/asm-mips/compat.h12
-rw-r--r--include/asm-mips/cpu-features.h66
-rw-r--r--include/asm-mips/cpu-info.h2
-rw-r--r--include/asm-mips/cpu.h87
-rw-r--r--include/asm-mips/dec/ecc.h3
-rw-r--r--include/asm-mips/dec/ioasic_addrs.h3
-rw-r--r--include/asm-mips/dec/kn01.h34
-rw-r--r--include/asm-mips/dec/kn02.h33
-rw-r--r--include/asm-mips/dec/kn02xa.h46
-rw-r--r--include/asm-mips/dec/kn03.h13
-rw-r--r--include/asm-mips/dec/kn05.h76
-rw-r--r--include/asm-mips/dec/prom.h30
-rw-r--r--include/asm-mips/dec/system.h18
-rw-r--r--include/asm-mips/dec/tc.h10
-rw-r--r--include/asm-mips/delay.h8
-rw-r--r--include/asm-mips/dsp.h83
-rw-r--r--include/asm-mips/elf.h96
-rw-r--r--include/asm-mips/errno.h4
-rw-r--r--include/asm-mips/fcntl.h17
-rw-r--r--include/asm-mips/fixmap.h7
-rw-r--r--include/asm-mips/fpu.h9
-rw-r--r--include/asm-mips/fpu_emulator.h19
-rw-r--r--include/asm-mips/futex.h50
-rw-r--r--include/asm-mips/hazards.h58
-rw-r--r--include/asm-mips/highmem.h2
-rw-r--r--include/asm-mips/inst.h10
-rw-r--r--include/asm-mips/interrupt.h137
-rw-r--r--include/asm-mips/inventory.h8
-rw-r--r--include/asm-mips/io.h164
-rw-r--r--include/asm-mips/irq.h4
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h14
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h554
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx.h44
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_dbdma.h128
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_gpio.h20
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_ide.h301
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_psc.h2
-rw-r--r--include/asm-mips/mach-au1x00/ioremap.h32
-rw-r--r--include/asm-mips/mach-db1x00/db1200.h224
-rw-r--r--include/asm-mips/mach-dec/mc146818rtc.h11
-rw-r--r--include/asm-mips/mach-generic/cpu-feature-overrides.h2
-rw-r--r--include/asm-mips/mach-generic/ide.h73
-rw-r--r--include/asm-mips/mach-generic/ioremap.h23
-rw-r--r--include/asm-mips/mach-generic/kernel-entry-init.h25
-rw-r--r--include/asm-mips/mach-generic/kmalloc.h13
-rw-r--r--include/asm-mips/mach-generic/spaces.h10
-rw-r--r--include/asm-mips/mach-ip22/cpu-feature-overrides.h8
-rw-r--r--include/asm-mips/mach-ip22/spaces.h2
-rw-r--r--include/asm-mips/mach-ip27/cpu-feature-overrides.h1
-rw-r--r--include/asm-mips/mach-ip27/kernel-entry-init.h52
-rw-r--r--include/asm-mips/mach-ip27/kmalloc.h8
-rw-r--r--include/asm-mips/mach-ip27/mmzone.h2
-rw-r--r--include/asm-mips/mach-ip27/spaces.h1
-rw-r--r--include/asm-mips/mach-ip27/topology.h3
-rw-r--r--include/asm-mips/mach-ip32/cpu-feature-overrides.h1
-rw-r--r--include/asm-mips/mach-ip32/kmalloc.h12
-rw-r--r--include/asm-mips/mach-ip32/spaces.h8
-rw-r--r--include/asm-mips/mach-ja/cpu-feature-overrides.h7
-rw-r--r--include/asm-mips/mach-mips/cpu-feature-overrides.h6
-rw-r--r--include/asm-mips/mach-mips/irq.h14
-rw-r--r--include/asm-mips/mach-ocelot3/cpu-feature-overrides.h7
-rw-r--r--include/asm-mips/mach-pb1x00/pb1200.h252
-rw-r--r--include/asm-mips/mach-pnx8550/cm.h43
-rw-r--r--include/asm-mips/mach-pnx8550/glb.h86
-rw-r--r--include/asm-mips/mach-pnx8550/int.h140
-rw-r--r--include/asm-mips/mach-pnx8550/kernel-entry-init.h262
-rw-r--r--include/asm-mips/mach-pnx8550/nand.h121
-rw-r--r--include/asm-mips/mach-pnx8550/pci.h185
-rw-r--r--include/asm-mips/mach-pnx8550/uart.h16
-rw-r--r--include/asm-mips/mach-pnx8550/usb.h32
-rw-r--r--include/asm-mips/mach-rm200/cpu-feature-overrides.h3
-rw-r--r--include/asm-mips/mach-sibyte/cpu-feature-overrides.h1
-rw-r--r--include/asm-mips/mach-sim/cpu-feature-overrides.h66
-rw-r--r--include/asm-mips/mach-yosemite/cpu-feature-overrides.h7
-rw-r--r--include/asm-mips/mips-boards/generic.h7
-rw-r--r--include/asm-mips/mips-boards/maltaint.h58
-rw-r--r--include/asm-mips/mips-boards/msc01_pci.h241
-rw-r--r--include/asm-mips/mips-boards/sim.h40
-rw-r--r--include/asm-mips/mips-boards/simint.h34
-rw-r--r--include/asm-mips/mipsmtregs.h391
-rw-r--r--include/asm-mips/mipsregs.h394
-rw-r--r--include/asm-mips/mmu_context.h4
-rw-r--r--include/asm-mips/mmzone.h1
-rw-r--r--include/asm-mips/module.h90
-rw-r--r--include/asm-mips/paccess.h8
-rw-r--r--include/asm-mips/page.h42
-rw-r--r--include/asm-mips/pci.h36
-rw-r--r--include/asm-mips/pgalloc.h19
-rw-r--r--include/asm-mips/pgtable-32.h53
-rw-r--r--include/asm-mips/pgtable-64.h70
-rw-r--r--include/asm-mips/pgtable-bits.h6
-rw-r--r--include/asm-mips/pgtable.h23
-rw-r--r--include/asm-mips/processor.h22
-rw-r--r--include/asm-mips/ptrace.h19
-rw-r--r--include/asm-mips/r4kcache.h72
-rw-r--r--include/asm-mips/rtc.h53
-rw-r--r--include/asm-mips/rtlx.h56
-rw-r--r--include/asm-mips/serial.h35
-rw-r--r--include/asm-mips/sibyte/bcm1480_int.h310
-rw-r--r--include/asm-mips/sibyte/bcm1480_l2c.h176
-rw-r--r--include/asm-mips/sibyte/bcm1480_mc.h962
-rw-r--r--include/asm-mips/sibyte/bcm1480_regs.h869
-rw-r--r--include/asm-mips/sibyte/bcm1480_scd.h436
-rw-r--r--include/asm-mips/sibyte/bigsur.h49
-rw-r--r--include/asm-mips/sibyte/board.h16
-rw-r--r--include/asm-mips/sibyte/sb1250.h13
-rw-r--r--include/asm-mips/sibyte/sb1250_defs.h33
-rw-r--r--include/asm-mips/sibyte/sb1250_dma.h70
-rw-r--r--include/asm-mips/sibyte/sb1250_genbus.h230
-rw-r--r--include/asm-mips/sibyte/sb1250_int.h8
-rw-r--r--include/asm-mips/sibyte/sb1250_l2c.h11
-rw-r--r--include/asm-mips/sibyte/sb1250_ldt.h2
-rw-r--r--include/asm-mips/sibyte/sb1250_mac.h35
-rw-r--r--include/asm-mips/sibyte/sb1250_mc.h6
-rw-r--r--include/asm-mips/sibyte/sb1250_regs.h35
-rw-r--r--include/asm-mips/sibyte/sb1250_scd.h102
-rw-r--r--include/asm-mips/sibyte/sb1250_smbus.h58
-rw-r--r--include/asm-mips/sibyte/sb1250_syncser.h2
-rw-r--r--include/asm-mips/sibyte/sb1250_uart.h13
-rw-r--r--include/asm-mips/sibyte/swarm.h2
-rw-r--r--include/asm-mips/sigcontext.h60
-rw-r--r--include/asm-mips/siginfo.h1
-rw-r--r--include/asm-mips/signal.h29
-rw-r--r--include/asm-mips/sn/sn0/arch.h5
-rw-r--r--include/asm-mips/socket.h5
-rw-r--r--include/asm-mips/spinlock.h26
-rw-r--r--include/asm-mips/stackframe.h29
-rw-r--r--include/asm-mips/system.h71
-rw-r--r--include/asm-mips/thread_info.h11
-rw-r--r--include/asm-mips/traps.h3
-rw-r--r--include/asm-mips/tx4938/rbtx4938.h207
-rw-r--r--include/asm-mips/tx4938/spi.h74
-rw-r--r--include/asm-mips/tx4938/tx4938.h706
-rw-r--r--include/asm-mips/tx4938/tx4938_mips.h54
-rw-r--r--include/asm-mips/uaccess.h158
-rw-r--r--include/asm-mips/unistd.h25
-rw-r--r--include/asm-mips/vga.h25
-rw-r--r--include/asm-mips/war.h14
-rw-r--r--include/linux/ide.h2
-rw-r--r--include/linux/serial_core.h3
-rw-r--r--include/linux/serial_ip3106.h81
-rw-r--r--sound/oss/au1550_ac97.c1
522 files changed, 49209 insertions, 13775 deletions
diff --git a/Documentation/mips/AU1xxx_IDE.README b/Documentation/mips/AU1xxx_IDE.README
new file mode 100644
index 000000000000..a7e4c4ea3560
--- /dev/null
+++ b/Documentation/mips/AU1xxx_IDE.README
@@ -0,0 +1,168 @@
1README for MIPS AU1XXX IDE driver - Released 2005-07-15
2
3ABOUT
4-----
5This file describes the 'drivers/ide/mips/au1xxx-ide.c', related files and the
6services they provide.
7
8If you are short in patience and just want to know how to add your hard disc to
9the white or black list, go to the 'ADD NEW HARD DISC TO WHITE OR BLACK LIST'
10section.
11
12
13LICENSE
14-------
15
16Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
17
18This program is free software; you can redistribute it and/or modify it under
19the terms of the GNU General Public License as published by the Free Software
20Foundation; either version 2 of the License, or (at your option) any later
21version.
22
23THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
24INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
25FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
26BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32POSSIBILITY OF SUCH DAMAGE.
33
34You should have received a copy of the GNU General Public License along with
35this program; if not, write to the Free Software Foundation, Inc.,
36675 Mass Ave, Cambridge, MA 02139, USA.
37
38Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
39 Interface and Linux Device Driver" Application Note.
40
41
42FILES, CONFIGS AND COMPATABILITY
43--------------------------------
44
45Two files are introduced:
46
47 a) 'include/asm-mips/mach-au1x00/au1xxx_ide.h'
48 containes : struct _auide_hwif
49 struct drive_list_entry dma_white_list
50 struct drive_list_entry dma_black_list
51 timing parameters for PIO mode 0/1/2/3/4
52 timing parameters for MWDMA 0/1/2
53
54 b) 'drivers/ide/mips/au1xxx-ide.c'
55 contains the functionality of the AU1XXX IDE driver
56
57Four configs variables are introduced:
58
59 CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA - enable the PIO+DBDMA mode
60 CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - enable the MWDMA mode
61 CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON - set Burstable FIFO in DBDMA
62 controler
63 CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ - maximum transfer size
64 per descriptor
65
66If MWDMA is enabled and the connected hard disc is not on the white list, the
67kernel switches to a "safe mwdma mode" at boot time. In this mode the IDE
68performance is substantial slower then in full speed mwdma. In this case
69please add your hard disc to the white list (follow instruction from 'ADD NEW
70HARD DISC TO WHITE OR BLACK LIST' section).
71
72
73SUPPORTED IDE MODES
74-------------------
75
76The AU1XXX IDE driver supported all PIO modes - PIO mode 0/1/2/3/4 - and all
77MWDMA modes - MWDMA 0/1/2 -. There is no support for SWDMA and UDMA mode.
78
79To change the PIO mode use the program hdparm with option -p, e.g.
80'hdparm -p0 [device]' for PIO mode 0. To enable the MWDMA mode use the option
81-X, e.g. 'hdparm -X32 [device]' for MWDMA mode 0.
82
83
84PERFORMANCE CONFIGURATIONS
85--------------------------
86
87If the used system doesn't need USB support enable the following kernel configs:
88
89CONFIG_IDE=y
90CONFIG_BLK_DEV_IDE=y
91CONFIG_IDE_GENERIC=y
92CONFIG_BLK_DEV_IDEPCI=y
93CONFIG_BLK_DEV_GENERIC=y
94CONFIG_BLK_DEV_IDEDMA_PCI=y
95CONFIG_IDEDMA_PCI_AUTO=y
96CONFIG_BLK_DEV_IDE_AU1XXX=y
97CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y
98CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON=y
99CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128
100CONFIG_BLK_DEV_IDEDMA=y
101CONFIG_IDEDMA_AUTO=y
102
103If the used system need the USB support enable the following kernel configs for
104high IDE to USB throughput.
105
106CONFIG_BLK_DEV_IDEDISK=y
107CONFIG_IDE_GENERIC=y
108CONFIG_BLK_DEV_IDEPCI=y
109CONFIG_BLK_DEV_GENERIC=y
110CONFIG_BLK_DEV_IDEDMA_PCI=y
111CONFIG_IDEDMA_PCI_AUTO=y
112CONFIG_BLK_DEV_IDE_AU1XXX=y
113CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y
114CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128
115CONFIG_BLK_DEV_IDEDMA=y
116CONFIG_IDEDMA_AUTO=y
117
118
119ADD NEW HARD DISC TO WHITE OR BLACK LIST
120----------------------------------------
121
122Step 1 : detect the model name of your hard disc
123
124 a) connect your hard disc to the AU1XXX
125
126 b) boot your kernel and get the hard disc model.
127
128 Example boot log:
129
130 --snipped--
131 Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
132 ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx
133 Au1xxx IDE(builtin) configured for MWDMA2
134 Probing IDE interface ide0...
135 hda: Maxtor 6E040L0, ATA DISK drive
136 ide0 at 0xac800000-0xac800007,0xac8001c0 on irq 64
137 hda: max request size: 64KiB
138 hda: 80293248 sectors (41110 MB) w/2048KiB Cache, CHS=65535/16/63, (U)DMA
139 --snipped--
140
141 In this example 'Maxtor 6E040L0'.
142
143Step 2 : edit 'include/asm-mips/mach-au1x00/au1xxx_ide.h'
144
145 Add your hard disc to the dma_white_list or dma_black_list structur.
146
147Step 3 : Recompile the kernel
148
149 Enable MWDMA support in the kernel configuration. Recompile the kernel and
150 reboot.
151
152Step 4 : Tests
153
154 If you have add a hard disc to the white list, please run some stress tests
155 for verification.
156
157
158ACKNOWLEDGMENTS
159---------------
160
161These drivers wouldn't have been done without the base of kernel 2.4.x AU1XXX
162IDE driver from AMD.
163
164Additional input also from:
165Matthias Lenk <matthias.lenk@amd.com>
166
167Happy hacking!
168Enrico Walther <enrico.walther@amd.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 251a28e2d4cc..e88d193d42f8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1643,7 +1643,7 @@ S: Maintained
1643MIPS 1643MIPS
1644P: Ralf Baechle 1644P: Ralf Baechle
1645M: ralf@linux-mips.org 1645M: ralf@linux-mips.org
1646W: http://oss.sgi.com/mips/mips-howto.html 1646W: http://www.linux-mips.org/
1647L: linux-mips@linux-mips.org 1647L: linux-mips@linux-mips.org
1648S: Maintained 1648S: Maintained
1649 1649
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4cd724c05700..0097a0d53b3b 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -4,216 +4,147 @@ config MIPS
4 # Horrible source of confusion. Die, die, die ... 4 # Horrible source of confusion. Die, die, die ...
5 select EMBEDDED 5 select EMBEDDED
6 6
7# shouldn't it be per-subarchitecture?
8config ARCH_MAY_HAVE_PC_FDC
9 bool
10 default y
11
12mainmenu "Linux/MIPS Kernel Configuration" 7mainmenu "Linux/MIPS Kernel Configuration"
13 8
14source "init/Kconfig" 9source "init/Kconfig"
15 10
16config SYS_SUPPORTS_32BIT_KERNEL
17 bool
18config SYS_SUPPORTS_64BIT_KERNEL
19 bool
20config CPU_SUPPORTS_32BIT_KERNEL
21 bool
22config CPU_SUPPORTS_64BIT_KERNEL
23 bool
24
25menu "Kernel type"
26
27choice
28
29 prompt "Kernel code model"
30 help
31 You should only select this option if you have a workload that
32 actually benefits from 64-bit processing or if your machine has
33 large memory. You will only be presented a single option in this
34 menu if your system does not support both 32-bit and 64-bit kernels.
35
36config 32BIT
37 bool "32-bit kernel"
38 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
39 select TRAD_SIGNALS
40 help
41 Select this option if you want to build a 32-bit kernel.
42
43config 64BIT
44 bool "64-bit kernel"
45 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
46 help
47 Select this option if you want to build a 64-bit kernel.
48
49endchoice
50
51endmenu
52
53menu "Machine selection" 11menu "Machine selection"
54 12
55config MACH_JAZZ 13choice
56 bool "Support for the Jazz family of machines" 14 prompt "System type"
57 select ARC 15 default SGI_IP22
58 select ARC32
59 select GENERIC_ISA_DMA
60 select I8259
61 select ISA
62 select SYS_SUPPORTS_32BIT_KERNEL
63 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
64 help
65 This a family of machines based on the MIPS R4030 chipset which was
66 used by several vendors to build RISC/os and Windows NT workstations.
67 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
68 Olivetti M700-10 workstations.
69 16
70config ACER_PICA_61 17config MIPS_MTX1
71 bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)" 18 bool "Support for 4G Systems MTX-1 board"
72 depends on MACH_JAZZ && EXPERIMENTAL
73 select DMA_NONCOHERENT 19 select DMA_NONCOHERENT
74 help 20 select HW_HAS_PCI
75 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux 21 select SOC_AU1500
76 kernel that runs on these, say Y here. For details about Linux on 22 select SYS_HAS_CPU_MIPS32_R1
77 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at 23 select SYS_SUPPORTS_LITTLE_ENDIAN
78 <http://www.linux-mips.org/>.
79 24
80config MIPS_MAGNUM_4000 25config MIPS_BOSPORUS
81 bool "Support for MIPS Magnum 4000" 26 bool "AMD Alchemy Bosporus board"
82 depends on MACH_JAZZ 27 select SOC_AU1500
83 select DMA_NONCOHERENT 28 select DMA_NONCOHERENT
84 help 29 select SYS_HAS_CPU_MIPS32_R1
85 This is a machine with a R4000 100 MHz CPU. To compile a Linux 30 select SYS_SUPPORTS_LITTLE_ENDIAN
86 kernel that runs on these, say Y here. For details about Linux on
87 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
88 <http://www.linux-mips.org/>.
89 31
90config OLIVETTI_M700 32config MIPS_PB1000
91 bool "Support for Olivetti M700-10" 33 bool "AMD Alchemy PB1000 board"
92 depends on MACH_JAZZ 34 select SOC_AU1000
93 select DMA_NONCOHERENT 35 select DMA_NONCOHERENT
94 help 36 select HW_HAS_PCI
95 This is a machine with a R4000 100 MHz CPU. To compile a Linux 37 select SWAP_IO_SPACE
96 kernel that runs on these, say Y here. For details about Linux on 38 select SYS_HAS_CPU_MIPS32_R1
97 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at 39 select SYS_SUPPORTS_LITTLE_ENDIAN
98 <http://www.linux-mips.org/>.
99
100config MACH_VR41XX
101 bool "Support for NEC VR4100 series based machines"
102 select SYS_SUPPORTS_32BIT_KERNEL
103 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
104 40
105config NEC_CMBVR4133 41config MIPS_PB1100
106 bool "Support for NEC CMB-VR4133" 42 bool "AMD Alchemy PB1100 board"
107 depends on MACH_VR41XX 43 select SOC_AU1100
108 select CPU_VR41XX
109 select DMA_NONCOHERENT 44 select DMA_NONCOHERENT
110 select IRQ_CPU
111 select HW_HAS_PCI 45 select HW_HAS_PCI
46 select SWAP_IO_SPACE
47 select SYS_HAS_CPU_MIPS32_R1
48 select SYS_SUPPORTS_LITTLE_ENDIAN
112 49
113config ROCKHOPPER 50config MIPS_PB1500
114 bool "Support for Rockhopper baseboard" 51 bool "AMD Alchemy PB1500 board"
115 depends on NEC_CMBVR4133 52 select SOC_AU1500
116 select I8259 53 select DMA_NONCOHERENT
117 select HAVE_STD_PC_SERIAL_PORT 54 select HW_HAS_PCI
55 select SYS_HAS_CPU_MIPS32_R1
56 select SYS_SUPPORTS_LITTLE_ENDIAN
118 57
119config CASIO_E55 58config MIPS_PB1550
120 bool "Support for CASIO CASSIOPEIA E-10/15/55/65" 59 bool "AMD Alchemy PB1550 board"
121 depends on MACH_VR41XX 60 select SOC_AU1550
122 select CPU_LITTLE_ENDIAN
123 select DMA_NONCOHERENT 61 select DMA_NONCOHERENT
124 select IRQ_CPU 62 select HW_HAS_PCI
125 select ISA 63 select MIPS_DISABLE_OBSOLETE_IDE
64 select SYS_HAS_CPU_MIPS32_R1
65 select SYS_SUPPORTS_LITTLE_ENDIAN
126 66
127config IBM_WORKPAD 67config MIPS_PB1200
128 bool "Support for IBM WorkPad z50" 68 bool "AMD Alchemy PB1200 board"
129 depends on MACH_VR41XX 69 select SOC_AU1200
130 select CPU_LITTLE_ENDIAN
131 select DMA_NONCOHERENT 70 select DMA_NONCOHERENT
132 select IRQ_CPU 71 select MIPS_DISABLE_OBSOLETE_IDE
133 select ISA 72 select SYS_HAS_CPU_MIPS32_R1
73 select SYS_SUPPORTS_LITTLE_ENDIAN
134 74
135config TANBAC_TB022X 75config MIPS_DB1000
136 bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM" 76 bool "AMD Alchemy DB1000 board"
137 depends on MACH_VR41XX 77 select SOC_AU1000
138 select CPU_LITTLE_ENDIAN
139 select DMA_NONCOHERENT 78 select DMA_NONCOHERENT
140 select IRQ_CPU
141 select HW_HAS_PCI 79 select HW_HAS_PCI
142 help 80 select SYS_HAS_CPU_MIPS32_R1
143 The TANBAC VR4131 multichip module(TB0225) and 81 select SYS_SUPPORTS_LITTLE_ENDIAN
144 the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms
145 manufactured by TANBAC.
146 Please refer to <http://www.tanbac.co.jp/>
147 about VR4131 multichip module and VR4131DIMM.
148 82
149config TANBAC_TB0226 83config MIPS_DB1100
150 bool "Support for TANBAC Mbase(TB0226)" 84 bool "AMD Alchemy DB1100 board"
151 depends on TANBAC_TB022X 85 select SOC_AU1100
152 select GPIO_VR41XX
153 help
154 The TANBAC Mbase(TB0226) is a MIPS-based platform manufactured by TANBAC.
155 Please refer to <http://www.tanbac.co.jp/> about Mbase.
156
157config TANBAC_TB0287
158 bool "Support for TANBAC Mini-ITX DIMM base(TB0287)"
159 depends on TANBAC_TB022X
160 help
161 The TANBAC Mini-ITX DIMM base(TB0287) is a MIPS-based platform manufactured by TANBAC.
162 Please refer to <http://www.tanbac.co.jp/> about Mini-ITX DIMM base.
163
164config VICTOR_MPC30X
165 bool "Support for Victor MP-C303/304"
166 depends on MACH_VR41XX
167 select CPU_LITTLE_ENDIAN
168 select DMA_NONCOHERENT 86 select DMA_NONCOHERENT
169 select IRQ_CPU 87 select SYS_HAS_CPU_MIPS32_R1
170 select HW_HAS_PCI 88 select SYS_SUPPORTS_LITTLE_ENDIAN
171 89
172config ZAO_CAPCELLA 90config MIPS_DB1500
173 bool "Support for ZAO Networks Capcella" 91 bool "AMD Alchemy DB1500 board"
174 depends on MACH_VR41XX 92 select SOC_AU1500
175 select CPU_LITTLE_ENDIAN
176 select DMA_NONCOHERENT 93 select DMA_NONCOHERENT
177 select IRQ_CPU
178 select HW_HAS_PCI 94 select HW_HAS_PCI
95 select MIPS_DISABLE_OBSOLETE_IDE
96 select SYS_HAS_CPU_MIPS32_R1
97 select SYS_SUPPORTS_BIG_ENDIAN
98 select SYS_SUPPORTS_LITTLE_ENDIAN
179 99
180config PCI_VR41XX 100config MIPS_DB1550
181 bool "Add PCI control unit support of NEC VR4100 series" 101 bool "AMD Alchemy DB1550 board"
182 depends on MACH_VR41XX && HW_HAS_PCI 102 select SOC_AU1550
183 default y 103 select HW_HAS_PCI
184 select PCI 104 select DMA_NONCOHERENT
105 select MIPS_DISABLE_OBSOLETE_IDE
106 select SYS_HAS_CPU_MIPS32_R1
107 select SYS_SUPPORTS_LITTLE_ENDIAN
185 108
186config VRC4173 109config MIPS_DB1200
187 tristate "Add NEC VRC4173 companion chip support" 110 bool "AMD Alchemy DB1200 board"
188 depends on MACH_VR41XX && PCI_VR41XX 111 select SOC_AU1200
189 ---help--- 112 select DMA_COHERENT
190 The NEC VRC4173 is a companion chip for NEC VR4122/VR4131. 113 select MIPS_DISABLE_OBSOLETE_IDE
114 select SYS_HAS_CPU_MIPS32_R1
115 select SYS_SUPPORTS_LITTLE_ENDIAN
191 116
192config TOSHIBA_JMR3927 117config MIPS_MIRAGE
193 bool "Support for Toshiba JMR-TX3927 board" 118 bool "AMD Alchemy Mirage board"
194 select DMA_NONCOHERENT 119 select DMA_NONCOHERENT
195 select HW_HAS_PCI 120 select SOC_AU1500
196 select SWAP_IO_SPACE 121 select SYS_HAS_CPU_MIPS32_R1
197 select SYS_SUPPORTS_32BIT_KERNEL 122 select SYS_SUPPORTS_LITTLE_ENDIAN
198 123
199config MIPS_COBALT 124config MIPS_COBALT
200 bool "Support for Cobalt Server" 125 bool "Support for Cobalt Server"
201 depends on EXPERIMENTAL
202 select DMA_NONCOHERENT 126 select DMA_NONCOHERENT
203 select HW_HAS_PCI 127 select HW_HAS_PCI
204 select I8259 128 select I8259
205 select IRQ_CPU 129 select IRQ_CPU
130 select MIPS_GT64111
131 select SYS_HAS_CPU_NEVADA
206 select SYS_SUPPORTS_32BIT_KERNEL 132 select SYS_SUPPORTS_32BIT_KERNEL
207 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 133 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
134 select SYS_SUPPORTS_LITTLE_ENDIAN
208 135
209config MACH_DECSTATION 136config MACH_DECSTATION
210 bool "Support for DECstations" 137 bool "Support for DECstations"
211 select BOOT_ELF32 138 select BOOT_ELF32
212 select DMA_NONCOHERENT 139 select DMA_NONCOHERENT
140 select EARLY_PRINTK
213 select IRQ_CPU 141 select IRQ_CPU
142 select SYS_HAS_CPU_R3000
143 select SYS_HAS_CPU_R4X00
214 select SYS_SUPPORTS_32BIT_KERNEL 144 select SYS_SUPPORTS_32BIT_KERNEL
215 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 145 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
216 ---help--- 146 select SYS_SUPPORTS_LITTLE_ENDIAN
147 help
217 This enables support for DEC's MIPS based workstations. For details 148 This enables support for DEC's MIPS based workstations. For details
218 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the 149 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
219 DECstation porting pages on <http://decstation.unix-ag.org/>. 150 DECstation porting pages on <http://decstation.unix-ag.org/>.
@@ -234,8 +165,10 @@ config MIPS_EV64120
234 select DMA_NONCOHERENT 165 select DMA_NONCOHERENT
235 select HW_HAS_PCI 166 select HW_HAS_PCI
236 select MIPS_GT64120 167 select MIPS_GT64120
168 select SYS_HAS_CPU_R5000
237 select SYS_SUPPORTS_32BIT_KERNEL 169 select SYS_SUPPORTS_32BIT_KERNEL
238 select SYS_SUPPORTS_64BIT_KERNEL 170 select SYS_SUPPORTS_64BIT_KERNEL
171 select SYS_SUPPORTS_BIG_ENDIAN
239 help 172 help
240 This is an evaluation board based on the Galileo GT-64120 173 This is an evaluation board based on the Galileo GT-64120
241 single-chip system controller that contains a MIPS R5000 compatible 174 single-chip system controller that contains a MIPS R5000 compatible
@@ -243,10 +176,6 @@ config MIPS_EV64120
243 <http://www.marvell.com/>. Say Y here if you wish to build a 176 <http://www.marvell.com/>. Say Y here if you wish to build a
244 kernel for this platform. 177 kernel for this platform.
245 178
246config EVB_PCI1
247 bool "Enable Second PCI (PCI1)"
248 depends on MIPS_EV64120
249
250config MIPS_EV96100 179config MIPS_EV96100
251 bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)" 180 bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)"
252 depends on EXPERIMENTAL 181 depends on EXPERIMENTAL
@@ -256,8 +185,11 @@ config MIPS_EV96100
256 select MIPS_GT96100 185 select MIPS_GT96100
257 select RM7000_CPU_SCACHE 186 select RM7000_CPU_SCACHE
258 select SWAP_IO_SPACE 187 select SWAP_IO_SPACE
188 select SYS_HAS_CPU_R5000
189 select SYS_HAS_CPU_RM7000
259 select SYS_SUPPORTS_32BIT_KERNEL 190 select SYS_SUPPORTS_32BIT_KERNEL
260 select SYS_SUPPORTS_64BIT_KERNEL 191 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
192 select SYS_SUPPORTS_BIG_ENDIAN
261 help 193 help
262 This is an evaluation board based on the Galileo GT-96100 LAN/WAN 194 This is an evaluation board based on the Galileo GT-96100 LAN/WAN
263 communications controllers containing a MIPS R5000 compatible core 195 communications controllers containing a MIPS R5000 compatible core
@@ -268,8 +200,11 @@ config MIPS_IVR
268 bool "Support for Globespan IVR board" 200 bool "Support for Globespan IVR board"
269 select DMA_NONCOHERENT 201 select DMA_NONCOHERENT
270 select HW_HAS_PCI 202 select HW_HAS_PCI
203 select ITE_BOARD_GEN
204 select SYS_HAS_CPU_NEVADA
271 select SYS_SUPPORTS_32BIT_KERNEL 205 select SYS_SUPPORTS_32BIT_KERNEL
272 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 206 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
207 select SYS_SUPPORTS_LITTLE_ENDIAN
273 help 208 help
274 This is an evaluation board built by Globespan to showcase thir 209 This is an evaluation board built by Globespan to showcase thir
275 iVR (Internet Video Recorder) design. It utilizes a QED RM5231 210 iVR (Internet Video Recorder) design. It utilizes a QED RM5231
@@ -277,37 +212,16 @@ config MIPS_IVR
277 located at <http://www.globespan.net/>. Say Y here if you wish to 212 located at <http://www.globespan.net/>. Say Y here if you wish to
278 build a kernel for this platform. 213 build a kernel for this platform.
279 214
280config LASAT
281 bool "Support for LASAT Networks platforms"
282 select DMA_NONCOHERENT
283 select HW_HAS_PCI
284 select MIPS_GT64120
285 select R5000_CPU_SCACHE
286 select SYS_SUPPORTS_32BIT_KERNEL
287 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
288
289config PICVUE
290 tristate "PICVUE LCD display driver"
291 depends on LASAT
292
293config PICVUE_PROC
294 tristate "PICVUE LCD display driver /proc interface"
295 depends on PICVUE
296
297config DS1603
298 bool "DS1603 RTC driver"
299 depends on LASAT
300
301config LASAT_SYSCTL
302 bool "LASAT sysctl interface"
303 depends on LASAT
304
305config MIPS_ITE8172 215config MIPS_ITE8172
306 bool "Support for ITE 8172G board" 216 bool "Support for ITE 8172G board"
307 select DMA_NONCOHERENT 217 select DMA_NONCOHERENT
308 select HW_HAS_PCI 218 select HW_HAS_PCI
219 select ITE_BOARD_GEN
220 select SYS_HAS_CPU_R5432
221 select SYS_HAS_CPU_NEVADA
309 select SYS_SUPPORTS_32BIT_KERNEL 222 select SYS_SUPPORTS_32BIT_KERNEL
310 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 223 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
224 select SYS_SUPPORTS_LITTLE_ENDIAN
311 help 225 help
312 Ths is an evaluation board made by ITE <http://www.ite.com.tw/> 226 Ths is an evaluation board made by ITE <http://www.ite.com.tw/>
313 with ATX form factor that utilizes a MIPS R5000 to work with its 227 with ATX form factor that utilizes a MIPS R5000 to work with its
@@ -315,42 +229,86 @@ config MIPS_ITE8172
315 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build 229 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
316 a kernel for this platform. 230 a kernel for this platform.
317 231
318config IT8172_REVC 232config MACH_JAZZ
319 bool "Support for older IT8172 (Rev C)" 233 bool "Support for the Jazz family of machines"
320 depends on MIPS_ITE8172 234 select ARC
235 select ARC32
236 select ARCH_MAY_HAVE_PC_FDC
237 select GENERIC_ISA_DMA
238 select I8259
239 select ISA
240 select SYS_HAS_CPU_R4X00
241 select SYS_SUPPORTS_32BIT_KERNEL
242 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
321 help 243 help
322 Say Y here to support the older, Revision C version of the Integrated 244 This a family of machines based on the MIPS R4030 chipset which was
323 Technology Express, Inc. ITE8172 SBC. Vendor page at 245 used by several vendors to build RISC/os and Windows NT workstations.
324 <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the 246 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
325 board at <http://www.mvista.com/partners/semiconductor/ite.html>. 247 Olivetti M700-10 workstations.
248
249config LASAT
250 bool "Support for LASAT Networks platforms"
251 select DMA_NONCOHERENT
252 select HW_HAS_PCI
253 select MIPS_GT64120
254 select MIPS_NILE4
255 select R5000_CPU_SCACHE
256 select SYS_HAS_CPU_R5000
257 select SYS_SUPPORTS_32BIT_KERNEL
258 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
259 select SYS_SUPPORTS_LITTLE_ENDIAN
326 260
327config MIPS_ATLAS 261config MIPS_ATLAS
328 bool "Support for MIPS Atlas board" 262 bool "Support for MIPS Atlas board"
329 select BOOT_ELF32 263 select BOOT_ELF32
330 select DMA_NONCOHERENT 264 select DMA_NONCOHERENT
265 select IRQ_CPU
331 select HW_HAS_PCI 266 select HW_HAS_PCI
267 select MIPS_BOARDS_GEN
268 select MIPS_BONITO64
332 select MIPS_GT64120 269 select MIPS_GT64120
270 select MIPS_MSC
271 select RM7000_CPU_SCACHE
333 select SWAP_IO_SPACE 272 select SWAP_IO_SPACE
273 select SYS_HAS_CPU_MIPS32_R1
274 select SYS_HAS_CPU_MIPS32_R2
275 select SYS_HAS_CPU_MIPS64_R1
276 select SYS_HAS_CPU_NEVADA
277 select SYS_HAS_CPU_RM7000
334 select SYS_SUPPORTS_32BIT_KERNEL 278 select SYS_SUPPORTS_32BIT_KERNEL
335 select SYS_SUPPORTS_64BIT_KERNEL 279 select SYS_SUPPORTS_64BIT_KERNEL
280 select SYS_SUPPORTS_BIG_ENDIAN
281 select SYS_SUPPORTS_LITTLE_ENDIAN
336 help 282 help
337 This enables support for the QED R5231-based MIPS Atlas evaluation 283 This enables support for the MIPS Technologies Atlas evaluation
338 board. 284 board.
339 285
340config MIPS_MALTA 286config MIPS_MALTA
341 bool "Support for MIPS Malta board" 287 bool "Support for MIPS Malta board"
288 select ARCH_MAY_HAVE_PC_FDC
342 select BOOT_ELF32 289 select BOOT_ELF32
343 select HAVE_STD_PC_SERIAL_PORT 290 select HAVE_STD_PC_SERIAL_PORT
344 select DMA_NONCOHERENT 291 select DMA_NONCOHERENT
292 select IRQ_CPU
345 select GENERIC_ISA_DMA 293 select GENERIC_ISA_DMA
346 select HW_HAS_PCI 294 select HW_HAS_PCI
347 select I8259 295 select I8259
296 select MIPS_BOARDS_GEN
297 select MIPS_BONITO64
348 select MIPS_GT64120 298 select MIPS_GT64120
299 select MIPS_MSC
349 select SWAP_IO_SPACE 300 select SWAP_IO_SPACE
301 select SYS_HAS_CPU_MIPS32_R1
302 select SYS_HAS_CPU_MIPS32_R2
303 select SYS_HAS_CPU_MIPS64_R1
304 select SYS_HAS_CPU_NEVADA
305 select SYS_HAS_CPU_RM7000
350 select SYS_SUPPORTS_32BIT_KERNEL 306 select SYS_SUPPORTS_32BIT_KERNEL
351 select SYS_SUPPORTS_64BIT_KERNEL 307 select SYS_SUPPORTS_64BIT_KERNEL
308 select SYS_SUPPORTS_BIG_ENDIAN
309 select SYS_SUPPORTS_LITTLE_ENDIAN
352 help 310 help
353 This enables support for the VR5000-based MIPS Malta evaluation 311 This enables support for the MIPS Technologies Malta evaluation
354 board. 312 board.
355 313
356config MIPS_SEAD 314config MIPS_SEAD
@@ -358,50 +316,64 @@ config MIPS_SEAD
358 depends on EXPERIMENTAL 316 depends on EXPERIMENTAL
359 select IRQ_CPU 317 select IRQ_CPU
360 select DMA_NONCOHERENT 318 select DMA_NONCOHERENT
319 select MIPS_BOARDS_GEN
320 select SYS_HAS_CPU_MIPS32_R1
321 select SYS_HAS_CPU_MIPS32_R2
322 select SYS_HAS_CPU_MIPS64_R1
361 select SYS_SUPPORTS_32BIT_KERNEL 323 select SYS_SUPPORTS_32BIT_KERNEL
362 select SYS_SUPPORTS_64BIT_KERNEL 324 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
325 select SYS_SUPPORTS_BIG_ENDIAN
326 select SYS_SUPPORTS_LITTLE_ENDIAN
327 help
328 This enables support for the MIPS Technologies SEAD evaluation
329 board.
363 330
364config MOMENCO_OCELOT 331config MIPS_SIM
365 bool "Support for Momentum Ocelot board" 332 bool 'Support for MIPS simulator (MIPSsim)'
366 select DMA_NONCOHERENT 333 select DMA_NONCOHERENT
367 select HW_HAS_PCI
368 select IRQ_CPU 334 select IRQ_CPU
369 select IRQ_CPU_RM7K 335 select SYS_HAS_CPU_MIPS32_R1
370 select MIPS_GT64120 336 select SYS_HAS_CPU_MIPS32_R2
371 select RM7000_CPU_SCACHE
372 select SWAP_IO_SPACE
373 select SYS_SUPPORTS_32BIT_KERNEL 337 select SYS_SUPPORTS_32BIT_KERNEL
374 select SYS_SUPPORTS_64BIT_KERNEL 338 select SYS_SUPPORTS_BIG_ENDIAN
339 select SYS_SUPPORTS_LITTLE_ENDIAN
375 help 340 help
376 The Ocelot is a MIPS-based Single Board Computer (SBC) made by 341 This option enables support for MIPS Technologies MIPSsim software
377 Momentum Computer <http://www.momenco.com/>. 342 emulator.
378 343
379config MOMENCO_OCELOT_G 344config MOMENCO_JAGUAR_ATX
380 bool "Support for Momentum Ocelot-G board" 345 bool "Support for Momentum Jaguar board"
346 select BOOT_ELF32
381 select DMA_NONCOHERENT 347 select DMA_NONCOHERENT
382 select HW_HAS_PCI 348 select HW_HAS_PCI
383 select IRQ_CPU 349 select IRQ_CPU
384 select IRQ_CPU_RM7K 350 select IRQ_CPU_RM7K
351 select IRQ_MV64340
352 select LIMITED_DMA
385 select PCI_MARVELL 353 select PCI_MARVELL
386 select RM7000_CPU_SCACHE 354 select RM7000_CPU_SCACHE
387 select SWAP_IO_SPACE 355 select SWAP_IO_SPACE
356 select SYS_HAS_CPU_RM9000
388 select SYS_SUPPORTS_32BIT_KERNEL 357 select SYS_SUPPORTS_32BIT_KERNEL
389 select SYS_SUPPORTS_64BIT_KERNEL 358 select SYS_SUPPORTS_64BIT_KERNEL
359 select SYS_SUPPORTS_BIG_ENDIAN
390 help 360 help
391 The Ocelot is a MIPS-based Single Board Computer (SBC) made by 361 The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
392 Momentum Computer <http://www.momenco.com/>. 362 Momentum Computer <http://www.momenco.com/>.
393 363
394config MOMENCO_OCELOT_C 364config MOMENCO_OCELOT
395 bool "Support for Momentum Ocelot-C board" 365 bool "Support for Momentum Ocelot board"
396 select DMA_NONCOHERENT 366 select DMA_NONCOHERENT
397 select HW_HAS_PCI 367 select HW_HAS_PCI
398 select IRQ_CPU 368 select IRQ_CPU
399 select IRQ_MV64340 369 select IRQ_CPU_RM7K
400 select PCI_MARVELL 370 select MIPS_GT64120
401 select RM7000_CPU_SCACHE 371 select RM7000_CPU_SCACHE
402 select SWAP_IO_SPACE 372 select SWAP_IO_SPACE
373 select SYS_HAS_CPU_RM7000
403 select SYS_SUPPORTS_32BIT_KERNEL 374 select SYS_SUPPORTS_32BIT_KERNEL
404 select SYS_SUPPORTS_64BIT_KERNEL 375 select SYS_SUPPORTS_64BIT_KERNEL
376 select SYS_SUPPORTS_BIG_ENDIAN
405 help 377 help
406 The Ocelot is a MIPS-based Single Board Computer (SBC) made by 378 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
407 Momentum Computer <http://www.momenco.com/>. 379 Momentum Computer <http://www.momenco.com/>.
@@ -417,80 +389,95 @@ config MOMENCO_OCELOT_3
417 select PCI_MARVELL 389 select PCI_MARVELL
418 select RM7000_CPU_SCACHE 390 select RM7000_CPU_SCACHE
419 select SWAP_IO_SPACE 391 select SWAP_IO_SPACE
392 select SYS_HAS_CPU_RM9000
420 select SYS_SUPPORTS_32BIT_KERNEL 393 select SYS_SUPPORTS_32BIT_KERNEL
421 select SYS_SUPPORTS_64BIT_KERNEL 394 select SYS_SUPPORTS_64BIT_KERNEL
395 select SYS_SUPPORTS_BIG_ENDIAN
422 help 396 help
423 The Ocelot-3 is based off Discovery III System Controller and 397 The Ocelot-3 is based off Discovery III System Controller and
424 PMC-Sierra Rm79000 core. 398 PMC-Sierra Rm79000 core.
425 399
426config MOMENCO_JAGUAR_ATX 400config MOMENCO_OCELOT_C
427 bool "Support for Momentum Jaguar board" 401 bool "Support for Momentum Ocelot-C board"
428 select BOOT_ELF32
429 select DMA_NONCOHERENT 402 select DMA_NONCOHERENT
430 select HW_HAS_PCI 403 select HW_HAS_PCI
431 select IRQ_CPU 404 select IRQ_CPU
432 select IRQ_CPU_RM7K
433 select IRQ_MV64340 405 select IRQ_MV64340
434 select LIMITED_DMA
435 select PCI_MARVELL 406 select PCI_MARVELL
436 select RM7000_CPU_SCACHE 407 select RM7000_CPU_SCACHE
437 select SWAP_IO_SPACE 408 select SWAP_IO_SPACE
409 select SYS_HAS_CPU_RM7000
438 select SYS_SUPPORTS_32BIT_KERNEL 410 select SYS_SUPPORTS_32BIT_KERNEL
439 select SYS_SUPPORTS_64BIT_KERNEL 411 select SYS_SUPPORTS_64BIT_KERNEL
412 select SYS_SUPPORTS_BIG_ENDIAN
440 help 413 help
441 The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by 414 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
442 Momentum Computer <http://www.momenco.com/>. 415 Momentum Computer <http://www.momenco.com/>.
443 416
444config JAGUAR_DMALOW 417config MOMENCO_OCELOT_G
445 bool "Low DMA Mode" 418 bool "Support for Momentum Ocelot-G board"
446 depends on MOMENCO_JAGUAR_ATX 419 select DMA_NONCOHERENT
447 help
448 Select to Y if jump JP5 is set on your board, N otherwise. Normally
449 the jumper is set, so if you feel unsafe, just say Y.
450
451config PMC_YOSEMITE
452 bool "Support for PMC-Sierra Yosemite eval board"
453 select DMA_COHERENT
454 select HW_HAS_PCI 420 select HW_HAS_PCI
455 select IRQ_CPU 421 select IRQ_CPU
456 select IRQ_CPU_RM7K 422 select IRQ_CPU_RM7K
457 select IRQ_CPU_RM9K 423 select PCI_MARVELL
424 select RM7000_CPU_SCACHE
458 select SWAP_IO_SPACE 425 select SWAP_IO_SPACE
426 select SYS_HAS_CPU_RM7000
459 select SYS_SUPPORTS_32BIT_KERNEL 427 select SYS_SUPPORTS_32BIT_KERNEL
460 select SYS_SUPPORTS_64BIT_KERNEL 428 select SYS_SUPPORTS_64BIT_KERNEL
429 select SYS_SUPPORTS_BIG_ENDIAN
461 help 430 help
462 Yosemite is an evaluation board for the RM9000x2 processor 431 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
463 manufactured by PMC-Sierra 432 Momentum Computer <http://www.momenco.com/>.
464 433
465config HYPERTRANSPORT 434config MIPS_XXS1500
466 bool "Hypertransport Support for PMC-Sierra Yosemite" 435 bool "Support for MyCable XXS1500 board"
467 depends on PMC_YOSEMITE 436 select DMA_NONCOHERENT
437 select SOC_AU1500
438 select SYS_SUPPORTS_LITTLE_ENDIAN
439
440config PNX8550_V2PCI
441 bool "Support for Philips PNX8550 based Viper2-PCI board"
442 select PNX8550
443 select SYS_SUPPORTS_LITTLE_ENDIAN
444
445config PNX8550_JBS
446 bool "Support for Philips PNX8550 based JBS board"
447 select PNX8550
448 select SYS_SUPPORTS_LITTLE_ENDIAN
468 449
469config DDB5074 450config DDB5074
470 bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)" 451 bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)"
471 depends on EXPERIMENTAL 452 depends on EXPERIMENTAL
453 select DDB5XXX_COMMON
472 select DMA_NONCOHERENT 454 select DMA_NONCOHERENT
473 select HAVE_STD_PC_SERIAL_PORT 455 select HAVE_STD_PC_SERIAL_PORT
474 select HW_HAS_PCI 456 select HW_HAS_PCI
475 select IRQ_CPU 457 select IRQ_CPU
476 select I8259 458 select I8259
477 select ISA 459 select ISA
460 select SYS_HAS_CPU_R5000
478 select SYS_SUPPORTS_32BIT_KERNEL 461 select SYS_SUPPORTS_32BIT_KERNEL
479 select SYS_SUPPORTS_64BIT_KERNEL 462 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
463 select SYS_SUPPORTS_LITTLE_ENDIAN
480 help 464 help
481 This enables support for the VR5000-based NEC DDB Vrc-5074 465 This enables support for the VR5000-based NEC DDB Vrc-5074
482 evaluation board. 466 evaluation board.
483 467
484config DDB5476 468config DDB5476
485 bool "Support for NEC DDB Vrc-5476" 469 bool "Support for NEC DDB Vrc-5476"
470 select DDB5XXX_COMMON
486 select DMA_NONCOHERENT 471 select DMA_NONCOHERENT
487 select HAVE_STD_PC_SERIAL_PORT 472 select HAVE_STD_PC_SERIAL_PORT
488 select HW_HAS_PCI 473 select HW_HAS_PCI
489 select IRQ_CPU 474 select IRQ_CPU
490 select I8259 475 select I8259
491 select ISA 476 select ISA
477 select SYS_HAS_CPU_R5432
492 select SYS_SUPPORTS_32BIT_KERNEL 478 select SYS_SUPPORTS_32BIT_KERNEL
493 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 479 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
480 select SYS_SUPPORTS_LITTLE_ENDIAN
494 help 481 help
495 This enables support for the R5432-based NEC DDB Vrc-5476 482 This enables support for the R5432-based NEC DDB Vrc-5476
496 evaluation board. 483 evaluation board.
@@ -501,12 +488,15 @@ config DDB5476
501 488
502config DDB5477 489config DDB5477
503 bool "Support for NEC DDB Vrc-5477" 490 bool "Support for NEC DDB Vrc-5477"
491 select DDB5XXX_COMMON
504 select DMA_NONCOHERENT 492 select DMA_NONCOHERENT
505 select HW_HAS_PCI 493 select HW_HAS_PCI
506 select I8259 494 select I8259
507 select IRQ_CPU 495 select IRQ_CPU
496 select SYS_HAS_CPU_R5432
508 select SYS_SUPPORTS_32BIT_KERNEL 497 select SYS_SUPPORTS_32BIT_KERNEL
509 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 498 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
499 select SYS_SUPPORTS_LITTLE_ENDIAN
510 help 500 help
511 This enables support for the R5432-based NEC DDB Vrc-5477, 501 This enables support for the R5432-based NEC DDB Vrc-5477,
512 or Rockhopper/SolutionGear boards with R5432/R5500 CPUs. 502 or Rockhopper/SolutionGear boards with R5432/R5500 CPUs.
@@ -514,10 +504,28 @@ config DDB5477
514 Features : kernel debugging, serial terminal, NFS root fs, on-board 504 Features : kernel debugging, serial terminal, NFS root fs, on-board
515 ether port USB, AC97, PCI, etc. 505 ether port USB, AC97, PCI, etc.
516 506
517config DDB5477_BUS_FREQUENCY 507config MACH_VR41XX
518 int "bus frequency (in kHZ, 0 for auto-detect)" 508 bool "Support for NEC VR4100 series based machines"
519 depends on DDB5477 509 select SYS_HAS_CPU_VR41XX
520 default 0 510 select SYS_SUPPORTS_32BIT_KERNEL
511 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
512
513config PMC_YOSEMITE
514 bool "Support for PMC-Sierra Yosemite eval board"
515 select DMA_COHERENT
516 select HW_HAS_PCI
517 select IRQ_CPU
518 select IRQ_CPU_RM7K
519 select IRQ_CPU_RM9K
520 select SWAP_IO_SPACE
521 select SYS_HAS_CPU_RM9000
522 select SYS_SUPPORTS_32BIT_KERNEL
523 select SYS_SUPPORTS_64BIT_KERNEL
524 select SYS_SUPPORTS_BIG_ENDIAN
525 select SYS_SUPPORTS_HIGHMEM
526 help
527 Yosemite is an evaluation board for the RM9000x2 processor
528 manufactured by PMC-Sierra.
521 529
522config QEMU 530config QEMU
523 bool "Support for Qemu" 531 bool "Support for Qemu"
@@ -527,15 +535,16 @@ config QEMU
527 select I8259 535 select I8259
528 select ISA 536 select ISA
529 select SWAP_IO_SPACE 537 select SWAP_IO_SPACE
538 select SYS_HAS_CPU_MIPS32_R1
530 select SYS_SUPPORTS_32BIT_KERNEL 539 select SYS_SUPPORTS_32BIT_KERNEL
531 select SYS_SUPPORTS_BIG_ENDIAN 540 select SYS_SUPPORTS_BIG_ENDIAN
532 help 541 help
533 Qemu is a software emulator which among other architectures also 542 Qemu is a software emulator which among other architectures also
534 can simulate a MIPS32 4Kc system. This patch adds support for the 543 can simulate a MIPS32 4Kc system. This patch adds support for the
535 system architecture that currently is being simulated by Qemu. It 544 system architecture that currently is being simulated by Qemu. It
536 will eventually be removed again when Qemu has the capability to 545 will eventually be removed again when Qemu has the capability to
537 simulate actual MIPS hardware platforms. More information on Qemu 546 simulate actual MIPS hardware platforms. More information on Qemu
538 can be found at http://www.linux-mips.org/wiki/Qemu. 547 can be found at http://www.linux-mips.org/wiki/Qemu.
539 548
540config SGI_IP22 549config SGI_IP22
541 bool "Support for SGI IP22 (Indy/Indigo2)" 550 bool "Support for SGI IP22 (Indy/Indigo2)"
@@ -543,11 +552,15 @@ config SGI_IP22
543 select ARC32 552 select ARC32
544 select BOOT_ELF32 553 select BOOT_ELF32
545 select DMA_NONCOHERENT 554 select DMA_NONCOHERENT
555 select HW_HAS_EISA
546 select IP22_CPU_SCACHE 556 select IP22_CPU_SCACHE
547 select IRQ_CPU 557 select IRQ_CPU
548 select SWAP_IO_SPACE 558 select SWAP_IO_SPACE
559 select SYS_HAS_CPU_R4X00
560 select SYS_HAS_CPU_R5000
549 select SYS_SUPPORTS_32BIT_KERNEL 561 select SYS_SUPPORTS_32BIT_KERNEL
550 select SYS_SUPPORTS_64BIT_KERNEL 562 select SYS_SUPPORTS_64BIT_KERNEL
563 select SYS_SUPPORTS_BIG_ENDIAN
551 help 564 help
552 This are the SGI Indy, Challenge S and Indigo2, as well as certain 565 This are the SGI Indy, Challenge S and Indigo2, as well as certain
553 OEM variants like the Tandem CMN B006S. To compile a Linux kernel 566 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
@@ -557,70 +570,18 @@ config SGI_IP27
557 bool "Support for SGI IP27 (Origin200/2000)" 570 bool "Support for SGI IP27 (Origin200/2000)"
558 select ARC 571 select ARC
559 select ARC64 572 select ARC64
573 select BOOT_ELF64
560 select DMA_IP27 574 select DMA_IP27
561 select HW_HAS_PCI 575 select HW_HAS_PCI
562 select PCI_DOMAINS 576 select PCI_DOMAINS
577 select SYS_HAS_CPU_R10000
563 select SYS_SUPPORTS_64BIT_KERNEL 578 select SYS_SUPPORTS_64BIT_KERNEL
579 select SYS_SUPPORTS_BIG_ENDIAN
564 help 580 help
565 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics 581 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
566 workstations. To compile a Linux kernel that runs on these, say Y 582 workstations. To compile a Linux kernel that runs on these, say Y
567 here. 583 here.
568 584
569#config SGI_SN0_XXL
570# bool "IP27 XXL"
571# depends on SGI_IP27
572# This options adds support for userspace processes upto 16TB size.
573# Normally the limit is just .5TB.
574
575config SGI_SN0_N_MODE
576 bool "IP27 N-Mode"
577 depends on SGI_IP27
578 help
579 The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be
580 configured in either N-Modes which allows for more nodes or M-Mode
581 which allows for more memory. Your system is most probably
582 running in M-Mode, so you should say N here.
583
584config ARCH_DISCONTIGMEM_ENABLE
585 bool
586 default y if SGI_IP27
587 help
588 Say Y to upport efficient handling of discontiguous physical memory,
589 for architectures which are either NUMA (Non-Uniform Memory Access)
590 or have huge holes in the physical address space for other reasons.
591 See <file:Documentation/vm/numa> for more.
592
593config NUMA
594 bool "NUMA Support"
595 depends on SGI_IP27
596 help
597 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
598 Access). This option is for configuring high-end multiprocessor
599 server machines. If in doubt, say N.
600
601config MAPPED_KERNEL
602 bool "Mapped kernel support"
603 depends on SGI_IP27
604 help
605 Change the way a Linux kernel is loaded into memory on a MIPS64
606 machine. This is required in order to support text replication and
607 NUMA. If you need to understand it, read the source code.
608
609config REPLICATE_KTEXT
610 bool "Kernel text replication support"
611 depends on SGI_IP27
612 help
613 Say Y here to enable replicating the kernel text across multiple
614 nodes in a NUMA cluster. This trades memory for speed.
615
616config REPLICATE_EXHANDLERS
617 bool "Exception handler replication support"
618 depends on SGI_IP27
619 help
620 Say Y here to enable replicating the kernel exception handlers
621 across multiple nodes in a NUMA cluster. This trades memory for
622 speed.
623
624config SGI_IP32 585config SGI_IP32
625 bool "Support for SGI IP32 (O2) (EXPERIMENTAL)" 586 bool "Support for SGI IP32 (O2) (EXPERIMENTAL)"
626 depends on EXPERIMENTAL 587 depends on EXPERIMENTAL
@@ -633,353 +594,152 @@ config SGI_IP32
633 select HW_HAS_PCI 594 select HW_HAS_PCI
634 select R5000_CPU_SCACHE 595 select R5000_CPU_SCACHE
635 select RM7000_CPU_SCACHE 596 select RM7000_CPU_SCACHE
597 select SYS_HAS_CPU_R5000
598 select SYS_HAS_CPU_R10000 if BROKEN
599 select SYS_HAS_CPU_RM7000
636 select SYS_SUPPORTS_64BIT_KERNEL 600 select SYS_SUPPORTS_64BIT_KERNEL
601 select SYS_SUPPORTS_BIG_ENDIAN
637 help 602 help
638 If you want this kernel to run on SGI O2 workstation, say Y here. 603 If you want this kernel to run on SGI O2 workstation, say Y here.
639 604
640config SOC_AU1X00 605config SIBYTE_BIGSUR
641 bool "Support for AMD/Alchemy Au1X00 SOCs" 606 bool "Support for Sibyte BigSur"
642 select SYS_SUPPORTS_32BIT_KERNEL
643
644choice
645 prompt "Au1X00 SOC Type"
646 depends on SOC_AU1X00
647 help
648 Say Y here to enable support for one of three AMD/Alchemy
649 SOCs. For additional documentation see www.amd.com.
650
651config SOC_AU1000
652 bool "SOC_AU1000"
653config SOC_AU1100
654 bool "SOC_AU1100"
655config SOC_AU1500
656 bool "SOC_AU1500"
657config SOC_AU1550
658 bool "SOC_AU1550"
659
660endchoice
661
662choice
663 prompt "AMD/Alchemy Au1x00 board support"
664 depends on SOC_AU1X00
665 help
666 These are evaluation boards built by AMD/Alchemy to
667 showcase their Au1X00 Internet Edge Processors. The SOC design
668 is based on the MIPS32 architecture running at 266/400/500MHz
669 with many integrated peripherals. Further information can be
670 found at their website, <http://www.amd.com/>. Say Y here if you
671 wish to build a kernel for this platform.
672
673config MIPS_PB1000
674 bool "PB1000 board"
675 depends on SOC_AU1000
676 select DMA_NONCOHERENT
677 select HW_HAS_PCI
678 select SWAP_IO_SPACE
679
680config MIPS_PB1100
681 bool "PB1100 board"
682 depends on SOC_AU1100
683 select DMA_NONCOHERENT
684 select HW_HAS_PCI
685 select SWAP_IO_SPACE
686
687config MIPS_PB1500
688 bool "PB1500 board"
689 depends on SOC_AU1500
690 select DMA_COHERENT
691 select HW_HAS_PCI
692
693config MIPS_PB1550
694 bool "PB1550 board"
695 depends on SOC_AU1550
696 select DMA_COHERENT
697 select HW_HAS_PCI
698 select MIPS_DISABLE_OBSOLETE_IDE
699
700config MIPS_DB1000
701 bool "DB1000 board"
702 depends on SOC_AU1000
703 select DMA_NONCOHERENT
704 select HW_HAS_PCI
705
706config MIPS_DB1100
707 bool "DB1100 board"
708 depends on SOC_AU1100
709 select DMA_NONCOHERENT
710
711config MIPS_DB1500
712 bool "DB1500 board"
713 depends on SOC_AU1500
714 select DMA_COHERENT
715 select HW_HAS_PCI
716 select MIPS_DISABLE_OBSOLETE_IDE
717
718config MIPS_DB1550
719 bool "DB1550 board"
720 depends on SOC_AU1550
721 select HW_HAS_PCI
722 select DMA_COHERENT
723 select MIPS_DISABLE_OBSOLETE_IDE
724
725config MIPS_BOSPORUS
726 bool "Bosporus board"
727 depends on SOC_AU1500
728 select DMA_NONCOHERENT
729
730config MIPS_MIRAGE
731 bool "Mirage board"
732 depends on SOC_AU1500
733 select DMA_NONCOHERENT
734
735config MIPS_XXS1500
736 bool "MyCable XXS1500 board"
737 depends on SOC_AU1500
738 select DMA_NONCOHERENT
739
740config MIPS_MTX1
741 bool "4G Systems MTX-1 board"
742 depends on SOC_AU1500
743 select HW_HAS_PCI
744 select DMA_NONCOHERENT
745
746endchoice
747
748config SIBYTE_SB1xxx_SOC
749 bool "Support for Broadcom BCM1xxx SOCs (EXPERIMENTAL)"
750 depends on EXPERIMENTAL
751 select BOOT_ELF32 607 select BOOT_ELF32
752 select DMA_COHERENT 608 select DMA_COHERENT
609 select PCI_DOMAINS
610 select SIBYTE_BCM1x80
753 select SWAP_IO_SPACE 611 select SWAP_IO_SPACE
754 select SYS_SUPPORTS_32BIT_KERNEL 612 select SYS_HAS_CPU_SB1
755 select SYS_SUPPORTS_64BIT_KERNEL 613 select SYS_SUPPORTS_BIG_ENDIAN
756 614 select SYS_SUPPORTS_LITTLE_ENDIAN
757choice
758 prompt "BCM1xxx SOC-based board"
759 depends on SIBYTE_SB1xxx_SOC
760 default SIBYTE_SWARM
761 help
762 Enable support for boards based on the SiByte line of SOCs
763 from Broadcom. There are configurations for the known
764 evaluation boards, or you can choose "Other" and add your
765 own board support code.
766 615
767config SIBYTE_SWARM 616config SIBYTE_SWARM
768 bool "BCM91250A-SWARM" 617 bool "Support for Sibyte BCM91250A-SWARM"
618 select BOOT_ELF32
619 select DMA_COHERENT
769 select SIBYTE_SB1250 620 select SIBYTE_SB1250
621 select SWAP_IO_SPACE
622 select SYS_HAS_CPU_SB1
623 select SYS_SUPPORTS_BIG_ENDIAN
624 select SYS_SUPPORTS_HIGHMEM
625 select SYS_SUPPORTS_LITTLE_ENDIAN
770 626
771config SIBYTE_SENTOSA 627config SIBYTE_SENTOSA
772 bool "BCM91250E-Sentosa" 628 bool "Support for Sibyte BCM91250E-Sentosa"
629 depends on EXPERIMENTAL
630 select BOOT_ELF32
631 select DMA_COHERENT
773 select SIBYTE_SB1250 632 select SIBYTE_SB1250
633 select SWAP_IO_SPACE
634 select SYS_HAS_CPU_SB1
635 select SYS_SUPPORTS_BIG_ENDIAN
636 select SYS_SUPPORTS_LITTLE_ENDIAN
774 637
775config SIBYTE_RHONE 638config SIBYTE_RHONE
776 bool "BCM91125E-Rhone" 639 bool "Support for Sibyte BCM91125E-Rhone"
640 depends on EXPERIMENTAL
641 select BOOT_ELF32
642 select DMA_COHERENT
777 select SIBYTE_BCM1125H 643 select SIBYTE_BCM1125H
644 select SWAP_IO_SPACE
645 select SYS_HAS_CPU_SB1
646 select SYS_SUPPORTS_BIG_ENDIAN
647 select SYS_SUPPORTS_LITTLE_ENDIAN
778 648
779config SIBYTE_CARMEL 649config SIBYTE_CARMEL
780 bool "BCM91120x-Carmel" 650 bool "Support for Sibyte BCM91120x-Carmel"
651 depends on EXPERIMENTAL
652 select BOOT_ELF32
653 select DMA_COHERENT
781 select SIBYTE_BCM1120 654 select SIBYTE_BCM1120
655 select SWAP_IO_SPACE
656 select SYS_HAS_CPU_SB1
657 select SYS_SUPPORTS_BIG_ENDIAN
658 select SYS_SUPPORTS_LITTLE_ENDIAN
782 659
783config SIBYTE_PTSWARM 660config SIBYTE_PTSWARM
784 bool "BCM91250PT-PTSWARM" 661 bool "Support for Sibyte BCM91250PT-PTSWARM"
662 depends on EXPERIMENTAL
663 select BOOT_ELF32
664 select DMA_COHERENT
785 select SIBYTE_SB1250 665 select SIBYTE_SB1250
666 select SWAP_IO_SPACE
667 select SYS_HAS_CPU_SB1
668 select SYS_SUPPORTS_BIG_ENDIAN
669 select SYS_SUPPORTS_HIGHMEM
670 select SYS_SUPPORTS_LITTLE_ENDIAN
786 671
787config SIBYTE_LITTLESUR 672config SIBYTE_LITTLESUR
788 bool "BCM91250C2-LittleSur" 673 bool "Support for Sibyte BCM91250C2-LittleSur"
674 depends on EXPERIMENTAL
675 select BOOT_ELF32
676 select DMA_COHERENT
789 select SIBYTE_SB1250 677 select SIBYTE_SB1250
678 select SWAP_IO_SPACE
679 select SYS_HAS_CPU_SB1
680 select SYS_SUPPORTS_BIG_ENDIAN
681 select SYS_SUPPORTS_HIGHMEM
682 select SYS_SUPPORTS_LITTLE_ENDIAN
790 683
791config SIBYTE_CRHINE 684config SIBYTE_CRHINE
792 bool "BCM91120C-CRhine" 685 bool "Support for Sibyte BCM91120C-CRhine"
686 depends on EXPERIMENTAL
687 select BOOT_ELF32
688 select DMA_COHERENT
793 select SIBYTE_BCM1120 689 select SIBYTE_BCM1120
690 select SWAP_IO_SPACE
691 select SYS_HAS_CPU_SB1
692 select SYS_SUPPORTS_BIG_ENDIAN
693 select SYS_SUPPORTS_LITTLE_ENDIAN
794 694
795config SIBYTE_CRHONE 695config SIBYTE_CRHONE
796 bool "BCM91125C-CRhone" 696 bool "Support for Sibyte BCM91125C-CRhone"
797 select SIBYTE_BCM1125 697 depends on EXPERIMENTAL
798 698 select BOOT_ELF32
799config SIBYTE_UNKNOWN 699 select DMA_COHERENT
800 bool "Other"
801
802endchoice
803
804config SIBYTE_BOARD
805 bool
806 depends on SIBYTE_SB1xxx_SOC && !SIBYTE_UNKNOWN
807 default y
808
809choice
810 prompt "BCM1xxx SOC Type"
811 depends on SIBYTE_UNKNOWN
812 default SIBYTE_UNK_BCM1250
813 help
814 Since you haven't chosen a known evaluation board from
815 Broadcom, you must explicitly pick the SOC this kernel is
816 targetted for.
817
818config SIBYTE_UNK_BCM1250
819 bool "BCM1250"
820 select SIBYTE_SB1250
821
822config SIBYTE_UNK_BCM1120
823 bool "BCM1120"
824 select SIBYTE_BCM1120
825
826config SIBYTE_UNK_BCM1125
827 bool "BCM1125"
828 select SIBYTE_BCM1125 700 select SIBYTE_BCM1125
829 701 select SWAP_IO_SPACE
830config SIBYTE_UNK_BCM1125H 702 select SYS_HAS_CPU_SB1
831 bool "BCM1125H" 703 select SYS_SUPPORTS_BIG_ENDIAN
832 select SIBYTE_BCM1125H 704 select SYS_SUPPORTS_HIGHMEM
833 705 select SYS_SUPPORTS_LITTLE_ENDIAN
834endchoice
835
836config SIBYTE_SB1250
837 bool
838 select HW_HAS_PCI
839
840config SIBYTE_BCM1120
841 bool
842 select SIBYTE_BCM112X
843
844config SIBYTE_BCM1125
845 bool
846 select HW_HAS_PCI
847 select SIBYTE_BCM112X
848
849config SIBYTE_BCM1125H
850 bool
851 select HW_HAS_PCI
852 select SIBYTE_BCM112X
853
854config SIBYTE_BCM112X
855 bool
856
857choice
858 prompt "SiByte SOC Stepping"
859 depends on SIBYTE_SB1xxx_SOC
860
861config CPU_SB1_PASS_1
862 bool "1250 Pass1"
863 depends on SIBYTE_SB1250
864 select CPU_HAS_PREFETCH
865
866config CPU_SB1_PASS_2_1250
867 bool "1250 An"
868 depends on SIBYTE_SB1250
869 select CPU_SB1_PASS_2
870 help
871 Also called BCM1250 Pass 2
872
873config CPU_SB1_PASS_2_2
874 bool "1250 Bn"
875 depends on SIBYTE_SB1250
876 select CPU_HAS_PREFETCH
877 help
878 Also called BCM1250 Pass 2.2
879
880config CPU_SB1_PASS_4
881 bool "1250 Cn"
882 depends on SIBYTE_SB1250
883 select CPU_HAS_PREFETCH
884 help
885 Also called BCM1250 Pass 3
886
887config CPU_SB1_PASS_2_112x
888 bool "112x Hybrid"
889 depends on SIBYTE_BCM112X
890 select CPU_SB1_PASS_2
891
892config CPU_SB1_PASS_3
893 bool "112x An"
894 depends on SIBYTE_BCM112X
895 select CPU_HAS_PREFETCH
896
897endchoice
898
899config CPU_SB1_PASS_2
900 bool
901
902config SIBYTE_HAS_LDT
903 bool
904 depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
905 default y
906
907config SIMULATION
908 bool "Running under simulation"
909 depends on SIBYTE_SB1xxx_SOC
910 help
911 Build a kernel suitable for running under the GDB simulator.
912 Primarily adjusts the kernel's notion of time.
913
914config SIBYTE_CFE
915 bool "Booting from CFE"
916 depends on SIBYTE_SB1xxx_SOC
917 help
918 Make use of the CFE API for enumerating available memory,
919 controlling secondary CPUs, and possibly console output.
920
921config SIBYTE_CFE_CONSOLE
922 bool "Use firmware console"
923 depends on SIBYTE_CFE
924 help
925 Use the CFE API's console write routines during boot. Other console
926 options (VT console, sb1250 duart console, etc.) should not be
927 configured.
928
929config SIBYTE_STANDALONE
930 bool
931 depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
932 default y
933
934config SIBYTE_STANDALONE_RAM_SIZE
935 int "Memory size (in megabytes)"
936 depends on SIBYTE_STANDALONE
937 default "32"
938
939config SIBYTE_BUS_WATCHER
940 bool "Support for Bus Watcher statistics"
941 depends on SIBYTE_SB1xxx_SOC
942 help
943 Handle and keep statistics on the bus error interrupts (COR_ECC,
944 BAD_ECC, IO_BUS).
945
946config SIBYTE_BW_TRACE
947 bool "Capture bus trace before bus error"
948 depends on SIBYTE_BUS_WATCHER
949 help
950 Run a continuous bus trace, dumping the raw data as soon as
951 a ZBbus error is detected. Cannot work if ZBbus profiling
952 is turned on, and also will interfere with JTAG-based trace
953 buffer activity. Raw buffer data is dumped to console, and
954 must be processed off-line.
955
956config SIBYTE_SB1250_PROF
957 bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
958 depends on SIBYTE_SB1xxx_SOC
959
960config SIBYTE_TBPROF
961 bool "Support for ZBbus profiling"
962 depends on SIBYTE_SB1xxx_SOC
963 706
964config SNI_RM200_PCI 707config SNI_RM200_PCI
965 bool "Support for SNI RM200 PCI" 708 bool "Support for SNI RM200 PCI"
966 select ARC 709 select ARC
967 select ARC32 710 select ARC32
711 select ARCH_MAY_HAVE_PC_FDC
968 select BOOT_ELF32 712 select BOOT_ELF32
969 select DMA_NONCOHERENT 713 select DMA_NONCOHERENT
970 select GENERIC_ISA_DMA 714 select GENERIC_ISA_DMA
971 select HAVE_STD_PC_SERIAL_PORT 715 select HAVE_STD_PC_SERIAL_PORT
716 select HW_HAS_EISA
972 select HW_HAS_PCI 717 select HW_HAS_PCI
973 select I8259 718 select I8259
974 select ISA 719 select ISA
720 select SYS_HAS_CPU_R4X00
975 select SYS_SUPPORTS_32BIT_KERNEL 721 select SYS_SUPPORTS_32BIT_KERNEL
976 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 722 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
723 select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL
724 select SYS_SUPPORTS_HIGHMEM
725 select SYS_SUPPORTS_LITTLE_ENDIAN
977 help 726 help
978 The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens 727 The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens
979 Nixdorf Informationssysteme (SNI), parent company of Pyramid 728 Nixdorf Informationssysteme (SNI), parent company of Pyramid
980 Technology and now in turn merged with Fujitsu. Say Y here to 729 Technology and now in turn merged with Fujitsu. Say Y here to
981 support this machine type. 730 support this machine type.
982 731
732config TOSHIBA_JMR3927
733 bool "Support for Toshiba JMR-TX3927 board"
734 select DMA_NONCOHERENT
735 select HW_HAS_PCI
736 select MIPS_TX3927
737 select SWAP_IO_SPACE
738 select SYS_HAS_CPU_TX39XX
739 select SYS_SUPPORTS_32BIT_KERNEL
740 select SYS_SUPPORTS_BIG_ENDIAN
741 select TOSHIBA_BOARDS
742
983config TOSHIBA_RBTX4927 743config TOSHIBA_RBTX4927
984 bool "Support for Toshiba TBTX49[23]7 board" 744 bool "Support for Toshiba TBTX49[23]7 board"
985 select DMA_NONCOHERENT 745 select DMA_NONCOHERENT
@@ -988,15 +748,51 @@ config TOSHIBA_RBTX4927
988 select I8259 748 select I8259
989 select ISA 749 select ISA
990 select SWAP_IO_SPACE 750 select SWAP_IO_SPACE
751 select SYS_HAS_CPU_TX49XX
991 select SYS_SUPPORTS_32BIT_KERNEL 752 select SYS_SUPPORTS_32BIT_KERNEL
992 select SYS_SUPPORTS_64BIT_KERNEL 753 select SYS_SUPPORTS_64BIT_KERNEL
754 select SYS_SUPPORTS_BIG_ENDIAN
755 select TOSHIBA_BOARDS
993 help 756 help
994 This Toshiba board is based on the TX4927 processor. Say Y here to 757 This Toshiba board is based on the TX4927 processor. Say Y here to
995 support this machine type 758 support this machine type
996 759
997config TOSHIBA_FPCIB0 760config TOSHIBA_RBTX4938
998 bool "FPCIB0 Backplane Support" 761 bool "Support for Toshiba RBTX4938 board"
999 depends on TOSHIBA_RBTX4927 762 select HAVE_STD_PC_SERIAL_PORT
763 select DMA_NONCOHERENT
764 select GENERIC_ISA_DMA
765 select HAS_TXX9_SERIAL
766 select HW_HAS_PCI
767 select I8259
768 select ISA
769 select SWAP_IO_SPACE
770 select SYS_HAS_CPU_TX49XX
771 select SYS_SUPPORTS_32BIT_KERNEL
772 select SYS_SUPPORTS_LITTLE_ENDIAN
773 select SYS_SUPPORTS_BIG_ENDIAN
774 select TOSHIBA_BOARDS
775 help
776 This Toshiba board is based on the TX4938 processor. Say Y here to
777 support this machine type
778
779endchoice
780
781source "arch/mips/ddb5xxx/Kconfig"
782source "arch/mips/gt64120/ev64120/Kconfig"
783source "arch/mips/jazz/Kconfig"
784source "arch/mips/ite-boards/Kconfig"
785source "arch/mips/lasat/Kconfig"
786source "arch/mips/momentum/Kconfig"
787source "arch/mips/pmc-sierra/Kconfig"
788source "arch/mips/sgi-ip27/Kconfig"
789source "arch/mips/sibyte/Kconfig"
790source "arch/mips/tx4927/Kconfig"
791source "arch/mips/tx4938/Kconfig"
792source "arch/mips/vr41xx/Kconfig"
793source "arch/mips/philips/pnx8550/common/Kconfig"
794
795endmenu
1000 796
1001config RWSEM_GENERIC_SPINLOCK 797config RWSEM_GENERIC_SPINLOCK
1002 bool 798 bool
@@ -1014,8 +810,9 @@ config GENERIC_CALIBRATE_DELAY
1014# 810#
1015config ARC 811config ARC
1016 bool 812 bool
1017 depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 813
1018 default y 814config ARCH_MAY_HAVE_PC_FDC
815 bool
1019 816
1020config DMA_COHERENT 817config DMA_COHERENT
1021 bool 818 bool
@@ -1034,51 +831,65 @@ config DMA_NONCOHERENT
1034config DMA_NEED_PCI_MAP_STATE 831config DMA_NEED_PCI_MAP_STATE
1035 bool 832 bool
1036 833
834config OWN_DMA
835 bool
836
1037config EARLY_PRINTK 837config EARLY_PRINTK
1038 bool 838 bool
1039 depends on MACH_DECSTATION
1040 default y
1041 839
1042config GENERIC_ISA_DMA 840config GENERIC_ISA_DMA
1043 bool 841 bool
1044 depends on SNI_RM200_PCI || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 || MIPS_MALTA
1045 default y
1046 842
1047config I8259 843config I8259
1048 bool 844 bool
1049 depends on SNI_RM200_PCI || DDB5477 || DDB5476 || DDB5074 || MACH_JAZZ || MIPS_MALTA || MIPS_COBALT
1050 default y
1051 845
1052config LIMITED_DMA 846config LIMITED_DMA
1053 bool 847 bool
1054 select HIGHMEM 848 select HIGHMEM
849 select SYS_SUPPORTS_HIGHMEM
1055 850
1056config MIPS_BONITO64 851config MIPS_BONITO64
1057 bool 852 bool
1058 depends on MIPS_ATLAS || MIPS_MALTA
1059 default y
1060 853
1061config MIPS_MSC 854config MIPS_MSC
1062 bool 855 bool
1063 depends on MIPS_ATLAS || MIPS_MALTA
1064 default y
1065 856
1066config MIPS_NILE4 857config MIPS_NILE4
1067 bool 858 bool
1068 depends on LASAT
1069 default y
1070 859
1071config MIPS_DISABLE_OBSOLETE_IDE 860config MIPS_DISABLE_OBSOLETE_IDE
1072 bool 861 bool
1073 862
1074config CPU_LITTLE_ENDIAN 863#
1075 bool "Generate little endian code" 864# Endianess selection. Suffiently obscure so many users don't know what to
1076 default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA 865# answer,so we try hard to limit the available choices. Also the use of a
1077 default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927 866# choice statement should be more obvious to the user.
867#
868choice
869 prompt "Endianess selection"
1078 help 870 help
1079 Some MIPS machines can be configured for either little or big endian 871 Some MIPS machines can be configured for either little or big endian
1080 byte order. These modes require different kernels. Say Y if your 872 byte order. These modes require different kernels and a different
1081 machine is little endian, N if it's a big endian machine. 873 Linux distribution. In general there is one prefered byteorder for a
874 particular system but some systems are just as commonly used in the
875 one or the other endianess.
876
877config CPU_BIG_ENDIAN
878 bool "Big endian"
879 depends on SYS_SUPPORTS_BIG_ENDIAN
880
881config CPU_LITTLE_ENDIAN
882 bool "Little endian"
883 depends on SYS_SUPPORTS_LITTLE_ENDIAN
884 help
885
886endchoice
887
888config SYS_SUPPORTS_BIG_ENDIAN
889 bool
890
891config SYS_SUPPORTS_LITTLE_ENDIAN
892 bool
1082 893
1083config IRQ_CPU 894config IRQ_CPU
1084 bool 895 bool
@@ -1086,42 +897,69 @@ config IRQ_CPU
1086config IRQ_CPU_RM7K 897config IRQ_CPU_RM7K
1087 bool 898 bool
1088 899
900config IRQ_CPU_RM9K
901 bool
902
1089config IRQ_MV64340 903config IRQ_MV64340
1090 bool 904 bool
1091 905
1092config DDB5XXX_COMMON 906config DDB5XXX_COMMON
1093 bool 907 bool
1094 depends on DDB5074 || DDB5476 || DDB5477
1095 default y
1096 908
1097config MIPS_BOARDS_GEN 909config MIPS_BOARDS_GEN
1098 bool 910 bool
1099 depends on MIPS_ATLAS || MIPS_MALTA || MIPS_SEAD
1100 default y
1101 911
1102config MIPS_GT64111 912config MIPS_GT64111
1103 bool 913 bool
1104 depends on MIPS_COBALT
1105 default y
1106 914
1107config MIPS_GT64120 915config MIPS_GT64120
1108 bool 916 bool
1109 depends on MIPS_EV64120 || MIPS_EV96100 || LASAT || MIPS_ATLAS || MIPS_MALTA || MOMENCO_OCELOT
1110 default y
1111 917
1112config MIPS_TX3927 918config MIPS_TX3927
1113 bool 919 bool
1114 depends on TOSHIBA_JMR3927
1115 select HAS_TXX9_SERIAL 920 select HAS_TXX9_SERIAL
1116 default y
1117 921
1118config PCI_MARVELL 922config PCI_MARVELL
1119 bool 923 bool
1120 924
1121config ITE_BOARD_GEN 925config ITE_BOARD_GEN
1122 bool 926 bool
1123 depends on MIPS_IVR || MIPS_ITE8172 927
1124 default y 928config SOC_AU1000
929 bool
930 select SOC_AU1X00
931
932config SOC_AU1100
933 bool
934 select SOC_AU1X00
935
936config SOC_AU1500
937 bool
938 select SOC_AU1X00
939
940config SOC_AU1550
941 bool
942 select SOC_AU1X00
943
944config SOC_AU1200
945 bool
946 select SOC_AU1X00
947
948config SOC_AU1X00
949 bool
950 select SYS_HAS_CPU_MIPS32_R1
951 select SYS_SUPPORTS_32BIT_KERNEL
952
953config PNX8550
954 bool
955 select SOC_PNX8550
956
957config SOC_PNX8550
958 bool
959 select DMA_NONCOHERENT
960 select HW_HAS_PCI
961 select SYS_HAS_CPU_R4X00
962 select SYS_SUPPORTS_32BIT_KERNEL
1125 963
1126config SWAP_IO_SPACE 964config SWAP_IO_SPACE
1127 bool 965 bool
@@ -1148,6 +986,9 @@ config SYSCLK_100
1148 986
1149endchoice 987endchoice
1150 988
989config ARC32
990 bool
991
1151config AU1X00_USB_DEVICE 992config AU1X00_USB_DEVICE
1152 bool 993 bool
1153 depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 994 depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000
@@ -1155,11 +996,7 @@ config AU1X00_USB_DEVICE
1155 996
1156config MIPS_GT96100 997config MIPS_GT96100
1157 bool 998 bool
1158 depends on MIPS_EV96100 999 select MIPS_GT64120
1159 default y
1160 help
1161 Say Y here to support the Galileo Technology GT96100 communications
1162 controller card. There is a web page at <http://www.galileot.com/>.
1163 1000
1164config IT8172_CIR 1001config IT8172_CIR
1165 bool 1002 bool
@@ -1173,8 +1010,6 @@ config IT8712
1173 1010
1174config BOOT_ELF32 1011config BOOT_ELF32
1175 bool 1012 bool
1176 depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI
1177 default y
1178 1013
1179config MIPS_L1_CACHE_SHIFT 1014config MIPS_L1_CACHE_SHIFT
1180 int 1015 int
@@ -1182,11 +1017,6 @@ config MIPS_L1_CACHE_SHIFT
1182 default "7" if SGI_IP27 1017 default "7" if SGI_IP27
1183 default "5" 1018 default "5"
1184 1019
1185config ARC32
1186 bool
1187 depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32
1188 default y
1189
1190config HAVE_STD_PC_SERIAL_PORT 1020config HAVE_STD_PC_SERIAL_PORT
1191 bool 1021 bool
1192 1022
@@ -1206,30 +1036,12 @@ config ARC_PROMLIB
1206 1036
1207config ARC64 1037config ARC64
1208 bool 1038 bool
1209 depends on SGI_IP27
1210 default y
1211 1039
1212config BOOT_ELF64 1040config BOOT_ELF64
1213 bool 1041 bool
1214 depends on SGI_IP27
1215 default y
1216
1217#config MAPPED_PCI_IO y
1218# bool
1219# depends on SGI_IP27
1220# default y
1221
1222config QL_ISP_A64
1223 bool
1224 depends on SGI_IP27
1225 default y
1226 1042
1227config TOSHIBA_BOARDS 1043config TOSHIBA_BOARDS
1228 bool 1044 bool
1229 depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927
1230 default y
1231
1232endmenu
1233 1045
1234menu "CPU selection" 1046menu "CPU selection"
1235 1047
@@ -1237,18 +1049,69 @@ choice
1237 prompt "CPU type" 1049 prompt "CPU type"
1238 default CPU_R4X00 1050 default CPU_R4X00
1239 1051
1240config CPU_MIPS32 1052config CPU_MIPS32_R1
1241 bool "MIPS32" 1053 bool "MIPS32 Release 1"
1054 depends on SYS_HAS_CPU_MIPS32_R1
1055 select CPU_HAS_PREFETCH
1242 select CPU_SUPPORTS_32BIT_KERNEL 1056 select CPU_SUPPORTS_32BIT_KERNEL
1057 help
1058 Choose this option to build a kernel for release 1 or later of the
1059 MIPS32 architecture. Most modern embedded systems with a 32-bit
1060 MIPS processor are based on a MIPS32 processor. If you know the
1061 specific type of processor in your system, choose those that one
1062 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1063 Release 2 of the MIPS32 architecture is available since several
1064 years so chances are you even have a MIPS32 Release 2 processor
1065 in which case you should choose CPU_MIPS32_R2 instead for better
1066 performance.
1067
1068config CPU_MIPS32_R2
1069 bool "MIPS32 Release 2"
1070 depends on SYS_HAS_CPU_MIPS32_R2
1071 select CPU_HAS_PREFETCH
1072 select CPU_SUPPORTS_32BIT_KERNEL
1073 help
1074 Choose this option to build a kernel for release 2 or later of the
1075 MIPS32 architecture. Most modern embedded systems with a 32-bit
1076 MIPS processor are based on a MIPS32 processor. If you know the
1077 specific type of processor in your system, choose those that one
1078 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1243 1079
1244config CPU_MIPS64 1080config CPU_MIPS64_R1
1245 bool "MIPS64" 1081 bool "MIPS64 Release 1"
1082 depends on SYS_HAS_CPU_MIPS64_R1
1083 select CPU_HAS_PREFETCH
1246 select CPU_SUPPORTS_32BIT_KERNEL 1084 select CPU_SUPPORTS_32BIT_KERNEL
1247 select CPU_SUPPORTS_64BIT_KERNEL 1085 select CPU_SUPPORTS_64BIT_KERNEL
1086 help
1087 Choose this option to build a kernel for release 1 or later of the
1088 MIPS64 architecture. Many modern embedded systems with a 64-bit
1089 MIPS processor are based on a MIPS64 processor. If you know the
1090 specific type of processor in your system, choose those that one
1091 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1092 Release 2 of the MIPS64 architecture is available since several
1093 years so chances are you even have a MIPS64 Release 2 processor
1094 in which case you should choose CPU_MIPS64_R2 instead for better
1095 performance.
1096
1097config CPU_MIPS64_R2
1098 bool "MIPS64 Release 2"
1099 depends on SYS_HAS_CPU_MIPS64_R2
1100 select CPU_HAS_PREFETCH
1101 select CPU_SUPPORTS_32BIT_KERNEL
1102 select CPU_SUPPORTS_64BIT_KERNEL
1103 help
1104 Choose this option to build a kernel for release 2 or later of the
1105 MIPS64 architecture. Many modern embedded systems with a 64-bit
1106 MIPS processor are based on a MIPS64 processor. If you know the
1107 specific type of processor in your system, choose those that one
1108 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1248 1109
1249config CPU_R3000 1110config CPU_R3000
1250 bool "R3000" 1111 bool "R3000"
1112 depends on SYS_HAS_CPU_R3000
1251 select CPU_SUPPORTS_32BIT_KERNEL 1113 select CPU_SUPPORTS_32BIT_KERNEL
1114 select CPU_SUPPORTS_HIGHMEM
1252 help 1115 help
1253 Please make sure to pick the right CPU type. Linux/MIPS is not 1116 Please make sure to pick the right CPU type. Linux/MIPS is not
1254 designed to be generic, i.e. Kernels compiled for R3000 CPUs will 1117 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
@@ -1259,20 +1122,23 @@ config CPU_R3000
1259 1122
1260config CPU_TX39XX 1123config CPU_TX39XX
1261 bool "R39XX" 1124 bool "R39XX"
1125 depends on SYS_HAS_CPU_TX39XX
1262 select CPU_SUPPORTS_32BIT_KERNEL 1126 select CPU_SUPPORTS_32BIT_KERNEL
1263 1127
1264config CPU_VR41XX 1128config CPU_VR41XX
1265 bool "R41xx" 1129 bool "R41xx"
1130 depends on SYS_HAS_CPU_VR41XX
1266 select CPU_SUPPORTS_32BIT_KERNEL 1131 select CPU_SUPPORTS_32BIT_KERNEL
1267 select CPU_SUPPORTS_64BIT_KERNEL 1132 select CPU_SUPPORTS_64BIT_KERNEL
1268 help 1133 help
1269 The options selects support for the NEC VR41xx series of processors. 1134 The options selects support for the NEC VR4100 series of processors.
1270 Only choose this option if you have one of these processors as a 1135 Only choose this option if you have one of these processors as a
1271 kernel built with this option will not run on any other type of 1136 kernel built with this option will not run on any other type of
1272 processor or vice versa. 1137 processor or vice versa.
1273 1138
1274config CPU_R4300 1139config CPU_R4300
1275 bool "R4300" 1140 bool "R4300"
1141 depends on SYS_HAS_CPU_R4300
1276 select CPU_SUPPORTS_32BIT_KERNEL 1142 select CPU_SUPPORTS_32BIT_KERNEL
1277 select CPU_SUPPORTS_64BIT_KERNEL 1143 select CPU_SUPPORTS_64BIT_KERNEL
1278 help 1144 help
@@ -1280,6 +1146,7 @@ config CPU_R4300
1280 1146
1281config CPU_R4X00 1147config CPU_R4X00
1282 bool "R4x00" 1148 bool "R4x00"
1149 depends on SYS_HAS_CPU_R4X00
1283 select CPU_SUPPORTS_32BIT_KERNEL 1150 select CPU_SUPPORTS_32BIT_KERNEL
1284 select CPU_SUPPORTS_64BIT_KERNEL 1151 select CPU_SUPPORTS_64BIT_KERNEL
1285 help 1152 help
@@ -1288,11 +1155,13 @@ config CPU_R4X00
1288 1155
1289config CPU_TX49XX 1156config CPU_TX49XX
1290 bool "R49XX" 1157 bool "R49XX"
1158 depends on SYS_HAS_CPU_TX49XX
1291 select CPU_SUPPORTS_32BIT_KERNEL 1159 select CPU_SUPPORTS_32BIT_KERNEL
1292 select CPU_SUPPORTS_64BIT_KERNEL 1160 select CPU_SUPPORTS_64BIT_KERNEL
1293 1161
1294config CPU_R5000 1162config CPU_R5000
1295 bool "R5000" 1163 bool "R5000"
1164 depends on SYS_HAS_CPU_R5000
1296 select CPU_SUPPORTS_32BIT_KERNEL 1165 select CPU_SUPPORTS_32BIT_KERNEL
1297 select CPU_SUPPORTS_64BIT_KERNEL 1166 select CPU_SUPPORTS_64BIT_KERNEL
1298 help 1167 help
@@ -1300,10 +1169,14 @@ config CPU_R5000
1300 1169
1301config CPU_R5432 1170config CPU_R5432
1302 bool "R5432" 1171 bool "R5432"
1172 depends on SYS_HAS_CPU_R5432
1173 select CPU_SUPPORTS_32BIT_KERNEL
1174 select CPU_SUPPORTS_64BIT_KERNEL
1303 1175
1304config CPU_R6000 1176config CPU_R6000
1305 bool "R6000" 1177 bool "R6000"
1306 depends on EXPERIMENTAL 1178 depends on EXPERIMENTAL
1179 depends on SYS_HAS_CPU_R6000
1307 select CPU_SUPPORTS_32BIT_KERNEL 1180 select CPU_SUPPORTS_32BIT_KERNEL
1308 help 1181 help
1309 MIPS Technologies R6000 and R6000A series processors. Note these 1182 MIPS Technologies R6000 and R6000A series processors. Note these
@@ -1311,6 +1184,7 @@ config CPU_R6000
1311 1184
1312config CPU_NEVADA 1185config CPU_NEVADA
1313 bool "RM52xx" 1186 bool "RM52xx"
1187 depends on SYS_HAS_CPU_NEVADA
1314 select CPU_SUPPORTS_32BIT_KERNEL 1188 select CPU_SUPPORTS_32BIT_KERNEL
1315 select CPU_SUPPORTS_64BIT_KERNEL 1189 select CPU_SUPPORTS_64BIT_KERNEL
1316 help 1190 help
@@ -1319,6 +1193,8 @@ config CPU_NEVADA
1319config CPU_R8000 1193config CPU_R8000
1320 bool "R8000" 1194 bool "R8000"
1321 depends on EXPERIMENTAL 1195 depends on EXPERIMENTAL
1196 depends on SYS_HAS_CPU_R8000
1197 select CPU_HAS_PREFETCH
1322 select CPU_SUPPORTS_64BIT_KERNEL 1198 select CPU_SUPPORTS_64BIT_KERNEL
1323 help 1199 help
1324 MIPS Technologies R8000 processors. Note these processors are 1200 MIPS Technologies R8000 processors. Note these processors are
@@ -1326,25 +1202,151 @@ config CPU_R8000
1326 1202
1327config CPU_R10000 1203config CPU_R10000
1328 bool "R10000" 1204 bool "R10000"
1205 depends on SYS_HAS_CPU_R10000
1206 select CPU_HAS_PREFETCH
1329 select CPU_SUPPORTS_32BIT_KERNEL 1207 select CPU_SUPPORTS_32BIT_KERNEL
1330 select CPU_SUPPORTS_64BIT_KERNEL 1208 select CPU_SUPPORTS_64BIT_KERNEL
1209 select CPU_SUPPORTS_HIGHMEM
1331 help 1210 help
1332 MIPS Technologies R10000-series processors. 1211 MIPS Technologies R10000-series processors.
1333 1212
1334config CPU_RM7000 1213config CPU_RM7000
1335 bool "RM7000" 1214 bool "RM7000"
1215 depends on SYS_HAS_CPU_RM7000
1216 select CPU_HAS_PREFETCH
1336 select CPU_SUPPORTS_32BIT_KERNEL 1217 select CPU_SUPPORTS_32BIT_KERNEL
1337 select CPU_SUPPORTS_64BIT_KERNEL 1218 select CPU_SUPPORTS_64BIT_KERNEL
1219 select CPU_SUPPORTS_HIGHMEM
1338 1220
1339config CPU_RM9000 1221config CPU_RM9000
1340 bool "RM9000" 1222 bool "RM9000"
1223 depends on SYS_HAS_CPU_RM9000
1224 select CPU_HAS_PREFETCH
1341 select CPU_SUPPORTS_32BIT_KERNEL 1225 select CPU_SUPPORTS_32BIT_KERNEL
1342 select CPU_SUPPORTS_64BIT_KERNEL 1226 select CPU_SUPPORTS_64BIT_KERNEL
1227 select CPU_SUPPORTS_HIGHMEM
1343 1228
1344config CPU_SB1 1229config CPU_SB1
1345 bool "SB1" 1230 bool "SB1"
1231 depends on SYS_HAS_CPU_SB1
1346 select CPU_SUPPORTS_32BIT_KERNEL 1232 select CPU_SUPPORTS_32BIT_KERNEL
1347 select CPU_SUPPORTS_64BIT_KERNEL 1233 select CPU_SUPPORTS_64BIT_KERNEL
1234 select CPU_SUPPORTS_HIGHMEM
1235
1236endchoice
1237
1238config SYS_HAS_CPU_MIPS32_R1
1239 bool
1240
1241config SYS_HAS_CPU_MIPS32_R2
1242 bool
1243
1244config SYS_HAS_CPU_MIPS64_R1
1245 bool
1246
1247config SYS_HAS_CPU_MIPS64_R2
1248 bool
1249
1250config SYS_HAS_CPU_R3000
1251 bool
1252
1253config SYS_HAS_CPU_TX39XX
1254 bool
1255
1256config SYS_HAS_CPU_VR41XX
1257 bool
1258
1259config SYS_HAS_CPU_R4300
1260 bool
1261
1262config SYS_HAS_CPU_R4X00
1263 bool
1264
1265config SYS_HAS_CPU_TX49XX
1266 bool
1267
1268config SYS_HAS_CPU_R5000
1269 bool
1270
1271config SYS_HAS_CPU_R5432
1272 bool
1273
1274config SYS_HAS_CPU_R6000
1275 bool
1276
1277config SYS_HAS_CPU_NEVADA
1278 bool
1279
1280config SYS_HAS_CPU_R8000
1281 bool
1282
1283config SYS_HAS_CPU_R10000
1284 bool
1285
1286config SYS_HAS_CPU_RM7000
1287 bool
1288
1289config SYS_HAS_CPU_RM9000
1290 bool
1291
1292config SYS_HAS_CPU_SB1
1293 bool
1294
1295endmenu
1296
1297#
1298# These two indicate any levelof the MIPS32 and MIPS64 architecture
1299#
1300config CPU_MIPS32
1301 bool
1302 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
1303
1304config CPU_MIPS64
1305 bool
1306 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
1307
1308#
1309# These two indicate the revision of the architecture, either 32 bot 64 bit.
1310#
1311config CPU_MIPSR1
1312 bool
1313 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1314
1315config CPU_MIPSR2
1316 bool
1317 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2
1318
1319config SYS_SUPPORTS_32BIT_KERNEL
1320 bool
1321config SYS_SUPPORTS_64BIT_KERNEL
1322 bool
1323config CPU_SUPPORTS_32BIT_KERNEL
1324 bool
1325config CPU_SUPPORTS_64BIT_KERNEL
1326 bool
1327
1328menu "Kernel type"
1329
1330choice
1331
1332 prompt "Kernel code model"
1333 help
1334 You should only select this option if you have a workload that
1335 actually benefits from 64-bit processing or if your machine has
1336 large memory. You will only be presented a single option in this
1337 menu if your system does not support both 32-bit and 64-bit kernels.
1338
1339config 32BIT
1340 bool "32-bit kernel"
1341 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1342 select TRAD_SIGNALS
1343 help
1344 Select this option if you want to build a 32-bit kernel.
1345config 64BIT
1346 bool "64-bit kernel"
1347 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1348 help
1349 Select this option if you want to build a 64-bit kernel.
1348 1350
1349endchoice 1351endchoice
1350 1352
@@ -1416,12 +1418,43 @@ config SIBYTE_DMA_PAGEOPS
1416 SiByte Linux port. Seems to give a small performance benefit. 1418 SiByte Linux port. Seems to give a small performance benefit.
1417 1419
1418config CPU_HAS_PREFETCH 1420config CPU_HAS_PREFETCH
1419 bool "Enable prefetches" if CPU_SB1 && !CPU_SB1_PASS_2 1421 bool
1420 default y if CPU_MIPS32 || CPU_MIPS64 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 1422
1423config MIPS_MT
1424 bool "Enable MIPS MT"
1425
1426choice
1427 prompt "MIPS MT options"
1428 depends on MIPS_MT
1421 1429
1422config VTAG_ICACHE 1430config MIPS_MT_SMP
1423 bool "Support for Virtual Tagged I-cache" if CPU_MIPS64 || CPU_MIPS32 1431 bool "Use 1 TC on each available VPE for SMP"
1424 default y if CPU_SB1 1432 select SMP
1433
1434config MIPS_VPE_LOADER
1435 bool "VPE loader support."
1436 depends on MIPS_MT
1437 help
1438 Includes a loader for loading an elf relocatable object
1439 onto another VPE and running it.
1440
1441endchoice
1442
1443config MIPS_VPE_LOADER_TOM
1444 bool "Load VPE program into memory hidden from linux"
1445 depends on MIPS_VPE_LOADER
1446 default y
1447 help
1448 The loader can use memory that is present but has been hidden from
1449 Linux using the kernel command line option "mem=xxMB". It's up to
1450 you to ensure the amount you put in the option and the space your
1451 program requires is less or equal to the amount physically present.
1452
1453# this should possibly be in drivers/char, but it is rather cpu related. Hmmm
1454config MIPS_VPE_APSP_API
1455 bool "Enable support for AP/SP API (RTLX)"
1456 depends on MIPS_VPE_LOADER
1457 help
1425 1458
1426config SB1_PASS_1_WORKAROUNDS 1459config SB1_PASS_1_WORKAROUNDS
1427 bool 1460 bool
@@ -1440,7 +1473,7 @@ config SB1_PASS_2_1_WORKAROUNDS
1440 1473
1441config 64BIT_PHYS_ADDR 1474config 64BIT_PHYS_ADDR
1442 bool "Support for 64-bit physical address space" 1475 bool "Support for 64-bit physical address space"
1443 depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT 1476 depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32_R1 || CPU_MIPS64_R1) && 32BIT
1444 1477
1445config CPU_ADVANCED 1478config CPU_ADVANCED
1446 bool "Override CPU Options" 1479 bool "Override CPU Options"
@@ -1463,7 +1496,7 @@ config CPU_HAS_LLSC
1463 1496
1464config CPU_HAS_LLDSCD 1497config CPU_HAS_LLDSCD
1465 bool "lld/scd Instructions available" if CPU_ADVANCED 1498 bool "lld/scd Instructions available" if CPU_ADVANCED
1466 default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32 1499 default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32_R1
1467 help 1500 help
1468 Say Y here if your CPU has the lld and scd instructions, the 64-bit 1501 Say Y here if your CPU has the lld and scd instructions, the 64-bit
1469 equivalents of ll and sc. Say Y here for better performance, N if 1502 equivalents of ll and sc. Say Y here for better performance, N if
@@ -1477,12 +1510,52 @@ config CPU_HAS_WB
1477 machines which require flushing of write buffers in software. Saying 1510 machines which require flushing of write buffers in software. Saying
1478 Y is the safe option; N may result in kernel malfunction and crashes. 1511 Y is the safe option; N may result in kernel malfunction and crashes.
1479 1512
1513menu "MIPSR2 Interrupt handling"
1514 depends on CPU_MIPSR2 && CPU_ADVANCED
1515
1516config CPU_MIPSR2_IRQ_VI
1517 bool "Vectored interrupt mode"
1518 help
1519 Vectored interrupt mode allowing faster dispatching of interrupts.
1520 The board support code needs to be written to take advantage of this
1521 mode. Compatibility code is included to allow the kernel to run on
1522 a CPU that does not support vectored interrupts. It's safe to
1523 say Y here.
1524
1525config CPU_MIPSR2_IRQ_EI
1526 bool "External interrupt controller mode"
1527 help
1528 Extended interrupt mode takes advantage of an external interrupt
1529 controller to allow fast dispatching from many possible interrupt
1530 sources. Say N unless you know that external interrupt support is
1531 required.
1532
1533config CPU_MIPSR2_SRS
1534 bool "Make shadow set registers available for interrupt handlers"
1535 depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI
1536 help
1537 Allow the kernel to use shadow register sets for fast interrupts.
1538 Interrupt handlers must be specially written to use shadow sets.
1539 Say N unless you know that shadow register set upport is needed.
1540endmenu
1541
1480config CPU_HAS_SYNC 1542config CPU_HAS_SYNC
1481 bool 1543 bool
1482 depends on !CPU_R3000 1544 depends on !CPU_R3000
1483 default y 1545 default y
1484 1546
1485# 1547#
1548# Use the generic interrupt handling code in kernel/irq/:
1549#
1550config GENERIC_HARDIRQS
1551 bool
1552 default y
1553
1554config GENERIC_IRQ_PROBE
1555 bool
1556 default y
1557
1558#
1486# - Highmem only makes sense for the 32-bit kernel. 1559# - Highmem only makes sense for the 32-bit kernel.
1487# - The current highmem code will only work properly on physically indexed 1560# - The current highmem code will only work properly on physically indexed
1488# caches such as R3000, SB1, R7000 or those that look like they're virtually 1561# caches such as R3000, SB1, R7000 or those that look like they're virtually
@@ -1491,14 +1564,19 @@ config CPU_HAS_SYNC
1491# where it's known to be safe. This will not offer highmem on a few systems 1564# where it's known to be safe. This will not offer highmem on a few systems
1492# such as MIPS32 and MIPS64 CPUs which may have virtual and physically 1565# such as MIPS32 and MIPS64 CPUs which may have virtual and physically
1493# indexed CPUs but we're playing safe. 1566# indexed CPUs but we're playing safe.
1494# - We should not offer highmem for system of which we already know that they 1567# - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
1495# don't have memory configurations that could gain from highmem support in 1568# know they might have memory configurations that could make use of highmem
1496# the kernel because they don't support configurations with RAM at physical 1569# support.
1497# addresses > 0x20000000.
1498# 1570#
1499config HIGHMEM 1571config HIGHMEM
1500 bool "High Memory Support" 1572 bool "High Memory Support"
1501 depends on 32BIT && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX) 1573 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM
1574
1575config CPU_SUPPORTS_HIGHMEM
1576 bool
1577
1578config SYS_SUPPORTS_HIGHMEM
1579 bool
1502 1580
1503config ARCH_FLATMEM_ENABLE 1581config ARCH_FLATMEM_ENABLE
1504 def_bool y 1582 def_bool y
@@ -1508,7 +1586,7 @@ source "mm/Kconfig"
1508 1586
1509config SMP 1587config SMP
1510 bool "Multi-Processing support" 1588 bool "Multi-Processing support"
1511 depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27 1589 depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP
1512 ---help--- 1590 ---help---
1513 This enables support for systems with more than one CPU. If you have 1591 This enables support for systems with more than one CPU. If you have
1514 a system with only one CPU, like most personal computers, say N. If 1592 a system with only one CPU, like most personal computers, say N. If
@@ -1543,14 +1621,7 @@ config NR_CPUS
1543 This is purely to save memory - each supported CPU adds 1621 This is purely to save memory - each supported CPU adds
1544 approximately eight kilobytes to the kernel image. 1622 approximately eight kilobytes to the kernel image.
1545 1623
1546config PREEMPT 1624source "kernel/Kconfig.preempt"
1547 bool "Preemptible Kernel"
1548 help
1549 This option reduces the latency of the kernel when reacting to
1550 real-time or interactive events by allowing a low priority process to
1551 be preempted even if it is in kernel mode executing a system call.
1552 This allows applications to run more reliably even when the system is
1553 under load.
1554 1625
1555config RTC_DS1742 1626config RTC_DS1742
1556 bool "DS1742 BRAM/RTC support" 1627 bool "DS1742 BRAM/RTC support"
@@ -1566,14 +1637,16 @@ config MIPS_INSANE_LARGE
1566 This will result in additional memory usage, so it is not 1637 This will result in additional memory usage, so it is not
1567 recommended for normal users. 1638 recommended for normal users.
1568 1639
1640endmenu
1641
1569config RWSEM_GENERIC_SPINLOCK 1642config RWSEM_GENERIC_SPINLOCK
1570 bool 1643 bool
1571 default y 1644 default y
1572 1645
1573endmenu
1574
1575menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)" 1646menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
1576 1647
1648config HW_HAS_EISA
1649 bool
1577config HW_HAS_PCI 1650config HW_HAS_PCI
1578 bool 1651 bool
1579 1652
@@ -1607,7 +1680,7 @@ config ISA
1607 1680
1608config EISA 1681config EISA
1609 bool "EISA support" 1682 bool "EISA support"
1610 depends on SGI_IP22 || SNI_RM200_PCI 1683 depends on HW_HAS_EISA
1611 select ISA 1684 select ISA
1612 ---help--- 1685 ---help---
1613 The Extended Industry Standard Architecture (EISA) bus was 1686 The Extended Industry Standard Architecture (EISA) bus was
@@ -1641,12 +1714,6 @@ config MMU
1641 bool 1714 bool
1642 default y 1715 default y
1643 1716
1644config MCA
1645 bool
1646
1647config SBUS
1648 bool
1649
1650source "drivers/pcmcia/Kconfig" 1717source "drivers/pcmcia/Kconfig"
1651 1718
1652source "drivers/pci/hotplug/Kconfig" 1719source "drivers/pci/hotplug/Kconfig"
@@ -1659,7 +1726,6 @@ source "fs/Kconfig.binfmt"
1659 1726
1660config TRAD_SIGNALS 1727config TRAD_SIGNALS
1661 bool 1728 bool
1662 default y if 32BIT
1663 1729
1664config BUILD_ELF64 1730config BUILD_ELF64
1665 bool "Use 64-bit ELF format for building" 1731 bool "Use 64-bit ELF format for building"
@@ -1678,7 +1744,7 @@ config BUILD_ELF64
1678 1744
1679config BINFMT_IRIX 1745config BINFMT_IRIX
1680 bool "Include IRIX binary compatibility" 1746 bool "Include IRIX binary compatibility"
1681 depends on !CPU_LITTLE_ENDIAN && 32BIT && BROKEN 1747 depends on CPU_BIG_ENDIAN && 32BIT && BROKEN
1682 1748
1683config MIPS32_COMPAT 1749config MIPS32_COMPAT
1684 bool "Kernel support for Linux/MIPS 32-bit binary compatibility" 1750 bool "Kernel support for Linux/MIPS 32-bit binary compatibility"
@@ -1718,9 +1784,26 @@ config BINFMT_ELF32
1718 bool 1784 bool
1719 default y if MIPS32_O32 || MIPS32_N32 1785 default y if MIPS32_O32 || MIPS32_N32
1720 1786
1787config SECCOMP
1788 bool "Enable seccomp to safely compute untrusted bytecode"
1789 depends on PROC_FS && BROKEN
1790 default y
1791 help
1792 This kernel feature is useful for number crunching applications
1793 that may need to compute untrusted bytecode during their
1794 execution. By using pipes or other transports made available to
1795 the process as file descriptors supporting the read/write
1796 syscalls, it's possible to isolate those applications in
1797 their own address space using seccomp. Once seccomp is
1798 enabled via /proc/<pid>/seccomp, it cannot be disabled
1799 and the task is only allowed to execute a few safe syscalls
1800 defined by each seccomp mode.
1801
1802 If unsure, say Y. Only embedded should say N here.
1803
1721config PM 1804config PM
1722 bool "Power Management support (EXPERIMENTAL)" 1805 bool "Power Management support (EXPERIMENTAL)"
1723 depends on EXPERIMENTAL && MACH_AU1X00 1806 depends on EXPERIMENTAL && SOC_AU1X00
1724 1807
1725endmenu 1808endmenu
1726 1809
@@ -1730,6 +1813,8 @@ source "drivers/Kconfig"
1730 1813
1731source "fs/Kconfig" 1814source "fs/Kconfig"
1732 1815
1816source "arch/mips/oprofile/Kconfig"
1817
1733source "arch/mips/Kconfig.debug" 1818source "arch/mips/Kconfig.debug"
1734 1819
1735source "security/Kconfig" 1820source "security/Kconfig"
@@ -1737,18 +1822,3 @@ source "security/Kconfig"
1737source "crypto/Kconfig" 1822source "crypto/Kconfig"
1738 1823
1739source "lib/Kconfig" 1824source "lib/Kconfig"
1740
1741#
1742# Use the generic interrupt handling code in kernel/irq/:
1743#
1744config GENERIC_HARDIRQS
1745 bool
1746 default y
1747
1748config GENERIC_IRQ_PROBE
1749 bool
1750 default y
1751
1752config ISA_DMA_API
1753 bool
1754 default y
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 346e803f153b..02692027730a 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -52,6 +52,21 @@ ifdef CONFIG_CROSSCOMPILE
52CROSS_COMPILE := $(tool-prefix) 52CROSS_COMPILE := $(tool-prefix)
53endif 53endif
54 54
55CHECKFLAGS-y += -D__linux__ -D__mips__ \
56 -D_ABIO32=1 \
57 -D_ABIN32=2 \
58 -D_ABI64=3
59CHECKFLAGS-$(CONFIG_32BIT) += -D_MIPS_SIM=_ABIO32 \
60 -D_MIPS_SZLONG=32 \
61 -D__PTRDIFF_TYPE__=int
62CHECKFLAGS-$(CONFIG_64BIT) += -m64 -D_MIPS_SIM=_ABI64 \
63 -D_MIPS_SZLONG=64 \
64 -D__PTRDIFF_TYPE__="long int"
65CHECKFLAGS-$(CONFIG_CPU_BIG_ENDIAN) += -D__MIPSEB__
66CHECKFLAGS-$(CONFIG_CPU_LITTLE_ENDIAN) += -D__MIPSEL__
67
68CHECKFLAGS = $(CHECKFLAGS-y)
69
55ifdef CONFIG_BUILD_ELF64 70ifdef CONFIG_BUILD_ELF64
56gas-abi = 64 71gas-abi = 64
57ld-emul = $(64bit-emul) 72ld-emul = $(64bit-emul)
@@ -79,9 +94,18 @@ endif
79cflags-y += -I $(TOPDIR)/include/asm/gcc 94cflags-y += -I $(TOPDIR)/include/asm/gcc
80cflags-y += -G 0 -mno-abicalls -fno-pic -pipe 95cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
81cflags-y += $(call cc-option, -finline-limit=100000) 96cflags-y += $(call cc-option, -finline-limit=100000)
82LDFLAGS_vmlinux += -G 0 -static -n 97LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
83MODFLAGS += -mlong-calls 98MODFLAGS += -mlong-calls
84 99
100#
101# We explicitly add the endianness specifier if needed, this allows
102# to compile kernels with a toolchain for the other endianness. We
103# carefully avoid to add it redundantly because gcc 3.3/3.4 complains
104# when fed the toolchain default!
105#
106cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB)
107cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL)
108
85cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer 109cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer
86 110
87# 111#
@@ -167,14 +191,22 @@ cflags-$(CONFIG_CPU_TX49XX) += \
167 $(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \ 191 $(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \
168 -Wa,--trap 192 -Wa,--trap
169 193
170cflags-$(CONFIG_CPU_MIPS32) += \ 194cflags-$(CONFIG_CPU_MIPS32_R1) += \
171 $(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \ 195 $(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \
172 -Wa,--trap 196 -Wa,--trap
173 197
174cflags-$(CONFIG_CPU_MIPS64) += \ 198cflags-$(CONFIG_CPU_MIPS32_R2) += \
199 $(call set_gccflags,mips32r2,mips32r2,r4600,mips3,mips2) \
200 -Wa,--trap
201
202cflags-$(CONFIG_CPU_MIPS64_R1) += \
175 $(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \ 203 $(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \
176 -Wa,--trap 204 -Wa,--trap
177 205
206cflags-$(CONFIG_CPU_MIPS64_R2) += \
207 $(call set_gccflags,mips64r2,mips64r2,r4600,mips3,mips2) \
208 -Wa,--trap
209
178cflags-$(CONFIG_CPU_R5000) += \ 210cflags-$(CONFIG_CPU_R5000) += \
179 $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \ 211 $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \
180 -Wa,--trap 212 -Wa,--trap
@@ -196,6 +228,7 @@ cflags-$(CONFIG_CPU_RM9000) += \
196 $(call set_gccflags,rm9000,mips4,r5000,mips4,mips2) \ 228 $(call set_gccflags,rm9000,mips4,r5000,mips4,mips2) \
197 -Wa,--trap 229 -Wa,--trap
198 230
231
199cflags-$(CONFIG_CPU_SB1) += \ 232cflags-$(CONFIG_CPU_SB1) += \
200 $(call set_gccflags,sb1,mips64,r5000,mips4,mips2) \ 233 $(call set_gccflags,sb1,mips64,r5000,mips4,mips2) \
201 -Wa,--trap 234 -Wa,--trap
@@ -266,6 +299,13 @@ cflags-$(CONFIG_MIPS_PB1550) += -Iinclude/asm-mips/mach-pb1x00
266load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 299load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
267 300
268# 301#
302# AMD Alchemy Pb1200 eval board
303#
304libs-$(CONFIG_MIPS_PB1200) += arch/mips/au1000/pb1200/
305cflags-$(CONFIG_MIPS_PB1200) += -Iinclude/asm-mips/mach-pb1x00
306load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
307
308#
269# AMD Alchemy Db1000 eval board 309# AMD Alchemy Db1000 eval board
270# 310#
271libs-$(CONFIG_MIPS_DB1000) += arch/mips/au1000/db1x00/ 311libs-$(CONFIG_MIPS_DB1000) += arch/mips/au1000/db1x00/
@@ -294,6 +334,13 @@ cflags-$(CONFIG_MIPS_DB1550) += -Iinclude/asm-mips/mach-db1x00
294load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 334load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
295 335
296# 336#
337# AMD Alchemy Db1200 eval board
338#
339libs-$(CONFIG_MIPS_DB1200) += arch/mips/au1000/pb1200/
340cflags-$(CONFIG_MIPS_DB1200) += -Iinclude/asm-mips/mach-db1x00
341load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
342
343#
297# AMD Alchemy Bosporus eval board 344# AMD Alchemy Bosporus eval board
298# 345#
299libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/au1000/db1x00/ 346libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/au1000/db1x00/
@@ -323,6 +370,7 @@ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
323# Cobalt Server 370# Cobalt Server
324# 371#
325core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/ 372core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
373cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/cobalt
326load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000 374load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
327 375
328# 376#
@@ -389,6 +437,13 @@ core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/
389load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000 437load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000
390 438
391# 439#
440# MIPS SIM
441#
442core-$(CONFIG_MIPS_SIM) += arch/mips/mips-boards/sim/
443cflags-$(CONFIG_MIPS_SIM) += -Iinclude/asm-mips/mach-sim
444load-$(CONFIG_MIPS_SIM) += 0x80100000
445
446#
392# Momentum Ocelot board 447# Momentum Ocelot board
393# 448#
394# The Ocelot setup.o must be linked early - it does the ioremap() for the 449# The Ocelot setup.o must be linked early - it does the ioremap() for the
@@ -514,6 +569,19 @@ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000
514load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 569load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000
515 570
516# 571#
572# Common Philips PNX8550
573#
574core-$(CONFIG_SOC_PNX8550) += arch/mips/philips/pnx8550/common/
575cflags-$(CONFIG_SOC_PNX8550) += -Iinclude/asm-mips/mach-pnx8550
576
577#
578# Philips PNX8550 JBS board
579#
580libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/
581#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550
582load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
583
584#
517# SGI IP22 (Indy/Indigo2) 585# SGI IP22 (Indy/Indigo2)
518# 586#
519# Set the load address to >= 0xffffffff88069000 if you want to leave space for 587# Set the load address to >= 0xffffffff88069000 if you want to leave space for
@@ -582,10 +650,20 @@ load-$(CONFIG_SGI_IP32) += 0xffffffff80004000
582# removed (as happens, even if they have __initcall/module_init) 650# removed (as happens, even if they have __initcall/module_init)
583# 651#
584core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/ 652core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/
585cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte 653cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte \
654 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
586 655
587core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/ 656core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/
588cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte 657cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte \
658 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
659
660core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/bcm1480/
661cflags-$(CONFIG_SIBYTE_BCM1x55) += -Iinclude/asm-mips/mach-sibyte \
662 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
663
664core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/bcm1480/
665cflags-$(CONFIG_SIBYTE_BCM1x80) += -Iinclude/asm-mips/mach-sibyte \
666 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
589 667
590# 668#
591# Sibyte BCM91120x (Carmel) board 669# Sibyte BCM91120x (Carmel) board
@@ -593,6 +671,7 @@ cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte
593# Sibyte BCM91125C (CRhone) board 671# Sibyte BCM91125C (CRhone) board
594# Sibyte BCM91125E (Rhone) board 672# Sibyte BCM91125E (Rhone) board
595# Sibyte SWARM board 673# Sibyte SWARM board
674# Sibyte BCM91x80 (BigSur) board
596# 675#
597libs-$(CONFIG_SIBYTE_CARMEL) += arch/mips/sibyte/swarm/ 676libs-$(CONFIG_SIBYTE_CARMEL) += arch/mips/sibyte/swarm/
598load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000 677load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000
@@ -606,6 +685,8 @@ libs-$(CONFIG_SIBYTE_SENTOSA) += arch/mips/sibyte/swarm/
606load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000 685load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000
607libs-$(CONFIG_SIBYTE_SWARM) += arch/mips/sibyte/swarm/ 686libs-$(CONFIG_SIBYTE_SWARM) += arch/mips/sibyte/swarm/
608load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000 687load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000
688libs-$(CONFIG_SIBYTE_BIGSUR) += arch/mips/sibyte/swarm/
689load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
609 690
610# 691#
611# SNI RM200 PCI 692# SNI RM200 PCI
@@ -629,6 +710,13 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/
629core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ 710core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/
630load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 711load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000
631 712
713#
714# Toshiba RBTX4938 board
715#
716core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/
717core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/
718load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000
719
632cflags-y += -Iinclude/asm-mips/mach-generic 720cflags-y += -Iinclude/asm-mips/mach-generic
633drivers-$(CONFIG_PCI) += arch/mips/pci/ 721drivers-$(CONFIG_PCI) += arch/mips/pci/
634 722
@@ -701,10 +789,29 @@ ifdef CONFIG_BOOT_ELF64
701all: $(vmlinux-64) 789all: $(vmlinux-64)
702endif 790endif
703 791
792ifdef CONFIG_MIPS_ATLAS
793all: vmlinux.srec
794endif
795
796ifdef CONFIG_MIPS_MALTA
797all: vmlinux.srec
798endif
799
800ifdef CONFIG_MIPS_SEAD
801all: vmlinux.srec
802endif
803
804ifdef CONFIG_QEMU
805all: vmlinux.bin
806endif
807
704ifdef CONFIG_SNI_RM200_PCI 808ifdef CONFIG_SNI_RM200_PCI
705all: vmlinux.ecoff 809all: vmlinux.ecoff
706endif 810endif
707 811
812vmlinux.bin: $(vmlinux-32)
813 +@$(call makeboot,$@)
814
708vmlinux.ecoff vmlinux.rm200: $(vmlinux-32) 815vmlinux.ecoff vmlinux.rm200: $(vmlinux-32)
709 +@$(call makeboot,$@) 816 +@$(call makeboot,$@)
710 817
@@ -720,7 +827,6 @@ archclean:
720 @$(MAKE) $(clean)=arch/mips/boot 827 @$(MAKE) $(clean)=arch/mips/boot
721 @$(MAKE) $(clean)=arch/mips/lasat 828 @$(MAKE) $(clean)=arch/mips/lasat
722 829
723
724CLEAN_FILES += vmlinux.32 \ 830CLEAN_FILES += vmlinux.32 \
725 vmlinux.64 \ 831 vmlinux.64 \
726 vmlinux.ecoff 832 vmlinux.ecoff
diff --git a/arch/mips/arc/Makefile b/arch/mips/arc/Makefile
index e8424932e1a3..4f349ec1ea2d 100644
--- a/arch/mips/arc/Makefile
+++ b/arch/mips/arc/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5lib-y += cmdline.o env.o file.o identify.o init.o \ 5lib-y += cmdline.o env.o file.o identify.o init.o \
6 misc.o time.o tree.o 6 misc.o salone.o time.o tree.o
7 7
8lib-$(CONFIG_ARC_MEMORY) += memory.o 8lib-$(CONFIG_ARC_MEMORY) += memory.o
9lib-$(CONFIG_ARC_CONSOLE) += arc_con.o 9lib-$(CONFIG_ARC_CONSOLE) += arc_con.o
diff --git a/arch/mips/arc/identify.c b/arch/mips/arc/identify.c
index 0dd7a345eb79..1bd6199e174a 100644
--- a/arch/mips/arc/identify.c
+++ b/arch/mips/arc/identify.c
@@ -44,6 +44,11 @@ static struct smatch mach_table[] = {
44 MACH_GROUP_SGI, 44 MACH_GROUP_SGI,
45 MACH_SGI_IP28, 45 MACH_SGI_IP28,
46 PROM_FLAG_ARCS 46 PROM_FLAG_ARCS
47 }, { "SGI-IP30",
48 "SGI Octane",
49 MACH_GROUP_SGI,
50 MACH_SGI_IP30,
51 PROM_FLAG_ARCS
47 }, { "SGI-IP32", 52 }, { "SGI-IP32",
48 "SGI O2", 53 "SGI O2",
49 MACH_GROUP_SGI, 54 MACH_GROUP_SGI,
diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile
index 594b75e5e080..a1edfd1f643c 100644
--- a/arch/mips/au1000/common/Makefile
+++ b/arch/mips/au1000/common/Makefile
@@ -8,7 +8,7 @@
8 8
9obj-y += prom.o int-handler.o irq.o puts.o time.o reset.o \ 9obj-y += prom.o int-handler.o irq.o puts.o time.o reset.o \
10 au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ 10 au1xxx_irqmap.o clocks.o platform.o power.o setup.o \
11 sleeper.o cputable.o dma.o dbdma.o 11 sleeper.o cputable.o dma.o dbdma.o gpio.o
12 12
13obj-$(CONFIG_AU1X00_USB_DEVICE) += usbdev.o 13obj-$(CONFIG_AU1X00_USB_DEVICE) += usbdev.o
14obj-$(CONFIG_KGDB) += dbg_io.o 14obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/au1000/common/au1xxx_irqmap.c b/arch/mips/au1000/common/au1xxx_irqmap.c
index 8a0f39f67c59..0b2c03c52319 100644
--- a/arch/mips/au1000/common/au1xxx_irqmap.c
+++ b/arch/mips/au1000/common/au1xxx_irqmap.c
@@ -173,14 +173,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = {
173 { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, 173 { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
174 { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0}, 174 { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0},
175 { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0}, 175 { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0},
176 { AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 }, 176 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
177 { AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 177 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
178 { AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 178 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
179 { AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, 179 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
180 { AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 }, 180 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
181 { AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 181 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
182 { AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 182 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
183 { AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, 183 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
184 { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0}, 184 { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0},
185 { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, 185 { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
186 { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, 186 { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
@@ -201,14 +201,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = {
201 { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, 201 { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
202 { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0}, 202 { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0},
203 { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0}, 203 { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0},
204 { AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 }, 204 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
205 { AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 205 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
206 { AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 206 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
207 { AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, 207 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
208 { AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 }, 208 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
209 { AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 209 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
210 { AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 210 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
211 { AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, 211 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
212 { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0}, 212 { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0},
213 { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, 213 { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
214 { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0}, 214 { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/au1000/common/cputable.c
index f5521dfccfd6..4dbde82c8215 100644
--- a/arch/mips/au1000/common/cputable.c
+++ b/arch/mips/au1000/common/cputable.c
@@ -37,7 +37,8 @@ struct cpu_spec cpu_specs[] = {
37 { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 }, 37 { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
38 { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 }, 38 { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
39 { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 }, 39 { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
40 { 0xffffffff, 0x04030200, "Au1200 AA", 0, 1 }, 40 { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 },
41 { 0xffffffff, 0x04030201, "Au1200 AC", 0, 1 },
41 { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 }, 42 { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
42}; 43};
43 44
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c
index adfc3172aace..d00e8247d6c2 100644
--- a/arch/mips/au1000/common/dbdma.c
+++ b/arch/mips/au1000/common/dbdma.c
@@ -29,6 +29,7 @@
29 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 * 30 *
31 */ 31 */
32
32#include <linux/config.h> 33#include <linux/config.h>
33#include <linux/kernel.h> 34#include <linux/kernel.h>
34#include <linux/errno.h> 35#include <linux/errno.h>
@@ -38,10 +39,12 @@
38#include <linux/string.h> 39#include <linux/string.h>
39#include <linux/delay.h> 40#include <linux/delay.h>
40#include <linux/interrupt.h> 41#include <linux/interrupt.h>
42#include <linux/module.h>
41#include <asm/mach-au1x00/au1000.h> 43#include <asm/mach-au1x00/au1000.h>
42#include <asm/mach-au1x00/au1xxx_dbdma.h> 44#include <asm/mach-au1x00/au1xxx_dbdma.h>
43#include <asm/system.h> 45#include <asm/system.h>
44 46
47
45#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 48#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
46 49
47/* 50/*
@@ -61,37 +64,10 @@ static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
61*/ 64*/
62#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) 65#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
63 66
64static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; 67static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
65static int dbdma_initialized; 68static int dbdma_initialized=0;
66static void au1xxx_dbdma_init(void); 69static void au1xxx_dbdma_init(void);
67 70
68typedef struct dbdma_device_table {
69 u32 dev_id;
70 u32 dev_flags;
71 u32 dev_tsize;
72 u32 dev_devwidth;
73 u32 dev_physaddr; /* If FIFO */
74 u32 dev_intlevel;
75 u32 dev_intpolarity;
76} dbdev_tab_t;
77
78typedef struct dbdma_chan_config {
79 u32 chan_flags;
80 u32 chan_index;
81 dbdev_tab_t *chan_src;
82 dbdev_tab_t *chan_dest;
83 au1x_dma_chan_t *chan_ptr;
84 au1x_ddma_desc_t *chan_desc_base;
85 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
86 void *chan_callparam;
87 void (*chan_callback)(int, void *, struct pt_regs *);
88} chan_tab_t;
89
90#define DEV_FLAGS_INUSE (1 << 0)
91#define DEV_FLAGS_ANYUSE (1 << 1)
92#define DEV_FLAGS_OUT (1 << 2)
93#define DEV_FLAGS_IN (1 << 3)
94
95static dbdev_tab_t dbdev_tab[] = { 71static dbdev_tab_t dbdev_tab[] = {
96#ifdef CONFIG_SOC_AU1550 72#ifdef CONFIG_SOC_AU1550
97 /* UARTS */ 73 /* UARTS */
@@ -157,25 +133,25 @@ static dbdev_tab_t dbdev_tab[] = {
157 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 133 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
158 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 134 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
159 135
160 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, 136 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
161 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 137 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
162 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, 138 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
163 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 139 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
164 140
165 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, 141 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
166 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 142 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
167 143
168 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, 144 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
169 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, 145 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
170 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 146 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
171 147
172 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, 148 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
173 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, 149 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
174 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 150 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
175 151
176 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 152 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
177 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 153 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
178 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 154 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
179 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 155 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
180 156
181 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 157 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
@@ -184,6 +160,24 @@ static dbdev_tab_t dbdev_tab[] = {
184 160
185 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 161 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
186 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 162 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
163
164 /* Provide 16 user definable device types */
165 { 0, 0, 0, 0, 0, 0, 0 },
166 { 0, 0, 0, 0, 0, 0, 0 },
167 { 0, 0, 0, 0, 0, 0, 0 },
168 { 0, 0, 0, 0, 0, 0, 0 },
169 { 0, 0, 0, 0, 0, 0, 0 },
170 { 0, 0, 0, 0, 0, 0, 0 },
171 { 0, 0, 0, 0, 0, 0, 0 },
172 { 0, 0, 0, 0, 0, 0, 0 },
173 { 0, 0, 0, 0, 0, 0, 0 },
174 { 0, 0, 0, 0, 0, 0, 0 },
175 { 0, 0, 0, 0, 0, 0, 0 },
176 { 0, 0, 0, 0, 0, 0, 0 },
177 { 0, 0, 0, 0, 0, 0, 0 },
178 { 0, 0, 0, 0, 0, 0, 0 },
179 { 0, 0, 0, 0, 0, 0, 0 },
180 { 0, 0, 0, 0, 0, 0, 0 },
187}; 181};
188 182
189#define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t)) 183#define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
@@ -203,6 +197,36 @@ find_dbdev_id (u32 id)
203 return NULL; 197 return NULL;
204} 198}
205 199
200void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
201{
202 return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
203}
204EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
205
206u32
207au1xxx_ddma_add_device(dbdev_tab_t *dev)
208{
209 u32 ret = 0;
210 dbdev_tab_t *p=NULL;
211 static u16 new_id=0x1000;
212
213 p = find_dbdev_id(0);
214 if ( NULL != p )
215 {
216 memcpy(p, dev, sizeof(dbdev_tab_t));
217 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
218 ret = p->dev_id;
219 new_id++;
220#if 0
221 printk("add_device: id:%x flags:%x padd:%x\n",
222 p->dev_id, p->dev_flags, p->dev_physaddr );
223#endif
224 }
225
226 return ret;
227}
228EXPORT_SYMBOL(au1xxx_ddma_add_device);
229
206/* Allocate a channel and return a non-zero descriptor if successful. 230/* Allocate a channel and return a non-zero descriptor if successful.
207*/ 231*/
208u32 232u32
@@ -215,7 +239,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
215 int i; 239 int i;
216 dbdev_tab_t *stp, *dtp; 240 dbdev_tab_t *stp, *dtp;
217 chan_tab_t *ctp; 241 chan_tab_t *ctp;
218 volatile au1x_dma_chan_t *cp; 242 au1x_dma_chan_t *cp;
219 243
220 /* We do the intialization on the first channel allocation. 244 /* We do the intialization on the first channel allocation.
221 * We have to wait because of the interrupt handler initialization 245 * We have to wait because of the interrupt handler initialization
@@ -225,9 +249,6 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
225 au1xxx_dbdma_init(); 249 au1xxx_dbdma_init();
226 dbdma_initialized = 1; 250 dbdma_initialized = 1;
227 251
228 if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS))
229 return 0;
230
231 if ((stp = find_dbdev_id(srcid)) == NULL) return 0; 252 if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
232 if ((dtp = find_dbdev_id(destid)) == NULL) return 0; 253 if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
233 254
@@ -271,7 +292,6 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
271 */ 292 */
272 ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL); 293 ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
273 chan_tab_ptr[i] = ctp; 294 chan_tab_ptr[i] = ctp;
274 ctp->chan_index = chan = i;
275 break; 295 break;
276 } 296 }
277 } 297 }
@@ -279,10 +299,11 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
279 299
280 if (ctp != NULL) { 300 if (ctp != NULL) {
281 memset(ctp, 0, sizeof(chan_tab_t)); 301 memset(ctp, 0, sizeof(chan_tab_t));
302 ctp->chan_index = chan = i;
282 dcp = DDMA_CHANNEL_BASE; 303 dcp = DDMA_CHANNEL_BASE;
283 dcp += (0x0100 * chan); 304 dcp += (0x0100 * chan);
284 ctp->chan_ptr = (au1x_dma_chan_t *)dcp; 305 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
285 cp = (volatile au1x_dma_chan_t *)dcp; 306 cp = (au1x_dma_chan_t *)dcp;
286 ctp->chan_src = stp; 307 ctp->chan_src = stp;
287 ctp->chan_dest = dtp; 308 ctp->chan_dest = dtp;
288 ctp->chan_callback = callback; 309 ctp->chan_callback = callback;
@@ -299,6 +320,9 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
299 i |= DDMA_CFG_DED; 320 i |= DDMA_CFG_DED;
300 if (dtp->dev_intpolarity) 321 if (dtp->dev_intpolarity)
301 i |= DDMA_CFG_DP; 322 i |= DDMA_CFG_DP;
323 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
324 (dtp->dev_flags & DEV_FLAGS_SYNC))
325 i |= DDMA_CFG_SYNC;
302 cp->ddma_cfg = i; 326 cp->ddma_cfg = i;
303 au_sync(); 327 au_sync();
304 328
@@ -309,14 +333,14 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
309 rv = (u32)(&chan_tab_ptr[chan]); 333 rv = (u32)(&chan_tab_ptr[chan]);
310 } 334 }
311 else { 335 else {
312 /* Release devices. 336 /* Release devices */
313 */
314 stp->dev_flags &= ~DEV_FLAGS_INUSE; 337 stp->dev_flags &= ~DEV_FLAGS_INUSE;
315 dtp->dev_flags &= ~DEV_FLAGS_INUSE; 338 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
316 } 339 }
317 } 340 }
318 return rv; 341 return rv;
319} 342}
343EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
320 344
321/* Set the device width if source or destination is a FIFO. 345/* Set the device width if source or destination is a FIFO.
322 * Should be 8, 16, or 32 bits. 346 * Should be 8, 16, or 32 bits.
@@ -344,6 +368,7 @@ au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
344 368
345 return rv; 369 return rv;
346} 370}
371EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
347 372
348/* Allocate a descriptor ring, initializing as much as possible. 373/* Allocate a descriptor ring, initializing as much as possible.
349*/ 374*/
@@ -370,7 +395,8 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
370 * and if we try that first we are likely to not waste larger 395 * and if we try that first we are likely to not waste larger
371 * slabs of memory. 396 * slabs of memory.
372 */ 397 */
373 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL); 398 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
399 GFP_KERNEL|GFP_DMA);
374 if (desc_base == 0) 400 if (desc_base == 0)
375 return 0; 401 return 0;
376 402
@@ -381,7 +407,7 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
381 kfree((const void *)desc_base); 407 kfree((const void *)desc_base);
382 i = entries * sizeof(au1x_ddma_desc_t); 408 i = entries * sizeof(au1x_ddma_desc_t);
383 i += (sizeof(au1x_ddma_desc_t) - 1); 409 i += (sizeof(au1x_ddma_desc_t) - 1);
384 if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0) 410 if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
385 return 0; 411 return 0;
386 412
387 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); 413 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
@@ -403,7 +429,13 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
403 cmd0 |= DSCR_CMD0_SID(srcid); 429 cmd0 |= DSCR_CMD0_SID(srcid);
404 cmd0 |= DSCR_CMD0_DID(destid); 430 cmd0 |= DSCR_CMD0_DID(destid);
405 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV; 431 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
406 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_CURRENT); 432 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
433
434 /* is it mem to mem transfer? */
435 if(((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
436 ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) {
437 cmd0 |= DSCR_CMD0_MEM;
438 }
407 439
408 switch (stp->dev_devwidth) { 440 switch (stp->dev_devwidth) {
409 case 8: 441 case 8:
@@ -461,9 +493,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
461 /* If source input is fifo, set static address. 493 /* If source input is fifo, set static address.
462 */ 494 */
463 if (stp->dev_flags & DEV_FLAGS_IN) { 495 if (stp->dev_flags & DEV_FLAGS_IN) {
464 src0 = stp->dev_physaddr; 496 if ( stp->dev_flags & DEV_FLAGS_BURSTABLE )
497 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
498 else
465 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); 499 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
500
466 } 501 }
502 if (stp->dev_physaddr)
503 src0 = stp->dev_physaddr;
467 504
468 /* Set up dest1. For now, assume no stride and increment. 505 /* Set up dest1. For now, assume no stride and increment.
469 * A channel attribute update can change this later. 506 * A channel attribute update can change this later.
@@ -487,10 +524,18 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
487 /* If destination output is fifo, set static address. 524 /* If destination output is fifo, set static address.
488 */ 525 */
489 if (dtp->dev_flags & DEV_FLAGS_OUT) { 526 if (dtp->dev_flags & DEV_FLAGS_OUT) {
490 dest0 = dtp->dev_physaddr; 527 if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
528 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
529 else
491 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); 530 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
492 } 531 }
532 if (dtp->dev_physaddr)
533 dest0 = dtp->dev_physaddr;
493 534
535#if 0
536 printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
537 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 );
538#endif
494 for (i=0; i<entries; i++) { 539 for (i=0; i<entries; i++) {
495 dp->dscr_cmd0 = cmd0; 540 dp->dscr_cmd0 = cmd0;
496 dp->dscr_cmd1 = cmd1; 541 dp->dscr_cmd1 = cmd1;
@@ -499,6 +544,8 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
499 dp->dscr_dest0 = dest0; 544 dp->dscr_dest0 = dest0;
500 dp->dscr_dest1 = dest1; 545 dp->dscr_dest1 = dest1;
501 dp->dscr_stat = 0; 546 dp->dscr_stat = 0;
547 dp->sw_context = 0;
548 dp->sw_status = 0;
502 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1)); 549 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
503 dp++; 550 dp++;
504 } 551 }
@@ -511,13 +558,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
511 558
512 return (u32)(ctp->chan_desc_base); 559 return (u32)(ctp->chan_desc_base);
513} 560}
561EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
514 562
515/* Put a source buffer into the DMA ring. 563/* Put a source buffer into the DMA ring.
516 * This updates the source pointer and byte count. Normally used 564 * This updates the source pointer and byte count. Normally used
517 * for memory to fifo transfers. 565 * for memory to fifo transfers.
518 */ 566 */
519u32 567u32
520au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes) 568_au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
521{ 569{
522 chan_tab_t *ctp; 570 chan_tab_t *ctp;
523 au1x_ddma_desc_t *dp; 571 au1x_ddma_desc_t *dp;
@@ -544,8 +592,24 @@ au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
544 */ 592 */
545 dp->dscr_source0 = virt_to_phys(buf); 593 dp->dscr_source0 = virt_to_phys(buf);
546 dp->dscr_cmd1 = nbytes; 594 dp->dscr_cmd1 = nbytes;
547 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 595 /* Check flags */
548 ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */ 596 if (flags & DDMA_FLAGS_IE)
597 dp->dscr_cmd0 |= DSCR_CMD0_IE;
598 if (flags & DDMA_FLAGS_NOIE)
599 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
600
601 /*
602 * There is an errata on the Au1200/Au1550 parts that could result
603 * in "stale" data being DMA'd. It has to do with the snoop logic on
604 * the dache eviction buffer. NONCOHERENT_IO is on by default for
605 * these parts. If it is fixedin the future, these dma_cache_inv will
606 * just be nothing more than empty macros. See io.h.
607 * */
608 dma_cache_wback_inv((unsigned long)buf, nbytes);
609 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
610 au_sync();
611 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
612 ctp->chan_ptr->ddma_dbell = 0;
549 613
550 /* Get next descriptor pointer. 614 /* Get next descriptor pointer.
551 */ 615 */
@@ -555,13 +619,14 @@ au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
555 */ 619 */
556 return nbytes; 620 return nbytes;
557} 621}
622EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
558 623
559/* Put a destination buffer into the DMA ring. 624/* Put a destination buffer into the DMA ring.
560 * This updates the destination pointer and byte count. Normally used 625 * This updates the destination pointer and byte count. Normally used
561 * to place an empty buffer into the ring for fifo to memory transfers. 626 * to place an empty buffer into the ring for fifo to memory transfers.
562 */ 627 */
563u32 628u32
564au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes) 629_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
565{ 630{
566 chan_tab_t *ctp; 631 chan_tab_t *ctp;
567 au1x_ddma_desc_t *dp; 632 au1x_ddma_desc_t *dp;
@@ -583,11 +648,33 @@ au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
583 if (dp->dscr_cmd0 & DSCR_CMD0_V) 648 if (dp->dscr_cmd0 & DSCR_CMD0_V)
584 return 0; 649 return 0;
585 650
586 /* Load up buffer address and byte count. 651 /* Load up buffer address and byte count */
587 */ 652
653 /* Check flags */
654 if (flags & DDMA_FLAGS_IE)
655 dp->dscr_cmd0 |= DSCR_CMD0_IE;
656 if (flags & DDMA_FLAGS_NOIE)
657 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
658
588 dp->dscr_dest0 = virt_to_phys(buf); 659 dp->dscr_dest0 = virt_to_phys(buf);
589 dp->dscr_cmd1 = nbytes; 660 dp->dscr_cmd1 = nbytes;
661#if 0
662 printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
663 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
664 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
665#endif
666 /*
667 * There is an errata on the Au1200/Au1550 parts that could result in
668 * "stale" data being DMA'd. It has to do with the snoop logic on the
669 * dache eviction buffer. NONCOHERENT_IO is on by default for these
670 * parts. If it is fixedin the future, these dma_cache_inv will just
671 * be nothing more than empty macros. See io.h.
672 * */
673 dma_cache_inv((unsigned long)buf,nbytes);
590 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 674 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
675 au_sync();
676 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
677 ctp->chan_ptr->ddma_dbell = 0;
591 678
592 /* Get next descriptor pointer. 679 /* Get next descriptor pointer.
593 */ 680 */
@@ -597,6 +684,7 @@ au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
597 */ 684 */
598 return nbytes; 685 return nbytes;
599} 686}
687EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
600 688
601/* Get a destination buffer into the DMA ring. 689/* Get a destination buffer into the DMA ring.
602 * Normally used to get a full buffer from the ring during fifo 690 * Normally used to get a full buffer from the ring during fifo
@@ -646,7 +734,7 @@ void
646au1xxx_dbdma_stop(u32 chanid) 734au1xxx_dbdma_stop(u32 chanid)
647{ 735{
648 chan_tab_t *ctp; 736 chan_tab_t *ctp;
649 volatile au1x_dma_chan_t *cp; 737 au1x_dma_chan_t *cp;
650 int halt_timeout = 0; 738 int halt_timeout = 0;
651 739
652 ctp = *((chan_tab_t **)chanid); 740 ctp = *((chan_tab_t **)chanid);
@@ -666,6 +754,7 @@ au1xxx_dbdma_stop(u32 chanid)
666 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); 754 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
667 au_sync(); 755 au_sync();
668} 756}
757EXPORT_SYMBOL(au1xxx_dbdma_stop);
669 758
670/* Start using the current descriptor pointer. If the dbdma encounters 759/* Start using the current descriptor pointer. If the dbdma encounters
671 * a not valid descriptor, it will stop. In this case, we can just 760 * a not valid descriptor, it will stop. In this case, we can just
@@ -675,17 +764,17 @@ void
675au1xxx_dbdma_start(u32 chanid) 764au1xxx_dbdma_start(u32 chanid)
676{ 765{
677 chan_tab_t *ctp; 766 chan_tab_t *ctp;
678 volatile au1x_dma_chan_t *cp; 767 au1x_dma_chan_t *cp;
679 768
680 ctp = *((chan_tab_t **)chanid); 769 ctp = *((chan_tab_t **)chanid);
681
682 cp = ctp->chan_ptr; 770 cp = ctp->chan_ptr;
683 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); 771 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
684 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ 772 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
685 au_sync(); 773 au_sync();
686 cp->ddma_dbell = 0xffffffff; /* Make it go */ 774 cp->ddma_dbell = 0;
687 au_sync(); 775 au_sync();
688} 776}
777EXPORT_SYMBOL(au1xxx_dbdma_start);
689 778
690void 779void
691au1xxx_dbdma_reset(u32 chanid) 780au1xxx_dbdma_reset(u32 chanid)
@@ -704,15 +793,21 @@ au1xxx_dbdma_reset(u32 chanid)
704 793
705 do { 794 do {
706 dp->dscr_cmd0 &= ~DSCR_CMD0_V; 795 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
796 /* reset our SW status -- this is used to determine
797 * if a descriptor is in use by upper level SW. Since
798 * posting can reset 'V' bit.
799 */
800 dp->sw_status = 0;
707 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 801 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
708 } while (dp != ctp->chan_desc_base); 802 } while (dp != ctp->chan_desc_base);
709} 803}
804EXPORT_SYMBOL(au1xxx_dbdma_reset);
710 805
711u32 806u32
712au1xxx_get_dma_residue(u32 chanid) 807au1xxx_get_dma_residue(u32 chanid)
713{ 808{
714 chan_tab_t *ctp; 809 chan_tab_t *ctp;
715 volatile au1x_dma_chan_t *cp; 810 au1x_dma_chan_t *cp;
716 u32 rv; 811 u32 rv;
717 812
718 ctp = *((chan_tab_t **)chanid); 813 ctp = *((chan_tab_t **)chanid);
@@ -738,8 +833,7 @@ au1xxx_dbdma_chan_free(u32 chanid)
738 833
739 au1xxx_dbdma_stop(chanid); 834 au1xxx_dbdma_stop(chanid);
740 835
741 if (ctp->chan_desc_base != NULL) 836 kfree((void *)ctp->chan_desc_base);
742 kfree(ctp->chan_desc_base);
743 837
744 stp->dev_flags &= ~DEV_FLAGS_INUSE; 838 stp->dev_flags &= ~DEV_FLAGS_INUSE;
745 dtp->dev_flags &= ~DEV_FLAGS_INUSE; 839 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
@@ -747,15 +841,16 @@ au1xxx_dbdma_chan_free(u32 chanid)
747 841
748 kfree(ctp); 842 kfree(ctp);
749} 843}
844EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
750 845
751static irqreturn_t 846static irqreturn_t
752dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs) 847dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
753{ 848{
754 u32 intstat; 849 u32 intstat;
755 u32 chan_index; 850 u32 chan_index;
756 chan_tab_t *ctp; 851 chan_tab_t *ctp;
757 au1x_ddma_desc_t *dp; 852 au1x_ddma_desc_t *dp;
758 volatile au1x_dma_chan_t *cp; 853 au1x_dma_chan_t *cp;
759 854
760 intstat = dbdma_gptr->ddma_intstat; 855 intstat = dbdma_gptr->ddma_intstat;
761 au_sync(); 856 au_sync();
@@ -774,19 +869,27 @@ dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
774 (ctp->chan_callback)(irq, ctp->chan_callparam, regs); 869 (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
775 870
776 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 871 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
777 872 return IRQ_RETVAL(1);
778 return IRQ_HANDLED;
779} 873}
780 874
781static void 875static void au1xxx_dbdma_init(void)
782au1xxx_dbdma_init(void)
783{ 876{
877 int irq_nr;
878
784 dbdma_gptr->ddma_config = 0; 879 dbdma_gptr->ddma_config = 0;
785 dbdma_gptr->ddma_throttle = 0; 880 dbdma_gptr->ddma_throttle = 0;
786 dbdma_gptr->ddma_inten = 0xffff; 881 dbdma_gptr->ddma_inten = 0xffff;
787 au_sync(); 882 au_sync();
788 883
789 if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT, 884#if defined(CONFIG_SOC_AU1550)
885 irq_nr = AU1550_DDMA_INT;
886#elif defined(CONFIG_SOC_AU1200)
887 irq_nr = AU1200_DDMA_INT;
888#else
889 #error Unknown Au1x00 SOC
890#endif
891
892 if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT,
790 "Au1xxx dbdma", (void *)dbdma_gptr)) 893 "Au1xxx dbdma", (void *)dbdma_gptr))
791 printk("Can't get 1550 dbdma irq"); 894 printk("Can't get 1550 dbdma irq");
792} 895}
@@ -797,7 +900,8 @@ au1xxx_dbdma_dump(u32 chanid)
797 chan_tab_t *ctp; 900 chan_tab_t *ctp;
798 au1x_ddma_desc_t *dp; 901 au1x_ddma_desc_t *dp;
799 dbdev_tab_t *stp, *dtp; 902 dbdev_tab_t *stp, *dtp;
800 volatile au1x_dma_chan_t *cp; 903 au1x_dma_chan_t *cp;
904 u32 i = 0;
801 905
802 ctp = *((chan_tab_t **)chanid); 906 ctp = *((chan_tab_t **)chanid);
803 stp = ctp->chan_src; 907 stp = ctp->chan_src;
@@ -822,15 +926,64 @@ au1xxx_dbdma_dump(u32 chanid)
822 dp = ctp->chan_desc_base; 926 dp = ctp->chan_desc_base;
823 927
824 do { 928 do {
825 printk("dp %08x, cmd0 %08x, cmd1 %08x\n", 929 printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
826 (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); 930 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
827 printk("src0 %08x, src1 %08x, dest0 %08x\n", 931 printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
828 dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0); 932 dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
829 printk("dest1 %08x, stat %08x, nxtptr %08x\n", 933 printk("stat %08x, nxtptr %08x\n",
830 dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr); 934 dp->dscr_stat, dp->dscr_nxtptr);
831 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 935 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
832 } while (dp != ctp->chan_desc_base); 936 } while (dp != ctp->chan_desc_base);
833} 937}
834 938
939/* Put a descriptor into the DMA ring.
940 * This updates the source/destination pointers and byte count.
941 */
942u32
943au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
944{
945 chan_tab_t *ctp;
946 au1x_ddma_desc_t *dp;
947 u32 nbytes=0;
948
949 /* I guess we could check this to be within the
950 * range of the table......
951 */
952 ctp = *((chan_tab_t **)chanid);
953
954 /* We should have multiple callers for a particular channel,
955 * an interrupt doesn't affect this pointer nor the descriptor,
956 * so no locking should be needed.
957 */
958 dp = ctp->put_ptr;
959
960 /* If the descriptor is valid, we are way ahead of the DMA
961 * engine, so just return an error condition.
962 */
963 if (dp->dscr_cmd0 & DSCR_CMD0_V)
964 return 0;
965
966 /* Load up buffer addresses and byte count.
967 */
968 dp->dscr_dest0 = dscr->dscr_dest0;
969 dp->dscr_source0 = dscr->dscr_source0;
970 dp->dscr_dest1 = dscr->dscr_dest1;
971 dp->dscr_source1 = dscr->dscr_source1;
972 dp->dscr_cmd1 = dscr->dscr_cmd1;
973 nbytes = dscr->dscr_cmd1;
974 /* Allow the caller to specifiy if an interrupt is generated */
975 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
976 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
977 ctp->chan_ptr->ddma_dbell = 0;
978
979 /* Get next descriptor pointer.
980 */
981 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
982
983 /* return something not zero.
984 */
985 return nbytes;
986}
987
835#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ 988#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
836 989
diff --git a/arch/mips/au1000/common/dma.c b/arch/mips/au1000/common/dma.c
index 372c33f1353d..1905c6b104f2 100644
--- a/arch/mips/au1000/common/dma.c
+++ b/arch/mips/au1000/common/dma.c
@@ -39,7 +39,6 @@
39#include <linux/string.h> 39#include <linux/string.h>
40#include <linux/delay.h> 40#include <linux/delay.h>
41#include <linux/interrupt.h> 41#include <linux/interrupt.h>
42#include <linux/module.h>
43#include <asm/system.h> 42#include <asm/system.h>
44#include <asm/mach-au1x00/au1000.h> 43#include <asm/mach-au1x00/au1000.h>
45#include <asm/mach-au1x00/au1000_dma.h> 44#include <asm/mach-au1x00/au1000_dma.h>
diff --git a/arch/mips/au1000/common/gpio.c b/arch/mips/au1000/common/gpio.c
new file mode 100644
index 000000000000..5f5915b83142
--- /dev/null
+++ b/arch/mips/au1000/common/gpio.c
@@ -0,0 +1,119 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22#include <linux/config.h>
23#include <linux/module.h>
24#include <au1000.h>
25#include <au1xxx_gpio.h>
26
27#define gpio1 sys
28#if !defined(CONFIG_SOC_AU1000)
29static AU1X00_GPIO2 * const gpio2 = (AU1X00_GPIO2 *)GPIO2_BASE;
30
31#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
32
33int au1xxx_gpio2_read(int signal)
34{
35 signal -= 200;
36/* gpio2->dir &= ~(0x01 << signal); //Set GPIO to input */
37 return ((gpio2->pinstate >> signal) & 0x01);
38}
39
40void au1xxx_gpio2_write(int signal, int value)
41{
42 signal -= 200;
43
44 gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << signal) |
45 (value << signal);
46}
47
48void au1xxx_gpio2_tristate(int signal)
49{
50 signal -= 200;
51 gpio2->dir &= ~(0x01 << signal); /* Set GPIO to input */
52}
53#endif
54
55int au1xxx_gpio1_read(int signal)
56{
57/* gpio1->trioutclr |= (0x01 << signal); */
58 return ((gpio1->pinstaterd >> signal) & 0x01);
59}
60
61void au1xxx_gpio1_write(int signal, int value)
62{
63 if(value)
64 gpio1->outputset = (0x01 << signal);
65 else
66 gpio1->outputclr = (0x01 << signal); /* Output a Zero */
67}
68
69void au1xxx_gpio1_tristate(int signal)
70{
71 gpio1->trioutclr = (0x01 << signal); /* Tristate signal */
72}
73
74
75int au1xxx_gpio_read(int signal)
76{
77 if(signal >= 200)
78#if defined(CONFIG_SOC_AU1000)
79 return 0;
80#else
81 return au1xxx_gpio2_read(signal);
82#endif
83 else
84 return au1xxx_gpio1_read(signal);
85}
86
87void au1xxx_gpio_write(int signal, int value)
88{
89 if(signal >= 200)
90#if defined(CONFIG_SOC_AU1000)
91 ;
92#else
93 au1xxx_gpio2_write(signal, value);
94#endif
95 else
96 au1xxx_gpio1_write(signal, value);
97}
98
99void au1xxx_gpio_tristate(int signal)
100{
101 if(signal >= 200)
102#if defined(CONFIG_SOC_AU1000)
103 ;
104#else
105 au1xxx_gpio2_tristate(signal);
106#endif
107 else
108 au1xxx_gpio1_tristate(signal);
109}
110
111void au1xxx_gpio1_set_inputs(void)
112{
113 gpio1->pininputen = 0;
114}
115
116EXPORT_SYMBOL(au1xxx_gpio1_set_inputs);
117EXPORT_SYMBOL(au1xxx_gpio_tristate);
118EXPORT_SYMBOL(au1xxx_gpio_write);
119EXPORT_SYMBOL(au1xxx_gpio_read);
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index d1eb5a4a9a19..1339a0979f66 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -83,7 +83,7 @@ inline void local_disable_irq(unsigned int irq_nr);
83void (*board_init_irq)(void); 83void (*board_init_irq)(void);
84 84
85#ifdef CONFIG_PM 85#ifdef CONFIG_PM
86extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs); 86extern irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
87#endif 87#endif
88 88
89static DEFINE_SPINLOCK(irq_lock); 89static DEFINE_SPINLOCK(irq_lock);
@@ -253,52 +253,72 @@ void restore_local_and_enable(int controller, unsigned long mask)
253 253
254 254
255static struct hw_interrupt_type rise_edge_irq_type = { 255static struct hw_interrupt_type rise_edge_irq_type = {
256 "Au1000 Rise Edge", 256 .typename = "Au1000 Rise Edge",
257 startup_irq, 257 .startup = startup_irq,
258 shutdown_irq, 258 .shutdown = shutdown_irq,
259 local_enable_irq, 259 .enable = local_enable_irq,
260 local_disable_irq, 260 .disable = local_disable_irq,
261 mask_and_ack_rise_edge_irq, 261 .ack = mask_and_ack_rise_edge_irq,
262 end_irq, 262 .end = end_irq,
263 NULL
264}; 263};
265 264
266static struct hw_interrupt_type fall_edge_irq_type = { 265static struct hw_interrupt_type fall_edge_irq_type = {
267 "Au1000 Fall Edge", 266 .typename = "Au1000 Fall Edge",
268 startup_irq, 267 .startup = startup_irq,
269 shutdown_irq, 268 .shutdown = shutdown_irq,
270 local_enable_irq, 269 .enable = local_enable_irq,
271 local_disable_irq, 270 .disable = local_disable_irq,
272 mask_and_ack_fall_edge_irq, 271 .ack = mask_and_ack_fall_edge_irq,
273 end_irq, 272 .end = end_irq,
274 NULL
275}; 273};
276 274
277static struct hw_interrupt_type either_edge_irq_type = { 275static struct hw_interrupt_type either_edge_irq_type = {
278 "Au1000 Rise or Fall Edge", 276 .typename = "Au1000 Rise or Fall Edge",
279 startup_irq, 277 .startup = startup_irq,
280 shutdown_irq, 278 .shutdown = shutdown_irq,
281 local_enable_irq, 279 .enable = local_enable_irq,
282 local_disable_irq, 280 .disable = local_disable_irq,
283 mask_and_ack_either_edge_irq, 281 .ack = mask_and_ack_either_edge_irq,
284 end_irq, 282 .end = end_irq,
285 NULL
286}; 283};
287 284
288static struct hw_interrupt_type level_irq_type = { 285static struct hw_interrupt_type level_irq_type = {
289 "Au1000 Level", 286 .typename = "Au1000 Level",
290 startup_irq, 287 .startup = startup_irq,
291 shutdown_irq, 288 .shutdown = shutdown_irq,
292 local_enable_irq, 289 .enable = local_enable_irq,
293 local_disable_irq, 290 .disable = local_disable_irq,
294 mask_and_ack_level_irq, 291 .ack = mask_and_ack_level_irq,
295 end_irq, 292 .end = end_irq,
296 NULL
297}; 293};
298 294
299#ifdef CONFIG_PM 295#ifdef CONFIG_PM
300void startup_match20_interrupt(void) 296void startup_match20_interrupt(irqreturn_t (*handler)(int, void *, struct pt_regs *))
301{ 297{
298 struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
299
300 static struct irqaction action;
301 memset(&action, 0, sizeof(struct irqaction));
302
303 /* This is a big problem.... since we didn't use request_irq
304 * when kernel/irq.c calls probe_irq_xxx this interrupt will
305 * be probed for usage. This will end up disabling the device :(
306 * Give it a bogus "action" pointer -- this will keep it from
307 * getting auto-probed!
308 *
309 * By setting the status to match that of request_irq() we
310 * can avoid it. --cgray
311 */
312 action.dev_id = handler;
313 action.flags = SA_INTERRUPT;
314 cpus_clear(action.mask);
315 action.name = "Au1xxx TOY";
316 action.handler = handler;
317 action.next = NULL;
318
319 desc->action = &action;
320 desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
321
302 local_enable_irq(AU1000_TOY_MATCH2_INT); 322 local_enable_irq(AU1000_TOY_MATCH2_INT);
303} 323}
304#endif 324#endif
@@ -426,7 +446,6 @@ void __init arch_init_irq(void)
426 extern int au1xxx_ic0_nr_irqs; 446 extern int au1xxx_ic0_nr_irqs;
427 447
428 cp0_status = read_c0_status(); 448 cp0_status = read_c0_status();
429 memset(irq_desc, 0, sizeof(irq_desc));
430 set_except_vector(0, au1000_IRQ); 449 set_except_vector(0, au1000_IRQ);
431 450
432 /* Initialize interrupt controllers to a safe state. 451 /* Initialize interrupt controllers to a safe state.
@@ -492,7 +511,7 @@ void intc0_req0_irqdispatch(struct pt_regs *regs)
492 intc0_req0 |= au_readl(IC0_REQ0INT); 511 intc0_req0 |= au_readl(IC0_REQ0INT);
493 512
494 if (!intc0_req0) return; 513 if (!intc0_req0) return;
495 514#ifdef AU1000_USB_DEV_REQ_INT
496 /* 515 /*
497 * Because of the tight timing of SETUP token to reply 516 * Because of the tight timing of SETUP token to reply
498 * transactions, the USB devices-side packet complete 517 * transactions, the USB devices-side packet complete
@@ -503,7 +522,7 @@ void intc0_req0_irqdispatch(struct pt_regs *regs)
503 do_IRQ(AU1000_USB_DEV_REQ_INT, regs); 522 do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
504 return; 523 return;
505 } 524 }
506 525#endif
507 irq = au_ffs(intc0_req0) - 1; 526 irq = au_ffs(intc0_req0) - 1;
508 intc0_req0 &= ~(1<<irq); 527 intc0_req0 &= ~(1<<irq);
509 do_IRQ(irq, regs); 528 do_IRQ(irq, regs);
@@ -521,17 +540,7 @@ void intc0_req1_irqdispatch(struct pt_regs *regs)
521 540
522 irq = au_ffs(intc0_req1) - 1; 541 irq = au_ffs(intc0_req1) - 1;
523 intc0_req1 &= ~(1<<irq); 542 intc0_req1 &= ~(1<<irq);
524#ifdef CONFIG_PM 543 do_IRQ(irq, regs);
525 if (irq == AU1000_TOY_MATCH2_INT) {
526 mask_and_ack_rise_edge_irq(irq);
527 counter0_irq(irq, NULL, regs);
528 local_enable_irq(irq);
529 }
530 else
531#endif
532 {
533 do_IRQ(irq, regs);
534 }
535} 544}
536 545
537 546
diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c
index 0776b2db5641..1f7b465c8038 100644
--- a/arch/mips/au1000/common/platform.c
+++ b/arch/mips/au1000/common/platform.c
@@ -7,13 +7,15 @@
7 * License version 2. This program is licensed "as is" without any 7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10#include <linux/config.h>
10#include <linux/device.h> 11#include <linux/device.h>
11#include <linux/kernel.h> 12#include <linux/kernel.h>
12#include <linux/init.h> 13#include <linux/init.h>
13#include <linux/resource.h> 14#include <linux/resource.h>
14 15
15#include <asm/mach-au1x00/au1000.h> 16#include <asm/mach-au1x00/au1xxx.h>
16 17
18/* OHCI (USB full speed host controller) */
17static struct resource au1xxx_usb_ohci_resources[] = { 19static struct resource au1xxx_usb_ohci_resources[] = {
18 [0] = { 20 [0] = {
19 .start = USB_OHCI_BASE, 21 .start = USB_OHCI_BASE,
@@ -41,8 +43,252 @@ static struct platform_device au1xxx_usb_ohci_device = {
41 .resource = au1xxx_usb_ohci_resources, 43 .resource = au1xxx_usb_ohci_resources,
42}; 44};
43 45
46/*** AU1100 LCD controller ***/
47
48#ifdef CONFIG_FB_AU1100
49static struct resource au1100_lcd_resources[] = {
50 [0] = {
51 .start = LCD_PHYS_ADDR,
52 .end = LCD_PHYS_ADDR + 0x800 - 1,
53 .flags = IORESOURCE_MEM,
54 },
55 [1] = {
56 .start = AU1100_LCD_INT,
57 .end = AU1100_LCD_INT,
58 .flags = IORESOURCE_IRQ,
59 }
60};
61
62static u64 au1100_lcd_dmamask = ~(u32)0;
63
64static struct platform_device au1100_lcd_device = {
65 .name = "au1100-lcd",
66 .id = 0,
67 .dev = {
68 .dma_mask = &au1100_lcd_dmamask,
69 .coherent_dma_mask = 0xffffffff,
70 },
71 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
72 .resource = au1100_lcd_resources,
73};
74#endif
75
76#ifdef CONFIG_SOC_AU1200
77/* EHCI (USB high speed host controller) */
78static struct resource au1xxx_usb_ehci_resources[] = {
79 [0] = {
80 .start = USB_EHCI_BASE,
81 .end = USB_EHCI_BASE + USB_EHCI_LEN - 1,
82 .flags = IORESOURCE_MEM,
83 },
84 [1] = {
85 .start = AU1000_USB_HOST_INT,
86 .end = AU1000_USB_HOST_INT,
87 .flags = IORESOURCE_IRQ,
88 },
89};
90
91static u64 ehci_dmamask = ~(u32)0;
92
93static struct platform_device au1xxx_usb_ehci_device = {
94 .name = "au1xxx-ehci",
95 .id = 0,
96 .dev = {
97 .dma_mask = &ehci_dmamask,
98 .coherent_dma_mask = 0xffffffff,
99 },
100 .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources),
101 .resource = au1xxx_usb_ehci_resources,
102};
103
104/* Au1200 UDC (USB gadget controller) */
105static struct resource au1xxx_usb_gdt_resources[] = {
106 [0] = {
107 .start = USB_UDC_BASE,
108 .end = USB_UDC_BASE + USB_UDC_LEN - 1,
109 .flags = IORESOURCE_MEM,
110 },
111 [1] = {
112 .start = AU1200_USB_INT,
113 .end = AU1200_USB_INT,
114 .flags = IORESOURCE_IRQ,
115 },
116};
117
118static struct resource au1xxx_mmc_resources[] = {
119 [0] = {
120 .start = SD0_PHYS_ADDR,
121 .end = SD0_PHYS_ADDR + 0x40,
122 .flags = IORESOURCE_MEM,
123 },
124 [1] = {
125 .start = SD1_PHYS_ADDR,
126 .end = SD1_PHYS_ADDR + 0x40,
127 .flags = IORESOURCE_MEM,
128 },
129 [2] = {
130 .start = AU1200_SD_INT,
131 .end = AU1200_SD_INT,
132 .flags = IORESOURCE_IRQ,
133 }
134};
135
136static u64 udc_dmamask = ~(u32)0;
137
138static struct platform_device au1xxx_usb_gdt_device = {
139 .name = "au1xxx-udc",
140 .id = 0,
141 .dev = {
142 .dma_mask = &udc_dmamask,
143 .coherent_dma_mask = 0xffffffff,
144 },
145 .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources),
146 .resource = au1xxx_usb_gdt_resources,
147};
148
149/* Au1200 UOC (USB OTG controller) */
150static struct resource au1xxx_usb_otg_resources[] = {
151 [0] = {
152 .start = USB_UOC_BASE,
153 .end = USB_UOC_BASE + USB_UOC_LEN - 1,
154 .flags = IORESOURCE_MEM,
155 },
156 [1] = {
157 .start = AU1200_USB_INT,
158 .end = AU1200_USB_INT,
159 .flags = IORESOURCE_IRQ,
160 },
161};
162
163static u64 uoc_dmamask = ~(u32)0;
164
165static struct platform_device au1xxx_usb_otg_device = {
166 .name = "au1xxx-uoc",
167 .id = 0,
168 .dev = {
169 .dma_mask = &uoc_dmamask,
170 .coherent_dma_mask = 0xffffffff,
171 },
172 .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources),
173 .resource = au1xxx_usb_otg_resources,
174};
175
176static struct resource au1200_lcd_resources[] = {
177 [0] = {
178 .start = LCD_PHYS_ADDR,
179 .end = LCD_PHYS_ADDR + 0x800 - 1,
180 .flags = IORESOURCE_MEM,
181 },
182 [1] = {
183 .start = AU1200_LCD_INT,
184 .end = AU1200_LCD_INT,
185 .flags = IORESOURCE_IRQ,
186 }
187};
188
189static struct resource au1200_ide0_resources[] = {
190 [0] = {
191 .start = AU1XXX_ATA_PHYS_ADDR,
192 .end = AU1XXX_ATA_PHYS_ADDR + AU1XXX_ATA_PHYS_LEN,
193 .flags = IORESOURCE_MEM,
194 },
195 [1] = {
196 .start = AU1XXX_ATA_INT,
197 .end = AU1XXX_ATA_INT,
198 .flags = IORESOURCE_IRQ,
199 }
200};
201
202static u64 au1200_lcd_dmamask = ~(u32)0;
203
204static struct platform_device au1200_lcd_device = {
205 .name = "au1200-lcd",
206 .id = 0,
207 .dev = {
208 .dma_mask = &au1200_lcd_dmamask,
209 .coherent_dma_mask = 0xffffffff,
210 },
211 .num_resources = ARRAY_SIZE(au1200_lcd_resources),
212 .resource = au1200_lcd_resources,
213};
214
215
216static u64 ide0_dmamask = ~(u32)0;
217
218static struct platform_device au1200_ide0_device = {
219 .name = "au1200-ide",
220 .id = 0,
221 .dev = {
222 .dma_mask = &ide0_dmamask,
223 .coherent_dma_mask = 0xffffffff,
224 },
225 .num_resources = ARRAY_SIZE(au1200_ide0_resources),
226 .resource = au1200_ide0_resources,
227};
228
229static u64 au1xxx_mmc_dmamask = ~(u32)0;
230
231static struct platform_device au1xxx_mmc_device = {
232 .name = "au1xxx-mmc",
233 .id = 0,
234 .dev = {
235 .dma_mask = &au1xxx_mmc_dmamask,
236 .coherent_dma_mask = 0xffffffff,
237 },
238 .num_resources = ARRAY_SIZE(au1xxx_mmc_resources),
239 .resource = au1xxx_mmc_resources,
240};
241#endif /* #ifdef CONFIG_SOC_AU1200 */
242
243static struct platform_device au1x00_pcmcia_device = {
244 .name = "au1x00-pcmcia",
245 .id = 0,
246};
247
248#ifdef CONFIG_MIPS_DB1200
249
250static struct resource smc91x_resources[] = {
251 [0] = {
252 .name = "smc91x-regs",
253 .start = AU1XXX_SMC91111_PHYS_ADDR,
254 .end = AU1XXX_SMC91111_PHYS_ADDR + 0xfffff,
255 .flags = IORESOURCE_MEM,
256 },
257 [1] = {
258 .start = AU1XXX_SMC91111_IRQ,
259 .end = AU1XXX_SMC91111_IRQ,
260 .flags = IORESOURCE_IRQ,
261 },
262};
263
264static struct platform_device smc91x_device = {
265 .name = "smc91x",
266 .id = -1,
267 .num_resources = ARRAY_SIZE(smc91x_resources),
268 .resource = smc91x_resources,
269};
270
271#endif
272
44static struct platform_device *au1xxx_platform_devices[] __initdata = { 273static struct platform_device *au1xxx_platform_devices[] __initdata = {
45 &au1xxx_usb_ohci_device, 274 &au1xxx_usb_ohci_device,
275 &au1x00_pcmcia_device,
276#ifdef CONFIG_FB_AU1100
277 &au1100_lcd_device,
278#endif
279#ifdef CONFIG_SOC_AU1200
280#if 0 /* fixme */
281 &au1xxx_usb_ehci_device,
282#endif
283 &au1xxx_usb_gdt_device,
284 &au1xxx_usb_otg_device,
285 &au1200_lcd_device,
286 &au1200_ide0_device,
287 &au1xxx_mmc_device,
288#endif
289#ifdef CONFIG_MIPS_DB1200
290 &smc91x_device,
291#endif
46}; 292};
47 293
48int au1xxx_platform_init(void) 294int au1xxx_platform_init(void)
diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c
index c40daccbb5b1..f85093b8d54d 100644
--- a/arch/mips/au1000/common/power.c
+++ b/arch/mips/au1000/common/power.c
@@ -34,11 +34,13 @@
34#include <linux/pm.h> 34#include <linux/pm.h>
35#include <linux/slab.h> 35#include <linux/slab.h>
36#include <linux/sysctl.h> 36#include <linux/sysctl.h>
37#include <linux/jiffies.h>
37 38
38#include <asm/string.h> 39#include <asm/string.h>
39#include <asm/uaccess.h> 40#include <asm/uaccess.h>
40#include <asm/io.h> 41#include <asm/io.h>
41#include <asm/system.h> 42#include <asm/system.h>
43#include <asm/cacheflush.h>
42#include <asm/mach-au1x00/au1000.h> 44#include <asm/mach-au1x00/au1000.h>
43 45
44#ifdef CONFIG_PM 46#ifdef CONFIG_PM
@@ -50,7 +52,7 @@
50# define DPRINTK(fmt, args...) 52# define DPRINTK(fmt, args...)
51#endif 53#endif
52 54
53static void calibrate_delay(void); 55static void au1000_calibrate_delay(void);
54 56
55extern void set_au1x00_speed(unsigned int new_freq); 57extern void set_au1x00_speed(unsigned int new_freq);
56extern unsigned int get_au1x00_speed(void); 58extern unsigned int get_au1x00_speed(void);
@@ -260,7 +262,7 @@ int au_sleep(void)
260} 262}
261 263
262static int pm_do_sleep(ctl_table * ctl, int write, struct file *file, 264static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
263 void *buffer, size_t * len) 265 void __user *buffer, size_t * len, loff_t *ppos)
264{ 266{
265 int retval = 0; 267 int retval = 0;
266#ifdef SLEEP_TEST_TIMEOUT 268#ifdef SLEEP_TEST_TIMEOUT
@@ -294,10 +296,9 @@ static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
294} 296}
295 297
296static int pm_do_suspend(ctl_table * ctl, int write, struct file *file, 298static int pm_do_suspend(ctl_table * ctl, int write, struct file *file,
297 void *buffer, size_t * len) 299 void __user *buffer, size_t * len, loff_t *ppos)
298{ 300{
299 int retval = 0; 301 int retval = 0;
300 void au1k_wait(void);
301 302
302 if (!write) { 303 if (!write) {
303 *len = 0; 304 *len = 0;
@@ -306,7 +307,7 @@ static int pm_do_suspend(ctl_table * ctl, int write, struct file *file,
306 if (retval) 307 if (retval)
307 return retval; 308 return retval;
308 suspend_mode = 1; 309 suspend_mode = 1;
309 au1k_wait(); 310
310 retval = pm_send_all(PM_RESUME, (void *) 0); 311 retval = pm_send_all(PM_RESUME, (void *) 0);
311 } 312 }
312 return retval; 313 return retval;
@@ -314,7 +315,7 @@ static int pm_do_suspend(ctl_table * ctl, int write, struct file *file,
314 315
315 316
316static int pm_do_freq(ctl_table * ctl, int write, struct file *file, 317static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
317 void *buffer, size_t * len) 318 void __user *buffer, size_t * len, loff_t *ppos)
318{ 319{
319 int retval = 0, i; 320 int retval = 0, i;
320 unsigned long val, pll; 321 unsigned long val, pll;
@@ -409,14 +410,14 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
409 410
410 411
411 /* We don't want _any_ interrupts other than 412 /* We don't want _any_ interrupts other than
412 * match20. Otherwise our calibrate_delay() 413 * match20. Otherwise our au1000_calibrate_delay()
413 * calculation will be off, potentially a lot. 414 * calculation will be off, potentially a lot.
414 */ 415 */
415 intc0_mask = save_local_and_disable(0); 416 intc0_mask = save_local_and_disable(0);
416 intc1_mask = save_local_and_disable(1); 417 intc1_mask = save_local_and_disable(1);
417 local_enable_irq(AU1000_TOY_MATCH2_INT); 418 local_enable_irq(AU1000_TOY_MATCH2_INT);
418 spin_unlock_irqrestore(&pm_lock, flags); 419 spin_unlock_irqrestore(&pm_lock, flags);
419 calibrate_delay(); 420 au1000_calibrate_delay();
420 restore_local_and_enable(0, intc0_mask); 421 restore_local_and_enable(0, intc0_mask);
421 restore_local_and_enable(1, intc1_mask); 422 restore_local_and_enable(1, intc1_mask);
422 return retval; 423 return retval;
@@ -456,7 +457,7 @@ __initcall(pm_init);
456 better than 1% */ 457 better than 1% */
457#define LPS_PREC 8 458#define LPS_PREC 8
458 459
459static void calibrate_delay(void) 460static void au1000_calibrate_delay(void)
460{ 461{
461 unsigned long ticks, loopbit; 462 unsigned long ticks, loopbit;
462 int lps_precision = LPS_PREC; 463 int lps_precision = LPS_PREC;
diff --git a/arch/mips/au1000/common/prom.c b/arch/mips/au1000/common/prom.c
index 22e5a85af4d5..9c171afd9a53 100644
--- a/arch/mips/au1000/common/prom.c
+++ b/arch/mips/au1000/common/prom.c
@@ -75,7 +75,8 @@ void prom_init_cmdline(void)
75 } 75 }
76 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ 76 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
77 --cp; 77 --cp;
78 *cp = '\0'; 78 if (prom_argc > 1)
79 *cp = '\0';
79 80
80} 81}
81 82
diff --git a/arch/mips/au1000/common/puts.c b/arch/mips/au1000/common/puts.c
index c2ae4624b77b..2705829cd466 100644
--- a/arch/mips/au1000/common/puts.c
+++ b/arch/mips/au1000/common/puts.c
@@ -39,7 +39,6 @@
39#define TIMEOUT 0xffffff 39#define TIMEOUT 0xffffff
40#define SLOW_DOWN 40#define SLOW_DOWN
41 41
42static const char digits[16] = "0123456789abcdef";
43static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE; 42static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE;
44 43
45 44
@@ -54,7 +53,7 @@ static inline void slow_down(void)
54#endif 53#endif
55 54
56void 55void
57putch(const unsigned char c) 56prom_putchar(const unsigned char c)
58{ 57{
59 unsigned char ch; 58 unsigned char ch;
60 int i = 0; 59 int i = 0;
@@ -69,77 +68,3 @@ putch(const unsigned char c)
69 } while (0 == (ch & TX_BUSY)); 68 } while (0 == (ch & TX_BUSY));
70 com1[SER_DATA] = c; 69 com1[SER_DATA] = c;
71} 70}
72
73void
74puts(unsigned char *cp)
75{
76 unsigned char ch;
77 int i = 0;
78
79 while (*cp) {
80 do {
81 ch = com1[SER_CMD];
82 slow_down();
83 i++;
84 if (i>TIMEOUT) {
85 break;
86 }
87 } while (0 == (ch & TX_BUSY));
88 com1[SER_DATA] = *cp++;
89 }
90 putch('\r');
91 putch('\n');
92}
93
94void
95fputs(const char *cp)
96{
97 unsigned char ch;
98 int i = 0;
99
100 while (*cp) {
101
102 do {
103 ch = com1[SER_CMD];
104 slow_down();
105 i++;
106 if (i>TIMEOUT) {
107 break;
108 }
109 } while (0 == (ch & TX_BUSY));
110 com1[SER_DATA] = *cp++;
111 }
112}
113
114
115void
116put64(uint64_t ul)
117{
118 int cnt;
119 unsigned ch;
120
121 cnt = 16; /* 16 nibbles in a 64 bit long */
122 putch('0');
123 putch('x');
124 do {
125 cnt--;
126 ch = (unsigned char)(ul >> cnt * 4) & 0x0F;
127 putch(digits[ch]);
128 } while (cnt > 0);
129}
130
131void
132put32(unsigned u)
133{
134 int cnt;
135 unsigned ch;
136
137 cnt = 8; /* 8 nibbles in a 32 bit long */
138 putch('0');
139 putch('x');
140 do {
141 cnt--;
142 ch = (unsigned char)(u >> cnt * 4) & 0x0F;
143 putch(digits[ch]);
144 } while (cnt > 0);
145}
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index eff89e109ce6..1ef15d5ef943 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -32,6 +32,7 @@
32#include <linux/mm.h> 32#include <linux/mm.h>
33#include <linux/delay.h> 33#include <linux/delay.h>
34#include <linux/interrupt.h> 34#include <linux/interrupt.h>
35#include <linux/module.h>
35 36
36#include <asm/cpu.h> 37#include <asm/cpu.h>
37#include <asm/bootinfo.h> 38#include <asm/bootinfo.h>
@@ -57,7 +58,7 @@ extern void au1xxx_time_init(void);
57extern void au1xxx_timer_setup(struct irqaction *irq); 58extern void au1xxx_timer_setup(struct irqaction *irq);
58extern void set_cpuspec(void); 59extern void set_cpuspec(void);
59 60
60static int __init au1x00_setup(void) 61void __init plat_setup(void)
61{ 62{
62 struct cpu_spec *sp; 63 struct cpu_spec *sp;
63 char *argptr; 64 char *argptr;
@@ -106,8 +107,6 @@ static int __init au1x00_setup(void)
106 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ 107 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
107#ifdef CONFIG_MIPS_HYDROGEN3 108#ifdef CONFIG_MIPS_HYDROGEN3
108 strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor"); 109 strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor");
109#else
110 strcat(argptr, " video=au1100fb:panel:s10,nohwcursor");
111#endif 110#endif
112 } 111 }
113#endif 112#endif
@@ -153,15 +152,11 @@ static int __init au1x00_setup(void)
153 au_sync(); 152 au_sync();
154 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); 153 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
155 au_writel(0, SYS_TOYTRIM); 154 au_writel(0, SYS_TOYTRIM);
156
157 return 0;
158} 155}
159 156
160early_initcall(au1x00_setup);
161
162#if defined(CONFIG_64BIT_PHYS_ADDR) 157#if defined(CONFIG_64BIT_PHYS_ADDR)
163/* This routine should be valid for all Au1x based boards */ 158/* This routine should be valid for all Au1x based boards */
164phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) 159phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
165{ 160{
166 u32 start, end; 161 u32 start, end;
167 162
@@ -192,4 +187,5 @@ phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
192 /* default nop */ 187 /* default nop */
193 return phys_addr; 188 return phys_addr;
194} 189}
190EXPORT_SYMBOL(__fixup_bigphys_addr);
195#endif 191#endif
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index 57675b41480e..883d3f3d8c53 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -50,7 +50,6 @@
50#include <linux/mc146818rtc.h> 50#include <linux/mc146818rtc.h>
51#include <linux/timex.h> 51#include <linux/timex.h>
52 52
53extern void startup_match20_interrupt(void);
54extern void do_softirq(void); 53extern void do_softirq(void);
55extern volatile unsigned long wall_jiffies; 54extern volatile unsigned long wall_jiffies;
56unsigned long missed_heart_beats = 0; 55unsigned long missed_heart_beats = 0;
@@ -58,14 +57,17 @@ unsigned long missed_heart_beats = 0;
58static unsigned long r4k_offset; /* Amount to increment compare reg each time */ 57static unsigned long r4k_offset; /* Amount to increment compare reg each time */
59static unsigned long r4k_cur; /* What counter should be at next timer irq */ 58static unsigned long r4k_cur; /* What counter should be at next timer irq */
60int no_au1xxx_32khz; 59int no_au1xxx_32khz;
61void (*au1k_wait_ptr)(void); 60extern int allow_au1k_wait; /* default off for CP0 Counter */
62 61
63/* Cycle counter value at the previous timer interrupt.. */ 62/* Cycle counter value at the previous timer interrupt.. */
64static unsigned int timerhi = 0, timerlo = 0; 63static unsigned int timerhi = 0, timerlo = 0;
65 64
66#ifdef CONFIG_PM 65#ifdef CONFIG_PM
67#define MATCH20_INC 328 66#if HZ < 100 || HZ > 1000
68extern void startup_match20_interrupt(void); 67#error "unsupported HZ value! Must be in [100,1000]"
68#endif
69#define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
70extern void startup_match20_interrupt(irqreturn_t (*handler)(int, void *, struct pt_regs *));
69static unsigned long last_pc0, last_match20; 71static unsigned long last_pc0, last_match20;
70#endif 72#endif
71 73
@@ -117,17 +119,16 @@ null:
117} 119}
118 120
119#ifdef CONFIG_PM 121#ifdef CONFIG_PM
120void counter0_irq(int irq, void *dev_id, struct pt_regs *regs) 122irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
121{ 123{
122 unsigned long pc0; 124 unsigned long pc0;
123 int time_elapsed; 125 int time_elapsed;
124 static int jiffie_drift = 0; 126 static int jiffie_drift = 0;
125 127
126 kstat.irqs[0][irq]++;
127 if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) { 128 if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
128 /* should never happen! */ 129 /* should never happen! */
129 printk(KERN_WARNING "counter 0 w status eror\n"); 130 printk(KERN_WARNING "counter 0 w status error\n");
130 return; 131 return IRQ_NONE;
131 } 132 }
132 133
133 pc0 = au_readl(SYS_TOYREAD); 134 pc0 = au_readl(SYS_TOYREAD);
@@ -164,6 +165,8 @@ void counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
164 update_process_times(user_mode(regs)); 165 update_process_times(user_mode(regs));
165#endif 166#endif
166 } 167 }
168
169 return IRQ_HANDLED;
167} 170}
168 171
169/* When we wakeup from sleep, we have to "catch up" on all of the 172/* When we wakeup from sleep, we have to "catch up" on all of the
@@ -388,7 +391,6 @@ void au1xxx_timer_setup(struct irqaction *irq)
388{ 391{
389 unsigned int est_freq; 392 unsigned int est_freq;
390 extern unsigned long (*do_gettimeoffset)(void); 393 extern unsigned long (*do_gettimeoffset)(void);
391 extern void au1k_wait(void);
392 394
393 printk("calculating r4koff... "); 395 printk("calculating r4koff... ");
394 r4k_offset = cal_r4koff(); 396 r4k_offset = cal_r4koff();
@@ -441,18 +443,18 @@ void au1xxx_timer_setup(struct irqaction *irq)
441 au_sync(); 443 au_sync();
442 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); 444 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
443 445
444 /* setup match20 to interrupt once every 10ms */ 446 /* setup match20 to interrupt once every HZ */
445 last_pc0 = last_match20 = au_readl(SYS_TOYREAD); 447 last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
446 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); 448 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
447 au_sync(); 449 au_sync();
448 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); 450 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
449 startup_match20_interrupt(); 451 startup_match20_interrupt(counter0_irq);
450 452
451 do_gettimeoffset = do_fast_pm_gettimeoffset; 453 do_gettimeoffset = do_fast_pm_gettimeoffset;
452 454
453 /* We can use the real 'wait' instruction. 455 /* We can use the real 'wait' instruction.
454 */ 456 */
455 au1k_wait_ptr = au1k_wait; 457 allow_au1k_wait = 1;
456 } 458 }
457 459
458#else 460#else
diff --git a/arch/mips/au1000/common/usbdev.c b/arch/mips/au1000/common/usbdev.c
index 447a9a4612a8..0b21bed7ee55 100644
--- a/arch/mips/au1000/common/usbdev.c
+++ b/arch/mips/au1000/common/usbdev.c
@@ -1005,11 +1005,11 @@ process_ep0_receive (struct usb_dev* dev)
1005#endif 1005#endif
1006 dev->ep0_stage = SETUP_STAGE; 1006 dev->ep0_stage = SETUP_STAGE;
1007 break; 1007 break;
1008 } 1008 }
1009 1009
1010 spin_unlock(&ep0->lock); 1010 spin_unlock(&ep0->lock);
1011 // we're done processing the packet, free it 1011 // we're done processing the packet, free it
1012 kfree(pkt); 1012 kfree(pkt);
1013} 1013}
1014 1014
1015 1015
@@ -1072,8 +1072,7 @@ dma_done_ep0_intr(int irq, void *dev_id, struct pt_regs *regs)
1072 clear_dma_done1(ep0->indma); 1072 clear_dma_done1(ep0->indma);
1073 1073
1074 pkt = send_packet_complete(ep0); 1074 pkt = send_packet_complete(ep0);
1075 if (pkt) 1075 kfree(pkt);
1076 kfree(pkt);
1077 } 1076 }
1078 1077
1079 /* 1078 /*
@@ -1302,8 +1301,7 @@ usbdev_exit(void)
1302 endpoint_flush(ep); 1301 endpoint_flush(ep);
1303 } 1302 }
1304 1303
1305 if (usbdev.full_conf_desc) 1304 kfree(usbdev.full_conf_desc);
1306 kfree(usbdev.full_conf_desc);
1307} 1305}
1308 1306
1309int 1307int
diff --git a/arch/mips/au1000/csb250/init.c b/arch/mips/au1000/csb250/init.c
index bd99733abc0b..a4898b1bc66a 100644
--- a/arch/mips/au1000/csb250/init.c
+++ b/arch/mips/au1000/csb250/init.c
@@ -35,7 +35,6 @@
35#include <asm/bootinfo.h> 35#include <asm/bootinfo.h>
36#include <linux/string.h> 36#include <linux/string.h>
37#include <linux/kernel.h> 37#include <linux/kernel.h>
38#include <linux/sched.h>
39 38
40int prom_argc; 39int prom_argc;
41char **prom_argv, **prom_envp; 40char **prom_argv, **prom_envp;
diff --git a/arch/mips/au1000/db1x00/irqmap.c b/arch/mips/au1000/db1x00/irqmap.c
index 8f6ef0dbe1f8..f63024a9893a 100644
--- a/arch/mips/au1000/db1x00/irqmap.c
+++ b/arch/mips/au1000/db1x00/irqmap.c
@@ -48,6 +48,38 @@
48#include <asm/system.h> 48#include <asm/system.h>
49#include <asm/mach-au1x00/au1000.h> 49#include <asm/mach-au1x00/au1000.h>
50 50
51#ifdef CONFIG_MIPS_DB1500
52char irq_tab_alchemy[][5] __initdata = {
53 [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT371 */
54 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
55};
56#endif
57
58#ifdef CONFIG_MIPS_BOSPORUS
59char irq_tab_alchemy[][5] __initdata = {
60 [11] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 11 - miniPCI */
61 [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - SN1741 */
62 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
63};
64#endif
65
66#ifdef CONFIG_MIPS_MIRAGE
67char irq_tab_alchemy[][5] __initdata = {
68 [11] = { -1, INTD, INTX, INTX, INTX}, /* IDSEL 11 - SMI VGX */
69 [12] = { -1, INTX, INTX, INTC, INTX}, /* IDSEL 12 - PNX1300 */
70 [13] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 13 - miniPCI */
71};
72#endif
73
74#ifdef CONFIG_MIPS_DB1550
75char irq_tab_alchemy[][5] __initdata = {
76 [11] = { -1, INTC, INTX, INTX, INTX}, /* IDSEL 11 - on-board HPT371 */
77 [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
78 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
79};
80#endif
81
82
51au1xxx_irq_map_t au1xxx_irq_map[] = { 83au1xxx_irq_map_t au1xxx_irq_map[] = {
52 84
53#ifndef CONFIG_MIPS_MIRAGE 85#ifndef CONFIG_MIPS_MIRAGE
diff --git a/arch/mips/au1000/db1x00/mirage_ts.c b/arch/mips/au1000/db1x00/mirage_ts.c
index ade35e432004..c29852c24b4f 100644
--- a/arch/mips/au1000/db1x00/mirage_ts.c
+++ b/arch/mips/au1000/db1x00/mirage_ts.c
@@ -102,15 +102,15 @@ static struct {
102} mirage_ts_cal = 102} mirage_ts_cal =
103{ 103{
104#if 0 104#if 0
105 xscale: 84, 105 .xscale = 84,
106 xtrans: -157, 106 .xtrans = -157,
107 yscale: 66, 107 .yscale = 66,
108 ytrans: -150, 108 .ytrans = -150,
109#else 109#else
110 xscale: 84, 110 .xscale = 84,
111 xtrans: -150, 111 .xtrans = -150,
112 yscale: 66, 112 .yscale = 66,
113 ytrans: -146, 113 .ytrans = -146,
114#endif 114#endif
115}; 115};
116 116
diff --git a/arch/mips/au1000/hydrogen3/init.c b/arch/mips/au1000/hydrogen3/init.c
index 8cc9879dd582..01ab28483959 100644
--- a/arch/mips/au1000/hydrogen3/init.c
+++ b/arch/mips/au1000/hydrogen3/init.c
@@ -37,7 +37,6 @@
37#include <linux/config.h> 37#include <linux/config.h>
38#include <linux/string.h> 38#include <linux/string.h>
39#include <linux/kernel.h> 39#include <linux/kernel.h>
40#include <linux/sched.h>
41 40
42int prom_argc; 41int prom_argc;
43char **prom_argv, **prom_envp; 42char **prom_argv, **prom_envp;
diff --git a/arch/mips/au1000/mtx-1/init.c b/arch/mips/au1000/mtx-1/init.c
index 02e7dbcff727..88f2b6d97281 100644
--- a/arch/mips/au1000/mtx-1/init.c
+++ b/arch/mips/au1000/mtx-1/init.c
@@ -33,7 +33,6 @@
33#include <linux/sched.h> 33#include <linux/sched.h>
34#include <linux/init.h> 34#include <linux/init.h>
35#include <linux/mm.h> 35#include <linux/mm.h>
36#include <linux/sched.h>
37#include <linux/bootmem.h> 36#include <linux/bootmem.h>
38#include <asm/addrspace.h> 37#include <asm/addrspace.h>
39#include <asm/bootinfo.h> 38#include <asm/bootinfo.h>
diff --git a/arch/mips/au1000/mtx-1/irqmap.c b/arch/mips/au1000/mtx-1/irqmap.c
index ddcb9d089dc1..f9a0a8b9def2 100644
--- a/arch/mips/au1000/mtx-1/irqmap.c
+++ b/arch/mips/au1000/mtx-1/irqmap.c
@@ -47,6 +47,17 @@
47#include <asm/system.h> 47#include <asm/system.h>
48#include <asm/mach-au1x00/au1000.h> 48#include <asm/mach-au1x00/au1000.h>
49 49
50char irq_tab_alchemy[][5] __initdata = {
51 [0] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */
52 [1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
53 [2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */
54 [3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
55 [4] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 04 - AdapterC-Slot0 (top) */
56 [5] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
57 [6] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 06 - AdapterD-Slot0 (top) */
58 [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
59};
60
50au1xxx_irq_map_t au1xxx_irq_map[] = { 61au1xxx_irq_map_t au1xxx_irq_map[] = {
51 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, 62 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
52 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, 63 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
diff --git a/arch/mips/au1000/pb1000/init.c b/arch/mips/au1000/pb1000/init.c
index 34713c5df0d7..e9fa1bab81f3 100644
--- a/arch/mips/au1000/pb1000/init.c
+++ b/arch/mips/au1000/pb1000/init.c
@@ -65,5 +65,4 @@ void __init prom_init(void)
65 memsize = simple_strtol(memsize_str, NULL, 0); 65 memsize = simple_strtol(memsize_str, NULL, 0);
66 } 66 }
67 add_memory_region(0, memsize, BOOT_MEM_RAM); 67 add_memory_region(0, memsize, BOOT_MEM_RAM);
68 return 0;
69} 68}
diff --git a/arch/mips/au1000/pb1200/Makefile b/arch/mips/au1000/pb1200/Makefile
new file mode 100644
index 000000000000..22b673cf55af
--- /dev/null
+++ b/arch/mips/au1000/pb1200/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the Alchemy Semiconductor PB1200 board.
3#
4
5lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c
new file mode 100644
index 000000000000..a45b17538ac9
--- /dev/null
+++ b/arch/mips/au1000/pb1200/board_setup.c
@@ -0,0 +1,193 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1200/Db1200 board setup.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#include <linux/config.h>
27#include <linux/init.h>
28#include <linux/sched.h>
29#include <linux/ioport.h>
30#include <linux/mm.h>
31#include <linux/console.h>
32#include <linux/mc146818rtc.h>
33#include <linux/delay.h>
34
35#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
36#include <linux/ide.h>
37#endif
38
39#include <asm/cpu.h>
40#include <asm/bootinfo.h>
41#include <asm/irq.h>
42#include <asm/mipsregs.h>
43#include <asm/reboot.h>
44#include <asm/pgtable.h>
45#include <asm/mach-au1x00/au1000.h>
46#include <asm/mach-au1x00/au1xxx_dbdma.h>
47
48#ifdef CONFIG_MIPS_PB1200
49#include <asm/mach-pb1x00/pb1200.h>
50#endif
51
52#ifdef CONFIG_MIPS_DB1200
53#include <asm/mach-db1x00/db1200.h>
54#define PB1200_ETH_INT DB1200_ETH_INT
55#define PB1200_IDE_INT DB1200_IDE_INT
56#endif
57
58extern void _board_init_irq(void);
59extern void (*board_init_irq)(void);
60
61void board_reset (void)
62{
63 bcsr->resets = 0;
64 bcsr->system = 0;
65}
66
67void __init board_setup(void)
68{
69 char *argptr = NULL;
70 u32 pin_func;
71
72#if 0
73 /* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
74 * but it is board specific code, so put it here.
75 */
76 pin_func = au_readl(SYS_PINFUNC);
77 au_sync();
78 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
79 au_writel(pin_func, SYS_PINFUNC);
80
81 au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
82 au_sync();
83#endif
84
85#if defined(CONFIG_I2C_AU1550)
86 {
87 u32 freq0, clksrc;
88
89 /* Select SMBUS in CPLD */
90 bcsr->resets &= ~(BCSR_RESETS_PCS0MUX);
91
92 pin_func = au_readl(SYS_PINFUNC);
93 au_sync();
94 pin_func &= ~(3<<17 | 1<<4);
95 /* Set GPIOs correctly */
96 pin_func |= 2<<17;
97 au_writel(pin_func, SYS_PINFUNC);
98 au_sync();
99
100 /* The i2c driver depends on 50Mhz clock */
101 freq0 = au_readl(SYS_FREQCTRL0);
102 au_sync();
103 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
104 freq0 |= (3<<SYS_FC_FRDIV1_BIT);
105 /* 396Mhz / (3+1)*2 == 49.5Mhz */
106 au_writel(freq0, SYS_FREQCTRL0);
107 au_sync();
108 freq0 |= SYS_FC_FE1;
109 au_writel(freq0, SYS_FREQCTRL0);
110 au_sync();
111
112 clksrc = au_readl(SYS_CLKSRC);
113 au_sync();
114 clksrc &= ~0x01f00000;
115 /* bit 22 is EXTCLK0 for PSC0 */
116 clksrc |= (0x3 << 22);
117 au_writel(clksrc, SYS_CLKSRC);
118 au_sync();
119 }
120#endif
121
122#ifdef CONFIG_FB_AU1200
123 argptr = prom_getcmdline();
124#ifdef CONFIG_MIPS_PB1200
125 strcat(argptr, " video=au1200fb:panel:bs");
126#endif
127#ifdef CONFIG_MIPS_DB1200
128 strcat(argptr, " video=au1200fb:panel:bs");
129#endif
130#endif
131
132 /* The Pb1200 development board uses external MUX for PSC0 to
133 support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
134 */
135#if defined(CONFIG_AU1XXX_PSC_SPI) && defined(CONFIG_I2C_AU1550)
136 #error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\
137 Refer to Pb1200/Db1200 documentation.
138#elif defined( CONFIG_AU1XXX_PSC_SPI )
139 bcsr->resets |= BCSR_RESETS_PCS0MUX;
140 /*Hard Coding Value to enable Temp Sensors [bit 14] Value for SOC Au1200. Pls refer documentation*/
141 bcsr->resets =0x900f;
142#elif defined( CONFIG_I2C_AU1550 )
143 bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
144#endif
145 au_sync();
146
147#ifdef CONFIG_MIPS_PB1200
148 printk("AMD Alchemy Pb1200 Board\n");
149#endif
150#ifdef CONFIG_MIPS_DB1200
151 printk("AMD Alchemy Db1200 Board\n");
152#endif
153
154 /* Setup Pb1200 External Interrupt Controller */
155 {
156 extern void (*board_init_irq)(void);
157 extern void _board_init_irq(void);
158 board_init_irq = _board_init_irq;
159 }
160}
161
162int
163board_au1200fb_panel (void)
164{
165 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
166 int p;
167
168 p = bcsr->switches;
169 p >>= 8;
170 p &= 0x0F;
171 return p;
172}
173
174int
175board_au1200fb_panel_init (void)
176{
177 /* Apply power */
178 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
179 bcsr->board |= (BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL);
180 /*printk("board_au1200fb_panel_init()\n"); */
181 return 0;
182}
183
184int
185board_au1200fb_panel_shutdown (void)
186{
187 /* Remove power */
188 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
189 bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL);
190 /*printk("board_au1200fb_panel_shutdown()\n"); */
191 return 0;
192}
193
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c
new file mode 100644
index 000000000000..27f09e374e15
--- /dev/null
+++ b/arch/mips/au1000/pb1200/init.c
@@ -0,0 +1,69 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PB1200 board setup
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30#include <linux/init.h>
31#include <linux/mm.h>
32#include <linux/sched.h>
33#include <linux/bootmem.h>
34#include <asm/addrspace.h>
35#include <asm/bootinfo.h>
36#include <linux/string.h>
37#include <linux/kernel.h>
38
39int prom_argc;
40char **prom_argv, **prom_envp;
41extern void __init prom_init_cmdline(void);
42extern char *prom_getenv(char *envname);
43
44const char *get_system_type(void)
45{
46 return "Alchemy Pb1200";
47}
48
49void __init prom_init(void)
50{
51 unsigned char *memsize_str;
52 unsigned long memsize;
53
54 prom_argc = (int) fw_arg0;
55 prom_argv = (char **) fw_arg1;
56 prom_envp = (char **) fw_arg2;
57
58 mips_machgroup = MACH_GROUP_ALCHEMY;
59 mips_machtype = MACH_PB1200;
60
61 prom_init_cmdline();
62 memsize_str = prom_getenv("memsize");
63 if (!memsize_str) {
64 memsize = 0x08000000;
65 } else {
66 memsize = simple_strtol(memsize_str, NULL, 0);
67 }
68 add_memory_region(0, memsize, BOOT_MEM_RAM);
69}
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
new file mode 100644
index 000000000000..59e70e5cf325
--- /dev/null
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -0,0 +1,182 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25#include <linux/config.h>
26#include <linux/errno.h>
27#include <linux/init.h>
28#include <linux/irq.h>
29#include <linux/kernel_stat.h>
30#include <linux/module.h>
31#include <linux/signal.h>
32#include <linux/sched.h>
33#include <linux/types.h>
34#include <linux/interrupt.h>
35#include <linux/ioport.h>
36#include <linux/timex.h>
37#include <linux/slab.h>
38#include <linux/random.h>
39#include <linux/delay.h>
40
41#include <asm/bitops.h>
42#include <asm/bootinfo.h>
43#include <asm/io.h>
44#include <asm/mipsregs.h>
45#include <asm/system.h>
46#include <asm/mach-au1x00/au1000.h>
47
48#ifdef CONFIG_MIPS_PB1200
49#include <asm/mach-pb1x00/pb1200.h>
50#endif
51
52#ifdef CONFIG_MIPS_DB1200
53#include <asm/mach-db1x00/db1200.h>
54#define PB1200_INT_BEGIN DB1200_INT_BEGIN
55#define PB1200_INT_END DB1200_INT_END
56#endif
57
58au1xxx_irq_map_t au1xxx_irq_map[] = {
59 { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
60};
61
62int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
63
64/*
65 * Support for External interrupts on the PbAu1200 Development platform.
66 */
67static volatile int pb1200_cascade_en=0;
68
69irqreturn_t pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
70{
71 unsigned short bisr = bcsr->int_status;
72 int extirq_nr = 0;
73
74 /* Clear all the edge interrupts. This has no effect on level */
75 bcsr->int_status = bisr;
76 for( ; bisr; bisr &= (bisr-1) )
77 {
78 extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
79 /* Ack and dispatch IRQ */
80 do_IRQ(extirq_nr,regs);
81 }
82 return IRQ_RETVAL(1);
83}
84
85inline void pb1200_enable_irq(unsigned int irq_nr)
86{
87 bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
88 bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN);
89}
90
91inline void pb1200_disable_irq(unsigned int irq_nr)
92{
93 bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
94 bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN);
95}
96
97static unsigned int pb1200_startup_irq( unsigned int irq_nr )
98{
99 if (++pb1200_cascade_en == 1)
100 {
101 request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
102 0, "Pb1200 Cascade", (void *)&pb1200_cascade_handler );
103#ifdef CONFIG_MIPS_PB1200
104 /* We have a problem with CPLD rev3. Enable a workaround */
105 if( ((bcsr->whoami & BCSR_WHOAMI_CPLD)>>4) <= 3)
106 {
107 printk("\nWARNING!!!\n");
108 printk("\nWARNING!!!\n");
109 printk("\nWARNING!!!\n");
110 printk("\nWARNING!!!\n");
111 printk("\nWARNING!!!\n");
112 printk("\nWARNING!!!\n");
113 printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n");
114 printk("updated to latest revision. This software will not\n");
115 printk("work on anything less than CPLD rev4\n");
116 printk("\nWARNING!!!\n");
117 printk("\nWARNING!!!\n");
118 printk("\nWARNING!!!\n");
119 printk("\nWARNING!!!\n");
120 printk("\nWARNING!!!\n");
121 printk("\nWARNING!!!\n");
122 while(1);
123 }
124#endif
125 }
126 pb1200_enable_irq(irq_nr);
127 return 0;
128}
129
130static void pb1200_shutdown_irq( unsigned int irq_nr )
131{
132 pb1200_disable_irq(irq_nr);
133 if (--pb1200_cascade_en == 0)
134 {
135 free_irq(AU1000_GPIO_7,&pb1200_cascade_handler );
136 }
137 return;
138}
139
140static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr)
141{
142 pb1200_disable_irq( irq_nr );
143}
144
145static void pb1200_end_irq(unsigned int irq_nr)
146{
147 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
148 pb1200_enable_irq(irq_nr);
149 }
150}
151
152static struct hw_interrupt_type external_irq_type =
153{
154#ifdef CONFIG_MIPS_PB1200
155 "Pb1200 Ext",
156#endif
157#ifdef CONFIG_MIPS_DB1200
158 "Db1200 Ext",
159#endif
160 pb1200_startup_irq,
161 pb1200_shutdown_irq,
162 pb1200_enable_irq,
163 pb1200_disable_irq,
164 pb1200_mask_and_ack_irq,
165 pb1200_end_irq,
166 NULL
167};
168
169void _board_init_irq(void)
170{
171 int irq_nr;
172
173 for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++)
174 {
175 irq_desc[irq_nr].handler = &external_irq_type;
176 pb1200_disable_irq(irq_nr);
177 }
178
179 /* GPIO_7 can not be hooked here, so it is hooked upon first
180 request of any source attached to the cascade */
181}
182
diff --git a/arch/mips/au1000/pb1500/irqmap.c b/arch/mips/au1000/pb1500/irqmap.c
index 476e25001681..8cb76c2edb5e 100644
--- a/arch/mips/au1000/pb1500/irqmap.c
+++ b/arch/mips/au1000/pb1500/irqmap.c
@@ -47,6 +47,11 @@
47#include <asm/system.h> 47#include <asm/system.h>
48#include <asm/mach-au1x00/au1000.h> 48#include <asm/mach-au1x00/au1000.h>
49 49
50char irq_tab_alchemy[][5] __initdata = {
51 [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT370 */
52 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
53};
54
50au1xxx_irq_map_t au1xxx_irq_map[] = { 55au1xxx_irq_map_t au1xxx_irq_map[] = {
51 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, 56 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
52 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, 57 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
diff --git a/arch/mips/au1000/pb1550/irqmap.c b/arch/mips/au1000/pb1550/irqmap.c
index 889d4949ee76..47c7a1c19f4b 100644
--- a/arch/mips/au1000/pb1550/irqmap.c
+++ b/arch/mips/au1000/pb1550/irqmap.c
@@ -47,6 +47,11 @@
47#include <asm/system.h> 47#include <asm/system.h>
48#include <asm/mach-au1x00/au1000.h> 48#include <asm/mach-au1x00/au1000.h>
49 49
50char irq_tab_alchemy[][5] __initdata = {
51 [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
52 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
53};
54
50au1xxx_irq_map_t au1xxx_irq_map[] = { 55au1xxx_irq_map_t au1xxx_irq_map[] = {
51 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, 56 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
52 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, 57 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index efbeac326815..0dc84417bf49 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -33,6 +33,9 @@ vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
33$(obj)/elf2ecoff: $(obj)/elf2ecoff.c 33$(obj)/elf2ecoff: $(obj)/elf2ecoff.c
34 $(HOSTCC) -o $@ $^ 34 $(HOSTCC) -o $@ $^
35 35
36vmlinux.bin: $(VMLINUX)
37 $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $(obj)/vmlinux.bin
38
36vmlinux.srec: $(VMLINUX) 39vmlinux.srec: $(VMLINUX)
37 $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec 40 $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec
38 41
@@ -45,5 +48,6 @@ archhelp:
45 48
46clean-files += addinitrd \ 49clean-files += addinitrd \
47 elf2ecoff \ 50 elf2ecoff \
51 vmlinux.bin \
48 vmlinux.ecoff \ 52 vmlinux.ecoff \
49 vmlinux.srec 53 vmlinux.srec
diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile
index a5e6554b2326..3b6b7579d1de 100644
--- a/arch/mips/cobalt/Makefile
+++ b/arch/mips/cobalt/Makefile
@@ -2,6 +2,6 @@
2# Makefile for the Cobalt micro systems family specific parts of the kernel 2# Makefile for the Cobalt micro systems family specific parts of the kernel
3# 3#
4 4
5obj-y := irq.o int-handler.o reset.o setup.o promcon.o 5obj-y := irq.o int-handler.o reset.o setup.o
6 6
7EXTRA_AFLAGS := $(CFLAGS) 7EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/cobalt/int-handler.S b/arch/mips/cobalt/int-handler.S
index 1a21dec1b3ca..f92608e8d84f 100644
--- a/arch/mips/cobalt/int-handler.S
+++ b/arch/mips/cobalt/int-handler.S
@@ -18,8 +18,8 @@
18 SAVE_ALL 18 SAVE_ALL
19 CLI 19 CLI
20 20
21 la ra, ret_from_irq 21 PTR_LA ra, ret_from_irq
22 move a1, sp 22 move a0, sp
23 j cobalt_irq 23 j cobalt_irq
24 24
25 END(cobalt_handle_int) 25 END(cobalt_handle_int)
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 6d2a81581397..0d90851f925e 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -10,6 +10,8 @@
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/irq.h> 12#include <linux/irq.h>
13#include <linux/interrupt.h>
14#include <linux/pci.h>
13 15
14#include <asm/i8259.h> 16#include <asm/i8259.h>
15#include <asm/irq_cpu.h> 17#include <asm/irq_cpu.h>
@@ -25,8 +27,8 @@ extern void cobalt_handle_int(void);
25 * the CPU interrupt lines, and ones that come in on the via chip. The CPU 27 * the CPU interrupt lines, and ones that come in on the via chip. The CPU
26 * mappings are: 28 * mappings are:
27 * 29 *
28 * 16, - Software interrupt 0 (unused) IE_SW0 30 * 16 - Software interrupt 0 (unused) IE_SW0
29 * 17 - Software interrupt 1 (unused) IE_SW0 31 * 17 - Software interrupt 1 (unused) IE_SW1
30 * 18 - Galileo chip (timer) IE_IRQ0 32 * 18 - Galileo chip (timer) IE_IRQ0
31 * 19 - Tulip 0 + NCR SCSI IE_IRQ1 33 * 19 - Tulip 0 + NCR SCSI IE_IRQ1
32 * 20 - Tulip 1 IE_IRQ2 34 * 20 - Tulip 1 IE_IRQ2
@@ -42,61 +44,94 @@ extern void cobalt_handle_int(void);
42 * 15 - IDE1 44 * 15 - IDE1
43 */ 45 */
44 46
45asmlinkage void cobalt_irq(struct pt_regs *regs) 47static inline void galileo_irq(struct pt_regs *regs)
46{ 48{
47 unsigned int pending = read_c0_status() & read_c0_cause(); 49 unsigned int mask, pending, devfn;
48
49 if (pending & CAUSEF_IP2) { /* int 18 */
50 unsigned long irq_src = GALILEO_INL(GT_INTRCAUSE_OFS);
51
52 /* Check for timer irq ... */
53 if (irq_src & GALILEO_T0EXP) {
54 /* Clear the int line */
55 GALILEO_OUTL(0, GT_INTRCAUSE_OFS);
56 do_IRQ(COBALT_TIMER_IRQ, regs);
57 }
58 return;
59 }
60 50
61 if (pending & CAUSEF_IP6) { /* int 22 */ 51 mask = GALILEO_INL(GT_INTRMASK_OFS);
62 int irq = i8259_irq(); 52 pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;
63 53
64 if (irq >= 0) 54 if (pending & GALILEO_INTR_T0EXP) {
65 do_IRQ(irq, regs);
66 return;
67 }
68 55
69 if (pending & CAUSEF_IP3) { /* int 19 */ 56 GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
70 do_IRQ(COBALT_ETH0_IRQ, regs); 57 do_IRQ(COBALT_GALILEO_IRQ, regs);
71 return;
72 }
73 58
74 if (pending & CAUSEF_IP4) { /* int 20 */ 59 } else if (pending & GALILEO_INTR_RETRY_CTR) {
75 do_IRQ(COBALT_ETH1_IRQ, regs);
76 return;
77 }
78 60
79 if (pending & CAUSEF_IP5) { /* int 21 */ 61 devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;
80 do_IRQ(COBALT_SERIAL_IRQ, regs); 62 GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);
81 return; 63 printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",
82 } 64 PCI_SLOT(devfn), PCI_FUNC(devfn));
65
66 } else {
83 67
84 if (pending & CAUSEF_IP7) { /* int 23 */ 68 GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);
85 do_IRQ(COBALT_QUBE_SLOT_IRQ, regs); 69 printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);
86 return;
87 } 70 }
88} 71}
89 72
73static inline void via_pic_irq(struct pt_regs *regs)
74{
75 int irq;
76
77 irq = i8259_irq();
78 if (irq >= 0)
79 do_IRQ(irq, regs);
80}
81
82asmlinkage void cobalt_irq(struct pt_regs *regs)
83{
84 unsigned pending;
85
86 pending = read_c0_status() & read_c0_cause();
87
88 if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
89
90 galileo_irq(regs);
91
92 else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
93
94 via_pic_irq(regs);
95
96 else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
97
98 do_IRQ(COBALT_CPU_IRQ + 3, regs);
99
100 else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
101
102 do_IRQ(COBALT_CPU_IRQ + 4, regs);
103
104 else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
105
106 do_IRQ(COBALT_CPU_IRQ + 5, regs);
107
108 else if (pending & CAUSEF_IP7) /* IRQ 23 */
109
110 do_IRQ(COBALT_CPU_IRQ + 7, regs);
111}
112
113static struct irqaction irq_via = {
114 no_action, 0, { { 0, } }, "cascade", NULL, NULL
115};
116
90void __init arch_init_irq(void) 117void __init arch_init_irq(void)
91{ 118{
119 /*
120 * Mask all Galileo interrupts. The Galileo
121 * handler is set in cobalt_timer_setup()
122 */
123 GALILEO_OUTL(0, GT_INTRMASK_OFS);
124
92 set_except_vector(0, cobalt_handle_int); 125 set_except_vector(0, cobalt_handle_int);
93 126
94 init_i8259_irqs(); /* 0 ... 15 */ 127 init_i8259_irqs(); /* 0 ... 15 */
95 mips_cpu_irq_init(16); /* 16 ... 23 */ 128 mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
96 129
97 /* 130 /*
98 * Mask all cpu interrupts 131 * Mask all cpu interrupts
99 * (except IE4, we already masked those at VIA level) 132 * (except IE4, we already masked those at VIA level)
100 */ 133 */
101 change_c0_status(ST0_IM, IE_IRQ4); 134 change_c0_status(ST0_IM, IE_IRQ4);
135
136 setup_irq(COBALT_VIA_IRQ, &irq_via);
102} 137}
diff --git a/arch/mips/cobalt/promcon.c b/arch/mips/cobalt/promcon.c
deleted file mode 100644
index f03df761e9f1..000000000000
--- a/arch/mips/cobalt/promcon.c
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * PROM console for Cobalt Raq2
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
9 * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
10 *
11 */
12
13#include <linux/init.h>
14#include <linux/console.h>
15#include <linux/kdev_t.h>
16#include <linux/serial_reg.h>
17
18#include <asm/delay.h>
19#include <asm/serial.h>
20#include <asm/io.h>
21
22static unsigned long port = 0xc800000;
23
24static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr)
25{
26 char lsr;
27
28 do {
29 lsr = inb(ioaddr + UART_LSR);
30 } while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
31 outb(ch, ioaddr + UART_TX);
32}
33
34static __inline__ char ns16550_cons_get_char(unsigned long ioaddr)
35{
36 while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0)
37 udelay(1);
38 return inb(ioaddr + UART_RX);
39}
40
41void ns16550_console_write(struct console *co, const char *s, unsigned count)
42{
43 char lsr, ier;
44 unsigned i;
45
46 ier = inb(port + UART_IER);
47 outb(0x00, port + UART_IER);
48 for (i=0; i < count; i++, s++) {
49
50 if(*s == '\n')
51 ns16550_cons_put_char('\r', port);
52 ns16550_cons_put_char(*s, port);
53 }
54
55 do {
56 lsr = inb(port + UART_LSR);
57 } while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
58
59 outb(ier, port + UART_IER);
60}
61
62char getDebugChar(void)
63{
64 return ns16550_cons_get_char(port);
65}
66
67void putDebugChar(char kgdb_char)
68{
69 ns16550_cons_put_char(kgdb_char, port);
70}
71
72static struct console ns16550_console = {
73 .name = "prom",
74 .setup = NULL,
75 .write = ns16550_console_write,
76 .flags = CON_PRINTBUFFER,
77 .index = -1,
78};
79
80static int __init ns16550_setup_console(void)
81{
82 register_console(&ns16550_console);
83
84 return 0;
85}
86
87console_initcall(ns16550_setup_console);
diff --git a/arch/mips/cobalt/reset.c b/arch/mips/cobalt/reset.c
index 084c8e59f42c..805a0e88507b 100644
--- a/arch/mips/cobalt/reset.c
+++ b/arch/mips/cobalt/reset.c
@@ -16,48 +16,45 @@
16#include <asm/reboot.h> 16#include <asm/reboot.h>
17#include <asm/system.h> 17#include <asm/system.h>
18#include <asm/mipsregs.h> 18#include <asm/mipsregs.h>
19#include <asm/cobalt/cobalt.h>
19 20
20void cobalt_machine_restart(char *command) 21void cobalt_machine_halt(void)
21{ 22{
22 *(volatile char *)0xbc000000 = 0x0f; 23 int state, last, diff;
24 unsigned long mark;
23 25
24 /* 26 /*
25 * Ouch, we're still alive ... This time we take the silver bullet ... 27 * turn off bar on Qube, flash power off LED on RaQ (0.5Hz)
26 * ... and find that we leave the hardware in a state in which the 28 *
27 * kernel in the flush locks up somewhen during of after the PCI 29 * restart if ENTER and SELECT are pressed
28 * detection stuff.
29 */ 30 */
30 set_c0_status(ST0_BEV | ST0_ERL);
31 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
32 flush_cache_all();
33 write_c0_wired(0);
34 __asm__ __volatile__(
35 "jr\t%0"
36 :
37 : "r" (0xbfc00000));
38}
39 31
40extern int led_state; 32 last = COBALT_KEY_PORT;
41#define kLED 0xBC000000
42#define LEDSet(x) (*(volatile unsigned char *) kLED) = (( unsigned char)x)
43 33
44void cobalt_machine_halt(void) 34 for (state = 0;;) {
45{ 35
46 int mark; 36 state ^= COBALT_LED_POWER_OFF;
37 COBALT_LED_PORT = state;
38
39 diff = COBALT_KEY_PORT ^ last;
40 last ^= diff;
47 41
48 /* Blink our cute? little LED (number 3)... */ 42 if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)))
49 while (1) { 43 COBALT_LED_PORT = COBALT_LED_RESET;
50 led_state = led_state | ( 1 << 3 ); 44
51 LEDSet(led_state); 45 for (mark = jiffies; jiffies - mark < HZ;)
52 mark = jiffies; 46 ;
53 while (jiffies<(mark+HZ));
54 led_state = led_state & ~( 1 << 3 );
55 LEDSet(led_state);
56 mark = jiffies;
57 while (jiffies<(mark+HZ));
58 } 47 }
59} 48}
60 49
50void cobalt_machine_restart(char *command)
51{
52 COBALT_LED_PORT = COBALT_LED_RESET;
53
54 /* we should never get here */
55 cobalt_machine_halt();
56}
57
61/* 58/*
62 * This triggers the luser mode device driver for the power switch ;-) 59 * This triggers the luser mode device driver for the power switch ;-)
63 */ 60 */
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index 6b4737e425ed..d358a118fa31 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -13,6 +13,8 @@
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/pci.h> 14#include <linux/pci.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/serial.h>
17#include <linux/serial_core.h>
16 18
17#include <asm/bootinfo.h> 19#include <asm/bootinfo.h>
18#include <asm/time.h> 20#include <asm/time.h>
@@ -21,6 +23,7 @@
21#include <asm/processor.h> 23#include <asm/processor.h>
22#include <asm/reboot.h> 24#include <asm/reboot.h>
23#include <asm/gt64120.h> 25#include <asm/gt64120.h>
26#include <asm/serial.h>
24 27
25#include <asm/cobalt/cobalt.h> 28#include <asm/cobalt/cobalt.h>
26 29
@@ -30,45 +33,44 @@ extern void cobalt_machine_power_off(void);
30 33
31int cobalt_board_id; 34int cobalt_board_id;
32 35
33static char my_cmdline[CL_SIZE] = {
34 "console=ttyS0,115200 "
35#ifdef CONFIG_IP_PNP
36 "ip=on "
37#endif
38#ifdef CONFIG_ROOT_NFS
39 "root=/dev/nfs "
40#else
41 "root=/dev/hda1 "
42#endif
43 };
44
45const char *get_system_type(void) 36const char *get_system_type(void)
46{ 37{
38 switch (cobalt_board_id) {
39 case COBALT_BRD_ID_QUBE1:
40 return "Cobalt Qube";
41 case COBALT_BRD_ID_RAQ1:
42 return "Cobalt RaQ";
43 case COBALT_BRD_ID_QUBE2:
44 return "Cobalt Qube2";
45 case COBALT_BRD_ID_RAQ2:
46 return "Cobalt RaQ2";
47 }
47 return "MIPS Cobalt"; 48 return "MIPS Cobalt";
48} 49}
49 50
50static void __init cobalt_timer_setup(struct irqaction *irq) 51static void __init cobalt_timer_setup(struct irqaction *irq)
51{ 52{
52 /* Load timer value for 150 Hz */ 53 /* Load timer value for 1KHz (TCLK is 50MHz) */
53 GALILEO_OUTL(500000, GT_TC0_OFS); 54 GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS);
54 55
55 /* Register our timer interrupt */ 56 /* Enable timer */
56 setup_irq(COBALT_TIMER_IRQ, irq); 57 GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS);
57 58
58 /* Enable timer ints */ 59 /* Register interrupt */
59 GALILEO_OUTL((GALILEO_ENTC0 | GALILEO_SELTC0), GT_TC_CONTROL_OFS); 60 setup_irq(COBALT_GALILEO_IRQ, irq);
60 /* Unmask timer int */ 61
61 GALILEO_OUTL(0x100, GT_INTRMASK_OFS); 62 /* Enable interrupt */
63 GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
62} 64}
63 65
64extern struct pci_ops gt64111_pci_ops; 66extern struct pci_ops gt64111_pci_ops;
65 67
66static struct resource cobalt_mem_resource = { 68static struct resource cobalt_mem_resource = {
67 "GT64111 PCI MEM", GT64111_IO_BASE, 0xffffffffUL, IORESOURCE_MEM 69 "PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM
68}; 70};
69 71
70static struct resource cobalt_io_resource = { 72static struct resource cobalt_io_resource = {
71 "GT64111 IO MEM", 0x00001000UL, 0x0fffffffUL, IORESOURCE_IO 73 "PCI I/O", 0x1000, 0xffff, IORESOURCE_IO
72}; 74};
73 75
74static struct resource cobalt_io_resources[] = { 76static struct resource cobalt_io_resources[] = {
@@ -86,11 +88,12 @@ static struct pci_controller cobalt_pci_controller = {
86 .mem_resource = &cobalt_mem_resource, 88 .mem_resource = &cobalt_mem_resource,
87 .mem_offset = 0, 89 .mem_offset = 0,
88 .io_resource = &cobalt_io_resource, 90 .io_resource = &cobalt_io_resource,
89 .io_offset = 0x00001000UL - GT64111_IO_BASE 91 .io_offset = 0 - GT64111_IO_BASE
90}; 92};
91 93
92static void __init cobalt_setup(void) 94void __init plat_setup(void)
93{ 95{
96 static struct uart_port uart;
94 unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); 97 unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
95 int i; 98 int i;
96 99
@@ -100,7 +103,10 @@ static void __init cobalt_setup(void)
100 103
101 board_timer_setup = cobalt_timer_setup; 104 board_timer_setup = cobalt_timer_setup;
102 105
103 set_io_port_base(KSEG1ADDR(GT64111_IO_BASE)); 106 set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
107
108 /* I/O port resource must include UART and LCD/buttons */
109 ioport_resource.end = 0x0fffffff;
104 110
105 /* 111 /*
106 * This is a prom style console. We just poke at the 112 * This is a prom style console. We just poke at the
@@ -120,27 +126,61 @@ static void __init cobalt_setup(void)
120 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); 126 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
121 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); 127 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
122 128
129 printk("Cobalt board ID: %d\n", cobalt_board_id);
130
123#ifdef CONFIG_PCI 131#ifdef CONFIG_PCI
124 register_pci_controller(&cobalt_pci_controller); 132 register_pci_controller(&cobalt_pci_controller);
125#endif 133#endif
126}
127 134
128early_initcall(cobalt_setup); 135#ifdef CONFIG_SERIAL_8250
136 if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
137
138 uart.line = 0;
139 uart.type = PORT_UNKNOWN;
140 uart.uartclk = 18432000;
141 uart.irq = COBALT_SERIAL_IRQ;
142 uart.flags = STD_COM_FLAGS;
143 uart.iobase = 0xc800000;
144 uart.iotype = UPIO_PORT;
145
146 early_serial_setup(&uart);
147 }
148#endif
149}
129 150
130/* 151/*
131 * Prom init. We read our one and only communication with the firmware. 152 * Prom init. We read our one and only communication with the firmware.
132 * Grab the amount of installed memory 153 * Grab the amount of installed memory.
154 * Better boot loaders (CoLo) pass a command line too :-)
133 */ 155 */
134 156
135void __init prom_init(void) 157void __init prom_init(void)
136{ 158{
137 int argc = fw_arg0; 159 int narg, indx, posn, nchr;
138 160 unsigned long memsz;
139 strcpy(arcs_cmdline, my_cmdline); 161 char **argv;
140 162
141 mips_machgroup = MACH_GROUP_COBALT; 163 mips_machgroup = MACH_GROUP_COBALT;
142 164
143 add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM); 165 memsz = fw_arg0 & 0x7fff0000;
166 narg = fw_arg0 & 0x0000ffff;
167
168 if (narg) {
169 arcs_cmdline[0] = '\0';
170 argv = (char **) fw_arg1;
171 posn = 0;
172 for (indx = 1; indx < narg; ++indx) {
173 nchr = strlen(argv[indx]);
174 if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
175 break;
176 if (posn)
177 arcs_cmdline[posn++] = ' ';
178 strcpy(arcs_cmdline + posn, argv[indx]);
179 posn += nchr;
180 }
181 }
182
183 add_memory_region(0x0, memsz, BOOT_MEM_RAM);
144} 184}
145 185
146unsigned long __init prom_free_prom_memory(void) 186unsigned long __init prom_free_prom_memory(void)
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig
index 3120a02b8670..132ec3dac63f 100644
--- a/arch/mips/configs/atlas_defconfig
+++ b/arch/mips/configs/atlas_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:00 2005 4# Thu Oct 20 22:25:13 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29CONFIG_HOTPLUG=y 27CONFIG_HOTPLUG=y
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,42 +59,72 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
69CONFIG_MIPS_ATLAS=y 83CONFIG_MIPS_ATLAS=y
70# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
83# CONFIG_SOC_AU1X00 is not set 102# CONFIG_SGI_IP27 is not set
84# CONFIG_SIBYTE_SB1xxx_SOC is not set 103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
85# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
86# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
87CONFIG_RWSEM_GENERIC_SPINLOCK=y 117CONFIG_RWSEM_GENERIC_SPINLOCK=y
88CONFIG_GENERIC_CALIBRATE_DELAY=y 118CONFIG_GENERIC_CALIBRATE_DELAY=y
89CONFIG_HAVE_DEC_LOCK=y
90CONFIG_DMA_NONCOHERENT=y 119CONFIG_DMA_NONCOHERENT=y
91CONFIG_DMA_NEED_PCI_MAP_STATE=y 120CONFIG_DMA_NEED_PCI_MAP_STATE=y
92CONFIG_MIPS_BONITO64=y 121CONFIG_MIPS_BONITO64=y
93CONFIG_MIPS_MSC=y 122CONFIG_MIPS_MSC=y
94# CONFIG_CPU_LITTLE_ENDIAN is not set 123# CONFIG_CPU_BIG_ENDIAN is not set
124CONFIG_CPU_LITTLE_ENDIAN=y
125CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
126CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
127CONFIG_IRQ_CPU=y
95CONFIG_MIPS_BOARDS_GEN=y 128CONFIG_MIPS_BOARDS_GEN=y
96CONFIG_MIPS_GT64120=y 129CONFIG_MIPS_GT64120=y
97CONFIG_SWAP_IO_SPACE=y 130CONFIG_SWAP_IO_SPACE=y
@@ -101,8 +134,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
101# 134#
102# CPU selection 135# CPU selection
103# 136#
104CONFIG_CPU_MIPS32=y 137CONFIG_CPU_MIPS32_R1=y
105# CONFIG_CPU_MIPS64 is not set 138# CONFIG_CPU_MIPS32_R2 is not set
139# CONFIG_CPU_MIPS64_R1 is not set
140# CONFIG_CPU_MIPS64_R2 is not set
106# CONFIG_CPU_R3000 is not set 141# CONFIG_CPU_R3000 is not set
107# CONFIG_CPU_TX39XX is not set 142# CONFIG_CPU_TX39XX is not set
108# CONFIG_CPU_VR41XX is not set 143# CONFIG_CPU_VR41XX is not set
@@ -118,15 +153,46 @@ CONFIG_CPU_MIPS32=y
118# CONFIG_CPU_RM7000 is not set 153# CONFIG_CPU_RM7000 is not set
119# CONFIG_CPU_RM9000 is not set 154# CONFIG_CPU_RM9000 is not set
120# CONFIG_CPU_SB1 is not set 155# CONFIG_CPU_SB1 is not set
156CONFIG_SYS_HAS_CPU_MIPS32_R1=y
157CONFIG_SYS_HAS_CPU_MIPS32_R2=y
158CONFIG_SYS_HAS_CPU_MIPS64_R1=y
159CONFIG_SYS_HAS_CPU_NEVADA=y
160CONFIG_SYS_HAS_CPU_RM7000=y
161CONFIG_CPU_MIPS32=y
162CONFIG_CPU_MIPSR1=y
163CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
164CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
165CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
166
167#
168# Kernel type
169#
170CONFIG_32BIT=y
171# CONFIG_64BIT is not set
121CONFIG_PAGE_SIZE_4KB=y 172CONFIG_PAGE_SIZE_4KB=y
122# CONFIG_PAGE_SIZE_8KB is not set 173# CONFIG_PAGE_SIZE_8KB is not set
123# CONFIG_PAGE_SIZE_16KB is not set 174# CONFIG_PAGE_SIZE_16KB is not set
124# CONFIG_PAGE_SIZE_64KB is not set 175# CONFIG_PAGE_SIZE_64KB is not set
176CONFIG_BOARD_SCACHE=y
177CONFIG_RM7000_CPU_SCACHE=y
125CONFIG_CPU_HAS_PREFETCH=y 178CONFIG_CPU_HAS_PREFETCH=y
179# CONFIG_MIPS_MT is not set
126# CONFIG_64BIT_PHYS_ADDR is not set 180# CONFIG_64BIT_PHYS_ADDR is not set
127# CONFIG_CPU_ADVANCED is not set 181# CONFIG_CPU_ADVANCED is not set
128CONFIG_CPU_HAS_LLSC=y 182CONFIG_CPU_HAS_LLSC=y
129CONFIG_CPU_HAS_SYNC=y 183CONFIG_CPU_HAS_SYNC=y
184CONFIG_GENERIC_HARDIRQS=y
185CONFIG_GENERIC_IRQ_PROBE=y
186CONFIG_ARCH_FLATMEM_ENABLE=y
187CONFIG_SELECT_MEMORY_MODEL=y
188CONFIG_FLATMEM_MANUAL=y
189# CONFIG_DISCONTIGMEM_MANUAL is not set
190# CONFIG_SPARSEMEM_MANUAL is not set
191CONFIG_FLATMEM=y
192CONFIG_FLAT_NODE_MEM_MAP=y
193# CONFIG_SPARSEMEM_STATIC is not set
194CONFIG_PREEMPT_NONE=y
195# CONFIG_PREEMPT_VOLUNTARY is not set
130# CONFIG_PREEMPT is not set 196# CONFIG_PREEMPT is not set
131 197
132# 198#
@@ -135,7 +201,6 @@ CONFIG_CPU_HAS_SYNC=y
135CONFIG_HW_HAS_PCI=y 201CONFIG_HW_HAS_PCI=y
136CONFIG_PCI=y 202CONFIG_PCI=y
137CONFIG_PCI_LEGACY_PROC=y 203CONFIG_PCI_LEGACY_PROC=y
138CONFIG_PCI_NAMES=y
139CONFIG_MMU=y 204CONFIG_MMU=y
140 205
141# 206#
@@ -144,10 +209,6 @@ CONFIG_MMU=y
144# CONFIG_PCCARD is not set 209# CONFIG_PCCARD is not set
145 210
146# 211#
147# PC-card bridges
148#
149
150#
151# PCI Hotplug Support 212# PCI Hotplug Support
152# 213#
153# CONFIG_HOTPLUG_PCI is not set 214# CONFIG_HOTPLUG_PCI is not set
@@ -160,199 +221,7 @@ CONFIG_BINFMT_ELF=y
160CONFIG_TRAD_SIGNALS=y 221CONFIG_TRAD_SIGNALS=y
161 222
162# 223#
163# Device Drivers 224# Networking
164#
165
166#
167# Generic Driver Options
168#
169CONFIG_STANDALONE=y
170CONFIG_PREVENT_FIRMWARE_BUILD=y
171CONFIG_FW_LOADER=y
172
173#
174# Memory Technology Devices (MTD)
175#
176# CONFIG_MTD is not set
177
178#
179# Parallel port support
180#
181# CONFIG_PARPORT is not set
182
183#
184# Plug and Play support
185#
186
187#
188# Block devices
189#
190# CONFIG_BLK_DEV_FD is not set
191# CONFIG_BLK_CPQ_DA is not set
192# CONFIG_BLK_CPQ_CISS_DA is not set
193# CONFIG_BLK_DEV_DAC960 is not set
194CONFIG_BLK_DEV_UMEM=m
195# CONFIG_BLK_DEV_COW_COMMON is not set
196CONFIG_BLK_DEV_LOOP=m
197CONFIG_BLK_DEV_CRYPTOLOOP=m
198CONFIG_BLK_DEV_NBD=m
199# CONFIG_BLK_DEV_SX8 is not set
200CONFIG_BLK_DEV_RAM=y
201CONFIG_BLK_DEV_RAM_COUNT=16
202CONFIG_BLK_DEV_RAM_SIZE=4096
203# CONFIG_BLK_DEV_INITRD is not set
204CONFIG_INITRAMFS_SOURCE=""
205# CONFIG_LBD is not set
206CONFIG_CDROM_PKTCDVD=m
207CONFIG_CDROM_PKTCDVD_BUFFERS=8
208# CONFIG_CDROM_PKTCDVD_WCACHE is not set
209
210#
211# IO Schedulers
212#
213CONFIG_IOSCHED_NOOP=y
214CONFIG_IOSCHED_AS=y
215CONFIG_IOSCHED_DEADLINE=y
216CONFIG_IOSCHED_CFQ=y
217CONFIG_ATA_OVER_ETH=m
218
219#
220# ATA/ATAPI/MFM/RLL support
221#
222CONFIG_IDE=y
223CONFIG_BLK_DEV_IDE=y
224
225#
226# Please see Documentation/ide.txt for help/info on IDE drives
227#
228# CONFIG_BLK_DEV_IDE_SATA is not set
229CONFIG_BLK_DEV_IDEDISK=y
230# CONFIG_IDEDISK_MULTI_MODE is not set
231CONFIG_BLK_DEV_IDECD=y
232# CONFIG_BLK_DEV_IDETAPE is not set
233# CONFIG_BLK_DEV_IDEFLOPPY is not set
234# CONFIG_BLK_DEV_IDESCSI is not set
235# CONFIG_IDE_TASK_IOCTL is not set
236
237#
238# IDE chipset support/bugfixes
239#
240CONFIG_IDE_GENERIC=y
241# CONFIG_BLK_DEV_IDEPCI is not set
242# CONFIG_IDE_ARM is not set
243# CONFIG_BLK_DEV_IDEDMA is not set
244# CONFIG_IDEDMA_AUTO is not set
245# CONFIG_BLK_DEV_HD is not set
246
247#
248# SCSI device support
249#
250CONFIG_SCSI=y
251CONFIG_SCSI_PROC_FS=y
252
253#
254# SCSI support type (disk, tape, CD-ROM)
255#
256CONFIG_BLK_DEV_SD=y
257CONFIG_CHR_DEV_ST=m
258CONFIG_CHR_DEV_OSST=m
259CONFIG_BLK_DEV_SR=m
260CONFIG_BLK_DEV_SR_VENDOR=y
261CONFIG_CHR_DEV_SG=m
262
263#
264# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
265#
266CONFIG_SCSI_MULTI_LUN=y
267CONFIG_SCSI_CONSTANTS=y
268CONFIG_SCSI_LOGGING=y
269
270#
271# SCSI Transport Attributes
272#
273CONFIG_SCSI_SPI_ATTRS=y
274CONFIG_SCSI_FC_ATTRS=m
275CONFIG_SCSI_ISCSI_ATTRS=m
276
277#
278# SCSI low-level drivers
279#
280# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
281# CONFIG_SCSI_3W_9XXX is not set
282# CONFIG_SCSI_ACARD is not set
283# CONFIG_SCSI_AACRAID is not set
284# CONFIG_SCSI_AIC7XXX is not set
285# CONFIG_SCSI_AIC7XXX_OLD is not set
286# CONFIG_SCSI_AIC79XX is not set
287# CONFIG_SCSI_DPT_I2O is not set
288# CONFIG_MEGARAID_NEWGEN is not set
289# CONFIG_MEGARAID_LEGACY is not set
290# CONFIG_SCSI_SATA is not set
291# CONFIG_SCSI_BUSLOGIC is not set
292# CONFIG_SCSI_DMX3191D is not set
293# CONFIG_SCSI_EATA is not set
294# CONFIG_SCSI_EATA_PIO is not set
295# CONFIG_SCSI_FUTURE_DOMAIN is not set
296# CONFIG_SCSI_GDTH is not set
297# CONFIG_SCSI_IPS is not set
298# CONFIG_SCSI_INITIO is not set
299# CONFIG_SCSI_INIA100 is not set
300CONFIG_SCSI_SYM53C8XX_2=y
301CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
302CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
303CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
304# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
305# CONFIG_SCSI_IPR is not set
306# CONFIG_SCSI_QLOGIC_ISP is not set
307# CONFIG_SCSI_QLOGIC_FC is not set
308# CONFIG_SCSI_QLOGIC_1280 is not set
309CONFIG_SCSI_QLA2XXX=y
310# CONFIG_SCSI_QLA21XX is not set
311# CONFIG_SCSI_QLA22XX is not set
312# CONFIG_SCSI_QLA2300 is not set
313# CONFIG_SCSI_QLA2322 is not set
314# CONFIG_SCSI_QLA6312 is not set
315# CONFIG_SCSI_DC395x is not set
316# CONFIG_SCSI_DC390T is not set
317# CONFIG_SCSI_NSP32 is not set
318# CONFIG_SCSI_DEBUG is not set
319
320#
321# Multi-device support (RAID and LVM)
322#
323CONFIG_MD=y
324CONFIG_BLK_DEV_MD=m
325CONFIG_MD_LINEAR=m
326CONFIG_MD_RAID0=m
327CONFIG_MD_RAID1=m
328CONFIG_MD_RAID10=m
329CONFIG_MD_RAID5=m
330CONFIG_MD_RAID6=m
331CONFIG_MD_MULTIPATH=m
332CONFIG_MD_FAULTY=m
333CONFIG_BLK_DEV_DM=m
334CONFIG_DM_CRYPT=m
335CONFIG_DM_SNAPSHOT=m
336CONFIG_DM_MIRROR=m
337CONFIG_DM_ZERO=m
338
339#
340# Fusion MPT device support
341#
342# CONFIG_FUSION is not set
343
344#
345# IEEE 1394 (FireWire) support
346#
347# CONFIG_IEEE1394 is not set
348
349#
350# I2O device support
351#
352# CONFIG_I2O is not set
353
354#
355# Networking support
356# 225#
357CONFIG_NET=y 226CONFIG_NET=y
358 227
@@ -361,15 +230,20 @@ CONFIG_NET=y
361# 230#
362CONFIG_PACKET=y 231CONFIG_PACKET=y
363CONFIG_PACKET_MMAP=y 232CONFIG_PACKET_MMAP=y
364CONFIG_NETLINK_DEV=y
365CONFIG_UNIX=y 233CONFIG_UNIX=y
234CONFIG_XFRM=y
235CONFIG_XFRM_USER=m
366CONFIG_NET_KEY=y 236CONFIG_NET_KEY=y
367CONFIG_INET=y 237CONFIG_INET=y
368CONFIG_IP_MULTICAST=y 238CONFIG_IP_MULTICAST=y
369CONFIG_IP_ADVANCED_ROUTER=y 239CONFIG_IP_ADVANCED_ROUTER=y
240CONFIG_ASK_IP_FIB_HASH=y
241# CONFIG_IP_FIB_TRIE is not set
242CONFIG_IP_FIB_HASH=y
370CONFIG_IP_MULTIPLE_TABLES=y 243CONFIG_IP_MULTIPLE_TABLES=y
371CONFIG_IP_ROUTE_FWMARK=y 244CONFIG_IP_ROUTE_FWMARK=y
372CONFIG_IP_ROUTE_MULTIPATH=y 245CONFIG_IP_ROUTE_MULTIPATH=y
246# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
373CONFIG_IP_ROUTE_VERBOSE=y 247CONFIG_IP_ROUTE_VERBOSE=y
374CONFIG_IP_PNP=y 248CONFIG_IP_PNP=y
375CONFIG_IP_PNP_DHCP=y 249CONFIG_IP_PNP_DHCP=y
@@ -387,8 +261,10 @@ CONFIG_INET_AH=m
387CONFIG_INET_ESP=m 261CONFIG_INET_ESP=m
388CONFIG_INET_IPCOMP=m 262CONFIG_INET_IPCOMP=m
389CONFIG_INET_TUNNEL=m 263CONFIG_INET_TUNNEL=m
390CONFIG_IP_TCPDIAG=m 264CONFIG_INET_DIAG=y
391CONFIG_IP_TCPDIAG_IPV6=y 265CONFIG_INET_TCP_DIAG=y
266# CONFIG_TCP_CONG_ADVANCED is not set
267CONFIG_TCP_CONG_BIC=y
392 268
393# 269#
394# IP: Virtual Server Configuration 270# IP: Virtual Server Configuration
@@ -433,6 +309,9 @@ CONFIG_IPV6_TUNNEL=m
433CONFIG_NETFILTER=y 309CONFIG_NETFILTER=y
434# CONFIG_NETFILTER_DEBUG is not set 310# CONFIG_NETFILTER_DEBUG is not set
435CONFIG_BRIDGE_NETFILTER=y 311CONFIG_BRIDGE_NETFILTER=y
312CONFIG_NETFILTER_NETLINK=m
313CONFIG_NETFILTER_NETLINK_QUEUE=m
314CONFIG_NETFILTER_NETLINK_LOG=m
436 315
437# 316#
438# IP: Netfilter Configuration 317# IP: Netfilter Configuration
@@ -440,11 +319,15 @@ CONFIG_BRIDGE_NETFILTER=y
440CONFIG_IP_NF_CONNTRACK=m 319CONFIG_IP_NF_CONNTRACK=m
441CONFIG_IP_NF_CT_ACCT=y 320CONFIG_IP_NF_CT_ACCT=y
442CONFIG_IP_NF_CONNTRACK_MARK=y 321CONFIG_IP_NF_CONNTRACK_MARK=y
322CONFIG_IP_NF_CONNTRACK_EVENTS=y
323CONFIG_IP_NF_CONNTRACK_NETLINK=m
443CONFIG_IP_NF_CT_PROTO_SCTP=m 324CONFIG_IP_NF_CT_PROTO_SCTP=m
444CONFIG_IP_NF_FTP=m 325CONFIG_IP_NF_FTP=m
445CONFIG_IP_NF_IRC=m 326CONFIG_IP_NF_IRC=m
327# CONFIG_IP_NF_NETBIOS_NS is not set
446CONFIG_IP_NF_TFTP=m 328CONFIG_IP_NF_TFTP=m
447CONFIG_IP_NF_AMANDA=m 329CONFIG_IP_NF_AMANDA=m
330CONFIG_IP_NF_PPTP=m
448CONFIG_IP_NF_QUEUE=m 331CONFIG_IP_NF_QUEUE=m
449CONFIG_IP_NF_IPTABLES=m 332CONFIG_IP_NF_IPTABLES=m
450CONFIG_IP_NF_MATCH_LIMIT=m 333CONFIG_IP_NF_MATCH_LIMIT=m
@@ -469,9 +352,12 @@ CONFIG_IP_NF_MATCH_PHYSDEV=m
469CONFIG_IP_NF_MATCH_ADDRTYPE=m 352CONFIG_IP_NF_MATCH_ADDRTYPE=m
470CONFIG_IP_NF_MATCH_REALM=m 353CONFIG_IP_NF_MATCH_REALM=m
471CONFIG_IP_NF_MATCH_SCTP=m 354CONFIG_IP_NF_MATCH_SCTP=m
355CONFIG_IP_NF_MATCH_DCCP=m
472CONFIG_IP_NF_MATCH_COMMENT=m 356CONFIG_IP_NF_MATCH_COMMENT=m
473CONFIG_IP_NF_MATCH_CONNMARK=m 357CONFIG_IP_NF_MATCH_CONNMARK=m
358CONFIG_IP_NF_MATCH_CONNBYTES=m
474CONFIG_IP_NF_MATCH_HASHLIMIT=m 359CONFIG_IP_NF_MATCH_HASHLIMIT=m
360CONFIG_IP_NF_MATCH_STRING=m
475CONFIG_IP_NF_FILTER=m 361CONFIG_IP_NF_FILTER=m
476CONFIG_IP_NF_TARGET_REJECT=m 362CONFIG_IP_NF_TARGET_REJECT=m
477CONFIG_IP_NF_TARGET_LOG=m 363CONFIG_IP_NF_TARGET_LOG=m
@@ -488,12 +374,14 @@ CONFIG_IP_NF_NAT_IRC=m
488CONFIG_IP_NF_NAT_FTP=m 374CONFIG_IP_NF_NAT_FTP=m
489CONFIG_IP_NF_NAT_TFTP=m 375CONFIG_IP_NF_NAT_TFTP=m
490CONFIG_IP_NF_NAT_AMANDA=m 376CONFIG_IP_NF_NAT_AMANDA=m
377CONFIG_IP_NF_NAT_PPTP=m
491CONFIG_IP_NF_MANGLE=m 378CONFIG_IP_NF_MANGLE=m
492CONFIG_IP_NF_TARGET_TOS=m 379CONFIG_IP_NF_TARGET_TOS=m
493CONFIG_IP_NF_TARGET_ECN=m 380CONFIG_IP_NF_TARGET_ECN=m
494CONFIG_IP_NF_TARGET_DSCP=m 381CONFIG_IP_NF_TARGET_DSCP=m
495CONFIG_IP_NF_TARGET_MARK=m 382CONFIG_IP_NF_TARGET_MARK=m
496CONFIG_IP_NF_TARGET_CLASSIFY=m 383CONFIG_IP_NF_TARGET_CLASSIFY=m
384CONFIG_IP_NF_TARGET_TTL=m
497CONFIG_IP_NF_TARGET_CONNMARK=m 385CONFIG_IP_NF_TARGET_CONNMARK=m
498CONFIG_IP_NF_TARGET_CLUSTERIP=m 386CONFIG_IP_NF_TARGET_CLUSTERIP=m
499CONFIG_IP_NF_RAW=m 387CONFIG_IP_NF_RAW=m
@@ -503,7 +391,7 @@ CONFIG_IP_NF_ARPFILTER=m
503CONFIG_IP_NF_ARP_MANGLE=m 391CONFIG_IP_NF_ARP_MANGLE=m
504 392
505# 393#
506# IPv6: Netfilter Configuration 394# IPv6: Netfilter Configuration (EXPERIMENTAL)
507# 395#
508CONFIG_IP6_NF_QUEUE=m 396CONFIG_IP6_NF_QUEUE=m
509CONFIG_IP6_NF_IPTABLES=m 397CONFIG_IP6_NF_IPTABLES=m
@@ -523,8 +411,10 @@ CONFIG_IP6_NF_MATCH_EUI64=m
523CONFIG_IP6_NF_MATCH_PHYSDEV=m 411CONFIG_IP6_NF_MATCH_PHYSDEV=m
524CONFIG_IP6_NF_FILTER=m 412CONFIG_IP6_NF_FILTER=m
525CONFIG_IP6_NF_TARGET_LOG=m 413CONFIG_IP6_NF_TARGET_LOG=m
414CONFIG_IP6_NF_TARGET_REJECT=m
526CONFIG_IP6_NF_MANGLE=m 415CONFIG_IP6_NF_MANGLE=m
527CONFIG_IP6_NF_TARGET_MARK=m 416CONFIG_IP6_NF_TARGET_MARK=m
417CONFIG_IP6_NF_TARGET_HL=m
528CONFIG_IP6_NF_RAW=m 418CONFIG_IP6_NF_RAW=m
529 419
530# 420#
@@ -550,8 +440,11 @@ CONFIG_BRIDGE_EBT_REDIRECT=m
550CONFIG_BRIDGE_EBT_SNAT=m 440CONFIG_BRIDGE_EBT_SNAT=m
551CONFIG_BRIDGE_EBT_LOG=m 441CONFIG_BRIDGE_EBT_LOG=m
552CONFIG_BRIDGE_EBT_ULOG=m 442CONFIG_BRIDGE_EBT_ULOG=m
553CONFIG_XFRM=y 443
554CONFIG_XFRM_USER=m 444#
445# DCCP Configuration (EXPERIMENTAL)
446#
447# CONFIG_IP_DCCP is not set
555 448
556# 449#
557# SCTP Configuration (EXPERIMENTAL) 450# SCTP Configuration (EXPERIMENTAL)
@@ -579,10 +472,6 @@ CONFIG_IPDDP_DECAP=y
579CONFIG_NET_DIVERT=y 472CONFIG_NET_DIVERT=y
580# CONFIG_ECONET is not set 473# CONFIG_ECONET is not set
581# CONFIG_WAN_ROUTER is not set 474# CONFIG_WAN_ROUTER is not set
582
583#
584# QoS and/or fair queueing
585#
586CONFIG_NET_SCHED=y 475CONFIG_NET_SCHED=y
587CONFIG_NET_SCH_CLK_JIFFIES=y 476CONFIG_NET_SCH_CLK_JIFFIES=y
588# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set 477# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
@@ -602,6 +491,7 @@ CONFIG_NET_SCH_INGRESS=m
602CONFIG_NET_QOS=y 491CONFIG_NET_QOS=y
603CONFIG_NET_ESTIMATOR=y 492CONFIG_NET_ESTIMATOR=y
604CONFIG_NET_CLS=y 493CONFIG_NET_CLS=y
494CONFIG_NET_CLS_BASIC=m
605CONFIG_NET_CLS_TCINDEX=m 495CONFIG_NET_CLS_TCINDEX=m
606CONFIG_NET_CLS_ROUTE4=m 496CONFIG_NET_CLS_ROUTE4=m
607CONFIG_NET_CLS_ROUTE=y 497CONFIG_NET_CLS_ROUTE=y
@@ -612,6 +502,7 @@ CONFIG_NET_CLS_IND=y
612# CONFIG_CLS_U32_MARK is not set 502# CONFIG_CLS_U32_MARK is not set
613CONFIG_NET_CLS_RSVP=m 503CONFIG_NET_CLS_RSVP=m
614CONFIG_NET_CLS_RSVP6=m 504CONFIG_NET_CLS_RSVP6=m
505# CONFIG_NET_EMATCH is not set
615# CONFIG_NET_CLS_ACT is not set 506# CONFIG_NET_CLS_ACT is not set
616CONFIG_NET_CLS_POLICE=y 507CONFIG_NET_CLS_POLICE=y
617 508
@@ -619,17 +510,222 @@ CONFIG_NET_CLS_POLICE=y
619# Network testing 510# Network testing
620# 511#
621# CONFIG_NET_PKTGEN is not set 512# CONFIG_NET_PKTGEN is not set
622# CONFIG_NETPOLL is not set
623# CONFIG_NET_POLL_CONTROLLER is not set
624# CONFIG_HAMRADIO is not set 513# CONFIG_HAMRADIO is not set
625# CONFIG_IRDA is not set 514# CONFIG_IRDA is not set
626# CONFIG_BT is not set 515# CONFIG_BT is not set
516CONFIG_IEEE80211=m
517# CONFIG_IEEE80211_DEBUG is not set
518CONFIG_IEEE80211_CRYPT_WEP=m
519CONFIG_IEEE80211_CRYPT_CCMP=m
520CONFIG_IEEE80211_CRYPT_TKIP=m
521
522#
523# Device Drivers
524#
525
526#
527# Generic Driver Options
528#
529CONFIG_STANDALONE=y
530CONFIG_PREVENT_FIRMWARE_BUILD=y
531CONFIG_FW_LOADER=y
532
533#
534# Connector - unified userspace <-> kernelspace linker
535#
536CONFIG_CONNECTOR=m
537
538#
539# Memory Technology Devices (MTD)
540#
541# CONFIG_MTD is not set
542
543#
544# Parallel port support
545#
546# CONFIG_PARPORT is not set
547
548#
549# Plug and Play support
550#
551
552#
553# Block devices
554#
555# CONFIG_BLK_CPQ_DA is not set
556# CONFIG_BLK_CPQ_CISS_DA is not set
557# CONFIG_BLK_DEV_DAC960 is not set
558CONFIG_BLK_DEV_UMEM=m
559# CONFIG_BLK_DEV_COW_COMMON is not set
560CONFIG_BLK_DEV_LOOP=m
561CONFIG_BLK_DEV_CRYPTOLOOP=m
562CONFIG_BLK_DEV_NBD=m
563# CONFIG_BLK_DEV_SX8 is not set
564CONFIG_BLK_DEV_RAM=y
565CONFIG_BLK_DEV_RAM_COUNT=16
566CONFIG_BLK_DEV_RAM_SIZE=4096
567# CONFIG_BLK_DEV_INITRD is not set
568# CONFIG_LBD is not set
569CONFIG_CDROM_PKTCDVD=m
570CONFIG_CDROM_PKTCDVD_BUFFERS=8
571# CONFIG_CDROM_PKTCDVD_WCACHE is not set
572
573#
574# IO Schedulers
575#
576CONFIG_IOSCHED_NOOP=y
577CONFIG_IOSCHED_AS=y
578CONFIG_IOSCHED_DEADLINE=y
579CONFIG_IOSCHED_CFQ=y
580CONFIG_ATA_OVER_ETH=m
581
582#
583# ATA/ATAPI/MFM/RLL support
584#
585CONFIG_IDE=y
586CONFIG_BLK_DEV_IDE=y
587
588#
589# Please see Documentation/ide.txt for help/info on IDE drives
590#
591# CONFIG_BLK_DEV_IDE_SATA is not set
592CONFIG_BLK_DEV_IDEDISK=y
593# CONFIG_IDEDISK_MULTI_MODE is not set
594CONFIG_BLK_DEV_IDECD=y
595# CONFIG_BLK_DEV_IDETAPE is not set
596# CONFIG_BLK_DEV_IDEFLOPPY is not set
597# CONFIG_BLK_DEV_IDESCSI is not set
598# CONFIG_IDE_TASK_IOCTL is not set
599
600#
601# IDE chipset support/bugfixes
602#
603CONFIG_IDE_GENERIC=y
604# CONFIG_BLK_DEV_IDEPCI is not set
605# CONFIG_IDE_ARM is not set
606# CONFIG_BLK_DEV_IDEDMA is not set
607# CONFIG_IDEDMA_AUTO is not set
608# CONFIG_BLK_DEV_HD is not set
609
610#
611# SCSI device support
612#
613CONFIG_RAID_ATTRS=m
614CONFIG_SCSI=y
615CONFIG_SCSI_PROC_FS=y
616
617#
618# SCSI support type (disk, tape, CD-ROM)
619#
620CONFIG_BLK_DEV_SD=y
621CONFIG_CHR_DEV_ST=m
622CONFIG_CHR_DEV_OSST=m
623CONFIG_BLK_DEV_SR=m
624CONFIG_BLK_DEV_SR_VENDOR=y
625CONFIG_CHR_DEV_SG=m
626CONFIG_CHR_DEV_SCH=m
627
628#
629# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
630#
631CONFIG_SCSI_MULTI_LUN=y
632CONFIG_SCSI_CONSTANTS=y
633CONFIG_SCSI_LOGGING=y
634
635#
636# SCSI Transport Attributes
637#
638CONFIG_SCSI_SPI_ATTRS=y
639CONFIG_SCSI_FC_ATTRS=m
640CONFIG_SCSI_ISCSI_ATTRS=m
641CONFIG_SCSI_SAS_ATTRS=m
642
643#
644# SCSI low-level drivers
645#
646# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
647# CONFIG_SCSI_3W_9XXX is not set
648# CONFIG_SCSI_ACARD is not set
649# CONFIG_SCSI_AACRAID is not set
650# CONFIG_SCSI_AIC7XXX is not set
651# CONFIG_SCSI_AIC7XXX_OLD is not set
652# CONFIG_SCSI_AIC79XX is not set
653# CONFIG_SCSI_DPT_I2O is not set
654# CONFIG_MEGARAID_NEWGEN is not set
655# CONFIG_MEGARAID_LEGACY is not set
656# CONFIG_SCSI_SATA is not set
657# CONFIG_SCSI_DMX3191D is not set
658# CONFIG_SCSI_FUTURE_DOMAIN is not set
659# CONFIG_SCSI_IPS is not set
660# CONFIG_SCSI_INITIO is not set
661# CONFIG_SCSI_INIA100 is not set
662CONFIG_SCSI_SYM53C8XX_2=y
663CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
664CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
665CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
666# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
667# CONFIG_SCSI_IPR is not set
668# CONFIG_SCSI_QLOGIC_FC is not set
669# CONFIG_SCSI_QLOGIC_1280 is not set
670CONFIG_SCSI_QLA2XXX=y
671# CONFIG_SCSI_QLA21XX is not set
672# CONFIG_SCSI_QLA22XX is not set
673# CONFIG_SCSI_QLA2300 is not set
674# CONFIG_SCSI_QLA2322 is not set
675# CONFIG_SCSI_QLA6312 is not set
676# CONFIG_SCSI_QLA24XX is not set
677# CONFIG_SCSI_LPFC is not set
678# CONFIG_SCSI_DC395x is not set
679# CONFIG_SCSI_DC390T is not set
680# CONFIG_SCSI_NSP32 is not set
681# CONFIG_SCSI_DEBUG is not set
682
683#
684# Multi-device support (RAID and LVM)
685#
686CONFIG_MD=y
687CONFIG_BLK_DEV_MD=m
688CONFIG_MD_LINEAR=m
689CONFIG_MD_RAID0=m
690CONFIG_MD_RAID1=m
691CONFIG_MD_RAID10=m
692CONFIG_MD_RAID5=m
693CONFIG_MD_RAID6=m
694CONFIG_MD_MULTIPATH=m
695CONFIG_MD_FAULTY=m
696CONFIG_BLK_DEV_DM=m
697CONFIG_DM_CRYPT=m
698CONFIG_DM_SNAPSHOT=m
699CONFIG_DM_MIRROR=m
700CONFIG_DM_ZERO=m
701CONFIG_DM_MULTIPATH=m
702CONFIG_DM_MULTIPATH_EMC=m
703
704#
705# Fusion MPT device support
706#
707# CONFIG_FUSION is not set
708# CONFIG_FUSION_SPI is not set
709# CONFIG_FUSION_FC is not set
710
711#
712# IEEE 1394 (FireWire) support
713#
714# CONFIG_IEEE1394 is not set
715
716#
717# I2O device support
718#
719# CONFIG_I2O is not set
720
721#
722# Network device support
723#
627CONFIG_NETDEVICES=y 724CONFIG_NETDEVICES=y
628CONFIG_DUMMY=m 725CONFIG_DUMMY=m
629CONFIG_BONDING=m 726CONFIG_BONDING=m
630CONFIG_EQUALIZER=m 727CONFIG_EQUALIZER=m
631CONFIG_TUN=m 728CONFIG_TUN=m
632# CONFIG_ETHERTAP is not set
633 729
634# 730#
635# ARCnet devices 731# ARCnet devices
@@ -637,6 +733,21 @@ CONFIG_TUN=m
637# CONFIG_ARCNET is not set 733# CONFIG_ARCNET is not set
638 734
639# 735#
736# PHY device support
737#
738CONFIG_PHYLIB=m
739CONFIG_PHYCONTROL=y
740
741#
742# MII PHY device drivers
743#
744CONFIG_MARVELL_PHY=m
745CONFIG_DAVICOM_PHY=m
746CONFIG_QSEMI_PHY=m
747CONFIG_LXT_PHY=m
748CONFIG_CICADA_PHY=m
749
750#
640# Ethernet (10 or 100Mbit) 751# Ethernet (10 or 100Mbit)
641# 752#
642CONFIG_NET_ETHERNET=y 753CONFIG_NET_ETHERNET=y
@@ -681,13 +792,17 @@ CONFIG_LAN_SAA9730=y
681# CONFIG_HAMACHI is not set 792# CONFIG_HAMACHI is not set
682# CONFIG_YELLOWFIN is not set 793# CONFIG_YELLOWFIN is not set
683# CONFIG_R8169 is not set 794# CONFIG_R8169 is not set
795# CONFIG_SIS190 is not set
796# CONFIG_SKGE is not set
684# CONFIG_SK98LIN is not set 797# CONFIG_SK98LIN is not set
685# CONFIG_VIA_VELOCITY is not set 798# CONFIG_VIA_VELOCITY is not set
686# CONFIG_TIGON3 is not set 799# CONFIG_TIGON3 is not set
800# CONFIG_BNX2 is not set
687 801
688# 802#
689# Ethernet (10000 Mbit) 803# Ethernet (10000 Mbit)
690# 804#
805# CONFIG_CHELSIO_T1 is not set
691# CONFIG_IXGB is not set 806# CONFIG_IXGB is not set
692# CONFIG_S2IO is not set 807# CONFIG_S2IO is not set
693 808
@@ -700,6 +815,8 @@ CONFIG_LAN_SAA9730=y
700# Wireless LAN (non-hamradio) 815# Wireless LAN (non-hamradio)
701# 816#
702# CONFIG_NET_RADIO is not set 817# CONFIG_NET_RADIO is not set
818# CONFIG_IPW_DEBUG is not set
819CONFIG_IPW2200=m
703 820
704# 821#
705# Wan interfaces 822# Wan interfaces
@@ -712,6 +829,8 @@ CONFIG_LAN_SAA9730=y
712# CONFIG_NET_FC is not set 829# CONFIG_NET_FC is not set
713# CONFIG_SHAPER is not set 830# CONFIG_SHAPER is not set
714# CONFIG_NETCONSOLE is not set 831# CONFIG_NETCONSOLE is not set
832# CONFIG_NETPOLL is not set
833# CONFIG_NET_POLL_CONTROLLER is not set
715 834
716# 835#
717# ISDN subsystem 836# ISDN subsystem
@@ -741,19 +860,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
741# CONFIG_INPUT_EVBUG is not set 860# CONFIG_INPUT_EVBUG is not set
742 861
743# 862#
744# Input I/O drivers
745#
746# CONFIG_GAMEPORT is not set
747CONFIG_SOUND_GAMEPORT=y
748CONFIG_SERIO=y
749# CONFIG_SERIO_I8042 is not set
750CONFIG_SERIO_SERPORT=y
751# CONFIG_SERIO_CT82C710 is not set
752# CONFIG_SERIO_PCIPS2 is not set
753CONFIG_SERIO_LIBPS2=y
754CONFIG_SERIO_RAW=y
755
756#
757# Input Device Drivers 863# Input Device Drivers
758# 864#
759# CONFIG_INPUT_KEYBOARD is not set 865# CONFIG_INPUT_KEYBOARD is not set
@@ -766,6 +872,17 @@ CONFIG_MOUSE_SERIAL=m
766# CONFIG_INPUT_MISC is not set 872# CONFIG_INPUT_MISC is not set
767 873
768# 874#
875# Hardware I/O ports
876#
877CONFIG_SERIO=y
878# CONFIG_SERIO_I8042 is not set
879CONFIG_SERIO_SERPORT=y
880# CONFIG_SERIO_PCIPS2 is not set
881CONFIG_SERIO_LIBPS2=y
882CONFIG_SERIO_RAW=y
883# CONFIG_GAMEPORT is not set
884
885#
769# Character devices 886# Character devices
770# 887#
771CONFIG_VT=y 888CONFIG_VT=y
@@ -786,6 +903,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
786# 903#
787CONFIG_SERIAL_CORE=y 904CONFIG_SERIAL_CORE=y
788CONFIG_SERIAL_CORE_CONSOLE=y 905CONFIG_SERIAL_CORE_CONSOLE=y
906# CONFIG_SERIAL_JSM is not set
789CONFIG_UNIX98_PTYS=y 907CONFIG_UNIX98_PTYS=y
790CONFIG_LEGACY_PTYS=y 908CONFIG_LEGACY_PTYS=y
791CONFIG_LEGACY_PTY_COUNT=256 909CONFIG_LEGACY_PTY_COUNT=256
@@ -812,6 +930,11 @@ CONFIG_LEGACY_PTY_COUNT=256
812# CONFIG_RAW_DRIVER is not set 930# CONFIG_RAW_DRIVER is not set
813 931
814# 932#
933# TPM devices
934#
935# CONFIG_TCG_TPM is not set
936
937#
815# I2C support 938# I2C support
816# 939#
817# CONFIG_I2C is not set 940# CONFIG_I2C is not set
@@ -822,10 +945,20 @@ CONFIG_LEGACY_PTY_COUNT=256
822# CONFIG_W1 is not set 945# CONFIG_W1 is not set
823 946
824# 947#
948# Hardware Monitoring support
949#
950# CONFIG_HWMON is not set
951# CONFIG_HWMON_VID is not set
952
953#
825# Misc devices 954# Misc devices
826# 955#
827 956
828# 957#
958# Multimedia Capabilities Port drivers
959#
960
961#
829# Multimedia devices 962# Multimedia devices
830# 963#
831# CONFIG_VIDEO_DEV is not set 964# CONFIG_VIDEO_DEV is not set
@@ -845,7 +978,6 @@ CONFIG_LEGACY_PTY_COUNT=256
845# 978#
846# CONFIG_VGA_CONSOLE is not set 979# CONFIG_VGA_CONSOLE is not set
847CONFIG_DUMMY_CONSOLE=y 980CONFIG_DUMMY_CONSOLE=y
848# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
849 981
850# 982#
851# Sound 983# Sound
@@ -855,13 +987,9 @@ CONFIG_DUMMY_CONSOLE=y
855# 987#
856# USB support 988# USB support
857# 989#
858# CONFIG_USB is not set
859CONFIG_USB_ARCH_HAS_HCD=y 990CONFIG_USB_ARCH_HAS_HCD=y
860CONFIG_USB_ARCH_HAS_OHCI=y 991CONFIG_USB_ARCH_HAS_OHCI=y
861 992# CONFIG_USB is not set
862#
863# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
864#
865 993
866# 994#
867# USB Gadget Support 995# USB Gadget Support
@@ -879,10 +1007,15 @@ CONFIG_USB_ARCH_HAS_OHCI=y
879# CONFIG_INFINIBAND is not set 1007# CONFIG_INFINIBAND is not set
880 1008
881# 1009#
1010# SN Devices
1011#
1012
1013#
882# File systems 1014# File systems
883# 1015#
884CONFIG_EXT2_FS=y 1016CONFIG_EXT2_FS=y
885# CONFIG_EXT2_FS_XATTR is not set 1017# CONFIG_EXT2_FS_XATTR is not set
1018# CONFIG_EXT2_FS_XIP is not set
886CONFIG_EXT3_FS=y 1019CONFIG_EXT3_FS=y
887CONFIG_EXT3_FS_XATTR=y 1020CONFIG_EXT3_FS_XATTR=y
888# CONFIG_EXT3_FS_POSIX_ACL is not set 1021# CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -903,12 +1036,14 @@ CONFIG_JFS_SECURITY=y
903# CONFIG_JFS_STATISTICS is not set 1036# CONFIG_JFS_STATISTICS is not set
904CONFIG_FS_POSIX_ACL=y 1037CONFIG_FS_POSIX_ACL=y
905CONFIG_XFS_FS=m 1038CONFIG_XFS_FS=m
906# CONFIG_XFS_RT is not set 1039CONFIG_XFS_EXPORT=y
907CONFIG_XFS_QUOTA=y 1040CONFIG_XFS_QUOTA=m
908CONFIG_XFS_SECURITY=y 1041CONFIG_XFS_SECURITY=y
909CONFIG_XFS_POSIX_ACL=y 1042CONFIG_XFS_POSIX_ACL=y
1043# CONFIG_XFS_RT is not set
910CONFIG_MINIX_FS=m 1044CONFIG_MINIX_FS=m
911CONFIG_ROMFS_FS=m 1045CONFIG_ROMFS_FS=m
1046CONFIG_INOTIFY=y
912CONFIG_QUOTA=y 1047CONFIG_QUOTA=y
913# CONFIG_QFMT_V1 is not set 1048# CONFIG_QFMT_V1 is not set
914CONFIG_QFMT_V2=y 1049CONFIG_QFMT_V2=y
@@ -916,6 +1051,7 @@ CONFIG_QUOTACTL=y
916CONFIG_DNOTIFY=y 1051CONFIG_DNOTIFY=y
917CONFIG_AUTOFS_FS=y 1052CONFIG_AUTOFS_FS=y
918# CONFIG_AUTOFS4_FS is not set 1053# CONFIG_AUTOFS4_FS is not set
1054CONFIG_FUSE_FS=m
919 1055
920# 1056#
921# CD-ROM/DVD Filesystems 1057# CD-ROM/DVD Filesystems
@@ -943,12 +1079,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
943CONFIG_PROC_FS=y 1079CONFIG_PROC_FS=y
944CONFIG_PROC_KCORE=y 1080CONFIG_PROC_KCORE=y
945CONFIG_SYSFS=y 1081CONFIG_SYSFS=y
946# CONFIG_DEVFS_FS is not set
947CONFIG_DEVPTS_FS_XATTR=y
948CONFIG_DEVPTS_FS_SECURITY=y
949# CONFIG_TMPFS is not set 1082# CONFIG_TMPFS is not set
950# CONFIG_HUGETLB_PAGE is not set 1083# CONFIG_HUGETLB_PAGE is not set
951CONFIG_RAMFS=y 1084CONFIG_RAMFS=y
1085CONFIG_RELAYFS_FS=m
952 1086
953# 1087#
954# Miscellaneous filesystems 1088# Miscellaneous filesystems
@@ -974,16 +1108,19 @@ CONFIG_UFS_FS=m
974# 1108#
975CONFIG_NFS_FS=y 1109CONFIG_NFS_FS=y
976CONFIG_NFS_V3=y 1110CONFIG_NFS_V3=y
1111# CONFIG_NFS_V3_ACL is not set
977# CONFIG_NFS_V4 is not set 1112# CONFIG_NFS_V4 is not set
978# CONFIG_NFS_DIRECTIO is not set 1113# CONFIG_NFS_DIRECTIO is not set
979CONFIG_NFSD=y 1114CONFIG_NFSD=y
980CONFIG_NFSD_V3=y 1115CONFIG_NFSD_V3=y
1116# CONFIG_NFSD_V3_ACL is not set
981# CONFIG_NFSD_V4 is not set 1117# CONFIG_NFSD_V4 is not set
982# CONFIG_NFSD_TCP is not set 1118# CONFIG_NFSD_TCP is not set
983CONFIG_ROOT_NFS=y 1119CONFIG_ROOT_NFS=y
984CONFIG_LOCKD=y 1120CONFIG_LOCKD=y
985CONFIG_LOCKD_V4=y 1121CONFIG_LOCKD_V4=y
986CONFIG_EXPORTFS=y 1122CONFIG_EXPORTFS=y
1123CONFIG_NFS_COMMON=y
987CONFIG_SUNRPC=y 1124CONFIG_SUNRPC=y
988# CONFIG_RPCSEC_GSS_KRB5 is not set 1125# CONFIG_RPCSEC_GSS_KRB5 is not set
989# CONFIG_RPCSEC_GSS_SPKM3 is not set 1126# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -992,6 +1129,7 @@ CONFIG_SUNRPC=y
992# CONFIG_NCP_FS is not set 1129# CONFIG_NCP_FS is not set
993# CONFIG_CODA_FS is not set 1130# CONFIG_CODA_FS is not set
994# CONFIG_AFS_FS is not set 1131# CONFIG_AFS_FS is not set
1132# CONFIG_9P_FS is not set
995 1133
996# 1134#
997# Partition Types 1135# Partition Types
@@ -1051,7 +1189,9 @@ CONFIG_NLS_UTF8=m
1051# 1189#
1052# Kernel hacking 1190# Kernel hacking
1053# 1191#
1192# CONFIG_PRINTK_TIME is not set
1054# CONFIG_DEBUG_KERNEL is not set 1193# CONFIG_DEBUG_KERNEL is not set
1194CONFIG_LOG_BUF_SHIFT=14
1055CONFIG_CROSSCOMPILE=y 1195CONFIG_CROSSCOMPILE=y
1056CONFIG_CMDLINE="" 1196CONFIG_CMDLINE=""
1057 1197
@@ -1073,6 +1213,7 @@ CONFIG_CRYPTO_SHA1=m
1073CONFIG_CRYPTO_SHA256=m 1213CONFIG_CRYPTO_SHA256=m
1074CONFIG_CRYPTO_SHA512=m 1214CONFIG_CRYPTO_SHA512=m
1075CONFIG_CRYPTO_WP512=m 1215CONFIG_CRYPTO_WP512=m
1216CONFIG_CRYPTO_TGR192=m
1076CONFIG_CRYPTO_DES=m 1217CONFIG_CRYPTO_DES=m
1077CONFIG_CRYPTO_BLOWFISH=m 1218CONFIG_CRYPTO_BLOWFISH=m
1078CONFIG_CRYPTO_TWOFISH=m 1219CONFIG_CRYPTO_TWOFISH=m
@@ -1097,9 +1238,12 @@ CONFIG_CRYPTO_CRC32C=m
1097# Library routines 1238# Library routines
1098# 1239#
1099# CONFIG_CRC_CCITT is not set 1240# CONFIG_CRC_CCITT is not set
1241CONFIG_CRC16=m
1100CONFIG_CRC32=y 1242CONFIG_CRC32=y
1101CONFIG_LIBCRC32C=m 1243CONFIG_LIBCRC32C=m
1102CONFIG_ZLIB_INFLATE=m 1244CONFIG_ZLIB_INFLATE=m
1103CONFIG_ZLIB_DEFLATE=m 1245CONFIG_ZLIB_DEFLATE=m
1104CONFIG_GENERIC_HARDIRQS=y 1246CONFIG_TEXTSEARCH=y
1105CONFIG_GENERIC_IRQ_PROBE=y 1247CONFIG_TEXTSEARCH_KMP=m
1248CONFIG_TEXTSEARCH_BM=m
1249CONFIG_TEXTSEARCH_FSM=m
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
new file mode 100644
index 000000000000..25e8a08e68be
--- /dev/null
+++ b/arch/mips/configs/bigsur_defconfig
@@ -0,0 +1,881 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.14-rc2
4# Thu Oct 20 22:25:17 2005
5#
6CONFIG_MIPS=y
7
8#
9# Code maturity level options
10#
11CONFIG_EXPERIMENTAL=y
12CONFIG_CLEAN_COMPILE=y
13CONFIG_LOCK_KERNEL=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
15
16#
17# General setup
18#
19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
21CONFIG_SWAP=y
22CONFIG_SYSVIPC=y
23# CONFIG_POSIX_MQUEUE is not set
24# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set
27# CONFIG_HOTPLUG is not set
28CONFIG_KOBJECT_UEVENT=y
29CONFIG_IKCONFIG=y
30CONFIG_IKCONFIG_PROC=y
31# CONFIG_CPUSETS is not set
32CONFIG_INITRAMFS_SOURCE=""
33CONFIG_EMBEDDED=y
34CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_ALL is not set
36# CONFIG_KALLSYMS_EXTRA_PASS is not set
37CONFIG_PRINTK=y
38CONFIG_BUG=y
39CONFIG_BASE_FULL=y
40CONFIG_FUTEX=y
41CONFIG_EPOLL=y
42# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
43CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0
45CONFIG_CC_ALIGN_LABELS=0
46CONFIG_CC_ALIGN_LOOPS=0
47CONFIG_CC_ALIGN_JUMPS=0
48# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58CONFIG_MODVERSIONS=y
59CONFIG_MODULE_SRCVERSION_ALL=y
60CONFIG_KMOD=y
61CONFIG_STOP_MACHINE=y
62
63#
64# Machine selection
65#
66# CONFIG_MIPS_MTX1 is not set
67# CONFIG_MIPS_BOSPORUS is not set
68# CONFIG_MIPS_PB1000 is not set
69# CONFIG_MIPS_PB1100 is not set
70# CONFIG_MIPS_PB1500 is not set
71# CONFIG_MIPS_PB1550 is not set
72# CONFIG_MIPS_PB1200 is not set
73# CONFIG_MIPS_DB1000 is not set
74# CONFIG_MIPS_DB1100 is not set
75# CONFIG_MIPS_DB1500 is not set
76# CONFIG_MIPS_DB1550 is not set
77# CONFIG_MIPS_DB1200 is not set
78# CONFIG_MIPS_MIRAGE is not set
79# CONFIG_MIPS_COBALT is not set
80# CONFIG_MACH_DECSTATION is not set
81# CONFIG_MIPS_EV64120 is not set
82# CONFIG_MIPS_EV96100 is not set
83# CONFIG_MIPS_IVR is not set
84# CONFIG_MIPS_ITE8172 is not set
85# CONFIG_MACH_JAZZ is not set
86# CONFIG_LASAT is not set
87# CONFIG_MIPS_ATLAS is not set
88# CONFIG_MIPS_MALTA is not set
89# CONFIG_MIPS_SEAD is not set
90# CONFIG_MIPS_SIM is not set
91# CONFIG_MOMENCO_JAGUAR_ATX is not set
92# CONFIG_MOMENCO_OCELOT is not set
93# CONFIG_MOMENCO_OCELOT_3 is not set
94# CONFIG_MOMENCO_OCELOT_C is not set
95# CONFIG_MOMENCO_OCELOT_G is not set
96# CONFIG_MIPS_XXS1500 is not set
97# CONFIG_PNX8550_V2PCI is not set
98# CONFIG_PNX8550_JBS is not set
99# CONFIG_DDB5074 is not set
100# CONFIG_DDB5476 is not set
101# CONFIG_DDB5477 is not set
102# CONFIG_MACH_VR41XX is not set
103# CONFIG_PMC_YOSEMITE is not set
104# CONFIG_QEMU is not set
105# CONFIG_SGI_IP22 is not set
106# CONFIG_SGI_IP27 is not set
107# CONFIG_SGI_IP32 is not set
108CONFIG_SIBYTE_BIGSUR=y
109# CONFIG_SIBYTE_SWARM is not set
110# CONFIG_SIBYTE_SENTOSA is not set
111# CONFIG_SIBYTE_RHONE is not set
112# CONFIG_SIBYTE_CARMEL is not set
113# CONFIG_SIBYTE_PTSWARM is not set
114# CONFIG_SIBYTE_LITTLESUR is not set
115# CONFIG_SIBYTE_CRHINE is not set
116# CONFIG_SIBYTE_CRHONE is not set
117# CONFIG_SNI_RM200_PCI is not set
118# CONFIG_TOSHIBA_JMR3927 is not set
119# CONFIG_TOSHIBA_RBTX4927 is not set
120# CONFIG_TOSHIBA_RBTX4938 is not set
121CONFIG_SIBYTE_BCM1x80=y
122CONFIG_SIBYTE_SB1xxx_SOC=y
123# CONFIG_CPU_SB1_PASS_1 is not set
124# CONFIG_CPU_SB1_PASS_2_1250 is not set
125# CONFIG_CPU_SB1_PASS_2_2 is not set
126# CONFIG_CPU_SB1_PASS_4 is not set
127# CONFIG_CPU_SB1_PASS_2_112x is not set
128# CONFIG_CPU_SB1_PASS_3 is not set
129# CONFIG_SIMULATION is not set
130# CONFIG_CONFIG_SB1_CEX_ALWAYS_FATAL is not set
131# CONFIG_CONFIG_SB1_CERR_STALL is not set
132CONFIG_SIBYTE_CFE=y
133# CONFIG_SIBYTE_CFE_CONSOLE is not set
134# CONFIG_SIBYTE_BUS_WATCHER is not set
135# CONFIG_SIBYTE_SB1250_PROF is not set
136# CONFIG_SIBYTE_TBPROF is not set
137CONFIG_RWSEM_GENERIC_SPINLOCK=y
138CONFIG_GENERIC_CALIBRATE_DELAY=y
139CONFIG_DMA_COHERENT=y
140CONFIG_CPU_BIG_ENDIAN=y
141# CONFIG_CPU_LITTLE_ENDIAN is not set
142CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
143CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
144CONFIG_SWAP_IO_SPACE=y
145CONFIG_BOOT_ELF32=y
146CONFIG_MIPS_L1_CACHE_SHIFT=5
147
148#
149# CPU selection
150#
151# CONFIG_CPU_MIPS32_R1 is not set
152# CONFIG_CPU_MIPS32_R2 is not set
153# CONFIG_CPU_MIPS64_R1 is not set
154# CONFIG_CPU_MIPS64_R2 is not set
155# CONFIG_CPU_R3000 is not set
156# CONFIG_CPU_TX39XX is not set
157# CONFIG_CPU_VR41XX is not set
158# CONFIG_CPU_R4300 is not set
159# CONFIG_CPU_R4X00 is not set
160# CONFIG_CPU_TX49XX is not set
161# CONFIG_CPU_R5000 is not set
162# CONFIG_CPU_R5432 is not set
163# CONFIG_CPU_R6000 is not set
164# CONFIG_CPU_NEVADA is not set
165# CONFIG_CPU_R8000 is not set
166# CONFIG_CPU_R10000 is not set
167# CONFIG_CPU_RM7000 is not set
168# CONFIG_CPU_RM9000 is not set
169CONFIG_CPU_SB1=y
170CONFIG_SYS_HAS_CPU_SB1=y
171CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
172CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
173CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
174CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
175
176#
177# Kernel type
178#
179# CONFIG_32BIT is not set
180CONFIG_64BIT=y
181CONFIG_PAGE_SIZE_4KB=y
182# CONFIG_PAGE_SIZE_8KB is not set
183# CONFIG_PAGE_SIZE_16KB is not set
184# CONFIG_PAGE_SIZE_64KB is not set
185# CONFIG_SIBYTE_DMA_PAGEOPS is not set
186# CONFIG_MIPS_MT is not set
187CONFIG_CPU_HAS_LLSC=y
188CONFIG_CPU_HAS_LLDSCD=y
189CONFIG_CPU_HAS_SYNC=y
190CONFIG_GENERIC_HARDIRQS=y
191CONFIG_GENERIC_IRQ_PROBE=y
192CONFIG_CPU_SUPPORTS_HIGHMEM=y
193CONFIG_ARCH_FLATMEM_ENABLE=y
194CONFIG_SELECT_MEMORY_MODEL=y
195CONFIG_FLATMEM_MANUAL=y
196# CONFIG_DISCONTIGMEM_MANUAL is not set
197# CONFIG_SPARSEMEM_MANUAL is not set
198CONFIG_FLATMEM=y
199CONFIG_FLAT_NODE_MEM_MAP=y
200# CONFIG_SPARSEMEM_STATIC is not set
201CONFIG_SMP=y
202CONFIG_NR_CPUS=4
203CONFIG_PREEMPT_NONE=y
204# CONFIG_PREEMPT_VOLUNTARY is not set
205# CONFIG_PREEMPT is not set
206# CONFIG_PREEMPT_BKL is not set
207
208#
209# Bus options (PCI, PCMCIA, EISA, ISA, TC)
210#
211CONFIG_HW_HAS_PCI=y
212CONFIG_PCI=y
213CONFIG_PCI_DOMAINS=y
214CONFIG_PCI_LEGACY_PROC=y
215CONFIG_PCI_DEBUG=y
216CONFIG_MMU=y
217
218#
219# PCCARD (PCMCIA/CardBus) support
220#
221# CONFIG_PCCARD is not set
222
223#
224# PCI Hotplug Support
225#
226# CONFIG_HOTPLUG_PCI is not set
227
228#
229# Executable file formats
230#
231CONFIG_BINFMT_ELF=y
232# CONFIG_BINFMT_MISC is not set
233CONFIG_BUILD_ELF64=y
234CONFIG_MIPS32_COMPAT=y
235CONFIG_COMPAT=y
236CONFIG_MIPS32_O32=y
237# CONFIG_MIPS32_N32 is not set
238CONFIG_BINFMT_ELF32=y
239
240#
241# Networking
242#
243CONFIG_NET=y
244
245#
246# Networking options
247#
248CONFIG_PACKET=y
249CONFIG_PACKET_MMAP=y
250CONFIG_UNIX=y
251CONFIG_XFRM=y
252CONFIG_XFRM_USER=m
253CONFIG_NET_KEY=y
254CONFIG_INET=y
255# CONFIG_IP_MULTICAST is not set
256# CONFIG_IP_ADVANCED_ROUTER is not set
257CONFIG_IP_FIB_HASH=y
258CONFIG_IP_PNP=y
259CONFIG_IP_PNP_DHCP=y
260CONFIG_IP_PNP_BOOTP=y
261# CONFIG_IP_PNP_RARP is not set
262# CONFIG_NET_IPIP is not set
263# CONFIG_NET_IPGRE is not set
264# CONFIG_ARPD is not set
265# CONFIG_SYN_COOKIES is not set
266# CONFIG_INET_AH is not set
267# CONFIG_INET_ESP is not set
268# CONFIG_INET_IPCOMP is not set
269CONFIG_INET_TUNNEL=m
270CONFIG_INET_DIAG=y
271CONFIG_INET_TCP_DIAG=y
272# CONFIG_TCP_CONG_ADVANCED is not set
273CONFIG_TCP_CONG_BIC=y
274# CONFIG_IPV6 is not set
275# CONFIG_NETFILTER is not set
276
277#
278# DCCP Configuration (EXPERIMENTAL)
279#
280# CONFIG_IP_DCCP is not set
281
282#
283# SCTP Configuration (EXPERIMENTAL)
284#
285# CONFIG_IP_SCTP is not set
286# CONFIG_ATM is not set
287# CONFIG_BRIDGE is not set
288# CONFIG_VLAN_8021Q is not set
289# CONFIG_DECNET is not set
290# CONFIG_LLC2 is not set
291# CONFIG_IPX is not set
292# CONFIG_ATALK is not set
293# CONFIG_X25 is not set
294# CONFIG_LAPB is not set
295# CONFIG_NET_DIVERT is not set
296# CONFIG_ECONET is not set
297# CONFIG_WAN_ROUTER is not set
298# CONFIG_NET_SCHED is not set
299# CONFIG_NET_CLS_ROUTE is not set
300
301#
302# Network testing
303#
304# CONFIG_NET_PKTGEN is not set
305# CONFIG_HAMRADIO is not set
306# CONFIG_IRDA is not set
307# CONFIG_BT is not set
308# CONFIG_IEEE80211 is not set
309
310#
311# Device Drivers
312#
313
314#
315# Generic Driver Options
316#
317CONFIG_STANDALONE=y
318CONFIG_PREVENT_FIRMWARE_BUILD=y
319# CONFIG_FW_LOADER is not set
320# CONFIG_DEBUG_DRIVER is not set
321
322#
323# Connector - unified userspace <-> kernelspace linker
324#
325# CONFIG_CONNECTOR is not set
326
327#
328# Memory Technology Devices (MTD)
329#
330# CONFIG_MTD is not set
331
332#
333# Parallel port support
334#
335# CONFIG_PARPORT is not set
336
337#
338# Plug and Play support
339#
340
341#
342# Block devices
343#
344# CONFIG_BLK_CPQ_DA is not set
345# CONFIG_BLK_CPQ_CISS_DA is not set
346# CONFIG_BLK_DEV_DAC960 is not set
347# CONFIG_BLK_DEV_UMEM is not set
348# CONFIG_BLK_DEV_COW_COMMON is not set
349CONFIG_BLK_DEV_LOOP=m
350# CONFIG_BLK_DEV_CRYPTOLOOP is not set
351CONFIG_BLK_DEV_NBD=m
352# CONFIG_BLK_DEV_SX8 is not set
353# CONFIG_BLK_DEV_RAM is not set
354CONFIG_BLK_DEV_RAM_COUNT=16
355# CONFIG_CDROM_PKTCDVD is not set
356
357#
358# IO Schedulers
359#
360CONFIG_IOSCHED_NOOP=y
361CONFIG_IOSCHED_AS=y
362CONFIG_IOSCHED_DEADLINE=y
363CONFIG_IOSCHED_CFQ=y
364# CONFIG_ATA_OVER_ETH is not set
365
366#
367# ATA/ATAPI/MFM/RLL support
368#
369CONFIG_IDE=y
370CONFIG_BLK_DEV_IDE=y
371
372#
373# Please see Documentation/ide.txt for help/info on IDE drives
374#
375# CONFIG_BLK_DEV_IDE_SATA is not set
376CONFIG_BLK_DEV_IDEDISK=y
377# CONFIG_IDEDISK_MULTI_MODE is not set
378CONFIG_BLK_DEV_IDECD=y
379CONFIG_BLK_DEV_IDETAPE=y
380CONFIG_BLK_DEV_IDEFLOPPY=y
381# CONFIG_IDE_TASK_IOCTL is not set
382
383#
384# IDE chipset support/bugfixes
385#
386CONFIG_IDE_GENERIC=y
387# CONFIG_BLK_DEV_IDEPCI is not set
388# CONFIG_BLK_DEV_IDE_SWARM is not set
389# CONFIG_IDE_ARM is not set
390# CONFIG_BLK_DEV_IDEDMA is not set
391# CONFIG_IDEDMA_AUTO is not set
392# CONFIG_BLK_DEV_HD is not set
393
394#
395# SCSI device support
396#
397# CONFIG_RAID_ATTRS is not set
398# CONFIG_SCSI is not set
399
400#
401# Multi-device support (RAID and LVM)
402#
403# CONFIG_MD is not set
404
405#
406# Fusion MPT device support
407#
408# CONFIG_FUSION is not set
409
410#
411# IEEE 1394 (FireWire) support
412#
413# CONFIG_IEEE1394 is not set
414
415#
416# I2O device support
417#
418# CONFIG_I2O is not set
419
420#
421# Network device support
422#
423CONFIG_NETDEVICES=y
424# CONFIG_DUMMY is not set
425# CONFIG_BONDING is not set
426# CONFIG_EQUALIZER is not set
427# CONFIG_TUN is not set
428
429#
430# ARCnet devices
431#
432# CONFIG_ARCNET is not set
433
434#
435# PHY device support
436#
437# CONFIG_PHYLIB is not set
438
439#
440# Ethernet (10 or 100Mbit)
441#
442CONFIG_NET_ETHERNET=y
443CONFIG_MII=y
444# CONFIG_HAPPYMEAL is not set
445# CONFIG_SUNGEM is not set
446# CONFIG_NET_VENDOR_3COM is not set
447
448#
449# Tulip family network device support
450#
451# CONFIG_NET_TULIP is not set
452# CONFIG_HP100 is not set
453# CONFIG_NET_PCI is not set
454
455#
456# Ethernet (1000 Mbit)
457#
458# CONFIG_ACENIC is not set
459# CONFIG_DL2K is not set
460# CONFIG_E1000 is not set
461# CONFIG_NS83820 is not set
462# CONFIG_HAMACHI is not set
463# CONFIG_YELLOWFIN is not set
464# CONFIG_R8169 is not set
465CONFIG_NET_SB1250_MAC=y
466# CONFIG_SIS190 is not set
467# CONFIG_SKGE is not set
468# CONFIG_SK98LIN is not set
469# CONFIG_TIGON3 is not set
470# CONFIG_BNX2 is not set
471
472#
473# Ethernet (10000 Mbit)
474#
475# CONFIG_CHELSIO_T1 is not set
476# CONFIG_IXGB is not set
477# CONFIG_S2IO is not set
478
479#
480# Token Ring devices
481#
482# CONFIG_TR is not set
483
484#
485# Wireless LAN (non-hamradio)
486#
487# CONFIG_NET_RADIO is not set
488
489#
490# Wan interfaces
491#
492# CONFIG_WAN is not set
493# CONFIG_FDDI is not set
494# CONFIG_HIPPI is not set
495# CONFIG_PPP is not set
496# CONFIG_SLIP is not set
497# CONFIG_SHAPER is not set
498# CONFIG_NETCONSOLE is not set
499# CONFIG_NETPOLL is not set
500# CONFIG_NET_POLL_CONTROLLER is not set
501
502#
503# ISDN subsystem
504#
505# CONFIG_ISDN is not set
506
507#
508# Telephony Support
509#
510# CONFIG_PHONE is not set
511
512#
513# Input device support
514#
515# CONFIG_INPUT is not set
516
517#
518# Hardware I/O ports
519#
520CONFIG_SERIO=y
521# CONFIG_SERIO_I8042 is not set
522CONFIG_SERIO_SERPORT=y
523# CONFIG_SERIO_PCIPS2 is not set
524# CONFIG_SERIO_LIBPS2 is not set
525CONFIG_SERIO_RAW=m
526# CONFIG_GAMEPORT is not set
527
528#
529# Character devices
530#
531# CONFIG_VT is not set
532CONFIG_SERIAL_NONSTANDARD=y
533# CONFIG_ROCKETPORT is not set
534# CONFIG_CYCLADES is not set
535# CONFIG_DIGIEPCA is not set
536# CONFIG_MOXA_SMARTIO is not set
537# CONFIG_ISI is not set
538# CONFIG_SYNCLINKMP is not set
539# CONFIG_N_HDLC is not set
540# CONFIG_SPECIALIX is not set
541# CONFIG_SX is not set
542# CONFIG_STALDRV is not set
543CONFIG_SIBYTE_SB1250_DUART=y
544CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y
545
546#
547# Serial drivers
548#
549# CONFIG_SERIAL_8250 is not set
550
551#
552# Non-8250 serial port support
553#
554# CONFIG_SERIAL_JSM is not set
555CONFIG_UNIX98_PTYS=y
556CONFIG_LEGACY_PTYS=y
557CONFIG_LEGACY_PTY_COUNT=256
558
559#
560# IPMI
561#
562# CONFIG_IPMI_HANDLER is not set
563
564#
565# Watchdog Cards
566#
567# CONFIG_WATCHDOG is not set
568# CONFIG_RTC is not set
569CONFIG_GEN_RTC=y
570# CONFIG_GEN_RTC_X is not set
571# CONFIG_DTLK is not set
572# CONFIG_R3964 is not set
573# CONFIG_APPLICOM is not set
574
575#
576# Ftape, the floppy tape device driver
577#
578# CONFIG_DRM is not set
579# CONFIG_RAW_DRIVER is not set
580
581#
582# TPM devices
583#
584# CONFIG_TCG_TPM is not set
585
586#
587# I2C support
588#
589CONFIG_I2C=y
590CONFIG_I2C_CHARDEV=y
591
592#
593# I2C Algorithms
594#
595# CONFIG_I2C_ALGOBIT is not set
596# CONFIG_I2C_ALGOPCF is not set
597# CONFIG_I2C_ALGOPCA is not set
598CONFIG_I2C_ALGO_SIBYTE=y
599
600#
601# I2C Hardware Bus support
602#
603# CONFIG_I2C_ALI1535 is not set
604# CONFIG_I2C_ALI1563 is not set
605# CONFIG_I2C_ALI15X3 is not set
606# CONFIG_I2C_AMD756 is not set
607# CONFIG_I2C_AMD8111 is not set
608# CONFIG_I2C_I801 is not set
609# CONFIG_I2C_I810 is not set
610# CONFIG_I2C_PIIX4 is not set
611# CONFIG_I2C_NFORCE2 is not set
612# CONFIG_I2C_PARPORT_LIGHT is not set
613# CONFIG_I2C_PROSAVAGE is not set
614# CONFIG_I2C_SAVAGE4 is not set
615CONFIG_I2C_SIBYTE=y
616# CONFIG_SCx200_ACB is not set
617# CONFIG_I2C_SIS5595 is not set
618# CONFIG_I2C_SIS630 is not set
619# CONFIG_I2C_SIS96X is not set
620# CONFIG_I2C_STUB is not set
621# CONFIG_I2C_VIA is not set
622# CONFIG_I2C_VIAPRO is not set
623# CONFIG_I2C_VOODOO3 is not set
624# CONFIG_I2C_PCA_ISA is not set
625
626#
627# Miscellaneous I2C Chip support
628#
629CONFIG_SENSORS_DS1337=y
630CONFIG_SENSORS_DS1374=y
631CONFIG_SENSORS_EEPROM=y
632CONFIG_SENSORS_PCF8574=y
633CONFIG_SENSORS_PCA9539=y
634CONFIG_SENSORS_PCF8591=y
635CONFIG_SENSORS_RTC8564=y
636CONFIG_SENSORS_MAX6875=y
637CONFIG_I2C_DEBUG_CORE=y
638CONFIG_I2C_DEBUG_ALGO=y
639CONFIG_I2C_DEBUG_BUS=y
640CONFIG_I2C_DEBUG_CHIP=y
641
642#
643# Dallas's 1-wire bus
644#
645# CONFIG_W1 is not set
646
647#
648# Hardware Monitoring support
649#
650# CONFIG_HWMON is not set
651# CONFIG_HWMON_VID is not set
652
653#
654# Misc devices
655#
656
657#
658# Multimedia Capabilities Port drivers
659#
660
661#
662# Multimedia devices
663#
664# CONFIG_VIDEO_DEV is not set
665
666#
667# Digital Video Broadcasting Devices
668#
669# CONFIG_DVB is not set
670
671#
672# Graphics support
673#
674# CONFIG_FB is not set
675
676#
677# Sound
678#
679# CONFIG_SOUND is not set
680
681#
682# USB support
683#
684CONFIG_USB_ARCH_HAS_HCD=y
685CONFIG_USB_ARCH_HAS_OHCI=y
686# CONFIG_USB is not set
687
688#
689# USB Gadget Support
690#
691# CONFIG_USB_GADGET is not set
692
693#
694# MMC/SD Card support
695#
696# CONFIG_MMC is not set
697
698#
699# InfiniBand support
700#
701# CONFIG_INFINIBAND is not set
702
703#
704# SN Devices
705#
706
707#
708# File systems
709#
710CONFIG_EXT2_FS=y
711CONFIG_EXT2_FS_XATTR=y
712CONFIG_EXT2_FS_POSIX_ACL=y
713CONFIG_EXT2_FS_SECURITY=y
714# CONFIG_EXT2_FS_XIP is not set
715# CONFIG_EXT3_FS is not set
716# CONFIG_JBD is not set
717CONFIG_FS_MBCACHE=y
718# CONFIG_REISERFS_FS is not set
719# CONFIG_JFS_FS is not set
720CONFIG_FS_POSIX_ACL=y
721# CONFIG_XFS_FS is not set
722# CONFIG_MINIX_FS is not set
723# CONFIG_ROMFS_FS is not set
724CONFIG_INOTIFY=y
725# CONFIG_QUOTA is not set
726CONFIG_DNOTIFY=y
727# CONFIG_AUTOFS_FS is not set
728# CONFIG_AUTOFS4_FS is not set
729# CONFIG_FUSE_FS is not set
730
731#
732# CD-ROM/DVD Filesystems
733#
734# CONFIG_ISO9660_FS is not set
735# CONFIG_UDF_FS is not set
736
737#
738# DOS/FAT/NT Filesystems
739#
740# CONFIG_MSDOS_FS is not set
741# CONFIG_VFAT_FS is not set
742# CONFIG_NTFS_FS is not set
743
744#
745# Pseudo filesystems
746#
747CONFIG_PROC_FS=y
748CONFIG_PROC_KCORE=y
749CONFIG_SYSFS=y
750# CONFIG_TMPFS is not set
751# CONFIG_HUGETLB_PAGE is not set
752CONFIG_RAMFS=y
753# CONFIG_RELAYFS_FS is not set
754
755#
756# Miscellaneous filesystems
757#
758# CONFIG_ADFS_FS is not set
759# CONFIG_AFFS_FS is not set
760# CONFIG_HFS_FS is not set
761# CONFIG_HFSPLUS_FS is not set
762# CONFIG_BEFS_FS is not set
763# CONFIG_BFS_FS is not set
764# CONFIG_EFS_FS is not set
765# CONFIG_CRAMFS is not set
766# CONFIG_VXFS_FS is not set
767# CONFIG_HPFS_FS is not set
768# CONFIG_QNX4FS_FS is not set
769# CONFIG_SYSV_FS is not set
770# CONFIG_UFS_FS is not set
771
772#
773# Network File Systems
774#
775CONFIG_NFS_FS=y
776CONFIG_NFS_V3=y
777# CONFIG_NFS_V3_ACL is not set
778# CONFIG_NFS_V4 is not set
779# CONFIG_NFS_DIRECTIO is not set
780# CONFIG_NFSD is not set
781CONFIG_ROOT_NFS=y
782CONFIG_LOCKD=y
783CONFIG_LOCKD_V4=y
784CONFIG_NFS_COMMON=y
785CONFIG_SUNRPC=y
786# CONFIG_RPCSEC_GSS_KRB5 is not set
787# CONFIG_RPCSEC_GSS_SPKM3 is not set
788# CONFIG_SMB_FS is not set
789# CONFIG_CIFS is not set
790# CONFIG_NCP_FS is not set
791# CONFIG_CODA_FS is not set
792# CONFIG_AFS_FS is not set
793# CONFIG_9P_FS is not set
794
795#
796# Partition Types
797#
798# CONFIG_PARTITION_ADVANCED is not set
799CONFIG_MSDOS_PARTITION=y
800
801#
802# Native Language Support
803#
804# CONFIG_NLS is not set
805
806#
807# Profiling support
808#
809# CONFIG_PROFILING is not set
810
811#
812# Kernel hacking
813#
814CONFIG_PRINTK_TIME=y
815CONFIG_DEBUG_KERNEL=y
816CONFIG_MAGIC_SYSRQ=y
817CONFIG_LOG_BUF_SHIFT=16
818CONFIG_DETECT_SOFTLOCKUP=y
819# CONFIG_SCHEDSTATS is not set
820# CONFIG_DEBUG_SLAB is not set
821# CONFIG_DEBUG_SPINLOCK is not set
822# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
823# CONFIG_DEBUG_KOBJECT is not set
824# CONFIG_DEBUG_INFO is not set
825# CONFIG_DEBUG_FS is not set
826CONFIG_CROSSCOMPILE=y
827CONFIG_CMDLINE=""
828# CONFIG_DEBUG_STACK_USAGE is not set
829# CONFIG_KGDB is not set
830# CONFIG_SB1XXX_CORELIS is not set
831# CONFIG_RUNTIME_DEBUG is not set
832
833#
834# Security options
835#
836CONFIG_KEYS=y
837CONFIG_KEYS_DEBUG_PROC_KEYS=y
838# CONFIG_SECURITY is not set
839
840#
841# Cryptographic options
842#
843CONFIG_CRYPTO=y
844CONFIG_CRYPTO_HMAC=y
845CONFIG_CRYPTO_NULL=y
846CONFIG_CRYPTO_MD4=y
847CONFIG_CRYPTO_MD5=y
848CONFIG_CRYPTO_SHA1=y
849CONFIG_CRYPTO_SHA256=y
850CONFIG_CRYPTO_SHA512=y
851CONFIG_CRYPTO_WP512=m
852CONFIG_CRYPTO_TGR192=m
853CONFIG_CRYPTO_DES=y
854CONFIG_CRYPTO_BLOWFISH=y
855CONFIG_CRYPTO_TWOFISH=y
856CONFIG_CRYPTO_SERPENT=y
857CONFIG_CRYPTO_AES=m
858# CONFIG_CRYPTO_CAST5 is not set
859# CONFIG_CRYPTO_CAST6 is not set
860CONFIG_CRYPTO_TEA=m
861# CONFIG_CRYPTO_ARC4 is not set
862CONFIG_CRYPTO_KHAZAD=m
863CONFIG_CRYPTO_ANUBIS=m
864CONFIG_CRYPTO_DEFLATE=y
865CONFIG_CRYPTO_MICHAEL_MIC=y
866# CONFIG_CRYPTO_CRC32C is not set
867# CONFIG_CRYPTO_TEST is not set
868
869#
870# Hardware crypto devices
871#
872
873#
874# Library routines
875#
876# CONFIG_CRC_CCITT is not set
877# CONFIG_CRC16 is not set
878CONFIG_CRC32=y
879# CONFIG_LIBCRC32C is not set
880CONFIG_ZLIB_INFLATE=y
881CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index 158e7165f4e3..bfbaa08c47cb 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:00 2005 4# Thu Oct 20 22:25:20 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,57 +59,86 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60CONFIG_MACH_VR41XX=y 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_NEC_CMBVR4133 is not set 64# CONFIG_MIPS_PB1000 is not set
62# CONFIG_CASIO_E55 is not set 65# CONFIG_MIPS_PB1100 is not set
63# CONFIG_IBM_WORKPAD is not set 66# CONFIG_MIPS_PB1500 is not set
64# CONFIG_TANBAC_TB0226 is not set 67# CONFIG_MIPS_PB1550 is not set
65# CONFIG_TANBAC_TB0229 is not set 68# CONFIG_MIPS_PB1200 is not set
66# CONFIG_VICTOR_MPC30X is not set 69# CONFIG_MIPS_DB1000 is not set
67CONFIG_ZAO_CAPCELLA=y 70# CONFIG_MIPS_DB1100 is not set
68CONFIG_PCI_VR41XX=y 71# CONFIG_MIPS_DB1500 is not set
69CONFIG_VRC4173=y 72# CONFIG_MIPS_DB1550 is not set
70# CONFIG_TOSHIBA_JMR3927 is not set 73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
71# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
72# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
73# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
74# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
75# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
76# CONFIG_LASAT is not set
77# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
78# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
79# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
80# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
81# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
82# CONFIG_MOMENCO_OCELOT_G is not set
83# CONFIG_MOMENCO_OCELOT_C is not set
84# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
85# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
86# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
87# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
88# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
89# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
90# CONFIG_NEC_OSPREY is not set 98CONFIG_MACH_VR41XX=y
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
91# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
92# CONFIG_SOC_AU1X00 is not set 102# CONFIG_SGI_IP27 is not set
93# CONFIG_SIBYTE_SB1xxx_SOC is not set 103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
94# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
95# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
117# CONFIG_NEC_CMBVR4133 is not set
118# CONFIG_CASIO_E55 is not set
119# CONFIG_IBM_WORKPAD is not set
120# CONFIG_TANBAC_TB022X is not set
121# CONFIG_VICTOR_MPC30X is not set
122CONFIG_ZAO_CAPCELLA=y
123CONFIG_PCI_VR41XX=y
124# CONFIG_VRC4173 is not set
96CONFIG_RWSEM_GENERIC_SPINLOCK=y 125CONFIG_RWSEM_GENERIC_SPINLOCK=y
97CONFIG_GENERIC_CALIBRATE_DELAY=y 126CONFIG_GENERIC_CALIBRATE_DELAY=y
98CONFIG_HAVE_DEC_LOCK=y
99CONFIG_DMA_NONCOHERENT=y 127CONFIG_DMA_NONCOHERENT=y
100CONFIG_DMA_NEED_PCI_MAP_STATE=y 128CONFIG_DMA_NEED_PCI_MAP_STATE=y
129# CONFIG_CPU_BIG_ENDIAN is not set
101CONFIG_CPU_LITTLE_ENDIAN=y 130CONFIG_CPU_LITTLE_ENDIAN=y
131CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
102CONFIG_IRQ_CPU=y 132CONFIG_IRQ_CPU=y
103CONFIG_MIPS_L1_CACHE_SHIFT=5 133CONFIG_MIPS_L1_CACHE_SHIFT=5
104 134
105# 135#
106# CPU selection 136# CPU selection
107# 137#
108# CONFIG_CPU_MIPS32 is not set 138# CONFIG_CPU_MIPS32_R1 is not set
109# CONFIG_CPU_MIPS64 is not set 139# CONFIG_CPU_MIPS32_R2 is not set
140# CONFIG_CPU_MIPS64_R1 is not set
141# CONFIG_CPU_MIPS64_R2 is not set
110# CONFIG_CPU_R3000 is not set 142# CONFIG_CPU_R3000 is not set
111# CONFIG_CPU_TX39XX is not set 143# CONFIG_CPU_TX39XX is not set
112CONFIG_CPU_VR41XX=y 144CONFIG_CPU_VR41XX=y
@@ -122,12 +154,36 @@ CONFIG_CPU_VR41XX=y
122# CONFIG_CPU_RM7000 is not set 154# CONFIG_CPU_RM7000 is not set
123# CONFIG_CPU_RM9000 is not set 155# CONFIG_CPU_RM9000 is not set
124# CONFIG_CPU_SB1 is not set 156# CONFIG_CPU_SB1 is not set
157CONFIG_SYS_HAS_CPU_VR41XX=y
158CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
159CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
160CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
161CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
162
163#
164# Kernel type
165#
166CONFIG_32BIT=y
167# CONFIG_64BIT is not set
125CONFIG_PAGE_SIZE_4KB=y 168CONFIG_PAGE_SIZE_4KB=y
126# CONFIG_PAGE_SIZE_8KB is not set 169# CONFIG_PAGE_SIZE_8KB is not set
127# CONFIG_PAGE_SIZE_16KB is not set 170# CONFIG_PAGE_SIZE_16KB is not set
128# CONFIG_PAGE_SIZE_64KB is not set 171# CONFIG_PAGE_SIZE_64KB is not set
172# CONFIG_MIPS_MT is not set
129# CONFIG_CPU_ADVANCED is not set 173# CONFIG_CPU_ADVANCED is not set
130CONFIG_CPU_HAS_SYNC=y 174CONFIG_CPU_HAS_SYNC=y
175CONFIG_GENERIC_HARDIRQS=y
176CONFIG_GENERIC_IRQ_PROBE=y
177CONFIG_ARCH_FLATMEM_ENABLE=y
178CONFIG_SELECT_MEMORY_MODEL=y
179CONFIG_FLATMEM_MANUAL=y
180# CONFIG_DISCONTIGMEM_MANUAL is not set
181# CONFIG_SPARSEMEM_MANUAL is not set
182CONFIG_FLATMEM=y
183CONFIG_FLAT_NODE_MEM_MAP=y
184# CONFIG_SPARSEMEM_STATIC is not set
185CONFIG_PREEMPT_NONE=y
186# CONFIG_PREEMPT_VOLUNTARY is not set
131# CONFIG_PREEMPT is not set 187# CONFIG_PREEMPT is not set
132 188
133# 189#
@@ -136,7 +192,6 @@ CONFIG_CPU_HAS_SYNC=y
136CONFIG_HW_HAS_PCI=y 192CONFIG_HW_HAS_PCI=y
137CONFIG_PCI=y 193CONFIG_PCI=y
138CONFIG_PCI_LEGACY_PROC=y 194CONFIG_PCI_LEGACY_PROC=y
139CONFIG_PCI_NAMES=y
140CONFIG_MMU=y 195CONFIG_MMU=y
141 196
142# 197#
@@ -145,10 +200,6 @@ CONFIG_MMU=y
145# CONFIG_PCCARD is not set 200# CONFIG_PCCARD is not set
146 201
147# 202#
148# PC-card bridges
149#
150
151#
152# PCI Hotplug Support 203# PCI Hotplug Support
153# 204#
154# CONFIG_HOTPLUG_PCI is not set 205# CONFIG_HOTPLUG_PCI is not set
@@ -161,6 +212,81 @@ CONFIG_BINFMT_ELF=y
161CONFIG_TRAD_SIGNALS=y 212CONFIG_TRAD_SIGNALS=y
162 213
163# 214#
215# Networking
216#
217CONFIG_NET=y
218
219#
220# Networking options
221#
222CONFIG_PACKET=y
223CONFIG_PACKET_MMAP=y
224CONFIG_UNIX=y
225CONFIG_XFRM=y
226CONFIG_XFRM_USER=m
227CONFIG_NET_KEY=y
228CONFIG_INET=y
229CONFIG_IP_MULTICAST=y
230# CONFIG_IP_ADVANCED_ROUTER is not set
231CONFIG_IP_FIB_HASH=y
232CONFIG_IP_PNP=y
233# CONFIG_IP_PNP_DHCP is not set
234CONFIG_IP_PNP_BOOTP=y
235# CONFIG_IP_PNP_RARP is not set
236# CONFIG_NET_IPIP is not set
237# CONFIG_NET_IPGRE is not set
238# CONFIG_IP_MROUTE is not set
239# CONFIG_ARPD is not set
240# CONFIG_SYN_COOKIES is not set
241# CONFIG_INET_AH is not set
242# CONFIG_INET_ESP is not set
243# CONFIG_INET_IPCOMP is not set
244CONFIG_INET_TUNNEL=m
245CONFIG_INET_DIAG=y
246CONFIG_INET_TCP_DIAG=y
247# CONFIG_TCP_CONG_ADVANCED is not set
248CONFIG_TCP_CONG_BIC=y
249# CONFIG_IPV6 is not set
250# CONFIG_NETFILTER is not set
251
252#
253# DCCP Configuration (EXPERIMENTAL)
254#
255# CONFIG_IP_DCCP is not set
256
257#
258# SCTP Configuration (EXPERIMENTAL)
259#
260# CONFIG_IP_SCTP is not set
261# CONFIG_ATM is not set
262# CONFIG_BRIDGE is not set
263# CONFIG_VLAN_8021Q is not set
264# CONFIG_DECNET is not set
265# CONFIG_LLC2 is not set
266# CONFIG_IPX is not set
267# CONFIG_ATALK is not set
268# CONFIG_X25 is not set
269# CONFIG_LAPB is not set
270# CONFIG_NET_DIVERT is not set
271# CONFIG_ECONET is not set
272# CONFIG_WAN_ROUTER is not set
273# CONFIG_NET_SCHED is not set
274# CONFIG_NET_CLS_ROUTE is not set
275
276#
277# Network testing
278#
279# CONFIG_NET_PKTGEN is not set
280# CONFIG_HAMRADIO is not set
281# CONFIG_IRDA is not set
282# CONFIG_BT is not set
283CONFIG_IEEE80211=m
284# CONFIG_IEEE80211_DEBUG is not set
285CONFIG_IEEE80211_CRYPT_WEP=m
286CONFIG_IEEE80211_CRYPT_CCMP=m
287CONFIG_IEEE80211_CRYPT_TKIP=m
288
289#
164# Device Drivers 290# Device Drivers
165# 291#
166 292
@@ -169,7 +295,12 @@ CONFIG_TRAD_SIGNALS=y
169# 295#
170CONFIG_STANDALONE=y 296CONFIG_STANDALONE=y
171CONFIG_PREVENT_FIRMWARE_BUILD=y 297CONFIG_PREVENT_FIRMWARE_BUILD=y
172# CONFIG_FW_LOADER is not set 298CONFIG_FW_LOADER=m
299
300#
301# Connector - unified userspace <-> kernelspace linker
302#
303CONFIG_CONNECTOR=m
173 304
174# 305#
175# Memory Technology Devices (MTD) 306# Memory Technology Devices (MTD)
@@ -188,7 +319,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
188# 319#
189# Block devices 320# Block devices
190# 321#
191# CONFIG_BLK_DEV_FD is not set
192# CONFIG_BLK_CPQ_DA is not set 322# CONFIG_BLK_CPQ_DA is not set
193# CONFIG_BLK_CPQ_CISS_DA is not set 323# CONFIG_BLK_CPQ_CISS_DA is not set
194# CONFIG_BLK_DEV_DAC960 is not set 324# CONFIG_BLK_DEV_DAC960 is not set
@@ -199,11 +329,8 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
199# CONFIG_BLK_DEV_SX8 is not set 329# CONFIG_BLK_DEV_SX8 is not set
200# CONFIG_BLK_DEV_RAM is not set 330# CONFIG_BLK_DEV_RAM is not set
201CONFIG_BLK_DEV_RAM_COUNT=16 331CONFIG_BLK_DEV_RAM_COUNT=16
202CONFIG_INITRAMFS_SOURCE=""
203# CONFIG_LBD is not set 332# CONFIG_LBD is not set
204CONFIG_CDROM_PKTCDVD=m 333# CONFIG_CDROM_PKTCDVD is not set
205CONFIG_CDROM_PKTCDVD_BUFFERS=8
206# CONFIG_CDROM_PKTCDVD_WCACHE is not set
207 334
208# 335#
209# IO Schedulers 336# IO Schedulers
@@ -244,6 +371,7 @@ CONFIG_IDE_GENERIC=y
244# 371#
245# SCSI device support 372# SCSI device support
246# 373#
374# CONFIG_RAID_ATTRS is not set
247# CONFIG_SCSI is not set 375# CONFIG_SCSI is not set
248 376
249# 377#
@@ -254,6 +382,7 @@ CONFIG_IDE_GENERIC=y
254# 382#
255# Fusion MPT device support 383# Fusion MPT device support
256# 384#
385# CONFIG_FUSION is not set
257 386
258# 387#
259# IEEE 1394 (FireWire) support 388# IEEE 1394 (FireWire) support
@@ -266,79 +395,13 @@ CONFIG_IDE_GENERIC=y
266# CONFIG_I2O is not set 395# CONFIG_I2O is not set
267 396
268# 397#
269# Networking support 398# Network device support
270#
271CONFIG_NET=y
272
273#
274# Networking options
275#
276CONFIG_PACKET=y
277CONFIG_PACKET_MMAP=y
278CONFIG_NETLINK_DEV=y
279CONFIG_UNIX=y
280CONFIG_NET_KEY=y
281CONFIG_INET=y
282CONFIG_IP_MULTICAST=y
283# CONFIG_IP_ADVANCED_ROUTER is not set
284CONFIG_IP_PNP=y
285# CONFIG_IP_PNP_DHCP is not set
286CONFIG_IP_PNP_BOOTP=y
287# CONFIG_IP_PNP_RARP is not set
288# CONFIG_NET_IPIP is not set
289# CONFIG_NET_IPGRE is not set
290# CONFIG_IP_MROUTE is not set
291# CONFIG_ARPD is not set
292# CONFIG_SYN_COOKIES is not set
293# CONFIG_INET_AH is not set
294# CONFIG_INET_ESP is not set
295# CONFIG_INET_IPCOMP is not set
296CONFIG_INET_TUNNEL=m
297CONFIG_IP_TCPDIAG=m
298# CONFIG_IP_TCPDIAG_IPV6 is not set
299# CONFIG_IPV6 is not set
300# CONFIG_NETFILTER is not set
301CONFIG_XFRM=y
302CONFIG_XFRM_USER=m
303
304#
305# SCTP Configuration (EXPERIMENTAL)
306#
307# CONFIG_IP_SCTP is not set
308# CONFIG_ATM is not set
309# CONFIG_BRIDGE is not set
310# CONFIG_VLAN_8021Q is not set
311# CONFIG_DECNET is not set
312# CONFIG_LLC2 is not set
313# CONFIG_IPX is not set
314# CONFIG_ATALK is not set
315# CONFIG_X25 is not set
316# CONFIG_LAPB is not set
317# CONFIG_NET_DIVERT is not set
318# CONFIG_ECONET is not set
319# CONFIG_WAN_ROUTER is not set
320
321#
322# QoS and/or fair queueing
323#
324# CONFIG_NET_SCHED is not set
325# CONFIG_NET_CLS_ROUTE is not set
326
327#
328# Network testing
329# 399#
330# CONFIG_NET_PKTGEN is not set
331# CONFIG_NETPOLL is not set
332# CONFIG_NET_POLL_CONTROLLER is not set
333# CONFIG_HAMRADIO is not set
334# CONFIG_IRDA is not set
335# CONFIG_BT is not set
336CONFIG_NETDEVICES=y 400CONFIG_NETDEVICES=y
337# CONFIG_DUMMY is not set 401# CONFIG_DUMMY is not set
338# CONFIG_BONDING is not set 402# CONFIG_BONDING is not set
339# CONFIG_EQUALIZER is not set 403# CONFIG_EQUALIZER is not set
340# CONFIG_TUN is not set 404# CONFIG_TUN is not set
341# CONFIG_ETHERTAP is not set
342 405
343# 406#
344# ARCnet devices 407# ARCnet devices
@@ -346,10 +409,25 @@ CONFIG_NETDEVICES=y
346# CONFIG_ARCNET is not set 409# CONFIG_ARCNET is not set
347 410
348# 411#
412# PHY device support
413#
414CONFIG_PHYLIB=m
415CONFIG_PHYCONTROL=y
416
417#
418# MII PHY device drivers
419#
420CONFIG_MARVELL_PHY=m
421CONFIG_DAVICOM_PHY=m
422CONFIG_QSEMI_PHY=m
423CONFIG_LXT_PHY=m
424CONFIG_CICADA_PHY=m
425
426#
349# Ethernet (10 or 100Mbit) 427# Ethernet (10 or 100Mbit)
350# 428#
351CONFIG_NET_ETHERNET=y 429CONFIG_NET_ETHERNET=y
352# CONFIG_MII is not set 430CONFIG_MII=y
353# CONFIG_HAPPYMEAL is not set 431# CONFIG_HAPPYMEAL is not set
354# CONFIG_SUNGEM is not set 432# CONFIG_SUNGEM is not set
355# CONFIG_NET_VENDOR_3COM is not set 433# CONFIG_NET_VENDOR_3COM is not set
@@ -359,7 +437,30 @@ CONFIG_NET_ETHERNET=y
359# 437#
360# CONFIG_NET_TULIP is not set 438# CONFIG_NET_TULIP is not set
361# CONFIG_HP100 is not set 439# CONFIG_HP100 is not set
362# CONFIG_NET_PCI is not set 440CONFIG_NET_PCI=y
441# CONFIG_PCNET32 is not set
442# CONFIG_AMD8111_ETH is not set
443# CONFIG_ADAPTEC_STARFIRE is not set
444# CONFIG_B44 is not set
445# CONFIG_FORCEDETH is not set
446# CONFIG_DGRS is not set
447# CONFIG_EEPRO100 is not set
448# CONFIG_E100 is not set
449# CONFIG_FEALNX is not set
450# CONFIG_NATSEMI is not set
451# CONFIG_NE2K_PCI is not set
452# CONFIG_8139CP is not set
453CONFIG_8139TOO=y
454CONFIG_8139TOO_PIO=y
455# CONFIG_8139TOO_TUNE_TWISTER is not set
456# CONFIG_8139TOO_8129 is not set
457# CONFIG_8139_OLD_RX_RESET is not set
458# CONFIG_SIS900 is not set
459# CONFIG_EPIC100 is not set
460# CONFIG_SUNDANCE is not set
461# CONFIG_TLAN is not set
462# CONFIG_VIA_RHINE is not set
463# CONFIG_LAN_SAA9730 is not set
363 464
364# 465#
365# Ethernet (1000 Mbit) 466# Ethernet (1000 Mbit)
@@ -371,12 +472,17 @@ CONFIG_NET_ETHERNET=y
371# CONFIG_HAMACHI is not set 472# CONFIG_HAMACHI is not set
372# CONFIG_YELLOWFIN is not set 473# CONFIG_YELLOWFIN is not set
373# CONFIG_R8169 is not set 474# CONFIG_R8169 is not set
475# CONFIG_SIS190 is not set
476# CONFIG_SKGE is not set
374# CONFIG_SK98LIN is not set 477# CONFIG_SK98LIN is not set
478# CONFIG_VIA_VELOCITY is not set
375# CONFIG_TIGON3 is not set 479# CONFIG_TIGON3 is not set
480# CONFIG_BNX2 is not set
376 481
377# 482#
378# Ethernet (10000 Mbit) 483# Ethernet (10000 Mbit)
379# 484#
485# CONFIG_CHELSIO_T1 is not set
380# CONFIG_IXGB is not set 486# CONFIG_IXGB is not set
381# CONFIG_S2IO is not set 487# CONFIG_S2IO is not set
382 488
@@ -389,6 +495,8 @@ CONFIG_NET_ETHERNET=y
389# Wireless LAN (non-hamradio) 495# Wireless LAN (non-hamradio)
390# 496#
391# CONFIG_NET_RADIO is not set 497# CONFIG_NET_RADIO is not set
498# CONFIG_IPW_DEBUG is not set
499CONFIG_IPW2200=m
392 500
393# 501#
394# Wan interfaces 502# Wan interfaces
@@ -400,6 +508,8 @@ CONFIG_NET_ETHERNET=y
400# CONFIG_SLIP is not set 508# CONFIG_SLIP is not set
401# CONFIG_SHAPER is not set 509# CONFIG_SHAPER is not set
402# CONFIG_NETCONSOLE is not set 510# CONFIG_NETCONSOLE is not set
511# CONFIG_NETPOLL is not set
512# CONFIG_NET_POLL_CONTROLLER is not set
403 513
404# 514#
405# ISDN subsystem 515# ISDN subsystem
@@ -419,29 +529,13 @@ CONFIG_INPUT=y
419# 529#
420# Userland interfaces 530# Userland interfaces
421# 531#
422CONFIG_INPUT_MOUSEDEV=y 532# CONFIG_INPUT_MOUSEDEV is not set
423CONFIG_INPUT_MOUSEDEV_PSAUX=y
424CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
425CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
426# CONFIG_INPUT_JOYDEV is not set 533# CONFIG_INPUT_JOYDEV is not set
427# CONFIG_INPUT_TSDEV is not set 534# CONFIG_INPUT_TSDEV is not set
428# CONFIG_INPUT_EVDEV is not set 535# CONFIG_INPUT_EVDEV is not set
429# CONFIG_INPUT_EVBUG is not set 536# CONFIG_INPUT_EVBUG is not set
430 537
431# 538#
432# Input I/O drivers
433#
434# CONFIG_GAMEPORT is not set
435CONFIG_SOUND_GAMEPORT=y
436CONFIG_SERIO=y
437CONFIG_SERIO_I8042=y
438CONFIG_SERIO_SERPORT=y
439# CONFIG_SERIO_CT82C710 is not set
440# CONFIG_SERIO_PCIPS2 is not set
441CONFIG_SERIO_LIBPS2=m
442CONFIG_SERIO_RAW=m
443
444#
445# Input Device Drivers 539# Input Device Drivers
446# 540#
447# CONFIG_INPUT_KEYBOARD is not set 541# CONFIG_INPUT_KEYBOARD is not set
@@ -451,6 +545,12 @@ CONFIG_SERIO_RAW=m
451# CONFIG_INPUT_MISC is not set 545# CONFIG_INPUT_MISC is not set
452 546
453# 547#
548# Hardware I/O ports
549#
550# CONFIG_SERIO is not set
551# CONFIG_GAMEPORT is not set
552
553#
454# Character devices 554# Character devices
455# 555#
456CONFIG_VT=y 556CONFIG_VT=y
@@ -461,16 +561,16 @@ CONFIG_HW_CONSOLE=y
461# 561#
462# Serial drivers 562# Serial drivers
463# 563#
464CONFIG_SERIAL_8250=y 564# CONFIG_SERIAL_8250 is not set
465CONFIG_SERIAL_8250_CONSOLE=y
466CONFIG_SERIAL_8250_NR_UARTS=4
467# CONFIG_SERIAL_8250_EXTENDED is not set
468 565
469# 566#
470# Non-8250 serial port support 567# Non-8250 serial port support
471# 568#
472CONFIG_SERIAL_CORE=y 569CONFIG_SERIAL_CORE=y
473CONFIG_SERIAL_CORE_CONSOLE=y 570CONFIG_SERIAL_CORE_CONSOLE=y
571CONFIG_SERIAL_VR41XX=y
572CONFIG_SERIAL_VR41XX_CONSOLE=y
573# CONFIG_SERIAL_JSM is not set
474CONFIG_UNIX98_PTYS=y 574CONFIG_UNIX98_PTYS=y
475CONFIG_LEGACY_PTYS=y 575CONFIG_LEGACY_PTYS=y
476CONFIG_LEGACY_PTY_COUNT=256 576CONFIG_LEGACY_PTY_COUNT=256
@@ -483,19 +583,7 @@ CONFIG_LEGACY_PTY_COUNT=256
483# 583#
484# Watchdog Cards 584# Watchdog Cards
485# 585#
486CONFIG_WATCHDOG=y 586# CONFIG_WATCHDOG is not set
487# CONFIG_WATCHDOG_NOWAYOUT is not set
488
489#
490# Watchdog Device Drivers
491#
492# CONFIG_SOFT_WATCHDOG is not set
493
494#
495# PCI-based Watchdog Cards
496#
497# CONFIG_PCIPCWATCHDOG is not set
498# CONFIG_WDTPCI is not set
499# CONFIG_RTC is not set 587# CONFIG_RTC is not set
500# CONFIG_GEN_RTC is not set 588# CONFIG_GEN_RTC is not set
501# CONFIG_DTLK is not set 589# CONFIG_DTLK is not set
@@ -506,9 +594,15 @@ CONFIG_WATCHDOG=y
506# Ftape, the floppy tape device driver 594# Ftape, the floppy tape device driver
507# 595#
508# CONFIG_DRM is not set 596# CONFIG_DRM is not set
597CONFIG_GPIO_VR41XX=y
509# CONFIG_RAW_DRIVER is not set 598# CONFIG_RAW_DRIVER is not set
510 599
511# 600#
601# TPM devices
602#
603# CONFIG_TCG_TPM is not set
604
605#
512# I2C support 606# I2C support
513# 607#
514# CONFIG_I2C is not set 608# CONFIG_I2C is not set
@@ -519,10 +613,20 @@ CONFIG_WATCHDOG=y
519# CONFIG_W1 is not set 613# CONFIG_W1 is not set
520 614
521# 615#
616# Hardware Monitoring support
617#
618# CONFIG_HWMON is not set
619# CONFIG_HWMON_VID is not set
620
621#
522# Misc devices 622# Misc devices
523# 623#
524 624
525# 625#
626# Multimedia Capabilities Port drivers
627#
628
629#
526# Multimedia devices 630# Multimedia devices
527# 631#
528# CONFIG_VIDEO_DEV is not set 632# CONFIG_VIDEO_DEV is not set
@@ -542,7 +646,6 @@ CONFIG_WATCHDOG=y
542# 646#
543# CONFIG_VGA_CONSOLE is not set 647# CONFIG_VGA_CONSOLE is not set
544CONFIG_DUMMY_CONSOLE=y 648CONFIG_DUMMY_CONSOLE=y
545# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
546 649
547# 650#
548# Sound 651# Sound
@@ -552,13 +655,9 @@ CONFIG_DUMMY_CONSOLE=y
552# 655#
553# USB support 656# USB support
554# 657#
555# CONFIG_USB is not set
556CONFIG_USB_ARCH_HAS_HCD=y 658CONFIG_USB_ARCH_HAS_HCD=y
557CONFIG_USB_ARCH_HAS_OHCI=y 659CONFIG_USB_ARCH_HAS_OHCI=y
558 660# CONFIG_USB is not set
559#
560# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
561#
562 661
563# 662#
564# USB Gadget Support 663# USB Gadget Support
@@ -576,21 +675,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y
576# CONFIG_INFINIBAND is not set 675# CONFIG_INFINIBAND is not set
577 676
578# 677#
678# SN Devices
679#
680
681#
579# File systems 682# File systems
580# 683#
581CONFIG_EXT2_FS=y 684CONFIG_EXT2_FS=y
582# CONFIG_EXT2_FS_XATTR is not set 685# CONFIG_EXT2_FS_XATTR is not set
686# CONFIG_EXT2_FS_XIP is not set
583# CONFIG_EXT3_FS is not set 687# CONFIG_EXT3_FS is not set
584# CONFIG_JBD is not set 688# CONFIG_JBD is not set
585# CONFIG_REISERFS_FS is not set 689# CONFIG_REISERFS_FS is not set
586# CONFIG_JFS_FS is not set 690# CONFIG_JFS_FS is not set
691# CONFIG_FS_POSIX_ACL is not set
587# CONFIG_XFS_FS is not set 692# CONFIG_XFS_FS is not set
588# CONFIG_MINIX_FS is not set 693# CONFIG_MINIX_FS is not set
589# CONFIG_ROMFS_FS is not set 694# CONFIG_ROMFS_FS is not set
695CONFIG_INOTIFY=y
590# CONFIG_QUOTA is not set 696# CONFIG_QUOTA is not set
591CONFIG_DNOTIFY=y 697CONFIG_DNOTIFY=y
592CONFIG_AUTOFS_FS=y 698CONFIG_AUTOFS_FS=y
593CONFIG_AUTOFS4_FS=y 699CONFIG_AUTOFS4_FS=y
700CONFIG_FUSE_FS=m
594 701
595# 702#
596# CD-ROM/DVD Filesystems 703# CD-ROM/DVD Filesystems
@@ -611,12 +718,10 @@ CONFIG_AUTOFS4_FS=y
611CONFIG_PROC_FS=y 718CONFIG_PROC_FS=y
612CONFIG_PROC_KCORE=y 719CONFIG_PROC_KCORE=y
613CONFIG_SYSFS=y 720CONFIG_SYSFS=y
614# CONFIG_DEVFS_FS is not set
615CONFIG_DEVPTS_FS_XATTR=y
616CONFIG_DEVPTS_FS_SECURITY=y
617# CONFIG_TMPFS is not set 721# CONFIG_TMPFS is not set
618# CONFIG_HUGETLB_PAGE is not set 722# CONFIG_HUGETLB_PAGE is not set
619CONFIG_RAMFS=y 723CONFIG_RAMFS=y
724CONFIG_RELAYFS_FS=m
620 725
621# 726#
622# Miscellaneous filesystems 727# Miscellaneous filesystems
@@ -648,6 +753,7 @@ CONFIG_NFSD=y
648CONFIG_ROOT_NFS=y 753CONFIG_ROOT_NFS=y
649CONFIG_LOCKD=y 754CONFIG_LOCKD=y
650CONFIG_EXPORTFS=y 755CONFIG_EXPORTFS=y
756CONFIG_NFS_COMMON=y
651CONFIG_SUNRPC=y 757CONFIG_SUNRPC=y
652# CONFIG_RPCSEC_GSS_KRB5 is not set 758# CONFIG_RPCSEC_GSS_KRB5 is not set
653# CONFIG_RPCSEC_GSS_SPKM3 is not set 759# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -656,6 +762,7 @@ CONFIG_SUNRPC=y
656# CONFIG_NCP_FS is not set 762# CONFIG_NCP_FS is not set
657# CONFIG_CODA_FS is not set 763# CONFIG_CODA_FS is not set
658# CONFIG_AFS_FS is not set 764# CONFIG_AFS_FS is not set
765# CONFIG_9P_FS is not set
659 766
660# 767#
661# Partition Types 768# Partition Types
@@ -676,9 +783,11 @@ CONFIG_MSDOS_PARTITION=y
676# 783#
677# Kernel hacking 784# Kernel hacking
678# 785#
786# CONFIG_PRINTK_TIME is not set
679# CONFIG_DEBUG_KERNEL is not set 787# CONFIG_DEBUG_KERNEL is not set
788CONFIG_LOG_BUF_SHIFT=14
680CONFIG_CROSSCOMPILE=y 789CONFIG_CROSSCOMPILE=y
681CONFIG_CMDLINE="" 790CONFIG_CMDLINE="mem=32M console=ttyVR0,38400"
682 791
683# 792#
684# Security options 793# Security options
@@ -690,7 +799,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
690# 799#
691# Cryptographic options 800# Cryptographic options
692# 801#
693# CONFIG_CRYPTO is not set 802CONFIG_CRYPTO=y
803CONFIG_CRYPTO_HMAC=y
804CONFIG_CRYPTO_NULL=m
805CONFIG_CRYPTO_MD4=m
806CONFIG_CRYPTO_MD5=m
807CONFIG_CRYPTO_SHA1=m
808CONFIG_CRYPTO_SHA256=m
809CONFIG_CRYPTO_SHA512=m
810CONFIG_CRYPTO_WP512=m
811CONFIG_CRYPTO_TGR192=m
812CONFIG_CRYPTO_DES=m
813CONFIG_CRYPTO_BLOWFISH=m
814CONFIG_CRYPTO_TWOFISH=m
815CONFIG_CRYPTO_SERPENT=m
816CONFIG_CRYPTO_AES=m
817CONFIG_CRYPTO_CAST5=m
818CONFIG_CRYPTO_CAST6=m
819CONFIG_CRYPTO_TEA=m
820CONFIG_CRYPTO_ARC4=m
821CONFIG_CRYPTO_KHAZAD=m
822CONFIG_CRYPTO_ANUBIS=m
823CONFIG_CRYPTO_DEFLATE=m
824CONFIG_CRYPTO_MICHAEL_MIC=m
825CONFIG_CRYPTO_CRC32C=m
826# CONFIG_CRYPTO_TEST is not set
694 827
695# 828#
696# Hardware crypto devices 829# Hardware crypto devices
@@ -700,7 +833,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
700# Library routines 833# Library routines
701# 834#
702# CONFIG_CRC_CCITT is not set 835# CONFIG_CRC_CCITT is not set
703# CONFIG_CRC32 is not set 836CONFIG_CRC16=m
837CONFIG_CRC32=y
704CONFIG_LIBCRC32C=m 838CONFIG_LIBCRC32C=m
705CONFIG_GENERIC_HARDIRQS=y 839CONFIG_ZLIB_INFLATE=m
706CONFIG_GENERIC_IRQ_PROBE=y 840CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 4302c6f914f5..4b4d1ddb3d42 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:00 2005 4# Thu Oct 20 22:25:23 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29CONFIG_HOTPLUG=y 27CONFIG_HOTPLUG=y
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -50,41 +53,69 @@ CONFIG_CC_ALIGN_JUMPS=0
50# 53#
51# Machine selection 54# Machine selection
52# 55#
53# CONFIG_MACH_JAZZ is not set 56# CONFIG_MIPS_MTX1 is not set
54# CONFIG_MACH_VR41XX is not set 57# CONFIG_MIPS_BOSPORUS is not set
55# CONFIG_TOSHIBA_JMR3927 is not set 58# CONFIG_MIPS_PB1000 is not set
59# CONFIG_MIPS_PB1100 is not set
60# CONFIG_MIPS_PB1500 is not set
61# CONFIG_MIPS_PB1550 is not set
62# CONFIG_MIPS_PB1200 is not set
63# CONFIG_MIPS_DB1000 is not set
64# CONFIG_MIPS_DB1100 is not set
65# CONFIG_MIPS_DB1500 is not set
66# CONFIG_MIPS_DB1550 is not set
67# CONFIG_MIPS_DB1200 is not set
68# CONFIG_MIPS_MIRAGE is not set
56CONFIG_MIPS_COBALT=y 69CONFIG_MIPS_COBALT=y
57# CONFIG_MACH_DECSTATION is not set 70# CONFIG_MACH_DECSTATION is not set
58# CONFIG_MIPS_EV64120 is not set 71# CONFIG_MIPS_EV64120 is not set
59# CONFIG_MIPS_EV96100 is not set 72# CONFIG_MIPS_EV96100 is not set
60# CONFIG_MIPS_IVR is not set 73# CONFIG_MIPS_IVR is not set
61# CONFIG_LASAT is not set
62# CONFIG_MIPS_ITE8172 is not set 74# CONFIG_MIPS_ITE8172 is not set
75# CONFIG_MACH_JAZZ is not set
76# CONFIG_LASAT is not set
63# CONFIG_MIPS_ATLAS is not set 77# CONFIG_MIPS_ATLAS is not set
64# CONFIG_MIPS_MALTA is not set 78# CONFIG_MIPS_MALTA is not set
65# CONFIG_MIPS_SEAD is not set 79# CONFIG_MIPS_SEAD is not set
80# CONFIG_MIPS_SIM is not set
81# CONFIG_MOMENCO_JAGUAR_ATX is not set
66# CONFIG_MOMENCO_OCELOT is not set 82# CONFIG_MOMENCO_OCELOT is not set
67# CONFIG_MOMENCO_OCELOT_G is not set
68# CONFIG_MOMENCO_OCELOT_C is not set
69# CONFIG_MOMENCO_OCELOT_3 is not set 83# CONFIG_MOMENCO_OCELOT_3 is not set
70# CONFIG_MOMENCO_JAGUAR_ATX is not set 84# CONFIG_MOMENCO_OCELOT_C is not set
71# CONFIG_PMC_YOSEMITE is not set 85# CONFIG_MOMENCO_OCELOT_G is not set
86# CONFIG_MIPS_XXS1500 is not set
87# CONFIG_PNX8550_V2PCI is not set
88# CONFIG_PNX8550_JBS is not set
72# CONFIG_DDB5074 is not set 89# CONFIG_DDB5074 is not set
73# CONFIG_DDB5476 is not set 90# CONFIG_DDB5476 is not set
74# CONFIG_DDB5477 is not set 91# CONFIG_DDB5477 is not set
75# CONFIG_NEC_OSPREY is not set 92# CONFIG_MACH_VR41XX is not set
93# CONFIG_PMC_YOSEMITE is not set
94# CONFIG_QEMU is not set
76# CONFIG_SGI_IP22 is not set 95# CONFIG_SGI_IP22 is not set
77# CONFIG_SOC_AU1X00 is not set 96# CONFIG_SGI_IP27 is not set
78# CONFIG_SIBYTE_SB1xxx_SOC is not set 97# CONFIG_SGI_IP32 is not set
98# CONFIG_SIBYTE_BIGSUR is not set
99# CONFIG_SIBYTE_SWARM is not set
100# CONFIG_SIBYTE_SENTOSA is not set
101# CONFIG_SIBYTE_RHONE is not set
102# CONFIG_SIBYTE_CARMEL is not set
103# CONFIG_SIBYTE_PTSWARM is not set
104# CONFIG_SIBYTE_LITTLESUR is not set
105# CONFIG_SIBYTE_CRHINE is not set
106# CONFIG_SIBYTE_CRHONE is not set
79# CONFIG_SNI_RM200_PCI is not set 107# CONFIG_SNI_RM200_PCI is not set
108# CONFIG_TOSHIBA_JMR3927 is not set
80# CONFIG_TOSHIBA_RBTX4927 is not set 109# CONFIG_TOSHIBA_RBTX4927 is not set
110# CONFIG_TOSHIBA_RBTX4938 is not set
81CONFIG_RWSEM_GENERIC_SPINLOCK=y 111CONFIG_RWSEM_GENERIC_SPINLOCK=y
82CONFIG_GENERIC_CALIBRATE_DELAY=y 112CONFIG_GENERIC_CALIBRATE_DELAY=y
83CONFIG_HAVE_DEC_LOCK=y
84CONFIG_DMA_NONCOHERENT=y 113CONFIG_DMA_NONCOHERENT=y
85CONFIG_DMA_NEED_PCI_MAP_STATE=y 114CONFIG_DMA_NEED_PCI_MAP_STATE=y
86CONFIG_I8259=y 115CONFIG_I8259=y
116# CONFIG_CPU_BIG_ENDIAN is not set
87CONFIG_CPU_LITTLE_ENDIAN=y 117CONFIG_CPU_LITTLE_ENDIAN=y
118CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
88CONFIG_IRQ_CPU=y 119CONFIG_IRQ_CPU=y
89CONFIG_MIPS_GT64111=y 120CONFIG_MIPS_GT64111=y
90CONFIG_MIPS_L1_CACHE_SHIFT=5 121CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -92,8 +123,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
92# 123#
93# CPU selection 124# CPU selection
94# 125#
95# CONFIG_CPU_MIPS32 is not set 126# CONFIG_CPU_MIPS32_R1 is not set
96# CONFIG_CPU_MIPS64 is not set 127# CONFIG_CPU_MIPS32_R2 is not set
128# CONFIG_CPU_MIPS64_R1 is not set
129# CONFIG_CPU_MIPS64_R2 is not set
97# CONFIG_CPU_R3000 is not set 130# CONFIG_CPU_R3000 is not set
98# CONFIG_CPU_TX39XX is not set 131# CONFIG_CPU_TX39XX is not set
99# CONFIG_CPU_VR41XX is not set 132# CONFIG_CPU_VR41XX is not set
@@ -109,14 +142,38 @@ CONFIG_CPU_NEVADA=y
109# CONFIG_CPU_RM7000 is not set 142# CONFIG_CPU_RM7000 is not set
110# CONFIG_CPU_RM9000 is not set 143# CONFIG_CPU_RM9000 is not set
111# CONFIG_CPU_SB1 is not set 144# CONFIG_CPU_SB1 is not set
145CONFIG_SYS_HAS_CPU_NEVADA=y
146CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
147CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
148CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
149CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
150
151#
152# Kernel type
153#
154CONFIG_32BIT=y
155# CONFIG_64BIT is not set
112CONFIG_PAGE_SIZE_4KB=y 156CONFIG_PAGE_SIZE_4KB=y
113# CONFIG_PAGE_SIZE_8KB is not set 157# CONFIG_PAGE_SIZE_8KB is not set
114# CONFIG_PAGE_SIZE_16KB is not set 158# CONFIG_PAGE_SIZE_16KB is not set
115# CONFIG_PAGE_SIZE_64KB is not set 159# CONFIG_PAGE_SIZE_64KB is not set
160# CONFIG_MIPS_MT is not set
116# CONFIG_CPU_ADVANCED is not set 161# CONFIG_CPU_ADVANCED is not set
117CONFIG_CPU_HAS_LLSC=y 162CONFIG_CPU_HAS_LLSC=y
118CONFIG_CPU_HAS_LLDSCD=y 163CONFIG_CPU_HAS_LLDSCD=y
119CONFIG_CPU_HAS_SYNC=y 164CONFIG_CPU_HAS_SYNC=y
165CONFIG_GENERIC_HARDIRQS=y
166CONFIG_GENERIC_IRQ_PROBE=y
167CONFIG_ARCH_FLATMEM_ENABLE=y
168CONFIG_SELECT_MEMORY_MODEL=y
169CONFIG_FLATMEM_MANUAL=y
170# CONFIG_DISCONTIGMEM_MANUAL is not set
171# CONFIG_SPARSEMEM_MANUAL is not set
172CONFIG_FLATMEM=y
173CONFIG_FLAT_NODE_MEM_MAP=y
174# CONFIG_SPARSEMEM_STATIC is not set
175CONFIG_PREEMPT_NONE=y
176# CONFIG_PREEMPT_VOLUNTARY is not set
120# CONFIG_PREEMPT is not set 177# CONFIG_PREEMPT is not set
121 178
122# 179#
@@ -125,7 +182,6 @@ CONFIG_CPU_HAS_SYNC=y
125CONFIG_HW_HAS_PCI=y 182CONFIG_HW_HAS_PCI=y
126CONFIG_PCI=y 183CONFIG_PCI=y
127CONFIG_PCI_LEGACY_PROC=y 184CONFIG_PCI_LEGACY_PROC=y
128CONFIG_PCI_NAMES=y
129CONFIG_MMU=y 185CONFIG_MMU=y
130 186
131# 187#
@@ -134,10 +190,6 @@ CONFIG_MMU=y
134# CONFIG_PCCARD is not set 190# CONFIG_PCCARD is not set
135 191
136# 192#
137# PC-card bridges
138#
139
140#
141# PCI Hotplug Support 193# PCI Hotplug Support
142# 194#
143# CONFIG_HOTPLUG_PCI is not set 195# CONFIG_HOTPLUG_PCI is not set
@@ -150,6 +202,77 @@ CONFIG_BINFMT_ELF=y
150CONFIG_TRAD_SIGNALS=y 202CONFIG_TRAD_SIGNALS=y
151 203
152# 204#
205# Networking
206#
207CONFIG_NET=y
208
209#
210# Networking options
211#
212CONFIG_PACKET=y
213# CONFIG_PACKET_MMAP is not set
214CONFIG_UNIX=y
215CONFIG_XFRM=y
216CONFIG_XFRM_USER=y
217CONFIG_NET_KEY=y
218CONFIG_INET=y
219# CONFIG_IP_MULTICAST is not set
220# CONFIG_IP_ADVANCED_ROUTER is not set
221CONFIG_IP_FIB_HASH=y
222# CONFIG_IP_PNP is not set
223# CONFIG_NET_IPIP is not set
224# CONFIG_NET_IPGRE is not set
225# CONFIG_ARPD is not set
226# CONFIG_SYN_COOKIES is not set
227# CONFIG_INET_AH is not set
228# CONFIG_INET_ESP is not set
229# CONFIG_INET_IPCOMP is not set
230CONFIG_INET_TUNNEL=y
231CONFIG_INET_DIAG=y
232CONFIG_INET_TCP_DIAG=y
233# CONFIG_TCP_CONG_ADVANCED is not set
234CONFIG_TCP_CONG_BIC=y
235# CONFIG_IPV6 is not set
236# CONFIG_NETFILTER is not set
237
238#
239# DCCP Configuration (EXPERIMENTAL)
240#
241# CONFIG_IP_DCCP is not set
242
243#
244# SCTP Configuration (EXPERIMENTAL)
245#
246# CONFIG_IP_SCTP is not set
247# CONFIG_ATM is not set
248# CONFIG_BRIDGE is not set
249# CONFIG_VLAN_8021Q is not set
250# CONFIG_DECNET is not set
251# CONFIG_LLC2 is not set
252# CONFIG_IPX is not set
253# CONFIG_ATALK is not set
254# CONFIG_X25 is not set
255# CONFIG_LAPB is not set
256# CONFIG_NET_DIVERT is not set
257# CONFIG_ECONET is not set
258# CONFIG_WAN_ROUTER is not set
259# CONFIG_NET_SCHED is not set
260# CONFIG_NET_CLS_ROUTE is not set
261
262#
263# Network testing
264#
265# CONFIG_NET_PKTGEN is not set
266# CONFIG_HAMRADIO is not set
267# CONFIG_IRDA is not set
268# CONFIG_BT is not set
269CONFIG_IEEE80211=y
270# CONFIG_IEEE80211_DEBUG is not set
271CONFIG_IEEE80211_CRYPT_WEP=y
272CONFIG_IEEE80211_CRYPT_CCMP=y
273CONFIG_IEEE80211_CRYPT_TKIP=y
274
275#
153# Device Drivers 276# Device Drivers
154# 277#
155 278
@@ -161,6 +284,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
161CONFIG_FW_LOADER=y 284CONFIG_FW_LOADER=y
162 285
163# 286#
287# Connector - unified userspace <-> kernelspace linker
288#
289CONFIG_CONNECTOR=y
290
291#
164# Memory Technology Devices (MTD) 292# Memory Technology Devices (MTD)
165# 293#
166# CONFIG_MTD is not set 294# CONFIG_MTD is not set
@@ -177,7 +305,6 @@ CONFIG_FW_LOADER=y
177# 305#
178# Block devices 306# Block devices
179# 307#
180# CONFIG_BLK_DEV_FD is not set
181# CONFIG_BLK_CPQ_DA is not set 308# CONFIG_BLK_CPQ_DA is not set
182# CONFIG_BLK_CPQ_CISS_DA is not set 309# CONFIG_BLK_CPQ_CISS_DA is not set
183# CONFIG_BLK_DEV_DAC960 is not set 310# CONFIG_BLK_DEV_DAC960 is not set
@@ -189,7 +316,6 @@ CONFIG_BLK_DEV_LOOP=y
189# CONFIG_BLK_DEV_SX8 is not set 316# CONFIG_BLK_DEV_SX8 is not set
190# CONFIG_BLK_DEV_RAM is not set 317# CONFIG_BLK_DEV_RAM is not set
191CONFIG_BLK_DEV_RAM_COUNT=16 318CONFIG_BLK_DEV_RAM_COUNT=16
192CONFIG_INITRAMFS_SOURCE=""
193# CONFIG_LBD is not set 319# CONFIG_LBD is not set
194CONFIG_CDROM_PKTCDVD=y 320CONFIG_CDROM_PKTCDVD=y
195CONFIG_CDROM_PKTCDVD_BUFFERS=8 321CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -234,6 +360,7 @@ CONFIG_IDE_GENERIC=y
234# 360#
235# SCSI device support 361# SCSI device support
236# 362#
363CONFIG_RAID_ATTRS=y
237# CONFIG_SCSI is not set 364# CONFIG_SCSI is not set
238 365
239# 366#
@@ -244,6 +371,7 @@ CONFIG_IDE_GENERIC=y
244# 371#
245# Fusion MPT device support 372# Fusion MPT device support
246# 373#
374# CONFIG_FUSION is not set
247 375
248# 376#
249# IEEE 1394 (FireWire) support 377# IEEE 1394 (FireWire) support
@@ -256,75 +384,13 @@ CONFIG_IDE_GENERIC=y
256# CONFIG_I2O is not set 384# CONFIG_I2O is not set
257 385
258# 386#
259# Networking support 387# Network device support
260#
261CONFIG_NET=y
262
263#
264# Networking options
265#
266CONFIG_PACKET=y
267# CONFIG_PACKET_MMAP is not set
268CONFIG_NETLINK_DEV=y
269CONFIG_UNIX=y
270CONFIG_NET_KEY=y
271CONFIG_INET=y
272# CONFIG_IP_MULTICAST is not set
273# CONFIG_IP_ADVANCED_ROUTER is not set
274# CONFIG_IP_PNP is not set
275# CONFIG_NET_IPIP is not set
276# CONFIG_NET_IPGRE is not set
277# CONFIG_ARPD is not set
278# CONFIG_SYN_COOKIES is not set
279# CONFIG_INET_AH is not set
280# CONFIG_INET_ESP is not set
281# CONFIG_INET_IPCOMP is not set
282CONFIG_INET_TUNNEL=y
283CONFIG_IP_TCPDIAG=y
284# CONFIG_IP_TCPDIAG_IPV6 is not set
285# CONFIG_IPV6 is not set
286# CONFIG_NETFILTER is not set
287CONFIG_XFRM=y
288CONFIG_XFRM_USER=y
289
290#
291# SCTP Configuration (EXPERIMENTAL)
292#
293# CONFIG_IP_SCTP is not set
294# CONFIG_ATM is not set
295# CONFIG_BRIDGE is not set
296# CONFIG_VLAN_8021Q is not set
297# CONFIG_DECNET is not set
298# CONFIG_LLC2 is not set
299# CONFIG_IPX is not set
300# CONFIG_ATALK is not set
301# CONFIG_X25 is not set
302# CONFIG_LAPB is not set
303# CONFIG_NET_DIVERT is not set
304# CONFIG_ECONET is not set
305# CONFIG_WAN_ROUTER is not set
306
307#
308# QoS and/or fair queueing
309#
310# CONFIG_NET_SCHED is not set
311# CONFIG_NET_CLS_ROUTE is not set
312
313#
314# Network testing
315# 388#
316# CONFIG_NET_PKTGEN is not set
317# CONFIG_NETPOLL is not set
318# CONFIG_NET_POLL_CONTROLLER is not set
319# CONFIG_HAMRADIO is not set
320# CONFIG_IRDA is not set
321# CONFIG_BT is not set
322CONFIG_NETDEVICES=y 389CONFIG_NETDEVICES=y
323# CONFIG_DUMMY is not set 390# CONFIG_DUMMY is not set
324# CONFIG_BONDING is not set 391# CONFIG_BONDING is not set
325# CONFIG_EQUALIZER is not set 392# CONFIG_EQUALIZER is not set
326# CONFIG_TUN is not set 393# CONFIG_TUN is not set
327# CONFIG_ETHERTAP is not set
328 394
329# 395#
330# ARCnet devices 396# ARCnet devices
@@ -332,6 +398,21 @@ CONFIG_NETDEVICES=y
332# CONFIG_ARCNET is not set 398# CONFIG_ARCNET is not set
333 399
334# 400#
401# PHY device support
402#
403CONFIG_PHYLIB=y
404CONFIG_PHYCONTROL=y
405
406#
407# MII PHY device drivers
408#
409CONFIG_MARVELL_PHY=y
410CONFIG_DAVICOM_PHY=y
411CONFIG_QSEMI_PHY=y
412CONFIG_LXT_PHY=y
413CONFIG_CICADA_PHY=y
414
415#
335# Ethernet (10 or 100Mbit) 416# Ethernet (10 or 100Mbit)
336# 417#
337CONFIG_NET_ETHERNET=y 418CONFIG_NET_ETHERNET=y
@@ -357,12 +438,16 @@ CONFIG_NET_ETHERNET=y
357# CONFIG_HAMACHI is not set 438# CONFIG_HAMACHI is not set
358# CONFIG_YELLOWFIN is not set 439# CONFIG_YELLOWFIN is not set
359# CONFIG_R8169 is not set 440# CONFIG_R8169 is not set
441# CONFIG_SIS190 is not set
442# CONFIG_SKGE is not set
360# CONFIG_SK98LIN is not set 443# CONFIG_SK98LIN is not set
361# CONFIG_TIGON3 is not set 444# CONFIG_TIGON3 is not set
445# CONFIG_BNX2 is not set
362 446
363# 447#
364# Ethernet (10000 Mbit) 448# Ethernet (10000 Mbit)
365# 449#
450# CONFIG_CHELSIO_T1 is not set
366# CONFIG_IXGB is not set 451# CONFIG_IXGB is not set
367# CONFIG_S2IO is not set 452# CONFIG_S2IO is not set
368 453
@@ -375,6 +460,8 @@ CONFIG_NET_ETHERNET=y
375# Wireless LAN (non-hamradio) 460# Wireless LAN (non-hamradio)
376# 461#
377# CONFIG_NET_RADIO is not set 462# CONFIG_NET_RADIO is not set
463# CONFIG_IPW_DEBUG is not set
464CONFIG_IPW2200=y
378 465
379# 466#
380# Wan interfaces 467# Wan interfaces
@@ -386,6 +473,8 @@ CONFIG_NET_ETHERNET=y
386# CONFIG_SLIP is not set 473# CONFIG_SLIP is not set
387# CONFIG_SHAPER is not set 474# CONFIG_SHAPER is not set
388# CONFIG_NETCONSOLE is not set 475# CONFIG_NETCONSOLE is not set
476# CONFIG_NETPOLL is not set
477# CONFIG_NET_POLL_CONTROLLER is not set
389 478
390# 479#
391# ISDN subsystem 480# ISDN subsystem
@@ -415,19 +504,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
415# CONFIG_INPUT_EVBUG is not set 504# CONFIG_INPUT_EVBUG is not set
416 505
417# 506#
418# Input I/O drivers
419#
420# CONFIG_GAMEPORT is not set
421CONFIG_SOUND_GAMEPORT=y
422CONFIG_SERIO=y
423# CONFIG_SERIO_I8042 is not set
424CONFIG_SERIO_SERPORT=y
425# CONFIG_SERIO_CT82C710 is not set
426# CONFIG_SERIO_PCIPS2 is not set
427# CONFIG_SERIO_LIBPS2 is not set
428CONFIG_SERIO_RAW=y
429
430#
431# Input Device Drivers 507# Input Device Drivers
432# 508#
433# CONFIG_INPUT_KEYBOARD is not set 509# CONFIG_INPUT_KEYBOARD is not set
@@ -437,6 +513,17 @@ CONFIG_SERIO_RAW=y
437# CONFIG_INPUT_MISC is not set 513# CONFIG_INPUT_MISC is not set
438 514
439# 515#
516# Hardware I/O ports
517#
518CONFIG_SERIO=y
519# CONFIG_SERIO_I8042 is not set
520CONFIG_SERIO_SERPORT=y
521# CONFIG_SERIO_PCIPS2 is not set
522# CONFIG_SERIO_LIBPS2 is not set
523CONFIG_SERIO_RAW=y
524# CONFIG_GAMEPORT is not set
525
526#
440# Character devices 527# Character devices
441# 528#
442CONFIG_VT=y 529CONFIG_VT=y
@@ -457,6 +544,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
457# 544#
458CONFIG_SERIAL_CORE=y 545CONFIG_SERIAL_CORE=y
459CONFIG_SERIAL_CORE_CONSOLE=y 546CONFIG_SERIAL_CORE_CONSOLE=y
547# CONFIG_SERIAL_JSM is not set
460CONFIG_UNIX98_PTYS=y 548CONFIG_UNIX98_PTYS=y
461CONFIG_LEGACY_PTYS=y 549CONFIG_LEGACY_PTYS=y
462CONFIG_LEGACY_PTY_COUNT=256 550CONFIG_LEGACY_PTY_COUNT=256
@@ -483,6 +571,11 @@ CONFIG_COBALT_LCD=y
483# CONFIG_RAW_DRIVER is not set 571# CONFIG_RAW_DRIVER is not set
484 572
485# 573#
574# TPM devices
575#
576# CONFIG_TCG_TPM is not set
577
578#
486# I2C support 579# I2C support
487# 580#
488# CONFIG_I2C is not set 581# CONFIG_I2C is not set
@@ -493,10 +586,20 @@ CONFIG_COBALT_LCD=y
493# CONFIG_W1 is not set 586# CONFIG_W1 is not set
494 587
495# 588#
589# Hardware Monitoring support
590#
591# CONFIG_HWMON is not set
592# CONFIG_HWMON_VID is not set
593
594#
496# Misc devices 595# Misc devices
497# 596#
498 597
499# 598#
599# Multimedia Capabilities Port drivers
600#
601
602#
500# Multimedia devices 603# Multimedia devices
501# 604#
502# CONFIG_VIDEO_DEV is not set 605# CONFIG_VIDEO_DEV is not set
@@ -516,7 +619,6 @@ CONFIG_COBALT_LCD=y
516# 619#
517# CONFIG_VGA_CONSOLE is not set 620# CONFIG_VGA_CONSOLE is not set
518CONFIG_DUMMY_CONSOLE=y 621CONFIG_DUMMY_CONSOLE=y
519# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
520 622
521# 623#
522# Sound 624# Sound
@@ -526,13 +628,9 @@ CONFIG_DUMMY_CONSOLE=y
526# 628#
527# USB support 629# USB support
528# 630#
529# CONFIG_USB is not set
530CONFIG_USB_ARCH_HAS_HCD=y 631CONFIG_USB_ARCH_HAS_HCD=y
531CONFIG_USB_ARCH_HAS_OHCI=y 632CONFIG_USB_ARCH_HAS_OHCI=y
532 633# CONFIG_USB is not set
533#
534# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
535#
536 634
537# 635#
538# USB Gadget Support 636# USB Gadget Support
@@ -550,12 +648,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y
550# CONFIG_INFINIBAND is not set 648# CONFIG_INFINIBAND is not set
551 649
552# 650#
651# SN Devices
652#
653
654#
553# File systems 655# File systems
554# 656#
555CONFIG_EXT2_FS=y 657CONFIG_EXT2_FS=y
556CONFIG_EXT2_FS_XATTR=y 658CONFIG_EXT2_FS_XATTR=y
557CONFIG_EXT2_FS_POSIX_ACL=y 659CONFIG_EXT2_FS_POSIX_ACL=y
558CONFIG_EXT2_FS_SECURITY=y 660CONFIG_EXT2_FS_SECURITY=y
661# CONFIG_EXT2_FS_XIP is not set
559# CONFIG_EXT3_FS is not set 662# CONFIG_EXT3_FS is not set
560# CONFIG_JBD is not set 663# CONFIG_JBD is not set
561CONFIG_FS_MBCACHE=y 664CONFIG_FS_MBCACHE=y
@@ -565,10 +668,12 @@ CONFIG_FS_POSIX_ACL=y
565# CONFIG_XFS_FS is not set 668# CONFIG_XFS_FS is not set
566# CONFIG_MINIX_FS is not set 669# CONFIG_MINIX_FS is not set
567# CONFIG_ROMFS_FS is not set 670# CONFIG_ROMFS_FS is not set
671CONFIG_INOTIFY=y
568# CONFIG_QUOTA is not set 672# CONFIG_QUOTA is not set
569CONFIG_DNOTIFY=y 673CONFIG_DNOTIFY=y
570# CONFIG_AUTOFS_FS is not set 674# CONFIG_AUTOFS_FS is not set
571# CONFIG_AUTOFS4_FS is not set 675# CONFIG_AUTOFS4_FS is not set
676CONFIG_FUSE_FS=y
572 677
573# 678#
574# CD-ROM/DVD Filesystems 679# CD-ROM/DVD Filesystems
@@ -589,12 +694,10 @@ CONFIG_DNOTIFY=y
589CONFIG_PROC_FS=y 694CONFIG_PROC_FS=y
590CONFIG_PROC_KCORE=y 695CONFIG_PROC_KCORE=y
591CONFIG_SYSFS=y 696CONFIG_SYSFS=y
592# CONFIG_DEVFS_FS is not set
593CONFIG_DEVPTS_FS_XATTR=y
594CONFIG_DEVPTS_FS_SECURITY=y
595# CONFIG_TMPFS is not set 697# CONFIG_TMPFS is not set
596# CONFIG_HUGETLB_PAGE is not set 698# CONFIG_HUGETLB_PAGE is not set
597CONFIG_RAMFS=y 699CONFIG_RAMFS=y
700CONFIG_RELAYFS_FS=y
598 701
599# 702#
600# Miscellaneous filesystems 703# Miscellaneous filesystems
@@ -622,7 +725,7 @@ CONFIG_NFS_FS=y
622# CONFIG_NFS_DIRECTIO is not set 725# CONFIG_NFS_DIRECTIO is not set
623# CONFIG_NFSD is not set 726# CONFIG_NFSD is not set
624CONFIG_LOCKD=y 727CONFIG_LOCKD=y
625# CONFIG_EXPORTFS is not set 728CONFIG_NFS_COMMON=y
626CONFIG_SUNRPC=y 729CONFIG_SUNRPC=y
627# CONFIG_RPCSEC_GSS_KRB5 is not set 730# CONFIG_RPCSEC_GSS_KRB5 is not set
628# CONFIG_RPCSEC_GSS_SPKM3 is not set 731# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -631,6 +734,7 @@ CONFIG_SUNRPC=y
631# CONFIG_NCP_FS is not set 734# CONFIG_NCP_FS is not set
632# CONFIG_CODA_FS is not set 735# CONFIG_CODA_FS is not set
633# CONFIG_AFS_FS is not set 736# CONFIG_AFS_FS is not set
737# CONFIG_9P_FS is not set
634 738
635# 739#
636# Partition Types 740# Partition Types
@@ -651,7 +755,9 @@ CONFIG_MSDOS_PARTITION=y
651# 755#
652# Kernel hacking 756# Kernel hacking
653# 757#
758# CONFIG_PRINTK_TIME is not set
654# CONFIG_DEBUG_KERNEL is not set 759# CONFIG_DEBUG_KERNEL is not set
760CONFIG_LOG_BUF_SHIFT=14
655CONFIG_CROSSCOMPILE=y 761CONFIG_CROSSCOMPILE=y
656CONFIG_CMDLINE="" 762CONFIG_CMDLINE=""
657 763
@@ -665,7 +771,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
665# 771#
666# Cryptographic options 772# Cryptographic options
667# 773#
668# CONFIG_CRYPTO is not set 774CONFIG_CRYPTO=y
775CONFIG_CRYPTO_HMAC=y
776CONFIG_CRYPTO_NULL=y
777CONFIG_CRYPTO_MD4=y
778CONFIG_CRYPTO_MD5=y
779CONFIG_CRYPTO_SHA1=y
780CONFIG_CRYPTO_SHA256=y
781CONFIG_CRYPTO_SHA512=y
782CONFIG_CRYPTO_WP512=y
783CONFIG_CRYPTO_TGR192=y
784CONFIG_CRYPTO_DES=y
785CONFIG_CRYPTO_BLOWFISH=y
786CONFIG_CRYPTO_TWOFISH=y
787CONFIG_CRYPTO_SERPENT=y
788CONFIG_CRYPTO_AES=y
789CONFIG_CRYPTO_CAST5=y
790CONFIG_CRYPTO_CAST6=y
791CONFIG_CRYPTO_TEA=y
792CONFIG_CRYPTO_ARC4=y
793CONFIG_CRYPTO_KHAZAD=y
794CONFIG_CRYPTO_ANUBIS=y
795CONFIG_CRYPTO_DEFLATE=y
796CONFIG_CRYPTO_MICHAEL_MIC=y
797CONFIG_CRYPTO_CRC32C=y
798# CONFIG_CRYPTO_TEST is not set
669 799
670# 800#
671# Hardware crypto devices 801# Hardware crypto devices
@@ -675,7 +805,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
675# Library routines 805# Library routines
676# 806#
677# CONFIG_CRC_CCITT is not set 807# CONFIG_CRC_CCITT is not set
678# CONFIG_CRC32 is not set 808CONFIG_CRC16=y
679# CONFIG_LIBCRC32C is not set 809CONFIG_CRC32=y
680CONFIG_GENERIC_HARDIRQS=y 810CONFIG_LIBCRC32C=y
681CONFIG_GENERIC_IRQ_PROBE=y 811CONFIG_ZLIB_INFLATE=y
812CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 962fc14b58c2..6501144ec612 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:01 2005 4# Thu Oct 20 22:25:26 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29CONFIG_HOTPLUG=y 27CONFIG_HOTPLUG=y
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,63 +59,79 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69CONFIG_MIPS_DB1000=y
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
83CONFIG_SOC_AU1X00=y 102# CONFIG_SGI_IP27 is not set
84CONFIG_SOC_AU1000=y 103# CONFIG_SGI_IP32 is not set
85# CONFIG_SOC_AU1100 is not set 104# CONFIG_SIBYTE_BIGSUR is not set
86# CONFIG_SOC_AU1500 is not set 105# CONFIG_SIBYTE_SWARM is not set
87# CONFIG_SOC_AU1550 is not set 106# CONFIG_SIBYTE_SENTOSA is not set
88# CONFIG_MIPS_PB1000 is not set 107# CONFIG_SIBYTE_RHONE is not set
89# CONFIG_MIPS_PB1100 is not set 108# CONFIG_SIBYTE_CARMEL is not set
90# CONFIG_MIPS_PB1500 is not set 109# CONFIG_SIBYTE_PTSWARM is not set
91# CONFIG_MIPS_PB1550 is not set 110# CONFIG_SIBYTE_LITTLESUR is not set
92CONFIG_MIPS_DB1000=y 111# CONFIG_SIBYTE_CRHINE is not set
93# CONFIG_MIPS_DB1100 is not set 112# CONFIG_SIBYTE_CRHONE is not set
94# CONFIG_MIPS_DB1500 is not set
95# CONFIG_MIPS_DB1550 is not set
96# CONFIG_MIPS_BOSPORUS is not set
97# CONFIG_MIPS_MIRAGE is not set
98# CONFIG_MIPS_XXS1500 is not set
99# CONFIG_MIPS_MTX1 is not set
100# CONFIG_SIBYTE_SB1xxx_SOC is not set
101# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
102# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
103CONFIG_RWSEM_GENERIC_SPINLOCK=y 117CONFIG_RWSEM_GENERIC_SPINLOCK=y
104CONFIG_GENERIC_CALIBRATE_DELAY=y 118CONFIG_GENERIC_CALIBRATE_DELAY=y
105CONFIG_HAVE_DEC_LOCK=y
106CONFIG_DMA_NONCOHERENT=y 119CONFIG_DMA_NONCOHERENT=y
107CONFIG_DMA_NEED_PCI_MAP_STATE=y 120CONFIG_DMA_NEED_PCI_MAP_STATE=y
121# CONFIG_CPU_BIG_ENDIAN is not set
108CONFIG_CPU_LITTLE_ENDIAN=y 122CONFIG_CPU_LITTLE_ENDIAN=y
123CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
124CONFIG_SOC_AU1000=y
125CONFIG_SOC_AU1X00=y
109CONFIG_MIPS_L1_CACHE_SHIFT=5 126CONFIG_MIPS_L1_CACHE_SHIFT=5
110 127
111# 128#
112# CPU selection 129# CPU selection
113# 130#
114CONFIG_CPU_MIPS32=y 131CONFIG_CPU_MIPS32_R1=y
115# CONFIG_CPU_MIPS64 is not set 132# CONFIG_CPU_MIPS32_R2 is not set
133# CONFIG_CPU_MIPS64_R1 is not set
134# CONFIG_CPU_MIPS64_R2 is not set
116# CONFIG_CPU_R3000 is not set 135# CONFIG_CPU_R3000 is not set
117# CONFIG_CPU_TX39XX is not set 136# CONFIG_CPU_TX39XX is not set
118# CONFIG_CPU_VR41XX is not set 137# CONFIG_CPU_VR41XX is not set
@@ -128,15 +147,39 @@ CONFIG_CPU_MIPS32=y
128# CONFIG_CPU_RM7000 is not set 147# CONFIG_CPU_RM7000 is not set
129# CONFIG_CPU_RM9000 is not set 148# CONFIG_CPU_RM9000 is not set
130# CONFIG_CPU_SB1 is not set 149# CONFIG_CPU_SB1 is not set
150CONFIG_SYS_HAS_CPU_MIPS32_R1=y
151CONFIG_CPU_MIPS32=y
152CONFIG_CPU_MIPSR1=y
153CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
154CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
155
156#
157# Kernel type
158#
159CONFIG_32BIT=y
160# CONFIG_64BIT is not set
131CONFIG_PAGE_SIZE_4KB=y 161CONFIG_PAGE_SIZE_4KB=y
132# CONFIG_PAGE_SIZE_8KB is not set 162# CONFIG_PAGE_SIZE_8KB is not set
133# CONFIG_PAGE_SIZE_16KB is not set 163# CONFIG_PAGE_SIZE_16KB is not set
134# CONFIG_PAGE_SIZE_64KB is not set 164# CONFIG_PAGE_SIZE_64KB is not set
135CONFIG_CPU_HAS_PREFETCH=y 165CONFIG_CPU_HAS_PREFETCH=y
166# CONFIG_MIPS_MT is not set
136CONFIG_64BIT_PHYS_ADDR=y 167CONFIG_64BIT_PHYS_ADDR=y
137# CONFIG_CPU_ADVANCED is not set 168# CONFIG_CPU_ADVANCED is not set
138CONFIG_CPU_HAS_LLSC=y 169CONFIG_CPU_HAS_LLSC=y
139CONFIG_CPU_HAS_SYNC=y 170CONFIG_CPU_HAS_SYNC=y
171CONFIG_GENERIC_HARDIRQS=y
172CONFIG_GENERIC_IRQ_PROBE=y
173CONFIG_ARCH_FLATMEM_ENABLE=y
174CONFIG_SELECT_MEMORY_MODEL=y
175CONFIG_FLATMEM_MANUAL=y
176# CONFIG_DISCONTIGMEM_MANUAL is not set
177# CONFIG_SPARSEMEM_MANUAL is not set
178CONFIG_FLATMEM=y
179CONFIG_FLAT_NODE_MEM_MAP=y
180# CONFIG_SPARSEMEM_STATIC is not set
181CONFIG_PREEMPT_NONE=y
182# CONFIG_PREEMPT_VOLUNTARY is not set
140# CONFIG_PREEMPT is not set 183# CONFIG_PREEMPT is not set
141 184
142# 185#
@@ -152,6 +195,8 @@ CONFIG_MMU=y
152CONFIG_PCCARD=m 195CONFIG_PCCARD=m
153# CONFIG_PCMCIA_DEBUG is not set 196# CONFIG_PCMCIA_DEBUG is not set
154CONFIG_PCMCIA=m 197CONFIG_PCMCIA=m
198CONFIG_PCMCIA_LOAD_CIS=y
199CONFIG_PCMCIA_IOCTL=y
155 200
156# 201#
157# PC-card bridges 202# PC-card bridges
@@ -169,6 +214,100 @@ CONFIG_PCMCIA=m
169CONFIG_BINFMT_ELF=y 214CONFIG_BINFMT_ELF=y
170# CONFIG_BINFMT_MISC is not set 215# CONFIG_BINFMT_MISC is not set
171CONFIG_TRAD_SIGNALS=y 216CONFIG_TRAD_SIGNALS=y
217# CONFIG_PM is not set
218
219#
220# Networking
221#
222CONFIG_NET=y
223
224#
225# Networking options
226#
227CONFIG_PACKET=y
228# CONFIG_PACKET_MMAP is not set
229CONFIG_UNIX=y
230CONFIG_XFRM=y
231CONFIG_XFRM_USER=m
232CONFIG_NET_KEY=y
233CONFIG_INET=y
234CONFIG_IP_MULTICAST=y
235# CONFIG_IP_ADVANCED_ROUTER is not set
236CONFIG_IP_FIB_HASH=y
237CONFIG_IP_PNP=y
238# CONFIG_IP_PNP_DHCP is not set
239CONFIG_IP_PNP_BOOTP=y
240# CONFIG_IP_PNP_RARP is not set
241# CONFIG_NET_IPIP is not set
242# CONFIG_NET_IPGRE is not set
243# CONFIG_IP_MROUTE is not set
244# CONFIG_ARPD is not set
245# CONFIG_SYN_COOKIES is not set
246# CONFIG_INET_AH is not set
247# CONFIG_INET_ESP is not set
248# CONFIG_INET_IPCOMP is not set
249CONFIG_INET_TUNNEL=m
250CONFIG_INET_DIAG=y
251CONFIG_INET_TCP_DIAG=y
252# CONFIG_TCP_CONG_ADVANCED is not set
253CONFIG_TCP_CONG_BIC=y
254
255#
256# IP: Virtual Server Configuration
257#
258# CONFIG_IP_VS is not set
259# CONFIG_IPV6 is not set
260CONFIG_NETFILTER=y
261# CONFIG_NETFILTER_DEBUG is not set
262CONFIG_NETFILTER_NETLINK=m
263CONFIG_NETFILTER_NETLINK_QUEUE=m
264CONFIG_NETFILTER_NETLINK_LOG=m
265
266#
267# IP: Netfilter Configuration
268#
269# CONFIG_IP_NF_CONNTRACK is not set
270CONFIG_IP_NF_PPTP=m
271# CONFIG_IP_NF_QUEUE is not set
272# CONFIG_IP_NF_IPTABLES is not set
273# CONFIG_IP_NF_ARPTABLES is not set
274
275#
276# DCCP Configuration (EXPERIMENTAL)
277#
278# CONFIG_IP_DCCP is not set
279
280#
281# SCTP Configuration (EXPERIMENTAL)
282#
283# CONFIG_IP_SCTP is not set
284# CONFIG_ATM is not set
285# CONFIG_BRIDGE is not set
286# CONFIG_VLAN_8021Q is not set
287# CONFIG_DECNET is not set
288# CONFIG_LLC2 is not set
289# CONFIG_IPX is not set
290# CONFIG_ATALK is not set
291# CONFIG_X25 is not set
292# CONFIG_LAPB is not set
293# CONFIG_NET_DIVERT is not set
294# CONFIG_ECONET is not set
295# CONFIG_WAN_ROUTER is not set
296# CONFIG_NET_SCHED is not set
297# CONFIG_NET_CLS_ROUTE is not set
298
299#
300# Network testing
301#
302# CONFIG_NET_PKTGEN is not set
303# CONFIG_HAMRADIO is not set
304# CONFIG_IRDA is not set
305# CONFIG_BT is not set
306CONFIG_IEEE80211=m
307# CONFIG_IEEE80211_DEBUG is not set
308CONFIG_IEEE80211_CRYPT_WEP=m
309CONFIG_IEEE80211_CRYPT_CCMP=m
310CONFIG_IEEE80211_CRYPT_TKIP=m
172 311
173# 312#
174# Device Drivers 313# Device Drivers
@@ -179,12 +318,86 @@ CONFIG_TRAD_SIGNALS=y
179# 318#
180CONFIG_STANDALONE=y 319CONFIG_STANDALONE=y
181CONFIG_PREVENT_FIRMWARE_BUILD=y 320CONFIG_PREVENT_FIRMWARE_BUILD=y
182# CONFIG_FW_LOADER is not set 321CONFIG_FW_LOADER=m
322
323#
324# Connector - unified userspace <-> kernelspace linker
325#
326CONFIG_CONNECTOR=m
183 327
184# 328#
185# Memory Technology Devices (MTD) 329# Memory Technology Devices (MTD)
186# 330#
187# CONFIG_MTD is not set 331CONFIG_MTD=y
332# CONFIG_MTD_DEBUG is not set
333# CONFIG_MTD_CONCAT is not set
334CONFIG_MTD_PARTITIONS=y
335# CONFIG_MTD_REDBOOT_PARTS is not set
336# CONFIG_MTD_CMDLINE_PARTS is not set
337
338#
339# User Modules And Translation Layers
340#
341CONFIG_MTD_CHAR=y
342CONFIG_MTD_BLOCK=y
343# CONFIG_FTL is not set
344# CONFIG_NFTL is not set
345# CONFIG_INFTL is not set
346
347#
348# RAM/ROM/Flash chip drivers
349#
350CONFIG_MTD_CFI=y
351# CONFIG_MTD_JEDECPROBE is not set
352CONFIG_MTD_GEN_PROBE=y
353# CONFIG_MTD_CFI_ADV_OPTIONS is not set
354CONFIG_MTD_MAP_BANK_WIDTH_1=y
355CONFIG_MTD_MAP_BANK_WIDTH_2=y
356CONFIG_MTD_MAP_BANK_WIDTH_4=y
357# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
358# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
359# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
360CONFIG_MTD_CFI_I1=y
361CONFIG_MTD_CFI_I2=y
362# CONFIG_MTD_CFI_I4 is not set
363# CONFIG_MTD_CFI_I8 is not set
364# CONFIG_MTD_CFI_INTELEXT is not set
365CONFIG_MTD_CFI_AMDSTD=y
366CONFIG_MTD_CFI_AMDSTD_RETRY=0
367# CONFIG_MTD_CFI_STAA is not set
368CONFIG_MTD_CFI_UTIL=y
369# CONFIG_MTD_RAM is not set
370# CONFIG_MTD_ROM is not set
371# CONFIG_MTD_ABSENT is not set
372
373#
374# Mapping drivers for chip access
375#
376# CONFIG_MTD_COMPLEX_MAPPINGS is not set
377# CONFIG_MTD_PHYSMAP is not set
378CONFIG_MTD_ALCHEMY=y
379# CONFIG_MTD_PLATRAM is not set
380
381#
382# Self-contained MTD device drivers
383#
384# CONFIG_MTD_SLRAM is not set
385# CONFIG_MTD_PHRAM is not set
386# CONFIG_MTD_MTDRAM is not set
387# CONFIG_MTD_BLKMTD is not set
388# CONFIG_MTD_BLOCK2MTD is not set
389
390#
391# Disk-On-Chip Device Drivers
392#
393# CONFIG_MTD_DOC2000 is not set
394# CONFIG_MTD_DOC2001 is not set
395# CONFIG_MTD_DOC2001PLUS is not set
396
397#
398# NAND Flash Device Drivers
399#
400# CONFIG_MTD_NAND is not set
188 401
189# 402#
190# Parallel port support 403# Parallel port support
@@ -198,14 +411,12 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
198# 411#
199# Block devices 412# Block devices
200# 413#
201# CONFIG_BLK_DEV_FD is not set
202# CONFIG_BLK_DEV_COW_COMMON is not set 414# CONFIG_BLK_DEV_COW_COMMON is not set
203CONFIG_BLK_DEV_LOOP=y 415CONFIG_BLK_DEV_LOOP=y
204# CONFIG_BLK_DEV_CRYPTOLOOP is not set 416# CONFIG_BLK_DEV_CRYPTOLOOP is not set
205# CONFIG_BLK_DEV_NBD is not set 417# CONFIG_BLK_DEV_NBD is not set
206# CONFIG_BLK_DEV_RAM is not set 418# CONFIG_BLK_DEV_RAM is not set
207CONFIG_BLK_DEV_RAM_COUNT=16 419CONFIG_BLK_DEV_RAM_COUNT=16
208CONFIG_INITRAMFS_SOURCE=""
209# CONFIG_LBD is not set 420# CONFIG_LBD is not set
210CONFIG_CDROM_PKTCDVD=m 421CONFIG_CDROM_PKTCDVD=m
211CONFIG_CDROM_PKTCDVD_BUFFERS=8 422CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -228,6 +439,7 @@ CONFIG_ATA_OVER_ETH=m
228# 439#
229# SCSI device support 440# SCSI device support
230# 441#
442CONFIG_RAID_ATTRS=m
231# CONFIG_SCSI is not set 443# CONFIG_SCSI is not set
232 444
233# 445#
@@ -238,6 +450,7 @@ CONFIG_ATA_OVER_ETH=m
238# 450#
239# Fusion MPT device support 451# Fusion MPT device support
240# 452#
453# CONFIG_FUSION is not set
241 454
242# 455#
243# IEEE 1394 (FireWire) support 456# IEEE 1394 (FireWire) support
@@ -248,94 +461,28 @@ CONFIG_ATA_OVER_ETH=m
248# 461#
249 462
250# 463#
251# Networking support 464# Network device support
252#
253CONFIG_NET=y
254
255#
256# Networking options
257#
258CONFIG_PACKET=y
259# CONFIG_PACKET_MMAP is not set
260CONFIG_NETLINK_DEV=y
261CONFIG_UNIX=y
262CONFIG_NET_KEY=y
263CONFIG_INET=y
264CONFIG_IP_MULTICAST=y
265# CONFIG_IP_ADVANCED_ROUTER is not set
266CONFIG_IP_PNP=y
267# CONFIG_IP_PNP_DHCP is not set
268CONFIG_IP_PNP_BOOTP=y
269# CONFIG_IP_PNP_RARP is not set
270# CONFIG_NET_IPIP is not set
271# CONFIG_NET_IPGRE is not set
272# CONFIG_IP_MROUTE is not set
273# CONFIG_ARPD is not set
274# CONFIG_SYN_COOKIES is not set
275# CONFIG_INET_AH is not set
276# CONFIG_INET_ESP is not set
277# CONFIG_INET_IPCOMP is not set
278CONFIG_INET_TUNNEL=m
279CONFIG_IP_TCPDIAG=m
280# CONFIG_IP_TCPDIAG_IPV6 is not set
281
282#
283# IP: Virtual Server Configuration
284#
285# CONFIG_IP_VS is not set
286# CONFIG_IPV6 is not set
287CONFIG_NETFILTER=y
288# CONFIG_NETFILTER_DEBUG is not set
289
290#
291# IP: Netfilter Configuration
292# 465#
293# CONFIG_IP_NF_CONNTRACK is not set 466CONFIG_NETDEVICES=y
294CONFIG_IP_NF_CONNTRACK_MARK=y 467# CONFIG_DUMMY is not set
295# CONFIG_IP_NF_QUEUE is not set 468# CONFIG_BONDING is not set
296# CONFIG_IP_NF_IPTABLES is not set 469# CONFIG_EQUALIZER is not set
297# CONFIG_IP_NF_ARPTABLES is not set 470# CONFIG_TUN is not set
298CONFIG_XFRM=y
299CONFIG_XFRM_USER=m
300
301#
302# SCTP Configuration (EXPERIMENTAL)
303#
304# CONFIG_IP_SCTP is not set
305# CONFIG_ATM is not set
306# CONFIG_BRIDGE is not set
307# CONFIG_VLAN_8021Q is not set
308# CONFIG_DECNET is not set
309# CONFIG_LLC2 is not set
310# CONFIG_IPX is not set
311# CONFIG_ATALK is not set
312# CONFIG_X25 is not set
313# CONFIG_LAPB is not set
314# CONFIG_NET_DIVERT is not set
315# CONFIG_ECONET is not set
316# CONFIG_WAN_ROUTER is not set
317 471
318# 472#
319# QoS and/or fair queueing 473# PHY device support
320# 474#
321# CONFIG_NET_SCHED is not set 475CONFIG_PHYLIB=m
322# CONFIG_NET_CLS_ROUTE is not set 476CONFIG_PHYCONTROL=y
323 477
324# 478#
325# Network testing 479# MII PHY device drivers
326# 480#
327# CONFIG_NET_PKTGEN is not set 481CONFIG_MARVELL_PHY=m
328# CONFIG_NETPOLL is not set 482CONFIG_DAVICOM_PHY=m
329# CONFIG_NET_POLL_CONTROLLER is not set 483CONFIG_QSEMI_PHY=m
330# CONFIG_HAMRADIO is not set 484CONFIG_LXT_PHY=m
331# CONFIG_IRDA is not set 485CONFIG_CICADA_PHY=m
332# CONFIG_BT is not set
333CONFIG_NETDEVICES=y
334# CONFIG_DUMMY is not set
335# CONFIG_BONDING is not set
336# CONFIG_EQUALIZER is not set
337# CONFIG_TUN is not set
338# CONFIG_ETHERTAP is not set
339 486
340# 487#
341# Ethernet (10 or 100Mbit) 488# Ethernet (10 or 100Mbit)
@@ -389,6 +536,8 @@ CONFIG_PPPOE=m
389# CONFIG_SLIP is not set 536# CONFIG_SLIP is not set
390# CONFIG_SHAPER is not set 537# CONFIG_SHAPER is not set
391# CONFIG_NETCONSOLE is not set 538# CONFIG_NETCONSOLE is not set
539# CONFIG_NETPOLL is not set
540# CONFIG_NET_POLL_CONTROLLER is not set
392 541
393# 542#
394# ISDN subsystem 543# ISDN subsystem
@@ -418,18 +567,6 @@ CONFIG_INPUT_EVDEV=y
418# CONFIG_INPUT_EVBUG is not set 567# CONFIG_INPUT_EVBUG is not set
419 568
420# 569#
421# Input I/O drivers
422#
423# CONFIG_GAMEPORT is not set
424CONFIG_SOUND_GAMEPORT=y
425CONFIG_SERIO=y
426# CONFIG_SERIO_I8042 is not set
427CONFIG_SERIO_SERPORT=y
428# CONFIG_SERIO_CT82C710 is not set
429# CONFIG_SERIO_LIBPS2 is not set
430CONFIG_SERIO_RAW=m
431
432#
433# Input Device Drivers 570# Input Device Drivers
434# 571#
435# CONFIG_INPUT_KEYBOARD is not set 572# CONFIG_INPUT_KEYBOARD is not set
@@ -439,6 +576,16 @@ CONFIG_SERIO_RAW=m
439# CONFIG_INPUT_MISC is not set 576# CONFIG_INPUT_MISC is not set
440 577
441# 578#
579# Hardware I/O ports
580#
581CONFIG_SERIO=y
582# CONFIG_SERIO_I8042 is not set
583CONFIG_SERIO_SERPORT=y
584# CONFIG_SERIO_LIBPS2 is not set
585CONFIG_SERIO_RAW=m
586# CONFIG_GAMEPORT is not set
587
588#
442# Character devices 589# Character devices
443# 590#
444CONFIG_VT=y 591CONFIG_VT=y
@@ -473,14 +620,14 @@ CONFIG_LEGACY_PTY_COUNT=256
473# Watchdog Cards 620# Watchdog Cards
474# 621#
475# CONFIG_WATCHDOG is not set 622# CONFIG_WATCHDOG is not set
476CONFIG_RTC=y 623# CONFIG_RTC is not set
624# CONFIG_GEN_RTC is not set
477# CONFIG_DTLK is not set 625# CONFIG_DTLK is not set
478# CONFIG_R3964 is not set 626# CONFIG_R3964 is not set
479 627
480# 628#
481# Ftape, the floppy tape device driver 629# Ftape, the floppy tape device driver
482# 630#
483# CONFIG_DRM is not set
484 631
485# 632#
486# PCMCIA character devices 633# PCMCIA character devices
@@ -489,6 +636,10 @@ CONFIG_SYNCLINK_CS=m
489# CONFIG_RAW_DRIVER is not set 636# CONFIG_RAW_DRIVER is not set
490 637
491# 638#
639# TPM devices
640#
641
642#
492# I2C support 643# I2C support
493# 644#
494# CONFIG_I2C is not set 645# CONFIG_I2C is not set
@@ -499,10 +650,20 @@ CONFIG_SYNCLINK_CS=m
499# CONFIG_W1 is not set 650# CONFIG_W1 is not set
500 651
501# 652#
653# Hardware Monitoring support
654#
655# CONFIG_HWMON is not set
656# CONFIG_HWMON_VID is not set
657
658#
502# Misc devices 659# Misc devices
503# 660#
504 661
505# 662#
663# Multimedia Capabilities Port drivers
664#
665
666#
506# Multimedia devices 667# Multimedia devices
507# 668#
508# CONFIG_VIDEO_DEV is not set 669# CONFIG_VIDEO_DEV is not set
@@ -522,7 +683,6 @@ CONFIG_SYNCLINK_CS=m
522# 683#
523# CONFIG_VGA_CONSOLE is not set 684# CONFIG_VGA_CONSOLE is not set
524CONFIG_DUMMY_CONSOLE=y 685CONFIG_DUMMY_CONSOLE=y
525# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
526 686
527# 687#
528# Sound 688# Sound
@@ -532,12 +692,9 @@ CONFIG_DUMMY_CONSOLE=y
532# 692#
533# USB support 693# USB support
534# 694#
535# CONFIG_USB_ARCH_HAS_HCD is not set 695CONFIG_USB_ARCH_HAS_HCD=y
536# CONFIG_USB_ARCH_HAS_OHCI is not set 696CONFIG_USB_ARCH_HAS_OHCI=y
537 697# CONFIG_USB is not set
538#
539# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
540#
541 698
542# 699#
543# USB Gadget Support 700# USB Gadget Support
@@ -552,7 +709,10 @@ CONFIG_DUMMY_CONSOLE=y
552# 709#
553# InfiniBand support 710# InfiniBand support
554# 711#
555# CONFIG_INFINIBAND is not set 712
713#
714# SN Devices
715#
556 716
557# 717#
558# File systems 718# File systems
@@ -561,6 +721,7 @@ CONFIG_EXT2_FS=y
561CONFIG_EXT2_FS_XATTR=y 721CONFIG_EXT2_FS_XATTR=y
562CONFIG_EXT2_FS_POSIX_ACL=y 722CONFIG_EXT2_FS_POSIX_ACL=y
563# CONFIG_EXT2_FS_SECURITY is not set 723# CONFIG_EXT2_FS_SECURITY is not set
724# CONFIG_EXT2_FS_XIP is not set
564CONFIG_EXT3_FS=y 725CONFIG_EXT3_FS=y
565CONFIG_EXT3_FS_XATTR=y 726CONFIG_EXT3_FS_XATTR=y
566CONFIG_EXT3_FS_POSIX_ACL=y 727CONFIG_EXT3_FS_POSIX_ACL=y
@@ -579,10 +740,12 @@ CONFIG_FS_POSIX_ACL=y
579# CONFIG_XFS_FS is not set 740# CONFIG_XFS_FS is not set
580# CONFIG_MINIX_FS is not set 741# CONFIG_MINIX_FS is not set
581# CONFIG_ROMFS_FS is not set 742# CONFIG_ROMFS_FS is not set
743CONFIG_INOTIFY=y
582# CONFIG_QUOTA is not set 744# CONFIG_QUOTA is not set
583CONFIG_DNOTIFY=y 745CONFIG_DNOTIFY=y
584CONFIG_AUTOFS_FS=m 746CONFIG_AUTOFS_FS=m
585CONFIG_AUTOFS4_FS=m 747CONFIG_AUTOFS4_FS=m
748CONFIG_FUSE_FS=m
586 749
587# 750#
588# CD-ROM/DVD Filesystems 751# CD-ROM/DVD Filesystems
@@ -603,13 +766,10 @@ CONFIG_AUTOFS4_FS=m
603CONFIG_PROC_FS=y 766CONFIG_PROC_FS=y
604CONFIG_PROC_KCORE=y 767CONFIG_PROC_KCORE=y
605CONFIG_SYSFS=y 768CONFIG_SYSFS=y
606# CONFIG_DEVFS_FS is not set
607CONFIG_DEVPTS_FS_XATTR=y
608CONFIG_DEVPTS_FS_SECURITY=y
609CONFIG_TMPFS=y 769CONFIG_TMPFS=y
610# CONFIG_TMPFS_XATTR is not set
611# CONFIG_HUGETLB_PAGE is not set 770# CONFIG_HUGETLB_PAGE is not set
612CONFIG_RAMFS=y 771CONFIG_RAMFS=y
772CONFIG_RELAYFS_FS=m
613 773
614# 774#
615# Miscellaneous filesystems 775# Miscellaneous filesystems
@@ -621,6 +781,8 @@ CONFIG_RAMFS=y
621# CONFIG_BEFS_FS is not set 781# CONFIG_BEFS_FS is not set
622# CONFIG_BFS_FS is not set 782# CONFIG_BFS_FS is not set
623# CONFIG_EFS_FS is not set 783# CONFIG_EFS_FS is not set
784# CONFIG_JFFS_FS is not set
785# CONFIG_JFFS2_FS is not set
624CONFIG_CRAMFS=m 786CONFIG_CRAMFS=m
625# CONFIG_VXFS_FS is not set 787# CONFIG_VXFS_FS is not set
626# CONFIG_HPFS_FS is not set 788# CONFIG_HPFS_FS is not set
@@ -641,6 +803,7 @@ CONFIG_NFSD=m
641CONFIG_ROOT_NFS=y 803CONFIG_ROOT_NFS=y
642CONFIG_LOCKD=y 804CONFIG_LOCKD=y
643CONFIG_EXPORTFS=m 805CONFIG_EXPORTFS=m
806CONFIG_NFS_COMMON=y
644CONFIG_SUNRPC=y 807CONFIG_SUNRPC=y
645# CONFIG_RPCSEC_GSS_KRB5 is not set 808# CONFIG_RPCSEC_GSS_KRB5 is not set
646# CONFIG_RPCSEC_GSS_SPKM3 is not set 809# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -650,6 +813,7 @@ CONFIG_SMB_FS=m
650# CONFIG_NCP_FS is not set 813# CONFIG_NCP_FS is not set
651# CONFIG_CODA_FS is not set 814# CONFIG_CODA_FS is not set
652# CONFIG_AFS_FS is not set 815# CONFIG_AFS_FS is not set
816# CONFIG_9P_FS is not set
653 817
654# 818#
655# Partition Types 819# Partition Types
@@ -709,7 +873,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
709# 873#
710# Kernel hacking 874# Kernel hacking
711# 875#
876# CONFIG_PRINTK_TIME is not set
712# CONFIG_DEBUG_KERNEL is not set 877# CONFIG_DEBUG_KERNEL is not set
878CONFIG_LOG_BUF_SHIFT=14
713CONFIG_CROSSCOMPILE=y 879CONFIG_CROSSCOMPILE=y
714CONFIG_CMDLINE="" 880CONFIG_CMDLINE=""
715 881
@@ -725,26 +891,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
725# 891#
726CONFIG_CRYPTO=y 892CONFIG_CRYPTO=y
727CONFIG_CRYPTO_HMAC=y 893CONFIG_CRYPTO_HMAC=y
728CONFIG_CRYPTO_NULL=y 894CONFIG_CRYPTO_NULL=m
729# CONFIG_CRYPTO_MD4 is not set 895CONFIG_CRYPTO_MD4=m
730# CONFIG_CRYPTO_MD5 is not set 896CONFIG_CRYPTO_MD5=m
731# CONFIG_CRYPTO_SHA1 is not set 897CONFIG_CRYPTO_SHA1=m
732# CONFIG_CRYPTO_SHA256 is not set 898CONFIG_CRYPTO_SHA256=m
733CONFIG_CRYPTO_SHA512=y 899CONFIG_CRYPTO_SHA512=m
734CONFIG_CRYPTO_WP512=m 900CONFIG_CRYPTO_WP512=m
735# CONFIG_CRYPTO_DES is not set 901CONFIG_CRYPTO_TGR192=m
736# CONFIG_CRYPTO_BLOWFISH is not set 902CONFIG_CRYPTO_DES=m
737CONFIG_CRYPTO_TWOFISH=y 903CONFIG_CRYPTO_BLOWFISH=m
738# CONFIG_CRYPTO_SERPENT is not set 904CONFIG_CRYPTO_TWOFISH=m
905CONFIG_CRYPTO_SERPENT=m
739CONFIG_CRYPTO_AES=m 906CONFIG_CRYPTO_AES=m
740# CONFIG_CRYPTO_CAST5 is not set 907CONFIG_CRYPTO_CAST5=m
741# CONFIG_CRYPTO_CAST6 is not set 908CONFIG_CRYPTO_CAST6=m
742CONFIG_CRYPTO_TEA=m 909CONFIG_CRYPTO_TEA=m
743# CONFIG_CRYPTO_ARC4 is not set 910CONFIG_CRYPTO_ARC4=m
744CONFIG_CRYPTO_KHAZAD=m 911CONFIG_CRYPTO_KHAZAD=m
745CONFIG_CRYPTO_ANUBIS=m 912CONFIG_CRYPTO_ANUBIS=m
746CONFIG_CRYPTO_DEFLATE=y 913CONFIG_CRYPTO_DEFLATE=m
747CONFIG_CRYPTO_MICHAEL_MIC=y 914CONFIG_CRYPTO_MICHAEL_MIC=m
748CONFIG_CRYPTO_CRC32C=m 915CONFIG_CRYPTO_CRC32C=m
749# CONFIG_CRYPTO_TEST is not set 916# CONFIG_CRYPTO_TEST is not set
750 917
@@ -756,9 +923,8 @@ CONFIG_CRYPTO_CRC32C=m
756# Library routines 923# Library routines
757# 924#
758CONFIG_CRC_CCITT=m 925CONFIG_CRC_CCITT=m
926CONFIG_CRC16=m
759CONFIG_CRC32=y 927CONFIG_CRC32=y
760CONFIG_LIBCRC32C=m 928CONFIG_LIBCRC32C=m
761CONFIG_ZLIB_INFLATE=y 929CONFIG_ZLIB_INFLATE=m
762CONFIG_ZLIB_DEFLATE=y 930CONFIG_ZLIB_DEFLATE=m
763CONFIG_GENERIC_HARDIRQS=y
764CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index 6a528d479d70..b8cd2cd923dd 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:01 2005 4# Thu Oct 20 22:25:29 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29CONFIG_HOTPLUG=y 27CONFIG_HOTPLUG=y
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,63 +59,79 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70CONFIG_MIPS_DB1100=y
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
83CONFIG_SOC_AU1X00=y 102# CONFIG_SGI_IP27 is not set
84# CONFIG_SOC_AU1000 is not set 103# CONFIG_SGI_IP32 is not set
85CONFIG_SOC_AU1100=y 104# CONFIG_SIBYTE_BIGSUR is not set
86# CONFIG_SOC_AU1500 is not set 105# CONFIG_SIBYTE_SWARM is not set
87# CONFIG_SOC_AU1550 is not set 106# CONFIG_SIBYTE_SENTOSA is not set
88# CONFIG_MIPS_PB1000 is not set 107# CONFIG_SIBYTE_RHONE is not set
89# CONFIG_MIPS_PB1100 is not set 108# CONFIG_SIBYTE_CARMEL is not set
90# CONFIG_MIPS_PB1500 is not set 109# CONFIG_SIBYTE_PTSWARM is not set
91# CONFIG_MIPS_PB1550 is not set 110# CONFIG_SIBYTE_LITTLESUR is not set
92# CONFIG_MIPS_DB1000 is not set 111# CONFIG_SIBYTE_CRHINE is not set
93CONFIG_MIPS_DB1100=y 112# CONFIG_SIBYTE_CRHONE is not set
94# CONFIG_MIPS_DB1500 is not set
95# CONFIG_MIPS_DB1550 is not set
96# CONFIG_MIPS_BOSPORUS is not set
97# CONFIG_MIPS_MIRAGE is not set
98# CONFIG_MIPS_XXS1500 is not set
99# CONFIG_MIPS_MTX1 is not set
100# CONFIG_SIBYTE_SB1xxx_SOC is not set
101# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
102# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
103CONFIG_RWSEM_GENERIC_SPINLOCK=y 117CONFIG_RWSEM_GENERIC_SPINLOCK=y
104CONFIG_GENERIC_CALIBRATE_DELAY=y 118CONFIG_GENERIC_CALIBRATE_DELAY=y
105CONFIG_HAVE_DEC_LOCK=y
106CONFIG_DMA_NONCOHERENT=y 119CONFIG_DMA_NONCOHERENT=y
107CONFIG_DMA_NEED_PCI_MAP_STATE=y 120CONFIG_DMA_NEED_PCI_MAP_STATE=y
121# CONFIG_CPU_BIG_ENDIAN is not set
108CONFIG_CPU_LITTLE_ENDIAN=y 122CONFIG_CPU_LITTLE_ENDIAN=y
123CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
124CONFIG_SOC_AU1100=y
125CONFIG_SOC_AU1X00=y
109CONFIG_MIPS_L1_CACHE_SHIFT=5 126CONFIG_MIPS_L1_CACHE_SHIFT=5
110 127
111# 128#
112# CPU selection 129# CPU selection
113# 130#
114CONFIG_CPU_MIPS32=y 131CONFIG_CPU_MIPS32_R1=y
115# CONFIG_CPU_MIPS64 is not set 132# CONFIG_CPU_MIPS32_R2 is not set
133# CONFIG_CPU_MIPS64_R1 is not set
134# CONFIG_CPU_MIPS64_R2 is not set
116# CONFIG_CPU_R3000 is not set 135# CONFIG_CPU_R3000 is not set
117# CONFIG_CPU_TX39XX is not set 136# CONFIG_CPU_TX39XX is not set
118# CONFIG_CPU_VR41XX is not set 137# CONFIG_CPU_VR41XX is not set
@@ -128,15 +147,39 @@ CONFIG_CPU_MIPS32=y
128# CONFIG_CPU_RM7000 is not set 147# CONFIG_CPU_RM7000 is not set
129# CONFIG_CPU_RM9000 is not set 148# CONFIG_CPU_RM9000 is not set
130# CONFIG_CPU_SB1 is not set 149# CONFIG_CPU_SB1 is not set
150CONFIG_SYS_HAS_CPU_MIPS32_R1=y
151CONFIG_CPU_MIPS32=y
152CONFIG_CPU_MIPSR1=y
153CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
154CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
155
156#
157# Kernel type
158#
159CONFIG_32BIT=y
160# CONFIG_64BIT is not set
131CONFIG_PAGE_SIZE_4KB=y 161CONFIG_PAGE_SIZE_4KB=y
132# CONFIG_PAGE_SIZE_8KB is not set 162# CONFIG_PAGE_SIZE_8KB is not set
133# CONFIG_PAGE_SIZE_16KB is not set 163# CONFIG_PAGE_SIZE_16KB is not set
134# CONFIG_PAGE_SIZE_64KB is not set 164# CONFIG_PAGE_SIZE_64KB is not set
135CONFIG_CPU_HAS_PREFETCH=y 165CONFIG_CPU_HAS_PREFETCH=y
136# CONFIG_64BIT_PHYS_ADDR is not set 166# CONFIG_MIPS_MT is not set
167CONFIG_64BIT_PHYS_ADDR=y
137# CONFIG_CPU_ADVANCED is not set 168# CONFIG_CPU_ADVANCED is not set
138CONFIG_CPU_HAS_LLSC=y 169CONFIG_CPU_HAS_LLSC=y
139CONFIG_CPU_HAS_SYNC=y 170CONFIG_CPU_HAS_SYNC=y
171CONFIG_GENERIC_HARDIRQS=y
172CONFIG_GENERIC_IRQ_PROBE=y
173CONFIG_ARCH_FLATMEM_ENABLE=y
174CONFIG_SELECT_MEMORY_MODEL=y
175CONFIG_FLATMEM_MANUAL=y
176# CONFIG_DISCONTIGMEM_MANUAL is not set
177# CONFIG_SPARSEMEM_MANUAL is not set
178CONFIG_FLATMEM=y
179CONFIG_FLAT_NODE_MEM_MAP=y
180# CONFIG_SPARSEMEM_STATIC is not set
181CONFIG_PREEMPT_NONE=y
182# CONFIG_PREEMPT_VOLUNTARY is not set
140# CONFIG_PREEMPT is not set 183# CONFIG_PREEMPT is not set
141 184
142# 185#
@@ -147,15 +190,7 @@ CONFIG_MMU=y
147# 190#
148# PCCARD (PCMCIA/CardBus) support 191# PCCARD (PCMCIA/CardBus) support
149# 192#
150CONFIG_PCCARD=m 193# CONFIG_PCCARD is not set
151# CONFIG_PCMCIA_DEBUG is not set
152CONFIG_PCMCIA=m
153
154#
155# PC-card bridges
156#
157# CONFIG_TCIC is not set
158# CONFIG_PCMCIA_AU1X00 is not set
159 194
160# 195#
161# PCI Hotplug Support 196# PCI Hotplug Support
@@ -167,6 +202,100 @@ CONFIG_PCMCIA=m
167CONFIG_BINFMT_ELF=y 202CONFIG_BINFMT_ELF=y
168# CONFIG_BINFMT_MISC is not set 203# CONFIG_BINFMT_MISC is not set
169CONFIG_TRAD_SIGNALS=y 204CONFIG_TRAD_SIGNALS=y
205# CONFIG_PM is not set
206
207#
208# Networking
209#
210CONFIG_NET=y
211
212#
213# Networking options
214#
215CONFIG_PACKET=y
216# CONFIG_PACKET_MMAP is not set
217CONFIG_UNIX=y
218CONFIG_XFRM=y
219CONFIG_XFRM_USER=m
220CONFIG_NET_KEY=y
221CONFIG_INET=y
222CONFIG_IP_MULTICAST=y
223# CONFIG_IP_ADVANCED_ROUTER is not set
224CONFIG_IP_FIB_HASH=y
225CONFIG_IP_PNP=y
226# CONFIG_IP_PNP_DHCP is not set
227CONFIG_IP_PNP_BOOTP=y
228# CONFIG_IP_PNP_RARP is not set
229# CONFIG_NET_IPIP is not set
230# CONFIG_NET_IPGRE is not set
231# CONFIG_IP_MROUTE is not set
232# CONFIG_ARPD is not set
233# CONFIG_SYN_COOKIES is not set
234# CONFIG_INET_AH is not set
235# CONFIG_INET_ESP is not set
236# CONFIG_INET_IPCOMP is not set
237CONFIG_INET_TUNNEL=m
238CONFIG_INET_DIAG=y
239CONFIG_INET_TCP_DIAG=y
240# CONFIG_TCP_CONG_ADVANCED is not set
241CONFIG_TCP_CONG_BIC=y
242
243#
244# IP: Virtual Server Configuration
245#
246# CONFIG_IP_VS is not set
247# CONFIG_IPV6 is not set
248CONFIG_NETFILTER=y
249# CONFIG_NETFILTER_DEBUG is not set
250CONFIG_NETFILTER_NETLINK=m
251CONFIG_NETFILTER_NETLINK_QUEUE=m
252CONFIG_NETFILTER_NETLINK_LOG=m
253
254#
255# IP: Netfilter Configuration
256#
257# CONFIG_IP_NF_CONNTRACK is not set
258CONFIG_IP_NF_PPTP=m
259# CONFIG_IP_NF_QUEUE is not set
260# CONFIG_IP_NF_IPTABLES is not set
261# CONFIG_IP_NF_ARPTABLES is not set
262
263#
264# DCCP Configuration (EXPERIMENTAL)
265#
266# CONFIG_IP_DCCP is not set
267
268#
269# SCTP Configuration (EXPERIMENTAL)
270#
271# CONFIG_IP_SCTP is not set
272# CONFIG_ATM is not set
273# CONFIG_BRIDGE is not set
274# CONFIG_VLAN_8021Q is not set
275# CONFIG_DECNET is not set
276# CONFIG_LLC2 is not set
277# CONFIG_IPX is not set
278# CONFIG_ATALK is not set
279# CONFIG_X25 is not set
280# CONFIG_LAPB is not set
281# CONFIG_NET_DIVERT is not set
282# CONFIG_ECONET is not set
283# CONFIG_WAN_ROUTER is not set
284# CONFIG_NET_SCHED is not set
285# CONFIG_NET_CLS_ROUTE is not set
286
287#
288# Network testing
289#
290# CONFIG_NET_PKTGEN is not set
291# CONFIG_HAMRADIO is not set
292# CONFIG_IRDA is not set
293# CONFIG_BT is not set
294CONFIG_IEEE80211=m
295# CONFIG_IEEE80211_DEBUG is not set
296CONFIG_IEEE80211_CRYPT_WEP=m
297CONFIG_IEEE80211_CRYPT_CCMP=m
298CONFIG_IEEE80211_CRYPT_TKIP=m
170 299
171# 300#
172# Device Drivers 301# Device Drivers
@@ -180,9 +309,83 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
180# CONFIG_FW_LOADER is not set 309# CONFIG_FW_LOADER is not set
181 310
182# 311#
312# Connector - unified userspace <-> kernelspace linker
313#
314CONFIG_CONNECTOR=m
315
316#
183# Memory Technology Devices (MTD) 317# Memory Technology Devices (MTD)
184# 318#
185# CONFIG_MTD is not set 319CONFIG_MTD=y
320# CONFIG_MTD_DEBUG is not set
321# CONFIG_MTD_CONCAT is not set
322CONFIG_MTD_PARTITIONS=y
323# CONFIG_MTD_REDBOOT_PARTS is not set
324# CONFIG_MTD_CMDLINE_PARTS is not set
325
326#
327# User Modules And Translation Layers
328#
329CONFIG_MTD_CHAR=y
330CONFIG_MTD_BLOCK=y
331# CONFIG_FTL is not set
332# CONFIG_NFTL is not set
333# CONFIG_INFTL is not set
334
335#
336# RAM/ROM/Flash chip drivers
337#
338CONFIG_MTD_CFI=y
339# CONFIG_MTD_JEDECPROBE is not set
340CONFIG_MTD_GEN_PROBE=y
341# CONFIG_MTD_CFI_ADV_OPTIONS is not set
342CONFIG_MTD_MAP_BANK_WIDTH_1=y
343CONFIG_MTD_MAP_BANK_WIDTH_2=y
344CONFIG_MTD_MAP_BANK_WIDTH_4=y
345# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
346# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
347# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
348CONFIG_MTD_CFI_I1=y
349CONFIG_MTD_CFI_I2=y
350# CONFIG_MTD_CFI_I4 is not set
351# CONFIG_MTD_CFI_I8 is not set
352# CONFIG_MTD_CFI_INTELEXT is not set
353CONFIG_MTD_CFI_AMDSTD=y
354CONFIG_MTD_CFI_AMDSTD_RETRY=0
355# CONFIG_MTD_CFI_STAA is not set
356CONFIG_MTD_CFI_UTIL=y
357# CONFIG_MTD_RAM is not set
358# CONFIG_MTD_ROM is not set
359# CONFIG_MTD_ABSENT is not set
360
361#
362# Mapping drivers for chip access
363#
364# CONFIG_MTD_COMPLEX_MAPPINGS is not set
365# CONFIG_MTD_PHYSMAP is not set
366CONFIG_MTD_ALCHEMY=y
367# CONFIG_MTD_PLATRAM is not set
368
369#
370# Self-contained MTD device drivers
371#
372# CONFIG_MTD_SLRAM is not set
373# CONFIG_MTD_PHRAM is not set
374# CONFIG_MTD_MTDRAM is not set
375# CONFIG_MTD_BLKMTD is not set
376# CONFIG_MTD_BLOCK2MTD is not set
377
378#
379# Disk-On-Chip Device Drivers
380#
381# CONFIG_MTD_DOC2000 is not set
382# CONFIG_MTD_DOC2001 is not set
383# CONFIG_MTD_DOC2001PLUS is not set
384
385#
386# NAND Flash Device Drivers
387#
388# CONFIG_MTD_NAND is not set
186 389
187# 390#
188# Parallel port support 391# Parallel port support
@@ -196,14 +399,12 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
196# 399#
197# Block devices 400# Block devices
198# 401#
199# CONFIG_BLK_DEV_FD is not set
200# CONFIG_BLK_DEV_COW_COMMON is not set 402# CONFIG_BLK_DEV_COW_COMMON is not set
201CONFIG_BLK_DEV_LOOP=y 403CONFIG_BLK_DEV_LOOP=y
202# CONFIG_BLK_DEV_CRYPTOLOOP is not set 404# CONFIG_BLK_DEV_CRYPTOLOOP is not set
203# CONFIG_BLK_DEV_NBD is not set 405# CONFIG_BLK_DEV_NBD is not set
204# CONFIG_BLK_DEV_RAM is not set 406# CONFIG_BLK_DEV_RAM is not set
205CONFIG_BLK_DEV_RAM_COUNT=16 407CONFIG_BLK_DEV_RAM_COUNT=16
206CONFIG_INITRAMFS_SOURCE=""
207# CONFIG_LBD is not set 408# CONFIG_LBD is not set
208CONFIG_CDROM_PKTCDVD=m 409CONFIG_CDROM_PKTCDVD=m
209CONFIG_CDROM_PKTCDVD_BUFFERS=8 410CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -226,6 +427,7 @@ CONFIG_ATA_OVER_ETH=m
226# 427#
227# SCSI device support 428# SCSI device support
228# 429#
430CONFIG_RAID_ATTRS=m
229# CONFIG_SCSI is not set 431# CONFIG_SCSI is not set
230 432
231# 433#
@@ -236,6 +438,7 @@ CONFIG_ATA_OVER_ETH=m
236# 438#
237# Fusion MPT device support 439# Fusion MPT device support
238# 440#
441# CONFIG_FUSION is not set
239 442
240# 443#
241# IEEE 1394 (FireWire) support 444# IEEE 1394 (FireWire) support
@@ -246,101 +449,35 @@ CONFIG_ATA_OVER_ETH=m
246# 449#
247 450
248# 451#
249# Networking support 452# Network device support
250#
251CONFIG_NET=y
252
253#
254# Networking options
255#
256CONFIG_PACKET=y
257# CONFIG_PACKET_MMAP is not set
258CONFIG_NETLINK_DEV=y
259CONFIG_UNIX=y
260CONFIG_NET_KEY=y
261CONFIG_INET=y
262CONFIG_IP_MULTICAST=y
263# CONFIG_IP_ADVANCED_ROUTER is not set
264CONFIG_IP_PNP=y
265# CONFIG_IP_PNP_DHCP is not set
266CONFIG_IP_PNP_BOOTP=y
267# CONFIG_IP_PNP_RARP is not set
268# CONFIG_NET_IPIP is not set
269# CONFIG_NET_IPGRE is not set
270# CONFIG_IP_MROUTE is not set
271# CONFIG_ARPD is not set
272# CONFIG_SYN_COOKIES is not set
273# CONFIG_INET_AH is not set
274# CONFIG_INET_ESP is not set
275# CONFIG_INET_IPCOMP is not set
276CONFIG_INET_TUNNEL=m
277CONFIG_IP_TCPDIAG=m
278# CONFIG_IP_TCPDIAG_IPV6 is not set
279
280#
281# IP: Virtual Server Configuration
282#
283# CONFIG_IP_VS is not set
284# CONFIG_IPV6 is not set
285CONFIG_NETFILTER=y
286# CONFIG_NETFILTER_DEBUG is not set
287
288#
289# IP: Netfilter Configuration
290# 453#
291# CONFIG_IP_NF_CONNTRACK is not set 454CONFIG_NETDEVICES=y
292CONFIG_IP_NF_CONNTRACK_MARK=y 455# CONFIG_DUMMY is not set
293# CONFIG_IP_NF_QUEUE is not set 456# CONFIG_BONDING is not set
294# CONFIG_IP_NF_IPTABLES is not set 457# CONFIG_EQUALIZER is not set
295# CONFIG_IP_NF_ARPTABLES is not set 458# CONFIG_TUN is not set
296CONFIG_XFRM=y
297CONFIG_XFRM_USER=m
298
299#
300# SCTP Configuration (EXPERIMENTAL)
301#
302# CONFIG_IP_SCTP is not set
303# CONFIG_ATM is not set
304# CONFIG_BRIDGE is not set
305# CONFIG_VLAN_8021Q is not set
306# CONFIG_DECNET is not set
307# CONFIG_LLC2 is not set
308# CONFIG_IPX is not set
309# CONFIG_ATALK is not set
310# CONFIG_X25 is not set
311# CONFIG_LAPB is not set
312# CONFIG_NET_DIVERT is not set
313# CONFIG_ECONET is not set
314# CONFIG_WAN_ROUTER is not set
315 459
316# 460#
317# QoS and/or fair queueing 461# PHY device support
318# 462#
319# CONFIG_NET_SCHED is not set 463CONFIG_PHYLIB=m
320# CONFIG_NET_CLS_ROUTE is not set 464CONFIG_PHYCONTROL=y
321 465
322# 466#
323# Network testing 467# MII PHY device drivers
324# 468#
325# CONFIG_NET_PKTGEN is not set 469CONFIG_MARVELL_PHY=m
326# CONFIG_NETPOLL is not set 470CONFIG_DAVICOM_PHY=m
327# CONFIG_NET_POLL_CONTROLLER is not set 471CONFIG_QSEMI_PHY=m
328# CONFIG_HAMRADIO is not set 472CONFIG_LXT_PHY=m
329# CONFIG_IRDA is not set 473CONFIG_CICADA_PHY=m
330# CONFIG_BT is not set
331CONFIG_NETDEVICES=y
332# CONFIG_DUMMY is not set
333# CONFIG_BONDING is not set
334# CONFIG_EQUALIZER is not set
335# CONFIG_TUN is not set
336# CONFIG_ETHERTAP is not set
337 474
338# 475#
339# Ethernet (10 or 100Mbit) 476# Ethernet (10 or 100Mbit)
340# 477#
341CONFIG_NET_ETHERNET=y 478CONFIG_NET_ETHERNET=y
342CONFIG_MII=m 479CONFIG_MII=m
343# CONFIG_MIPS_AU1X00_ENET is not set 480CONFIG_MIPS_AU1X00_ENET=y
344 481
345# 482#
346# Ethernet (1000 Mbit) 483# Ethernet (1000 Mbit)
@@ -360,19 +497,6 @@ CONFIG_MII=m
360# CONFIG_NET_RADIO is not set 497# CONFIG_NET_RADIO is not set
361 498
362# 499#
363# PCMCIA network device support
364#
365CONFIG_NET_PCMCIA=y
366CONFIG_PCMCIA_3C589=m
367CONFIG_PCMCIA_3C574=m
368CONFIG_PCMCIA_FMVJ18X=m
369CONFIG_PCMCIA_PCNET=m
370CONFIG_PCMCIA_NMCLAN=m
371CONFIG_PCMCIA_SMC91C92=m
372CONFIG_PCMCIA_XIRC2PS=m
373CONFIG_PCMCIA_AXNET=m
374
375#
376# Wan interfaces 500# Wan interfaces
377# 501#
378# CONFIG_WAN is not set 502# CONFIG_WAN is not set
@@ -387,6 +511,8 @@ CONFIG_PPPOE=m
387# CONFIG_SLIP is not set 511# CONFIG_SLIP is not set
388# CONFIG_SHAPER is not set 512# CONFIG_SHAPER is not set
389# CONFIG_NETCONSOLE is not set 513# CONFIG_NETCONSOLE is not set
514# CONFIG_NETPOLL is not set
515# CONFIG_NET_POLL_CONTROLLER is not set
390 516
391# 517#
392# ISDN subsystem 518# ISDN subsystem
@@ -416,18 +542,6 @@ CONFIG_INPUT_EVDEV=y
416# CONFIG_INPUT_EVBUG is not set 542# CONFIG_INPUT_EVBUG is not set
417 543
418# 544#
419# Input I/O drivers
420#
421# CONFIG_GAMEPORT is not set
422CONFIG_SOUND_GAMEPORT=y
423CONFIG_SERIO=y
424# CONFIG_SERIO_I8042 is not set
425CONFIG_SERIO_SERPORT=y
426# CONFIG_SERIO_CT82C710 is not set
427CONFIG_SERIO_LIBPS2=m
428CONFIG_SERIO_RAW=m
429
430#
431# Input Device Drivers 545# Input Device Drivers
432# 546#
433# CONFIG_INPUT_KEYBOARD is not set 547# CONFIG_INPUT_KEYBOARD is not set
@@ -437,6 +551,16 @@ CONFIG_SERIO_RAW=m
437# CONFIG_INPUT_MISC is not set 551# CONFIG_INPUT_MISC is not set
438 552
439# 553#
554# Hardware I/O ports
555#
556CONFIG_SERIO=y
557# CONFIG_SERIO_I8042 is not set
558CONFIG_SERIO_SERPORT=y
559CONFIG_SERIO_LIBPS2=m
560CONFIG_SERIO_RAW=m
561# CONFIG_GAMEPORT is not set
562
563#
440# Character devices 564# Character devices
441# 565#
442CONFIG_VT=y 566CONFIG_VT=y
@@ -454,7 +578,10 @@ CONFIG_HW_CONSOLE=y
454# 578#
455# Non-8250 serial port support 579# Non-8250 serial port support
456# 580#
457# CONFIG_SERIAL_AU1X00 is not set 581CONFIG_SERIAL_AU1X00=y
582CONFIG_SERIAL_AU1X00_CONSOLE=y
583CONFIG_SERIAL_CORE=y
584CONFIG_SERIAL_CORE_CONSOLE=y
458CONFIG_UNIX98_PTYS=y 585CONFIG_UNIX98_PTYS=y
459CONFIG_LEGACY_PTYS=y 586CONFIG_LEGACY_PTYS=y
460CONFIG_LEGACY_PTY_COUNT=256 587CONFIG_LEGACY_PTY_COUNT=256
@@ -468,20 +595,19 @@ CONFIG_LEGACY_PTY_COUNT=256
468# Watchdog Cards 595# Watchdog Cards
469# 596#
470# CONFIG_WATCHDOG is not set 597# CONFIG_WATCHDOG is not set
471CONFIG_RTC=y 598# CONFIG_RTC is not set
599# CONFIG_GEN_RTC is not set
472# CONFIG_DTLK is not set 600# CONFIG_DTLK is not set
473# CONFIG_R3964 is not set 601# CONFIG_R3964 is not set
474 602
475# 603#
476# Ftape, the floppy tape device driver 604# Ftape, the floppy tape device driver
477# 605#
478# CONFIG_DRM is not set 606# CONFIG_RAW_DRIVER is not set
479 607
480# 608#
481# PCMCIA character devices 609# TPM devices
482# 610#
483CONFIG_SYNCLINK_CS=m
484# CONFIG_RAW_DRIVER is not set
485 611
486# 612#
487# I2C support 613# I2C support
@@ -494,10 +620,20 @@ CONFIG_SYNCLINK_CS=m
494# CONFIG_W1 is not set 620# CONFIG_W1 is not set
495 621
496# 622#
623# Hardware Monitoring support
624#
625# CONFIG_HWMON is not set
626# CONFIG_HWMON_VID is not set
627
628#
497# Misc devices 629# Misc devices
498# 630#
499 631
500# 632#
633# Multimedia Capabilities Port drivers
634#
635
636#
501# Multimedia devices 637# Multimedia devices
502# 638#
503# CONFIG_VIDEO_DEV is not set 639# CONFIG_VIDEO_DEV is not set
@@ -510,13 +646,43 @@ CONFIG_SYNCLINK_CS=m
510# 646#
511# Graphics support 647# Graphics support
512# 648#
513# CONFIG_FB is not set 649CONFIG_FB=y
650CONFIG_FB_CFB_FILLRECT=y
651CONFIG_FB_CFB_COPYAREA=y
652CONFIG_FB_CFB_IMAGEBLIT=y
653CONFIG_FB_SOFT_CURSOR=y
654# CONFIG_FB_MACMODES is not set
655# CONFIG_FB_MODE_HELPERS is not set
656# CONFIG_FB_TILEBLITTING is not set
657CONFIG_FB_AU1100=y
658# CONFIG_FB_S1D13XXX is not set
659# CONFIG_FB_VIRTUAL is not set
514 660
515# 661#
516# Console display driver support 662# Console display driver support
517# 663#
518# CONFIG_VGA_CONSOLE is not set 664# CONFIG_VGA_CONSOLE is not set
519CONFIG_DUMMY_CONSOLE=y 665CONFIG_DUMMY_CONSOLE=y
666CONFIG_FRAMEBUFFER_CONSOLE=y
667CONFIG_FONTS=y
668CONFIG_FONT_8x8=y
669CONFIG_FONT_8x16=y
670# CONFIG_FONT_6x11 is not set
671# CONFIG_FONT_7x14 is not set
672# CONFIG_FONT_PEARL_8x8 is not set
673# CONFIG_FONT_ACORN_8x8 is not set
674# CONFIG_FONT_MINI_4x6 is not set
675# CONFIG_FONT_SUN8x16 is not set
676# CONFIG_FONT_SUN12x22 is not set
677# CONFIG_FONT_10x18 is not set
678
679#
680# Logo configuration
681#
682CONFIG_LOGO=y
683CONFIG_LOGO_LINUX_MONO=y
684CONFIG_LOGO_LINUX_VGA16=y
685CONFIG_LOGO_LINUX_CLUT224=y
520# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 686# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
521 687
522# 688#
@@ -527,12 +693,9 @@ CONFIG_DUMMY_CONSOLE=y
527# 693#
528# USB support 694# USB support
529# 695#
530# CONFIG_USB_ARCH_HAS_HCD is not set 696CONFIG_USB_ARCH_HAS_HCD=y
531# CONFIG_USB_ARCH_HAS_OHCI is not set 697CONFIG_USB_ARCH_HAS_OHCI=y
532 698# CONFIG_USB is not set
533#
534# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
535#
536 699
537# 700#
538# USB Gadget Support 701# USB Gadget Support
@@ -547,7 +710,10 @@ CONFIG_DUMMY_CONSOLE=y
547# 710#
548# InfiniBand support 711# InfiniBand support
549# 712#
550# CONFIG_INFINIBAND is not set 713
714#
715# SN Devices
716#
551 717
552# 718#
553# File systems 719# File systems
@@ -556,6 +722,7 @@ CONFIG_EXT2_FS=y
556CONFIG_EXT2_FS_XATTR=y 722CONFIG_EXT2_FS_XATTR=y
557CONFIG_EXT2_FS_POSIX_ACL=y 723CONFIG_EXT2_FS_POSIX_ACL=y
558# CONFIG_EXT2_FS_SECURITY is not set 724# CONFIG_EXT2_FS_SECURITY is not set
725# CONFIG_EXT2_FS_XIP is not set
559CONFIG_EXT3_FS=y 726CONFIG_EXT3_FS=y
560CONFIG_EXT3_FS_XATTR=y 727CONFIG_EXT3_FS_XATTR=y
561CONFIG_EXT3_FS_POSIX_ACL=y 728CONFIG_EXT3_FS_POSIX_ACL=y
@@ -574,10 +741,12 @@ CONFIG_FS_POSIX_ACL=y
574# CONFIG_XFS_FS is not set 741# CONFIG_XFS_FS is not set
575# CONFIG_MINIX_FS is not set 742# CONFIG_MINIX_FS is not set
576# CONFIG_ROMFS_FS is not set 743# CONFIG_ROMFS_FS is not set
744CONFIG_INOTIFY=y
577# CONFIG_QUOTA is not set 745# CONFIG_QUOTA is not set
578CONFIG_DNOTIFY=y 746CONFIG_DNOTIFY=y
579CONFIG_AUTOFS_FS=m 747CONFIG_AUTOFS_FS=m
580CONFIG_AUTOFS4_FS=m 748CONFIG_AUTOFS4_FS=m
749CONFIG_FUSE_FS=m
581 750
582# 751#
583# CD-ROM/DVD Filesystems 752# CD-ROM/DVD Filesystems
@@ -598,13 +767,10 @@ CONFIG_AUTOFS4_FS=m
598CONFIG_PROC_FS=y 767CONFIG_PROC_FS=y
599CONFIG_PROC_KCORE=y 768CONFIG_PROC_KCORE=y
600CONFIG_SYSFS=y 769CONFIG_SYSFS=y
601# CONFIG_DEVFS_FS is not set
602CONFIG_DEVPTS_FS_XATTR=y
603CONFIG_DEVPTS_FS_SECURITY=y
604CONFIG_TMPFS=y 770CONFIG_TMPFS=y
605# CONFIG_TMPFS_XATTR is not set
606# CONFIG_HUGETLB_PAGE is not set 771# CONFIG_HUGETLB_PAGE is not set
607CONFIG_RAMFS=y 772CONFIG_RAMFS=y
773CONFIG_RELAYFS_FS=m
608 774
609# 775#
610# Miscellaneous filesystems 776# Miscellaneous filesystems
@@ -616,6 +782,8 @@ CONFIG_RAMFS=y
616# CONFIG_BEFS_FS is not set 782# CONFIG_BEFS_FS is not set
617# CONFIG_BFS_FS is not set 783# CONFIG_BFS_FS is not set
618# CONFIG_EFS_FS is not set 784# CONFIG_EFS_FS is not set
785# CONFIG_JFFS_FS is not set
786# CONFIG_JFFS2_FS is not set
619CONFIG_CRAMFS=m 787CONFIG_CRAMFS=m
620# CONFIG_VXFS_FS is not set 788# CONFIG_VXFS_FS is not set
621# CONFIG_HPFS_FS is not set 789# CONFIG_HPFS_FS is not set
@@ -636,6 +804,7 @@ CONFIG_NFSD=m
636CONFIG_ROOT_NFS=y 804CONFIG_ROOT_NFS=y
637CONFIG_LOCKD=y 805CONFIG_LOCKD=y
638CONFIG_EXPORTFS=m 806CONFIG_EXPORTFS=m
807CONFIG_NFS_COMMON=y
639CONFIG_SUNRPC=y 808CONFIG_SUNRPC=y
640# CONFIG_RPCSEC_GSS_KRB5 is not set 809# CONFIG_RPCSEC_GSS_KRB5 is not set
641# CONFIG_RPCSEC_GSS_SPKM3 is not set 810# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -645,6 +814,7 @@ CONFIG_SMB_FS=m
645# CONFIG_NCP_FS is not set 814# CONFIG_NCP_FS is not set
646# CONFIG_CODA_FS is not set 815# CONFIG_CODA_FS is not set
647# CONFIG_AFS_FS is not set 816# CONFIG_AFS_FS is not set
817# CONFIG_9P_FS is not set
648 818
649# 819#
650# Partition Types 820# Partition Types
@@ -704,7 +874,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
704# 874#
705# Kernel hacking 875# Kernel hacking
706# 876#
877# CONFIG_PRINTK_TIME is not set
707# CONFIG_DEBUG_KERNEL is not set 878# CONFIG_DEBUG_KERNEL is not set
879CONFIG_LOG_BUF_SHIFT=14
708CONFIG_CROSSCOMPILE=y 880CONFIG_CROSSCOMPILE=y
709CONFIG_CMDLINE="" 881CONFIG_CMDLINE=""
710 882
@@ -720,26 +892,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
720# 892#
721CONFIG_CRYPTO=y 893CONFIG_CRYPTO=y
722CONFIG_CRYPTO_HMAC=y 894CONFIG_CRYPTO_HMAC=y
723CONFIG_CRYPTO_NULL=y 895CONFIG_CRYPTO_NULL=m
724# CONFIG_CRYPTO_MD4 is not set 896CONFIG_CRYPTO_MD4=m
725# CONFIG_CRYPTO_MD5 is not set 897CONFIG_CRYPTO_MD5=m
726# CONFIG_CRYPTO_SHA1 is not set 898CONFIG_CRYPTO_SHA1=m
727# CONFIG_CRYPTO_SHA256 is not set 899CONFIG_CRYPTO_SHA256=m
728CONFIG_CRYPTO_SHA512=y 900CONFIG_CRYPTO_SHA512=m
729CONFIG_CRYPTO_WP512=m 901CONFIG_CRYPTO_WP512=m
730# CONFIG_CRYPTO_DES is not set 902CONFIG_CRYPTO_TGR192=m
731# CONFIG_CRYPTO_BLOWFISH is not set 903CONFIG_CRYPTO_DES=m
732CONFIG_CRYPTO_TWOFISH=y 904CONFIG_CRYPTO_BLOWFISH=m
733# CONFIG_CRYPTO_SERPENT is not set 905CONFIG_CRYPTO_TWOFISH=m
906CONFIG_CRYPTO_SERPENT=m
734CONFIG_CRYPTO_AES=m 907CONFIG_CRYPTO_AES=m
735# CONFIG_CRYPTO_CAST5 is not set 908CONFIG_CRYPTO_CAST5=m
736# CONFIG_CRYPTO_CAST6 is not set 909CONFIG_CRYPTO_CAST6=m
737CONFIG_CRYPTO_TEA=m 910CONFIG_CRYPTO_TEA=m
738# CONFIG_CRYPTO_ARC4 is not set 911CONFIG_CRYPTO_ARC4=m
739CONFIG_CRYPTO_KHAZAD=m 912CONFIG_CRYPTO_KHAZAD=m
740CONFIG_CRYPTO_ANUBIS=m 913CONFIG_CRYPTO_ANUBIS=m
741CONFIG_CRYPTO_DEFLATE=y 914CONFIG_CRYPTO_DEFLATE=m
742CONFIG_CRYPTO_MICHAEL_MIC=y 915CONFIG_CRYPTO_MICHAEL_MIC=m
743CONFIG_CRYPTO_CRC32C=m 916CONFIG_CRYPTO_CRC32C=m
744# CONFIG_CRYPTO_TEST is not set 917# CONFIG_CRYPTO_TEST is not set
745 918
@@ -751,9 +924,8 @@ CONFIG_CRYPTO_CRC32C=m
751# Library routines 924# Library routines
752# 925#
753CONFIG_CRC_CCITT=m 926CONFIG_CRC_CCITT=m
927CONFIG_CRC16=m
754CONFIG_CRC32=y 928CONFIG_CRC32=y
755CONFIG_LIBCRC32C=m 929CONFIG_LIBCRC32C=m
756CONFIG_ZLIB_INFLATE=y 930CONFIG_ZLIB_INFLATE=m
757CONFIG_ZLIB_DEFLATE=y 931CONFIG_ZLIB_DEFLATE=m
758CONFIG_GENERIC_HARDIRQS=y
759CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
new file mode 100644
index 000000000000..530b6c2d99f6
--- /dev/null
+++ b/arch/mips/configs/db1200_defconfig
@@ -0,0 +1,987 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.14-rc2
4# Thu Oct 20 22:25:32 2005
5#
6CONFIG_MIPS=y
7
8#
9# Code maturity level options
10#
11CONFIG_EXPERIMENTAL=y
12CONFIG_CLEAN_COMPILE=y
13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
15
16#
17# General setup
18#
19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
21CONFIG_SWAP=y
22CONFIG_SYSVIPC=y
23# CONFIG_POSIX_MQUEUE is not set
24# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set
27CONFIG_HOTPLUG=y
28CONFIG_KOBJECT_UEVENT=y
29CONFIG_IKCONFIG=y
30CONFIG_IKCONFIG_PROC=y
31CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
38CONFIG_FUTEX=y
39CONFIG_EPOLL=y
40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
41CONFIG_SHMEM=y
42CONFIG_CC_ALIGN_FUNCTIONS=0
43CONFIG_CC_ALIGN_LABELS=0
44CONFIG_CC_ALIGN_LOOPS=0
45CONFIG_CC_ALIGN_JUMPS=0
46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
48
49#
50# Loadable module support
51#
52CONFIG_MODULES=y
53CONFIG_MODULE_UNLOAD=y
54# CONFIG_MODULE_FORCE_UNLOAD is not set
55CONFIG_OBSOLETE_MODPARM=y
56CONFIG_MODVERSIONS=y
57CONFIG_MODULE_SRCVERSION_ALL=y
58CONFIG_KMOD=y
59
60#
61# Machine selection
62#
63# CONFIG_MIPS_MTX1 is not set
64# CONFIG_MIPS_BOSPORUS is not set
65# CONFIG_MIPS_PB1000 is not set
66# CONFIG_MIPS_PB1100 is not set
67# CONFIG_MIPS_PB1500 is not set
68# CONFIG_MIPS_PB1550 is not set
69# CONFIG_MIPS_PB1200 is not set
70# CONFIG_MIPS_DB1000 is not set
71# CONFIG_MIPS_DB1100 is not set
72# CONFIG_MIPS_DB1500 is not set
73# CONFIG_MIPS_DB1550 is not set
74CONFIG_MIPS_DB1200=y
75# CONFIG_MIPS_MIRAGE is not set
76# CONFIG_MIPS_COBALT is not set
77# CONFIG_MACH_DECSTATION is not set
78# CONFIG_MIPS_EV64120 is not set
79# CONFIG_MIPS_EV96100 is not set
80# CONFIG_MIPS_IVR is not set
81# CONFIG_MIPS_ITE8172 is not set
82# CONFIG_MACH_JAZZ is not set
83# CONFIG_LASAT is not set
84# CONFIG_MIPS_ATLAS is not set
85# CONFIG_MIPS_MALTA is not set
86# CONFIG_MIPS_SEAD is not set
87# CONFIG_MIPS_SIM is not set
88# CONFIG_MOMENCO_JAGUAR_ATX is not set
89# CONFIG_MOMENCO_OCELOT is not set
90# CONFIG_MOMENCO_OCELOT_3 is not set
91# CONFIG_MOMENCO_OCELOT_C is not set
92# CONFIG_MOMENCO_OCELOT_G is not set
93# CONFIG_MIPS_XXS1500 is not set
94# CONFIG_PNX8550_V2PCI is not set
95# CONFIG_PNX8550_JBS is not set
96# CONFIG_DDB5074 is not set
97# CONFIG_DDB5476 is not set
98# CONFIG_DDB5477 is not set
99# CONFIG_MACH_VR41XX is not set
100# CONFIG_PMC_YOSEMITE is not set
101# CONFIG_QEMU is not set
102# CONFIG_SGI_IP22 is not set
103# CONFIG_SGI_IP27 is not set
104# CONFIG_SGI_IP32 is not set
105# CONFIG_SIBYTE_BIGSUR is not set
106# CONFIG_SIBYTE_SWARM is not set
107# CONFIG_SIBYTE_SENTOSA is not set
108# CONFIG_SIBYTE_RHONE is not set
109# CONFIG_SIBYTE_CARMEL is not set
110# CONFIG_SIBYTE_PTSWARM is not set
111# CONFIG_SIBYTE_LITTLESUR is not set
112# CONFIG_SIBYTE_CRHINE is not set
113# CONFIG_SIBYTE_CRHONE is not set
114# CONFIG_SNI_RM200_PCI is not set
115# CONFIG_TOSHIBA_JMR3927 is not set
116# CONFIG_TOSHIBA_RBTX4927 is not set
117# CONFIG_TOSHIBA_RBTX4938 is not set
118CONFIG_RWSEM_GENERIC_SPINLOCK=y
119CONFIG_GENERIC_CALIBRATE_DELAY=y
120CONFIG_DMA_COHERENT=y
121CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
122# CONFIG_CPU_BIG_ENDIAN is not set
123CONFIG_CPU_LITTLE_ENDIAN=y
124CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
125CONFIG_SOC_AU1200=y
126CONFIG_SOC_AU1X00=y
127CONFIG_MIPS_L1_CACHE_SHIFT=5
128
129#
130# CPU selection
131#
132CONFIG_CPU_MIPS32_R1=y
133# CONFIG_CPU_MIPS32_R2 is not set
134# CONFIG_CPU_MIPS64_R1 is not set
135# CONFIG_CPU_MIPS64_R2 is not set
136# CONFIG_CPU_R3000 is not set
137# CONFIG_CPU_TX39XX is not set
138# CONFIG_CPU_VR41XX is not set
139# CONFIG_CPU_R4300 is not set
140# CONFIG_CPU_R4X00 is not set
141# CONFIG_CPU_TX49XX is not set
142# CONFIG_CPU_R5000 is not set
143# CONFIG_CPU_R5432 is not set
144# CONFIG_CPU_R6000 is not set
145# CONFIG_CPU_NEVADA is not set
146# CONFIG_CPU_R8000 is not set
147# CONFIG_CPU_R10000 is not set
148# CONFIG_CPU_RM7000 is not set
149# CONFIG_CPU_RM9000 is not set
150# CONFIG_CPU_SB1 is not set
151CONFIG_SYS_HAS_CPU_MIPS32_R1=y
152CONFIG_CPU_MIPS32=y
153CONFIG_CPU_MIPSR1=y
154CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
155CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
156
157#
158# Kernel type
159#
160CONFIG_32BIT=y
161# CONFIG_64BIT is not set
162CONFIG_PAGE_SIZE_4KB=y
163# CONFIG_PAGE_SIZE_8KB is not set
164# CONFIG_PAGE_SIZE_16KB is not set
165# CONFIG_PAGE_SIZE_64KB is not set
166CONFIG_CPU_HAS_PREFETCH=y
167# CONFIG_MIPS_MT is not set
168CONFIG_64BIT_PHYS_ADDR=y
169# CONFIG_CPU_ADVANCED is not set
170CONFIG_CPU_HAS_LLSC=y
171CONFIG_CPU_HAS_SYNC=y
172CONFIG_GENERIC_HARDIRQS=y
173CONFIG_GENERIC_IRQ_PROBE=y
174CONFIG_ARCH_FLATMEM_ENABLE=y
175CONFIG_SELECT_MEMORY_MODEL=y
176CONFIG_FLATMEM_MANUAL=y
177# CONFIG_DISCONTIGMEM_MANUAL is not set
178# CONFIG_SPARSEMEM_MANUAL is not set
179CONFIG_FLATMEM=y
180CONFIG_FLAT_NODE_MEM_MAP=y
181# CONFIG_SPARSEMEM_STATIC is not set
182CONFIG_PREEMPT_NONE=y
183# CONFIG_PREEMPT_VOLUNTARY is not set
184# CONFIG_PREEMPT is not set
185
186#
187# Bus options (PCI, PCMCIA, EISA, ISA, TC)
188#
189CONFIG_MMU=y
190
191#
192# PCCARD (PCMCIA/CardBus) support
193#
194CONFIG_PCCARD=m
195# CONFIG_PCMCIA_DEBUG is not set
196CONFIG_PCMCIA=m
197CONFIG_PCMCIA_LOAD_CIS=y
198CONFIG_PCMCIA_IOCTL=y
199
200#
201# PC-card bridges
202#
203# CONFIG_TCIC is not set
204CONFIG_PCMCIA_AU1X00=m
205
206#
207# PCI Hotplug Support
208#
209
210#
211# Executable file formats
212#
213CONFIG_BINFMT_ELF=y
214# CONFIG_BINFMT_MISC is not set
215CONFIG_TRAD_SIGNALS=y
216# CONFIG_PM is not set
217
218#
219# Networking
220#
221CONFIG_NET=y
222
223#
224# Networking options
225#
226CONFIG_PACKET=y
227# CONFIG_PACKET_MMAP is not set
228CONFIG_UNIX=y
229CONFIG_XFRM=y
230CONFIG_XFRM_USER=m
231CONFIG_NET_KEY=y
232CONFIG_INET=y
233CONFIG_IP_MULTICAST=y
234# CONFIG_IP_ADVANCED_ROUTER is not set
235CONFIG_IP_FIB_HASH=y
236# CONFIG_IP_PNP is not set
237# CONFIG_NET_IPIP is not set
238# CONFIG_NET_IPGRE is not set
239# CONFIG_IP_MROUTE is not set
240# CONFIG_ARPD is not set
241# CONFIG_SYN_COOKIES is not set
242# CONFIG_INET_AH is not set
243# CONFIG_INET_ESP is not set
244# CONFIG_INET_IPCOMP is not set
245CONFIG_INET_TUNNEL=m
246CONFIG_INET_DIAG=y
247CONFIG_INET_TCP_DIAG=y
248# CONFIG_TCP_CONG_ADVANCED is not set
249CONFIG_TCP_CONG_BIC=y
250
251#
252# IP: Virtual Server Configuration
253#
254# CONFIG_IP_VS is not set
255# CONFIG_IPV6 is not set
256CONFIG_NETFILTER=y
257# CONFIG_NETFILTER_DEBUG is not set
258# CONFIG_NETFILTER_NETLINK is not set
259
260#
261# IP: Netfilter Configuration
262#
263# CONFIG_IP_NF_CONNTRACK is not set
264CONFIG_IP_NF_PPTP=m
265# CONFIG_IP_NF_QUEUE is not set
266# CONFIG_IP_NF_IPTABLES is not set
267# CONFIG_IP_NF_ARPTABLES is not set
268
269#
270# DCCP Configuration (EXPERIMENTAL)
271#
272# CONFIG_IP_DCCP is not set
273
274#
275# SCTP Configuration (EXPERIMENTAL)
276#
277# CONFIG_IP_SCTP is not set
278# CONFIG_ATM is not set
279# CONFIG_BRIDGE is not set
280# CONFIG_VLAN_8021Q is not set
281# CONFIG_DECNET is not set
282# CONFIG_LLC2 is not set
283# CONFIG_IPX is not set
284# CONFIG_ATALK is not set
285# CONFIG_X25 is not set
286# CONFIG_LAPB is not set
287# CONFIG_NET_DIVERT is not set
288# CONFIG_ECONET is not set
289# CONFIG_WAN_ROUTER is not set
290# CONFIG_NET_SCHED is not set
291# CONFIG_NET_CLS_ROUTE is not set
292
293#
294# Network testing
295#
296# CONFIG_NET_PKTGEN is not set
297# CONFIG_HAMRADIO is not set
298# CONFIG_IRDA is not set
299# CONFIG_BT is not set
300# CONFIG_IEEE80211 is not set
301
302#
303# Device Drivers
304#
305
306#
307# Generic Driver Options
308#
309CONFIG_STANDALONE=y
310CONFIG_PREVENT_FIRMWARE_BUILD=y
311CONFIG_FW_LOADER=y
312
313#
314# Connector - unified userspace <-> kernelspace linker
315#
316# CONFIG_CONNECTOR is not set
317
318#
319# Memory Technology Devices (MTD)
320#
321CONFIG_MTD=y
322# CONFIG_MTD_DEBUG is not set
323# CONFIG_MTD_CONCAT is not set
324CONFIG_MTD_PARTITIONS=y
325# CONFIG_MTD_REDBOOT_PARTS is not set
326# CONFIG_MTD_CMDLINE_PARTS is not set
327
328#
329# User Modules And Translation Layers
330#
331CONFIG_MTD_CHAR=y
332CONFIG_MTD_BLOCK=y
333# CONFIG_FTL is not set
334# CONFIG_NFTL is not set
335# CONFIG_INFTL is not set
336
337#
338# RAM/ROM/Flash chip drivers
339#
340CONFIG_MTD_CFI=y
341# CONFIG_MTD_JEDECPROBE is not set
342CONFIG_MTD_GEN_PROBE=y
343# CONFIG_MTD_CFI_ADV_OPTIONS is not set
344CONFIG_MTD_MAP_BANK_WIDTH_1=y
345CONFIG_MTD_MAP_BANK_WIDTH_2=y
346CONFIG_MTD_MAP_BANK_WIDTH_4=y
347# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
348# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
349# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
350CONFIG_MTD_CFI_I1=y
351CONFIG_MTD_CFI_I2=y
352# CONFIG_MTD_CFI_I4 is not set
353# CONFIG_MTD_CFI_I8 is not set
354# CONFIG_MTD_CFI_INTELEXT is not set
355CONFIG_MTD_CFI_AMDSTD=y
356CONFIG_MTD_CFI_AMDSTD_RETRY=0
357# CONFIG_MTD_CFI_STAA is not set
358CONFIG_MTD_CFI_UTIL=y
359# CONFIG_MTD_RAM is not set
360# CONFIG_MTD_ROM is not set
361# CONFIG_MTD_ABSENT is not set
362
363#
364# Mapping drivers for chip access
365#
366# CONFIG_MTD_COMPLEX_MAPPINGS is not set
367# CONFIG_MTD_PHYSMAP is not set
368CONFIG_MTD_ALCHEMY=y
369# CONFIG_MTD_PLATRAM is not set
370
371#
372# Self-contained MTD device drivers
373#
374# CONFIG_MTD_SLRAM is not set
375# CONFIG_MTD_PHRAM is not set
376# CONFIG_MTD_MTDRAM is not set
377# CONFIG_MTD_BLKMTD is not set
378# CONFIG_MTD_BLOCK2MTD is not set
379
380#
381# Disk-On-Chip Device Drivers
382#
383# CONFIG_MTD_DOC2000 is not set
384# CONFIG_MTD_DOC2001 is not set
385# CONFIG_MTD_DOC2001PLUS is not set
386
387#
388# NAND Flash Device Drivers
389#
390CONFIG_MTD_NAND=y
391# CONFIG_MTD_NAND_VERIFY_WRITE is not set
392CONFIG_MTD_NAND_IDS=y
393# CONFIG_MTD_NAND_AU1550 is not set
394# CONFIG_MTD_NAND_DISKONCHIP is not set
395# CONFIG_MTD_NAND_NANDSIM is not set
396
397#
398# Parallel port support
399#
400# CONFIG_PARPORT is not set
401
402#
403# Plug and Play support
404#
405
406#
407# Block devices
408#
409# CONFIG_BLK_DEV_COW_COMMON is not set
410CONFIG_BLK_DEV_LOOP=y
411# CONFIG_BLK_DEV_CRYPTOLOOP is not set
412# CONFIG_BLK_DEV_NBD is not set
413CONFIG_BLK_DEV_RAM=y
414CONFIG_BLK_DEV_RAM_COUNT=16
415CONFIG_BLK_DEV_RAM_SIZE=4096
416# CONFIG_BLK_DEV_INITRD is not set
417# CONFIG_LBD is not set
418# CONFIG_CDROM_PKTCDVD is not set
419
420#
421# IO Schedulers
422#
423CONFIG_IOSCHED_NOOP=y
424CONFIG_IOSCHED_AS=y
425CONFIG_IOSCHED_DEADLINE=y
426CONFIG_IOSCHED_CFQ=y
427# CONFIG_ATA_OVER_ETH is not set
428
429#
430# ATA/ATAPI/MFM/RLL support
431#
432CONFIG_IDE=y
433CONFIG_BLK_DEV_IDE=y
434
435#
436# Please see Documentation/ide.txt for help/info on IDE drives
437#
438# CONFIG_BLK_DEV_IDE_SATA is not set
439CONFIG_BLK_DEV_IDEDISK=y
440CONFIG_IDEDISK_MULTI_MODE=y
441CONFIG_BLK_DEV_IDECS=m
442# CONFIG_BLK_DEV_IDECD is not set
443# CONFIG_BLK_DEV_IDETAPE is not set
444# CONFIG_BLK_DEV_IDEFLOPPY is not set
445# CONFIG_BLK_DEV_IDESCSI is not set
446# CONFIG_IDE_TASK_IOCTL is not set
447
448#
449# IDE chipset support/bugfixes
450#
451CONFIG_IDE_GENERIC=y
452CONFIG_BLK_DEV_IDE_AU1XXX=y
453CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA=y
454# CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA is not set
455# CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON is not set
456CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128
457# CONFIG_IDE_ARM is not set
458# CONFIG_BLK_DEV_IDEDMA is not set
459# CONFIG_IDEDMA_AUTO is not set
460# CONFIG_BLK_DEV_HD is not set
461
462#
463# SCSI device support
464#
465# CONFIG_RAID_ATTRS is not set
466CONFIG_SCSI=y
467CONFIG_SCSI_PROC_FS=y
468
469#
470# SCSI support type (disk, tape, CD-ROM)
471#
472CONFIG_BLK_DEV_SD=y
473# CONFIG_CHR_DEV_ST is not set
474# CONFIG_CHR_DEV_OSST is not set
475CONFIG_BLK_DEV_SR=y
476# CONFIG_BLK_DEV_SR_VENDOR is not set
477CONFIG_CHR_DEV_SG=y
478# CONFIG_CHR_DEV_SCH is not set
479
480#
481# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
482#
483CONFIG_SCSI_MULTI_LUN=y
484# CONFIG_SCSI_CONSTANTS is not set
485# CONFIG_SCSI_LOGGING is not set
486
487#
488# SCSI Transport Attributes
489#
490# CONFIG_SCSI_SPI_ATTRS is not set
491# CONFIG_SCSI_FC_ATTRS is not set
492# CONFIG_SCSI_ISCSI_ATTRS is not set
493# CONFIG_SCSI_SAS_ATTRS is not set
494
495#
496# SCSI low-level drivers
497#
498# CONFIG_SCSI_SATA is not set
499# CONFIG_SCSI_DEBUG is not set
500
501#
502# PCMCIA SCSI adapter support
503#
504# CONFIG_PCMCIA_AHA152X is not set
505# CONFIG_PCMCIA_FDOMAIN is not set
506# CONFIG_PCMCIA_NINJA_SCSI is not set
507# CONFIG_PCMCIA_QLOGIC is not set
508# CONFIG_PCMCIA_SYM53C500 is not set
509
510#
511# Multi-device support (RAID and LVM)
512#
513# CONFIG_MD is not set
514
515#
516# Fusion MPT device support
517#
518# CONFIG_FUSION is not set
519
520#
521# IEEE 1394 (FireWire) support
522#
523
524#
525# I2O device support
526#
527
528#
529# Network device support
530#
531CONFIG_NETDEVICES=y
532# CONFIG_DUMMY is not set
533# CONFIG_BONDING is not set
534# CONFIG_EQUALIZER is not set
535# CONFIG_TUN is not set
536
537#
538# PHY device support
539#
540# CONFIG_PHYLIB is not set
541
542#
543# Ethernet (10 or 100Mbit)
544#
545CONFIG_NET_ETHERNET=y
546CONFIG_MII=m
547# CONFIG_MIPS_AU1X00_ENET is not set
548
549#
550# Ethernet (1000 Mbit)
551#
552
553#
554# Ethernet (10000 Mbit)
555#
556
557#
558# Token Ring devices
559#
560
561#
562# Wireless LAN (non-hamradio)
563#
564# CONFIG_NET_RADIO is not set
565
566#
567# PCMCIA network device support
568#
569# CONFIG_NET_PCMCIA is not set
570
571#
572# Wan interfaces
573#
574# CONFIG_WAN is not set
575# CONFIG_PPP is not set
576# CONFIG_SLIP is not set
577# CONFIG_SHAPER is not set
578# CONFIG_NETCONSOLE is not set
579# CONFIG_NETPOLL is not set
580# CONFIG_NET_POLL_CONTROLLER is not set
581
582#
583# ISDN subsystem
584#
585# CONFIG_ISDN is not set
586
587#
588# Telephony Support
589#
590# CONFIG_PHONE is not set
591
592#
593# Input device support
594#
595CONFIG_INPUT=y
596
597#
598# Userland interfaces
599#
600CONFIG_INPUT_MOUSEDEV=y
601CONFIG_INPUT_MOUSEDEV_PSAUX=y
602CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
603CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
604# CONFIG_INPUT_JOYDEV is not set
605# CONFIG_INPUT_TSDEV is not set
606CONFIG_INPUT_EVDEV=y
607# CONFIG_INPUT_EVBUG is not set
608
609#
610# Input Device Drivers
611#
612# CONFIG_INPUT_KEYBOARD is not set
613# CONFIG_INPUT_MOUSE is not set
614# CONFIG_INPUT_JOYSTICK is not set
615# CONFIG_INPUT_TOUCHSCREEN is not set
616# CONFIG_INPUT_MISC is not set
617
618#
619# Hardware I/O ports
620#
621CONFIG_SERIO=y
622# CONFIG_SERIO_I8042 is not set
623CONFIG_SERIO_SERPORT=y
624# CONFIG_SERIO_LIBPS2 is not set
625CONFIG_SERIO_RAW=y
626# CONFIG_GAMEPORT is not set
627
628#
629# Character devices
630#
631CONFIG_VT=y
632CONFIG_VT_CONSOLE=y
633CONFIG_HW_CONSOLE=y
634# CONFIG_SERIAL_NONSTANDARD is not set
635# CONFIG_AU1X00_GPIO is not set
636# CONFIG_TS_AU1X00_ADS7846 is not set
637
638#
639# Serial drivers
640#
641# CONFIG_SERIAL_8250 is not set
642
643#
644# Non-8250 serial port support
645#
646CONFIG_SERIAL_AU1X00=y
647CONFIG_SERIAL_AU1X00_CONSOLE=y
648CONFIG_SERIAL_CORE=y
649CONFIG_SERIAL_CORE_CONSOLE=y
650CONFIG_UNIX98_PTYS=y
651CONFIG_LEGACY_PTYS=y
652CONFIG_LEGACY_PTY_COUNT=256
653
654#
655# IPMI
656#
657# CONFIG_IPMI_HANDLER is not set
658
659#
660# Watchdog Cards
661#
662# CONFIG_WATCHDOG is not set
663# CONFIG_RTC is not set
664# CONFIG_GEN_RTC is not set
665# CONFIG_DTLK is not set
666# CONFIG_R3964 is not set
667
668#
669# Ftape, the floppy tape device driver
670#
671
672#
673# PCMCIA character devices
674#
675# CONFIG_SYNCLINK_CS is not set
676# CONFIG_RAW_DRIVER is not set
677
678#
679# TPM devices
680#
681
682#
683# I2C support
684#
685# CONFIG_I2C is not set
686
687#
688# Dallas's 1-wire bus
689#
690# CONFIG_W1 is not set
691
692#
693# Hardware Monitoring support
694#
695# CONFIG_HWMON is not set
696# CONFIG_HWMON_VID is not set
697
698#
699# Misc devices
700#
701
702#
703# Multimedia Capabilities Port drivers
704#
705
706#
707# Multimedia devices
708#
709# CONFIG_VIDEO_DEV is not set
710
711#
712# Digital Video Broadcasting Devices
713#
714# CONFIG_DVB is not set
715
716#
717# Graphics support
718#
719CONFIG_FB=y
720CONFIG_FB_CFB_FILLRECT=y
721CONFIG_FB_CFB_COPYAREA=y
722CONFIG_FB_CFB_IMAGEBLIT=y
723CONFIG_FB_SOFT_CURSOR=y
724# CONFIG_FB_MACMODES is not set
725# CONFIG_FB_MODE_HELPERS is not set
726# CONFIG_FB_TILEBLITTING is not set
727CONFIG_FB_AU1200=y
728# CONFIG_FB_S1D13XXX is not set
729# CONFIG_FB_VIRTUAL is not set
730
731#
732# Console display driver support
733#
734CONFIG_VGA_CONSOLE=y
735CONFIG_DUMMY_CONSOLE=y
736# CONFIG_FRAMEBUFFER_CONSOLE is not set
737
738#
739# Logo configuration
740#
741CONFIG_LOGO=y
742CONFIG_LOGO_LINUX_MONO=y
743CONFIG_LOGO_LINUX_VGA16=y
744CONFIG_LOGO_LINUX_CLUT224=y
745# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
746
747#
748# Sound
749#
750# CONFIG_SOUND is not set
751
752#
753# USB support
754#
755CONFIG_USB_ARCH_HAS_HCD=y
756CONFIG_USB_ARCH_HAS_OHCI=y
757# CONFIG_USB is not set
758
759#
760# USB Gadget Support
761#
762CONFIG_USB_GADGET=m
763# CONFIG_USB_GADGET_DEBUG_FILES is not set
764# CONFIG_USB_GADGET_NET2280 is not set
765# CONFIG_USB_GADGET_PXA2XX is not set
766# CONFIG_USB_GADGET_GOKU is not set
767# CONFIG_USB_GADGET_LH7A40X is not set
768# CONFIG_USB_GADGET_OMAP is not set
769# CONFIG_USB_GADGET_DUMMY_HCD is not set
770# CONFIG_USB_GADGET_DUALSPEED is not set
771
772#
773# MMC/SD Card support
774#
775CONFIG_MMC=y
776# CONFIG_MMC_DEBUG is not set
777CONFIG_MMC_BLOCK=y
778CONFIG_MMC_AU1X=y
779
780#
781# InfiniBand support
782#
783
784#
785# SN Devices
786#
787
788#
789# File systems
790#
791CONFIG_EXT2_FS=y
792CONFIG_EXT2_FS_XATTR=y
793CONFIG_EXT2_FS_POSIX_ACL=y
794# CONFIG_EXT2_FS_SECURITY is not set
795# CONFIG_EXT2_FS_XIP is not set
796CONFIG_EXT3_FS=y
797CONFIG_EXT3_FS_XATTR=y
798CONFIG_EXT3_FS_POSIX_ACL=y
799CONFIG_EXT3_FS_SECURITY=y
800CONFIG_JBD=y
801# CONFIG_JBD_DEBUG is not set
802CONFIG_FS_MBCACHE=y
803# CONFIG_REISERFS_FS is not set
804CONFIG_JFS_FS=y
805# CONFIG_JFS_POSIX_ACL is not set
806# CONFIG_JFS_SECURITY is not set
807# CONFIG_JFS_DEBUG is not set
808# CONFIG_JFS_STATISTICS is not set
809CONFIG_FS_POSIX_ACL=y
810# CONFIG_XFS_FS is not set
811# CONFIG_MINIX_FS is not set
812# CONFIG_ROMFS_FS is not set
813CONFIG_INOTIFY=y
814# CONFIG_QUOTA is not set
815CONFIG_DNOTIFY=y
816# CONFIG_AUTOFS_FS is not set
817# CONFIG_AUTOFS4_FS is not set
818# CONFIG_FUSE_FS is not set
819
820#
821# CD-ROM/DVD Filesystems
822#
823CONFIG_ISO9660_FS=m
824CONFIG_JOLIET=y
825CONFIG_ZISOFS=y
826CONFIG_ZISOFS_FS=m
827CONFIG_UDF_FS=m
828CONFIG_UDF_NLS=y
829
830#
831# DOS/FAT/NT Filesystems
832#
833CONFIG_FAT_FS=m
834CONFIG_MSDOS_FS=m
835CONFIG_VFAT_FS=m
836CONFIG_FAT_DEFAULT_CODEPAGE=437
837CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
838# CONFIG_NTFS_FS is not set
839
840#
841# Pseudo filesystems
842#
843CONFIG_PROC_FS=y
844CONFIG_PROC_KCORE=y
845CONFIG_SYSFS=y
846CONFIG_TMPFS=y
847# CONFIG_HUGETLB_PAGE is not set
848CONFIG_RAMFS=y
849# CONFIG_RELAYFS_FS is not set
850
851#
852# Miscellaneous filesystems
853#
854# CONFIG_ADFS_FS is not set
855# CONFIG_AFFS_FS is not set
856# CONFIG_HFS_FS is not set
857# CONFIG_HFSPLUS_FS is not set
858# CONFIG_BEFS_FS is not set
859# CONFIG_BFS_FS is not set
860# CONFIG_EFS_FS is not set
861# CONFIG_JFFS_FS is not set
862CONFIG_JFFS2_FS=y
863CONFIG_JFFS2_FS_DEBUG=0
864CONFIG_JFFS2_FS_WRITEBUFFER=y
865# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
866CONFIG_JFFS2_ZLIB=y
867CONFIG_JFFS2_RTIME=y
868# CONFIG_JFFS2_RUBIN is not set
869CONFIG_CRAMFS=m
870# CONFIG_VXFS_FS is not set
871# CONFIG_HPFS_FS is not set
872# CONFIG_QNX4FS_FS is not set
873# CONFIG_SYSV_FS is not set
874# CONFIG_UFS_FS is not set
875
876#
877# Network File Systems
878#
879CONFIG_NFS_FS=y
880CONFIG_NFS_V3=y
881# CONFIG_NFS_V3_ACL is not set
882# CONFIG_NFS_V4 is not set
883# CONFIG_NFS_DIRECTIO is not set
884# CONFIG_NFSD is not set
885CONFIG_LOCKD=y
886CONFIG_LOCKD_V4=y
887CONFIG_NFS_COMMON=y
888CONFIG_SUNRPC=y
889# CONFIG_RPCSEC_GSS_KRB5 is not set
890# CONFIG_RPCSEC_GSS_SPKM3 is not set
891CONFIG_SMB_FS=y
892# CONFIG_SMB_NLS_DEFAULT is not set
893# CONFIG_CIFS is not set
894# CONFIG_NCP_FS is not set
895# CONFIG_CODA_FS is not set
896# CONFIG_AFS_FS is not set
897# CONFIG_9P_FS is not set
898
899#
900# Partition Types
901#
902# CONFIG_PARTITION_ADVANCED is not set
903CONFIG_MSDOS_PARTITION=y
904
905#
906# Native Language Support
907#
908CONFIG_NLS=y
909CONFIG_NLS_DEFAULT="iso8859-1"
910CONFIG_NLS_CODEPAGE_437=m
911CONFIG_NLS_CODEPAGE_737=m
912CONFIG_NLS_CODEPAGE_775=m
913CONFIG_NLS_CODEPAGE_850=m
914CONFIG_NLS_CODEPAGE_852=m
915CONFIG_NLS_CODEPAGE_855=m
916CONFIG_NLS_CODEPAGE_857=m
917CONFIG_NLS_CODEPAGE_860=m
918CONFIG_NLS_CODEPAGE_861=m
919CONFIG_NLS_CODEPAGE_862=m
920CONFIG_NLS_CODEPAGE_863=m
921CONFIG_NLS_CODEPAGE_864=m
922CONFIG_NLS_CODEPAGE_865=m
923CONFIG_NLS_CODEPAGE_866=m
924CONFIG_NLS_CODEPAGE_869=m
925CONFIG_NLS_CODEPAGE_936=m
926CONFIG_NLS_CODEPAGE_950=m
927CONFIG_NLS_CODEPAGE_932=m
928CONFIG_NLS_CODEPAGE_949=m
929CONFIG_NLS_CODEPAGE_874=m
930CONFIG_NLS_ISO8859_8=m
931CONFIG_NLS_CODEPAGE_1250=m
932CONFIG_NLS_CODEPAGE_1251=m
933CONFIG_NLS_ASCII=m
934CONFIG_NLS_ISO8859_1=m
935CONFIG_NLS_ISO8859_2=m
936CONFIG_NLS_ISO8859_3=m
937CONFIG_NLS_ISO8859_4=m
938CONFIG_NLS_ISO8859_5=m
939CONFIG_NLS_ISO8859_6=m
940CONFIG_NLS_ISO8859_7=m
941CONFIG_NLS_ISO8859_9=m
942CONFIG_NLS_ISO8859_13=m
943CONFIG_NLS_ISO8859_14=m
944CONFIG_NLS_ISO8859_15=m
945CONFIG_NLS_KOI8_R=m
946CONFIG_NLS_KOI8_U=m
947CONFIG_NLS_UTF8=m
948
949#
950# Profiling support
951#
952# CONFIG_PROFILING is not set
953
954#
955# Kernel hacking
956#
957# CONFIG_PRINTK_TIME is not set
958# CONFIG_DEBUG_KERNEL is not set
959CONFIG_LOG_BUF_SHIFT=14
960CONFIG_CROSSCOMPILE=y
961CONFIG_CMDLINE="mem=48M"
962
963#
964# Security options
965#
966CONFIG_KEYS=y
967CONFIG_KEYS_DEBUG_PROC_KEYS=y
968# CONFIG_SECURITY is not set
969
970#
971# Cryptographic options
972#
973# CONFIG_CRYPTO is not set
974
975#
976# Hardware crypto devices
977#
978
979#
980# Library routines
981#
982CONFIG_CRC_CCITT=y
983# CONFIG_CRC16 is not set
984CONFIG_CRC32=y
985CONFIG_LIBCRC32C=y
986CONFIG_ZLIB_INFLATE=y
987CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index fed6f2fab48b..1c2784dee697 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:01 2005 4# Thu Oct 20 22:25:36 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29CONFIG_HOTPLUG=y 27CONFIG_HOTPLUG=y
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,63 +59,81 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71CONFIG_MIPS_DB1500=y
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
83CONFIG_SOC_AU1X00=y 102# CONFIG_SGI_IP27 is not set
84# CONFIG_SOC_AU1000 is not set 103# CONFIG_SGI_IP32 is not set
85# CONFIG_SOC_AU1100 is not set 104# CONFIG_SIBYTE_BIGSUR is not set
86CONFIG_SOC_AU1500=y 105# CONFIG_SIBYTE_SWARM is not set
87# CONFIG_SOC_AU1550 is not set 106# CONFIG_SIBYTE_SENTOSA is not set
88# CONFIG_MIPS_PB1000 is not set 107# CONFIG_SIBYTE_RHONE is not set
89# CONFIG_MIPS_PB1100 is not set 108# CONFIG_SIBYTE_CARMEL is not set
90# CONFIG_MIPS_PB1500 is not set 109# CONFIG_SIBYTE_PTSWARM is not set
91# CONFIG_MIPS_PB1550 is not set 110# CONFIG_SIBYTE_LITTLESUR is not set
92# CONFIG_MIPS_DB1000 is not set 111# CONFIG_SIBYTE_CRHINE is not set
93# CONFIG_MIPS_DB1100 is not set 112# CONFIG_SIBYTE_CRHONE is not set
94CONFIG_MIPS_DB1500=y
95# CONFIG_MIPS_DB1550 is not set
96# CONFIG_MIPS_BOSPORUS is not set
97# CONFIG_MIPS_MIRAGE is not set
98# CONFIG_MIPS_XXS1500 is not set
99# CONFIG_MIPS_MTX1 is not set
100# CONFIG_SIBYTE_SB1xxx_SOC is not set
101# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
102# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
103CONFIG_RWSEM_GENERIC_SPINLOCK=y 117CONFIG_RWSEM_GENERIC_SPINLOCK=y
104CONFIG_GENERIC_CALIBRATE_DELAY=y 118CONFIG_GENERIC_CALIBRATE_DELAY=y
105CONFIG_HAVE_DEC_LOCK=y 119CONFIG_DMA_NONCOHERENT=y
106CONFIG_DMA_COHERENT=y 120CONFIG_DMA_NEED_PCI_MAP_STATE=y
107CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y 121CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
122# CONFIG_CPU_BIG_ENDIAN is not set
108CONFIG_CPU_LITTLE_ENDIAN=y 123CONFIG_CPU_LITTLE_ENDIAN=y
124CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
125CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
126CONFIG_SOC_AU1500=y
127CONFIG_SOC_AU1X00=y
109CONFIG_MIPS_L1_CACHE_SHIFT=5 128CONFIG_MIPS_L1_CACHE_SHIFT=5
110 129
111# 130#
112# CPU selection 131# CPU selection
113# 132#
114CONFIG_CPU_MIPS32=y 133CONFIG_CPU_MIPS32_R1=y
115# CONFIG_CPU_MIPS64 is not set 134# CONFIG_CPU_MIPS32_R2 is not set
135# CONFIG_CPU_MIPS64_R1 is not set
136# CONFIG_CPU_MIPS64_R2 is not set
116# CONFIG_CPU_R3000 is not set 137# CONFIG_CPU_R3000 is not set
117# CONFIG_CPU_TX39XX is not set 138# CONFIG_CPU_TX39XX is not set
118# CONFIG_CPU_VR41XX is not set 139# CONFIG_CPU_VR41XX is not set
@@ -128,15 +149,39 @@ CONFIG_CPU_MIPS32=y
128# CONFIG_CPU_RM7000 is not set 149# CONFIG_CPU_RM7000 is not set
129# CONFIG_CPU_RM9000 is not set 150# CONFIG_CPU_RM9000 is not set
130# CONFIG_CPU_SB1 is not set 151# CONFIG_CPU_SB1 is not set
152CONFIG_SYS_HAS_CPU_MIPS32_R1=y
153CONFIG_CPU_MIPS32=y
154CONFIG_CPU_MIPSR1=y
155CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
156CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
157
158#
159# Kernel type
160#
161CONFIG_32BIT=y
162# CONFIG_64BIT is not set
131CONFIG_PAGE_SIZE_4KB=y 163CONFIG_PAGE_SIZE_4KB=y
132# CONFIG_PAGE_SIZE_8KB is not set 164# CONFIG_PAGE_SIZE_8KB is not set
133# CONFIG_PAGE_SIZE_16KB is not set 165# CONFIG_PAGE_SIZE_16KB is not set
134# CONFIG_PAGE_SIZE_64KB is not set 166# CONFIG_PAGE_SIZE_64KB is not set
135CONFIG_CPU_HAS_PREFETCH=y 167CONFIG_CPU_HAS_PREFETCH=y
168# CONFIG_MIPS_MT is not set
136CONFIG_64BIT_PHYS_ADDR=y 169CONFIG_64BIT_PHYS_ADDR=y
137# CONFIG_CPU_ADVANCED is not set 170# CONFIG_CPU_ADVANCED is not set
138CONFIG_CPU_HAS_LLSC=y 171CONFIG_CPU_HAS_LLSC=y
139CONFIG_CPU_HAS_SYNC=y 172CONFIG_CPU_HAS_SYNC=y
173CONFIG_GENERIC_HARDIRQS=y
174CONFIG_GENERIC_IRQ_PROBE=y
175CONFIG_ARCH_FLATMEM_ENABLE=y
176CONFIG_SELECT_MEMORY_MODEL=y
177CONFIG_FLATMEM_MANUAL=y
178# CONFIG_DISCONTIGMEM_MANUAL is not set
179# CONFIG_SPARSEMEM_MANUAL is not set
180CONFIG_FLATMEM=y
181CONFIG_FLAT_NODE_MEM_MAP=y
182# CONFIG_SPARSEMEM_STATIC is not set
183CONFIG_PREEMPT_NONE=y
184# CONFIG_PREEMPT_VOLUNTARY is not set
140# CONFIG_PREEMPT is not set 185# CONFIG_PREEMPT is not set
141 186
142# 187#
@@ -145,7 +190,6 @@ CONFIG_CPU_HAS_SYNC=y
145CONFIG_HW_HAS_PCI=y 190CONFIG_HW_HAS_PCI=y
146CONFIG_PCI=y 191CONFIG_PCI=y
147CONFIG_PCI_LEGACY_PROC=y 192CONFIG_PCI_LEGACY_PROC=y
148CONFIG_PCI_NAMES=y
149CONFIG_MMU=y 193CONFIG_MMU=y
150 194
151# 195#
@@ -154,6 +198,8 @@ CONFIG_MMU=y
154CONFIG_PCCARD=m 198CONFIG_PCCARD=m
155# CONFIG_PCMCIA_DEBUG is not set 199# CONFIG_PCMCIA_DEBUG is not set
156CONFIG_PCMCIA=m 200CONFIG_PCMCIA=m
201CONFIG_PCMCIA_LOAD_CIS=y
202CONFIG_PCMCIA_IOCTL=y
157CONFIG_CARDBUS=y 203CONFIG_CARDBUS=y
158 204
159# 205#
@@ -176,6 +222,100 @@ CONFIG_PCMCIA_AU1X00=m
176CONFIG_BINFMT_ELF=y 222CONFIG_BINFMT_ELF=y
177# CONFIG_BINFMT_MISC is not set 223# CONFIG_BINFMT_MISC is not set
178CONFIG_TRAD_SIGNALS=y 224CONFIG_TRAD_SIGNALS=y
225# CONFIG_PM is not set
226
227#
228# Networking
229#
230CONFIG_NET=y
231
232#
233# Networking options
234#
235CONFIG_PACKET=y
236# CONFIG_PACKET_MMAP is not set
237CONFIG_UNIX=y
238CONFIG_XFRM=y
239CONFIG_XFRM_USER=m
240CONFIG_NET_KEY=y
241CONFIG_INET=y
242CONFIG_IP_MULTICAST=y
243# CONFIG_IP_ADVANCED_ROUTER is not set
244CONFIG_IP_FIB_HASH=y
245CONFIG_IP_PNP=y
246# CONFIG_IP_PNP_DHCP is not set
247CONFIG_IP_PNP_BOOTP=y
248# CONFIG_IP_PNP_RARP is not set
249# CONFIG_NET_IPIP is not set
250# CONFIG_NET_IPGRE is not set
251# CONFIG_IP_MROUTE is not set
252# CONFIG_ARPD is not set
253# CONFIG_SYN_COOKIES is not set
254# CONFIG_INET_AH is not set
255# CONFIG_INET_ESP is not set
256# CONFIG_INET_IPCOMP is not set
257CONFIG_INET_TUNNEL=m
258CONFIG_INET_DIAG=y
259CONFIG_INET_TCP_DIAG=y
260# CONFIG_TCP_CONG_ADVANCED is not set
261CONFIG_TCP_CONG_BIC=y
262
263#
264# IP: Virtual Server Configuration
265#
266# CONFIG_IP_VS is not set
267# CONFIG_IPV6 is not set
268CONFIG_NETFILTER=y
269# CONFIG_NETFILTER_DEBUG is not set
270CONFIG_NETFILTER_NETLINK=m
271CONFIG_NETFILTER_NETLINK_QUEUE=m
272CONFIG_NETFILTER_NETLINK_LOG=m
273
274#
275# IP: Netfilter Configuration
276#
277# CONFIG_IP_NF_CONNTRACK is not set
278CONFIG_IP_NF_PPTP=m
279# CONFIG_IP_NF_QUEUE is not set
280# CONFIG_IP_NF_IPTABLES is not set
281# CONFIG_IP_NF_ARPTABLES is not set
282
283#
284# DCCP Configuration (EXPERIMENTAL)
285#
286# CONFIG_IP_DCCP is not set
287
288#
289# SCTP Configuration (EXPERIMENTAL)
290#
291# CONFIG_IP_SCTP is not set
292# CONFIG_ATM is not set
293# CONFIG_BRIDGE is not set
294# CONFIG_VLAN_8021Q is not set
295# CONFIG_DECNET is not set
296# CONFIG_LLC2 is not set
297# CONFIG_IPX is not set
298# CONFIG_ATALK is not set
299# CONFIG_X25 is not set
300# CONFIG_LAPB is not set
301# CONFIG_NET_DIVERT is not set
302# CONFIG_ECONET is not set
303# CONFIG_WAN_ROUTER is not set
304# CONFIG_NET_SCHED is not set
305# CONFIG_NET_CLS_ROUTE is not set
306
307#
308# Network testing
309#
310# CONFIG_NET_PKTGEN is not set
311# CONFIG_HAMRADIO is not set
312# CONFIG_IRDA is not set
313# CONFIG_BT is not set
314CONFIG_IEEE80211=m
315# CONFIG_IEEE80211_DEBUG is not set
316CONFIG_IEEE80211_CRYPT_WEP=m
317CONFIG_IEEE80211_CRYPT_CCMP=m
318CONFIG_IEEE80211_CRYPT_TKIP=m
179 319
180# 320#
181# Device Drivers 321# Device Drivers
@@ -186,15 +326,20 @@ CONFIG_TRAD_SIGNALS=y
186# 326#
187CONFIG_STANDALONE=y 327CONFIG_STANDALONE=y
188CONFIG_PREVENT_FIRMWARE_BUILD=y 328CONFIG_PREVENT_FIRMWARE_BUILD=y
189# CONFIG_FW_LOADER is not set 329CONFIG_FW_LOADER=m
330
331#
332# Connector - unified userspace <-> kernelspace linker
333#
334CONFIG_CONNECTOR=m
190 335
191# 336#
192# Memory Technology Devices (MTD) 337# Memory Technology Devices (MTD)
193# 338#
194CONFIG_MTD=y 339CONFIG_MTD=y
195# CONFIG_MTD_DEBUG is not set 340# CONFIG_MTD_DEBUG is not set
196CONFIG_MTD_PARTITIONS=y
197# CONFIG_MTD_CONCAT is not set 341# CONFIG_MTD_CONCAT is not set
342CONFIG_MTD_PARTITIONS=y
198# CONFIG_MTD_REDBOOT_PARTS is not set 343# CONFIG_MTD_REDBOOT_PARTS is not set
199# CONFIG_MTD_CMDLINE_PARTS is not set 344# CONFIG_MTD_CMDLINE_PARTS is not set
200 345
@@ -232,16 +377,14 @@ CONFIG_MTD_CFI_UTIL=y
232# CONFIG_MTD_RAM is not set 377# CONFIG_MTD_RAM is not set
233# CONFIG_MTD_ROM is not set 378# CONFIG_MTD_ROM is not set
234# CONFIG_MTD_ABSENT is not set 379# CONFIG_MTD_ABSENT is not set
235# CONFIG_MTD_XIP is not set
236 380
237# 381#
238# Mapping drivers for chip access 382# Mapping drivers for chip access
239# 383#
240# CONFIG_MTD_COMPLEX_MAPPINGS is not set 384# CONFIG_MTD_COMPLEX_MAPPINGS is not set
241# CONFIG_MTD_PHYSMAP is not set 385# CONFIG_MTD_PHYSMAP is not set
242CONFIG_MTD_DB1X00=y 386CONFIG_MTD_ALCHEMY=y
243CONFIG_MTD_DB1X00_BOOT=y 387# CONFIG_MTD_PLATRAM is not set
244CONFIG_MTD_DB1X00_USER=y
245 388
246# 389#
247# Self-contained MTD device drivers 390# Self-contained MTD device drivers
@@ -277,7 +420,6 @@ CONFIG_MTD_DB1X00_USER=y
277# 420#
278# Block devices 421# Block devices
279# 422#
280# CONFIG_BLK_DEV_FD is not set
281# CONFIG_BLK_CPQ_DA is not set 423# CONFIG_BLK_CPQ_DA is not set
282# CONFIG_BLK_CPQ_CISS_DA is not set 424# CONFIG_BLK_CPQ_CISS_DA is not set
283# CONFIG_BLK_DEV_DAC960 is not set 425# CONFIG_BLK_DEV_DAC960 is not set
@@ -290,7 +432,6 @@ CONFIG_BLK_DEV_LOOP=y
290# CONFIG_BLK_DEV_UB is not set 432# CONFIG_BLK_DEV_UB is not set
291# CONFIG_BLK_DEV_RAM is not set 433# CONFIG_BLK_DEV_RAM is not set
292CONFIG_BLK_DEV_RAM_COUNT=16 434CONFIG_BLK_DEV_RAM_COUNT=16
293CONFIG_INITRAMFS_SOURCE=""
294# CONFIG_LBD is not set 435# CONFIG_LBD is not set
295CONFIG_CDROM_PKTCDVD=m 436CONFIG_CDROM_PKTCDVD=m
296CONFIG_CDROM_PKTCDVD_BUFFERS=8 437CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -336,6 +477,7 @@ CONFIG_BLK_DEV_IDECS=m
336# 477#
337# SCSI device support 478# SCSI device support
338# 479#
480CONFIG_RAID_ATTRS=m
339# CONFIG_SCSI is not set 481# CONFIG_SCSI is not set
340 482
341# 483#
@@ -346,6 +488,7 @@ CONFIG_BLK_DEV_IDECS=m
346# 488#
347# Fusion MPT device support 489# Fusion MPT device support
348# 490#
491# CONFIG_FUSION is not set
349 492
350# 493#
351# IEEE 1394 (FireWire) support 494# IEEE 1394 (FireWire) support
@@ -358,94 +501,13 @@ CONFIG_BLK_DEV_IDECS=m
358# CONFIG_I2O is not set 501# CONFIG_I2O is not set
359 502
360# 503#
361# Networking support 504# Network device support
362#
363CONFIG_NET=y
364
365#
366# Networking options
367#
368CONFIG_PACKET=y
369# CONFIG_PACKET_MMAP is not set
370CONFIG_NETLINK_DEV=y
371CONFIG_UNIX=y
372CONFIG_NET_KEY=y
373CONFIG_INET=y
374CONFIG_IP_MULTICAST=y
375# CONFIG_IP_ADVANCED_ROUTER is not set
376CONFIG_IP_PNP=y
377# CONFIG_IP_PNP_DHCP is not set
378CONFIG_IP_PNP_BOOTP=y
379# CONFIG_IP_PNP_RARP is not set
380# CONFIG_NET_IPIP is not set
381# CONFIG_NET_IPGRE is not set
382# CONFIG_IP_MROUTE is not set
383# CONFIG_ARPD is not set
384# CONFIG_SYN_COOKIES is not set
385# CONFIG_INET_AH is not set
386# CONFIG_INET_ESP is not set
387# CONFIG_INET_IPCOMP is not set
388CONFIG_INET_TUNNEL=m
389CONFIG_IP_TCPDIAG=m
390# CONFIG_IP_TCPDIAG_IPV6 is not set
391
392#
393# IP: Virtual Server Configuration
394# 505#
395# CONFIG_IP_VS is not set
396# CONFIG_IPV6 is not set
397CONFIG_NETFILTER=y
398# CONFIG_NETFILTER_DEBUG is not set
399
400#
401# IP: Netfilter Configuration
402#
403# CONFIG_IP_NF_CONNTRACK is not set
404CONFIG_IP_NF_CONNTRACK_MARK=y
405# CONFIG_IP_NF_QUEUE is not set
406# CONFIG_IP_NF_IPTABLES is not set
407# CONFIG_IP_NF_ARPTABLES is not set
408CONFIG_XFRM=y
409CONFIG_XFRM_USER=m
410
411#
412# SCTP Configuration (EXPERIMENTAL)
413#
414# CONFIG_IP_SCTP is not set
415# CONFIG_ATM is not set
416# CONFIG_BRIDGE is not set
417# CONFIG_VLAN_8021Q is not set
418# CONFIG_DECNET is not set
419# CONFIG_LLC2 is not set
420# CONFIG_IPX is not set
421# CONFIG_ATALK is not set
422# CONFIG_X25 is not set
423# CONFIG_LAPB is not set
424# CONFIG_NET_DIVERT is not set
425# CONFIG_ECONET is not set
426# CONFIG_WAN_ROUTER is not set
427
428#
429# QoS and/or fair queueing
430#
431# CONFIG_NET_SCHED is not set
432# CONFIG_NET_CLS_ROUTE is not set
433
434#
435# Network testing
436#
437# CONFIG_NET_PKTGEN is not set
438# CONFIG_NETPOLL is not set
439# CONFIG_NET_POLL_CONTROLLER is not set
440# CONFIG_HAMRADIO is not set
441# CONFIG_IRDA is not set
442# CONFIG_BT is not set
443CONFIG_NETDEVICES=y 506CONFIG_NETDEVICES=y
444# CONFIG_DUMMY is not set 507# CONFIG_DUMMY is not set
445# CONFIG_BONDING is not set 508# CONFIG_BONDING is not set
446# CONFIG_EQUALIZER is not set 509# CONFIG_EQUALIZER is not set
447# CONFIG_TUN is not set 510# CONFIG_TUN is not set
448# CONFIG_ETHERTAP is not set
449 511
450# 512#
451# ARCnet devices 513# ARCnet devices
@@ -453,6 +515,21 @@ CONFIG_NETDEVICES=y
453# CONFIG_ARCNET is not set 515# CONFIG_ARCNET is not set
454 516
455# 517#
518# PHY device support
519#
520CONFIG_PHYLIB=m
521CONFIG_PHYCONTROL=y
522
523#
524# MII PHY device drivers
525#
526CONFIG_MARVELL_PHY=m
527CONFIG_DAVICOM_PHY=m
528CONFIG_QSEMI_PHY=m
529CONFIG_LXT_PHY=m
530CONFIG_CICADA_PHY=m
531
532#
456# Ethernet (10 or 100Mbit) 533# Ethernet (10 or 100Mbit)
457# 534#
458CONFIG_NET_ETHERNET=y 535CONFIG_NET_ETHERNET=y
@@ -479,12 +556,16 @@ CONFIG_MIPS_AU1X00_ENET=y
479# CONFIG_HAMACHI is not set 556# CONFIG_HAMACHI is not set
480# CONFIG_YELLOWFIN is not set 557# CONFIG_YELLOWFIN is not set
481# CONFIG_R8169 is not set 558# CONFIG_R8169 is not set
559# CONFIG_SIS190 is not set
560# CONFIG_SKGE is not set
482# CONFIG_SK98LIN is not set 561# CONFIG_SK98LIN is not set
483# CONFIG_TIGON3 is not set 562# CONFIG_TIGON3 is not set
563# CONFIG_BNX2 is not set
484 564
485# 565#
486# Ethernet (10000 Mbit) 566# Ethernet (10000 Mbit)
487# 567#
568# CONFIG_CHELSIO_T1 is not set
488# CONFIG_IXGB is not set 569# CONFIG_IXGB is not set
489# CONFIG_S2IO is not set 570# CONFIG_S2IO is not set
490 571
@@ -497,6 +578,8 @@ CONFIG_MIPS_AU1X00_ENET=y
497# Wireless LAN (non-hamradio) 578# Wireless LAN (non-hamradio)
498# 579#
499# CONFIG_NET_RADIO is not set 580# CONFIG_NET_RADIO is not set
581# CONFIG_IPW_DEBUG is not set
582CONFIG_IPW2200=m
500 583
501# 584#
502# PCMCIA network device support 585# PCMCIA network device support
@@ -520,6 +603,8 @@ CONFIG_PPPOE=m
520# CONFIG_SLIP is not set 603# CONFIG_SLIP is not set
521# CONFIG_SHAPER is not set 604# CONFIG_SHAPER is not set
522# CONFIG_NETCONSOLE is not set 605# CONFIG_NETCONSOLE is not set
606# CONFIG_NETPOLL is not set
607# CONFIG_NET_POLL_CONTROLLER is not set
523 608
524# 609#
525# ISDN subsystem 610# ISDN subsystem
@@ -549,19 +634,6 @@ CONFIG_INPUT_EVDEV=y
549# CONFIG_INPUT_EVBUG is not set 634# CONFIG_INPUT_EVBUG is not set
550 635
551# 636#
552# Input I/O drivers
553#
554# CONFIG_GAMEPORT is not set
555CONFIG_SOUND_GAMEPORT=y
556CONFIG_SERIO=y
557# CONFIG_SERIO_I8042 is not set
558CONFIG_SERIO_SERPORT=y
559# CONFIG_SERIO_CT82C710 is not set
560# CONFIG_SERIO_PCIPS2 is not set
561# CONFIG_SERIO_LIBPS2 is not set
562CONFIG_SERIO_RAW=m
563
564#
565# Input Device Drivers 637# Input Device Drivers
566# 638#
567# CONFIG_INPUT_KEYBOARD is not set 639# CONFIG_INPUT_KEYBOARD is not set
@@ -571,6 +643,17 @@ CONFIG_SERIO_RAW=m
571# CONFIG_INPUT_MISC is not set 643# CONFIG_INPUT_MISC is not set
572 644
573# 645#
646# Hardware I/O ports
647#
648CONFIG_SERIO=y
649# CONFIG_SERIO_I8042 is not set
650CONFIG_SERIO_SERPORT=y
651# CONFIG_SERIO_PCIPS2 is not set
652# CONFIG_SERIO_LIBPS2 is not set
653CONFIG_SERIO_RAW=m
654# CONFIG_GAMEPORT is not set
655
656#
574# Character devices 657# Character devices
575# 658#
576# CONFIG_VT is not set 659# CONFIG_VT is not set
@@ -590,6 +673,7 @@ CONFIG_SERIAL_AU1X00=y
590CONFIG_SERIAL_AU1X00_CONSOLE=y 673CONFIG_SERIAL_AU1X00_CONSOLE=y
591CONFIG_SERIAL_CORE=y 674CONFIG_SERIAL_CORE=y
592CONFIG_SERIAL_CORE_CONSOLE=y 675CONFIG_SERIAL_CORE_CONSOLE=y
676# CONFIG_SERIAL_JSM is not set
593CONFIG_UNIX98_PTYS=y 677CONFIG_UNIX98_PTYS=y
594CONFIG_LEGACY_PTYS=y 678CONFIG_LEGACY_PTYS=y
595CONFIG_LEGACY_PTY_COUNT=256 679CONFIG_LEGACY_PTY_COUNT=256
@@ -603,7 +687,8 @@ CONFIG_LEGACY_PTY_COUNT=256
603# Watchdog Cards 687# Watchdog Cards
604# 688#
605# CONFIG_WATCHDOG is not set 689# CONFIG_WATCHDOG is not set
606CONFIG_RTC=y 690# CONFIG_RTC is not set
691# CONFIG_GEN_RTC is not set
607# CONFIG_DTLK is not set 692# CONFIG_DTLK is not set
608# CONFIG_R3964 is not set 693# CONFIG_R3964 is not set
609# CONFIG_APPLICOM is not set 694# CONFIG_APPLICOM is not set
@@ -620,6 +705,11 @@ CONFIG_SYNCLINK_CS=m
620# CONFIG_RAW_DRIVER is not set 705# CONFIG_RAW_DRIVER is not set
621 706
622# 707#
708# TPM devices
709#
710# CONFIG_TCG_TPM is not set
711
712#
623# I2C support 713# I2C support
624# 714#
625# CONFIG_I2C is not set 715# CONFIG_I2C is not set
@@ -630,10 +720,20 @@ CONFIG_SYNCLINK_CS=m
630# CONFIG_W1 is not set 720# CONFIG_W1 is not set
631 721
632# 722#
723# Hardware Monitoring support
724#
725# CONFIG_HWMON is not set
726# CONFIG_HWMON_VID is not set
727
728#
633# Misc devices 729# Misc devices
634# 730#
635 731
636# 732#
733# Multimedia Capabilities Port drivers
734#
735
736#
637# Multimedia devices 737# Multimedia devices
638# 738#
639# CONFIG_VIDEO_DEV is not set 739# CONFIG_VIDEO_DEV is not set
@@ -647,7 +747,6 @@ CONFIG_SYNCLINK_CS=m
647# Graphics support 747# Graphics support
648# 748#
649# CONFIG_FB is not set 749# CONFIG_FB is not set
650# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
651 750
652# 751#
653# Sound 752# Sound
@@ -680,7 +779,6 @@ CONFIG_SOUND_AU1000=y
680# CONFIG_SOUND_MSNDCLAS is not set 779# CONFIG_SOUND_MSNDCLAS is not set
681# CONFIG_SOUND_MSNDPIN is not set 780# CONFIG_SOUND_MSNDPIN is not set
682# CONFIG_SOUND_VIA82CXXX is not set 781# CONFIG_SOUND_VIA82CXXX is not set
683# CONFIG_SOUND_OSS is not set
684# CONFIG_SOUND_ALI5455 is not set 782# CONFIG_SOUND_ALI5455 is not set
685# CONFIG_SOUND_FORTE is not set 783# CONFIG_SOUND_FORTE is not set
686# CONFIG_SOUND_RME96XX is not set 784# CONFIG_SOUND_RME96XX is not set
@@ -689,6 +787,8 @@ CONFIG_SOUND_AU1000=y
689# 787#
690# USB support 788# USB support
691# 789#
790CONFIG_USB_ARCH_HAS_HCD=y
791CONFIG_USB_ARCH_HAS_OHCI=y
692CONFIG_USB=y 792CONFIG_USB=y
693# CONFIG_USB_DEBUG is not set 793# CONFIG_USB_DEBUG is not set
694 794
@@ -699,23 +799,23 @@ CONFIG_USB=y
699# CONFIG_USB_BANDWIDTH is not set 799# CONFIG_USB_BANDWIDTH is not set
700# CONFIG_USB_DYNAMIC_MINORS is not set 800# CONFIG_USB_DYNAMIC_MINORS is not set
701# CONFIG_USB_OTG is not set 801# CONFIG_USB_OTG is not set
702CONFIG_USB_ARCH_HAS_HCD=y
703CONFIG_USB_ARCH_HAS_OHCI=y
704 802
705# 803#
706# USB Host Controller Drivers 804# USB Host Controller Drivers
707# 805#
708# CONFIG_USB_EHCI_HCD is not set 806# CONFIG_USB_EHCI_HCD is not set
807# CONFIG_USB_ISP116X_HCD is not set
709CONFIG_USB_OHCI_HCD=y 808CONFIG_USB_OHCI_HCD=y
809# CONFIG_USB_OHCI_BIG_ENDIAN is not set
810CONFIG_USB_OHCI_LITTLE_ENDIAN=y
710# CONFIG_USB_UHCI_HCD is not set 811# CONFIG_USB_UHCI_HCD is not set
711# CONFIG_USB_SL811_HCD is not set 812# CONFIG_USB_SL811_HCD is not set
712 813
713# 814#
714# USB Device Class drivers 815# USB Device Class drivers
715# 816#
716# CONFIG_USB_AUDIO is not set 817# CONFIG_OBSOLETE_OSS_USB_DRIVER is not set
717# CONFIG_USB_BLUETOOTH_TTY is not set 818# CONFIG_USB_BLUETOOTH_TTY is not set
718# CONFIG_USB_MIDI is not set
719# CONFIG_USB_ACM is not set 819# CONFIG_USB_ACM is not set
720# CONFIG_USB_PRINTER is not set 820# CONFIG_USB_PRINTER is not set
721 821
@@ -733,12 +833,17 @@ CONFIG_USB_HIDINPUT=y
733# CONFIG_USB_HIDDEV is not set 833# CONFIG_USB_HIDDEV is not set
734# CONFIG_USB_AIPTEK is not set 834# CONFIG_USB_AIPTEK is not set
735# CONFIG_USB_WACOM is not set 835# CONFIG_USB_WACOM is not set
836# CONFIG_USB_ACECAD is not set
736# CONFIG_USB_KBTAB is not set 837# CONFIG_USB_KBTAB is not set
737# CONFIG_USB_POWERMATE is not set 838# CONFIG_USB_POWERMATE is not set
738# CONFIG_USB_MTOUCH is not set 839# CONFIG_USB_MTOUCH is not set
840# CONFIG_USB_ITMTOUCH is not set
739# CONFIG_USB_EGALAX is not set 841# CONFIG_USB_EGALAX is not set
842CONFIG_USB_YEALINK=m
740# CONFIG_USB_XPAD is not set 843# CONFIG_USB_XPAD is not set
741# CONFIG_USB_ATI_REMOTE is not set 844# CONFIG_USB_ATI_REMOTE is not set
845# CONFIG_USB_KEYSPAN_REMOTE is not set
846# CONFIG_USB_APPLETOUCH is not set
742 847
743# 848#
744# USB Imaging devices 849# USB Imaging devices
@@ -762,6 +867,7 @@ CONFIG_USB_HIDINPUT=y
762# CONFIG_USB_PEGASUS is not set 867# CONFIG_USB_PEGASUS is not set
763# CONFIG_USB_RTL8150 is not set 868# CONFIG_USB_RTL8150 is not set
764# CONFIG_USB_USBNET is not set 869# CONFIG_USB_USBNET is not set
870CONFIG_USB_MON=y
765 871
766# 872#
767# USB port drivers 873# USB port drivers
@@ -786,9 +892,10 @@ CONFIG_USB_HIDINPUT=y
786# CONFIG_USB_PHIDGETKIT is not set 892# CONFIG_USB_PHIDGETKIT is not set
787# CONFIG_USB_PHIDGETSERVO is not set 893# CONFIG_USB_PHIDGETSERVO is not set
788# CONFIG_USB_IDMOUSE is not set 894# CONFIG_USB_IDMOUSE is not set
895CONFIG_USB_LD=m
789 896
790# 897#
791# USB ATM/DSL drivers 898# USB DSL modem support
792# 899#
793 900
794# 901#
@@ -807,12 +914,17 @@ CONFIG_USB_HIDINPUT=y
807# CONFIG_INFINIBAND is not set 914# CONFIG_INFINIBAND is not set
808 915
809# 916#
917# SN Devices
918#
919
920#
810# File systems 921# File systems
811# 922#
812CONFIG_EXT2_FS=y 923CONFIG_EXT2_FS=y
813CONFIG_EXT2_FS_XATTR=y 924CONFIG_EXT2_FS_XATTR=y
814CONFIG_EXT2_FS_POSIX_ACL=y 925CONFIG_EXT2_FS_POSIX_ACL=y
815# CONFIG_EXT2_FS_SECURITY is not set 926# CONFIG_EXT2_FS_SECURITY is not set
927# CONFIG_EXT2_FS_XIP is not set
816CONFIG_EXT3_FS=y 928CONFIG_EXT3_FS=y
817CONFIG_EXT3_FS_XATTR=y 929CONFIG_EXT3_FS_XATTR=y
818CONFIG_EXT3_FS_POSIX_ACL=y 930CONFIG_EXT3_FS_POSIX_ACL=y
@@ -831,10 +943,12 @@ CONFIG_FS_POSIX_ACL=y
831# CONFIG_XFS_FS is not set 943# CONFIG_XFS_FS is not set
832# CONFIG_MINIX_FS is not set 944# CONFIG_MINIX_FS is not set
833# CONFIG_ROMFS_FS is not set 945# CONFIG_ROMFS_FS is not set
946CONFIG_INOTIFY=y
834# CONFIG_QUOTA is not set 947# CONFIG_QUOTA is not set
835CONFIG_DNOTIFY=y 948CONFIG_DNOTIFY=y
836CONFIG_AUTOFS_FS=m 949CONFIG_AUTOFS_FS=m
837CONFIG_AUTOFS4_FS=m 950CONFIG_AUTOFS4_FS=m
951CONFIG_FUSE_FS=m
838 952
839# 953#
840# CD-ROM/DVD Filesystems 954# CD-ROM/DVD Filesystems
@@ -855,13 +969,10 @@ CONFIG_AUTOFS4_FS=m
855CONFIG_PROC_FS=y 969CONFIG_PROC_FS=y
856CONFIG_PROC_KCORE=y 970CONFIG_PROC_KCORE=y
857CONFIG_SYSFS=y 971CONFIG_SYSFS=y
858# CONFIG_DEVFS_FS is not set
859CONFIG_DEVPTS_FS_XATTR=y
860CONFIG_DEVPTS_FS_SECURITY=y
861CONFIG_TMPFS=y 972CONFIG_TMPFS=y
862# CONFIG_TMPFS_XATTR is not set
863# CONFIG_HUGETLB_PAGE is not set 973# CONFIG_HUGETLB_PAGE is not set
864CONFIG_RAMFS=y 974CONFIG_RAMFS=y
975CONFIG_RELAYFS_FS=m
865 976
866# 977#
867# Miscellaneous filesystems 978# Miscellaneous filesystems
@@ -895,6 +1006,7 @@ CONFIG_NFSD=m
895CONFIG_ROOT_NFS=y 1006CONFIG_ROOT_NFS=y
896CONFIG_LOCKD=y 1007CONFIG_LOCKD=y
897CONFIG_EXPORTFS=m 1008CONFIG_EXPORTFS=m
1009CONFIG_NFS_COMMON=y
898CONFIG_SUNRPC=y 1010CONFIG_SUNRPC=y
899# CONFIG_RPCSEC_GSS_KRB5 is not set 1011# CONFIG_RPCSEC_GSS_KRB5 is not set
900# CONFIG_RPCSEC_GSS_SPKM3 is not set 1012# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -904,6 +1016,7 @@ CONFIG_SMB_FS=m
904# CONFIG_NCP_FS is not set 1016# CONFIG_NCP_FS is not set
905# CONFIG_CODA_FS is not set 1017# CONFIG_CODA_FS is not set
906# CONFIG_AFS_FS is not set 1018# CONFIG_AFS_FS is not set
1019# CONFIG_9P_FS is not set
907 1020
908# 1021#
909# Partition Types 1022# Partition Types
@@ -963,7 +1076,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
963# 1076#
964# Kernel hacking 1077# Kernel hacking
965# 1078#
1079# CONFIG_PRINTK_TIME is not set
966# CONFIG_DEBUG_KERNEL is not set 1080# CONFIG_DEBUG_KERNEL is not set
1081CONFIG_LOG_BUF_SHIFT=14
967CONFIG_CROSSCOMPILE=y 1082CONFIG_CROSSCOMPILE=y
968CONFIG_CMDLINE="" 1083CONFIG_CMDLINE=""
969 1084
@@ -979,26 +1094,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
979# 1094#
980CONFIG_CRYPTO=y 1095CONFIG_CRYPTO=y
981CONFIG_CRYPTO_HMAC=y 1096CONFIG_CRYPTO_HMAC=y
982CONFIG_CRYPTO_NULL=y 1097CONFIG_CRYPTO_NULL=m
983# CONFIG_CRYPTO_MD4 is not set 1098CONFIG_CRYPTO_MD4=m
984# CONFIG_CRYPTO_MD5 is not set 1099CONFIG_CRYPTO_MD5=m
985# CONFIG_CRYPTO_SHA1 is not set 1100CONFIG_CRYPTO_SHA1=m
986# CONFIG_CRYPTO_SHA256 is not set 1101CONFIG_CRYPTO_SHA256=m
987CONFIG_CRYPTO_SHA512=y 1102CONFIG_CRYPTO_SHA512=m
988CONFIG_CRYPTO_WP512=m 1103CONFIG_CRYPTO_WP512=m
989# CONFIG_CRYPTO_DES is not set 1104CONFIG_CRYPTO_TGR192=m
990# CONFIG_CRYPTO_BLOWFISH is not set 1105CONFIG_CRYPTO_DES=m
991CONFIG_CRYPTO_TWOFISH=y 1106CONFIG_CRYPTO_BLOWFISH=m
992# CONFIG_CRYPTO_SERPENT is not set 1107CONFIG_CRYPTO_TWOFISH=m
1108CONFIG_CRYPTO_SERPENT=m
993CONFIG_CRYPTO_AES=m 1109CONFIG_CRYPTO_AES=m
994# CONFIG_CRYPTO_CAST5 is not set 1110CONFIG_CRYPTO_CAST5=m
995# CONFIG_CRYPTO_CAST6 is not set 1111CONFIG_CRYPTO_CAST6=m
996CONFIG_CRYPTO_TEA=m 1112CONFIG_CRYPTO_TEA=m
997# CONFIG_CRYPTO_ARC4 is not set 1113CONFIG_CRYPTO_ARC4=m
998CONFIG_CRYPTO_KHAZAD=m 1114CONFIG_CRYPTO_KHAZAD=m
999CONFIG_CRYPTO_ANUBIS=m 1115CONFIG_CRYPTO_ANUBIS=m
1000CONFIG_CRYPTO_DEFLATE=y 1116CONFIG_CRYPTO_DEFLATE=m
1001CONFIG_CRYPTO_MICHAEL_MIC=y 1117CONFIG_CRYPTO_MICHAEL_MIC=m
1002CONFIG_CRYPTO_CRC32C=m 1118CONFIG_CRYPTO_CRC32C=m
1003# CONFIG_CRYPTO_TEST is not set 1119# CONFIG_CRYPTO_TEST is not set
1004 1120
@@ -1010,9 +1126,8 @@ CONFIG_CRYPTO_CRC32C=m
1010# Library routines 1126# Library routines
1011# 1127#
1012CONFIG_CRC_CCITT=m 1128CONFIG_CRC_CCITT=m
1129CONFIG_CRC16=m
1013CONFIG_CRC32=y 1130CONFIG_CRC32=y
1014CONFIG_LIBCRC32C=m 1131CONFIG_LIBCRC32C=m
1015CONFIG_ZLIB_INFLATE=y 1132CONFIG_ZLIB_INFLATE=m
1016CONFIG_ZLIB_DEFLATE=y 1133CONFIG_ZLIB_DEFLATE=m
1017CONFIG_GENERIC_HARDIRQS=y
1018CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 178c0ad1af75..64248e2e924a 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:02 2005 4# Thu Oct 20 22:25:39 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29CONFIG_HOTPLUG=y 27CONFIG_HOTPLUG=y
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,63 +59,80 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72CONFIG_MIPS_DB1550=y
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
83CONFIG_SOC_AU1X00=y 102# CONFIG_SGI_IP27 is not set
84# CONFIG_SOC_AU1000 is not set 103# CONFIG_SGI_IP32 is not set
85# CONFIG_SOC_AU1100 is not set 104# CONFIG_SIBYTE_BIGSUR is not set
86# CONFIG_SOC_AU1500 is not set 105# CONFIG_SIBYTE_SWARM is not set
87CONFIG_SOC_AU1550=y 106# CONFIG_SIBYTE_SENTOSA is not set
88# CONFIG_MIPS_PB1000 is not set 107# CONFIG_SIBYTE_RHONE is not set
89# CONFIG_MIPS_PB1100 is not set 108# CONFIG_SIBYTE_CARMEL is not set
90# CONFIG_MIPS_PB1500 is not set 109# CONFIG_SIBYTE_PTSWARM is not set
91# CONFIG_MIPS_PB1550 is not set 110# CONFIG_SIBYTE_LITTLESUR is not set
92# CONFIG_MIPS_DB1000 is not set 111# CONFIG_SIBYTE_CRHINE is not set
93# CONFIG_MIPS_DB1100 is not set 112# CONFIG_SIBYTE_CRHONE is not set
94# CONFIG_MIPS_DB1500 is not set
95CONFIG_MIPS_DB1550=y
96# CONFIG_MIPS_BOSPORUS is not set
97# CONFIG_MIPS_MIRAGE is not set
98# CONFIG_MIPS_XXS1500 is not set
99# CONFIG_MIPS_MTX1 is not set
100# CONFIG_SIBYTE_SB1xxx_SOC is not set
101# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
102# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
103CONFIG_RWSEM_GENERIC_SPINLOCK=y 117CONFIG_RWSEM_GENERIC_SPINLOCK=y
104CONFIG_GENERIC_CALIBRATE_DELAY=y 118CONFIG_GENERIC_CALIBRATE_DELAY=y
105CONFIG_HAVE_DEC_LOCK=y 119CONFIG_DMA_NONCOHERENT=y
106CONFIG_DMA_COHERENT=y 120CONFIG_DMA_NEED_PCI_MAP_STATE=y
107CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y 121CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
122# CONFIG_CPU_BIG_ENDIAN is not set
108CONFIG_CPU_LITTLE_ENDIAN=y 123CONFIG_CPU_LITTLE_ENDIAN=y
124CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
125CONFIG_SOC_AU1550=y
126CONFIG_SOC_AU1X00=y
109CONFIG_MIPS_L1_CACHE_SHIFT=5 127CONFIG_MIPS_L1_CACHE_SHIFT=5
110 128
111# 129#
112# CPU selection 130# CPU selection
113# 131#
114CONFIG_CPU_MIPS32=y 132CONFIG_CPU_MIPS32_R1=y
115# CONFIG_CPU_MIPS64 is not set 133# CONFIG_CPU_MIPS32_R2 is not set
134# CONFIG_CPU_MIPS64_R1 is not set
135# CONFIG_CPU_MIPS64_R2 is not set
116# CONFIG_CPU_R3000 is not set 136# CONFIG_CPU_R3000 is not set
117# CONFIG_CPU_TX39XX is not set 137# CONFIG_CPU_TX39XX is not set
118# CONFIG_CPU_VR41XX is not set 138# CONFIG_CPU_VR41XX is not set
@@ -128,15 +148,39 @@ CONFIG_CPU_MIPS32=y
128# CONFIG_CPU_RM7000 is not set 148# CONFIG_CPU_RM7000 is not set
129# CONFIG_CPU_RM9000 is not set 149# CONFIG_CPU_RM9000 is not set
130# CONFIG_CPU_SB1 is not set 150# CONFIG_CPU_SB1 is not set
151CONFIG_SYS_HAS_CPU_MIPS32_R1=y
152CONFIG_CPU_MIPS32=y
153CONFIG_CPU_MIPSR1=y
154CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
155CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
156
157#
158# Kernel type
159#
160CONFIG_32BIT=y
161# CONFIG_64BIT is not set
131CONFIG_PAGE_SIZE_4KB=y 162CONFIG_PAGE_SIZE_4KB=y
132# CONFIG_PAGE_SIZE_8KB is not set 163# CONFIG_PAGE_SIZE_8KB is not set
133# CONFIG_PAGE_SIZE_16KB is not set 164# CONFIG_PAGE_SIZE_16KB is not set
134# CONFIG_PAGE_SIZE_64KB is not set 165# CONFIG_PAGE_SIZE_64KB is not set
135CONFIG_CPU_HAS_PREFETCH=y 166CONFIG_CPU_HAS_PREFETCH=y
167# CONFIG_MIPS_MT is not set
136CONFIG_64BIT_PHYS_ADDR=y 168CONFIG_64BIT_PHYS_ADDR=y
137# CONFIG_CPU_ADVANCED is not set 169# CONFIG_CPU_ADVANCED is not set
138CONFIG_CPU_HAS_LLSC=y 170CONFIG_CPU_HAS_LLSC=y
139CONFIG_CPU_HAS_SYNC=y 171CONFIG_CPU_HAS_SYNC=y
172CONFIG_GENERIC_HARDIRQS=y
173CONFIG_GENERIC_IRQ_PROBE=y
174CONFIG_ARCH_FLATMEM_ENABLE=y
175CONFIG_SELECT_MEMORY_MODEL=y
176CONFIG_FLATMEM_MANUAL=y
177# CONFIG_DISCONTIGMEM_MANUAL is not set
178# CONFIG_SPARSEMEM_MANUAL is not set
179CONFIG_FLATMEM=y
180CONFIG_FLAT_NODE_MEM_MAP=y
181# CONFIG_SPARSEMEM_STATIC is not set
182CONFIG_PREEMPT_NONE=y
183# CONFIG_PREEMPT_VOLUNTARY is not set
140# CONFIG_PREEMPT is not set 184# CONFIG_PREEMPT is not set
141 185
142# 186#
@@ -145,7 +189,6 @@ CONFIG_CPU_HAS_SYNC=y
145CONFIG_HW_HAS_PCI=y 189CONFIG_HW_HAS_PCI=y
146CONFIG_PCI=y 190CONFIG_PCI=y
147CONFIG_PCI_LEGACY_PROC=y 191CONFIG_PCI_LEGACY_PROC=y
148CONFIG_PCI_NAMES=y
149CONFIG_MMU=y 192CONFIG_MMU=y
150 193
151# 194#
@@ -154,6 +197,8 @@ CONFIG_MMU=y
154CONFIG_PCCARD=m 197CONFIG_PCCARD=m
155# CONFIG_PCMCIA_DEBUG is not set 198# CONFIG_PCMCIA_DEBUG is not set
156CONFIG_PCMCIA=m 199CONFIG_PCMCIA=m
200CONFIG_PCMCIA_LOAD_CIS=y
201CONFIG_PCMCIA_IOCTL=y
157CONFIG_CARDBUS=y 202CONFIG_CARDBUS=y
158 203
159# 204#
@@ -176,6 +221,100 @@ CONFIG_PCMCIA_AU1X00=m
176CONFIG_BINFMT_ELF=y 221CONFIG_BINFMT_ELF=y
177# CONFIG_BINFMT_MISC is not set 222# CONFIG_BINFMT_MISC is not set
178CONFIG_TRAD_SIGNALS=y 223CONFIG_TRAD_SIGNALS=y
224# CONFIG_PM is not set
225
226#
227# Networking
228#
229CONFIG_NET=y
230
231#
232# Networking options
233#
234CONFIG_PACKET=y
235# CONFIG_PACKET_MMAP is not set
236CONFIG_UNIX=y
237CONFIG_XFRM=y
238CONFIG_XFRM_USER=m
239CONFIG_NET_KEY=y
240CONFIG_INET=y
241CONFIG_IP_MULTICAST=y
242# CONFIG_IP_ADVANCED_ROUTER is not set
243CONFIG_IP_FIB_HASH=y
244CONFIG_IP_PNP=y
245# CONFIG_IP_PNP_DHCP is not set
246CONFIG_IP_PNP_BOOTP=y
247# CONFIG_IP_PNP_RARP is not set
248# CONFIG_NET_IPIP is not set
249# CONFIG_NET_IPGRE is not set
250# CONFIG_IP_MROUTE is not set
251# CONFIG_ARPD is not set
252# CONFIG_SYN_COOKIES is not set
253# CONFIG_INET_AH is not set
254# CONFIG_INET_ESP is not set
255# CONFIG_INET_IPCOMP is not set
256CONFIG_INET_TUNNEL=m
257CONFIG_INET_DIAG=y
258CONFIG_INET_TCP_DIAG=y
259# CONFIG_TCP_CONG_ADVANCED is not set
260CONFIG_TCP_CONG_BIC=y
261
262#
263# IP: Virtual Server Configuration
264#
265# CONFIG_IP_VS is not set
266# CONFIG_IPV6 is not set
267CONFIG_NETFILTER=y
268# CONFIG_NETFILTER_DEBUG is not set
269CONFIG_NETFILTER_NETLINK=m
270CONFIG_NETFILTER_NETLINK_QUEUE=m
271CONFIG_NETFILTER_NETLINK_LOG=m
272
273#
274# IP: Netfilter Configuration
275#
276# CONFIG_IP_NF_CONNTRACK is not set
277CONFIG_IP_NF_PPTP=m
278# CONFIG_IP_NF_QUEUE is not set
279# CONFIG_IP_NF_IPTABLES is not set
280# CONFIG_IP_NF_ARPTABLES is not set
281
282#
283# DCCP Configuration (EXPERIMENTAL)
284#
285# CONFIG_IP_DCCP is not set
286
287#
288# SCTP Configuration (EXPERIMENTAL)
289#
290# CONFIG_IP_SCTP is not set
291# CONFIG_ATM is not set
292# CONFIG_BRIDGE is not set
293# CONFIG_VLAN_8021Q is not set
294# CONFIG_DECNET is not set
295# CONFIG_LLC2 is not set
296# CONFIG_IPX is not set
297# CONFIG_ATALK is not set
298# CONFIG_X25 is not set
299# CONFIG_LAPB is not set
300# CONFIG_NET_DIVERT is not set
301# CONFIG_ECONET is not set
302# CONFIG_WAN_ROUTER is not set
303# CONFIG_NET_SCHED is not set
304# CONFIG_NET_CLS_ROUTE is not set
305
306#
307# Network testing
308#
309# CONFIG_NET_PKTGEN is not set
310# CONFIG_HAMRADIO is not set
311# CONFIG_IRDA is not set
312# CONFIG_BT is not set
313CONFIG_IEEE80211=m
314# CONFIG_IEEE80211_DEBUG is not set
315CONFIG_IEEE80211_CRYPT_WEP=m
316CONFIG_IEEE80211_CRYPT_CCMP=m
317CONFIG_IEEE80211_CRYPT_TKIP=m
179 318
180# 319#
181# Device Drivers 320# Device Drivers
@@ -186,15 +325,20 @@ CONFIG_TRAD_SIGNALS=y
186# 325#
187CONFIG_STANDALONE=y 326CONFIG_STANDALONE=y
188CONFIG_PREVENT_FIRMWARE_BUILD=y 327CONFIG_PREVENT_FIRMWARE_BUILD=y
189# CONFIG_FW_LOADER is not set 328CONFIG_FW_LOADER=m
329
330#
331# Connector - unified userspace <-> kernelspace linker
332#
333CONFIG_CONNECTOR=m
190 334
191# 335#
192# Memory Technology Devices (MTD) 336# Memory Technology Devices (MTD)
193# 337#
194CONFIG_MTD=y 338CONFIG_MTD=y
195# CONFIG_MTD_DEBUG is not set 339# CONFIG_MTD_DEBUG is not set
196CONFIG_MTD_PARTITIONS=y
197# CONFIG_MTD_CONCAT is not set 340# CONFIG_MTD_CONCAT is not set
341CONFIG_MTD_PARTITIONS=y
198# CONFIG_MTD_REDBOOT_PARTS is not set 342# CONFIG_MTD_REDBOOT_PARTS is not set
199# CONFIG_MTD_CMDLINE_PARTS is not set 343# CONFIG_MTD_CMDLINE_PARTS is not set
200 344
@@ -238,9 +382,8 @@ CONFIG_MTD_CFI_UTIL=y
238# 382#
239# CONFIG_MTD_COMPLEX_MAPPINGS is not set 383# CONFIG_MTD_COMPLEX_MAPPINGS is not set
240# CONFIG_MTD_PHYSMAP is not set 384# CONFIG_MTD_PHYSMAP is not set
241CONFIG_MTD_DB1550=y 385CONFIG_MTD_ALCHEMY=y
242CONFIG_MTD_DB1550_BOOT=y 386# CONFIG_MTD_PLATRAM is not set
243CONFIG_MTD_DB1550_USER=y
244 387
245# 388#
246# Self-contained MTD device drivers 389# Self-contained MTD device drivers
@@ -281,7 +424,6 @@ CONFIG_MTD_NAND_AU1550=m
281# 424#
282# Block devices 425# Block devices
283# 426#
284# CONFIG_BLK_DEV_FD is not set
285# CONFIG_BLK_CPQ_DA is not set 427# CONFIG_BLK_CPQ_DA is not set
286# CONFIG_BLK_CPQ_CISS_DA is not set 428# CONFIG_BLK_CPQ_CISS_DA is not set
287# CONFIG_BLK_DEV_DAC960 is not set 429# CONFIG_BLK_DEV_DAC960 is not set
@@ -293,7 +435,6 @@ CONFIG_BLK_DEV_LOOP=y
293# CONFIG_BLK_DEV_SX8 is not set 435# CONFIG_BLK_DEV_SX8 is not set
294# CONFIG_BLK_DEV_RAM is not set 436# CONFIG_BLK_DEV_RAM is not set
295CONFIG_BLK_DEV_RAM_COUNT=16 437CONFIG_BLK_DEV_RAM_COUNT=16
296CONFIG_INITRAMFS_SOURCE=""
297# CONFIG_LBD is not set 438# CONFIG_LBD is not set
298CONFIG_CDROM_PKTCDVD=m 439CONFIG_CDROM_PKTCDVD=m
299CONFIG_CDROM_PKTCDVD_BUFFERS=8 440CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -350,6 +491,7 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
350# CONFIG_BLK_DEV_HPT366 is not set 491# CONFIG_BLK_DEV_HPT366 is not set
351# CONFIG_BLK_DEV_SC1200 is not set 492# CONFIG_BLK_DEV_SC1200 is not set
352# CONFIG_BLK_DEV_PIIX is not set 493# CONFIG_BLK_DEV_PIIX is not set
494# CONFIG_BLK_DEV_IT821X is not set
353# CONFIG_BLK_DEV_NS87415 is not set 495# CONFIG_BLK_DEV_NS87415 is not set
354# CONFIG_BLK_DEV_PDC202XX_OLD is not set 496# CONFIG_BLK_DEV_PDC202XX_OLD is not set
355# CONFIG_BLK_DEV_PDC202XX_NEW is not set 497# CONFIG_BLK_DEV_PDC202XX_NEW is not set
@@ -367,6 +509,7 @@ CONFIG_BLK_DEV_IDEDMA=y
367# 509#
368# SCSI device support 510# SCSI device support
369# 511#
512CONFIG_RAID_ATTRS=m
370# CONFIG_SCSI is not set 513# CONFIG_SCSI is not set
371 514
372# 515#
@@ -377,6 +520,7 @@ CONFIG_BLK_DEV_IDEDMA=y
377# 520#
378# Fusion MPT device support 521# Fusion MPT device support
379# 522#
523# CONFIG_FUSION is not set
380 524
381# 525#
382# IEEE 1394 (FireWire) support 526# IEEE 1394 (FireWire) support
@@ -389,94 +533,13 @@ CONFIG_BLK_DEV_IDEDMA=y
389# CONFIG_I2O is not set 533# CONFIG_I2O is not set
390 534
391# 535#
392# Networking support 536# Network device support
393#
394CONFIG_NET=y
395
396#
397# Networking options
398#
399CONFIG_PACKET=y
400# CONFIG_PACKET_MMAP is not set
401CONFIG_NETLINK_DEV=y
402CONFIG_UNIX=y
403CONFIG_NET_KEY=y
404CONFIG_INET=y
405CONFIG_IP_MULTICAST=y
406# CONFIG_IP_ADVANCED_ROUTER is not set
407CONFIG_IP_PNP=y
408# CONFIG_IP_PNP_DHCP is not set
409CONFIG_IP_PNP_BOOTP=y
410# CONFIG_IP_PNP_RARP is not set
411# CONFIG_NET_IPIP is not set
412# CONFIG_NET_IPGRE is not set
413# CONFIG_IP_MROUTE is not set
414# CONFIG_ARPD is not set
415# CONFIG_SYN_COOKIES is not set
416# CONFIG_INET_AH is not set
417# CONFIG_INET_ESP is not set
418# CONFIG_INET_IPCOMP is not set
419CONFIG_INET_TUNNEL=m
420CONFIG_IP_TCPDIAG=m
421# CONFIG_IP_TCPDIAG_IPV6 is not set
422
423#
424# IP: Virtual Server Configuration
425# 537#
426# CONFIG_IP_VS is not set
427# CONFIG_IPV6 is not set
428CONFIG_NETFILTER=y
429# CONFIG_NETFILTER_DEBUG is not set
430
431#
432# IP: Netfilter Configuration
433#
434# CONFIG_IP_NF_CONNTRACK is not set
435CONFIG_IP_NF_CONNTRACK_MARK=y
436# CONFIG_IP_NF_QUEUE is not set
437# CONFIG_IP_NF_IPTABLES is not set
438# CONFIG_IP_NF_ARPTABLES is not set
439CONFIG_XFRM=y
440CONFIG_XFRM_USER=m
441
442#
443# SCTP Configuration (EXPERIMENTAL)
444#
445# CONFIG_IP_SCTP is not set
446# CONFIG_ATM is not set
447# CONFIG_BRIDGE is not set
448# CONFIG_VLAN_8021Q is not set
449# CONFIG_DECNET is not set
450# CONFIG_LLC2 is not set
451# CONFIG_IPX is not set
452# CONFIG_ATALK is not set
453# CONFIG_X25 is not set
454# CONFIG_LAPB is not set
455# CONFIG_NET_DIVERT is not set
456# CONFIG_ECONET is not set
457# CONFIG_WAN_ROUTER is not set
458
459#
460# QoS and/or fair queueing
461#
462# CONFIG_NET_SCHED is not set
463# CONFIG_NET_CLS_ROUTE is not set
464
465#
466# Network testing
467#
468# CONFIG_NET_PKTGEN is not set
469# CONFIG_NETPOLL is not set
470# CONFIG_NET_POLL_CONTROLLER is not set
471# CONFIG_HAMRADIO is not set
472# CONFIG_IRDA is not set
473# CONFIG_BT is not set
474CONFIG_NETDEVICES=y 538CONFIG_NETDEVICES=y
475# CONFIG_DUMMY is not set 539# CONFIG_DUMMY is not set
476# CONFIG_BONDING is not set 540# CONFIG_BONDING is not set
477# CONFIG_EQUALIZER is not set 541# CONFIG_EQUALIZER is not set
478# CONFIG_TUN is not set 542# CONFIG_TUN is not set
479# CONFIG_ETHERTAP is not set
480 543
481# 544#
482# ARCnet devices 545# ARCnet devices
@@ -484,6 +547,21 @@ CONFIG_NETDEVICES=y
484# CONFIG_ARCNET is not set 547# CONFIG_ARCNET is not set
485 548
486# 549#
550# PHY device support
551#
552CONFIG_PHYLIB=m
553CONFIG_PHYCONTROL=y
554
555#
556# MII PHY device drivers
557#
558CONFIG_MARVELL_PHY=m
559CONFIG_DAVICOM_PHY=m
560CONFIG_QSEMI_PHY=m
561CONFIG_LXT_PHY=m
562CONFIG_CICADA_PHY=m
563
564#
487# Ethernet (10 or 100Mbit) 565# Ethernet (10 or 100Mbit)
488# 566#
489CONFIG_NET_ETHERNET=y 567CONFIG_NET_ETHERNET=y
@@ -510,12 +588,16 @@ CONFIG_MIPS_AU1X00_ENET=y
510# CONFIG_HAMACHI is not set 588# CONFIG_HAMACHI is not set
511# CONFIG_YELLOWFIN is not set 589# CONFIG_YELLOWFIN is not set
512# CONFIG_R8169 is not set 590# CONFIG_R8169 is not set
591# CONFIG_SIS190 is not set
592# CONFIG_SKGE is not set
513# CONFIG_SK98LIN is not set 593# CONFIG_SK98LIN is not set
514# CONFIG_TIGON3 is not set 594# CONFIG_TIGON3 is not set
595# CONFIG_BNX2 is not set
515 596
516# 597#
517# Ethernet (10000 Mbit) 598# Ethernet (10000 Mbit)
518# 599#
600# CONFIG_CHELSIO_T1 is not set
519# CONFIG_IXGB is not set 601# CONFIG_IXGB is not set
520# CONFIG_S2IO is not set 602# CONFIG_S2IO is not set
521 603
@@ -528,6 +610,8 @@ CONFIG_MIPS_AU1X00_ENET=y
528# Wireless LAN (non-hamradio) 610# Wireless LAN (non-hamradio)
529# 611#
530# CONFIG_NET_RADIO is not set 612# CONFIG_NET_RADIO is not set
613# CONFIG_IPW_DEBUG is not set
614CONFIG_IPW2200=m
531 615
532# 616#
533# PCMCIA network device support 617# PCMCIA network device support
@@ -559,6 +643,8 @@ CONFIG_PPPOE=m
559# CONFIG_SLIP is not set 643# CONFIG_SLIP is not set
560# CONFIG_SHAPER is not set 644# CONFIG_SHAPER is not set
561# CONFIG_NETCONSOLE is not set 645# CONFIG_NETCONSOLE is not set
646# CONFIG_NETPOLL is not set
647# CONFIG_NET_POLL_CONTROLLER is not set
562 648
563# 649#
564# ISDN subsystem 650# ISDN subsystem
@@ -588,19 +674,6 @@ CONFIG_INPUT_EVDEV=y
588# CONFIG_INPUT_EVBUG is not set 674# CONFIG_INPUT_EVBUG is not set
589 675
590# 676#
591# Input I/O drivers
592#
593# CONFIG_GAMEPORT is not set
594CONFIG_SOUND_GAMEPORT=y
595CONFIG_SERIO=y
596# CONFIG_SERIO_I8042 is not set
597CONFIG_SERIO_SERPORT=y
598# CONFIG_SERIO_CT82C710 is not set
599# CONFIG_SERIO_PCIPS2 is not set
600# CONFIG_SERIO_LIBPS2 is not set
601CONFIG_SERIO_RAW=m
602
603#
604# Input Device Drivers 677# Input Device Drivers
605# 678#
606# CONFIG_INPUT_KEYBOARD is not set 679# CONFIG_INPUT_KEYBOARD is not set
@@ -610,6 +683,17 @@ CONFIG_SERIO_RAW=m
610# CONFIG_INPUT_MISC is not set 683# CONFIG_INPUT_MISC is not set
611 684
612# 685#
686# Hardware I/O ports
687#
688CONFIG_SERIO=y
689# CONFIG_SERIO_I8042 is not set
690CONFIG_SERIO_SERPORT=y
691# CONFIG_SERIO_PCIPS2 is not set
692# CONFIG_SERIO_LIBPS2 is not set
693CONFIG_SERIO_RAW=m
694# CONFIG_GAMEPORT is not set
695
696#
613# Character devices 697# Character devices
614# 698#
615# CONFIG_VT is not set 699# CONFIG_VT is not set
@@ -629,6 +713,7 @@ CONFIG_SERIAL_AU1X00=y
629CONFIG_SERIAL_AU1X00_CONSOLE=y 713CONFIG_SERIAL_AU1X00_CONSOLE=y
630CONFIG_SERIAL_CORE=y 714CONFIG_SERIAL_CORE=y
631CONFIG_SERIAL_CORE_CONSOLE=y 715CONFIG_SERIAL_CORE_CONSOLE=y
716# CONFIG_SERIAL_JSM is not set
632CONFIG_UNIX98_PTYS=y 717CONFIG_UNIX98_PTYS=y
633CONFIG_LEGACY_PTYS=y 718CONFIG_LEGACY_PTYS=y
634CONFIG_LEGACY_PTY_COUNT=256 719CONFIG_LEGACY_PTY_COUNT=256
@@ -660,6 +745,11 @@ CONFIG_SYNCLINK_CS=m
660# CONFIG_RAW_DRIVER is not set 745# CONFIG_RAW_DRIVER is not set
661 746
662# 747#
748# TPM devices
749#
750# CONFIG_TCG_TPM is not set
751
752#
663# I2C support 753# I2C support
664# 754#
665# CONFIG_I2C is not set 755# CONFIG_I2C is not set
@@ -670,10 +760,20 @@ CONFIG_SYNCLINK_CS=m
670# CONFIG_W1 is not set 760# CONFIG_W1 is not set
671 761
672# 762#
763# Hardware Monitoring support
764#
765# CONFIG_HWMON is not set
766# CONFIG_HWMON_VID is not set
767
768#
673# Misc devices 769# Misc devices
674# 770#
675 771
676# 772#
773# Multimedia Capabilities Port drivers
774#
775
776#
677# Multimedia devices 777# Multimedia devices
678# 778#
679# CONFIG_VIDEO_DEV is not set 779# CONFIG_VIDEO_DEV is not set
@@ -687,7 +787,6 @@ CONFIG_SYNCLINK_CS=m
687# Graphics support 787# Graphics support
688# 788#
689# CONFIG_FB is not set 789# CONFIG_FB is not set
690# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
691 790
692# 791#
693# Sound 792# Sound
@@ -697,13 +796,9 @@ CONFIG_SYNCLINK_CS=m
697# 796#
698# USB support 797# USB support
699# 798#
700# CONFIG_USB is not set
701CONFIG_USB_ARCH_HAS_HCD=y 799CONFIG_USB_ARCH_HAS_HCD=y
702CONFIG_USB_ARCH_HAS_OHCI=y 800CONFIG_USB_ARCH_HAS_OHCI=y
703 801# CONFIG_USB is not set
704#
705# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
706#
707 802
708# 803#
709# USB Gadget Support 804# USB Gadget Support
@@ -721,12 +816,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y
721# CONFIG_INFINIBAND is not set 816# CONFIG_INFINIBAND is not set
722 817
723# 818#
819# SN Devices
820#
821
822#
724# File systems 823# File systems
725# 824#
726CONFIG_EXT2_FS=y 825CONFIG_EXT2_FS=y
727CONFIG_EXT2_FS_XATTR=y 826CONFIG_EXT2_FS_XATTR=y
728CONFIG_EXT2_FS_POSIX_ACL=y 827CONFIG_EXT2_FS_POSIX_ACL=y
729# CONFIG_EXT2_FS_SECURITY is not set 828# CONFIG_EXT2_FS_SECURITY is not set
829# CONFIG_EXT2_FS_XIP is not set
730CONFIG_EXT3_FS=y 830CONFIG_EXT3_FS=y
731CONFIG_EXT3_FS_XATTR=y 831CONFIG_EXT3_FS_XATTR=y
732CONFIG_EXT3_FS_POSIX_ACL=y 832CONFIG_EXT3_FS_POSIX_ACL=y
@@ -745,10 +845,12 @@ CONFIG_FS_POSIX_ACL=y
745# CONFIG_XFS_FS is not set 845# CONFIG_XFS_FS is not set
746# CONFIG_MINIX_FS is not set 846# CONFIG_MINIX_FS is not set
747# CONFIG_ROMFS_FS is not set 847# CONFIG_ROMFS_FS is not set
848CONFIG_INOTIFY=y
748# CONFIG_QUOTA is not set 849# CONFIG_QUOTA is not set
749CONFIG_DNOTIFY=y 850CONFIG_DNOTIFY=y
750CONFIG_AUTOFS_FS=m 851CONFIG_AUTOFS_FS=m
751CONFIG_AUTOFS4_FS=m 852CONFIG_AUTOFS4_FS=m
853CONFIG_FUSE_FS=m
752 854
753# 855#
754# CD-ROM/DVD Filesystems 856# CD-ROM/DVD Filesystems
@@ -769,13 +871,10 @@ CONFIG_AUTOFS4_FS=m
769CONFIG_PROC_FS=y 871CONFIG_PROC_FS=y
770CONFIG_PROC_KCORE=y 872CONFIG_PROC_KCORE=y
771CONFIG_SYSFS=y 873CONFIG_SYSFS=y
772# CONFIG_DEVFS_FS is not set
773CONFIG_DEVPTS_FS_XATTR=y
774CONFIG_DEVPTS_FS_SECURITY=y
775CONFIG_TMPFS=y 874CONFIG_TMPFS=y
776# CONFIG_TMPFS_XATTR is not set
777# CONFIG_HUGETLB_PAGE is not set 875# CONFIG_HUGETLB_PAGE is not set
778CONFIG_RAMFS=y 876CONFIG_RAMFS=y
877CONFIG_RELAYFS_FS=m
779 878
780# 879#
781# Miscellaneous filesystems 880# Miscellaneous filesystems
@@ -809,6 +908,7 @@ CONFIG_NFSD=m
809CONFIG_ROOT_NFS=y 908CONFIG_ROOT_NFS=y
810CONFIG_LOCKD=y 909CONFIG_LOCKD=y
811CONFIG_EXPORTFS=m 910CONFIG_EXPORTFS=m
911CONFIG_NFS_COMMON=y
812CONFIG_SUNRPC=y 912CONFIG_SUNRPC=y
813# CONFIG_RPCSEC_GSS_KRB5 is not set 913# CONFIG_RPCSEC_GSS_KRB5 is not set
814# CONFIG_RPCSEC_GSS_SPKM3 is not set 914# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -818,6 +918,7 @@ CONFIG_SMB_FS=m
818# CONFIG_NCP_FS is not set 918# CONFIG_NCP_FS is not set
819# CONFIG_CODA_FS is not set 919# CONFIG_CODA_FS is not set
820# CONFIG_AFS_FS is not set 920# CONFIG_AFS_FS is not set
921# CONFIG_9P_FS is not set
821 922
822# 923#
823# Partition Types 924# Partition Types
@@ -877,7 +978,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
877# 978#
878# Kernel hacking 979# Kernel hacking
879# 980#
981# CONFIG_PRINTK_TIME is not set
880# CONFIG_DEBUG_KERNEL is not set 982# CONFIG_DEBUG_KERNEL is not set
983CONFIG_LOG_BUF_SHIFT=14
881CONFIG_CROSSCOMPILE=y 984CONFIG_CROSSCOMPILE=y
882CONFIG_CMDLINE="" 985CONFIG_CMDLINE=""
883 986
@@ -893,26 +996,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
893# 996#
894CONFIG_CRYPTO=y 997CONFIG_CRYPTO=y
895CONFIG_CRYPTO_HMAC=y 998CONFIG_CRYPTO_HMAC=y
896CONFIG_CRYPTO_NULL=y 999CONFIG_CRYPTO_NULL=m
897# CONFIG_CRYPTO_MD4 is not set 1000CONFIG_CRYPTO_MD4=m
898# CONFIG_CRYPTO_MD5 is not set 1001CONFIG_CRYPTO_MD5=m
899# CONFIG_CRYPTO_SHA1 is not set 1002CONFIG_CRYPTO_SHA1=m
900# CONFIG_CRYPTO_SHA256 is not set 1003CONFIG_CRYPTO_SHA256=m
901CONFIG_CRYPTO_SHA512=y 1004CONFIG_CRYPTO_SHA512=m
902CONFIG_CRYPTO_WP512=m 1005CONFIG_CRYPTO_WP512=m
903# CONFIG_CRYPTO_DES is not set 1006CONFIG_CRYPTO_TGR192=m
904# CONFIG_CRYPTO_BLOWFISH is not set 1007CONFIG_CRYPTO_DES=m
905CONFIG_CRYPTO_TWOFISH=y 1008CONFIG_CRYPTO_BLOWFISH=m
906# CONFIG_CRYPTO_SERPENT is not set 1009CONFIG_CRYPTO_TWOFISH=m
1010CONFIG_CRYPTO_SERPENT=m
907CONFIG_CRYPTO_AES=m 1011CONFIG_CRYPTO_AES=m
908# CONFIG_CRYPTO_CAST5 is not set 1012CONFIG_CRYPTO_CAST5=m
909# CONFIG_CRYPTO_CAST6 is not set 1013CONFIG_CRYPTO_CAST6=m
910CONFIG_CRYPTO_TEA=m 1014CONFIG_CRYPTO_TEA=m
911# CONFIG_CRYPTO_ARC4 is not set 1015CONFIG_CRYPTO_ARC4=m
912CONFIG_CRYPTO_KHAZAD=m 1016CONFIG_CRYPTO_KHAZAD=m
913CONFIG_CRYPTO_ANUBIS=m 1017CONFIG_CRYPTO_ANUBIS=m
914CONFIG_CRYPTO_DEFLATE=y 1018CONFIG_CRYPTO_DEFLATE=m
915CONFIG_CRYPTO_MICHAEL_MIC=y 1019CONFIG_CRYPTO_MICHAEL_MIC=m
916CONFIG_CRYPTO_CRC32C=m 1020CONFIG_CRYPTO_CRC32C=m
917# CONFIG_CRYPTO_TEST is not set 1021# CONFIG_CRYPTO_TEST is not set
918 1022
@@ -924,9 +1028,8 @@ CONFIG_CRYPTO_CRC32C=m
924# Library routines 1028# Library routines
925# 1029#
926CONFIG_CRC_CCITT=m 1030CONFIG_CRC_CCITT=m
1031CONFIG_CRC16=m
927CONFIG_CRC32=y 1032CONFIG_CRC32=y
928CONFIG_LIBCRC32C=m 1033CONFIG_LIBCRC32C=m
929CONFIG_ZLIB_INFLATE=y 1034CONFIG_ZLIB_INFLATE=m
930CONFIG_ZLIB_DEFLATE=y 1035CONFIG_ZLIB_DEFLATE=m
931CONFIG_GENERIC_HARDIRQS=y
932CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/ddb5476_defconfig b/arch/mips/configs/ddb5476_defconfig
index 70addc73f699..b260e51eb517 100644
--- a/arch/mips/configs/ddb5476_defconfig
+++ b/arch/mips/configs/ddb5476_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:02 2005 4# Thu Oct 20 22:25:42 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -50,41 +53,69 @@ CONFIG_CC_ALIGN_JUMPS=0
50# 53#
51# Machine selection 54# Machine selection
52# 55#
53# CONFIG_MACH_JAZZ is not set 56# CONFIG_MIPS_MTX1 is not set
54# CONFIG_MACH_VR41XX is not set 57# CONFIG_MIPS_BOSPORUS is not set
55# CONFIG_TOSHIBA_JMR3927 is not set 58# CONFIG_MIPS_PB1000 is not set
59# CONFIG_MIPS_PB1100 is not set
60# CONFIG_MIPS_PB1500 is not set
61# CONFIG_MIPS_PB1550 is not set
62# CONFIG_MIPS_PB1200 is not set
63# CONFIG_MIPS_DB1000 is not set
64# CONFIG_MIPS_DB1100 is not set
65# CONFIG_MIPS_DB1500 is not set
66# CONFIG_MIPS_DB1550 is not set
67# CONFIG_MIPS_DB1200 is not set
68# CONFIG_MIPS_MIRAGE is not set
56# CONFIG_MIPS_COBALT is not set 69# CONFIG_MIPS_COBALT is not set
57# CONFIG_MACH_DECSTATION is not set 70# CONFIG_MACH_DECSTATION is not set
58# CONFIG_MIPS_EV64120 is not set 71# CONFIG_MIPS_EV64120 is not set
59# CONFIG_MIPS_EV96100 is not set 72# CONFIG_MIPS_EV96100 is not set
60# CONFIG_MIPS_IVR is not set 73# CONFIG_MIPS_IVR is not set
61# CONFIG_LASAT is not set
62# CONFIG_MIPS_ITE8172 is not set 74# CONFIG_MIPS_ITE8172 is not set
75# CONFIG_MACH_JAZZ is not set
76# CONFIG_LASAT is not set
63# CONFIG_MIPS_ATLAS is not set 77# CONFIG_MIPS_ATLAS is not set
64# CONFIG_MIPS_MALTA is not set 78# CONFIG_MIPS_MALTA is not set
65# CONFIG_MIPS_SEAD is not set 79# CONFIG_MIPS_SEAD is not set
80# CONFIG_MIPS_SIM is not set
81# CONFIG_MOMENCO_JAGUAR_ATX is not set
66# CONFIG_MOMENCO_OCELOT is not set 82# CONFIG_MOMENCO_OCELOT is not set
67# CONFIG_MOMENCO_OCELOT_G is not set
68# CONFIG_MOMENCO_OCELOT_C is not set
69# CONFIG_MOMENCO_OCELOT_3 is not set 83# CONFIG_MOMENCO_OCELOT_3 is not set
70# CONFIG_MOMENCO_JAGUAR_ATX is not set 84# CONFIG_MOMENCO_OCELOT_C is not set
71# CONFIG_PMC_YOSEMITE is not set 85# CONFIG_MOMENCO_OCELOT_G is not set
86# CONFIG_MIPS_XXS1500 is not set
87# CONFIG_PNX8550_V2PCI is not set
88# CONFIG_PNX8550_JBS is not set
72# CONFIG_DDB5074 is not set 89# CONFIG_DDB5074 is not set
73CONFIG_DDB5476=y 90CONFIG_DDB5476=y
74# CONFIG_DDB5477 is not set 91# CONFIG_DDB5477 is not set
75# CONFIG_NEC_OSPREY is not set 92# CONFIG_MACH_VR41XX is not set
93# CONFIG_PMC_YOSEMITE is not set
94# CONFIG_QEMU is not set
76# CONFIG_SGI_IP22 is not set 95# CONFIG_SGI_IP22 is not set
77# CONFIG_SOC_AU1X00 is not set 96# CONFIG_SGI_IP27 is not set
78# CONFIG_SIBYTE_SB1xxx_SOC is not set 97# CONFIG_SGI_IP32 is not set
98# CONFIG_SIBYTE_BIGSUR is not set
99# CONFIG_SIBYTE_SWARM is not set
100# CONFIG_SIBYTE_SENTOSA is not set
101# CONFIG_SIBYTE_RHONE is not set
102# CONFIG_SIBYTE_CARMEL is not set
103# CONFIG_SIBYTE_PTSWARM is not set
104# CONFIG_SIBYTE_LITTLESUR is not set
105# CONFIG_SIBYTE_CRHINE is not set
106# CONFIG_SIBYTE_CRHONE is not set
79# CONFIG_SNI_RM200_PCI is not set 107# CONFIG_SNI_RM200_PCI is not set
108# CONFIG_TOSHIBA_JMR3927 is not set
80# CONFIG_TOSHIBA_RBTX4927 is not set 109# CONFIG_TOSHIBA_RBTX4927 is not set
110# CONFIG_TOSHIBA_RBTX4938 is not set
81CONFIG_RWSEM_GENERIC_SPINLOCK=y 111CONFIG_RWSEM_GENERIC_SPINLOCK=y
82CONFIG_GENERIC_CALIBRATE_DELAY=y 112CONFIG_GENERIC_CALIBRATE_DELAY=y
83CONFIG_HAVE_DEC_LOCK=y
84CONFIG_DMA_NONCOHERENT=y 113CONFIG_DMA_NONCOHERENT=y
85CONFIG_DMA_NEED_PCI_MAP_STATE=y 114CONFIG_DMA_NEED_PCI_MAP_STATE=y
86CONFIG_I8259=y 115CONFIG_I8259=y
116# CONFIG_CPU_BIG_ENDIAN is not set
87CONFIG_CPU_LITTLE_ENDIAN=y 117CONFIG_CPU_LITTLE_ENDIAN=y
118CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
88CONFIG_IRQ_CPU=y 119CONFIG_IRQ_CPU=y
89CONFIG_DDB5XXX_COMMON=y 120CONFIG_DDB5XXX_COMMON=y
90CONFIG_MIPS_L1_CACHE_SHIFT=5 121CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -93,8 +124,10 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y
93# 124#
94# CPU selection 125# CPU selection
95# 126#
96# CONFIG_CPU_MIPS32 is not set 127# CONFIG_CPU_MIPS32_R1 is not set
97# CONFIG_CPU_MIPS64 is not set 128# CONFIG_CPU_MIPS32_R2 is not set
129# CONFIG_CPU_MIPS64_R1 is not set
130# CONFIG_CPU_MIPS64_R2 is not set
98# CONFIG_CPU_R3000 is not set 131# CONFIG_CPU_R3000 is not set
99# CONFIG_CPU_TX39XX is not set 132# CONFIG_CPU_TX39XX is not set
100# CONFIG_CPU_VR41XX is not set 133# CONFIG_CPU_VR41XX is not set
@@ -110,14 +143,38 @@ CONFIG_CPU_R5432=y
110# CONFIG_CPU_RM7000 is not set 143# CONFIG_CPU_RM7000 is not set
111# CONFIG_CPU_RM9000 is not set 144# CONFIG_CPU_RM9000 is not set
112# CONFIG_CPU_SB1 is not set 145# CONFIG_CPU_SB1 is not set
146CONFIG_SYS_HAS_CPU_R5432=y
147CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
148CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
149CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
150CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
151
152#
153# Kernel type
154#
155CONFIG_32BIT=y
156# CONFIG_64BIT is not set
113CONFIG_PAGE_SIZE_4KB=y 157CONFIG_PAGE_SIZE_4KB=y
114# CONFIG_PAGE_SIZE_8KB is not set 158# CONFIG_PAGE_SIZE_8KB is not set
115# CONFIG_PAGE_SIZE_16KB is not set 159# CONFIG_PAGE_SIZE_16KB is not set
116# CONFIG_PAGE_SIZE_64KB is not set 160# CONFIG_PAGE_SIZE_64KB is not set
161# CONFIG_MIPS_MT is not set
117# CONFIG_CPU_ADVANCED is not set 162# CONFIG_CPU_ADVANCED is not set
118CONFIG_CPU_HAS_LLSC=y 163CONFIG_CPU_HAS_LLSC=y
119CONFIG_CPU_HAS_LLDSCD=y 164CONFIG_CPU_HAS_LLDSCD=y
120CONFIG_CPU_HAS_SYNC=y 165CONFIG_CPU_HAS_SYNC=y
166CONFIG_GENERIC_HARDIRQS=y
167CONFIG_GENERIC_IRQ_PROBE=y
168CONFIG_ARCH_FLATMEM_ENABLE=y
169CONFIG_SELECT_MEMORY_MODEL=y
170CONFIG_FLATMEM_MANUAL=y
171# CONFIG_DISCONTIGMEM_MANUAL is not set
172# CONFIG_SPARSEMEM_MANUAL is not set
173CONFIG_FLATMEM=y
174CONFIG_FLAT_NODE_MEM_MAP=y
175# CONFIG_SPARSEMEM_STATIC is not set
176CONFIG_PREEMPT_NONE=y
177# CONFIG_PREEMPT_VOLUNTARY is not set
121# CONFIG_PREEMPT is not set 178# CONFIG_PREEMPT is not set
122 179
123# 180#
@@ -126,7 +183,6 @@ CONFIG_CPU_HAS_SYNC=y
126CONFIG_HW_HAS_PCI=y 183CONFIG_HW_HAS_PCI=y
127CONFIG_PCI=y 184CONFIG_PCI=y
128CONFIG_PCI_LEGACY_PROC=y 185CONFIG_PCI_LEGACY_PROC=y
129CONFIG_PCI_NAMES=y
130CONFIG_ISA=y 186CONFIG_ISA=y
131CONFIG_MMU=y 187CONFIG_MMU=y
132 188
@@ -136,11 +192,6 @@ CONFIG_MMU=y
136# CONFIG_PCCARD is not set 192# CONFIG_PCCARD is not set
137 193
138# 194#
139# PC-card bridges
140#
141CONFIG_PCMCIA_PROBE=y
142
143#
144# PCI Hotplug Support 195# PCI Hotplug Support
145# 196#
146# CONFIG_HOTPLUG_PCI is not set 197# CONFIG_HOTPLUG_PCI is not set
@@ -153,6 +204,80 @@ CONFIG_BINFMT_ELF=y
153CONFIG_TRAD_SIGNALS=y 204CONFIG_TRAD_SIGNALS=y
154 205
155# 206#
207# Networking
208#
209CONFIG_NET=y
210
211#
212# Networking options
213#
214CONFIG_PACKET=y
215# CONFIG_PACKET_MMAP is not set
216CONFIG_UNIX=y
217CONFIG_XFRM=y
218CONFIG_XFRM_USER=y
219CONFIG_NET_KEY=y
220CONFIG_INET=y
221# CONFIG_IP_MULTICAST is not set
222# CONFIG_IP_ADVANCED_ROUTER is not set
223CONFIG_IP_FIB_HASH=y
224CONFIG_IP_PNP=y
225# CONFIG_IP_PNP_DHCP is not set
226CONFIG_IP_PNP_BOOTP=y
227# CONFIG_IP_PNP_RARP is not set
228# CONFIG_NET_IPIP is not set
229# CONFIG_NET_IPGRE is not set
230# CONFIG_ARPD is not set
231# CONFIG_SYN_COOKIES is not set
232# CONFIG_INET_AH is not set
233# CONFIG_INET_ESP is not set
234# CONFIG_INET_IPCOMP is not set
235CONFIG_INET_TUNNEL=y
236CONFIG_INET_DIAG=y
237CONFIG_INET_TCP_DIAG=y
238# CONFIG_TCP_CONG_ADVANCED is not set
239CONFIG_TCP_CONG_BIC=y
240# CONFIG_IPV6 is not set
241# CONFIG_NETFILTER is not set
242
243#
244# DCCP Configuration (EXPERIMENTAL)
245#
246# CONFIG_IP_DCCP is not set
247
248#
249# SCTP Configuration (EXPERIMENTAL)
250#
251# CONFIG_IP_SCTP is not set
252# CONFIG_ATM is not set
253# CONFIG_BRIDGE is not set
254# CONFIG_VLAN_8021Q is not set
255# CONFIG_DECNET is not set
256# CONFIG_LLC2 is not set
257# CONFIG_IPX is not set
258# CONFIG_ATALK is not set
259# CONFIG_X25 is not set
260# CONFIG_LAPB is not set
261# CONFIG_NET_DIVERT is not set
262# CONFIG_ECONET is not set
263# CONFIG_WAN_ROUTER is not set
264# CONFIG_NET_SCHED is not set
265# CONFIG_NET_CLS_ROUTE is not set
266
267#
268# Network testing
269#
270# CONFIG_NET_PKTGEN is not set
271# CONFIG_HAMRADIO is not set
272# CONFIG_IRDA is not set
273# CONFIG_BT is not set
274CONFIG_IEEE80211=y
275# CONFIG_IEEE80211_DEBUG is not set
276CONFIG_IEEE80211_CRYPT_WEP=y
277CONFIG_IEEE80211_CRYPT_CCMP=y
278CONFIG_IEEE80211_CRYPT_TKIP=y
279
280#
156# Device Drivers 281# Device Drivers
157# 282#
158 283
@@ -161,7 +286,12 @@ CONFIG_TRAD_SIGNALS=y
161# 286#
162CONFIG_STANDALONE=y 287CONFIG_STANDALONE=y
163CONFIG_PREVENT_FIRMWARE_BUILD=y 288CONFIG_PREVENT_FIRMWARE_BUILD=y
164# CONFIG_FW_LOADER is not set 289CONFIG_FW_LOADER=y
290
291#
292# Connector - unified userspace <-> kernelspace linker
293#
294CONFIG_CONNECTOR=y
165 295
166# 296#
167# Memory Technology Devices (MTD) 297# Memory Technology Devices (MTD)
@@ -181,8 +311,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
181# 311#
182# Block devices 312# Block devices
183# 313#
184# CONFIG_BLK_DEV_FD is not set
185# CONFIG_BLK_DEV_XD is not set
186# CONFIG_BLK_CPQ_DA is not set 314# CONFIG_BLK_CPQ_DA is not set
187# CONFIG_BLK_CPQ_CISS_DA is not set 315# CONFIG_BLK_CPQ_CISS_DA is not set
188# CONFIG_BLK_DEV_DAC960 is not set 316# CONFIG_BLK_DEV_DAC960 is not set
@@ -193,7 +321,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
193# CONFIG_BLK_DEV_SX8 is not set 321# CONFIG_BLK_DEV_SX8 is not set
194# CONFIG_BLK_DEV_RAM is not set 322# CONFIG_BLK_DEV_RAM is not set
195CONFIG_BLK_DEV_RAM_COUNT=16 323CONFIG_BLK_DEV_RAM_COUNT=16
196CONFIG_INITRAMFS_SOURCE=""
197# CONFIG_LBD is not set 324# CONFIG_LBD is not set
198CONFIG_CDROM_PKTCDVD=y 325CONFIG_CDROM_PKTCDVD=y
199CONFIG_CDROM_PKTCDVD_BUFFERS=8 326CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -239,6 +366,7 @@ CONFIG_IDE_GENERIC=y
239# 366#
240# SCSI device support 367# SCSI device support
241# 368#
369CONFIG_RAID_ATTRS=y
242# CONFIG_SCSI is not set 370# CONFIG_SCSI is not set
243 371
244# 372#
@@ -254,6 +382,7 @@ CONFIG_IDE_GENERIC=y
254# 382#
255# Fusion MPT device support 383# Fusion MPT device support
256# 384#
385# CONFIG_FUSION is not set
257 386
258# 387#
259# IEEE 1394 (FireWire) support 388# IEEE 1394 (FireWire) support
@@ -266,78 +395,13 @@ CONFIG_IDE_GENERIC=y
266# CONFIG_I2O is not set 395# CONFIG_I2O is not set
267 396
268# 397#
269# Networking support 398# Network device support
270#
271CONFIG_NET=y
272
273#
274# Networking options
275#
276CONFIG_PACKET=y
277# CONFIG_PACKET_MMAP is not set
278CONFIG_NETLINK_DEV=y
279CONFIG_UNIX=y
280CONFIG_NET_KEY=y
281CONFIG_INET=y
282# CONFIG_IP_MULTICAST is not set
283# CONFIG_IP_ADVANCED_ROUTER is not set
284CONFIG_IP_PNP=y
285# CONFIG_IP_PNP_DHCP is not set
286CONFIG_IP_PNP_BOOTP=y
287# CONFIG_IP_PNP_RARP is not set
288# CONFIG_NET_IPIP is not set
289# CONFIG_NET_IPGRE is not set
290# CONFIG_ARPD is not set
291# CONFIG_SYN_COOKIES is not set
292# CONFIG_INET_AH is not set
293# CONFIG_INET_ESP is not set
294# CONFIG_INET_IPCOMP is not set
295CONFIG_INET_TUNNEL=y
296CONFIG_IP_TCPDIAG=y
297# CONFIG_IP_TCPDIAG_IPV6 is not set
298# CONFIG_IPV6 is not set
299# CONFIG_NETFILTER is not set
300CONFIG_XFRM=y
301CONFIG_XFRM_USER=y
302
303#
304# SCTP Configuration (EXPERIMENTAL)
305# 399#
306# CONFIG_IP_SCTP is not set
307# CONFIG_ATM is not set
308# CONFIG_BRIDGE is not set
309# CONFIG_VLAN_8021Q is not set
310# CONFIG_DECNET is not set
311# CONFIG_LLC2 is not set
312# CONFIG_IPX is not set
313# CONFIG_ATALK is not set
314# CONFIG_X25 is not set
315# CONFIG_LAPB is not set
316# CONFIG_NET_DIVERT is not set
317# CONFIG_ECONET is not set
318# CONFIG_WAN_ROUTER is not set
319
320#
321# QoS and/or fair queueing
322#
323# CONFIG_NET_SCHED is not set
324# CONFIG_NET_CLS_ROUTE is not set
325
326#
327# Network testing
328#
329# CONFIG_NET_PKTGEN is not set
330# CONFIG_NETPOLL is not set
331# CONFIG_NET_POLL_CONTROLLER is not set
332# CONFIG_HAMRADIO is not set
333# CONFIG_IRDA is not set
334# CONFIG_BT is not set
335CONFIG_NETDEVICES=y 400CONFIG_NETDEVICES=y
336# CONFIG_DUMMY is not set 401# CONFIG_DUMMY is not set
337# CONFIG_BONDING is not set 402# CONFIG_BONDING is not set
338# CONFIG_EQUALIZER is not set 403# CONFIG_EQUALIZER is not set
339# CONFIG_TUN is not set 404# CONFIG_TUN is not set
340# CONFIG_ETHERTAP is not set
341 405
342# 406#
343# ARCnet devices 407# ARCnet devices
@@ -345,6 +409,21 @@ CONFIG_NETDEVICES=y
345# CONFIG_ARCNET is not set 409# CONFIG_ARCNET is not set
346 410
347# 411#
412# PHY device support
413#
414CONFIG_PHYLIB=y
415CONFIG_PHYCONTROL=y
416
417#
418# MII PHY device drivers
419#
420CONFIG_MARVELL_PHY=y
421CONFIG_DAVICOM_PHY=y
422CONFIG_QSEMI_PHY=y
423CONFIG_LXT_PHY=y
424CONFIG_CICADA_PHY=y
425
426#
348# Ethernet (10 or 100Mbit) 427# Ethernet (10 or 100Mbit)
349# 428#
350CONFIG_NET_ETHERNET=y 429CONFIG_NET_ETHERNET=y
@@ -352,7 +431,6 @@ CONFIG_NET_ETHERNET=y
352# CONFIG_HAPPYMEAL is not set 431# CONFIG_HAPPYMEAL is not set
353# CONFIG_SUNGEM is not set 432# CONFIG_SUNGEM is not set
354# CONFIG_NET_VENDOR_3COM is not set 433# CONFIG_NET_VENDOR_3COM is not set
355# CONFIG_LANCE is not set
356# CONFIG_NET_VENDOR_SMC is not set 434# CONFIG_NET_VENDOR_SMC is not set
357# CONFIG_NET_VENDOR_RACAL is not set 435# CONFIG_NET_VENDOR_RACAL is not set
358 436
@@ -377,12 +455,16 @@ CONFIG_NET_ETHERNET=y
377# CONFIG_HAMACHI is not set 455# CONFIG_HAMACHI is not set
378# CONFIG_YELLOWFIN is not set 456# CONFIG_YELLOWFIN is not set
379# CONFIG_R8169 is not set 457# CONFIG_R8169 is not set
458# CONFIG_SIS190 is not set
459# CONFIG_SKGE is not set
380# CONFIG_SK98LIN is not set 460# CONFIG_SK98LIN is not set
381# CONFIG_TIGON3 is not set 461# CONFIG_TIGON3 is not set
462# CONFIG_BNX2 is not set
382 463
383# 464#
384# Ethernet (10000 Mbit) 465# Ethernet (10000 Mbit)
385# 466#
467# CONFIG_CHELSIO_T1 is not set
386# CONFIG_IXGB is not set 468# CONFIG_IXGB is not set
387# CONFIG_S2IO is not set 469# CONFIG_S2IO is not set
388 470
@@ -395,6 +477,8 @@ CONFIG_NET_ETHERNET=y
395# Wireless LAN (non-hamradio) 477# Wireless LAN (non-hamradio)
396# 478#
397# CONFIG_NET_RADIO is not set 479# CONFIG_NET_RADIO is not set
480# CONFIG_IPW_DEBUG is not set
481CONFIG_IPW2200=y
398 482
399# 483#
400# Wan interfaces 484# Wan interfaces
@@ -406,6 +490,8 @@ CONFIG_NET_ETHERNET=y
406# CONFIG_SLIP is not set 490# CONFIG_SLIP is not set
407# CONFIG_SHAPER is not set 491# CONFIG_SHAPER is not set
408# CONFIG_NETCONSOLE is not set 492# CONFIG_NETCONSOLE is not set
493# CONFIG_NETPOLL is not set
494# CONFIG_NET_POLL_CONTROLLER is not set
409 495
410# 496#
411# ISDN subsystem 497# ISDN subsystem
@@ -435,19 +521,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
435# CONFIG_INPUT_EVBUG is not set 521# CONFIG_INPUT_EVBUG is not set
436 522
437# 523#
438# Input I/O drivers
439#
440# CONFIG_GAMEPORT is not set
441CONFIG_SOUND_GAMEPORT=y
442CONFIG_SERIO=y
443# CONFIG_SERIO_I8042 is not set
444CONFIG_SERIO_SERPORT=y
445# CONFIG_SERIO_CT82C710 is not set
446# CONFIG_SERIO_PCIPS2 is not set
447# CONFIG_SERIO_LIBPS2 is not set
448CONFIG_SERIO_RAW=y
449
450#
451# Input Device Drivers 524# Input Device Drivers
452# 525#
453# CONFIG_INPUT_KEYBOARD is not set 526# CONFIG_INPUT_KEYBOARD is not set
@@ -457,6 +530,17 @@ CONFIG_SERIO_RAW=y
457# CONFIG_INPUT_MISC is not set 530# CONFIG_INPUT_MISC is not set
458 531
459# 532#
533# Hardware I/O ports
534#
535CONFIG_SERIO=y
536# CONFIG_SERIO_I8042 is not set
537CONFIG_SERIO_SERPORT=y
538# CONFIG_SERIO_PCIPS2 is not set
539# CONFIG_SERIO_LIBPS2 is not set
540CONFIG_SERIO_RAW=y
541# CONFIG_GAMEPORT is not set
542
543#
460# Character devices 544# Character devices
461# 545#
462CONFIG_VT=y 546CONFIG_VT=y
@@ -477,6 +561,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
477# 561#
478CONFIG_SERIAL_CORE=y 562CONFIG_SERIAL_CORE=y
479CONFIG_SERIAL_CORE_CONSOLE=y 563CONFIG_SERIAL_CORE_CONSOLE=y
564# CONFIG_SERIAL_JSM is not set
480CONFIG_UNIX98_PTYS=y 565CONFIG_UNIX98_PTYS=y
481CONFIG_LEGACY_PTYS=y 566CONFIG_LEGACY_PTYS=y
482CONFIG_LEGACY_PTY_COUNT=256 567CONFIG_LEGACY_PTY_COUNT=256
@@ -503,6 +588,11 @@ CONFIG_LEGACY_PTY_COUNT=256
503# CONFIG_RAW_DRIVER is not set 588# CONFIG_RAW_DRIVER is not set
504 589
505# 590#
591# TPM devices
592#
593# CONFIG_TCG_TPM is not set
594
595#
506# I2C support 596# I2C support
507# 597#
508# CONFIG_I2C is not set 598# CONFIG_I2C is not set
@@ -513,10 +603,20 @@ CONFIG_LEGACY_PTY_COUNT=256
513# CONFIG_W1 is not set 603# CONFIG_W1 is not set
514 604
515# 605#
606# Hardware Monitoring support
607#
608# CONFIG_HWMON is not set
609# CONFIG_HWMON_VID is not set
610
611#
516# Misc devices 612# Misc devices
517# 613#
518 614
519# 615#
616# Multimedia Capabilities Port drivers
617#
618
619#
520# Multimedia devices 620# Multimedia devices
521# 621#
522# CONFIG_VIDEO_DEV is not set 622# CONFIG_VIDEO_DEV is not set
@@ -530,6 +630,11 @@ CONFIG_LEGACY_PTY_COUNT=256
530# Graphics support 630# Graphics support
531# 631#
532CONFIG_FB=y 632CONFIG_FB=y
633# CONFIG_FB_CFB_FILLRECT is not set
634# CONFIG_FB_CFB_COPYAREA is not set
635# CONFIG_FB_CFB_IMAGEBLIT is not set
636# CONFIG_FB_SOFT_CURSOR is not set
637# CONFIG_FB_MACMODES is not set
533# CONFIG_FB_MODE_HELPERS is not set 638# CONFIG_FB_MODE_HELPERS is not set
534# CONFIG_FB_TILEBLITTING is not set 639# CONFIG_FB_TILEBLITTING is not set
535# CONFIG_FB_CIRRUS is not set 640# CONFIG_FB_CIRRUS is not set
@@ -537,6 +642,7 @@ CONFIG_FB=y
537# CONFIG_FB_CYBER2000 is not set 642# CONFIG_FB_CYBER2000 is not set
538# CONFIG_FB_ASILIANT is not set 643# CONFIG_FB_ASILIANT is not set
539# CONFIG_FB_IMSTT is not set 644# CONFIG_FB_IMSTT is not set
645# CONFIG_FB_NVIDIA is not set
540# CONFIG_FB_RIVA is not set 646# CONFIG_FB_RIVA is not set
541# CONFIG_FB_MATROX is not set 647# CONFIG_FB_MATROX is not set
542# CONFIG_FB_RADEON_OLD is not set 648# CONFIG_FB_RADEON_OLD is not set
@@ -549,8 +655,11 @@ CONFIG_FB=y
549# CONFIG_FB_KYRO is not set 655# CONFIG_FB_KYRO is not set
550# CONFIG_FB_3DFX is not set 656# CONFIG_FB_3DFX is not set
551# CONFIG_FB_VOODOO1 is not set 657# CONFIG_FB_VOODOO1 is not set
658# CONFIG_FB_SMIVGX is not set
659# CONFIG_FB_CYBLA is not set
552# CONFIG_FB_TRIDENT is not set 660# CONFIG_FB_TRIDENT is not set
553# CONFIG_FB_E1356 is not set 661# CONFIG_FB_E1356 is not set
662# CONFIG_FB_S1D13XXX is not set
554# CONFIG_FB_VIRTUAL is not set 663# CONFIG_FB_VIRTUAL is not set
555 664
556# 665#
@@ -575,13 +684,9 @@ CONFIG_DUMMY_CONSOLE=y
575# 684#
576# USB support 685# USB support
577# 686#
578# CONFIG_USB is not set
579CONFIG_USB_ARCH_HAS_HCD=y 687CONFIG_USB_ARCH_HAS_HCD=y
580CONFIG_USB_ARCH_HAS_OHCI=y 688CONFIG_USB_ARCH_HAS_OHCI=y
581 689# CONFIG_USB is not set
582#
583# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
584#
585 690
586# 691#
587# USB Gadget Support 692# USB Gadget Support
@@ -599,21 +704,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y
599# CONFIG_INFINIBAND is not set 704# CONFIG_INFINIBAND is not set
600 705
601# 706#
707# SN Devices
708#
709
710#
602# File systems 711# File systems
603# 712#
604CONFIG_EXT2_FS=y 713CONFIG_EXT2_FS=y
605# CONFIG_EXT2_FS_XATTR is not set 714# CONFIG_EXT2_FS_XATTR is not set
715# CONFIG_EXT2_FS_XIP is not set
606# CONFIG_EXT3_FS is not set 716# CONFIG_EXT3_FS is not set
607# CONFIG_JBD is not set 717# CONFIG_JBD is not set
608# CONFIG_REISERFS_FS is not set 718# CONFIG_REISERFS_FS is not set
609# CONFIG_JFS_FS is not set 719# CONFIG_JFS_FS is not set
720# CONFIG_FS_POSIX_ACL is not set
610# CONFIG_XFS_FS is not set 721# CONFIG_XFS_FS is not set
611# CONFIG_MINIX_FS is not set 722# CONFIG_MINIX_FS is not set
612# CONFIG_ROMFS_FS is not set 723# CONFIG_ROMFS_FS is not set
724CONFIG_INOTIFY=y
613# CONFIG_QUOTA is not set 725# CONFIG_QUOTA is not set
614CONFIG_DNOTIFY=y 726CONFIG_DNOTIFY=y
615# CONFIG_AUTOFS_FS is not set 727# CONFIG_AUTOFS_FS is not set
616# CONFIG_AUTOFS4_FS is not set 728# CONFIG_AUTOFS4_FS is not set
729CONFIG_FUSE_FS=y
617 730
618# 731#
619# CD-ROM/DVD Filesystems 732# CD-ROM/DVD Filesystems
@@ -634,12 +747,10 @@ CONFIG_DNOTIFY=y
634CONFIG_PROC_FS=y 747CONFIG_PROC_FS=y
635CONFIG_PROC_KCORE=y 748CONFIG_PROC_KCORE=y
636CONFIG_SYSFS=y 749CONFIG_SYSFS=y
637# CONFIG_DEVFS_FS is not set
638CONFIG_DEVPTS_FS_XATTR=y
639CONFIG_DEVPTS_FS_SECURITY=y
640# CONFIG_TMPFS is not set 750# CONFIG_TMPFS is not set
641# CONFIG_HUGETLB_PAGE is not set 751# CONFIG_HUGETLB_PAGE is not set
642CONFIG_RAMFS=y 752CONFIG_RAMFS=y
753CONFIG_RELAYFS_FS=y
643 754
644# 755#
645# Miscellaneous filesystems 756# Miscellaneous filesystems
@@ -668,7 +779,7 @@ CONFIG_NFS_FS=y
668# CONFIG_NFSD is not set 779# CONFIG_NFSD is not set
669CONFIG_ROOT_NFS=y 780CONFIG_ROOT_NFS=y
670CONFIG_LOCKD=y 781CONFIG_LOCKD=y
671# CONFIG_EXPORTFS is not set 782CONFIG_NFS_COMMON=y
672CONFIG_SUNRPC=y 783CONFIG_SUNRPC=y
673# CONFIG_RPCSEC_GSS_KRB5 is not set 784# CONFIG_RPCSEC_GSS_KRB5 is not set
674# CONFIG_RPCSEC_GSS_SPKM3 is not set 785# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -677,6 +788,7 @@ CONFIG_SUNRPC=y
677# CONFIG_NCP_FS is not set 788# CONFIG_NCP_FS is not set
678# CONFIG_CODA_FS is not set 789# CONFIG_CODA_FS is not set
679# CONFIG_AFS_FS is not set 790# CONFIG_AFS_FS is not set
791# CONFIG_9P_FS is not set
680 792
681# 793#
682# Partition Types 794# Partition Types
@@ -697,7 +809,9 @@ CONFIG_MSDOS_PARTITION=y
697# 809#
698# Kernel hacking 810# Kernel hacking
699# 811#
812# CONFIG_PRINTK_TIME is not set
700# CONFIG_DEBUG_KERNEL is not set 813# CONFIG_DEBUG_KERNEL is not set
814CONFIG_LOG_BUF_SHIFT=14
701CONFIG_CROSSCOMPILE=y 815CONFIG_CROSSCOMPILE=y
702CONFIG_CMDLINE="ip=any" 816CONFIG_CMDLINE="ip=any"
703 817
@@ -711,7 +825,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
711# 825#
712# Cryptographic options 826# Cryptographic options
713# 827#
714# CONFIG_CRYPTO is not set 828CONFIG_CRYPTO=y
829CONFIG_CRYPTO_HMAC=y
830CONFIG_CRYPTO_NULL=y
831CONFIG_CRYPTO_MD4=y
832CONFIG_CRYPTO_MD5=y
833CONFIG_CRYPTO_SHA1=y
834CONFIG_CRYPTO_SHA256=y
835CONFIG_CRYPTO_SHA512=y
836CONFIG_CRYPTO_WP512=y
837CONFIG_CRYPTO_TGR192=y
838CONFIG_CRYPTO_DES=y
839CONFIG_CRYPTO_BLOWFISH=y
840CONFIG_CRYPTO_TWOFISH=y
841CONFIG_CRYPTO_SERPENT=y
842CONFIG_CRYPTO_AES=y
843CONFIG_CRYPTO_CAST5=y
844CONFIG_CRYPTO_CAST6=y
845CONFIG_CRYPTO_TEA=y
846CONFIG_CRYPTO_ARC4=y
847CONFIG_CRYPTO_KHAZAD=y
848CONFIG_CRYPTO_ANUBIS=y
849CONFIG_CRYPTO_DEFLATE=y
850CONFIG_CRYPTO_MICHAEL_MIC=y
851CONFIG_CRYPTO_CRC32C=y
852# CONFIG_CRYPTO_TEST is not set
715 853
716# 854#
717# Hardware crypto devices 855# Hardware crypto devices
@@ -721,7 +859,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
721# Library routines 859# Library routines
722# 860#
723# CONFIG_CRC_CCITT is not set 861# CONFIG_CRC_CCITT is not set
724# CONFIG_CRC32 is not set 862CONFIG_CRC16=y
725# CONFIG_LIBCRC32C is not set 863CONFIG_CRC32=y
726CONFIG_GENERIC_HARDIRQS=y 864CONFIG_LIBCRC32C=y
727CONFIG_GENERIC_IRQ_PROBE=y 865CONFIG_ZLIB_INFLATE=y
866CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig
index 60292808b384..c2a01df3c8df 100644
--- a/arch/mips/configs/ddb5477_defconfig
+++ b/arch/mips/configs/ddb5477_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:02 2005 4# Thu Oct 20 22:25:45 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -50,42 +53,70 @@ CONFIG_CC_ALIGN_JUMPS=0
50# 53#
51# Machine selection 54# Machine selection
52# 55#
53# CONFIG_MACH_JAZZ is not set 56# CONFIG_MIPS_MTX1 is not set
54# CONFIG_MACH_VR41XX is not set 57# CONFIG_MIPS_BOSPORUS is not set
55# CONFIG_TOSHIBA_JMR3927 is not set 58# CONFIG_MIPS_PB1000 is not set
59# CONFIG_MIPS_PB1100 is not set
60# CONFIG_MIPS_PB1500 is not set
61# CONFIG_MIPS_PB1550 is not set
62# CONFIG_MIPS_PB1200 is not set
63# CONFIG_MIPS_DB1000 is not set
64# CONFIG_MIPS_DB1100 is not set
65# CONFIG_MIPS_DB1500 is not set
66# CONFIG_MIPS_DB1550 is not set
67# CONFIG_MIPS_DB1200 is not set
68# CONFIG_MIPS_MIRAGE is not set
56# CONFIG_MIPS_COBALT is not set 69# CONFIG_MIPS_COBALT is not set
57# CONFIG_MACH_DECSTATION is not set 70# CONFIG_MACH_DECSTATION is not set
58# CONFIG_MIPS_EV64120 is not set 71# CONFIG_MIPS_EV64120 is not set
59# CONFIG_MIPS_EV96100 is not set 72# CONFIG_MIPS_EV96100 is not set
60# CONFIG_MIPS_IVR is not set 73# CONFIG_MIPS_IVR is not set
61# CONFIG_LASAT is not set
62# CONFIG_MIPS_ITE8172 is not set 74# CONFIG_MIPS_ITE8172 is not set
75# CONFIG_MACH_JAZZ is not set
76# CONFIG_LASAT is not set
63# CONFIG_MIPS_ATLAS is not set 77# CONFIG_MIPS_ATLAS is not set
64# CONFIG_MIPS_MALTA is not set 78# CONFIG_MIPS_MALTA is not set
65# CONFIG_MIPS_SEAD is not set 79# CONFIG_MIPS_SEAD is not set
80# CONFIG_MIPS_SIM is not set
81# CONFIG_MOMENCO_JAGUAR_ATX is not set
66# CONFIG_MOMENCO_OCELOT is not set 82# CONFIG_MOMENCO_OCELOT is not set
67# CONFIG_MOMENCO_OCELOT_G is not set
68# CONFIG_MOMENCO_OCELOT_C is not set
69# CONFIG_MOMENCO_OCELOT_3 is not set 83# CONFIG_MOMENCO_OCELOT_3 is not set
70# CONFIG_MOMENCO_JAGUAR_ATX is not set 84# CONFIG_MOMENCO_OCELOT_C is not set
71# CONFIG_PMC_YOSEMITE is not set 85# CONFIG_MOMENCO_OCELOT_G is not set
86# CONFIG_MIPS_XXS1500 is not set
87# CONFIG_PNX8550_V2PCI is not set
88# CONFIG_PNX8550_JBS is not set
72# CONFIG_DDB5074 is not set 89# CONFIG_DDB5074 is not set
73# CONFIG_DDB5476 is not set 90# CONFIG_DDB5476 is not set
74CONFIG_DDB5477=y 91CONFIG_DDB5477=y
75CONFIG_DDB5477_BUS_FREQUENCY=0 92# CONFIG_MACH_VR41XX is not set
76# CONFIG_NEC_OSPREY is not set 93# CONFIG_PMC_YOSEMITE is not set
94# CONFIG_QEMU is not set
77# CONFIG_SGI_IP22 is not set 95# CONFIG_SGI_IP22 is not set
78# CONFIG_SOC_AU1X00 is not set 96# CONFIG_SGI_IP27 is not set
79# CONFIG_SIBYTE_SB1xxx_SOC is not set 97# CONFIG_SGI_IP32 is not set
98# CONFIG_SIBYTE_BIGSUR is not set
99# CONFIG_SIBYTE_SWARM is not set
100# CONFIG_SIBYTE_SENTOSA is not set
101# CONFIG_SIBYTE_RHONE is not set
102# CONFIG_SIBYTE_CARMEL is not set
103# CONFIG_SIBYTE_PTSWARM is not set
104# CONFIG_SIBYTE_LITTLESUR is not set
105# CONFIG_SIBYTE_CRHINE is not set
106# CONFIG_SIBYTE_CRHONE is not set
80# CONFIG_SNI_RM200_PCI is not set 107# CONFIG_SNI_RM200_PCI is not set
108# CONFIG_TOSHIBA_JMR3927 is not set
81# CONFIG_TOSHIBA_RBTX4927 is not set 109# CONFIG_TOSHIBA_RBTX4927 is not set
110# CONFIG_TOSHIBA_RBTX4938 is not set
111CONFIG_DDB5477_BUS_FREQUENCY=0
82CONFIG_RWSEM_GENERIC_SPINLOCK=y 112CONFIG_RWSEM_GENERIC_SPINLOCK=y
83CONFIG_GENERIC_CALIBRATE_DELAY=y 113CONFIG_GENERIC_CALIBRATE_DELAY=y
84CONFIG_HAVE_DEC_LOCK=y
85CONFIG_DMA_NONCOHERENT=y 114CONFIG_DMA_NONCOHERENT=y
86CONFIG_DMA_NEED_PCI_MAP_STATE=y 115CONFIG_DMA_NEED_PCI_MAP_STATE=y
87CONFIG_I8259=y 116CONFIG_I8259=y
117# CONFIG_CPU_BIG_ENDIAN is not set
88CONFIG_CPU_LITTLE_ENDIAN=y 118CONFIG_CPU_LITTLE_ENDIAN=y
119CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
89CONFIG_IRQ_CPU=y 120CONFIG_IRQ_CPU=y
90CONFIG_DDB5XXX_COMMON=y 121CONFIG_DDB5XXX_COMMON=y
91CONFIG_MIPS_L1_CACHE_SHIFT=5 122CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -93,8 +124,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
93# 124#
94# CPU selection 125# CPU selection
95# 126#
96# CONFIG_CPU_MIPS32 is not set 127# CONFIG_CPU_MIPS32_R1 is not set
97# CONFIG_CPU_MIPS64 is not set 128# CONFIG_CPU_MIPS32_R2 is not set
129# CONFIG_CPU_MIPS64_R1 is not set
130# CONFIG_CPU_MIPS64_R2 is not set
98# CONFIG_CPU_R3000 is not set 131# CONFIG_CPU_R3000 is not set
99# CONFIG_CPU_TX39XX is not set 132# CONFIG_CPU_TX39XX is not set
100# CONFIG_CPU_VR41XX is not set 133# CONFIG_CPU_VR41XX is not set
@@ -110,14 +143,38 @@ CONFIG_CPU_R5432=y
110# CONFIG_CPU_RM7000 is not set 143# CONFIG_CPU_RM7000 is not set
111# CONFIG_CPU_RM9000 is not set 144# CONFIG_CPU_RM9000 is not set
112# CONFIG_CPU_SB1 is not set 145# CONFIG_CPU_SB1 is not set
146CONFIG_SYS_HAS_CPU_R5432=y
147CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
148CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
149CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
150CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
151
152#
153# Kernel type
154#
155CONFIG_32BIT=y
156# CONFIG_64BIT is not set
113CONFIG_PAGE_SIZE_4KB=y 157CONFIG_PAGE_SIZE_4KB=y
114# CONFIG_PAGE_SIZE_8KB is not set 158# CONFIG_PAGE_SIZE_8KB is not set
115# CONFIG_PAGE_SIZE_16KB is not set 159# CONFIG_PAGE_SIZE_16KB is not set
116# CONFIG_PAGE_SIZE_64KB is not set 160# CONFIG_PAGE_SIZE_64KB is not set
161# CONFIG_MIPS_MT is not set
117# CONFIG_CPU_ADVANCED is not set 162# CONFIG_CPU_ADVANCED is not set
118CONFIG_CPU_HAS_LLSC=y 163CONFIG_CPU_HAS_LLSC=y
119CONFIG_CPU_HAS_LLDSCD=y 164CONFIG_CPU_HAS_LLDSCD=y
120CONFIG_CPU_HAS_SYNC=y 165CONFIG_CPU_HAS_SYNC=y
166CONFIG_GENERIC_HARDIRQS=y
167CONFIG_GENERIC_IRQ_PROBE=y
168CONFIG_ARCH_FLATMEM_ENABLE=y
169CONFIG_SELECT_MEMORY_MODEL=y
170CONFIG_FLATMEM_MANUAL=y
171# CONFIG_DISCONTIGMEM_MANUAL is not set
172# CONFIG_SPARSEMEM_MANUAL is not set
173CONFIG_FLATMEM=y
174CONFIG_FLAT_NODE_MEM_MAP=y
175# CONFIG_SPARSEMEM_STATIC is not set
176CONFIG_PREEMPT_NONE=y
177# CONFIG_PREEMPT_VOLUNTARY is not set
121# CONFIG_PREEMPT is not set 178# CONFIG_PREEMPT is not set
122 179
123# 180#
@@ -126,7 +183,6 @@ CONFIG_CPU_HAS_SYNC=y
126CONFIG_HW_HAS_PCI=y 183CONFIG_HW_HAS_PCI=y
127CONFIG_PCI=y 184CONFIG_PCI=y
128CONFIG_PCI_LEGACY_PROC=y 185CONFIG_PCI_LEGACY_PROC=y
129CONFIG_PCI_NAMES=y
130CONFIG_MMU=y 186CONFIG_MMU=y
131 187
132# 188#
@@ -135,10 +191,6 @@ CONFIG_MMU=y
135# CONFIG_PCCARD is not set 191# CONFIG_PCCARD is not set
136 192
137# 193#
138# PC-card bridges
139#
140
141#
142# PCI Hotplug Support 194# PCI Hotplug Support
143# 195#
144# CONFIG_HOTPLUG_PCI is not set 196# CONFIG_HOTPLUG_PCI is not set
@@ -151,6 +203,80 @@ CONFIG_BINFMT_ELF=y
151CONFIG_TRAD_SIGNALS=y 203CONFIG_TRAD_SIGNALS=y
152 204
153# 205#
206# Networking
207#
208CONFIG_NET=y
209
210#
211# Networking options
212#
213CONFIG_PACKET=y
214# CONFIG_PACKET_MMAP is not set
215CONFIG_UNIX=y
216CONFIG_XFRM=y
217CONFIG_XFRM_USER=y
218CONFIG_NET_KEY=y
219CONFIG_INET=y
220# CONFIG_IP_MULTICAST is not set
221# CONFIG_IP_ADVANCED_ROUTER is not set
222CONFIG_IP_FIB_HASH=y
223CONFIG_IP_PNP=y
224# CONFIG_IP_PNP_DHCP is not set
225CONFIG_IP_PNP_BOOTP=y
226# CONFIG_IP_PNP_RARP is not set
227# CONFIG_NET_IPIP is not set
228# CONFIG_NET_IPGRE is not set
229# CONFIG_ARPD is not set
230# CONFIG_SYN_COOKIES is not set
231# CONFIG_INET_AH is not set
232# CONFIG_INET_ESP is not set
233# CONFIG_INET_IPCOMP is not set
234CONFIG_INET_TUNNEL=y
235CONFIG_INET_DIAG=y
236CONFIG_INET_TCP_DIAG=y
237# CONFIG_TCP_CONG_ADVANCED is not set
238CONFIG_TCP_CONG_BIC=y
239# CONFIG_IPV6 is not set
240# CONFIG_NETFILTER is not set
241
242#
243# DCCP Configuration (EXPERIMENTAL)
244#
245# CONFIG_IP_DCCP is not set
246
247#
248# SCTP Configuration (EXPERIMENTAL)
249#
250# CONFIG_IP_SCTP is not set
251# CONFIG_ATM is not set
252# CONFIG_BRIDGE is not set
253# CONFIG_VLAN_8021Q is not set
254# CONFIG_DECNET is not set
255# CONFIG_LLC2 is not set
256# CONFIG_IPX is not set
257# CONFIG_ATALK is not set
258# CONFIG_X25 is not set
259# CONFIG_LAPB is not set
260# CONFIG_NET_DIVERT is not set
261# CONFIG_ECONET is not set
262# CONFIG_WAN_ROUTER is not set
263# CONFIG_NET_SCHED is not set
264# CONFIG_NET_CLS_ROUTE is not set
265
266#
267# Network testing
268#
269# CONFIG_NET_PKTGEN is not set
270# CONFIG_HAMRADIO is not set
271# CONFIG_IRDA is not set
272# CONFIG_BT is not set
273CONFIG_IEEE80211=y
274# CONFIG_IEEE80211_DEBUG is not set
275CONFIG_IEEE80211_CRYPT_WEP=y
276CONFIG_IEEE80211_CRYPT_CCMP=y
277CONFIG_IEEE80211_CRYPT_TKIP=y
278
279#
154# Device Drivers 280# Device Drivers
155# 281#
156 282
@@ -159,7 +285,12 @@ CONFIG_TRAD_SIGNALS=y
159# 285#
160CONFIG_STANDALONE=y 286CONFIG_STANDALONE=y
161CONFIG_PREVENT_FIRMWARE_BUILD=y 287CONFIG_PREVENT_FIRMWARE_BUILD=y
162# CONFIG_FW_LOADER is not set 288CONFIG_FW_LOADER=y
289
290#
291# Connector - unified userspace <-> kernelspace linker
292#
293CONFIG_CONNECTOR=y
163 294
164# 295#
165# Memory Technology Devices (MTD) 296# Memory Technology Devices (MTD)
@@ -178,7 +309,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
178# 309#
179# Block devices 310# Block devices
180# 311#
181# CONFIG_BLK_DEV_FD is not set
182# CONFIG_BLK_CPQ_DA is not set 312# CONFIG_BLK_CPQ_DA is not set
183# CONFIG_BLK_CPQ_CISS_DA is not set 313# CONFIG_BLK_CPQ_CISS_DA is not set
184# CONFIG_BLK_DEV_DAC960 is not set 314# CONFIG_BLK_DEV_DAC960 is not set
@@ -189,7 +319,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
189# CONFIG_BLK_DEV_SX8 is not set 319# CONFIG_BLK_DEV_SX8 is not set
190# CONFIG_BLK_DEV_RAM is not set 320# CONFIG_BLK_DEV_RAM is not set
191CONFIG_BLK_DEV_RAM_COUNT=16 321CONFIG_BLK_DEV_RAM_COUNT=16
192CONFIG_INITRAMFS_SOURCE=""
193# CONFIG_LBD is not set 322# CONFIG_LBD is not set
194CONFIG_CDROM_PKTCDVD=y 323CONFIG_CDROM_PKTCDVD=y
195CONFIG_CDROM_PKTCDVD_BUFFERS=8 324CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -212,6 +341,7 @@ CONFIG_ATA_OVER_ETH=y
212# 341#
213# SCSI device support 342# SCSI device support
214# 343#
344CONFIG_RAID_ATTRS=y
215# CONFIG_SCSI is not set 345# CONFIG_SCSI is not set
216 346
217# 347#
@@ -222,6 +352,7 @@ CONFIG_ATA_OVER_ETH=y
222# 352#
223# Fusion MPT device support 353# Fusion MPT device support
224# 354#
355# CONFIG_FUSION is not set
225 356
226# 357#
227# IEEE 1394 (FireWire) support 358# IEEE 1394 (FireWire) support
@@ -234,78 +365,13 @@ CONFIG_ATA_OVER_ETH=y
234# CONFIG_I2O is not set 365# CONFIG_I2O is not set
235 366
236# 367#
237# Networking support 368# Network device support
238#
239CONFIG_NET=y
240
241#
242# Networking options
243#
244CONFIG_PACKET=y
245# CONFIG_PACKET_MMAP is not set
246CONFIG_NETLINK_DEV=y
247CONFIG_UNIX=y
248CONFIG_NET_KEY=y
249CONFIG_INET=y
250# CONFIG_IP_MULTICAST is not set
251# CONFIG_IP_ADVANCED_ROUTER is not set
252CONFIG_IP_PNP=y
253# CONFIG_IP_PNP_DHCP is not set
254CONFIG_IP_PNP_BOOTP=y
255# CONFIG_IP_PNP_RARP is not set
256# CONFIG_NET_IPIP is not set
257# CONFIG_NET_IPGRE is not set
258# CONFIG_ARPD is not set
259# CONFIG_SYN_COOKIES is not set
260# CONFIG_INET_AH is not set
261# CONFIG_INET_ESP is not set
262# CONFIG_INET_IPCOMP is not set
263CONFIG_INET_TUNNEL=y
264CONFIG_IP_TCPDIAG=y
265# CONFIG_IP_TCPDIAG_IPV6 is not set
266# CONFIG_IPV6 is not set
267# CONFIG_NETFILTER is not set
268CONFIG_XFRM=y
269CONFIG_XFRM_USER=y
270
271#
272# SCTP Configuration (EXPERIMENTAL)
273#
274# CONFIG_IP_SCTP is not set
275# CONFIG_ATM is not set
276# CONFIG_BRIDGE is not set
277# CONFIG_VLAN_8021Q is not set
278# CONFIG_DECNET is not set
279# CONFIG_LLC2 is not set
280# CONFIG_IPX is not set
281# CONFIG_ATALK is not set
282# CONFIG_X25 is not set
283# CONFIG_LAPB is not set
284# CONFIG_NET_DIVERT is not set
285# CONFIG_ECONET is not set
286# CONFIG_WAN_ROUTER is not set
287
288#
289# QoS and/or fair queueing
290# 369#
291# CONFIG_NET_SCHED is not set
292# CONFIG_NET_CLS_ROUTE is not set
293
294#
295# Network testing
296#
297# CONFIG_NET_PKTGEN is not set
298# CONFIG_NETPOLL is not set
299# CONFIG_NET_POLL_CONTROLLER is not set
300# CONFIG_HAMRADIO is not set
301# CONFIG_IRDA is not set
302# CONFIG_BT is not set
303CONFIG_NETDEVICES=y 370CONFIG_NETDEVICES=y
304# CONFIG_DUMMY is not set 371# CONFIG_DUMMY is not set
305# CONFIG_BONDING is not set 372# CONFIG_BONDING is not set
306# CONFIG_EQUALIZER is not set 373# CONFIG_EQUALIZER is not set
307# CONFIG_TUN is not set 374# CONFIG_TUN is not set
308# CONFIG_ETHERTAP is not set
309 375
310# 376#
311# ARCnet devices 377# ARCnet devices
@@ -313,6 +379,21 @@ CONFIG_NETDEVICES=y
313# CONFIG_ARCNET is not set 379# CONFIG_ARCNET is not set
314 380
315# 381#
382# PHY device support
383#
384CONFIG_PHYLIB=y
385CONFIG_PHYCONTROL=y
386
387#
388# MII PHY device drivers
389#
390CONFIG_MARVELL_PHY=y
391CONFIG_DAVICOM_PHY=y
392CONFIG_QSEMI_PHY=y
393CONFIG_LXT_PHY=y
394CONFIG_CICADA_PHY=y
395
396#
316# Ethernet (10 or 100Mbit) 397# Ethernet (10 or 100Mbit)
317# 398#
318CONFIG_NET_ETHERNET=y 399CONFIG_NET_ETHERNET=y
@@ -357,13 +438,17 @@ CONFIG_PCNET32=y
357# CONFIG_HAMACHI is not set 438# CONFIG_HAMACHI is not set
358# CONFIG_YELLOWFIN is not set 439# CONFIG_YELLOWFIN is not set
359# CONFIG_R8169 is not set 440# CONFIG_R8169 is not set
441# CONFIG_SIS190 is not set
442# CONFIG_SKGE is not set
360# CONFIG_SK98LIN is not set 443# CONFIG_SK98LIN is not set
361# CONFIG_VIA_VELOCITY is not set 444# CONFIG_VIA_VELOCITY is not set
362# CONFIG_TIGON3 is not set 445# CONFIG_TIGON3 is not set
446# CONFIG_BNX2 is not set
363 447
364# 448#
365# Ethernet (10000 Mbit) 449# Ethernet (10000 Mbit)
366# 450#
451# CONFIG_CHELSIO_T1 is not set
367# CONFIG_IXGB is not set 452# CONFIG_IXGB is not set
368# CONFIG_S2IO is not set 453# CONFIG_S2IO is not set
369 454
@@ -376,6 +461,8 @@ CONFIG_PCNET32=y
376# Wireless LAN (non-hamradio) 461# Wireless LAN (non-hamradio)
377# 462#
378# CONFIG_NET_RADIO is not set 463# CONFIG_NET_RADIO is not set
464# CONFIG_IPW_DEBUG is not set
465CONFIG_IPW2200=y
379 466
380# 467#
381# Wan interfaces 468# Wan interfaces
@@ -387,6 +474,8 @@ CONFIG_PCNET32=y
387# CONFIG_SLIP is not set 474# CONFIG_SLIP is not set
388# CONFIG_SHAPER is not set 475# CONFIG_SHAPER is not set
389# CONFIG_NETCONSOLE is not set 476# CONFIG_NETCONSOLE is not set
477# CONFIG_NETPOLL is not set
478# CONFIG_NET_POLL_CONTROLLER is not set
390 479
391# 480#
392# ISDN subsystem 481# ISDN subsystem
@@ -416,19 +505,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
416# CONFIG_INPUT_EVBUG is not set 505# CONFIG_INPUT_EVBUG is not set
417 506
418# 507#
419# Input I/O drivers
420#
421# CONFIG_GAMEPORT is not set
422CONFIG_SOUND_GAMEPORT=y
423CONFIG_SERIO=y
424# CONFIG_SERIO_I8042 is not set
425CONFIG_SERIO_SERPORT=y
426# CONFIG_SERIO_CT82C710 is not set
427# CONFIG_SERIO_PCIPS2 is not set
428# CONFIG_SERIO_LIBPS2 is not set
429CONFIG_SERIO_RAW=y
430
431#
432# Input Device Drivers 508# Input Device Drivers
433# 509#
434# CONFIG_INPUT_KEYBOARD is not set 510# CONFIG_INPUT_KEYBOARD is not set
@@ -438,6 +514,17 @@ CONFIG_SERIO_RAW=y
438# CONFIG_INPUT_MISC is not set 514# CONFIG_INPUT_MISC is not set
439 515
440# 516#
517# Hardware I/O ports
518#
519CONFIG_SERIO=y
520# CONFIG_SERIO_I8042 is not set
521CONFIG_SERIO_SERPORT=y
522# CONFIG_SERIO_PCIPS2 is not set
523# CONFIG_SERIO_LIBPS2 is not set
524CONFIG_SERIO_RAW=y
525# CONFIG_GAMEPORT is not set
526
527#
441# Character devices 528# Character devices
442# 529#
443CONFIG_VT=y 530CONFIG_VT=y
@@ -458,6 +545,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
458# 545#
459CONFIG_SERIAL_CORE=y 546CONFIG_SERIAL_CORE=y
460CONFIG_SERIAL_CORE_CONSOLE=y 547CONFIG_SERIAL_CORE_CONSOLE=y
548# CONFIG_SERIAL_JSM is not set
461CONFIG_UNIX98_PTYS=y 549CONFIG_UNIX98_PTYS=y
462CONFIG_LEGACY_PTYS=y 550CONFIG_LEGACY_PTYS=y
463CONFIG_LEGACY_PTY_COUNT=256 551CONFIG_LEGACY_PTY_COUNT=256
@@ -484,6 +572,11 @@ CONFIG_LEGACY_PTY_COUNT=256
484# CONFIG_RAW_DRIVER is not set 572# CONFIG_RAW_DRIVER is not set
485 573
486# 574#
575# TPM devices
576#
577# CONFIG_TCG_TPM is not set
578
579#
487# I2C support 580# I2C support
488# 581#
489# CONFIG_I2C is not set 582# CONFIG_I2C is not set
@@ -494,10 +587,20 @@ CONFIG_LEGACY_PTY_COUNT=256
494# CONFIG_W1 is not set 587# CONFIG_W1 is not set
495 588
496# 589#
590# Hardware Monitoring support
591#
592# CONFIG_HWMON is not set
593# CONFIG_HWMON_VID is not set
594
595#
497# Misc devices 596# Misc devices
498# 597#
499 598
500# 599#
600# Multimedia Capabilities Port drivers
601#
602
603#
501# Multimedia devices 604# Multimedia devices
502# 605#
503# CONFIG_VIDEO_DEV is not set 606# CONFIG_VIDEO_DEV is not set
@@ -517,7 +620,6 @@ CONFIG_LEGACY_PTY_COUNT=256
517# 620#
518# CONFIG_VGA_CONSOLE is not set 621# CONFIG_VGA_CONSOLE is not set
519CONFIG_DUMMY_CONSOLE=y 622CONFIG_DUMMY_CONSOLE=y
520# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
521 623
522# 624#
523# Sound 625# Sound
@@ -527,13 +629,9 @@ CONFIG_DUMMY_CONSOLE=y
527# 629#
528# USB support 630# USB support
529# 631#
530# CONFIG_USB is not set
531CONFIG_USB_ARCH_HAS_HCD=y 632CONFIG_USB_ARCH_HAS_HCD=y
532CONFIG_USB_ARCH_HAS_OHCI=y 633CONFIG_USB_ARCH_HAS_OHCI=y
533 634# CONFIG_USB is not set
534#
535# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
536#
537 635
538# 636#
539# USB Gadget Support 637# USB Gadget Support
@@ -551,21 +649,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y
551# CONFIG_INFINIBAND is not set 649# CONFIG_INFINIBAND is not set
552 650
553# 651#
652# SN Devices
653#
654
655#
554# File systems 656# File systems
555# 657#
556CONFIG_EXT2_FS=y 658CONFIG_EXT2_FS=y
557# CONFIG_EXT2_FS_XATTR is not set 659# CONFIG_EXT2_FS_XATTR is not set
660# CONFIG_EXT2_FS_XIP is not set
558# CONFIG_EXT3_FS is not set 661# CONFIG_EXT3_FS is not set
559# CONFIG_JBD is not set 662# CONFIG_JBD is not set
560# CONFIG_REISERFS_FS is not set 663# CONFIG_REISERFS_FS is not set
561# CONFIG_JFS_FS is not set 664# CONFIG_JFS_FS is not set
665# CONFIG_FS_POSIX_ACL is not set
562# CONFIG_XFS_FS is not set 666# CONFIG_XFS_FS is not set
563# CONFIG_MINIX_FS is not set 667# CONFIG_MINIX_FS is not set
564# CONFIG_ROMFS_FS is not set 668# CONFIG_ROMFS_FS is not set
669CONFIG_INOTIFY=y
565# CONFIG_QUOTA is not set 670# CONFIG_QUOTA is not set
566CONFIG_DNOTIFY=y 671CONFIG_DNOTIFY=y
567CONFIG_AUTOFS_FS=y 672CONFIG_AUTOFS_FS=y
568CONFIG_AUTOFS4_FS=y 673CONFIG_AUTOFS4_FS=y
674CONFIG_FUSE_FS=y
569 675
570# 676#
571# CD-ROM/DVD Filesystems 677# CD-ROM/DVD Filesystems
@@ -586,12 +692,10 @@ CONFIG_AUTOFS4_FS=y
586CONFIG_PROC_FS=y 692CONFIG_PROC_FS=y
587CONFIG_PROC_KCORE=y 693CONFIG_PROC_KCORE=y
588CONFIG_SYSFS=y 694CONFIG_SYSFS=y
589# CONFIG_DEVFS_FS is not set
590CONFIG_DEVPTS_FS_XATTR=y
591CONFIG_DEVPTS_FS_SECURITY=y
592# CONFIG_TMPFS is not set 695# CONFIG_TMPFS is not set
593# CONFIG_HUGETLB_PAGE is not set 696# CONFIG_HUGETLB_PAGE is not set
594CONFIG_RAMFS=y 697CONFIG_RAMFS=y
698CONFIG_RELAYFS_FS=y
595 699
596# 700#
597# Miscellaneous filesystems 701# Miscellaneous filesystems
@@ -623,6 +727,7 @@ CONFIG_NFSD=y
623CONFIG_ROOT_NFS=y 727CONFIG_ROOT_NFS=y
624CONFIG_LOCKD=y 728CONFIG_LOCKD=y
625CONFIG_EXPORTFS=y 729CONFIG_EXPORTFS=y
730CONFIG_NFS_COMMON=y
626CONFIG_SUNRPC=y 731CONFIG_SUNRPC=y
627# CONFIG_RPCSEC_GSS_KRB5 is not set 732# CONFIG_RPCSEC_GSS_KRB5 is not set
628# CONFIG_RPCSEC_GSS_SPKM3 is not set 733# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -631,6 +736,7 @@ CONFIG_SUNRPC=y
631# CONFIG_NCP_FS is not set 736# CONFIG_NCP_FS is not set
632# CONFIG_CODA_FS is not set 737# CONFIG_CODA_FS is not set
633# CONFIG_AFS_FS is not set 738# CONFIG_AFS_FS is not set
739# CONFIG_9P_FS is not set
634 740
635# 741#
636# Partition Types 742# Partition Types
@@ -651,7 +757,9 @@ CONFIG_MSDOS_PARTITION=y
651# 757#
652# Kernel hacking 758# Kernel hacking
653# 759#
760# CONFIG_PRINTK_TIME is not set
654# CONFIG_DEBUG_KERNEL is not set 761# CONFIG_DEBUG_KERNEL is not set
762CONFIG_LOG_BUF_SHIFT=14
655CONFIG_CROSSCOMPILE=y 763CONFIG_CROSSCOMPILE=y
656CONFIG_CMDLINE="ip=any" 764CONFIG_CMDLINE="ip=any"
657 765
@@ -665,7 +773,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
665# 773#
666# Cryptographic options 774# Cryptographic options
667# 775#
668# CONFIG_CRYPTO is not set 776CONFIG_CRYPTO=y
777CONFIG_CRYPTO_HMAC=y
778CONFIG_CRYPTO_NULL=y
779CONFIG_CRYPTO_MD4=y
780CONFIG_CRYPTO_MD5=y
781CONFIG_CRYPTO_SHA1=y
782CONFIG_CRYPTO_SHA256=y
783CONFIG_CRYPTO_SHA512=y
784CONFIG_CRYPTO_WP512=y
785CONFIG_CRYPTO_TGR192=y
786CONFIG_CRYPTO_DES=y
787CONFIG_CRYPTO_BLOWFISH=y
788CONFIG_CRYPTO_TWOFISH=y
789CONFIG_CRYPTO_SERPENT=y
790CONFIG_CRYPTO_AES=y
791CONFIG_CRYPTO_CAST5=y
792CONFIG_CRYPTO_CAST6=y
793CONFIG_CRYPTO_TEA=y
794CONFIG_CRYPTO_ARC4=y
795CONFIG_CRYPTO_KHAZAD=y
796CONFIG_CRYPTO_ANUBIS=y
797CONFIG_CRYPTO_DEFLATE=y
798CONFIG_CRYPTO_MICHAEL_MIC=y
799CONFIG_CRYPTO_CRC32C=y
800# CONFIG_CRYPTO_TEST is not set
669 801
670# 802#
671# Hardware crypto devices 803# Hardware crypto devices
@@ -675,7 +807,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
675# Library routines 807# Library routines
676# 808#
677# CONFIG_CRC_CCITT is not set 809# CONFIG_CRC_CCITT is not set
810CONFIG_CRC16=y
678CONFIG_CRC32=y 811CONFIG_CRC32=y
679# CONFIG_LIBCRC32C is not set 812CONFIG_LIBCRC32C=y
680CONFIG_GENERIC_HARDIRQS=y 813CONFIG_ZLIB_INFLATE=y
681CONFIG_GENERIC_IRQ_PROBE=y 814CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 66ec1f41d122..5bc885b72d14 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:03 2005 4# Thu Oct 20 22:25:48 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,30 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29# CONFIG_HOTPLUG is not set 27# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
33# CONFIG_KALLSYMS_ALL is not set
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 38CONFIG_FUTEX=y
36CONFIG_EPOLL=y 39CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 44CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 45CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
44 48
45# 49#
46# Loadable module support 50# Loadable module support
@@ -49,48 +53,76 @@ CONFIG_MODULES=y
49CONFIG_MODULE_UNLOAD=y 53CONFIG_MODULE_UNLOAD=y
50# CONFIG_MODULE_FORCE_UNLOAD is not set 54# CONFIG_MODULE_FORCE_UNLOAD is not set
51CONFIG_OBSOLETE_MODPARM=y 55CONFIG_OBSOLETE_MODPARM=y
52CONFIG_MODVERSIONS=y 56# CONFIG_MODVERSIONS is not set
53CONFIG_MODULE_SRCVERSION_ALL=y 57CONFIG_MODULE_SRCVERSION_ALL=y
54CONFIG_KMOD=y 58CONFIG_KMOD=y
55 59
56# 60#
57# Machine selection 61# Machine selection
58# 62#
59# CONFIG_MACH_JAZZ is not set 63# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 64# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 65# CONFIG_MIPS_PB1000 is not set
66# CONFIG_MIPS_PB1100 is not set
67# CONFIG_MIPS_PB1500 is not set
68# CONFIG_MIPS_PB1550 is not set
69# CONFIG_MIPS_PB1200 is not set
70# CONFIG_MIPS_DB1000 is not set
71# CONFIG_MIPS_DB1100 is not set
72# CONFIG_MIPS_DB1500 is not set
73# CONFIG_MIPS_DB1550 is not set
74# CONFIG_MIPS_DB1200 is not set
75# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 76# CONFIG_MIPS_COBALT is not set
63CONFIG_MACH_DECSTATION=y 77CONFIG_MACH_DECSTATION=y
64# CONFIG_MIPS_EV64120 is not set 78# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 79# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 80# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 81# CONFIG_MIPS_ITE8172 is not set
82# CONFIG_MACH_JAZZ is not set
83# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 84# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set 85# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 86# CONFIG_MIPS_SEAD is not set
87# CONFIG_MIPS_SIM is not set
88# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 89# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 90# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 91# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 92# CONFIG_MOMENCO_OCELOT_G is not set
93# CONFIG_MIPS_XXS1500 is not set
94# CONFIG_PNX8550_V2PCI is not set
95# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 96# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 97# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 98# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 99# CONFIG_MACH_VR41XX is not set
100# CONFIG_PMC_YOSEMITE is not set
101# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 102# CONFIG_SGI_IP22 is not set
83# CONFIG_SOC_AU1X00 is not set 103# CONFIG_SGI_IP27 is not set
84# CONFIG_SIBYTE_SB1xxx_SOC is not set 104# CONFIG_SGI_IP32 is not set
105# CONFIG_SIBYTE_BIGSUR is not set
106# CONFIG_SIBYTE_SWARM is not set
107# CONFIG_SIBYTE_SENTOSA is not set
108# CONFIG_SIBYTE_RHONE is not set
109# CONFIG_SIBYTE_CARMEL is not set
110# CONFIG_SIBYTE_PTSWARM is not set
111# CONFIG_SIBYTE_LITTLESUR is not set
112# CONFIG_SIBYTE_CRHINE is not set
113# CONFIG_SIBYTE_CRHONE is not set
85# CONFIG_SNI_RM200_PCI is not set 114# CONFIG_SNI_RM200_PCI is not set
115# CONFIG_TOSHIBA_JMR3927 is not set
86# CONFIG_TOSHIBA_RBTX4927 is not set 116# CONFIG_TOSHIBA_RBTX4927 is not set
117# CONFIG_TOSHIBA_RBTX4938 is not set
87CONFIG_RWSEM_GENERIC_SPINLOCK=y 118CONFIG_RWSEM_GENERIC_SPINLOCK=y
88CONFIG_GENERIC_CALIBRATE_DELAY=y 119CONFIG_GENERIC_CALIBRATE_DELAY=y
89CONFIG_HAVE_DEC_LOCK=y
90CONFIG_DMA_NONCOHERENT=y 120CONFIG_DMA_NONCOHERENT=y
91CONFIG_DMA_NEED_PCI_MAP_STATE=y 121CONFIG_DMA_NEED_PCI_MAP_STATE=y
92CONFIG_EARLY_PRINTK=y 122CONFIG_EARLY_PRINTK=y
123# CONFIG_CPU_BIG_ENDIAN is not set
93CONFIG_CPU_LITTLE_ENDIAN=y 124CONFIG_CPU_LITTLE_ENDIAN=y
125CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
94CONFIG_IRQ_CPU=y 126CONFIG_IRQ_CPU=y
95CONFIG_BOOT_ELF32=y 127CONFIG_BOOT_ELF32=y
96CONFIG_MIPS_L1_CACHE_SHIFT=4 128CONFIG_MIPS_L1_CACHE_SHIFT=4
@@ -98,8 +130,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=4
98# 130#
99# CPU selection 131# CPU selection
100# 132#
101# CONFIG_CPU_MIPS32 is not set 133# CONFIG_CPU_MIPS32_R1 is not set
102# CONFIG_CPU_MIPS64 is not set 134# CONFIG_CPU_MIPS32_R2 is not set
135# CONFIG_CPU_MIPS64_R1 is not set
136# CONFIG_CPU_MIPS64_R2 is not set
103CONFIG_CPU_R3000=y 137CONFIG_CPU_R3000=y
104# CONFIG_CPU_TX39XX is not set 138# CONFIG_CPU_TX39XX is not set
105# CONFIG_CPU_VR41XX is not set 139# CONFIG_CPU_VR41XX is not set
@@ -115,12 +149,37 @@ CONFIG_CPU_R3000=y
115# CONFIG_CPU_RM7000 is not set 149# CONFIG_CPU_RM7000 is not set
116# CONFIG_CPU_RM9000 is not set 150# CONFIG_CPU_RM9000 is not set
117# CONFIG_CPU_SB1 is not set 151# CONFIG_CPU_SB1 is not set
152CONFIG_SYS_HAS_CPU_R3000=y
153CONFIG_SYS_HAS_CPU_R4X00=y
154CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
155CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
156CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
157
158#
159# Kernel type
160#
161CONFIG_32BIT=y
162# CONFIG_64BIT is not set
118CONFIG_PAGE_SIZE_4KB=y 163CONFIG_PAGE_SIZE_4KB=y
119# CONFIG_PAGE_SIZE_8KB is not set 164# CONFIG_PAGE_SIZE_8KB is not set
120# CONFIG_PAGE_SIZE_16KB is not set 165# CONFIG_PAGE_SIZE_16KB is not set
121# CONFIG_PAGE_SIZE_64KB is not set 166# CONFIG_PAGE_SIZE_64KB is not set
167# CONFIG_MIPS_MT is not set
122# CONFIG_CPU_ADVANCED is not set 168# CONFIG_CPU_ADVANCED is not set
123CONFIG_CPU_HAS_WB=y 169CONFIG_CPU_HAS_WB=y
170CONFIG_GENERIC_HARDIRQS=y
171CONFIG_GENERIC_IRQ_PROBE=y
172CONFIG_CPU_SUPPORTS_HIGHMEM=y
173CONFIG_ARCH_FLATMEM_ENABLE=y
174CONFIG_SELECT_MEMORY_MODEL=y
175CONFIG_FLATMEM_MANUAL=y
176# CONFIG_DISCONTIGMEM_MANUAL is not set
177# CONFIG_SPARSEMEM_MANUAL is not set
178CONFIG_FLATMEM=y
179CONFIG_FLAT_NODE_MEM_MAP=y
180# CONFIG_SPARSEMEM_STATIC is not set
181CONFIG_PREEMPT_NONE=y
182# CONFIG_PREEMPT_VOLUNTARY is not set
124# CONFIG_PREEMPT is not set 183# CONFIG_PREEMPT is not set
125 184
126# 185#
@@ -135,10 +194,6 @@ CONFIG_MMU=y
135# CONFIG_PCCARD is not set 194# CONFIG_PCCARD is not set
136 195
137# 196#
138# PC-card bridges
139#
140
141#
142# PCI Hotplug Support 197# PCI Hotplug Support
143# 198#
144 199
@@ -150,6 +205,80 @@ CONFIG_BINFMT_ELF=y
150CONFIG_TRAD_SIGNALS=y 205CONFIG_TRAD_SIGNALS=y
151 206
152# 207#
208# Networking
209#
210CONFIG_NET=y
211
212#
213# Networking options
214#
215CONFIG_PACKET=y
216CONFIG_PACKET_MMAP=y
217CONFIG_UNIX=y
218CONFIG_XFRM=y
219CONFIG_XFRM_USER=m
220# CONFIG_NET_KEY is not set
221CONFIG_INET=y
222# CONFIG_IP_MULTICAST is not set
223# CONFIG_IP_ADVANCED_ROUTER is not set
224CONFIG_IP_FIB_HASH=y
225CONFIG_IP_PNP=y
226# CONFIG_IP_PNP_DHCP is not set
227CONFIG_IP_PNP_BOOTP=y
228# CONFIG_IP_PNP_RARP is not set
229# CONFIG_NET_IPIP is not set
230# CONFIG_NET_IPGRE is not set
231# CONFIG_ARPD is not set
232# CONFIG_SYN_COOKIES is not set
233# CONFIG_INET_AH is not set
234# CONFIG_INET_ESP is not set
235# CONFIG_INET_IPCOMP is not set
236CONFIG_INET_TUNNEL=m
237CONFIG_INET_DIAG=y
238CONFIG_INET_TCP_DIAG=y
239# CONFIG_TCP_CONG_ADVANCED is not set
240CONFIG_TCP_CONG_BIC=y
241# CONFIG_IPV6 is not set
242# CONFIG_NETFILTER is not set
243
244#
245# DCCP Configuration (EXPERIMENTAL)
246#
247# CONFIG_IP_DCCP is not set
248
249#
250# SCTP Configuration (EXPERIMENTAL)
251#
252# CONFIG_IP_SCTP is not set
253# CONFIG_ATM is not set
254# CONFIG_BRIDGE is not set
255# CONFIG_VLAN_8021Q is not set
256# CONFIG_DECNET is not set
257# CONFIG_LLC2 is not set
258# CONFIG_IPX is not set
259# CONFIG_ATALK is not set
260# CONFIG_X25 is not set
261# CONFIG_LAPB is not set
262# CONFIG_NET_DIVERT is not set
263# CONFIG_ECONET is not set
264# CONFIG_WAN_ROUTER is not set
265# CONFIG_NET_SCHED is not set
266# CONFIG_NET_CLS_ROUTE is not set
267
268#
269# Network testing
270#
271# CONFIG_NET_PKTGEN is not set
272# CONFIG_HAMRADIO is not set
273# CONFIG_IRDA is not set
274# CONFIG_BT is not set
275CONFIG_IEEE80211=m
276# CONFIG_IEEE80211_DEBUG is not set
277CONFIG_IEEE80211_CRYPT_WEP=m
278CONFIG_IEEE80211_CRYPT_CCMP=m
279CONFIG_IEEE80211_CRYPT_TKIP=m
280
281#
153# Device Drivers 282# Device Drivers
154# 283#
155 284
@@ -159,6 +288,12 @@ CONFIG_TRAD_SIGNALS=y
159CONFIG_STANDALONE=y 288CONFIG_STANDALONE=y
160CONFIG_PREVENT_FIRMWARE_BUILD=y 289CONFIG_PREVENT_FIRMWARE_BUILD=y
161# CONFIG_FW_LOADER is not set 290# CONFIG_FW_LOADER is not set
291# CONFIG_DEBUG_DRIVER is not set
292
293#
294# Connector - unified userspace <-> kernelspace linker
295#
296CONFIG_CONNECTOR=m
162 297
163# 298#
164# Memory Technology Devices (MTD) 299# Memory Technology Devices (MTD)
@@ -177,17 +312,14 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
177# 312#
178# Block devices 313# Block devices
179# 314#
180# CONFIG_BLK_DEV_FD is not set
181# CONFIG_BLK_DEV_COW_COMMON is not set 315# CONFIG_BLK_DEV_COW_COMMON is not set
182# CONFIG_BLK_DEV_LOOP is not set 316CONFIG_BLK_DEV_LOOP=m
317# CONFIG_BLK_DEV_CRYPTOLOOP is not set
183# CONFIG_BLK_DEV_NBD is not set 318# CONFIG_BLK_DEV_NBD is not set
184# CONFIG_BLK_DEV_RAM is not set 319# CONFIG_BLK_DEV_RAM is not set
185CONFIG_BLK_DEV_RAM_COUNT=16 320CONFIG_BLK_DEV_RAM_COUNT=16
186CONFIG_INITRAMFS_SOURCE=""
187# CONFIG_LBD is not set 321# CONFIG_LBD is not set
188CONFIG_CDROM_PKTCDVD=m 322# CONFIG_CDROM_PKTCDVD is not set
189CONFIG_CDROM_PKTCDVD_BUFFERS=8
190# CONFIG_CDROM_PKTCDVD_WCACHE is not set
191 323
192# 324#
193# IO Schedulers 325# IO Schedulers
@@ -196,7 +328,7 @@ CONFIG_IOSCHED_NOOP=y
196CONFIG_IOSCHED_AS=y 328CONFIG_IOSCHED_AS=y
197CONFIG_IOSCHED_DEADLINE=y 329CONFIG_IOSCHED_DEADLINE=y
198CONFIG_IOSCHED_CFQ=y 330CONFIG_IOSCHED_CFQ=y
199CONFIG_ATA_OVER_ETH=m 331# CONFIG_ATA_OVER_ETH is not set
200 332
201# 333#
202# ATA/ATAPI/MFM/RLL support 334# ATA/ATAPI/MFM/RLL support
@@ -206,6 +338,7 @@ CONFIG_ATA_OVER_ETH=m
206# 338#
207# SCSI device support 339# SCSI device support
208# 340#
341CONFIG_RAID_ATTRS=m
209CONFIG_SCSI=y 342CONFIG_SCSI=y
210CONFIG_SCSI_PROC_FS=y 343CONFIG_SCSI_PROC_FS=y
211 344
@@ -213,10 +346,12 @@ CONFIG_SCSI_PROC_FS=y
213# SCSI support type (disk, tape, CD-ROM) 346# SCSI support type (disk, tape, CD-ROM)
214# 347#
215CONFIG_BLK_DEV_SD=y 348CONFIG_BLK_DEV_SD=y
216# CONFIG_CHR_DEV_ST is not set 349CONFIG_CHR_DEV_ST=m
217# CONFIG_CHR_DEV_OSST is not set 350# CONFIG_CHR_DEV_OSST is not set
218# CONFIG_BLK_DEV_SR is not set 351CONFIG_BLK_DEV_SR=m
219# CONFIG_CHR_DEV_SG is not set 352# CONFIG_BLK_DEV_SR_VENDOR is not set
353CONFIG_CHR_DEV_SG=m
354# CONFIG_CHR_DEV_SCH is not set
220 355
221# 356#
222# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 357# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -228,9 +363,10 @@ CONFIG_SCSI_CONSTANTS=y
228# 363#
229# SCSI Transport Attributes 364# SCSI Transport Attributes
230# 365#
231# CONFIG_SCSI_SPI_ATTRS is not set 366CONFIG_SCSI_SPI_ATTRS=m
232# CONFIG_SCSI_FC_ATTRS is not set 367# CONFIG_SCSI_FC_ATTRS is not set
233# CONFIG_SCSI_ISCSI_ATTRS is not set 368# CONFIG_SCSI_ISCSI_ATTRS is not set
369CONFIG_SCSI_SAS_ATTRS=m
234 370
235# 371#
236# SCSI low-level drivers 372# SCSI low-level drivers
@@ -248,6 +384,7 @@ CONFIG_SCSI_DECNCR=y
248# 384#
249# Fusion MPT device support 385# Fusion MPT device support
250# 386#
387# CONFIG_FUSION is not set
251 388
252# 389#
253# IEEE 1394 (FireWire) support 390# IEEE 1394 (FireWire) support
@@ -258,78 +395,28 @@ CONFIG_SCSI_DECNCR=y
258# 395#
259 396
260# 397#
261# Networking support 398# Network device support
262#
263CONFIG_NET=y
264
265#
266# Networking options
267#
268CONFIG_PACKET=y
269# CONFIG_PACKET_MMAP is not set
270CONFIG_NETLINK_DEV=y
271CONFIG_UNIX=y
272CONFIG_NET_KEY=y
273CONFIG_INET=y
274# CONFIG_IP_MULTICAST is not set
275# CONFIG_IP_ADVANCED_ROUTER is not set
276CONFIG_IP_PNP=y
277# CONFIG_IP_PNP_DHCP is not set
278CONFIG_IP_PNP_BOOTP=y
279# CONFIG_IP_PNP_RARP is not set
280# CONFIG_NET_IPIP is not set
281# CONFIG_NET_IPGRE is not set
282# CONFIG_ARPD is not set
283# CONFIG_SYN_COOKIES is not set
284# CONFIG_INET_AH is not set
285# CONFIG_INET_ESP is not set
286# CONFIG_INET_IPCOMP is not set
287CONFIG_INET_TUNNEL=m
288CONFIG_IP_TCPDIAG=m
289# CONFIG_IP_TCPDIAG_IPV6 is not set
290# CONFIG_IPV6 is not set
291# CONFIG_NETFILTER is not set
292CONFIG_XFRM=y
293CONFIG_XFRM_USER=m
294
295#
296# SCTP Configuration (EXPERIMENTAL)
297# 399#
298# CONFIG_IP_SCTP is not set 400CONFIG_NETDEVICES=y
299# CONFIG_ATM is not set 401# CONFIG_DUMMY is not set
300# CONFIG_BRIDGE is not set 402# CONFIG_BONDING is not set
301# CONFIG_VLAN_8021Q is not set 403# CONFIG_EQUALIZER is not set
302# CONFIG_DECNET is not set 404# CONFIG_TUN is not set
303# CONFIG_LLC2 is not set
304# CONFIG_IPX is not set
305# CONFIG_ATALK is not set
306# CONFIG_X25 is not set
307# CONFIG_LAPB is not set
308# CONFIG_NET_DIVERT is not set
309# CONFIG_ECONET is not set
310# CONFIG_WAN_ROUTER is not set
311 405
312# 406#
313# QoS and/or fair queueing 407# PHY device support
314# 408#
315# CONFIG_NET_SCHED is not set 409CONFIG_PHYLIB=m
316# CONFIG_NET_CLS_ROUTE is not set 410CONFIG_PHYCONTROL=y
317 411
318# 412#
319# Network testing 413# MII PHY device drivers
320# 414#
321# CONFIG_NET_PKTGEN is not set 415CONFIG_MARVELL_PHY=m
322# CONFIG_NETPOLL is not set 416CONFIG_DAVICOM_PHY=m
323# CONFIG_NET_POLL_CONTROLLER is not set 417CONFIG_QSEMI_PHY=m
324# CONFIG_HAMRADIO is not set 418CONFIG_LXT_PHY=m
325# CONFIG_IRDA is not set 419CONFIG_CICADA_PHY=m
326# CONFIG_BT is not set
327CONFIG_NETDEVICES=y
328# CONFIG_DUMMY is not set
329# CONFIG_BONDING is not set
330# CONFIG_EQUALIZER is not set
331# CONFIG_TUN is not set
332# CONFIG_ETHERTAP is not set
333 420
334# 421#
335# Ethernet (10 or 100Mbit) 422# Ethernet (10 or 100Mbit)
@@ -363,6 +450,8 @@ CONFIG_DECLANCE=y
363# CONFIG_SLIP is not set 450# CONFIG_SLIP is not set
364# CONFIG_SHAPER is not set 451# CONFIG_SHAPER is not set
365# CONFIG_NETCONSOLE is not set 452# CONFIG_NETCONSOLE is not set
453# CONFIG_NETPOLL is not set
454# CONFIG_NET_POLL_CONTROLLER is not set
366 455
367# 456#
368# ISDN subsystem 457# ISDN subsystem
@@ -377,48 +466,22 @@ CONFIG_DECLANCE=y
377# 466#
378# Input device support 467# Input device support
379# 468#
380CONFIG_INPUT=y 469# CONFIG_INPUT is not set
381 470
382# 471#
383# Userland interfaces 472# Hardware I/O ports
384#
385CONFIG_INPUT_MOUSEDEV=y
386CONFIG_INPUT_MOUSEDEV_PSAUX=y
387CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
388CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
389# CONFIG_INPUT_JOYDEV is not set
390# CONFIG_INPUT_TSDEV is not set
391# CONFIG_INPUT_EVDEV is not set
392# CONFIG_INPUT_EVBUG is not set
393
394#
395# Input I/O drivers
396# 473#
474# CONFIG_SERIO is not set
397# CONFIG_GAMEPORT is not set 475# CONFIG_GAMEPORT is not set
398CONFIG_SOUND_GAMEPORT=y
399CONFIG_SERIO=y
400# CONFIG_SERIO_I8042 is not set
401CONFIG_SERIO_SERPORT=y
402# CONFIG_SERIO_CT82C710 is not set
403# CONFIG_SERIO_LIBPS2 is not set
404CONFIG_SERIO_RAW=m
405
406#
407# Input Device Drivers
408#
409# CONFIG_INPUT_KEYBOARD is not set
410# CONFIG_INPUT_MOUSE is not set
411# CONFIG_INPUT_JOYSTICK is not set
412# CONFIG_INPUT_TOUCHSCREEN is not set
413# CONFIG_INPUT_MISC is not set
414 476
415# 477#
416# Character devices 478# Character devices
417# 479#
418CONFIG_VT=y 480# CONFIG_VT is not set
419CONFIG_VT_CONSOLE=y
420CONFIG_HW_CONSOLE=y
421# CONFIG_SERIAL_NONSTANDARD is not set 481# CONFIG_SERIAL_NONSTANDARD is not set
482CONFIG_SERIAL_DEC=y
483CONFIG_SERIAL_DEC_CONSOLE=y
484CONFIG_ZS=y
422 485
423# 486#
424# Serial drivers 487# Serial drivers
@@ -445,18 +508,20 @@ CONFIG_LEGACY_PTY_COUNT=256
445# Watchdog Cards 508# Watchdog Cards
446# 509#
447# CONFIG_WATCHDOG is not set 510# CONFIG_WATCHDOG is not set
448# CONFIG_RTC is not set 511CONFIG_RTC=y
449# CONFIG_GEN_RTC is not set
450# CONFIG_DTLK is not set 512# CONFIG_DTLK is not set
451# CONFIG_R3964 is not set 513# CONFIG_R3964 is not set
452 514
453# 515#
454# Ftape, the floppy tape device driver 516# Ftape, the floppy tape device driver
455# 517#
456# CONFIG_DRM is not set
457# CONFIG_RAW_DRIVER is not set 518# CONFIG_RAW_DRIVER is not set
458 519
459# 520#
521# TPM devices
522#
523
524#
460# I2C support 525# I2C support
461# 526#
462# CONFIG_I2C is not set 527# CONFIG_I2C is not set
@@ -467,10 +532,20 @@ CONFIG_LEGACY_PTY_COUNT=256
467# CONFIG_W1 is not set 532# CONFIG_W1 is not set
468 533
469# 534#
535# Hardware Monitoring support
536#
537# CONFIG_HWMON is not set
538# CONFIG_HWMON_VID is not set
539
540#
470# Misc devices 541# Misc devices
471# 542#
472 543
473# 544#
545# Multimedia Capabilities Port drivers
546#
547
548#
474# Multimedia devices 549# Multimedia devices
475# 550#
476# CONFIG_VIDEO_DEV is not set 551# CONFIG_VIDEO_DEV is not set
@@ -483,13 +558,29 @@ CONFIG_LEGACY_PTY_COUNT=256
483# 558#
484# Graphics support 559# Graphics support
485# 560#
486# CONFIG_FB is not set 561CONFIG_FB=y
487 562CONFIG_FB_CFB_FILLRECT=y
488# 563CONFIG_FB_CFB_COPYAREA=y
489# Console display driver support 564CONFIG_FB_CFB_IMAGEBLIT=y
490# 565CONFIG_FB_SOFT_CURSOR=y
491# CONFIG_VGA_CONSOLE is not set 566# CONFIG_FB_MACMODES is not set
492CONFIG_DUMMY_CONSOLE=y 567# CONFIG_FB_MODE_HELPERS is not set
568# CONFIG_FB_TILEBLITTING is not set
569# CONFIG_FB_PMAG_AA is not set
570CONFIG_FB_PMAG_BA=y
571CONFIG_FB_PMAGB_B=y
572# CONFIG_FB_MAXINE is not set
573# CONFIG_FB_S1D13XXX is not set
574# CONFIG_FB_VIRTUAL is not set
575
576#
577# Logo configuration
578#
579CONFIG_LOGO=y
580# CONFIG_LOGO_LINUX_MONO is not set
581# CONFIG_LOGO_LINUX_VGA16 is not set
582# CONFIG_LOGO_LINUX_CLUT224 is not set
583CONFIG_LOGO_DEC_CLUT224=y
493# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 584# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
494 585
495# 586#
@@ -504,10 +595,6 @@ CONFIG_DUMMY_CONSOLE=y
504# CONFIG_USB_ARCH_HAS_OHCI is not set 595# CONFIG_USB_ARCH_HAS_OHCI is not set
505 596
506# 597#
507# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
508#
509
510#
511# USB Gadget Support 598# USB Gadget Support
512# 599#
513# CONFIG_USB_GADGET is not set 600# CONFIG_USB_GADGET is not set
@@ -520,7 +607,10 @@ CONFIG_DUMMY_CONSOLE=y
520# 607#
521# InfiniBand support 608# InfiniBand support
522# 609#
523# CONFIG_INFINIBAND is not set 610
611#
612# SN Devices
613#
524 614
525# 615#
526# File systems 616# File systems
@@ -529,6 +619,7 @@ CONFIG_EXT2_FS=y
529CONFIG_EXT2_FS_XATTR=y 619CONFIG_EXT2_FS_XATTR=y
530CONFIG_EXT2_FS_POSIX_ACL=y 620CONFIG_EXT2_FS_POSIX_ACL=y
531CONFIG_EXT2_FS_SECURITY=y 621CONFIG_EXT2_FS_SECURITY=y
622# CONFIG_EXT2_FS_XIP is not set
532# CONFIG_EXT3_FS is not set 623# CONFIG_EXT3_FS is not set
533# CONFIG_JBD is not set 624# CONFIG_JBD is not set
534CONFIG_FS_MBCACHE=y 625CONFIG_FS_MBCACHE=y
@@ -538,10 +629,12 @@ CONFIG_FS_POSIX_ACL=y
538# CONFIG_XFS_FS is not set 629# CONFIG_XFS_FS is not set
539# CONFIG_MINIX_FS is not set 630# CONFIG_MINIX_FS is not set
540# CONFIG_ROMFS_FS is not set 631# CONFIG_ROMFS_FS is not set
632CONFIG_INOTIFY=y
541# CONFIG_QUOTA is not set 633# CONFIG_QUOTA is not set
542CONFIG_DNOTIFY=y 634CONFIG_DNOTIFY=y
543# CONFIG_AUTOFS_FS is not set 635# CONFIG_AUTOFS_FS is not set
544# CONFIG_AUTOFS4_FS is not set 636# CONFIG_AUTOFS4_FS is not set
637CONFIG_FUSE_FS=m
545 638
546# 639#
547# CD-ROM/DVD Filesystems 640# CD-ROM/DVD Filesystems
@@ -562,12 +655,10 @@ CONFIG_DNOTIFY=y
562CONFIG_PROC_FS=y 655CONFIG_PROC_FS=y
563CONFIG_PROC_KCORE=y 656CONFIG_PROC_KCORE=y
564CONFIG_SYSFS=y 657CONFIG_SYSFS=y
565# CONFIG_DEVFS_FS is not set 658CONFIG_TMPFS=y
566CONFIG_DEVPTS_FS_XATTR=y
567CONFIG_DEVPTS_FS_SECURITY=y
568# CONFIG_TMPFS is not set
569# CONFIG_HUGETLB_PAGE is not set 659# CONFIG_HUGETLB_PAGE is not set
570CONFIG_RAMFS=y 660CONFIG_RAMFS=y
661CONFIG_RELAYFS_FS=m
571 662
572# 663#
573# Miscellaneous filesystems 664# Miscellaneous filesystems
@@ -584,19 +675,31 @@ CONFIG_RAMFS=y
584# CONFIG_HPFS_FS is not set 675# CONFIG_HPFS_FS is not set
585# CONFIG_QNX4FS_FS is not set 676# CONFIG_QNX4FS_FS is not set
586# CONFIG_SYSV_FS is not set 677# CONFIG_SYSV_FS is not set
587# CONFIG_UFS_FS is not set 678CONFIG_UFS_FS=y
679CONFIG_UFS_FS_WRITE=y
588 680
589# 681#
590# Network File Systems 682# Network File Systems
591# 683#
592# CONFIG_NFS_FS is not set 684CONFIG_NFS_FS=y
685CONFIG_NFS_V3=y
686# CONFIG_NFS_V3_ACL is not set
687# CONFIG_NFS_V4 is not set
688# CONFIG_NFS_DIRECTIO is not set
593# CONFIG_NFSD is not set 689# CONFIG_NFSD is not set
594# CONFIG_EXPORTFS is not set 690CONFIG_ROOT_NFS=y
691CONFIG_LOCKD=y
692CONFIG_LOCKD_V4=y
693CONFIG_NFS_COMMON=y
694CONFIG_SUNRPC=y
695# CONFIG_RPCSEC_GSS_KRB5 is not set
696# CONFIG_RPCSEC_GSS_SPKM3 is not set
595# CONFIG_SMB_FS is not set 697# CONFIG_SMB_FS is not set
596# CONFIG_CIFS is not set 698# CONFIG_CIFS is not set
597# CONFIG_NCP_FS is not set 699# CONFIG_NCP_FS is not set
598# CONFIG_CODA_FS is not set 700# CONFIG_CODA_FS is not set
599# CONFIG_AFS_FS is not set 701# CONFIG_AFS_FS is not set
702# CONFIG_9P_FS is not set
600 703
601# 704#
602# Partition Types 705# Partition Types
@@ -631,9 +734,24 @@ CONFIG_ULTRIX_PARTITION=y
631# 734#
632# Kernel hacking 735# Kernel hacking
633# 736#
634# CONFIG_DEBUG_KERNEL is not set 737# CONFIG_PRINTK_TIME is not set
738CONFIG_DEBUG_KERNEL=y
739CONFIG_MAGIC_SYSRQ=y
740CONFIG_LOG_BUF_SHIFT=14
741CONFIG_DETECT_SOFTLOCKUP=y
742# CONFIG_SCHEDSTATS is not set
743# CONFIG_DEBUG_SLAB is not set
744# CONFIG_DEBUG_SPINLOCK is not set
745# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
746# CONFIG_DEBUG_KOBJECT is not set
747# CONFIG_DEBUG_INFO is not set
748# CONFIG_DEBUG_FS is not set
635CONFIG_CROSSCOMPILE=y 749CONFIG_CROSSCOMPILE=y
636CONFIG_CMDLINE="" 750CONFIG_CMDLINE=""
751# CONFIG_DEBUG_STACK_USAGE is not set
752# CONFIG_KGDB is not set
753# CONFIG_RUNTIME_DEBUG is not set
754# CONFIG_MIPS_UNCACHED is not set
637 755
638# 756#
639# Security options 757# Security options
@@ -645,7 +763,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
645# 763#
646# Cryptographic options 764# Cryptographic options
647# 765#
648# CONFIG_CRYPTO is not set 766CONFIG_CRYPTO=y
767CONFIG_CRYPTO_HMAC=y
768CONFIG_CRYPTO_NULL=m
769CONFIG_CRYPTO_MD4=m
770CONFIG_CRYPTO_MD5=m
771CONFIG_CRYPTO_SHA1=m
772CONFIG_CRYPTO_SHA256=m
773CONFIG_CRYPTO_SHA512=m
774CONFIG_CRYPTO_WP512=m
775CONFIG_CRYPTO_TGR192=m
776CONFIG_CRYPTO_DES=m
777CONFIG_CRYPTO_BLOWFISH=m
778CONFIG_CRYPTO_TWOFISH=m
779CONFIG_CRYPTO_SERPENT=m
780CONFIG_CRYPTO_AES=m
781CONFIG_CRYPTO_CAST5=m
782CONFIG_CRYPTO_CAST6=m
783CONFIG_CRYPTO_TEA=m
784CONFIG_CRYPTO_ARC4=m
785CONFIG_CRYPTO_KHAZAD=m
786CONFIG_CRYPTO_ANUBIS=m
787CONFIG_CRYPTO_DEFLATE=m
788CONFIG_CRYPTO_MICHAEL_MIC=m
789CONFIG_CRYPTO_CRC32C=m
790# CONFIG_CRYPTO_TEST is not set
649 791
650# 792#
651# Hardware crypto devices 793# Hardware crypto devices
@@ -655,7 +797,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
655# Library routines 797# Library routines
656# 798#
657# CONFIG_CRC_CCITT is not set 799# CONFIG_CRC_CCITT is not set
800CONFIG_CRC16=m
658CONFIG_CRC32=y 801CONFIG_CRC32=y
659CONFIG_LIBCRC32C=m 802CONFIG_LIBCRC32C=m
660CONFIG_GENERIC_HARDIRQS=y 803CONFIG_ZLIB_INFLATE=m
661CONFIG_GENERIC_IRQ_PROBE=y 804CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index ba2ec01defb1..c0d06ea5566c 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:03 2005 4# Thu Oct 20 22:25:51 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29# CONFIG_HOTPLUG is not set 27# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,56 +59,84 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60CONFIG_MACH_VR41XX=y 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_NEC_CMBVR4133 is not set 64# CONFIG_MIPS_PB1000 is not set
62CONFIG_CASIO_E55=y 65# CONFIG_MIPS_PB1100 is not set
63# CONFIG_IBM_WORKPAD is not set 66# CONFIG_MIPS_PB1500 is not set
64# CONFIG_TANBAC_TB0226 is not set 67# CONFIG_MIPS_PB1550 is not set
65# CONFIG_TANBAC_TB0229 is not set 68# CONFIG_MIPS_PB1200 is not set
66# CONFIG_VICTOR_MPC30X is not set 69# CONFIG_MIPS_DB1000 is not set
67# CONFIG_ZAO_CAPCELLA is not set 70# CONFIG_MIPS_DB1100 is not set
68# CONFIG_VRC4171 is not set 71# CONFIG_MIPS_DB1500 is not set
69# CONFIG_TOSHIBA_JMR3927 is not set 72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
70# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
71# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
72# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
73# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
74# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
75# CONFIG_LASAT is not set
76# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
77# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
78# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
79# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
80# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
81# CONFIG_MOMENCO_OCELOT_G is not set
82# CONFIG_MOMENCO_OCELOT_C is not set
83# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
84# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
85# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
86# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
87# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
88# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
89# CONFIG_NEC_OSPREY is not set 98CONFIG_MACH_VR41XX=y
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
90# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
91# CONFIG_SOC_AU1X00 is not set 102# CONFIG_SGI_IP27 is not set
92# CONFIG_SIBYTE_SB1xxx_SOC is not set 103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
93# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
94# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
117# CONFIG_NEC_CMBVR4133 is not set
118CONFIG_CASIO_E55=y
119# CONFIG_IBM_WORKPAD is not set
120# CONFIG_TANBAC_TB022X is not set
121# CONFIG_VICTOR_MPC30X is not set
122# CONFIG_ZAO_CAPCELLA is not set
95CONFIG_RWSEM_GENERIC_SPINLOCK=y 123CONFIG_RWSEM_GENERIC_SPINLOCK=y
96CONFIG_GENERIC_CALIBRATE_DELAY=y 124CONFIG_GENERIC_CALIBRATE_DELAY=y
97CONFIG_HAVE_DEC_LOCK=y
98CONFIG_DMA_NONCOHERENT=y 125CONFIG_DMA_NONCOHERENT=y
99CONFIG_DMA_NEED_PCI_MAP_STATE=y 126CONFIG_DMA_NEED_PCI_MAP_STATE=y
127# CONFIG_CPU_BIG_ENDIAN is not set
100CONFIG_CPU_LITTLE_ENDIAN=y 128CONFIG_CPU_LITTLE_ENDIAN=y
129CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
101CONFIG_IRQ_CPU=y 130CONFIG_IRQ_CPU=y
102CONFIG_MIPS_L1_CACHE_SHIFT=5 131CONFIG_MIPS_L1_CACHE_SHIFT=5
103 132
104# 133#
105# CPU selection 134# CPU selection
106# 135#
107# CONFIG_CPU_MIPS32 is not set 136# CONFIG_CPU_MIPS32_R1 is not set
108# CONFIG_CPU_MIPS64 is not set 137# CONFIG_CPU_MIPS32_R2 is not set
138# CONFIG_CPU_MIPS64_R1 is not set
139# CONFIG_CPU_MIPS64_R2 is not set
109# CONFIG_CPU_R3000 is not set 140# CONFIG_CPU_R3000 is not set
110# CONFIG_CPU_TX39XX is not set 141# CONFIG_CPU_TX39XX is not set
111CONFIG_CPU_VR41XX=y 142CONFIG_CPU_VR41XX=y
@@ -121,12 +152,36 @@ CONFIG_CPU_VR41XX=y
121# CONFIG_CPU_RM7000 is not set 152# CONFIG_CPU_RM7000 is not set
122# CONFIG_CPU_RM9000 is not set 153# CONFIG_CPU_RM9000 is not set
123# CONFIG_CPU_SB1 is not set 154# CONFIG_CPU_SB1 is not set
155CONFIG_SYS_HAS_CPU_VR41XX=y
156CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
157CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
158CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
159CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
160
161#
162# Kernel type
163#
164CONFIG_32BIT=y
165# CONFIG_64BIT is not set
124CONFIG_PAGE_SIZE_4KB=y 166CONFIG_PAGE_SIZE_4KB=y
125# CONFIG_PAGE_SIZE_8KB is not set 167# CONFIG_PAGE_SIZE_8KB is not set
126# CONFIG_PAGE_SIZE_16KB is not set 168# CONFIG_PAGE_SIZE_16KB is not set
127# CONFIG_PAGE_SIZE_64KB is not set 169# CONFIG_PAGE_SIZE_64KB is not set
170# CONFIG_MIPS_MT is not set
128# CONFIG_CPU_ADVANCED is not set 171# CONFIG_CPU_ADVANCED is not set
129CONFIG_CPU_HAS_SYNC=y 172CONFIG_CPU_HAS_SYNC=y
173CONFIG_GENERIC_HARDIRQS=y
174CONFIG_GENERIC_IRQ_PROBE=y
175CONFIG_ARCH_FLATMEM_ENABLE=y
176CONFIG_SELECT_MEMORY_MODEL=y
177CONFIG_FLATMEM_MANUAL=y
178# CONFIG_DISCONTIGMEM_MANUAL is not set
179# CONFIG_SPARSEMEM_MANUAL is not set
180CONFIG_FLATMEM=y
181CONFIG_FLAT_NODE_MEM_MAP=y
182# CONFIG_SPARSEMEM_STATIC is not set
183CONFIG_PREEMPT_NONE=y
184# CONFIG_PREEMPT_VOLUNTARY is not set
130# CONFIG_PREEMPT is not set 185# CONFIG_PREEMPT is not set
131 186
132# 187#
@@ -141,11 +196,6 @@ CONFIG_MMU=y
141# CONFIG_PCCARD is not set 196# CONFIG_PCCARD is not set
142 197
143# 198#
144# PC-card bridges
145#
146CONFIG_PCMCIA_PROBE=y
147
148#
149# PCI Hotplug Support 199# PCI Hotplug Support
150# 200#
151 201
@@ -157,6 +207,78 @@ CONFIG_BINFMT_ELF=y
157CONFIG_TRAD_SIGNALS=y 207CONFIG_TRAD_SIGNALS=y
158 208
159# 209#
210# Networking
211#
212CONFIG_NET=y
213
214#
215# Networking options
216#
217CONFIG_PACKET=y
218CONFIG_PACKET_MMAP=y
219CONFIG_UNIX=y
220CONFIG_XFRM=y
221CONFIG_XFRM_USER=m
222CONFIG_NET_KEY=y
223CONFIG_INET=y
224CONFIG_IP_MULTICAST=y
225# CONFIG_IP_ADVANCED_ROUTER is not set
226CONFIG_IP_FIB_HASH=y
227# CONFIG_IP_PNP is not set
228# CONFIG_NET_IPIP is not set
229# CONFIG_NET_IPGRE is not set
230# CONFIG_IP_MROUTE is not set
231# CONFIG_ARPD is not set
232# CONFIG_SYN_COOKIES is not set
233# CONFIG_INET_AH is not set
234# CONFIG_INET_ESP is not set
235# CONFIG_INET_IPCOMP is not set
236CONFIG_INET_TUNNEL=m
237CONFIG_INET_DIAG=y
238CONFIG_INET_TCP_DIAG=y
239# CONFIG_TCP_CONG_ADVANCED is not set
240CONFIG_TCP_CONG_BIC=y
241# CONFIG_IPV6 is not set
242# CONFIG_NETFILTER is not set
243
244#
245# DCCP Configuration (EXPERIMENTAL)
246#
247# CONFIG_IP_DCCP is not set
248
249#
250# SCTP Configuration (EXPERIMENTAL)
251#
252# CONFIG_IP_SCTP is not set
253# CONFIG_ATM is not set
254# CONFIG_BRIDGE is not set
255# CONFIG_VLAN_8021Q is not set
256# CONFIG_DECNET is not set
257# CONFIG_LLC2 is not set
258# CONFIG_IPX is not set
259# CONFIG_ATALK is not set
260# CONFIG_X25 is not set
261# CONFIG_LAPB is not set
262# CONFIG_NET_DIVERT is not set
263# CONFIG_ECONET is not set
264# CONFIG_WAN_ROUTER is not set
265# CONFIG_NET_SCHED is not set
266# CONFIG_NET_CLS_ROUTE is not set
267
268#
269# Network testing
270#
271# CONFIG_NET_PKTGEN is not set
272# CONFIG_HAMRADIO is not set
273# CONFIG_IRDA is not set
274# CONFIG_BT is not set
275CONFIG_IEEE80211=m
276# CONFIG_IEEE80211_DEBUG is not set
277CONFIG_IEEE80211_CRYPT_WEP=m
278CONFIG_IEEE80211_CRYPT_CCMP=m
279CONFIG_IEEE80211_CRYPT_TKIP=m
280
281#
160# Device Drivers 282# Device Drivers
161# 283#
162 284
@@ -168,6 +290,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
168# CONFIG_FW_LOADER is not set 290# CONFIG_FW_LOADER is not set
169 291
170# 292#
293# Connector - unified userspace <-> kernelspace linker
294#
295CONFIG_CONNECTOR=m
296
297#
171# Memory Technology Devices (MTD) 298# Memory Technology Devices (MTD)
172# 299#
173# CONFIG_MTD is not set 300# CONFIG_MTD is not set
@@ -185,18 +312,13 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
185# 312#
186# Block devices 313# Block devices
187# 314#
188# CONFIG_BLK_DEV_FD is not set
189# CONFIG_BLK_DEV_XD is not set
190# CONFIG_BLK_DEV_COW_COMMON is not set 315# CONFIG_BLK_DEV_COW_COMMON is not set
191# CONFIG_BLK_DEV_LOOP is not set 316# CONFIG_BLK_DEV_LOOP is not set
192# CONFIG_BLK_DEV_NBD is not set 317# CONFIG_BLK_DEV_NBD is not set
193# CONFIG_BLK_DEV_RAM is not set 318# CONFIG_BLK_DEV_RAM is not set
194CONFIG_BLK_DEV_RAM_COUNT=16 319CONFIG_BLK_DEV_RAM_COUNT=16
195CONFIG_INITRAMFS_SOURCE=""
196# CONFIG_LBD is not set 320# CONFIG_LBD is not set
197CONFIG_CDROM_PKTCDVD=m 321# CONFIG_CDROM_PKTCDVD is not set
198CONFIG_CDROM_PKTCDVD_BUFFERS=8
199# CONFIG_CDROM_PKTCDVD_WCACHE is not set
200 322
201# 323#
202# IO Schedulers 324# IO Schedulers
@@ -205,7 +327,7 @@ CONFIG_IOSCHED_NOOP=y
205CONFIG_IOSCHED_AS=y 327CONFIG_IOSCHED_AS=y
206CONFIG_IOSCHED_DEADLINE=y 328CONFIG_IOSCHED_DEADLINE=y
207CONFIG_IOSCHED_CFQ=y 329CONFIG_IOSCHED_CFQ=y
208CONFIG_ATA_OVER_ETH=m 330# CONFIG_ATA_OVER_ETH is not set
209 331
210# 332#
211# ATA/ATAPI/MFM/RLL support 333# ATA/ATAPI/MFM/RLL support
@@ -237,6 +359,7 @@ CONFIG_IDE_GENERIC=y
237# 359#
238# SCSI device support 360# SCSI device support
239# 361#
362# CONFIG_RAID_ATTRS is not set
240# CONFIG_SCSI is not set 363# CONFIG_SCSI is not set
241 364
242# 365#
@@ -252,6 +375,7 @@ CONFIG_IDE_GENERIC=y
252# 375#
253# Fusion MPT device support 376# Fusion MPT device support
254# 377#
378# CONFIG_FUSION is not set
255 379
256# 380#
257# IEEE 1394 (FireWire) support 381# IEEE 1394 (FireWire) support
@@ -262,76 +386,13 @@ CONFIG_IDE_GENERIC=y
262# 386#
263 387
264# 388#
265# Networking support 389# Network device support
266#
267CONFIG_NET=y
268
269#
270# Networking options
271#
272CONFIG_PACKET=y
273CONFIG_PACKET_MMAP=y
274CONFIG_NETLINK_DEV=y
275CONFIG_UNIX=y
276CONFIG_NET_KEY=y
277CONFIG_INET=y
278CONFIG_IP_MULTICAST=y
279# CONFIG_IP_ADVANCED_ROUTER is not set
280# CONFIG_IP_PNP is not set
281# CONFIG_NET_IPIP is not set
282# CONFIG_NET_IPGRE is not set
283# CONFIG_IP_MROUTE is not set
284# CONFIG_ARPD is not set
285# CONFIG_SYN_COOKIES is not set
286# CONFIG_INET_AH is not set
287# CONFIG_INET_ESP is not set
288# CONFIG_INET_IPCOMP is not set
289CONFIG_INET_TUNNEL=m
290CONFIG_IP_TCPDIAG=m
291# CONFIG_IP_TCPDIAG_IPV6 is not set
292# CONFIG_IPV6 is not set
293# CONFIG_NETFILTER is not set
294CONFIG_XFRM=y
295CONFIG_XFRM_USER=m
296
297#
298# SCTP Configuration (EXPERIMENTAL)
299#
300# CONFIG_IP_SCTP is not set
301# CONFIG_ATM is not set
302# CONFIG_BRIDGE is not set
303# CONFIG_VLAN_8021Q is not set
304# CONFIG_DECNET is not set
305# CONFIG_LLC2 is not set
306# CONFIG_IPX is not set
307# CONFIG_ATALK is not set
308# CONFIG_X25 is not set
309# CONFIG_LAPB is not set
310# CONFIG_NET_DIVERT is not set
311# CONFIG_ECONET is not set
312# CONFIG_WAN_ROUTER is not set
313
314#
315# QoS and/or fair queueing
316#
317# CONFIG_NET_SCHED is not set
318# CONFIG_NET_CLS_ROUTE is not set
319
320#
321# Network testing
322# 390#
323# CONFIG_NET_PKTGEN is not set
324# CONFIG_NETPOLL is not set
325# CONFIG_NET_POLL_CONTROLLER is not set
326# CONFIG_HAMRADIO is not set
327# CONFIG_IRDA is not set
328# CONFIG_BT is not set
329CONFIG_NETDEVICES=y 391CONFIG_NETDEVICES=y
330# CONFIG_DUMMY is not set 392# CONFIG_DUMMY is not set
331# CONFIG_BONDING is not set 393# CONFIG_BONDING is not set
332# CONFIG_EQUALIZER is not set 394# CONFIG_EQUALIZER is not set
333# CONFIG_TUN is not set 395# CONFIG_TUN is not set
334# CONFIG_ETHERTAP is not set
335 396
336# 397#
337# ARCnet devices 398# ARCnet devices
@@ -339,12 +400,26 @@ CONFIG_NETDEVICES=y
339# CONFIG_ARCNET is not set 400# CONFIG_ARCNET is not set
340 401
341# 402#
403# PHY device support
404#
405CONFIG_PHYLIB=m
406CONFIG_PHYCONTROL=y
407
408#
409# MII PHY device drivers
410#
411CONFIG_MARVELL_PHY=m
412CONFIG_DAVICOM_PHY=m
413CONFIG_QSEMI_PHY=m
414CONFIG_LXT_PHY=m
415CONFIG_CICADA_PHY=m
416
417#
342# Ethernet (10 or 100Mbit) 418# Ethernet (10 or 100Mbit)
343# 419#
344CONFIG_NET_ETHERNET=y 420CONFIG_NET_ETHERNET=y
345# CONFIG_MII is not set 421# CONFIG_MII is not set
346# CONFIG_NET_VENDOR_3COM is not set 422# CONFIG_NET_VENDOR_3COM is not set
347# CONFIG_LANCE is not set
348# CONFIG_NET_VENDOR_SMC is not set 423# CONFIG_NET_VENDOR_SMC is not set
349# CONFIG_NET_VENDOR_RACAL is not set 424# CONFIG_NET_VENDOR_RACAL is not set
350# CONFIG_AT1700 is not set 425# CONFIG_AT1700 is not set
@@ -380,6 +455,8 @@ CONFIG_NET_ETHERNET=y
380# CONFIG_SLIP is not set 455# CONFIG_SLIP is not set
381# CONFIG_SHAPER is not set 456# CONFIG_SHAPER is not set
382# CONFIG_NETCONSOLE is not set 457# CONFIG_NETCONSOLE is not set
458# CONFIG_NETPOLL is not set
459# CONFIG_NET_POLL_CONTROLLER is not set
383 460
384# 461#
385# ISDN subsystem 462# ISDN subsystem
@@ -401,26 +478,14 @@ CONFIG_INPUT=y
401# 478#
402CONFIG_INPUT_MOUSEDEV=y 479CONFIG_INPUT_MOUSEDEV=y
403CONFIG_INPUT_MOUSEDEV_PSAUX=y 480CONFIG_INPUT_MOUSEDEV_PSAUX=y
404CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 481CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
405CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 482CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
406# CONFIG_INPUT_JOYDEV is not set 483# CONFIG_INPUT_JOYDEV is not set
407# CONFIG_INPUT_TSDEV is not set 484# CONFIG_INPUT_TSDEV is not set
408# CONFIG_INPUT_EVDEV is not set 485# CONFIG_INPUT_EVDEV is not set
409# CONFIG_INPUT_EVBUG is not set 486# CONFIG_INPUT_EVBUG is not set
410 487
411# 488#
412# Input I/O drivers
413#
414# CONFIG_GAMEPORT is not set
415CONFIG_SOUND_GAMEPORT=y
416CONFIG_SERIO=y
417CONFIG_SERIO_I8042=y
418CONFIG_SERIO_SERPORT=y
419# CONFIG_SERIO_CT82C710 is not set
420# CONFIG_SERIO_LIBPS2 is not set
421CONFIG_SERIO_RAW=m
422
423#
424# Input Device Drivers 489# Input Device Drivers
425# 490#
426# CONFIG_INPUT_KEYBOARD is not set 491# CONFIG_INPUT_KEYBOARD is not set
@@ -430,6 +495,16 @@ CONFIG_SERIO_RAW=m
430# CONFIG_INPUT_MISC is not set 495# CONFIG_INPUT_MISC is not set
431 496
432# 497#
498# Hardware I/O ports
499#
500CONFIG_SERIO=y
501# CONFIG_SERIO_I8042 is not set
502CONFIG_SERIO_SERPORT=y
503# CONFIG_SERIO_LIBPS2 is not set
504CONFIG_SERIO_RAW=m
505# CONFIG_GAMEPORT is not set
506
507#
433# Character devices 508# Character devices
434# 509#
435CONFIG_VT=y 510CONFIG_VT=y
@@ -440,16 +515,15 @@ CONFIG_HW_CONSOLE=y
440# 515#
441# Serial drivers 516# Serial drivers
442# 517#
443CONFIG_SERIAL_8250=y 518# CONFIG_SERIAL_8250 is not set
444CONFIG_SERIAL_8250_CONSOLE=y
445CONFIG_SERIAL_8250_NR_UARTS=4
446# CONFIG_SERIAL_8250_EXTENDED is not set
447 519
448# 520#
449# Non-8250 serial port support 521# Non-8250 serial port support
450# 522#
451CONFIG_SERIAL_CORE=y 523CONFIG_SERIAL_CORE=y
452CONFIG_SERIAL_CORE_CONSOLE=y 524CONFIG_SERIAL_CORE_CONSOLE=y
525CONFIG_SERIAL_VR41XX=y
526CONFIG_SERIAL_VR41XX_CONSOLE=y
453CONFIG_UNIX98_PTYS=y 527CONFIG_UNIX98_PTYS=y
454CONFIG_LEGACY_PTYS=y 528CONFIG_LEGACY_PTYS=y
455CONFIG_LEGACY_PTY_COUNT=256 529CONFIG_LEGACY_PTY_COUNT=256
@@ -484,10 +558,14 @@ CONFIG_WATCHDOG=y
484# 558#
485# Ftape, the floppy tape device driver 559# Ftape, the floppy tape device driver
486# 560#
487# CONFIG_DRM is not set 561CONFIG_GPIO_VR41XX=y
488# CONFIG_RAW_DRIVER is not set 562# CONFIG_RAW_DRIVER is not set
489 563
490# 564#
565# TPM devices
566#
567
568#
491# I2C support 569# I2C support
492# 570#
493# CONFIG_I2C is not set 571# CONFIG_I2C is not set
@@ -498,10 +576,20 @@ CONFIG_WATCHDOG=y
498# CONFIG_W1 is not set 576# CONFIG_W1 is not set
499 577
500# 578#
579# Hardware Monitoring support
580#
581# CONFIG_HWMON is not set
582# CONFIG_HWMON_VID is not set
583
584#
501# Misc devices 585# Misc devices
502# 586#
503 587
504# 588#
589# Multimedia Capabilities Port drivers
590#
591
592#
505# Multimedia devices 593# Multimedia devices
506# 594#
507# CONFIG_VIDEO_DEV is not set 595# CONFIG_VIDEO_DEV is not set
@@ -522,7 +610,6 @@ CONFIG_WATCHDOG=y
522# CONFIG_VGA_CONSOLE is not set 610# CONFIG_VGA_CONSOLE is not set
523# CONFIG_MDA_CONSOLE is not set 611# CONFIG_MDA_CONSOLE is not set
524CONFIG_DUMMY_CONSOLE=y 612CONFIG_DUMMY_CONSOLE=y
525# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
526 613
527# 614#
528# Sound 615# Sound
@@ -536,10 +623,6 @@ CONFIG_DUMMY_CONSOLE=y
536# CONFIG_USB_ARCH_HAS_OHCI is not set 623# CONFIG_USB_ARCH_HAS_OHCI is not set
537 624
538# 625#
539# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
540#
541
542#
543# USB Gadget Support 626# USB Gadget Support
544# 627#
545# CONFIG_USB_GADGET is not set 628# CONFIG_USB_GADGET is not set
@@ -552,24 +635,31 @@ CONFIG_DUMMY_CONSOLE=y
552# 635#
553# InfiniBand support 636# InfiniBand support
554# 637#
555# CONFIG_INFINIBAND is not set 638
639#
640# SN Devices
641#
556 642
557# 643#
558# File systems 644# File systems
559# 645#
560CONFIG_EXT2_FS=y 646CONFIG_EXT2_FS=y
561# CONFIG_EXT2_FS_XATTR is not set 647# CONFIG_EXT2_FS_XATTR is not set
648# CONFIG_EXT2_FS_XIP is not set
562# CONFIG_EXT3_FS is not set 649# CONFIG_EXT3_FS is not set
563# CONFIG_JBD is not set 650# CONFIG_JBD is not set
564# CONFIG_REISERFS_FS is not set 651# CONFIG_REISERFS_FS is not set
565# CONFIG_JFS_FS is not set 652# CONFIG_JFS_FS is not set
653# CONFIG_FS_POSIX_ACL is not set
566# CONFIG_XFS_FS is not set 654# CONFIG_XFS_FS is not set
567# CONFIG_MINIX_FS is not set 655# CONFIG_MINIX_FS is not set
568# CONFIG_ROMFS_FS is not set 656# CONFIG_ROMFS_FS is not set
657CONFIG_INOTIFY=y
569# CONFIG_QUOTA is not set 658# CONFIG_QUOTA is not set
570CONFIG_DNOTIFY=y 659CONFIG_DNOTIFY=y
571CONFIG_AUTOFS_FS=y 660CONFIG_AUTOFS_FS=y
572CONFIG_AUTOFS4_FS=y 661CONFIG_AUTOFS4_FS=y
662CONFIG_FUSE_FS=m
573 663
574# 664#
575# CD-ROM/DVD Filesystems 665# CD-ROM/DVD Filesystems
@@ -590,12 +680,10 @@ CONFIG_AUTOFS4_FS=y
590CONFIG_PROC_FS=y 680CONFIG_PROC_FS=y
591CONFIG_PROC_KCORE=y 681CONFIG_PROC_KCORE=y
592CONFIG_SYSFS=y 682CONFIG_SYSFS=y
593# CONFIG_DEVFS_FS is not set
594CONFIG_DEVPTS_FS_XATTR=y
595CONFIG_DEVPTS_FS_SECURITY=y
596# CONFIG_TMPFS is not set 683# CONFIG_TMPFS is not set
597# CONFIG_HUGETLB_PAGE is not set 684# CONFIG_HUGETLB_PAGE is not set
598CONFIG_RAMFS=y 685CONFIG_RAMFS=y
686CONFIG_RELAYFS_FS=m
599 687
600# 688#
601# Miscellaneous filesystems 689# Miscellaneous filesystems
@@ -617,16 +705,17 @@ CONFIG_RAMFS=y
617# 705#
618# Network File Systems 706# Network File Systems
619# 707#
620CONFIG_NFS_FS=y 708CONFIG_NFS_FS=m
621# CONFIG_NFS_V3 is not set 709# CONFIG_NFS_V3 is not set
622# CONFIG_NFS_V4 is not set 710# CONFIG_NFS_V4 is not set
623# CONFIG_NFS_DIRECTIO is not set 711# CONFIG_NFS_DIRECTIO is not set
624CONFIG_NFSD=y 712CONFIG_NFSD=m
625# CONFIG_NFSD_V3 is not set 713# CONFIG_NFSD_V3 is not set
626# CONFIG_NFSD_TCP is not set 714# CONFIG_NFSD_TCP is not set
627CONFIG_LOCKD=y 715CONFIG_LOCKD=m
628CONFIG_EXPORTFS=y 716CONFIG_EXPORTFS=m
629CONFIG_SUNRPC=y 717CONFIG_NFS_COMMON=y
718CONFIG_SUNRPC=m
630# CONFIG_RPCSEC_GSS_KRB5 is not set 719# CONFIG_RPCSEC_GSS_KRB5 is not set
631# CONFIG_RPCSEC_GSS_SPKM3 is not set 720# CONFIG_RPCSEC_GSS_SPKM3 is not set
632# CONFIG_SMB_FS is not set 721# CONFIG_SMB_FS is not set
@@ -634,6 +723,7 @@ CONFIG_SUNRPC=y
634# CONFIG_NCP_FS is not set 723# CONFIG_NCP_FS is not set
635# CONFIG_CODA_FS is not set 724# CONFIG_CODA_FS is not set
636# CONFIG_AFS_FS is not set 725# CONFIG_AFS_FS is not set
726# CONFIG_9P_FS is not set
637 727
638# 728#
639# Partition Types 729# Partition Types
@@ -654,9 +744,11 @@ CONFIG_MSDOS_PARTITION=y
654# 744#
655# Kernel hacking 745# Kernel hacking
656# 746#
747# CONFIG_PRINTK_TIME is not set
657# CONFIG_DEBUG_KERNEL is not set 748# CONFIG_DEBUG_KERNEL is not set
749CONFIG_LOG_BUF_SHIFT=14
658CONFIG_CROSSCOMPILE=y 750CONFIG_CROSSCOMPILE=y
659CONFIG_CMDLINE="" 751CONFIG_CMDLINE="console=ttyVR0,19200 mem=8M"
660 752
661# 753#
662# Security options 754# Security options
@@ -668,7 +760,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
668# 760#
669# Cryptographic options 761# Cryptographic options
670# 762#
671# CONFIG_CRYPTO is not set 763CONFIG_CRYPTO=y
764CONFIG_CRYPTO_HMAC=y
765CONFIG_CRYPTO_NULL=m
766CONFIG_CRYPTO_MD4=m
767CONFIG_CRYPTO_MD5=m
768CONFIG_CRYPTO_SHA1=m
769CONFIG_CRYPTO_SHA256=m
770CONFIG_CRYPTO_SHA512=m
771CONFIG_CRYPTO_WP512=m
772CONFIG_CRYPTO_TGR192=m
773CONFIG_CRYPTO_DES=m
774CONFIG_CRYPTO_BLOWFISH=m
775CONFIG_CRYPTO_TWOFISH=m
776CONFIG_CRYPTO_SERPENT=m
777CONFIG_CRYPTO_AES=m
778CONFIG_CRYPTO_CAST5=m
779CONFIG_CRYPTO_CAST6=m
780CONFIG_CRYPTO_TEA=m
781CONFIG_CRYPTO_ARC4=m
782CONFIG_CRYPTO_KHAZAD=m
783CONFIG_CRYPTO_ANUBIS=m
784CONFIG_CRYPTO_DEFLATE=m
785CONFIG_CRYPTO_MICHAEL_MIC=m
786CONFIG_CRYPTO_CRC32C=m
787# CONFIG_CRYPTO_TEST is not set
672 788
673# 789#
674# Hardware crypto devices 790# Hardware crypto devices
@@ -678,7 +794,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
678# Library routines 794# Library routines
679# 795#
680# CONFIG_CRC_CCITT is not set 796# CONFIG_CRC_CCITT is not set
681# CONFIG_CRC32 is not set 797CONFIG_CRC16=m
798CONFIG_CRC32=m
682CONFIG_LIBCRC32C=m 799CONFIG_LIBCRC32C=m
683CONFIG_GENERIC_HARDIRQS=y 800CONFIG_ZLIB_INFLATE=m
684CONFIG_GENERIC_IRQ_PROBE=y 801CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig
index 17e87f70f602..f1309d84d2fe 100644
--- a/arch/mips/configs/ev64120_defconfig
+++ b/arch/mips/configs/ev64120_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:03 2005 4# Thu Oct 20 22:25:54 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,41 +59,69 @@ CONFIG_MODULE_SRCVERSION_ALL=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64CONFIG_MIPS_EV64120=y 77CONFIG_MIPS_EV64120=y
65# CONFIG_EVB_PCI1 is not set
66# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
67# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
68# CONFIG_LASAT is not set
69# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
70# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
71# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
72# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
73# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
74# CONFIG_MOMENCO_OCELOT_G is not set
75# CONFIG_MOMENCO_OCELOT_C is not set
76# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
77# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
78# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
79# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
80# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
81# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
82# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
83# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
84# CONFIG_SOC_AU1X00 is not set 102# CONFIG_SGI_IP27 is not set
85# CONFIG_SIBYTE_SB1xxx_SOC is not set 103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
86# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
87# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
117# CONFIG_EVB_PCI1 is not set
88CONFIG_RWSEM_GENERIC_SPINLOCK=y 118CONFIG_RWSEM_GENERIC_SPINLOCK=y
89CONFIG_GENERIC_CALIBRATE_DELAY=y 119CONFIG_GENERIC_CALIBRATE_DELAY=y
90CONFIG_HAVE_DEC_LOCK=y
91CONFIG_DMA_NONCOHERENT=y 120CONFIG_DMA_NONCOHERENT=y
92CONFIG_DMA_NEED_PCI_MAP_STATE=y 121CONFIG_DMA_NEED_PCI_MAP_STATE=y
122CONFIG_CPU_BIG_ENDIAN=y
93# CONFIG_CPU_LITTLE_ENDIAN is not set 123# CONFIG_CPU_LITTLE_ENDIAN is not set
124CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
94CONFIG_MIPS_GT64120=y 125CONFIG_MIPS_GT64120=y
95# CONFIG_SYSCLK_75 is not set 126# CONFIG_SYSCLK_75 is not set
96# CONFIG_SYSCLK_83 is not set 127# CONFIG_SYSCLK_83 is not set
@@ -100,8 +131,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
100# 131#
101# CPU selection 132# CPU selection
102# 133#
103# CONFIG_CPU_MIPS32 is not set 134# CONFIG_CPU_MIPS32_R1 is not set
104# CONFIG_CPU_MIPS64 is not set 135# CONFIG_CPU_MIPS32_R2 is not set
136# CONFIG_CPU_MIPS64_R1 is not set
137# CONFIG_CPU_MIPS64_R2 is not set
105# CONFIG_CPU_R3000 is not set 138# CONFIG_CPU_R3000 is not set
106# CONFIG_CPU_TX39XX is not set 139# CONFIG_CPU_TX39XX is not set
107# CONFIG_CPU_VR41XX is not set 140# CONFIG_CPU_VR41XX is not set
@@ -117,15 +150,39 @@ CONFIG_CPU_R5000=y
117# CONFIG_CPU_RM7000 is not set 150# CONFIG_CPU_RM7000 is not set
118# CONFIG_CPU_RM9000 is not set 151# CONFIG_CPU_RM9000 is not set
119# CONFIG_CPU_SB1 is not set 152# CONFIG_CPU_SB1 is not set
153CONFIG_SYS_HAS_CPU_R5000=y
154CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
155CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
156CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
157CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
158
159#
160# Kernel type
161#
162CONFIG_32BIT=y
163# CONFIG_64BIT is not set
120CONFIG_PAGE_SIZE_4KB=y 164CONFIG_PAGE_SIZE_4KB=y
121# CONFIG_PAGE_SIZE_8KB is not set 165# CONFIG_PAGE_SIZE_8KB is not set
122# CONFIG_PAGE_SIZE_16KB is not set 166# CONFIG_PAGE_SIZE_16KB is not set
123# CONFIG_PAGE_SIZE_64KB is not set 167# CONFIG_PAGE_SIZE_64KB is not set
168# CONFIG_MIPS_MT is not set
124# CONFIG_64BIT_PHYS_ADDR is not set 169# CONFIG_64BIT_PHYS_ADDR is not set
125# CONFIG_CPU_ADVANCED is not set 170# CONFIG_CPU_ADVANCED is not set
126CONFIG_CPU_HAS_LLSC=y 171CONFIG_CPU_HAS_LLSC=y
127CONFIG_CPU_HAS_LLDSCD=y 172CONFIG_CPU_HAS_LLDSCD=y
128CONFIG_CPU_HAS_SYNC=y 173CONFIG_CPU_HAS_SYNC=y
174CONFIG_GENERIC_HARDIRQS=y
175CONFIG_GENERIC_IRQ_PROBE=y
176CONFIG_ARCH_FLATMEM_ENABLE=y
177CONFIG_SELECT_MEMORY_MODEL=y
178CONFIG_FLATMEM_MANUAL=y
179# CONFIG_DISCONTIGMEM_MANUAL is not set
180# CONFIG_SPARSEMEM_MANUAL is not set
181CONFIG_FLATMEM=y
182CONFIG_FLAT_NODE_MEM_MAP=y
183# CONFIG_SPARSEMEM_STATIC is not set
184CONFIG_PREEMPT_NONE=y
185# CONFIG_PREEMPT_VOLUNTARY is not set
129# CONFIG_PREEMPT is not set 186# CONFIG_PREEMPT is not set
130 187
131# 188#
@@ -134,7 +191,6 @@ CONFIG_CPU_HAS_SYNC=y
134CONFIG_HW_HAS_PCI=y 191CONFIG_HW_HAS_PCI=y
135CONFIG_PCI=y 192CONFIG_PCI=y
136CONFIG_PCI_LEGACY_PROC=y 193CONFIG_PCI_LEGACY_PROC=y
137CONFIG_PCI_NAMES=y
138CONFIG_MMU=y 194CONFIG_MMU=y
139 195
140# 196#
@@ -143,10 +199,6 @@ CONFIG_MMU=y
143# CONFIG_PCCARD is not set 199# CONFIG_PCCARD is not set
144 200
145# 201#
146# PC-card bridges
147#
148
149#
150# PCI Hotplug Support 202# PCI Hotplug Support
151# 203#
152# CONFIG_HOTPLUG_PCI is not set 204# CONFIG_HOTPLUG_PCI is not set
@@ -159,6 +211,79 @@ CONFIG_BINFMT_ELF=y
159CONFIG_TRAD_SIGNALS=y 211CONFIG_TRAD_SIGNALS=y
160 212
161# 213#
214# Networking
215#
216CONFIG_NET=y
217
218#
219# Networking options
220#
221# CONFIG_PACKET is not set
222CONFIG_UNIX=y
223CONFIG_XFRM=y
224CONFIG_XFRM_USER=m
225CONFIG_NET_KEY=y
226CONFIG_INET=y
227# CONFIG_IP_MULTICAST is not set
228# CONFIG_IP_ADVANCED_ROUTER is not set
229CONFIG_IP_FIB_HASH=y
230CONFIG_IP_PNP=y
231# CONFIG_IP_PNP_DHCP is not set
232# CONFIG_IP_PNP_BOOTP is not set
233# CONFIG_IP_PNP_RARP is not set
234# CONFIG_NET_IPIP is not set
235# CONFIG_NET_IPGRE is not set
236# CONFIG_ARPD is not set
237# CONFIG_SYN_COOKIES is not set
238# CONFIG_INET_AH is not set
239# CONFIG_INET_ESP is not set
240# CONFIG_INET_IPCOMP is not set
241CONFIG_INET_TUNNEL=m
242CONFIG_INET_DIAG=y
243CONFIG_INET_TCP_DIAG=y
244# CONFIG_TCP_CONG_ADVANCED is not set
245CONFIG_TCP_CONG_BIC=y
246# CONFIG_IPV6 is not set
247# CONFIG_NETFILTER is not set
248
249#
250# DCCP Configuration (EXPERIMENTAL)
251#
252# CONFIG_IP_DCCP is not set
253
254#
255# SCTP Configuration (EXPERIMENTAL)
256#
257# CONFIG_IP_SCTP is not set
258# CONFIG_ATM is not set
259# CONFIG_BRIDGE is not set
260# CONFIG_VLAN_8021Q is not set
261# CONFIG_DECNET is not set
262# CONFIG_LLC2 is not set
263# CONFIG_IPX is not set
264# CONFIG_ATALK is not set
265# CONFIG_X25 is not set
266# CONFIG_LAPB is not set
267# CONFIG_NET_DIVERT is not set
268# CONFIG_ECONET is not set
269# CONFIG_WAN_ROUTER is not set
270# CONFIG_NET_SCHED is not set
271# CONFIG_NET_CLS_ROUTE is not set
272
273#
274# Network testing
275#
276# CONFIG_NET_PKTGEN is not set
277# CONFIG_HAMRADIO is not set
278# CONFIG_IRDA is not set
279# CONFIG_BT is not set
280CONFIG_IEEE80211=m
281# CONFIG_IEEE80211_DEBUG is not set
282CONFIG_IEEE80211_CRYPT_WEP=m
283CONFIG_IEEE80211_CRYPT_CCMP=m
284CONFIG_IEEE80211_CRYPT_TKIP=m
285
286#
162# Device Drivers 287# Device Drivers
163# 288#
164 289
@@ -167,7 +292,12 @@ CONFIG_TRAD_SIGNALS=y
167# 292#
168CONFIG_STANDALONE=y 293CONFIG_STANDALONE=y
169CONFIG_PREVENT_FIRMWARE_BUILD=y 294CONFIG_PREVENT_FIRMWARE_BUILD=y
170# CONFIG_FW_LOADER is not set 295CONFIG_FW_LOADER=m
296
297#
298# Connector - unified userspace <-> kernelspace linker
299#
300CONFIG_CONNECTOR=m
171 301
172# 302#
173# Memory Technology Devices (MTD) 303# Memory Technology Devices (MTD)
@@ -186,7 +316,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
186# 316#
187# Block devices 317# Block devices
188# 318#
189# CONFIG_BLK_DEV_FD is not set
190# CONFIG_BLK_CPQ_DA is not set 319# CONFIG_BLK_CPQ_DA is not set
191# CONFIG_BLK_CPQ_CISS_DA is not set 320# CONFIG_BLK_CPQ_CISS_DA is not set
192# CONFIG_BLK_DEV_DAC960 is not set 321# CONFIG_BLK_DEV_DAC960 is not set
@@ -197,7 +326,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
197# CONFIG_BLK_DEV_SX8 is not set 326# CONFIG_BLK_DEV_SX8 is not set
198# CONFIG_BLK_DEV_RAM is not set 327# CONFIG_BLK_DEV_RAM is not set
199CONFIG_BLK_DEV_RAM_COUNT=16 328CONFIG_BLK_DEV_RAM_COUNT=16
200CONFIG_INITRAMFS_SOURCE=""
201# CONFIG_LBD is not set 329# CONFIG_LBD is not set
202CONFIG_CDROM_PKTCDVD=m 330CONFIG_CDROM_PKTCDVD=m
203CONFIG_CDROM_PKTCDVD_BUFFERS=8 331CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -220,6 +348,7 @@ CONFIG_ATA_OVER_ETH=m
220# 348#
221# SCSI device support 349# SCSI device support
222# 350#
351CONFIG_RAID_ATTRS=m
223# CONFIG_SCSI is not set 352# CONFIG_SCSI is not set
224 353
225# 354#
@@ -230,6 +359,7 @@ CONFIG_ATA_OVER_ETH=m
230# 359#
231# Fusion MPT device support 360# Fusion MPT device support
232# 361#
362# CONFIG_FUSION is not set
233 363
234# 364#
235# IEEE 1394 (FireWire) support 365# IEEE 1394 (FireWire) support
@@ -242,77 +372,13 @@ CONFIG_ATA_OVER_ETH=m
242# CONFIG_I2O is not set 372# CONFIG_I2O is not set
243 373
244# 374#
245# Networking support 375# Network device support
246#
247CONFIG_NET=y
248
249#
250# Networking options
251#
252# CONFIG_PACKET is not set
253CONFIG_NETLINK_DEV=y
254CONFIG_UNIX=y
255CONFIG_NET_KEY=y
256CONFIG_INET=y
257# CONFIG_IP_MULTICAST is not set
258# CONFIG_IP_ADVANCED_ROUTER is not set
259CONFIG_IP_PNP=y
260# CONFIG_IP_PNP_DHCP is not set
261# CONFIG_IP_PNP_BOOTP is not set
262# CONFIG_IP_PNP_RARP is not set
263# CONFIG_NET_IPIP is not set
264# CONFIG_NET_IPGRE is not set
265# CONFIG_ARPD is not set
266# CONFIG_SYN_COOKIES is not set
267# CONFIG_INET_AH is not set
268# CONFIG_INET_ESP is not set
269# CONFIG_INET_IPCOMP is not set
270CONFIG_INET_TUNNEL=m
271CONFIG_IP_TCPDIAG=m
272# CONFIG_IP_TCPDIAG_IPV6 is not set
273# CONFIG_IPV6 is not set
274# CONFIG_NETFILTER is not set
275CONFIG_XFRM=y
276CONFIG_XFRM_USER=m
277
278#
279# SCTP Configuration (EXPERIMENTAL)
280# 376#
281# CONFIG_IP_SCTP is not set
282# CONFIG_ATM is not set
283# CONFIG_BRIDGE is not set
284# CONFIG_VLAN_8021Q is not set
285# CONFIG_DECNET is not set
286# CONFIG_LLC2 is not set
287# CONFIG_IPX is not set
288# CONFIG_ATALK is not set
289# CONFIG_X25 is not set
290# CONFIG_LAPB is not set
291# CONFIG_NET_DIVERT is not set
292# CONFIG_ECONET is not set
293# CONFIG_WAN_ROUTER is not set
294
295#
296# QoS and/or fair queueing
297#
298# CONFIG_NET_SCHED is not set
299# CONFIG_NET_CLS_ROUTE is not set
300
301#
302# Network testing
303#
304# CONFIG_NET_PKTGEN is not set
305# CONFIG_NETPOLL is not set
306# CONFIG_NET_POLL_CONTROLLER is not set
307# CONFIG_HAMRADIO is not set
308# CONFIG_IRDA is not set
309# CONFIG_BT is not set
310CONFIG_NETDEVICES=y 377CONFIG_NETDEVICES=y
311# CONFIG_DUMMY is not set 378# CONFIG_DUMMY is not set
312# CONFIG_BONDING is not set 379# CONFIG_BONDING is not set
313# CONFIG_EQUALIZER is not set 380# CONFIG_EQUALIZER is not set
314# CONFIG_TUN is not set 381# CONFIG_TUN is not set
315# CONFIG_ETHERTAP is not set
316 382
317# 383#
318# ARCnet devices 384# ARCnet devices
@@ -320,6 +386,21 @@ CONFIG_NETDEVICES=y
320# CONFIG_ARCNET is not set 386# CONFIG_ARCNET is not set
321 387
322# 388#
389# PHY device support
390#
391CONFIG_PHYLIB=m
392CONFIG_PHYCONTROL=y
393
394#
395# MII PHY device drivers
396#
397CONFIG_MARVELL_PHY=m
398CONFIG_DAVICOM_PHY=m
399CONFIG_QSEMI_PHY=m
400CONFIG_LXT_PHY=m
401CONFIG_CICADA_PHY=m
402
403#
323# Ethernet (10 or 100Mbit) 404# Ethernet (10 or 100Mbit)
324# 405#
325CONFIG_NET_ETHERNET=y 406CONFIG_NET_ETHERNET=y
@@ -345,12 +426,16 @@ CONFIG_NET_ETHERNET=y
345# CONFIG_HAMACHI is not set 426# CONFIG_HAMACHI is not set
346# CONFIG_YELLOWFIN is not set 427# CONFIG_YELLOWFIN is not set
347# CONFIG_R8169 is not set 428# CONFIG_R8169 is not set
429# CONFIG_SIS190 is not set
430# CONFIG_SKGE is not set
348# CONFIG_SK98LIN is not set 431# CONFIG_SK98LIN is not set
349# CONFIG_TIGON3 is not set 432# CONFIG_TIGON3 is not set
433# CONFIG_BNX2 is not set
350 434
351# 435#
352# Ethernet (10000 Mbit) 436# Ethernet (10000 Mbit)
353# 437#
438# CONFIG_CHELSIO_T1 is not set
354# CONFIG_IXGB is not set 439# CONFIG_IXGB is not set
355# CONFIG_S2IO is not set 440# CONFIG_S2IO is not set
356 441
@@ -363,6 +448,8 @@ CONFIG_NET_ETHERNET=y
363# Wireless LAN (non-hamradio) 448# Wireless LAN (non-hamradio)
364# 449#
365# CONFIG_NET_RADIO is not set 450# CONFIG_NET_RADIO is not set
451# CONFIG_IPW_DEBUG is not set
452CONFIG_IPW2200=m
366 453
367# 454#
368# Wan interfaces 455# Wan interfaces
@@ -381,6 +468,8 @@ CONFIG_PPP_ASYNC=y
381# CONFIG_SLIP is not set 468# CONFIG_SLIP is not set
382# CONFIG_SHAPER is not set 469# CONFIG_SHAPER is not set
383# CONFIG_NETCONSOLE is not set 470# CONFIG_NETCONSOLE is not set
471# CONFIG_NETPOLL is not set
472# CONFIG_NET_POLL_CONTROLLER is not set
384 473
385# 474#
386# ISDN subsystem 475# ISDN subsystem
@@ -410,19 +499,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
410# CONFIG_INPUT_EVBUG is not set 499# CONFIG_INPUT_EVBUG is not set
411 500
412# 501#
413# Input I/O drivers
414#
415# CONFIG_GAMEPORT is not set
416CONFIG_SOUND_GAMEPORT=y
417CONFIG_SERIO=y
418# CONFIG_SERIO_I8042 is not set
419CONFIG_SERIO_SERPORT=y
420# CONFIG_SERIO_CT82C710 is not set
421# CONFIG_SERIO_PCIPS2 is not set
422# CONFIG_SERIO_LIBPS2 is not set
423CONFIG_SERIO_RAW=m
424
425#
426# Input Device Drivers 502# Input Device Drivers
427# 503#
428# CONFIG_INPUT_KEYBOARD is not set 504# CONFIG_INPUT_KEYBOARD is not set
@@ -432,6 +508,17 @@ CONFIG_SERIO_RAW=m
432# CONFIG_INPUT_MISC is not set 508# CONFIG_INPUT_MISC is not set
433 509
434# 510#
511# Hardware I/O ports
512#
513CONFIG_SERIO=y
514# CONFIG_SERIO_I8042 is not set
515CONFIG_SERIO_SERPORT=y
516# CONFIG_SERIO_PCIPS2 is not set
517# CONFIG_SERIO_LIBPS2 is not set
518CONFIG_SERIO_RAW=m
519# CONFIG_GAMEPORT is not set
520
521#
435# Character devices 522# Character devices
436# 523#
437CONFIG_VT=y 524CONFIG_VT=y
@@ -452,6 +539,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
452# 539#
453CONFIG_SERIAL_CORE=y 540CONFIG_SERIAL_CORE=y
454CONFIG_SERIAL_CORE_CONSOLE=y 541CONFIG_SERIAL_CORE_CONSOLE=y
542# CONFIG_SERIAL_JSM is not set
455CONFIG_UNIX98_PTYS=y 543CONFIG_UNIX98_PTYS=y
456CONFIG_LEGACY_PTYS=y 544CONFIG_LEGACY_PTYS=y
457CONFIG_LEGACY_PTY_COUNT=256 545CONFIG_LEGACY_PTY_COUNT=256
@@ -478,6 +566,11 @@ CONFIG_LEGACY_PTY_COUNT=256
478# CONFIG_RAW_DRIVER is not set 566# CONFIG_RAW_DRIVER is not set
479 567
480# 568#
569# TPM devices
570#
571# CONFIG_TCG_TPM is not set
572
573#
481# I2C support 574# I2C support
482# 575#
483# CONFIG_I2C is not set 576# CONFIG_I2C is not set
@@ -488,10 +581,20 @@ CONFIG_LEGACY_PTY_COUNT=256
488# CONFIG_W1 is not set 581# CONFIG_W1 is not set
489 582
490# 583#
584# Hardware Monitoring support
585#
586# CONFIG_HWMON is not set
587# CONFIG_HWMON_VID is not set
588
589#
491# Misc devices 590# Misc devices
492# 591#
493 592
494# 593#
594# Multimedia Capabilities Port drivers
595#
596
597#
495# Multimedia devices 598# Multimedia devices
496# 599#
497# CONFIG_VIDEO_DEV is not set 600# CONFIG_VIDEO_DEV is not set
@@ -511,7 +614,6 @@ CONFIG_LEGACY_PTY_COUNT=256
511# 614#
512# CONFIG_VGA_CONSOLE is not set 615# CONFIG_VGA_CONSOLE is not set
513CONFIG_DUMMY_CONSOLE=y 616CONFIG_DUMMY_CONSOLE=y
514# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
515 617
516# 618#
517# Sound 619# Sound
@@ -521,13 +623,9 @@ CONFIG_DUMMY_CONSOLE=y
521# 623#
522# USB support 624# USB support
523# 625#
524# CONFIG_USB is not set
525CONFIG_USB_ARCH_HAS_HCD=y 626CONFIG_USB_ARCH_HAS_HCD=y
526CONFIG_USB_ARCH_HAS_OHCI=y 627CONFIG_USB_ARCH_HAS_OHCI=y
527 628# CONFIG_USB is not set
528#
529# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
530#
531 629
532# 630#
533# USB Gadget Support 631# USB Gadget Support
@@ -545,21 +643,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y
545# CONFIG_INFINIBAND is not set 643# CONFIG_INFINIBAND is not set
546 644
547# 645#
646# SN Devices
647#
648
649#
548# File systems 650# File systems
549# 651#
550CONFIG_EXT2_FS=y 652CONFIG_EXT2_FS=y
551# CONFIG_EXT2_FS_XATTR is not set 653# CONFIG_EXT2_FS_XATTR is not set
654# CONFIG_EXT2_FS_XIP is not set
552# CONFIG_EXT3_FS is not set 655# CONFIG_EXT3_FS is not set
553# CONFIG_JBD is not set 656# CONFIG_JBD is not set
554# CONFIG_REISERFS_FS is not set 657# CONFIG_REISERFS_FS is not set
555# CONFIG_JFS_FS is not set 658# CONFIG_JFS_FS is not set
659# CONFIG_FS_POSIX_ACL is not set
556# CONFIG_XFS_FS is not set 660# CONFIG_XFS_FS is not set
557# CONFIG_MINIX_FS is not set 661# CONFIG_MINIX_FS is not set
558# CONFIG_ROMFS_FS is not set 662# CONFIG_ROMFS_FS is not set
663CONFIG_INOTIFY=y
559# CONFIG_QUOTA is not set 664# CONFIG_QUOTA is not set
560CONFIG_DNOTIFY=y 665CONFIG_DNOTIFY=y
561# CONFIG_AUTOFS_FS is not set 666# CONFIG_AUTOFS_FS is not set
562# CONFIG_AUTOFS4_FS is not set 667# CONFIG_AUTOFS4_FS is not set
668CONFIG_FUSE_FS=m
563 669
564# 670#
565# CD-ROM/DVD Filesystems 671# CD-ROM/DVD Filesystems
@@ -580,12 +686,10 @@ CONFIG_DNOTIFY=y
580CONFIG_PROC_FS=y 686CONFIG_PROC_FS=y
581CONFIG_PROC_KCORE=y 687CONFIG_PROC_KCORE=y
582CONFIG_SYSFS=y 688CONFIG_SYSFS=y
583# CONFIG_DEVFS_FS is not set
584CONFIG_DEVPTS_FS_XATTR=y
585CONFIG_DEVPTS_FS_SECURITY=y
586# CONFIG_TMPFS is not set 689# CONFIG_TMPFS is not set
587# CONFIG_HUGETLB_PAGE is not set 690# CONFIG_HUGETLB_PAGE is not set
588CONFIG_RAMFS=y 691CONFIG_RAMFS=y
692CONFIG_RELAYFS_FS=m
589 693
590# 694#
591# Miscellaneous filesystems 695# Miscellaneous filesystems
@@ -614,7 +718,7 @@ CONFIG_NFS_FS=y
614# CONFIG_NFSD is not set 718# CONFIG_NFSD is not set
615CONFIG_ROOT_NFS=y 719CONFIG_ROOT_NFS=y
616CONFIG_LOCKD=y 720CONFIG_LOCKD=y
617# CONFIG_EXPORTFS is not set 721CONFIG_NFS_COMMON=y
618CONFIG_SUNRPC=y 722CONFIG_SUNRPC=y
619# CONFIG_RPCSEC_GSS_KRB5 is not set 723# CONFIG_RPCSEC_GSS_KRB5 is not set
620# CONFIG_RPCSEC_GSS_SPKM3 is not set 724# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -623,6 +727,7 @@ CONFIG_SUNRPC=y
623# CONFIG_NCP_FS is not set 727# CONFIG_NCP_FS is not set
624# CONFIG_CODA_FS is not set 728# CONFIG_CODA_FS is not set
625# CONFIG_AFS_FS is not set 729# CONFIG_AFS_FS is not set
730# CONFIG_9P_FS is not set
626 731
627# 732#
628# Partition Types 733# Partition Types
@@ -643,7 +748,9 @@ CONFIG_MSDOS_PARTITION=y
643# 748#
644# Kernel hacking 749# Kernel hacking
645# 750#
751# CONFIG_PRINTK_TIME is not set
646# CONFIG_DEBUG_KERNEL is not set 752# CONFIG_DEBUG_KERNEL is not set
753CONFIG_LOG_BUF_SHIFT=14
647CONFIG_CROSSCOMPILE=y 754CONFIG_CROSSCOMPILE=y
648CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw nfsroot=192.168.1.1:/mnt/disk2/fs.gal ip=192.168.1.211:192.168.1.1:::gt::" 755CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw nfsroot=192.168.1.1:/mnt/disk2/fs.gal ip=192.168.1.211:192.168.1.1:::gt::"
649 756
@@ -657,7 +764,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
657# 764#
658# Cryptographic options 765# Cryptographic options
659# 766#
660# CONFIG_CRYPTO is not set 767CONFIG_CRYPTO=y
768CONFIG_CRYPTO_HMAC=y
769CONFIG_CRYPTO_NULL=m
770CONFIG_CRYPTO_MD4=m
771CONFIG_CRYPTO_MD5=m
772CONFIG_CRYPTO_SHA1=m
773CONFIG_CRYPTO_SHA256=m
774CONFIG_CRYPTO_SHA512=m
775CONFIG_CRYPTO_WP512=m
776CONFIG_CRYPTO_TGR192=m
777CONFIG_CRYPTO_DES=m
778CONFIG_CRYPTO_BLOWFISH=m
779CONFIG_CRYPTO_TWOFISH=m
780CONFIG_CRYPTO_SERPENT=m
781CONFIG_CRYPTO_AES=m
782CONFIG_CRYPTO_CAST5=m
783CONFIG_CRYPTO_CAST6=m
784CONFIG_CRYPTO_TEA=m
785CONFIG_CRYPTO_ARC4=m
786CONFIG_CRYPTO_KHAZAD=m
787CONFIG_CRYPTO_ANUBIS=m
788CONFIG_CRYPTO_DEFLATE=m
789CONFIG_CRYPTO_MICHAEL_MIC=m
790CONFIG_CRYPTO_CRC32C=m
791# CONFIG_CRYPTO_TEST is not set
661 792
662# 793#
663# Hardware crypto devices 794# Hardware crypto devices
@@ -667,7 +798,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
667# Library routines 798# Library routines
668# 799#
669CONFIG_CRC_CCITT=y 800CONFIG_CRC_CCITT=y
670# CONFIG_CRC32 is not set 801CONFIG_CRC16=m
802CONFIG_CRC32=m
671CONFIG_LIBCRC32C=m 803CONFIG_LIBCRC32C=m
672CONFIG_GENERIC_HARDIRQS=y 804CONFIG_ZLIB_INFLATE=m
673CONFIG_GENERIC_IRQ_PROBE=y 805CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/configs/ev96100_defconfig b/arch/mips/configs/ev96100_defconfig
index 9da4140eae00..8ac55b7acc01 100644
--- a/arch/mips/configs/ev96100_defconfig
+++ b/arch/mips/configs/ev96100_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:03 2005 4# Thu Oct 20 22:25:57 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29# CONFIG_HOTPLUG is not set 27# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,40 +59,68 @@ CONFIG_MODULE_SRCVERSION_ALL=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
65CONFIG_MIPS_EV96100=y 78CONFIG_MIPS_EV96100=y
66# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
83# CONFIG_SOC_AU1X00 is not set 102# CONFIG_SGI_IP27 is not set
84# CONFIG_SIBYTE_SB1xxx_SOC is not set 103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
85# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
86# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
87CONFIG_RWSEM_GENERIC_SPINLOCK=y 117CONFIG_RWSEM_GENERIC_SPINLOCK=y
88CONFIG_GENERIC_CALIBRATE_DELAY=y 118CONFIG_GENERIC_CALIBRATE_DELAY=y
89CONFIG_HAVE_DEC_LOCK=y
90CONFIG_DMA_NONCOHERENT=y 119CONFIG_DMA_NONCOHERENT=y
91CONFIG_DMA_NEED_PCI_MAP_STATE=y 120CONFIG_DMA_NEED_PCI_MAP_STATE=y
121CONFIG_CPU_BIG_ENDIAN=y
92# CONFIG_CPU_LITTLE_ENDIAN is not set 122# CONFIG_CPU_LITTLE_ENDIAN is not set
123CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
93CONFIG_IRQ_CPU=y 124CONFIG_IRQ_CPU=y
94CONFIG_MIPS_GT64120=y 125CONFIG_MIPS_GT64120=y
95CONFIG_SWAP_IO_SPACE=y 126CONFIG_SWAP_IO_SPACE=y
@@ -99,8 +130,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
99# 130#
100# CPU selection 131# CPU selection
101# 132#
102# CONFIG_CPU_MIPS32 is not set 133# CONFIG_CPU_MIPS32_R1 is not set
103# CONFIG_CPU_MIPS64 is not set 134# CONFIG_CPU_MIPS32_R2 is not set
135# CONFIG_CPU_MIPS64_R1 is not set
136# CONFIG_CPU_MIPS64_R2 is not set
104# CONFIG_CPU_R3000 is not set 137# CONFIG_CPU_R3000 is not set
105# CONFIG_CPU_TX39XX is not set 138# CONFIG_CPU_TX39XX is not set
106# CONFIG_CPU_VR41XX is not set 139# CONFIG_CPU_VR41XX is not set
@@ -116,6 +149,18 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
116CONFIG_CPU_RM7000=y 149CONFIG_CPU_RM7000=y
117# CONFIG_CPU_RM9000 is not set 150# CONFIG_CPU_RM9000 is not set
118# CONFIG_CPU_SB1 is not set 151# CONFIG_CPU_SB1 is not set
152CONFIG_SYS_HAS_CPU_R5000=y
153CONFIG_SYS_HAS_CPU_RM7000=y
154CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
155CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
156CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
157CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
158
159#
160# Kernel type
161#
162CONFIG_32BIT=y
163# CONFIG_64BIT is not set
119CONFIG_PAGE_SIZE_4KB=y 164CONFIG_PAGE_SIZE_4KB=y
120# CONFIG_PAGE_SIZE_8KB is not set 165# CONFIG_PAGE_SIZE_8KB is not set
121# CONFIG_PAGE_SIZE_16KB is not set 166# CONFIG_PAGE_SIZE_16KB is not set
@@ -123,11 +168,25 @@ CONFIG_PAGE_SIZE_4KB=y
123CONFIG_BOARD_SCACHE=y 168CONFIG_BOARD_SCACHE=y
124CONFIG_RM7000_CPU_SCACHE=y 169CONFIG_RM7000_CPU_SCACHE=y
125CONFIG_CPU_HAS_PREFETCH=y 170CONFIG_CPU_HAS_PREFETCH=y
171# CONFIG_MIPS_MT is not set
126# CONFIG_64BIT_PHYS_ADDR is not set 172# CONFIG_64BIT_PHYS_ADDR is not set
127# CONFIG_CPU_ADVANCED is not set 173# CONFIG_CPU_ADVANCED is not set
128CONFIG_CPU_HAS_LLSC=y 174CONFIG_CPU_HAS_LLSC=y
129CONFIG_CPU_HAS_LLDSCD=y 175CONFIG_CPU_HAS_LLDSCD=y
130CONFIG_CPU_HAS_SYNC=y 176CONFIG_CPU_HAS_SYNC=y
177CONFIG_GENERIC_HARDIRQS=y
178CONFIG_GENERIC_IRQ_PROBE=y
179CONFIG_CPU_SUPPORTS_HIGHMEM=y
180CONFIG_ARCH_FLATMEM_ENABLE=y
181CONFIG_SELECT_MEMORY_MODEL=y
182CONFIG_FLATMEM_MANUAL=y
183# CONFIG_DISCONTIGMEM_MANUAL is not set
184# CONFIG_SPARSEMEM_MANUAL is not set
185CONFIG_FLATMEM=y
186CONFIG_FLAT_NODE_MEM_MAP=y
187# CONFIG_SPARSEMEM_STATIC is not set
188CONFIG_PREEMPT_NONE=y
189# CONFIG_PREEMPT_VOLUNTARY is not set
131# CONFIG_PREEMPT is not set 190# CONFIG_PREEMPT is not set
132 191
133# 192#
@@ -143,10 +202,6 @@ CONFIG_MMU=y
143# CONFIG_PCCARD is not set 202# CONFIG_PCCARD is not set
144 203
145# 204#
146# PC-card bridges
147#
148
149#
150# PCI Hotplug Support 205# PCI Hotplug Support
151# 206#
152 207
@@ -158,6 +213,79 @@ CONFIG_BINFMT_ELF=y
158CONFIG_TRAD_SIGNALS=y 213CONFIG_TRAD_SIGNALS=y
159 214
160# 215#
216# Networking
217#
218CONFIG_NET=y
219
220#
221# Networking options
222#
223# CONFIG_PACKET is not set
224CONFIG_UNIX=y
225CONFIG_XFRM=y
226CONFIG_XFRM_USER=m
227CONFIG_NET_KEY=y
228CONFIG_INET=y
229# CONFIG_IP_MULTICAST is not set
230# CONFIG_IP_ADVANCED_ROUTER is not set
231CONFIG_IP_FIB_HASH=y
232CONFIG_IP_PNP=y
233# CONFIG_IP_PNP_DHCP is not set
234CONFIG_IP_PNP_BOOTP=y
235# CONFIG_IP_PNP_RARP is not set
236# CONFIG_NET_IPIP is not set
237# CONFIG_NET_IPGRE is not set
238# CONFIG_ARPD is not set
239# CONFIG_SYN_COOKIES is not set
240# CONFIG_INET_AH is not set
241# CONFIG_INET_ESP is not set
242# CONFIG_INET_IPCOMP is not set
243CONFIG_INET_TUNNEL=m
244CONFIG_INET_DIAG=y
245CONFIG_INET_TCP_DIAG=y
246# CONFIG_TCP_CONG_ADVANCED is not set
247CONFIG_TCP_CONG_BIC=y
248# CONFIG_IPV6 is not set
249# CONFIG_NETFILTER is not set
250
251#
252# DCCP Configuration (EXPERIMENTAL)
253#
254# CONFIG_IP_DCCP is not set
255
256#
257# SCTP Configuration (EXPERIMENTAL)
258#
259# CONFIG_IP_SCTP is not set
260# CONFIG_ATM is not set
261# CONFIG_BRIDGE is not set
262# CONFIG_VLAN_8021Q is not set
263# CONFIG_DECNET is not set
264# CONFIG_LLC2 is not set
265# CONFIG_IPX is not set
266# CONFIG_ATALK is not set
267# CONFIG_X25 is not set
268# CONFIG_LAPB is not set
269# CONFIG_NET_DIVERT is not set
270# CONFIG_ECONET is not set
271# CONFIG_WAN_ROUTER is not set
272# CONFIG_NET_SCHED is not set
273# CONFIG_NET_CLS_ROUTE is not set
274
275#
276# Network testing
277#
278# CONFIG_NET_PKTGEN is not set
279# CONFIG_HAMRADIO is not set
280# CONFIG_IRDA is not set
281# CONFIG_BT is not set
282CONFIG_IEEE80211=m
283# CONFIG_IEEE80211_DEBUG is not set
284CONFIG_IEEE80211_CRYPT_WEP=m
285CONFIG_IEEE80211_CRYPT_CCMP=m
286CONFIG_IEEE80211_CRYPT_TKIP=m
287
288#
161# Device Drivers 289# Device Drivers
162# 290#
163 291
@@ -169,6 +297,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
169# CONFIG_FW_LOADER is not set 297# CONFIG_FW_LOADER is not set
170 298
171# 299#
300# Connector - unified userspace <-> kernelspace linker
301#
302CONFIG_CONNECTOR=m
303
304#
172# Memory Technology Devices (MTD) 305# Memory Technology Devices (MTD)
173# 306#
174# CONFIG_MTD is not set 307# CONFIG_MTD is not set
@@ -185,13 +318,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
185# 318#
186# Block devices 319# Block devices
187# 320#
188# CONFIG_BLK_DEV_FD is not set
189# CONFIG_BLK_DEV_COW_COMMON is not set 321# CONFIG_BLK_DEV_COW_COMMON is not set
190# CONFIG_BLK_DEV_LOOP is not set 322# CONFIG_BLK_DEV_LOOP is not set
191# CONFIG_BLK_DEV_NBD is not set 323# CONFIG_BLK_DEV_NBD is not set
192# CONFIG_BLK_DEV_RAM is not set 324# CONFIG_BLK_DEV_RAM is not set
193CONFIG_BLK_DEV_RAM_COUNT=16 325CONFIG_BLK_DEV_RAM_COUNT=16
194CONFIG_INITRAMFS_SOURCE=""
195# CONFIG_LBD is not set 326# CONFIG_LBD is not set
196CONFIG_CDROM_PKTCDVD=m 327CONFIG_CDROM_PKTCDVD=m
197CONFIG_CDROM_PKTCDVD_BUFFERS=8 328CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -214,6 +345,7 @@ CONFIG_ATA_OVER_ETH=m
214# 345#
215# SCSI device support 346# SCSI device support
216# 347#
348CONFIG_RAID_ATTRS=m
217# CONFIG_SCSI is not set 349# CONFIG_SCSI is not set
218 350
219# 351#
@@ -224,6 +356,7 @@ CONFIG_ATA_OVER_ETH=m
224# 356#
225# Fusion MPT device support 357# Fusion MPT device support
226# 358#
359# CONFIG_FUSION is not set
227 360
228# 361#
229# IEEE 1394 (FireWire) support 362# IEEE 1394 (FireWire) support
@@ -234,77 +367,28 @@ CONFIG_ATA_OVER_ETH=m
234# 367#
235 368
236# 369#
237# Networking support 370# Network device support
238#
239CONFIG_NET=y
240
241#
242# Networking options
243# 371#
244# CONFIG_PACKET is not set 372CONFIG_NETDEVICES=y
245CONFIG_NETLINK_DEV=y 373# CONFIG_DUMMY is not set
246CONFIG_UNIX=y 374# CONFIG_BONDING is not set
247CONFIG_NET_KEY=y 375# CONFIG_EQUALIZER is not set
248CONFIG_INET=y 376# CONFIG_TUN is not set
249# CONFIG_IP_MULTICAST is not set
250# CONFIG_IP_ADVANCED_ROUTER is not set
251CONFIG_IP_PNP=y
252# CONFIG_IP_PNP_DHCP is not set
253CONFIG_IP_PNP_BOOTP=y
254# CONFIG_IP_PNP_RARP is not set
255# CONFIG_NET_IPIP is not set
256# CONFIG_NET_IPGRE is not set
257# CONFIG_ARPD is not set
258# CONFIG_SYN_COOKIES is not set
259# CONFIG_INET_AH is not set
260# CONFIG_INET_ESP is not set
261# CONFIG_INET_IPCOMP is not set
262CONFIG_INET_TUNNEL=m
263CONFIG_IP_TCPDIAG=m
264# CONFIG_IP_TCPDIAG_IPV6 is not set
265# CONFIG_IPV6 is not set
266# CONFIG_NETFILTER is not set
267CONFIG_XFRM=y
268CONFIG_XFRM_USER=m
269
270#
271# SCTP Configuration (EXPERIMENTAL)
272#
273# CONFIG_IP_SCTP is not set
274# CONFIG_ATM is not set
275# CONFIG_BRIDGE is not set
276# CONFIG_VLAN_8021Q is not set
277# CONFIG_DECNET is not set
278# CONFIG_LLC2 is not set
279# CONFIG_IPX is not set
280# CONFIG_ATALK is not set
281# CONFIG_X25 is not set
282# CONFIG_LAPB is not set
283# CONFIG_NET_DIVERT is not set
284# CONFIG_ECONET is not set
285# CONFIG_WAN_ROUTER is not set
286 377
287# 378#
288# QoS and/or fair queueing 379# PHY device support
289# 380#
290# CONFIG_NET_SCHED is not set 381CONFIG_PHYLIB=m
291# CONFIG_NET_CLS_ROUTE is not set 382CONFIG_PHYCONTROL=y
292 383
293# 384#
294# Network testing 385# MII PHY device drivers
295# 386#
296# CONFIG_NET_PKTGEN is not set 387CONFIG_MARVELL_PHY=m
297# CONFIG_NETPOLL is not set 388CONFIG_DAVICOM_PHY=m
298# CONFIG_NET_POLL_CONTROLLER is not set 389CONFIG_QSEMI_PHY=m
299# CONFIG_HAMRADIO is not set 390CONFIG_LXT_PHY=m
300# CONFIG_IRDA is not set 391CONFIG_CICADA_PHY=m
301# CONFIG_BT is not set
302CONFIG_NETDEVICES=y
303# CONFIG_DUMMY is not set
304# CONFIG_BONDING is not set
305# CONFIG_EQUALIZER is not set
306# CONFIG_TUN is not set
307# CONFIG_ETHERTAP is not set
308 392
309# 393#
310# Ethernet (10 or 100Mbit) 394# Ethernet (10 or 100Mbit)
@@ -338,6 +422,8 @@ CONFIG_MIPS_GT96100ETH=y
338# CONFIG_SLIP is not set 422# CONFIG_SLIP is not set
339# CONFIG_SHAPER is not set 423# CONFIG_SHAPER is not set
340# CONFIG_NETCONSOLE is not set 424# CONFIG_NETCONSOLE is not set
425# CONFIG_NETPOLL is not set
426# CONFIG_NET_POLL_CONTROLLER is not set
341 427
342# 428#
343# ISDN subsystem 429# ISDN subsystem
@@ -367,18 +453,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
367# CONFIG_INPUT_EVBUG is not set 453# CONFIG_INPUT_EVBUG is not set
368 454
369# 455#
370# Input I/O drivers
371#
372# CONFIG_GAMEPORT is not set
373CONFIG_SOUND_GAMEPORT=y
374CONFIG_SERIO=y
375# CONFIG_SERIO_I8042 is not set
376CONFIG_SERIO_SERPORT=y
377# CONFIG_SERIO_CT82C710 is not set
378# CONFIG_SERIO_LIBPS2 is not set
379CONFIG_SERIO_RAW=m
380
381#
382# Input Device Drivers 456# Input Device Drivers
383# 457#
384# CONFIG_INPUT_KEYBOARD is not set 458# CONFIG_INPUT_KEYBOARD is not set
@@ -388,6 +462,16 @@ CONFIG_SERIO_RAW=m
388# CONFIG_INPUT_MISC is not set 462# CONFIG_INPUT_MISC is not set
389 463
390# 464#
465# Hardware I/O ports
466#
467CONFIG_SERIO=y
468# CONFIG_SERIO_I8042 is not set
469CONFIG_SERIO_SERPORT=y
470# CONFIG_SERIO_LIBPS2 is not set
471CONFIG_SERIO_RAW=m
472# CONFIG_GAMEPORT is not set
473
474#
391# Character devices 475# Character devices
392# 476#
393CONFIG_VT=y 477CONFIG_VT=y
@@ -429,10 +513,13 @@ CONFIG_LEGACY_PTY_COUNT=256
429# 513#
430# Ftape, the floppy tape device driver 514# Ftape, the floppy tape device driver
431# 515#
432# CONFIG_DRM is not set
433# CONFIG_RAW_DRIVER is not set 516# CONFIG_RAW_DRIVER is not set
434 517
435# 518#
519# TPM devices
520#
521
522#
436# I2C support 523# I2C support
437# 524#
438# CONFIG_I2C is not set 525# CONFIG_I2C is not set
@@ -443,10 +530,20 @@ CONFIG_LEGACY_PTY_COUNT=256
443# CONFIG_W1 is not set 530# CONFIG_W1 is not set
444 531
445# 532#
533# Hardware Monitoring support
534#
535# CONFIG_HWMON is not set
536# CONFIG_HWMON_VID is not set
537
538#
446# Misc devices 539# Misc devices
447# 540#
448 541
449# 542#
543# Multimedia Capabilities Port drivers
544#
545
546#
450# Multimedia devices 547# Multimedia devices
451# 548#
452# CONFIG_VIDEO_DEV is not set 549# CONFIG_VIDEO_DEV is not set
@@ -466,7 +563,6 @@ CONFIG_LEGACY_PTY_COUNT=256
466# 563#
467# CONFIG_VGA_CONSOLE is not set 564# CONFIG_VGA_CONSOLE is not set
468CONFIG_DUMMY_CONSOLE=y 565CONFIG_DUMMY_CONSOLE=y
469# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
470 566
471# 567#
472# Sound 568# Sound
@@ -480,10 +576,6 @@ CONFIG_DUMMY_CONSOLE=y
480# CONFIG_USB_ARCH_HAS_OHCI is not set 576# CONFIG_USB_ARCH_HAS_OHCI is not set
481 577
482# 578#
483# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
484#
485
486#
487# USB Gadget Support 579# USB Gadget Support
488# 580#
489# CONFIG_USB_GADGET is not set 581# CONFIG_USB_GADGET is not set
@@ -496,24 +588,31 @@ CONFIG_DUMMY_CONSOLE=y
496# 588#
497# InfiniBand support 589# InfiniBand support
498# 590#
499# CONFIG_INFINIBAND is not set 591
592#
593# SN Devices
594#
500 595
501# 596#
502# File systems 597# File systems
503# 598#
504CONFIG_EXT2_FS=y 599CONFIG_EXT2_FS=y
505# CONFIG_EXT2_FS_XATTR is not set 600# CONFIG_EXT2_FS_XATTR is not set
601# CONFIG_EXT2_FS_XIP is not set
506# CONFIG_EXT3_FS is not set 602# CONFIG_EXT3_FS is not set
507# CONFIG_JBD is not set 603# CONFIG_JBD is not set
508# CONFIG_REISERFS_FS is not set 604# CONFIG_REISERFS_FS is not set
509# CONFIG_JFS_FS is not set 605# CONFIG_JFS_FS is not set
606# CONFIG_FS_POSIX_ACL is not set
510# CONFIG_XFS_FS is not set 607# CONFIG_XFS_FS is not set
511# CONFIG_MINIX_FS is not set 608# CONFIG_MINIX_FS is not set
512# CONFIG_ROMFS_FS is not set 609# CONFIG_ROMFS_FS is not set
610CONFIG_INOTIFY=y
513# CONFIG_QUOTA is not set 611# CONFIG_QUOTA is not set
514CONFIG_DNOTIFY=y 612CONFIG_DNOTIFY=y
515# CONFIG_AUTOFS_FS is not set 613# CONFIG_AUTOFS_FS is not set
516# CONFIG_AUTOFS4_FS is not set 614# CONFIG_AUTOFS4_FS is not set
615CONFIG_FUSE_FS=m
517 616
518# 617#
519# CD-ROM/DVD Filesystems 618# CD-ROM/DVD Filesystems
@@ -534,12 +633,10 @@ CONFIG_DNOTIFY=y
534CONFIG_PROC_FS=y 633CONFIG_PROC_FS=y
535CONFIG_PROC_KCORE=y 634CONFIG_PROC_KCORE=y
536CONFIG_SYSFS=y 635CONFIG_SYSFS=y
537# CONFIG_DEVFS_FS is not set
538CONFIG_DEVPTS_FS_XATTR=y
539CONFIG_DEVPTS_FS_SECURITY=y
540# CONFIG_TMPFS is not set 636# CONFIG_TMPFS is not set
541# CONFIG_HUGETLB_PAGE is not set 637# CONFIG_HUGETLB_PAGE is not set
542CONFIG_RAMFS=y 638CONFIG_RAMFS=y
639CONFIG_RELAYFS_FS=m
543 640
544# 641#
545# Miscellaneous filesystems 642# Miscellaneous filesystems
@@ -568,7 +665,7 @@ CONFIG_NFS_FS=y
568# CONFIG_NFSD is not set 665# CONFIG_NFSD is not set
569CONFIG_ROOT_NFS=y 666CONFIG_ROOT_NFS=y
570CONFIG_LOCKD=y 667CONFIG_LOCKD=y
571# CONFIG_EXPORTFS is not set 668CONFIG_NFS_COMMON=y
572CONFIG_SUNRPC=y 669CONFIG_SUNRPC=y
573# CONFIG_RPCSEC_GSS_KRB5 is not set 670# CONFIG_RPCSEC_GSS_KRB5 is not set
574# CONFIG_RPCSEC_GSS_SPKM3 is not set 671# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -577,6 +674,7 @@ CONFIG_SUNRPC=y
577# CONFIG_NCP_FS is not set 674# CONFIG_NCP_FS is not set
578# CONFIG_CODA_FS is not set 675# CONFIG_CODA_FS is not set
579# CONFIG_AFS_FS is not set 676# CONFIG_AFS_FS is not set
677# CONFIG_9P_FS is not set
580 678
581# 679#
582# Partition Types 680# Partition Types
@@ -597,7 +695,9 @@ CONFIG_MSDOS_PARTITION=y
597# 695#
598# Kernel hacking 696# Kernel hacking
599# 697#
698# CONFIG_PRINTK_TIME is not set
600# CONFIG_DEBUG_KERNEL is not set 699# CONFIG_DEBUG_KERNEL is not set
700CONFIG_LOG_BUF_SHIFT=14
601CONFIG_CROSSCOMPILE=y 701CONFIG_CROSSCOMPILE=y
602CONFIG_CMDLINE="" 702CONFIG_CMDLINE=""
603 703
@@ -611,7 +711,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
611# 711#
612# Cryptographic options 712# Cryptographic options
613# 713#
614# CONFIG_CRYPTO is not set 714CONFIG_CRYPTO=y
715CONFIG_CRYPTO_HMAC=y
716CONFIG_CRYPTO_NULL=m
717CONFIG_CRYPTO_MD4=m
718CONFIG_CRYPTO_MD5=m
719CONFIG_CRYPTO_SHA1=m
720CONFIG_CRYPTO_SHA256=m
721CONFIG_CRYPTO_SHA512=m
722CONFIG_CRYPTO_WP512=m
723CONFIG_CRYPTO_TGR192=m
724CONFIG_CRYPTO_DES=m
725CONFIG_CRYPTO_BLOWFISH=m
726CONFIG_CRYPTO_TWOFISH=m
727CONFIG_CRYPTO_SERPENT=m
728CONFIG_CRYPTO_AES=m
729CONFIG_CRYPTO_CAST5=m
730CONFIG_CRYPTO_CAST6=m
731CONFIG_CRYPTO_TEA=m
732CONFIG_CRYPTO_ARC4=m
733CONFIG_CRYPTO_KHAZAD=m
734CONFIG_CRYPTO_ANUBIS=m
735CONFIG_CRYPTO_DEFLATE=m
736CONFIG_CRYPTO_MICHAEL_MIC=m
737CONFIG_CRYPTO_CRC32C=m
738# CONFIG_CRYPTO_TEST is not set
615 739
616# 740#
617# Hardware crypto devices 741# Hardware crypto devices
@@ -621,7 +745,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
621# Library routines 745# Library routines
622# 746#
623# CONFIG_CRC_CCITT is not set 747# CONFIG_CRC_CCITT is not set
624# CONFIG_CRC32 is not set 748CONFIG_CRC16=m
749CONFIG_CRC32=m
625CONFIG_LIBCRC32C=m 750CONFIG_LIBCRC32C=m
626CONFIG_GENERIC_HARDIRQS=y 751CONFIG_ZLIB_INFLATE=m
627CONFIG_GENERIC_IRQ_PROBE=y 752CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index 17fa5c4e3ad1..3ae3838f283c 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:04 2005 4# Thu Oct 20 22:26:01 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,25 +11,30 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29# CONFIG_HOTPLUG is not set 27# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31CONFIG_IKCONFIG=y 29CONFIG_IKCONFIG=y
32CONFIG_IKCONFIG_PROC=y 30CONFIG_IKCONFIG_PROC=y
31CONFIG_INITRAMFS_SOURCE=""
33CONFIG_EMBEDDED=y 32CONFIG_EMBEDDED=y
34CONFIG_KALLSYMS=y 33CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_EXTRA_PASS is not set 34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
36CONFIG_FUTEX=y 38CONFIG_FUTEX=y
37CONFIG_EPOLL=y 39CONFIG_EPOLL=y
38# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -42,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0
42CONFIG_CC_ALIGN_LOOPS=0 44CONFIG_CC_ALIGN_LOOPS=0
43CONFIG_CC_ALIGN_JUMPS=0 45CONFIG_CC_ALIGN_JUMPS=0
44# CONFIG_TINY_SHMEM is not set 46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
45 48
46# 49#
47# Loadable module support 50# Loadable module support
@@ -57,41 +60,69 @@ CONFIG_KMOD=y
57# 60#
58# Machine selection 61# Machine selection
59# 62#
60# CONFIG_MACH_JAZZ is not set 63# CONFIG_MIPS_MTX1 is not set
61# CONFIG_MACH_VR41XX is not set 64# CONFIG_MIPS_BOSPORUS is not set
62# CONFIG_TOSHIBA_JMR3927 is not set 65# CONFIG_MIPS_PB1000 is not set
66# CONFIG_MIPS_PB1100 is not set
67# CONFIG_MIPS_PB1500 is not set
68# CONFIG_MIPS_PB1550 is not set
69# CONFIG_MIPS_PB1200 is not set
70# CONFIG_MIPS_DB1000 is not set
71# CONFIG_MIPS_DB1100 is not set
72# CONFIG_MIPS_DB1500 is not set
73# CONFIG_MIPS_DB1550 is not set
74# CONFIG_MIPS_DB1200 is not set
75# CONFIG_MIPS_MIRAGE is not set
63# CONFIG_MIPS_COBALT is not set 76# CONFIG_MIPS_COBALT is not set
64# CONFIG_MACH_DECSTATION is not set 77# CONFIG_MACH_DECSTATION is not set
65# CONFIG_MIPS_EV64120 is not set 78# CONFIG_MIPS_EV64120 is not set
66# CONFIG_MIPS_EV96100 is not set 79# CONFIG_MIPS_EV96100 is not set
67# CONFIG_MIPS_IVR is not set 80# CONFIG_MIPS_IVR is not set
68# CONFIG_LASAT is not set
69# CONFIG_MIPS_ITE8172 is not set 81# CONFIG_MIPS_ITE8172 is not set
82# CONFIG_MACH_JAZZ is not set
83# CONFIG_LASAT is not set
70# CONFIG_MIPS_ATLAS is not set 84# CONFIG_MIPS_ATLAS is not set
71# CONFIG_MIPS_MALTA is not set 85# CONFIG_MIPS_MALTA is not set
72# CONFIG_MIPS_SEAD is not set 86# CONFIG_MIPS_SEAD is not set
87# CONFIG_MIPS_SIM is not set
88# CONFIG_MOMENCO_JAGUAR_ATX is not set
73# CONFIG_MOMENCO_OCELOT is not set 89# CONFIG_MOMENCO_OCELOT is not set
74# CONFIG_MOMENCO_OCELOT_G is not set
75# CONFIG_MOMENCO_OCELOT_C is not set
76# CONFIG_MOMENCO_OCELOT_3 is not set 90# CONFIG_MOMENCO_OCELOT_3 is not set
77# CONFIG_MOMENCO_JAGUAR_ATX is not set 91# CONFIG_MOMENCO_OCELOT_C is not set
78# CONFIG_PMC_YOSEMITE is not set 92# CONFIG_MOMENCO_OCELOT_G is not set
93# CONFIG_MIPS_XXS1500 is not set
94# CONFIG_PNX8550_V2PCI is not set
95# CONFIG_PNX8550_JBS is not set
79# CONFIG_DDB5074 is not set 96# CONFIG_DDB5074 is not set
80# CONFIG_DDB5476 is not set 97# CONFIG_DDB5476 is not set
81# CONFIG_DDB5477 is not set 98# CONFIG_DDB5477 is not set
82# CONFIG_NEC_OSPREY is not set 99# CONFIG_MACH_VR41XX is not set
100# CONFIG_PMC_YOSEMITE is not set
101# CONFIG_QEMU is not set
83CONFIG_SGI_IP22=y 102CONFIG_SGI_IP22=y
84# CONFIG_SOC_AU1X00 is not set 103# CONFIG_SGI_IP27 is not set
85# CONFIG_SIBYTE_SB1xxx_SOC is not set 104# CONFIG_SGI_IP32 is not set
105# CONFIG_SIBYTE_BIGSUR is not set
106# CONFIG_SIBYTE_SWARM is not set
107# CONFIG_SIBYTE_SENTOSA is not set
108# CONFIG_SIBYTE_RHONE is not set
109# CONFIG_SIBYTE_CARMEL is not set
110# CONFIG_SIBYTE_PTSWARM is not set
111# CONFIG_SIBYTE_LITTLESUR is not set
112# CONFIG_SIBYTE_CRHINE is not set
113# CONFIG_SIBYTE_CRHONE is not set
86# CONFIG_SNI_RM200_PCI is not set 114# CONFIG_SNI_RM200_PCI is not set
115# CONFIG_TOSHIBA_JMR3927 is not set
87# CONFIG_TOSHIBA_RBTX4927 is not set 116# CONFIG_TOSHIBA_RBTX4927 is not set
117# CONFIG_TOSHIBA_RBTX4938 is not set
88CONFIG_RWSEM_GENERIC_SPINLOCK=y 118CONFIG_RWSEM_GENERIC_SPINLOCK=y
89CONFIG_GENERIC_CALIBRATE_DELAY=y 119CONFIG_GENERIC_CALIBRATE_DELAY=y
90CONFIG_HAVE_DEC_LOCK=y
91CONFIG_ARC=y 120CONFIG_ARC=y
92CONFIG_DMA_NONCOHERENT=y 121CONFIG_DMA_NONCOHERENT=y
93CONFIG_DMA_NEED_PCI_MAP_STATE=y 122CONFIG_DMA_NEED_PCI_MAP_STATE=y
123CONFIG_CPU_BIG_ENDIAN=y
94# CONFIG_CPU_LITTLE_ENDIAN is not set 124# CONFIG_CPU_LITTLE_ENDIAN is not set
125CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
95CONFIG_IRQ_CPU=y 126CONFIG_IRQ_CPU=y
96CONFIG_SWAP_IO_SPACE=y 127CONFIG_SWAP_IO_SPACE=y
97CONFIG_ARC32=y 128CONFIG_ARC32=y
@@ -103,8 +134,10 @@ CONFIG_ARC_PROMLIB=y
103# 134#
104# CPU selection 135# CPU selection
105# 136#
106# CONFIG_CPU_MIPS32 is not set 137# CONFIG_CPU_MIPS32_R1 is not set
107# CONFIG_CPU_MIPS64 is not set 138# CONFIG_CPU_MIPS32_R2 is not set
139# CONFIG_CPU_MIPS64_R1 is not set
140# CONFIG_CPU_MIPS64_R2 is not set
108# CONFIG_CPU_R3000 is not set 141# CONFIG_CPU_R3000 is not set
109# CONFIG_CPU_TX39XX is not set 142# CONFIG_CPU_TX39XX is not set
110# CONFIG_CPU_VR41XX is not set 143# CONFIG_CPU_VR41XX is not set
@@ -120,22 +153,48 @@ CONFIG_CPU_R5000=y
120# CONFIG_CPU_RM7000 is not set 153# CONFIG_CPU_RM7000 is not set
121# CONFIG_CPU_RM9000 is not set 154# CONFIG_CPU_RM9000 is not set
122# CONFIG_CPU_SB1 is not set 155# CONFIG_CPU_SB1 is not set
156CONFIG_SYS_HAS_CPU_R4X00=y
157CONFIG_SYS_HAS_CPU_R5000=y
158CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
159CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
160CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
161CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
162
163#
164# Kernel type
165#
166CONFIG_32BIT=y
167# CONFIG_64BIT is not set
123CONFIG_PAGE_SIZE_4KB=y 168CONFIG_PAGE_SIZE_4KB=y
124# CONFIG_PAGE_SIZE_8KB is not set 169# CONFIG_PAGE_SIZE_8KB is not set
125# CONFIG_PAGE_SIZE_16KB is not set 170# CONFIG_PAGE_SIZE_16KB is not set
126# CONFIG_PAGE_SIZE_64KB is not set 171# CONFIG_PAGE_SIZE_64KB is not set
127CONFIG_BOARD_SCACHE=y 172CONFIG_BOARD_SCACHE=y
128CONFIG_IP22_CPU_SCACHE=y 173CONFIG_IP22_CPU_SCACHE=y
174# CONFIG_MIPS_MT is not set
129# CONFIG_64BIT_PHYS_ADDR is not set 175# CONFIG_64BIT_PHYS_ADDR is not set
130# CONFIG_CPU_ADVANCED is not set 176# CONFIG_CPU_ADVANCED is not set
131CONFIG_CPU_HAS_LLSC=y 177CONFIG_CPU_HAS_LLSC=y
132CONFIG_CPU_HAS_LLDSCD=y 178CONFIG_CPU_HAS_LLDSCD=y
133CONFIG_CPU_HAS_SYNC=y 179CONFIG_CPU_HAS_SYNC=y
180CONFIG_GENERIC_HARDIRQS=y
181CONFIG_GENERIC_IRQ_PROBE=y
182CONFIG_ARCH_FLATMEM_ENABLE=y
183CONFIG_SELECT_MEMORY_MODEL=y
184CONFIG_FLATMEM_MANUAL=y
185# CONFIG_DISCONTIGMEM_MANUAL is not set
186# CONFIG_SPARSEMEM_MANUAL is not set
187CONFIG_FLATMEM=y
188CONFIG_FLAT_NODE_MEM_MAP=y
189# CONFIG_SPARSEMEM_STATIC is not set
190# CONFIG_PREEMPT_NONE is not set
191CONFIG_PREEMPT_VOLUNTARY=y
134# CONFIG_PREEMPT is not set 192# CONFIG_PREEMPT is not set
135 193
136# 194#
137# Bus options (PCI, PCMCIA, EISA, ISA, TC) 195# Bus options (PCI, PCMCIA, EISA, ISA, TC)
138# 196#
197CONFIG_HW_HAS_EISA=y
139# CONFIG_EISA is not set 198# CONFIG_EISA is not set
140CONFIG_MMU=y 199CONFIG_MMU=y
141 200
@@ -145,10 +204,6 @@ CONFIG_MMU=y
145# CONFIG_PCCARD is not set 204# CONFIG_PCCARD is not set
146 205
147# 206#
148# PC-card bridges
149#
150
151#
152# PCI Hotplug Support 207# PCI Hotplug Support
153# 208#
154 209
@@ -160,115 +215,7 @@ CONFIG_BINFMT_MISC=m
160CONFIG_TRAD_SIGNALS=y 215CONFIG_TRAD_SIGNALS=y
161 216
162# 217#
163# Device Drivers 218# Networking
164#
165
166#
167# Generic Driver Options
168#
169CONFIG_STANDALONE=y
170CONFIG_PREVENT_FIRMWARE_BUILD=y
171# CONFIG_FW_LOADER is not set
172
173#
174# Memory Technology Devices (MTD)
175#
176# CONFIG_MTD is not set
177
178#
179# Parallel port support
180#
181# CONFIG_PARPORT is not set
182
183#
184# Plug and Play support
185#
186
187#
188# Block devices
189#
190# CONFIG_BLK_DEV_FD is not set
191# CONFIG_BLK_DEV_COW_COMMON is not set
192# CONFIG_BLK_DEV_LOOP is not set
193# CONFIG_BLK_DEV_NBD is not set
194# CONFIG_BLK_DEV_RAM is not set
195CONFIG_BLK_DEV_RAM_COUNT=16
196CONFIG_INITRAMFS_SOURCE=""
197# CONFIG_LBD is not set
198CONFIG_CDROM_PKTCDVD=m
199CONFIG_CDROM_PKTCDVD_BUFFERS=8
200# CONFIG_CDROM_PKTCDVD_WCACHE is not set
201
202#
203# IO Schedulers
204#
205CONFIG_IOSCHED_NOOP=y
206CONFIG_IOSCHED_AS=y
207CONFIG_IOSCHED_DEADLINE=y
208CONFIG_IOSCHED_CFQ=y
209CONFIG_ATA_OVER_ETH=m
210
211#
212# ATA/ATAPI/MFM/RLL support
213#
214# CONFIG_IDE is not set
215
216#
217# SCSI device support
218#
219CONFIG_SCSI=y
220CONFIG_SCSI_PROC_FS=y
221
222#
223# SCSI support type (disk, tape, CD-ROM)
224#
225CONFIG_BLK_DEV_SD=y
226CONFIG_CHR_DEV_ST=y
227# CONFIG_CHR_DEV_OSST is not set
228CONFIG_BLK_DEV_SR=y
229# CONFIG_BLK_DEV_SR_VENDOR is not set
230# CONFIG_CHR_DEV_SG is not set
231
232#
233# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
234#
235# CONFIG_SCSI_MULTI_LUN is not set
236CONFIG_SCSI_CONSTANTS=y
237# CONFIG_SCSI_LOGGING is not set
238
239#
240# SCSI Transport Attributes
241#
242CONFIG_SCSI_SPI_ATTRS=m
243# CONFIG_SCSI_FC_ATTRS is not set
244# CONFIG_SCSI_ISCSI_ATTRS is not set
245
246#
247# SCSI low-level drivers
248#
249CONFIG_SGIWD93_SCSI=y
250# CONFIG_SCSI_SATA is not set
251# CONFIG_SCSI_DEBUG is not set
252
253#
254# Multi-device support (RAID and LVM)
255#
256# CONFIG_MD is not set
257
258#
259# Fusion MPT device support
260#
261
262#
263# IEEE 1394 (FireWire) support
264#
265
266#
267# I2O device support
268#
269
270#
271# Networking support
272# 219#
273CONFIG_NET=y 220CONFIG_NET=y
274 221
@@ -277,12 +224,14 @@ CONFIG_NET=y
277# 224#
278CONFIG_PACKET=y 225CONFIG_PACKET=y
279CONFIG_PACKET_MMAP=y 226CONFIG_PACKET_MMAP=y
280CONFIG_NETLINK_DEV=y
281CONFIG_UNIX=y 227CONFIG_UNIX=y
228CONFIG_XFRM=y
229CONFIG_XFRM_USER=m
282CONFIG_NET_KEY=y 230CONFIG_NET_KEY=y
283CONFIG_INET=y 231CONFIG_INET=y
284CONFIG_IP_MULTICAST=y 232CONFIG_IP_MULTICAST=y
285# CONFIG_IP_ADVANCED_ROUTER is not set 233# CONFIG_IP_ADVANCED_ROUTER is not set
234CONFIG_IP_FIB_HASH=y
286CONFIG_IP_PNP=y 235CONFIG_IP_PNP=y
287# CONFIG_IP_PNP_DHCP is not set 236# CONFIG_IP_PNP_DHCP is not set
288CONFIG_IP_PNP_BOOTP=y 237CONFIG_IP_PNP_BOOTP=y
@@ -296,8 +245,10 @@ CONFIG_INET_AH=m
296CONFIG_INET_ESP=m 245CONFIG_INET_ESP=m
297CONFIG_INET_IPCOMP=m 246CONFIG_INET_IPCOMP=m
298CONFIG_INET_TUNNEL=m 247CONFIG_INET_TUNNEL=m
299CONFIG_IP_TCPDIAG=m 248CONFIG_INET_DIAG=y
300CONFIG_IP_TCPDIAG_IPV6=y 249CONFIG_INET_TCP_DIAG=y
250# CONFIG_TCP_CONG_ADVANCED is not set
251CONFIG_TCP_CONG_BIC=y
301 252
302# 253#
303# IP: Virtual Server Configuration 254# IP: Virtual Server Configuration
@@ -341,6 +292,9 @@ CONFIG_INET6_TUNNEL=m
341CONFIG_IPV6_TUNNEL=m 292CONFIG_IPV6_TUNNEL=m
342CONFIG_NETFILTER=y 293CONFIG_NETFILTER=y
343# CONFIG_NETFILTER_DEBUG is not set 294# CONFIG_NETFILTER_DEBUG is not set
295CONFIG_NETFILTER_NETLINK=m
296CONFIG_NETFILTER_NETLINK_QUEUE=m
297CONFIG_NETFILTER_NETLINK_LOG=m
344 298
345# 299#
346# IP: Netfilter Configuration 300# IP: Netfilter Configuration
@@ -348,11 +302,15 @@ CONFIG_NETFILTER=y
348CONFIG_IP_NF_CONNTRACK=m 302CONFIG_IP_NF_CONNTRACK=m
349CONFIG_IP_NF_CT_ACCT=y 303CONFIG_IP_NF_CT_ACCT=y
350CONFIG_IP_NF_CONNTRACK_MARK=y 304CONFIG_IP_NF_CONNTRACK_MARK=y
305CONFIG_IP_NF_CONNTRACK_EVENTS=y
306CONFIG_IP_NF_CONNTRACK_NETLINK=m
351# CONFIG_IP_NF_CT_PROTO_SCTP is not set 307# CONFIG_IP_NF_CT_PROTO_SCTP is not set
352CONFIG_IP_NF_FTP=m 308CONFIG_IP_NF_FTP=m
353CONFIG_IP_NF_IRC=m 309CONFIG_IP_NF_IRC=m
310# CONFIG_IP_NF_NETBIOS_NS is not set
354CONFIG_IP_NF_TFTP=m 311CONFIG_IP_NF_TFTP=m
355CONFIG_IP_NF_AMANDA=m 312CONFIG_IP_NF_AMANDA=m
313CONFIG_IP_NF_PPTP=m
356CONFIG_IP_NF_QUEUE=m 314CONFIG_IP_NF_QUEUE=m
357CONFIG_IP_NF_IPTABLES=m 315CONFIG_IP_NF_IPTABLES=m
358CONFIG_IP_NF_MATCH_LIMIT=m 316CONFIG_IP_NF_MATCH_LIMIT=m
@@ -376,9 +334,12 @@ CONFIG_IP_NF_MATCH_OWNER=m
376CONFIG_IP_NF_MATCH_ADDRTYPE=m 334CONFIG_IP_NF_MATCH_ADDRTYPE=m
377CONFIG_IP_NF_MATCH_REALM=m 335CONFIG_IP_NF_MATCH_REALM=m
378CONFIG_IP_NF_MATCH_SCTP=m 336CONFIG_IP_NF_MATCH_SCTP=m
337CONFIG_IP_NF_MATCH_DCCP=m
379CONFIG_IP_NF_MATCH_COMMENT=m 338CONFIG_IP_NF_MATCH_COMMENT=m
380CONFIG_IP_NF_MATCH_CONNMARK=m 339CONFIG_IP_NF_MATCH_CONNMARK=m
340CONFIG_IP_NF_MATCH_CONNBYTES=m
381CONFIG_IP_NF_MATCH_HASHLIMIT=m 341CONFIG_IP_NF_MATCH_HASHLIMIT=m
342CONFIG_IP_NF_MATCH_STRING=m
382CONFIG_IP_NF_FILTER=m 343CONFIG_IP_NF_FILTER=m
383CONFIG_IP_NF_TARGET_REJECT=m 344CONFIG_IP_NF_TARGET_REJECT=m
384CONFIG_IP_NF_TARGET_LOG=m 345CONFIG_IP_NF_TARGET_LOG=m
@@ -395,12 +356,14 @@ CONFIG_IP_NF_NAT_IRC=m
395CONFIG_IP_NF_NAT_FTP=m 356CONFIG_IP_NF_NAT_FTP=m
396CONFIG_IP_NF_NAT_TFTP=m 357CONFIG_IP_NF_NAT_TFTP=m
397CONFIG_IP_NF_NAT_AMANDA=m 358CONFIG_IP_NF_NAT_AMANDA=m
359CONFIG_IP_NF_NAT_PPTP=m
398CONFIG_IP_NF_MANGLE=m 360CONFIG_IP_NF_MANGLE=m
399CONFIG_IP_NF_TARGET_TOS=m 361CONFIG_IP_NF_TARGET_TOS=m
400CONFIG_IP_NF_TARGET_ECN=m 362CONFIG_IP_NF_TARGET_ECN=m
401CONFIG_IP_NF_TARGET_DSCP=m 363CONFIG_IP_NF_TARGET_DSCP=m
402CONFIG_IP_NF_TARGET_MARK=m 364CONFIG_IP_NF_TARGET_MARK=m
403CONFIG_IP_NF_TARGET_CLASSIFY=m 365CONFIG_IP_NF_TARGET_CLASSIFY=m
366CONFIG_IP_NF_TARGET_TTL=m
404CONFIG_IP_NF_TARGET_CONNMARK=m 367CONFIG_IP_NF_TARGET_CONNMARK=m
405CONFIG_IP_NF_TARGET_CLUSTERIP=m 368CONFIG_IP_NF_TARGET_CLUSTERIP=m
406CONFIG_IP_NF_RAW=m 369CONFIG_IP_NF_RAW=m
@@ -410,7 +373,7 @@ CONFIG_IP_NF_ARPFILTER=m
410CONFIG_IP_NF_ARP_MANGLE=m 373CONFIG_IP_NF_ARP_MANGLE=m
411 374
412# 375#
413# IPv6: Netfilter Configuration 376# IPv6: Netfilter Configuration (EXPERIMENTAL)
414# 377#
415CONFIG_IP6_NF_QUEUE=m 378CONFIG_IP6_NF_QUEUE=m
416CONFIG_IP6_NF_IPTABLES=m 379CONFIG_IP6_NF_IPTABLES=m
@@ -429,11 +392,16 @@ CONFIG_IP6_NF_MATCH_LENGTH=m
429CONFIG_IP6_NF_MATCH_EUI64=m 392CONFIG_IP6_NF_MATCH_EUI64=m
430CONFIG_IP6_NF_FILTER=m 393CONFIG_IP6_NF_FILTER=m
431CONFIG_IP6_NF_TARGET_LOG=m 394CONFIG_IP6_NF_TARGET_LOG=m
395CONFIG_IP6_NF_TARGET_REJECT=m
432CONFIG_IP6_NF_MANGLE=m 396CONFIG_IP6_NF_MANGLE=m
433CONFIG_IP6_NF_TARGET_MARK=m 397CONFIG_IP6_NF_TARGET_MARK=m
398CONFIG_IP6_NF_TARGET_HL=m
434CONFIG_IP6_NF_RAW=m 399CONFIG_IP6_NF_RAW=m
435CONFIG_XFRM=y 400
436CONFIG_XFRM_USER=m 401#
402# DCCP Configuration (EXPERIMENTAL)
403#
404# CONFIG_IP_DCCP is not set
437 405
438# 406#
439# SCTP Configuration (EXPERIMENTAL) 407# SCTP Configuration (EXPERIMENTAL)
@@ -456,10 +424,6 @@ CONFIG_SCTP_HMAC_MD5=y
456CONFIG_NET_DIVERT=y 424CONFIG_NET_DIVERT=y
457# CONFIG_ECONET is not set 425# CONFIG_ECONET is not set
458# CONFIG_WAN_ROUTER is not set 426# CONFIG_WAN_ROUTER is not set
459
460#
461# QoS and/or fair queueing
462#
463CONFIG_NET_SCHED=y 427CONFIG_NET_SCHED=y
464# CONFIG_NET_SCH_CLK_JIFFIES is not set 428# CONFIG_NET_SCH_CLK_JIFFIES is not set
465CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y 429CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y
@@ -479,6 +443,7 @@ CONFIG_NET_SCH_INGRESS=m
479CONFIG_NET_QOS=y 443CONFIG_NET_QOS=y
480CONFIG_NET_ESTIMATOR=y 444CONFIG_NET_ESTIMATOR=y
481CONFIG_NET_CLS=y 445CONFIG_NET_CLS=y
446CONFIG_NET_CLS_BASIC=m
482CONFIG_NET_CLS_TCINDEX=m 447CONFIG_NET_CLS_TCINDEX=m
483CONFIG_NET_CLS_ROUTE4=m 448CONFIG_NET_CLS_ROUTE4=m
484CONFIG_NET_CLS_ROUTE=y 449CONFIG_NET_CLS_ROUTE=y
@@ -489,6 +454,7 @@ CONFIG_NET_CLS_U32=m
489# CONFIG_CLS_U32_MARK is not set 454# CONFIG_CLS_U32_MARK is not set
490CONFIG_NET_CLS_RSVP=m 455CONFIG_NET_CLS_RSVP=m
491CONFIG_NET_CLS_RSVP6=m 456CONFIG_NET_CLS_RSVP6=m
457# CONFIG_NET_EMATCH is not set
492# CONFIG_NET_CLS_ACT is not set 458# CONFIG_NET_CLS_ACT is not set
493CONFIG_NET_CLS_POLICE=y 459CONFIG_NET_CLS_POLICE=y
494 460
@@ -496,17 +462,153 @@ CONFIG_NET_CLS_POLICE=y
496# Network testing 462# Network testing
497# 463#
498# CONFIG_NET_PKTGEN is not set 464# CONFIG_NET_PKTGEN is not set
499# CONFIG_NETPOLL is not set
500# CONFIG_NET_POLL_CONTROLLER is not set
501# CONFIG_HAMRADIO is not set 465# CONFIG_HAMRADIO is not set
502# CONFIG_IRDA is not set 466# CONFIG_IRDA is not set
503# CONFIG_BT is not set 467# CONFIG_BT is not set
468CONFIG_IEEE80211=m
469# CONFIG_IEEE80211_DEBUG is not set
470CONFIG_IEEE80211_CRYPT_WEP=m
471CONFIG_IEEE80211_CRYPT_CCMP=m
472CONFIG_IEEE80211_CRYPT_TKIP=m
473
474#
475# Device Drivers
476#
477
478#
479# Generic Driver Options
480#
481CONFIG_STANDALONE=y
482CONFIG_PREVENT_FIRMWARE_BUILD=y
483# CONFIG_FW_LOADER is not set
484
485#
486# Connector - unified userspace <-> kernelspace linker
487#
488CONFIG_CONNECTOR=m
489
490#
491# Memory Technology Devices (MTD)
492#
493# CONFIG_MTD is not set
494
495#
496# Parallel port support
497#
498# CONFIG_PARPORT is not set
499
500#
501# Plug and Play support
502#
503
504#
505# Block devices
506#
507# CONFIG_BLK_DEV_COW_COMMON is not set
508# CONFIG_BLK_DEV_LOOP is not set
509# CONFIG_BLK_DEV_NBD is not set
510# CONFIG_BLK_DEV_RAM is not set
511CONFIG_BLK_DEV_RAM_COUNT=16
512# CONFIG_LBD is not set
513CONFIG_CDROM_PKTCDVD=m
514CONFIG_CDROM_PKTCDVD_BUFFERS=8
515# CONFIG_CDROM_PKTCDVD_WCACHE is not set
516
517#
518# IO Schedulers
519#
520CONFIG_IOSCHED_NOOP=y
521CONFIG_IOSCHED_AS=y
522CONFIG_IOSCHED_DEADLINE=y
523CONFIG_IOSCHED_CFQ=y
524CONFIG_ATA_OVER_ETH=m
525
526#
527# ATA/ATAPI/MFM/RLL support
528#
529# CONFIG_IDE is not set
530
531#
532# SCSI device support
533#
534CONFIG_RAID_ATTRS=m
535CONFIG_SCSI=y
536CONFIG_SCSI_PROC_FS=y
537
538#
539# SCSI support type (disk, tape, CD-ROM)
540#
541CONFIG_BLK_DEV_SD=y
542CONFIG_CHR_DEV_ST=y
543# CONFIG_CHR_DEV_OSST is not set
544CONFIG_BLK_DEV_SR=y
545# CONFIG_BLK_DEV_SR_VENDOR is not set
546# CONFIG_CHR_DEV_SG is not set
547CONFIG_CHR_DEV_SCH=m
548
549#
550# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
551#
552# CONFIG_SCSI_MULTI_LUN is not set
553CONFIG_SCSI_CONSTANTS=y
554# CONFIG_SCSI_LOGGING is not set
555
556#
557# SCSI Transport Attributes
558#
559CONFIG_SCSI_SPI_ATTRS=m
560# CONFIG_SCSI_FC_ATTRS is not set
561CONFIG_SCSI_ISCSI_ATTRS=m
562CONFIG_SCSI_SAS_ATTRS=m
563
564#
565# SCSI low-level drivers
566#
567CONFIG_SGIWD93_SCSI=y
568# CONFIG_SCSI_SATA is not set
569# CONFIG_SCSI_DEBUG is not set
570
571#
572# Multi-device support (RAID and LVM)
573#
574# CONFIG_MD is not set
575
576#
577# Fusion MPT device support
578#
579# CONFIG_FUSION is not set
580
581#
582# IEEE 1394 (FireWire) support
583#
584
585#
586# I2O device support
587#
588
589#
590# Network device support
591#
504CONFIG_NETDEVICES=y 592CONFIG_NETDEVICES=y
505CONFIG_DUMMY=m 593CONFIG_DUMMY=m
506CONFIG_BONDING=m 594CONFIG_BONDING=m
507CONFIG_EQUALIZER=m 595CONFIG_EQUALIZER=m
508CONFIG_TUN=m 596CONFIG_TUN=m
509CONFIG_ETHERTAP=m 597
598#
599# PHY device support
600#
601CONFIG_PHYLIB=m
602CONFIG_PHYCONTROL=y
603
604#
605# MII PHY device drivers
606#
607CONFIG_MARVELL_PHY=m
608CONFIG_DAVICOM_PHY=m
609CONFIG_QSEMI_PHY=m
610CONFIG_LXT_PHY=m
611CONFIG_CICADA_PHY=m
510 612
511# 613#
512# Ethernet (10 or 100Mbit) 614# Ethernet (10 or 100Mbit)
@@ -540,6 +642,8 @@ CONFIG_SGISEEQ=y
540# CONFIG_SLIP is not set 642# CONFIG_SLIP is not set
541# CONFIG_SHAPER is not set 643# CONFIG_SHAPER is not set
542# CONFIG_NETCONSOLE is not set 644# CONFIG_NETCONSOLE is not set
645# CONFIG_NETPOLL is not set
646# CONFIG_NET_POLL_CONTROLLER is not set
543 647
544# 648#
545# ISDN subsystem 649# ISDN subsystem
@@ -569,18 +673,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
569# CONFIG_INPUT_EVBUG is not set 673# CONFIG_INPUT_EVBUG is not set
570 674
571# 675#
572# Input I/O drivers
573#
574# CONFIG_GAMEPORT is not set
575CONFIG_SOUND_GAMEPORT=y
576CONFIG_SERIO=y
577CONFIG_SERIO_I8042=y
578CONFIG_SERIO_SERPORT=y
579# CONFIG_SERIO_CT82C710 is not set
580CONFIG_SERIO_LIBPS2=y
581CONFIG_SERIO_RAW=m
582
583#
584# Input Device Drivers 676# Input Device Drivers
585# 677#
586CONFIG_INPUT_KEYBOARD=y 678CONFIG_INPUT_KEYBOARD=y
@@ -598,6 +690,16 @@ CONFIG_MOUSE_SERIAL=m
598# CONFIG_INPUT_MISC is not set 690# CONFIG_INPUT_MISC is not set
599 691
600# 692#
693# Hardware I/O ports
694#
695CONFIG_SERIO=y
696CONFIG_SERIO_I8042=y
697CONFIG_SERIO_SERPORT=y
698CONFIG_SERIO_LIBPS2=y
699CONFIG_SERIO_RAW=m
700# CONFIG_GAMEPORT is not set
701
702#
601# Character devices 703# Character devices
602# 704#
603CONFIG_VT=y 705CONFIG_VT=y
@@ -644,11 +746,14 @@ CONFIG_SGI_DS1286=m
644# 746#
645# Ftape, the floppy tape device driver 747# Ftape, the floppy tape device driver
646# 748#
647# CONFIG_DRM is not set
648CONFIG_RAW_DRIVER=m 749CONFIG_RAW_DRIVER=m
649CONFIG_MAX_RAW_DEVS=256 750CONFIG_MAX_RAW_DEVS=256
650 751
651# 752#
753# TPM devices
754#
755
756#
652# I2C support 757# I2C support
653# 758#
654# CONFIG_I2C is not set 759# CONFIG_I2C is not set
@@ -659,10 +764,20 @@ CONFIG_MAX_RAW_DEVS=256
659# CONFIG_W1 is not set 764# CONFIG_W1 is not set
660 765
661# 766#
767# Hardware Monitoring support
768#
769# CONFIG_HWMON is not set
770# CONFIG_HWMON_VID is not set
771
772#
662# Misc devices 773# Misc devices
663# 774#
664 775
665# 776#
777# Multimedia Capabilities Port drivers
778#
779
780#
666# Multimedia devices 781# Multimedia devices
667# 782#
668# CONFIG_VIDEO_DEV is not set 783# CONFIG_VIDEO_DEV is not set
@@ -693,7 +808,6 @@ CONFIG_LOGO=y
693# CONFIG_LOGO_LINUX_VGA16 is not set 808# CONFIG_LOGO_LINUX_VGA16 is not set
694# CONFIG_LOGO_LINUX_CLUT224 is not set 809# CONFIG_LOGO_LINUX_CLUT224 is not set
695CONFIG_LOGO_SGI_CLUT224=y 810CONFIG_LOGO_SGI_CLUT224=y
696# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
697 811
698# 812#
699# Sound 813# Sound
@@ -707,10 +821,6 @@ CONFIG_LOGO_SGI_CLUT224=y
707# CONFIG_USB_ARCH_HAS_OHCI is not set 821# CONFIG_USB_ARCH_HAS_OHCI is not set
708 822
709# 823#
710# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
711#
712
713#
714# USB Gadget Support 824# USB Gadget Support
715# 825#
716# CONFIG_USB_GADGET is not set 826# CONFIG_USB_GADGET is not set
@@ -723,13 +833,17 @@ CONFIG_LOGO_SGI_CLUT224=y
723# 833#
724# InfiniBand support 834# InfiniBand support
725# 835#
726# CONFIG_INFINIBAND is not set 836
837#
838# SN Devices
839#
727 840
728# 841#
729# File systems 842# File systems
730# 843#
731CONFIG_EXT2_FS=m 844CONFIG_EXT2_FS=m
732# CONFIG_EXT2_FS_XATTR is not set 845# CONFIG_EXT2_FS_XATTR is not set
846# CONFIG_EXT2_FS_XIP is not set
733CONFIG_EXT3_FS=y 847CONFIG_EXT3_FS=y
734CONFIG_EXT3_FS_XATTR=y 848CONFIG_EXT3_FS_XATTR=y
735CONFIG_EXT3_FS_POSIX_ACL=y 849CONFIG_EXT3_FS_POSIX_ACL=y
@@ -741,12 +855,14 @@ CONFIG_FS_MBCACHE=y
741# CONFIG_JFS_FS is not set 855# CONFIG_JFS_FS is not set
742CONFIG_FS_POSIX_ACL=y 856CONFIG_FS_POSIX_ACL=y
743CONFIG_XFS_FS=m 857CONFIG_XFS_FS=m
744# CONFIG_XFS_RT is not set 858CONFIG_XFS_EXPORT=y
745CONFIG_XFS_QUOTA=y 859CONFIG_XFS_QUOTA=m
746CONFIG_XFS_SECURITY=y 860CONFIG_XFS_SECURITY=y
747# CONFIG_XFS_POSIX_ACL is not set 861# CONFIG_XFS_POSIX_ACL is not set
862# CONFIG_XFS_RT is not set
748CONFIG_MINIX_FS=m 863CONFIG_MINIX_FS=m
749# CONFIG_ROMFS_FS is not set 864# CONFIG_ROMFS_FS is not set
865CONFIG_INOTIFY=y
750CONFIG_QUOTA=y 866CONFIG_QUOTA=y
751# CONFIG_QFMT_V1 is not set 867# CONFIG_QFMT_V1 is not set
752CONFIG_QFMT_V2=m 868CONFIG_QFMT_V2=m
@@ -754,6 +870,7 @@ CONFIG_QUOTACTL=y
754CONFIG_DNOTIFY=y 870CONFIG_DNOTIFY=y
755CONFIG_AUTOFS_FS=m 871CONFIG_AUTOFS_FS=m
756CONFIG_AUTOFS4_FS=m 872CONFIG_AUTOFS4_FS=m
873CONFIG_FUSE_FS=m
757 874
758# 875#
759# CD-ROM/DVD Filesystems 876# CD-ROM/DVD Filesystems
@@ -781,12 +898,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
781CONFIG_PROC_FS=y 898CONFIG_PROC_FS=y
782CONFIG_PROC_KCORE=y 899CONFIG_PROC_KCORE=y
783CONFIG_SYSFS=y 900CONFIG_SYSFS=y
784# CONFIG_DEVFS_FS is not set
785CONFIG_DEVPTS_FS_XATTR=y
786CONFIG_DEVPTS_FS_SECURITY=y
787# CONFIG_TMPFS is not set 901# CONFIG_TMPFS is not set
788# CONFIG_HUGETLB_PAGE is not set 902# CONFIG_HUGETLB_PAGE is not set
789CONFIG_RAMFS=y 903CONFIG_RAMFS=y
904CONFIG_RELAYFS_FS=m
790 905
791# 906#
792# Miscellaneous filesystems 907# Miscellaneous filesystems
@@ -811,15 +926,20 @@ CONFIG_UFS_FS=m
811# 926#
812CONFIG_NFS_FS=m 927CONFIG_NFS_FS=m
813CONFIG_NFS_V3=y 928CONFIG_NFS_V3=y
929CONFIG_NFS_V3_ACL=y
814# CONFIG_NFS_V4 is not set 930# CONFIG_NFS_V4 is not set
815# CONFIG_NFS_DIRECTIO is not set 931# CONFIG_NFS_DIRECTIO is not set
816CONFIG_NFSD=m 932CONFIG_NFSD=m
933CONFIG_NFSD_V2_ACL=y
817CONFIG_NFSD_V3=y 934CONFIG_NFSD_V3=y
935CONFIG_NFSD_V3_ACL=y
818# CONFIG_NFSD_V4 is not set 936# CONFIG_NFSD_V4 is not set
819CONFIG_NFSD_TCP=y 937CONFIG_NFSD_TCP=y
820CONFIG_LOCKD=m 938CONFIG_LOCKD=m
821CONFIG_LOCKD_V4=y 939CONFIG_LOCKD_V4=y
822CONFIG_EXPORTFS=m 940CONFIG_EXPORTFS=m
941CONFIG_NFS_ACL_SUPPORT=m
942CONFIG_NFS_COMMON=y
823CONFIG_SUNRPC=m 943CONFIG_SUNRPC=m
824CONFIG_SUNRPC_GSS=m 944CONFIG_SUNRPC_GSS=m
825CONFIG_RPCSEC_GSS_KRB5=m 945CONFIG_RPCSEC_GSS_KRB5=m
@@ -835,6 +955,7 @@ CONFIG_CIFS=m
835CONFIG_CODA_FS=m 955CONFIG_CODA_FS=m
836# CONFIG_CODA_FS_OLD_API is not set 956# CONFIG_CODA_FS_OLD_API is not set
837# CONFIG_AFS_FS is not set 957# CONFIG_AFS_FS is not set
958# CONFIG_9P_FS is not set
838 959
839# 960#
840# Partition Types 961# Partition Types
@@ -908,7 +1029,9 @@ CONFIG_NLS_UTF8=m
908# 1029#
909# Kernel hacking 1030# Kernel hacking
910# 1031#
1032# CONFIG_PRINTK_TIME is not set
911# CONFIG_DEBUG_KERNEL is not set 1033# CONFIG_DEBUG_KERNEL is not set
1034CONFIG_LOG_BUF_SHIFT=14
912CONFIG_CROSSCOMPILE=y 1035CONFIG_CROSSCOMPILE=y
913CONFIG_CMDLINE="" 1036CONFIG_CMDLINE=""
914 1037
@@ -931,6 +1054,7 @@ CONFIG_CRYPTO_SHA1=m
931CONFIG_CRYPTO_SHA256=m 1054CONFIG_CRYPTO_SHA256=m
932CONFIG_CRYPTO_SHA512=m 1055CONFIG_CRYPTO_SHA512=m
933CONFIG_CRYPTO_WP512=m 1056CONFIG_CRYPTO_WP512=m
1057CONFIG_CRYPTO_TGR192=m
934CONFIG_CRYPTO_DES=m 1058CONFIG_CRYPTO_DES=m
935CONFIG_CRYPTO_BLOWFISH=m 1059CONFIG_CRYPTO_BLOWFISH=m
936CONFIG_CRYPTO_TWOFISH=m 1060CONFIG_CRYPTO_TWOFISH=m
@@ -942,10 +1066,10 @@ CONFIG_CRYPTO_TEA=m
942CONFIG_CRYPTO_ARC4=m 1066CONFIG_CRYPTO_ARC4=m
943CONFIG_CRYPTO_KHAZAD=m 1067CONFIG_CRYPTO_KHAZAD=m
944CONFIG_CRYPTO_ANUBIS=m 1068CONFIG_CRYPTO_ANUBIS=m
945CONFIG_CRYPTO_DEFLATE=y 1069CONFIG_CRYPTO_DEFLATE=m
946CONFIG_CRYPTO_MICHAEL_MIC=m 1070CONFIG_CRYPTO_MICHAEL_MIC=m
947CONFIG_CRYPTO_CRC32C=m 1071CONFIG_CRYPTO_CRC32C=m
948CONFIG_CRYPTO_TEST=m 1072# CONFIG_CRYPTO_TEST is not set
949 1073
950# 1074#
951# Hardware crypto devices 1075# Hardware crypto devices
@@ -955,9 +1079,12 @@ CONFIG_CRYPTO_TEST=m
955# Library routines 1079# Library routines
956# 1080#
957# CONFIG_CRC_CCITT is not set 1081# CONFIG_CRC_CCITT is not set
1082CONFIG_CRC16=m
958CONFIG_CRC32=m 1083CONFIG_CRC32=m
959CONFIG_LIBCRC32C=m 1084CONFIG_LIBCRC32C=m
960CONFIG_ZLIB_INFLATE=y 1085CONFIG_ZLIB_INFLATE=m
961CONFIG_ZLIB_DEFLATE=y 1086CONFIG_ZLIB_DEFLATE=m
962CONFIG_GENERIC_HARDIRQS=y 1087CONFIG_TEXTSEARCH=y
963CONFIG_GENERIC_IRQ_PROBE=y 1088CONFIG_TEXTSEARCH_KMP=m
1089CONFIG_TEXTSEARCH_BM=m
1090CONFIG_TEXTSEARCH_FSM=m
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index b2a67da1e031..d962f61d5b98 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -1,11 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:04 2005 4# Thu Oct 20 22:26:04 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7CONFIG_64BIT=y
8CONFIG_64BIT=y
9 7
10# 8#
11# Code maturity level options 9# Code maturity level options
@@ -13,25 +11,31 @@ CONFIG_64BIT=y
13CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
14CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
15CONFIG_LOCK_KERNEL=y 13CONFIG_LOCK_KERNEL=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
16 15
17# 16#
18# General setup 17# General setup
19# 18#
20CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
21CONFIG_SWAP=y 21CONFIG_SWAP=y
22CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
23CONFIG_POSIX_MQUEUE=y 23CONFIG_POSIX_MQUEUE=y
24# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
27CONFIG_LOG_BUF_SHIFT=15 27CONFIG_HOTPLUG=y
28# CONFIG_HOTPLUG is not set
29CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
30CONFIG_IKCONFIG=y 29CONFIG_IKCONFIG=y
31CONFIG_IKCONFIG_PROC=y 30CONFIG_IKCONFIG_PROC=y
31CONFIG_CPUSETS=y
32CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 33CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 34CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 35# CONFIG_KALLSYMS_EXTRA_PASS is not set
36CONFIG_PRINTK=y
37CONFIG_BUG=y
38CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 39CONFIG_FUTEX=y
36CONFIG_EPOLL=y 40CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 41# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +45,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 45CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 46CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 47# CONFIG_TINY_SHMEM is not set
48CONFIG_BASE_SMALL=0
44 49
45# 50#
46# Loadable module support 51# Loadable module support
@@ -57,55 +62,85 @@ CONFIG_STOP_MACHINE=y
57# 62#
58# Machine selection 63# Machine selection
59# 64#
60# CONFIG_MACH_JAZZ is not set 65# CONFIG_MIPS_MTX1 is not set
61# CONFIG_MACH_VR41XX is not set 66# CONFIG_MIPS_BOSPORUS is not set
67# CONFIG_MIPS_PB1000 is not set
68# CONFIG_MIPS_PB1100 is not set
69# CONFIG_MIPS_PB1500 is not set
70# CONFIG_MIPS_PB1550 is not set
71# CONFIG_MIPS_PB1200 is not set
72# CONFIG_MIPS_DB1000 is not set
73# CONFIG_MIPS_DB1100 is not set
74# CONFIG_MIPS_DB1500 is not set
75# CONFIG_MIPS_DB1550 is not set
76# CONFIG_MIPS_DB1200 is not set
77# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 78# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 79# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 80# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 81# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 82# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 83# CONFIG_MIPS_ITE8172 is not set
84# CONFIG_MACH_JAZZ is not set
85# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 86# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set 87# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 88# CONFIG_MIPS_SEAD is not set
89# CONFIG_MIPS_SIM is not set
90# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 91# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 92# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 93# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 94# CONFIG_MOMENCO_OCELOT_G is not set
95# CONFIG_MIPS_XXS1500 is not set
96# CONFIG_PNX8550_V2PCI is not set
97# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 98# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 99# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 100# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 101# CONFIG_MACH_VR41XX is not set
102# CONFIG_PMC_YOSEMITE is not set
103# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 104# CONFIG_SGI_IP22 is not set
83CONFIG_SGI_IP27=y 105CONFIG_SGI_IP27=y
106# CONFIG_SGI_IP32 is not set
107# CONFIG_SIBYTE_BIGSUR is not set
108# CONFIG_SIBYTE_SWARM is not set
109# CONFIG_SIBYTE_SENTOSA is not set
110# CONFIG_SIBYTE_RHONE is not set
111# CONFIG_SIBYTE_CARMEL is not set
112# CONFIG_SIBYTE_PTSWARM is not set
113# CONFIG_SIBYTE_LITTLESUR is not set
114# CONFIG_SIBYTE_CRHINE is not set
115# CONFIG_SIBYTE_CRHONE is not set
116# CONFIG_SNI_RM200_PCI is not set
117# CONFIG_TOSHIBA_JMR3927 is not set
118# CONFIG_TOSHIBA_RBTX4927 is not set
119# CONFIG_TOSHIBA_RBTX4938 is not set
84# CONFIG_SGI_SN0_N_MODE is not set 120# CONFIG_SGI_SN0_N_MODE is not set
85CONFIG_ARCH_DISCONTIGMEM_ENABLE=y 121CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
86CONFIG_NUMA=y 122CONFIG_NUMA=y
87# CONFIG_MAPPED_KERNEL is not set 123# CONFIG_MAPPED_KERNEL is not set
88# CONFIG_REPLICATE_KTEXT is not set 124# CONFIG_REPLICATE_KTEXT is not set
89# CONFIG_REPLICATE_EXHANDLERS is not set 125# CONFIG_REPLICATE_EXHANDLERS is not set
90# CONFIG_SGI_IP32 is not set
91# CONFIG_SIBYTE_SB1xxx_SOC is not set
92# CONFIG_SNI_RM200_PCI is not set
93CONFIG_RWSEM_GENERIC_SPINLOCK=y 126CONFIG_RWSEM_GENERIC_SPINLOCK=y
94CONFIG_GENERIC_CALIBRATE_DELAY=y 127CONFIG_GENERIC_CALIBRATE_DELAY=y
95CONFIG_HAVE_DEC_LOCK=y
96CONFIG_ARC=y 128CONFIG_ARC=y
97CONFIG_DMA_IP27=y 129CONFIG_DMA_IP27=y
130CONFIG_CPU_BIG_ENDIAN=y
98# CONFIG_CPU_LITTLE_ENDIAN is not set 131# CONFIG_CPU_LITTLE_ENDIAN is not set
132CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
99CONFIG_MIPS_L1_CACHE_SHIFT=7 133CONFIG_MIPS_L1_CACHE_SHIFT=7
100CONFIG_ARC64=y 134CONFIG_ARC64=y
101CONFIG_BOOT_ELF64=y 135CONFIG_BOOT_ELF64=y
102CONFIG_QL_ISP_A64=y
103 136
104# 137#
105# CPU selection 138# CPU selection
106# 139#
107# CONFIG_CPU_MIPS32 is not set 140# CONFIG_CPU_MIPS32_R1 is not set
108# CONFIG_CPU_MIPS64 is not set 141# CONFIG_CPU_MIPS32_R2 is not set
142# CONFIG_CPU_MIPS64_R1 is not set
143# CONFIG_CPU_MIPS64_R2 is not set
109# CONFIG_CPU_R3000 is not set 144# CONFIG_CPU_R3000 is not set
110# CONFIG_CPU_TX39XX is not set 145# CONFIG_CPU_TX39XX is not set
111# CONFIG_CPU_VR41XX is not set 146# CONFIG_CPU_VR41XX is not set
@@ -121,17 +156,42 @@ CONFIG_CPU_R10000=y
121# CONFIG_CPU_RM7000 is not set 156# CONFIG_CPU_RM7000 is not set
122# CONFIG_CPU_RM9000 is not set 157# CONFIG_CPU_RM9000 is not set
123# CONFIG_CPU_SB1 is not set 158# CONFIG_CPU_SB1 is not set
159CONFIG_SYS_HAS_CPU_R10000=y
160CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
161CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
162CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
163
164#
165# Kernel type
166#
167# CONFIG_32BIT is not set
168CONFIG_64BIT=y
124CONFIG_PAGE_SIZE_4KB=y 169CONFIG_PAGE_SIZE_4KB=y
125# CONFIG_PAGE_SIZE_8KB is not set 170# CONFIG_PAGE_SIZE_8KB is not set
126# CONFIG_PAGE_SIZE_16KB is not set 171# CONFIG_PAGE_SIZE_16KB is not set
127# CONFIG_PAGE_SIZE_64KB is not set 172# CONFIG_PAGE_SIZE_64KB is not set
128CONFIG_CPU_HAS_PREFETCH=y 173CONFIG_CPU_HAS_PREFETCH=y
174# CONFIG_MIPS_MT is not set
129CONFIG_CPU_HAS_LLSC=y 175CONFIG_CPU_HAS_LLSC=y
130CONFIG_CPU_HAS_LLDSCD=y 176CONFIG_CPU_HAS_LLDSCD=y
131CONFIG_CPU_HAS_SYNC=y 177CONFIG_CPU_HAS_SYNC=y
178CONFIG_GENERIC_HARDIRQS=y
179CONFIG_GENERIC_IRQ_PROBE=y
180CONFIG_CPU_SUPPORTS_HIGHMEM=y
181CONFIG_SELECT_MEMORY_MODEL=y
182# CONFIG_FLATMEM_MANUAL is not set
183CONFIG_DISCONTIGMEM_MANUAL=y
184# CONFIG_SPARSEMEM_MANUAL is not set
185CONFIG_DISCONTIGMEM=y
186CONFIG_FLAT_NODE_MEM_MAP=y
187CONFIG_NEED_MULTIPLE_NODES=y
188# CONFIG_SPARSEMEM_STATIC is not set
132CONFIG_SMP=y 189CONFIG_SMP=y
133CONFIG_NR_CPUS=64 190CONFIG_NR_CPUS=64
191CONFIG_PREEMPT_NONE=y
192# CONFIG_PREEMPT_VOLUNTARY is not set
134# CONFIG_PREEMPT is not set 193# CONFIG_PREEMPT is not set
194CONFIG_PREEMPT_BKL=y
135# CONFIG_MIPS_INSANE_LARGE is not set 195# CONFIG_MIPS_INSANE_LARGE is not set
136 196
137# 197#
@@ -141,7 +201,6 @@ CONFIG_HW_HAS_PCI=y
141CONFIG_PCI=y 201CONFIG_PCI=y
142CONFIG_PCI_DOMAINS=y 202CONFIG_PCI_DOMAINS=y
143CONFIG_PCI_LEGACY_PROC=y 203CONFIG_PCI_LEGACY_PROC=y
144CONFIG_PCI_NAMES=y
145CONFIG_MMU=y 204CONFIG_MMU=y
146 205
147# 206#
@@ -150,10 +209,6 @@ CONFIG_MMU=y
150# CONFIG_PCCARD is not set 209# CONFIG_PCCARD is not set
151 210
152# 211#
153# PC-card bridges
154#
155
156#
157# PCI Hotplug Support 212# PCI Hotplug Support
158# 213#
159# CONFIG_HOTPLUG_PCI is not set 214# CONFIG_HOTPLUG_PCI is not set
@@ -163,7 +218,7 @@ CONFIG_MMU=y
163# 218#
164CONFIG_BINFMT_ELF=y 219CONFIG_BINFMT_ELF=y
165# CONFIG_BINFMT_MISC is not set 220# CONFIG_BINFMT_MISC is not set
166# CONFIG_BUILD_ELF64 is not set 221CONFIG_BUILD_ELF64=y
167CONFIG_MIPS32_COMPAT=y 222CONFIG_MIPS32_COMPAT=y
168CONFIG_COMPAT=y 223CONFIG_COMPAT=y
169CONFIG_MIPS32_O32=y 224CONFIG_MIPS32_O32=y
@@ -171,6 +226,111 @@ CONFIG_MIPS32_O32=y
171CONFIG_BINFMT_ELF32=y 226CONFIG_BINFMT_ELF32=y
172 227
173# 228#
229# Networking
230#
231CONFIG_NET=y
232
233#
234# Networking options
235#
236CONFIG_PACKET=y
237CONFIG_PACKET_MMAP=y
238CONFIG_UNIX=y
239CONFIG_XFRM=y
240CONFIG_XFRM_USER=m
241CONFIG_NET_KEY=y
242CONFIG_INET=y
243CONFIG_IP_MULTICAST=y
244# CONFIG_IP_ADVANCED_ROUTER is not set
245CONFIG_IP_FIB_HASH=y
246CONFIG_IP_PNP=y
247# CONFIG_IP_PNP_DHCP is not set
248# CONFIG_IP_PNP_BOOTP is not set
249# CONFIG_IP_PNP_RARP is not set
250# CONFIG_NET_IPIP is not set
251# CONFIG_NET_IPGRE is not set
252# CONFIG_IP_MROUTE is not set
253# CONFIG_ARPD is not set
254# CONFIG_SYN_COOKIES is not set
255# CONFIG_INET_AH is not set
256# CONFIG_INET_ESP is not set
257# CONFIG_INET_IPCOMP is not set
258CONFIG_INET_TUNNEL=m
259CONFIG_INET_DIAG=y
260CONFIG_INET_TCP_DIAG=y
261# CONFIG_TCP_CONG_ADVANCED is not set
262CONFIG_TCP_CONG_BIC=y
263# CONFIG_IPV6 is not set
264# CONFIG_NETFILTER is not set
265
266#
267# DCCP Configuration (EXPERIMENTAL)
268#
269# CONFIG_IP_DCCP is not set
270
271#
272# SCTP Configuration (EXPERIMENTAL)
273#
274# CONFIG_IP_SCTP is not set
275# CONFIG_ATM is not set
276# CONFIG_BRIDGE is not set
277# CONFIG_VLAN_8021Q is not set
278# CONFIG_DECNET is not set
279# CONFIG_LLC2 is not set
280# CONFIG_IPX is not set
281# CONFIG_ATALK is not set
282# CONFIG_X25 is not set
283# CONFIG_LAPB is not set
284# CONFIG_NET_DIVERT is not set
285# CONFIG_ECONET is not set
286# CONFIG_WAN_ROUTER is not set
287CONFIG_NET_SCHED=y
288# CONFIG_NET_SCH_CLK_JIFFIES is not set
289CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y
290# CONFIG_NET_SCH_CLK_CPU is not set
291CONFIG_NET_SCH_CBQ=m
292CONFIG_NET_SCH_HTB=m
293CONFIG_NET_SCH_HFSC=m
294CONFIG_NET_SCH_PRIO=m
295CONFIG_NET_SCH_RED=m
296CONFIG_NET_SCH_SFQ=m
297CONFIG_NET_SCH_TEQL=m
298CONFIG_NET_SCH_TBF=m
299CONFIG_NET_SCH_GRED=m
300CONFIG_NET_SCH_DSMARK=m
301CONFIG_NET_SCH_NETEM=m
302CONFIG_NET_SCH_INGRESS=m
303CONFIG_NET_QOS=y
304CONFIG_NET_ESTIMATOR=y
305CONFIG_NET_CLS=y
306CONFIG_NET_CLS_BASIC=m
307CONFIG_NET_CLS_TCINDEX=m
308CONFIG_NET_CLS_ROUTE4=m
309CONFIG_NET_CLS_ROUTE=y
310CONFIG_NET_CLS_FW=m
311CONFIG_NET_CLS_U32=m
312# CONFIG_CLS_U32_PERF is not set
313# CONFIG_NET_CLS_IND is not set
314CONFIG_NET_CLS_RSVP=m
315CONFIG_NET_CLS_RSVP6=m
316# CONFIG_NET_EMATCH is not set
317# CONFIG_NET_CLS_ACT is not set
318CONFIG_NET_CLS_POLICE=y
319
320#
321# Network testing
322#
323# CONFIG_NET_PKTGEN is not set
324# CONFIG_HAMRADIO is not set
325# CONFIG_IRDA is not set
326# CONFIG_BT is not set
327CONFIG_IEEE80211=m
328# CONFIG_IEEE80211_DEBUG is not set
329CONFIG_IEEE80211_CRYPT_WEP=m
330CONFIG_IEEE80211_CRYPT_CCMP=m
331CONFIG_IEEE80211_CRYPT_TKIP=m
332
333#
174# Device Drivers 334# Device Drivers
175# 335#
176 336
@@ -179,7 +339,12 @@ CONFIG_BINFMT_ELF32=y
179# 339#
180CONFIG_STANDALONE=y 340CONFIG_STANDALONE=y
181CONFIG_PREVENT_FIRMWARE_BUILD=y 341CONFIG_PREVENT_FIRMWARE_BUILD=y
182# CONFIG_FW_LOADER is not set 342CONFIG_FW_LOADER=m
343
344#
345# Connector - unified userspace <-> kernelspace linker
346#
347CONFIG_CONNECTOR=m
183 348
184# 349#
185# Memory Technology Devices (MTD) 350# Memory Technology Devices (MTD)
@@ -198,7 +363,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
198# 363#
199# Block devices 364# Block devices
200# 365#
201# CONFIG_BLK_DEV_FD is not set
202# CONFIG_BLK_CPQ_DA is not set 366# CONFIG_BLK_CPQ_DA is not set
203# CONFIG_BLK_CPQ_CISS_DA is not set 367# CONFIG_BLK_CPQ_CISS_DA is not set
204# CONFIG_BLK_DEV_DAC960 is not set 368# CONFIG_BLK_DEV_DAC960 is not set
@@ -210,7 +374,6 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m
210# CONFIG_BLK_DEV_SX8 is not set 374# CONFIG_BLK_DEV_SX8 is not set
211# CONFIG_BLK_DEV_RAM is not set 375# CONFIG_BLK_DEV_RAM is not set
212CONFIG_BLK_DEV_RAM_COUNT=16 376CONFIG_BLK_DEV_RAM_COUNT=16
213CONFIG_INITRAMFS_SOURCE=""
214CONFIG_CDROM_PKTCDVD=m 377CONFIG_CDROM_PKTCDVD=m
215CONFIG_CDROM_PKTCDVD_BUFFERS=8 378CONFIG_CDROM_PKTCDVD_BUFFERS=8
216# CONFIG_CDROM_PKTCDVD_WCACHE is not set 379# CONFIG_CDROM_PKTCDVD_WCACHE is not set
@@ -232,6 +395,7 @@ CONFIG_ATA_OVER_ETH=m
232# 395#
233# SCSI device support 396# SCSI device support
234# 397#
398CONFIG_RAID_ATTRS=m
235CONFIG_SCSI=y 399CONFIG_SCSI=y
236CONFIG_SCSI_PROC_FS=y 400CONFIG_SCSI_PROC_FS=y
237 401
@@ -241,8 +405,10 @@ CONFIG_SCSI_PROC_FS=y
241CONFIG_BLK_DEV_SD=y 405CONFIG_BLK_DEV_SD=y
242CONFIG_CHR_DEV_ST=y 406CONFIG_CHR_DEV_ST=y
243# CONFIG_CHR_DEV_OSST is not set 407# CONFIG_CHR_DEV_OSST is not set
244# CONFIG_BLK_DEV_SR is not set 408CONFIG_BLK_DEV_SR=m
245# CONFIG_CHR_DEV_SG is not set 409CONFIG_BLK_DEV_SR_VENDOR=y
410CONFIG_CHR_DEV_SG=m
411CONFIG_CHR_DEV_SCH=m
246 412
247# 413#
248# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 414# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -256,7 +422,8 @@ CONFIG_SCSI_LOGGING=y
256# 422#
257CONFIG_SCSI_SPI_ATTRS=y 423CONFIG_SCSI_SPI_ATTRS=y
258# CONFIG_SCSI_FC_ATTRS is not set 424# CONFIG_SCSI_FC_ATTRS is not set
259# CONFIG_SCSI_ISCSI_ATTRS is not set 425CONFIG_SCSI_ISCSI_ATTRS=m
426CONFIG_SCSI_SAS_ATTRS=m
260 427
261# 428#
262# SCSI low-level drivers 429# SCSI low-level drivers
@@ -271,26 +438,24 @@ CONFIG_SCSI_SPI_ATTRS=y
271# CONFIG_MEGARAID_NEWGEN is not set 438# CONFIG_MEGARAID_NEWGEN is not set
272# CONFIG_MEGARAID_LEGACY is not set 439# CONFIG_MEGARAID_LEGACY is not set
273# CONFIG_SCSI_SATA is not set 440# CONFIG_SCSI_SATA is not set
274# CONFIG_SCSI_BUSLOGIC is not set
275# CONFIG_SCSI_DMX3191D is not set 441# CONFIG_SCSI_DMX3191D is not set
276# CONFIG_SCSI_EATA is not set
277# CONFIG_SCSI_EATA_PIO is not set
278# CONFIG_SCSI_FUTURE_DOMAIN is not set 442# CONFIG_SCSI_FUTURE_DOMAIN is not set
279# CONFIG_SCSI_GDTH is not set
280# CONFIG_SCSI_IPS is not set 443# CONFIG_SCSI_IPS is not set
281# CONFIG_SCSI_INITIO is not set 444# CONFIG_SCSI_INITIO is not set
282# CONFIG_SCSI_INIA100 is not set 445# CONFIG_SCSI_INIA100 is not set
283# CONFIG_SCSI_SYM53C8XX_2 is not set 446# CONFIG_SCSI_SYM53C8XX_2 is not set
284# CONFIG_SCSI_IPR is not set 447# CONFIG_SCSI_IPR is not set
285CONFIG_SCSI_QLOGIC_ISP=y
286# CONFIG_SCSI_QLOGIC_FC is not set 448# CONFIG_SCSI_QLOGIC_FC is not set
287# CONFIG_SCSI_QLOGIC_1280 is not set 449CONFIG_SCSI_QLOGIC_1280=y
450CONFIG_SCSI_QLOGIC_1280_1040=y
288CONFIG_SCSI_QLA2XXX=y 451CONFIG_SCSI_QLA2XXX=y
289# CONFIG_SCSI_QLA21XX is not set 452# CONFIG_SCSI_QLA21XX is not set
290# CONFIG_SCSI_QLA22XX is not set 453# CONFIG_SCSI_QLA22XX is not set
291# CONFIG_SCSI_QLA2300 is not set 454# CONFIG_SCSI_QLA2300 is not set
292# CONFIG_SCSI_QLA2322 is not set 455# CONFIG_SCSI_QLA2322 is not set
293# CONFIG_SCSI_QLA6312 is not set 456# CONFIG_SCSI_QLA6312 is not set
457# CONFIG_SCSI_QLA24XX is not set
458# CONFIG_SCSI_LPFC is not set
294# CONFIG_SCSI_DC395x is not set 459# CONFIG_SCSI_DC395x is not set
295# CONFIG_SCSI_DC390T is not set 460# CONFIG_SCSI_DC390T is not set
296# CONFIG_SCSI_DEBUG is not set 461# CONFIG_SCSI_DEBUG is not set
@@ -313,11 +478,15 @@ CONFIG_DM_CRYPT=m
313CONFIG_DM_SNAPSHOT=m 478CONFIG_DM_SNAPSHOT=m
314CONFIG_DM_MIRROR=m 479CONFIG_DM_MIRROR=m
315CONFIG_DM_ZERO=m 480CONFIG_DM_ZERO=m
481CONFIG_DM_MULTIPATH=m
482CONFIG_DM_MULTIPATH_EMC=m
316 483
317# 484#
318# Fusion MPT device support 485# Fusion MPT device support
319# 486#
320# CONFIG_FUSION is not set 487# CONFIG_FUSION is not set
488# CONFIG_FUSION_SPI is not set
489# CONFIG_FUSION_FC is not set
321 490
322# 491#
323# IEEE 1394 (FireWire) support 492# IEEE 1394 (FireWire) support
@@ -330,107 +499,13 @@ CONFIG_DM_ZERO=m
330# CONFIG_I2O is not set 499# CONFIG_I2O is not set
331 500
332# 501#
333# Networking support 502# Network device support
334#
335CONFIG_NET=y
336
337#
338# Networking options
339#
340CONFIG_PACKET=y
341CONFIG_PACKET_MMAP=y
342CONFIG_NETLINK_DEV=y
343CONFIG_UNIX=y
344CONFIG_NET_KEY=y
345CONFIG_INET=y
346CONFIG_IP_MULTICAST=y
347# CONFIG_IP_ADVANCED_ROUTER is not set
348CONFIG_IP_PNP=y
349# CONFIG_IP_PNP_DHCP is not set
350# CONFIG_IP_PNP_BOOTP is not set
351# CONFIG_IP_PNP_RARP is not set
352# CONFIG_NET_IPIP is not set
353# CONFIG_NET_IPGRE is not set
354# CONFIG_IP_MROUTE is not set
355# CONFIG_ARPD is not set
356# CONFIG_SYN_COOKIES is not set
357# CONFIG_INET_AH is not set
358# CONFIG_INET_ESP is not set
359# CONFIG_INET_IPCOMP is not set
360CONFIG_INET_TUNNEL=m
361CONFIG_IP_TCPDIAG=m
362# CONFIG_IP_TCPDIAG_IPV6 is not set
363# CONFIG_IPV6 is not set
364# CONFIG_NETFILTER is not set
365CONFIG_XFRM=y
366CONFIG_XFRM_USER=m
367
368#
369# SCTP Configuration (EXPERIMENTAL)
370#
371# CONFIG_IP_SCTP is not set
372# CONFIG_ATM is not set
373# CONFIG_BRIDGE is not set
374# CONFIG_VLAN_8021Q is not set
375# CONFIG_DECNET is not set
376# CONFIG_LLC2 is not set
377# CONFIG_IPX is not set
378# CONFIG_ATALK is not set
379# CONFIG_X25 is not set
380# CONFIG_LAPB is not set
381# CONFIG_NET_DIVERT is not set
382# CONFIG_ECONET is not set
383# CONFIG_WAN_ROUTER is not set
384
385#
386# QoS and/or fair queueing
387#
388CONFIG_NET_SCHED=y
389# CONFIG_NET_SCH_CLK_JIFFIES is not set
390CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y
391# CONFIG_NET_SCH_CLK_CPU is not set
392CONFIG_NET_SCH_CBQ=m
393CONFIG_NET_SCH_HTB=m
394CONFIG_NET_SCH_HFSC=m
395CONFIG_NET_SCH_PRIO=m
396CONFIG_NET_SCH_RED=m
397CONFIG_NET_SCH_SFQ=m
398CONFIG_NET_SCH_TEQL=m
399CONFIG_NET_SCH_TBF=m
400CONFIG_NET_SCH_GRED=m
401CONFIG_NET_SCH_DSMARK=m
402CONFIG_NET_SCH_NETEM=m
403CONFIG_NET_SCH_INGRESS=m
404CONFIG_NET_QOS=y
405CONFIG_NET_ESTIMATOR=y
406CONFIG_NET_CLS=y
407CONFIG_NET_CLS_TCINDEX=m
408CONFIG_NET_CLS_ROUTE4=m
409CONFIG_NET_CLS_ROUTE=y
410CONFIG_NET_CLS_FW=m
411CONFIG_NET_CLS_U32=m
412# CONFIG_CLS_U32_PERF is not set
413# CONFIG_NET_CLS_IND is not set
414CONFIG_NET_CLS_RSVP=m
415CONFIG_NET_CLS_RSVP6=m
416# CONFIG_NET_CLS_ACT is not set
417CONFIG_NET_CLS_POLICE=y
418
419#
420# Network testing
421# 503#
422# CONFIG_NET_PKTGEN is not set
423# CONFIG_NETPOLL is not set
424# CONFIG_NET_POLL_CONTROLLER is not set
425# CONFIG_HAMRADIO is not set
426# CONFIG_IRDA is not set
427# CONFIG_BT is not set
428CONFIG_NETDEVICES=y 504CONFIG_NETDEVICES=y
429# CONFIG_DUMMY is not set 505# CONFIG_DUMMY is not set
430# CONFIG_BONDING is not set 506# CONFIG_BONDING is not set
431# CONFIG_EQUALIZER is not set 507# CONFIG_EQUALIZER is not set
432# CONFIG_TUN is not set 508# CONFIG_TUN is not set
433# CONFIG_ETHERTAP is not set
434 509
435# 510#
436# ARCnet devices 511# ARCnet devices
@@ -438,13 +513,25 @@ CONFIG_NETDEVICES=y
438# CONFIG_ARCNET is not set 513# CONFIG_ARCNET is not set
439 514
440# 515#
516# PHY device support
517#
518CONFIG_PHYLIB=m
519CONFIG_PHYCONTROL=y
520
521#
522# MII PHY device drivers
523#
524CONFIG_MARVELL_PHY=m
525CONFIG_DAVICOM_PHY=m
526CONFIG_QSEMI_PHY=m
527CONFIG_LXT_PHY=m
528CONFIG_CICADA_PHY=m
529
530#
441# Ethernet (10 or 100Mbit) 531# Ethernet (10 or 100Mbit)
442# 532#
443CONFIG_NET_ETHERNET=y 533CONFIG_NET_ETHERNET=y
444CONFIG_MII=y 534CONFIG_MII=y
445CONFIG_SGI_IOC3_ETH=y
446CONFIG_SGI_IOC3_ETH_HW_RX_CSUM=y
447CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y
448# CONFIG_HAPPYMEAL is not set 535# CONFIG_HAPPYMEAL is not set
449# CONFIG_SUNGEM is not set 536# CONFIG_SUNGEM is not set
450# CONFIG_NET_VENDOR_3COM is not set 537# CONFIG_NET_VENDOR_3COM is not set
@@ -466,12 +553,16 @@ CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y
466# CONFIG_HAMACHI is not set 553# CONFIG_HAMACHI is not set
467# CONFIG_YELLOWFIN is not set 554# CONFIG_YELLOWFIN is not set
468# CONFIG_R8169 is not set 555# CONFIG_R8169 is not set
556# CONFIG_SIS190 is not set
557# CONFIG_SKGE is not set
469# CONFIG_SK98LIN is not set 558# CONFIG_SK98LIN is not set
470# CONFIG_TIGON3 is not set 559# CONFIG_TIGON3 is not set
560# CONFIG_BNX2 is not set
471 561
472# 562#
473# Ethernet (10000 Mbit) 563# Ethernet (10000 Mbit)
474# 564#
565# CONFIG_CHELSIO_T1 is not set
475# CONFIG_IXGB is not set 566# CONFIG_IXGB is not set
476# CONFIG_S2IO is not set 567# CONFIG_S2IO is not set
477 568
@@ -484,6 +575,8 @@ CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y
484# Wireless LAN (non-hamradio) 575# Wireless LAN (non-hamradio)
485# 576#
486# CONFIG_NET_RADIO is not set 577# CONFIG_NET_RADIO is not set
578# CONFIG_IPW_DEBUG is not set
579CONFIG_IPW2200=m
487 580
488# 581#
489# Wan interfaces 582# Wan interfaces
@@ -496,6 +589,8 @@ CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y
496# CONFIG_NET_FC is not set 589# CONFIG_NET_FC is not set
497# CONFIG_SHAPER is not set 590# CONFIG_SHAPER is not set
498# CONFIG_NETCONSOLE is not set 591# CONFIG_NETCONSOLE is not set
592# CONFIG_NETPOLL is not set
593# CONFIG_NET_POLL_CONTROLLER is not set
499 594
500# 595#
501# ISDN subsystem 596# ISDN subsystem
@@ -513,25 +608,15 @@ CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y
513# CONFIG_INPUT is not set 608# CONFIG_INPUT is not set
514 609
515# 610#
516# Userland interfaces 611# Hardware I/O ports
517#
518
519#
520# Input I/O drivers
521# 612#
522# CONFIG_GAMEPORT is not set
523CONFIG_SOUND_GAMEPORT=y
524CONFIG_SERIO=y 613CONFIG_SERIO=y
525# CONFIG_SERIO_I8042 is not set 614# CONFIG_SERIO_I8042 is not set
526CONFIG_SERIO_SERPORT=y 615CONFIG_SERIO_SERPORT=y
527# CONFIG_SERIO_CT82C710 is not set
528# CONFIG_SERIO_PCIPS2 is not set 616# CONFIG_SERIO_PCIPS2 is not set
529# CONFIG_SERIO_LIBPS2 is not set 617CONFIG_SERIO_LIBPS2=m
530CONFIG_SERIO_RAW=m 618CONFIG_SERIO_RAW=m
531 619# CONFIG_GAMEPORT is not set
532#
533# Input Device Drivers
534#
535 620
536# 621#
537# Character devices 622# Character devices
@@ -549,7 +634,6 @@ CONFIG_SERIAL_8250_EXTENDED=y
549CONFIG_SERIAL_8250_MANY_PORTS=y 634CONFIG_SERIAL_8250_MANY_PORTS=y
550CONFIG_SERIAL_8250_SHARE_IRQ=y 635CONFIG_SERIAL_8250_SHARE_IRQ=y
551# CONFIG_SERIAL_8250_DETECT_IRQ is not set 636# CONFIG_SERIAL_8250_DETECT_IRQ is not set
552# CONFIG_SERIAL_8250_MULTIPORT is not set
553# CONFIG_SERIAL_8250_RSA is not set 637# CONFIG_SERIAL_8250_RSA is not set
554 638
555# 639#
@@ -557,6 +641,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
557# 641#
558CONFIG_SERIAL_CORE=y 642CONFIG_SERIAL_CORE=y
559CONFIG_SERIAL_CORE_CONSOLE=y 643CONFIG_SERIAL_CORE_CONSOLE=y
644# CONFIG_SERIAL_JSM is not set
560CONFIG_UNIX98_PTYS=y 645CONFIG_UNIX98_PTYS=y
561CONFIG_LEGACY_PTYS=y 646CONFIG_LEGACY_PTYS=y
562CONFIG_LEGACY_PTY_COUNT=256 647CONFIG_LEGACY_PTY_COUNT=256
@@ -584,6 +669,11 @@ CONFIG_SGI_IP27_RTC=y
584# CONFIG_RAW_DRIVER is not set 669# CONFIG_RAW_DRIVER is not set
585 670
586# 671#
672# TPM devices
673#
674# CONFIG_TCG_TPM is not set
675
676#
587# I2C support 677# I2C support
588# 678#
589# CONFIG_I2C is not set 679# CONFIG_I2C is not set
@@ -594,10 +684,20 @@ CONFIG_SGI_IP27_RTC=y
594# CONFIG_W1 is not set 684# CONFIG_W1 is not set
595 685
596# 686#
687# Hardware Monitoring support
688#
689# CONFIG_HWMON is not set
690# CONFIG_HWMON_VID is not set
691
692#
597# Misc devices 693# Misc devices
598# 694#
599 695
600# 696#
697# Multimedia Capabilities Port drivers
698#
699
700#
601# Multimedia devices 701# Multimedia devices
602# 702#
603# CONFIG_VIDEO_DEV is not set 703# CONFIG_VIDEO_DEV is not set
@@ -611,7 +711,6 @@ CONFIG_SGI_IP27_RTC=y
611# Graphics support 711# Graphics support
612# 712#
613# CONFIG_FB is not set 713# CONFIG_FB is not set
614# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
615 714
616# 715#
617# Sound 716# Sound
@@ -621,13 +720,9 @@ CONFIG_SGI_IP27_RTC=y
621# 720#
622# USB support 721# USB support
623# 722#
624# CONFIG_USB is not set
625CONFIG_USB_ARCH_HAS_HCD=y 723CONFIG_USB_ARCH_HAS_HCD=y
626CONFIG_USB_ARCH_HAS_OHCI=y 724CONFIG_USB_ARCH_HAS_OHCI=y
627 725# CONFIG_USB is not set
628#
629# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
630#
631 726
632# 727#
633# USB Gadget Support 728# USB Gadget Support
@@ -645,12 +740,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y
645# CONFIG_INFINIBAND is not set 740# CONFIG_INFINIBAND is not set
646 741
647# 742#
743# SN Devices
744#
745
746#
648# File systems 747# File systems
649# 748#
650CONFIG_EXT2_FS=y 749CONFIG_EXT2_FS=y
651CONFIG_EXT2_FS_XATTR=y 750CONFIG_EXT2_FS_XATTR=y
652CONFIG_EXT2_FS_POSIX_ACL=y 751CONFIG_EXT2_FS_POSIX_ACL=y
653CONFIG_EXT2_FS_SECURITY=y 752CONFIG_EXT2_FS_SECURITY=y
753# CONFIG_EXT2_FS_XIP is not set
654CONFIG_EXT3_FS=y 754CONFIG_EXT3_FS=y
655CONFIG_EXT3_FS_XATTR=y 755CONFIG_EXT3_FS_XATTR=y
656CONFIG_EXT3_FS_POSIX_ACL=y 756CONFIG_EXT3_FS_POSIX_ACL=y
@@ -662,17 +762,19 @@ CONFIG_FS_MBCACHE=y
662# CONFIG_JFS_FS is not set 762# CONFIG_JFS_FS is not set
663CONFIG_FS_POSIX_ACL=y 763CONFIG_FS_POSIX_ACL=y
664CONFIG_XFS_FS=m 764CONFIG_XFS_FS=m
665# CONFIG_XFS_RT is not set 765CONFIG_XFS_QUOTA=m
666CONFIG_XFS_QUOTA=y
667CONFIG_XFS_SECURITY=y 766CONFIG_XFS_SECURITY=y
668CONFIG_XFS_POSIX_ACL=y 767CONFIG_XFS_POSIX_ACL=y
768# CONFIG_XFS_RT is not set
669# CONFIG_MINIX_FS is not set 769# CONFIG_MINIX_FS is not set
670# CONFIG_ROMFS_FS is not set 770# CONFIG_ROMFS_FS is not set
771CONFIG_INOTIFY=y
671# CONFIG_QUOTA is not set 772# CONFIG_QUOTA is not set
672CONFIG_QUOTACTL=y 773CONFIG_QUOTACTL=y
673CONFIG_DNOTIFY=y 774CONFIG_DNOTIFY=y
674CONFIG_AUTOFS_FS=m 775CONFIG_AUTOFS_FS=m
675# CONFIG_AUTOFS4_FS is not set 776# CONFIG_AUTOFS4_FS is not set
777CONFIG_FUSE_FS=m
676 778
677# 779#
678# CD-ROM/DVD Filesystems 780# CD-ROM/DVD Filesystems
@@ -693,12 +795,10 @@ CONFIG_AUTOFS_FS=m
693CONFIG_PROC_FS=y 795CONFIG_PROC_FS=y
694CONFIG_PROC_KCORE=y 796CONFIG_PROC_KCORE=y
695CONFIG_SYSFS=y 797CONFIG_SYSFS=y
696# CONFIG_DEVFS_FS is not set
697CONFIG_DEVPTS_FS_XATTR=y
698CONFIG_DEVPTS_FS_SECURITY=y
699# CONFIG_TMPFS is not set 798# CONFIG_TMPFS is not set
700# CONFIG_HUGETLB_PAGE is not set 799# CONFIG_HUGETLB_PAGE is not set
701CONFIG_RAMFS=y 800CONFIG_RAMFS=y
801CONFIG_RELAYFS_FS=m
702 802
703# 803#
704# Miscellaneous filesystems 804# Miscellaneous filesystems
@@ -722,13 +822,14 @@ CONFIG_RAMFS=y
722# 822#
723CONFIG_NFS_FS=y 823CONFIG_NFS_FS=y
724CONFIG_NFS_V3=y 824CONFIG_NFS_V3=y
825# CONFIG_NFS_V3_ACL is not set
725# CONFIG_NFS_V4 is not set 826# CONFIG_NFS_V4 is not set
726# CONFIG_NFS_DIRECTIO is not set 827# CONFIG_NFS_DIRECTIO is not set
727# CONFIG_NFSD is not set 828# CONFIG_NFSD is not set
728# CONFIG_ROOT_NFS is not set 829# CONFIG_ROOT_NFS is not set
729CONFIG_LOCKD=y 830CONFIG_LOCKD=y
730CONFIG_LOCKD_V4=y 831CONFIG_LOCKD_V4=y
731# CONFIG_EXPORTFS is not set 832CONFIG_NFS_COMMON=y
732CONFIG_SUNRPC=y 833CONFIG_SUNRPC=y
733CONFIG_SUNRPC_GSS=y 834CONFIG_SUNRPC_GSS=y
734CONFIG_RPCSEC_GSS_KRB5=y 835CONFIG_RPCSEC_GSS_KRB5=y
@@ -738,6 +839,7 @@ CONFIG_RPCSEC_GSS_KRB5=y
738# CONFIG_NCP_FS is not set 839# CONFIG_NCP_FS is not set
739# CONFIG_CODA_FS is not set 840# CONFIG_CODA_FS is not set
740# CONFIG_AFS_FS is not set 841# CONFIG_AFS_FS is not set
842# CONFIG_9P_FS is not set
741 843
742# 844#
743# Partition Types 845# Partition Types
@@ -772,7 +874,9 @@ CONFIG_SGI_PARTITION=y
772# 874#
773# Kernel hacking 875# Kernel hacking
774# 876#
877# CONFIG_PRINTK_TIME is not set
775# CONFIG_DEBUG_KERNEL is not set 878# CONFIG_DEBUG_KERNEL is not set
879CONFIG_LOG_BUF_SHIFT=15
776CONFIG_CROSSCOMPILE=y 880CONFIG_CROSSCOMPILE=y
777CONFIG_CMDLINE="" 881CONFIG_CMDLINE=""
778 882
@@ -788,28 +892,29 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
788# 892#
789CONFIG_CRYPTO=y 893CONFIG_CRYPTO=y
790CONFIG_CRYPTO_HMAC=y 894CONFIG_CRYPTO_HMAC=y
791CONFIG_CRYPTO_NULL=y 895CONFIG_CRYPTO_NULL=m
792CONFIG_CRYPTO_MD4=y 896CONFIG_CRYPTO_MD4=m
793CONFIG_CRYPTO_MD5=y 897CONFIG_CRYPTO_MD5=y
794CONFIG_CRYPTO_SHA1=y 898CONFIG_CRYPTO_SHA1=m
795CONFIG_CRYPTO_SHA256=y 899CONFIG_CRYPTO_SHA256=m
796CONFIG_CRYPTO_SHA512=y 900CONFIG_CRYPTO_SHA512=m
797CONFIG_CRYPTO_WP512=m 901CONFIG_CRYPTO_WP512=m
902CONFIG_CRYPTO_TGR192=m
798CONFIG_CRYPTO_DES=y 903CONFIG_CRYPTO_DES=y
799CONFIG_CRYPTO_BLOWFISH=y 904CONFIG_CRYPTO_BLOWFISH=m
800CONFIG_CRYPTO_TWOFISH=y 905CONFIG_CRYPTO_TWOFISH=m
801CONFIG_CRYPTO_SERPENT=y 906CONFIG_CRYPTO_SERPENT=m
802CONFIG_CRYPTO_AES=m 907CONFIG_CRYPTO_AES=m
803CONFIG_CRYPTO_CAST5=y 908CONFIG_CRYPTO_CAST5=m
804CONFIG_CRYPTO_CAST6=y 909CONFIG_CRYPTO_CAST6=m
805CONFIG_CRYPTO_TEA=m 910CONFIG_CRYPTO_TEA=m
806CONFIG_CRYPTO_ARC4=y 911CONFIG_CRYPTO_ARC4=m
807CONFIG_CRYPTO_KHAZAD=m 912CONFIG_CRYPTO_KHAZAD=m
808CONFIG_CRYPTO_ANUBIS=m 913CONFIG_CRYPTO_ANUBIS=m
809CONFIG_CRYPTO_DEFLATE=y 914CONFIG_CRYPTO_DEFLATE=m
810CONFIG_CRYPTO_MICHAEL_MIC=y 915CONFIG_CRYPTO_MICHAEL_MIC=m
811CONFIG_CRYPTO_CRC32C=m 916CONFIG_CRYPTO_CRC32C=m
812CONFIG_CRYPTO_TEST=m 917# CONFIG_CRYPTO_TEST is not set
813 918
814# 919#
815# Hardware crypto devices 920# Hardware crypto devices
@@ -819,9 +924,8 @@ CONFIG_CRYPTO_TEST=m
819# Library routines 924# Library routines
820# 925#
821# CONFIG_CRC_CCITT is not set 926# CONFIG_CRC_CCITT is not set
927CONFIG_CRC16=m
822CONFIG_CRC32=y 928CONFIG_CRC32=y
823CONFIG_LIBCRC32C=m 929CONFIG_LIBCRC32C=m
824CONFIG_ZLIB_INFLATE=y 930CONFIG_ZLIB_INFLATE=m
825CONFIG_ZLIB_DEFLATE=y 931CONFIG_ZLIB_DEFLATE=m
826CONFIG_GENERIC_HARDIRQS=y
827CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index b26e1173365d..bf8fb95b21dc 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -1,11 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:04 2005 4# Thu Oct 20 22:26:07 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7CONFIG_64BIT=y
8CONFIG_64BIT=y
9 7
10# 8#
11# Code maturity level options 9# Code maturity level options
@@ -13,11 +11,13 @@ CONFIG_64BIT=y
13CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
14CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
15CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
16 15
17# 16#
18# General setup 17# General setup
19# 18#
20CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
21CONFIG_SWAP=y 21CONFIG_SWAP=y
22CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
23# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
@@ -25,13 +25,16 @@ CONFIG_BSD_PROCESS_ACCT=y
25# CONFIG_BSD_PROCESS_ACCT_V3 is not set 25# CONFIG_BSD_PROCESS_ACCT_V3 is not set
26CONFIG_SYSCTL=y 26CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 27# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14 28CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 29CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 30# CONFIG_IKCONFIG is not set
31CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 32CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 33CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 38CONFIG_FUTEX=y
36CONFIG_EPOLL=y 39CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 44CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 45CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
44 48
45# 49#
46# Loadable module support 50# Loadable module support
@@ -50,42 +54,71 @@ CONFIG_CC_ALIGN_JUMPS=0
50# 54#
51# Machine selection 55# Machine selection
52# 56#
53# CONFIG_MACH_JAZZ is not set 57# CONFIG_MIPS_MTX1 is not set
54# CONFIG_MACH_VR41XX is not set 58# CONFIG_MIPS_BOSPORUS is not set
59# CONFIG_MIPS_PB1000 is not set
60# CONFIG_MIPS_PB1100 is not set
61# CONFIG_MIPS_PB1500 is not set
62# CONFIG_MIPS_PB1550 is not set
63# CONFIG_MIPS_PB1200 is not set
64# CONFIG_MIPS_DB1000 is not set
65# CONFIG_MIPS_DB1100 is not set
66# CONFIG_MIPS_DB1500 is not set
67# CONFIG_MIPS_DB1550 is not set
68# CONFIG_MIPS_DB1200 is not set
69# CONFIG_MIPS_MIRAGE is not set
55# CONFIG_MIPS_COBALT is not set 70# CONFIG_MIPS_COBALT is not set
56# CONFIG_MACH_DECSTATION is not set 71# CONFIG_MACH_DECSTATION is not set
57# CONFIG_MIPS_EV64120 is not set 72# CONFIG_MIPS_EV64120 is not set
58# CONFIG_MIPS_EV96100 is not set 73# CONFIG_MIPS_EV96100 is not set
59# CONFIG_MIPS_IVR is not set 74# CONFIG_MIPS_IVR is not set
60# CONFIG_LASAT is not set
61# CONFIG_MIPS_ITE8172 is not set 75# CONFIG_MIPS_ITE8172 is not set
76# CONFIG_MACH_JAZZ is not set
77# CONFIG_LASAT is not set
62# CONFIG_MIPS_ATLAS is not set 78# CONFIG_MIPS_ATLAS is not set
63# CONFIG_MIPS_MALTA is not set 79# CONFIG_MIPS_MALTA is not set
64# CONFIG_MIPS_SEAD is not set 80# CONFIG_MIPS_SEAD is not set
81# CONFIG_MIPS_SIM is not set
82# CONFIG_MOMENCO_JAGUAR_ATX is not set
65# CONFIG_MOMENCO_OCELOT is not set 83# CONFIG_MOMENCO_OCELOT is not set
66# CONFIG_MOMENCO_OCELOT_G is not set
67# CONFIG_MOMENCO_OCELOT_C is not set
68# CONFIG_MOMENCO_OCELOT_3 is not set 84# CONFIG_MOMENCO_OCELOT_3 is not set
69# CONFIG_MOMENCO_JAGUAR_ATX is not set 85# CONFIG_MOMENCO_OCELOT_C is not set
70# CONFIG_PMC_YOSEMITE is not set 86# CONFIG_MOMENCO_OCELOT_G is not set
87# CONFIG_MIPS_XXS1500 is not set
88# CONFIG_PNX8550_V2PCI is not set
89# CONFIG_PNX8550_JBS is not set
71# CONFIG_DDB5074 is not set 90# CONFIG_DDB5074 is not set
72# CONFIG_DDB5476 is not set 91# CONFIG_DDB5476 is not set
73# CONFIG_DDB5477 is not set 92# CONFIG_DDB5477 is not set
74# CONFIG_NEC_OSPREY is not set 93# CONFIG_MACH_VR41XX is not set
94# CONFIG_PMC_YOSEMITE is not set
95# CONFIG_QEMU is not set
75# CONFIG_SGI_IP22 is not set 96# CONFIG_SGI_IP22 is not set
76# CONFIG_SGI_IP27 is not set 97# CONFIG_SGI_IP27 is not set
77CONFIG_SGI_IP32=y 98CONFIG_SGI_IP32=y
78# CONFIG_SIBYTE_SB1xxx_SOC is not set 99# CONFIG_SIBYTE_BIGSUR is not set
100# CONFIG_SIBYTE_SWARM is not set
101# CONFIG_SIBYTE_SENTOSA is not set
102# CONFIG_SIBYTE_RHONE is not set
103# CONFIG_SIBYTE_CARMEL is not set
104# CONFIG_SIBYTE_PTSWARM is not set
105# CONFIG_SIBYTE_LITTLESUR is not set
106# CONFIG_SIBYTE_CRHINE is not set
107# CONFIG_SIBYTE_CRHONE is not set
79# CONFIG_SNI_RM200_PCI is not set 108# CONFIG_SNI_RM200_PCI is not set
109# CONFIG_TOSHIBA_JMR3927 is not set
110# CONFIG_TOSHIBA_RBTX4927 is not set
111# CONFIG_TOSHIBA_RBTX4938 is not set
80CONFIG_RWSEM_GENERIC_SPINLOCK=y 112CONFIG_RWSEM_GENERIC_SPINLOCK=y
81CONFIG_GENERIC_CALIBRATE_DELAY=y 113CONFIG_GENERIC_CALIBRATE_DELAY=y
82CONFIG_HAVE_DEC_LOCK=y
83CONFIG_ARC=y 114CONFIG_ARC=y
84CONFIG_DMA_IP32=y 115CONFIG_DMA_IP32=y
85CONFIG_OWN_DMA=y
86CONFIG_DMA_NONCOHERENT=y 116CONFIG_DMA_NONCOHERENT=y
87CONFIG_DMA_NEED_PCI_MAP_STATE=y 117CONFIG_DMA_NEED_PCI_MAP_STATE=y
118CONFIG_OWN_DMA=y
119CONFIG_CPU_BIG_ENDIAN=y
88# CONFIG_CPU_LITTLE_ENDIAN is not set 120# CONFIG_CPU_LITTLE_ENDIAN is not set
121CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
89CONFIG_ARC32=y 122CONFIG_ARC32=y
90CONFIG_BOOT_ELF32=y 123CONFIG_BOOT_ELF32=y
91CONFIG_MIPS_L1_CACHE_SHIFT=5 124CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -95,8 +128,10 @@ CONFIG_ARC_PROMLIB=y
95# 128#
96# CPU selection 129# CPU selection
97# 130#
98# CONFIG_CPU_MIPS32 is not set 131# CONFIG_CPU_MIPS32_R1 is not set
99# CONFIG_CPU_MIPS64 is not set 132# CONFIG_CPU_MIPS32_R2 is not set
133# CONFIG_CPU_MIPS64_R1 is not set
134# CONFIG_CPU_MIPS64_R2 is not set
100# CONFIG_CPU_R3000 is not set 135# CONFIG_CPU_R3000 is not set
101# CONFIG_CPU_TX39XX is not set 136# CONFIG_CPU_TX39XX is not set
102# CONFIG_CPU_VR41XX is not set 137# CONFIG_CPU_VR41XX is not set
@@ -112,6 +147,17 @@ CONFIG_CPU_R5000=y
112# CONFIG_CPU_RM7000 is not set 147# CONFIG_CPU_RM7000 is not set
113# CONFIG_CPU_RM9000 is not set 148# CONFIG_CPU_RM9000 is not set
114# CONFIG_CPU_SB1 is not set 149# CONFIG_CPU_SB1 is not set
150CONFIG_SYS_HAS_CPU_R5000=y
151CONFIG_SYS_HAS_CPU_RM7000=y
152CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
153CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
154CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
155
156#
157# Kernel type
158#
159# CONFIG_32BIT is not set
160CONFIG_64BIT=y
115CONFIG_PAGE_SIZE_4KB=y 161CONFIG_PAGE_SIZE_4KB=y
116# CONFIG_PAGE_SIZE_8KB is not set 162# CONFIG_PAGE_SIZE_8KB is not set
117# CONFIG_PAGE_SIZE_16KB is not set 163# CONFIG_PAGE_SIZE_16KB is not set
@@ -119,9 +165,22 @@ CONFIG_PAGE_SIZE_4KB=y
119CONFIG_BOARD_SCACHE=y 165CONFIG_BOARD_SCACHE=y
120CONFIG_R5000_CPU_SCACHE=y 166CONFIG_R5000_CPU_SCACHE=y
121CONFIG_RM7000_CPU_SCACHE=y 167CONFIG_RM7000_CPU_SCACHE=y
168# CONFIG_MIPS_MT is not set
122CONFIG_CPU_HAS_LLSC=y 169CONFIG_CPU_HAS_LLSC=y
123CONFIG_CPU_HAS_LLDSCD=y 170CONFIG_CPU_HAS_LLDSCD=y
124CONFIG_CPU_HAS_SYNC=y 171CONFIG_CPU_HAS_SYNC=y
172CONFIG_GENERIC_HARDIRQS=y
173CONFIG_GENERIC_IRQ_PROBE=y
174CONFIG_ARCH_FLATMEM_ENABLE=y
175CONFIG_SELECT_MEMORY_MODEL=y
176CONFIG_FLATMEM_MANUAL=y
177# CONFIG_DISCONTIGMEM_MANUAL is not set
178# CONFIG_SPARSEMEM_MANUAL is not set
179CONFIG_FLATMEM=y
180CONFIG_FLAT_NODE_MEM_MAP=y
181# CONFIG_SPARSEMEM_STATIC is not set
182# CONFIG_PREEMPT_NONE is not set
183CONFIG_PREEMPT_VOLUNTARY=y
125# CONFIG_PREEMPT is not set 184# CONFIG_PREEMPT is not set
126 185
127# 186#
@@ -130,7 +189,6 @@ CONFIG_CPU_HAS_SYNC=y
130CONFIG_HW_HAS_PCI=y 189CONFIG_HW_HAS_PCI=y
131CONFIG_PCI=y 190CONFIG_PCI=y
132CONFIG_PCI_LEGACY_PROC=y 191CONFIG_PCI_LEGACY_PROC=y
133CONFIG_PCI_NAMES=y
134CONFIG_MMU=y 192CONFIG_MMU=y
135 193
136# 194#
@@ -139,10 +197,6 @@ CONFIG_MMU=y
139# CONFIG_PCCARD is not set 197# CONFIG_PCCARD is not set
140 198
141# 199#
142# PC-card bridges
143#
144
145#
146# PCI Hotplug Support 200# PCI Hotplug Support
147# 201#
148# CONFIG_HOTPLUG_PCI is not set 202# CONFIG_HOTPLUG_PCI is not set
@@ -160,6 +214,80 @@ CONFIG_MIPS32_O32=y
160CONFIG_BINFMT_ELF32=y 214CONFIG_BINFMT_ELF32=y
161 215
162# 216#
217# Networking
218#
219CONFIG_NET=y
220
221#
222# Networking options
223#
224CONFIG_PACKET=y
225CONFIG_PACKET_MMAP=y
226CONFIG_UNIX=y
227CONFIG_XFRM=y
228CONFIG_XFRM_USER=y
229CONFIG_NET_KEY=y
230CONFIG_INET=y
231# CONFIG_IP_MULTICAST is not set
232# CONFIG_IP_ADVANCED_ROUTER is not set
233CONFIG_IP_FIB_HASH=y
234CONFIG_IP_PNP=y
235# CONFIG_IP_PNP_DHCP is not set
236CONFIG_IP_PNP_BOOTP=y
237# CONFIG_IP_PNP_RARP is not set
238# CONFIG_NET_IPIP is not set
239# CONFIG_NET_IPGRE is not set
240# CONFIG_ARPD is not set
241# CONFIG_SYN_COOKIES is not set
242# CONFIG_INET_AH is not set
243# CONFIG_INET_ESP is not set
244# CONFIG_INET_IPCOMP is not set
245CONFIG_INET_TUNNEL=y
246CONFIG_INET_DIAG=y
247CONFIG_INET_TCP_DIAG=y
248# CONFIG_TCP_CONG_ADVANCED is not set
249CONFIG_TCP_CONG_BIC=y
250# CONFIG_IPV6 is not set
251# CONFIG_NETFILTER is not set
252
253#
254# DCCP Configuration (EXPERIMENTAL)
255#
256# CONFIG_IP_DCCP is not set
257
258#
259# SCTP Configuration (EXPERIMENTAL)
260#
261# CONFIG_IP_SCTP is not set
262# CONFIG_ATM is not set
263# CONFIG_BRIDGE is not set
264# CONFIG_VLAN_8021Q is not set
265# CONFIG_DECNET is not set
266# CONFIG_LLC2 is not set
267# CONFIG_IPX is not set
268# CONFIG_ATALK is not set
269# CONFIG_X25 is not set
270# CONFIG_LAPB is not set
271# CONFIG_NET_DIVERT is not set
272# CONFIG_ECONET is not set
273# CONFIG_WAN_ROUTER is not set
274# CONFIG_NET_SCHED is not set
275# CONFIG_NET_CLS_ROUTE is not set
276
277#
278# Network testing
279#
280# CONFIG_NET_PKTGEN is not set
281# CONFIG_HAMRADIO is not set
282# CONFIG_IRDA is not set
283# CONFIG_BT is not set
284CONFIG_IEEE80211=y
285# CONFIG_IEEE80211_DEBUG is not set
286CONFIG_IEEE80211_CRYPT_WEP=y
287CONFIG_IEEE80211_CRYPT_CCMP=y
288CONFIG_IEEE80211_CRYPT_TKIP=y
289
290#
163# Device Drivers 291# Device Drivers
164# 292#
165 293
@@ -168,7 +296,12 @@ CONFIG_BINFMT_ELF32=y
168# 296#
169CONFIG_STANDALONE=y 297CONFIG_STANDALONE=y
170CONFIG_PREVENT_FIRMWARE_BUILD=y 298CONFIG_PREVENT_FIRMWARE_BUILD=y
171# CONFIG_FW_LOADER is not set 299CONFIG_FW_LOADER=y
300
301#
302# Connector - unified userspace <-> kernelspace linker
303#
304CONFIG_CONNECTOR=y
172 305
173# 306#
174# Memory Technology Devices (MTD) 307# Memory Technology Devices (MTD)
@@ -187,7 +320,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
187# 320#
188# Block devices 321# Block devices
189# 322#
190# CONFIG_BLK_DEV_FD is not set
191# CONFIG_BLK_CPQ_DA is not set 323# CONFIG_BLK_CPQ_DA is not set
192# CONFIG_BLK_CPQ_CISS_DA is not set 324# CONFIG_BLK_CPQ_CISS_DA is not set
193# CONFIG_BLK_DEV_DAC960 is not set 325# CONFIG_BLK_DEV_DAC960 is not set
@@ -199,7 +331,6 @@ CONFIG_BLK_DEV_LOOP=y
199# CONFIG_BLK_DEV_SX8 is not set 331# CONFIG_BLK_DEV_SX8 is not set
200# CONFIG_BLK_DEV_RAM is not set 332# CONFIG_BLK_DEV_RAM is not set
201CONFIG_BLK_DEV_RAM_COUNT=16 333CONFIG_BLK_DEV_RAM_COUNT=16
202CONFIG_INITRAMFS_SOURCE=""
203CONFIG_CDROM_PKTCDVD=y 334CONFIG_CDROM_PKTCDVD=y
204CONFIG_CDROM_PKTCDVD_BUFFERS=8 335CONFIG_CDROM_PKTCDVD_BUFFERS=8
205# CONFIG_CDROM_PKTCDVD_WCACHE is not set 336# CONFIG_CDROM_PKTCDVD_WCACHE is not set
@@ -221,6 +352,7 @@ CONFIG_ATA_OVER_ETH=y
221# 352#
222# SCSI device support 353# SCSI device support
223# 354#
355CONFIG_RAID_ATTRS=y
224CONFIG_SCSI=y 356CONFIG_SCSI=y
225CONFIG_SCSI_PROC_FS=y 357CONFIG_SCSI_PROC_FS=y
226 358
@@ -233,6 +365,7 @@ CONFIG_CHR_DEV_OSST=y
233CONFIG_BLK_DEV_SR=y 365CONFIG_BLK_DEV_SR=y
234CONFIG_BLK_DEV_SR_VENDOR=y 366CONFIG_BLK_DEV_SR_VENDOR=y
235CONFIG_CHR_DEV_SG=y 367CONFIG_CHR_DEV_SG=y
368# CONFIG_CHR_DEV_SCH is not set
236 369
237# 370#
238# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 371# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -244,9 +377,10 @@ CONFIG_SCSI_LOGGING=y
244# 377#
245# SCSI Transport Attributes 378# SCSI Transport Attributes
246# 379#
247# CONFIG_SCSI_SPI_ATTRS is not set 380CONFIG_SCSI_SPI_ATTRS=y
248# CONFIG_SCSI_FC_ATTRS is not set 381# CONFIG_SCSI_FC_ATTRS is not set
249# CONFIG_SCSI_ISCSI_ATTRS is not set 382# CONFIG_SCSI_ISCSI_ATTRS is not set
383CONFIG_SCSI_SAS_ATTRS=y
250 384
251# 385#
252# SCSI low-level drivers 386# SCSI low-level drivers
@@ -266,18 +400,13 @@ CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
266# CONFIG_MEGARAID_NEWGEN is not set 400# CONFIG_MEGARAID_NEWGEN is not set
267# CONFIG_MEGARAID_LEGACY is not set 401# CONFIG_MEGARAID_LEGACY is not set
268# CONFIG_SCSI_SATA is not set 402# CONFIG_SCSI_SATA is not set
269# CONFIG_SCSI_BUSLOGIC is not set
270# CONFIG_SCSI_DMX3191D is not set 403# CONFIG_SCSI_DMX3191D is not set
271# CONFIG_SCSI_EATA is not set
272# CONFIG_SCSI_EATA_PIO is not set
273# CONFIG_SCSI_FUTURE_DOMAIN is not set 404# CONFIG_SCSI_FUTURE_DOMAIN is not set
274# CONFIG_SCSI_GDTH is not set
275# CONFIG_SCSI_IPS is not set 405# CONFIG_SCSI_IPS is not set
276# CONFIG_SCSI_INITIO is not set 406# CONFIG_SCSI_INITIO is not set
277# CONFIG_SCSI_INIA100 is not set 407# CONFIG_SCSI_INIA100 is not set
278# CONFIG_SCSI_SYM53C8XX_2 is not set 408# CONFIG_SCSI_SYM53C8XX_2 is not set
279# CONFIG_SCSI_IPR is not set 409# CONFIG_SCSI_IPR is not set
280# CONFIG_SCSI_QLOGIC_ISP is not set
281# CONFIG_SCSI_QLOGIC_FC is not set 410# CONFIG_SCSI_QLOGIC_FC is not set
282# CONFIG_SCSI_QLOGIC_1280 is not set 411# CONFIG_SCSI_QLOGIC_1280 is not set
283CONFIG_SCSI_QLA2XXX=y 412CONFIG_SCSI_QLA2XXX=y
@@ -286,6 +415,8 @@ CONFIG_SCSI_QLA2XXX=y
286# CONFIG_SCSI_QLA2300 is not set 415# CONFIG_SCSI_QLA2300 is not set
287# CONFIG_SCSI_QLA2322 is not set 416# CONFIG_SCSI_QLA2322 is not set
288# CONFIG_SCSI_QLA6312 is not set 417# CONFIG_SCSI_QLA6312 is not set
418# CONFIG_SCSI_QLA24XX is not set
419# CONFIG_SCSI_LPFC is not set
289# CONFIG_SCSI_DC395x is not set 420# CONFIG_SCSI_DC395x is not set
290# CONFIG_SCSI_DC390T is not set 421# CONFIG_SCSI_DC390T is not set
291# CONFIG_SCSI_DEBUG is not set 422# CONFIG_SCSI_DEBUG is not set
@@ -299,6 +430,8 @@ CONFIG_SCSI_QLA2XXX=y
299# Fusion MPT device support 430# Fusion MPT device support
300# 431#
301# CONFIG_FUSION is not set 432# CONFIG_FUSION is not set
433# CONFIG_FUSION_SPI is not set
434# CONFIG_FUSION_FC is not set
302 435
303# 436#
304# IEEE 1394 (FireWire) support 437# IEEE 1394 (FireWire) support
@@ -311,78 +444,13 @@ CONFIG_SCSI_QLA2XXX=y
311# CONFIG_I2O is not set 444# CONFIG_I2O is not set
312 445
313# 446#
314# Networking support 447# Network device support
315#
316CONFIG_NET=y
317
318#
319# Networking options
320#
321CONFIG_PACKET=y
322CONFIG_PACKET_MMAP=y
323CONFIG_NETLINK_DEV=y
324CONFIG_UNIX=y
325CONFIG_NET_KEY=y
326CONFIG_INET=y
327# CONFIG_IP_MULTICAST is not set
328# CONFIG_IP_ADVANCED_ROUTER is not set
329CONFIG_IP_PNP=y
330# CONFIG_IP_PNP_DHCP is not set
331CONFIG_IP_PNP_BOOTP=y
332# CONFIG_IP_PNP_RARP is not set
333# CONFIG_NET_IPIP is not set
334# CONFIG_NET_IPGRE is not set
335# CONFIG_ARPD is not set
336# CONFIG_SYN_COOKIES is not set
337# CONFIG_INET_AH is not set
338# CONFIG_INET_ESP is not set
339# CONFIG_INET_IPCOMP is not set
340CONFIG_INET_TUNNEL=y
341CONFIG_IP_TCPDIAG=y
342# CONFIG_IP_TCPDIAG_IPV6 is not set
343# CONFIG_IPV6 is not set
344# CONFIG_NETFILTER is not set
345CONFIG_XFRM=y
346CONFIG_XFRM_USER=y
347
348#
349# SCTP Configuration (EXPERIMENTAL)
350# 448#
351# CONFIG_IP_SCTP is not set
352# CONFIG_ATM is not set
353# CONFIG_BRIDGE is not set
354# CONFIG_VLAN_8021Q is not set
355# CONFIG_DECNET is not set
356# CONFIG_LLC2 is not set
357# CONFIG_IPX is not set
358# CONFIG_ATALK is not set
359# CONFIG_X25 is not set
360# CONFIG_LAPB is not set
361# CONFIG_NET_DIVERT is not set
362# CONFIG_ECONET is not set
363# CONFIG_WAN_ROUTER is not set
364
365#
366# QoS and/or fair queueing
367#
368# CONFIG_NET_SCHED is not set
369# CONFIG_NET_CLS_ROUTE is not set
370
371#
372# Network testing
373#
374# CONFIG_NET_PKTGEN is not set
375# CONFIG_NETPOLL is not set
376# CONFIG_NET_POLL_CONTROLLER is not set
377# CONFIG_HAMRADIO is not set
378# CONFIG_IRDA is not set
379# CONFIG_BT is not set
380CONFIG_NETDEVICES=y 449CONFIG_NETDEVICES=y
381# CONFIG_DUMMY is not set 450# CONFIG_DUMMY is not set
382# CONFIG_BONDING is not set 451# CONFIG_BONDING is not set
383# CONFIG_EQUALIZER is not set 452# CONFIG_EQUALIZER is not set
384# CONFIG_TUN is not set 453# CONFIG_TUN is not set
385# CONFIG_ETHERTAP is not set
386 454
387# 455#
388# ARCnet devices 456# ARCnet devices
@@ -390,6 +458,21 @@ CONFIG_NETDEVICES=y
390# CONFIG_ARCNET is not set 458# CONFIG_ARCNET is not set
391 459
392# 460#
461# PHY device support
462#
463CONFIG_PHYLIB=y
464CONFIG_PHYCONTROL=y
465
466#
467# MII PHY device drivers
468#
469CONFIG_MARVELL_PHY=y
470CONFIG_DAVICOM_PHY=y
471CONFIG_QSEMI_PHY=y
472CONFIG_LXT_PHY=y
473CONFIG_CICADA_PHY=y
474
475#
393# Ethernet (10 or 100Mbit) 476# Ethernet (10 or 100Mbit)
394# 477#
395CONFIG_NET_ETHERNET=y 478CONFIG_NET_ETHERNET=y
@@ -416,12 +499,16 @@ CONFIG_SGI_O2MACE_ETH=y
416# CONFIG_HAMACHI is not set 499# CONFIG_HAMACHI is not set
417# CONFIG_YELLOWFIN is not set 500# CONFIG_YELLOWFIN is not set
418# CONFIG_R8169 is not set 501# CONFIG_R8169 is not set
502# CONFIG_SIS190 is not set
503# CONFIG_SKGE is not set
419# CONFIG_SK98LIN is not set 504# CONFIG_SK98LIN is not set
420# CONFIG_TIGON3 is not set 505# CONFIG_TIGON3 is not set
506# CONFIG_BNX2 is not set
421 507
422# 508#
423# Ethernet (10000 Mbit) 509# Ethernet (10000 Mbit)
424# 510#
511# CONFIG_CHELSIO_T1 is not set
425# CONFIG_IXGB is not set 512# CONFIG_IXGB is not set
426# CONFIG_S2IO is not set 513# CONFIG_S2IO is not set
427 514
@@ -434,6 +521,8 @@ CONFIG_SGI_O2MACE_ETH=y
434# Wireless LAN (non-hamradio) 521# Wireless LAN (non-hamradio)
435# 522#
436# CONFIG_NET_RADIO is not set 523# CONFIG_NET_RADIO is not set
524# CONFIG_IPW_DEBUG is not set
525CONFIG_IPW2200=y
437 526
438# 527#
439# Wan interfaces 528# Wan interfaces
@@ -446,6 +535,8 @@ CONFIG_SGI_O2MACE_ETH=y
446# CONFIG_NET_FC is not set 535# CONFIG_NET_FC is not set
447# CONFIG_SHAPER is not set 536# CONFIG_SHAPER is not set
448# CONFIG_NETCONSOLE is not set 537# CONFIG_NETCONSOLE is not set
538# CONFIG_NETPOLL is not set
539# CONFIG_NET_POLL_CONTROLLER is not set
449 540
450# 541#
451# ISDN subsystem 542# ISDN subsystem
@@ -475,27 +566,25 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
475# CONFIG_INPUT_EVBUG is not set 566# CONFIG_INPUT_EVBUG is not set
476 567
477# 568#
478# Input I/O drivers 569# Input Device Drivers
570#
571# CONFIG_INPUT_KEYBOARD is not set
572# CONFIG_INPUT_MOUSE is not set
573# CONFIG_INPUT_JOYSTICK is not set
574# CONFIG_INPUT_TOUCHSCREEN is not set
575# CONFIG_INPUT_MISC is not set
576
577#
578# Hardware I/O ports
479# 579#
480# CONFIG_GAMEPORT is not set
481CONFIG_SOUND_GAMEPORT=y
482CONFIG_SERIO=y 580CONFIG_SERIO=y
483# CONFIG_SERIO_I8042 is not set 581# CONFIG_SERIO_I8042 is not set
484CONFIG_SERIO_SERPORT=y 582CONFIG_SERIO_SERPORT=y
485# CONFIG_SERIO_CT82C710 is not set
486# CONFIG_SERIO_PCIPS2 is not set 583# CONFIG_SERIO_PCIPS2 is not set
487# CONFIG_SERIO_MACEPS2 is not set 584# CONFIG_SERIO_MACEPS2 is not set
488# CONFIG_SERIO_LIBPS2 is not set 585# CONFIG_SERIO_LIBPS2 is not set
489CONFIG_SERIO_RAW=y 586CONFIG_SERIO_RAW=y
490 587# CONFIG_GAMEPORT is not set
491#
492# Input Device Drivers
493#
494# CONFIG_INPUT_KEYBOARD is not set
495# CONFIG_INPUT_MOUSE is not set
496# CONFIG_INPUT_JOYSTICK is not set
497# CONFIG_INPUT_TOUCHSCREEN is not set
498# CONFIG_INPUT_MISC is not set
499 588
500# 589#
501# Character devices 590# Character devices
@@ -518,6 +607,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
518# 607#
519CONFIG_SERIAL_CORE=y 608CONFIG_SERIAL_CORE=y
520CONFIG_SERIAL_CORE_CONSOLE=y 609CONFIG_SERIAL_CORE_CONSOLE=y
610# CONFIG_SERIAL_JSM is not set
521CONFIG_UNIX98_PTYS=y 611CONFIG_UNIX98_PTYS=y
522CONFIG_LEGACY_PTYS=y 612CONFIG_LEGACY_PTYS=y
523CONFIG_LEGACY_PTY_COUNT=256 613CONFIG_LEGACY_PTY_COUNT=256
@@ -544,6 +634,11 @@ CONFIG_LEGACY_PTY_COUNT=256
544# CONFIG_RAW_DRIVER is not set 634# CONFIG_RAW_DRIVER is not set
545 635
546# 636#
637# TPM devices
638#
639# CONFIG_TCG_TPM is not set
640
641#
547# I2C support 642# I2C support
548# 643#
549# CONFIG_I2C is not set 644# CONFIG_I2C is not set
@@ -554,10 +649,20 @@ CONFIG_LEGACY_PTY_COUNT=256
554# CONFIG_W1 is not set 649# CONFIG_W1 is not set
555 650
556# 651#
652# Hardware Monitoring support
653#
654# CONFIG_HWMON is not set
655# CONFIG_HWMON_VID is not set
656
657#
557# Misc devices 658# Misc devices
558# 659#
559 660
560# 661#
662# Multimedia Capabilities Port drivers
663#
664
665#
561# Multimedia devices 666# Multimedia devices
562# 667#
563# CONFIG_VIDEO_DEV is not set 668# CONFIG_VIDEO_DEV is not set
@@ -577,7 +682,6 @@ CONFIG_LEGACY_PTY_COUNT=256
577# 682#
578# CONFIG_VGA_CONSOLE is not set 683# CONFIG_VGA_CONSOLE is not set
579CONFIG_DUMMY_CONSOLE=y 684CONFIG_DUMMY_CONSOLE=y
580# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
581 685
582# 686#
583# Sound 687# Sound
@@ -587,13 +691,9 @@ CONFIG_DUMMY_CONSOLE=y
587# 691#
588# USB support 692# USB support
589# 693#
590# CONFIG_USB is not set
591CONFIG_USB_ARCH_HAS_HCD=y 694CONFIG_USB_ARCH_HAS_HCD=y
592CONFIG_USB_ARCH_HAS_OHCI=y 695CONFIG_USB_ARCH_HAS_OHCI=y
593 696# CONFIG_USB is not set
594#
595# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
596#
597 697
598# 698#
599# USB Gadget Support 699# USB Gadget Support
@@ -611,21 +711,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y
611# CONFIG_INFINIBAND is not set 711# CONFIG_INFINIBAND is not set
612 712
613# 713#
714# SN Devices
715#
716
717#
614# File systems 718# File systems
615# 719#
616CONFIG_EXT2_FS=y 720CONFIG_EXT2_FS=y
617# CONFIG_EXT2_FS_XATTR is not set 721# CONFIG_EXT2_FS_XATTR is not set
722# CONFIG_EXT2_FS_XIP is not set
618# CONFIG_EXT3_FS is not set 723# CONFIG_EXT3_FS is not set
619# CONFIG_JBD is not set 724# CONFIG_JBD is not set
620# CONFIG_REISERFS_FS is not set 725# CONFIG_REISERFS_FS is not set
621# CONFIG_JFS_FS is not set 726# CONFIG_JFS_FS is not set
727# CONFIG_FS_POSIX_ACL is not set
622# CONFIG_XFS_FS is not set 728# CONFIG_XFS_FS is not set
623# CONFIG_MINIX_FS is not set 729# CONFIG_MINIX_FS is not set
624# CONFIG_ROMFS_FS is not set 730# CONFIG_ROMFS_FS is not set
731CONFIG_INOTIFY=y
625# CONFIG_QUOTA is not set 732# CONFIG_QUOTA is not set
626CONFIG_DNOTIFY=y 733CONFIG_DNOTIFY=y
627# CONFIG_AUTOFS_FS is not set 734# CONFIG_AUTOFS_FS is not set
628# CONFIG_AUTOFS4_FS is not set 735# CONFIG_AUTOFS4_FS is not set
736CONFIG_FUSE_FS=y
629 737
630# 738#
631# CD-ROM/DVD Filesystems 739# CD-ROM/DVD Filesystems
@@ -646,13 +754,10 @@ CONFIG_DNOTIFY=y
646CONFIG_PROC_FS=y 754CONFIG_PROC_FS=y
647CONFIG_PROC_KCORE=y 755CONFIG_PROC_KCORE=y
648CONFIG_SYSFS=y 756CONFIG_SYSFS=y
649# CONFIG_DEVFS_FS is not set
650CONFIG_DEVPTS_FS_XATTR=y
651CONFIG_DEVPTS_FS_SECURITY=y
652CONFIG_TMPFS=y 757CONFIG_TMPFS=y
653# CONFIG_TMPFS_XATTR is not set
654# CONFIG_HUGETLB_PAGE is not set 758# CONFIG_HUGETLB_PAGE is not set
655CONFIG_RAMFS=y 759CONFIG_RAMFS=y
760CONFIG_RELAYFS_FS=y
656 761
657# 762#
658# Miscellaneous filesystems 763# Miscellaneous filesystems
@@ -676,13 +781,14 @@ CONFIG_RAMFS=y
676# 781#
677CONFIG_NFS_FS=y 782CONFIG_NFS_FS=y
678CONFIG_NFS_V3=y 783CONFIG_NFS_V3=y
784# CONFIG_NFS_V3_ACL is not set
679# CONFIG_NFS_V4 is not set 785# CONFIG_NFS_V4 is not set
680# CONFIG_NFS_DIRECTIO is not set 786# CONFIG_NFS_DIRECTIO is not set
681# CONFIG_NFSD is not set 787# CONFIG_NFSD is not set
682CONFIG_ROOT_NFS=y 788CONFIG_ROOT_NFS=y
683CONFIG_LOCKD=y 789CONFIG_LOCKD=y
684CONFIG_LOCKD_V4=y 790CONFIG_LOCKD_V4=y
685# CONFIG_EXPORTFS is not set 791CONFIG_NFS_COMMON=y
686CONFIG_SUNRPC=y 792CONFIG_SUNRPC=y
687# CONFIG_RPCSEC_GSS_KRB5 is not set 793# CONFIG_RPCSEC_GSS_KRB5 is not set
688# CONFIG_RPCSEC_GSS_SPKM3 is not set 794# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -691,6 +797,7 @@ CONFIG_SUNRPC=y
691# CONFIG_NCP_FS is not set 797# CONFIG_NCP_FS is not set
692# CONFIG_CODA_FS is not set 798# CONFIG_CODA_FS is not set
693# CONFIG_AFS_FS is not set 799# CONFIG_AFS_FS is not set
800# CONFIG_9P_FS is not set
694 801
695# 802#
696# Partition Types 803# Partition Types
@@ -721,7 +828,9 @@ CONFIG_SGI_PARTITION=y
721# 828#
722# Kernel hacking 829# Kernel hacking
723# 830#
831# CONFIG_PRINTK_TIME is not set
724# CONFIG_DEBUG_KERNEL is not set 832# CONFIG_DEBUG_KERNEL is not set
833CONFIG_LOG_BUF_SHIFT=14
725CONFIG_CROSSCOMPILE=y 834CONFIG_CROSSCOMPILE=y
726CONFIG_CMDLINE="" 835CONFIG_CMDLINE=""
727 836
@@ -735,7 +844,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
735# 844#
736# Cryptographic options 845# Cryptographic options
737# 846#
738# CONFIG_CRYPTO is not set 847CONFIG_CRYPTO=y
848CONFIG_CRYPTO_HMAC=y
849CONFIG_CRYPTO_NULL=y
850CONFIG_CRYPTO_MD4=y
851CONFIG_CRYPTO_MD5=y
852CONFIG_CRYPTO_SHA1=y
853CONFIG_CRYPTO_SHA256=y
854CONFIG_CRYPTO_SHA512=y
855CONFIG_CRYPTO_WP512=y
856CONFIG_CRYPTO_TGR192=y
857CONFIG_CRYPTO_DES=y
858CONFIG_CRYPTO_BLOWFISH=y
859CONFIG_CRYPTO_TWOFISH=y
860CONFIG_CRYPTO_SERPENT=y
861CONFIG_CRYPTO_AES=y
862CONFIG_CRYPTO_CAST5=y
863CONFIG_CRYPTO_CAST6=y
864CONFIG_CRYPTO_TEA=y
865CONFIG_CRYPTO_ARC4=y
866CONFIG_CRYPTO_KHAZAD=y
867CONFIG_CRYPTO_ANUBIS=y
868CONFIG_CRYPTO_DEFLATE=y
869CONFIG_CRYPTO_MICHAEL_MIC=y
870CONFIG_CRYPTO_CRC32C=y
871# CONFIG_CRYPTO_TEST is not set
739 872
740# 873#
741# Hardware crypto devices 874# Hardware crypto devices
@@ -745,7 +878,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
745# Library routines 878# Library routines
746# 879#
747# CONFIG_CRC_CCITT is not set 880# CONFIG_CRC_CCITT is not set
748# CONFIG_CRC32 is not set 881CONFIG_CRC16=y
749# CONFIG_LIBCRC32C is not set 882CONFIG_CRC32=y
750CONFIG_GENERIC_HARDIRQS=y 883CONFIG_LIBCRC32C=y
751CONFIG_GENERIC_IRQ_PROBE=y 884CONFIG_ZLIB_INFLATE=y
885CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig
index 08bd3ad64761..0940771bafb1 100644
--- a/arch/mips/configs/it8172_defconfig
+++ b/arch/mips/configs/it8172_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:05 2005 4# Thu Oct 20 22:26:09 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,11 +11,13 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
@@ -26,13 +25,16 @@ CONFIG_BSD_PROCESS_ACCT=y
26# CONFIG_BSD_PROCESS_ACCT_V3 is not set 25# CONFIG_BSD_PROCESS_ACCT_V3 is not set
27CONFIG_SYSCTL=y 26CONFIG_SYSCTL=y
28# CONFIG_AUDIT is not set 27# CONFIG_AUDIT is not set
29CONFIG_LOG_BUF_SHIFT=14
30# CONFIG_HOTPLUG is not set 28# CONFIG_HOTPLUG is not set
31CONFIG_KOBJECT_UEVENT=y 29CONFIG_KOBJECT_UEVENT=y
32# CONFIG_IKCONFIG is not set 30# CONFIG_IKCONFIG is not set
31CONFIG_INITRAMFS_SOURCE=""
33CONFIG_EMBEDDED=y 32CONFIG_EMBEDDED=y
34CONFIG_KALLSYMS=y 33CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_EXTRA_PASS is not set 34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
36CONFIG_FUTEX=y 38CONFIG_FUTEX=y
37CONFIG_EPOLL=y 39CONFIG_EPOLL=y
38# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -42,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0
42CONFIG_CC_ALIGN_LOOPS=0 44CONFIG_CC_ALIGN_LOOPS=0
43CONFIG_CC_ALIGN_JUMPS=0 45CONFIG_CC_ALIGN_JUMPS=0
44# CONFIG_TINY_SHMEM is not set 46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
45 48
46# 49#
47# Loadable module support 50# Loadable module support
@@ -57,41 +60,69 @@ CONFIG_KMOD=y
57# 60#
58# Machine selection 61# Machine selection
59# 62#
60# CONFIG_MACH_JAZZ is not set 63# CONFIG_MIPS_MTX1 is not set
61# CONFIG_MACH_VR41XX is not set 64# CONFIG_MIPS_BOSPORUS is not set
62# CONFIG_TOSHIBA_JMR3927 is not set 65# CONFIG_MIPS_PB1000 is not set
66# CONFIG_MIPS_PB1100 is not set
67# CONFIG_MIPS_PB1500 is not set
68# CONFIG_MIPS_PB1550 is not set
69# CONFIG_MIPS_PB1200 is not set
70# CONFIG_MIPS_DB1000 is not set
71# CONFIG_MIPS_DB1100 is not set
72# CONFIG_MIPS_DB1500 is not set
73# CONFIG_MIPS_DB1550 is not set
74# CONFIG_MIPS_DB1200 is not set
75# CONFIG_MIPS_MIRAGE is not set
63# CONFIG_MIPS_COBALT is not set 76# CONFIG_MIPS_COBALT is not set
64# CONFIG_MACH_DECSTATION is not set 77# CONFIG_MACH_DECSTATION is not set
65# CONFIG_MIPS_EV64120 is not set 78# CONFIG_MIPS_EV64120 is not set
66# CONFIG_MIPS_EV96100 is not set 79# CONFIG_MIPS_EV96100 is not set
67# CONFIG_MIPS_IVR is not set 80# CONFIG_MIPS_IVR is not set
68# CONFIG_LASAT is not set
69CONFIG_MIPS_ITE8172=y 81CONFIG_MIPS_ITE8172=y
70# CONFIG_IT8172_REVC is not set 82# CONFIG_MACH_JAZZ is not set
83# CONFIG_LASAT is not set
71# CONFIG_MIPS_ATLAS is not set 84# CONFIG_MIPS_ATLAS is not set
72# CONFIG_MIPS_MALTA is not set 85# CONFIG_MIPS_MALTA is not set
73# CONFIG_MIPS_SEAD is not set 86# CONFIG_MIPS_SEAD is not set
87# CONFIG_MIPS_SIM is not set
88# CONFIG_MOMENCO_JAGUAR_ATX is not set
74# CONFIG_MOMENCO_OCELOT is not set 89# CONFIG_MOMENCO_OCELOT is not set
75# CONFIG_MOMENCO_OCELOT_G is not set
76# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_MOMENCO_OCELOT_3 is not set 90# CONFIG_MOMENCO_OCELOT_3 is not set
78# CONFIG_MOMENCO_JAGUAR_ATX is not set 91# CONFIG_MOMENCO_OCELOT_C is not set
79# CONFIG_PMC_YOSEMITE is not set 92# CONFIG_MOMENCO_OCELOT_G is not set
93# CONFIG_MIPS_XXS1500 is not set
94# CONFIG_PNX8550_V2PCI is not set
95# CONFIG_PNX8550_JBS is not set
80# CONFIG_DDB5074 is not set 96# CONFIG_DDB5074 is not set
81# CONFIG_DDB5476 is not set 97# CONFIG_DDB5476 is not set
82# CONFIG_DDB5477 is not set 98# CONFIG_DDB5477 is not set
83# CONFIG_NEC_OSPREY is not set 99# CONFIG_MACH_VR41XX is not set
100# CONFIG_PMC_YOSEMITE is not set
101# CONFIG_QEMU is not set
84# CONFIG_SGI_IP22 is not set 102# CONFIG_SGI_IP22 is not set
85# CONFIG_SOC_AU1X00 is not set 103# CONFIG_SGI_IP27 is not set
86# CONFIG_SIBYTE_SB1xxx_SOC is not set 104# CONFIG_SGI_IP32 is not set
105# CONFIG_SIBYTE_BIGSUR is not set
106# CONFIG_SIBYTE_SWARM is not set
107# CONFIG_SIBYTE_SENTOSA is not set
108# CONFIG_SIBYTE_RHONE is not set
109# CONFIG_SIBYTE_CARMEL is not set
110# CONFIG_SIBYTE_PTSWARM is not set
111# CONFIG_SIBYTE_LITTLESUR is not set
112# CONFIG_SIBYTE_CRHINE is not set
113# CONFIG_SIBYTE_CRHONE is not set
87# CONFIG_SNI_RM200_PCI is not set 114# CONFIG_SNI_RM200_PCI is not set
115# CONFIG_TOSHIBA_JMR3927 is not set
88# CONFIG_TOSHIBA_RBTX4927 is not set 116# CONFIG_TOSHIBA_RBTX4927 is not set
117# CONFIG_TOSHIBA_RBTX4938 is not set
118# CONFIG_IT8172_REVC is not set
89CONFIG_RWSEM_GENERIC_SPINLOCK=y 119CONFIG_RWSEM_GENERIC_SPINLOCK=y
90CONFIG_GENERIC_CALIBRATE_DELAY=y 120CONFIG_GENERIC_CALIBRATE_DELAY=y
91CONFIG_HAVE_DEC_LOCK=y
92CONFIG_DMA_NONCOHERENT=y 121CONFIG_DMA_NONCOHERENT=y
93CONFIG_DMA_NEED_PCI_MAP_STATE=y 122CONFIG_DMA_NEED_PCI_MAP_STATE=y
123# CONFIG_CPU_BIG_ENDIAN is not set
94CONFIG_CPU_LITTLE_ENDIAN=y 124CONFIG_CPU_LITTLE_ENDIAN=y
125CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
95CONFIG_ITE_BOARD_GEN=y 126CONFIG_ITE_BOARD_GEN=y
96CONFIG_IT8172_CIR=y 127CONFIG_IT8172_CIR=y
97CONFIG_IT8712=y 128CONFIG_IT8712=y
@@ -100,8 +131,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
100# 131#
101# CPU selection 132# CPU selection
102# 133#
103# CONFIG_CPU_MIPS32 is not set 134# CONFIG_CPU_MIPS32_R1 is not set
104# CONFIG_CPU_MIPS64 is not set 135# CONFIG_CPU_MIPS32_R2 is not set
136# CONFIG_CPU_MIPS64_R1 is not set
137# CONFIG_CPU_MIPS64_R2 is not set
105# CONFIG_CPU_R3000 is not set 138# CONFIG_CPU_R3000 is not set
106# CONFIG_CPU_TX39XX is not set 139# CONFIG_CPU_TX39XX is not set
107# CONFIG_CPU_VR41XX is not set 140# CONFIG_CPU_VR41XX is not set
@@ -117,14 +150,39 @@ CONFIG_CPU_NEVADA=y
117# CONFIG_CPU_RM7000 is not set 150# CONFIG_CPU_RM7000 is not set
118# CONFIG_CPU_RM9000 is not set 151# CONFIG_CPU_RM9000 is not set
119# CONFIG_CPU_SB1 is not set 152# CONFIG_CPU_SB1 is not set
153CONFIG_SYS_HAS_CPU_R5432=y
154CONFIG_SYS_HAS_CPU_NEVADA=y
155CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
156CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
157CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
158CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
159
160#
161# Kernel type
162#
163CONFIG_32BIT=y
164# CONFIG_64BIT is not set
120CONFIG_PAGE_SIZE_4KB=y 165CONFIG_PAGE_SIZE_4KB=y
121# CONFIG_PAGE_SIZE_8KB is not set 166# CONFIG_PAGE_SIZE_8KB is not set
122# CONFIG_PAGE_SIZE_16KB is not set 167# CONFIG_PAGE_SIZE_16KB is not set
123# CONFIG_PAGE_SIZE_64KB is not set 168# CONFIG_PAGE_SIZE_64KB is not set
169# CONFIG_MIPS_MT is not set
124# CONFIG_CPU_ADVANCED is not set 170# CONFIG_CPU_ADVANCED is not set
125CONFIG_CPU_HAS_LLSC=y 171CONFIG_CPU_HAS_LLSC=y
126CONFIG_CPU_HAS_LLDSCD=y 172CONFIG_CPU_HAS_LLDSCD=y
127CONFIG_CPU_HAS_SYNC=y 173CONFIG_CPU_HAS_SYNC=y
174CONFIG_GENERIC_HARDIRQS=y
175CONFIG_GENERIC_IRQ_PROBE=y
176CONFIG_ARCH_FLATMEM_ENABLE=y
177CONFIG_SELECT_MEMORY_MODEL=y
178CONFIG_FLATMEM_MANUAL=y
179# CONFIG_DISCONTIGMEM_MANUAL is not set
180# CONFIG_SPARSEMEM_MANUAL is not set
181CONFIG_FLATMEM=y
182CONFIG_FLAT_NODE_MEM_MAP=y
183# CONFIG_SPARSEMEM_STATIC is not set
184CONFIG_PREEMPT_NONE=y
185# CONFIG_PREEMPT_VOLUNTARY is not set
128# CONFIG_PREEMPT is not set 186# CONFIG_PREEMPT is not set
129 187
130# 188#
@@ -140,10 +198,6 @@ CONFIG_MMU=y
140# CONFIG_PCCARD is not set 198# CONFIG_PCCARD is not set
141 199
142# 200#
143# PC-card bridges
144#
145
146#
147# PCI Hotplug Support 201# PCI Hotplug Support
148# 202#
149 203
@@ -155,6 +209,80 @@ CONFIG_BINFMT_ELF=y
155CONFIG_TRAD_SIGNALS=y 209CONFIG_TRAD_SIGNALS=y
156 210
157# 211#
212# Networking
213#
214CONFIG_NET=y
215
216#
217# Networking options
218#
219CONFIG_PACKET=y
220CONFIG_PACKET_MMAP=y
221CONFIG_UNIX=y
222CONFIG_XFRM=y
223CONFIG_XFRM_USER=m
224CONFIG_NET_KEY=y
225CONFIG_INET=y
226# CONFIG_IP_MULTICAST is not set
227# CONFIG_IP_ADVANCED_ROUTER is not set
228CONFIG_IP_FIB_HASH=y
229CONFIG_IP_PNP=y
230# CONFIG_IP_PNP_DHCP is not set
231CONFIG_IP_PNP_BOOTP=y
232# CONFIG_IP_PNP_RARP is not set
233# CONFIG_NET_IPIP is not set
234# CONFIG_NET_IPGRE is not set
235# CONFIG_ARPD is not set
236# CONFIG_SYN_COOKIES is not set
237# CONFIG_INET_AH is not set
238# CONFIG_INET_ESP is not set
239# CONFIG_INET_IPCOMP is not set
240CONFIG_INET_TUNNEL=m
241CONFIG_INET_DIAG=y
242CONFIG_INET_TCP_DIAG=y
243# CONFIG_TCP_CONG_ADVANCED is not set
244CONFIG_TCP_CONG_BIC=y
245# CONFIG_IPV6 is not set
246# CONFIG_NETFILTER is not set
247
248#
249# DCCP Configuration (EXPERIMENTAL)
250#
251# CONFIG_IP_DCCP is not set
252
253#
254# SCTP Configuration (EXPERIMENTAL)
255#
256# CONFIG_IP_SCTP is not set
257# CONFIG_ATM is not set
258# CONFIG_BRIDGE is not set
259# CONFIG_VLAN_8021Q is not set
260# CONFIG_DECNET is not set
261# CONFIG_LLC2 is not set
262# CONFIG_IPX is not set
263# CONFIG_ATALK is not set
264# CONFIG_X25 is not set
265# CONFIG_LAPB is not set
266# CONFIG_NET_DIVERT is not set
267# CONFIG_ECONET is not set
268# CONFIG_WAN_ROUTER is not set
269# CONFIG_NET_SCHED is not set
270# CONFIG_NET_CLS_ROUTE is not set
271
272#
273# Network testing
274#
275# CONFIG_NET_PKTGEN is not set
276# CONFIG_HAMRADIO is not set
277# CONFIG_IRDA is not set
278# CONFIG_BT is not set
279CONFIG_IEEE80211=m
280# CONFIG_IEEE80211_DEBUG is not set
281CONFIG_IEEE80211_CRYPT_WEP=m
282CONFIG_IEEE80211_CRYPT_CCMP=m
283CONFIG_IEEE80211_CRYPT_TKIP=m
284
285#
158# Device Drivers 286# Device Drivers
159# 287#
160 288
@@ -166,12 +294,17 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
166# CONFIG_FW_LOADER is not set 294# CONFIG_FW_LOADER is not set
167 295
168# 296#
297# Connector - unified userspace <-> kernelspace linker
298#
299CONFIG_CONNECTOR=m
300
301#
169# Memory Technology Devices (MTD) 302# Memory Technology Devices (MTD)
170# 303#
171CONFIG_MTD=y 304CONFIG_MTD=y
172# CONFIG_MTD_DEBUG is not set 305# CONFIG_MTD_DEBUG is not set
173# CONFIG_MTD_PARTITIONS is not set
174# CONFIG_MTD_CONCAT is not set 306# CONFIG_MTD_CONCAT is not set
307# CONFIG_MTD_PARTITIONS is not set
175 308
176# 309#
177# User Modules And Translation Layers 310# User Modules And Translation Layers
@@ -207,7 +340,6 @@ CONFIG_MTD_CFI_UTIL=y
207# CONFIG_MTD_RAM is not set 340# CONFIG_MTD_RAM is not set
208# CONFIG_MTD_ROM is not set 341# CONFIG_MTD_ROM is not set
209# CONFIG_MTD_ABSENT is not set 342# CONFIG_MTD_ABSENT is not set
210# CONFIG_MTD_XIP is not set
211 343
212# 344#
213# Mapping drivers for chip access 345# Mapping drivers for chip access
@@ -217,6 +349,7 @@ CONFIG_MTD_PHYSMAP=y
217CONFIG_MTD_PHYSMAP_START=0x8000000 349CONFIG_MTD_PHYSMAP_START=0x8000000
218CONFIG_MTD_PHYSMAP_LEN=0x2000000 350CONFIG_MTD_PHYSMAP_LEN=0x2000000
219CONFIG_MTD_PHYSMAP_BANKWIDTH=2 351CONFIG_MTD_PHYSMAP_BANKWIDTH=2
352# CONFIG_MTD_PLATRAM is not set
220 353
221# 354#
222# Self-contained MTD device drivers 355# Self-contained MTD device drivers
@@ -251,14 +384,12 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
251# 384#
252# Block devices 385# Block devices
253# 386#
254# CONFIG_BLK_DEV_FD is not set
255# CONFIG_BLK_DEV_COW_COMMON is not set 387# CONFIG_BLK_DEV_COW_COMMON is not set
256CONFIG_BLK_DEV_LOOP=y 388CONFIG_BLK_DEV_LOOP=y
257# CONFIG_BLK_DEV_CRYPTOLOOP is not set 389# CONFIG_BLK_DEV_CRYPTOLOOP is not set
258# CONFIG_BLK_DEV_NBD is not set 390# CONFIG_BLK_DEV_NBD is not set
259# CONFIG_BLK_DEV_RAM is not set 391# CONFIG_BLK_DEV_RAM is not set
260CONFIG_BLK_DEV_RAM_COUNT=16 392CONFIG_BLK_DEV_RAM_COUNT=16
261CONFIG_INITRAMFS_SOURCE=""
262# CONFIG_LBD is not set 393# CONFIG_LBD is not set
263CONFIG_CDROM_PKTCDVD=m 394CONFIG_CDROM_PKTCDVD=m
264CONFIG_CDROM_PKTCDVD_BUFFERS=8 395CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -302,6 +433,7 @@ CONFIG_IDE_GENERIC=y
302# 433#
303# SCSI device support 434# SCSI device support
304# 435#
436CONFIG_RAID_ATTRS=m
305# CONFIG_SCSI is not set 437# CONFIG_SCSI is not set
306 438
307# 439#
@@ -312,6 +444,7 @@ CONFIG_IDE_GENERIC=y
312# 444#
313# Fusion MPT device support 445# Fusion MPT device support
314# 446#
447# CONFIG_FUSION is not set
315 448
316# 449#
317# IEEE 1394 (FireWire) support 450# IEEE 1394 (FireWire) support
@@ -322,78 +455,28 @@ CONFIG_IDE_GENERIC=y
322# 455#
323 456
324# 457#
325# Networking support 458# Network device support
326#
327CONFIG_NET=y
328
329#
330# Networking options
331# 459#
332CONFIG_PACKET=y 460CONFIG_NETDEVICES=y
333CONFIG_PACKET_MMAP=y 461# CONFIG_DUMMY is not set
334CONFIG_NETLINK_DEV=y 462# CONFIG_BONDING is not set
335CONFIG_UNIX=y 463# CONFIG_EQUALIZER is not set
336CONFIG_NET_KEY=y 464# CONFIG_TUN is not set
337CONFIG_INET=y
338# CONFIG_IP_MULTICAST is not set
339# CONFIG_IP_ADVANCED_ROUTER is not set
340CONFIG_IP_PNP=y
341# CONFIG_IP_PNP_DHCP is not set
342CONFIG_IP_PNP_BOOTP=y
343# CONFIG_IP_PNP_RARP is not set
344# CONFIG_NET_IPIP is not set
345# CONFIG_NET_IPGRE is not set
346# CONFIG_ARPD is not set
347# CONFIG_SYN_COOKIES is not set
348# CONFIG_INET_AH is not set
349# CONFIG_INET_ESP is not set
350# CONFIG_INET_IPCOMP is not set
351CONFIG_INET_TUNNEL=m
352CONFIG_IP_TCPDIAG=m
353# CONFIG_IP_TCPDIAG_IPV6 is not set
354# CONFIG_IPV6 is not set
355# CONFIG_NETFILTER is not set
356CONFIG_XFRM=y
357CONFIG_XFRM_USER=m
358 465
359# 466#
360# SCTP Configuration (EXPERIMENTAL) 467# PHY device support
361# 468#
362# CONFIG_IP_SCTP is not set 469CONFIG_PHYLIB=m
363# CONFIG_ATM is not set 470CONFIG_PHYCONTROL=y
364# CONFIG_BRIDGE is not set
365# CONFIG_VLAN_8021Q is not set
366# CONFIG_DECNET is not set
367# CONFIG_LLC2 is not set
368# CONFIG_IPX is not set
369# CONFIG_ATALK is not set
370# CONFIG_X25 is not set
371# CONFIG_LAPB is not set
372# CONFIG_NET_DIVERT is not set
373# CONFIG_ECONET is not set
374# CONFIG_WAN_ROUTER is not set
375 471
376# 472#
377# QoS and/or fair queueing 473# MII PHY device drivers
378# 474#
379# CONFIG_NET_SCHED is not set 475CONFIG_MARVELL_PHY=m
380# CONFIG_NET_CLS_ROUTE is not set 476CONFIG_DAVICOM_PHY=m
381 477CONFIG_QSEMI_PHY=m
382# 478CONFIG_LXT_PHY=m
383# Network testing 479CONFIG_CICADA_PHY=m
384#
385# CONFIG_NET_PKTGEN is not set
386# CONFIG_NETPOLL is not set
387# CONFIG_NET_POLL_CONTROLLER is not set
388# CONFIG_HAMRADIO is not set
389# CONFIG_IRDA is not set
390# CONFIG_BT is not set
391CONFIG_NETDEVICES=y
392# CONFIG_DUMMY is not set
393# CONFIG_BONDING is not set
394# CONFIG_EQUALIZER is not set
395# CONFIG_TUN is not set
396# CONFIG_ETHERTAP is not set
397 480
398# 481#
399# Ethernet (10 or 100Mbit) 482# Ethernet (10 or 100Mbit)
@@ -426,6 +509,8 @@ CONFIG_NET_ETHERNET=y
426# CONFIG_SLIP is not set 509# CONFIG_SLIP is not set
427# CONFIG_SHAPER is not set 510# CONFIG_SHAPER is not set
428# CONFIG_NETCONSOLE is not set 511# CONFIG_NETCONSOLE is not set
512# CONFIG_NETPOLL is not set
513# CONFIG_NET_POLL_CONTROLLER is not set
429 514
430# 515#
431# ISDN subsystem 516# ISDN subsystem
@@ -455,18 +540,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
455# CONFIG_INPUT_EVBUG is not set 540# CONFIG_INPUT_EVBUG is not set
456 541
457# 542#
458# Input I/O drivers
459#
460# CONFIG_GAMEPORT is not set
461CONFIG_SOUND_GAMEPORT=y
462CONFIG_SERIO=y
463# CONFIG_SERIO_I8042 is not set
464CONFIG_SERIO_SERPORT=y
465# CONFIG_SERIO_CT82C710 is not set
466# CONFIG_SERIO_LIBPS2 is not set
467CONFIG_SERIO_RAW=m
468
469#
470# Input Device Drivers 543# Input Device Drivers
471# 544#
472# CONFIG_INPUT_KEYBOARD is not set 545# CONFIG_INPUT_KEYBOARD is not set
@@ -476,6 +549,16 @@ CONFIG_SERIO_RAW=m
476# CONFIG_INPUT_MISC is not set 549# CONFIG_INPUT_MISC is not set
477 550
478# 551#
552# Hardware I/O ports
553#
554CONFIG_SERIO=y
555# CONFIG_SERIO_I8042 is not set
556CONFIG_SERIO_SERPORT=y
557# CONFIG_SERIO_LIBPS2 is not set
558CONFIG_SERIO_RAW=m
559# CONFIG_GAMEPORT is not set
560
561#
479# Character devices 562# Character devices
480# 563#
481CONFIG_VT=y 564CONFIG_VT=y
@@ -521,10 +604,13 @@ CONFIG_LEGACY_PTY_COUNT=256
521# 604#
522# Ftape, the floppy tape device driver 605# Ftape, the floppy tape device driver
523# 606#
524# CONFIG_DRM is not set
525# CONFIG_RAW_DRIVER is not set 607# CONFIG_RAW_DRIVER is not set
526 608
527# 609#
610# TPM devices
611#
612
613#
528# I2C support 614# I2C support
529# 615#
530# CONFIG_I2C is not set 616# CONFIG_I2C is not set
@@ -535,10 +621,20 @@ CONFIG_LEGACY_PTY_COUNT=256
535# CONFIG_W1 is not set 621# CONFIG_W1 is not set
536 622
537# 623#
624# Hardware Monitoring support
625#
626# CONFIG_HWMON is not set
627# CONFIG_HWMON_VID is not set
628
629#
538# Misc devices 630# Misc devices
539# 631#
540 632
541# 633#
634# Multimedia Capabilities Port drivers
635#
636
637#
542# Multimedia devices 638# Multimedia devices
543# 639#
544# CONFIG_VIDEO_DEV is not set 640# CONFIG_VIDEO_DEV is not set
@@ -558,7 +654,6 @@ CONFIG_LEGACY_PTY_COUNT=256
558# 654#
559# CONFIG_VGA_CONSOLE is not set 655# CONFIG_VGA_CONSOLE is not set
560CONFIG_DUMMY_CONSOLE=y 656CONFIG_DUMMY_CONSOLE=y
561# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
562 657
563# 658#
564# Sound 659# Sound
@@ -574,15 +669,9 @@ CONFIG_SOUND=y
574# Open Sound System 669# Open Sound System
575# 670#
576CONFIG_SOUND_PRIME=y 671CONFIG_SOUND_PRIME=y
577# CONFIG_SOUND_BT878 is not set
578# CONFIG_SOUND_FUSION is not set
579# CONFIG_SOUND_CS4281 is not set
580# CONFIG_SOUND_SONICVIBES is not set
581CONFIG_SOUND_IT8172=y 672CONFIG_SOUND_IT8172=y
582# CONFIG_SOUND_TRIDENT is not set
583# CONFIG_SOUND_MSNDCLAS is not set 673# CONFIG_SOUND_MSNDCLAS is not set
584# CONFIG_SOUND_MSNDPIN is not set 674# CONFIG_SOUND_MSNDPIN is not set
585# CONFIG_SOUND_OSS is not set
586# CONFIG_SOUND_AD1980 is not set 675# CONFIG_SOUND_AD1980 is not set
587 676
588# 677#
@@ -592,10 +681,6 @@ CONFIG_SOUND_IT8172=y
592# CONFIG_USB_ARCH_HAS_OHCI is not set 681# CONFIG_USB_ARCH_HAS_OHCI is not set
593 682
594# 683#
595# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
596#
597
598#
599# USB Gadget Support 684# USB Gadget Support
600# 685#
601# CONFIG_USB_GADGET is not set 686# CONFIG_USB_GADGET is not set
@@ -608,24 +693,31 @@ CONFIG_SOUND_IT8172=y
608# 693#
609# InfiniBand support 694# InfiniBand support
610# 695#
611# CONFIG_INFINIBAND is not set 696
697#
698# SN Devices
699#
612 700
613# 701#
614# File systems 702# File systems
615# 703#
616CONFIG_EXT2_FS=y 704CONFIG_EXT2_FS=y
617# CONFIG_EXT2_FS_XATTR is not set 705# CONFIG_EXT2_FS_XATTR is not set
706# CONFIG_EXT2_FS_XIP is not set
618# CONFIG_EXT3_FS is not set 707# CONFIG_EXT3_FS is not set
619# CONFIG_JBD is not set 708# CONFIG_JBD is not set
620# CONFIG_REISERFS_FS is not set 709# CONFIG_REISERFS_FS is not set
621# CONFIG_JFS_FS is not set 710# CONFIG_JFS_FS is not set
711# CONFIG_FS_POSIX_ACL is not set
622# CONFIG_XFS_FS is not set 712# CONFIG_XFS_FS is not set
623# CONFIG_MINIX_FS is not set 713# CONFIG_MINIX_FS is not set
624# CONFIG_ROMFS_FS is not set 714# CONFIG_ROMFS_FS is not set
715CONFIG_INOTIFY=y
625# CONFIG_QUOTA is not set 716# CONFIG_QUOTA is not set
626CONFIG_DNOTIFY=y 717CONFIG_DNOTIFY=y
627# CONFIG_AUTOFS_FS is not set 718# CONFIG_AUTOFS_FS is not set
628# CONFIG_AUTOFS4_FS is not set 719# CONFIG_AUTOFS4_FS is not set
720CONFIG_FUSE_FS=m
629 721
630# 722#
631# CD-ROM/DVD Filesystems 723# CD-ROM/DVD Filesystems
@@ -646,12 +738,10 @@ CONFIG_DNOTIFY=y
646CONFIG_PROC_FS=y 738CONFIG_PROC_FS=y
647CONFIG_PROC_KCORE=y 739CONFIG_PROC_KCORE=y
648CONFIG_SYSFS=y 740CONFIG_SYSFS=y
649# CONFIG_DEVFS_FS is not set
650CONFIG_DEVPTS_FS_XATTR=y
651CONFIG_DEVPTS_FS_SECURITY=y
652# CONFIG_TMPFS is not set 741# CONFIG_TMPFS is not set
653# CONFIG_HUGETLB_PAGE is not set 742# CONFIG_HUGETLB_PAGE is not set
654CONFIG_RAMFS=y 743CONFIG_RAMFS=y
744CONFIG_RELAYFS_FS=m
655 745
656# 746#
657# Miscellaneous filesystems 747# Miscellaneous filesystems
@@ -682,7 +772,7 @@ CONFIG_NFS_FS=y
682# CONFIG_NFSD is not set 772# CONFIG_NFSD is not set
683CONFIG_ROOT_NFS=y 773CONFIG_ROOT_NFS=y
684CONFIG_LOCKD=y 774CONFIG_LOCKD=y
685# CONFIG_EXPORTFS is not set 775CONFIG_NFS_COMMON=y
686CONFIG_SUNRPC=y 776CONFIG_SUNRPC=y
687# CONFIG_RPCSEC_GSS_KRB5 is not set 777# CONFIG_RPCSEC_GSS_KRB5 is not set
688# CONFIG_RPCSEC_GSS_SPKM3 is not set 778# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -691,6 +781,7 @@ CONFIG_SUNRPC=y
691# CONFIG_NCP_FS is not set 781# CONFIG_NCP_FS is not set
692# CONFIG_CODA_FS is not set 782# CONFIG_CODA_FS is not set
693# CONFIG_AFS_FS is not set 783# CONFIG_AFS_FS is not set
784# CONFIG_9P_FS is not set
694 785
695# 786#
696# Partition Types 787# Partition Types
@@ -711,7 +802,9 @@ CONFIG_MSDOS_PARTITION=y
711# 802#
712# Kernel hacking 803# Kernel hacking
713# 804#
805# CONFIG_PRINTK_TIME is not set
714# CONFIG_DEBUG_KERNEL is not set 806# CONFIG_DEBUG_KERNEL is not set
807CONFIG_LOG_BUF_SHIFT=14
715CONFIG_CROSSCOMPILE=y 808CONFIG_CROSSCOMPILE=y
716CONFIG_CMDLINE="" 809CONFIG_CMDLINE=""
717 810
@@ -725,7 +818,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
725# 818#
726# Cryptographic options 819# Cryptographic options
727# 820#
728# CONFIG_CRYPTO is not set 821CONFIG_CRYPTO=y
822CONFIG_CRYPTO_HMAC=y
823CONFIG_CRYPTO_NULL=m
824CONFIG_CRYPTO_MD4=m
825CONFIG_CRYPTO_MD5=m
826CONFIG_CRYPTO_SHA1=m
827CONFIG_CRYPTO_SHA256=m
828CONFIG_CRYPTO_SHA512=m
829CONFIG_CRYPTO_WP512=m
830CONFIG_CRYPTO_TGR192=m
831CONFIG_CRYPTO_DES=m
832CONFIG_CRYPTO_BLOWFISH=m
833CONFIG_CRYPTO_TWOFISH=m
834CONFIG_CRYPTO_SERPENT=m
835CONFIG_CRYPTO_AES=m
836CONFIG_CRYPTO_CAST5=m
837CONFIG_CRYPTO_CAST6=m
838CONFIG_CRYPTO_TEA=m
839CONFIG_CRYPTO_ARC4=m
840CONFIG_CRYPTO_KHAZAD=m
841CONFIG_CRYPTO_ANUBIS=m
842CONFIG_CRYPTO_DEFLATE=m
843CONFIG_CRYPTO_MICHAEL_MIC=m
844CONFIG_CRYPTO_CRC32C=m
845# CONFIG_CRYPTO_TEST is not set
729 846
730# 847#
731# Hardware crypto devices 848# Hardware crypto devices
@@ -735,7 +852,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
735# Library routines 852# Library routines
736# 853#
737# CONFIG_CRC_CCITT is not set 854# CONFIG_CRC_CCITT is not set
738# CONFIG_CRC32 is not set 855CONFIG_CRC16=m
856CONFIG_CRC32=m
739CONFIG_LIBCRC32C=m 857CONFIG_LIBCRC32C=m
740CONFIG_GENERIC_HARDIRQS=y 858CONFIG_ZLIB_INFLATE=m
741CONFIG_GENERIC_IRQ_PROBE=y 859CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig
index 583ef5c5b1cd..9ba61dfc490d 100644
--- a/arch/mips/configs/ivr_defconfig
+++ b/arch/mips/configs/ivr_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:05 2005 4# Thu Oct 20 22:26:12 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,11 +11,13 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
@@ -26,13 +25,16 @@ CONFIG_BSD_PROCESS_ACCT=y
26# CONFIG_BSD_PROCESS_ACCT_V3 is not set 25# CONFIG_BSD_PROCESS_ACCT_V3 is not set
27CONFIG_SYSCTL=y 26CONFIG_SYSCTL=y
28# CONFIG_AUDIT is not set 27# CONFIG_AUDIT is not set
29CONFIG_LOG_BUF_SHIFT=14 28CONFIG_HOTPLUG=y
30# CONFIG_HOTPLUG is not set
31CONFIG_KOBJECT_UEVENT=y 29CONFIG_KOBJECT_UEVENT=y
32# CONFIG_IKCONFIG is not set 30# CONFIG_IKCONFIG is not set
31CONFIG_INITRAMFS_SOURCE=""
33CONFIG_EMBEDDED=y 32CONFIG_EMBEDDED=y
34CONFIG_KALLSYMS=y 33CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_EXTRA_PASS is not set 34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
36CONFIG_FUTEX=y 38CONFIG_FUTEX=y
37CONFIG_EPOLL=y 39CONFIG_EPOLL=y
38# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -42,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0
42CONFIG_CC_ALIGN_LOOPS=0 44CONFIG_CC_ALIGN_LOOPS=0
43CONFIG_CC_ALIGN_JUMPS=0 45CONFIG_CC_ALIGN_JUMPS=0
44# CONFIG_TINY_SHMEM is not set 46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
45 48
46# 49#
47# Loadable module support 50# Loadable module support
@@ -57,40 +60,68 @@ CONFIG_KMOD=y
57# 60#
58# Machine selection 61# Machine selection
59# 62#
60# CONFIG_MACH_JAZZ is not set 63# CONFIG_MIPS_MTX1 is not set
61# CONFIG_MACH_VR41XX is not set 64# CONFIG_MIPS_BOSPORUS is not set
62# CONFIG_TOSHIBA_JMR3927 is not set 65# CONFIG_MIPS_PB1000 is not set
66# CONFIG_MIPS_PB1100 is not set
67# CONFIG_MIPS_PB1500 is not set
68# CONFIG_MIPS_PB1550 is not set
69# CONFIG_MIPS_PB1200 is not set
70# CONFIG_MIPS_DB1000 is not set
71# CONFIG_MIPS_DB1100 is not set
72# CONFIG_MIPS_DB1500 is not set
73# CONFIG_MIPS_DB1550 is not set
74# CONFIG_MIPS_DB1200 is not set
75# CONFIG_MIPS_MIRAGE is not set
63# CONFIG_MIPS_COBALT is not set 76# CONFIG_MIPS_COBALT is not set
64# CONFIG_MACH_DECSTATION is not set 77# CONFIG_MACH_DECSTATION is not set
65# CONFIG_MIPS_EV64120 is not set 78# CONFIG_MIPS_EV64120 is not set
66# CONFIG_MIPS_EV96100 is not set 79# CONFIG_MIPS_EV96100 is not set
67CONFIG_MIPS_IVR=y 80CONFIG_MIPS_IVR=y
68# CONFIG_LASAT is not set
69# CONFIG_MIPS_ITE8172 is not set 81# CONFIG_MIPS_ITE8172 is not set
82# CONFIG_MACH_JAZZ is not set
83# CONFIG_LASAT is not set
70# CONFIG_MIPS_ATLAS is not set 84# CONFIG_MIPS_ATLAS is not set
71# CONFIG_MIPS_MALTA is not set 85# CONFIG_MIPS_MALTA is not set
72# CONFIG_MIPS_SEAD is not set 86# CONFIG_MIPS_SEAD is not set
87# CONFIG_MIPS_SIM is not set
88# CONFIG_MOMENCO_JAGUAR_ATX is not set
73# CONFIG_MOMENCO_OCELOT is not set 89# CONFIG_MOMENCO_OCELOT is not set
74# CONFIG_MOMENCO_OCELOT_G is not set
75# CONFIG_MOMENCO_OCELOT_C is not set
76# CONFIG_MOMENCO_OCELOT_3 is not set 90# CONFIG_MOMENCO_OCELOT_3 is not set
77# CONFIG_MOMENCO_JAGUAR_ATX is not set 91# CONFIG_MOMENCO_OCELOT_C is not set
78# CONFIG_PMC_YOSEMITE is not set 92# CONFIG_MOMENCO_OCELOT_G is not set
93# CONFIG_MIPS_XXS1500 is not set
94# CONFIG_PNX8550_V2PCI is not set
95# CONFIG_PNX8550_JBS is not set
79# CONFIG_DDB5074 is not set 96# CONFIG_DDB5074 is not set
80# CONFIG_DDB5476 is not set 97# CONFIG_DDB5476 is not set
81# CONFIG_DDB5477 is not set 98# CONFIG_DDB5477 is not set
82# CONFIG_NEC_OSPREY is not set 99# CONFIG_MACH_VR41XX is not set
100# CONFIG_PMC_YOSEMITE is not set
101# CONFIG_QEMU is not set
83# CONFIG_SGI_IP22 is not set 102# CONFIG_SGI_IP22 is not set
84# CONFIG_SOC_AU1X00 is not set 103# CONFIG_SGI_IP27 is not set
85# CONFIG_SIBYTE_SB1xxx_SOC is not set 104# CONFIG_SGI_IP32 is not set
105# CONFIG_SIBYTE_BIGSUR is not set
106# CONFIG_SIBYTE_SWARM is not set
107# CONFIG_SIBYTE_SENTOSA is not set
108# CONFIG_SIBYTE_RHONE is not set
109# CONFIG_SIBYTE_CARMEL is not set
110# CONFIG_SIBYTE_PTSWARM is not set
111# CONFIG_SIBYTE_LITTLESUR is not set
112# CONFIG_SIBYTE_CRHINE is not set
113# CONFIG_SIBYTE_CRHONE is not set
86# CONFIG_SNI_RM200_PCI is not set 114# CONFIG_SNI_RM200_PCI is not set
115# CONFIG_TOSHIBA_JMR3927 is not set
87# CONFIG_TOSHIBA_RBTX4927 is not set 116# CONFIG_TOSHIBA_RBTX4927 is not set
117# CONFIG_TOSHIBA_RBTX4938 is not set
88CONFIG_RWSEM_GENERIC_SPINLOCK=y 118CONFIG_RWSEM_GENERIC_SPINLOCK=y
89CONFIG_GENERIC_CALIBRATE_DELAY=y 119CONFIG_GENERIC_CALIBRATE_DELAY=y
90CONFIG_HAVE_DEC_LOCK=y
91CONFIG_DMA_NONCOHERENT=y 120CONFIG_DMA_NONCOHERENT=y
92CONFIG_DMA_NEED_PCI_MAP_STATE=y 121CONFIG_DMA_NEED_PCI_MAP_STATE=y
122# CONFIG_CPU_BIG_ENDIAN is not set
93CONFIG_CPU_LITTLE_ENDIAN=y 123CONFIG_CPU_LITTLE_ENDIAN=y
124CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
94CONFIG_ITE_BOARD_GEN=y 125CONFIG_ITE_BOARD_GEN=y
95CONFIG_IT8172_CIR=y 126CONFIG_IT8172_CIR=y
96CONFIG_MIPS_L1_CACHE_SHIFT=5 127CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -98,8 +129,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
98# 129#
99# CPU selection 130# CPU selection
100# 131#
101# CONFIG_CPU_MIPS32 is not set 132# CONFIG_CPU_MIPS32_R1 is not set
102# CONFIG_CPU_MIPS64 is not set 133# CONFIG_CPU_MIPS32_R2 is not set
134# CONFIG_CPU_MIPS64_R1 is not set
135# CONFIG_CPU_MIPS64_R2 is not set
103# CONFIG_CPU_R3000 is not set 136# CONFIG_CPU_R3000 is not set
104# CONFIG_CPU_TX39XX is not set 137# CONFIG_CPU_TX39XX is not set
105# CONFIG_CPU_VR41XX is not set 138# CONFIG_CPU_VR41XX is not set
@@ -115,14 +148,38 @@ CONFIG_CPU_NEVADA=y
115# CONFIG_CPU_RM7000 is not set 148# CONFIG_CPU_RM7000 is not set
116# CONFIG_CPU_RM9000 is not set 149# CONFIG_CPU_RM9000 is not set
117# CONFIG_CPU_SB1 is not set 150# CONFIG_CPU_SB1 is not set
151CONFIG_SYS_HAS_CPU_NEVADA=y
152CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
153CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
154CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
155CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
156
157#
158# Kernel type
159#
160CONFIG_32BIT=y
161# CONFIG_64BIT is not set
118CONFIG_PAGE_SIZE_4KB=y 162CONFIG_PAGE_SIZE_4KB=y
119# CONFIG_PAGE_SIZE_8KB is not set 163# CONFIG_PAGE_SIZE_8KB is not set
120# CONFIG_PAGE_SIZE_16KB is not set 164# CONFIG_PAGE_SIZE_16KB is not set
121# CONFIG_PAGE_SIZE_64KB is not set 165# CONFIG_PAGE_SIZE_64KB is not set
166# CONFIG_MIPS_MT is not set
122# CONFIG_CPU_ADVANCED is not set 167# CONFIG_CPU_ADVANCED is not set
123CONFIG_CPU_HAS_LLSC=y 168CONFIG_CPU_HAS_LLSC=y
124CONFIG_CPU_HAS_LLDSCD=y 169CONFIG_CPU_HAS_LLDSCD=y
125CONFIG_CPU_HAS_SYNC=y 170CONFIG_CPU_HAS_SYNC=y
171CONFIG_GENERIC_HARDIRQS=y
172CONFIG_GENERIC_IRQ_PROBE=y
173CONFIG_ARCH_FLATMEM_ENABLE=y
174CONFIG_SELECT_MEMORY_MODEL=y
175CONFIG_FLATMEM_MANUAL=y
176# CONFIG_DISCONTIGMEM_MANUAL is not set
177# CONFIG_SPARSEMEM_MANUAL is not set
178CONFIG_FLATMEM=y
179CONFIG_FLAT_NODE_MEM_MAP=y
180# CONFIG_SPARSEMEM_STATIC is not set
181CONFIG_PREEMPT_NONE=y
182# CONFIG_PREEMPT_VOLUNTARY is not set
126# CONFIG_PREEMPT is not set 183# CONFIG_PREEMPT is not set
127 184
128# 185#
@@ -131,7 +188,6 @@ CONFIG_CPU_HAS_SYNC=y
131CONFIG_HW_HAS_PCI=y 188CONFIG_HW_HAS_PCI=y
132CONFIG_PCI=y 189CONFIG_PCI=y
133CONFIG_PCI_LEGACY_PROC=y 190CONFIG_PCI_LEGACY_PROC=y
134CONFIG_PCI_NAMES=y
135CONFIG_MMU=y 191CONFIG_MMU=y
136 192
137# 193#
@@ -140,10 +196,6 @@ CONFIG_MMU=y
140# CONFIG_PCCARD is not set 196# CONFIG_PCCARD is not set
141 197
142# 198#
143# PC-card bridges
144#
145
146#
147# PCI Hotplug Support 199# PCI Hotplug Support
148# 200#
149# CONFIG_HOTPLUG_PCI is not set 201# CONFIG_HOTPLUG_PCI is not set
@@ -156,6 +208,80 @@ CONFIG_BINFMT_ELF=y
156CONFIG_TRAD_SIGNALS=y 208CONFIG_TRAD_SIGNALS=y
157 209
158# 210#
211# Networking
212#
213CONFIG_NET=y
214
215#
216# Networking options
217#
218CONFIG_PACKET=y
219CONFIG_PACKET_MMAP=y
220CONFIG_UNIX=y
221CONFIG_XFRM=y
222CONFIG_XFRM_USER=m
223CONFIG_NET_KEY=y
224CONFIG_INET=y
225# CONFIG_IP_MULTICAST is not set
226# CONFIG_IP_ADVANCED_ROUTER is not set
227CONFIG_IP_FIB_HASH=y
228CONFIG_IP_PNP=y
229# CONFIG_IP_PNP_DHCP is not set
230CONFIG_IP_PNP_BOOTP=y
231# CONFIG_IP_PNP_RARP is not set
232# CONFIG_NET_IPIP is not set
233# CONFIG_NET_IPGRE is not set
234# CONFIG_ARPD is not set
235# CONFIG_SYN_COOKIES is not set
236# CONFIG_INET_AH is not set
237# CONFIG_INET_ESP is not set
238# CONFIG_INET_IPCOMP is not set
239CONFIG_INET_TUNNEL=m
240CONFIG_INET_DIAG=y
241CONFIG_INET_TCP_DIAG=y
242# CONFIG_TCP_CONG_ADVANCED is not set
243CONFIG_TCP_CONG_BIC=y
244# CONFIG_IPV6 is not set
245# CONFIG_NETFILTER is not set
246
247#
248# DCCP Configuration (EXPERIMENTAL)
249#
250# CONFIG_IP_DCCP is not set
251
252#
253# SCTP Configuration (EXPERIMENTAL)
254#
255# CONFIG_IP_SCTP is not set
256# CONFIG_ATM is not set
257# CONFIG_BRIDGE is not set
258# CONFIG_VLAN_8021Q is not set
259# CONFIG_DECNET is not set
260# CONFIG_LLC2 is not set
261# CONFIG_IPX is not set
262# CONFIG_ATALK is not set
263# CONFIG_X25 is not set
264# CONFIG_LAPB is not set
265# CONFIG_NET_DIVERT is not set
266# CONFIG_ECONET is not set
267# CONFIG_WAN_ROUTER is not set
268# CONFIG_NET_SCHED is not set
269# CONFIG_NET_CLS_ROUTE is not set
270
271#
272# Network testing
273#
274# CONFIG_NET_PKTGEN is not set
275# CONFIG_HAMRADIO is not set
276# CONFIG_IRDA is not set
277# CONFIG_BT is not set
278CONFIG_IEEE80211=m
279# CONFIG_IEEE80211_DEBUG is not set
280CONFIG_IEEE80211_CRYPT_WEP=m
281CONFIG_IEEE80211_CRYPT_CCMP=m
282CONFIG_IEEE80211_CRYPT_TKIP=m
283
284#
159# Device Drivers 285# Device Drivers
160# 286#
161 287
@@ -164,7 +290,12 @@ CONFIG_TRAD_SIGNALS=y
164# 290#
165CONFIG_STANDALONE=y 291CONFIG_STANDALONE=y
166CONFIG_PREVENT_FIRMWARE_BUILD=y 292CONFIG_PREVENT_FIRMWARE_BUILD=y
167# CONFIG_FW_LOADER is not set 293CONFIG_FW_LOADER=m
294
295#
296# Connector - unified userspace <-> kernelspace linker
297#
298CONFIG_CONNECTOR=m
168 299
169# 300#
170# Memory Technology Devices (MTD) 301# Memory Technology Devices (MTD)
@@ -183,7 +314,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
183# 314#
184# Block devices 315# Block devices
185# 316#
186# CONFIG_BLK_DEV_FD is not set
187# CONFIG_BLK_CPQ_DA is not set 317# CONFIG_BLK_CPQ_DA is not set
188# CONFIG_BLK_CPQ_CISS_DA is not set 318# CONFIG_BLK_CPQ_CISS_DA is not set
189# CONFIG_BLK_DEV_DAC960 is not set 319# CONFIG_BLK_DEV_DAC960 is not set
@@ -194,7 +324,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
194# CONFIG_BLK_DEV_SX8 is not set 324# CONFIG_BLK_DEV_SX8 is not set
195# CONFIG_BLK_DEV_RAM is not set 325# CONFIG_BLK_DEV_RAM is not set
196CONFIG_BLK_DEV_RAM_COUNT=16 326CONFIG_BLK_DEV_RAM_COUNT=16
197CONFIG_INITRAMFS_SOURCE=""
198# CONFIG_LBD is not set 327# CONFIG_LBD is not set
199CONFIG_CDROM_PKTCDVD=m 328CONFIG_CDROM_PKTCDVD=m
200CONFIG_CDROM_PKTCDVD_BUFFERS=8 329CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -239,6 +368,7 @@ CONFIG_IDE_GENERIC=y
239# 368#
240# SCSI device support 369# SCSI device support
241# 370#
371CONFIG_RAID_ATTRS=m
242# CONFIG_SCSI is not set 372# CONFIG_SCSI is not set
243 373
244# 374#
@@ -249,6 +379,7 @@ CONFIG_IDE_GENERIC=y
249# 379#
250# Fusion MPT device support 380# Fusion MPT device support
251# 381#
382# CONFIG_FUSION is not set
252 383
253# 384#
254# IEEE 1394 (FireWire) support 385# IEEE 1394 (FireWire) support
@@ -261,78 +392,13 @@ CONFIG_IDE_GENERIC=y
261# CONFIG_I2O is not set 392# CONFIG_I2O is not set
262 393
263# 394#
264# Networking support 395# Network device support
265#
266CONFIG_NET=y
267
268#
269# Networking options
270#
271CONFIG_PACKET=y
272CONFIG_PACKET_MMAP=y
273CONFIG_NETLINK_DEV=y
274CONFIG_UNIX=y
275CONFIG_NET_KEY=y
276CONFIG_INET=y
277# CONFIG_IP_MULTICAST is not set
278# CONFIG_IP_ADVANCED_ROUTER is not set
279CONFIG_IP_PNP=y
280# CONFIG_IP_PNP_DHCP is not set
281CONFIG_IP_PNP_BOOTP=y
282# CONFIG_IP_PNP_RARP is not set
283# CONFIG_NET_IPIP is not set
284# CONFIG_NET_IPGRE is not set
285# CONFIG_ARPD is not set
286# CONFIG_SYN_COOKIES is not set
287# CONFIG_INET_AH is not set
288# CONFIG_INET_ESP is not set
289# CONFIG_INET_IPCOMP is not set
290CONFIG_INET_TUNNEL=m
291CONFIG_IP_TCPDIAG=m
292# CONFIG_IP_TCPDIAG_IPV6 is not set
293# CONFIG_IPV6 is not set
294# CONFIG_NETFILTER is not set
295CONFIG_XFRM=y
296CONFIG_XFRM_USER=m
297
298#
299# SCTP Configuration (EXPERIMENTAL)
300# 396#
301# CONFIG_IP_SCTP is not set
302# CONFIG_ATM is not set
303# CONFIG_BRIDGE is not set
304# CONFIG_VLAN_8021Q is not set
305# CONFIG_DECNET is not set
306# CONFIG_LLC2 is not set
307# CONFIG_IPX is not set
308# CONFIG_ATALK is not set
309# CONFIG_X25 is not set
310# CONFIG_LAPB is not set
311# CONFIG_NET_DIVERT is not set
312# CONFIG_ECONET is not set
313# CONFIG_WAN_ROUTER is not set
314
315#
316# QoS and/or fair queueing
317#
318# CONFIG_NET_SCHED is not set
319# CONFIG_NET_CLS_ROUTE is not set
320
321#
322# Network testing
323#
324# CONFIG_NET_PKTGEN is not set
325# CONFIG_NETPOLL is not set
326# CONFIG_NET_POLL_CONTROLLER is not set
327# CONFIG_HAMRADIO is not set
328# CONFIG_IRDA is not set
329# CONFIG_BT is not set
330CONFIG_NETDEVICES=y 397CONFIG_NETDEVICES=y
331# CONFIG_DUMMY is not set 398# CONFIG_DUMMY is not set
332# CONFIG_BONDING is not set 399# CONFIG_BONDING is not set
333# CONFIG_EQUALIZER is not set 400# CONFIG_EQUALIZER is not set
334# CONFIG_TUN is not set 401# CONFIG_TUN is not set
335# CONFIG_ETHERTAP is not set
336 402
337# 403#
338# ARCnet devices 404# ARCnet devices
@@ -340,6 +406,21 @@ CONFIG_NETDEVICES=y
340# CONFIG_ARCNET is not set 406# CONFIG_ARCNET is not set
341 407
342# 408#
409# PHY device support
410#
411CONFIG_PHYLIB=m
412CONFIG_PHYCONTROL=y
413
414#
415# MII PHY device drivers
416#
417CONFIG_MARVELL_PHY=m
418CONFIG_DAVICOM_PHY=m
419CONFIG_QSEMI_PHY=m
420CONFIG_LXT_PHY=m
421CONFIG_CICADA_PHY=m
422
423#
343# Ethernet (10 or 100Mbit) 424# Ethernet (10 or 100Mbit)
344# 425#
345CONFIG_NET_ETHERNET=y 426CONFIG_NET_ETHERNET=y
@@ -365,12 +446,16 @@ CONFIG_NET_ETHERNET=y
365# CONFIG_HAMACHI is not set 446# CONFIG_HAMACHI is not set
366# CONFIG_YELLOWFIN is not set 447# CONFIG_YELLOWFIN is not set
367# CONFIG_R8169 is not set 448# CONFIG_R8169 is not set
449# CONFIG_SIS190 is not set
450# CONFIG_SKGE is not set
368# CONFIG_SK98LIN is not set 451# CONFIG_SK98LIN is not set
369# CONFIG_TIGON3 is not set 452# CONFIG_TIGON3 is not set
453# CONFIG_BNX2 is not set
370 454
371# 455#
372# Ethernet (10000 Mbit) 456# Ethernet (10000 Mbit)
373# 457#
458# CONFIG_CHELSIO_T1 is not set
374# CONFIG_IXGB is not set 459# CONFIG_IXGB is not set
375# CONFIG_S2IO is not set 460# CONFIG_S2IO is not set
376 461
@@ -383,6 +468,8 @@ CONFIG_NET_ETHERNET=y
383# Wireless LAN (non-hamradio) 468# Wireless LAN (non-hamradio)
384# 469#
385# CONFIG_NET_RADIO is not set 470# CONFIG_NET_RADIO is not set
471# CONFIG_IPW_DEBUG is not set
472CONFIG_IPW2200=m
386 473
387# 474#
388# Wan interfaces 475# Wan interfaces
@@ -394,6 +481,8 @@ CONFIG_NET_ETHERNET=y
394# CONFIG_SLIP is not set 481# CONFIG_SLIP is not set
395# CONFIG_SHAPER is not set 482# CONFIG_SHAPER is not set
396# CONFIG_NETCONSOLE is not set 483# CONFIG_NETCONSOLE is not set
484# CONFIG_NETPOLL is not set
485# CONFIG_NET_POLL_CONTROLLER is not set
397 486
398# 487#
399# ISDN subsystem 488# ISDN subsystem
@@ -423,19 +512,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
423# CONFIG_INPUT_EVBUG is not set 512# CONFIG_INPUT_EVBUG is not set
424 513
425# 514#
426# Input I/O drivers
427#
428# CONFIG_GAMEPORT is not set
429CONFIG_SOUND_GAMEPORT=y
430CONFIG_SERIO=y
431# CONFIG_SERIO_I8042 is not set
432CONFIG_SERIO_SERPORT=y
433# CONFIG_SERIO_CT82C710 is not set
434# CONFIG_SERIO_PCIPS2 is not set
435# CONFIG_SERIO_LIBPS2 is not set
436CONFIG_SERIO_RAW=m
437
438#
439# Input Device Drivers 515# Input Device Drivers
440# 516#
441# CONFIG_INPUT_KEYBOARD is not set 517# CONFIG_INPUT_KEYBOARD is not set
@@ -445,6 +521,17 @@ CONFIG_SERIO_RAW=m
445# CONFIG_INPUT_MISC is not set 521# CONFIG_INPUT_MISC is not set
446 522
447# 523#
524# Hardware I/O ports
525#
526CONFIG_SERIO=y
527# CONFIG_SERIO_I8042 is not set
528CONFIG_SERIO_SERPORT=y
529# CONFIG_SERIO_PCIPS2 is not set
530# CONFIG_SERIO_LIBPS2 is not set
531CONFIG_SERIO_RAW=m
532# CONFIG_GAMEPORT is not set
533
534#
448# Character devices 535# Character devices
449# 536#
450CONFIG_VT=y 537CONFIG_VT=y
@@ -467,6 +554,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
467# 554#
468CONFIG_SERIAL_CORE=y 555CONFIG_SERIAL_CORE=y
469CONFIG_SERIAL_CORE_CONSOLE=y 556CONFIG_SERIAL_CORE_CONSOLE=y
557# CONFIG_SERIAL_JSM is not set
470CONFIG_UNIX98_PTYS=y 558CONFIG_UNIX98_PTYS=y
471CONFIG_LEGACY_PTYS=y 559CONFIG_LEGACY_PTYS=y
472CONFIG_LEGACY_PTY_COUNT=256 560CONFIG_LEGACY_PTY_COUNT=256
@@ -492,6 +580,11 @@ CONFIG_RTC=y
492# CONFIG_RAW_DRIVER is not set 580# CONFIG_RAW_DRIVER is not set
493 581
494# 582#
583# TPM devices
584#
585# CONFIG_TCG_TPM is not set
586
587#
495# I2C support 588# I2C support
496# 589#
497# CONFIG_I2C is not set 590# CONFIG_I2C is not set
@@ -502,10 +595,20 @@ CONFIG_RTC=y
502# CONFIG_W1 is not set 595# CONFIG_W1 is not set
503 596
504# 597#
598# Hardware Monitoring support
599#
600# CONFIG_HWMON is not set
601# CONFIG_HWMON_VID is not set
602
603#
505# Misc devices 604# Misc devices
506# 605#
507 606
508# 607#
608# Multimedia Capabilities Port drivers
609#
610
611#
509# Multimedia devices 612# Multimedia devices
510# 613#
511# CONFIG_VIDEO_DEV is not set 614# CONFIG_VIDEO_DEV is not set
@@ -525,7 +628,6 @@ CONFIG_RTC=y
525# 628#
526# CONFIG_VGA_CONSOLE is not set 629# CONFIG_VGA_CONSOLE is not set
527CONFIG_DUMMY_CONSOLE=y 630CONFIG_DUMMY_CONSOLE=y
528# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
529 631
530# 632#
531# Sound 633# Sound
@@ -535,13 +637,9 @@ CONFIG_DUMMY_CONSOLE=y
535# 637#
536# USB support 638# USB support
537# 639#
538# CONFIG_USB is not set
539CONFIG_USB_ARCH_HAS_HCD=y 640CONFIG_USB_ARCH_HAS_HCD=y
540CONFIG_USB_ARCH_HAS_OHCI=y 641CONFIG_USB_ARCH_HAS_OHCI=y
541 642# CONFIG_USB is not set
542#
543# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
544#
545 643
546# 644#
547# USB Gadget Support 645# USB Gadget Support
@@ -559,21 +657,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y
559# CONFIG_INFINIBAND is not set 657# CONFIG_INFINIBAND is not set
560 658
561# 659#
660# SN Devices
661#
662
663#
562# File systems 664# File systems
563# 665#
564CONFIG_EXT2_FS=y 666CONFIG_EXT2_FS=y
565# CONFIG_EXT2_FS_XATTR is not set 667# CONFIG_EXT2_FS_XATTR is not set
668# CONFIG_EXT2_FS_XIP is not set
566# CONFIG_EXT3_FS is not set 669# CONFIG_EXT3_FS is not set
567# CONFIG_JBD is not set 670# CONFIG_JBD is not set
568# CONFIG_REISERFS_FS is not set 671# CONFIG_REISERFS_FS is not set
569# CONFIG_JFS_FS is not set 672# CONFIG_JFS_FS is not set
673# CONFIG_FS_POSIX_ACL is not set
570# CONFIG_XFS_FS is not set 674# CONFIG_XFS_FS is not set
571# CONFIG_MINIX_FS is not set 675# CONFIG_MINIX_FS is not set
572# CONFIG_ROMFS_FS is not set 676# CONFIG_ROMFS_FS is not set
677CONFIG_INOTIFY=y
573# CONFIG_QUOTA is not set 678# CONFIG_QUOTA is not set
574CONFIG_DNOTIFY=y 679CONFIG_DNOTIFY=y
575# CONFIG_AUTOFS_FS is not set 680# CONFIG_AUTOFS_FS is not set
576# CONFIG_AUTOFS4_FS is not set 681# CONFIG_AUTOFS4_FS is not set
682CONFIG_FUSE_FS=m
577 683
578# 684#
579# CD-ROM/DVD Filesystems 685# CD-ROM/DVD Filesystems
@@ -594,12 +700,10 @@ CONFIG_DNOTIFY=y
594CONFIG_PROC_FS=y 700CONFIG_PROC_FS=y
595CONFIG_PROC_KCORE=y 701CONFIG_PROC_KCORE=y
596CONFIG_SYSFS=y 702CONFIG_SYSFS=y
597# CONFIG_DEVFS_FS is not set
598CONFIG_DEVPTS_FS_XATTR=y
599CONFIG_DEVPTS_FS_SECURITY=y
600# CONFIG_TMPFS is not set 703# CONFIG_TMPFS is not set
601# CONFIG_HUGETLB_PAGE is not set 704# CONFIG_HUGETLB_PAGE is not set
602CONFIG_RAMFS=y 705CONFIG_RAMFS=y
706CONFIG_RELAYFS_FS=m
603 707
604# 708#
605# Miscellaneous filesystems 709# Miscellaneous filesystems
@@ -628,7 +732,7 @@ CONFIG_NFS_FS=y
628# CONFIG_NFSD is not set 732# CONFIG_NFSD is not set
629CONFIG_ROOT_NFS=y 733CONFIG_ROOT_NFS=y
630CONFIG_LOCKD=y 734CONFIG_LOCKD=y
631# CONFIG_EXPORTFS is not set 735CONFIG_NFS_COMMON=y
632CONFIG_SUNRPC=y 736CONFIG_SUNRPC=y
633# CONFIG_RPCSEC_GSS_KRB5 is not set 737# CONFIG_RPCSEC_GSS_KRB5 is not set
634# CONFIG_RPCSEC_GSS_SPKM3 is not set 738# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -637,6 +741,7 @@ CONFIG_SUNRPC=y
637# CONFIG_NCP_FS is not set 741# CONFIG_NCP_FS is not set
638# CONFIG_CODA_FS is not set 742# CONFIG_CODA_FS is not set
639# CONFIG_AFS_FS is not set 743# CONFIG_AFS_FS is not set
744# CONFIG_9P_FS is not set
640 745
641# 746#
642# Partition Types 747# Partition Types
@@ -657,7 +762,9 @@ CONFIG_MSDOS_PARTITION=y
657# 762#
658# Kernel hacking 763# Kernel hacking
659# 764#
765# CONFIG_PRINTK_TIME is not set
660# CONFIG_DEBUG_KERNEL is not set 766# CONFIG_DEBUG_KERNEL is not set
767CONFIG_LOG_BUF_SHIFT=14
661CONFIG_CROSSCOMPILE=y 768CONFIG_CROSSCOMPILE=y
662CONFIG_CMDLINE="" 769CONFIG_CMDLINE=""
663 770
@@ -671,7 +778,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
671# 778#
672# Cryptographic options 779# Cryptographic options
673# 780#
674# CONFIG_CRYPTO is not set 781CONFIG_CRYPTO=y
782CONFIG_CRYPTO_HMAC=y
783CONFIG_CRYPTO_NULL=m
784CONFIG_CRYPTO_MD4=m
785CONFIG_CRYPTO_MD5=m
786CONFIG_CRYPTO_SHA1=m
787CONFIG_CRYPTO_SHA256=m
788CONFIG_CRYPTO_SHA512=m
789CONFIG_CRYPTO_WP512=m
790CONFIG_CRYPTO_TGR192=m
791CONFIG_CRYPTO_DES=m
792CONFIG_CRYPTO_BLOWFISH=m
793CONFIG_CRYPTO_TWOFISH=m
794CONFIG_CRYPTO_SERPENT=m
795CONFIG_CRYPTO_AES=m
796CONFIG_CRYPTO_CAST5=m
797CONFIG_CRYPTO_CAST6=m
798CONFIG_CRYPTO_TEA=m
799CONFIG_CRYPTO_ARC4=m
800CONFIG_CRYPTO_KHAZAD=m
801CONFIG_CRYPTO_ANUBIS=m
802CONFIG_CRYPTO_DEFLATE=m
803CONFIG_CRYPTO_MICHAEL_MIC=m
804CONFIG_CRYPTO_CRC32C=m
805# CONFIG_CRYPTO_TEST is not set
675 806
676# 807#
677# Hardware crypto devices 808# Hardware crypto devices
@@ -681,7 +812,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
681# Library routines 812# Library routines
682# 813#
683# CONFIG_CRC_CCITT is not set 814# CONFIG_CRC_CCITT is not set
684# CONFIG_CRC32 is not set 815CONFIG_CRC16=m
816CONFIG_CRC32=m
685CONFIG_LIBCRC32C=m 817CONFIG_LIBCRC32C=m
686CONFIG_GENERIC_HARDIRQS=y 818CONFIG_ZLIB_INFLATE=m
687CONFIG_GENERIC_IRQ_PROBE=y 819CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig
index 8abb5a0c6c12..21b2b8042f91 100644
--- a/arch/mips/configs/jaguar-atx_defconfig
+++ b/arch/mips/configs/jaguar-atx_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:05 2005 4# Thu Oct 20 22:26:14 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14# CONFIG_EXPERIMENTAL is not set 11# CONFIG_EXPERIMENTAL is not set
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_BSD_PROCESS_ACCT is not set 23# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y 24CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set 25# CONFIG_AUDIT is not set
27CONFIG_LOG_BUF_SHIFT=14 26CONFIG_HOTPLUG=y
28# CONFIG_HOTPLUG is not set
29CONFIG_KOBJECT_UEVENT=y 27CONFIG_KOBJECT_UEVENT=y
30CONFIG_IKCONFIG=y 28CONFIG_IKCONFIG=y
31CONFIG_IKCONFIG_PROC=y 29CONFIG_IKCONFIG_PROC=y
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -54,36 +57,70 @@ CONFIG_KMOD=y
54# 57#
55# Machine selection 58# Machine selection
56# 59#
57# CONFIG_MACH_JAZZ is not set 60# CONFIG_MIPS_MTX1 is not set
58# CONFIG_MACH_VR41XX is not set 61# CONFIG_MIPS_BOSPORUS is not set
59# CONFIG_TOSHIBA_JMR3927 is not set 62# CONFIG_MIPS_PB1000 is not set
63# CONFIG_MIPS_PB1100 is not set
64# CONFIG_MIPS_PB1500 is not set
65# CONFIG_MIPS_PB1550 is not set
66# CONFIG_MIPS_PB1200 is not set
67# CONFIG_MIPS_DB1000 is not set
68# CONFIG_MIPS_DB1100 is not set
69# CONFIG_MIPS_DB1500 is not set
70# CONFIG_MIPS_DB1550 is not set
71# CONFIG_MIPS_DB1200 is not set
72# CONFIG_MIPS_MIRAGE is not set
73# CONFIG_MIPS_COBALT is not set
60# CONFIG_MACH_DECSTATION is not set 74# CONFIG_MACH_DECSTATION is not set
75# CONFIG_MIPS_EV64120 is not set
76# CONFIG_MIPS_EV96100 is not set
61# CONFIG_MIPS_IVR is not set 77# CONFIG_MIPS_IVR is not set
62# CONFIG_LASAT is not set
63# CONFIG_MIPS_ITE8172 is not set 78# CONFIG_MIPS_ITE8172 is not set
79# CONFIG_MACH_JAZZ is not set
80# CONFIG_LASAT is not set
64# CONFIG_MIPS_ATLAS is not set 81# CONFIG_MIPS_ATLAS is not set
65# CONFIG_MIPS_MALTA is not set 82# CONFIG_MIPS_MALTA is not set
83# CONFIG_MIPS_SEAD is not set
84# CONFIG_MIPS_SIM is not set
85CONFIG_MOMENCO_JAGUAR_ATX=y
66# CONFIG_MOMENCO_OCELOT is not set 86# CONFIG_MOMENCO_OCELOT is not set
67# CONFIG_MOMENCO_OCELOT_G is not set
68# CONFIG_MOMENCO_OCELOT_C is not set
69# CONFIG_MOMENCO_OCELOT_3 is not set 87# CONFIG_MOMENCO_OCELOT_3 is not set
70CONFIG_MOMENCO_JAGUAR_ATX=y 88# CONFIG_MOMENCO_OCELOT_C is not set
71CONFIG_JAGUAR_DMALOW=y 89# CONFIG_MOMENCO_OCELOT_G is not set
72# CONFIG_PMC_YOSEMITE is not set 90# CONFIG_MIPS_XXS1500 is not set
91# CONFIG_PNX8550_V2PCI is not set
92# CONFIG_PNX8550_JBS is not set
93# CONFIG_DDB5074 is not set
73# CONFIG_DDB5476 is not set 94# CONFIG_DDB5476 is not set
74# CONFIG_DDB5477 is not set 95# CONFIG_DDB5477 is not set
75# CONFIG_NEC_OSPREY is not set 96# CONFIG_MACH_VR41XX is not set
97# CONFIG_PMC_YOSEMITE is not set
98# CONFIG_QEMU is not set
76# CONFIG_SGI_IP22 is not set 99# CONFIG_SGI_IP22 is not set
77# CONFIG_SOC_AU1X00 is not set 100# CONFIG_SGI_IP27 is not set
101# CONFIG_SGI_IP32 is not set
102# CONFIG_SIBYTE_BIGSUR is not set
103# CONFIG_SIBYTE_SWARM is not set
104# CONFIG_SIBYTE_SENTOSA is not set
105# CONFIG_SIBYTE_RHONE is not set
106# CONFIG_SIBYTE_CARMEL is not set
107# CONFIG_SIBYTE_PTSWARM is not set
108# CONFIG_SIBYTE_LITTLESUR is not set
109# CONFIG_SIBYTE_CRHINE is not set
110# CONFIG_SIBYTE_CRHONE is not set
78# CONFIG_SNI_RM200_PCI is not set 111# CONFIG_SNI_RM200_PCI is not set
112# CONFIG_TOSHIBA_JMR3927 is not set
79# CONFIG_TOSHIBA_RBTX4927 is not set 113# CONFIG_TOSHIBA_RBTX4927 is not set
114# CONFIG_TOSHIBA_RBTX4938 is not set
115CONFIG_JAGUAR_DMALOW=y
80CONFIG_RWSEM_GENERIC_SPINLOCK=y 116CONFIG_RWSEM_GENERIC_SPINLOCK=y
81CONFIG_GENERIC_CALIBRATE_DELAY=y 117CONFIG_GENERIC_CALIBRATE_DELAY=y
82CONFIG_HAVE_DEC_LOCK=y
83CONFIG_DMA_NONCOHERENT=y 118CONFIG_DMA_NONCOHERENT=y
84CONFIG_DMA_NEED_PCI_MAP_STATE=y 119CONFIG_DMA_NEED_PCI_MAP_STATE=y
85CONFIG_LIMITED_DMA=y 120CONFIG_LIMITED_DMA=y
121CONFIG_CPU_BIG_ENDIAN=y
86# CONFIG_CPU_LITTLE_ENDIAN is not set 122# CONFIG_CPU_LITTLE_ENDIAN is not set
123CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
87CONFIG_IRQ_CPU=y 124CONFIG_IRQ_CPU=y
88CONFIG_IRQ_CPU_RM7K=y 125CONFIG_IRQ_CPU_RM7K=y
89CONFIG_IRQ_MV64340=y 126CONFIG_IRQ_MV64340=y
@@ -95,8 +132,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
95# 132#
96# CPU selection 133# CPU selection
97# 134#
98# CONFIG_CPU_MIPS32 is not set 135# CONFIG_CPU_MIPS32_R1 is not set
99# CONFIG_CPU_MIPS64 is not set 136# CONFIG_CPU_MIPS32_R2 is not set
137# CONFIG_CPU_MIPS64_R1 is not set
138# CONFIG_CPU_MIPS64_R2 is not set
100# CONFIG_CPU_R3000 is not set 139# CONFIG_CPU_R3000 is not set
101# CONFIG_CPU_TX39XX is not set 140# CONFIG_CPU_TX39XX is not set
102# CONFIG_CPU_VR41XX is not set 141# CONFIG_CPU_VR41XX is not set
@@ -112,6 +151,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
112# CONFIG_CPU_RM7000 is not set 151# CONFIG_CPU_RM7000 is not set
113CONFIG_CPU_RM9000=y 152CONFIG_CPU_RM9000=y
114# CONFIG_CPU_SB1 is not set 153# CONFIG_CPU_SB1 is not set
154CONFIG_SYS_HAS_CPU_RM9000=y
155CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
156CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
157CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
158CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
159
160#
161# Kernel type
162#
163CONFIG_32BIT=y
164# CONFIG_64BIT is not set
115CONFIG_PAGE_SIZE_4KB=y 165CONFIG_PAGE_SIZE_4KB=y
116# CONFIG_PAGE_SIZE_8KB is not set 166# CONFIG_PAGE_SIZE_8KB is not set
117# CONFIG_PAGE_SIZE_16KB is not set 167# CONFIG_PAGE_SIZE_16KB is not set
@@ -119,13 +169,24 @@ CONFIG_PAGE_SIZE_4KB=y
119CONFIG_BOARD_SCACHE=y 169CONFIG_BOARD_SCACHE=y
120CONFIG_RM7000_CPU_SCACHE=y 170CONFIG_RM7000_CPU_SCACHE=y
121CONFIG_CPU_HAS_PREFETCH=y 171CONFIG_CPU_HAS_PREFETCH=y
172# CONFIG_MIPS_MT is not set
122# CONFIG_64BIT_PHYS_ADDR is not set 173# CONFIG_64BIT_PHYS_ADDR is not set
123# CONFIG_CPU_ADVANCED is not set 174# CONFIG_CPU_ADVANCED is not set
124CONFIG_CPU_HAS_LLSC=y 175CONFIG_CPU_HAS_LLSC=y
125CONFIG_CPU_HAS_LLDSCD=y 176CONFIG_CPU_HAS_LLDSCD=y
126CONFIG_CPU_HAS_SYNC=y 177CONFIG_CPU_HAS_SYNC=y
178CONFIG_GENERIC_HARDIRQS=y
179CONFIG_GENERIC_IRQ_PROBE=y
127CONFIG_HIGHMEM=y 180CONFIG_HIGHMEM=y
181CONFIG_CPU_SUPPORTS_HIGHMEM=y
182CONFIG_SYS_SUPPORTS_HIGHMEM=y
183CONFIG_ARCH_FLATMEM_ENABLE=y
184CONFIG_FLATMEM=y
185CONFIG_FLAT_NODE_MEM_MAP=y
186# CONFIG_SPARSEMEM_STATIC is not set
128# CONFIG_SMP is not set 187# CONFIG_SMP is not set
188CONFIG_PREEMPT_NONE=y
189# CONFIG_PREEMPT_VOLUNTARY is not set
129# CONFIG_PREEMPT is not set 190# CONFIG_PREEMPT is not set
130 191
131# 192#
@@ -134,7 +195,6 @@ CONFIG_HIGHMEM=y
134CONFIG_HW_HAS_PCI=y 195CONFIG_HW_HAS_PCI=y
135CONFIG_PCI=y 196CONFIG_PCI=y
136CONFIG_PCI_LEGACY_PROC=y 197CONFIG_PCI_LEGACY_PROC=y
137CONFIG_PCI_NAMES=y
138CONFIG_MMU=y 198CONFIG_MMU=y
139 199
140# 200#
@@ -143,10 +203,6 @@ CONFIG_MMU=y
143# CONFIG_PCCARD is not set 203# CONFIG_PCCARD is not set
144 204
145# 205#
146# PC-card bridges
147#
148
149#
150# PCI Hotplug Support 206# PCI Hotplug Support
151# 207#
152 208
@@ -158,6 +214,68 @@ CONFIG_BINFMT_ELF=y
158CONFIG_TRAD_SIGNALS=y 214CONFIG_TRAD_SIGNALS=y
159 215
160# 216#
217# Networking
218#
219CONFIG_NET=y
220
221#
222# Networking options
223#
224# CONFIG_PACKET is not set
225CONFIG_UNIX=y
226CONFIG_XFRM=y
227CONFIG_XFRM_USER=m
228# CONFIG_NET_KEY is not set
229CONFIG_INET=y
230# CONFIG_IP_MULTICAST is not set
231# CONFIG_IP_ADVANCED_ROUTER is not set
232CONFIG_IP_FIB_HASH=y
233CONFIG_IP_PNP=y
234# CONFIG_IP_PNP_DHCP is not set
235CONFIG_IP_PNP_BOOTP=y
236# CONFIG_IP_PNP_RARP is not set
237# CONFIG_NET_IPIP is not set
238# CONFIG_NET_IPGRE is not set
239# CONFIG_SYN_COOKIES is not set
240# CONFIG_INET_AH is not set
241# CONFIG_INET_ESP is not set
242# CONFIG_INET_IPCOMP is not set
243CONFIG_INET_TUNNEL=m
244CONFIG_INET_DIAG=y
245CONFIG_INET_TCP_DIAG=y
246# CONFIG_TCP_CONG_ADVANCED is not set
247CONFIG_TCP_CONG_BIC=y
248CONFIG_IPV6=m
249CONFIG_IPV6_PRIVACY=y
250CONFIG_INET6_AH=m
251CONFIG_INET6_ESP=m
252CONFIG_INET6_IPCOMP=m
253CONFIG_INET6_TUNNEL=m
254CONFIG_IPV6_TUNNEL=m
255# CONFIG_NETFILTER is not set
256# CONFIG_BRIDGE is not set
257# CONFIG_VLAN_8021Q is not set
258# CONFIG_DECNET is not set
259# CONFIG_LLC2 is not set
260# CONFIG_IPX is not set
261# CONFIG_ATALK is not set
262# CONFIG_NET_SCHED is not set
263# CONFIG_NET_CLS_ROUTE is not set
264
265#
266# Network testing
267#
268# CONFIG_NET_PKTGEN is not set
269# CONFIG_HAMRADIO is not set
270# CONFIG_IRDA is not set
271# CONFIG_BT is not set
272CONFIG_IEEE80211=m
273# CONFIG_IEEE80211_DEBUG is not set
274CONFIG_IEEE80211_CRYPT_WEP=m
275CONFIG_IEEE80211_CRYPT_CCMP=m
276CONFIG_IEEE80211_CRYPT_TKIP=m
277
278#
161# Device Drivers 279# Device Drivers
162# 280#
163 281
@@ -166,7 +284,12 @@ CONFIG_TRAD_SIGNALS=y
166# 284#
167CONFIG_STANDALONE=y 285CONFIG_STANDALONE=y
168CONFIG_PREVENT_FIRMWARE_BUILD=y 286CONFIG_PREVENT_FIRMWARE_BUILD=y
169# CONFIG_FW_LOADER is not set 287CONFIG_FW_LOADER=m
288
289#
290# Connector - unified userspace <-> kernelspace linker
291#
292CONFIG_CONNECTOR=m
170 293
171# 294#
172# Memory Technology Devices (MTD) 295# Memory Technology Devices (MTD)
@@ -185,7 +308,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
185# 308#
186# Block devices 309# Block devices
187# 310#
188# CONFIG_BLK_DEV_FD is not set
189# CONFIG_BLK_CPQ_DA is not set 311# CONFIG_BLK_CPQ_DA is not set
190# CONFIG_BLK_CPQ_CISS_DA is not set 312# CONFIG_BLK_CPQ_CISS_DA is not set
191# CONFIG_BLK_DEV_DAC960 is not set 313# CONFIG_BLK_DEV_DAC960 is not set
@@ -195,7 +317,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
195# CONFIG_BLK_DEV_SX8 is not set 317# CONFIG_BLK_DEV_SX8 is not set
196# CONFIG_BLK_DEV_RAM is not set 318# CONFIG_BLK_DEV_RAM is not set
197CONFIG_BLK_DEV_RAM_COUNT=16 319CONFIG_BLK_DEV_RAM_COUNT=16
198CONFIG_INITRAMFS_SOURCE=""
199# CONFIG_LBD is not set 320# CONFIG_LBD is not set
200CONFIG_CDROM_PKTCDVD=m 321CONFIG_CDROM_PKTCDVD=m
201CONFIG_CDROM_PKTCDVD_BUFFERS=8 322CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -218,6 +339,7 @@ CONFIG_ATA_OVER_ETH=m
218# 339#
219# SCSI device support 340# SCSI device support
220# 341#
342CONFIG_RAID_ATTRS=m
221# CONFIG_SCSI is not set 343# CONFIG_SCSI is not set
222 344
223# 345#
@@ -228,6 +350,7 @@ CONFIG_ATA_OVER_ETH=m
228# 350#
229# Fusion MPT device support 351# Fusion MPT device support
230# 352#
353# CONFIG_FUSION is not set
231 354
232# 355#
233# IEEE 1394 (FireWire) support 356# IEEE 1394 (FireWire) support
@@ -240,58 +363,8 @@ CONFIG_ATA_OVER_ETH=m
240# CONFIG_I2O is not set 363# CONFIG_I2O is not set
241 364
242# 365#
243# Networking support 366# Network device support
244# 367#
245CONFIG_NET=y
246
247#
248# Networking options
249#
250# CONFIG_PACKET is not set
251# CONFIG_NETLINK_DEV is not set
252CONFIG_UNIX=y
253# CONFIG_NET_KEY is not set
254CONFIG_INET=y
255# CONFIG_IP_MULTICAST is not set
256# CONFIG_IP_ADVANCED_ROUTER is not set
257CONFIG_IP_PNP=y
258# CONFIG_IP_PNP_DHCP is not set
259CONFIG_IP_PNP_BOOTP=y
260# CONFIG_IP_PNP_RARP is not set
261# CONFIG_NET_IPIP is not set
262# CONFIG_NET_IPGRE is not set
263# CONFIG_SYN_COOKIES is not set
264# CONFIG_INET_AH is not set
265# CONFIG_INET_ESP is not set
266# CONFIG_INET_IPCOMP is not set
267CONFIG_INET_TUNNEL=m
268CONFIG_IP_TCPDIAG=m
269# CONFIG_IP_TCPDIAG_IPV6 is not set
270# CONFIG_NETFILTER is not set
271CONFIG_XFRM=y
272CONFIG_XFRM_USER=m
273# CONFIG_BRIDGE is not set
274# CONFIG_VLAN_8021Q is not set
275# CONFIG_DECNET is not set
276# CONFIG_LLC2 is not set
277# CONFIG_IPX is not set
278# CONFIG_ATALK is not set
279
280#
281# QoS and/or fair queueing
282#
283# CONFIG_NET_SCHED is not set
284# CONFIG_NET_CLS_ROUTE is not set
285
286#
287# Network testing
288#
289# CONFIG_NET_PKTGEN is not set
290# CONFIG_NETPOLL is not set
291# CONFIG_NET_POLL_CONTROLLER is not set
292# CONFIG_HAMRADIO is not set
293# CONFIG_IRDA is not set
294# CONFIG_BT is not set
295CONFIG_NETDEVICES=y 368CONFIG_NETDEVICES=y
296# CONFIG_DUMMY is not set 369# CONFIG_DUMMY is not set
297# CONFIG_BONDING is not set 370# CONFIG_BONDING is not set
@@ -304,6 +377,21 @@ CONFIG_NETDEVICES=y
304# CONFIG_ARCNET is not set 377# CONFIG_ARCNET is not set
305 378
306# 379#
380# PHY device support
381#
382CONFIG_PHYLIB=m
383CONFIG_PHYCONTROL=y
384
385#
386# MII PHY device drivers
387#
388CONFIG_MARVELL_PHY=m
389CONFIG_DAVICOM_PHY=m
390CONFIG_QSEMI_PHY=m
391CONFIG_LXT_PHY=m
392CONFIG_CICADA_PHY=m
393
394#
307# Ethernet (10 or 100Mbit) 395# Ethernet (10 or 100Mbit)
308# 396#
309CONFIG_NET_ETHERNET=y 397CONFIG_NET_ETHERNET=y
@@ -343,9 +431,11 @@ CONFIG_EEPRO100=y
343# CONFIG_NS83820 is not set 431# CONFIG_NS83820 is not set
344# CONFIG_HAMACHI is not set 432# CONFIG_HAMACHI is not set
345# CONFIG_R8169 is not set 433# CONFIG_R8169 is not set
434# CONFIG_SIS190 is not set
346# CONFIG_SK98LIN is not set 435# CONFIG_SK98LIN is not set
347# CONFIG_VIA_VELOCITY is not set 436# CONFIG_VIA_VELOCITY is not set
348# CONFIG_TIGON3 is not set 437# CONFIG_TIGON3 is not set
438# CONFIG_BNX2 is not set
349CONFIG_MV643XX_ETH=y 439CONFIG_MV643XX_ETH=y
350CONFIG_MV643XX_ETH_0=y 440CONFIG_MV643XX_ETH_0=y
351CONFIG_MV643XX_ETH_1=y 441CONFIG_MV643XX_ETH_1=y
@@ -354,6 +444,7 @@ CONFIG_MV643XX_ETH_2=y
354# 444#
355# Ethernet (10000 Mbit) 445# Ethernet (10000 Mbit)
356# 446#
447# CONFIG_CHELSIO_T1 is not set
357# CONFIG_IXGB is not set 448# CONFIG_IXGB is not set
358# CONFIG_S2IO is not set 449# CONFIG_S2IO is not set
359 450
@@ -366,6 +457,8 @@ CONFIG_MV643XX_ETH_2=y
366# Wireless LAN (non-hamradio) 457# Wireless LAN (non-hamradio)
367# 458#
368# CONFIG_NET_RADIO is not set 459# CONFIG_NET_RADIO is not set
460# CONFIG_IPW_DEBUG is not set
461CONFIG_IPW2200=m
369 462
370# 463#
371# Wan interfaces 464# Wan interfaces
@@ -374,6 +467,8 @@ CONFIG_MV643XX_ETH_2=y
374# CONFIG_FDDI is not set 467# CONFIG_FDDI is not set
375# CONFIG_PPP is not set 468# CONFIG_PPP is not set
376# CONFIG_SLIP is not set 469# CONFIG_SLIP is not set
470# CONFIG_NETPOLL is not set
471# CONFIG_NET_POLL_CONTROLLER is not set
377 472
378# 473#
379# ISDN subsystem 474# ISDN subsystem
@@ -391,20 +486,10 @@ CONFIG_MV643XX_ETH_2=y
391# CONFIG_INPUT is not set 486# CONFIG_INPUT is not set
392 487
393# 488#
394# Userland interfaces 489# Hardware I/O ports
395#
396
397#
398# Input I/O drivers
399# 490#
400# CONFIG_GAMEPORT is not set
401CONFIG_SOUND_GAMEPORT=y
402# CONFIG_SERIO is not set 491# CONFIG_SERIO is not set
403# CONFIG_SERIO_I8042 is not set 492# CONFIG_GAMEPORT is not set
404
405#
406# Input Device Drivers
407#
408 493
409# 494#
410# Character devices 495# Character devices
@@ -425,6 +510,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
425# 510#
426CONFIG_SERIAL_CORE=y 511CONFIG_SERIAL_CORE=y
427CONFIG_SERIAL_CORE_CONSOLE=y 512CONFIG_SERIAL_CORE_CONSOLE=y
513# CONFIG_SERIAL_JSM is not set
428CONFIG_UNIX98_PTYS=y 514CONFIG_UNIX98_PTYS=y
429CONFIG_LEGACY_PTYS=y 515CONFIG_LEGACY_PTYS=y
430CONFIG_LEGACY_PTY_COUNT=256 516CONFIG_LEGACY_PTY_COUNT=256
@@ -451,6 +537,10 @@ CONFIG_LEGACY_PTY_COUNT=256
451# CONFIG_RAW_DRIVER is not set 537# CONFIG_RAW_DRIVER is not set
452 538
453# 539#
540# TPM devices
541#
542
543#
454# I2C support 544# I2C support
455# 545#
456# CONFIG_I2C is not set 546# CONFIG_I2C is not set
@@ -461,10 +551,20 @@ CONFIG_LEGACY_PTY_COUNT=256
461# CONFIG_W1 is not set 551# CONFIG_W1 is not set
462 552
463# 553#
554# Hardware Monitoring support
555#
556# CONFIG_HWMON is not set
557# CONFIG_HWMON_VID is not set
558
559#
464# Misc devices 560# Misc devices
465# 561#
466 562
467# 563#
564# Multimedia Capabilities Port drivers
565#
566
567#
468# Multimedia devices 568# Multimedia devices
469# 569#
470# CONFIG_VIDEO_DEV is not set 570# CONFIG_VIDEO_DEV is not set
@@ -478,7 +578,6 @@ CONFIG_LEGACY_PTY_COUNT=256
478# Graphics support 578# Graphics support
479# 579#
480# CONFIG_FB is not set 580# CONFIG_FB is not set
481# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
482 581
483# 582#
484# Sound 583# Sound
@@ -488,13 +587,9 @@ CONFIG_LEGACY_PTY_COUNT=256
488# 587#
489# USB support 588# USB support
490# 589#
491# CONFIG_USB is not set
492CONFIG_USB_ARCH_HAS_HCD=y 590CONFIG_USB_ARCH_HAS_HCD=y
493CONFIG_USB_ARCH_HAS_OHCI=y 591CONFIG_USB_ARCH_HAS_OHCI=y
494 592# CONFIG_USB is not set
495#
496# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
497#
498 593
499# 594#
500# USB Gadget Support 595# USB Gadget Support
@@ -512,6 +607,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y
512# CONFIG_INFINIBAND is not set 607# CONFIG_INFINIBAND is not set
513 608
514# 609#
610# SN Devices
611#
612
613#
515# File systems 614# File systems
516# 615#
517# CONFIG_EXT2_FS is not set 616# CONFIG_EXT2_FS is not set
@@ -519,13 +618,16 @@ CONFIG_USB_ARCH_HAS_OHCI=y
519# CONFIG_JBD is not set 618# CONFIG_JBD is not set
520# CONFIG_REISERFS_FS is not set 619# CONFIG_REISERFS_FS is not set
521# CONFIG_JFS_FS is not set 620# CONFIG_JFS_FS is not set
621# CONFIG_FS_POSIX_ACL is not set
522# CONFIG_XFS_FS is not set 622# CONFIG_XFS_FS is not set
523# CONFIG_MINIX_FS is not set 623# CONFIG_MINIX_FS is not set
524# CONFIG_ROMFS_FS is not set 624# CONFIG_ROMFS_FS is not set
625CONFIG_INOTIFY=y
525# CONFIG_QUOTA is not set 626# CONFIG_QUOTA is not set
526CONFIG_DNOTIFY=y 627CONFIG_DNOTIFY=y
527# CONFIG_AUTOFS_FS is not set 628# CONFIG_AUTOFS_FS is not set
528# CONFIG_AUTOFS4_FS is not set 629# CONFIG_AUTOFS4_FS is not set
630CONFIG_FUSE_FS=m
529 631
530# 632#
531# CD-ROM/DVD Filesystems 633# CD-ROM/DVD Filesystems
@@ -546,10 +648,10 @@ CONFIG_DNOTIFY=y
546CONFIG_PROC_FS=y 648CONFIG_PROC_FS=y
547CONFIG_PROC_KCORE=y 649CONFIG_PROC_KCORE=y
548CONFIG_SYSFS=y 650CONFIG_SYSFS=y
549# CONFIG_DEVPTS_FS_XATTR is not set
550# CONFIG_TMPFS is not set 651# CONFIG_TMPFS is not set
551# CONFIG_HUGETLB_PAGE is not set 652# CONFIG_HUGETLB_PAGE is not set
552CONFIG_RAMFS=y 653CONFIG_RAMFS=y
654CONFIG_RELAYFS_FS=m
553 655
554# 656#
555# Miscellaneous filesystems 657# Miscellaneous filesystems
@@ -570,7 +672,7 @@ CONFIG_NFS_FS=y
570# CONFIG_NFSD is not set 672# CONFIG_NFSD is not set
571CONFIG_ROOT_NFS=y 673CONFIG_ROOT_NFS=y
572CONFIG_LOCKD=y 674CONFIG_LOCKD=y
573# CONFIG_EXPORTFS is not set 675CONFIG_NFS_COMMON=y
574CONFIG_SUNRPC=y 676CONFIG_SUNRPC=y
575# CONFIG_SMB_FS is not set 677# CONFIG_SMB_FS is not set
576# CONFIG_CIFS is not set 678# CONFIG_CIFS is not set
@@ -591,7 +693,9 @@ CONFIG_MSDOS_PARTITION=y
591# 693#
592# Kernel hacking 694# Kernel hacking
593# 695#
696# CONFIG_PRINTK_TIME is not set
594# CONFIG_DEBUG_KERNEL is not set 697# CONFIG_DEBUG_KERNEL is not set
698CONFIG_LOG_BUF_SHIFT=14
595CONFIG_CROSSCOMPILE=y 699CONFIG_CROSSCOMPILE=y
596CONFIG_CMDLINE="" 700CONFIG_CMDLINE=""
597 701
@@ -605,7 +709,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
605# 709#
606# Cryptographic options 710# Cryptographic options
607# 711#
608# CONFIG_CRYPTO is not set 712CONFIG_CRYPTO=y
713CONFIG_CRYPTO_HMAC=y
714CONFIG_CRYPTO_NULL=m
715CONFIG_CRYPTO_MD4=m
716CONFIG_CRYPTO_MD5=m
717CONFIG_CRYPTO_SHA1=m
718CONFIG_CRYPTO_SHA256=m
719CONFIG_CRYPTO_SHA512=m
720CONFIG_CRYPTO_WP512=m
721CONFIG_CRYPTO_TGR192=m
722CONFIG_CRYPTO_DES=m
723CONFIG_CRYPTO_BLOWFISH=m
724CONFIG_CRYPTO_TWOFISH=m
725CONFIG_CRYPTO_SERPENT=m
726CONFIG_CRYPTO_AES=m
727CONFIG_CRYPTO_CAST5=m
728CONFIG_CRYPTO_CAST6=m
729CONFIG_CRYPTO_TEA=m
730CONFIG_CRYPTO_ARC4=m
731CONFIG_CRYPTO_KHAZAD=m
732CONFIG_CRYPTO_ANUBIS=m
733CONFIG_CRYPTO_DEFLATE=m
734CONFIG_CRYPTO_MICHAEL_MIC=m
735CONFIG_CRYPTO_CRC32C=m
736# CONFIG_CRYPTO_TEST is not set
609 737
610# 738#
611# Hardware crypto devices 739# Hardware crypto devices
@@ -615,7 +743,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
615# Library routines 743# Library routines
616# 744#
617# CONFIG_CRC_CCITT is not set 745# CONFIG_CRC_CCITT is not set
618# CONFIG_CRC32 is not set 746CONFIG_CRC16=m
619# CONFIG_LIBCRC32C is not set 747CONFIG_CRC32=m
620CONFIG_GENERIC_HARDIRQS=y 748CONFIG_LIBCRC32C=m
621CONFIG_GENERIC_IRQ_PROBE=y 749CONFIG_ZLIB_INFLATE=m
750CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index da5d9ee2ecce..9a728c2d8fd5 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:06 2005 4# Thu Oct 20 22:26:17 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -50,40 +53,68 @@ CONFIG_CC_ALIGN_JUMPS=0
50# 53#
51# Machine selection 54# Machine selection
52# 55#
53# CONFIG_MACH_JAZZ is not set 56# CONFIG_MIPS_MTX1 is not set
54# CONFIG_MACH_VR41XX is not set 57# CONFIG_MIPS_BOSPORUS is not set
55CONFIG_TOSHIBA_JMR3927=y 58# CONFIG_MIPS_PB1000 is not set
59# CONFIG_MIPS_PB1100 is not set
60# CONFIG_MIPS_PB1500 is not set
61# CONFIG_MIPS_PB1550 is not set
62# CONFIG_MIPS_PB1200 is not set
63# CONFIG_MIPS_DB1000 is not set
64# CONFIG_MIPS_DB1100 is not set
65# CONFIG_MIPS_DB1500 is not set
66# CONFIG_MIPS_DB1550 is not set
67# CONFIG_MIPS_DB1200 is not set
68# CONFIG_MIPS_MIRAGE is not set
56# CONFIG_MIPS_COBALT is not set 69# CONFIG_MIPS_COBALT is not set
57# CONFIG_MACH_DECSTATION is not set 70# CONFIG_MACH_DECSTATION is not set
58# CONFIG_MIPS_EV64120 is not set 71# CONFIG_MIPS_EV64120 is not set
59# CONFIG_MIPS_EV96100 is not set 72# CONFIG_MIPS_EV96100 is not set
60# CONFIG_MIPS_IVR is not set 73# CONFIG_MIPS_IVR is not set
61# CONFIG_LASAT is not set
62# CONFIG_MIPS_ITE8172 is not set 74# CONFIG_MIPS_ITE8172 is not set
75# CONFIG_MACH_JAZZ is not set
76# CONFIG_LASAT is not set
63# CONFIG_MIPS_ATLAS is not set 77# CONFIG_MIPS_ATLAS is not set
64# CONFIG_MIPS_MALTA is not set 78# CONFIG_MIPS_MALTA is not set
65# CONFIG_MIPS_SEAD is not set 79# CONFIG_MIPS_SEAD is not set
80# CONFIG_MIPS_SIM is not set
81# CONFIG_MOMENCO_JAGUAR_ATX is not set
66# CONFIG_MOMENCO_OCELOT is not set 82# CONFIG_MOMENCO_OCELOT is not set
67# CONFIG_MOMENCO_OCELOT_G is not set
68# CONFIG_MOMENCO_OCELOT_C is not set
69# CONFIG_MOMENCO_OCELOT_3 is not set 83# CONFIG_MOMENCO_OCELOT_3 is not set
70# CONFIG_MOMENCO_JAGUAR_ATX is not set 84# CONFIG_MOMENCO_OCELOT_C is not set
71# CONFIG_PMC_YOSEMITE is not set 85# CONFIG_MOMENCO_OCELOT_G is not set
86# CONFIG_MIPS_XXS1500 is not set
87# CONFIG_PNX8550_V2PCI is not set
88# CONFIG_PNX8550_JBS is not set
72# CONFIG_DDB5074 is not set 89# CONFIG_DDB5074 is not set
73# CONFIG_DDB5476 is not set 90# CONFIG_DDB5476 is not set
74# CONFIG_DDB5477 is not set 91# CONFIG_DDB5477 is not set
75# CONFIG_NEC_OSPREY is not set 92# CONFIG_MACH_VR41XX is not set
93# CONFIG_PMC_YOSEMITE is not set
94# CONFIG_QEMU is not set
76# CONFIG_SGI_IP22 is not set 95# CONFIG_SGI_IP22 is not set
77# CONFIG_SOC_AU1X00 is not set 96# CONFIG_SGI_IP27 is not set
78# CONFIG_SIBYTE_SB1xxx_SOC is not set 97# CONFIG_SGI_IP32 is not set
98# CONFIG_SIBYTE_BIGSUR is not set
99# CONFIG_SIBYTE_SWARM is not set
100# CONFIG_SIBYTE_SENTOSA is not set
101# CONFIG_SIBYTE_RHONE is not set
102# CONFIG_SIBYTE_CARMEL is not set
103# CONFIG_SIBYTE_PTSWARM is not set
104# CONFIG_SIBYTE_LITTLESUR is not set
105# CONFIG_SIBYTE_CRHINE is not set
106# CONFIG_SIBYTE_CRHONE is not set
79# CONFIG_SNI_RM200_PCI is not set 107# CONFIG_SNI_RM200_PCI is not set
108CONFIG_TOSHIBA_JMR3927=y
80# CONFIG_TOSHIBA_RBTX4927 is not set 109# CONFIG_TOSHIBA_RBTX4927 is not set
110# CONFIG_TOSHIBA_RBTX4938 is not set
81CONFIG_RWSEM_GENERIC_SPINLOCK=y 111CONFIG_RWSEM_GENERIC_SPINLOCK=y
82CONFIG_GENERIC_CALIBRATE_DELAY=y 112CONFIG_GENERIC_CALIBRATE_DELAY=y
83CONFIG_HAVE_DEC_LOCK=y
84CONFIG_DMA_NONCOHERENT=y 113CONFIG_DMA_NONCOHERENT=y
85CONFIG_DMA_NEED_PCI_MAP_STATE=y 114CONFIG_DMA_NEED_PCI_MAP_STATE=y
115CONFIG_CPU_BIG_ENDIAN=y
86# CONFIG_CPU_LITTLE_ENDIAN is not set 116# CONFIG_CPU_LITTLE_ENDIAN is not set
117CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
87CONFIG_MIPS_TX3927=y 118CONFIG_MIPS_TX3927=y
88CONFIG_SWAP_IO_SPACE=y 119CONFIG_SWAP_IO_SPACE=y
89CONFIG_MIPS_L1_CACHE_SHIFT=5 120CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -92,8 +123,10 @@ CONFIG_TOSHIBA_BOARDS=y
92# 123#
93# CPU selection 124# CPU selection
94# 125#
95# CONFIG_CPU_MIPS32 is not set 126# CONFIG_CPU_MIPS32_R1 is not set
96# CONFIG_CPU_MIPS64 is not set 127# CONFIG_CPU_MIPS32_R2 is not set
128# CONFIG_CPU_MIPS64_R1 is not set
129# CONFIG_CPU_MIPS64_R2 is not set
97# CONFIG_CPU_R3000 is not set 130# CONFIG_CPU_R3000 is not set
98CONFIG_CPU_TX39XX=y 131CONFIG_CPU_TX39XX=y
99# CONFIG_CPU_VR41XX is not set 132# CONFIG_CPU_VR41XX is not set
@@ -109,12 +142,34 @@ CONFIG_CPU_TX39XX=y
109# CONFIG_CPU_RM7000 is not set 142# CONFIG_CPU_RM7000 is not set
110# CONFIG_CPU_RM9000 is not set 143# CONFIG_CPU_RM9000 is not set
111# CONFIG_CPU_SB1 is not set 144# CONFIG_CPU_SB1 is not set
145CONFIG_SYS_HAS_CPU_TX39XX=y
146CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
147CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
148
149#
150# Kernel type
151#
152CONFIG_32BIT=y
153# CONFIG_64BIT is not set
112CONFIG_PAGE_SIZE_4KB=y 154CONFIG_PAGE_SIZE_4KB=y
113# CONFIG_PAGE_SIZE_8KB is not set 155# CONFIG_PAGE_SIZE_8KB is not set
114# CONFIG_PAGE_SIZE_16KB is not set 156# CONFIG_PAGE_SIZE_16KB is not set
115# CONFIG_PAGE_SIZE_64KB is not set 157# CONFIG_PAGE_SIZE_64KB is not set
158# CONFIG_MIPS_MT is not set
116# CONFIG_CPU_ADVANCED is not set 159# CONFIG_CPU_ADVANCED is not set
117CONFIG_CPU_HAS_SYNC=y 160CONFIG_CPU_HAS_SYNC=y
161CONFIG_GENERIC_HARDIRQS=y
162CONFIG_GENERIC_IRQ_PROBE=y
163CONFIG_ARCH_FLATMEM_ENABLE=y
164CONFIG_SELECT_MEMORY_MODEL=y
165CONFIG_FLATMEM_MANUAL=y
166# CONFIG_DISCONTIGMEM_MANUAL is not set
167# CONFIG_SPARSEMEM_MANUAL is not set
168CONFIG_FLATMEM=y
169CONFIG_FLAT_NODE_MEM_MAP=y
170# CONFIG_SPARSEMEM_STATIC is not set
171CONFIG_PREEMPT_NONE=y
172# CONFIG_PREEMPT_VOLUNTARY is not set
118# CONFIG_PREEMPT is not set 173# CONFIG_PREEMPT is not set
119CONFIG_RTC_DS1742=y 174CONFIG_RTC_DS1742=y
120 175
@@ -124,7 +179,6 @@ CONFIG_RTC_DS1742=y
124CONFIG_HW_HAS_PCI=y 179CONFIG_HW_HAS_PCI=y
125CONFIG_PCI=y 180CONFIG_PCI=y
126CONFIG_PCI_LEGACY_PROC=y 181CONFIG_PCI_LEGACY_PROC=y
127CONFIG_PCI_NAMES=y
128CONFIG_MMU=y 182CONFIG_MMU=y
129 183
130# 184#
@@ -133,10 +187,6 @@ CONFIG_MMU=y
133# CONFIG_PCCARD is not set 187# CONFIG_PCCARD is not set
134 188
135# 189#
136# PC-card bridges
137#
138
139#
140# PCI Hotplug Support 190# PCI Hotplug Support
141# 191#
142# CONFIG_HOTPLUG_PCI is not set 192# CONFIG_HOTPLUG_PCI is not set
@@ -149,6 +199,80 @@ CONFIG_BINFMT_ELF=y
149CONFIG_TRAD_SIGNALS=y 199CONFIG_TRAD_SIGNALS=y
150 200
151# 201#
202# Networking
203#
204CONFIG_NET=y
205
206#
207# Networking options
208#
209CONFIG_PACKET=y
210# CONFIG_PACKET_MMAP is not set
211CONFIG_UNIX=y
212CONFIG_XFRM=y
213CONFIG_XFRM_USER=y
214CONFIG_NET_KEY=y
215CONFIG_INET=y
216# CONFIG_IP_MULTICAST is not set
217# CONFIG_IP_ADVANCED_ROUTER is not set
218CONFIG_IP_FIB_HASH=y
219CONFIG_IP_PNP=y
220# CONFIG_IP_PNP_DHCP is not set
221CONFIG_IP_PNP_BOOTP=y
222# CONFIG_IP_PNP_RARP is not set
223# CONFIG_NET_IPIP is not set
224# CONFIG_NET_IPGRE is not set
225# CONFIG_ARPD is not set
226# CONFIG_SYN_COOKIES is not set
227# CONFIG_INET_AH is not set
228# CONFIG_INET_ESP is not set
229# CONFIG_INET_IPCOMP is not set
230CONFIG_INET_TUNNEL=y
231CONFIG_INET_DIAG=y
232CONFIG_INET_TCP_DIAG=y
233# CONFIG_TCP_CONG_ADVANCED is not set
234CONFIG_TCP_CONG_BIC=y
235# CONFIG_IPV6 is not set
236# CONFIG_NETFILTER is not set
237
238#
239# DCCP Configuration (EXPERIMENTAL)
240#
241# CONFIG_IP_DCCP is not set
242
243#
244# SCTP Configuration (EXPERIMENTAL)
245#
246# CONFIG_IP_SCTP is not set
247# CONFIG_ATM is not set
248# CONFIG_BRIDGE is not set
249# CONFIG_VLAN_8021Q is not set
250# CONFIG_DECNET is not set
251# CONFIG_LLC2 is not set
252# CONFIG_IPX is not set
253# CONFIG_ATALK is not set
254# CONFIG_X25 is not set
255# CONFIG_LAPB is not set
256# CONFIG_NET_DIVERT is not set
257# CONFIG_ECONET is not set
258# CONFIG_WAN_ROUTER is not set
259# CONFIG_NET_SCHED is not set
260# CONFIG_NET_CLS_ROUTE is not set
261
262#
263# Network testing
264#
265# CONFIG_NET_PKTGEN is not set
266# CONFIG_HAMRADIO is not set
267# CONFIG_IRDA is not set
268# CONFIG_BT is not set
269CONFIG_IEEE80211=y
270# CONFIG_IEEE80211_DEBUG is not set
271CONFIG_IEEE80211_CRYPT_WEP=y
272CONFIG_IEEE80211_CRYPT_CCMP=y
273CONFIG_IEEE80211_CRYPT_TKIP=y
274
275#
152# Device Drivers 276# Device Drivers
153# 277#
154 278
@@ -157,7 +281,12 @@ CONFIG_TRAD_SIGNALS=y
157# 281#
158CONFIG_STANDALONE=y 282CONFIG_STANDALONE=y
159CONFIG_PREVENT_FIRMWARE_BUILD=y 283CONFIG_PREVENT_FIRMWARE_BUILD=y
160# CONFIG_FW_LOADER is not set 284CONFIG_FW_LOADER=y
285
286#
287# Connector - unified userspace <-> kernelspace linker
288#
289CONFIG_CONNECTOR=y
161 290
162# 291#
163# Memory Technology Devices (MTD) 292# Memory Technology Devices (MTD)
@@ -176,7 +305,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
176# 305#
177# Block devices 306# Block devices
178# 307#
179# CONFIG_BLK_DEV_FD is not set
180# CONFIG_BLK_CPQ_DA is not set 308# CONFIG_BLK_CPQ_DA is not set
181# CONFIG_BLK_CPQ_CISS_DA is not set 309# CONFIG_BLK_CPQ_CISS_DA is not set
182# CONFIG_BLK_DEV_DAC960 is not set 310# CONFIG_BLK_DEV_DAC960 is not set
@@ -187,7 +315,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
187# CONFIG_BLK_DEV_SX8 is not set 315# CONFIG_BLK_DEV_SX8 is not set
188# CONFIG_BLK_DEV_RAM is not set 316# CONFIG_BLK_DEV_RAM is not set
189CONFIG_BLK_DEV_RAM_COUNT=16 317CONFIG_BLK_DEV_RAM_COUNT=16
190CONFIG_INITRAMFS_SOURCE=""
191# CONFIG_LBD is not set 318# CONFIG_LBD is not set
192CONFIG_CDROM_PKTCDVD=y 319CONFIG_CDROM_PKTCDVD=y
193CONFIG_CDROM_PKTCDVD_BUFFERS=8 320CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -210,6 +337,7 @@ CONFIG_ATA_OVER_ETH=y
210# 337#
211# SCSI device support 338# SCSI device support
212# 339#
340CONFIG_RAID_ATTRS=y
213# CONFIG_SCSI is not set 341# CONFIG_SCSI is not set
214 342
215# 343#
@@ -220,6 +348,7 @@ CONFIG_ATA_OVER_ETH=y
220# 348#
221# Fusion MPT device support 349# Fusion MPT device support
222# 350#
351# CONFIG_FUSION is not set
223 352
224# 353#
225# IEEE 1394 (FireWire) support 354# IEEE 1394 (FireWire) support
@@ -232,78 +361,13 @@ CONFIG_ATA_OVER_ETH=y
232# CONFIG_I2O is not set 361# CONFIG_I2O is not set
233 362
234# 363#
235# Networking support 364# Network device support
236#
237CONFIG_NET=y
238
239#
240# Networking options
241#
242CONFIG_PACKET=y
243# CONFIG_PACKET_MMAP is not set
244CONFIG_NETLINK_DEV=y
245CONFIG_UNIX=y
246CONFIG_NET_KEY=y
247CONFIG_INET=y
248# CONFIG_IP_MULTICAST is not set
249# CONFIG_IP_ADVANCED_ROUTER is not set
250CONFIG_IP_PNP=y
251# CONFIG_IP_PNP_DHCP is not set
252CONFIG_IP_PNP_BOOTP=y
253# CONFIG_IP_PNP_RARP is not set
254# CONFIG_NET_IPIP is not set
255# CONFIG_NET_IPGRE is not set
256# CONFIG_ARPD is not set
257# CONFIG_SYN_COOKIES is not set
258# CONFIG_INET_AH is not set
259# CONFIG_INET_ESP is not set
260# CONFIG_INET_IPCOMP is not set
261CONFIG_INET_TUNNEL=y
262CONFIG_IP_TCPDIAG=y
263# CONFIG_IP_TCPDIAG_IPV6 is not set
264# CONFIG_IPV6 is not set
265# CONFIG_NETFILTER is not set
266CONFIG_XFRM=y
267CONFIG_XFRM_USER=y
268
269#
270# SCTP Configuration (EXPERIMENTAL)
271# 365#
272# CONFIG_IP_SCTP is not set
273# CONFIG_ATM is not set
274# CONFIG_BRIDGE is not set
275# CONFIG_VLAN_8021Q is not set
276# CONFIG_DECNET is not set
277# CONFIG_LLC2 is not set
278# CONFIG_IPX is not set
279# CONFIG_ATALK is not set
280# CONFIG_X25 is not set
281# CONFIG_LAPB is not set
282# CONFIG_NET_DIVERT is not set
283# CONFIG_ECONET is not set
284# CONFIG_WAN_ROUTER is not set
285
286#
287# QoS and/or fair queueing
288#
289# CONFIG_NET_SCHED is not set
290# CONFIG_NET_CLS_ROUTE is not set
291
292#
293# Network testing
294#
295# CONFIG_NET_PKTGEN is not set
296# CONFIG_NETPOLL is not set
297# CONFIG_NET_POLL_CONTROLLER is not set
298# CONFIG_HAMRADIO is not set
299# CONFIG_IRDA is not set
300# CONFIG_BT is not set
301CONFIG_NETDEVICES=y 366CONFIG_NETDEVICES=y
302# CONFIG_DUMMY is not set 367# CONFIG_DUMMY is not set
303# CONFIG_BONDING is not set 368# CONFIG_BONDING is not set
304# CONFIG_EQUALIZER is not set 369# CONFIG_EQUALIZER is not set
305# CONFIG_TUN is not set 370# CONFIG_TUN is not set
306# CONFIG_ETHERTAP is not set
307 371
308# 372#
309# ARCnet devices 373# ARCnet devices
@@ -311,6 +375,21 @@ CONFIG_NETDEVICES=y
311# CONFIG_ARCNET is not set 375# CONFIG_ARCNET is not set
312 376
313# 377#
378# PHY device support
379#
380CONFIG_PHYLIB=y
381CONFIG_PHYCONTROL=y
382
383#
384# MII PHY device drivers
385#
386CONFIG_MARVELL_PHY=y
387CONFIG_DAVICOM_PHY=y
388CONFIG_QSEMI_PHY=y
389CONFIG_LXT_PHY=y
390CONFIG_CICADA_PHY=y
391
392#
314# Ethernet (10 or 100Mbit) 393# Ethernet (10 or 100Mbit)
315# 394#
316CONFIG_NET_ETHERNET=y 395CONFIG_NET_ETHERNET=y
@@ -336,12 +415,16 @@ CONFIG_NET_ETHERNET=y
336# CONFIG_HAMACHI is not set 415# CONFIG_HAMACHI is not set
337# CONFIG_YELLOWFIN is not set 416# CONFIG_YELLOWFIN is not set
338# CONFIG_R8169 is not set 417# CONFIG_R8169 is not set
418# CONFIG_SIS190 is not set
419# CONFIG_SKGE is not set
339# CONFIG_SK98LIN is not set 420# CONFIG_SK98LIN is not set
340# CONFIG_TIGON3 is not set 421# CONFIG_TIGON3 is not set
422# CONFIG_BNX2 is not set
341 423
342# 424#
343# Ethernet (10000 Mbit) 425# Ethernet (10000 Mbit)
344# 426#
427# CONFIG_CHELSIO_T1 is not set
345# CONFIG_IXGB is not set 428# CONFIG_IXGB is not set
346# CONFIG_S2IO is not set 429# CONFIG_S2IO is not set
347 430
@@ -354,6 +437,8 @@ CONFIG_NET_ETHERNET=y
354# Wireless LAN (non-hamradio) 437# Wireless LAN (non-hamradio)
355# 438#
356# CONFIG_NET_RADIO is not set 439# CONFIG_NET_RADIO is not set
440# CONFIG_IPW_DEBUG is not set
441CONFIG_IPW2200=y
357 442
358# 443#
359# Wan interfaces 444# Wan interfaces
@@ -365,6 +450,8 @@ CONFIG_NET_ETHERNET=y
365# CONFIG_SLIP is not set 450# CONFIG_SLIP is not set
366# CONFIG_SHAPER is not set 451# CONFIG_SHAPER is not set
367# CONFIG_NETCONSOLE is not set 452# CONFIG_NETCONSOLE is not set
453# CONFIG_NETPOLL is not set
454# CONFIG_NET_POLL_CONTROLLER is not set
368 455
369# 456#
370# ISDN subsystem 457# ISDN subsystem
@@ -394,19 +481,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
394# CONFIG_INPUT_EVBUG is not set 481# CONFIG_INPUT_EVBUG is not set
395 482
396# 483#
397# Input I/O drivers
398#
399# CONFIG_GAMEPORT is not set
400CONFIG_SOUND_GAMEPORT=y
401CONFIG_SERIO=y
402# CONFIG_SERIO_I8042 is not set
403CONFIG_SERIO_SERPORT=y
404# CONFIG_SERIO_CT82C710 is not set
405# CONFIG_SERIO_PCIPS2 is not set
406# CONFIG_SERIO_LIBPS2 is not set
407CONFIG_SERIO_RAW=y
408
409#
410# Input Device Drivers 484# Input Device Drivers
411# 485#
412# CONFIG_INPUT_KEYBOARD is not set 486# CONFIG_INPUT_KEYBOARD is not set
@@ -416,6 +490,17 @@ CONFIG_SERIO_RAW=y
416# CONFIG_INPUT_MISC is not set 490# CONFIG_INPUT_MISC is not set
417 491
418# 492#
493# Hardware I/O ports
494#
495CONFIG_SERIO=y
496# CONFIG_SERIO_I8042 is not set
497CONFIG_SERIO_SERPORT=y
498# CONFIG_SERIO_PCIPS2 is not set
499# CONFIG_SERIO_LIBPS2 is not set
500CONFIG_SERIO_RAW=y
501# CONFIG_GAMEPORT is not set
502
503#
419# Character devices 504# Character devices
420# 505#
421CONFIG_VT=y 506CONFIG_VT=y
@@ -426,11 +511,9 @@ CONFIG_SERIAL_NONSTANDARD=y
426# CONFIG_ROCKETPORT is not set 511# CONFIG_ROCKETPORT is not set
427# CONFIG_CYCLADES is not set 512# CONFIG_CYCLADES is not set
428# CONFIG_DIGIEPCA is not set 513# CONFIG_DIGIEPCA is not set
429# CONFIG_DIGI is not set
430# CONFIG_MOXA_INTELLIO is not set 514# CONFIG_MOXA_INTELLIO is not set
431# CONFIG_MOXA_SMARTIO is not set 515# CONFIG_MOXA_SMARTIO is not set
432# CONFIG_ISI is not set 516# CONFIG_ISI is not set
433# CONFIG_SYNCLINK is not set
434# CONFIG_SYNCLINKMP is not set 517# CONFIG_SYNCLINKMP is not set
435# CONFIG_N_HDLC is not set 518# CONFIG_N_HDLC is not set
436# CONFIG_RISCOM8 is not set 519# CONFIG_RISCOM8 is not set
@@ -438,10 +521,6 @@ CONFIG_SERIAL_NONSTANDARD=y
438# CONFIG_SX is not set 521# CONFIG_SX is not set
439# CONFIG_RIO is not set 522# CONFIG_RIO is not set
440# CONFIG_STALDRV is not set 523# CONFIG_STALDRV is not set
441# CONFIG_SERIAL_TX3912 is not set
442CONFIG_TXX927_SERIAL=y
443CONFIG_TXX927_SERIAL_CONSOLE=y
444# CONFIG_SERIAL_TXX9 is not set
445 524
446# 525#
447# Serial drivers 526# Serial drivers
@@ -451,6 +530,8 @@ CONFIG_TXX927_SERIAL_CONSOLE=y
451# 530#
452# Non-8250 serial port support 531# Non-8250 serial port support
453# 532#
533CONFIG_HAS_TXX9_SERIAL=y
534# CONFIG_SERIAL_JSM is not set
454# CONFIG_UNIX98_PTYS is not set 535# CONFIG_UNIX98_PTYS is not set
455CONFIG_LEGACY_PTYS=y 536CONFIG_LEGACY_PTYS=y
456CONFIG_LEGACY_PTY_COUNT=256 537CONFIG_LEGACY_PTY_COUNT=256
@@ -477,6 +558,11 @@ CONFIG_LEGACY_PTY_COUNT=256
477# CONFIG_RAW_DRIVER is not set 558# CONFIG_RAW_DRIVER is not set
478 559
479# 560#
561# TPM devices
562#
563# CONFIG_TCG_TPM is not set
564
565#
480# I2C support 566# I2C support
481# 567#
482# CONFIG_I2C is not set 568# CONFIG_I2C is not set
@@ -487,10 +573,20 @@ CONFIG_LEGACY_PTY_COUNT=256
487# CONFIG_W1 is not set 573# CONFIG_W1 is not set
488 574
489# 575#
576# Hardware Monitoring support
577#
578# CONFIG_HWMON is not set
579# CONFIG_HWMON_VID is not set
580
581#
490# Misc devices 582# Misc devices
491# 583#
492 584
493# 585#
586# Multimedia Capabilities Port drivers
587#
588
589#
494# Multimedia devices 590# Multimedia devices
495# 591#
496# CONFIG_VIDEO_DEV is not set 592# CONFIG_VIDEO_DEV is not set
@@ -504,6 +600,11 @@ CONFIG_LEGACY_PTY_COUNT=256
504# Graphics support 600# Graphics support
505# 601#
506CONFIG_FB=y 602CONFIG_FB=y
603# CONFIG_FB_CFB_FILLRECT is not set
604# CONFIG_FB_CFB_COPYAREA is not set
605# CONFIG_FB_CFB_IMAGEBLIT is not set
606# CONFIG_FB_SOFT_CURSOR is not set
607# CONFIG_FB_MACMODES is not set
507# CONFIG_FB_MODE_HELPERS is not set 608# CONFIG_FB_MODE_HELPERS is not set
508# CONFIG_FB_TILEBLITTING is not set 609# CONFIG_FB_TILEBLITTING is not set
509# CONFIG_FB_CIRRUS is not set 610# CONFIG_FB_CIRRUS is not set
@@ -511,6 +612,7 @@ CONFIG_FB=y
511# CONFIG_FB_CYBER2000 is not set 612# CONFIG_FB_CYBER2000 is not set
512# CONFIG_FB_ASILIANT is not set 613# CONFIG_FB_ASILIANT is not set
513# CONFIG_FB_IMSTT is not set 614# CONFIG_FB_IMSTT is not set
615# CONFIG_FB_NVIDIA is not set
514# CONFIG_FB_RIVA is not set 616# CONFIG_FB_RIVA is not set
515# CONFIG_FB_MATROX is not set 617# CONFIG_FB_MATROX is not set
516# CONFIG_FB_RADEON_OLD is not set 618# CONFIG_FB_RADEON_OLD is not set
@@ -523,8 +625,11 @@ CONFIG_FB=y
523# CONFIG_FB_KYRO is not set 625# CONFIG_FB_KYRO is not set
524# CONFIG_FB_3DFX is not set 626# CONFIG_FB_3DFX is not set
525# CONFIG_FB_VOODOO1 is not set 627# CONFIG_FB_VOODOO1 is not set
628# CONFIG_FB_SMIVGX is not set
629# CONFIG_FB_CYBLA is not set
526# CONFIG_FB_TRIDENT is not set 630# CONFIG_FB_TRIDENT is not set
527# CONFIG_FB_E1356 is not set 631# CONFIG_FB_E1356 is not set
632# CONFIG_FB_S1D13XXX is not set
528# CONFIG_FB_VIRTUAL is not set 633# CONFIG_FB_VIRTUAL is not set
529 634
530# 635#
@@ -548,13 +653,9 @@ CONFIG_DUMMY_CONSOLE=y
548# 653#
549# USB support 654# USB support
550# 655#
551# CONFIG_USB is not set
552CONFIG_USB_ARCH_HAS_HCD=y 656CONFIG_USB_ARCH_HAS_HCD=y
553CONFIG_USB_ARCH_HAS_OHCI=y 657CONFIG_USB_ARCH_HAS_OHCI=y
554 658# CONFIG_USB is not set
555#
556# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
557#
558 659
559# 660#
560# USB Gadget Support 661# USB Gadget Support
@@ -572,6 +673,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y
572# CONFIG_INFINIBAND is not set 673# CONFIG_INFINIBAND is not set
573 674
574# 675#
676# SN Devices
677#
678
679#
575# File systems 680# File systems
576# 681#
577# CONFIG_EXT2_FS is not set 682# CONFIG_EXT2_FS is not set
@@ -579,13 +684,16 @@ CONFIG_USB_ARCH_HAS_OHCI=y
579# CONFIG_JBD is not set 684# CONFIG_JBD is not set
580# CONFIG_REISERFS_FS is not set 685# CONFIG_REISERFS_FS is not set
581# CONFIG_JFS_FS is not set 686# CONFIG_JFS_FS is not set
687# CONFIG_FS_POSIX_ACL is not set
582# CONFIG_XFS_FS is not set 688# CONFIG_XFS_FS is not set
583# CONFIG_MINIX_FS is not set 689# CONFIG_MINIX_FS is not set
584# CONFIG_ROMFS_FS is not set 690# CONFIG_ROMFS_FS is not set
691CONFIG_INOTIFY=y
585# CONFIG_QUOTA is not set 692# CONFIG_QUOTA is not set
586CONFIG_DNOTIFY=y 693CONFIG_DNOTIFY=y
587# CONFIG_AUTOFS_FS is not set 694# CONFIG_AUTOFS_FS is not set
588# CONFIG_AUTOFS4_FS is not set 695# CONFIG_AUTOFS4_FS is not set
696CONFIG_FUSE_FS=y
589 697
590# 698#
591# CD-ROM/DVD Filesystems 699# CD-ROM/DVD Filesystems
@@ -606,10 +714,10 @@ CONFIG_DNOTIFY=y
606CONFIG_PROC_FS=y 714CONFIG_PROC_FS=y
607CONFIG_PROC_KCORE=y 715CONFIG_PROC_KCORE=y
608CONFIG_SYSFS=y 716CONFIG_SYSFS=y
609# CONFIG_DEVFS_FS is not set
610# CONFIG_TMPFS is not set 717# CONFIG_TMPFS is not set
611# CONFIG_HUGETLB_PAGE is not set 718# CONFIG_HUGETLB_PAGE is not set
612CONFIG_RAMFS=y 719CONFIG_RAMFS=y
720CONFIG_RELAYFS_FS=y
613 721
614# 722#
615# Miscellaneous filesystems 723# Miscellaneous filesystems
@@ -638,7 +746,7 @@ CONFIG_NFS_FS=y
638# CONFIG_NFSD is not set 746# CONFIG_NFSD is not set
639CONFIG_ROOT_NFS=y 747CONFIG_ROOT_NFS=y
640CONFIG_LOCKD=y 748CONFIG_LOCKD=y
641# CONFIG_EXPORTFS is not set 749CONFIG_NFS_COMMON=y
642CONFIG_SUNRPC=y 750CONFIG_SUNRPC=y
643# CONFIG_RPCSEC_GSS_KRB5 is not set 751# CONFIG_RPCSEC_GSS_KRB5 is not set
644# CONFIG_RPCSEC_GSS_SPKM3 is not set 752# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -647,6 +755,7 @@ CONFIG_SUNRPC=y
647# CONFIG_NCP_FS is not set 755# CONFIG_NCP_FS is not set
648# CONFIG_CODA_FS is not set 756# CONFIG_CODA_FS is not set
649# CONFIG_AFS_FS is not set 757# CONFIG_AFS_FS is not set
758# CONFIG_9P_FS is not set
650 759
651# 760#
652# Partition Types 761# Partition Types
@@ -667,7 +776,9 @@ CONFIG_MSDOS_PARTITION=y
667# 776#
668# Kernel hacking 777# Kernel hacking
669# 778#
779# CONFIG_PRINTK_TIME is not set
670# CONFIG_DEBUG_KERNEL is not set 780# CONFIG_DEBUG_KERNEL is not set
781CONFIG_LOG_BUF_SHIFT=14
671CONFIG_CROSSCOMPILE=y 782CONFIG_CROSSCOMPILE=y
672CONFIG_CMDLINE="" 783CONFIG_CMDLINE=""
673 784
@@ -681,7 +792,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
681# 792#
682# Cryptographic options 793# Cryptographic options
683# 794#
684# CONFIG_CRYPTO is not set 795CONFIG_CRYPTO=y
796CONFIG_CRYPTO_HMAC=y
797CONFIG_CRYPTO_NULL=y
798CONFIG_CRYPTO_MD4=y
799CONFIG_CRYPTO_MD5=y
800CONFIG_CRYPTO_SHA1=y
801CONFIG_CRYPTO_SHA256=y
802CONFIG_CRYPTO_SHA512=y
803CONFIG_CRYPTO_WP512=y
804CONFIG_CRYPTO_TGR192=y
805CONFIG_CRYPTO_DES=y
806CONFIG_CRYPTO_BLOWFISH=y
807CONFIG_CRYPTO_TWOFISH=y
808CONFIG_CRYPTO_SERPENT=y
809CONFIG_CRYPTO_AES=y
810CONFIG_CRYPTO_CAST5=y
811CONFIG_CRYPTO_CAST6=y
812CONFIG_CRYPTO_TEA=y
813CONFIG_CRYPTO_ARC4=y
814CONFIG_CRYPTO_KHAZAD=y
815CONFIG_CRYPTO_ANUBIS=y
816CONFIG_CRYPTO_DEFLATE=y
817CONFIG_CRYPTO_MICHAEL_MIC=y
818CONFIG_CRYPTO_CRC32C=y
819# CONFIG_CRYPTO_TEST is not set
685 820
686# 821#
687# Hardware crypto devices 822# Hardware crypto devices
@@ -691,7 +826,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
691# Library routines 826# Library routines
692# 827#
693# CONFIG_CRC_CCITT is not set 828# CONFIG_CRC_CCITT is not set
694# CONFIG_CRC32 is not set 829CONFIG_CRC16=y
695# CONFIG_LIBCRC32C is not set 830CONFIG_CRC32=y
696CONFIG_GENERIC_HARDIRQS=y 831CONFIG_LIBCRC32C=y
697CONFIG_GENERIC_IRQ_PROBE=y 832CONFIG_ZLIB_INFLATE=y
833CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig
index 8d600ae890f4..03cd0ca6e639 100644
--- a/arch/mips/configs/lasat200_defconfig
+++ b/arch/mips/configs/lasat200_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:06 2005 4# Thu Oct 20 22:26:19 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,53 +59,83 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
67CONFIG_LASAT=y
68CONFIG_PICVUE=y
69CONFIG_PICVUE_PROC=y
70CONFIG_DS1603=y
71CONFIG_LASAT_SYSCTL=y
72# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82CONFIG_LASAT=y
73# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
74# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
75# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
76# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
77# CONFIG_MOMENCO_OCELOT_G is not set
78# CONFIG_MOMENCO_OCELOT_C is not set
79# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
80# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
81# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
82# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
83# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
84# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
85# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
86# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
87# CONFIG_SOC_AU1X00 is not set 102# CONFIG_SGI_IP27 is not set
88# CONFIG_SIBYTE_SB1xxx_SOC is not set 103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
89# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
90# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
117CONFIG_PICVUE=y
118CONFIG_PICVUE_PROC=y
119CONFIG_DS1603=y
120CONFIG_LASAT_SYSCTL=y
91CONFIG_RWSEM_GENERIC_SPINLOCK=y 121CONFIG_RWSEM_GENERIC_SPINLOCK=y
92CONFIG_GENERIC_CALIBRATE_DELAY=y 122CONFIG_GENERIC_CALIBRATE_DELAY=y
93CONFIG_HAVE_DEC_LOCK=y
94CONFIG_DMA_NONCOHERENT=y 123CONFIG_DMA_NONCOHERENT=y
95CONFIG_DMA_NEED_PCI_MAP_STATE=y 124CONFIG_DMA_NEED_PCI_MAP_STATE=y
96CONFIG_MIPS_NILE4=y 125CONFIG_MIPS_NILE4=y
126# CONFIG_CPU_BIG_ENDIAN is not set
97CONFIG_CPU_LITTLE_ENDIAN=y 127CONFIG_CPU_LITTLE_ENDIAN=y
128CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
98CONFIG_MIPS_GT64120=y 129CONFIG_MIPS_GT64120=y
99CONFIG_MIPS_L1_CACHE_SHIFT=5 130CONFIG_MIPS_L1_CACHE_SHIFT=5
100 131
101# 132#
102# CPU selection 133# CPU selection
103# 134#
104# CONFIG_CPU_MIPS32 is not set 135# CONFIG_CPU_MIPS32_R1 is not set
105# CONFIG_CPU_MIPS64 is not set 136# CONFIG_CPU_MIPS32_R2 is not set
137# CONFIG_CPU_MIPS64_R1 is not set
138# CONFIG_CPU_MIPS64_R2 is not set
106# CONFIG_CPU_R3000 is not set 139# CONFIG_CPU_R3000 is not set
107# CONFIG_CPU_TX39XX is not set 140# CONFIG_CPU_TX39XX is not set
108# CONFIG_CPU_VR41XX is not set 141# CONFIG_CPU_VR41XX is not set
@@ -118,17 +151,41 @@ CONFIG_CPU_R5000=y
118# CONFIG_CPU_RM7000 is not set 151# CONFIG_CPU_RM7000 is not set
119# CONFIG_CPU_RM9000 is not set 152# CONFIG_CPU_RM9000 is not set
120# CONFIG_CPU_SB1 is not set 153# CONFIG_CPU_SB1 is not set
154CONFIG_SYS_HAS_CPU_R5000=y
155CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
156CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
157CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
158CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
159
160#
161# Kernel type
162#
163CONFIG_32BIT=y
164# CONFIG_64BIT is not set
121CONFIG_PAGE_SIZE_4KB=y 165CONFIG_PAGE_SIZE_4KB=y
122# CONFIG_PAGE_SIZE_8KB is not set 166# CONFIG_PAGE_SIZE_8KB is not set
123# CONFIG_PAGE_SIZE_16KB is not set 167# CONFIG_PAGE_SIZE_16KB is not set
124# CONFIG_PAGE_SIZE_64KB is not set 168# CONFIG_PAGE_SIZE_64KB is not set
125CONFIG_BOARD_SCACHE=y 169CONFIG_BOARD_SCACHE=y
126CONFIG_R5000_CPU_SCACHE=y 170CONFIG_R5000_CPU_SCACHE=y
171# CONFIG_MIPS_MT is not set
127# CONFIG_64BIT_PHYS_ADDR is not set 172# CONFIG_64BIT_PHYS_ADDR is not set
128# CONFIG_CPU_ADVANCED is not set 173# CONFIG_CPU_ADVANCED is not set
129CONFIG_CPU_HAS_LLSC=y 174CONFIG_CPU_HAS_LLSC=y
130CONFIG_CPU_HAS_LLDSCD=y 175CONFIG_CPU_HAS_LLDSCD=y
131CONFIG_CPU_HAS_SYNC=y 176CONFIG_CPU_HAS_SYNC=y
177CONFIG_GENERIC_HARDIRQS=y
178CONFIG_GENERIC_IRQ_PROBE=y
179CONFIG_ARCH_FLATMEM_ENABLE=y
180CONFIG_SELECT_MEMORY_MODEL=y
181CONFIG_FLATMEM_MANUAL=y
182# CONFIG_DISCONTIGMEM_MANUAL is not set
183# CONFIG_SPARSEMEM_MANUAL is not set
184CONFIG_FLATMEM=y
185CONFIG_FLAT_NODE_MEM_MAP=y
186# CONFIG_SPARSEMEM_STATIC is not set
187CONFIG_PREEMPT_NONE=y
188# CONFIG_PREEMPT_VOLUNTARY is not set
132# CONFIG_PREEMPT is not set 189# CONFIG_PREEMPT is not set
133 190
134# 191#
@@ -137,7 +194,6 @@ CONFIG_CPU_HAS_SYNC=y
137CONFIG_HW_HAS_PCI=y 194CONFIG_HW_HAS_PCI=y
138CONFIG_PCI=y 195CONFIG_PCI=y
139CONFIG_PCI_LEGACY_PROC=y 196CONFIG_PCI_LEGACY_PROC=y
140# CONFIG_PCI_NAMES is not set
141CONFIG_MMU=y 197CONFIG_MMU=y
142 198
143# 199#
@@ -146,10 +202,6 @@ CONFIG_MMU=y
146# CONFIG_PCCARD is not set 202# CONFIG_PCCARD is not set
147 203
148# 204#
149# PC-card bridges
150#
151
152#
153# PCI Hotplug Support 205# PCI Hotplug Support
154# 206#
155# CONFIG_HOTPLUG_PCI is not set 207# CONFIG_HOTPLUG_PCI is not set
@@ -162,6 +214,76 @@ CONFIG_BINFMT_ELF=y
162CONFIG_TRAD_SIGNALS=y 214CONFIG_TRAD_SIGNALS=y
163 215
164# 216#
217# Networking
218#
219CONFIG_NET=y
220
221#
222# Networking options
223#
224# CONFIG_PACKET is not set
225CONFIG_UNIX=y
226CONFIG_XFRM=y
227CONFIG_XFRM_USER=m
228CONFIG_NET_KEY=y
229CONFIG_INET=y
230# CONFIG_IP_MULTICAST is not set
231# CONFIG_IP_ADVANCED_ROUTER is not set
232CONFIG_IP_FIB_HASH=y
233# CONFIG_IP_PNP is not set
234# CONFIG_NET_IPIP is not set
235# CONFIG_NET_IPGRE is not set
236# CONFIG_ARPD is not set
237# CONFIG_SYN_COOKIES is not set
238# CONFIG_INET_AH is not set
239# CONFIG_INET_ESP is not set
240# CONFIG_INET_IPCOMP is not set
241CONFIG_INET_TUNNEL=m
242CONFIG_INET_DIAG=y
243CONFIG_INET_TCP_DIAG=y
244# CONFIG_TCP_CONG_ADVANCED is not set
245CONFIG_TCP_CONG_BIC=y
246# CONFIG_IPV6 is not set
247# CONFIG_NETFILTER is not set
248
249#
250# DCCP Configuration (EXPERIMENTAL)
251#
252# CONFIG_IP_DCCP is not set
253
254#
255# SCTP Configuration (EXPERIMENTAL)
256#
257# CONFIG_IP_SCTP is not set
258# CONFIG_ATM is not set
259# CONFIG_BRIDGE is not set
260# CONFIG_VLAN_8021Q is not set
261# CONFIG_DECNET is not set
262# CONFIG_LLC2 is not set
263# CONFIG_IPX is not set
264# CONFIG_ATALK is not set
265# CONFIG_X25 is not set
266# CONFIG_LAPB is not set
267# CONFIG_NET_DIVERT is not set
268# CONFIG_ECONET is not set
269# CONFIG_WAN_ROUTER is not set
270# CONFIG_NET_SCHED is not set
271# CONFIG_NET_CLS_ROUTE is not set
272
273#
274# Network testing
275#
276# CONFIG_NET_PKTGEN is not set
277# CONFIG_HAMRADIO is not set
278# CONFIG_IRDA is not set
279# CONFIG_BT is not set
280CONFIG_IEEE80211=m
281# CONFIG_IEEE80211_DEBUG is not set
282CONFIG_IEEE80211_CRYPT_WEP=m
283CONFIG_IEEE80211_CRYPT_CCMP=m
284CONFIG_IEEE80211_CRYPT_TKIP=m
285
286#
165# Device Drivers 287# Device Drivers
166# 288#
167 289
@@ -170,15 +292,20 @@ CONFIG_TRAD_SIGNALS=y
170# 292#
171CONFIG_STANDALONE=y 293CONFIG_STANDALONE=y
172CONFIG_PREVENT_FIRMWARE_BUILD=y 294CONFIG_PREVENT_FIRMWARE_BUILD=y
173# CONFIG_FW_LOADER is not set 295CONFIG_FW_LOADER=m
296
297#
298# Connector - unified userspace <-> kernelspace linker
299#
300CONFIG_CONNECTOR=m
174 301
175# 302#
176# Memory Technology Devices (MTD) 303# Memory Technology Devices (MTD)
177# 304#
178CONFIG_MTD=y 305CONFIG_MTD=y
179# CONFIG_MTD_DEBUG is not set 306# CONFIG_MTD_DEBUG is not set
180CONFIG_MTD_PARTITIONS=y
181# CONFIG_MTD_CONCAT is not set 307# CONFIG_MTD_CONCAT is not set
308CONFIG_MTD_PARTITIONS=y
182# CONFIG_MTD_REDBOOT_PARTS is not set 309# CONFIG_MTD_REDBOOT_PARTS is not set
183# CONFIG_MTD_CMDLINE_PARTS is not set 310# CONFIG_MTD_CMDLINE_PARTS is not set
184 311
@@ -223,6 +350,7 @@ CONFIG_MTD_CFI_UTIL=y
223# CONFIG_MTD_COMPLEX_MAPPINGS is not set 350# CONFIG_MTD_COMPLEX_MAPPINGS is not set
224# CONFIG_MTD_PHYSMAP is not set 351# CONFIG_MTD_PHYSMAP is not set
225CONFIG_MTD_LASAT=y 352CONFIG_MTD_LASAT=y
353# CONFIG_MTD_PLATRAM is not set
226 354
227# 355#
228# Self-contained MTD device drivers 356# Self-contained MTD device drivers
@@ -258,7 +386,6 @@ CONFIG_MTD_LASAT=y
258# 386#
259# Block devices 387# Block devices
260# 388#
261# CONFIG_BLK_DEV_FD is not set
262# CONFIG_BLK_CPQ_DA is not set 389# CONFIG_BLK_CPQ_DA is not set
263# CONFIG_BLK_CPQ_CISS_DA is not set 390# CONFIG_BLK_CPQ_CISS_DA is not set
264# CONFIG_BLK_DEV_DAC960 is not set 391# CONFIG_BLK_DEV_DAC960 is not set
@@ -269,7 +396,6 @@ CONFIG_MTD_LASAT=y
269# CONFIG_BLK_DEV_SX8 is not set 396# CONFIG_BLK_DEV_SX8 is not set
270# CONFIG_BLK_DEV_RAM is not set 397# CONFIG_BLK_DEV_RAM is not set
271CONFIG_BLK_DEV_RAM_COUNT=16 398CONFIG_BLK_DEV_RAM_COUNT=16
272CONFIG_INITRAMFS_SOURCE=""
273# CONFIG_LBD is not set 399# CONFIG_LBD is not set
274CONFIG_CDROM_PKTCDVD=m 400CONFIG_CDROM_PKTCDVD=m
275CONFIG_CDROM_PKTCDVD_BUFFERS=8 401CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -326,6 +452,7 @@ CONFIG_BLK_DEV_CMD64X=y
326# CONFIG_BLK_DEV_HPT366 is not set 452# CONFIG_BLK_DEV_HPT366 is not set
327# CONFIG_BLK_DEV_SC1200 is not set 453# CONFIG_BLK_DEV_SC1200 is not set
328# CONFIG_BLK_DEV_PIIX is not set 454# CONFIG_BLK_DEV_PIIX is not set
455# CONFIG_BLK_DEV_IT821X is not set
329# CONFIG_BLK_DEV_NS87415 is not set 456# CONFIG_BLK_DEV_NS87415 is not set
330# CONFIG_BLK_DEV_PDC202XX_OLD is not set 457# CONFIG_BLK_DEV_PDC202XX_OLD is not set
331# CONFIG_BLK_DEV_PDC202XX_NEW is not set 458# CONFIG_BLK_DEV_PDC202XX_NEW is not set
@@ -343,6 +470,7 @@ CONFIG_IDEDMA_AUTO=y
343# 470#
344# SCSI device support 471# SCSI device support
345# 472#
473CONFIG_RAID_ATTRS=m
346# CONFIG_SCSI is not set 474# CONFIG_SCSI is not set
347 475
348# 476#
@@ -353,6 +481,7 @@ CONFIG_IDEDMA_AUTO=y
353# 481#
354# Fusion MPT device support 482# Fusion MPT device support
355# 483#
484# CONFIG_FUSION is not set
356 485
357# 486#
358# IEEE 1394 (FireWire) support 487# IEEE 1394 (FireWire) support
@@ -365,68 +494,8 @@ CONFIG_IDEDMA_AUTO=y
365# CONFIG_I2O is not set 494# CONFIG_I2O is not set
366 495
367# 496#
368# Networking support 497# Network device support
369#
370CONFIG_NET=y
371
372#
373# Networking options
374#
375# CONFIG_PACKET is not set
376# CONFIG_NETLINK_DEV is not set
377CONFIG_UNIX=y
378CONFIG_NET_KEY=y
379CONFIG_INET=y
380# CONFIG_IP_MULTICAST is not set
381# CONFIG_IP_ADVANCED_ROUTER is not set
382# CONFIG_IP_PNP is not set
383# CONFIG_NET_IPIP is not set
384# CONFIG_NET_IPGRE is not set
385# CONFIG_ARPD is not set
386# CONFIG_SYN_COOKIES is not set
387# CONFIG_INET_AH is not set
388# CONFIG_INET_ESP is not set
389# CONFIG_INET_IPCOMP is not set
390CONFIG_INET_TUNNEL=m
391CONFIG_IP_TCPDIAG=m
392# CONFIG_IP_TCPDIAG_IPV6 is not set
393# CONFIG_IPV6 is not set
394# CONFIG_NETFILTER is not set
395CONFIG_XFRM=y
396CONFIG_XFRM_USER=m
397
398#
399# SCTP Configuration (EXPERIMENTAL)
400#
401# CONFIG_IP_SCTP is not set
402# CONFIG_ATM is not set
403# CONFIG_BRIDGE is not set
404# CONFIG_VLAN_8021Q is not set
405# CONFIG_DECNET is not set
406# CONFIG_LLC2 is not set
407# CONFIG_IPX is not set
408# CONFIG_ATALK is not set
409# CONFIG_X25 is not set
410# CONFIG_LAPB is not set
411# CONFIG_NET_DIVERT is not set
412# CONFIG_ECONET is not set
413# CONFIG_WAN_ROUTER is not set
414
415#
416# QoS and/or fair queueing
417# 498#
418# CONFIG_NET_SCHED is not set
419# CONFIG_NET_CLS_ROUTE is not set
420
421#
422# Network testing
423#
424# CONFIG_NET_PKTGEN is not set
425# CONFIG_NETPOLL is not set
426# CONFIG_NET_POLL_CONTROLLER is not set
427# CONFIG_HAMRADIO is not set
428# CONFIG_IRDA is not set
429# CONFIG_BT is not set
430CONFIG_NETDEVICES=y 499CONFIG_NETDEVICES=y
431# CONFIG_DUMMY is not set 500# CONFIG_DUMMY is not set
432# CONFIG_BONDING is not set 501# CONFIG_BONDING is not set
@@ -439,6 +508,21 @@ CONFIG_NETDEVICES=y
439# CONFIG_ARCNET is not set 508# CONFIG_ARCNET is not set
440 509
441# 510#
511# PHY device support
512#
513CONFIG_PHYLIB=m
514CONFIG_PHYCONTROL=y
515
516#
517# MII PHY device drivers
518#
519CONFIG_MARVELL_PHY=m
520CONFIG_DAVICOM_PHY=m
521CONFIG_QSEMI_PHY=m
522CONFIG_LXT_PHY=m
523CONFIG_CICADA_PHY=m
524
525#
442# Ethernet (10 or 100Mbit) 526# Ethernet (10 or 100Mbit)
443# 527#
444CONFIG_NET_ETHERNET=y 528CONFIG_NET_ETHERNET=y
@@ -464,12 +548,16 @@ CONFIG_NET_ETHERNET=y
464# CONFIG_HAMACHI is not set 548# CONFIG_HAMACHI is not set
465# CONFIG_YELLOWFIN is not set 549# CONFIG_YELLOWFIN is not set
466# CONFIG_R8169 is not set 550# CONFIG_R8169 is not set
551# CONFIG_SIS190 is not set
552# CONFIG_SKGE is not set
467# CONFIG_SK98LIN is not set 553# CONFIG_SK98LIN is not set
468# CONFIG_TIGON3 is not set 554# CONFIG_TIGON3 is not set
555# CONFIG_BNX2 is not set
469 556
470# 557#
471# Ethernet (10000 Mbit) 558# Ethernet (10000 Mbit)
472# 559#
560# CONFIG_CHELSIO_T1 is not set
473# CONFIG_IXGB is not set 561# CONFIG_IXGB is not set
474# CONFIG_S2IO is not set 562# CONFIG_S2IO is not set
475 563
@@ -482,6 +570,8 @@ CONFIG_NET_ETHERNET=y
482# Wireless LAN (non-hamradio) 570# Wireless LAN (non-hamradio)
483# 571#
484# CONFIG_NET_RADIO is not set 572# CONFIG_NET_RADIO is not set
573# CONFIG_IPW_DEBUG is not set
574CONFIG_IPW2200=m
485 575
486# 576#
487# Wan interfaces 577# Wan interfaces
@@ -493,6 +583,8 @@ CONFIG_NET_ETHERNET=y
493# CONFIG_SLIP is not set 583# CONFIG_SLIP is not set
494# CONFIG_SHAPER is not set 584# CONFIG_SHAPER is not set
495# CONFIG_NETCONSOLE is not set 585# CONFIG_NETCONSOLE is not set
586# CONFIG_NETPOLL is not set
587# CONFIG_NET_POLL_CONTROLLER is not set
496 588
497# 589#
498# ISDN subsystem 590# ISDN subsystem
@@ -522,19 +614,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
522# CONFIG_INPUT_EVBUG is not set 614# CONFIG_INPUT_EVBUG is not set
523 615
524# 616#
525# Input I/O drivers
526#
527# CONFIG_GAMEPORT is not set
528CONFIG_SOUND_GAMEPORT=y
529CONFIG_SERIO=y
530CONFIG_SERIO_I8042=y
531CONFIG_SERIO_SERPORT=y
532# CONFIG_SERIO_CT82C710 is not set
533# CONFIG_SERIO_PCIPS2 is not set
534# CONFIG_SERIO_LIBPS2 is not set
535CONFIG_SERIO_RAW=m
536
537#
538# Input Device Drivers 617# Input Device Drivers
539# 618#
540# CONFIG_INPUT_KEYBOARD is not set 619# CONFIG_INPUT_KEYBOARD is not set
@@ -544,6 +623,17 @@ CONFIG_SERIO_RAW=m
544# CONFIG_INPUT_MISC is not set 623# CONFIG_INPUT_MISC is not set
545 624
546# 625#
626# Hardware I/O ports
627#
628CONFIG_SERIO=y
629CONFIG_SERIO_I8042=y
630CONFIG_SERIO_SERPORT=y
631# CONFIG_SERIO_PCIPS2 is not set
632# CONFIG_SERIO_LIBPS2 is not set
633CONFIG_SERIO_RAW=m
634# CONFIG_GAMEPORT is not set
635
636#
547# Character devices 637# Character devices
548# 638#
549CONFIG_VT=y 639CONFIG_VT=y
@@ -564,6 +654,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
564# 654#
565CONFIG_SERIAL_CORE=y 655CONFIG_SERIAL_CORE=y
566CONFIG_SERIAL_CORE_CONSOLE=y 656CONFIG_SERIAL_CORE_CONSOLE=y
657# CONFIG_SERIAL_JSM is not set
567CONFIG_UNIX98_PTYS=y 658CONFIG_UNIX98_PTYS=y
568CONFIG_LEGACY_PTYS=y 659CONFIG_LEGACY_PTYS=y
569CONFIG_LEGACY_PTY_COUNT=256 660CONFIG_LEGACY_PTY_COUNT=256
@@ -590,6 +681,11 @@ CONFIG_LEGACY_PTY_COUNT=256
590# CONFIG_RAW_DRIVER is not set 681# CONFIG_RAW_DRIVER is not set
591 682
592# 683#
684# TPM devices
685#
686# CONFIG_TCG_TPM is not set
687
688#
593# I2C support 689# I2C support
594# 690#
595# CONFIG_I2C is not set 691# CONFIG_I2C is not set
@@ -600,10 +696,20 @@ CONFIG_LEGACY_PTY_COUNT=256
600# CONFIG_W1 is not set 696# CONFIG_W1 is not set
601 697
602# 698#
699# Hardware Monitoring support
700#
701# CONFIG_HWMON is not set
702# CONFIG_HWMON_VID is not set
703
704#
603# Misc devices 705# Misc devices
604# 706#
605 707
606# 708#
709# Multimedia Capabilities Port drivers
710#
711
712#
607# Multimedia devices 713# Multimedia devices
608# 714#
609# CONFIG_VIDEO_DEV is not set 715# CONFIG_VIDEO_DEV is not set
@@ -623,7 +729,6 @@ CONFIG_LEGACY_PTY_COUNT=256
623# 729#
624# CONFIG_VGA_CONSOLE is not set 730# CONFIG_VGA_CONSOLE is not set
625CONFIG_DUMMY_CONSOLE=y 731CONFIG_DUMMY_CONSOLE=y
626# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
627 732
628# 733#
629# Sound 734# Sound
@@ -633,13 +738,9 @@ CONFIG_DUMMY_CONSOLE=y
633# 738#
634# USB support 739# USB support
635# 740#
636# CONFIG_USB is not set
637CONFIG_USB_ARCH_HAS_HCD=y 741CONFIG_USB_ARCH_HAS_HCD=y
638CONFIG_USB_ARCH_HAS_OHCI=y 742CONFIG_USB_ARCH_HAS_OHCI=y
639 743# CONFIG_USB is not set
640#
641# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
642#
643 744
644# 745#
645# USB Gadget Support 746# USB Gadget Support
@@ -657,10 +758,15 @@ CONFIG_USB_ARCH_HAS_OHCI=y
657# CONFIG_INFINIBAND is not set 758# CONFIG_INFINIBAND is not set
658 759
659# 760#
761# SN Devices
762#
763
764#
660# File systems 765# File systems
661# 766#
662CONFIG_EXT2_FS=y 767CONFIG_EXT2_FS=y
663# CONFIG_EXT2_FS_XATTR is not set 768# CONFIG_EXT2_FS_XATTR is not set
769# CONFIG_EXT2_FS_XIP is not set
664CONFIG_EXT3_FS=y 770CONFIG_EXT3_FS=y
665CONFIG_EXT3_FS_XATTR=y 771CONFIG_EXT3_FS_XATTR=y
666# CONFIG_EXT3_FS_POSIX_ACL is not set 772# CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -670,13 +776,16 @@ CONFIG_JBD=y
670CONFIG_FS_MBCACHE=y 776CONFIG_FS_MBCACHE=y
671# CONFIG_REISERFS_FS is not set 777# CONFIG_REISERFS_FS is not set
672# CONFIG_JFS_FS is not set 778# CONFIG_JFS_FS is not set
779# CONFIG_FS_POSIX_ACL is not set
673# CONFIG_XFS_FS is not set 780# CONFIG_XFS_FS is not set
674# CONFIG_MINIX_FS is not set 781# CONFIG_MINIX_FS is not set
675# CONFIG_ROMFS_FS is not set 782# CONFIG_ROMFS_FS is not set
783CONFIG_INOTIFY=y
676# CONFIG_QUOTA is not set 784# CONFIG_QUOTA is not set
677CONFIG_DNOTIFY=y 785CONFIG_DNOTIFY=y
678# CONFIG_AUTOFS_FS is not set 786# CONFIG_AUTOFS_FS is not set
679# CONFIG_AUTOFS4_FS is not set 787# CONFIG_AUTOFS4_FS is not set
788CONFIG_FUSE_FS=m
680 789
681# 790#
682# CD-ROM/DVD Filesystems 791# CD-ROM/DVD Filesystems
@@ -697,12 +806,10 @@ CONFIG_DNOTIFY=y
697CONFIG_PROC_FS=y 806CONFIG_PROC_FS=y
698CONFIG_PROC_KCORE=y 807CONFIG_PROC_KCORE=y
699CONFIG_SYSFS=y 808CONFIG_SYSFS=y
700# CONFIG_DEVFS_FS is not set
701CONFIG_DEVPTS_FS_XATTR=y
702CONFIG_DEVPTS_FS_SECURITY=y
703# CONFIG_TMPFS is not set 809# CONFIG_TMPFS is not set
704# CONFIG_HUGETLB_PAGE is not set 810# CONFIG_HUGETLB_PAGE is not set
705CONFIG_RAMFS=y 811CONFIG_RAMFS=y
812CONFIG_RELAYFS_FS=m
706 813
707# 814#
708# Miscellaneous filesystems 815# Miscellaneous filesystems
@@ -728,12 +835,13 @@ CONFIG_RAMFS=y
728# 835#
729CONFIG_NFS_FS=y 836CONFIG_NFS_FS=y
730CONFIG_NFS_V3=y 837CONFIG_NFS_V3=y
838# CONFIG_NFS_V3_ACL is not set
731# CONFIG_NFS_V4 is not set 839# CONFIG_NFS_V4 is not set
732# CONFIG_NFS_DIRECTIO is not set 840# CONFIG_NFS_DIRECTIO is not set
733# CONFIG_NFSD is not set 841# CONFIG_NFSD is not set
734CONFIG_LOCKD=y 842CONFIG_LOCKD=y
735CONFIG_LOCKD_V4=y 843CONFIG_LOCKD_V4=y
736# CONFIG_EXPORTFS is not set 844CONFIG_NFS_COMMON=y
737CONFIG_SUNRPC=y 845CONFIG_SUNRPC=y
738# CONFIG_RPCSEC_GSS_KRB5 is not set 846# CONFIG_RPCSEC_GSS_KRB5 is not set
739# CONFIG_RPCSEC_GSS_SPKM3 is not set 847# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -742,6 +850,7 @@ CONFIG_SUNRPC=y
742# CONFIG_NCP_FS is not set 850# CONFIG_NCP_FS is not set
743# CONFIG_CODA_FS is not set 851# CONFIG_CODA_FS is not set
744# CONFIG_AFS_FS is not set 852# CONFIG_AFS_FS is not set
853# CONFIG_9P_FS is not set
745 854
746# 855#
747# Partition Types 856# Partition Types
@@ -762,7 +871,9 @@ CONFIG_MSDOS_PARTITION=y
762# 871#
763# Kernel hacking 872# Kernel hacking
764# 873#
874# CONFIG_PRINTK_TIME is not set
765# CONFIG_DEBUG_KERNEL is not set 875# CONFIG_DEBUG_KERNEL is not set
876CONFIG_LOG_BUF_SHIFT=14
766CONFIG_CROSSCOMPILE=y 877CONFIG_CROSSCOMPILE=y
767CONFIG_CMDLINE="" 878CONFIG_CMDLINE=""
768 879
@@ -776,7 +887,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
776# 887#
777# Cryptographic options 888# Cryptographic options
778# 889#
779# CONFIG_CRYPTO is not set 890CONFIG_CRYPTO=y
891CONFIG_CRYPTO_HMAC=y
892CONFIG_CRYPTO_NULL=m
893CONFIG_CRYPTO_MD4=m
894CONFIG_CRYPTO_MD5=m
895CONFIG_CRYPTO_SHA1=m
896CONFIG_CRYPTO_SHA256=m
897CONFIG_CRYPTO_SHA512=m
898CONFIG_CRYPTO_WP512=m
899CONFIG_CRYPTO_TGR192=m
900CONFIG_CRYPTO_DES=m
901CONFIG_CRYPTO_BLOWFISH=m
902CONFIG_CRYPTO_TWOFISH=m
903CONFIG_CRYPTO_SERPENT=m
904CONFIG_CRYPTO_AES=m
905CONFIG_CRYPTO_CAST5=m
906CONFIG_CRYPTO_CAST6=m
907CONFIG_CRYPTO_TEA=m
908CONFIG_CRYPTO_ARC4=m
909CONFIG_CRYPTO_KHAZAD=m
910CONFIG_CRYPTO_ANUBIS=m
911CONFIG_CRYPTO_DEFLATE=m
912CONFIG_CRYPTO_MICHAEL_MIC=m
913CONFIG_CRYPTO_CRC32C=m
914# CONFIG_CRYPTO_TEST is not set
780 915
781# 916#
782# Hardware crypto devices 917# Hardware crypto devices
@@ -786,7 +921,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
786# Library routines 921# Library routines
787# 922#
788# CONFIG_CRC_CCITT is not set 923# CONFIG_CRC_CCITT is not set
924CONFIG_CRC16=m
789CONFIG_CRC32=y 925CONFIG_CRC32=y
790CONFIG_LIBCRC32C=m 926CONFIG_LIBCRC32C=m
791CONFIG_GENERIC_HARDIRQS=y 927CONFIG_ZLIB_INFLATE=m
792CONFIG_GENERIC_IRQ_PROBE=y 928CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 79519ac5af4a..2acdec959dd0 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:53:14 2005 4# Thu Oct 20 22:26:22 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29CONFIG_HOTPLUG=y 27CONFIG_HOTPLUG=y
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,44 +59,75 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
70CONFIG_MIPS_MALTA=y 84CONFIG_MIPS_MALTA=y
71# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
83# CONFIG_SOC_AU1X00 is not set 102# CONFIG_SGI_IP27 is not set
84# CONFIG_SIBYTE_SB1xxx_SOC is not set 103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
85# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
86# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
87CONFIG_RWSEM_GENERIC_SPINLOCK=y 117CONFIG_RWSEM_GENERIC_SPINLOCK=y
88CONFIG_GENERIC_CALIBRATE_DELAY=y 118CONFIG_GENERIC_CALIBRATE_DELAY=y
89CONFIG_HAVE_DEC_LOCK=y 119CONFIG_ARCH_MAY_HAVE_PC_FDC=y
90CONFIG_DMA_NONCOHERENT=y 120CONFIG_DMA_NONCOHERENT=y
91CONFIG_DMA_NEED_PCI_MAP_STATE=y 121CONFIG_DMA_NEED_PCI_MAP_STATE=y
92CONFIG_GENERIC_ISA_DMA=y 122CONFIG_GENERIC_ISA_DMA=y
93CONFIG_I8259=y 123CONFIG_I8259=y
94CONFIG_MIPS_BONITO64=y 124CONFIG_MIPS_BONITO64=y
95CONFIG_MIPS_MSC=y 125CONFIG_MIPS_MSC=y
126# CONFIG_CPU_BIG_ENDIAN is not set
96CONFIG_CPU_LITTLE_ENDIAN=y 127CONFIG_CPU_LITTLE_ENDIAN=y
128CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
129CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
130CONFIG_IRQ_CPU=y
97CONFIG_MIPS_BOARDS_GEN=y 131CONFIG_MIPS_BOARDS_GEN=y
98CONFIG_MIPS_GT64120=y 132CONFIG_MIPS_GT64120=y
99CONFIG_SWAP_IO_SPACE=y 133CONFIG_SWAP_IO_SPACE=y
@@ -104,8 +138,10 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y
104# 138#
105# CPU selection 139# CPU selection
106# 140#
107CONFIG_CPU_MIPS32=y 141CONFIG_CPU_MIPS32_R1=y
108# CONFIG_CPU_MIPS64 is not set 142# CONFIG_CPU_MIPS32_R2 is not set
143# CONFIG_CPU_MIPS64_R1 is not set
144# CONFIG_CPU_MIPS64_R2 is not set
109# CONFIG_CPU_R3000 is not set 145# CONFIG_CPU_R3000 is not set
110# CONFIG_CPU_TX39XX is not set 146# CONFIG_CPU_TX39XX is not set
111# CONFIG_CPU_VR41XX is not set 147# CONFIG_CPU_VR41XX is not set
@@ -121,14 +157,48 @@ CONFIG_CPU_MIPS32=y
121# CONFIG_CPU_RM7000 is not set 157# CONFIG_CPU_RM7000 is not set
122# CONFIG_CPU_RM9000 is not set 158# CONFIG_CPU_RM9000 is not set
123# CONFIG_CPU_SB1 is not set 159# CONFIG_CPU_SB1 is not set
160CONFIG_SYS_HAS_CPU_MIPS32_R1=y
161CONFIG_SYS_HAS_CPU_MIPS32_R2=y
162CONFIG_SYS_HAS_CPU_MIPS64_R1=y
163CONFIG_SYS_HAS_CPU_NEVADA=y
164CONFIG_SYS_HAS_CPU_RM7000=y
165CONFIG_CPU_MIPS32=y
166CONFIG_CPU_MIPSR1=y
167CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
168CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
169CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
170
171#
172# Kernel type
173#
174CONFIG_32BIT=y
175# CONFIG_64BIT is not set
124CONFIG_PAGE_SIZE_4KB=y 176CONFIG_PAGE_SIZE_4KB=y
125# CONFIG_PAGE_SIZE_8KB is not set 177# CONFIG_PAGE_SIZE_8KB is not set
126# CONFIG_PAGE_SIZE_16KB is not set 178# CONFIG_PAGE_SIZE_16KB is not set
127# CONFIG_PAGE_SIZE_64KB is not set 179# CONFIG_PAGE_SIZE_64KB is not set
180CONFIG_CPU_HAS_PREFETCH=y
181CONFIG_MIPS_MT=y
182# CONFIG_MIPS_MT_SMP is not set
183CONFIG_MIPS_VPE_LOADER=y
184CONFIG_MIPS_VPE_LOADER_TOM=y
185CONFIG_MIPS_VPE_APSP_API=y
128# CONFIG_64BIT_PHYS_ADDR is not set 186# CONFIG_64BIT_PHYS_ADDR is not set
129# CONFIG_CPU_ADVANCED is not set 187# CONFIG_CPU_ADVANCED is not set
130CONFIG_CPU_HAS_LLSC=y 188CONFIG_CPU_HAS_LLSC=y
131CONFIG_CPU_HAS_SYNC=y 189CONFIG_CPU_HAS_SYNC=y
190CONFIG_GENERIC_HARDIRQS=y
191CONFIG_GENERIC_IRQ_PROBE=y
192CONFIG_ARCH_FLATMEM_ENABLE=y
193CONFIG_SELECT_MEMORY_MODEL=y
194CONFIG_FLATMEM_MANUAL=y
195# CONFIG_DISCONTIGMEM_MANUAL is not set
196# CONFIG_SPARSEMEM_MANUAL is not set
197CONFIG_FLATMEM=y
198CONFIG_FLAT_NODE_MEM_MAP=y
199# CONFIG_SPARSEMEM_STATIC is not set
200CONFIG_PREEMPT_NONE=y
201# CONFIG_PREEMPT_VOLUNTARY is not set
132# CONFIG_PREEMPT is not set 202# CONFIG_PREEMPT is not set
133 203
134# 204#
@@ -137,7 +207,6 @@ CONFIG_CPU_HAS_SYNC=y
137CONFIG_HW_HAS_PCI=y 207CONFIG_HW_HAS_PCI=y
138CONFIG_PCI=y 208CONFIG_PCI=y
139CONFIG_PCI_LEGACY_PROC=y 209CONFIG_PCI_LEGACY_PROC=y
140CONFIG_PCI_NAMES=y
141CONFIG_MMU=y 210CONFIG_MMU=y
142 211
143# 212#
@@ -146,10 +215,6 @@ CONFIG_MMU=y
146# CONFIG_PCCARD is not set 215# CONFIG_PCCARD is not set
147 216
148# 217#
149# PC-card bridges
150#
151
152#
153# PCI Hotplug Support 218# PCI Hotplug Support
154# 219#
155# CONFIG_HOTPLUG_PCI is not set 220# CONFIG_HOTPLUG_PCI is not set
@@ -162,229 +227,7 @@ CONFIG_BINFMT_ELF=y
162CONFIG_TRAD_SIGNALS=y 227CONFIG_TRAD_SIGNALS=y
163 228
164# 229#
165# Device Drivers 230# Networking
166#
167
168#
169# Generic Driver Options
170#
171CONFIG_STANDALONE=y
172CONFIG_PREVENT_FIRMWARE_BUILD=y
173CONFIG_FW_LOADER=y
174
175#
176# Memory Technology Devices (MTD)
177#
178# CONFIG_MTD is not set
179
180#
181# Parallel port support
182#
183# CONFIG_PARPORT is not set
184
185#
186# Plug and Play support
187#
188
189#
190# Block devices
191#
192CONFIG_BLK_DEV_FD=m
193# CONFIG_BLK_CPQ_DA is not set
194# CONFIG_BLK_CPQ_CISS_DA is not set
195# CONFIG_BLK_DEV_DAC960 is not set
196CONFIG_BLK_DEV_UMEM=m
197# CONFIG_BLK_DEV_COW_COMMON is not set
198CONFIG_BLK_DEV_LOOP=m
199CONFIG_BLK_DEV_CRYPTOLOOP=m
200CONFIG_BLK_DEV_NBD=m
201# CONFIG_BLK_DEV_SX8 is not set
202CONFIG_BLK_DEV_RAM=y
203CONFIG_BLK_DEV_RAM_COUNT=16
204CONFIG_BLK_DEV_RAM_SIZE=4096
205# CONFIG_BLK_DEV_INITRD is not set
206CONFIG_INITRAMFS_SOURCE=""
207# CONFIG_LBD is not set
208CONFIG_CDROM_PKTCDVD=m
209CONFIG_CDROM_PKTCDVD_BUFFERS=8
210# CONFIG_CDROM_PKTCDVD_WCACHE is not set
211
212#
213# IO Schedulers
214#
215CONFIG_IOSCHED_NOOP=y
216CONFIG_IOSCHED_AS=y
217CONFIG_IOSCHED_DEADLINE=y
218CONFIG_IOSCHED_CFQ=y
219CONFIG_ATA_OVER_ETH=m
220
221#
222# ATA/ATAPI/MFM/RLL support
223#
224CONFIG_IDE=y
225CONFIG_BLK_DEV_IDE=y
226
227#
228# Please see Documentation/ide.txt for help/info on IDE drives
229#
230# CONFIG_BLK_DEV_IDE_SATA is not set
231CONFIG_BLK_DEV_IDEDISK=y
232# CONFIG_IDEDISK_MULTI_MODE is not set
233CONFIG_BLK_DEV_IDECD=y
234# CONFIG_BLK_DEV_IDETAPE is not set
235# CONFIG_BLK_DEV_IDEFLOPPY is not set
236# CONFIG_BLK_DEV_IDESCSI is not set
237# CONFIG_IDE_TASK_IOCTL is not set
238
239#
240# IDE chipset support/bugfixes
241#
242CONFIG_IDE_GENERIC=y
243CONFIG_BLK_DEV_IDEPCI=y
244# CONFIG_IDEPCI_SHARE_IRQ is not set
245# CONFIG_BLK_DEV_OFFBOARD is not set
246CONFIG_BLK_DEV_GENERIC=y
247# CONFIG_BLK_DEV_OPTI621 is not set
248CONFIG_BLK_DEV_IDEDMA_PCI=y
249# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
250CONFIG_IDEDMA_PCI_AUTO=y
251# CONFIG_IDEDMA_ONLYDISK is not set
252# CONFIG_BLK_DEV_AEC62XX is not set
253# CONFIG_BLK_DEV_ALI15X3 is not set
254# CONFIG_BLK_DEV_AMD74XX is not set
255# CONFIG_BLK_DEV_CMD64X is not set
256# CONFIG_BLK_DEV_TRIFLEX is not set
257# CONFIG_BLK_DEV_CY82C693 is not set
258# CONFIG_BLK_DEV_CS5520 is not set
259# CONFIG_BLK_DEV_CS5530 is not set
260# CONFIG_BLK_DEV_HPT34X is not set
261# CONFIG_BLK_DEV_HPT366 is not set
262# CONFIG_BLK_DEV_SC1200 is not set
263CONFIG_BLK_DEV_PIIX=y
264# CONFIG_BLK_DEV_NS87415 is not set
265# CONFIG_BLK_DEV_PDC202XX_OLD is not set
266# CONFIG_BLK_DEV_PDC202XX_NEW is not set
267# CONFIG_BLK_DEV_SVWKS is not set
268# CONFIG_BLK_DEV_SIIMAGE is not set
269# CONFIG_BLK_DEV_SLC90E66 is not set
270# CONFIG_BLK_DEV_TRM290 is not set
271# CONFIG_BLK_DEV_VIA82CXXX is not set
272# CONFIG_IDE_ARM is not set
273CONFIG_BLK_DEV_IDEDMA=y
274# CONFIG_IDEDMA_IVB is not set
275CONFIG_IDEDMA_AUTO=y
276# CONFIG_BLK_DEV_HD is not set
277
278#
279# SCSI device support
280#
281CONFIG_SCSI=m
282CONFIG_SCSI_PROC_FS=y
283
284#
285# SCSI support type (disk, tape, CD-ROM)
286#
287CONFIG_BLK_DEV_SD=m
288CONFIG_CHR_DEV_ST=m
289CONFIG_CHR_DEV_OSST=m
290CONFIG_BLK_DEV_SR=m
291CONFIG_BLK_DEV_SR_VENDOR=y
292CONFIG_CHR_DEV_SG=m
293
294#
295# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
296#
297CONFIG_SCSI_MULTI_LUN=y
298CONFIG_SCSI_CONSTANTS=y
299CONFIG_SCSI_LOGGING=y
300
301#
302# SCSI Transport Attributes
303#
304CONFIG_SCSI_SPI_ATTRS=m
305CONFIG_SCSI_FC_ATTRS=m
306CONFIG_SCSI_ISCSI_ATTRS=m
307
308#
309# SCSI low-level drivers
310#
311CONFIG_BLK_DEV_3W_XXXX_RAID=m
312CONFIG_SCSI_3W_9XXX=m
313CONFIG_SCSI_ACARD=m
314CONFIG_SCSI_AACRAID=m
315CONFIG_SCSI_AIC7XXX=m
316CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
317CONFIG_AIC7XXX_RESET_DELAY_MS=15000
318# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
319CONFIG_AIC7XXX_DEBUG_MASK=0
320CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
321# CONFIG_SCSI_AIC7XXX_OLD is not set
322# CONFIG_SCSI_AIC79XX is not set
323# CONFIG_SCSI_DPT_I2O is not set
324# CONFIG_MEGARAID_NEWGEN is not set
325# CONFIG_MEGARAID_LEGACY is not set
326# CONFIG_SCSI_SATA is not set
327# CONFIG_SCSI_BUSLOGIC is not set
328# CONFIG_SCSI_DMX3191D is not set
329# CONFIG_SCSI_EATA is not set
330# CONFIG_SCSI_EATA_PIO is not set
331# CONFIG_SCSI_FUTURE_DOMAIN is not set
332# CONFIG_SCSI_GDTH is not set
333# CONFIG_SCSI_IPS is not set
334# CONFIG_SCSI_INITIO is not set
335# CONFIG_SCSI_INIA100 is not set
336# CONFIG_SCSI_SYM53C8XX_2 is not set
337# CONFIG_SCSI_IPR is not set
338# CONFIG_SCSI_QLOGIC_ISP is not set
339# CONFIG_SCSI_QLOGIC_FC is not set
340# CONFIG_SCSI_QLOGIC_1280 is not set
341CONFIG_SCSI_QLA2XXX=m
342# CONFIG_SCSI_QLA21XX is not set
343# CONFIG_SCSI_QLA22XX is not set
344# CONFIG_SCSI_QLA2300 is not set
345# CONFIG_SCSI_QLA2322 is not set
346# CONFIG_SCSI_QLA6312 is not set
347# CONFIG_SCSI_DC395x is not set
348# CONFIG_SCSI_DC390T is not set
349# CONFIG_SCSI_NSP32 is not set
350# CONFIG_SCSI_DEBUG is not set
351
352#
353# Multi-device support (RAID and LVM)
354#
355CONFIG_MD=y
356CONFIG_BLK_DEV_MD=m
357CONFIG_MD_LINEAR=m
358CONFIG_MD_RAID0=m
359CONFIG_MD_RAID1=m
360CONFIG_MD_RAID10=m
361CONFIG_MD_RAID5=m
362CONFIG_MD_RAID6=m
363CONFIG_MD_MULTIPATH=m
364CONFIG_MD_FAULTY=m
365CONFIG_BLK_DEV_DM=m
366CONFIG_DM_CRYPT=m
367CONFIG_DM_SNAPSHOT=m
368CONFIG_DM_MIRROR=m
369CONFIG_DM_ZERO=m
370
371#
372# Fusion MPT device support
373#
374# CONFIG_FUSION is not set
375
376#
377# IEEE 1394 (FireWire) support
378#
379# CONFIG_IEEE1394 is not set
380
381#
382# I2O device support
383#
384# CONFIG_I2O is not set
385
386#
387# Networking support
388# 231#
389CONFIG_NET=y 232CONFIG_NET=y
390 233
@@ -393,15 +236,20 @@ CONFIG_NET=y
393# 236#
394CONFIG_PACKET=y 237CONFIG_PACKET=y
395CONFIG_PACKET_MMAP=y 238CONFIG_PACKET_MMAP=y
396CONFIG_NETLINK_DEV=y
397CONFIG_UNIX=y 239CONFIG_UNIX=y
240CONFIG_XFRM=y
241CONFIG_XFRM_USER=m
398CONFIG_NET_KEY=y 242CONFIG_NET_KEY=y
399CONFIG_INET=y 243CONFIG_INET=y
400CONFIG_IP_MULTICAST=y 244CONFIG_IP_MULTICAST=y
401CONFIG_IP_ADVANCED_ROUTER=y 245CONFIG_IP_ADVANCED_ROUTER=y
246CONFIG_ASK_IP_FIB_HASH=y
247# CONFIG_IP_FIB_TRIE is not set
248CONFIG_IP_FIB_HASH=y
402CONFIG_IP_MULTIPLE_TABLES=y 249CONFIG_IP_MULTIPLE_TABLES=y
403CONFIG_IP_ROUTE_FWMARK=y 250CONFIG_IP_ROUTE_FWMARK=y
404CONFIG_IP_ROUTE_MULTIPATH=y 251CONFIG_IP_ROUTE_MULTIPATH=y
252# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
405CONFIG_IP_ROUTE_VERBOSE=y 253CONFIG_IP_ROUTE_VERBOSE=y
406CONFIG_IP_PNP=y 254CONFIG_IP_PNP=y
407CONFIG_IP_PNP_DHCP=y 255CONFIG_IP_PNP_DHCP=y
@@ -419,8 +267,10 @@ CONFIG_INET_AH=m
419CONFIG_INET_ESP=m 267CONFIG_INET_ESP=m
420CONFIG_INET_IPCOMP=m 268CONFIG_INET_IPCOMP=m
421CONFIG_INET_TUNNEL=m 269CONFIG_INET_TUNNEL=m
422CONFIG_IP_TCPDIAG=m 270CONFIG_INET_DIAG=y
423CONFIG_IP_TCPDIAG_IPV6=y 271CONFIG_INET_TCP_DIAG=y
272# CONFIG_TCP_CONG_ADVANCED is not set
273CONFIG_TCP_CONG_BIC=y
424 274
425# 275#
426# IP: Virtual Server Configuration 276# IP: Virtual Server Configuration
@@ -465,6 +315,9 @@ CONFIG_IPV6_TUNNEL=m
465CONFIG_NETFILTER=y 315CONFIG_NETFILTER=y
466# CONFIG_NETFILTER_DEBUG is not set 316# CONFIG_NETFILTER_DEBUG is not set
467CONFIG_BRIDGE_NETFILTER=y 317CONFIG_BRIDGE_NETFILTER=y
318CONFIG_NETFILTER_NETLINK=m
319CONFIG_NETFILTER_NETLINK_QUEUE=m
320CONFIG_NETFILTER_NETLINK_LOG=m
468 321
469# 322#
470# IP: Netfilter Configuration 323# IP: Netfilter Configuration
@@ -472,11 +325,15 @@ CONFIG_BRIDGE_NETFILTER=y
472CONFIG_IP_NF_CONNTRACK=m 325CONFIG_IP_NF_CONNTRACK=m
473CONFIG_IP_NF_CT_ACCT=y 326CONFIG_IP_NF_CT_ACCT=y
474CONFIG_IP_NF_CONNTRACK_MARK=y 327CONFIG_IP_NF_CONNTRACK_MARK=y
328CONFIG_IP_NF_CONNTRACK_EVENTS=y
329CONFIG_IP_NF_CONNTRACK_NETLINK=m
475CONFIG_IP_NF_CT_PROTO_SCTP=m 330CONFIG_IP_NF_CT_PROTO_SCTP=m
476CONFIG_IP_NF_FTP=m 331CONFIG_IP_NF_FTP=m
477CONFIG_IP_NF_IRC=m 332CONFIG_IP_NF_IRC=m
333# CONFIG_IP_NF_NETBIOS_NS is not set
478CONFIG_IP_NF_TFTP=m 334CONFIG_IP_NF_TFTP=m
479CONFIG_IP_NF_AMANDA=m 335CONFIG_IP_NF_AMANDA=m
336CONFIG_IP_NF_PPTP=m
480CONFIG_IP_NF_QUEUE=m 337CONFIG_IP_NF_QUEUE=m
481CONFIG_IP_NF_IPTABLES=m 338CONFIG_IP_NF_IPTABLES=m
482CONFIG_IP_NF_MATCH_LIMIT=m 339CONFIG_IP_NF_MATCH_LIMIT=m
@@ -501,9 +358,12 @@ CONFIG_IP_NF_MATCH_PHYSDEV=m
501CONFIG_IP_NF_MATCH_ADDRTYPE=m 358CONFIG_IP_NF_MATCH_ADDRTYPE=m
502CONFIG_IP_NF_MATCH_REALM=m 359CONFIG_IP_NF_MATCH_REALM=m
503CONFIG_IP_NF_MATCH_SCTP=m 360CONFIG_IP_NF_MATCH_SCTP=m
361CONFIG_IP_NF_MATCH_DCCP=m
504CONFIG_IP_NF_MATCH_COMMENT=m 362CONFIG_IP_NF_MATCH_COMMENT=m
505CONFIG_IP_NF_MATCH_CONNMARK=m 363CONFIG_IP_NF_MATCH_CONNMARK=m
364CONFIG_IP_NF_MATCH_CONNBYTES=m
506CONFIG_IP_NF_MATCH_HASHLIMIT=m 365CONFIG_IP_NF_MATCH_HASHLIMIT=m
366CONFIG_IP_NF_MATCH_STRING=m
507CONFIG_IP_NF_FILTER=m 367CONFIG_IP_NF_FILTER=m
508CONFIG_IP_NF_TARGET_REJECT=m 368CONFIG_IP_NF_TARGET_REJECT=m
509CONFIG_IP_NF_TARGET_LOG=m 369CONFIG_IP_NF_TARGET_LOG=m
@@ -520,12 +380,14 @@ CONFIG_IP_NF_NAT_IRC=m
520CONFIG_IP_NF_NAT_FTP=m 380CONFIG_IP_NF_NAT_FTP=m
521CONFIG_IP_NF_NAT_TFTP=m 381CONFIG_IP_NF_NAT_TFTP=m
522CONFIG_IP_NF_NAT_AMANDA=m 382CONFIG_IP_NF_NAT_AMANDA=m
383CONFIG_IP_NF_NAT_PPTP=m
523CONFIG_IP_NF_MANGLE=m 384CONFIG_IP_NF_MANGLE=m
524CONFIG_IP_NF_TARGET_TOS=m 385CONFIG_IP_NF_TARGET_TOS=m
525CONFIG_IP_NF_TARGET_ECN=m 386CONFIG_IP_NF_TARGET_ECN=m
526CONFIG_IP_NF_TARGET_DSCP=m 387CONFIG_IP_NF_TARGET_DSCP=m
527CONFIG_IP_NF_TARGET_MARK=m 388CONFIG_IP_NF_TARGET_MARK=m
528CONFIG_IP_NF_TARGET_CLASSIFY=m 389CONFIG_IP_NF_TARGET_CLASSIFY=m
390CONFIG_IP_NF_TARGET_TTL=m
529CONFIG_IP_NF_TARGET_CONNMARK=m 391CONFIG_IP_NF_TARGET_CONNMARK=m
530CONFIG_IP_NF_TARGET_CLUSTERIP=m 392CONFIG_IP_NF_TARGET_CLUSTERIP=m
531CONFIG_IP_NF_RAW=m 393CONFIG_IP_NF_RAW=m
@@ -535,7 +397,7 @@ CONFIG_IP_NF_ARPFILTER=m
535CONFIG_IP_NF_ARP_MANGLE=m 397CONFIG_IP_NF_ARP_MANGLE=m
536 398
537# 399#
538# IPv6: Netfilter Configuration 400# IPv6: Netfilter Configuration (EXPERIMENTAL)
539# 401#
540CONFIG_IP6_NF_QUEUE=m 402CONFIG_IP6_NF_QUEUE=m
541CONFIG_IP6_NF_IPTABLES=m 403CONFIG_IP6_NF_IPTABLES=m
@@ -555,8 +417,10 @@ CONFIG_IP6_NF_MATCH_EUI64=m
555CONFIG_IP6_NF_MATCH_PHYSDEV=m 417CONFIG_IP6_NF_MATCH_PHYSDEV=m
556CONFIG_IP6_NF_FILTER=m 418CONFIG_IP6_NF_FILTER=m
557CONFIG_IP6_NF_TARGET_LOG=m 419CONFIG_IP6_NF_TARGET_LOG=m
420CONFIG_IP6_NF_TARGET_REJECT=m
558CONFIG_IP6_NF_MANGLE=m 421CONFIG_IP6_NF_MANGLE=m
559CONFIG_IP6_NF_TARGET_MARK=m 422CONFIG_IP6_NF_TARGET_MARK=m
423CONFIG_IP6_NF_TARGET_HL=m
560CONFIG_IP6_NF_RAW=m 424CONFIG_IP6_NF_RAW=m
561 425
562# 426#
@@ -582,8 +446,11 @@ CONFIG_BRIDGE_EBT_REDIRECT=m
582CONFIG_BRIDGE_EBT_SNAT=m 446CONFIG_BRIDGE_EBT_SNAT=m
583CONFIG_BRIDGE_EBT_LOG=m 447CONFIG_BRIDGE_EBT_LOG=m
584CONFIG_BRIDGE_EBT_ULOG=m 448CONFIG_BRIDGE_EBT_ULOG=m
585CONFIG_XFRM=y 449
586CONFIG_XFRM_USER=m 450#
451# DCCP Configuration (EXPERIMENTAL)
452#
453# CONFIG_IP_DCCP is not set
587 454
588# 455#
589# SCTP Configuration (EXPERIMENTAL) 456# SCTP Configuration (EXPERIMENTAL)
@@ -611,10 +478,6 @@ CONFIG_IPDDP_DECAP=y
611CONFIG_NET_DIVERT=y 478CONFIG_NET_DIVERT=y
612# CONFIG_ECONET is not set 479# CONFIG_ECONET is not set
613# CONFIG_WAN_ROUTER is not set 480# CONFIG_WAN_ROUTER is not set
614
615#
616# QoS and/or fair queueing
617#
618CONFIG_NET_SCHED=y 481CONFIG_NET_SCHED=y
619CONFIG_NET_SCH_CLK_JIFFIES=y 482CONFIG_NET_SCH_CLK_JIFFIES=y
620# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set 483# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
@@ -634,6 +497,7 @@ CONFIG_NET_SCH_INGRESS=m
634CONFIG_NET_QOS=y 497CONFIG_NET_QOS=y
635CONFIG_NET_ESTIMATOR=y 498CONFIG_NET_ESTIMATOR=y
636CONFIG_NET_CLS=y 499CONFIG_NET_CLS=y
500CONFIG_NET_CLS_BASIC=m
637CONFIG_NET_CLS_TCINDEX=m 501CONFIG_NET_CLS_TCINDEX=m
638CONFIG_NET_CLS_ROUTE4=m 502CONFIG_NET_CLS_ROUTE4=m
639CONFIG_NET_CLS_ROUTE=y 503CONFIG_NET_CLS_ROUTE=y
@@ -644,6 +508,7 @@ CONFIG_NET_CLS_IND=y
644# CONFIG_CLS_U32_MARK is not set 508# CONFIG_CLS_U32_MARK is not set
645CONFIG_NET_CLS_RSVP=m 509CONFIG_NET_CLS_RSVP=m
646CONFIG_NET_CLS_RSVP6=m 510CONFIG_NET_CLS_RSVP6=m
511# CONFIG_NET_EMATCH is not set
647# CONFIG_NET_CLS_ACT is not set 512# CONFIG_NET_CLS_ACT is not set
648CONFIG_NET_CLS_POLICE=y 513CONFIG_NET_CLS_POLICE=y
649 514
@@ -651,17 +516,254 @@ CONFIG_NET_CLS_POLICE=y
651# Network testing 516# Network testing
652# 517#
653# CONFIG_NET_PKTGEN is not set 518# CONFIG_NET_PKTGEN is not set
654# CONFIG_NETPOLL is not set
655# CONFIG_NET_POLL_CONTROLLER is not set
656# CONFIG_HAMRADIO is not set 519# CONFIG_HAMRADIO is not set
657# CONFIG_IRDA is not set 520# CONFIG_IRDA is not set
658# CONFIG_BT is not set 521# CONFIG_BT is not set
522CONFIG_IEEE80211=m
523# CONFIG_IEEE80211_DEBUG is not set
524CONFIG_IEEE80211_CRYPT_WEP=m
525CONFIG_IEEE80211_CRYPT_CCMP=m
526CONFIG_IEEE80211_CRYPT_TKIP=m
527
528#
529# Device Drivers
530#
531
532#
533# Generic Driver Options
534#
535CONFIG_STANDALONE=y
536CONFIG_PREVENT_FIRMWARE_BUILD=y
537CONFIG_FW_LOADER=y
538
539#
540# Connector - unified userspace <-> kernelspace linker
541#
542CONFIG_CONNECTOR=m
543
544#
545# Memory Technology Devices (MTD)
546#
547# CONFIG_MTD is not set
548
549#
550# Parallel port support
551#
552# CONFIG_PARPORT is not set
553
554#
555# Plug and Play support
556#
557
558#
559# Block devices
560#
561CONFIG_BLK_DEV_FD=m
562# CONFIG_BLK_CPQ_DA is not set
563# CONFIG_BLK_CPQ_CISS_DA is not set
564# CONFIG_BLK_DEV_DAC960 is not set
565CONFIG_BLK_DEV_UMEM=m
566# CONFIG_BLK_DEV_COW_COMMON is not set
567CONFIG_BLK_DEV_LOOP=m
568CONFIG_BLK_DEV_CRYPTOLOOP=m
569CONFIG_BLK_DEV_NBD=m
570# CONFIG_BLK_DEV_SX8 is not set
571CONFIG_BLK_DEV_RAM=y
572CONFIG_BLK_DEV_RAM_COUNT=16
573CONFIG_BLK_DEV_RAM_SIZE=4096
574# CONFIG_BLK_DEV_INITRD is not set
575# CONFIG_LBD is not set
576CONFIG_CDROM_PKTCDVD=m
577CONFIG_CDROM_PKTCDVD_BUFFERS=8
578# CONFIG_CDROM_PKTCDVD_WCACHE is not set
579
580#
581# IO Schedulers
582#
583CONFIG_IOSCHED_NOOP=y
584CONFIG_IOSCHED_AS=y
585CONFIG_IOSCHED_DEADLINE=y
586CONFIG_IOSCHED_CFQ=y
587CONFIG_ATA_OVER_ETH=m
588
589#
590# ATA/ATAPI/MFM/RLL support
591#
592CONFIG_IDE=y
593CONFIG_BLK_DEV_IDE=y
594
595#
596# Please see Documentation/ide.txt for help/info on IDE drives
597#
598# CONFIG_BLK_DEV_IDE_SATA is not set
599CONFIG_BLK_DEV_IDEDISK=y
600# CONFIG_IDEDISK_MULTI_MODE is not set
601CONFIG_BLK_DEV_IDECD=y
602# CONFIG_BLK_DEV_IDETAPE is not set
603# CONFIG_BLK_DEV_IDEFLOPPY is not set
604# CONFIG_BLK_DEV_IDESCSI is not set
605# CONFIG_IDE_TASK_IOCTL is not set
606
607#
608# IDE chipset support/bugfixes
609#
610CONFIG_IDE_GENERIC=y
611CONFIG_BLK_DEV_IDEPCI=y
612# CONFIG_IDEPCI_SHARE_IRQ is not set
613# CONFIG_BLK_DEV_OFFBOARD is not set
614CONFIG_BLK_DEV_GENERIC=y
615# CONFIG_BLK_DEV_OPTI621 is not set
616CONFIG_BLK_DEV_IDEDMA_PCI=y
617# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
618CONFIG_IDEDMA_PCI_AUTO=y
619# CONFIG_IDEDMA_ONLYDISK is not set
620# CONFIG_BLK_DEV_AEC62XX is not set
621# CONFIG_BLK_DEV_ALI15X3 is not set
622# CONFIG_BLK_DEV_AMD74XX is not set
623# CONFIG_BLK_DEV_CMD64X is not set
624# CONFIG_BLK_DEV_TRIFLEX is not set
625# CONFIG_BLK_DEV_CY82C693 is not set
626# CONFIG_BLK_DEV_CS5520 is not set
627# CONFIG_BLK_DEV_CS5530 is not set
628# CONFIG_BLK_DEV_HPT34X is not set
629# CONFIG_BLK_DEV_HPT366 is not set
630# CONFIG_BLK_DEV_SC1200 is not set
631CONFIG_BLK_DEV_PIIX=y
632# CONFIG_BLK_DEV_IT821X is not set
633# CONFIG_BLK_DEV_NS87415 is not set
634# CONFIG_BLK_DEV_PDC202XX_OLD is not set
635# CONFIG_BLK_DEV_PDC202XX_NEW is not set
636# CONFIG_BLK_DEV_SVWKS is not set
637# CONFIG_BLK_DEV_SIIMAGE is not set
638# CONFIG_BLK_DEV_SLC90E66 is not set
639# CONFIG_BLK_DEV_TRM290 is not set
640# CONFIG_BLK_DEV_VIA82CXXX is not set
641# CONFIG_IDE_ARM is not set
642CONFIG_BLK_DEV_IDEDMA=y
643# CONFIG_IDEDMA_IVB is not set
644CONFIG_IDEDMA_AUTO=y
645# CONFIG_BLK_DEV_HD is not set
646
647#
648# SCSI device support
649#
650CONFIG_RAID_ATTRS=m
651CONFIG_SCSI=m
652CONFIG_SCSI_PROC_FS=y
653
654#
655# SCSI support type (disk, tape, CD-ROM)
656#
657CONFIG_BLK_DEV_SD=m
658CONFIG_CHR_DEV_ST=m
659CONFIG_CHR_DEV_OSST=m
660CONFIG_BLK_DEV_SR=m
661CONFIG_BLK_DEV_SR_VENDOR=y
662CONFIG_CHR_DEV_SG=m
663# CONFIG_CHR_DEV_SCH is not set
664
665#
666# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
667#
668CONFIG_SCSI_MULTI_LUN=y
669CONFIG_SCSI_CONSTANTS=y
670CONFIG_SCSI_LOGGING=y
671
672#
673# SCSI Transport Attributes
674#
675CONFIG_SCSI_SPI_ATTRS=m
676CONFIG_SCSI_FC_ATTRS=m
677CONFIG_SCSI_ISCSI_ATTRS=m
678CONFIG_SCSI_SAS_ATTRS=m
679
680#
681# SCSI low-level drivers
682#
683CONFIG_BLK_DEV_3W_XXXX_RAID=m
684CONFIG_SCSI_3W_9XXX=m
685CONFIG_SCSI_ACARD=m
686CONFIG_SCSI_AACRAID=m
687CONFIG_SCSI_AIC7XXX=m
688CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
689CONFIG_AIC7XXX_RESET_DELAY_MS=15000
690# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
691CONFIG_AIC7XXX_DEBUG_MASK=0
692CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
693# CONFIG_SCSI_AIC7XXX_OLD is not set
694# CONFIG_SCSI_AIC79XX is not set
695# CONFIG_SCSI_DPT_I2O is not set
696# CONFIG_MEGARAID_NEWGEN is not set
697# CONFIG_MEGARAID_LEGACY is not set
698# CONFIG_SCSI_SATA is not set
699# CONFIG_SCSI_DMX3191D is not set
700# CONFIG_SCSI_FUTURE_DOMAIN is not set
701# CONFIG_SCSI_IPS is not set
702# CONFIG_SCSI_INITIO is not set
703# CONFIG_SCSI_INIA100 is not set
704# CONFIG_SCSI_SYM53C8XX_2 is not set
705# CONFIG_SCSI_IPR is not set
706# CONFIG_SCSI_QLOGIC_FC is not set
707# CONFIG_SCSI_QLOGIC_1280 is not set
708CONFIG_SCSI_QLA2XXX=m
709# CONFIG_SCSI_QLA21XX is not set
710# CONFIG_SCSI_QLA22XX is not set
711# CONFIG_SCSI_QLA2300 is not set
712# CONFIG_SCSI_QLA2322 is not set
713# CONFIG_SCSI_QLA6312 is not set
714# CONFIG_SCSI_QLA24XX is not set
715# CONFIG_SCSI_LPFC is not set
716# CONFIG_SCSI_DC395x is not set
717# CONFIG_SCSI_DC390T is not set
718# CONFIG_SCSI_NSP32 is not set
719# CONFIG_SCSI_DEBUG is not set
720
721#
722# Multi-device support (RAID and LVM)
723#
724CONFIG_MD=y
725CONFIG_BLK_DEV_MD=m
726CONFIG_MD_LINEAR=m
727CONFIG_MD_RAID0=m
728CONFIG_MD_RAID1=m
729CONFIG_MD_RAID10=m
730CONFIG_MD_RAID5=m
731CONFIG_MD_RAID6=m
732CONFIG_MD_MULTIPATH=m
733CONFIG_MD_FAULTY=m
734CONFIG_BLK_DEV_DM=m
735CONFIG_DM_CRYPT=m
736CONFIG_DM_SNAPSHOT=m
737CONFIG_DM_MIRROR=m
738CONFIG_DM_ZERO=m
739CONFIG_DM_MULTIPATH=m
740CONFIG_DM_MULTIPATH_EMC=m
741
742#
743# Fusion MPT device support
744#
745# CONFIG_FUSION is not set
746# CONFIG_FUSION_SPI is not set
747# CONFIG_FUSION_FC is not set
748
749#
750# IEEE 1394 (FireWire) support
751#
752# CONFIG_IEEE1394 is not set
753
754#
755# I2O device support
756#
757# CONFIG_I2O is not set
758
759#
760# Network device support
761#
659CONFIG_NETDEVICES=y 762CONFIG_NETDEVICES=y
660CONFIG_DUMMY=m 763CONFIG_DUMMY=m
661CONFIG_BONDING=m 764CONFIG_BONDING=m
662CONFIG_EQUALIZER=m 765CONFIG_EQUALIZER=m
663CONFIG_TUN=m 766CONFIG_TUN=m
664# CONFIG_ETHERTAP is not set
665 767
666# 768#
667# ARCnet devices 769# ARCnet devices
@@ -669,6 +771,21 @@ CONFIG_TUN=m
669# CONFIG_ARCNET is not set 771# CONFIG_ARCNET is not set
670 772
671# 773#
774# PHY device support
775#
776CONFIG_PHYLIB=m
777CONFIG_PHYCONTROL=y
778
779#
780# MII PHY device drivers
781#
782CONFIG_MARVELL_PHY=m
783CONFIG_DAVICOM_PHY=m
784CONFIG_QSEMI_PHY=m
785CONFIG_LXT_PHY=m
786CONFIG_CICADA_PHY=m
787
788#
672# Ethernet (10 or 100Mbit) 789# Ethernet (10 or 100Mbit)
673# 790#
674CONFIG_NET_ETHERNET=y 791CONFIG_NET_ETHERNET=y
@@ -713,13 +830,17 @@ CONFIG_PCNET32=y
713# CONFIG_HAMACHI is not set 830# CONFIG_HAMACHI is not set
714# CONFIG_YELLOWFIN is not set 831# CONFIG_YELLOWFIN is not set
715# CONFIG_R8169 is not set 832# CONFIG_R8169 is not set
833# CONFIG_SIS190 is not set
834# CONFIG_SKGE is not set
716# CONFIG_SK98LIN is not set 835# CONFIG_SK98LIN is not set
717# CONFIG_VIA_VELOCITY is not set 836# CONFIG_VIA_VELOCITY is not set
718# CONFIG_TIGON3 is not set 837# CONFIG_TIGON3 is not set
838# CONFIG_BNX2 is not set
719 839
720# 840#
721# Ethernet (10000 Mbit) 841# Ethernet (10000 Mbit)
722# 842#
843# CONFIG_CHELSIO_T1 is not set
723# CONFIG_IXGB is not set 844# CONFIG_IXGB is not set
724# CONFIG_S2IO is not set 845# CONFIG_S2IO is not set
725 846
@@ -732,6 +853,8 @@ CONFIG_PCNET32=y
732# Wireless LAN (non-hamradio) 853# Wireless LAN (non-hamradio)
733# 854#
734# CONFIG_NET_RADIO is not set 855# CONFIG_NET_RADIO is not set
856# CONFIG_IPW_DEBUG is not set
857CONFIG_IPW2200=m
735 858
736# 859#
737# Wan interfaces 860# Wan interfaces
@@ -744,6 +867,8 @@ CONFIG_PCNET32=y
744# CONFIG_NET_FC is not set 867# CONFIG_NET_FC is not set
745# CONFIG_SHAPER is not set 868# CONFIG_SHAPER is not set
746# CONFIG_NETCONSOLE is not set 869# CONFIG_NETCONSOLE is not set
870# CONFIG_NETPOLL is not set
871# CONFIG_NET_POLL_CONTROLLER is not set
747 872
748# 873#
749# ISDN subsystem 874# ISDN subsystem
@@ -773,19 +898,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
773# CONFIG_INPUT_EVBUG is not set 898# CONFIG_INPUT_EVBUG is not set
774 899
775# 900#
776# Input I/O drivers
777#
778# CONFIG_GAMEPORT is not set
779CONFIG_SOUND_GAMEPORT=y
780CONFIG_SERIO=y
781# CONFIG_SERIO_I8042 is not set
782CONFIG_SERIO_SERPORT=y
783# CONFIG_SERIO_CT82C710 is not set
784# CONFIG_SERIO_PCIPS2 is not set
785# CONFIG_SERIO_LIBPS2 is not set
786# CONFIG_SERIO_RAW is not set
787
788#
789# Input Device Drivers 901# Input Device Drivers
790# 902#
791# CONFIG_INPUT_KEYBOARD is not set 903# CONFIG_INPUT_KEYBOARD is not set
@@ -795,6 +907,17 @@ CONFIG_SERIO_SERPORT=y
795# CONFIG_INPUT_MISC is not set 907# CONFIG_INPUT_MISC is not set
796 908
797# 909#
910# Hardware I/O ports
911#
912CONFIG_SERIO=y
913# CONFIG_SERIO_I8042 is not set
914CONFIG_SERIO_SERPORT=y
915# CONFIG_SERIO_PCIPS2 is not set
916# CONFIG_SERIO_LIBPS2 is not set
917# CONFIG_SERIO_RAW is not set
918# CONFIG_GAMEPORT is not set
919
920#
798# Character devices 921# Character devices
799# 922#
800CONFIG_VT=y 923CONFIG_VT=y
@@ -815,6 +938,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
815# 938#
816CONFIG_SERIAL_CORE=y 939CONFIG_SERIAL_CORE=y
817CONFIG_SERIAL_CORE_CONSOLE=y 940CONFIG_SERIAL_CORE_CONSOLE=y
941# CONFIG_SERIAL_JSM is not set
818CONFIG_UNIX98_PTYS=y 942CONFIG_UNIX98_PTYS=y
819CONFIG_LEGACY_PTYS=y 943CONFIG_LEGACY_PTYS=y
820CONFIG_LEGACY_PTY_COUNT=256 944CONFIG_LEGACY_PTY_COUNT=256
@@ -840,6 +964,11 @@ CONFIG_RTC=y
840# CONFIG_RAW_DRIVER is not set 964# CONFIG_RAW_DRIVER is not set
841 965
842# 966#
967# TPM devices
968#
969# CONFIG_TCG_TPM is not set
970
971#
843# I2C support 972# I2C support
844# 973#
845# CONFIG_I2C is not set 974# CONFIG_I2C is not set
@@ -850,10 +979,20 @@ CONFIG_RTC=y
850# CONFIG_W1 is not set 979# CONFIG_W1 is not set
851 980
852# 981#
982# Hardware Monitoring support
983#
984# CONFIG_HWMON is not set
985# CONFIG_HWMON_VID is not set
986
987#
853# Misc devices 988# Misc devices
854# 989#
855 990
856# 991#
992# Multimedia Capabilities Port drivers
993#
994
995#
857# Multimedia devices 996# Multimedia devices
858# 997#
859# CONFIG_VIDEO_DEV is not set 998# CONFIG_VIDEO_DEV is not set
@@ -873,7 +1012,6 @@ CONFIG_RTC=y
873# 1012#
874# CONFIG_VGA_CONSOLE is not set 1013# CONFIG_VGA_CONSOLE is not set
875CONFIG_DUMMY_CONSOLE=y 1014CONFIG_DUMMY_CONSOLE=y
876# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
877 1015
878# 1016#
879# Sound 1017# Sound
@@ -883,13 +1021,9 @@ CONFIG_DUMMY_CONSOLE=y
883# 1021#
884# USB support 1022# USB support
885# 1023#
886# CONFIG_USB is not set
887CONFIG_USB_ARCH_HAS_HCD=y 1024CONFIG_USB_ARCH_HAS_HCD=y
888CONFIG_USB_ARCH_HAS_OHCI=y 1025CONFIG_USB_ARCH_HAS_OHCI=y
889 1026# CONFIG_USB is not set
890#
891# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
892#
893 1027
894# 1028#
895# USB Gadget Support 1029# USB Gadget Support
@@ -907,10 +1041,15 @@ CONFIG_USB_ARCH_HAS_OHCI=y
907# CONFIG_INFINIBAND is not set 1041# CONFIG_INFINIBAND is not set
908 1042
909# 1043#
1044# SN Devices
1045#
1046
1047#
910# File systems 1048# File systems
911# 1049#
912CONFIG_EXT2_FS=y 1050CONFIG_EXT2_FS=y
913# CONFIG_EXT2_FS_XATTR is not set 1051# CONFIG_EXT2_FS_XATTR is not set
1052# CONFIG_EXT2_FS_XIP is not set
914CONFIG_EXT3_FS=y 1053CONFIG_EXT3_FS=y
915CONFIG_EXT3_FS_XATTR=y 1054CONFIG_EXT3_FS_XATTR=y
916# CONFIG_EXT3_FS_POSIX_ACL is not set 1055# CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -931,12 +1070,14 @@ CONFIG_JFS_SECURITY=y
931# CONFIG_JFS_STATISTICS is not set 1070# CONFIG_JFS_STATISTICS is not set
932CONFIG_FS_POSIX_ACL=y 1071CONFIG_FS_POSIX_ACL=y
933CONFIG_XFS_FS=m 1072CONFIG_XFS_FS=m
934# CONFIG_XFS_RT is not set 1073CONFIG_XFS_EXPORT=y
935CONFIG_XFS_QUOTA=y 1074CONFIG_XFS_QUOTA=m
936CONFIG_XFS_SECURITY=y 1075CONFIG_XFS_SECURITY=y
937CONFIG_XFS_POSIX_ACL=y 1076CONFIG_XFS_POSIX_ACL=y
1077# CONFIG_XFS_RT is not set
938CONFIG_MINIX_FS=m 1078CONFIG_MINIX_FS=m
939CONFIG_ROMFS_FS=m 1079CONFIG_ROMFS_FS=m
1080CONFIG_INOTIFY=y
940CONFIG_QUOTA=y 1081CONFIG_QUOTA=y
941# CONFIG_QFMT_V1 is not set 1082# CONFIG_QFMT_V1 is not set
942CONFIG_QFMT_V2=y 1083CONFIG_QFMT_V2=y
@@ -944,6 +1085,7 @@ CONFIG_QUOTACTL=y
944CONFIG_DNOTIFY=y 1085CONFIG_DNOTIFY=y
945CONFIG_AUTOFS_FS=y 1086CONFIG_AUTOFS_FS=y
946# CONFIG_AUTOFS4_FS is not set 1087# CONFIG_AUTOFS4_FS is not set
1088CONFIG_FUSE_FS=m
947 1089
948# 1090#
949# CD-ROM/DVD Filesystems 1091# CD-ROM/DVD Filesystems
@@ -971,12 +1113,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
971CONFIG_PROC_FS=y 1113CONFIG_PROC_FS=y
972CONFIG_PROC_KCORE=y 1114CONFIG_PROC_KCORE=y
973CONFIG_SYSFS=y 1115CONFIG_SYSFS=y
974# CONFIG_DEVFS_FS is not set
975CONFIG_DEVPTS_FS_XATTR=y
976CONFIG_DEVPTS_FS_SECURITY=y
977# CONFIG_TMPFS is not set 1116# CONFIG_TMPFS is not set
978# CONFIG_HUGETLB_PAGE is not set 1117# CONFIG_HUGETLB_PAGE is not set
979CONFIG_RAMFS=y 1118CONFIG_RAMFS=y
1119CONFIG_RELAYFS_FS=m
980 1120
981# 1121#
982# Miscellaneous filesystems 1122# Miscellaneous filesystems
@@ -1002,16 +1142,19 @@ CONFIG_UFS_FS=m
1002# 1142#
1003CONFIG_NFS_FS=y 1143CONFIG_NFS_FS=y
1004CONFIG_NFS_V3=y 1144CONFIG_NFS_V3=y
1145# CONFIG_NFS_V3_ACL is not set
1005# CONFIG_NFS_V4 is not set 1146# CONFIG_NFS_V4 is not set
1006# CONFIG_NFS_DIRECTIO is not set 1147# CONFIG_NFS_DIRECTIO is not set
1007CONFIG_NFSD=y 1148CONFIG_NFSD=y
1008CONFIG_NFSD_V3=y 1149CONFIG_NFSD_V3=y
1150# CONFIG_NFSD_V3_ACL is not set
1009# CONFIG_NFSD_V4 is not set 1151# CONFIG_NFSD_V4 is not set
1010# CONFIG_NFSD_TCP is not set 1152# CONFIG_NFSD_TCP is not set
1011CONFIG_ROOT_NFS=y 1153CONFIG_ROOT_NFS=y
1012CONFIG_LOCKD=y 1154CONFIG_LOCKD=y
1013CONFIG_LOCKD_V4=y 1155CONFIG_LOCKD_V4=y
1014CONFIG_EXPORTFS=y 1156CONFIG_EXPORTFS=y
1157CONFIG_NFS_COMMON=y
1015CONFIG_SUNRPC=y 1158CONFIG_SUNRPC=y
1016# CONFIG_RPCSEC_GSS_KRB5 is not set 1159# CONFIG_RPCSEC_GSS_KRB5 is not set
1017# CONFIG_RPCSEC_GSS_SPKM3 is not set 1160# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -1020,6 +1163,7 @@ CONFIG_SUNRPC=y
1020# CONFIG_NCP_FS is not set 1163# CONFIG_NCP_FS is not set
1021# CONFIG_CODA_FS is not set 1164# CONFIG_CODA_FS is not set
1022# CONFIG_AFS_FS is not set 1165# CONFIG_AFS_FS is not set
1166# CONFIG_9P_FS is not set
1023 1167
1024# 1168#
1025# Partition Types 1169# Partition Types
@@ -1079,7 +1223,9 @@ CONFIG_NLS_UTF8=m
1079# 1223#
1080# Kernel hacking 1224# Kernel hacking
1081# 1225#
1226# CONFIG_PRINTK_TIME is not set
1082# CONFIG_DEBUG_KERNEL is not set 1227# CONFIG_DEBUG_KERNEL is not set
1228CONFIG_LOG_BUF_SHIFT=14
1083CONFIG_CROSSCOMPILE=y 1229CONFIG_CROSSCOMPILE=y
1084CONFIG_CMDLINE="" 1230CONFIG_CMDLINE=""
1085 1231
@@ -1101,6 +1247,7 @@ CONFIG_CRYPTO_SHA1=m
1101CONFIG_CRYPTO_SHA256=m 1247CONFIG_CRYPTO_SHA256=m
1102CONFIG_CRYPTO_SHA512=m 1248CONFIG_CRYPTO_SHA512=m
1103CONFIG_CRYPTO_WP512=m 1249CONFIG_CRYPTO_WP512=m
1250CONFIG_CRYPTO_TGR192=m
1104CONFIG_CRYPTO_DES=m 1251CONFIG_CRYPTO_DES=m
1105CONFIG_CRYPTO_BLOWFISH=m 1252CONFIG_CRYPTO_BLOWFISH=m
1106CONFIG_CRYPTO_TWOFISH=m 1253CONFIG_CRYPTO_TWOFISH=m
@@ -1125,9 +1272,12 @@ CONFIG_CRYPTO_CRC32C=m
1125# Library routines 1272# Library routines
1126# 1273#
1127# CONFIG_CRC_CCITT is not set 1274# CONFIG_CRC_CCITT is not set
1275CONFIG_CRC16=m
1128CONFIG_CRC32=y 1276CONFIG_CRC32=y
1129CONFIG_LIBCRC32C=m 1277CONFIG_LIBCRC32C=m
1130CONFIG_ZLIB_INFLATE=m 1278CONFIG_ZLIB_INFLATE=m
1131CONFIG_ZLIB_DEFLATE=m 1279CONFIG_ZLIB_DEFLATE=m
1132CONFIG_GENERIC_HARDIRQS=y 1280CONFIG_TEXTSEARCH=y
1133CONFIG_GENERIC_IRQ_PROBE=y 1281CONFIG_TEXTSEARCH_KMP=m
1282CONFIG_TEXTSEARCH_BM=m
1283CONFIG_TEXTSEARCH_FSM=m
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
new file mode 100644
index 000000000000..fb9bdd9e3151
--- /dev/null
+++ b/arch/mips/configs/mipssim_defconfig
@@ -0,0 +1,775 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.14-rc2
4# Thu Oct 20 22:26:25 2005
5#
6CONFIG_MIPS=y
7
8#
9# Code maturity level options
10#
11CONFIG_EXPERIMENTAL=y
12CONFIG_CLEAN_COMPILE=y
13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
15
16#
17# General setup
18#
19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
21CONFIG_SWAP=y
22CONFIG_SYSVIPC=y
23# CONFIG_POSIX_MQUEUE is not set
24# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set
27CONFIG_HOTPLUG=y
28CONFIG_KOBJECT_UEVENT=y
29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
31CONFIG_EMBEDDED=y
32CONFIG_KALLSYMS=y
33# CONFIG_KALLSYMS_ALL is not set
34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
38CONFIG_FUTEX=y
39CONFIG_EPOLL=y
40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
41CONFIG_SHMEM=y
42CONFIG_CC_ALIGN_FUNCTIONS=0
43CONFIG_CC_ALIGN_LABELS=0
44CONFIG_CC_ALIGN_LOOPS=0
45CONFIG_CC_ALIGN_JUMPS=0
46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
48
49#
50# Loadable module support
51#
52CONFIG_MODULES=y
53CONFIG_MODULE_UNLOAD=y
54# CONFIG_MODULE_FORCE_UNLOAD is not set
55CONFIG_OBSOLETE_MODPARM=y
56CONFIG_MODVERSIONS=y
57CONFIG_MODULE_SRCVERSION_ALL=y
58CONFIG_KMOD=y
59
60#
61# Machine selection
62#
63# CONFIG_MIPS_MTX1 is not set
64# CONFIG_MIPS_BOSPORUS is not set
65# CONFIG_MIPS_PB1000 is not set
66# CONFIG_MIPS_PB1100 is not set
67# CONFIG_MIPS_PB1500 is not set
68# CONFIG_MIPS_PB1550 is not set
69# CONFIG_MIPS_PB1200 is not set
70# CONFIG_MIPS_DB1000 is not set
71# CONFIG_MIPS_DB1100 is not set
72# CONFIG_MIPS_DB1500 is not set
73# CONFIG_MIPS_DB1550 is not set
74# CONFIG_MIPS_DB1200 is not set
75# CONFIG_MIPS_MIRAGE is not set
76# CONFIG_MIPS_COBALT is not set
77# CONFIG_MACH_DECSTATION is not set
78# CONFIG_MIPS_EV64120 is not set
79# CONFIG_MIPS_EV96100 is not set
80# CONFIG_MIPS_IVR is not set
81# CONFIG_MIPS_ITE8172 is not set
82# CONFIG_MACH_JAZZ is not set
83# CONFIG_LASAT is not set
84# CONFIG_MIPS_ATLAS is not set
85# CONFIG_MIPS_MALTA is not set
86# CONFIG_MIPS_SEAD is not set
87CONFIG_MIPS_SIM=y
88# CONFIG_MOMENCO_JAGUAR_ATX is not set
89# CONFIG_MOMENCO_OCELOT is not set
90# CONFIG_MOMENCO_OCELOT_3 is not set
91# CONFIG_MOMENCO_OCELOT_C is not set
92# CONFIG_MOMENCO_OCELOT_G is not set
93# CONFIG_MIPS_XXS1500 is not set
94# CONFIG_PNX8550_V2PCI is not set
95# CONFIG_PNX8550_JBS is not set
96# CONFIG_DDB5074 is not set
97# CONFIG_DDB5476 is not set
98# CONFIG_DDB5477 is not set
99# CONFIG_MACH_VR41XX is not set
100# CONFIG_PMC_YOSEMITE is not set
101# CONFIG_QEMU is not set
102# CONFIG_SGI_IP22 is not set
103# CONFIG_SGI_IP27 is not set
104# CONFIG_SGI_IP32 is not set
105# CONFIG_SIBYTE_BIGSUR is not set
106# CONFIG_SIBYTE_SWARM is not set
107# CONFIG_SIBYTE_SENTOSA is not set
108# CONFIG_SIBYTE_RHONE is not set
109# CONFIG_SIBYTE_CARMEL is not set
110# CONFIG_SIBYTE_PTSWARM is not set
111# CONFIG_SIBYTE_LITTLESUR is not set
112# CONFIG_SIBYTE_CRHINE is not set
113# CONFIG_SIBYTE_CRHONE is not set
114# CONFIG_SNI_RM200_PCI is not set
115# CONFIG_TOSHIBA_JMR3927 is not set
116# CONFIG_TOSHIBA_RBTX4927 is not set
117# CONFIG_TOSHIBA_RBTX4938 is not set
118CONFIG_RWSEM_GENERIC_SPINLOCK=y
119CONFIG_GENERIC_CALIBRATE_DELAY=y
120CONFIG_DMA_NONCOHERENT=y
121CONFIG_DMA_NEED_PCI_MAP_STATE=y
122# CONFIG_CPU_BIG_ENDIAN is not set
123CONFIG_CPU_LITTLE_ENDIAN=y
124CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
125CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
126CONFIG_IRQ_CPU=y
127CONFIG_MIPS_L1_CACHE_SHIFT=5
128
129#
130# CPU selection
131#
132CONFIG_CPU_MIPS32_R1=y
133# CONFIG_CPU_MIPS32_R2 is not set
134# CONFIG_CPU_MIPS64_R1 is not set
135# CONFIG_CPU_MIPS64_R2 is not set
136# CONFIG_CPU_R3000 is not set
137# CONFIG_CPU_TX39XX is not set
138# CONFIG_CPU_VR41XX is not set
139# CONFIG_CPU_R4300 is not set
140# CONFIG_CPU_R4X00 is not set
141# CONFIG_CPU_TX49XX is not set
142# CONFIG_CPU_R5000 is not set
143# CONFIG_CPU_R5432 is not set
144# CONFIG_CPU_R6000 is not set
145# CONFIG_CPU_NEVADA is not set
146# CONFIG_CPU_R8000 is not set
147# CONFIG_CPU_R10000 is not set
148# CONFIG_CPU_RM7000 is not set
149# CONFIG_CPU_RM9000 is not set
150# CONFIG_CPU_SB1 is not set
151CONFIG_SYS_HAS_CPU_MIPS32_R1=y
152CONFIG_SYS_HAS_CPU_MIPS32_R2=y
153CONFIG_CPU_MIPS32=y
154CONFIG_CPU_MIPSR1=y
155CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
156CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
157
158#
159# Kernel type
160#
161CONFIG_32BIT=y
162# CONFIG_64BIT is not set
163CONFIG_PAGE_SIZE_4KB=y
164# CONFIG_PAGE_SIZE_8KB is not set
165# CONFIG_PAGE_SIZE_16KB is not set
166# CONFIG_PAGE_SIZE_64KB is not set
167CONFIG_CPU_HAS_PREFETCH=y
168CONFIG_MIPS_MT=y
169# CONFIG_MIPS_MT_SMP is not set
170CONFIG_MIPS_VPE_LOADER=y
171CONFIG_MIPS_VPE_LOADER_TOM=y
172CONFIG_MIPS_VPE_APSP_API=y
173# CONFIG_64BIT_PHYS_ADDR is not set
174# CONFIG_CPU_ADVANCED is not set
175CONFIG_CPU_HAS_LLSC=y
176CONFIG_CPU_HAS_SYNC=y
177CONFIG_GENERIC_HARDIRQS=y
178CONFIG_GENERIC_IRQ_PROBE=y
179CONFIG_ARCH_FLATMEM_ENABLE=y
180CONFIG_SELECT_MEMORY_MODEL=y
181CONFIG_FLATMEM_MANUAL=y
182# CONFIG_DISCONTIGMEM_MANUAL is not set
183# CONFIG_SPARSEMEM_MANUAL is not set
184CONFIG_FLATMEM=y
185CONFIG_FLAT_NODE_MEM_MAP=y
186# CONFIG_SPARSEMEM_STATIC is not set
187CONFIG_PREEMPT_NONE=y
188# CONFIG_PREEMPT_VOLUNTARY is not set
189# CONFIG_PREEMPT is not set
190
191#
192# Bus options (PCI, PCMCIA, EISA, ISA, TC)
193#
194CONFIG_MMU=y
195
196#
197# PCCARD (PCMCIA/CardBus) support
198#
199# CONFIG_PCCARD is not set
200
201#
202# PCI Hotplug Support
203#
204
205#
206# Executable file formats
207#
208CONFIG_BINFMT_ELF=y
209# CONFIG_BINFMT_MISC is not set
210CONFIG_TRAD_SIGNALS=y
211
212#
213# Networking
214#
215CONFIG_NET=y
216
217#
218# Networking options
219#
220CONFIG_PACKET=y
221CONFIG_PACKET_MMAP=y
222CONFIG_UNIX=y
223CONFIG_XFRM=y
224# CONFIG_XFRM_USER is not set
225CONFIG_NET_KEY=y
226CONFIG_INET=y
227CONFIG_IP_MULTICAST=y
228CONFIG_IP_ADVANCED_ROUTER=y
229CONFIG_ASK_IP_FIB_HASH=y
230# CONFIG_IP_FIB_TRIE is not set
231CONFIG_IP_FIB_HASH=y
232CONFIG_IP_MULTIPLE_TABLES=y
233CONFIG_IP_ROUTE_MULTIPATH=y
234# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
235CONFIG_IP_ROUTE_VERBOSE=y
236CONFIG_IP_PNP=y
237CONFIG_IP_PNP_DHCP=y
238CONFIG_IP_PNP_BOOTP=y
239# CONFIG_IP_PNP_RARP is not set
240# CONFIG_NET_IPIP is not set
241# CONFIG_NET_IPGRE is not set
242CONFIG_IP_MROUTE=y
243CONFIG_IP_PIMSM_V1=y
244CONFIG_IP_PIMSM_V2=y
245# CONFIG_ARPD is not set
246CONFIG_SYN_COOKIES=y
247# CONFIG_INET_AH is not set
248# CONFIG_INET_ESP is not set
249# CONFIG_INET_IPCOMP is not set
250# CONFIG_INET_TUNNEL is not set
251CONFIG_INET_DIAG=y
252CONFIG_INET_TCP_DIAG=y
253# CONFIG_TCP_CONG_ADVANCED is not set
254CONFIG_TCP_CONG_BIC=y
255# CONFIG_IPV6 is not set
256# CONFIG_NETFILTER is not set
257
258#
259# DCCP Configuration (EXPERIMENTAL)
260#
261# CONFIG_IP_DCCP is not set
262
263#
264# SCTP Configuration (EXPERIMENTAL)
265#
266CONFIG_IP_SCTP=m
267# CONFIG_SCTP_DBG_MSG is not set
268# CONFIG_SCTP_DBG_OBJCNT is not set
269# CONFIG_SCTP_HMAC_NONE is not set
270# CONFIG_SCTP_HMAC_SHA1 is not set
271CONFIG_SCTP_HMAC_MD5=y
272# CONFIG_ATM is not set
273# CONFIG_BRIDGE is not set
274# CONFIG_VLAN_8021Q is not set
275# CONFIG_DECNET is not set
276# CONFIG_LLC2 is not set
277# CONFIG_IPX is not set
278# CONFIG_ATALK is not set
279# CONFIG_X25 is not set
280# CONFIG_LAPB is not set
281CONFIG_NET_DIVERT=y
282# CONFIG_ECONET is not set
283# CONFIG_WAN_ROUTER is not set
284CONFIG_NET_SCHED=y
285CONFIG_NET_SCH_CLK_JIFFIES=y
286# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
287# CONFIG_NET_SCH_CLK_CPU is not set
288CONFIG_NET_SCH_CBQ=m
289CONFIG_NET_SCH_HTB=m
290CONFIG_NET_SCH_HFSC=m
291CONFIG_NET_SCH_PRIO=m
292CONFIG_NET_SCH_RED=m
293CONFIG_NET_SCH_SFQ=m
294CONFIG_NET_SCH_TEQL=m
295CONFIG_NET_SCH_TBF=m
296CONFIG_NET_SCH_GRED=m
297CONFIG_NET_SCH_DSMARK=m
298CONFIG_NET_SCH_NETEM=m
299CONFIG_NET_SCH_INGRESS=m
300CONFIG_NET_QOS=y
301CONFIG_NET_ESTIMATOR=y
302CONFIG_NET_CLS=y
303CONFIG_NET_CLS_BASIC=m
304CONFIG_NET_CLS_TCINDEX=m
305CONFIG_NET_CLS_ROUTE4=m
306CONFIG_NET_CLS_ROUTE=y
307# CONFIG_NET_CLS_FW is not set
308# CONFIG_NET_CLS_U32 is not set
309# CONFIG_NET_CLS_RSVP is not set
310# CONFIG_NET_CLS_RSVP6 is not set
311# CONFIG_NET_EMATCH is not set
312# CONFIG_NET_CLS_ACT is not set
313# CONFIG_NET_CLS_POLICE is not set
314
315#
316# Network testing
317#
318# CONFIG_NET_PKTGEN is not set
319# CONFIG_HAMRADIO is not set
320# CONFIG_IRDA is not set
321# CONFIG_BT is not set
322# CONFIG_IEEE80211 is not set
323
324#
325# Device Drivers
326#
327
328#
329# Generic Driver Options
330#
331# CONFIG_STANDALONE is not set
332# CONFIG_PREVENT_FIRMWARE_BUILD is not set
333# CONFIG_FW_LOADER is not set
334# CONFIG_DEBUG_DRIVER is not set
335
336#
337# Connector - unified userspace <-> kernelspace linker
338#
339# CONFIG_CONNECTOR is not set
340
341#
342# Memory Technology Devices (MTD)
343#
344# CONFIG_MTD is not set
345
346#
347# Parallel port support
348#
349# CONFIG_PARPORT is not set
350
351#
352# Plug and Play support
353#
354
355#
356# Block devices
357#
358# CONFIG_BLK_DEV_COW_COMMON is not set
359CONFIG_BLK_DEV_LOOP=y
360# CONFIG_BLK_DEV_CRYPTOLOOP is not set
361CONFIG_BLK_DEV_NBD=y
362# CONFIG_BLK_DEV_RAM is not set
363CONFIG_BLK_DEV_RAM_COUNT=16
364# CONFIG_LBD is not set
365# CONFIG_CDROM_PKTCDVD is not set
366
367#
368# IO Schedulers
369#
370CONFIG_IOSCHED_NOOP=y
371CONFIG_IOSCHED_AS=y
372CONFIG_IOSCHED_DEADLINE=y
373CONFIG_IOSCHED_CFQ=y
374# CONFIG_ATA_OVER_ETH is not set
375
376#
377# ATA/ATAPI/MFM/RLL support
378#
379# CONFIG_IDE is not set
380
381#
382# SCSI device support
383#
384# CONFIG_RAID_ATTRS is not set
385# CONFIG_SCSI is not set
386
387#
388# Multi-device support (RAID and LVM)
389#
390# CONFIG_MD is not set
391
392#
393# Fusion MPT device support
394#
395# CONFIG_FUSION is not set
396
397#
398# IEEE 1394 (FireWire) support
399#
400
401#
402# I2O device support
403#
404
405#
406# Network device support
407#
408CONFIG_NETDEVICES=y
409# CONFIG_DUMMY is not set
410# CONFIG_BONDING is not set
411# CONFIG_EQUALIZER is not set
412# CONFIG_TUN is not set
413
414#
415# PHY device support
416#
417
418#
419# Ethernet (10 or 100Mbit)
420#
421# CONFIG_NET_ETHERNET is not set
422# CONFIG_MIPS_SIM_NET is not set
423
424#
425# Ethernet (1000 Mbit)
426#
427
428#
429# Ethernet (10000 Mbit)
430#
431
432#
433# Token Ring devices
434#
435
436#
437# Wireless LAN (non-hamradio)
438#
439# CONFIG_NET_RADIO is not set
440
441#
442# Wan interfaces
443#
444# CONFIG_WAN is not set
445# CONFIG_PPP is not set
446# CONFIG_SLIP is not set
447# CONFIG_SHAPER is not set
448# CONFIG_NETCONSOLE is not set
449# CONFIG_NETPOLL is not set
450# CONFIG_NET_POLL_CONTROLLER is not set
451
452#
453# ISDN subsystem
454#
455# CONFIG_ISDN is not set
456
457#
458# Telephony Support
459#
460# CONFIG_PHONE is not set
461
462#
463# Input device support
464#
465CONFIG_INPUT=y
466
467#
468# Userland interfaces
469#
470# CONFIG_INPUT_MOUSEDEV is not set
471# CONFIG_INPUT_JOYDEV is not set
472# CONFIG_INPUT_TSDEV is not set
473# CONFIG_INPUT_EVDEV is not set
474# CONFIG_INPUT_EVBUG is not set
475
476#
477# Input Device Drivers
478#
479# CONFIG_INPUT_KEYBOARD is not set
480# CONFIG_INPUT_MOUSE is not set
481# CONFIG_INPUT_JOYSTICK is not set
482# CONFIG_INPUT_TOUCHSCREEN is not set
483# CONFIG_INPUT_MISC is not set
484
485#
486# Hardware I/O ports
487#
488CONFIG_SERIO=y
489# CONFIG_SERIO_I8042 is not set
490CONFIG_SERIO_SERPORT=y
491# CONFIG_SERIO_LIBPS2 is not set
492# CONFIG_SERIO_RAW is not set
493# CONFIG_GAMEPORT is not set
494
495#
496# Character devices
497#
498# CONFIG_VT is not set
499# CONFIG_SERIAL_NONSTANDARD is not set
500
501#
502# Serial drivers
503#
504CONFIG_SERIAL_8250=y
505CONFIG_SERIAL_8250_CONSOLE=y
506CONFIG_SERIAL_8250_NR_UARTS=1
507# CONFIG_SERIAL_8250_EXTENDED is not set
508
509#
510# Non-8250 serial port support
511#
512CONFIG_SERIAL_CORE=y
513CONFIG_SERIAL_CORE_CONSOLE=y
514CONFIG_UNIX98_PTYS=y
515CONFIG_LEGACY_PTYS=y
516CONFIG_LEGACY_PTY_COUNT=256
517
518#
519# IPMI
520#
521# CONFIG_IPMI_HANDLER is not set
522
523#
524# Watchdog Cards
525#
526# CONFIG_WATCHDOG is not set
527# CONFIG_RTC is not set
528# CONFIG_GEN_RTC is not set
529# CONFIG_DTLK is not set
530# CONFIG_R3964 is not set
531
532#
533# Ftape, the floppy tape device driver
534#
535# CONFIG_RAW_DRIVER is not set
536
537#
538# TPM devices
539#
540
541#
542# I2C support
543#
544# CONFIG_I2C is not set
545
546#
547# Dallas's 1-wire bus
548#
549# CONFIG_W1 is not set
550
551#
552# Hardware Monitoring support
553#
554# CONFIG_HWMON is not set
555# CONFIG_HWMON_VID is not set
556
557#
558# Misc devices
559#
560
561#
562# Multimedia Capabilities Port drivers
563#
564
565#
566# Multimedia devices
567#
568# CONFIG_VIDEO_DEV is not set
569
570#
571# Digital Video Broadcasting Devices
572#
573# CONFIG_DVB is not set
574
575#
576# Graphics support
577#
578# CONFIG_FB is not set
579
580#
581# Sound
582#
583# CONFIG_SOUND is not set
584
585#
586# USB support
587#
588# CONFIG_USB_ARCH_HAS_HCD is not set
589# CONFIG_USB_ARCH_HAS_OHCI is not set
590
591#
592# USB Gadget Support
593#
594# CONFIG_USB_GADGET is not set
595
596#
597# MMC/SD Card support
598#
599# CONFIG_MMC is not set
600
601#
602# InfiniBand support
603#
604
605#
606# SN Devices
607#
608
609#
610# File systems
611#
612CONFIG_EXT2_FS=y
613# CONFIG_EXT2_FS_XATTR is not set
614# CONFIG_EXT2_FS_XIP is not set
615# CONFIG_EXT3_FS is not set
616# CONFIG_JBD is not set
617# CONFIG_REISERFS_FS is not set
618# CONFIG_JFS_FS is not set
619# CONFIG_FS_POSIX_ACL is not set
620# CONFIG_XFS_FS is not set
621# CONFIG_MINIX_FS is not set
622CONFIG_ROMFS_FS=y
623# CONFIG_INOTIFY is not set
624# CONFIG_QUOTA is not set
625# CONFIG_DNOTIFY is not set
626# CONFIG_AUTOFS_FS is not set
627# CONFIG_AUTOFS4_FS is not set
628# CONFIG_FUSE_FS is not set
629
630#
631# CD-ROM/DVD Filesystems
632#
633# CONFIG_ISO9660_FS is not set
634# CONFIG_UDF_FS is not set
635
636#
637# DOS/FAT/NT Filesystems
638#
639# CONFIG_MSDOS_FS is not set
640# CONFIG_VFAT_FS is not set
641# CONFIG_NTFS_FS is not set
642
643#
644# Pseudo filesystems
645#
646CONFIG_PROC_FS=y
647# CONFIG_PROC_KCORE is not set
648# CONFIG_SYSFS is not set
649# CONFIG_TMPFS is not set
650# CONFIG_HUGETLB_PAGE is not set
651CONFIG_RAMFS=y
652# CONFIG_RELAYFS_FS is not set
653
654#
655# Miscellaneous filesystems
656#
657# CONFIG_ADFS_FS is not set
658# CONFIG_AFFS_FS is not set
659# CONFIG_HFS_FS is not set
660# CONFIG_HFSPLUS_FS is not set
661# CONFIG_BEFS_FS is not set
662# CONFIG_BFS_FS is not set
663# CONFIG_EFS_FS is not set
664# CONFIG_CRAMFS is not set
665# CONFIG_VXFS_FS is not set
666# CONFIG_HPFS_FS is not set
667# CONFIG_QNX4FS_FS is not set
668# CONFIG_SYSV_FS is not set
669# CONFIG_UFS_FS is not set
670
671#
672# Network File Systems
673#
674CONFIG_NFS_FS=y
675CONFIG_NFS_V3=y
676# CONFIG_NFS_V3_ACL is not set
677# CONFIG_NFS_V4 is not set
678# CONFIG_NFS_DIRECTIO is not set
679# CONFIG_NFSD is not set
680CONFIG_ROOT_NFS=y
681CONFIG_LOCKD=y
682CONFIG_LOCKD_V4=y
683CONFIG_NFS_COMMON=y
684CONFIG_SUNRPC=y
685# CONFIG_RPCSEC_GSS_KRB5 is not set
686# CONFIG_RPCSEC_GSS_SPKM3 is not set
687# CONFIG_SMB_FS is not set
688# CONFIG_CIFS is not set
689# CONFIG_NCP_FS is not set
690# CONFIG_CODA_FS is not set
691# CONFIG_AFS_FS is not set
692# CONFIG_9P_FS is not set
693
694#
695# Partition Types
696#
697# CONFIG_PARTITION_ADVANCED is not set
698CONFIG_MSDOS_PARTITION=y
699
700#
701# Native Language Support
702#
703# CONFIG_NLS is not set
704
705#
706# Profiling support
707#
708# CONFIG_PROFILING is not set
709
710#
711# Kernel hacking
712#
713# CONFIG_PRINTK_TIME is not set
714CONFIG_DEBUG_KERNEL=y
715# CONFIG_MAGIC_SYSRQ is not set
716CONFIG_LOG_BUF_SHIFT=14
717# CONFIG_DETECT_SOFTLOCKUP is not set
718# CONFIG_SCHEDSTATS is not set
719# CONFIG_DEBUG_SLAB is not set
720# CONFIG_DEBUG_SPINLOCK is not set
721# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
722# CONFIG_DEBUG_KOBJECT is not set
723CONFIG_DEBUG_INFO=y
724CONFIG_CROSSCOMPILE=y
725CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
726# CONFIG_DEBUG_STACK_USAGE is not set
727# CONFIG_KGDB is not set
728# CONFIG_RUNTIME_DEBUG is not set
729# CONFIG_MIPS_UNCACHED is not set
730
731#
732# Security options
733#
734# CONFIG_KEYS is not set
735
736#
737# Cryptographic options
738#
739CONFIG_CRYPTO=y
740CONFIG_CRYPTO_HMAC=y
741# CONFIG_CRYPTO_NULL is not set
742# CONFIG_CRYPTO_MD4 is not set
743CONFIG_CRYPTO_MD5=y
744# CONFIG_CRYPTO_SHA1 is not set
745# CONFIG_CRYPTO_SHA256 is not set
746# CONFIG_CRYPTO_SHA512 is not set
747# CONFIG_CRYPTO_WP512 is not set
748# CONFIG_CRYPTO_TGR192 is not set
749# CONFIG_CRYPTO_DES is not set
750# CONFIG_CRYPTO_BLOWFISH is not set
751# CONFIG_CRYPTO_TWOFISH is not set
752# CONFIG_CRYPTO_SERPENT is not set
753# CONFIG_CRYPTO_AES is not set
754# CONFIG_CRYPTO_CAST5 is not set
755# CONFIG_CRYPTO_CAST6 is not set
756# CONFIG_CRYPTO_TEA is not set
757# CONFIG_CRYPTO_ARC4 is not set
758# CONFIG_CRYPTO_KHAZAD is not set
759# CONFIG_CRYPTO_ANUBIS is not set
760# CONFIG_CRYPTO_DEFLATE is not set
761# CONFIG_CRYPTO_MICHAEL_MIC is not set
762# CONFIG_CRYPTO_CRC32C is not set
763# CONFIG_CRYPTO_TEST is not set
764
765#
766# Hardware crypto devices
767#
768
769#
770# Library routines
771#
772# CONFIG_CRC_CCITT is not set
773CONFIG_CRC16=y
774CONFIG_CRC32=y
775# CONFIG_LIBCRC32C is not set
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 0fea57ef18f2..e2c082128532 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:07 2005 4# Thu Oct 20 22:26:28 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,57 +59,86 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60CONFIG_MACH_VR41XX=y 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_NEC_CMBVR4133 is not set 64# CONFIG_MIPS_PB1000 is not set
62# CONFIG_CASIO_E55 is not set 65# CONFIG_MIPS_PB1100 is not set
63# CONFIG_IBM_WORKPAD is not set 66# CONFIG_MIPS_PB1500 is not set
64# CONFIG_TANBAC_TB0226 is not set 67# CONFIG_MIPS_PB1550 is not set
65# CONFIG_TANBAC_TB0229 is not set 68# CONFIG_MIPS_PB1200 is not set
66CONFIG_VICTOR_MPC30X=y 69# CONFIG_MIPS_DB1000 is not set
67# CONFIG_ZAO_CAPCELLA is not set 70# CONFIG_MIPS_DB1100 is not set
68CONFIG_PCI_VR41XX=y 71# CONFIG_MIPS_DB1500 is not set
69CONFIG_VRC4173=y 72# CONFIG_MIPS_DB1550 is not set
70# CONFIG_TOSHIBA_JMR3927 is not set 73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
71# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
72# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
73# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
74# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
75# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
76# CONFIG_LASAT is not set
77# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
78# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
79# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
80# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
81# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
82# CONFIG_MOMENCO_OCELOT_G is not set
83# CONFIG_MOMENCO_OCELOT_C is not set
84# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
85# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
86# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
87# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
88# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
89# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
90# CONFIG_NEC_OSPREY is not set 98CONFIG_MACH_VR41XX=y
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
91# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
92# CONFIG_SOC_AU1X00 is not set 102# CONFIG_SGI_IP27 is not set
93# CONFIG_SIBYTE_SB1xxx_SOC is not set 103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
94# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
95# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
117# CONFIG_NEC_CMBVR4133 is not set
118# CONFIG_CASIO_E55 is not set
119# CONFIG_IBM_WORKPAD is not set
120# CONFIG_TANBAC_TB022X is not set
121CONFIG_VICTOR_MPC30X=y
122# CONFIG_ZAO_CAPCELLA is not set
123CONFIG_PCI_VR41XX=y
124CONFIG_VRC4173=y
96CONFIG_RWSEM_GENERIC_SPINLOCK=y 125CONFIG_RWSEM_GENERIC_SPINLOCK=y
97CONFIG_GENERIC_CALIBRATE_DELAY=y 126CONFIG_GENERIC_CALIBRATE_DELAY=y
98CONFIG_HAVE_DEC_LOCK=y
99CONFIG_DMA_NONCOHERENT=y 127CONFIG_DMA_NONCOHERENT=y
100CONFIG_DMA_NEED_PCI_MAP_STATE=y 128CONFIG_DMA_NEED_PCI_MAP_STATE=y
129# CONFIG_CPU_BIG_ENDIAN is not set
101CONFIG_CPU_LITTLE_ENDIAN=y 130CONFIG_CPU_LITTLE_ENDIAN=y
131CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
102CONFIG_IRQ_CPU=y 132CONFIG_IRQ_CPU=y
103CONFIG_MIPS_L1_CACHE_SHIFT=5 133CONFIG_MIPS_L1_CACHE_SHIFT=5
104 134
105# 135#
106# CPU selection 136# CPU selection
107# 137#
108# CONFIG_CPU_MIPS32 is not set 138# CONFIG_CPU_MIPS32_R1 is not set
109# CONFIG_CPU_MIPS64 is not set 139# CONFIG_CPU_MIPS32_R2 is not set
140# CONFIG_CPU_MIPS64_R1 is not set
141# CONFIG_CPU_MIPS64_R2 is not set
110# CONFIG_CPU_R3000 is not set 142# CONFIG_CPU_R3000 is not set
111# CONFIG_CPU_TX39XX is not set 143# CONFIG_CPU_TX39XX is not set
112CONFIG_CPU_VR41XX=y 144CONFIG_CPU_VR41XX=y
@@ -122,12 +154,36 @@ CONFIG_CPU_VR41XX=y
122# CONFIG_CPU_RM7000 is not set 154# CONFIG_CPU_RM7000 is not set
123# CONFIG_CPU_RM9000 is not set 155# CONFIG_CPU_RM9000 is not set
124# CONFIG_CPU_SB1 is not set 156# CONFIG_CPU_SB1 is not set
157CONFIG_SYS_HAS_CPU_VR41XX=y
158CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
159CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
160CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
161CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
162
163#
164# Kernel type
165#
166CONFIG_32BIT=y
167# CONFIG_64BIT is not set
125CONFIG_PAGE_SIZE_4KB=y 168CONFIG_PAGE_SIZE_4KB=y
126# CONFIG_PAGE_SIZE_8KB is not set 169# CONFIG_PAGE_SIZE_8KB is not set
127# CONFIG_PAGE_SIZE_16KB is not set 170# CONFIG_PAGE_SIZE_16KB is not set
128# CONFIG_PAGE_SIZE_64KB is not set 171# CONFIG_PAGE_SIZE_64KB is not set
172# CONFIG_MIPS_MT is not set
129# CONFIG_CPU_ADVANCED is not set 173# CONFIG_CPU_ADVANCED is not set
130CONFIG_CPU_HAS_SYNC=y 174CONFIG_CPU_HAS_SYNC=y
175CONFIG_GENERIC_HARDIRQS=y
176CONFIG_GENERIC_IRQ_PROBE=y
177CONFIG_ARCH_FLATMEM_ENABLE=y
178CONFIG_SELECT_MEMORY_MODEL=y
179CONFIG_FLATMEM_MANUAL=y
180# CONFIG_DISCONTIGMEM_MANUAL is not set
181# CONFIG_SPARSEMEM_MANUAL is not set
182CONFIG_FLATMEM=y
183CONFIG_FLAT_NODE_MEM_MAP=y
184# CONFIG_SPARSEMEM_STATIC is not set
185CONFIG_PREEMPT_NONE=y
186# CONFIG_PREEMPT_VOLUNTARY is not set
131# CONFIG_PREEMPT is not set 187# CONFIG_PREEMPT is not set
132 188
133# 189#
@@ -136,17 +192,26 @@ CONFIG_CPU_HAS_SYNC=y
136CONFIG_HW_HAS_PCI=y 192CONFIG_HW_HAS_PCI=y
137CONFIG_PCI=y 193CONFIG_PCI=y
138CONFIG_PCI_LEGACY_PROC=y 194CONFIG_PCI_LEGACY_PROC=y
139CONFIG_PCI_NAMES=y
140CONFIG_MMU=y 195CONFIG_MMU=y
141 196
142# 197#
143# PCCARD (PCMCIA/CardBus) support 198# PCCARD (PCMCIA/CardBus) support
144# 199#
145# CONFIG_PCCARD is not set 200CONFIG_PCCARD=y
201# CONFIG_PCMCIA_DEBUG is not set
202CONFIG_PCMCIA=y
203CONFIG_PCMCIA_LOAD_CIS=y
204CONFIG_PCMCIA_IOCTL=y
205# CONFIG_CARDBUS is not set
146 206
147# 207#
148# PC-card bridges 208# PC-card bridges
149# 209#
210# CONFIG_YENTA is not set
211# CONFIG_PD6729 is not set
212# CONFIG_I82092 is not set
213# CONFIG_TCIC is not set
214CONFIG_PCMCIA_VRC4173=y
150 215
151# 216#
152# PCI Hotplug Support 217# PCI Hotplug Support
@@ -161,6 +226,78 @@ CONFIG_BINFMT_ELF=y
161CONFIG_TRAD_SIGNALS=y 226CONFIG_TRAD_SIGNALS=y
162 227
163# 228#
229# Networking
230#
231CONFIG_NET=y
232
233#
234# Networking options
235#
236CONFIG_PACKET=y
237CONFIG_PACKET_MMAP=y
238CONFIG_UNIX=y
239CONFIG_XFRM=y
240CONFIG_XFRM_USER=m
241CONFIG_NET_KEY=y
242CONFIG_INET=y
243CONFIG_IP_MULTICAST=y
244# CONFIG_IP_ADVANCED_ROUTER is not set
245CONFIG_IP_FIB_HASH=y
246# CONFIG_IP_PNP is not set
247# CONFIG_NET_IPIP is not set
248# CONFIG_NET_IPGRE is not set
249# CONFIG_IP_MROUTE is not set
250# CONFIG_ARPD is not set
251# CONFIG_SYN_COOKIES is not set
252# CONFIG_INET_AH is not set
253# CONFIG_INET_ESP is not set
254# CONFIG_INET_IPCOMP is not set
255CONFIG_INET_TUNNEL=m
256CONFIG_INET_DIAG=y
257CONFIG_INET_TCP_DIAG=y
258# CONFIG_TCP_CONG_ADVANCED is not set
259CONFIG_TCP_CONG_BIC=y
260# CONFIG_IPV6 is not set
261# CONFIG_NETFILTER is not set
262
263#
264# DCCP Configuration (EXPERIMENTAL)
265#
266# CONFIG_IP_DCCP is not set
267
268#
269# SCTP Configuration (EXPERIMENTAL)
270#
271# CONFIG_IP_SCTP is not set
272# CONFIG_ATM is not set
273# CONFIG_BRIDGE is not set
274# CONFIG_VLAN_8021Q is not set
275# CONFIG_DECNET is not set
276# CONFIG_LLC2 is not set
277# CONFIG_IPX is not set
278# CONFIG_ATALK is not set
279# CONFIG_X25 is not set
280# CONFIG_LAPB is not set
281# CONFIG_NET_DIVERT is not set
282# CONFIG_ECONET is not set
283# CONFIG_WAN_ROUTER is not set
284# CONFIG_NET_SCHED is not set
285# CONFIG_NET_CLS_ROUTE is not set
286
287#
288# Network testing
289#
290# CONFIG_NET_PKTGEN is not set
291# CONFIG_HAMRADIO is not set
292# CONFIG_IRDA is not set
293# CONFIG_BT is not set
294CONFIG_IEEE80211=m
295# CONFIG_IEEE80211_DEBUG is not set
296CONFIG_IEEE80211_CRYPT_WEP=m
297CONFIG_IEEE80211_CRYPT_CCMP=m
298CONFIG_IEEE80211_CRYPT_TKIP=m
299
300#
164# Device Drivers 301# Device Drivers
165# 302#
166 303
@@ -169,7 +306,12 @@ CONFIG_TRAD_SIGNALS=y
169# 306#
170CONFIG_STANDALONE=y 307CONFIG_STANDALONE=y
171CONFIG_PREVENT_FIRMWARE_BUILD=y 308CONFIG_PREVENT_FIRMWARE_BUILD=y
172# CONFIG_FW_LOADER is not set 309CONFIG_FW_LOADER=y
310
311#
312# Connector - unified userspace <-> kernelspace linker
313#
314CONFIG_CONNECTOR=m
173 315
174# 316#
175# Memory Technology Devices (MTD) 317# Memory Technology Devices (MTD)
@@ -188,7 +330,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
188# 330#
189# Block devices 331# Block devices
190# 332#
191# CONFIG_BLK_DEV_FD is not set
192# CONFIG_BLK_CPQ_DA is not set 333# CONFIG_BLK_CPQ_DA is not set
193# CONFIG_BLK_CPQ_CISS_DA is not set 334# CONFIG_BLK_CPQ_CISS_DA is not set
194# CONFIG_BLK_DEV_DAC960 is not set 335# CONFIG_BLK_DEV_DAC960 is not set
@@ -197,13 +338,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
197# CONFIG_BLK_DEV_LOOP is not set 338# CONFIG_BLK_DEV_LOOP is not set
198# CONFIG_BLK_DEV_NBD is not set 339# CONFIG_BLK_DEV_NBD is not set
199# CONFIG_BLK_DEV_SX8 is not set 340# CONFIG_BLK_DEV_SX8 is not set
341# CONFIG_BLK_DEV_UB is not set
200# CONFIG_BLK_DEV_RAM is not set 342# CONFIG_BLK_DEV_RAM is not set
201CONFIG_BLK_DEV_RAM_COUNT=16 343CONFIG_BLK_DEV_RAM_COUNT=16
202CONFIG_INITRAMFS_SOURCE=""
203# CONFIG_LBD is not set 344# CONFIG_LBD is not set
204CONFIG_CDROM_PKTCDVD=m 345# CONFIG_CDROM_PKTCDVD is not set
205CONFIG_CDROM_PKTCDVD_BUFFERS=8
206# CONFIG_CDROM_PKTCDVD_WCACHE is not set
207 346
208# 347#
209# IO Schedulers 348# IO Schedulers
@@ -217,11 +356,35 @@ CONFIG_ATA_OVER_ETH=m
217# 356#
218# ATA/ATAPI/MFM/RLL support 357# ATA/ATAPI/MFM/RLL support
219# 358#
220# CONFIG_IDE is not set 359CONFIG_IDE=y
360CONFIG_BLK_DEV_IDE=y
361
362#
363# Please see Documentation/ide.txt for help/info on IDE drives
364#
365# CONFIG_BLK_DEV_IDE_SATA is not set
366CONFIG_BLK_DEV_IDEDISK=y
367# CONFIG_IDEDISK_MULTI_MODE is not set
368CONFIG_BLK_DEV_IDECS=m
369# CONFIG_BLK_DEV_IDECD is not set
370# CONFIG_BLK_DEV_IDETAPE is not set
371# CONFIG_BLK_DEV_IDEFLOPPY is not set
372# CONFIG_IDE_TASK_IOCTL is not set
373
374#
375# IDE chipset support/bugfixes
376#
377CONFIG_IDE_GENERIC=y
378# CONFIG_BLK_DEV_IDEPCI is not set
379# CONFIG_IDE_ARM is not set
380# CONFIG_BLK_DEV_IDEDMA is not set
381# CONFIG_IDEDMA_AUTO is not set
382# CONFIG_BLK_DEV_HD is not set
221 383
222# 384#
223# SCSI device support 385# SCSI device support
224# 386#
387# CONFIG_RAID_ATTRS is not set
225# CONFIG_SCSI is not set 388# CONFIG_SCSI is not set
226 389
227# 390#
@@ -232,6 +395,7 @@ CONFIG_ATA_OVER_ETH=m
232# 395#
233# Fusion MPT device support 396# Fusion MPT device support
234# 397#
398# CONFIG_FUSION is not set
235 399
236# 400#
237# IEEE 1394 (FireWire) support 401# IEEE 1394 (FireWire) support
@@ -244,79 +408,13 @@ CONFIG_ATA_OVER_ETH=m
244# CONFIG_I2O is not set 408# CONFIG_I2O is not set
245 409
246# 410#
247# Networking support 411# Network device support
248#
249CONFIG_NET=y
250
251#
252# Networking options
253#
254CONFIG_PACKET=y
255CONFIG_PACKET_MMAP=y
256CONFIG_NETLINK_DEV=y
257CONFIG_UNIX=y
258CONFIG_NET_KEY=y
259CONFIG_INET=y
260CONFIG_IP_MULTICAST=y
261# CONFIG_IP_ADVANCED_ROUTER is not set
262CONFIG_IP_PNP=y
263# CONFIG_IP_PNP_DHCP is not set
264CONFIG_IP_PNP_BOOTP=y
265# CONFIG_IP_PNP_RARP is not set
266# CONFIG_NET_IPIP is not set
267# CONFIG_NET_IPGRE is not set
268# CONFIG_IP_MROUTE is not set
269# CONFIG_ARPD is not set
270# CONFIG_SYN_COOKIES is not set
271# CONFIG_INET_AH is not set
272# CONFIG_INET_ESP is not set
273# CONFIG_INET_IPCOMP is not set
274CONFIG_INET_TUNNEL=m
275CONFIG_IP_TCPDIAG=m
276# CONFIG_IP_TCPDIAG_IPV6 is not set
277# CONFIG_IPV6 is not set
278# CONFIG_NETFILTER is not set
279CONFIG_XFRM=y
280CONFIG_XFRM_USER=m
281
282#
283# SCTP Configuration (EXPERIMENTAL)
284# 412#
285# CONFIG_IP_SCTP is not set
286# CONFIG_ATM is not set
287# CONFIG_BRIDGE is not set
288# CONFIG_VLAN_8021Q is not set
289# CONFIG_DECNET is not set
290# CONFIG_LLC2 is not set
291# CONFIG_IPX is not set
292# CONFIG_ATALK is not set
293# CONFIG_X25 is not set
294# CONFIG_LAPB is not set
295# CONFIG_NET_DIVERT is not set
296# CONFIG_ECONET is not set
297# CONFIG_WAN_ROUTER is not set
298
299#
300# QoS and/or fair queueing
301#
302# CONFIG_NET_SCHED is not set
303# CONFIG_NET_CLS_ROUTE is not set
304
305#
306# Network testing
307#
308# CONFIG_NET_PKTGEN is not set
309# CONFIG_NETPOLL is not set
310# CONFIG_NET_POLL_CONTROLLER is not set
311# CONFIG_HAMRADIO is not set
312# CONFIG_IRDA is not set
313# CONFIG_BT is not set
314CONFIG_NETDEVICES=y 413CONFIG_NETDEVICES=y
315# CONFIG_DUMMY is not set 414# CONFIG_DUMMY is not set
316# CONFIG_BONDING is not set 415# CONFIG_BONDING is not set
317# CONFIG_EQUALIZER is not set 416# CONFIG_EQUALIZER is not set
318# CONFIG_TUN is not set 417# CONFIG_TUN is not set
319# CONFIG_ETHERTAP is not set
320 418
321# 419#
322# ARCnet devices 420# ARCnet devices
@@ -324,20 +422,14 @@ CONFIG_NETDEVICES=y
324# CONFIG_ARCNET is not set 422# CONFIG_ARCNET is not set
325 423
326# 424#
327# Ethernet (10 or 100Mbit) 425# PHY device support
328# 426#
329CONFIG_NET_ETHERNET=y
330# CONFIG_MII is not set
331# CONFIG_HAPPYMEAL is not set
332# CONFIG_SUNGEM is not set
333# CONFIG_NET_VENDOR_3COM is not set
334 427
335# 428#
336# Tulip family network device support 429# Ethernet (10 or 100Mbit)
337# 430#
338# CONFIG_NET_TULIP is not set 431# CONFIG_NET_ETHERNET is not set
339# CONFIG_HP100 is not set 432CONFIG_MII=m
340# CONFIG_NET_PCI is not set
341 433
342# 434#
343# Ethernet (1000 Mbit) 435# Ethernet (1000 Mbit)
@@ -349,12 +441,16 @@ CONFIG_NET_ETHERNET=y
349# CONFIG_HAMACHI is not set 441# CONFIG_HAMACHI is not set
350# CONFIG_YELLOWFIN is not set 442# CONFIG_YELLOWFIN is not set
351# CONFIG_R8169 is not set 443# CONFIG_R8169 is not set
444# CONFIG_SIS190 is not set
445# CONFIG_SKGE is not set
352# CONFIG_SK98LIN is not set 446# CONFIG_SK98LIN is not set
353# CONFIG_TIGON3 is not set 447# CONFIG_TIGON3 is not set
448# CONFIG_BNX2 is not set
354 449
355# 450#
356# Ethernet (10000 Mbit) 451# Ethernet (10000 Mbit)
357# 452#
453# CONFIG_CHELSIO_T1 is not set
358# CONFIG_IXGB is not set 454# CONFIG_IXGB is not set
359# CONFIG_S2IO is not set 455# CONFIG_S2IO is not set
360 456
@@ -366,7 +462,59 @@ CONFIG_NET_ETHERNET=y
366# 462#
367# Wireless LAN (non-hamradio) 463# Wireless LAN (non-hamradio)
368# 464#
369# CONFIG_NET_RADIO is not set 465CONFIG_NET_RADIO=y
466
467#
468# Obsolete Wireless cards support (pre-802.11)
469#
470# CONFIG_STRIP is not set
471# CONFIG_PCMCIA_WAVELAN is not set
472# CONFIG_PCMCIA_NETWAVE is not set
473
474#
475# Wireless 802.11 Frequency Hopping cards support
476#
477# CONFIG_PCMCIA_RAYCS is not set
478
479#
480# Wireless 802.11b ISA/PCI cards support
481#
482# CONFIG_IPW2100 is not set
483# CONFIG_IPW2200 is not set
484CONFIG_HERMES=m
485# CONFIG_PLX_HERMES is not set
486# CONFIG_TMD_HERMES is not set
487# CONFIG_NORTEL_HERMES is not set
488# CONFIG_PCI_HERMES is not set
489# CONFIG_ATMEL is not set
490
491#
492# Wireless 802.11b Pcmcia/Cardbus cards support
493#
494CONFIG_PCMCIA_HERMES=m
495# CONFIG_PCMCIA_SPECTRUM is not set
496# CONFIG_AIRO_CS is not set
497# CONFIG_PCMCIA_WL3501 is not set
498
499#
500# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support
501#
502# CONFIG_PRISM54 is not set
503# CONFIG_HOSTAP is not set
504CONFIG_NET_WIRELESS=y
505
506#
507# PCMCIA network device support
508#
509CONFIG_NET_PCMCIA=y
510CONFIG_PCMCIA_3C589=m
511CONFIG_PCMCIA_3C574=m
512CONFIG_PCMCIA_FMVJ18X=m
513CONFIG_PCMCIA_PCNET=m
514CONFIG_PCMCIA_NMCLAN=m
515CONFIG_PCMCIA_SMC91C92=m
516CONFIG_PCMCIA_XIRC2PS=m
517CONFIG_PCMCIA_AXNET=m
370 518
371# 519#
372# Wan interfaces 520# Wan interfaces
@@ -378,6 +526,8 @@ CONFIG_NET_ETHERNET=y
378# CONFIG_SLIP is not set 526# CONFIG_SLIP is not set
379# CONFIG_SHAPER is not set 527# CONFIG_SHAPER is not set
380# CONFIG_NETCONSOLE is not set 528# CONFIG_NETCONSOLE is not set
529# CONFIG_NETPOLL is not set
530# CONFIG_NET_POLL_CONTROLLER is not set
381 531
382# 532#
383# ISDN subsystem 533# ISDN subsystem
@@ -407,19 +557,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
407# CONFIG_INPUT_EVBUG is not set 557# CONFIG_INPUT_EVBUG is not set
408 558
409# 559#
410# Input I/O drivers
411#
412# CONFIG_GAMEPORT is not set
413CONFIG_SOUND_GAMEPORT=y
414CONFIG_SERIO=y
415CONFIG_SERIO_I8042=y
416CONFIG_SERIO_SERPORT=y
417# CONFIG_SERIO_CT82C710 is not set
418# CONFIG_SERIO_PCIPS2 is not set
419# CONFIG_SERIO_LIBPS2 is not set
420CONFIG_SERIO_RAW=m
421
422#
423# Input Device Drivers 560# Input Device Drivers
424# 561#
425# CONFIG_INPUT_KEYBOARD is not set 562# CONFIG_INPUT_KEYBOARD is not set
@@ -429,6 +566,17 @@ CONFIG_SERIO_RAW=m
429# CONFIG_INPUT_MISC is not set 566# CONFIG_INPUT_MISC is not set
430 567
431# 568#
569# Hardware I/O ports
570#
571CONFIG_SERIO=y
572# CONFIG_SERIO_I8042 is not set
573CONFIG_SERIO_SERPORT=y
574# CONFIG_SERIO_PCIPS2 is not set
575# CONFIG_SERIO_LIBPS2 is not set
576CONFIG_SERIO_RAW=m
577# CONFIG_GAMEPORT is not set
578
579#
432# Character devices 580# Character devices
433# 581#
434CONFIG_VT=y 582CONFIG_VT=y
@@ -439,16 +587,16 @@ CONFIG_HW_CONSOLE=y
439# 587#
440# Serial drivers 588# Serial drivers
441# 589#
442CONFIG_SERIAL_8250=y 590# CONFIG_SERIAL_8250 is not set
443CONFIG_SERIAL_8250_CONSOLE=y
444CONFIG_SERIAL_8250_NR_UARTS=4
445# CONFIG_SERIAL_8250_EXTENDED is not set
446 591
447# 592#
448# Non-8250 serial port support 593# Non-8250 serial port support
449# 594#
450CONFIG_SERIAL_CORE=y 595CONFIG_SERIAL_CORE=y
451CONFIG_SERIAL_CORE_CONSOLE=y 596CONFIG_SERIAL_CORE_CONSOLE=y
597CONFIG_SERIAL_VR41XX=y
598CONFIG_SERIAL_VR41XX_CONSOLE=y
599# CONFIG_SERIAL_JSM is not set
452CONFIG_UNIX98_PTYS=y 600CONFIG_UNIX98_PTYS=y
453CONFIG_LEGACY_PTYS=y 601CONFIG_LEGACY_PTYS=y
454CONFIG_LEGACY_PTY_COUNT=256 602CONFIG_LEGACY_PTY_COUNT=256
@@ -472,9 +620,20 @@ CONFIG_LEGACY_PTY_COUNT=256
472# Ftape, the floppy tape device driver 620# Ftape, the floppy tape device driver
473# 621#
474# CONFIG_DRM is not set 622# CONFIG_DRM is not set
623
624#
625# PCMCIA character devices
626#
627# CONFIG_SYNCLINK_CS is not set
628CONFIG_GPIO_VR41XX=y
475# CONFIG_RAW_DRIVER is not set 629# CONFIG_RAW_DRIVER is not set
476 630
477# 631#
632# TPM devices
633#
634# CONFIG_TCG_TPM is not set
635
636#
478# I2C support 637# I2C support
479# 638#
480# CONFIG_I2C is not set 639# CONFIG_I2C is not set
@@ -485,10 +644,20 @@ CONFIG_LEGACY_PTY_COUNT=256
485# CONFIG_W1 is not set 644# CONFIG_W1 is not set
486 645
487# 646#
647# Hardware Monitoring support
648#
649# CONFIG_HWMON is not set
650# CONFIG_HWMON_VID is not set
651
652#
488# Misc devices 653# Misc devices
489# 654#
490 655
491# 656#
657# Multimedia Capabilities Port drivers
658#
659
660#
492# Multimedia devices 661# Multimedia devices
493# 662#
494# CONFIG_VIDEO_DEV is not set 663# CONFIG_VIDEO_DEV is not set
@@ -508,7 +677,6 @@ CONFIG_LEGACY_PTY_COUNT=256
508# 677#
509# CONFIG_VGA_CONSOLE is not set 678# CONFIG_VGA_CONSOLE is not set
510CONFIG_DUMMY_CONSOLE=y 679CONFIG_DUMMY_CONSOLE=y
511# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
512 680
513# 681#
514# Sound 682# Sound
@@ -518,13 +686,120 @@ CONFIG_DUMMY_CONSOLE=y
518# 686#
519# USB support 687# USB support
520# 688#
521# CONFIG_USB is not set
522CONFIG_USB_ARCH_HAS_HCD=y 689CONFIG_USB_ARCH_HAS_HCD=y
523CONFIG_USB_ARCH_HAS_OHCI=y 690CONFIG_USB_ARCH_HAS_OHCI=y
691CONFIG_USB=m
692# CONFIG_USB_DEBUG is not set
693
694#
695# Miscellaneous USB options
696#
697CONFIG_USB_DEVICEFS=y
698# CONFIG_USB_BANDWIDTH is not set
699# CONFIG_USB_DYNAMIC_MINORS is not set
700# CONFIG_USB_OTG is not set
701
702#
703# USB Host Controller Drivers
704#
705# CONFIG_USB_EHCI_HCD is not set
706# CONFIG_USB_ISP116X_HCD is not set
707CONFIG_USB_OHCI_HCD=m
708# CONFIG_USB_OHCI_BIG_ENDIAN is not set
709CONFIG_USB_OHCI_LITTLE_ENDIAN=y
710# CONFIG_USB_UHCI_HCD is not set
711# CONFIG_USB_SL811_HCD is not set
712
713#
714# USB Device Class drivers
715#
716# CONFIG_USB_BLUETOOTH_TTY is not set
717# CONFIG_USB_ACM is not set
718# CONFIG_USB_PRINTER is not set
524 719
525# 720#
526# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information 721# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
527# 722#
723# CONFIG_USB_STORAGE is not set
724
725#
726# USB Input Devices
727#
728# CONFIG_USB_HID is not set
729
730#
731# USB HID Boot Protocol drivers
732#
733# CONFIG_USB_KBD is not set
734# CONFIG_USB_MOUSE is not set
735# CONFIG_USB_AIPTEK is not set
736# CONFIG_USB_WACOM is not set
737# CONFIG_USB_ACECAD is not set
738# CONFIG_USB_KBTAB is not set
739# CONFIG_USB_POWERMATE is not set
740# CONFIG_USB_MTOUCH is not set
741# CONFIG_USB_ITMTOUCH is not set
742# CONFIG_USB_EGALAX is not set
743# CONFIG_USB_YEALINK is not set
744# CONFIG_USB_XPAD is not set
745# CONFIG_USB_ATI_REMOTE is not set
746# CONFIG_USB_KEYSPAN_REMOTE is not set
747# CONFIG_USB_APPLETOUCH is not set
748
749#
750# USB Imaging devices
751#
752# CONFIG_USB_MDC800 is not set
753
754#
755# USB Multimedia devices
756#
757# CONFIG_USB_DABUSB is not set
758
759#
760# Video4Linux support is needed for USB Multimedia device support
761#
762
763#
764# USB Network Adapters
765#
766# CONFIG_USB_CATC is not set
767# CONFIG_USB_KAWETH is not set
768CONFIG_USB_PEGASUS=m
769# CONFIG_USB_RTL8150 is not set
770# CONFIG_USB_USBNET is not set
771# CONFIG_USB_ZD1201 is not set
772# CONFIG_USB_MON is not set
773
774#
775# USB port drivers
776#
777
778#
779# USB Serial Converter support
780#
781# CONFIG_USB_SERIAL is not set
782
783#
784# USB Miscellaneous drivers
785#
786# CONFIG_USB_EMI62 is not set
787# CONFIG_USB_EMI26 is not set
788# CONFIG_USB_AUERSWALD is not set
789# CONFIG_USB_RIO500 is not set
790# CONFIG_USB_LEGOTOWER is not set
791# CONFIG_USB_LCD is not set
792# CONFIG_USB_LED is not set
793# CONFIG_USB_CYTHERM is not set
794# CONFIG_USB_PHIDGETKIT is not set
795# CONFIG_USB_PHIDGETSERVO is not set
796# CONFIG_USB_IDMOUSE is not set
797# CONFIG_USB_LD is not set
798# CONFIG_USB_TEST is not set
799
800#
801# USB DSL modem support
802#
528 803
529# 804#
530# USB Gadget Support 805# USB Gadget Support
@@ -542,21 +817,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y
542# CONFIG_INFINIBAND is not set 817# CONFIG_INFINIBAND is not set
543 818
544# 819#
820# SN Devices
821#
822
823#
545# File systems 824# File systems
546# 825#
547CONFIG_EXT2_FS=y 826CONFIG_EXT2_FS=y
548# CONFIG_EXT2_FS_XATTR is not set 827# CONFIG_EXT2_FS_XATTR is not set
828# CONFIG_EXT2_FS_XIP is not set
549# CONFIG_EXT3_FS is not set 829# CONFIG_EXT3_FS is not set
550# CONFIG_JBD is not set 830# CONFIG_JBD is not set
551# CONFIG_REISERFS_FS is not set 831# CONFIG_REISERFS_FS is not set
552# CONFIG_JFS_FS is not set 832# CONFIG_JFS_FS is not set
833# CONFIG_FS_POSIX_ACL is not set
553# CONFIG_XFS_FS is not set 834# CONFIG_XFS_FS is not set
554# CONFIG_MINIX_FS is not set 835# CONFIG_MINIX_FS is not set
555# CONFIG_ROMFS_FS is not set 836# CONFIG_ROMFS_FS is not set
837CONFIG_INOTIFY=y
556# CONFIG_QUOTA is not set 838# CONFIG_QUOTA is not set
557CONFIG_DNOTIFY=y 839CONFIG_DNOTIFY=y
558CONFIG_AUTOFS_FS=y 840CONFIG_AUTOFS_FS=y
559CONFIG_AUTOFS4_FS=y 841CONFIG_AUTOFS4_FS=y
842CONFIG_FUSE_FS=m
560 843
561# 844#
562# CD-ROM/DVD Filesystems 845# CD-ROM/DVD Filesystems
@@ -577,12 +860,10 @@ CONFIG_AUTOFS4_FS=y
577CONFIG_PROC_FS=y 860CONFIG_PROC_FS=y
578CONFIG_PROC_KCORE=y 861CONFIG_PROC_KCORE=y
579CONFIG_SYSFS=y 862CONFIG_SYSFS=y
580# CONFIG_DEVFS_FS is not set
581CONFIG_DEVPTS_FS_XATTR=y
582CONFIG_DEVPTS_FS_SECURITY=y
583# CONFIG_TMPFS is not set 863# CONFIG_TMPFS is not set
584# CONFIG_HUGETLB_PAGE is not set 864# CONFIG_HUGETLB_PAGE is not set
585CONFIG_RAMFS=y 865CONFIG_RAMFS=y
866CONFIG_RELAYFS_FS=m
586 867
587# 868#
588# Miscellaneous filesystems 869# Miscellaneous filesystems
@@ -609,9 +890,8 @@ CONFIG_NFS_FS=y
609# CONFIG_NFS_V4 is not set 890# CONFIG_NFS_V4 is not set
610# CONFIG_NFS_DIRECTIO is not set 891# CONFIG_NFS_DIRECTIO is not set
611# CONFIG_NFSD is not set 892# CONFIG_NFSD is not set
612CONFIG_ROOT_NFS=y
613CONFIG_LOCKD=y 893CONFIG_LOCKD=y
614# CONFIG_EXPORTFS is not set 894CONFIG_NFS_COMMON=y
615CONFIG_SUNRPC=y 895CONFIG_SUNRPC=y
616# CONFIG_RPCSEC_GSS_KRB5 is not set 896# CONFIG_RPCSEC_GSS_KRB5 is not set
617# CONFIG_RPCSEC_GSS_SPKM3 is not set 897# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -620,6 +900,7 @@ CONFIG_SUNRPC=y
620# CONFIG_NCP_FS is not set 900# CONFIG_NCP_FS is not set
621# CONFIG_CODA_FS is not set 901# CONFIG_CODA_FS is not set
622# CONFIG_AFS_FS is not set 902# CONFIG_AFS_FS is not set
903# CONFIG_9P_FS is not set
623 904
624# 905#
625# Partition Types 906# Partition Types
@@ -640,9 +921,11 @@ CONFIG_MSDOS_PARTITION=y
640# 921#
641# Kernel hacking 922# Kernel hacking
642# 923#
924# CONFIG_PRINTK_TIME is not set
643# CONFIG_DEBUG_KERNEL is not set 925# CONFIG_DEBUG_KERNEL is not set
926CONFIG_LOG_BUF_SHIFT=14
644CONFIG_CROSSCOMPILE=y 927CONFIG_CROSSCOMPILE=y
645CONFIG_CMDLINE="" 928CONFIG_CMDLINE="mem=32M console=ttyVR0,19200"
646 929
647# 930#
648# Security options 931# Security options
@@ -656,26 +939,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
656# 939#
657CONFIG_CRYPTO=y 940CONFIG_CRYPTO=y
658CONFIG_CRYPTO_HMAC=y 941CONFIG_CRYPTO_HMAC=y
659CONFIG_CRYPTO_NULL=y 942CONFIG_CRYPTO_NULL=m
660# CONFIG_CRYPTO_MD4 is not set 943CONFIG_CRYPTO_MD4=m
661# CONFIG_CRYPTO_MD5 is not set 944CONFIG_CRYPTO_MD5=m
662# CONFIG_CRYPTO_SHA1 is not set 945CONFIG_CRYPTO_SHA1=m
663# CONFIG_CRYPTO_SHA256 is not set 946CONFIG_CRYPTO_SHA256=m
664CONFIG_CRYPTO_SHA512=y 947CONFIG_CRYPTO_SHA512=m
665CONFIG_CRYPTO_WP512=m 948CONFIG_CRYPTO_WP512=m
666# CONFIG_CRYPTO_DES is not set 949CONFIG_CRYPTO_TGR192=m
667# CONFIG_CRYPTO_BLOWFISH is not set 950CONFIG_CRYPTO_DES=m
668CONFIG_CRYPTO_TWOFISH=y 951CONFIG_CRYPTO_BLOWFISH=m
669# CONFIG_CRYPTO_SERPENT is not set 952CONFIG_CRYPTO_TWOFISH=m
953CONFIG_CRYPTO_SERPENT=m
670CONFIG_CRYPTO_AES=m 954CONFIG_CRYPTO_AES=m
671# CONFIG_CRYPTO_CAST5 is not set 955CONFIG_CRYPTO_CAST5=m
672# CONFIG_CRYPTO_CAST6 is not set 956CONFIG_CRYPTO_CAST6=m
673CONFIG_CRYPTO_TEA=m 957CONFIG_CRYPTO_TEA=m
674# CONFIG_CRYPTO_ARC4 is not set 958CONFIG_CRYPTO_ARC4=m
675CONFIG_CRYPTO_KHAZAD=m 959CONFIG_CRYPTO_KHAZAD=m
676CONFIG_CRYPTO_ANUBIS=m 960CONFIG_CRYPTO_ANUBIS=m
677CONFIG_CRYPTO_DEFLATE=y 961CONFIG_CRYPTO_DEFLATE=m
678CONFIG_CRYPTO_MICHAEL_MIC=y 962CONFIG_CRYPTO_MICHAEL_MIC=m
679CONFIG_CRYPTO_CRC32C=m 963CONFIG_CRYPTO_CRC32C=m
680# CONFIG_CRYPTO_TEST is not set 964# CONFIG_CRYPTO_TEST is not set
681 965
@@ -687,9 +971,8 @@ CONFIG_CRYPTO_CRC32C=m
687# Library routines 971# Library routines
688# 972#
689# CONFIG_CRC_CCITT is not set 973# CONFIG_CRC_CCITT is not set
690# CONFIG_CRC32 is not set 974CONFIG_CRC16=m
975CONFIG_CRC32=y
691CONFIG_LIBCRC32C=m 976CONFIG_LIBCRC32C=m
692CONFIG_ZLIB_INFLATE=y 977CONFIG_ZLIB_INFLATE=m
693CONFIG_ZLIB_DEFLATE=y 978CONFIG_ZLIB_DEFLATE=m
694CONFIG_GENERIC_HARDIRQS=y
695CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig
index b4cf97a732bc..ffb23fcab862 100644
--- a/arch/mips/configs/ocelot_3_defconfig
+++ b/arch/mips/configs/ocelot_3_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:07 2005 4# Thu Oct 20 22:26:30 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,25 +11,30 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31CONFIG_IKCONFIG=y 29CONFIG_IKCONFIG=y
32CONFIG_IKCONFIG_PROC=y 30CONFIG_IKCONFIG_PROC=y
31CONFIG_INITRAMFS_SOURCE=""
33CONFIG_EMBEDDED=y 32CONFIG_EMBEDDED=y
34CONFIG_KALLSYMS=y 33CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_EXTRA_PASS is not set 34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
36CONFIG_FUTEX=y 38CONFIG_FUTEX=y
37CONFIG_EPOLL=y 39CONFIG_EPOLL=y
38# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -42,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0
42CONFIG_CC_ALIGN_LOOPS=0 44CONFIG_CC_ALIGN_LOOPS=0
43CONFIG_CC_ALIGN_JUMPS=0 45CONFIG_CC_ALIGN_JUMPS=0
44# CONFIG_TINY_SHMEM is not set 46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
45 48
46# 49#
47# Loadable module support 50# Loadable module support
@@ -57,40 +60,68 @@ CONFIG_KMOD=y
57# 60#
58# Machine selection 61# Machine selection
59# 62#
60# CONFIG_MACH_JAZZ is not set 63# CONFIG_MIPS_MTX1 is not set
61# CONFIG_MACH_VR41XX is not set 64# CONFIG_MIPS_BOSPORUS is not set
62# CONFIG_TOSHIBA_JMR3927 is not set 65# CONFIG_MIPS_PB1000 is not set
66# CONFIG_MIPS_PB1100 is not set
67# CONFIG_MIPS_PB1500 is not set
68# CONFIG_MIPS_PB1550 is not set
69# CONFIG_MIPS_PB1200 is not set
70# CONFIG_MIPS_DB1000 is not set
71# CONFIG_MIPS_DB1100 is not set
72# CONFIG_MIPS_DB1500 is not set
73# CONFIG_MIPS_DB1550 is not set
74# CONFIG_MIPS_DB1200 is not set
75# CONFIG_MIPS_MIRAGE is not set
63# CONFIG_MIPS_COBALT is not set 76# CONFIG_MIPS_COBALT is not set
64# CONFIG_MACH_DECSTATION is not set 77# CONFIG_MACH_DECSTATION is not set
65# CONFIG_MIPS_EV64120 is not set 78# CONFIG_MIPS_EV64120 is not set
66# CONFIG_MIPS_EV96100 is not set 79# CONFIG_MIPS_EV96100 is not set
67# CONFIG_MIPS_IVR is not set 80# CONFIG_MIPS_IVR is not set
68# CONFIG_LASAT is not set
69# CONFIG_MIPS_ITE8172 is not set 81# CONFIG_MIPS_ITE8172 is not set
82# CONFIG_MACH_JAZZ is not set
83# CONFIG_LASAT is not set
70# CONFIG_MIPS_ATLAS is not set 84# CONFIG_MIPS_ATLAS is not set
71# CONFIG_MIPS_MALTA is not set 85# CONFIG_MIPS_MALTA is not set
72# CONFIG_MIPS_SEAD is not set 86# CONFIG_MIPS_SEAD is not set
87# CONFIG_MIPS_SIM is not set
88# CONFIG_MOMENCO_JAGUAR_ATX is not set
73# CONFIG_MOMENCO_OCELOT is not set 89# CONFIG_MOMENCO_OCELOT is not set
74# CONFIG_MOMENCO_OCELOT_G is not set
75# CONFIG_MOMENCO_OCELOT_C is not set
76CONFIG_MOMENCO_OCELOT_3=y 90CONFIG_MOMENCO_OCELOT_3=y
77# CONFIG_MOMENCO_JAGUAR_ATX is not set 91# CONFIG_MOMENCO_OCELOT_C is not set
78# CONFIG_PMC_YOSEMITE is not set 92# CONFIG_MOMENCO_OCELOT_G is not set
93# CONFIG_MIPS_XXS1500 is not set
94# CONFIG_PNX8550_V2PCI is not set
95# CONFIG_PNX8550_JBS is not set
79# CONFIG_DDB5074 is not set 96# CONFIG_DDB5074 is not set
80# CONFIG_DDB5476 is not set 97# CONFIG_DDB5476 is not set
81# CONFIG_DDB5477 is not set 98# CONFIG_DDB5477 is not set
82# CONFIG_NEC_OSPREY is not set 99# CONFIG_MACH_VR41XX is not set
100# CONFIG_PMC_YOSEMITE is not set
101# CONFIG_QEMU is not set
83# CONFIG_SGI_IP22 is not set 102# CONFIG_SGI_IP22 is not set
84# CONFIG_SOC_AU1X00 is not set 103# CONFIG_SGI_IP27 is not set
85# CONFIG_SIBYTE_SB1xxx_SOC is not set 104# CONFIG_SGI_IP32 is not set
105# CONFIG_SIBYTE_BIGSUR is not set
106# CONFIG_SIBYTE_SWARM is not set
107# CONFIG_SIBYTE_SENTOSA is not set
108# CONFIG_SIBYTE_RHONE is not set
109# CONFIG_SIBYTE_CARMEL is not set
110# CONFIG_SIBYTE_PTSWARM is not set
111# CONFIG_SIBYTE_LITTLESUR is not set
112# CONFIG_SIBYTE_CRHINE is not set
113# CONFIG_SIBYTE_CRHONE is not set
86# CONFIG_SNI_RM200_PCI is not set 114# CONFIG_SNI_RM200_PCI is not set
115# CONFIG_TOSHIBA_JMR3927 is not set
87# CONFIG_TOSHIBA_RBTX4927 is not set 116# CONFIG_TOSHIBA_RBTX4927 is not set
117# CONFIG_TOSHIBA_RBTX4938 is not set
88CONFIG_RWSEM_GENERIC_SPINLOCK=y 118CONFIG_RWSEM_GENERIC_SPINLOCK=y
89CONFIG_GENERIC_CALIBRATE_DELAY=y 119CONFIG_GENERIC_CALIBRATE_DELAY=y
90CONFIG_HAVE_DEC_LOCK=y
91CONFIG_DMA_NONCOHERENT=y 120CONFIG_DMA_NONCOHERENT=y
92CONFIG_DMA_NEED_PCI_MAP_STATE=y 121CONFIG_DMA_NEED_PCI_MAP_STATE=y
122CONFIG_CPU_BIG_ENDIAN=y
93# CONFIG_CPU_LITTLE_ENDIAN is not set 123# CONFIG_CPU_LITTLE_ENDIAN is not set
124CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
94CONFIG_IRQ_CPU=y 125CONFIG_IRQ_CPU=y
95CONFIG_IRQ_CPU_RM7K=y 126CONFIG_IRQ_CPU_RM7K=y
96CONFIG_IRQ_MV64340=y 127CONFIG_IRQ_MV64340=y
@@ -102,8 +133,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
102# 133#
103# CPU selection 134# CPU selection
104# 135#
105# CONFIG_CPU_MIPS32 is not set 136# CONFIG_CPU_MIPS32_R1 is not set
106# CONFIG_CPU_MIPS64 is not set 137# CONFIG_CPU_MIPS32_R2 is not set
138# CONFIG_CPU_MIPS64_R1 is not set
139# CONFIG_CPU_MIPS64_R2 is not set
107# CONFIG_CPU_R3000 is not set 140# CONFIG_CPU_R3000 is not set
108# CONFIG_CPU_TX39XX is not set 141# CONFIG_CPU_TX39XX is not set
109# CONFIG_CPU_VR41XX is not set 142# CONFIG_CPU_VR41XX is not set
@@ -119,6 +152,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
119# CONFIG_CPU_RM7000 is not set 152# CONFIG_CPU_RM7000 is not set
120CONFIG_CPU_RM9000=y 153CONFIG_CPU_RM9000=y
121# CONFIG_CPU_SB1 is not set 154# CONFIG_CPU_SB1 is not set
155CONFIG_SYS_HAS_CPU_RM9000=y
156CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
157CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
158CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
159CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
160
161#
162# Kernel type
163#
164CONFIG_32BIT=y
165# CONFIG_64BIT is not set
122CONFIG_PAGE_SIZE_4KB=y 166CONFIG_PAGE_SIZE_4KB=y
123# CONFIG_PAGE_SIZE_8KB is not set 167# CONFIG_PAGE_SIZE_8KB is not set
124# CONFIG_PAGE_SIZE_16KB is not set 168# CONFIG_PAGE_SIZE_16KB is not set
@@ -126,13 +170,26 @@ CONFIG_PAGE_SIZE_4KB=y
126CONFIG_BOARD_SCACHE=y 170CONFIG_BOARD_SCACHE=y
127CONFIG_RM7000_CPU_SCACHE=y 171CONFIG_RM7000_CPU_SCACHE=y
128CONFIG_CPU_HAS_PREFETCH=y 172CONFIG_CPU_HAS_PREFETCH=y
173# CONFIG_MIPS_MT is not set
129# CONFIG_64BIT_PHYS_ADDR is not set 174# CONFIG_64BIT_PHYS_ADDR is not set
130# CONFIG_CPU_ADVANCED is not set 175# CONFIG_CPU_ADVANCED is not set
131CONFIG_CPU_HAS_LLSC=y 176CONFIG_CPU_HAS_LLSC=y
132CONFIG_CPU_HAS_LLDSCD=y 177CONFIG_CPU_HAS_LLDSCD=y
133CONFIG_CPU_HAS_SYNC=y 178CONFIG_CPU_HAS_SYNC=y
134# CONFIG_HIGHMEM is not set 179CONFIG_GENERIC_HARDIRQS=y
180CONFIG_GENERIC_IRQ_PROBE=y
181CONFIG_CPU_SUPPORTS_HIGHMEM=y
182CONFIG_ARCH_FLATMEM_ENABLE=y
183CONFIG_SELECT_MEMORY_MODEL=y
184CONFIG_FLATMEM_MANUAL=y
185# CONFIG_DISCONTIGMEM_MANUAL is not set
186# CONFIG_SPARSEMEM_MANUAL is not set
187CONFIG_FLATMEM=y
188CONFIG_FLAT_NODE_MEM_MAP=y
189# CONFIG_SPARSEMEM_STATIC is not set
135# CONFIG_SMP is not set 190# CONFIG_SMP is not set
191CONFIG_PREEMPT_NONE=y
192# CONFIG_PREEMPT_VOLUNTARY is not set
136# CONFIG_PREEMPT is not set 193# CONFIG_PREEMPT is not set
137 194
138# 195#
@@ -141,7 +198,6 @@ CONFIG_CPU_HAS_SYNC=y
141CONFIG_HW_HAS_PCI=y 198CONFIG_HW_HAS_PCI=y
142CONFIG_PCI=y 199CONFIG_PCI=y
143CONFIG_PCI_LEGACY_PROC=y 200CONFIG_PCI_LEGACY_PROC=y
144CONFIG_PCI_NAMES=y
145CONFIG_MMU=y 201CONFIG_MMU=y
146 202
147# 203#
@@ -150,10 +206,6 @@ CONFIG_MMU=y
150# CONFIG_PCCARD is not set 206# CONFIG_PCCARD is not set
151 207
152# 208#
153# PC-card bridges
154#
155
156#
157# PCI Hotplug Support 209# PCI Hotplug Support
158# 210#
159# CONFIG_HOTPLUG_PCI is not set 211# CONFIG_HOTPLUG_PCI is not set
@@ -166,6 +218,110 @@ CONFIG_BINFMT_ELF=y
166CONFIG_TRAD_SIGNALS=y 218CONFIG_TRAD_SIGNALS=y
167 219
168# 220#
221# Networking
222#
223CONFIG_NET=y
224
225#
226# Networking options
227#
228CONFIG_PACKET=y
229# CONFIG_PACKET_MMAP is not set
230CONFIG_UNIX=y
231CONFIG_XFRM=y
232# CONFIG_XFRM_USER is not set
233CONFIG_NET_KEY=y
234CONFIG_INET=y
235# CONFIG_IP_MULTICAST is not set
236# CONFIG_IP_ADVANCED_ROUTER is not set
237CONFIG_IP_FIB_HASH=y
238CONFIG_IP_PNP=y
239CONFIG_IP_PNP_DHCP=y
240CONFIG_IP_PNP_BOOTP=y
241# CONFIG_IP_PNP_RARP is not set
242# CONFIG_NET_IPIP is not set
243# CONFIG_NET_IPGRE is not set
244# CONFIG_ARPD is not set
245# CONFIG_SYN_COOKIES is not set
246# CONFIG_INET_AH is not set
247# CONFIG_INET_ESP is not set
248# CONFIG_INET_IPCOMP is not set
249# CONFIG_INET_TUNNEL is not set
250CONFIG_INET_DIAG=y
251CONFIG_INET_TCP_DIAG=y
252# CONFIG_TCP_CONG_ADVANCED is not set
253CONFIG_TCP_CONG_BIC=y
254
255#
256# IP: Virtual Server Configuration
257#
258# CONFIG_IP_VS is not set
259CONFIG_IPV6=m
260# CONFIG_IPV6_PRIVACY is not set
261# CONFIG_INET6_AH is not set
262# CONFIG_INET6_ESP is not set
263# CONFIG_INET6_IPCOMP is not set
264# CONFIG_INET6_TUNNEL is not set
265# CONFIG_IPV6_TUNNEL is not set
266CONFIG_NETFILTER=y
267# CONFIG_NETFILTER_DEBUG is not set
268CONFIG_NETFILTER_NETLINK=m
269CONFIG_NETFILTER_NETLINK_QUEUE=m
270CONFIG_NETFILTER_NETLINK_LOG=m
271
272#
273# IP: Netfilter Configuration
274#
275# CONFIG_IP_NF_CONNTRACK is not set
276CONFIG_IP_NF_PPTP=m
277# CONFIG_IP_NF_QUEUE is not set
278# CONFIG_IP_NF_IPTABLES is not set
279# CONFIG_IP_NF_ARPTABLES is not set
280
281#
282# IPv6: Netfilter Configuration (EXPERIMENTAL)
283#
284# CONFIG_IP6_NF_QUEUE is not set
285# CONFIG_IP6_NF_IPTABLES is not set
286
287#
288# DCCP Configuration (EXPERIMENTAL)
289#
290# CONFIG_IP_DCCP is not set
291
292#
293# SCTP Configuration (EXPERIMENTAL)
294#
295# CONFIG_IP_SCTP is not set
296# CONFIG_ATM is not set
297# CONFIG_BRIDGE is not set
298# CONFIG_VLAN_8021Q is not set
299# CONFIG_DECNET is not set
300# CONFIG_LLC2 is not set
301# CONFIG_IPX is not set
302# CONFIG_ATALK is not set
303# CONFIG_X25 is not set
304# CONFIG_LAPB is not set
305# CONFIG_NET_DIVERT is not set
306# CONFIG_ECONET is not set
307# CONFIG_WAN_ROUTER is not set
308# CONFIG_NET_SCHED is not set
309# CONFIG_NET_CLS_ROUTE is not set
310
311#
312# Network testing
313#
314# CONFIG_NET_PKTGEN is not set
315# CONFIG_HAMRADIO is not set
316# CONFIG_IRDA is not set
317# CONFIG_BT is not set
318CONFIG_IEEE80211=m
319# CONFIG_IEEE80211_DEBUG is not set
320CONFIG_IEEE80211_CRYPT_WEP=m
321CONFIG_IEEE80211_CRYPT_CCMP=m
322CONFIG_IEEE80211_CRYPT_TKIP=m
323
324#
169# Device Drivers 325# Device Drivers
170# 326#
171 327
@@ -174,7 +330,12 @@ CONFIG_TRAD_SIGNALS=y
174# 330#
175CONFIG_STANDALONE=y 331CONFIG_STANDALONE=y
176CONFIG_PREVENT_FIRMWARE_BUILD=y 332CONFIG_PREVENT_FIRMWARE_BUILD=y
177# CONFIG_FW_LOADER is not set 333CONFIG_FW_LOADER=m
334
335#
336# Connector - unified userspace <-> kernelspace linker
337#
338CONFIG_CONNECTOR=m
178 339
179# 340#
180# Memory Technology Devices (MTD) 341# Memory Technology Devices (MTD)
@@ -193,7 +354,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
193# 354#
194# Block devices 355# Block devices
195# 356#
196# CONFIG_BLK_DEV_FD is not set
197# CONFIG_BLK_CPQ_DA is not set 357# CONFIG_BLK_CPQ_DA is not set
198# CONFIG_BLK_CPQ_CISS_DA is not set 358# CONFIG_BLK_CPQ_CISS_DA is not set
199# CONFIG_BLK_DEV_DAC960 is not set 359# CONFIG_BLK_DEV_DAC960 is not set
@@ -205,7 +365,6 @@ CONFIG_BLK_DEV_LOOP=y
205# CONFIG_BLK_DEV_SX8 is not set 365# CONFIG_BLK_DEV_SX8 is not set
206# CONFIG_BLK_DEV_RAM is not set 366# CONFIG_BLK_DEV_RAM is not set
207CONFIG_BLK_DEV_RAM_COUNT=16 367CONFIG_BLK_DEV_RAM_COUNT=16
208CONFIG_INITRAMFS_SOURCE=""
209# CONFIG_LBD is not set 368# CONFIG_LBD is not set
210# CONFIG_CDROM_PKTCDVD is not set 369# CONFIG_CDROM_PKTCDVD is not set
211 370
@@ -226,6 +385,7 @@ CONFIG_ATA_OVER_ETH=m
226# 385#
227# SCSI device support 386# SCSI device support
228# 387#
388CONFIG_RAID_ATTRS=m
229CONFIG_SCSI=m 389CONFIG_SCSI=m
230CONFIG_SCSI_PROC_FS=y 390CONFIG_SCSI_PROC_FS=y
231 391
@@ -237,6 +397,7 @@ CONFIG_SCSI_PROC_FS=y
237# CONFIG_CHR_DEV_OSST is not set 397# CONFIG_CHR_DEV_OSST is not set
238# CONFIG_BLK_DEV_SR is not set 398# CONFIG_BLK_DEV_SR is not set
239# CONFIG_CHR_DEV_SG is not set 399# CONFIG_CHR_DEV_SG is not set
400# CONFIG_CHR_DEV_SCH is not set
240 401
241# 402#
242# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 403# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -251,6 +412,7 @@ CONFIG_SCSI_PROC_FS=y
251# CONFIG_SCSI_SPI_ATTRS is not set 412# CONFIG_SCSI_SPI_ATTRS is not set
252# CONFIG_SCSI_FC_ATTRS is not set 413# CONFIG_SCSI_FC_ATTRS is not set
253# CONFIG_SCSI_ISCSI_ATTRS is not set 414# CONFIG_SCSI_ISCSI_ATTRS is not set
415CONFIG_SCSI_SAS_ATTRS=m
254 416
255# 417#
256# SCSI low-level drivers 418# SCSI low-level drivers
@@ -266,18 +428,13 @@ CONFIG_SCSI_PROC_FS=y
266# CONFIG_MEGARAID_NEWGEN is not set 428# CONFIG_MEGARAID_NEWGEN is not set
267# CONFIG_MEGARAID_LEGACY is not set 429# CONFIG_MEGARAID_LEGACY is not set
268# CONFIG_SCSI_SATA is not set 430# CONFIG_SCSI_SATA is not set
269# CONFIG_SCSI_BUSLOGIC is not set
270# CONFIG_SCSI_DMX3191D is not set 431# CONFIG_SCSI_DMX3191D is not set
271# CONFIG_SCSI_EATA is not set
272# CONFIG_SCSI_EATA_PIO is not set
273# CONFIG_SCSI_FUTURE_DOMAIN is not set 432# CONFIG_SCSI_FUTURE_DOMAIN is not set
274# CONFIG_SCSI_GDTH is not set
275# CONFIG_SCSI_IPS is not set 433# CONFIG_SCSI_IPS is not set
276# CONFIG_SCSI_INITIO is not set 434# CONFIG_SCSI_INITIO is not set
277# CONFIG_SCSI_INIA100 is not set 435# CONFIG_SCSI_INIA100 is not set
278# CONFIG_SCSI_SYM53C8XX_2 is not set 436# CONFIG_SCSI_SYM53C8XX_2 is not set
279# CONFIG_SCSI_IPR is not set 437# CONFIG_SCSI_IPR is not set
280# CONFIG_SCSI_QLOGIC_ISP is not set
281# CONFIG_SCSI_QLOGIC_FC is not set 438# CONFIG_SCSI_QLOGIC_FC is not set
282# CONFIG_SCSI_QLOGIC_1280 is not set 439# CONFIG_SCSI_QLOGIC_1280 is not set
283CONFIG_SCSI_QLA2XXX=m 440CONFIG_SCSI_QLA2XXX=m
@@ -286,6 +443,8 @@ CONFIG_SCSI_QLA2XXX=m
286# CONFIG_SCSI_QLA2300 is not set 443# CONFIG_SCSI_QLA2300 is not set
287# CONFIG_SCSI_QLA2322 is not set 444# CONFIG_SCSI_QLA2322 is not set
288# CONFIG_SCSI_QLA6312 is not set 445# CONFIG_SCSI_QLA6312 is not set
446# CONFIG_SCSI_QLA24XX is not set
447# CONFIG_SCSI_LPFC is not set
289# CONFIG_SCSI_DC395x is not set 448# CONFIG_SCSI_DC395x is not set
290# CONFIG_SCSI_DC390T is not set 449# CONFIG_SCSI_DC390T is not set
291# CONFIG_SCSI_NSP32 is not set 450# CONFIG_SCSI_NSP32 is not set
@@ -300,6 +459,8 @@ CONFIG_SCSI_QLA2XXX=m
300# Fusion MPT device support 459# Fusion MPT device support
301# 460#
302# CONFIG_FUSION is not set 461# CONFIG_FUSION is not set
462# CONFIG_FUSION_SPI is not set
463# CONFIG_FUSION_FC is not set
303 464
304# 465#
305# IEEE 1394 (FireWire) support 466# IEEE 1394 (FireWire) support
@@ -312,105 +473,13 @@ CONFIG_SCSI_QLA2XXX=m
312# CONFIG_I2O is not set 473# CONFIG_I2O is not set
313 474
314# 475#
315# Networking support 476# Network device support
316#
317CONFIG_NET=y
318
319#
320# Networking options
321#
322CONFIG_PACKET=y
323# CONFIG_PACKET_MMAP is not set
324CONFIG_NETLINK_DEV=y
325CONFIG_UNIX=y
326CONFIG_NET_KEY=y
327CONFIG_INET=y
328# CONFIG_IP_MULTICAST is not set
329# CONFIG_IP_ADVANCED_ROUTER is not set
330CONFIG_IP_PNP=y
331CONFIG_IP_PNP_DHCP=y
332CONFIG_IP_PNP_BOOTP=y
333# CONFIG_IP_PNP_RARP is not set
334# CONFIG_NET_IPIP is not set
335# CONFIG_NET_IPGRE is not set
336# CONFIG_ARPD is not set
337# CONFIG_SYN_COOKIES is not set
338# CONFIG_INET_AH is not set
339# CONFIG_INET_ESP is not set
340# CONFIG_INET_IPCOMP is not set
341# CONFIG_INET_TUNNEL is not set
342CONFIG_IP_TCPDIAG=m
343CONFIG_IP_TCPDIAG_IPV6=y
344
345#
346# IP: Virtual Server Configuration
347#
348# CONFIG_IP_VS is not set
349CONFIG_IPV6=m
350# CONFIG_IPV6_PRIVACY is not set
351# CONFIG_INET6_AH is not set
352# CONFIG_INET6_ESP is not set
353# CONFIG_INET6_IPCOMP is not set
354# CONFIG_INET6_TUNNEL is not set
355# CONFIG_IPV6_TUNNEL is not set
356CONFIG_NETFILTER=y
357# CONFIG_NETFILTER_DEBUG is not set
358
359#
360# IP: Netfilter Configuration
361#
362# CONFIG_IP_NF_CONNTRACK is not set
363# CONFIG_IP_NF_CONNTRACK_MARK is not set
364# CONFIG_IP_NF_QUEUE is not set
365# CONFIG_IP_NF_IPTABLES is not set
366# CONFIG_IP_NF_ARPTABLES is not set
367
368#
369# IPv6: Netfilter Configuration
370#
371# CONFIG_IP6_NF_QUEUE is not set
372# CONFIG_IP6_NF_IPTABLES is not set
373CONFIG_XFRM=y
374# CONFIG_XFRM_USER is not set
375
376#
377# SCTP Configuration (EXPERIMENTAL)
378#
379# CONFIG_IP_SCTP is not set
380# CONFIG_ATM is not set
381# CONFIG_BRIDGE is not set
382# CONFIG_VLAN_8021Q is not set
383# CONFIG_DECNET is not set
384# CONFIG_LLC2 is not set
385# CONFIG_IPX is not set
386# CONFIG_ATALK is not set
387# CONFIG_X25 is not set
388# CONFIG_LAPB is not set
389# CONFIG_NET_DIVERT is not set
390# CONFIG_ECONET is not set
391# CONFIG_WAN_ROUTER is not set
392
393#
394# QoS and/or fair queueing
395#
396# CONFIG_NET_SCHED is not set
397# CONFIG_NET_CLS_ROUTE is not set
398
399#
400# Network testing
401# 477#
402# CONFIG_NET_PKTGEN is not set
403# CONFIG_NETPOLL is not set
404# CONFIG_NET_POLL_CONTROLLER is not set
405# CONFIG_HAMRADIO is not set
406# CONFIG_IRDA is not set
407# CONFIG_BT is not set
408CONFIG_NETDEVICES=y 478CONFIG_NETDEVICES=y
409# CONFIG_DUMMY is not set 479# CONFIG_DUMMY is not set
410# CONFIG_BONDING is not set 480# CONFIG_BONDING is not set
411# CONFIG_EQUALIZER is not set 481# CONFIG_EQUALIZER is not set
412CONFIG_TUN=m 482CONFIG_TUN=m
413# CONFIG_ETHERTAP is not set
414 483
415# 484#
416# ARCnet devices 485# ARCnet devices
@@ -418,6 +487,21 @@ CONFIG_TUN=m
418# CONFIG_ARCNET is not set 487# CONFIG_ARCNET is not set
419 488
420# 489#
490# PHY device support
491#
492CONFIG_PHYLIB=m
493CONFIG_PHYCONTROL=y
494
495#
496# MII PHY device drivers
497#
498CONFIG_MARVELL_PHY=m
499CONFIG_DAVICOM_PHY=m
500CONFIG_QSEMI_PHY=m
501CONFIG_LXT_PHY=m
502CONFIG_CICADA_PHY=m
503
504#
421# Ethernet (10 or 100Mbit) 505# Ethernet (10 or 100Mbit)
422# 506#
423CONFIG_NET_ETHERNET=y 507CONFIG_NET_ETHERNET=y
@@ -440,7 +524,6 @@ CONFIG_NET_PCI=y
440# CONFIG_DGRS is not set 524# CONFIG_DGRS is not set
441# CONFIG_EEPRO100 is not set 525# CONFIG_EEPRO100 is not set
442CONFIG_E100=y 526CONFIG_E100=y
443# CONFIG_E100_NAPI is not set
444# CONFIG_FEALNX is not set 527# CONFIG_FEALNX is not set
445# CONFIG_NATSEMI is not set 528# CONFIG_NATSEMI is not set
446# CONFIG_NE2K_PCI is not set 529# CONFIG_NE2K_PCI is not set
@@ -463,9 +546,12 @@ CONFIG_E100=y
463# CONFIG_HAMACHI is not set 546# CONFIG_HAMACHI is not set
464# CONFIG_YELLOWFIN is not set 547# CONFIG_YELLOWFIN is not set
465# CONFIG_R8169 is not set 548# CONFIG_R8169 is not set
549# CONFIG_SIS190 is not set
550# CONFIG_SKGE is not set
466# CONFIG_SK98LIN is not set 551# CONFIG_SK98LIN is not set
467# CONFIG_VIA_VELOCITY is not set 552# CONFIG_VIA_VELOCITY is not set
468# CONFIG_TIGON3 is not set 553# CONFIG_TIGON3 is not set
554# CONFIG_BNX2 is not set
469CONFIG_MV643XX_ETH=y 555CONFIG_MV643XX_ETH=y
470CONFIG_MV643XX_ETH_0=y 556CONFIG_MV643XX_ETH_0=y
471CONFIG_MV643XX_ETH_1=y 557CONFIG_MV643XX_ETH_1=y
@@ -474,6 +560,7 @@ CONFIG_MV643XX_ETH_2=y
474# 560#
475# Ethernet (10000 Mbit) 561# Ethernet (10000 Mbit)
476# 562#
563# CONFIG_CHELSIO_T1 is not set
477# CONFIG_IXGB is not set 564# CONFIG_IXGB is not set
478# CONFIG_S2IO is not set 565# CONFIG_S2IO is not set
479 566
@@ -486,6 +573,8 @@ CONFIG_MV643XX_ETH_2=y
486# Wireless LAN (non-hamradio) 573# Wireless LAN (non-hamradio)
487# 574#
488# CONFIG_NET_RADIO is not set 575# CONFIG_NET_RADIO is not set
576# CONFIG_IPW_DEBUG is not set
577CONFIG_IPW2200=m
489 578
490# 579#
491# Wan interfaces 580# Wan interfaces
@@ -505,6 +594,8 @@ CONFIG_PPPOE=m
505# CONFIG_NET_FC is not set 594# CONFIG_NET_FC is not set
506# CONFIG_SHAPER is not set 595# CONFIG_SHAPER is not set
507# CONFIG_NETCONSOLE is not set 596# CONFIG_NETCONSOLE is not set
597# CONFIG_NETPOLL is not set
598# CONFIG_NET_POLL_CONTROLLER is not set
508 599
509# 600#
510# ISDN subsystem 601# ISDN subsystem
@@ -531,19 +622,6 @@ CONFIG_INPUT=y
531# CONFIG_INPUT_EVBUG is not set 622# CONFIG_INPUT_EVBUG is not set
532 623
533# 624#
534# Input I/O drivers
535#
536# CONFIG_GAMEPORT is not set
537CONFIG_SOUND_GAMEPORT=y
538CONFIG_SERIO=y
539# CONFIG_SERIO_I8042 is not set
540# CONFIG_SERIO_SERPORT is not set
541# CONFIG_SERIO_CT82C710 is not set
542# CONFIG_SERIO_PCIPS2 is not set
543# CONFIG_SERIO_LIBPS2 is not set
544# CONFIG_SERIO_RAW is not set
545
546#
547# Input Device Drivers 625# Input Device Drivers
548# 626#
549# CONFIG_INPUT_KEYBOARD is not set 627# CONFIG_INPUT_KEYBOARD is not set
@@ -553,6 +631,17 @@ CONFIG_SERIO=y
553# CONFIG_INPUT_MISC is not set 631# CONFIG_INPUT_MISC is not set
554 632
555# 633#
634# Hardware I/O ports
635#
636CONFIG_SERIO=y
637# CONFIG_SERIO_I8042 is not set
638# CONFIG_SERIO_SERPORT is not set
639# CONFIG_SERIO_PCIPS2 is not set
640# CONFIG_SERIO_LIBPS2 is not set
641# CONFIG_SERIO_RAW is not set
642# CONFIG_GAMEPORT is not set
643
644#
556# Character devices 645# Character devices
557# 646#
558CONFIG_VT=y 647CONFIG_VT=y
@@ -573,6 +662,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
573# 662#
574CONFIG_SERIAL_CORE=y 663CONFIG_SERIAL_CORE=y
575CONFIG_SERIAL_CORE_CONSOLE=y 664CONFIG_SERIAL_CORE_CONSOLE=y
665# CONFIG_SERIAL_JSM is not set
576CONFIG_UNIX98_PTYS=y 666CONFIG_UNIX98_PTYS=y
577CONFIG_LEGACY_PTYS=y 667CONFIG_LEGACY_PTYS=y
578CONFIG_LEGACY_PTY_COUNT=256 668CONFIG_LEGACY_PTY_COUNT=256
@@ -598,6 +688,11 @@ CONFIG_RTC=y
598# CONFIG_RAW_DRIVER is not set 688# CONFIG_RAW_DRIVER is not set
599 689
600# 690#
691# TPM devices
692#
693# CONFIG_TCG_TPM is not set
694
695#
601# I2C support 696# I2C support
602# 697#
603# CONFIG_I2C is not set 698# CONFIG_I2C is not set
@@ -608,10 +703,20 @@ CONFIG_RTC=y
608# CONFIG_W1 is not set 703# CONFIG_W1 is not set
609 704
610# 705#
706# Hardware Monitoring support
707#
708# CONFIG_HWMON is not set
709# CONFIG_HWMON_VID is not set
710
711#
611# Misc devices 712# Misc devices
612# 713#
613 714
614# 715#
716# Multimedia Capabilities Port drivers
717#
718
719#
615# Multimedia devices 720# Multimedia devices
616# 721#
617# CONFIG_VIDEO_DEV is not set 722# CONFIG_VIDEO_DEV is not set
@@ -625,6 +730,11 @@ CONFIG_RTC=y
625# Graphics support 730# Graphics support
626# 731#
627CONFIG_FB=y 732CONFIG_FB=y
733# CONFIG_FB_CFB_FILLRECT is not set
734# CONFIG_FB_CFB_COPYAREA is not set
735# CONFIG_FB_CFB_IMAGEBLIT is not set
736# CONFIG_FB_SOFT_CURSOR is not set
737# CONFIG_FB_MACMODES is not set
628CONFIG_FB_MODE_HELPERS=y 738CONFIG_FB_MODE_HELPERS=y
629# CONFIG_FB_TILEBLITTING is not set 739# CONFIG_FB_TILEBLITTING is not set
630# CONFIG_FB_CIRRUS is not set 740# CONFIG_FB_CIRRUS is not set
@@ -632,6 +742,7 @@ CONFIG_FB_MODE_HELPERS=y
632# CONFIG_FB_CYBER2000 is not set 742# CONFIG_FB_CYBER2000 is not set
633# CONFIG_FB_ASILIANT is not set 743# CONFIG_FB_ASILIANT is not set
634# CONFIG_FB_IMSTT is not set 744# CONFIG_FB_IMSTT is not set
745# CONFIG_FB_NVIDIA is not set
635# CONFIG_FB_RIVA is not set 746# CONFIG_FB_RIVA is not set
636# CONFIG_FB_MATROX is not set 747# CONFIG_FB_MATROX is not set
637# CONFIG_FB_RADEON_OLD is not set 748# CONFIG_FB_RADEON_OLD is not set
@@ -644,8 +755,11 @@ CONFIG_FB_MODE_HELPERS=y
644# CONFIG_FB_KYRO is not set 755# CONFIG_FB_KYRO is not set
645# CONFIG_FB_3DFX is not set 756# CONFIG_FB_3DFX is not set
646# CONFIG_FB_VOODOO1 is not set 757# CONFIG_FB_VOODOO1 is not set
758# CONFIG_FB_SMIVGX is not set
759# CONFIG_FB_CYBLA is not set
647# CONFIG_FB_TRIDENT is not set 760# CONFIG_FB_TRIDENT is not set
648# CONFIG_FB_E1356 is not set 761# CONFIG_FB_E1356 is not set
762# CONFIG_FB_S1D13XXX is not set
649# CONFIG_FB_VIRTUAL is not set 763# CONFIG_FB_VIRTUAL is not set
650 764
651# 765#
@@ -675,13 +789,9 @@ CONFIG_LOGO_LINUX_CLUT224=y
675# 789#
676# USB support 790# USB support
677# 791#
678# CONFIG_USB is not set
679CONFIG_USB_ARCH_HAS_HCD=y 792CONFIG_USB_ARCH_HAS_HCD=y
680CONFIG_USB_ARCH_HAS_OHCI=y 793CONFIG_USB_ARCH_HAS_OHCI=y
681 794# CONFIG_USB is not set
682#
683# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
684#
685 795
686# 796#
687# USB Gadget Support 797# USB Gadget Support
@@ -699,10 +809,15 @@ CONFIG_USB_ARCH_HAS_OHCI=y
699# CONFIG_INFINIBAND is not set 809# CONFIG_INFINIBAND is not set
700 810
701# 811#
812# SN Devices
813#
814
815#
702# File systems 816# File systems
703# 817#
704CONFIG_EXT2_FS=y 818CONFIG_EXT2_FS=y
705# CONFIG_EXT2_FS_XATTR is not set 819# CONFIG_EXT2_FS_XATTR is not set
820# CONFIG_EXT2_FS_XIP is not set
706CONFIG_EXT3_FS=m 821CONFIG_EXT3_FS=m
707CONFIG_EXT3_FS_XATTR=y 822CONFIG_EXT3_FS_XATTR=y
708# CONFIG_EXT3_FS_POSIX_ACL is not set 823# CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -715,17 +830,21 @@ CONFIG_REISERFS_FS=m
715# CONFIG_REISERFS_PROC_INFO is not set 830# CONFIG_REISERFS_PROC_INFO is not set
716# CONFIG_REISERFS_FS_XATTR is not set 831# CONFIG_REISERFS_FS_XATTR is not set
717# CONFIG_JFS_FS is not set 832# CONFIG_JFS_FS is not set
833# CONFIG_FS_POSIX_ACL is not set
718CONFIG_XFS_FS=m 834CONFIG_XFS_FS=m
719# CONFIG_XFS_RT is not set 835CONFIG_XFS_EXPORT=y
720# CONFIG_XFS_QUOTA is not set 836# CONFIG_XFS_QUOTA is not set
721# CONFIG_XFS_SECURITY is not set 837# CONFIG_XFS_SECURITY is not set
722# CONFIG_XFS_POSIX_ACL is not set 838# CONFIG_XFS_POSIX_ACL is not set
839# CONFIG_XFS_RT is not set
723# CONFIG_MINIX_FS is not set 840# CONFIG_MINIX_FS is not set
724# CONFIG_ROMFS_FS is not set 841# CONFIG_ROMFS_FS is not set
842CONFIG_INOTIFY=y
725# CONFIG_QUOTA is not set 843# CONFIG_QUOTA is not set
726CONFIG_DNOTIFY=y 844CONFIG_DNOTIFY=y
727CONFIG_AUTOFS_FS=y 845CONFIG_AUTOFS_FS=y
728CONFIG_AUTOFS4_FS=m 846CONFIG_AUTOFS4_FS=m
847CONFIG_FUSE_FS=m
729 848
730# 849#
731# CD-ROM/DVD Filesystems 850# CD-ROM/DVD Filesystems
@@ -746,15 +865,10 @@ CONFIG_AUTOFS4_FS=m
746CONFIG_PROC_FS=y 865CONFIG_PROC_FS=y
747CONFIG_PROC_KCORE=y 866CONFIG_PROC_KCORE=y
748CONFIG_SYSFS=y 867CONFIG_SYSFS=y
749CONFIG_DEVFS_FS=y
750CONFIG_DEVFS_MOUNT=y
751# CONFIG_DEVFS_DEBUG is not set
752CONFIG_DEVPTS_FS_XATTR=y
753CONFIG_DEVPTS_FS_SECURITY=y
754CONFIG_TMPFS=y 868CONFIG_TMPFS=y
755# CONFIG_TMPFS_XATTR is not set
756# CONFIG_HUGETLB_PAGE is not set 869# CONFIG_HUGETLB_PAGE is not set
757CONFIG_RAMFS=y 870CONFIG_RAMFS=y
871CONFIG_RELAYFS_FS=m
758 872
759# 873#
760# Miscellaneous filesystems 874# Miscellaneous filesystems
@@ -778,16 +892,19 @@ CONFIG_CRAMFS=y
778# 892#
779CONFIG_NFS_FS=y 893CONFIG_NFS_FS=y
780CONFIG_NFS_V3=y 894CONFIG_NFS_V3=y
895# CONFIG_NFS_V3_ACL is not set
781# CONFIG_NFS_V4 is not set 896# CONFIG_NFS_V4 is not set
782# CONFIG_NFS_DIRECTIO is not set 897# CONFIG_NFS_DIRECTIO is not set
783CONFIG_NFSD=y 898CONFIG_NFSD=y
784CONFIG_NFSD_V3=y 899CONFIG_NFSD_V3=y
900# CONFIG_NFSD_V3_ACL is not set
785# CONFIG_NFSD_V4 is not set 901# CONFIG_NFSD_V4 is not set
786# CONFIG_NFSD_TCP is not set 902# CONFIG_NFSD_TCP is not set
787CONFIG_ROOT_NFS=y 903CONFIG_ROOT_NFS=y
788CONFIG_LOCKD=y 904CONFIG_LOCKD=y
789CONFIG_LOCKD_V4=y 905CONFIG_LOCKD_V4=y
790CONFIG_EXPORTFS=y 906CONFIG_EXPORTFS=y
907CONFIG_NFS_COMMON=y
791CONFIG_SUNRPC=y 908CONFIG_SUNRPC=y
792# CONFIG_RPCSEC_GSS_KRB5 is not set 909# CONFIG_RPCSEC_GSS_KRB5 is not set
793# CONFIG_RPCSEC_GSS_SPKM3 is not set 910# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -797,6 +914,7 @@ CONFIG_SMB_FS=m
797# CONFIG_NCP_FS is not set 914# CONFIG_NCP_FS is not set
798# CONFIG_CODA_FS is not set 915# CONFIG_CODA_FS is not set
799# CONFIG_AFS_FS is not set 916# CONFIG_AFS_FS is not set
917# CONFIG_9P_FS is not set
800 918
801# 919#
802# Partition Types 920# Partition Types
@@ -856,7 +974,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
856# 974#
857# Kernel hacking 975# Kernel hacking
858# 976#
977# CONFIG_PRINTK_TIME is not set
859# CONFIG_DEBUG_KERNEL is not set 978# CONFIG_DEBUG_KERNEL is not set
979CONFIG_LOG_BUF_SHIFT=14
860CONFIG_CROSSCOMPILE=y 980CONFIG_CROSSCOMPILE=y
861CONFIG_CMDLINE="ip=any root=nfs" 981CONFIG_CMDLINE="ip=any root=nfs"
862 982
@@ -869,7 +989,31 @@ CONFIG_CMDLINE="ip=any root=nfs"
869# 989#
870# Cryptographic options 990# Cryptographic options
871# 991#
872# CONFIG_CRYPTO is not set 992CONFIG_CRYPTO=y
993CONFIG_CRYPTO_HMAC=y
994CONFIG_CRYPTO_NULL=m
995CONFIG_CRYPTO_MD4=m
996CONFIG_CRYPTO_MD5=m
997CONFIG_CRYPTO_SHA1=m
998CONFIG_CRYPTO_SHA256=m
999CONFIG_CRYPTO_SHA512=m
1000CONFIG_CRYPTO_WP512=m
1001CONFIG_CRYPTO_TGR192=m
1002CONFIG_CRYPTO_DES=m
1003CONFIG_CRYPTO_BLOWFISH=m
1004CONFIG_CRYPTO_TWOFISH=m
1005CONFIG_CRYPTO_SERPENT=m
1006CONFIG_CRYPTO_AES=m
1007CONFIG_CRYPTO_CAST5=m
1008CONFIG_CRYPTO_CAST6=m
1009CONFIG_CRYPTO_TEA=m
1010CONFIG_CRYPTO_ARC4=m
1011CONFIG_CRYPTO_KHAZAD=m
1012CONFIG_CRYPTO_ANUBIS=m
1013CONFIG_CRYPTO_DEFLATE=m
1014CONFIG_CRYPTO_MICHAEL_MIC=m
1015CONFIG_CRYPTO_CRC32C=m
1016# CONFIG_CRYPTO_TEST is not set
873 1017
874# 1018#
875# Hardware crypto devices 1019# Hardware crypto devices
@@ -879,9 +1023,8 @@ CONFIG_CMDLINE="ip=any root=nfs"
879# Library routines 1023# Library routines
880# 1024#
881CONFIG_CRC_CCITT=m 1025CONFIG_CRC_CCITT=m
1026CONFIG_CRC16=m
882CONFIG_CRC32=y 1027CONFIG_CRC32=y
883CONFIG_LIBCRC32C=m 1028CONFIG_LIBCRC32C=m
884CONFIG_ZLIB_INFLATE=y 1029CONFIG_ZLIB_INFLATE=y
885CONFIG_ZLIB_DEFLATE=m 1030CONFIG_ZLIB_DEFLATE=m
886CONFIG_GENERIC_HARDIRQS=y
887CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig
index a38903db85a0..d3a5fee02b79 100644
--- a/arch/mips/configs/ocelot_c_defconfig
+++ b/arch/mips/configs/ocelot_c_defconfig
@@ -1,11 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:07 2005 4# Thu Oct 20 22:26:33 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7CONFIG_64BIT=y
8CONFIG_64BIT=y
9 7
10# 8#
11# Code maturity level options 9# Code maturity level options
@@ -13,24 +11,29 @@ CONFIG_64BIT=y
13CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
14CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
15CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
16 15
17# 16#
18# General setup 17# General setup
19# 18#
20CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
21CONFIG_SWAP=y 21CONFIG_SWAP=y
22CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
23# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
24# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
27CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
28# CONFIG_HOTPLUG is not set
29CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
30# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
31CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
32CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
33# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
34CONFIG_FUTEX=y 37CONFIG_FUTEX=y
35CONFIG_EPOLL=y 38CONFIG_EPOLL=y
36# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -40,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
40CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
41CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
42# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
43 47
44# 48#
45# Loadable module support 49# Loadable module support
@@ -49,39 +53,68 @@ CONFIG_CC_ALIGN_JUMPS=0
49# 53#
50# Machine selection 54# Machine selection
51# 55#
52# CONFIG_MACH_JAZZ is not set 56# CONFIG_MIPS_MTX1 is not set
53# CONFIG_MACH_VR41XX is not set 57# CONFIG_MIPS_BOSPORUS is not set
58# CONFIG_MIPS_PB1000 is not set
59# CONFIG_MIPS_PB1100 is not set
60# CONFIG_MIPS_PB1500 is not set
61# CONFIG_MIPS_PB1550 is not set
62# CONFIG_MIPS_PB1200 is not set
63# CONFIG_MIPS_DB1000 is not set
64# CONFIG_MIPS_DB1100 is not set
65# CONFIG_MIPS_DB1500 is not set
66# CONFIG_MIPS_DB1550 is not set
67# CONFIG_MIPS_DB1200 is not set
68# CONFIG_MIPS_MIRAGE is not set
54# CONFIG_MIPS_COBALT is not set 69# CONFIG_MIPS_COBALT is not set
55# CONFIG_MACH_DECSTATION is not set 70# CONFIG_MACH_DECSTATION is not set
56# CONFIG_MIPS_EV64120 is not set 71# CONFIG_MIPS_EV64120 is not set
57# CONFIG_MIPS_EV96100 is not set 72# CONFIG_MIPS_EV96100 is not set
58# CONFIG_MIPS_IVR is not set 73# CONFIG_MIPS_IVR is not set
59# CONFIG_LASAT is not set
60# CONFIG_MIPS_ITE8172 is not set 74# CONFIG_MIPS_ITE8172 is not set
75# CONFIG_MACH_JAZZ is not set
76# CONFIG_LASAT is not set
61# CONFIG_MIPS_ATLAS is not set 77# CONFIG_MIPS_ATLAS is not set
62# CONFIG_MIPS_MALTA is not set 78# CONFIG_MIPS_MALTA is not set
63# CONFIG_MIPS_SEAD is not set 79# CONFIG_MIPS_SEAD is not set
80# CONFIG_MIPS_SIM is not set
81# CONFIG_MOMENCO_JAGUAR_ATX is not set
64# CONFIG_MOMENCO_OCELOT is not set 82# CONFIG_MOMENCO_OCELOT is not set
65# CONFIG_MOMENCO_OCELOT_G is not set
66CONFIG_MOMENCO_OCELOT_C=y
67# CONFIG_MOMENCO_OCELOT_3 is not set 83# CONFIG_MOMENCO_OCELOT_3 is not set
68# CONFIG_MOMENCO_JAGUAR_ATX is not set 84CONFIG_MOMENCO_OCELOT_C=y
69# CONFIG_PMC_YOSEMITE is not set 85# CONFIG_MOMENCO_OCELOT_G is not set
86# CONFIG_MIPS_XXS1500 is not set
87# CONFIG_PNX8550_V2PCI is not set
88# CONFIG_PNX8550_JBS is not set
70# CONFIG_DDB5074 is not set 89# CONFIG_DDB5074 is not set
71# CONFIG_DDB5476 is not set 90# CONFIG_DDB5476 is not set
72# CONFIG_DDB5477 is not set 91# CONFIG_DDB5477 is not set
73# CONFIG_NEC_OSPREY is not set 92# CONFIG_MACH_VR41XX is not set
93# CONFIG_PMC_YOSEMITE is not set
94# CONFIG_QEMU is not set
74# CONFIG_SGI_IP22 is not set 95# CONFIG_SGI_IP22 is not set
75# CONFIG_SGI_IP27 is not set 96# CONFIG_SGI_IP27 is not set
76# CONFIG_SGI_IP32 is not set 97# CONFIG_SGI_IP32 is not set
77# CONFIG_SIBYTE_SB1xxx_SOC is not set 98# CONFIG_SIBYTE_BIGSUR is not set
99# CONFIG_SIBYTE_SWARM is not set
100# CONFIG_SIBYTE_SENTOSA is not set
101# CONFIG_SIBYTE_RHONE is not set
102# CONFIG_SIBYTE_CARMEL is not set
103# CONFIG_SIBYTE_PTSWARM is not set
104# CONFIG_SIBYTE_LITTLESUR is not set
105# CONFIG_SIBYTE_CRHINE is not set
106# CONFIG_SIBYTE_CRHONE is not set
78# CONFIG_SNI_RM200_PCI is not set 107# CONFIG_SNI_RM200_PCI is not set
108# CONFIG_TOSHIBA_JMR3927 is not set
109# CONFIG_TOSHIBA_RBTX4927 is not set
110# CONFIG_TOSHIBA_RBTX4938 is not set
79CONFIG_RWSEM_GENERIC_SPINLOCK=y 111CONFIG_RWSEM_GENERIC_SPINLOCK=y
80CONFIG_GENERIC_CALIBRATE_DELAY=y 112CONFIG_GENERIC_CALIBRATE_DELAY=y
81CONFIG_HAVE_DEC_LOCK=y
82CONFIG_DMA_NONCOHERENT=y 113CONFIG_DMA_NONCOHERENT=y
83CONFIG_DMA_NEED_PCI_MAP_STATE=y 114CONFIG_DMA_NEED_PCI_MAP_STATE=y
115CONFIG_CPU_BIG_ENDIAN=y
84# CONFIG_CPU_LITTLE_ENDIAN is not set 116# CONFIG_CPU_LITTLE_ENDIAN is not set
117CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
85CONFIG_IRQ_CPU=y 118CONFIG_IRQ_CPU=y
86CONFIG_IRQ_MV64340=y 119CONFIG_IRQ_MV64340=y
87CONFIG_PCI_MARVELL=y 120CONFIG_PCI_MARVELL=y
@@ -91,8 +124,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
91# 124#
92# CPU selection 125# CPU selection
93# 126#
94# CONFIG_CPU_MIPS32 is not set 127# CONFIG_CPU_MIPS32_R1 is not set
95# CONFIG_CPU_MIPS64 is not set 128# CONFIG_CPU_MIPS32_R2 is not set
129# CONFIG_CPU_MIPS64_R1 is not set
130# CONFIG_CPU_MIPS64_R2 is not set
96# CONFIG_CPU_R3000 is not set 131# CONFIG_CPU_R3000 is not set
97# CONFIG_CPU_TX39XX is not set 132# CONFIG_CPU_TX39XX is not set
98# CONFIG_CPU_VR41XX is not set 133# CONFIG_CPU_VR41XX is not set
@@ -108,6 +143,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
108CONFIG_CPU_RM7000=y 143CONFIG_CPU_RM7000=y
109# CONFIG_CPU_RM9000 is not set 144# CONFIG_CPU_RM9000 is not set
110# CONFIG_CPU_SB1 is not set 145# CONFIG_CPU_SB1 is not set
146CONFIG_SYS_HAS_CPU_RM7000=y
147CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
148CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
149CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
150CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
151
152#
153# Kernel type
154#
155# CONFIG_32BIT is not set
156CONFIG_64BIT=y
111CONFIG_PAGE_SIZE_4KB=y 157CONFIG_PAGE_SIZE_4KB=y
112# CONFIG_PAGE_SIZE_8KB is not set 158# CONFIG_PAGE_SIZE_8KB is not set
113# CONFIG_PAGE_SIZE_16KB is not set 159# CONFIG_PAGE_SIZE_16KB is not set
@@ -115,9 +161,23 @@ CONFIG_PAGE_SIZE_4KB=y
115CONFIG_BOARD_SCACHE=y 161CONFIG_BOARD_SCACHE=y
116CONFIG_RM7000_CPU_SCACHE=y 162CONFIG_RM7000_CPU_SCACHE=y
117CONFIG_CPU_HAS_PREFETCH=y 163CONFIG_CPU_HAS_PREFETCH=y
164# CONFIG_MIPS_MT is not set
118CONFIG_CPU_HAS_LLSC=y 165CONFIG_CPU_HAS_LLSC=y
119CONFIG_CPU_HAS_LLDSCD=y 166CONFIG_CPU_HAS_LLDSCD=y
120CONFIG_CPU_HAS_SYNC=y 167CONFIG_CPU_HAS_SYNC=y
168CONFIG_GENERIC_HARDIRQS=y
169CONFIG_GENERIC_IRQ_PROBE=y
170CONFIG_CPU_SUPPORTS_HIGHMEM=y
171CONFIG_ARCH_FLATMEM_ENABLE=y
172CONFIG_SELECT_MEMORY_MODEL=y
173CONFIG_FLATMEM_MANUAL=y
174# CONFIG_DISCONTIGMEM_MANUAL is not set
175# CONFIG_SPARSEMEM_MANUAL is not set
176CONFIG_FLATMEM=y
177CONFIG_FLAT_NODE_MEM_MAP=y
178# CONFIG_SPARSEMEM_STATIC is not set
179CONFIG_PREEMPT_NONE=y
180# CONFIG_PREEMPT_VOLUNTARY is not set
121# CONFIG_PREEMPT is not set 181# CONFIG_PREEMPT is not set
122 182
123# 183#
@@ -126,7 +186,6 @@ CONFIG_CPU_HAS_SYNC=y
126CONFIG_HW_HAS_PCI=y 186CONFIG_HW_HAS_PCI=y
127CONFIG_PCI=y 187CONFIG_PCI=y
128CONFIG_PCI_LEGACY_PROC=y 188CONFIG_PCI_LEGACY_PROC=y
129CONFIG_PCI_NAMES=y
130CONFIG_MMU=y 189CONFIG_MMU=y
131 190
132# 191#
@@ -135,10 +194,6 @@ CONFIG_MMU=y
135# CONFIG_PCCARD is not set 194# CONFIG_PCCARD is not set
136 195
137# 196#
138# PC-card bridges
139#
140
141#
142# PCI Hotplug Support 197# PCI Hotplug Support
143# 198#
144# CONFIG_HOTPLUG_PCI is not set 199# CONFIG_HOTPLUG_PCI is not set
@@ -156,6 +211,79 @@ CONFIG_MIPS32_N32=y
156CONFIG_BINFMT_ELF32=y 211CONFIG_BINFMT_ELF32=y
157 212
158# 213#
214# Networking
215#
216CONFIG_NET=y
217
218#
219# Networking options
220#
221# CONFIG_PACKET is not set
222CONFIG_UNIX=y
223CONFIG_XFRM=y
224CONFIG_XFRM_USER=y
225CONFIG_NET_KEY=y
226CONFIG_INET=y
227# CONFIG_IP_MULTICAST is not set
228# CONFIG_IP_ADVANCED_ROUTER is not set
229CONFIG_IP_FIB_HASH=y
230CONFIG_IP_PNP=y
231CONFIG_IP_PNP_DHCP=y
232# CONFIG_IP_PNP_BOOTP is not set
233# CONFIG_IP_PNP_RARP is not set
234# CONFIG_NET_IPIP is not set
235# CONFIG_NET_IPGRE is not set
236# CONFIG_ARPD is not set
237# CONFIG_SYN_COOKIES is not set
238# CONFIG_INET_AH is not set
239# CONFIG_INET_ESP is not set
240# CONFIG_INET_IPCOMP is not set
241CONFIG_INET_TUNNEL=y
242CONFIG_INET_DIAG=y
243CONFIG_INET_TCP_DIAG=y
244# CONFIG_TCP_CONG_ADVANCED is not set
245CONFIG_TCP_CONG_BIC=y
246# CONFIG_IPV6 is not set
247# CONFIG_NETFILTER is not set
248
249#
250# DCCP Configuration (EXPERIMENTAL)
251#
252# CONFIG_IP_DCCP is not set
253
254#
255# SCTP Configuration (EXPERIMENTAL)
256#
257# CONFIG_IP_SCTP is not set
258# CONFIG_ATM is not set
259# CONFIG_BRIDGE is not set
260# CONFIG_VLAN_8021Q is not set
261# CONFIG_DECNET is not set
262# CONFIG_LLC2 is not set
263# CONFIG_IPX is not set
264# CONFIG_ATALK is not set
265# CONFIG_X25 is not set
266# CONFIG_LAPB is not set
267# CONFIG_NET_DIVERT is not set
268# CONFIG_ECONET is not set
269# CONFIG_WAN_ROUTER is not set
270# CONFIG_NET_SCHED is not set
271# CONFIG_NET_CLS_ROUTE is not set
272
273#
274# Network testing
275#
276# CONFIG_NET_PKTGEN is not set
277# CONFIG_HAMRADIO is not set
278# CONFIG_IRDA is not set
279# CONFIG_BT is not set
280CONFIG_IEEE80211=y
281# CONFIG_IEEE80211_DEBUG is not set
282CONFIG_IEEE80211_CRYPT_WEP=y
283CONFIG_IEEE80211_CRYPT_CCMP=y
284CONFIG_IEEE80211_CRYPT_TKIP=y
285
286#
159# Device Drivers 287# Device Drivers
160# 288#
161 289
@@ -164,7 +292,12 @@ CONFIG_BINFMT_ELF32=y
164# 292#
165CONFIG_STANDALONE=y 293CONFIG_STANDALONE=y
166CONFIG_PREVENT_FIRMWARE_BUILD=y 294CONFIG_PREVENT_FIRMWARE_BUILD=y
167# CONFIG_FW_LOADER is not set 295CONFIG_FW_LOADER=y
296
297#
298# Connector - unified userspace <-> kernelspace linker
299#
300CONFIG_CONNECTOR=y
168 301
169# 302#
170# Memory Technology Devices (MTD) 303# Memory Technology Devices (MTD)
@@ -183,7 +316,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
183# 316#
184# Block devices 317# Block devices
185# 318#
186# CONFIG_BLK_DEV_FD is not set
187# CONFIG_BLK_CPQ_DA is not set 319# CONFIG_BLK_CPQ_DA is not set
188# CONFIG_BLK_CPQ_CISS_DA is not set 320# CONFIG_BLK_CPQ_CISS_DA is not set
189# CONFIG_BLK_DEV_DAC960 is not set 321# CONFIG_BLK_DEV_DAC960 is not set
@@ -194,7 +326,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
194# CONFIG_BLK_DEV_SX8 is not set 326# CONFIG_BLK_DEV_SX8 is not set
195# CONFIG_BLK_DEV_RAM is not set 327# CONFIG_BLK_DEV_RAM is not set
196CONFIG_BLK_DEV_RAM_COUNT=16 328CONFIG_BLK_DEV_RAM_COUNT=16
197CONFIG_INITRAMFS_SOURCE=""
198CONFIG_CDROM_PKTCDVD=y 329CONFIG_CDROM_PKTCDVD=y
199CONFIG_CDROM_PKTCDVD_BUFFERS=8 330CONFIG_CDROM_PKTCDVD_BUFFERS=8
200# CONFIG_CDROM_PKTCDVD_WCACHE is not set 331# CONFIG_CDROM_PKTCDVD_WCACHE is not set
@@ -216,6 +347,7 @@ CONFIG_ATA_OVER_ETH=y
216# 347#
217# SCSI device support 348# SCSI device support
218# 349#
350CONFIG_RAID_ATTRS=y
219# CONFIG_SCSI is not set 351# CONFIG_SCSI is not set
220 352
221# 353#
@@ -226,6 +358,7 @@ CONFIG_ATA_OVER_ETH=y
226# 358#
227# Fusion MPT device support 359# Fusion MPT device support
228# 360#
361# CONFIG_FUSION is not set
229 362
230# 363#
231# IEEE 1394 (FireWire) support 364# IEEE 1394 (FireWire) support
@@ -238,77 +371,13 @@ CONFIG_ATA_OVER_ETH=y
238# CONFIG_I2O is not set 371# CONFIG_I2O is not set
239 372
240# 373#
241# Networking support 374# Network device support
242#
243CONFIG_NET=y
244
245#
246# Networking options
247#
248# CONFIG_PACKET is not set
249CONFIG_NETLINK_DEV=y
250CONFIG_UNIX=y
251CONFIG_NET_KEY=y
252CONFIG_INET=y
253# CONFIG_IP_MULTICAST is not set
254# CONFIG_IP_ADVANCED_ROUTER is not set
255CONFIG_IP_PNP=y
256CONFIG_IP_PNP_DHCP=y
257# CONFIG_IP_PNP_BOOTP is not set
258# CONFIG_IP_PNP_RARP is not set
259# CONFIG_NET_IPIP is not set
260# CONFIG_NET_IPGRE is not set
261# CONFIG_ARPD is not set
262# CONFIG_SYN_COOKIES is not set
263# CONFIG_INET_AH is not set
264# CONFIG_INET_ESP is not set
265# CONFIG_INET_IPCOMP is not set
266CONFIG_INET_TUNNEL=y
267CONFIG_IP_TCPDIAG=y
268# CONFIG_IP_TCPDIAG_IPV6 is not set
269# CONFIG_IPV6 is not set
270# CONFIG_NETFILTER is not set
271CONFIG_XFRM=y
272CONFIG_XFRM_USER=y
273
274#
275# SCTP Configuration (EXPERIMENTAL)
276#
277# CONFIG_IP_SCTP is not set
278# CONFIG_ATM is not set
279# CONFIG_BRIDGE is not set
280# CONFIG_VLAN_8021Q is not set
281# CONFIG_DECNET is not set
282# CONFIG_LLC2 is not set
283# CONFIG_IPX is not set
284# CONFIG_ATALK is not set
285# CONFIG_X25 is not set
286# CONFIG_LAPB is not set
287# CONFIG_NET_DIVERT is not set
288# CONFIG_ECONET is not set
289# CONFIG_WAN_ROUTER is not set
290
291#
292# QoS and/or fair queueing
293#
294# CONFIG_NET_SCHED is not set
295# CONFIG_NET_CLS_ROUTE is not set
296
297#
298# Network testing
299# 375#
300# CONFIG_NET_PKTGEN is not set
301# CONFIG_NETPOLL is not set
302# CONFIG_NET_POLL_CONTROLLER is not set
303# CONFIG_HAMRADIO is not set
304# CONFIG_IRDA is not set
305# CONFIG_BT is not set
306CONFIG_NETDEVICES=y 376CONFIG_NETDEVICES=y
307# CONFIG_DUMMY is not set 377# CONFIG_DUMMY is not set
308# CONFIG_BONDING is not set 378# CONFIG_BONDING is not set
309# CONFIG_EQUALIZER is not set 379# CONFIG_EQUALIZER is not set
310# CONFIG_TUN is not set 380# CONFIG_TUN is not set
311# CONFIG_ETHERTAP is not set
312 381
313# 382#
314# ARCnet devices 383# ARCnet devices
@@ -316,6 +385,21 @@ CONFIG_NETDEVICES=y
316# CONFIG_ARCNET is not set 385# CONFIG_ARCNET is not set
317 386
318# 387#
388# PHY device support
389#
390CONFIG_PHYLIB=y
391CONFIG_PHYCONTROL=y
392
393#
394# MII PHY device drivers
395#
396CONFIG_MARVELL_PHY=y
397CONFIG_DAVICOM_PHY=y
398CONFIG_QSEMI_PHY=y
399CONFIG_LXT_PHY=y
400CONFIG_CICADA_PHY=y
401
402#
319# Ethernet (10 or 100Mbit) 403# Ethernet (10 or 100Mbit)
320# 404#
321CONFIG_NET_ETHERNET=y 405CONFIG_NET_ETHERNET=y
@@ -341,13 +425,17 @@ CONFIG_NET_ETHERNET=y
341# CONFIG_HAMACHI is not set 425# CONFIG_HAMACHI is not set
342# CONFIG_YELLOWFIN is not set 426# CONFIG_YELLOWFIN is not set
343# CONFIG_R8169 is not set 427# CONFIG_R8169 is not set
428# CONFIG_SIS190 is not set
429# CONFIG_SKGE is not set
344# CONFIG_SK98LIN is not set 430# CONFIG_SK98LIN is not set
345# CONFIG_TIGON3 is not set 431# CONFIG_TIGON3 is not set
432# CONFIG_BNX2 is not set
346# CONFIG_MV643XX_ETH is not set 433# CONFIG_MV643XX_ETH is not set
347 434
348# 435#
349# Ethernet (10000 Mbit) 436# Ethernet (10000 Mbit)
350# 437#
438# CONFIG_CHELSIO_T1 is not set
351# CONFIG_IXGB is not set 439# CONFIG_IXGB is not set
352# CONFIG_S2IO is not set 440# CONFIG_S2IO is not set
353 441
@@ -360,6 +448,8 @@ CONFIG_NET_ETHERNET=y
360# Wireless LAN (non-hamradio) 448# Wireless LAN (non-hamradio)
361# 449#
362# CONFIG_NET_RADIO is not set 450# CONFIG_NET_RADIO is not set
451# CONFIG_IPW_DEBUG is not set
452CONFIG_IPW2200=y
363 453
364# 454#
365# Wan interfaces 455# Wan interfaces
@@ -371,6 +461,8 @@ CONFIG_NET_ETHERNET=y
371# CONFIG_SLIP is not set 461# CONFIG_SLIP is not set
372# CONFIG_SHAPER is not set 462# CONFIG_SHAPER is not set
373# CONFIG_NETCONSOLE is not set 463# CONFIG_NETCONSOLE is not set
464# CONFIG_NETPOLL is not set
465# CONFIG_NET_POLL_CONTROLLER is not set
374 466
375# 467#
376# ISDN subsystem 468# ISDN subsystem
@@ -400,19 +492,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
400# CONFIG_INPUT_EVBUG is not set 492# CONFIG_INPUT_EVBUG is not set
401 493
402# 494#
403# Input I/O drivers
404#
405# CONFIG_GAMEPORT is not set
406CONFIG_SOUND_GAMEPORT=y
407CONFIG_SERIO=y
408# CONFIG_SERIO_I8042 is not set
409CONFIG_SERIO_SERPORT=y
410# CONFIG_SERIO_CT82C710 is not set
411# CONFIG_SERIO_PCIPS2 is not set
412# CONFIG_SERIO_LIBPS2 is not set
413CONFIG_SERIO_RAW=y
414
415#
416# Input Device Drivers 495# Input Device Drivers
417# 496#
418# CONFIG_INPUT_KEYBOARD is not set 497# CONFIG_INPUT_KEYBOARD is not set
@@ -422,6 +501,17 @@ CONFIG_SERIO_RAW=y
422# CONFIG_INPUT_MISC is not set 501# CONFIG_INPUT_MISC is not set
423 502
424# 503#
504# Hardware I/O ports
505#
506CONFIG_SERIO=y
507# CONFIG_SERIO_I8042 is not set
508CONFIG_SERIO_SERPORT=y
509# CONFIG_SERIO_PCIPS2 is not set
510# CONFIG_SERIO_LIBPS2 is not set
511CONFIG_SERIO_RAW=y
512# CONFIG_GAMEPORT is not set
513
514#
425# Character devices 515# Character devices
426# 516#
427CONFIG_VT=y 517CONFIG_VT=y
@@ -442,6 +532,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
442# 532#
443CONFIG_SERIAL_CORE=y 533CONFIG_SERIAL_CORE=y
444CONFIG_SERIAL_CORE_CONSOLE=y 534CONFIG_SERIAL_CORE_CONSOLE=y
535# CONFIG_SERIAL_JSM is not set
445CONFIG_UNIX98_PTYS=y 536CONFIG_UNIX98_PTYS=y
446CONFIG_LEGACY_PTYS=y 537CONFIG_LEGACY_PTYS=y
447CONFIG_LEGACY_PTY_COUNT=256 538CONFIG_LEGACY_PTY_COUNT=256
@@ -468,6 +559,11 @@ CONFIG_LEGACY_PTY_COUNT=256
468# CONFIG_RAW_DRIVER is not set 559# CONFIG_RAW_DRIVER is not set
469 560
470# 561#
562# TPM devices
563#
564# CONFIG_TCG_TPM is not set
565
566#
471# I2C support 567# I2C support
472# 568#
473# CONFIG_I2C is not set 569# CONFIG_I2C is not set
@@ -478,10 +574,20 @@ CONFIG_LEGACY_PTY_COUNT=256
478# CONFIG_W1 is not set 574# CONFIG_W1 is not set
479 575
480# 576#
577# Hardware Monitoring support
578#
579# CONFIG_HWMON is not set
580# CONFIG_HWMON_VID is not set
581
582#
481# Misc devices 583# Misc devices
482# 584#
483 585
484# 586#
587# Multimedia Capabilities Port drivers
588#
589
590#
485# Multimedia devices 591# Multimedia devices
486# 592#
487# CONFIG_VIDEO_DEV is not set 593# CONFIG_VIDEO_DEV is not set
@@ -501,7 +607,6 @@ CONFIG_LEGACY_PTY_COUNT=256
501# 607#
502# CONFIG_VGA_CONSOLE is not set 608# CONFIG_VGA_CONSOLE is not set
503CONFIG_DUMMY_CONSOLE=y 609CONFIG_DUMMY_CONSOLE=y
504# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
505 610
506# 611#
507# Sound 612# Sound
@@ -511,13 +616,9 @@ CONFIG_DUMMY_CONSOLE=y
511# 616#
512# USB support 617# USB support
513# 618#
514# CONFIG_USB is not set
515CONFIG_USB_ARCH_HAS_HCD=y 619CONFIG_USB_ARCH_HAS_HCD=y
516CONFIG_USB_ARCH_HAS_OHCI=y 620CONFIG_USB_ARCH_HAS_OHCI=y
517 621# CONFIG_USB is not set
518#
519# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
520#
521 622
522# 623#
523# USB Gadget Support 624# USB Gadget Support
@@ -535,21 +636,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y
535# CONFIG_INFINIBAND is not set 636# CONFIG_INFINIBAND is not set
536 637
537# 638#
639# SN Devices
640#
641
642#
538# File systems 643# File systems
539# 644#
540CONFIG_EXT2_FS=y 645CONFIG_EXT2_FS=y
541# CONFIG_EXT2_FS_XATTR is not set 646# CONFIG_EXT2_FS_XATTR is not set
647# CONFIG_EXT2_FS_XIP is not set
542# CONFIG_EXT3_FS is not set 648# CONFIG_EXT3_FS is not set
543# CONFIG_JBD is not set 649# CONFIG_JBD is not set
544# CONFIG_REISERFS_FS is not set 650# CONFIG_REISERFS_FS is not set
545# CONFIG_JFS_FS is not set 651# CONFIG_JFS_FS is not set
652# CONFIG_FS_POSIX_ACL is not set
546# CONFIG_XFS_FS is not set 653# CONFIG_XFS_FS is not set
547# CONFIG_MINIX_FS is not set 654# CONFIG_MINIX_FS is not set
548# CONFIG_ROMFS_FS is not set 655# CONFIG_ROMFS_FS is not set
656CONFIG_INOTIFY=y
549# CONFIG_QUOTA is not set 657# CONFIG_QUOTA is not set
550CONFIG_DNOTIFY=y 658CONFIG_DNOTIFY=y
551# CONFIG_AUTOFS_FS is not set 659# CONFIG_AUTOFS_FS is not set
552# CONFIG_AUTOFS4_FS is not set 660# CONFIG_AUTOFS4_FS is not set
661CONFIG_FUSE_FS=y
553 662
554# 663#
555# CD-ROM/DVD Filesystems 664# CD-ROM/DVD Filesystems
@@ -570,12 +679,10 @@ CONFIG_DNOTIFY=y
570CONFIG_PROC_FS=y 679CONFIG_PROC_FS=y
571CONFIG_PROC_KCORE=y 680CONFIG_PROC_KCORE=y
572CONFIG_SYSFS=y 681CONFIG_SYSFS=y
573# CONFIG_DEVFS_FS is not set
574CONFIG_DEVPTS_FS_XATTR=y
575CONFIG_DEVPTS_FS_SECURITY=y
576# CONFIG_TMPFS is not set 682# CONFIG_TMPFS is not set
577# CONFIG_HUGETLB_PAGE is not set 683# CONFIG_HUGETLB_PAGE is not set
578CONFIG_RAMFS=y 684CONFIG_RAMFS=y
685CONFIG_RELAYFS_FS=y
579 686
580# 687#
581# Miscellaneous filesystems 688# Miscellaneous filesystems
@@ -607,6 +714,7 @@ CONFIG_NFSD=y
607CONFIG_ROOT_NFS=y 714CONFIG_ROOT_NFS=y
608CONFIG_LOCKD=y 715CONFIG_LOCKD=y
609CONFIG_EXPORTFS=y 716CONFIG_EXPORTFS=y
717CONFIG_NFS_COMMON=y
610CONFIG_SUNRPC=y 718CONFIG_SUNRPC=y
611# CONFIG_RPCSEC_GSS_KRB5 is not set 719# CONFIG_RPCSEC_GSS_KRB5 is not set
612# CONFIG_RPCSEC_GSS_SPKM3 is not set 720# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -615,6 +723,7 @@ CONFIG_SUNRPC=y
615# CONFIG_NCP_FS is not set 723# CONFIG_NCP_FS is not set
616# CONFIG_CODA_FS is not set 724# CONFIG_CODA_FS is not set
617# CONFIG_AFS_FS is not set 725# CONFIG_AFS_FS is not set
726# CONFIG_9P_FS is not set
618 727
619# 728#
620# Partition Types 729# Partition Types
@@ -635,7 +744,9 @@ CONFIG_MSDOS_PARTITION=y
635# 744#
636# Kernel hacking 745# Kernel hacking
637# 746#
747# CONFIG_PRINTK_TIME is not set
638# CONFIG_DEBUG_KERNEL is not set 748# CONFIG_DEBUG_KERNEL is not set
749CONFIG_LOG_BUF_SHIFT=14
639CONFIG_CROSSCOMPILE=y 750CONFIG_CROSSCOMPILE=y
640CONFIG_CMDLINE="" 751CONFIG_CMDLINE=""
641 752
@@ -649,7 +760,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
649# 760#
650# Cryptographic options 761# Cryptographic options
651# 762#
652# CONFIG_CRYPTO is not set 763CONFIG_CRYPTO=y
764CONFIG_CRYPTO_HMAC=y
765CONFIG_CRYPTO_NULL=y
766CONFIG_CRYPTO_MD4=y
767CONFIG_CRYPTO_MD5=y
768CONFIG_CRYPTO_SHA1=y
769CONFIG_CRYPTO_SHA256=y
770CONFIG_CRYPTO_SHA512=y
771CONFIG_CRYPTO_WP512=y
772CONFIG_CRYPTO_TGR192=y
773CONFIG_CRYPTO_DES=y
774CONFIG_CRYPTO_BLOWFISH=y
775CONFIG_CRYPTO_TWOFISH=y
776CONFIG_CRYPTO_SERPENT=y
777CONFIG_CRYPTO_AES=y
778CONFIG_CRYPTO_CAST5=y
779CONFIG_CRYPTO_CAST6=y
780CONFIG_CRYPTO_TEA=y
781CONFIG_CRYPTO_ARC4=y
782CONFIG_CRYPTO_KHAZAD=y
783CONFIG_CRYPTO_ANUBIS=y
784CONFIG_CRYPTO_DEFLATE=y
785CONFIG_CRYPTO_MICHAEL_MIC=y
786CONFIG_CRYPTO_CRC32C=y
787# CONFIG_CRYPTO_TEST is not set
653 788
654# 789#
655# Hardware crypto devices 790# Hardware crypto devices
@@ -659,7 +794,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
659# Library routines 794# Library routines
660# 795#
661# CONFIG_CRC_CCITT is not set 796# CONFIG_CRC_CCITT is not set
662# CONFIG_CRC32 is not set 797CONFIG_CRC16=y
663# CONFIG_LIBCRC32C is not set 798CONFIG_CRC32=y
664CONFIG_GENERIC_HARDIRQS=y 799CONFIG_LIBCRC32C=y
665CONFIG_GENERIC_IRQ_PROBE=y 800CONFIG_ZLIB_INFLATE=y
801CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig
index 920d59b56a4e..1edde12ebff9 100644
--- a/arch/mips/configs/ocelot_defconfig
+++ b/arch/mips/configs/ocelot_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:08 2005 4# Thu Oct 20 22:26:35 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29# CONFIG_HOTPLUG is not set 27# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -50,40 +53,68 @@ CONFIG_CC_ALIGN_JUMPS=0
50# 53#
51# Machine selection 54# Machine selection
52# 55#
53# CONFIG_MACH_JAZZ is not set 56# CONFIG_MIPS_MTX1 is not set
54# CONFIG_MACH_VR41XX is not set 57# CONFIG_MIPS_BOSPORUS is not set
55# CONFIG_TOSHIBA_JMR3927 is not set 58# CONFIG_MIPS_PB1000 is not set
59# CONFIG_MIPS_PB1100 is not set
60# CONFIG_MIPS_PB1500 is not set
61# CONFIG_MIPS_PB1550 is not set
62# CONFIG_MIPS_PB1200 is not set
63# CONFIG_MIPS_DB1000 is not set
64# CONFIG_MIPS_DB1100 is not set
65# CONFIG_MIPS_DB1500 is not set
66# CONFIG_MIPS_DB1550 is not set
67# CONFIG_MIPS_DB1200 is not set
68# CONFIG_MIPS_MIRAGE is not set
56# CONFIG_MIPS_COBALT is not set 69# CONFIG_MIPS_COBALT is not set
57# CONFIG_MACH_DECSTATION is not set 70# CONFIG_MACH_DECSTATION is not set
58# CONFIG_MIPS_EV64120 is not set 71# CONFIG_MIPS_EV64120 is not set
59# CONFIG_MIPS_EV96100 is not set 72# CONFIG_MIPS_EV96100 is not set
60# CONFIG_MIPS_IVR is not set 73# CONFIG_MIPS_IVR is not set
61# CONFIG_LASAT is not set
62# CONFIG_MIPS_ITE8172 is not set 74# CONFIG_MIPS_ITE8172 is not set
75# CONFIG_MACH_JAZZ is not set
76# CONFIG_LASAT is not set
63# CONFIG_MIPS_ATLAS is not set 77# CONFIG_MIPS_ATLAS is not set
64# CONFIG_MIPS_MALTA is not set 78# CONFIG_MIPS_MALTA is not set
65# CONFIG_MIPS_SEAD is not set 79# CONFIG_MIPS_SEAD is not set
80# CONFIG_MIPS_SIM is not set
81# CONFIG_MOMENCO_JAGUAR_ATX is not set
66CONFIG_MOMENCO_OCELOT=y 82CONFIG_MOMENCO_OCELOT=y
67# CONFIG_MOMENCO_OCELOT_G is not set
68# CONFIG_MOMENCO_OCELOT_C is not set
69# CONFIG_MOMENCO_OCELOT_3 is not set 83# CONFIG_MOMENCO_OCELOT_3 is not set
70# CONFIG_MOMENCO_JAGUAR_ATX is not set 84# CONFIG_MOMENCO_OCELOT_C is not set
71# CONFIG_PMC_YOSEMITE is not set 85# CONFIG_MOMENCO_OCELOT_G is not set
86# CONFIG_MIPS_XXS1500 is not set
87# CONFIG_PNX8550_V2PCI is not set
88# CONFIG_PNX8550_JBS is not set
72# CONFIG_DDB5074 is not set 89# CONFIG_DDB5074 is not set
73# CONFIG_DDB5476 is not set 90# CONFIG_DDB5476 is not set
74# CONFIG_DDB5477 is not set 91# CONFIG_DDB5477 is not set
75# CONFIG_NEC_OSPREY is not set 92# CONFIG_MACH_VR41XX is not set
93# CONFIG_PMC_YOSEMITE is not set
94# CONFIG_QEMU is not set
76# CONFIG_SGI_IP22 is not set 95# CONFIG_SGI_IP22 is not set
77# CONFIG_SOC_AU1X00 is not set 96# CONFIG_SGI_IP27 is not set
78# CONFIG_SIBYTE_SB1xxx_SOC is not set 97# CONFIG_SGI_IP32 is not set
98# CONFIG_SIBYTE_BIGSUR is not set
99# CONFIG_SIBYTE_SWARM is not set
100# CONFIG_SIBYTE_SENTOSA is not set
101# CONFIG_SIBYTE_RHONE is not set
102# CONFIG_SIBYTE_CARMEL is not set
103# CONFIG_SIBYTE_PTSWARM is not set
104# CONFIG_SIBYTE_LITTLESUR is not set
105# CONFIG_SIBYTE_CRHINE is not set
106# CONFIG_SIBYTE_CRHONE is not set
79# CONFIG_SNI_RM200_PCI is not set 107# CONFIG_SNI_RM200_PCI is not set
108# CONFIG_TOSHIBA_JMR3927 is not set
80# CONFIG_TOSHIBA_RBTX4927 is not set 109# CONFIG_TOSHIBA_RBTX4927 is not set
110# CONFIG_TOSHIBA_RBTX4938 is not set
81CONFIG_RWSEM_GENERIC_SPINLOCK=y 111CONFIG_RWSEM_GENERIC_SPINLOCK=y
82CONFIG_GENERIC_CALIBRATE_DELAY=y 112CONFIG_GENERIC_CALIBRATE_DELAY=y
83CONFIG_HAVE_DEC_LOCK=y
84CONFIG_DMA_NONCOHERENT=y 113CONFIG_DMA_NONCOHERENT=y
85CONFIG_DMA_NEED_PCI_MAP_STATE=y 114CONFIG_DMA_NEED_PCI_MAP_STATE=y
115CONFIG_CPU_BIG_ENDIAN=y
86# CONFIG_CPU_LITTLE_ENDIAN is not set 116# CONFIG_CPU_LITTLE_ENDIAN is not set
117CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
87CONFIG_IRQ_CPU=y 118CONFIG_IRQ_CPU=y
88CONFIG_IRQ_CPU_RM7K=y 119CONFIG_IRQ_CPU_RM7K=y
89CONFIG_MIPS_GT64120=y 120CONFIG_MIPS_GT64120=y
@@ -96,8 +127,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
96# 127#
97# CPU selection 128# CPU selection
98# 129#
99# CONFIG_CPU_MIPS32 is not set 130# CONFIG_CPU_MIPS32_R1 is not set
100# CONFIG_CPU_MIPS64 is not set 131# CONFIG_CPU_MIPS32_R2 is not set
132# CONFIG_CPU_MIPS64_R1 is not set
133# CONFIG_CPU_MIPS64_R2 is not set
101# CONFIG_CPU_R3000 is not set 134# CONFIG_CPU_R3000 is not set
102# CONFIG_CPU_TX39XX is not set 135# CONFIG_CPU_TX39XX is not set
103# CONFIG_CPU_VR41XX is not set 136# CONFIG_CPU_VR41XX is not set
@@ -113,6 +146,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
113CONFIG_CPU_RM7000=y 146CONFIG_CPU_RM7000=y
114# CONFIG_CPU_RM9000 is not set 147# CONFIG_CPU_RM9000 is not set
115# CONFIG_CPU_SB1 is not set 148# CONFIG_CPU_SB1 is not set
149CONFIG_SYS_HAS_CPU_RM7000=y
150CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
151CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
152CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
153CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
154
155#
156# Kernel type
157#
158CONFIG_32BIT=y
159# CONFIG_64BIT is not set
116CONFIG_PAGE_SIZE_4KB=y 160CONFIG_PAGE_SIZE_4KB=y
117# CONFIG_PAGE_SIZE_8KB is not set 161# CONFIG_PAGE_SIZE_8KB is not set
118# CONFIG_PAGE_SIZE_16KB is not set 162# CONFIG_PAGE_SIZE_16KB is not set
@@ -120,11 +164,25 @@ CONFIG_PAGE_SIZE_4KB=y
120CONFIG_BOARD_SCACHE=y 164CONFIG_BOARD_SCACHE=y
121CONFIG_RM7000_CPU_SCACHE=y 165CONFIG_RM7000_CPU_SCACHE=y
122CONFIG_CPU_HAS_PREFETCH=y 166CONFIG_CPU_HAS_PREFETCH=y
167# CONFIG_MIPS_MT is not set
123# CONFIG_64BIT_PHYS_ADDR is not set 168# CONFIG_64BIT_PHYS_ADDR is not set
124# CONFIG_CPU_ADVANCED is not set 169# CONFIG_CPU_ADVANCED is not set
125CONFIG_CPU_HAS_LLSC=y 170CONFIG_CPU_HAS_LLSC=y
126CONFIG_CPU_HAS_LLDSCD=y 171CONFIG_CPU_HAS_LLDSCD=y
127CONFIG_CPU_HAS_SYNC=y 172CONFIG_CPU_HAS_SYNC=y
173CONFIG_GENERIC_HARDIRQS=y
174CONFIG_GENERIC_IRQ_PROBE=y
175CONFIG_CPU_SUPPORTS_HIGHMEM=y
176CONFIG_ARCH_FLATMEM_ENABLE=y
177CONFIG_SELECT_MEMORY_MODEL=y
178CONFIG_FLATMEM_MANUAL=y
179# CONFIG_DISCONTIGMEM_MANUAL is not set
180# CONFIG_SPARSEMEM_MANUAL is not set
181CONFIG_FLATMEM=y
182CONFIG_FLAT_NODE_MEM_MAP=y
183# CONFIG_SPARSEMEM_STATIC is not set
184CONFIG_PREEMPT_NONE=y
185# CONFIG_PREEMPT_VOLUNTARY is not set
128# CONFIG_PREEMPT is not set 186# CONFIG_PREEMPT is not set
129 187
130# 188#
@@ -140,10 +198,6 @@ CONFIG_MMU=y
140# CONFIG_PCCARD is not set 198# CONFIG_PCCARD is not set
141 199
142# 200#
143# PC-card bridges
144#
145
146#
147# PCI Hotplug Support 201# PCI Hotplug Support
148# 202#
149 203
@@ -155,6 +209,79 @@ CONFIG_BINFMT_ELF=y
155CONFIG_TRAD_SIGNALS=y 209CONFIG_TRAD_SIGNALS=y
156 210
157# 211#
212# Networking
213#
214CONFIG_NET=y
215
216#
217# Networking options
218#
219# CONFIG_PACKET is not set
220CONFIG_UNIX=y
221CONFIG_XFRM=y
222CONFIG_XFRM_USER=y
223CONFIG_NET_KEY=y
224CONFIG_INET=y
225# CONFIG_IP_MULTICAST is not set
226# CONFIG_IP_ADVANCED_ROUTER is not set
227CONFIG_IP_FIB_HASH=y
228CONFIG_IP_PNP=y
229# CONFIG_IP_PNP_DHCP is not set
230CONFIG_IP_PNP_BOOTP=y
231# CONFIG_IP_PNP_RARP is not set
232# CONFIG_NET_IPIP is not set
233# CONFIG_NET_IPGRE is not set
234# CONFIG_ARPD is not set
235# CONFIG_SYN_COOKIES is not set
236# CONFIG_INET_AH is not set
237# CONFIG_INET_ESP is not set
238# CONFIG_INET_IPCOMP is not set
239CONFIG_INET_TUNNEL=y
240CONFIG_INET_DIAG=y
241CONFIG_INET_TCP_DIAG=y
242# CONFIG_TCP_CONG_ADVANCED is not set
243CONFIG_TCP_CONG_BIC=y
244# CONFIG_IPV6 is not set
245# CONFIG_NETFILTER is not set
246
247#
248# DCCP Configuration (EXPERIMENTAL)
249#
250# CONFIG_IP_DCCP is not set
251
252#
253# SCTP Configuration (EXPERIMENTAL)
254#
255# CONFIG_IP_SCTP is not set
256# CONFIG_ATM is not set
257# CONFIG_BRIDGE is not set
258# CONFIG_VLAN_8021Q is not set
259# CONFIG_DECNET is not set
260# CONFIG_LLC2 is not set
261# CONFIG_IPX is not set
262# CONFIG_ATALK is not set
263# CONFIG_X25 is not set
264# CONFIG_LAPB is not set
265# CONFIG_NET_DIVERT is not set
266# CONFIG_ECONET is not set
267# CONFIG_WAN_ROUTER is not set
268# CONFIG_NET_SCHED is not set
269# CONFIG_NET_CLS_ROUTE is not set
270
271#
272# Network testing
273#
274# CONFIG_NET_PKTGEN is not set
275# CONFIG_HAMRADIO is not set
276# CONFIG_IRDA is not set
277# CONFIG_BT is not set
278CONFIG_IEEE80211=y
279# CONFIG_IEEE80211_DEBUG is not set
280CONFIG_IEEE80211_CRYPT_WEP=y
281CONFIG_IEEE80211_CRYPT_CCMP=y
282CONFIG_IEEE80211_CRYPT_TKIP=y
283
284#
158# Device Drivers 285# Device Drivers
159# 286#
160 287
@@ -166,6 +293,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
166# CONFIG_FW_LOADER is not set 293# CONFIG_FW_LOADER is not set
167 294
168# 295#
296# Connector - unified userspace <-> kernelspace linker
297#
298CONFIG_CONNECTOR=y
299
300#
169# Memory Technology Devices (MTD) 301# Memory Technology Devices (MTD)
170# 302#
171# CONFIG_MTD is not set 303# CONFIG_MTD is not set
@@ -182,13 +314,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
182# 314#
183# Block devices 315# Block devices
184# 316#
185# CONFIG_BLK_DEV_FD is not set
186# CONFIG_BLK_DEV_COW_COMMON is not set 317# CONFIG_BLK_DEV_COW_COMMON is not set
187# CONFIG_BLK_DEV_LOOP is not set 318# CONFIG_BLK_DEV_LOOP is not set
188# CONFIG_BLK_DEV_NBD is not set 319# CONFIG_BLK_DEV_NBD is not set
189# CONFIG_BLK_DEV_RAM is not set 320# CONFIG_BLK_DEV_RAM is not set
190CONFIG_BLK_DEV_RAM_COUNT=16 321CONFIG_BLK_DEV_RAM_COUNT=16
191CONFIG_INITRAMFS_SOURCE=""
192# CONFIG_LBD is not set 322# CONFIG_LBD is not set
193CONFIG_CDROM_PKTCDVD=y 323CONFIG_CDROM_PKTCDVD=y
194CONFIG_CDROM_PKTCDVD_BUFFERS=8 324CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -211,6 +341,7 @@ CONFIG_ATA_OVER_ETH=y
211# 341#
212# SCSI device support 342# SCSI device support
213# 343#
344CONFIG_RAID_ATTRS=y
214# CONFIG_SCSI is not set 345# CONFIG_SCSI is not set
215 346
216# 347#
@@ -221,6 +352,7 @@ CONFIG_ATA_OVER_ETH=y
221# 352#
222# Fusion MPT device support 353# Fusion MPT device support
223# 354#
355# CONFIG_FUSION is not set
224 356
225# 357#
226# IEEE 1394 (FireWire) support 358# IEEE 1394 (FireWire) support
@@ -231,77 +363,28 @@ CONFIG_ATA_OVER_ETH=y
231# 363#
232 364
233# 365#
234# Networking support 366# Network device support
235#
236CONFIG_NET=y
237
238#
239# Networking options
240# 367#
241# CONFIG_PACKET is not set 368CONFIG_NETDEVICES=y
242CONFIG_NETLINK_DEV=y 369# CONFIG_DUMMY is not set
243CONFIG_UNIX=y 370# CONFIG_BONDING is not set
244CONFIG_NET_KEY=y 371# CONFIG_EQUALIZER is not set
245CONFIG_INET=y 372# CONFIG_TUN is not set
246# CONFIG_IP_MULTICAST is not set
247# CONFIG_IP_ADVANCED_ROUTER is not set
248CONFIG_IP_PNP=y
249# CONFIG_IP_PNP_DHCP is not set
250CONFIG_IP_PNP_BOOTP=y
251# CONFIG_IP_PNP_RARP is not set
252# CONFIG_NET_IPIP is not set
253# CONFIG_NET_IPGRE is not set
254# CONFIG_ARPD is not set
255# CONFIG_SYN_COOKIES is not set
256# CONFIG_INET_AH is not set
257# CONFIG_INET_ESP is not set
258# CONFIG_INET_IPCOMP is not set
259CONFIG_INET_TUNNEL=y
260CONFIG_IP_TCPDIAG=y
261# CONFIG_IP_TCPDIAG_IPV6 is not set
262# CONFIG_IPV6 is not set
263# CONFIG_NETFILTER is not set
264CONFIG_XFRM=y
265CONFIG_XFRM_USER=y
266
267#
268# SCTP Configuration (EXPERIMENTAL)
269#
270# CONFIG_IP_SCTP is not set
271# CONFIG_ATM is not set
272# CONFIG_BRIDGE is not set
273# CONFIG_VLAN_8021Q is not set
274# CONFIG_DECNET is not set
275# CONFIG_LLC2 is not set
276# CONFIG_IPX is not set
277# CONFIG_ATALK is not set
278# CONFIG_X25 is not set
279# CONFIG_LAPB is not set
280# CONFIG_NET_DIVERT is not set
281# CONFIG_ECONET is not set
282# CONFIG_WAN_ROUTER is not set
283 373
284# 374#
285# QoS and/or fair queueing 375# PHY device support
286# 376#
287# CONFIG_NET_SCHED is not set 377CONFIG_PHYLIB=y
288# CONFIG_NET_CLS_ROUTE is not set 378CONFIG_PHYCONTROL=y
289 379
290# 380#
291# Network testing 381# MII PHY device drivers
292# 382#
293# CONFIG_NET_PKTGEN is not set 383CONFIG_MARVELL_PHY=y
294# CONFIG_NETPOLL is not set 384CONFIG_DAVICOM_PHY=y
295# CONFIG_NET_POLL_CONTROLLER is not set 385CONFIG_QSEMI_PHY=y
296# CONFIG_HAMRADIO is not set 386CONFIG_LXT_PHY=y
297# CONFIG_IRDA is not set 387CONFIG_CICADA_PHY=y
298# CONFIG_BT is not set
299CONFIG_NETDEVICES=y
300# CONFIG_DUMMY is not set
301# CONFIG_BONDING is not set
302# CONFIG_EQUALIZER is not set
303# CONFIG_TUN is not set
304# CONFIG_ETHERTAP is not set
305 388
306# 389#
307# Ethernet (10 or 100Mbit) 390# Ethernet (10 or 100Mbit)
@@ -334,6 +417,8 @@ CONFIG_NET_ETHERNET=y
334# CONFIG_SLIP is not set 417# CONFIG_SLIP is not set
335# CONFIG_SHAPER is not set 418# CONFIG_SHAPER is not set
336# CONFIG_NETCONSOLE is not set 419# CONFIG_NETCONSOLE is not set
420# CONFIG_NETPOLL is not set
421# CONFIG_NET_POLL_CONTROLLER is not set
337 422
338# 423#
339# ISDN subsystem 424# ISDN subsystem
@@ -363,18 +448,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
363# CONFIG_INPUT_EVBUG is not set 448# CONFIG_INPUT_EVBUG is not set
364 449
365# 450#
366# Input I/O drivers
367#
368# CONFIG_GAMEPORT is not set
369CONFIG_SOUND_GAMEPORT=y
370CONFIG_SERIO=y
371# CONFIG_SERIO_I8042 is not set
372CONFIG_SERIO_SERPORT=y
373# CONFIG_SERIO_CT82C710 is not set
374# CONFIG_SERIO_LIBPS2 is not set
375CONFIG_SERIO_RAW=y
376
377#
378# Input Device Drivers 451# Input Device Drivers
379# 452#
380# CONFIG_INPUT_KEYBOARD is not set 453# CONFIG_INPUT_KEYBOARD is not set
@@ -384,6 +457,16 @@ CONFIG_SERIO_RAW=y
384# CONFIG_INPUT_MISC is not set 457# CONFIG_INPUT_MISC is not set
385 458
386# 459#
460# Hardware I/O ports
461#
462CONFIG_SERIO=y
463# CONFIG_SERIO_I8042 is not set
464CONFIG_SERIO_SERPORT=y
465# CONFIG_SERIO_LIBPS2 is not set
466CONFIG_SERIO_RAW=y
467# CONFIG_GAMEPORT is not set
468
469#
387# Character devices 470# Character devices
388# 471#
389CONFIG_VT=y 472CONFIG_VT=y
@@ -425,10 +508,13 @@ CONFIG_LEGACY_PTY_COUNT=256
425# 508#
426# Ftape, the floppy tape device driver 509# Ftape, the floppy tape device driver
427# 510#
428# CONFIG_DRM is not set
429# CONFIG_RAW_DRIVER is not set 511# CONFIG_RAW_DRIVER is not set
430 512
431# 513#
514# TPM devices
515#
516
517#
432# I2C support 518# I2C support
433# 519#
434# CONFIG_I2C is not set 520# CONFIG_I2C is not set
@@ -439,10 +525,20 @@ CONFIG_LEGACY_PTY_COUNT=256
439# CONFIG_W1 is not set 525# CONFIG_W1 is not set
440 526
441# 527#
528# Hardware Monitoring support
529#
530# CONFIG_HWMON is not set
531# CONFIG_HWMON_VID is not set
532
533#
442# Misc devices 534# Misc devices
443# 535#
444 536
445# 537#
538# Multimedia Capabilities Port drivers
539#
540
541#
446# Multimedia devices 542# Multimedia devices
447# 543#
448# CONFIG_VIDEO_DEV is not set 544# CONFIG_VIDEO_DEV is not set
@@ -462,7 +558,6 @@ CONFIG_LEGACY_PTY_COUNT=256
462# 558#
463# CONFIG_VGA_CONSOLE is not set 559# CONFIG_VGA_CONSOLE is not set
464CONFIG_DUMMY_CONSOLE=y 560CONFIG_DUMMY_CONSOLE=y
465# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
466 561
467# 562#
468# Sound 563# Sound
@@ -476,10 +571,6 @@ CONFIG_DUMMY_CONSOLE=y
476# CONFIG_USB_ARCH_HAS_OHCI is not set 571# CONFIG_USB_ARCH_HAS_OHCI is not set
477 572
478# 573#
479# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
480#
481
482#
483# USB Gadget Support 574# USB Gadget Support
484# 575#
485# CONFIG_USB_GADGET is not set 576# CONFIG_USB_GADGET is not set
@@ -492,24 +583,31 @@ CONFIG_DUMMY_CONSOLE=y
492# 583#
493# InfiniBand support 584# InfiniBand support
494# 585#
495# CONFIG_INFINIBAND is not set 586
587#
588# SN Devices
589#
496 590
497# 591#
498# File systems 592# File systems
499# 593#
500CONFIG_EXT2_FS=y 594CONFIG_EXT2_FS=y
501# CONFIG_EXT2_FS_XATTR is not set 595# CONFIG_EXT2_FS_XATTR is not set
596# CONFIG_EXT2_FS_XIP is not set
502# CONFIG_EXT3_FS is not set 597# CONFIG_EXT3_FS is not set
503# CONFIG_JBD is not set 598# CONFIG_JBD is not set
504# CONFIG_REISERFS_FS is not set 599# CONFIG_REISERFS_FS is not set
505# CONFIG_JFS_FS is not set 600# CONFIG_JFS_FS is not set
601# CONFIG_FS_POSIX_ACL is not set
506# CONFIG_XFS_FS is not set 602# CONFIG_XFS_FS is not set
507# CONFIG_MINIX_FS is not set 603# CONFIG_MINIX_FS is not set
508# CONFIG_ROMFS_FS is not set 604# CONFIG_ROMFS_FS is not set
605CONFIG_INOTIFY=y
509# CONFIG_QUOTA is not set 606# CONFIG_QUOTA is not set
510CONFIG_DNOTIFY=y 607CONFIG_DNOTIFY=y
511# CONFIG_AUTOFS_FS is not set 608# CONFIG_AUTOFS_FS is not set
512# CONFIG_AUTOFS4_FS is not set 609# CONFIG_AUTOFS4_FS is not set
610CONFIG_FUSE_FS=y
513 611
514# 612#
515# CD-ROM/DVD Filesystems 613# CD-ROM/DVD Filesystems
@@ -530,12 +628,10 @@ CONFIG_DNOTIFY=y
530CONFIG_PROC_FS=y 628CONFIG_PROC_FS=y
531CONFIG_PROC_KCORE=y 629CONFIG_PROC_KCORE=y
532CONFIG_SYSFS=y 630CONFIG_SYSFS=y
533# CONFIG_DEVFS_FS is not set
534CONFIG_DEVPTS_FS_XATTR=y
535CONFIG_DEVPTS_FS_SECURITY=y
536# CONFIG_TMPFS is not set 631# CONFIG_TMPFS is not set
537# CONFIG_HUGETLB_PAGE is not set 632# CONFIG_HUGETLB_PAGE is not set
538CONFIG_RAMFS=y 633CONFIG_RAMFS=y
634CONFIG_RELAYFS_FS=y
539 635
540# 636#
541# Miscellaneous filesystems 637# Miscellaneous filesystems
@@ -567,6 +663,7 @@ CONFIG_NFSD=y
567CONFIG_ROOT_NFS=y 663CONFIG_ROOT_NFS=y
568CONFIG_LOCKD=y 664CONFIG_LOCKD=y
569CONFIG_EXPORTFS=y 665CONFIG_EXPORTFS=y
666CONFIG_NFS_COMMON=y
570CONFIG_SUNRPC=y 667CONFIG_SUNRPC=y
571# CONFIG_RPCSEC_GSS_KRB5 is not set 668# CONFIG_RPCSEC_GSS_KRB5 is not set
572# CONFIG_RPCSEC_GSS_SPKM3 is not set 669# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -575,6 +672,7 @@ CONFIG_SUNRPC=y
575# CONFIG_NCP_FS is not set 672# CONFIG_NCP_FS is not set
576# CONFIG_CODA_FS is not set 673# CONFIG_CODA_FS is not set
577# CONFIG_AFS_FS is not set 674# CONFIG_AFS_FS is not set
675# CONFIG_9P_FS is not set
578 676
579# 677#
580# Partition Types 678# Partition Types
@@ -595,7 +693,9 @@ CONFIG_MSDOS_PARTITION=y
595# 693#
596# Kernel hacking 694# Kernel hacking
597# 695#
696# CONFIG_PRINTK_TIME is not set
598# CONFIG_DEBUG_KERNEL is not set 697# CONFIG_DEBUG_KERNEL is not set
698CONFIG_LOG_BUF_SHIFT=14
599CONFIG_CROSSCOMPILE=y 699CONFIG_CROSSCOMPILE=y
600CONFIG_CMDLINE="" 700CONFIG_CMDLINE=""
601 701
@@ -609,7 +709,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
609# 709#
610# Cryptographic options 710# Cryptographic options
611# 711#
612# CONFIG_CRYPTO is not set 712CONFIG_CRYPTO=y
713CONFIG_CRYPTO_HMAC=y
714CONFIG_CRYPTO_NULL=y
715CONFIG_CRYPTO_MD4=y
716CONFIG_CRYPTO_MD5=y
717CONFIG_CRYPTO_SHA1=y
718CONFIG_CRYPTO_SHA256=y
719CONFIG_CRYPTO_SHA512=y
720CONFIG_CRYPTO_WP512=y
721CONFIG_CRYPTO_TGR192=y
722CONFIG_CRYPTO_DES=y
723CONFIG_CRYPTO_BLOWFISH=y
724CONFIG_CRYPTO_TWOFISH=y
725CONFIG_CRYPTO_SERPENT=y
726CONFIG_CRYPTO_AES=y
727CONFIG_CRYPTO_CAST5=y
728CONFIG_CRYPTO_CAST6=y
729CONFIG_CRYPTO_TEA=y
730CONFIG_CRYPTO_ARC4=y
731CONFIG_CRYPTO_KHAZAD=y
732CONFIG_CRYPTO_ANUBIS=y
733CONFIG_CRYPTO_DEFLATE=y
734CONFIG_CRYPTO_MICHAEL_MIC=y
735CONFIG_CRYPTO_CRC32C=y
736# CONFIG_CRYPTO_TEST is not set
613 737
614# 738#
615# Hardware crypto devices 739# Hardware crypto devices
@@ -619,7 +743,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
619# Library routines 743# Library routines
620# 744#
621# CONFIG_CRC_CCITT is not set 745# CONFIG_CRC_CCITT is not set
622# CONFIG_CRC32 is not set 746CONFIG_CRC16=y
623# CONFIG_LIBCRC32C is not set 747CONFIG_CRC32=y
624CONFIG_GENERIC_HARDIRQS=y 748CONFIG_LIBCRC32C=y
625CONFIG_GENERIC_IRQ_PROBE=y 749CONFIG_ZLIB_INFLATE=y
750CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig
index ef5ea50893d1..e2d5188cdc15 100644
--- a/arch/mips/configs/ocelot_g_defconfig
+++ b/arch/mips/configs/ocelot_g_defconfig
@@ -1,11 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:08 2005 4# Thu Oct 20 22:26:38 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7CONFIG_64BIT=y
8CONFIG_64BIT=y
9 7
10# 8#
11# Code maturity level options 9# Code maturity level options
@@ -13,24 +11,29 @@ CONFIG_64BIT=y
13CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
14CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
15CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
16 15
17# 16#
18# General setup 17# General setup
19# 18#
20CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
21CONFIG_SWAP=y 21CONFIG_SWAP=y
22CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
23# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
24# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
27CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
28# CONFIG_HOTPLUG is not set
29CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
30# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
31CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
32CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
33# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
34CONFIG_FUTEX=y 37CONFIG_FUTEX=y
35CONFIG_EPOLL=y 38CONFIG_EPOLL=y
36# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -40,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
40CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
41CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
42# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
43 47
44# 48#
45# Loadable module support 49# Loadable module support
@@ -49,39 +53,68 @@ CONFIG_CC_ALIGN_JUMPS=0
49# 53#
50# Machine selection 54# Machine selection
51# 55#
52# CONFIG_MACH_JAZZ is not set 56# CONFIG_MIPS_MTX1 is not set
53# CONFIG_MACH_VR41XX is not set 57# CONFIG_MIPS_BOSPORUS is not set
58# CONFIG_MIPS_PB1000 is not set
59# CONFIG_MIPS_PB1100 is not set
60# CONFIG_MIPS_PB1500 is not set
61# CONFIG_MIPS_PB1550 is not set
62# CONFIG_MIPS_PB1200 is not set
63# CONFIG_MIPS_DB1000 is not set
64# CONFIG_MIPS_DB1100 is not set
65# CONFIG_MIPS_DB1500 is not set
66# CONFIG_MIPS_DB1550 is not set
67# CONFIG_MIPS_DB1200 is not set
68# CONFIG_MIPS_MIRAGE is not set
54# CONFIG_MIPS_COBALT is not set 69# CONFIG_MIPS_COBALT is not set
55# CONFIG_MACH_DECSTATION is not set 70# CONFIG_MACH_DECSTATION is not set
56# CONFIG_MIPS_EV64120 is not set 71# CONFIG_MIPS_EV64120 is not set
57# CONFIG_MIPS_EV96100 is not set 72# CONFIG_MIPS_EV96100 is not set
58# CONFIG_MIPS_IVR is not set 73# CONFIG_MIPS_IVR is not set
59# CONFIG_LASAT is not set
60# CONFIG_MIPS_ITE8172 is not set 74# CONFIG_MIPS_ITE8172 is not set
75# CONFIG_MACH_JAZZ is not set
76# CONFIG_LASAT is not set
61# CONFIG_MIPS_ATLAS is not set 77# CONFIG_MIPS_ATLAS is not set
62# CONFIG_MIPS_MALTA is not set 78# CONFIG_MIPS_MALTA is not set
63# CONFIG_MIPS_SEAD is not set 79# CONFIG_MIPS_SEAD is not set
80# CONFIG_MIPS_SIM is not set
81# CONFIG_MOMENCO_JAGUAR_ATX is not set
64# CONFIG_MOMENCO_OCELOT is not set 82# CONFIG_MOMENCO_OCELOT is not set
65CONFIG_MOMENCO_OCELOT_G=y
66# CONFIG_MOMENCO_OCELOT_C is not set
67# CONFIG_MOMENCO_OCELOT_3 is not set 83# CONFIG_MOMENCO_OCELOT_3 is not set
68# CONFIG_MOMENCO_JAGUAR_ATX is not set 84# CONFIG_MOMENCO_OCELOT_C is not set
69# CONFIG_PMC_YOSEMITE is not set 85CONFIG_MOMENCO_OCELOT_G=y
86# CONFIG_MIPS_XXS1500 is not set
87# CONFIG_PNX8550_V2PCI is not set
88# CONFIG_PNX8550_JBS is not set
70# CONFIG_DDB5074 is not set 89# CONFIG_DDB5074 is not set
71# CONFIG_DDB5476 is not set 90# CONFIG_DDB5476 is not set
72# CONFIG_DDB5477 is not set 91# CONFIG_DDB5477 is not set
73# CONFIG_NEC_OSPREY is not set 92# CONFIG_MACH_VR41XX is not set
93# CONFIG_PMC_YOSEMITE is not set
94# CONFIG_QEMU is not set
74# CONFIG_SGI_IP22 is not set 95# CONFIG_SGI_IP22 is not set
75# CONFIG_SGI_IP27 is not set 96# CONFIG_SGI_IP27 is not set
76# CONFIG_SGI_IP32 is not set 97# CONFIG_SGI_IP32 is not set
77# CONFIG_SIBYTE_SB1xxx_SOC is not set 98# CONFIG_SIBYTE_BIGSUR is not set
99# CONFIG_SIBYTE_SWARM is not set
100# CONFIG_SIBYTE_SENTOSA is not set
101# CONFIG_SIBYTE_RHONE is not set
102# CONFIG_SIBYTE_CARMEL is not set
103# CONFIG_SIBYTE_PTSWARM is not set
104# CONFIG_SIBYTE_LITTLESUR is not set
105# CONFIG_SIBYTE_CRHINE is not set
106# CONFIG_SIBYTE_CRHONE is not set
78# CONFIG_SNI_RM200_PCI is not set 107# CONFIG_SNI_RM200_PCI is not set
108# CONFIG_TOSHIBA_JMR3927 is not set
109# CONFIG_TOSHIBA_RBTX4927 is not set
110# CONFIG_TOSHIBA_RBTX4938 is not set
79CONFIG_RWSEM_GENERIC_SPINLOCK=y 111CONFIG_RWSEM_GENERIC_SPINLOCK=y
80CONFIG_GENERIC_CALIBRATE_DELAY=y 112CONFIG_GENERIC_CALIBRATE_DELAY=y
81CONFIG_HAVE_DEC_LOCK=y
82CONFIG_DMA_NONCOHERENT=y 113CONFIG_DMA_NONCOHERENT=y
83CONFIG_DMA_NEED_PCI_MAP_STATE=y 114CONFIG_DMA_NEED_PCI_MAP_STATE=y
115CONFIG_CPU_BIG_ENDIAN=y
84# CONFIG_CPU_LITTLE_ENDIAN is not set 116# CONFIG_CPU_LITTLE_ENDIAN is not set
117CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
85CONFIG_IRQ_CPU=y 118CONFIG_IRQ_CPU=y
86CONFIG_IRQ_CPU_RM7K=y 119CONFIG_IRQ_CPU_RM7K=y
87CONFIG_PCI_MARVELL=y 120CONFIG_PCI_MARVELL=y
@@ -94,8 +127,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
94# 127#
95# CPU selection 128# CPU selection
96# 129#
97# CONFIG_CPU_MIPS32 is not set 130# CONFIG_CPU_MIPS32_R1 is not set
98# CONFIG_CPU_MIPS64 is not set 131# CONFIG_CPU_MIPS32_R2 is not set
132# CONFIG_CPU_MIPS64_R1 is not set
133# CONFIG_CPU_MIPS64_R2 is not set
99# CONFIG_CPU_R3000 is not set 134# CONFIG_CPU_R3000 is not set
100# CONFIG_CPU_TX39XX is not set 135# CONFIG_CPU_TX39XX is not set
101# CONFIG_CPU_VR41XX is not set 136# CONFIG_CPU_VR41XX is not set
@@ -111,6 +146,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
111CONFIG_CPU_RM7000=y 146CONFIG_CPU_RM7000=y
112# CONFIG_CPU_RM9000 is not set 147# CONFIG_CPU_RM9000 is not set
113# CONFIG_CPU_SB1 is not set 148# CONFIG_CPU_SB1 is not set
149CONFIG_SYS_HAS_CPU_RM7000=y
150CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
151CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
152CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
153CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
154
155#
156# Kernel type
157#
158# CONFIG_32BIT is not set
159CONFIG_64BIT=y
114CONFIG_PAGE_SIZE_4KB=y 160CONFIG_PAGE_SIZE_4KB=y
115# CONFIG_PAGE_SIZE_8KB is not set 161# CONFIG_PAGE_SIZE_8KB is not set
116# CONFIG_PAGE_SIZE_16KB is not set 162# CONFIG_PAGE_SIZE_16KB is not set
@@ -118,9 +164,23 @@ CONFIG_PAGE_SIZE_4KB=y
118CONFIG_BOARD_SCACHE=y 164CONFIG_BOARD_SCACHE=y
119CONFIG_RM7000_CPU_SCACHE=y 165CONFIG_RM7000_CPU_SCACHE=y
120CONFIG_CPU_HAS_PREFETCH=y 166CONFIG_CPU_HAS_PREFETCH=y
167# CONFIG_MIPS_MT is not set
121CONFIG_CPU_HAS_LLSC=y 168CONFIG_CPU_HAS_LLSC=y
122CONFIG_CPU_HAS_LLDSCD=y 169CONFIG_CPU_HAS_LLDSCD=y
123CONFIG_CPU_HAS_SYNC=y 170CONFIG_CPU_HAS_SYNC=y
171CONFIG_GENERIC_HARDIRQS=y
172CONFIG_GENERIC_IRQ_PROBE=y
173CONFIG_CPU_SUPPORTS_HIGHMEM=y
174CONFIG_ARCH_FLATMEM_ENABLE=y
175CONFIG_SELECT_MEMORY_MODEL=y
176CONFIG_FLATMEM_MANUAL=y
177# CONFIG_DISCONTIGMEM_MANUAL is not set
178# CONFIG_SPARSEMEM_MANUAL is not set
179CONFIG_FLATMEM=y
180CONFIG_FLAT_NODE_MEM_MAP=y
181# CONFIG_SPARSEMEM_STATIC is not set
182CONFIG_PREEMPT_NONE=y
183# CONFIG_PREEMPT_VOLUNTARY is not set
124# CONFIG_PREEMPT is not set 184# CONFIG_PREEMPT is not set
125 185
126# 186#
@@ -129,7 +189,6 @@ CONFIG_CPU_HAS_SYNC=y
129CONFIG_HW_HAS_PCI=y 189CONFIG_HW_HAS_PCI=y
130CONFIG_PCI=y 190CONFIG_PCI=y
131CONFIG_PCI_LEGACY_PROC=y 191CONFIG_PCI_LEGACY_PROC=y
132CONFIG_PCI_NAMES=y
133CONFIG_MMU=y 192CONFIG_MMU=y
134 193
135# 194#
@@ -138,10 +197,6 @@ CONFIG_MMU=y
138# CONFIG_PCCARD is not set 197# CONFIG_PCCARD is not set
139 198
140# 199#
141# PC-card bridges
142#
143
144#
145# PCI Hotplug Support 200# PCI Hotplug Support
146# 201#
147# CONFIG_HOTPLUG_PCI is not set 202# CONFIG_HOTPLUG_PCI is not set
@@ -159,6 +214,79 @@ CONFIG_MIPS32_N32=y
159CONFIG_BINFMT_ELF32=y 214CONFIG_BINFMT_ELF32=y
160 215
161# 216#
217# Networking
218#
219CONFIG_NET=y
220
221#
222# Networking options
223#
224# CONFIG_PACKET is not set
225CONFIG_UNIX=y
226CONFIG_XFRM=y
227CONFIG_XFRM_USER=y
228CONFIG_NET_KEY=y
229CONFIG_INET=y
230# CONFIG_IP_MULTICAST is not set
231# CONFIG_IP_ADVANCED_ROUTER is not set
232CONFIG_IP_FIB_HASH=y
233CONFIG_IP_PNP=y
234CONFIG_IP_PNP_DHCP=y
235# CONFIG_IP_PNP_BOOTP is not set
236# CONFIG_IP_PNP_RARP is not set
237# CONFIG_NET_IPIP is not set
238# CONFIG_NET_IPGRE is not set
239# CONFIG_ARPD is not set
240# CONFIG_SYN_COOKIES is not set
241# CONFIG_INET_AH is not set
242# CONFIG_INET_ESP is not set
243# CONFIG_INET_IPCOMP is not set
244CONFIG_INET_TUNNEL=y
245CONFIG_INET_DIAG=y
246CONFIG_INET_TCP_DIAG=y
247# CONFIG_TCP_CONG_ADVANCED is not set
248CONFIG_TCP_CONG_BIC=y
249# CONFIG_IPV6 is not set
250# CONFIG_NETFILTER is not set
251
252#
253# DCCP Configuration (EXPERIMENTAL)
254#
255# CONFIG_IP_DCCP is not set
256
257#
258# SCTP Configuration (EXPERIMENTAL)
259#
260# CONFIG_IP_SCTP is not set
261# CONFIG_ATM is not set
262# CONFIG_BRIDGE is not set
263# CONFIG_VLAN_8021Q is not set
264# CONFIG_DECNET is not set
265# CONFIG_LLC2 is not set
266# CONFIG_IPX is not set
267# CONFIG_ATALK is not set
268# CONFIG_X25 is not set
269# CONFIG_LAPB is not set
270# CONFIG_NET_DIVERT is not set
271# CONFIG_ECONET is not set
272# CONFIG_WAN_ROUTER is not set
273# CONFIG_NET_SCHED is not set
274# CONFIG_NET_CLS_ROUTE is not set
275
276#
277# Network testing
278#
279# CONFIG_NET_PKTGEN is not set
280# CONFIG_HAMRADIO is not set
281# CONFIG_IRDA is not set
282# CONFIG_BT is not set
283CONFIG_IEEE80211=y
284# CONFIG_IEEE80211_DEBUG is not set
285CONFIG_IEEE80211_CRYPT_WEP=y
286CONFIG_IEEE80211_CRYPT_CCMP=y
287CONFIG_IEEE80211_CRYPT_TKIP=y
288
289#
162# Device Drivers 290# Device Drivers
163# 291#
164 292
@@ -167,7 +295,12 @@ CONFIG_BINFMT_ELF32=y
167# 295#
168CONFIG_STANDALONE=y 296CONFIG_STANDALONE=y
169CONFIG_PREVENT_FIRMWARE_BUILD=y 297CONFIG_PREVENT_FIRMWARE_BUILD=y
170# CONFIG_FW_LOADER is not set 298CONFIG_FW_LOADER=y
299
300#
301# Connector - unified userspace <-> kernelspace linker
302#
303CONFIG_CONNECTOR=y
171 304
172# 305#
173# Memory Technology Devices (MTD) 306# Memory Technology Devices (MTD)
@@ -186,7 +319,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
186# 319#
187# Block devices 320# Block devices
188# 321#
189# CONFIG_BLK_DEV_FD is not set
190# CONFIG_BLK_CPQ_DA is not set 322# CONFIG_BLK_CPQ_DA is not set
191# CONFIG_BLK_CPQ_CISS_DA is not set 323# CONFIG_BLK_CPQ_CISS_DA is not set
192# CONFIG_BLK_DEV_DAC960 is not set 324# CONFIG_BLK_DEV_DAC960 is not set
@@ -197,7 +329,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
197# CONFIG_BLK_DEV_SX8 is not set 329# CONFIG_BLK_DEV_SX8 is not set
198# CONFIG_BLK_DEV_RAM is not set 330# CONFIG_BLK_DEV_RAM is not set
199CONFIG_BLK_DEV_RAM_COUNT=16 331CONFIG_BLK_DEV_RAM_COUNT=16
200CONFIG_INITRAMFS_SOURCE=""
201CONFIG_CDROM_PKTCDVD=y 332CONFIG_CDROM_PKTCDVD=y
202CONFIG_CDROM_PKTCDVD_BUFFERS=8 333CONFIG_CDROM_PKTCDVD_BUFFERS=8
203# CONFIG_CDROM_PKTCDVD_WCACHE is not set 334# CONFIG_CDROM_PKTCDVD_WCACHE is not set
@@ -219,6 +350,7 @@ CONFIG_ATA_OVER_ETH=y
219# 350#
220# SCSI device support 351# SCSI device support
221# 352#
353CONFIG_RAID_ATTRS=y
222# CONFIG_SCSI is not set 354# CONFIG_SCSI is not set
223 355
224# 356#
@@ -229,6 +361,7 @@ CONFIG_ATA_OVER_ETH=y
229# 361#
230# Fusion MPT device support 362# Fusion MPT device support
231# 363#
364# CONFIG_FUSION is not set
232 365
233# 366#
234# IEEE 1394 (FireWire) support 367# IEEE 1394 (FireWire) support
@@ -241,77 +374,13 @@ CONFIG_ATA_OVER_ETH=y
241# CONFIG_I2O is not set 374# CONFIG_I2O is not set
242 375
243# 376#
244# Networking support 377# Network device support
245#
246CONFIG_NET=y
247
248#
249# Networking options
250#
251# CONFIG_PACKET is not set
252CONFIG_NETLINK_DEV=y
253CONFIG_UNIX=y
254CONFIG_NET_KEY=y
255CONFIG_INET=y
256# CONFIG_IP_MULTICAST is not set
257# CONFIG_IP_ADVANCED_ROUTER is not set
258CONFIG_IP_PNP=y
259CONFIG_IP_PNP_DHCP=y
260# CONFIG_IP_PNP_BOOTP is not set
261# CONFIG_IP_PNP_RARP is not set
262# CONFIG_NET_IPIP is not set
263# CONFIG_NET_IPGRE is not set
264# CONFIG_ARPD is not set
265# CONFIG_SYN_COOKIES is not set
266# CONFIG_INET_AH is not set
267# CONFIG_INET_ESP is not set
268# CONFIG_INET_IPCOMP is not set
269CONFIG_INET_TUNNEL=y
270CONFIG_IP_TCPDIAG=y
271# CONFIG_IP_TCPDIAG_IPV6 is not set
272# CONFIG_IPV6 is not set
273# CONFIG_NETFILTER is not set
274CONFIG_XFRM=y
275CONFIG_XFRM_USER=y
276
277#
278# SCTP Configuration (EXPERIMENTAL)
279#
280# CONFIG_IP_SCTP is not set
281# CONFIG_ATM is not set
282# CONFIG_BRIDGE is not set
283# CONFIG_VLAN_8021Q is not set
284# CONFIG_DECNET is not set
285# CONFIG_LLC2 is not set
286# CONFIG_IPX is not set
287# CONFIG_ATALK is not set
288# CONFIG_X25 is not set
289# CONFIG_LAPB is not set
290# CONFIG_NET_DIVERT is not set
291# CONFIG_ECONET is not set
292# CONFIG_WAN_ROUTER is not set
293
294#
295# QoS and/or fair queueing
296#
297# CONFIG_NET_SCHED is not set
298# CONFIG_NET_CLS_ROUTE is not set
299
300#
301# Network testing
302# 378#
303# CONFIG_NET_PKTGEN is not set
304# CONFIG_NETPOLL is not set
305# CONFIG_NET_POLL_CONTROLLER is not set
306# CONFIG_HAMRADIO is not set
307# CONFIG_IRDA is not set
308# CONFIG_BT is not set
309CONFIG_NETDEVICES=y 379CONFIG_NETDEVICES=y
310# CONFIG_DUMMY is not set 380# CONFIG_DUMMY is not set
311# CONFIG_BONDING is not set 381# CONFIG_BONDING is not set
312# CONFIG_EQUALIZER is not set 382# CONFIG_EQUALIZER is not set
313# CONFIG_TUN is not set 383# CONFIG_TUN is not set
314# CONFIG_ETHERTAP is not set
315 384
316# 385#
317# ARCnet devices 386# ARCnet devices
@@ -319,6 +388,21 @@ CONFIG_NETDEVICES=y
319# CONFIG_ARCNET is not set 388# CONFIG_ARCNET is not set
320 389
321# 390#
391# PHY device support
392#
393CONFIG_PHYLIB=y
394CONFIG_PHYCONTROL=y
395
396#
397# MII PHY device drivers
398#
399CONFIG_MARVELL_PHY=y
400CONFIG_DAVICOM_PHY=y
401CONFIG_QSEMI_PHY=y
402CONFIG_LXT_PHY=y
403CONFIG_CICADA_PHY=y
404
405#
322# Ethernet (10 or 100Mbit) 406# Ethernet (10 or 100Mbit)
323# 407#
324CONFIG_NET_ETHERNET=y 408CONFIG_NET_ETHERNET=y
@@ -345,12 +429,16 @@ CONFIG_GALILEO_64240_ETH=y
345# CONFIG_HAMACHI is not set 429# CONFIG_HAMACHI is not set
346# CONFIG_YELLOWFIN is not set 430# CONFIG_YELLOWFIN is not set
347# CONFIG_R8169 is not set 431# CONFIG_R8169 is not set
432# CONFIG_SIS190 is not set
433# CONFIG_SKGE is not set
348# CONFIG_SK98LIN is not set 434# CONFIG_SK98LIN is not set
349# CONFIG_TIGON3 is not set 435# CONFIG_TIGON3 is not set
436# CONFIG_BNX2 is not set
350 437
351# 438#
352# Ethernet (10000 Mbit) 439# Ethernet (10000 Mbit)
353# 440#
441# CONFIG_CHELSIO_T1 is not set
354# CONFIG_IXGB is not set 442# CONFIG_IXGB is not set
355# CONFIG_S2IO is not set 443# CONFIG_S2IO is not set
356 444
@@ -363,6 +451,8 @@ CONFIG_GALILEO_64240_ETH=y
363# Wireless LAN (non-hamradio) 451# Wireless LAN (non-hamradio)
364# 452#
365# CONFIG_NET_RADIO is not set 453# CONFIG_NET_RADIO is not set
454# CONFIG_IPW_DEBUG is not set
455CONFIG_IPW2200=y
366 456
367# 457#
368# Wan interfaces 458# Wan interfaces
@@ -374,6 +464,8 @@ CONFIG_GALILEO_64240_ETH=y
374# CONFIG_SLIP is not set 464# CONFIG_SLIP is not set
375# CONFIG_SHAPER is not set 465# CONFIG_SHAPER is not set
376# CONFIG_NETCONSOLE is not set 466# CONFIG_NETCONSOLE is not set
467# CONFIG_NETPOLL is not set
468# CONFIG_NET_POLL_CONTROLLER is not set
377 469
378# 470#
379# ISDN subsystem 471# ISDN subsystem
@@ -403,19 +495,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
403# CONFIG_INPUT_EVBUG is not set 495# CONFIG_INPUT_EVBUG is not set
404 496
405# 497#
406# Input I/O drivers
407#
408# CONFIG_GAMEPORT is not set
409CONFIG_SOUND_GAMEPORT=y
410CONFIG_SERIO=y
411# CONFIG_SERIO_I8042 is not set
412CONFIG_SERIO_SERPORT=y
413# CONFIG_SERIO_CT82C710 is not set
414# CONFIG_SERIO_PCIPS2 is not set
415# CONFIG_SERIO_LIBPS2 is not set
416CONFIG_SERIO_RAW=y
417
418#
419# Input Device Drivers 498# Input Device Drivers
420# 499#
421# CONFIG_INPUT_KEYBOARD is not set 500# CONFIG_INPUT_KEYBOARD is not set
@@ -425,6 +504,17 @@ CONFIG_SERIO_RAW=y
425# CONFIG_INPUT_MISC is not set 504# CONFIG_INPUT_MISC is not set
426 505
427# 506#
507# Hardware I/O ports
508#
509CONFIG_SERIO=y
510# CONFIG_SERIO_I8042 is not set
511CONFIG_SERIO_SERPORT=y
512# CONFIG_SERIO_PCIPS2 is not set
513# CONFIG_SERIO_LIBPS2 is not set
514CONFIG_SERIO_RAW=y
515# CONFIG_GAMEPORT is not set
516
517#
428# Character devices 518# Character devices
429# 519#
430CONFIG_VT=y 520CONFIG_VT=y
@@ -445,6 +535,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
445# 535#
446CONFIG_SERIAL_CORE=y 536CONFIG_SERIAL_CORE=y
447CONFIG_SERIAL_CORE_CONSOLE=y 537CONFIG_SERIAL_CORE_CONSOLE=y
538# CONFIG_SERIAL_JSM is not set
448CONFIG_UNIX98_PTYS=y 539CONFIG_UNIX98_PTYS=y
449CONFIG_LEGACY_PTYS=y 540CONFIG_LEGACY_PTYS=y
450CONFIG_LEGACY_PTY_COUNT=256 541CONFIG_LEGACY_PTY_COUNT=256
@@ -471,6 +562,11 @@ CONFIG_LEGACY_PTY_COUNT=256
471# CONFIG_RAW_DRIVER is not set 562# CONFIG_RAW_DRIVER is not set
472 563
473# 564#
565# TPM devices
566#
567# CONFIG_TCG_TPM is not set
568
569#
474# I2C support 570# I2C support
475# 571#
476# CONFIG_I2C is not set 572# CONFIG_I2C is not set
@@ -481,10 +577,20 @@ CONFIG_LEGACY_PTY_COUNT=256
481# CONFIG_W1 is not set 577# CONFIG_W1 is not set
482 578
483# 579#
580# Hardware Monitoring support
581#
582# CONFIG_HWMON is not set
583# CONFIG_HWMON_VID is not set
584
585#
484# Misc devices 586# Misc devices
485# 587#
486 588
487# 589#
590# Multimedia Capabilities Port drivers
591#
592
593#
488# Multimedia devices 594# Multimedia devices
489# 595#
490# CONFIG_VIDEO_DEV is not set 596# CONFIG_VIDEO_DEV is not set
@@ -504,7 +610,6 @@ CONFIG_LEGACY_PTY_COUNT=256
504# 610#
505# CONFIG_VGA_CONSOLE is not set 611# CONFIG_VGA_CONSOLE is not set
506CONFIG_DUMMY_CONSOLE=y 612CONFIG_DUMMY_CONSOLE=y
507# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
508 613
509# 614#
510# Sound 615# Sound
@@ -514,13 +619,9 @@ CONFIG_DUMMY_CONSOLE=y
514# 619#
515# USB support 620# USB support
516# 621#
517# CONFIG_USB is not set
518CONFIG_USB_ARCH_HAS_HCD=y 622CONFIG_USB_ARCH_HAS_HCD=y
519CONFIG_USB_ARCH_HAS_OHCI=y 623CONFIG_USB_ARCH_HAS_OHCI=y
520 624# CONFIG_USB is not set
521#
522# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
523#
524 625
525# 626#
526# USB Gadget Support 627# USB Gadget Support
@@ -538,21 +639,29 @@ CONFIG_USB_ARCH_HAS_OHCI=y
538# CONFIG_INFINIBAND is not set 639# CONFIG_INFINIBAND is not set
539 640
540# 641#
642# SN Devices
643#
644
645#
541# File systems 646# File systems
542# 647#
543CONFIG_EXT2_FS=y 648CONFIG_EXT2_FS=y
544# CONFIG_EXT2_FS_XATTR is not set 649# CONFIG_EXT2_FS_XATTR is not set
650# CONFIG_EXT2_FS_XIP is not set
545# CONFIG_EXT3_FS is not set 651# CONFIG_EXT3_FS is not set
546# CONFIG_JBD is not set 652# CONFIG_JBD is not set
547# CONFIG_REISERFS_FS is not set 653# CONFIG_REISERFS_FS is not set
548# CONFIG_JFS_FS is not set 654# CONFIG_JFS_FS is not set
655# CONFIG_FS_POSIX_ACL is not set
549# CONFIG_XFS_FS is not set 656# CONFIG_XFS_FS is not set
550# CONFIG_MINIX_FS is not set 657# CONFIG_MINIX_FS is not set
551# CONFIG_ROMFS_FS is not set 658# CONFIG_ROMFS_FS is not set
659CONFIG_INOTIFY=y
552# CONFIG_QUOTA is not set 660# CONFIG_QUOTA is not set
553CONFIG_DNOTIFY=y 661CONFIG_DNOTIFY=y
554# CONFIG_AUTOFS_FS is not set 662# CONFIG_AUTOFS_FS is not set
555# CONFIG_AUTOFS4_FS is not set 663# CONFIG_AUTOFS4_FS is not set
664CONFIG_FUSE_FS=y
556 665
557# 666#
558# CD-ROM/DVD Filesystems 667# CD-ROM/DVD Filesystems
@@ -573,12 +682,10 @@ CONFIG_DNOTIFY=y
573CONFIG_PROC_FS=y 682CONFIG_PROC_FS=y
574CONFIG_PROC_KCORE=y 683CONFIG_PROC_KCORE=y
575CONFIG_SYSFS=y 684CONFIG_SYSFS=y
576# CONFIG_DEVFS_FS is not set
577CONFIG_DEVPTS_FS_XATTR=y
578CONFIG_DEVPTS_FS_SECURITY=y
579# CONFIG_TMPFS is not set 685# CONFIG_TMPFS is not set
580# CONFIG_HUGETLB_PAGE is not set 686# CONFIG_HUGETLB_PAGE is not set
581CONFIG_RAMFS=y 687CONFIG_RAMFS=y
688CONFIG_RELAYFS_FS=y
582 689
583# 690#
584# Miscellaneous filesystems 691# Miscellaneous filesystems
@@ -610,6 +717,7 @@ CONFIG_NFSD=y
610CONFIG_ROOT_NFS=y 717CONFIG_ROOT_NFS=y
611CONFIG_LOCKD=y 718CONFIG_LOCKD=y
612CONFIG_EXPORTFS=y 719CONFIG_EXPORTFS=y
720CONFIG_NFS_COMMON=y
613CONFIG_SUNRPC=y 721CONFIG_SUNRPC=y
614# CONFIG_RPCSEC_GSS_KRB5 is not set 722# CONFIG_RPCSEC_GSS_KRB5 is not set
615# CONFIG_RPCSEC_GSS_SPKM3 is not set 723# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -618,6 +726,7 @@ CONFIG_SUNRPC=y
618# CONFIG_NCP_FS is not set 726# CONFIG_NCP_FS is not set
619# CONFIG_CODA_FS is not set 727# CONFIG_CODA_FS is not set
620# CONFIG_AFS_FS is not set 728# CONFIG_AFS_FS is not set
729# CONFIG_9P_FS is not set
621 730
622# 731#
623# Partition Types 732# Partition Types
@@ -638,7 +747,9 @@ CONFIG_MSDOS_PARTITION=y
638# 747#
639# Kernel hacking 748# Kernel hacking
640# 749#
750# CONFIG_PRINTK_TIME is not set
641# CONFIG_DEBUG_KERNEL is not set 751# CONFIG_DEBUG_KERNEL is not set
752CONFIG_LOG_BUF_SHIFT=14
642CONFIG_CROSSCOMPILE=y 753CONFIG_CROSSCOMPILE=y
643CONFIG_CMDLINE="" 754CONFIG_CMDLINE=""
644 755
@@ -652,7 +763,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
652# 763#
653# Cryptographic options 764# Cryptographic options
654# 765#
655# CONFIG_CRYPTO is not set 766CONFIG_CRYPTO=y
767CONFIG_CRYPTO_HMAC=y
768CONFIG_CRYPTO_NULL=y
769CONFIG_CRYPTO_MD4=y
770CONFIG_CRYPTO_MD5=y
771CONFIG_CRYPTO_SHA1=y
772CONFIG_CRYPTO_SHA256=y
773CONFIG_CRYPTO_SHA512=y
774CONFIG_CRYPTO_WP512=y
775CONFIG_CRYPTO_TGR192=y
776CONFIG_CRYPTO_DES=y
777CONFIG_CRYPTO_BLOWFISH=y
778CONFIG_CRYPTO_TWOFISH=y
779CONFIG_CRYPTO_SERPENT=y
780CONFIG_CRYPTO_AES=y
781CONFIG_CRYPTO_CAST5=y
782CONFIG_CRYPTO_CAST6=y
783CONFIG_CRYPTO_TEA=y
784CONFIG_CRYPTO_ARC4=y
785CONFIG_CRYPTO_KHAZAD=y
786CONFIG_CRYPTO_ANUBIS=y
787CONFIG_CRYPTO_DEFLATE=y
788CONFIG_CRYPTO_MICHAEL_MIC=y
789CONFIG_CRYPTO_CRC32C=y
790# CONFIG_CRYPTO_TEST is not set
656 791
657# 792#
658# Hardware crypto devices 793# Hardware crypto devices
@@ -662,7 +797,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
662# Library routines 797# Library routines
663# 798#
664# CONFIG_CRC_CCITT is not set 799# CONFIG_CRC_CCITT is not set
665# CONFIG_CRC32 is not set 800CONFIG_CRC16=y
666# CONFIG_LIBCRC32C is not set 801CONFIG_CRC32=y
667CONFIG_GENERIC_HARDIRQS=y 802CONFIG_LIBCRC32C=y
668CONFIG_GENERIC_IRQ_PROBE=y 803CONFIG_ZLIB_INFLATE=y
804CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 813e3a8b480b..47247addee1b 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:08 2005 4# Thu Oct 20 22:26:41 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29CONFIG_HOTPLUG=y 27CONFIG_HOTPLUG=y
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,56 +59,70 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65CONFIG_MIPS_PB1100=y
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
83CONFIG_SOC_AU1X00=y 102# CONFIG_SGI_IP27 is not set
84# CONFIG_SOC_AU1000 is not set 103# CONFIG_SGI_IP32 is not set
85CONFIG_SOC_AU1100=y 104# CONFIG_SIBYTE_BIGSUR is not set
86# CONFIG_SOC_AU1500 is not set 105# CONFIG_SIBYTE_SWARM is not set
87# CONFIG_SOC_AU1550 is not set 106# CONFIG_SIBYTE_SENTOSA is not set
88# CONFIG_MIPS_PB1000 is not set 107# CONFIG_SIBYTE_RHONE is not set
89CONFIG_MIPS_PB1100=y 108# CONFIG_SIBYTE_CARMEL is not set
90# CONFIG_MIPS_PB1500 is not set 109# CONFIG_SIBYTE_PTSWARM is not set
91# CONFIG_MIPS_PB1550 is not set 110# CONFIG_SIBYTE_LITTLESUR is not set
92# CONFIG_MIPS_DB1000 is not set 111# CONFIG_SIBYTE_CRHINE is not set
93# CONFIG_MIPS_DB1100 is not set 112# CONFIG_SIBYTE_CRHONE is not set
94# CONFIG_MIPS_DB1500 is not set
95# CONFIG_MIPS_DB1550 is not set
96# CONFIG_MIPS_BOSPORUS is not set
97# CONFIG_MIPS_MIRAGE is not set
98# CONFIG_MIPS_XXS1500 is not set
99# CONFIG_MIPS_MTX1 is not set
100# CONFIG_SIBYTE_SB1xxx_SOC is not set
101# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
102# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
103CONFIG_RWSEM_GENERIC_SPINLOCK=y 117CONFIG_RWSEM_GENERIC_SPINLOCK=y
104CONFIG_GENERIC_CALIBRATE_DELAY=y 118CONFIG_GENERIC_CALIBRATE_DELAY=y
105CONFIG_HAVE_DEC_LOCK=y
106CONFIG_DMA_NONCOHERENT=y 119CONFIG_DMA_NONCOHERENT=y
107CONFIG_DMA_NEED_PCI_MAP_STATE=y 120CONFIG_DMA_NEED_PCI_MAP_STATE=y
121# CONFIG_CPU_BIG_ENDIAN is not set
108CONFIG_CPU_LITTLE_ENDIAN=y 122CONFIG_CPU_LITTLE_ENDIAN=y
123CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
124CONFIG_SOC_AU1100=y
125CONFIG_SOC_AU1X00=y
109CONFIG_SWAP_IO_SPACE=y 126CONFIG_SWAP_IO_SPACE=y
110# CONFIG_AU1X00_USB_DEVICE is not set 127# CONFIG_AU1X00_USB_DEVICE is not set
111CONFIG_MIPS_L1_CACHE_SHIFT=5 128CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -113,8 +130,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
113# 130#
114# CPU selection 131# CPU selection
115# 132#
116CONFIG_CPU_MIPS32=y 133CONFIG_CPU_MIPS32_R1=y
117# CONFIG_CPU_MIPS64 is not set 134# CONFIG_CPU_MIPS32_R2 is not set
135# CONFIG_CPU_MIPS64_R1 is not set
136# CONFIG_CPU_MIPS64_R2 is not set
118# CONFIG_CPU_R3000 is not set 137# CONFIG_CPU_R3000 is not set
119# CONFIG_CPU_TX39XX is not set 138# CONFIG_CPU_TX39XX is not set
120# CONFIG_CPU_VR41XX is not set 139# CONFIG_CPU_VR41XX is not set
@@ -130,15 +149,39 @@ CONFIG_CPU_MIPS32=y
130# CONFIG_CPU_RM7000 is not set 149# CONFIG_CPU_RM7000 is not set
131# CONFIG_CPU_RM9000 is not set 150# CONFIG_CPU_RM9000 is not set
132# CONFIG_CPU_SB1 is not set 151# CONFIG_CPU_SB1 is not set
152CONFIG_SYS_HAS_CPU_MIPS32_R1=y
153CONFIG_CPU_MIPS32=y
154CONFIG_CPU_MIPSR1=y
155CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
156CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
157
158#
159# Kernel type
160#
161CONFIG_32BIT=y
162# CONFIG_64BIT is not set
133CONFIG_PAGE_SIZE_4KB=y 163CONFIG_PAGE_SIZE_4KB=y
134# CONFIG_PAGE_SIZE_8KB is not set 164# CONFIG_PAGE_SIZE_8KB is not set
135# CONFIG_PAGE_SIZE_16KB is not set 165# CONFIG_PAGE_SIZE_16KB is not set
136# CONFIG_PAGE_SIZE_64KB is not set 166# CONFIG_PAGE_SIZE_64KB is not set
137CONFIG_CPU_HAS_PREFETCH=y 167CONFIG_CPU_HAS_PREFETCH=y
138# CONFIG_64BIT_PHYS_ADDR is not set 168# CONFIG_MIPS_MT is not set
169CONFIG_64BIT_PHYS_ADDR=y
139# CONFIG_CPU_ADVANCED is not set 170# CONFIG_CPU_ADVANCED is not set
140CONFIG_CPU_HAS_LLSC=y 171CONFIG_CPU_HAS_LLSC=y
141CONFIG_CPU_HAS_SYNC=y 172CONFIG_CPU_HAS_SYNC=y
173CONFIG_GENERIC_HARDIRQS=y
174CONFIG_GENERIC_IRQ_PROBE=y
175CONFIG_ARCH_FLATMEM_ENABLE=y
176CONFIG_SELECT_MEMORY_MODEL=y
177CONFIG_FLATMEM_MANUAL=y
178# CONFIG_DISCONTIGMEM_MANUAL is not set
179# CONFIG_SPARSEMEM_MANUAL is not set
180CONFIG_FLATMEM=y
181CONFIG_FLAT_NODE_MEM_MAP=y
182# CONFIG_SPARSEMEM_STATIC is not set
183CONFIG_PREEMPT_NONE=y
184# CONFIG_PREEMPT_VOLUNTARY is not set
142# CONFIG_PREEMPT is not set 185# CONFIG_PREEMPT is not set
143 186
144# 187#
@@ -154,6 +197,8 @@ CONFIG_MMU=y
154CONFIG_PCCARD=m 197CONFIG_PCCARD=m
155# CONFIG_PCMCIA_DEBUG is not set 198# CONFIG_PCMCIA_DEBUG is not set
156CONFIG_PCMCIA=m 199CONFIG_PCMCIA=m
200CONFIG_PCMCIA_LOAD_CIS=y
201CONFIG_PCMCIA_IOCTL=y
157 202
158# 203#
159# PC-card bridges 204# PC-card bridges
@@ -171,6 +216,100 @@ CONFIG_PCMCIA=m
171CONFIG_BINFMT_ELF=y 216CONFIG_BINFMT_ELF=y
172# CONFIG_BINFMT_MISC is not set 217# CONFIG_BINFMT_MISC is not set
173CONFIG_TRAD_SIGNALS=y 218CONFIG_TRAD_SIGNALS=y
219# CONFIG_PM is not set
220
221#
222# Networking
223#
224CONFIG_NET=y
225
226#
227# Networking options
228#
229CONFIG_PACKET=y
230# CONFIG_PACKET_MMAP is not set
231CONFIG_UNIX=y
232CONFIG_XFRM=y
233CONFIG_XFRM_USER=m
234CONFIG_NET_KEY=y
235CONFIG_INET=y
236CONFIG_IP_MULTICAST=y
237# CONFIG_IP_ADVANCED_ROUTER is not set
238CONFIG_IP_FIB_HASH=y
239CONFIG_IP_PNP=y
240# CONFIG_IP_PNP_DHCP is not set
241CONFIG_IP_PNP_BOOTP=y
242# CONFIG_IP_PNP_RARP is not set
243# CONFIG_NET_IPIP is not set
244# CONFIG_NET_IPGRE is not set
245# CONFIG_IP_MROUTE is not set
246# CONFIG_ARPD is not set
247# CONFIG_SYN_COOKIES is not set
248# CONFIG_INET_AH is not set
249# CONFIG_INET_ESP is not set
250# CONFIG_INET_IPCOMP is not set
251CONFIG_INET_TUNNEL=m
252CONFIG_INET_DIAG=y
253CONFIG_INET_TCP_DIAG=y
254# CONFIG_TCP_CONG_ADVANCED is not set
255CONFIG_TCP_CONG_BIC=y
256
257#
258# IP: Virtual Server Configuration
259#
260# CONFIG_IP_VS is not set
261# CONFIG_IPV6 is not set
262CONFIG_NETFILTER=y
263# CONFIG_NETFILTER_DEBUG is not set
264CONFIG_NETFILTER_NETLINK=m
265CONFIG_NETFILTER_NETLINK_QUEUE=m
266CONFIG_NETFILTER_NETLINK_LOG=m
267
268#
269# IP: Netfilter Configuration
270#
271# CONFIG_IP_NF_CONNTRACK is not set
272CONFIG_IP_NF_PPTP=m
273# CONFIG_IP_NF_QUEUE is not set
274# CONFIG_IP_NF_IPTABLES is not set
275# CONFIG_IP_NF_ARPTABLES is not set
276
277#
278# DCCP Configuration (EXPERIMENTAL)
279#
280# CONFIG_IP_DCCP is not set
281
282#
283# SCTP Configuration (EXPERIMENTAL)
284#
285# CONFIG_IP_SCTP is not set
286# CONFIG_ATM is not set
287# CONFIG_BRIDGE is not set
288# CONFIG_VLAN_8021Q is not set
289# CONFIG_DECNET is not set
290# CONFIG_LLC2 is not set
291# CONFIG_IPX is not set
292# CONFIG_ATALK is not set
293# CONFIG_X25 is not set
294# CONFIG_LAPB is not set
295# CONFIG_NET_DIVERT is not set
296# CONFIG_ECONET is not set
297# CONFIG_WAN_ROUTER is not set
298# CONFIG_NET_SCHED is not set
299# CONFIG_NET_CLS_ROUTE is not set
300
301#
302# Network testing
303#
304# CONFIG_NET_PKTGEN is not set
305# CONFIG_HAMRADIO is not set
306# CONFIG_IRDA is not set
307# CONFIG_BT is not set
308CONFIG_IEEE80211=m
309# CONFIG_IEEE80211_DEBUG is not set
310CONFIG_IEEE80211_CRYPT_WEP=m
311CONFIG_IEEE80211_CRYPT_CCMP=m
312CONFIG_IEEE80211_CRYPT_TKIP=m
174 313
175# 314#
176# Device Drivers 315# Device Drivers
@@ -181,15 +320,20 @@ CONFIG_TRAD_SIGNALS=y
181# 320#
182CONFIG_STANDALONE=y 321CONFIG_STANDALONE=y
183CONFIG_PREVENT_FIRMWARE_BUILD=y 322CONFIG_PREVENT_FIRMWARE_BUILD=y
184# CONFIG_FW_LOADER is not set 323CONFIG_FW_LOADER=m
324
325#
326# Connector - unified userspace <-> kernelspace linker
327#
328CONFIG_CONNECTOR=m
185 329
186# 330#
187# Memory Technology Devices (MTD) 331# Memory Technology Devices (MTD)
188# 332#
189CONFIG_MTD=y 333CONFIG_MTD=y
190# CONFIG_MTD_DEBUG is not set 334# CONFIG_MTD_DEBUG is not set
191CONFIG_MTD_PARTITIONS=y
192# CONFIG_MTD_CONCAT is not set 335# CONFIG_MTD_CONCAT is not set
336CONFIG_MTD_PARTITIONS=y
193# CONFIG_MTD_REDBOOT_PARTS is not set 337# CONFIG_MTD_REDBOOT_PARTS is not set
194# CONFIG_MTD_CMDLINE_PARTS is not set 338# CONFIG_MTD_CMDLINE_PARTS is not set
195 339
@@ -233,9 +377,8 @@ CONFIG_MTD_CFI_UTIL=y
233# 377#
234# CONFIG_MTD_COMPLEX_MAPPINGS is not set 378# CONFIG_MTD_COMPLEX_MAPPINGS is not set
235# CONFIG_MTD_PHYSMAP is not set 379# CONFIG_MTD_PHYSMAP is not set
236CONFIG_MTD_PB1100=y 380CONFIG_MTD_ALCHEMY=y
237CONFIG_MTD_PB1500_BOOT=y 381# CONFIG_MTD_PLATRAM is not set
238CONFIG_MTD_PB1500_USER=y
239 382
240# 383#
241# Self-contained MTD device drivers 384# Self-contained MTD device drivers
@@ -270,14 +413,12 @@ CONFIG_MTD_PB1500_USER=y
270# 413#
271# Block devices 414# Block devices
272# 415#
273# CONFIG_BLK_DEV_FD is not set
274# CONFIG_BLK_DEV_COW_COMMON is not set 416# CONFIG_BLK_DEV_COW_COMMON is not set
275CONFIG_BLK_DEV_LOOP=y 417CONFIG_BLK_DEV_LOOP=y
276# CONFIG_BLK_DEV_CRYPTOLOOP is not set 418# CONFIG_BLK_DEV_CRYPTOLOOP is not set
277# CONFIG_BLK_DEV_NBD is not set 419# CONFIG_BLK_DEV_NBD is not set
278# CONFIG_BLK_DEV_RAM is not set 420# CONFIG_BLK_DEV_RAM is not set
279CONFIG_BLK_DEV_RAM_COUNT=16 421CONFIG_BLK_DEV_RAM_COUNT=16
280CONFIG_INITRAMFS_SOURCE=""
281# CONFIG_LBD is not set 422# CONFIG_LBD is not set
282CONFIG_CDROM_PKTCDVD=m 423CONFIG_CDROM_PKTCDVD=m
283CONFIG_CDROM_PKTCDVD_BUFFERS=8 424CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -300,6 +441,7 @@ CONFIG_ATA_OVER_ETH=m
300# 441#
301# SCSI device support 442# SCSI device support
302# 443#
444CONFIG_RAID_ATTRS=m
303# CONFIG_SCSI is not set 445# CONFIG_SCSI is not set
304 446
305# 447#
@@ -310,6 +452,7 @@ CONFIG_ATA_OVER_ETH=m
310# 452#
311# Fusion MPT device support 453# Fusion MPT device support
312# 454#
455# CONFIG_FUSION is not set
313 456
314# 457#
315# IEEE 1394 (FireWire) support 458# IEEE 1394 (FireWire) support
@@ -320,94 +463,28 @@ CONFIG_ATA_OVER_ETH=m
320# 463#
321 464
322# 465#
323# Networking support 466# Network device support
324#
325CONFIG_NET=y
326
327#
328# Networking options
329#
330CONFIG_PACKET=y
331# CONFIG_PACKET_MMAP is not set
332CONFIG_NETLINK_DEV=y
333CONFIG_UNIX=y
334CONFIG_NET_KEY=y
335CONFIG_INET=y
336CONFIG_IP_MULTICAST=y
337# CONFIG_IP_ADVANCED_ROUTER is not set
338CONFIG_IP_PNP=y
339# CONFIG_IP_PNP_DHCP is not set
340CONFIG_IP_PNP_BOOTP=y
341# CONFIG_IP_PNP_RARP is not set
342# CONFIG_NET_IPIP is not set
343# CONFIG_NET_IPGRE is not set
344# CONFIG_IP_MROUTE is not set
345# CONFIG_ARPD is not set
346# CONFIG_SYN_COOKIES is not set
347# CONFIG_INET_AH is not set
348# CONFIG_INET_ESP is not set
349# CONFIG_INET_IPCOMP is not set
350CONFIG_INET_TUNNEL=m
351CONFIG_IP_TCPDIAG=m
352# CONFIG_IP_TCPDIAG_IPV6 is not set
353
354#
355# IP: Virtual Server Configuration
356#
357# CONFIG_IP_VS is not set
358# CONFIG_IPV6 is not set
359CONFIG_NETFILTER=y
360# CONFIG_NETFILTER_DEBUG is not set
361
362#
363# IP: Netfilter Configuration
364#
365# CONFIG_IP_NF_CONNTRACK is not set
366CONFIG_IP_NF_CONNTRACK_MARK=y
367# CONFIG_IP_NF_QUEUE is not set
368# CONFIG_IP_NF_IPTABLES is not set
369# CONFIG_IP_NF_ARPTABLES is not set
370CONFIG_XFRM=y
371CONFIG_XFRM_USER=m
372
373#
374# SCTP Configuration (EXPERIMENTAL)
375# 467#
376# CONFIG_IP_SCTP is not set 468CONFIG_NETDEVICES=y
377# CONFIG_ATM is not set 469# CONFIG_DUMMY is not set
378# CONFIG_BRIDGE is not set 470# CONFIG_BONDING is not set
379# CONFIG_VLAN_8021Q is not set 471# CONFIG_EQUALIZER is not set
380# CONFIG_DECNET is not set 472# CONFIG_TUN is not set
381# CONFIG_LLC2 is not set
382# CONFIG_IPX is not set
383# CONFIG_ATALK is not set
384# CONFIG_X25 is not set
385# CONFIG_LAPB is not set
386# CONFIG_NET_DIVERT is not set
387# CONFIG_ECONET is not set
388# CONFIG_WAN_ROUTER is not set
389 473
390# 474#
391# QoS and/or fair queueing 475# PHY device support
392# 476#
393# CONFIG_NET_SCHED is not set 477CONFIG_PHYLIB=m
394# CONFIG_NET_CLS_ROUTE is not set 478CONFIG_PHYCONTROL=y
395 479
396# 480#
397# Network testing 481# MII PHY device drivers
398# 482#
399# CONFIG_NET_PKTGEN is not set 483CONFIG_MARVELL_PHY=m
400# CONFIG_NETPOLL is not set 484CONFIG_DAVICOM_PHY=m
401# CONFIG_NET_POLL_CONTROLLER is not set 485CONFIG_QSEMI_PHY=m
402# CONFIG_HAMRADIO is not set 486CONFIG_LXT_PHY=m
403# CONFIG_IRDA is not set 487CONFIG_CICADA_PHY=m
404# CONFIG_BT is not set
405CONFIG_NETDEVICES=y
406# CONFIG_DUMMY is not set
407# CONFIG_BONDING is not set
408# CONFIG_EQUALIZER is not set
409# CONFIG_TUN is not set
410# CONFIG_ETHERTAP is not set
411 488
412# 489#
413# Ethernet (10 or 100Mbit) 490# Ethernet (10 or 100Mbit)
@@ -453,6 +530,8 @@ CONFIG_PPPOE=m
453# CONFIG_SLIP is not set 530# CONFIG_SLIP is not set
454# CONFIG_SHAPER is not set 531# CONFIG_SHAPER is not set
455# CONFIG_NETCONSOLE is not set 532# CONFIG_NETCONSOLE is not set
533# CONFIG_NETPOLL is not set
534# CONFIG_NET_POLL_CONTROLLER is not set
456 535
457# 536#
458# ISDN subsystem 537# ISDN subsystem
@@ -482,18 +561,6 @@ CONFIG_INPUT_EVDEV=y
482# CONFIG_INPUT_EVBUG is not set 561# CONFIG_INPUT_EVBUG is not set
483 562
484# 563#
485# Input I/O drivers
486#
487# CONFIG_GAMEPORT is not set
488CONFIG_SOUND_GAMEPORT=y
489CONFIG_SERIO=y
490# CONFIG_SERIO_I8042 is not set
491CONFIG_SERIO_SERPORT=y
492# CONFIG_SERIO_CT82C710 is not set
493# CONFIG_SERIO_LIBPS2 is not set
494CONFIG_SERIO_RAW=m
495
496#
497# Input Device Drivers 564# Input Device Drivers
498# 565#
499# CONFIG_INPUT_KEYBOARD is not set 566# CONFIG_INPUT_KEYBOARD is not set
@@ -503,6 +570,16 @@ CONFIG_SERIO_RAW=m
503# CONFIG_INPUT_MISC is not set 570# CONFIG_INPUT_MISC is not set
504 571
505# 572#
573# Hardware I/O ports
574#
575CONFIG_SERIO=y
576# CONFIG_SERIO_I8042 is not set
577CONFIG_SERIO_SERPORT=y
578# CONFIG_SERIO_LIBPS2 is not set
579CONFIG_SERIO_RAW=m
580# CONFIG_GAMEPORT is not set
581
582#
506# Character devices 583# Character devices
507# 584#
508CONFIG_VT=y 585CONFIG_VT=y
@@ -534,14 +611,14 @@ CONFIG_LEGACY_PTY_COUNT=256
534# Watchdog Cards 611# Watchdog Cards
535# 612#
536# CONFIG_WATCHDOG is not set 613# CONFIG_WATCHDOG is not set
537CONFIG_RTC=y 614# CONFIG_RTC is not set
615# CONFIG_GEN_RTC is not set
538# CONFIG_DTLK is not set 616# CONFIG_DTLK is not set
539# CONFIG_R3964 is not set 617# CONFIG_R3964 is not set
540 618
541# 619#
542# Ftape, the floppy tape device driver 620# Ftape, the floppy tape device driver
543# 621#
544# CONFIG_DRM is not set
545 622
546# 623#
547# PCMCIA character devices 624# PCMCIA character devices
@@ -550,6 +627,10 @@ CONFIG_SYNCLINK_CS=m
550# CONFIG_RAW_DRIVER is not set 627# CONFIG_RAW_DRIVER is not set
551 628
552# 629#
630# TPM devices
631#
632
633#
553# I2C support 634# I2C support
554# 635#
555# CONFIG_I2C is not set 636# CONFIG_I2C is not set
@@ -560,10 +641,20 @@ CONFIG_SYNCLINK_CS=m
560# CONFIG_W1 is not set 641# CONFIG_W1 is not set
561 642
562# 643#
644# Hardware Monitoring support
645#
646# CONFIG_HWMON is not set
647# CONFIG_HWMON_VID is not set
648
649#
563# Misc devices 650# Misc devices
564# 651#
565 652
566# 653#
654# Multimedia Capabilities Port drivers
655#
656
657#
567# Multimedia devices 658# Multimedia devices
568# 659#
569# CONFIG_VIDEO_DEV is not set 660# CONFIG_VIDEO_DEV is not set
@@ -583,7 +674,6 @@ CONFIG_SYNCLINK_CS=m
583# 674#
584# CONFIG_VGA_CONSOLE is not set 675# CONFIG_VGA_CONSOLE is not set
585CONFIG_DUMMY_CONSOLE=y 676CONFIG_DUMMY_CONSOLE=y
586# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
587 677
588# 678#
589# Sound 679# Sound
@@ -593,12 +683,9 @@ CONFIG_DUMMY_CONSOLE=y
593# 683#
594# USB support 684# USB support
595# 685#
596# CONFIG_USB_ARCH_HAS_HCD is not set 686CONFIG_USB_ARCH_HAS_HCD=y
597# CONFIG_USB_ARCH_HAS_OHCI is not set 687CONFIG_USB_ARCH_HAS_OHCI=y
598 688# CONFIG_USB is not set
599#
600# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
601#
602 689
603# 690#
604# USB Gadget Support 691# USB Gadget Support
@@ -613,7 +700,10 @@ CONFIG_DUMMY_CONSOLE=y
613# 700#
614# InfiniBand support 701# InfiniBand support
615# 702#
616# CONFIG_INFINIBAND is not set 703
704#
705# SN Devices
706#
617 707
618# 708#
619# File systems 709# File systems
@@ -622,6 +712,7 @@ CONFIG_EXT2_FS=y
622CONFIG_EXT2_FS_XATTR=y 712CONFIG_EXT2_FS_XATTR=y
623CONFIG_EXT2_FS_POSIX_ACL=y 713CONFIG_EXT2_FS_POSIX_ACL=y
624# CONFIG_EXT2_FS_SECURITY is not set 714# CONFIG_EXT2_FS_SECURITY is not set
715# CONFIG_EXT2_FS_XIP is not set
625CONFIG_EXT3_FS=y 716CONFIG_EXT3_FS=y
626CONFIG_EXT3_FS_XATTR=y 717CONFIG_EXT3_FS_XATTR=y
627CONFIG_EXT3_FS_POSIX_ACL=y 718CONFIG_EXT3_FS_POSIX_ACL=y
@@ -640,10 +731,12 @@ CONFIG_FS_POSIX_ACL=y
640# CONFIG_XFS_FS is not set 731# CONFIG_XFS_FS is not set
641# CONFIG_MINIX_FS is not set 732# CONFIG_MINIX_FS is not set
642# CONFIG_ROMFS_FS is not set 733# CONFIG_ROMFS_FS is not set
734CONFIG_INOTIFY=y
643# CONFIG_QUOTA is not set 735# CONFIG_QUOTA is not set
644CONFIG_DNOTIFY=y 736CONFIG_DNOTIFY=y
645CONFIG_AUTOFS_FS=m 737CONFIG_AUTOFS_FS=m
646CONFIG_AUTOFS4_FS=m 738CONFIG_AUTOFS4_FS=m
739CONFIG_FUSE_FS=m
647 740
648# 741#
649# CD-ROM/DVD Filesystems 742# CD-ROM/DVD Filesystems
@@ -664,13 +757,10 @@ CONFIG_AUTOFS4_FS=m
664CONFIG_PROC_FS=y 757CONFIG_PROC_FS=y
665CONFIG_PROC_KCORE=y 758CONFIG_PROC_KCORE=y
666CONFIG_SYSFS=y 759CONFIG_SYSFS=y
667# CONFIG_DEVFS_FS is not set
668CONFIG_DEVPTS_FS_XATTR=y
669CONFIG_DEVPTS_FS_SECURITY=y
670CONFIG_TMPFS=y 760CONFIG_TMPFS=y
671# CONFIG_TMPFS_XATTR is not set
672# CONFIG_HUGETLB_PAGE is not set 761# CONFIG_HUGETLB_PAGE is not set
673CONFIG_RAMFS=y 762CONFIG_RAMFS=y
763CONFIG_RELAYFS_FS=m
674 764
675# 765#
676# Miscellaneous filesystems 766# Miscellaneous filesystems
@@ -704,6 +794,7 @@ CONFIG_NFSD=m
704CONFIG_ROOT_NFS=y 794CONFIG_ROOT_NFS=y
705CONFIG_LOCKD=y 795CONFIG_LOCKD=y
706CONFIG_EXPORTFS=m 796CONFIG_EXPORTFS=m
797CONFIG_NFS_COMMON=y
707CONFIG_SUNRPC=y 798CONFIG_SUNRPC=y
708# CONFIG_RPCSEC_GSS_KRB5 is not set 799# CONFIG_RPCSEC_GSS_KRB5 is not set
709# CONFIG_RPCSEC_GSS_SPKM3 is not set 800# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -713,6 +804,7 @@ CONFIG_SMB_FS=m
713# CONFIG_NCP_FS is not set 804# CONFIG_NCP_FS is not set
714# CONFIG_CODA_FS is not set 805# CONFIG_CODA_FS is not set
715# CONFIG_AFS_FS is not set 806# CONFIG_AFS_FS is not set
807# CONFIG_9P_FS is not set
716 808
717# 809#
718# Partition Types 810# Partition Types
@@ -772,7 +864,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
772# 864#
773# Kernel hacking 865# Kernel hacking
774# 866#
867# CONFIG_PRINTK_TIME is not set
775# CONFIG_DEBUG_KERNEL is not set 868# CONFIG_DEBUG_KERNEL is not set
869CONFIG_LOG_BUF_SHIFT=14
776CONFIG_CROSSCOMPILE=y 870CONFIG_CROSSCOMPILE=y
777CONFIG_CMDLINE="" 871CONFIG_CMDLINE=""
778 872
@@ -788,26 +882,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
788# 882#
789CONFIG_CRYPTO=y 883CONFIG_CRYPTO=y
790CONFIG_CRYPTO_HMAC=y 884CONFIG_CRYPTO_HMAC=y
791CONFIG_CRYPTO_NULL=y 885CONFIG_CRYPTO_NULL=m
792# CONFIG_CRYPTO_MD4 is not set 886CONFIG_CRYPTO_MD4=m
793# CONFIG_CRYPTO_MD5 is not set 887CONFIG_CRYPTO_MD5=m
794# CONFIG_CRYPTO_SHA1 is not set 888CONFIG_CRYPTO_SHA1=m
795# CONFIG_CRYPTO_SHA256 is not set 889CONFIG_CRYPTO_SHA256=m
796CONFIG_CRYPTO_SHA512=y 890CONFIG_CRYPTO_SHA512=m
797CONFIG_CRYPTO_WP512=m 891CONFIG_CRYPTO_WP512=m
798# CONFIG_CRYPTO_DES is not set 892CONFIG_CRYPTO_TGR192=m
799# CONFIG_CRYPTO_BLOWFISH is not set 893CONFIG_CRYPTO_DES=m
800CONFIG_CRYPTO_TWOFISH=y 894CONFIG_CRYPTO_BLOWFISH=m
801# CONFIG_CRYPTO_SERPENT is not set 895CONFIG_CRYPTO_TWOFISH=m
896CONFIG_CRYPTO_SERPENT=m
802CONFIG_CRYPTO_AES=m 897CONFIG_CRYPTO_AES=m
803# CONFIG_CRYPTO_CAST5 is not set 898CONFIG_CRYPTO_CAST5=m
804# CONFIG_CRYPTO_CAST6 is not set 899CONFIG_CRYPTO_CAST6=m
805CONFIG_CRYPTO_TEA=m 900CONFIG_CRYPTO_TEA=m
806# CONFIG_CRYPTO_ARC4 is not set 901CONFIG_CRYPTO_ARC4=m
807CONFIG_CRYPTO_KHAZAD=m 902CONFIG_CRYPTO_KHAZAD=m
808CONFIG_CRYPTO_ANUBIS=m 903CONFIG_CRYPTO_ANUBIS=m
809CONFIG_CRYPTO_DEFLATE=y 904CONFIG_CRYPTO_DEFLATE=m
810CONFIG_CRYPTO_MICHAEL_MIC=y 905CONFIG_CRYPTO_MICHAEL_MIC=m
811CONFIG_CRYPTO_CRC32C=m 906CONFIG_CRYPTO_CRC32C=m
812# CONFIG_CRYPTO_TEST is not set 907# CONFIG_CRYPTO_TEST is not set
813 908
@@ -819,9 +914,8 @@ CONFIG_CRYPTO_CRC32C=m
819# Library routines 914# Library routines
820# 915#
821CONFIG_CRC_CCITT=m 916CONFIG_CRC_CCITT=m
917CONFIG_CRC16=m
822CONFIG_CRC32=y 918CONFIG_CRC32=y
823CONFIG_LIBCRC32C=m 919CONFIG_LIBCRC32C=m
824CONFIG_ZLIB_INFLATE=y 920CONFIG_ZLIB_INFLATE=m
825CONFIG_ZLIB_DEFLATE=y 921CONFIG_ZLIB_DEFLATE=m
826CONFIG_GENERIC_HARDIRQS=y
827CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 49e528340a39..f91a4eaae51a 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:09 2005 4# Thu Oct 20 22:26:44 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29CONFIG_HOTPLUG=y 27CONFIG_HOTPLUG=y
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,63 +59,80 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66CONFIG_MIPS_PB1500=y
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
83CONFIG_SOC_AU1X00=y 102# CONFIG_SGI_IP27 is not set
84# CONFIG_SOC_AU1000 is not set 103# CONFIG_SGI_IP32 is not set
85# CONFIG_SOC_AU1100 is not set 104# CONFIG_SIBYTE_BIGSUR is not set
86CONFIG_SOC_AU1500=y 105# CONFIG_SIBYTE_SWARM is not set
87# CONFIG_SOC_AU1550 is not set 106# CONFIG_SIBYTE_SENTOSA is not set
88# CONFIG_MIPS_PB1000 is not set 107# CONFIG_SIBYTE_RHONE is not set
89# CONFIG_MIPS_PB1100 is not set 108# CONFIG_SIBYTE_CARMEL is not set
90CONFIG_MIPS_PB1500=y 109# CONFIG_SIBYTE_PTSWARM is not set
91# CONFIG_MIPS_PB1550 is not set 110# CONFIG_SIBYTE_LITTLESUR is not set
92# CONFIG_MIPS_DB1000 is not set 111# CONFIG_SIBYTE_CRHINE is not set
93# CONFIG_MIPS_DB1100 is not set 112# CONFIG_SIBYTE_CRHONE is not set
94# CONFIG_MIPS_DB1500 is not set
95# CONFIG_MIPS_DB1550 is not set
96# CONFIG_MIPS_BOSPORUS is not set
97# CONFIG_MIPS_MIRAGE is not set
98# CONFIG_MIPS_XXS1500 is not set
99# CONFIG_MIPS_MTX1 is not set
100# CONFIG_SIBYTE_SB1xxx_SOC is not set
101# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
102# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
103CONFIG_RWSEM_GENERIC_SPINLOCK=y 117CONFIG_RWSEM_GENERIC_SPINLOCK=y
104CONFIG_GENERIC_CALIBRATE_DELAY=y 118CONFIG_GENERIC_CALIBRATE_DELAY=y
105CONFIG_HAVE_DEC_LOCK=y 119CONFIG_DMA_NONCOHERENT=y
106CONFIG_DMA_COHERENT=y 120CONFIG_DMA_NEED_PCI_MAP_STATE=y
121# CONFIG_CPU_BIG_ENDIAN is not set
107CONFIG_CPU_LITTLE_ENDIAN=y 122CONFIG_CPU_LITTLE_ENDIAN=y
123CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
124CONFIG_SOC_AU1500=y
125CONFIG_SOC_AU1X00=y
108# CONFIG_AU1X00_USB_DEVICE is not set 126# CONFIG_AU1X00_USB_DEVICE is not set
109CONFIG_MIPS_L1_CACHE_SHIFT=5 127CONFIG_MIPS_L1_CACHE_SHIFT=5
110 128
111# 129#
112# CPU selection 130# CPU selection
113# 131#
114CONFIG_CPU_MIPS32=y 132CONFIG_CPU_MIPS32_R1=y
115# CONFIG_CPU_MIPS64 is not set 133# CONFIG_CPU_MIPS32_R2 is not set
134# CONFIG_CPU_MIPS64_R1 is not set
135# CONFIG_CPU_MIPS64_R2 is not set
116# CONFIG_CPU_R3000 is not set 136# CONFIG_CPU_R3000 is not set
117# CONFIG_CPU_TX39XX is not set 137# CONFIG_CPU_TX39XX is not set
118# CONFIG_CPU_VR41XX is not set 138# CONFIG_CPU_VR41XX is not set
@@ -128,15 +148,39 @@ CONFIG_CPU_MIPS32=y
128# CONFIG_CPU_RM7000 is not set 148# CONFIG_CPU_RM7000 is not set
129# CONFIG_CPU_RM9000 is not set 149# CONFIG_CPU_RM9000 is not set
130# CONFIG_CPU_SB1 is not set 150# CONFIG_CPU_SB1 is not set
151CONFIG_SYS_HAS_CPU_MIPS32_R1=y
152CONFIG_CPU_MIPS32=y
153CONFIG_CPU_MIPSR1=y
154CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
155CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
156
157#
158# Kernel type
159#
160CONFIG_32BIT=y
161# CONFIG_64BIT is not set
131CONFIG_PAGE_SIZE_4KB=y 162CONFIG_PAGE_SIZE_4KB=y
132# CONFIG_PAGE_SIZE_8KB is not set 163# CONFIG_PAGE_SIZE_8KB is not set
133# CONFIG_PAGE_SIZE_16KB is not set 164# CONFIG_PAGE_SIZE_16KB is not set
134# CONFIG_PAGE_SIZE_64KB is not set 165# CONFIG_PAGE_SIZE_64KB is not set
135CONFIG_CPU_HAS_PREFETCH=y 166CONFIG_CPU_HAS_PREFETCH=y
167# CONFIG_MIPS_MT is not set
136CONFIG_64BIT_PHYS_ADDR=y 168CONFIG_64BIT_PHYS_ADDR=y
137# CONFIG_CPU_ADVANCED is not set 169# CONFIG_CPU_ADVANCED is not set
138CONFIG_CPU_HAS_LLSC=y 170CONFIG_CPU_HAS_LLSC=y
139CONFIG_CPU_HAS_SYNC=y 171CONFIG_CPU_HAS_SYNC=y
172CONFIG_GENERIC_HARDIRQS=y
173CONFIG_GENERIC_IRQ_PROBE=y
174CONFIG_ARCH_FLATMEM_ENABLE=y
175CONFIG_SELECT_MEMORY_MODEL=y
176CONFIG_FLATMEM_MANUAL=y
177# CONFIG_DISCONTIGMEM_MANUAL is not set
178# CONFIG_SPARSEMEM_MANUAL is not set
179CONFIG_FLATMEM=y
180CONFIG_FLAT_NODE_MEM_MAP=y
181# CONFIG_SPARSEMEM_STATIC is not set
182CONFIG_PREEMPT_NONE=y
183# CONFIG_PREEMPT_VOLUNTARY is not set
140# CONFIG_PREEMPT is not set 184# CONFIG_PREEMPT is not set
141 185
142# 186#
@@ -145,7 +189,6 @@ CONFIG_CPU_HAS_SYNC=y
145CONFIG_HW_HAS_PCI=y 189CONFIG_HW_HAS_PCI=y
146CONFIG_PCI=y 190CONFIG_PCI=y
147CONFIG_PCI_LEGACY_PROC=y 191CONFIG_PCI_LEGACY_PROC=y
148CONFIG_PCI_NAMES=y
149CONFIG_MMU=y 192CONFIG_MMU=y
150 193
151# 194#
@@ -154,6 +197,8 @@ CONFIG_MMU=y
154CONFIG_PCCARD=m 197CONFIG_PCCARD=m
155# CONFIG_PCMCIA_DEBUG is not set 198# CONFIG_PCMCIA_DEBUG is not set
156CONFIG_PCMCIA=m 199CONFIG_PCMCIA=m
200CONFIG_PCMCIA_LOAD_CIS=y
201CONFIG_PCMCIA_IOCTL=y
157CONFIG_CARDBUS=y 202CONFIG_CARDBUS=y
158 203
159# 204#
@@ -177,6 +222,100 @@ CONFIG_PCCARD_NONSTATIC=m
177CONFIG_BINFMT_ELF=y 222CONFIG_BINFMT_ELF=y
178# CONFIG_BINFMT_MISC is not set 223# CONFIG_BINFMT_MISC is not set
179CONFIG_TRAD_SIGNALS=y 224CONFIG_TRAD_SIGNALS=y
225# CONFIG_PM is not set
226
227#
228# Networking
229#
230CONFIG_NET=y
231
232#
233# Networking options
234#
235CONFIG_PACKET=y
236# CONFIG_PACKET_MMAP is not set
237CONFIG_UNIX=y
238CONFIG_XFRM=y
239CONFIG_XFRM_USER=m
240CONFIG_NET_KEY=y
241CONFIG_INET=y
242CONFIG_IP_MULTICAST=y
243# CONFIG_IP_ADVANCED_ROUTER is not set
244CONFIG_IP_FIB_HASH=y
245CONFIG_IP_PNP=y
246# CONFIG_IP_PNP_DHCP is not set
247CONFIG_IP_PNP_BOOTP=y
248# CONFIG_IP_PNP_RARP is not set
249# CONFIG_NET_IPIP is not set
250# CONFIG_NET_IPGRE is not set
251# CONFIG_IP_MROUTE is not set
252# CONFIG_ARPD is not set
253# CONFIG_SYN_COOKIES is not set
254# CONFIG_INET_AH is not set
255# CONFIG_INET_ESP is not set
256# CONFIG_INET_IPCOMP is not set
257CONFIG_INET_TUNNEL=m
258CONFIG_INET_DIAG=y
259CONFIG_INET_TCP_DIAG=y
260# CONFIG_TCP_CONG_ADVANCED is not set
261CONFIG_TCP_CONG_BIC=y
262
263#
264# IP: Virtual Server Configuration
265#
266# CONFIG_IP_VS is not set
267# CONFIG_IPV6 is not set
268CONFIG_NETFILTER=y
269# CONFIG_NETFILTER_DEBUG is not set
270CONFIG_NETFILTER_NETLINK=m
271CONFIG_NETFILTER_NETLINK_QUEUE=m
272CONFIG_NETFILTER_NETLINK_LOG=m
273
274#
275# IP: Netfilter Configuration
276#
277# CONFIG_IP_NF_CONNTRACK is not set
278CONFIG_IP_NF_PPTP=m
279# CONFIG_IP_NF_QUEUE is not set
280# CONFIG_IP_NF_IPTABLES is not set
281# CONFIG_IP_NF_ARPTABLES is not set
282
283#
284# DCCP Configuration (EXPERIMENTAL)
285#
286# CONFIG_IP_DCCP is not set
287
288#
289# SCTP Configuration (EXPERIMENTAL)
290#
291# CONFIG_IP_SCTP is not set
292# CONFIG_ATM is not set
293# CONFIG_BRIDGE is not set
294# CONFIG_VLAN_8021Q is not set
295# CONFIG_DECNET is not set
296# CONFIG_LLC2 is not set
297# CONFIG_IPX is not set
298# CONFIG_ATALK is not set
299# CONFIG_X25 is not set
300# CONFIG_LAPB is not set
301# CONFIG_NET_DIVERT is not set
302# CONFIG_ECONET is not set
303# CONFIG_WAN_ROUTER is not set
304# CONFIG_NET_SCHED is not set
305# CONFIG_NET_CLS_ROUTE is not set
306
307#
308# Network testing
309#
310# CONFIG_NET_PKTGEN is not set
311# CONFIG_HAMRADIO is not set
312# CONFIG_IRDA is not set
313# CONFIG_BT is not set
314CONFIG_IEEE80211=m
315# CONFIG_IEEE80211_DEBUG is not set
316CONFIG_IEEE80211_CRYPT_WEP=m
317CONFIG_IEEE80211_CRYPT_CCMP=m
318CONFIG_IEEE80211_CRYPT_TKIP=m
180 319
181# 320#
182# Device Drivers 321# Device Drivers
@@ -187,12 +326,87 @@ CONFIG_TRAD_SIGNALS=y
187# 326#
188CONFIG_STANDALONE=y 327CONFIG_STANDALONE=y
189CONFIG_PREVENT_FIRMWARE_BUILD=y 328CONFIG_PREVENT_FIRMWARE_BUILD=y
190# CONFIG_FW_LOADER is not set 329CONFIG_FW_LOADER=m
330
331#
332# Connector - unified userspace <-> kernelspace linker
333#
334CONFIG_CONNECTOR=m
191 335
192# 336#
193# Memory Technology Devices (MTD) 337# Memory Technology Devices (MTD)
194# 338#
195# CONFIG_MTD is not set 339CONFIG_MTD=y
340# CONFIG_MTD_DEBUG is not set
341# CONFIG_MTD_CONCAT is not set
342CONFIG_MTD_PARTITIONS=y
343# CONFIG_MTD_REDBOOT_PARTS is not set
344# CONFIG_MTD_CMDLINE_PARTS is not set
345
346#
347# User Modules And Translation Layers
348#
349CONFIG_MTD_CHAR=y
350CONFIG_MTD_BLOCK=y
351# CONFIG_FTL is not set
352# CONFIG_NFTL is not set
353# CONFIG_INFTL is not set
354
355#
356# RAM/ROM/Flash chip drivers
357#
358CONFIG_MTD_CFI=y
359# CONFIG_MTD_JEDECPROBE is not set
360CONFIG_MTD_GEN_PROBE=y
361# CONFIG_MTD_CFI_ADV_OPTIONS is not set
362CONFIG_MTD_MAP_BANK_WIDTH_1=y
363CONFIG_MTD_MAP_BANK_WIDTH_2=y
364CONFIG_MTD_MAP_BANK_WIDTH_4=y
365# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
366# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
367# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
368CONFIG_MTD_CFI_I1=y
369CONFIG_MTD_CFI_I2=y
370# CONFIG_MTD_CFI_I4 is not set
371# CONFIG_MTD_CFI_I8 is not set
372# CONFIG_MTD_CFI_INTELEXT is not set
373CONFIG_MTD_CFI_AMDSTD=y
374CONFIG_MTD_CFI_AMDSTD_RETRY=0
375# CONFIG_MTD_CFI_STAA is not set
376CONFIG_MTD_CFI_UTIL=y
377# CONFIG_MTD_RAM is not set
378# CONFIG_MTD_ROM is not set
379# CONFIG_MTD_ABSENT is not set
380
381#
382# Mapping drivers for chip access
383#
384# CONFIG_MTD_COMPLEX_MAPPINGS is not set
385# CONFIG_MTD_PHYSMAP is not set
386CONFIG_MTD_ALCHEMY=y
387# CONFIG_MTD_PLATRAM is not set
388
389#
390# Self-contained MTD device drivers
391#
392# CONFIG_MTD_PMC551 is not set
393# CONFIG_MTD_SLRAM is not set
394# CONFIG_MTD_PHRAM is not set
395# CONFIG_MTD_MTDRAM is not set
396# CONFIG_MTD_BLKMTD is not set
397# CONFIG_MTD_BLOCK2MTD is not set
398
399#
400# Disk-On-Chip Device Drivers
401#
402# CONFIG_MTD_DOC2000 is not set
403# CONFIG_MTD_DOC2001 is not set
404# CONFIG_MTD_DOC2001PLUS is not set
405
406#
407# NAND Flash Device Drivers
408#
409# CONFIG_MTD_NAND is not set
196 410
197# 411#
198# Parallel port support 412# Parallel port support
@@ -206,7 +420,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
206# 420#
207# Block devices 421# Block devices
208# 422#
209# CONFIG_BLK_DEV_FD is not set
210# CONFIG_BLK_CPQ_DA is not set 423# CONFIG_BLK_CPQ_DA is not set
211# CONFIG_BLK_CPQ_CISS_DA is not set 424# CONFIG_BLK_CPQ_CISS_DA is not set
212# CONFIG_BLK_DEV_DAC960 is not set 425# CONFIG_BLK_DEV_DAC960 is not set
@@ -218,7 +431,6 @@ CONFIG_BLK_DEV_LOOP=y
218# CONFIG_BLK_DEV_SX8 is not set 431# CONFIG_BLK_DEV_SX8 is not set
219# CONFIG_BLK_DEV_RAM is not set 432# CONFIG_BLK_DEV_RAM is not set
220CONFIG_BLK_DEV_RAM_COUNT=16 433CONFIG_BLK_DEV_RAM_COUNT=16
221CONFIG_INITRAMFS_SOURCE=""
222# CONFIG_LBD is not set 434# CONFIG_LBD is not set
223CONFIG_CDROM_PKTCDVD=m 435CONFIG_CDROM_PKTCDVD=m
224CONFIG_CDROM_PKTCDVD_BUFFERS=8 436CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -275,6 +487,7 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
275CONFIG_BLK_DEV_HPT366=y 487CONFIG_BLK_DEV_HPT366=y
276# CONFIG_BLK_DEV_SC1200 is not set 488# CONFIG_BLK_DEV_SC1200 is not set
277# CONFIG_BLK_DEV_PIIX is not set 489# CONFIG_BLK_DEV_PIIX is not set
490# CONFIG_BLK_DEV_IT821X is not set
278# CONFIG_BLK_DEV_NS87415 is not set 491# CONFIG_BLK_DEV_NS87415 is not set
279# CONFIG_BLK_DEV_PDC202XX_OLD is not set 492# CONFIG_BLK_DEV_PDC202XX_OLD is not set
280# CONFIG_BLK_DEV_PDC202XX_NEW is not set 493# CONFIG_BLK_DEV_PDC202XX_NEW is not set
@@ -292,6 +505,7 @@ CONFIG_BLK_DEV_IDEDMA=y
292# 505#
293# SCSI device support 506# SCSI device support
294# 507#
508CONFIG_RAID_ATTRS=m
295# CONFIG_SCSI is not set 509# CONFIG_SCSI is not set
296 510
297# 511#
@@ -302,6 +516,7 @@ CONFIG_BLK_DEV_IDEDMA=y
302# 516#
303# Fusion MPT device support 517# Fusion MPT device support
304# 518#
519# CONFIG_FUSION is not set
305 520
306# 521#
307# IEEE 1394 (FireWire) support 522# IEEE 1394 (FireWire) support
@@ -314,94 +529,13 @@ CONFIG_BLK_DEV_IDEDMA=y
314# CONFIG_I2O is not set 529# CONFIG_I2O is not set
315 530
316# 531#
317# Networking support 532# Network device support
318#
319CONFIG_NET=y
320
321#
322# Networking options
323#
324CONFIG_PACKET=y
325# CONFIG_PACKET_MMAP is not set
326CONFIG_NETLINK_DEV=y
327CONFIG_UNIX=y
328CONFIG_NET_KEY=y
329CONFIG_INET=y
330CONFIG_IP_MULTICAST=y
331# CONFIG_IP_ADVANCED_ROUTER is not set
332CONFIG_IP_PNP=y
333# CONFIG_IP_PNP_DHCP is not set
334CONFIG_IP_PNP_BOOTP=y
335# CONFIG_IP_PNP_RARP is not set
336# CONFIG_NET_IPIP is not set
337# CONFIG_NET_IPGRE is not set
338# CONFIG_IP_MROUTE is not set
339# CONFIG_ARPD is not set
340# CONFIG_SYN_COOKIES is not set
341# CONFIG_INET_AH is not set
342# CONFIG_INET_ESP is not set
343# CONFIG_INET_IPCOMP is not set
344CONFIG_INET_TUNNEL=m
345CONFIG_IP_TCPDIAG=m
346# CONFIG_IP_TCPDIAG_IPV6 is not set
347
348#
349# IP: Virtual Server Configuration
350#
351# CONFIG_IP_VS is not set
352# CONFIG_IPV6 is not set
353CONFIG_NETFILTER=y
354# CONFIG_NETFILTER_DEBUG is not set
355
356#
357# IP: Netfilter Configuration
358# 533#
359# CONFIG_IP_NF_CONNTRACK is not set
360CONFIG_IP_NF_CONNTRACK_MARK=y
361# CONFIG_IP_NF_QUEUE is not set
362# CONFIG_IP_NF_IPTABLES is not set
363# CONFIG_IP_NF_ARPTABLES is not set
364CONFIG_XFRM=y
365CONFIG_XFRM_USER=m
366
367#
368# SCTP Configuration (EXPERIMENTAL)
369#
370# CONFIG_IP_SCTP is not set
371# CONFIG_ATM is not set
372# CONFIG_BRIDGE is not set
373# CONFIG_VLAN_8021Q is not set
374# CONFIG_DECNET is not set
375# CONFIG_LLC2 is not set
376# CONFIG_IPX is not set
377# CONFIG_ATALK is not set
378# CONFIG_X25 is not set
379# CONFIG_LAPB is not set
380# CONFIG_NET_DIVERT is not set
381# CONFIG_ECONET is not set
382# CONFIG_WAN_ROUTER is not set
383
384#
385# QoS and/or fair queueing
386#
387# CONFIG_NET_SCHED is not set
388# CONFIG_NET_CLS_ROUTE is not set
389
390#
391# Network testing
392#
393# CONFIG_NET_PKTGEN is not set
394# CONFIG_NETPOLL is not set
395# CONFIG_NET_POLL_CONTROLLER is not set
396# CONFIG_HAMRADIO is not set
397# CONFIG_IRDA is not set
398# CONFIG_BT is not set
399CONFIG_NETDEVICES=y 534CONFIG_NETDEVICES=y
400# CONFIG_DUMMY is not set 535# CONFIG_DUMMY is not set
401# CONFIG_BONDING is not set 536# CONFIG_BONDING is not set
402# CONFIG_EQUALIZER is not set 537# CONFIG_EQUALIZER is not set
403# CONFIG_TUN is not set 538# CONFIG_TUN is not set
404# CONFIG_ETHERTAP is not set
405 539
406# 540#
407# ARCnet devices 541# ARCnet devices
@@ -409,6 +543,21 @@ CONFIG_NETDEVICES=y
409# CONFIG_ARCNET is not set 543# CONFIG_ARCNET is not set
410 544
411# 545#
546# PHY device support
547#
548CONFIG_PHYLIB=m
549CONFIG_PHYCONTROL=y
550
551#
552# MII PHY device drivers
553#
554CONFIG_MARVELL_PHY=m
555CONFIG_DAVICOM_PHY=m
556CONFIG_QSEMI_PHY=m
557CONFIG_LXT_PHY=m
558CONFIG_CICADA_PHY=m
559
560#
412# Ethernet (10 or 100Mbit) 561# Ethernet (10 or 100Mbit)
413# 562#
414CONFIG_NET_ETHERNET=y 563CONFIG_NET_ETHERNET=y
@@ -435,12 +584,16 @@ CONFIG_MIPS_AU1X00_ENET=y
435# CONFIG_HAMACHI is not set 584# CONFIG_HAMACHI is not set
436# CONFIG_YELLOWFIN is not set 585# CONFIG_YELLOWFIN is not set
437# CONFIG_R8169 is not set 586# CONFIG_R8169 is not set
587# CONFIG_SIS190 is not set
588# CONFIG_SKGE is not set
438# CONFIG_SK98LIN is not set 589# CONFIG_SK98LIN is not set
439# CONFIG_TIGON3 is not set 590# CONFIG_TIGON3 is not set
591# CONFIG_BNX2 is not set
440 592
441# 593#
442# Ethernet (10000 Mbit) 594# Ethernet (10000 Mbit)
443# 595#
596# CONFIG_CHELSIO_T1 is not set
444# CONFIG_IXGB is not set 597# CONFIG_IXGB is not set
445# CONFIG_S2IO is not set 598# CONFIG_S2IO is not set
446 599
@@ -453,6 +606,8 @@ CONFIG_MIPS_AU1X00_ENET=y
453# Wireless LAN (non-hamradio) 606# Wireless LAN (non-hamradio)
454# 607#
455# CONFIG_NET_RADIO is not set 608# CONFIG_NET_RADIO is not set
609# CONFIG_IPW_DEBUG is not set
610CONFIG_IPW2200=m
456 611
457# 612#
458# PCMCIA network device support 613# PCMCIA network device support
@@ -484,6 +639,8 @@ CONFIG_PPPOE=m
484# CONFIG_SLIP is not set 639# CONFIG_SLIP is not set
485# CONFIG_SHAPER is not set 640# CONFIG_SHAPER is not set
486# CONFIG_NETCONSOLE is not set 641# CONFIG_NETCONSOLE is not set
642# CONFIG_NETPOLL is not set
643# CONFIG_NET_POLL_CONTROLLER is not set
487 644
488# 645#
489# ISDN subsystem 646# ISDN subsystem
@@ -513,19 +670,6 @@ CONFIG_INPUT_EVDEV=y
513# CONFIG_INPUT_EVBUG is not set 670# CONFIG_INPUT_EVBUG is not set
514 671
515# 672#
516# Input I/O drivers
517#
518# CONFIG_GAMEPORT is not set
519CONFIG_SOUND_GAMEPORT=y
520CONFIG_SERIO=y
521# CONFIG_SERIO_I8042 is not set
522CONFIG_SERIO_SERPORT=y
523# CONFIG_SERIO_CT82C710 is not set
524# CONFIG_SERIO_PCIPS2 is not set
525# CONFIG_SERIO_LIBPS2 is not set
526CONFIG_SERIO_RAW=m
527
528#
529# Input Device Drivers 673# Input Device Drivers
530# 674#
531# CONFIG_INPUT_KEYBOARD is not set 675# CONFIG_INPUT_KEYBOARD is not set
@@ -535,6 +679,17 @@ CONFIG_SERIO_RAW=m
535# CONFIG_INPUT_MISC is not set 679# CONFIG_INPUT_MISC is not set
536 680
537# 681#
682# Hardware I/O ports
683#
684CONFIG_SERIO=y
685# CONFIG_SERIO_I8042 is not set
686CONFIG_SERIO_SERPORT=y
687# CONFIG_SERIO_PCIPS2 is not set
688# CONFIG_SERIO_LIBPS2 is not set
689CONFIG_SERIO_RAW=m
690# CONFIG_GAMEPORT is not set
691
692#
538# Character devices 693# Character devices
539# 694#
540# CONFIG_VT is not set 695# CONFIG_VT is not set
@@ -554,6 +709,7 @@ CONFIG_SERIAL_AU1X00=y
554CONFIG_SERIAL_AU1X00_CONSOLE=y 709CONFIG_SERIAL_AU1X00_CONSOLE=y
555CONFIG_SERIAL_CORE=y 710CONFIG_SERIAL_CORE=y
556CONFIG_SERIAL_CORE_CONSOLE=y 711CONFIG_SERIAL_CORE_CONSOLE=y
712# CONFIG_SERIAL_JSM is not set
557CONFIG_UNIX98_PTYS=y 713CONFIG_UNIX98_PTYS=y
558CONFIG_LEGACY_PTYS=y 714CONFIG_LEGACY_PTYS=y
559CONFIG_LEGACY_PTY_COUNT=256 715CONFIG_LEGACY_PTY_COUNT=256
@@ -585,6 +741,11 @@ CONFIG_SYNCLINK_CS=m
585# CONFIG_RAW_DRIVER is not set 741# CONFIG_RAW_DRIVER is not set
586 742
587# 743#
744# TPM devices
745#
746# CONFIG_TCG_TPM is not set
747
748#
588# I2C support 749# I2C support
589# 750#
590# CONFIG_I2C is not set 751# CONFIG_I2C is not set
@@ -595,10 +756,20 @@ CONFIG_SYNCLINK_CS=m
595# CONFIG_W1 is not set 756# CONFIG_W1 is not set
596 757
597# 758#
759# Hardware Monitoring support
760#
761# CONFIG_HWMON is not set
762# CONFIG_HWMON_VID is not set
763
764#
598# Misc devices 765# Misc devices
599# 766#
600 767
601# 768#
769# Multimedia Capabilities Port drivers
770#
771
772#
602# Multimedia devices 773# Multimedia devices
603# 774#
604# CONFIG_VIDEO_DEV is not set 775# CONFIG_VIDEO_DEV is not set
@@ -612,7 +783,6 @@ CONFIG_SYNCLINK_CS=m
612# Graphics support 783# Graphics support
613# 784#
614# CONFIG_FB is not set 785# CONFIG_FB is not set
615# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
616 786
617# 787#
618# Sound 788# Sound
@@ -622,13 +792,9 @@ CONFIG_SYNCLINK_CS=m
622# 792#
623# USB support 793# USB support
624# 794#
625# CONFIG_USB is not set
626CONFIG_USB_ARCH_HAS_HCD=y 795CONFIG_USB_ARCH_HAS_HCD=y
627CONFIG_USB_ARCH_HAS_OHCI=y 796CONFIG_USB_ARCH_HAS_OHCI=y
628 797# CONFIG_USB is not set
629#
630# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
631#
632 798
633# 799#
634# USB Gadget Support 800# USB Gadget Support
@@ -646,12 +812,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y
646# CONFIG_INFINIBAND is not set 812# CONFIG_INFINIBAND is not set
647 813
648# 814#
815# SN Devices
816#
817
818#
649# File systems 819# File systems
650# 820#
651CONFIG_EXT2_FS=y 821CONFIG_EXT2_FS=y
652CONFIG_EXT2_FS_XATTR=y 822CONFIG_EXT2_FS_XATTR=y
653CONFIG_EXT2_FS_POSIX_ACL=y 823CONFIG_EXT2_FS_POSIX_ACL=y
654# CONFIG_EXT2_FS_SECURITY is not set 824# CONFIG_EXT2_FS_SECURITY is not set
825# CONFIG_EXT2_FS_XIP is not set
655CONFIG_EXT3_FS=y 826CONFIG_EXT3_FS=y
656CONFIG_EXT3_FS_XATTR=y 827CONFIG_EXT3_FS_XATTR=y
657CONFIG_EXT3_FS_POSIX_ACL=y 828CONFIG_EXT3_FS_POSIX_ACL=y
@@ -670,10 +841,12 @@ CONFIG_FS_POSIX_ACL=y
670# CONFIG_XFS_FS is not set 841# CONFIG_XFS_FS is not set
671# CONFIG_MINIX_FS is not set 842# CONFIG_MINIX_FS is not set
672# CONFIG_ROMFS_FS is not set 843# CONFIG_ROMFS_FS is not set
844CONFIG_INOTIFY=y
673# CONFIG_QUOTA is not set 845# CONFIG_QUOTA is not set
674CONFIG_DNOTIFY=y 846CONFIG_DNOTIFY=y
675CONFIG_AUTOFS_FS=m 847CONFIG_AUTOFS_FS=m
676CONFIG_AUTOFS4_FS=m 848CONFIG_AUTOFS4_FS=m
849CONFIG_FUSE_FS=m
677 850
678# 851#
679# CD-ROM/DVD Filesystems 852# CD-ROM/DVD Filesystems
@@ -694,13 +867,10 @@ CONFIG_AUTOFS4_FS=m
694CONFIG_PROC_FS=y 867CONFIG_PROC_FS=y
695CONFIG_PROC_KCORE=y 868CONFIG_PROC_KCORE=y
696CONFIG_SYSFS=y 869CONFIG_SYSFS=y
697# CONFIG_DEVFS_FS is not set
698CONFIG_DEVPTS_FS_XATTR=y
699CONFIG_DEVPTS_FS_SECURITY=y
700CONFIG_TMPFS=y 870CONFIG_TMPFS=y
701# CONFIG_TMPFS_XATTR is not set
702# CONFIG_HUGETLB_PAGE is not set 871# CONFIG_HUGETLB_PAGE is not set
703CONFIG_RAMFS=y 872CONFIG_RAMFS=y
873CONFIG_RELAYFS_FS=m
704 874
705# 875#
706# Miscellaneous filesystems 876# Miscellaneous filesystems
@@ -712,6 +882,8 @@ CONFIG_RAMFS=y
712# CONFIG_BEFS_FS is not set 882# CONFIG_BEFS_FS is not set
713# CONFIG_BFS_FS is not set 883# CONFIG_BFS_FS is not set
714# CONFIG_EFS_FS is not set 884# CONFIG_EFS_FS is not set
885# CONFIG_JFFS_FS is not set
886# CONFIG_JFFS2_FS is not set
715CONFIG_CRAMFS=m 887CONFIG_CRAMFS=m
716# CONFIG_VXFS_FS is not set 888# CONFIG_VXFS_FS is not set
717# CONFIG_HPFS_FS is not set 889# CONFIG_HPFS_FS is not set
@@ -732,6 +904,7 @@ CONFIG_NFSD=m
732CONFIG_ROOT_NFS=y 904CONFIG_ROOT_NFS=y
733CONFIG_LOCKD=y 905CONFIG_LOCKD=y
734CONFIG_EXPORTFS=m 906CONFIG_EXPORTFS=m
907CONFIG_NFS_COMMON=y
735CONFIG_SUNRPC=y 908CONFIG_SUNRPC=y
736# CONFIG_RPCSEC_GSS_KRB5 is not set 909# CONFIG_RPCSEC_GSS_KRB5 is not set
737# CONFIG_RPCSEC_GSS_SPKM3 is not set 910# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -741,6 +914,7 @@ CONFIG_SMB_FS=m
741# CONFIG_NCP_FS is not set 914# CONFIG_NCP_FS is not set
742# CONFIG_CODA_FS is not set 915# CONFIG_CODA_FS is not set
743# CONFIG_AFS_FS is not set 916# CONFIG_AFS_FS is not set
917# CONFIG_9P_FS is not set
744 918
745# 919#
746# Partition Types 920# Partition Types
@@ -800,7 +974,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
800# 974#
801# Kernel hacking 975# Kernel hacking
802# 976#
977# CONFIG_PRINTK_TIME is not set
803# CONFIG_DEBUG_KERNEL is not set 978# CONFIG_DEBUG_KERNEL is not set
979CONFIG_LOG_BUF_SHIFT=14
804CONFIG_CROSSCOMPILE=y 980CONFIG_CROSSCOMPILE=y
805CONFIG_CMDLINE="" 981CONFIG_CMDLINE=""
806 982
@@ -816,27 +992,28 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
816# 992#
817CONFIG_CRYPTO=y 993CONFIG_CRYPTO=y
818CONFIG_CRYPTO_HMAC=y 994CONFIG_CRYPTO_HMAC=y
819CONFIG_CRYPTO_NULL=y 995CONFIG_CRYPTO_NULL=m
820# CONFIG_CRYPTO_MD4 is not set 996CONFIG_CRYPTO_MD4=m
821# CONFIG_CRYPTO_MD5 is not set 997CONFIG_CRYPTO_MD5=m
822# CONFIG_CRYPTO_SHA1 is not set 998CONFIG_CRYPTO_SHA1=m
823# CONFIG_CRYPTO_SHA256 is not set 999CONFIG_CRYPTO_SHA256=m
824CONFIG_CRYPTO_SHA512=y 1000CONFIG_CRYPTO_SHA512=m
825CONFIG_CRYPTO_WP512=m 1001CONFIG_CRYPTO_WP512=m
826# CONFIG_CRYPTO_DES is not set 1002CONFIG_CRYPTO_TGR192=m
827# CONFIG_CRYPTO_BLOWFISH is not set 1003CONFIG_CRYPTO_DES=m
828CONFIG_CRYPTO_TWOFISH=y 1004CONFIG_CRYPTO_BLOWFISH=m
829# CONFIG_CRYPTO_SERPENT is not set 1005CONFIG_CRYPTO_TWOFISH=m
1006CONFIG_CRYPTO_SERPENT=m
830CONFIG_CRYPTO_AES=m 1007CONFIG_CRYPTO_AES=m
831# CONFIG_CRYPTO_CAST5 is not set 1008CONFIG_CRYPTO_CAST5=m
832# CONFIG_CRYPTO_CAST6 is not set 1009CONFIG_CRYPTO_CAST6=m
833CONFIG_CRYPTO_TEA=m 1010CONFIG_CRYPTO_TEA=m
834# CONFIG_CRYPTO_ARC4 is not set 1011CONFIG_CRYPTO_ARC4=m
835CONFIG_CRYPTO_KHAZAD=m 1012CONFIG_CRYPTO_KHAZAD=m
836CONFIG_CRYPTO_ANUBIS=m 1013CONFIG_CRYPTO_ANUBIS=m
837CONFIG_CRYPTO_DEFLATE=y 1014CONFIG_CRYPTO_DEFLATE=m
838CONFIG_CRYPTO_MICHAEL_MIC=y 1015CONFIG_CRYPTO_MICHAEL_MIC=m
839# CONFIG_CRYPTO_CRC32C is not set 1016CONFIG_CRYPTO_CRC32C=m
840# CONFIG_CRYPTO_TEST is not set 1017# CONFIG_CRYPTO_TEST is not set
841 1018
842# 1019#
@@ -847,9 +1024,8 @@ CONFIG_CRYPTO_MICHAEL_MIC=y
847# Library routines 1024# Library routines
848# 1025#
849CONFIG_CRC_CCITT=m 1026CONFIG_CRC_CCITT=m
1027CONFIG_CRC16=m
850CONFIG_CRC32=y 1028CONFIG_CRC32=y
851# CONFIG_LIBCRC32C is not set 1029CONFIG_LIBCRC32C=m
852CONFIG_ZLIB_INFLATE=y 1030CONFIG_ZLIB_INFLATE=m
853CONFIG_ZLIB_DEFLATE=y 1031CONFIG_ZLIB_DEFLATE=m
854CONFIG_GENERIC_HARDIRQS=y
855CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 8e426776c098..bbad27cb40a2 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:09 2005 4# Thu Oct 20 22:26:47 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29CONFIG_HOTPLUG=y 27CONFIG_HOTPLUG=y
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,63 +59,80 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67CONFIG_MIPS_PB1550=y
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
81# CONFIG_NEC_OSPREY is not set 98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
82# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
83CONFIG_SOC_AU1X00=y 102# CONFIG_SGI_IP27 is not set
84# CONFIG_SOC_AU1000 is not set 103# CONFIG_SGI_IP32 is not set
85# CONFIG_SOC_AU1100 is not set 104# CONFIG_SIBYTE_BIGSUR is not set
86# CONFIG_SOC_AU1500 is not set 105# CONFIG_SIBYTE_SWARM is not set
87CONFIG_SOC_AU1550=y 106# CONFIG_SIBYTE_SENTOSA is not set
88# CONFIG_MIPS_PB1000 is not set 107# CONFIG_SIBYTE_RHONE is not set
89# CONFIG_MIPS_PB1100 is not set 108# CONFIG_SIBYTE_CARMEL is not set
90# CONFIG_MIPS_PB1500 is not set 109# CONFIG_SIBYTE_PTSWARM is not set
91CONFIG_MIPS_PB1550=y 110# CONFIG_SIBYTE_LITTLESUR is not set
92# CONFIG_MIPS_DB1000 is not set 111# CONFIG_SIBYTE_CRHINE is not set
93# CONFIG_MIPS_DB1100 is not set 112# CONFIG_SIBYTE_CRHONE is not set
94# CONFIG_MIPS_DB1500 is not set
95# CONFIG_MIPS_DB1550 is not set
96# CONFIG_MIPS_BOSPORUS is not set
97# CONFIG_MIPS_MIRAGE is not set
98# CONFIG_MIPS_XXS1500 is not set
99# CONFIG_MIPS_MTX1 is not set
100# CONFIG_SIBYTE_SB1xxx_SOC is not set
101# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
102# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
103CONFIG_RWSEM_GENERIC_SPINLOCK=y 117CONFIG_RWSEM_GENERIC_SPINLOCK=y
104CONFIG_GENERIC_CALIBRATE_DELAY=y 118CONFIG_GENERIC_CALIBRATE_DELAY=y
105CONFIG_HAVE_DEC_LOCK=y 119CONFIG_DMA_NONCOHERENT=y
106CONFIG_DMA_COHERENT=y 120CONFIG_DMA_NEED_PCI_MAP_STATE=y
107CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y 121CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
122# CONFIG_CPU_BIG_ENDIAN is not set
108CONFIG_CPU_LITTLE_ENDIAN=y 123CONFIG_CPU_LITTLE_ENDIAN=y
124CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
125CONFIG_SOC_AU1550=y
126CONFIG_SOC_AU1X00=y
109CONFIG_MIPS_L1_CACHE_SHIFT=5 127CONFIG_MIPS_L1_CACHE_SHIFT=5
110 128
111# 129#
112# CPU selection 130# CPU selection
113# 131#
114CONFIG_CPU_MIPS32=y 132CONFIG_CPU_MIPS32_R1=y
115# CONFIG_CPU_MIPS64 is not set 133# CONFIG_CPU_MIPS32_R2 is not set
134# CONFIG_CPU_MIPS64_R1 is not set
135# CONFIG_CPU_MIPS64_R2 is not set
116# CONFIG_CPU_R3000 is not set 136# CONFIG_CPU_R3000 is not set
117# CONFIG_CPU_TX39XX is not set 137# CONFIG_CPU_TX39XX is not set
118# CONFIG_CPU_VR41XX is not set 138# CONFIG_CPU_VR41XX is not set
@@ -128,15 +148,39 @@ CONFIG_CPU_MIPS32=y
128# CONFIG_CPU_RM7000 is not set 148# CONFIG_CPU_RM7000 is not set
129# CONFIG_CPU_RM9000 is not set 149# CONFIG_CPU_RM9000 is not set
130# CONFIG_CPU_SB1 is not set 150# CONFIG_CPU_SB1 is not set
151CONFIG_SYS_HAS_CPU_MIPS32_R1=y
152CONFIG_CPU_MIPS32=y
153CONFIG_CPU_MIPSR1=y
154CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
155CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
156
157#
158# Kernel type
159#
160CONFIG_32BIT=y
161# CONFIG_64BIT is not set
131CONFIG_PAGE_SIZE_4KB=y 162CONFIG_PAGE_SIZE_4KB=y
132# CONFIG_PAGE_SIZE_8KB is not set 163# CONFIG_PAGE_SIZE_8KB is not set
133# CONFIG_PAGE_SIZE_16KB is not set 164# CONFIG_PAGE_SIZE_16KB is not set
134# CONFIG_PAGE_SIZE_64KB is not set 165# CONFIG_PAGE_SIZE_64KB is not set
135CONFIG_CPU_HAS_PREFETCH=y 166CONFIG_CPU_HAS_PREFETCH=y
167# CONFIG_MIPS_MT is not set
136CONFIG_64BIT_PHYS_ADDR=y 168CONFIG_64BIT_PHYS_ADDR=y
137# CONFIG_CPU_ADVANCED is not set 169# CONFIG_CPU_ADVANCED is not set
138CONFIG_CPU_HAS_LLSC=y 170CONFIG_CPU_HAS_LLSC=y
139CONFIG_CPU_HAS_SYNC=y 171CONFIG_CPU_HAS_SYNC=y
172CONFIG_GENERIC_HARDIRQS=y
173CONFIG_GENERIC_IRQ_PROBE=y
174CONFIG_ARCH_FLATMEM_ENABLE=y
175CONFIG_SELECT_MEMORY_MODEL=y
176CONFIG_FLATMEM_MANUAL=y
177# CONFIG_DISCONTIGMEM_MANUAL is not set
178# CONFIG_SPARSEMEM_MANUAL is not set
179CONFIG_FLATMEM=y
180CONFIG_FLAT_NODE_MEM_MAP=y
181# CONFIG_SPARSEMEM_STATIC is not set
182CONFIG_PREEMPT_NONE=y
183# CONFIG_PREEMPT_VOLUNTARY is not set
140# CONFIG_PREEMPT is not set 184# CONFIG_PREEMPT is not set
141 185
142# 186#
@@ -145,7 +189,6 @@ CONFIG_CPU_HAS_SYNC=y
145CONFIG_HW_HAS_PCI=y 189CONFIG_HW_HAS_PCI=y
146CONFIG_PCI=y 190CONFIG_PCI=y
147CONFIG_PCI_LEGACY_PROC=y 191CONFIG_PCI_LEGACY_PROC=y
148CONFIG_PCI_NAMES=y
149CONFIG_MMU=y 192CONFIG_MMU=y
150 193
151# 194#
@@ -154,6 +197,8 @@ CONFIG_MMU=y
154CONFIG_PCCARD=m 197CONFIG_PCCARD=m
155# CONFIG_PCMCIA_DEBUG is not set 198# CONFIG_PCMCIA_DEBUG is not set
156CONFIG_PCMCIA=m 199CONFIG_PCMCIA=m
200CONFIG_PCMCIA_LOAD_CIS=y
201CONFIG_PCMCIA_IOCTL=y
157CONFIG_CARDBUS=y 202CONFIG_CARDBUS=y
158 203
159# 204#
@@ -177,6 +222,100 @@ CONFIG_PCCARD_NONSTATIC=m
177CONFIG_BINFMT_ELF=y 222CONFIG_BINFMT_ELF=y
178# CONFIG_BINFMT_MISC is not set 223# CONFIG_BINFMT_MISC is not set
179CONFIG_TRAD_SIGNALS=y 224CONFIG_TRAD_SIGNALS=y
225# CONFIG_PM is not set
226
227#
228# Networking
229#
230CONFIG_NET=y
231
232#
233# Networking options
234#
235CONFIG_PACKET=y
236# CONFIG_PACKET_MMAP is not set
237CONFIG_UNIX=y
238CONFIG_XFRM=y
239CONFIG_XFRM_USER=m
240CONFIG_NET_KEY=y
241CONFIG_INET=y
242CONFIG_IP_MULTICAST=y
243# CONFIG_IP_ADVANCED_ROUTER is not set
244CONFIG_IP_FIB_HASH=y
245CONFIG_IP_PNP=y
246# CONFIG_IP_PNP_DHCP is not set
247CONFIG_IP_PNP_BOOTP=y
248# CONFIG_IP_PNP_RARP is not set
249# CONFIG_NET_IPIP is not set
250# CONFIG_NET_IPGRE is not set
251# CONFIG_IP_MROUTE is not set
252# CONFIG_ARPD is not set
253# CONFIG_SYN_COOKIES is not set
254# CONFIG_INET_AH is not set
255# CONFIG_INET_ESP is not set
256# CONFIG_INET_IPCOMP is not set
257CONFIG_INET_TUNNEL=m
258CONFIG_INET_DIAG=y
259CONFIG_INET_TCP_DIAG=y
260# CONFIG_TCP_CONG_ADVANCED is not set
261CONFIG_TCP_CONG_BIC=y
262
263#
264# IP: Virtual Server Configuration
265#
266# CONFIG_IP_VS is not set
267# CONFIG_IPV6 is not set
268CONFIG_NETFILTER=y
269# CONFIG_NETFILTER_DEBUG is not set
270CONFIG_NETFILTER_NETLINK=m
271CONFIG_NETFILTER_NETLINK_QUEUE=m
272CONFIG_NETFILTER_NETLINK_LOG=m
273
274#
275# IP: Netfilter Configuration
276#
277# CONFIG_IP_NF_CONNTRACK is not set
278CONFIG_IP_NF_PPTP=m
279# CONFIG_IP_NF_QUEUE is not set
280# CONFIG_IP_NF_IPTABLES is not set
281# CONFIG_IP_NF_ARPTABLES is not set
282
283#
284# DCCP Configuration (EXPERIMENTAL)
285#
286# CONFIG_IP_DCCP is not set
287
288#
289# SCTP Configuration (EXPERIMENTAL)
290#
291# CONFIG_IP_SCTP is not set
292# CONFIG_ATM is not set
293# CONFIG_BRIDGE is not set
294# CONFIG_VLAN_8021Q is not set
295# CONFIG_DECNET is not set
296# CONFIG_LLC2 is not set
297# CONFIG_IPX is not set
298# CONFIG_ATALK is not set
299# CONFIG_X25 is not set
300# CONFIG_LAPB is not set
301# CONFIG_NET_DIVERT is not set
302# CONFIG_ECONET is not set
303# CONFIG_WAN_ROUTER is not set
304# CONFIG_NET_SCHED is not set
305# CONFIG_NET_CLS_ROUTE is not set
306
307#
308# Network testing
309#
310# CONFIG_NET_PKTGEN is not set
311# CONFIG_HAMRADIO is not set
312# CONFIG_IRDA is not set
313# CONFIG_BT is not set
314CONFIG_IEEE80211=m
315# CONFIG_IEEE80211_DEBUG is not set
316CONFIG_IEEE80211_CRYPT_WEP=m
317CONFIG_IEEE80211_CRYPT_CCMP=m
318CONFIG_IEEE80211_CRYPT_TKIP=m
180 319
181# 320#
182# Device Drivers 321# Device Drivers
@@ -187,12 +326,87 @@ CONFIG_TRAD_SIGNALS=y
187# 326#
188CONFIG_STANDALONE=y 327CONFIG_STANDALONE=y
189CONFIG_PREVENT_FIRMWARE_BUILD=y 328CONFIG_PREVENT_FIRMWARE_BUILD=y
190# CONFIG_FW_LOADER is not set 329CONFIG_FW_LOADER=m
330
331#
332# Connector - unified userspace <-> kernelspace linker
333#
334CONFIG_CONNECTOR=m
191 335
192# 336#
193# Memory Technology Devices (MTD) 337# Memory Technology Devices (MTD)
194# 338#
195# CONFIG_MTD is not set 339CONFIG_MTD=y
340# CONFIG_MTD_DEBUG is not set
341# CONFIG_MTD_CONCAT is not set
342CONFIG_MTD_PARTITIONS=y
343# CONFIG_MTD_REDBOOT_PARTS is not set
344# CONFIG_MTD_CMDLINE_PARTS is not set
345
346#
347# User Modules And Translation Layers
348#
349CONFIG_MTD_CHAR=y
350CONFIG_MTD_BLOCK=y
351# CONFIG_FTL is not set
352# CONFIG_NFTL is not set
353# CONFIG_INFTL is not set
354
355#
356# RAM/ROM/Flash chip drivers
357#
358CONFIG_MTD_CFI=y
359# CONFIG_MTD_JEDECPROBE is not set
360CONFIG_MTD_GEN_PROBE=y
361# CONFIG_MTD_CFI_ADV_OPTIONS is not set
362CONFIG_MTD_MAP_BANK_WIDTH_1=y
363CONFIG_MTD_MAP_BANK_WIDTH_2=y
364CONFIG_MTD_MAP_BANK_WIDTH_4=y
365# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
366# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
367# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
368CONFIG_MTD_CFI_I1=y
369CONFIG_MTD_CFI_I2=y
370# CONFIG_MTD_CFI_I4 is not set
371# CONFIG_MTD_CFI_I8 is not set
372# CONFIG_MTD_CFI_INTELEXT is not set
373CONFIG_MTD_CFI_AMDSTD=y
374CONFIG_MTD_CFI_AMDSTD_RETRY=0
375# CONFIG_MTD_CFI_STAA is not set
376CONFIG_MTD_CFI_UTIL=y
377# CONFIG_MTD_RAM is not set
378# CONFIG_MTD_ROM is not set
379# CONFIG_MTD_ABSENT is not set
380
381#
382# Mapping drivers for chip access
383#
384# CONFIG_MTD_COMPLEX_MAPPINGS is not set
385# CONFIG_MTD_PHYSMAP is not set
386CONFIG_MTD_ALCHEMY=y
387# CONFIG_MTD_PLATRAM is not set
388
389#
390# Self-contained MTD device drivers
391#
392# CONFIG_MTD_PMC551 is not set
393# CONFIG_MTD_SLRAM is not set
394# CONFIG_MTD_PHRAM is not set
395# CONFIG_MTD_MTDRAM is not set
396# CONFIG_MTD_BLKMTD is not set
397# CONFIG_MTD_BLOCK2MTD is not set
398
399#
400# Disk-On-Chip Device Drivers
401#
402# CONFIG_MTD_DOC2000 is not set
403# CONFIG_MTD_DOC2001 is not set
404# CONFIG_MTD_DOC2001PLUS is not set
405
406#
407# NAND Flash Device Drivers
408#
409# CONFIG_MTD_NAND is not set
196 410
197# 411#
198# Parallel port support 412# Parallel port support
@@ -206,7 +420,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
206# 420#
207# Block devices 421# Block devices
208# 422#
209# CONFIG_BLK_DEV_FD is not set
210# CONFIG_BLK_CPQ_DA is not set 423# CONFIG_BLK_CPQ_DA is not set
211# CONFIG_BLK_CPQ_CISS_DA is not set 424# CONFIG_BLK_CPQ_CISS_DA is not set
212# CONFIG_BLK_DEV_DAC960 is not set 425# CONFIG_BLK_DEV_DAC960 is not set
@@ -218,7 +431,6 @@ CONFIG_BLK_DEV_LOOP=y
218# CONFIG_BLK_DEV_SX8 is not set 431# CONFIG_BLK_DEV_SX8 is not set
219# CONFIG_BLK_DEV_RAM is not set 432# CONFIG_BLK_DEV_RAM is not set
220CONFIG_BLK_DEV_RAM_COUNT=16 433CONFIG_BLK_DEV_RAM_COUNT=16
221CONFIG_INITRAMFS_SOURCE=""
222# CONFIG_LBD is not set 434# CONFIG_LBD is not set
223CONFIG_CDROM_PKTCDVD=m 435CONFIG_CDROM_PKTCDVD=m
224CONFIG_CDROM_PKTCDVD_BUFFERS=8 436CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -275,6 +487,7 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
275CONFIG_BLK_DEV_HPT366=y 487CONFIG_BLK_DEV_HPT366=y
276# CONFIG_BLK_DEV_SC1200 is not set 488# CONFIG_BLK_DEV_SC1200 is not set
277# CONFIG_BLK_DEV_PIIX is not set 489# CONFIG_BLK_DEV_PIIX is not set
490# CONFIG_BLK_DEV_IT821X is not set
278# CONFIG_BLK_DEV_NS87415 is not set 491# CONFIG_BLK_DEV_NS87415 is not set
279# CONFIG_BLK_DEV_PDC202XX_OLD is not set 492# CONFIG_BLK_DEV_PDC202XX_OLD is not set
280# CONFIG_BLK_DEV_PDC202XX_NEW is not set 493# CONFIG_BLK_DEV_PDC202XX_NEW is not set
@@ -292,6 +505,7 @@ CONFIG_BLK_DEV_IDEDMA=y
292# 505#
293# SCSI device support 506# SCSI device support
294# 507#
508CONFIG_RAID_ATTRS=m
295# CONFIG_SCSI is not set 509# CONFIG_SCSI is not set
296 510
297# 511#
@@ -302,6 +516,7 @@ CONFIG_BLK_DEV_IDEDMA=y
302# 516#
303# Fusion MPT device support 517# Fusion MPT device support
304# 518#
519# CONFIG_FUSION is not set
305 520
306# 521#
307# IEEE 1394 (FireWire) support 522# IEEE 1394 (FireWire) support
@@ -314,94 +529,13 @@ CONFIG_BLK_DEV_IDEDMA=y
314# CONFIG_I2O is not set 529# CONFIG_I2O is not set
315 530
316# 531#
317# Networking support 532# Network device support
318#
319CONFIG_NET=y
320
321#
322# Networking options
323#
324CONFIG_PACKET=y
325# CONFIG_PACKET_MMAP is not set
326CONFIG_NETLINK_DEV=y
327CONFIG_UNIX=y
328CONFIG_NET_KEY=y
329CONFIG_INET=y
330CONFIG_IP_MULTICAST=y
331# CONFIG_IP_ADVANCED_ROUTER is not set
332CONFIG_IP_PNP=y
333# CONFIG_IP_PNP_DHCP is not set
334CONFIG_IP_PNP_BOOTP=y
335# CONFIG_IP_PNP_RARP is not set
336# CONFIG_NET_IPIP is not set
337# CONFIG_NET_IPGRE is not set
338# CONFIG_IP_MROUTE is not set
339# CONFIG_ARPD is not set
340# CONFIG_SYN_COOKIES is not set
341# CONFIG_INET_AH is not set
342# CONFIG_INET_ESP is not set
343# CONFIG_INET_IPCOMP is not set
344CONFIG_INET_TUNNEL=m
345CONFIG_IP_TCPDIAG=m
346# CONFIG_IP_TCPDIAG_IPV6 is not set
347
348#
349# IP: Virtual Server Configuration
350#
351# CONFIG_IP_VS is not set
352# CONFIG_IPV6 is not set
353CONFIG_NETFILTER=y
354# CONFIG_NETFILTER_DEBUG is not set
355
356#
357# IP: Netfilter Configuration
358# 533#
359# CONFIG_IP_NF_CONNTRACK is not set
360CONFIG_IP_NF_CONNTRACK_MARK=y
361# CONFIG_IP_NF_QUEUE is not set
362# CONFIG_IP_NF_IPTABLES is not set
363# CONFIG_IP_NF_ARPTABLES is not set
364CONFIG_XFRM=y
365CONFIG_XFRM_USER=m
366
367#
368# SCTP Configuration (EXPERIMENTAL)
369#
370# CONFIG_IP_SCTP is not set
371# CONFIG_ATM is not set
372# CONFIG_BRIDGE is not set
373# CONFIG_VLAN_8021Q is not set
374# CONFIG_DECNET is not set
375# CONFIG_LLC2 is not set
376# CONFIG_IPX is not set
377# CONFIG_ATALK is not set
378# CONFIG_X25 is not set
379# CONFIG_LAPB is not set
380# CONFIG_NET_DIVERT is not set
381# CONFIG_ECONET is not set
382# CONFIG_WAN_ROUTER is not set
383
384#
385# QoS and/or fair queueing
386#
387# CONFIG_NET_SCHED is not set
388# CONFIG_NET_CLS_ROUTE is not set
389
390#
391# Network testing
392#
393# CONFIG_NET_PKTGEN is not set
394# CONFIG_NETPOLL is not set
395# CONFIG_NET_POLL_CONTROLLER is not set
396# CONFIG_HAMRADIO is not set
397# CONFIG_IRDA is not set
398# CONFIG_BT is not set
399CONFIG_NETDEVICES=y 534CONFIG_NETDEVICES=y
400# CONFIG_DUMMY is not set 535# CONFIG_DUMMY is not set
401# CONFIG_BONDING is not set 536# CONFIG_BONDING is not set
402# CONFIG_EQUALIZER is not set 537# CONFIG_EQUALIZER is not set
403# CONFIG_TUN is not set 538# CONFIG_TUN is not set
404# CONFIG_ETHERTAP is not set
405 539
406# 540#
407# ARCnet devices 541# ARCnet devices
@@ -409,6 +543,21 @@ CONFIG_NETDEVICES=y
409# CONFIG_ARCNET is not set 543# CONFIG_ARCNET is not set
410 544
411# 545#
546# PHY device support
547#
548CONFIG_PHYLIB=m
549CONFIG_PHYCONTROL=y
550
551#
552# MII PHY device drivers
553#
554CONFIG_MARVELL_PHY=m
555CONFIG_DAVICOM_PHY=m
556CONFIG_QSEMI_PHY=m
557CONFIG_LXT_PHY=m
558CONFIG_CICADA_PHY=m
559
560#
412# Ethernet (10 or 100Mbit) 561# Ethernet (10 or 100Mbit)
413# 562#
414CONFIG_NET_ETHERNET=y 563CONFIG_NET_ETHERNET=y
@@ -435,12 +584,16 @@ CONFIG_MIPS_AU1X00_ENET=y
435# CONFIG_HAMACHI is not set 584# CONFIG_HAMACHI is not set
436# CONFIG_YELLOWFIN is not set 585# CONFIG_YELLOWFIN is not set
437# CONFIG_R8169 is not set 586# CONFIG_R8169 is not set
587# CONFIG_SIS190 is not set
588# CONFIG_SKGE is not set
438# CONFIG_SK98LIN is not set 589# CONFIG_SK98LIN is not set
439# CONFIG_TIGON3 is not set 590# CONFIG_TIGON3 is not set
591# CONFIG_BNX2 is not set
440 592
441# 593#
442# Ethernet (10000 Mbit) 594# Ethernet (10000 Mbit)
443# 595#
596# CONFIG_CHELSIO_T1 is not set
444# CONFIG_IXGB is not set 597# CONFIG_IXGB is not set
445# CONFIG_S2IO is not set 598# CONFIG_S2IO is not set
446 599
@@ -453,6 +606,8 @@ CONFIG_MIPS_AU1X00_ENET=y
453# Wireless LAN (non-hamradio) 606# Wireless LAN (non-hamradio)
454# 607#
455# CONFIG_NET_RADIO is not set 608# CONFIG_NET_RADIO is not set
609# CONFIG_IPW_DEBUG is not set
610CONFIG_IPW2200=m
456 611
457# 612#
458# PCMCIA network device support 613# PCMCIA network device support
@@ -476,6 +631,8 @@ CONFIG_PPPOE=m
476# CONFIG_SLIP is not set 631# CONFIG_SLIP is not set
477# CONFIG_SHAPER is not set 632# CONFIG_SHAPER is not set
478# CONFIG_NETCONSOLE is not set 633# CONFIG_NETCONSOLE is not set
634# CONFIG_NETPOLL is not set
635# CONFIG_NET_POLL_CONTROLLER is not set
479 636
480# 637#
481# ISDN subsystem 638# ISDN subsystem
@@ -505,19 +662,6 @@ CONFIG_INPUT_EVDEV=y
505# CONFIG_INPUT_EVBUG is not set 662# CONFIG_INPUT_EVBUG is not set
506 663
507# 664#
508# Input I/O drivers
509#
510# CONFIG_GAMEPORT is not set
511CONFIG_SOUND_GAMEPORT=y
512CONFIG_SERIO=y
513# CONFIG_SERIO_I8042 is not set
514CONFIG_SERIO_SERPORT=y
515# CONFIG_SERIO_CT82C710 is not set
516# CONFIG_SERIO_PCIPS2 is not set
517# CONFIG_SERIO_LIBPS2 is not set
518CONFIG_SERIO_RAW=m
519
520#
521# Input Device Drivers 665# Input Device Drivers
522# 666#
523# CONFIG_INPUT_KEYBOARD is not set 667# CONFIG_INPUT_KEYBOARD is not set
@@ -527,6 +671,17 @@ CONFIG_SERIO_RAW=m
527# CONFIG_INPUT_MISC is not set 671# CONFIG_INPUT_MISC is not set
528 672
529# 673#
674# Hardware I/O ports
675#
676CONFIG_SERIO=y
677# CONFIG_SERIO_I8042 is not set
678CONFIG_SERIO_SERPORT=y
679# CONFIG_SERIO_PCIPS2 is not set
680# CONFIG_SERIO_LIBPS2 is not set
681CONFIG_SERIO_RAW=m
682# CONFIG_GAMEPORT is not set
683
684#
530# Character devices 685# Character devices
531# 686#
532# CONFIG_VT is not set 687# CONFIG_VT is not set
@@ -546,6 +701,7 @@ CONFIG_SERIAL_AU1X00=y
546CONFIG_SERIAL_AU1X00_CONSOLE=y 701CONFIG_SERIAL_AU1X00_CONSOLE=y
547CONFIG_SERIAL_CORE=y 702CONFIG_SERIAL_CORE=y
548CONFIG_SERIAL_CORE_CONSOLE=y 703CONFIG_SERIAL_CORE_CONSOLE=y
704# CONFIG_SERIAL_JSM is not set
549CONFIG_UNIX98_PTYS=y 705CONFIG_UNIX98_PTYS=y
550CONFIG_LEGACY_PTYS=y 706CONFIG_LEGACY_PTYS=y
551CONFIG_LEGACY_PTY_COUNT=256 707CONFIG_LEGACY_PTY_COUNT=256
@@ -577,6 +733,11 @@ CONFIG_SYNCLINK_CS=m
577# CONFIG_RAW_DRIVER is not set 733# CONFIG_RAW_DRIVER is not set
578 734
579# 735#
736# TPM devices
737#
738# CONFIG_TCG_TPM is not set
739
740#
580# I2C support 741# I2C support
581# 742#
582# CONFIG_I2C is not set 743# CONFIG_I2C is not set
@@ -587,10 +748,20 @@ CONFIG_SYNCLINK_CS=m
587# CONFIG_W1 is not set 748# CONFIG_W1 is not set
588 749
589# 750#
751# Hardware Monitoring support
752#
753# CONFIG_HWMON is not set
754# CONFIG_HWMON_VID is not set
755
756#
590# Misc devices 757# Misc devices
591# 758#
592 759
593# 760#
761# Multimedia Capabilities Port drivers
762#
763
764#
594# Multimedia devices 765# Multimedia devices
595# 766#
596# CONFIG_VIDEO_DEV is not set 767# CONFIG_VIDEO_DEV is not set
@@ -604,7 +775,6 @@ CONFIG_SYNCLINK_CS=m
604# Graphics support 775# Graphics support
605# 776#
606# CONFIG_FB is not set 777# CONFIG_FB is not set
607# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
608 778
609# 779#
610# Sound 780# Sound
@@ -614,13 +784,9 @@ CONFIG_SYNCLINK_CS=m
614# 784#
615# USB support 785# USB support
616# 786#
617# CONFIG_USB is not set
618CONFIG_USB_ARCH_HAS_HCD=y 787CONFIG_USB_ARCH_HAS_HCD=y
619CONFIG_USB_ARCH_HAS_OHCI=y 788CONFIG_USB_ARCH_HAS_OHCI=y
620 789# CONFIG_USB is not set
621#
622# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
623#
624 790
625# 791#
626# USB Gadget Support 792# USB Gadget Support
@@ -638,12 +804,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y
638# CONFIG_INFINIBAND is not set 804# CONFIG_INFINIBAND is not set
639 805
640# 806#
807# SN Devices
808#
809
810#
641# File systems 811# File systems
642# 812#
643CONFIG_EXT2_FS=y 813CONFIG_EXT2_FS=y
644CONFIG_EXT2_FS_XATTR=y 814CONFIG_EXT2_FS_XATTR=y
645CONFIG_EXT2_FS_POSIX_ACL=y 815CONFIG_EXT2_FS_POSIX_ACL=y
646# CONFIG_EXT2_FS_SECURITY is not set 816# CONFIG_EXT2_FS_SECURITY is not set
817# CONFIG_EXT2_FS_XIP is not set
647CONFIG_EXT3_FS=y 818CONFIG_EXT3_FS=y
648CONFIG_EXT3_FS_XATTR=y 819CONFIG_EXT3_FS_XATTR=y
649CONFIG_EXT3_FS_POSIX_ACL=y 820CONFIG_EXT3_FS_POSIX_ACL=y
@@ -662,10 +833,12 @@ CONFIG_FS_POSIX_ACL=y
662# CONFIG_XFS_FS is not set 833# CONFIG_XFS_FS is not set
663# CONFIG_MINIX_FS is not set 834# CONFIG_MINIX_FS is not set
664# CONFIG_ROMFS_FS is not set 835# CONFIG_ROMFS_FS is not set
836CONFIG_INOTIFY=y
665# CONFIG_QUOTA is not set 837# CONFIG_QUOTA is not set
666CONFIG_DNOTIFY=y 838CONFIG_DNOTIFY=y
667CONFIG_AUTOFS_FS=m 839CONFIG_AUTOFS_FS=m
668CONFIG_AUTOFS4_FS=m 840CONFIG_AUTOFS4_FS=m
841CONFIG_FUSE_FS=m
669 842
670# 843#
671# CD-ROM/DVD Filesystems 844# CD-ROM/DVD Filesystems
@@ -686,13 +859,10 @@ CONFIG_AUTOFS4_FS=m
686CONFIG_PROC_FS=y 859CONFIG_PROC_FS=y
687CONFIG_PROC_KCORE=y 860CONFIG_PROC_KCORE=y
688CONFIG_SYSFS=y 861CONFIG_SYSFS=y
689# CONFIG_DEVFS_FS is not set
690CONFIG_DEVPTS_FS_XATTR=y
691CONFIG_DEVPTS_FS_SECURITY=y
692CONFIG_TMPFS=y 862CONFIG_TMPFS=y
693# CONFIG_TMPFS_XATTR is not set
694# CONFIG_HUGETLB_PAGE is not set 863# CONFIG_HUGETLB_PAGE is not set
695CONFIG_RAMFS=y 864CONFIG_RAMFS=y
865CONFIG_RELAYFS_FS=m
696 866
697# 867#
698# Miscellaneous filesystems 868# Miscellaneous filesystems
@@ -704,6 +874,8 @@ CONFIG_RAMFS=y
704# CONFIG_BEFS_FS is not set 874# CONFIG_BEFS_FS is not set
705# CONFIG_BFS_FS is not set 875# CONFIG_BFS_FS is not set
706# CONFIG_EFS_FS is not set 876# CONFIG_EFS_FS is not set
877# CONFIG_JFFS_FS is not set
878# CONFIG_JFFS2_FS is not set
707CONFIG_CRAMFS=m 879CONFIG_CRAMFS=m
708# CONFIG_VXFS_FS is not set 880# CONFIG_VXFS_FS is not set
709# CONFIG_HPFS_FS is not set 881# CONFIG_HPFS_FS is not set
@@ -724,6 +896,7 @@ CONFIG_NFSD=m
724CONFIG_ROOT_NFS=y 896CONFIG_ROOT_NFS=y
725CONFIG_LOCKD=y 897CONFIG_LOCKD=y
726CONFIG_EXPORTFS=m 898CONFIG_EXPORTFS=m
899CONFIG_NFS_COMMON=y
727CONFIG_SUNRPC=y 900CONFIG_SUNRPC=y
728# CONFIG_RPCSEC_GSS_KRB5 is not set 901# CONFIG_RPCSEC_GSS_KRB5 is not set
729# CONFIG_RPCSEC_GSS_SPKM3 is not set 902# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -733,6 +906,7 @@ CONFIG_SMB_FS=m
733# CONFIG_NCP_FS is not set 906# CONFIG_NCP_FS is not set
734# CONFIG_CODA_FS is not set 907# CONFIG_CODA_FS is not set
735# CONFIG_AFS_FS is not set 908# CONFIG_AFS_FS is not set
909# CONFIG_9P_FS is not set
736 910
737# 911#
738# Partition Types 912# Partition Types
@@ -792,7 +966,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
792# 966#
793# Kernel hacking 967# Kernel hacking
794# 968#
969# CONFIG_PRINTK_TIME is not set
795# CONFIG_DEBUG_KERNEL is not set 970# CONFIG_DEBUG_KERNEL is not set
971CONFIG_LOG_BUF_SHIFT=14
796CONFIG_CROSSCOMPILE=y 972CONFIG_CROSSCOMPILE=y
797CONFIG_CMDLINE="" 973CONFIG_CMDLINE=""
798 974
@@ -808,26 +984,27 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
808# 984#
809CONFIG_CRYPTO=y 985CONFIG_CRYPTO=y
810CONFIG_CRYPTO_HMAC=y 986CONFIG_CRYPTO_HMAC=y
811CONFIG_CRYPTO_NULL=y 987CONFIG_CRYPTO_NULL=m
812# CONFIG_CRYPTO_MD4 is not set 988CONFIG_CRYPTO_MD4=m
813# CONFIG_CRYPTO_MD5 is not set 989CONFIG_CRYPTO_MD5=m
814# CONFIG_CRYPTO_SHA1 is not set 990CONFIG_CRYPTO_SHA1=m
815# CONFIG_CRYPTO_SHA256 is not set 991CONFIG_CRYPTO_SHA256=m
816CONFIG_CRYPTO_SHA512=y 992CONFIG_CRYPTO_SHA512=m
817CONFIG_CRYPTO_WP512=m 993CONFIG_CRYPTO_WP512=m
818# CONFIG_CRYPTO_DES is not set 994CONFIG_CRYPTO_TGR192=m
819# CONFIG_CRYPTO_BLOWFISH is not set 995CONFIG_CRYPTO_DES=m
820CONFIG_CRYPTO_TWOFISH=y 996CONFIG_CRYPTO_BLOWFISH=m
821# CONFIG_CRYPTO_SERPENT is not set 997CONFIG_CRYPTO_TWOFISH=m
998CONFIG_CRYPTO_SERPENT=m
822CONFIG_CRYPTO_AES=m 999CONFIG_CRYPTO_AES=m
823# CONFIG_CRYPTO_CAST5 is not set 1000CONFIG_CRYPTO_CAST5=m
824# CONFIG_CRYPTO_CAST6 is not set 1001CONFIG_CRYPTO_CAST6=m
825CONFIG_CRYPTO_TEA=m 1002CONFIG_CRYPTO_TEA=m
826# CONFIG_CRYPTO_ARC4 is not set 1003CONFIG_CRYPTO_ARC4=m
827CONFIG_CRYPTO_KHAZAD=m 1004CONFIG_CRYPTO_KHAZAD=m
828CONFIG_CRYPTO_ANUBIS=m 1005CONFIG_CRYPTO_ANUBIS=m
829CONFIG_CRYPTO_DEFLATE=y 1006CONFIG_CRYPTO_DEFLATE=m
830CONFIG_CRYPTO_MICHAEL_MIC=y 1007CONFIG_CRYPTO_MICHAEL_MIC=m
831CONFIG_CRYPTO_CRC32C=m 1008CONFIG_CRYPTO_CRC32C=m
832# CONFIG_CRYPTO_TEST is not set 1009# CONFIG_CRYPTO_TEST is not set
833 1010
@@ -839,9 +1016,8 @@ CONFIG_CRYPTO_CRC32C=m
839# Library routines 1016# Library routines
840# 1017#
841CONFIG_CRC_CCITT=m 1018CONFIG_CRC_CCITT=m
1019CONFIG_CRC16=m
842CONFIG_CRC32=y 1020CONFIG_CRC32=y
843CONFIG_LIBCRC32C=m 1021CONFIG_LIBCRC32C=m
844CONFIG_ZLIB_INFLATE=y 1022CONFIG_ZLIB_INFLATE=m
845CONFIG_ZLIB_DEFLATE=y 1023CONFIG_ZLIB_DEFLATE=m
846CONFIG_GENERIC_HARDIRQS=y
847CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
new file mode 100644
index 000000000000..95f84d711912
--- /dev/null
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -0,0 +1,1069 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.14-rc2
4# Thu Oct 20 22:26:50 2005
5#
6CONFIG_MIPS=y
7
8#
9# Code maturity level options
10#
11CONFIG_EXPERIMENTAL=y
12CONFIG_CLEAN_COMPILE=y
13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
15
16#
17# General setup
18#
19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
21CONFIG_SWAP=y
22CONFIG_SYSVIPC=y
23# CONFIG_POSIX_MQUEUE is not set
24# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set
27# CONFIG_HOTPLUG is not set
28CONFIG_KOBJECT_UEVENT=y
29CONFIG_IKCONFIG=y
30CONFIG_IKCONFIG_PROC=y
31CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_ALL is not set
35# CONFIG_KALLSYMS_EXTRA_PASS is not set
36CONFIG_PRINTK=y
37CONFIG_BUG=y
38CONFIG_BASE_FULL=y
39CONFIG_FUTEX=y
40CONFIG_EPOLL=y
41# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
42CONFIG_SHMEM=y
43CONFIG_CC_ALIGN_FUNCTIONS=0
44CONFIG_CC_ALIGN_LABELS=0
45CONFIG_CC_ALIGN_LOOPS=0
46CONFIG_CC_ALIGN_JUMPS=0
47# CONFIG_TINY_SHMEM is not set
48CONFIG_BASE_SMALL=0
49
50#
51# Loadable module support
52#
53CONFIG_MODULES=y
54# CONFIG_MODULE_UNLOAD is not set
55CONFIG_OBSOLETE_MODPARM=y
56# CONFIG_MODVERSIONS is not set
57# CONFIG_MODULE_SRCVERSION_ALL is not set
58CONFIG_KMOD=y
59
60#
61# Machine selection
62#
63# CONFIG_MIPS_MTX1 is not set
64# CONFIG_MIPS_BOSPORUS is not set
65# CONFIG_MIPS_PB1000 is not set
66# CONFIG_MIPS_PB1100 is not set
67# CONFIG_MIPS_PB1500 is not set
68# CONFIG_MIPS_PB1550 is not set
69# CONFIG_MIPS_PB1200 is not set
70# CONFIG_MIPS_DB1000 is not set
71# CONFIG_MIPS_DB1100 is not set
72# CONFIG_MIPS_DB1500 is not set
73# CONFIG_MIPS_DB1550 is not set
74# CONFIG_MIPS_DB1200 is not set
75# CONFIG_MIPS_MIRAGE is not set
76# CONFIG_MIPS_COBALT is not set
77# CONFIG_MACH_DECSTATION is not set
78# CONFIG_MIPS_EV64120 is not set
79# CONFIG_MIPS_EV96100 is not set
80# CONFIG_MIPS_IVR is not set
81# CONFIG_MIPS_ITE8172 is not set
82# CONFIG_MACH_JAZZ is not set
83# CONFIG_LASAT is not set
84# CONFIG_MIPS_ATLAS is not set
85# CONFIG_MIPS_MALTA is not set
86# CONFIG_MIPS_SEAD is not set
87# CONFIG_MIPS_SIM is not set
88# CONFIG_MOMENCO_JAGUAR_ATX is not set
89# CONFIG_MOMENCO_OCELOT is not set
90# CONFIG_MOMENCO_OCELOT_3 is not set
91# CONFIG_MOMENCO_OCELOT_C is not set
92# CONFIG_MOMENCO_OCELOT_G is not set
93# CONFIG_MIPS_XXS1500 is not set
94# CONFIG_PNX8550_V2PCI is not set
95CONFIG_PNX8550_JBS=y
96# CONFIG_DDB5074 is not set
97# CONFIG_DDB5476 is not set
98# CONFIG_DDB5477 is not set
99# CONFIG_MACH_VR41XX is not set
100# CONFIG_PMC_YOSEMITE is not set
101# CONFIG_QEMU is not set
102# CONFIG_SGI_IP22 is not set
103# CONFIG_SGI_IP27 is not set
104# CONFIG_SGI_IP32 is not set
105# CONFIG_SIBYTE_BIGSUR is not set
106# CONFIG_SIBYTE_SWARM is not set
107# CONFIG_SIBYTE_SENTOSA is not set
108# CONFIG_SIBYTE_RHONE is not set
109# CONFIG_SIBYTE_CARMEL is not set
110# CONFIG_SIBYTE_PTSWARM is not set
111# CONFIG_SIBYTE_LITTLESUR is not set
112# CONFIG_SIBYTE_CRHINE is not set
113# CONFIG_SIBYTE_CRHONE is not set
114# CONFIG_SNI_RM200_PCI is not set
115# CONFIG_TOSHIBA_JMR3927 is not set
116# CONFIG_TOSHIBA_RBTX4927 is not set
117# CONFIG_TOSHIBA_RBTX4938 is not set
118CONFIG_RWSEM_GENERIC_SPINLOCK=y
119CONFIG_GENERIC_CALIBRATE_DELAY=y
120CONFIG_DMA_NONCOHERENT=y
121CONFIG_DMA_NEED_PCI_MAP_STATE=y
122# CONFIG_CPU_BIG_ENDIAN is not set
123CONFIG_CPU_LITTLE_ENDIAN=y
124CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
125CONFIG_PNX8550=y
126CONFIG_SOC_PNX8550=y
127CONFIG_MIPS_L1_CACHE_SHIFT=5
128
129#
130# CPU selection
131#
132# CONFIG_CPU_MIPS32_R1 is not set
133# CONFIG_CPU_MIPS32_R2 is not set
134# CONFIG_CPU_MIPS64_R1 is not set
135# CONFIG_CPU_MIPS64_R2 is not set
136# CONFIG_CPU_R3000 is not set
137# CONFIG_CPU_TX39XX is not set
138# CONFIG_CPU_VR41XX is not set
139# CONFIG_CPU_R4300 is not set
140CONFIG_CPU_R4X00=y
141# CONFIG_CPU_TX49XX is not set
142# CONFIG_CPU_R5000 is not set
143# CONFIG_CPU_R5432 is not set
144# CONFIG_CPU_R6000 is not set
145# CONFIG_CPU_NEVADA is not set
146# CONFIG_CPU_R8000 is not set
147# CONFIG_CPU_R10000 is not set
148# CONFIG_CPU_RM7000 is not set
149# CONFIG_CPU_RM9000 is not set
150# CONFIG_CPU_SB1 is not set
151CONFIG_SYS_HAS_CPU_R4X00=y
152CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
153CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
154CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
155
156#
157# Kernel type
158#
159CONFIG_32BIT=y
160# CONFIG_64BIT is not set
161CONFIG_PAGE_SIZE_4KB=y
162# CONFIG_PAGE_SIZE_8KB is not set
163# CONFIG_PAGE_SIZE_16KB is not set
164# CONFIG_PAGE_SIZE_64KB is not set
165# CONFIG_MIPS_MT is not set
166# CONFIG_64BIT_PHYS_ADDR is not set
167# CONFIG_CPU_ADVANCED is not set
168CONFIG_CPU_HAS_LLSC=y
169CONFIG_CPU_HAS_LLDSCD=y
170CONFIG_CPU_HAS_SYNC=y
171CONFIG_GENERIC_HARDIRQS=y
172CONFIG_GENERIC_IRQ_PROBE=y
173CONFIG_ARCH_FLATMEM_ENABLE=y
174CONFIG_SELECT_MEMORY_MODEL=y
175CONFIG_FLATMEM_MANUAL=y
176# CONFIG_DISCONTIGMEM_MANUAL is not set
177# CONFIG_SPARSEMEM_MANUAL is not set
178CONFIG_FLATMEM=y
179CONFIG_FLAT_NODE_MEM_MAP=y
180# CONFIG_SPARSEMEM_STATIC is not set
181CONFIG_PREEMPT_NONE=y
182# CONFIG_PREEMPT_VOLUNTARY is not set
183# CONFIG_PREEMPT is not set
184
185#
186# Bus options (PCI, PCMCIA, EISA, ISA, TC)
187#
188CONFIG_HW_HAS_PCI=y
189CONFIG_PCI=y
190# CONFIG_PCI_LEGACY_PROC is not set
191# CONFIG_PCI_DEBUG is not set
192CONFIG_MMU=y
193
194#
195# PCCARD (PCMCIA/CardBus) support
196#
197# CONFIG_PCCARD is not set
198
199#
200# PCI Hotplug Support
201#
202# CONFIG_HOTPLUG_PCI is not set
203
204#
205# Executable file formats
206#
207CONFIG_BINFMT_ELF=y
208# CONFIG_BINFMT_MISC is not set
209CONFIG_TRAD_SIGNALS=y
210
211#
212# Networking
213#
214CONFIG_NET=y
215
216#
217# Networking options
218#
219CONFIG_PACKET=y
220# CONFIG_PACKET_MMAP is not set
221CONFIG_UNIX=y
222# CONFIG_NET_KEY is not set
223CONFIG_INET=y
224# CONFIG_IP_MULTICAST is not set
225# CONFIG_IP_ADVANCED_ROUTER is not set
226CONFIG_IP_FIB_HASH=y
227CONFIG_IP_PNP=y
228CONFIG_IP_PNP_DHCP=y
229CONFIG_IP_PNP_BOOTP=y
230# CONFIG_IP_PNP_RARP is not set
231# CONFIG_NET_IPIP is not set
232# CONFIG_NET_IPGRE is not set
233# CONFIG_ARPD is not set
234# CONFIG_SYN_COOKIES is not set
235# CONFIG_INET_AH is not set
236# CONFIG_INET_ESP is not set
237# CONFIG_INET_IPCOMP is not set
238# CONFIG_INET_TUNNEL is not set
239CONFIG_INET_DIAG=y
240CONFIG_INET_TCP_DIAG=y
241# CONFIG_TCP_CONG_ADVANCED is not set
242CONFIG_TCP_CONG_BIC=y
243# CONFIG_IPV6 is not set
244# CONFIG_NETFILTER is not set
245
246#
247# DCCP Configuration (EXPERIMENTAL)
248#
249# CONFIG_IP_DCCP is not set
250
251#
252# SCTP Configuration (EXPERIMENTAL)
253#
254# CONFIG_IP_SCTP is not set
255# CONFIG_ATM is not set
256# CONFIG_BRIDGE is not set
257# CONFIG_VLAN_8021Q is not set
258# CONFIG_DECNET is not set
259# CONFIG_LLC2 is not set
260# CONFIG_IPX is not set
261# CONFIG_ATALK is not set
262# CONFIG_X25 is not set
263# CONFIG_LAPB is not set
264# CONFIG_NET_DIVERT is not set
265# CONFIG_ECONET is not set
266# CONFIG_WAN_ROUTER is not set
267# CONFIG_NET_SCHED is not set
268# CONFIG_NET_CLS_ROUTE is not set
269
270#
271# Network testing
272#
273# CONFIG_NET_PKTGEN is not set
274# CONFIG_HAMRADIO is not set
275# CONFIG_IRDA is not set
276# CONFIG_BT is not set
277# CONFIG_IEEE80211 is not set
278
279#
280# Device Drivers
281#
282
283#
284# Generic Driver Options
285#
286CONFIG_STANDALONE=y
287CONFIG_PREVENT_FIRMWARE_BUILD=y
288# CONFIG_FW_LOADER is not set
289# CONFIG_DEBUG_DRIVER is not set
290
291#
292# Connector - unified userspace <-> kernelspace linker
293#
294# CONFIG_CONNECTOR is not set
295
296#
297# Memory Technology Devices (MTD)
298#
299# CONFIG_MTD is not set
300
301#
302# Parallel port support
303#
304# CONFIG_PARPORT is not set
305
306#
307# Plug and Play support
308#
309
310#
311# Block devices
312#
313# CONFIG_BLK_CPQ_DA is not set
314# CONFIG_BLK_CPQ_CISS_DA is not set
315# CONFIG_BLK_DEV_DAC960 is not set
316# CONFIG_BLK_DEV_UMEM is not set
317# CONFIG_BLK_DEV_COW_COMMON is not set
318CONFIG_BLK_DEV_LOOP=y
319# CONFIG_BLK_DEV_CRYPTOLOOP is not set
320# CONFIG_BLK_DEV_NBD is not set
321# CONFIG_BLK_DEV_SX8 is not set
322# CONFIG_BLK_DEV_UB is not set
323CONFIG_BLK_DEV_RAM=y
324CONFIG_BLK_DEV_RAM_COUNT=16
325CONFIG_BLK_DEV_RAM_SIZE=8192
326CONFIG_BLK_DEV_INITRD=y
327# CONFIG_LBD is not set
328# CONFIG_CDROM_PKTCDVD is not set
329
330#
331# IO Schedulers
332#
333CONFIG_IOSCHED_NOOP=y
334CONFIG_IOSCHED_AS=y
335CONFIG_IOSCHED_DEADLINE=y
336CONFIG_IOSCHED_CFQ=y
337# CONFIG_ATA_OVER_ETH is not set
338
339#
340# ATA/ATAPI/MFM/RLL support
341#
342CONFIG_IDE=y
343CONFIG_BLK_DEV_IDE=y
344
345#
346# Please see Documentation/ide.txt for help/info on IDE drives
347#
348# CONFIG_BLK_DEV_IDE_SATA is not set
349CONFIG_BLK_DEV_IDEDISK=y
350# CONFIG_IDEDISK_MULTI_MODE is not set
351CONFIG_BLK_DEV_IDECD=m
352# CONFIG_BLK_DEV_IDETAPE is not set
353# CONFIG_BLK_DEV_IDEFLOPPY is not set
354CONFIG_BLK_DEV_IDESCSI=y
355# CONFIG_IDE_TASK_IOCTL is not set
356
357#
358# IDE chipset support/bugfixes
359#
360CONFIG_IDE_GENERIC=y
361CONFIG_BLK_DEV_IDEPCI=y
362CONFIG_IDEPCI_SHARE_IRQ=y
363CONFIG_BLK_DEV_OFFBOARD=y
364CONFIG_BLK_DEV_GENERIC=y
365# CONFIG_BLK_DEV_OPTI621 is not set
366CONFIG_BLK_DEV_IDEDMA_PCI=y
367# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
368# CONFIG_IDEDMA_PCI_AUTO is not set
369# CONFIG_BLK_DEV_AEC62XX is not set
370# CONFIG_BLK_DEV_ALI15X3 is not set
371# CONFIG_BLK_DEV_AMD74XX is not set
372# CONFIG_BLK_DEV_CMD64X is not set
373# CONFIG_BLK_DEV_TRIFLEX is not set
374# CONFIG_BLK_DEV_CY82C693 is not set
375# CONFIG_BLK_DEV_CS5520 is not set
376# CONFIG_BLK_DEV_CS5530 is not set
377# CONFIG_BLK_DEV_HPT34X is not set
378CONFIG_BLK_DEV_HPT366=y
379# CONFIG_BLK_DEV_SC1200 is not set
380# CONFIG_BLK_DEV_PIIX is not set
381# CONFIG_BLK_DEV_IT821X is not set
382# CONFIG_BLK_DEV_NS87415 is not set
383# CONFIG_BLK_DEV_PDC202XX_OLD is not set
384# CONFIG_BLK_DEV_PDC202XX_NEW is not set
385# CONFIG_BLK_DEV_SVWKS is not set
386# CONFIG_BLK_DEV_SIIMAGE is not set
387# CONFIG_BLK_DEV_SLC90E66 is not set
388# CONFIG_BLK_DEV_TRM290 is not set
389# CONFIG_BLK_DEV_VIA82CXXX is not set
390# CONFIG_IDE_ARM is not set
391CONFIG_BLK_DEV_IDEDMA=y
392# CONFIG_IDEDMA_IVB is not set
393# CONFIG_IDEDMA_AUTO is not set
394# CONFIG_BLK_DEV_HD is not set
395
396#
397# SCSI device support
398#
399# CONFIG_RAID_ATTRS is not set
400CONFIG_SCSI=y
401CONFIG_SCSI_PROC_FS=y
402
403#
404# SCSI support type (disk, tape, CD-ROM)
405#
406CONFIG_BLK_DEV_SD=y
407# CONFIG_CHR_DEV_ST is not set
408# CONFIG_CHR_DEV_OSST is not set
409# CONFIG_BLK_DEV_SR is not set
410# CONFIG_CHR_DEV_SG is not set
411# CONFIG_CHR_DEV_SCH is not set
412
413#
414# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
415#
416# CONFIG_SCSI_MULTI_LUN is not set
417CONFIG_SCSI_CONSTANTS=y
418# CONFIG_SCSI_LOGGING is not set
419
420#
421# SCSI Transport Attributes
422#
423# CONFIG_SCSI_SPI_ATTRS is not set
424# CONFIG_SCSI_FC_ATTRS is not set
425# CONFIG_SCSI_ISCSI_ATTRS is not set
426# CONFIG_SCSI_SAS_ATTRS is not set
427
428#
429# SCSI low-level drivers
430#
431# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
432# CONFIG_SCSI_3W_9XXX is not set
433# CONFIG_SCSI_ACARD is not set
434# CONFIG_SCSI_AACRAID is not set
435# CONFIG_SCSI_AIC7XXX is not set
436# CONFIG_SCSI_AIC7XXX_OLD is not set
437# CONFIG_SCSI_AIC79XX is not set
438# CONFIG_SCSI_DPT_I2O is not set
439# CONFIG_MEGARAID_NEWGEN is not set
440# CONFIG_MEGARAID_LEGACY is not set
441# CONFIG_SCSI_SATA is not set
442# CONFIG_SCSI_DMX3191D is not set
443# CONFIG_SCSI_FUTURE_DOMAIN is not set
444# CONFIG_SCSI_IPS is not set
445# CONFIG_SCSI_INITIO is not set
446# CONFIG_SCSI_INIA100 is not set
447# CONFIG_SCSI_SYM53C8XX_2 is not set
448# CONFIG_SCSI_IPR is not set
449# CONFIG_SCSI_QLOGIC_FC is not set
450# CONFIG_SCSI_QLOGIC_1280 is not set
451CONFIG_SCSI_QLA2XXX=y
452# CONFIG_SCSI_QLA21XX is not set
453# CONFIG_SCSI_QLA22XX is not set
454# CONFIG_SCSI_QLA2300 is not set
455# CONFIG_SCSI_QLA2322 is not set
456# CONFIG_SCSI_QLA6312 is not set
457# CONFIG_SCSI_QLA24XX is not set
458# CONFIG_SCSI_LPFC is not set
459# CONFIG_SCSI_DC395x is not set
460# CONFIG_SCSI_DC390T is not set
461# CONFIG_SCSI_NSP32 is not set
462# CONFIG_SCSI_DEBUG is not set
463
464#
465# Multi-device support (RAID and LVM)
466#
467# CONFIG_MD is not set
468
469#
470# Fusion MPT device support
471#
472# CONFIG_FUSION is not set
473# CONFIG_FUSION_SPI is not set
474# CONFIG_FUSION_FC is not set
475
476#
477# IEEE 1394 (FireWire) support
478#
479# CONFIG_IEEE1394 is not set
480
481#
482# I2O device support
483#
484# CONFIG_I2O is not set
485
486#
487# Network device support
488#
489CONFIG_NETDEVICES=y
490# CONFIG_DUMMY is not set
491# CONFIG_BONDING is not set
492# CONFIG_EQUALIZER is not set
493# CONFIG_TUN is not set
494
495#
496# ARCnet devices
497#
498# CONFIG_ARCNET is not set
499
500#
501# PHY device support
502#
503# CONFIG_PHYLIB is not set
504
505#
506# Ethernet (10 or 100Mbit)
507#
508CONFIG_NET_ETHERNET=y
509CONFIG_MII=y
510# CONFIG_HAPPYMEAL is not set
511# CONFIG_SUNGEM is not set
512# CONFIG_NET_VENDOR_3COM is not set
513
514#
515# Tulip family network device support
516#
517# CONFIG_NET_TULIP is not set
518# CONFIG_HP100 is not set
519CONFIG_NET_PCI=y
520# CONFIG_PCNET32 is not set
521# CONFIG_AMD8111_ETH is not set
522# CONFIG_ADAPTEC_STARFIRE is not set
523# CONFIG_B44 is not set
524# CONFIG_FORCEDETH is not set
525# CONFIG_DGRS is not set
526# CONFIG_EEPRO100 is not set
527# CONFIG_E100 is not set
528# CONFIG_FEALNX is not set
529# CONFIG_NATSEMI is not set
530# CONFIG_NE2K_PCI is not set
531# CONFIG_8139CP is not set
532CONFIG_8139TOO=y
533# CONFIG_8139TOO_PIO is not set
534CONFIG_8139TOO_TUNE_TWISTER=y
535CONFIG_8139TOO_8129=y
536# CONFIG_8139_OLD_RX_RESET is not set
537# CONFIG_SIS900 is not set
538# CONFIG_EPIC100 is not set
539# CONFIG_SUNDANCE is not set
540# CONFIG_TLAN is not set
541# CONFIG_VIA_RHINE is not set
542# CONFIG_LAN_SAA9730 is not set
543
544#
545# Ethernet (1000 Mbit)
546#
547# CONFIG_ACENIC is not set
548# CONFIG_DL2K is not set
549# CONFIG_E1000 is not set
550# CONFIG_NS83820 is not set
551# CONFIG_HAMACHI is not set
552# CONFIG_YELLOWFIN is not set
553# CONFIG_R8169 is not set
554# CONFIG_SIS190 is not set
555# CONFIG_SKGE is not set
556# CONFIG_SK98LIN is not set
557# CONFIG_VIA_VELOCITY is not set
558# CONFIG_TIGON3 is not set
559# CONFIG_BNX2 is not set
560
561#
562# Ethernet (10000 Mbit)
563#
564# CONFIG_CHELSIO_T1 is not set
565# CONFIG_IXGB is not set
566# CONFIG_S2IO is not set
567
568#
569# Token Ring devices
570#
571# CONFIG_TR is not set
572
573#
574# Wireless LAN (non-hamradio)
575#
576# CONFIG_NET_RADIO is not set
577
578#
579# Wan interfaces
580#
581# CONFIG_WAN is not set
582# CONFIG_FDDI is not set
583# CONFIG_HIPPI is not set
584# CONFIG_PPP is not set
585# CONFIG_SLIP is not set
586# CONFIG_NET_FC is not set
587# CONFIG_SHAPER is not set
588# CONFIG_NETCONSOLE is not set
589# CONFIG_NETPOLL is not set
590# CONFIG_NET_POLL_CONTROLLER is not set
591
592#
593# ISDN subsystem
594#
595# CONFIG_ISDN is not set
596
597#
598# Telephony Support
599#
600# CONFIG_PHONE is not set
601
602#
603# Input device support
604#
605CONFIG_INPUT=y
606
607#
608# Userland interfaces
609#
610# CONFIG_INPUT_MOUSEDEV is not set
611# CONFIG_INPUT_JOYDEV is not set
612# CONFIG_INPUT_TSDEV is not set
613# CONFIG_INPUT_EVDEV is not set
614# CONFIG_INPUT_EVBUG is not set
615
616#
617# Input Device Drivers
618#
619# CONFIG_INPUT_KEYBOARD is not set
620# CONFIG_INPUT_MOUSE is not set
621# CONFIG_INPUT_JOYSTICK is not set
622# CONFIG_INPUT_TOUCHSCREEN is not set
623# CONFIG_INPUT_MISC is not set
624
625#
626# Hardware I/O ports
627#
628CONFIG_SERIO=y
629# CONFIG_SERIO_I8042 is not set
630# CONFIG_SERIO_SERPORT is not set
631# CONFIG_SERIO_PCIPS2 is not set
632CONFIG_SERIO_LIBPS2=y
633# CONFIG_SERIO_RAW is not set
634# CONFIG_GAMEPORT is not set
635
636#
637# Character devices
638#
639CONFIG_VT=y
640CONFIG_VT_CONSOLE=y
641CONFIG_HW_CONSOLE=y
642# CONFIG_SERIAL_NONSTANDARD is not set
643
644#
645# Serial drivers
646#
647# CONFIG_SERIAL_8250 is not set
648
649#
650# Non-8250 serial port support
651#
652# CONFIG_SERIAL_IP3106 is not set
653# CONFIG_SERIAL_JSM is not set
654CONFIG_UNIX98_PTYS=y
655CONFIG_LEGACY_PTYS=y
656CONFIG_LEGACY_PTY_COUNT=256
657
658#
659# IPMI
660#
661# CONFIG_IPMI_HANDLER is not set
662
663#
664# Watchdog Cards
665#
666# CONFIG_WATCHDOG is not set
667# CONFIG_RTC is not set
668# CONFIG_GEN_RTC is not set
669# CONFIG_DTLK is not set
670# CONFIG_R3964 is not set
671# CONFIG_APPLICOM is not set
672
673#
674# Ftape, the floppy tape device driver
675#
676# CONFIG_DRM is not set
677# CONFIG_RAW_DRIVER is not set
678
679#
680# TPM devices
681#
682# CONFIG_TCG_TPM is not set
683
684#
685# I2C support
686#
687# CONFIG_I2C is not set
688
689#
690# Dallas's 1-wire bus
691#
692# CONFIG_W1 is not set
693
694#
695# Hardware Monitoring support
696#
697CONFIG_HWMON=y
698# CONFIG_HWMON_VID is not set
699# CONFIG_HWMON_DEBUG_CHIP is not set
700
701#
702# Misc devices
703#
704
705#
706# Multimedia Capabilities Port drivers
707#
708
709#
710# Multimedia devices
711#
712# CONFIG_VIDEO_DEV is not set
713
714#
715# Digital Video Broadcasting Devices
716#
717# CONFIG_DVB is not set
718
719#
720# Graphics support
721#
722# CONFIG_FB is not set
723
724#
725# Console display driver support
726#
727# CONFIG_VGA_CONSOLE is not set
728CONFIG_DUMMY_CONSOLE=y
729
730#
731# Sound
732#
733# CONFIG_SOUND is not set
734
735#
736# USB support
737#
738CONFIG_USB_ARCH_HAS_HCD=y
739CONFIG_USB_ARCH_HAS_OHCI=y
740CONFIG_USB=y
741# CONFIG_USB_DEBUG is not set
742
743#
744# Miscellaneous USB options
745#
746# CONFIG_USB_DEVICEFS is not set
747# CONFIG_USB_BANDWIDTH is not set
748# CONFIG_USB_DYNAMIC_MINORS is not set
749# CONFIG_USB_OTG is not set
750
751#
752# USB Host Controller Drivers
753#
754# CONFIG_USB_EHCI_HCD is not set
755# CONFIG_USB_ISP116X_HCD is not set
756CONFIG_USB_OHCI_HCD=y
757# CONFIG_USB_OHCI_BIG_ENDIAN is not set
758CONFIG_USB_OHCI_LITTLE_ENDIAN=y
759# CONFIG_USB_UHCI_HCD is not set
760# CONFIG_USB_SL811_HCD is not set
761
762#
763# USB Device Class drivers
764#
765# CONFIG_USB_BLUETOOTH_TTY is not set
766# CONFIG_USB_ACM is not set
767# CONFIG_USB_PRINTER is not set
768
769#
770# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
771#
772CONFIG_USB_STORAGE=y
773# CONFIG_USB_STORAGE_DEBUG is not set
774CONFIG_USB_STORAGE_DATAFAB=y
775CONFIG_USB_STORAGE_FREECOM=y
776CONFIG_USB_STORAGE_ISD200=y
777CONFIG_USB_STORAGE_DPCM=y
778CONFIG_USB_STORAGE_USBAT=y
779CONFIG_USB_STORAGE_SDDR09=y
780CONFIG_USB_STORAGE_SDDR55=y
781CONFIG_USB_STORAGE_JUMPSHOT=y
782
783#
784# USB Input Devices
785#
786# CONFIG_USB_HID is not set
787
788#
789# USB HID Boot Protocol drivers
790#
791# CONFIG_USB_KBD is not set
792# CONFIG_USB_MOUSE is not set
793# CONFIG_USB_AIPTEK is not set
794# CONFIG_USB_WACOM is not set
795# CONFIG_USB_ACECAD is not set
796# CONFIG_USB_KBTAB is not set
797# CONFIG_USB_POWERMATE is not set
798# CONFIG_USB_MTOUCH is not set
799# CONFIG_USB_ITMTOUCH is not set
800# CONFIG_USB_EGALAX is not set
801# CONFIG_USB_YEALINK is not set
802# CONFIG_USB_XPAD is not set
803# CONFIG_USB_ATI_REMOTE is not set
804# CONFIG_USB_KEYSPAN_REMOTE is not set
805# CONFIG_USB_APPLETOUCH is not set
806
807#
808# USB Imaging devices
809#
810# CONFIG_USB_MDC800 is not set
811# CONFIG_USB_MICROTEK is not set
812
813#
814# USB Multimedia devices
815#
816# CONFIG_USB_DABUSB is not set
817
818#
819# Video4Linux support is needed for USB Multimedia device support
820#
821
822#
823# USB Network Adapters
824#
825# CONFIG_USB_CATC is not set
826# CONFIG_USB_KAWETH is not set
827# CONFIG_USB_PEGASUS is not set
828# CONFIG_USB_RTL8150 is not set
829# CONFIG_USB_USBNET is not set
830CONFIG_USB_MON=y
831
832#
833# USB port drivers
834#
835
836#
837# USB Serial Converter support
838#
839# CONFIG_USB_SERIAL is not set
840
841#
842# USB Miscellaneous drivers
843#
844# CONFIG_USB_EMI62 is not set
845# CONFIG_USB_EMI26 is not set
846# CONFIG_USB_AUERSWALD is not set
847# CONFIG_USB_RIO500 is not set
848# CONFIG_USB_LEGOTOWER is not set
849# CONFIG_USB_LCD is not set
850# CONFIG_USB_LED is not set
851# CONFIG_USB_CYTHERM is not set
852# CONFIG_USB_PHIDGETKIT is not set
853# CONFIG_USB_PHIDGETSERVO is not set
854# CONFIG_USB_IDMOUSE is not set
855# CONFIG_USB_LD is not set
856
857#
858# USB DSL modem support
859#
860
861#
862# USB Gadget Support
863#
864# CONFIG_USB_GADGET is not set
865
866#
867# MMC/SD Card support
868#
869# CONFIG_MMC is not set
870
871#
872# InfiniBand support
873#
874# CONFIG_INFINIBAND is not set
875
876#
877# SN Devices
878#
879
880#
881# File systems
882#
883CONFIG_EXT2_FS=y
884# CONFIG_EXT2_FS_XATTR is not set
885# CONFIG_EXT2_FS_XIP is not set
886# CONFIG_EXT3_FS is not set
887# CONFIG_JBD is not set
888# CONFIG_REISERFS_FS is not set
889# CONFIG_JFS_FS is not set
890# CONFIG_FS_POSIX_ACL is not set
891# CONFIG_XFS_FS is not set
892# CONFIG_MINIX_FS is not set
893# CONFIG_ROMFS_FS is not set
894CONFIG_INOTIFY=y
895# CONFIG_QUOTA is not set
896# CONFIG_DNOTIFY is not set
897# CONFIG_AUTOFS_FS is not set
898# CONFIG_AUTOFS4_FS is not set
899# CONFIG_FUSE_FS is not set
900
901#
902# CD-ROM/DVD Filesystems
903#
904# CONFIG_ISO9660_FS is not set
905# CONFIG_UDF_FS is not set
906
907#
908# DOS/FAT/NT Filesystems
909#
910CONFIG_FAT_FS=y
911CONFIG_MSDOS_FS=y
912CONFIG_VFAT_FS=y
913CONFIG_FAT_DEFAULT_CODEPAGE=437
914CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
915# CONFIG_NTFS_FS is not set
916
917#
918# Pseudo filesystems
919#
920CONFIG_PROC_FS=y
921# CONFIG_PROC_KCORE is not set
922CONFIG_SYSFS=y
923CONFIG_TMPFS=y
924# CONFIG_HUGETLB_PAGE is not set
925CONFIG_RAMFS=y
926# CONFIG_RELAYFS_FS is not set
927
928#
929# Miscellaneous filesystems
930#
931# CONFIG_ADFS_FS is not set
932# CONFIG_AFFS_FS is not set
933# CONFIG_HFS_FS is not set
934# CONFIG_HFSPLUS_FS is not set
935# CONFIG_BEFS_FS is not set
936# CONFIG_BFS_FS is not set
937# CONFIG_EFS_FS is not set
938# CONFIG_CRAMFS is not set
939# CONFIG_VXFS_FS is not set
940# CONFIG_HPFS_FS is not set
941# CONFIG_QNX4FS_FS is not set
942# CONFIG_SYSV_FS is not set
943# CONFIG_UFS_FS is not set
944
945#
946# Network File Systems
947#
948CONFIG_NFS_FS=y
949CONFIG_NFS_V3=y
950# CONFIG_NFS_V3_ACL is not set
951# CONFIG_NFS_V4 is not set
952# CONFIG_NFS_DIRECTIO is not set
953CONFIG_NFSD=m
954# CONFIG_NFSD_V3 is not set
955# CONFIG_NFSD_TCP is not set
956CONFIG_ROOT_NFS=y
957CONFIG_LOCKD=y
958CONFIG_LOCKD_V4=y
959CONFIG_EXPORTFS=m
960CONFIG_NFS_COMMON=y
961CONFIG_SUNRPC=y
962# CONFIG_RPCSEC_GSS_KRB5 is not set
963# CONFIG_RPCSEC_GSS_SPKM3 is not set
964# CONFIG_SMB_FS is not set
965# CONFIG_CIFS is not set
966# CONFIG_NCP_FS is not set
967# CONFIG_CODA_FS is not set
968# CONFIG_AFS_FS is not set
969# CONFIG_9P_FS is not set
970
971#
972# Partition Types
973#
974# CONFIG_PARTITION_ADVANCED is not set
975CONFIG_MSDOS_PARTITION=y
976
977#
978# Native Language Support
979#
980CONFIG_NLS=y
981CONFIG_NLS_DEFAULT="iso8859-1"
982# CONFIG_NLS_CODEPAGE_437 is not set
983# CONFIG_NLS_CODEPAGE_737 is not set
984# CONFIG_NLS_CODEPAGE_775 is not set
985# CONFIG_NLS_CODEPAGE_850 is not set
986# CONFIG_NLS_CODEPAGE_852 is not set
987# CONFIG_NLS_CODEPAGE_855 is not set
988# CONFIG_NLS_CODEPAGE_857 is not set
989# CONFIG_NLS_CODEPAGE_860 is not set
990# CONFIG_NLS_CODEPAGE_861 is not set
991# CONFIG_NLS_CODEPAGE_862 is not set
992# CONFIG_NLS_CODEPAGE_863 is not set
993# CONFIG_NLS_CODEPAGE_864 is not set
994# CONFIG_NLS_CODEPAGE_865 is not set
995# CONFIG_NLS_CODEPAGE_866 is not set
996# CONFIG_NLS_CODEPAGE_869 is not set
997# CONFIG_NLS_CODEPAGE_936 is not set
998# CONFIG_NLS_CODEPAGE_950 is not set
999# CONFIG_NLS_CODEPAGE_932 is not set
1000# CONFIG_NLS_CODEPAGE_949 is not set
1001# CONFIG_NLS_CODEPAGE_874 is not set
1002# CONFIG_NLS_ISO8859_8 is not set
1003# CONFIG_NLS_CODEPAGE_1250 is not set
1004# CONFIG_NLS_CODEPAGE_1251 is not set
1005# CONFIG_NLS_ASCII is not set
1006# CONFIG_NLS_ISO8859_1 is not set
1007# CONFIG_NLS_ISO8859_2 is not set
1008# CONFIG_NLS_ISO8859_3 is not set
1009# CONFIG_NLS_ISO8859_4 is not set
1010# CONFIG_NLS_ISO8859_5 is not set
1011# CONFIG_NLS_ISO8859_6 is not set
1012# CONFIG_NLS_ISO8859_7 is not set
1013# CONFIG_NLS_ISO8859_9 is not set
1014# CONFIG_NLS_ISO8859_13 is not set
1015# CONFIG_NLS_ISO8859_14 is not set
1016# CONFIG_NLS_ISO8859_15 is not set
1017# CONFIG_NLS_KOI8_R is not set
1018# CONFIG_NLS_KOI8_U is not set
1019# CONFIG_NLS_UTF8 is not set
1020
1021#
1022# Profiling support
1023#
1024# CONFIG_PROFILING is not set
1025
1026#
1027# Kernel hacking
1028#
1029# CONFIG_PRINTK_TIME is not set
1030CONFIG_DEBUG_KERNEL=y
1031CONFIG_MAGIC_SYSRQ=y
1032CONFIG_LOG_BUF_SHIFT=14
1033CONFIG_DETECT_SOFTLOCKUP=y
1034# CONFIG_SCHEDSTATS is not set
1035CONFIG_DEBUG_SLAB=y
1036# CONFIG_DEBUG_SPINLOCK is not set
1037# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1038# CONFIG_DEBUG_KOBJECT is not set
1039# CONFIG_DEBUG_INFO is not set
1040# CONFIG_DEBUG_FS is not set
1041CONFIG_CROSSCOMPILE=y
1042CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp"
1043# CONFIG_DEBUG_STACK_USAGE is not set
1044# CONFIG_KGDB is not set
1045# CONFIG_RUNTIME_DEBUG is not set
1046# CONFIG_MIPS_UNCACHED is not set
1047
1048#
1049# Security options
1050#
1051# CONFIG_KEYS is not set
1052# CONFIG_SECURITY is not set
1053
1054#
1055# Cryptographic options
1056#
1057# CONFIG_CRYPTO is not set
1058
1059#
1060# Hardware crypto devices
1061#
1062
1063#
1064# Library routines
1065#
1066CONFIG_CRC_CCITT=m
1067# CONFIG_CRC16 is not set
1068CONFIG_CRC32=y
1069# CONFIG_LIBCRC32C is not set
diff --git a/arch/mips/configs/pnx8550-v2pci_defconfig b/arch/mips/configs/pnx8550-v2pci_defconfig
new file mode 100644
index 000000000000..deb24c29ac0a
--- /dev/null
+++ b/arch/mips/configs/pnx8550-v2pci_defconfig
@@ -0,0 +1,1251 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.14-rc2
4# Thu Oct 20 22:26:53 2005
5#
6CONFIG_MIPS=y
7
8#
9# Code maturity level options
10#
11CONFIG_EXPERIMENTAL=y
12CONFIG_CLEAN_COMPILE=y
13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
15
16#
17# General setup
18#
19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
21CONFIG_SWAP=y
22CONFIG_SYSVIPC=y
23# CONFIG_POSIX_MQUEUE is not set
24# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set
27# CONFIG_HOTPLUG is not set
28CONFIG_KOBJECT_UEVENT=y
29CONFIG_IKCONFIG=y
30CONFIG_IKCONFIG_PROC=y
31CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
38CONFIG_FUTEX=y
39CONFIG_EPOLL=y
40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
41CONFIG_SHMEM=y
42CONFIG_CC_ALIGN_FUNCTIONS=0
43CONFIG_CC_ALIGN_LABELS=0
44CONFIG_CC_ALIGN_LOOPS=0
45CONFIG_CC_ALIGN_JUMPS=0
46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
48
49#
50# Loadable module support
51#
52CONFIG_MODULES=y
53# CONFIG_MODULE_UNLOAD is not set
54CONFIG_OBSOLETE_MODPARM=y
55# CONFIG_MODVERSIONS is not set
56# CONFIG_MODULE_SRCVERSION_ALL is not set
57CONFIG_KMOD=y
58
59#
60# Machine selection
61#
62# CONFIG_MIPS_MTX1 is not set
63# CONFIG_MIPS_BOSPORUS is not set
64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
75# CONFIG_MIPS_COBALT is not set
76# CONFIG_MACH_DECSTATION is not set
77# CONFIG_MIPS_EV64120 is not set
78# CONFIG_MIPS_EV96100 is not set
79# CONFIG_MIPS_IVR is not set
80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
83# CONFIG_MIPS_ATLAS is not set
84# CONFIG_MIPS_MALTA is not set
85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
88# CONFIG_MOMENCO_OCELOT is not set
89# CONFIG_MOMENCO_OCELOT_3 is not set
90# CONFIG_MOMENCO_OCELOT_C is not set
91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93CONFIG_PNX8550_V2PCI=y
94# CONFIG_PNX8550_JBS is not set
95# CONFIG_DDB5074 is not set
96# CONFIG_DDB5476 is not set
97# CONFIG_DDB5477 is not set
98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
101# CONFIG_SGI_IP22 is not set
102# CONFIG_SGI_IP27 is not set
103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
117CONFIG_RWSEM_GENERIC_SPINLOCK=y
118CONFIG_GENERIC_CALIBRATE_DELAY=y
119CONFIG_DMA_NONCOHERENT=y
120CONFIG_DMA_NEED_PCI_MAP_STATE=y
121# CONFIG_CPU_BIG_ENDIAN is not set
122CONFIG_CPU_LITTLE_ENDIAN=y
123CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
124CONFIG_PNX8550=y
125CONFIG_SOC_PNX8550=y
126CONFIG_MIPS_L1_CACHE_SHIFT=5
127
128#
129# CPU selection
130#
131# CONFIG_CPU_MIPS32_R1 is not set
132# CONFIG_CPU_MIPS32_R2 is not set
133# CONFIG_CPU_MIPS64_R1 is not set
134# CONFIG_CPU_MIPS64_R2 is not set
135# CONFIG_CPU_R3000 is not set
136# CONFIG_CPU_TX39XX is not set
137# CONFIG_CPU_VR41XX is not set
138# CONFIG_CPU_R4300 is not set
139CONFIG_CPU_R4X00=y
140# CONFIG_CPU_TX49XX is not set
141# CONFIG_CPU_R5000 is not set
142# CONFIG_CPU_R5432 is not set
143# CONFIG_CPU_R6000 is not set
144# CONFIG_CPU_NEVADA is not set
145# CONFIG_CPU_R8000 is not set
146# CONFIG_CPU_R10000 is not set
147# CONFIG_CPU_RM7000 is not set
148# CONFIG_CPU_RM9000 is not set
149# CONFIG_CPU_SB1 is not set
150CONFIG_SYS_HAS_CPU_R4X00=y
151CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
152CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
153CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
154
155#
156# Kernel type
157#
158CONFIG_32BIT=y
159# CONFIG_64BIT is not set
160CONFIG_PAGE_SIZE_4KB=y
161# CONFIG_PAGE_SIZE_8KB is not set
162# CONFIG_PAGE_SIZE_16KB is not set
163# CONFIG_PAGE_SIZE_64KB is not set
164# CONFIG_MIPS_MT is not set
165# CONFIG_64BIT_PHYS_ADDR is not set
166CONFIG_CPU_ADVANCED=y
167CONFIG_CPU_HAS_LLSC=y
168# CONFIG_CPU_HAS_LLDSCD is not set
169# CONFIG_CPU_HAS_WB is not set
170CONFIG_CPU_HAS_SYNC=y
171CONFIG_GENERIC_HARDIRQS=y
172CONFIG_GENERIC_IRQ_PROBE=y
173CONFIG_ARCH_FLATMEM_ENABLE=y
174CONFIG_SELECT_MEMORY_MODEL=y
175CONFIG_FLATMEM_MANUAL=y
176# CONFIG_DISCONTIGMEM_MANUAL is not set
177# CONFIG_SPARSEMEM_MANUAL is not set
178CONFIG_FLATMEM=y
179CONFIG_FLAT_NODE_MEM_MAP=y
180# CONFIG_SPARSEMEM_STATIC is not set
181CONFIG_PREEMPT_NONE=y
182# CONFIG_PREEMPT_VOLUNTARY is not set
183# CONFIG_PREEMPT is not set
184
185#
186# Bus options (PCI, PCMCIA, EISA, ISA, TC)
187#
188CONFIG_HW_HAS_PCI=y
189CONFIG_PCI=y
190# CONFIG_PCI_LEGACY_PROC is not set
191CONFIG_MMU=y
192
193#
194# PCCARD (PCMCIA/CardBus) support
195#
196# CONFIG_PCCARD is not set
197
198#
199# PCI Hotplug Support
200#
201# CONFIG_HOTPLUG_PCI is not set
202
203#
204# Executable file formats
205#
206CONFIG_BINFMT_ELF=y
207# CONFIG_BINFMT_MISC is not set
208CONFIG_TRAD_SIGNALS=y
209
210#
211# Networking
212#
213CONFIG_NET=y
214
215#
216# Networking options
217#
218CONFIG_PACKET=y
219# CONFIG_PACKET_MMAP is not set
220CONFIG_UNIX=y
221# CONFIG_NET_KEY is not set
222CONFIG_INET=y
223# CONFIG_IP_MULTICAST is not set
224# CONFIG_IP_ADVANCED_ROUTER is not set
225CONFIG_IP_FIB_HASH=y
226CONFIG_IP_PNP=y
227# CONFIG_IP_PNP_DHCP is not set
228# CONFIG_IP_PNP_BOOTP is not set
229# CONFIG_IP_PNP_RARP is not set
230# CONFIG_NET_IPIP is not set
231# CONFIG_NET_IPGRE is not set
232# CONFIG_ARPD is not set
233# CONFIG_SYN_COOKIES is not set
234# CONFIG_INET_AH is not set
235# CONFIG_INET_ESP is not set
236# CONFIG_INET_IPCOMP is not set
237# CONFIG_INET_TUNNEL is not set
238CONFIG_INET_DIAG=y
239CONFIG_INET_TCP_DIAG=y
240# CONFIG_TCP_CONG_ADVANCED is not set
241CONFIG_TCP_CONG_BIC=y
242
243#
244# IP: Virtual Server Configuration
245#
246# CONFIG_IP_VS is not set
247CONFIG_IPV6=m
248# CONFIG_IPV6_PRIVACY is not set
249# CONFIG_INET6_AH is not set
250# CONFIG_INET6_ESP is not set
251# CONFIG_INET6_IPCOMP is not set
252# CONFIG_INET6_TUNNEL is not set
253# CONFIG_IPV6_TUNNEL is not set
254CONFIG_NETFILTER=y
255# CONFIG_NETFILTER_DEBUG is not set
256# CONFIG_NETFILTER_NETLINK is not set
257
258#
259# IP: Netfilter Configuration
260#
261# CONFIG_IP_NF_CONNTRACK is not set
262CONFIG_IP_NF_PPTP=m
263# CONFIG_IP_NF_QUEUE is not set
264# CONFIG_IP_NF_IPTABLES is not set
265# CONFIG_IP_NF_ARPTABLES is not set
266
267#
268# IPv6: Netfilter Configuration (EXPERIMENTAL)
269#
270# CONFIG_IP6_NF_QUEUE is not set
271# CONFIG_IP6_NF_IPTABLES is not set
272
273#
274# DCCP Configuration (EXPERIMENTAL)
275#
276# CONFIG_IP_DCCP is not set
277
278#
279# SCTP Configuration (EXPERIMENTAL)
280#
281# CONFIG_IP_SCTP is not set
282# CONFIG_ATM is not set
283# CONFIG_BRIDGE is not set
284# CONFIG_VLAN_8021Q is not set
285# CONFIG_DECNET is not set
286# CONFIG_LLC2 is not set
287# CONFIG_IPX is not set
288# CONFIG_ATALK is not set
289# CONFIG_X25 is not set
290# CONFIG_LAPB is not set
291# CONFIG_NET_DIVERT is not set
292# CONFIG_ECONET is not set
293# CONFIG_WAN_ROUTER is not set
294# CONFIG_NET_SCHED is not set
295# CONFIG_NET_CLS_ROUTE is not set
296
297#
298# Network testing
299#
300# CONFIG_NET_PKTGEN is not set
301# CONFIG_HAMRADIO is not set
302# CONFIG_IRDA is not set
303# CONFIG_BT is not set
304# CONFIG_IEEE80211 is not set
305
306#
307# Device Drivers
308#
309
310#
311# Generic Driver Options
312#
313CONFIG_STANDALONE=y
314CONFIG_PREVENT_FIRMWARE_BUILD=y
315# CONFIG_FW_LOADER is not set
316
317#
318# Connector - unified userspace <-> kernelspace linker
319#
320# CONFIG_CONNECTOR is not set
321
322#
323# Memory Technology Devices (MTD)
324#
325# CONFIG_MTD is not set
326
327#
328# Parallel port support
329#
330# CONFIG_PARPORT is not set
331
332#
333# Plug and Play support
334#
335
336#
337# Block devices
338#
339# CONFIG_BLK_CPQ_DA is not set
340# CONFIG_BLK_CPQ_CISS_DA is not set
341# CONFIG_BLK_DEV_DAC960 is not set
342# CONFIG_BLK_DEV_UMEM is not set
343# CONFIG_BLK_DEV_COW_COMMON is not set
344CONFIG_BLK_DEV_LOOP=y
345# CONFIG_BLK_DEV_CRYPTOLOOP is not set
346# CONFIG_BLK_DEV_NBD is not set
347# CONFIG_BLK_DEV_SX8 is not set
348# CONFIG_BLK_DEV_UB is not set
349CONFIG_BLK_DEV_RAM=y
350CONFIG_BLK_DEV_RAM_COUNT=16
351CONFIG_BLK_DEV_RAM_SIZE=8192
352CONFIG_BLK_DEV_INITRD=y
353# CONFIG_LBD is not set
354# CONFIG_CDROM_PKTCDVD is not set
355
356#
357# IO Schedulers
358#
359CONFIG_IOSCHED_NOOP=y
360CONFIG_IOSCHED_AS=y
361CONFIG_IOSCHED_DEADLINE=y
362CONFIG_IOSCHED_CFQ=y
363# CONFIG_ATA_OVER_ETH is not set
364
365#
366# ATA/ATAPI/MFM/RLL support
367#
368CONFIG_IDE=y
369CONFIG_BLK_DEV_IDE=y
370
371#
372# Please see Documentation/ide.txt for help/info on IDE drives
373#
374# CONFIG_BLK_DEV_IDE_SATA is not set
375CONFIG_BLK_DEV_IDEDISK=y
376CONFIG_IDEDISK_MULTI_MODE=y
377# CONFIG_BLK_DEV_IDECD is not set
378# CONFIG_BLK_DEV_IDETAPE is not set
379# CONFIG_BLK_DEV_IDEFLOPPY is not set
380# CONFIG_BLK_DEV_IDESCSI is not set
381# CONFIG_IDE_TASK_IOCTL is not set
382
383#
384# IDE chipset support/bugfixes
385#
386CONFIG_IDE_GENERIC=y
387CONFIG_BLK_DEV_IDEPCI=y
388CONFIG_IDEPCI_SHARE_IRQ=y
389# CONFIG_BLK_DEV_OFFBOARD is not set
390# CONFIG_BLK_DEV_GENERIC is not set
391# CONFIG_BLK_DEV_OPTI621 is not set
392CONFIG_BLK_DEV_IDEDMA_PCI=y
393# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
394CONFIG_IDEDMA_PCI_AUTO=y
395# CONFIG_IDEDMA_ONLYDISK is not set
396# CONFIG_BLK_DEV_AEC62XX is not set
397# CONFIG_BLK_DEV_ALI15X3 is not set
398# CONFIG_BLK_DEV_AMD74XX is not set
399CONFIG_BLK_DEV_CMD64X=y
400# CONFIG_BLK_DEV_TRIFLEX is not set
401# CONFIG_BLK_DEV_CY82C693 is not set
402# CONFIG_BLK_DEV_CS5520 is not set
403# CONFIG_BLK_DEV_CS5530 is not set
404# CONFIG_BLK_DEV_HPT34X is not set
405# CONFIG_BLK_DEV_HPT366 is not set
406# CONFIG_BLK_DEV_SC1200 is not set
407# CONFIG_BLK_DEV_PIIX is not set
408# CONFIG_BLK_DEV_IT821X is not set
409# CONFIG_BLK_DEV_NS87415 is not set
410# CONFIG_BLK_DEV_PDC202XX_OLD is not set
411# CONFIG_BLK_DEV_PDC202XX_NEW is not set
412# CONFIG_BLK_DEV_SVWKS is not set
413# CONFIG_BLK_DEV_SIIMAGE is not set
414# CONFIG_BLK_DEV_SLC90E66 is not set
415# CONFIG_BLK_DEV_TRM290 is not set
416# CONFIG_BLK_DEV_VIA82CXXX is not set
417# CONFIG_IDE_ARM is not set
418CONFIG_BLK_DEV_IDEDMA=y
419# CONFIG_IDEDMA_IVB is not set
420CONFIG_IDEDMA_AUTO=y
421# CONFIG_BLK_DEV_HD is not set
422
423#
424# SCSI device support
425#
426# CONFIG_RAID_ATTRS is not set
427CONFIG_SCSI=y
428CONFIG_SCSI_PROC_FS=y
429
430#
431# SCSI support type (disk, tape, CD-ROM)
432#
433CONFIG_BLK_DEV_SD=y
434# CONFIG_CHR_DEV_ST is not set
435# CONFIG_CHR_DEV_OSST is not set
436# CONFIG_BLK_DEV_SR is not set
437# CONFIG_CHR_DEV_SG is not set
438# CONFIG_CHR_DEV_SCH is not set
439
440#
441# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
442#
443# CONFIG_SCSI_MULTI_LUN is not set
444# CONFIG_SCSI_CONSTANTS is not set
445# CONFIG_SCSI_LOGGING is not set
446
447#
448# SCSI Transport Attributes
449#
450CONFIG_SCSI_SPI_ATTRS=m
451# CONFIG_SCSI_FC_ATTRS is not set
452# CONFIG_SCSI_ISCSI_ATTRS is not set
453# CONFIG_SCSI_SAS_ATTRS is not set
454
455#
456# SCSI low-level drivers
457#
458# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
459# CONFIG_SCSI_3W_9XXX is not set
460# CONFIG_SCSI_ACARD is not set
461# CONFIG_SCSI_AACRAID is not set
462CONFIG_SCSI_AIC7XXX=m
463CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
464CONFIG_AIC7XXX_RESET_DELAY_MS=15000
465# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
466CONFIG_AIC7XXX_DEBUG_MASK=0
467# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
468# CONFIG_SCSI_AIC7XXX_OLD is not set
469# CONFIG_SCSI_AIC79XX is not set
470# CONFIG_SCSI_DPT_I2O is not set
471# CONFIG_MEGARAID_NEWGEN is not set
472# CONFIG_MEGARAID_LEGACY is not set
473# CONFIG_SCSI_SATA is not set
474# CONFIG_SCSI_DMX3191D is not set
475# CONFIG_SCSI_FUTURE_DOMAIN is not set
476# CONFIG_SCSI_IPS is not set
477# CONFIG_SCSI_INITIO is not set
478# CONFIG_SCSI_INIA100 is not set
479# CONFIG_SCSI_SYM53C8XX_2 is not set
480# CONFIG_SCSI_IPR is not set
481# CONFIG_SCSI_QLOGIC_FC is not set
482# CONFIG_SCSI_QLOGIC_1280 is not set
483CONFIG_SCSI_QLA2XXX=y
484# CONFIG_SCSI_QLA21XX is not set
485# CONFIG_SCSI_QLA22XX is not set
486# CONFIG_SCSI_QLA2300 is not set
487# CONFIG_SCSI_QLA2322 is not set
488# CONFIG_SCSI_QLA6312 is not set
489# CONFIG_SCSI_QLA24XX is not set
490# CONFIG_SCSI_LPFC is not set
491# CONFIG_SCSI_DC395x is not set
492# CONFIG_SCSI_DC390T is not set
493# CONFIG_SCSI_NSP32 is not set
494# CONFIG_SCSI_DEBUG is not set
495
496#
497# Multi-device support (RAID and LVM)
498#
499# CONFIG_MD is not set
500
501#
502# Fusion MPT device support
503#
504# CONFIG_FUSION is not set
505# CONFIG_FUSION_SPI is not set
506# CONFIG_FUSION_FC is not set
507
508#
509# IEEE 1394 (FireWire) support
510#
511# CONFIG_IEEE1394 is not set
512
513#
514# I2O device support
515#
516# CONFIG_I2O is not set
517
518#
519# Network device support
520#
521CONFIG_NETDEVICES=y
522# CONFIG_DUMMY is not set
523# CONFIG_BONDING is not set
524# CONFIG_EQUALIZER is not set
525CONFIG_TUN=m
526
527#
528# ARCnet devices
529#
530# CONFIG_ARCNET is not set
531
532#
533# PHY device support
534#
535# CONFIG_PHYLIB is not set
536
537#
538# Ethernet (10 or 100Mbit)
539#
540CONFIG_NET_ETHERNET=y
541CONFIG_MII=y
542# CONFIG_HAPPYMEAL is not set
543# CONFIG_SUNGEM is not set
544# CONFIG_NET_VENDOR_3COM is not set
545
546#
547# Tulip family network device support
548#
549# CONFIG_NET_TULIP is not set
550# CONFIG_HP100 is not set
551CONFIG_NET_PCI=y
552# CONFIG_PCNET32 is not set
553# CONFIG_AMD8111_ETH is not set
554# CONFIG_ADAPTEC_STARFIRE is not set
555# CONFIG_B44 is not set
556# CONFIG_FORCEDETH is not set
557# CONFIG_DGRS is not set
558# CONFIG_EEPRO100 is not set
559# CONFIG_E100 is not set
560# CONFIG_FEALNX is not set
561CONFIG_NATSEMI=y
562# CONFIG_NE2K_PCI is not set
563# CONFIG_8139CP is not set
564CONFIG_8139TOO=y
565# CONFIG_8139TOO_PIO is not set
566# CONFIG_8139TOO_TUNE_TWISTER is not set
567# CONFIG_8139TOO_8129 is not set
568# CONFIG_8139_OLD_RX_RESET is not set
569# CONFIG_SIS900 is not set
570# CONFIG_EPIC100 is not set
571# CONFIG_SUNDANCE is not set
572# CONFIG_TLAN is not set
573# CONFIG_VIA_RHINE is not set
574# CONFIG_LAN_SAA9730 is not set
575
576#
577# Ethernet (1000 Mbit)
578#
579# CONFIG_ACENIC is not set
580# CONFIG_DL2K is not set
581# CONFIG_E1000 is not set
582# CONFIG_NS83820 is not set
583# CONFIG_HAMACHI is not set
584# CONFIG_YELLOWFIN is not set
585# CONFIG_R8169 is not set
586# CONFIG_SIS190 is not set
587# CONFIG_SKGE is not set
588# CONFIG_SK98LIN is not set
589# CONFIG_VIA_VELOCITY is not set
590# CONFIG_TIGON3 is not set
591# CONFIG_BNX2 is not set
592
593#
594# Ethernet (10000 Mbit)
595#
596# CONFIG_CHELSIO_T1 is not set
597# CONFIG_IXGB is not set
598# CONFIG_S2IO is not set
599
600#
601# Token Ring devices
602#
603# CONFIG_TR is not set
604
605#
606# Wireless LAN (non-hamradio)
607#
608# CONFIG_NET_RADIO is not set
609
610#
611# Wan interfaces
612#
613# CONFIG_WAN is not set
614# CONFIG_FDDI is not set
615# CONFIG_HIPPI is not set
616CONFIG_PPP=m
617# CONFIG_PPP_MULTILINK is not set
618# CONFIG_PPP_FILTER is not set
619CONFIG_PPP_ASYNC=m
620CONFIG_PPP_SYNC_TTY=m
621CONFIG_PPP_DEFLATE=m
622# CONFIG_PPP_BSDCOMP is not set
623# CONFIG_PPPOE is not set
624# CONFIG_SLIP is not set
625# CONFIG_NET_FC is not set
626# CONFIG_SHAPER is not set
627# CONFIG_NETCONSOLE is not set
628# CONFIG_NETPOLL is not set
629# CONFIG_NET_POLL_CONTROLLER is not set
630
631#
632# ISDN subsystem
633#
634# CONFIG_ISDN is not set
635
636#
637# Telephony Support
638#
639# CONFIG_PHONE is not set
640
641#
642# Input device support
643#
644CONFIG_INPUT=y
645
646#
647# Userland interfaces
648#
649CONFIG_INPUT_MOUSEDEV=y
650CONFIG_INPUT_MOUSEDEV_PSAUX=y
651CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
652CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
653# CONFIG_INPUT_JOYDEV is not set
654# CONFIG_INPUT_TSDEV is not set
655CONFIG_INPUT_EVDEV=m
656# CONFIG_INPUT_EVBUG is not set
657
658#
659# Input Device Drivers
660#
661CONFIG_INPUT_KEYBOARD=y
662CONFIG_KEYBOARD_ATKBD=y
663# CONFIG_KEYBOARD_SUNKBD is not set
664# CONFIG_KEYBOARD_LKKBD is not set
665# CONFIG_KEYBOARD_XTKBD is not set
666# CONFIG_KEYBOARD_NEWTON is not set
667CONFIG_INPUT_MOUSE=y
668CONFIG_MOUSE_PS2=y
669# CONFIG_MOUSE_SERIAL is not set
670# CONFIG_MOUSE_VSXXXAA is not set
671# CONFIG_INPUT_JOYSTICK is not set
672# CONFIG_INPUT_TOUCHSCREEN is not set
673# CONFIG_INPUT_MISC is not set
674
675#
676# Hardware I/O ports
677#
678CONFIG_SERIO=y
679CONFIG_SERIO_I8042=y
680CONFIG_SERIO_SERPORT=y
681# CONFIG_SERIO_PCIPS2 is not set
682CONFIG_SERIO_LIBPS2=y
683# CONFIG_SERIO_RAW is not set
684# CONFIG_GAMEPORT is not set
685
686#
687# Character devices
688#
689CONFIG_VT=y
690# CONFIG_VT_CONSOLE is not set
691CONFIG_HW_CONSOLE=y
692CONFIG_SERIAL_NONSTANDARD=y
693# CONFIG_COMPUTONE is not set
694# CONFIG_ROCKETPORT is not set
695# CONFIG_CYCLADES is not set
696# CONFIG_DIGIEPCA is not set
697# CONFIG_MOXA_INTELLIO is not set
698# CONFIG_MOXA_SMARTIO is not set
699# CONFIG_ISI is not set
700# CONFIG_SYNCLINKMP is not set
701# CONFIG_N_HDLC is not set
702# CONFIG_RISCOM8 is not set
703# CONFIG_SPECIALIX is not set
704# CONFIG_SX is not set
705# CONFIG_RIO is not set
706# CONFIG_STALDRV is not set
707
708#
709# Serial drivers
710#
711# CONFIG_SERIAL_8250 is not set
712
713#
714# Non-8250 serial port support
715#
716# CONFIG_SERIAL_IP3106 is not set
717# CONFIG_SERIAL_JSM is not set
718CONFIG_UNIX98_PTYS=y
719CONFIG_LEGACY_PTYS=y
720CONFIG_LEGACY_PTY_COUNT=256
721
722#
723# IPMI
724#
725# CONFIG_IPMI_HANDLER is not set
726
727#
728# Watchdog Cards
729#
730# CONFIG_WATCHDOG is not set
731# CONFIG_RTC is not set
732# CONFIG_GEN_RTC is not set
733# CONFIG_DTLK is not set
734# CONFIG_R3964 is not set
735# CONFIG_APPLICOM is not set
736
737#
738# Ftape, the floppy tape device driver
739#
740# CONFIG_DRM is not set
741# CONFIG_RAW_DRIVER is not set
742
743#
744# TPM devices
745#
746# CONFIG_TCG_TPM is not set
747
748#
749# I2C support
750#
751CONFIG_I2C=m
752CONFIG_I2C_CHARDEV=m
753
754#
755# I2C Algorithms
756#
757CONFIG_I2C_ALGOBIT=m
758# CONFIG_I2C_ALGOPCF is not set
759# CONFIG_I2C_ALGOPCA is not set
760
761#
762# I2C Hardware Bus support
763#
764# CONFIG_I2C_ALI1535 is not set
765# CONFIG_I2C_ALI1563 is not set
766# CONFIG_I2C_ALI15X3 is not set
767# CONFIG_I2C_AMD756 is not set
768# CONFIG_I2C_AMD8111 is not set
769# CONFIG_I2C_I801 is not set
770# CONFIG_I2C_I810 is not set
771# CONFIG_I2C_PIIX4 is not set
772# CONFIG_I2C_NFORCE2 is not set
773# CONFIG_I2C_PARPORT_LIGHT is not set
774# CONFIG_I2C_PROSAVAGE is not set
775# CONFIG_I2C_SAVAGE4 is not set
776# CONFIG_SCx200_ACB is not set
777# CONFIG_I2C_SIS5595 is not set
778# CONFIG_I2C_SIS630 is not set
779# CONFIG_I2C_SIS96X is not set
780# CONFIG_I2C_STUB is not set
781# CONFIG_I2C_VIA is not set
782# CONFIG_I2C_VIAPRO is not set
783# CONFIG_I2C_VOODOO3 is not set
784# CONFIG_I2C_PCA_ISA is not set
785
786#
787# Miscellaneous I2C Chip support
788#
789# CONFIG_SENSORS_DS1337 is not set
790# CONFIG_SENSORS_DS1374 is not set
791# CONFIG_SENSORS_EEPROM is not set
792# CONFIG_SENSORS_PCF8574 is not set
793# CONFIG_SENSORS_PCA9539 is not set
794# CONFIG_SENSORS_PCF8591 is not set
795# CONFIG_SENSORS_RTC8564 is not set
796# CONFIG_SENSORS_MAX6875 is not set
797# CONFIG_I2C_DEBUG_CORE is not set
798# CONFIG_I2C_DEBUG_ALGO is not set
799# CONFIG_I2C_DEBUG_BUS is not set
800# CONFIG_I2C_DEBUG_CHIP is not set
801
802#
803# Dallas's 1-wire bus
804#
805# CONFIG_W1 is not set
806
807#
808# Hardware Monitoring support
809#
810CONFIG_HWMON=y
811# CONFIG_HWMON_VID is not set
812# CONFIG_SENSORS_ADM1021 is not set
813# CONFIG_SENSORS_ADM1025 is not set
814# CONFIG_SENSORS_ADM1026 is not set
815# CONFIG_SENSORS_ADM1031 is not set
816# CONFIG_SENSORS_ADM9240 is not set
817# CONFIG_SENSORS_ASB100 is not set
818# CONFIG_SENSORS_ATXP1 is not set
819# CONFIG_SENSORS_DS1621 is not set
820# CONFIG_SENSORS_FSCHER is not set
821# CONFIG_SENSORS_FSCPOS is not set
822# CONFIG_SENSORS_GL518SM is not set
823# CONFIG_SENSORS_GL520SM is not set
824# CONFIG_SENSORS_IT87 is not set
825# CONFIG_SENSORS_LM63 is not set
826# CONFIG_SENSORS_LM75 is not set
827# CONFIG_SENSORS_LM77 is not set
828# CONFIG_SENSORS_LM78 is not set
829# CONFIG_SENSORS_LM80 is not set
830# CONFIG_SENSORS_LM83 is not set
831# CONFIG_SENSORS_LM85 is not set
832# CONFIG_SENSORS_LM87 is not set
833# CONFIG_SENSORS_LM90 is not set
834# CONFIG_SENSORS_LM92 is not set
835# CONFIG_SENSORS_MAX1619 is not set
836# CONFIG_SENSORS_PC87360 is not set
837# CONFIG_SENSORS_SIS5595 is not set
838# CONFIG_SENSORS_SMSC47M1 is not set
839# CONFIG_SENSORS_SMSC47B397 is not set
840# CONFIG_SENSORS_VIA686A is not set
841# CONFIG_SENSORS_W83781D is not set
842# CONFIG_SENSORS_W83792D is not set
843# CONFIG_SENSORS_W83L785TS is not set
844# CONFIG_SENSORS_W83627HF is not set
845# CONFIG_SENSORS_W83627EHF is not set
846# CONFIG_HWMON_DEBUG_CHIP is not set
847
848#
849# Misc devices
850#
851
852#
853# Multimedia Capabilities Port drivers
854#
855
856#
857# Multimedia devices
858#
859# CONFIG_VIDEO_DEV is not set
860
861#
862# Digital Video Broadcasting Devices
863#
864# CONFIG_DVB is not set
865
866#
867# Graphics support
868#
869CONFIG_FB=y
870# CONFIG_FB_CFB_FILLRECT is not set
871# CONFIG_FB_CFB_COPYAREA is not set
872# CONFIG_FB_CFB_IMAGEBLIT is not set
873# CONFIG_FB_SOFT_CURSOR is not set
874# CONFIG_FB_MACMODES is not set
875# CONFIG_FB_MODE_HELPERS is not set
876# CONFIG_FB_TILEBLITTING is not set
877# CONFIG_FB_CIRRUS is not set
878# CONFIG_FB_PM2 is not set
879# CONFIG_FB_CYBER2000 is not set
880# CONFIG_FB_ASILIANT is not set
881# CONFIG_FB_IMSTT is not set
882# CONFIG_FB_NVIDIA is not set
883# CONFIG_FB_RIVA is not set
884# CONFIG_FB_MATROX is not set
885# CONFIG_FB_RADEON_OLD is not set
886# CONFIG_FB_RADEON is not set
887# CONFIG_FB_ATY128 is not set
888# CONFIG_FB_ATY is not set
889# CONFIG_FB_SAVAGE is not set
890# CONFIG_FB_SIS is not set
891# CONFIG_FB_NEOMAGIC is not set
892# CONFIG_FB_KYRO is not set
893# CONFIG_FB_3DFX is not set
894# CONFIG_FB_VOODOO1 is not set
895# CONFIG_FB_SMIVGX is not set
896# CONFIG_FB_CYBLA is not set
897# CONFIG_FB_TRIDENT is not set
898# CONFIG_FB_E1356 is not set
899# CONFIG_FB_S1D13XXX is not set
900# CONFIG_FB_VIRTUAL is not set
901
902#
903# Console display driver support
904#
905# CONFIG_VGA_CONSOLE is not set
906CONFIG_DUMMY_CONSOLE=y
907# CONFIG_FRAMEBUFFER_CONSOLE is not set
908
909#
910# Logo configuration
911#
912# CONFIG_LOGO is not set
913# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
914
915#
916# Sound
917#
918# CONFIG_SOUND is not set
919
920#
921# USB support
922#
923CONFIG_USB_ARCH_HAS_HCD=y
924CONFIG_USB_ARCH_HAS_OHCI=y
925CONFIG_USB=y
926# CONFIG_USB_DEBUG is not set
927
928#
929# Miscellaneous USB options
930#
931CONFIG_USB_DEVICEFS=y
932# CONFIG_USB_BANDWIDTH is not set
933# CONFIG_USB_DYNAMIC_MINORS is not set
934# CONFIG_USB_OTG is not set
935
936#
937# USB Host Controller Drivers
938#
939# CONFIG_USB_EHCI_HCD is not set
940# CONFIG_USB_ISP116X_HCD is not set
941# CONFIG_USB_OHCI_HCD is not set
942# CONFIG_USB_UHCI_HCD is not set
943# CONFIG_USB_SL811_HCD is not set
944
945#
946# USB Device Class drivers
947#
948# CONFIG_USB_BLUETOOTH_TTY is not set
949# CONFIG_USB_ACM is not set
950# CONFIG_USB_PRINTER is not set
951
952#
953# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
954#
955CONFIG_USB_STORAGE=y
956# CONFIG_USB_STORAGE_DEBUG is not set
957# CONFIG_USB_STORAGE_DATAFAB is not set
958# CONFIG_USB_STORAGE_FREECOM is not set
959# CONFIG_USB_STORAGE_ISD200 is not set
960# CONFIG_USB_STORAGE_DPCM is not set
961# CONFIG_USB_STORAGE_USBAT is not set
962# CONFIG_USB_STORAGE_SDDR09 is not set
963# CONFIG_USB_STORAGE_SDDR55 is not set
964# CONFIG_USB_STORAGE_JUMPSHOT is not set
965# CONFIG_USB_STORAGE_ONETOUCH is not set
966
967#
968# USB Input Devices
969#
970CONFIG_USB_HID=y
971CONFIG_USB_HIDINPUT=y
972# CONFIG_HID_FF is not set
973CONFIG_USB_HIDDEV=y
974# CONFIG_USB_AIPTEK is not set
975# CONFIG_USB_WACOM is not set
976# CONFIG_USB_ACECAD is not set
977# CONFIG_USB_KBTAB is not set
978# CONFIG_USB_POWERMATE is not set
979# CONFIG_USB_MTOUCH is not set
980# CONFIG_USB_ITMTOUCH is not set
981# CONFIG_USB_EGALAX is not set
982# CONFIG_USB_YEALINK is not set
983# CONFIG_USB_XPAD is not set
984# CONFIG_USB_ATI_REMOTE is not set
985# CONFIG_USB_KEYSPAN_REMOTE is not set
986# CONFIG_USB_APPLETOUCH is not set
987
988#
989# USB Imaging devices
990#
991# CONFIG_USB_MDC800 is not set
992# CONFIG_USB_MICROTEK is not set
993
994#
995# USB Multimedia devices
996#
997# CONFIG_USB_DABUSB is not set
998
999#
1000# Video4Linux support is needed for USB Multimedia device support
1001#
1002
1003#
1004# USB Network Adapters
1005#
1006# CONFIG_USB_CATC is not set
1007# CONFIG_USB_KAWETH is not set
1008# CONFIG_USB_PEGASUS is not set
1009# CONFIG_USB_RTL8150 is not set
1010# CONFIG_USB_USBNET is not set
1011CONFIG_USB_MON=y
1012
1013#
1014# USB port drivers
1015#
1016
1017#
1018# USB Serial Converter support
1019#
1020# CONFIG_USB_SERIAL is not set
1021
1022#
1023# USB Miscellaneous drivers
1024#
1025# CONFIG_USB_EMI62 is not set
1026# CONFIG_USB_EMI26 is not set
1027# CONFIG_USB_AUERSWALD is not set
1028# CONFIG_USB_RIO500 is not set
1029# CONFIG_USB_LEGOTOWER is not set
1030# CONFIG_USB_LCD is not set
1031# CONFIG_USB_LED is not set
1032# CONFIG_USB_CYTHERM is not set
1033# CONFIG_USB_PHIDGETKIT is not set
1034# CONFIG_USB_PHIDGETSERVO is not set
1035# CONFIG_USB_IDMOUSE is not set
1036# CONFIG_USB_LD is not set
1037# CONFIG_USB_TEST is not set
1038
1039#
1040# USB DSL modem support
1041#
1042
1043#
1044# USB Gadget Support
1045#
1046# CONFIG_USB_GADGET is not set
1047
1048#
1049# MMC/SD Card support
1050#
1051# CONFIG_MMC is not set
1052
1053#
1054# InfiniBand support
1055#
1056# CONFIG_INFINIBAND is not set
1057
1058#
1059# SN Devices
1060#
1061
1062#
1063# File systems
1064#
1065CONFIG_EXT2_FS=y
1066# CONFIG_EXT2_FS_XATTR is not set
1067# CONFIG_EXT2_FS_XIP is not set
1068CONFIG_EXT3_FS=y
1069CONFIG_EXT3_FS_XATTR=y
1070# CONFIG_EXT3_FS_POSIX_ACL is not set
1071# CONFIG_EXT3_FS_SECURITY is not set
1072CONFIG_JBD=y
1073# CONFIG_JBD_DEBUG is not set
1074CONFIG_FS_MBCACHE=y
1075# CONFIG_REISERFS_FS is not set
1076# CONFIG_JFS_FS is not set
1077# CONFIG_FS_POSIX_ACL is not set
1078CONFIG_XFS_FS=m
1079CONFIG_XFS_EXPORT=y
1080# CONFIG_XFS_QUOTA is not set
1081# CONFIG_XFS_SECURITY is not set
1082# CONFIG_XFS_POSIX_ACL is not set
1083# CONFIG_XFS_RT is not set
1084# CONFIG_MINIX_FS is not set
1085# CONFIG_ROMFS_FS is not set
1086CONFIG_INOTIFY=y
1087# CONFIG_QUOTA is not set
1088CONFIG_DNOTIFY=y
1089CONFIG_AUTOFS_FS=y
1090CONFIG_AUTOFS4_FS=y
1091# CONFIG_FUSE_FS is not set
1092
1093#
1094# CD-ROM/DVD Filesystems
1095#
1096# CONFIG_ISO9660_FS is not set
1097# CONFIG_UDF_FS is not set
1098
1099#
1100# DOS/FAT/NT Filesystems
1101#
1102CONFIG_FAT_FS=y
1103CONFIG_MSDOS_FS=y
1104CONFIG_VFAT_FS=y
1105CONFIG_FAT_DEFAULT_CODEPAGE=437
1106CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1107# CONFIG_NTFS_FS is not set
1108
1109#
1110# Pseudo filesystems
1111#
1112CONFIG_PROC_FS=y
1113# CONFIG_PROC_KCORE is not set
1114CONFIG_SYSFS=y
1115CONFIG_TMPFS=y
1116# CONFIG_HUGETLB_PAGE is not set
1117CONFIG_RAMFS=y
1118# CONFIG_RELAYFS_FS is not set
1119
1120#
1121# Miscellaneous filesystems
1122#
1123# CONFIG_ADFS_FS is not set
1124# CONFIG_AFFS_FS is not set
1125# CONFIG_HFS_FS is not set
1126# CONFIG_HFSPLUS_FS is not set
1127# CONFIG_BEFS_FS is not set
1128# CONFIG_BFS_FS is not set
1129# CONFIG_EFS_FS is not set
1130CONFIG_CRAMFS=y
1131# CONFIG_VXFS_FS is not set
1132# CONFIG_HPFS_FS is not set
1133# CONFIG_QNX4FS_FS is not set
1134# CONFIG_SYSV_FS is not set
1135# CONFIG_UFS_FS is not set
1136
1137#
1138# Network File Systems
1139#
1140CONFIG_NFS_FS=y
1141CONFIG_NFS_V3=y
1142# CONFIG_NFS_V3_ACL is not set
1143# CONFIG_NFS_V4 is not set
1144# CONFIG_NFS_DIRECTIO is not set
1145CONFIG_NFSD=m
1146# CONFIG_NFSD_V3 is not set
1147# CONFIG_NFSD_TCP is not set
1148CONFIG_ROOT_NFS=y
1149CONFIG_LOCKD=y
1150CONFIG_LOCKD_V4=y
1151CONFIG_EXPORTFS=m
1152CONFIG_NFS_COMMON=y
1153CONFIG_SUNRPC=y
1154# CONFIG_RPCSEC_GSS_KRB5 is not set
1155# CONFIG_RPCSEC_GSS_SPKM3 is not set
1156CONFIG_SMB_FS=m
1157# CONFIG_SMB_NLS_DEFAULT is not set
1158# CONFIG_CIFS is not set
1159# CONFIG_NCP_FS is not set
1160# CONFIG_CODA_FS is not set
1161# CONFIG_AFS_FS is not set
1162# CONFIG_9P_FS is not set
1163
1164#
1165# Partition Types
1166#
1167# CONFIG_PARTITION_ADVANCED is not set
1168CONFIG_MSDOS_PARTITION=y
1169
1170#
1171# Native Language Support
1172#
1173CONFIG_NLS=y
1174CONFIG_NLS_DEFAULT="iso8859-1"
1175# CONFIG_NLS_CODEPAGE_437 is not set
1176# CONFIG_NLS_CODEPAGE_737 is not set
1177# CONFIG_NLS_CODEPAGE_775 is not set
1178# CONFIG_NLS_CODEPAGE_850 is not set
1179# CONFIG_NLS_CODEPAGE_852 is not set
1180# CONFIG_NLS_CODEPAGE_855 is not set
1181# CONFIG_NLS_CODEPAGE_857 is not set
1182# CONFIG_NLS_CODEPAGE_860 is not set
1183# CONFIG_NLS_CODEPAGE_861 is not set
1184# CONFIG_NLS_CODEPAGE_862 is not set
1185# CONFIG_NLS_CODEPAGE_863 is not set
1186# CONFIG_NLS_CODEPAGE_864 is not set
1187# CONFIG_NLS_CODEPAGE_865 is not set
1188# CONFIG_NLS_CODEPAGE_866 is not set
1189# CONFIG_NLS_CODEPAGE_869 is not set
1190# CONFIG_NLS_CODEPAGE_936 is not set
1191# CONFIG_NLS_CODEPAGE_950 is not set
1192# CONFIG_NLS_CODEPAGE_932 is not set
1193# CONFIG_NLS_CODEPAGE_949 is not set
1194# CONFIG_NLS_CODEPAGE_874 is not set
1195# CONFIG_NLS_ISO8859_8 is not set
1196# CONFIG_NLS_CODEPAGE_1250 is not set
1197# CONFIG_NLS_CODEPAGE_1251 is not set
1198# CONFIG_NLS_ASCII is not set
1199# CONFIG_NLS_ISO8859_1 is not set
1200# CONFIG_NLS_ISO8859_2 is not set
1201# CONFIG_NLS_ISO8859_3 is not set
1202# CONFIG_NLS_ISO8859_4 is not set
1203# CONFIG_NLS_ISO8859_5 is not set
1204# CONFIG_NLS_ISO8859_6 is not set
1205# CONFIG_NLS_ISO8859_7 is not set
1206# CONFIG_NLS_ISO8859_9 is not set
1207# CONFIG_NLS_ISO8859_13 is not set
1208# CONFIG_NLS_ISO8859_14 is not set
1209# CONFIG_NLS_ISO8859_15 is not set
1210# CONFIG_NLS_KOI8_R is not set
1211# CONFIG_NLS_KOI8_U is not set
1212# CONFIG_NLS_UTF8 is not set
1213
1214#
1215# Profiling support
1216#
1217# CONFIG_PROFILING is not set
1218
1219#
1220# Kernel hacking
1221#
1222# CONFIG_PRINTK_TIME is not set
1223# CONFIG_DEBUG_KERNEL is not set
1224CONFIG_LOG_BUF_SHIFT=14
1225CONFIG_CROSSCOMPILE=y
1226CONFIG_CMDLINE=""
1227
1228#
1229# Security options
1230#
1231# CONFIG_KEYS is not set
1232# CONFIG_SECURITY is not set
1233
1234#
1235# Cryptographic options
1236#
1237# CONFIG_CRYPTO is not set
1238
1239#
1240# Hardware crypto devices
1241#
1242
1243#
1244# Library routines
1245#
1246CONFIG_CRC_CCITT=m
1247# CONFIG_CRC16 is not set
1248CONFIG_CRC32=y
1249# CONFIG_LIBCRC32C is not set
1250CONFIG_ZLIB_INFLATE=y
1251CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig
index b6568e421b99..741a9a971367 100644
--- a/arch/mips/configs/qemu_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.13-rc6 3# Linux kernel version: 2.6.14-rc2
4# Mon Aug 8 11:49:54 2005 4# Thu Oct 20 22:26:56 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -17,6 +17,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32
17# General setup 17# General setup
18# 18#
19CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
20# CONFIG_SWAP is not set 21# CONFIG_SWAP is not set
21# CONFIG_SYSVIPC is not set 22# CONFIG_SYSVIPC is not set
22# CONFIG_BSD_PROCESS_ACCT is not set 23# CONFIG_BSD_PROCESS_ACCT is not set
@@ -25,6 +26,7 @@ CONFIG_LOCALVERSION=""
25# CONFIG_HOTPLUG is not set 26# CONFIG_HOTPLUG is not set
26CONFIG_KOBJECT_UEVENT=y 27CONFIG_KOBJECT_UEVENT=y
27# CONFIG_IKCONFIG is not set 28# CONFIG_IKCONFIG is not set
29CONFIG_INITRAMFS_SOURCE=""
28CONFIG_EMBEDDED=y 30CONFIG_EMBEDDED=y
29CONFIG_KALLSYMS=y 31CONFIG_KALLSYMS=y
30# CONFIG_KALLSYMS_EXTRA_PASS is not set 32# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -74,6 +76,7 @@ CONFIG_BASE_SMALL=1
74# CONFIG_MIPS_ATLAS is not set 76# CONFIG_MIPS_ATLAS is not set
75# CONFIG_MIPS_MALTA is not set 77# CONFIG_MIPS_MALTA is not set
76# CONFIG_MIPS_SEAD is not set 78# CONFIG_MIPS_SEAD is not set
79# CONFIG_MIPS_SIM is not set
77# CONFIG_MOMENCO_JAGUAR_ATX is not set 80# CONFIG_MOMENCO_JAGUAR_ATX is not set
78# CONFIG_MOMENCO_OCELOT is not set 81# CONFIG_MOMENCO_OCELOT is not set
79# CONFIG_MOMENCO_OCELOT_3 is not set 82# CONFIG_MOMENCO_OCELOT_3 is not set
@@ -91,6 +94,7 @@ CONFIG_QEMU=y
91# CONFIG_SGI_IP22 is not set 94# CONFIG_SGI_IP22 is not set
92# CONFIG_SGI_IP27 is not set 95# CONFIG_SGI_IP27 is not set
93# CONFIG_SGI_IP32 is not set 96# CONFIG_SGI_IP32 is not set
97# CONFIG_SIBYTE_BIGSUR is not set
94# CONFIG_SIBYTE_SWARM is not set 98# CONFIG_SIBYTE_SWARM is not set
95# CONFIG_SIBYTE_SENTOSA is not set 99# CONFIG_SIBYTE_SENTOSA is not set
96# CONFIG_SIBYTE_RHONE is not set 100# CONFIG_SIBYTE_RHONE is not set
@@ -105,7 +109,6 @@ CONFIG_QEMU=y
105# CONFIG_TOSHIBA_RBTX4938 is not set 109# CONFIG_TOSHIBA_RBTX4938 is not set
106CONFIG_RWSEM_GENERIC_SPINLOCK=y 110CONFIG_RWSEM_GENERIC_SPINLOCK=y
107CONFIG_GENERIC_CALIBRATE_DELAY=y 111CONFIG_GENERIC_CALIBRATE_DELAY=y
108CONFIG_HAVE_DEC_LOCK=y
109CONFIG_DMA_COHERENT=y 112CONFIG_DMA_COHERENT=y
110CONFIG_GENERIC_ISA_DMA=y 113CONFIG_GENERIC_ISA_DMA=y
111CONFIG_I8259=y 114CONFIG_I8259=y
@@ -119,7 +122,7 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y
119# 122#
120# CPU selection 123# CPU selection
121# 124#
122# CONFIG_CPU_MIPS32_R1 is not set 125CONFIG_CPU_MIPS32_R1=y
123# CONFIG_CPU_MIPS32_R2 is not set 126# CONFIG_CPU_MIPS32_R2 is not set
124# CONFIG_CPU_MIPS64_R1 is not set 127# CONFIG_CPU_MIPS64_R1 is not set
125# CONFIG_CPU_MIPS64_R2 is not set 128# CONFIG_CPU_MIPS64_R2 is not set
@@ -127,7 +130,7 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y
127# CONFIG_CPU_TX39XX is not set 130# CONFIG_CPU_TX39XX is not set
128# CONFIG_CPU_VR41XX is not set 131# CONFIG_CPU_VR41XX is not set
129# CONFIG_CPU_R4300 is not set 132# CONFIG_CPU_R4300 is not set
130CONFIG_CPU_R4X00=y 133# CONFIG_CPU_R4X00 is not set
131# CONFIG_CPU_TX49XX is not set 134# CONFIG_CPU_TX49XX is not set
132# CONFIG_CPU_R5000 is not set 135# CONFIG_CPU_R5000 is not set
133# CONFIG_CPU_R5432 is not set 136# CONFIG_CPU_R5432 is not set
@@ -138,9 +141,11 @@ CONFIG_CPU_R4X00=y
138# CONFIG_CPU_RM7000 is not set 141# CONFIG_CPU_RM7000 is not set
139# CONFIG_CPU_RM9000 is not set 142# CONFIG_CPU_RM9000 is not set
140# CONFIG_CPU_SB1 is not set 143# CONFIG_CPU_SB1 is not set
144CONFIG_SYS_HAS_CPU_MIPS32_R1=y
145CONFIG_CPU_MIPS32=y
146CONFIG_CPU_MIPSR1=y
141CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y 147CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
142CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y 148CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
143CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
144 149
145# 150#
146# Kernel type 151# Kernel type
@@ -151,15 +156,18 @@ CONFIG_PAGE_SIZE_4KB=y
151# CONFIG_PAGE_SIZE_8KB is not set 156# CONFIG_PAGE_SIZE_8KB is not set
152# CONFIG_PAGE_SIZE_16KB is not set 157# CONFIG_PAGE_SIZE_16KB is not set
153# CONFIG_PAGE_SIZE_64KB is not set 158# CONFIG_PAGE_SIZE_64KB is not set
159CONFIG_CPU_HAS_PREFETCH=y
154# CONFIG_MIPS_MT is not set 160# CONFIG_MIPS_MT is not set
155# CONFIG_64BIT_PHYS_ADDR is not set 161# CONFIG_64BIT_PHYS_ADDR is not set
156# CONFIG_CPU_ADVANCED is not set 162# CONFIG_CPU_ADVANCED is not set
157CONFIG_CPU_HAS_LLSC=y 163CONFIG_CPU_HAS_LLSC=y
158CONFIG_CPU_HAS_LLDSCD=y
159CONFIG_CPU_HAS_SYNC=y 164CONFIG_CPU_HAS_SYNC=y
165CONFIG_GENERIC_HARDIRQS=y
166CONFIG_GENERIC_IRQ_PROBE=y
160CONFIG_ARCH_FLATMEM_ENABLE=y 167CONFIG_ARCH_FLATMEM_ENABLE=y
161CONFIG_FLATMEM=y 168CONFIG_FLATMEM=y
162CONFIG_FLAT_NODE_MEM_MAP=y 169CONFIG_FLAT_NODE_MEM_MAP=y
170# CONFIG_SPARSEMEM_STATIC is not set
163CONFIG_PREEMPT_NONE=y 171CONFIG_PREEMPT_NONE=y
164# CONFIG_PREEMPT_VOLUNTARY is not set 172# CONFIG_PREEMPT_VOLUNTARY is not set
165# CONFIG_PREEMPT is not set 173# CONFIG_PREEMPT is not set
@@ -214,8 +222,8 @@ CONFIG_IP_PNP_BOOTP=y
214# CONFIG_INET_ESP is not set 222# CONFIG_INET_ESP is not set
215# CONFIG_INET_IPCOMP is not set 223# CONFIG_INET_IPCOMP is not set
216# CONFIG_INET_TUNNEL is not set 224# CONFIG_INET_TUNNEL is not set
217CONFIG_IP_TCPDIAG=y 225CONFIG_INET_DIAG=y
218# CONFIG_IP_TCPDIAG_IPV6 is not set 226CONFIG_INET_TCP_DIAG=y
219# CONFIG_TCP_CONG_ADVANCED is not set 227# CONFIG_TCP_CONG_ADVANCED is not set
220CONFIG_TCP_CONG_BIC=y 228CONFIG_TCP_CONG_BIC=y
221# CONFIG_IPV6 is not set 229# CONFIG_IPV6 is not set
@@ -232,9 +240,15 @@ CONFIG_TCP_CONG_BIC=y
232# 240#
233# Network testing 241# Network testing
234# 242#
243# CONFIG_NET_PKTGEN is not set
235# CONFIG_HAMRADIO is not set 244# CONFIG_HAMRADIO is not set
236# CONFIG_IRDA is not set 245# CONFIG_IRDA is not set
237# CONFIG_BT is not set 246# CONFIG_BT is not set
247CONFIG_IEEE80211=y
248# CONFIG_IEEE80211_DEBUG is not set
249CONFIG_IEEE80211_CRYPT_WEP=y
250CONFIG_IEEE80211_CRYPT_CCMP=y
251CONFIG_IEEE80211_CRYPT_TKIP=y
238 252
239# 253#
240# Device Drivers 254# Device Drivers
@@ -248,6 +262,11 @@ CONFIG_STANDALONE=y
248# CONFIG_FW_LOADER is not set 262# CONFIG_FW_LOADER is not set
249 263
250# 264#
265# Connector - unified userspace <-> kernelspace linker
266#
267CONFIG_CONNECTOR=y
268
269#
251# Memory Technology Devices (MTD) 270# Memory Technology Devices (MTD)
252# 271#
253# CONFIG_MTD is not set 272# CONFIG_MTD is not set
@@ -265,13 +284,12 @@ CONFIG_STANDALONE=y
265# 284#
266# Block devices 285# Block devices
267# 286#
268# CONFIG_BLK_DEV_FD is not set
269# CONFIG_BLK_DEV_COW_COMMON is not set 287# CONFIG_BLK_DEV_COW_COMMON is not set
270# CONFIG_BLK_DEV_LOOP is not set 288# CONFIG_BLK_DEV_LOOP is not set
271# CONFIG_BLK_DEV_NBD is not set 289# CONFIG_BLK_DEV_NBD is not set
272# CONFIG_BLK_DEV_RAM is not set 290# CONFIG_BLK_DEV_RAM is not set
273CONFIG_BLK_DEV_RAM_COUNT=16 291CONFIG_BLK_DEV_RAM_COUNT=16
274CONFIG_INITRAMFS_SOURCE="" 292# CONFIG_LBD is not set
275# CONFIG_CDROM_PKTCDVD is not set 293# CONFIG_CDROM_PKTCDVD is not set
276 294
277# 295#
@@ -291,6 +309,7 @@ CONFIG_IOSCHED_NOOP=y
291# 309#
292# SCSI device support 310# SCSI device support
293# 311#
312CONFIG_RAID_ATTRS=y
294# CONFIG_SCSI is not set 313# CONFIG_SCSI is not set
295 314
296# 315#
@@ -331,6 +350,21 @@ CONFIG_NETDEVICES=y
331# CONFIG_ARCNET is not set 350# CONFIG_ARCNET is not set
332 351
333# 352#
353# PHY device support
354#
355CONFIG_PHYLIB=y
356CONFIG_PHYCONTROL=y
357
358#
359# MII PHY device drivers
360#
361CONFIG_MARVELL_PHY=y
362CONFIG_DAVICOM_PHY=y
363CONFIG_QSEMI_PHY=y
364CONFIG_LXT_PHY=y
365CONFIG_CICADA_PHY=y
366
367#
334# Ethernet (10 or 100Mbit) 368# Ethernet (10 or 100Mbit)
335# 369#
336CONFIG_NET_ETHERNET=y 370CONFIG_NET_ETHERNET=y
@@ -470,7 +504,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y
470# I2C support 504# I2C support
471# 505#
472# CONFIG_I2C is not set 506# CONFIG_I2C is not set
473# CONFIG_I2C_SENSOR is not set
474 507
475# 508#
476# Dallas's 1-wire bus 509# Dallas's 1-wire bus
@@ -481,12 +514,17 @@ CONFIG_SERIAL_CORE_CONSOLE=y
481# Hardware Monitoring support 514# Hardware Monitoring support
482# 515#
483# CONFIG_HWMON is not set 516# CONFIG_HWMON is not set
517# CONFIG_HWMON_VID is not set
484 518
485# 519#
486# Misc devices 520# Misc devices
487# 521#
488 522
489# 523#
524# Multimedia Capabilities Port drivers
525#
526
527#
490# Multimedia devices 528# Multimedia devices
491# 529#
492# CONFIG_VIDEO_DEV is not set 530# CONFIG_VIDEO_DEV is not set
@@ -532,7 +570,6 @@ CONFIG_DUMMY_CONSOLE=y
532# 570#
533# InfiniBand support 571# InfiniBand support
534# 572#
535# CONFIG_INFINIBAND is not set
536 573
537# 574#
538# SN Devices 575# SN Devices
@@ -547,10 +584,6 @@ CONFIG_DUMMY_CONSOLE=y
547# CONFIG_REISERFS_FS is not set 584# CONFIG_REISERFS_FS is not set
548# CONFIG_JFS_FS is not set 585# CONFIG_JFS_FS is not set
549# CONFIG_FS_POSIX_ACL is not set 586# CONFIG_FS_POSIX_ACL is not set
550
551#
552# XFS support
553#
554# CONFIG_XFS_FS is not set 587# CONFIG_XFS_FS is not set
555# CONFIG_MINIX_FS is not set 588# CONFIG_MINIX_FS is not set
556# CONFIG_ROMFS_FS is not set 589# CONFIG_ROMFS_FS is not set
@@ -559,6 +592,7 @@ CONFIG_INOTIFY=y
559# CONFIG_DNOTIFY is not set 592# CONFIG_DNOTIFY is not set
560# CONFIG_AUTOFS_FS is not set 593# CONFIG_AUTOFS_FS is not set
561# CONFIG_AUTOFS4_FS is not set 594# CONFIG_AUTOFS4_FS is not set
595CONFIG_FUSE_FS=y
562 596
563# 597#
564# CD-ROM/DVD Filesystems 598# CD-ROM/DVD Filesystems
@@ -576,11 +610,13 @@ CONFIG_INOTIFY=y
576# 610#
577# Pseudo filesystems 611# Pseudo filesystems
578# 612#
579# CONFIG_PROC_FS is not set 613CONFIG_PROC_FS=y
614CONFIG_PROC_KCORE=y
580# CONFIG_SYSFS is not set 615# CONFIG_SYSFS is not set
581# CONFIG_TMPFS is not set 616# CONFIG_TMPFS is not set
582# CONFIG_HUGETLB_PAGE is not set 617# CONFIG_HUGETLB_PAGE is not set
583CONFIG_RAMFS=y 618CONFIG_RAMFS=y
619CONFIG_RELAYFS_FS=y
584 620
585# 621#
586# Miscellaneous filesystems 622# Miscellaneous filesystems
@@ -634,12 +670,35 @@ CONFIG_CMDLINE="console=ttyS0 debug ip=172.20.0.2:172.20.0.1::255.255.0.0"
634# Security options 670# Security options
635# 671#
636# CONFIG_KEYS is not set 672# CONFIG_KEYS is not set
637# CONFIG_SECURITY is not set
638 673
639# 674#
640# Cryptographic options 675# Cryptographic options
641# 676#
642# CONFIG_CRYPTO is not set 677CONFIG_CRYPTO=y
678CONFIG_CRYPTO_HMAC=y
679CONFIG_CRYPTO_NULL=y
680CONFIG_CRYPTO_MD4=y
681CONFIG_CRYPTO_MD5=y
682CONFIG_CRYPTO_SHA1=y
683CONFIG_CRYPTO_SHA256=y
684CONFIG_CRYPTO_SHA512=y
685CONFIG_CRYPTO_WP512=y
686CONFIG_CRYPTO_TGR192=y
687CONFIG_CRYPTO_DES=y
688CONFIG_CRYPTO_BLOWFISH=y
689CONFIG_CRYPTO_TWOFISH=y
690CONFIG_CRYPTO_SERPENT=y
691CONFIG_CRYPTO_AES=y
692CONFIG_CRYPTO_CAST5=y
693CONFIG_CRYPTO_CAST6=y
694CONFIG_CRYPTO_TEA=y
695CONFIG_CRYPTO_ARC4=y
696CONFIG_CRYPTO_KHAZAD=y
697CONFIG_CRYPTO_ANUBIS=y
698CONFIG_CRYPTO_DEFLATE=y
699CONFIG_CRYPTO_MICHAEL_MIC=y
700CONFIG_CRYPTO_CRC32C=y
701# CONFIG_CRYPTO_TEST is not set
643 702
644# 703#
645# Hardware crypto devices 704# Hardware crypto devices
@@ -649,7 +708,8 @@ CONFIG_CMDLINE="console=ttyS0 debug ip=172.20.0.2:172.20.0.1::255.255.0.0"
649# Library routines 708# Library routines
650# 709#
651# CONFIG_CRC_CCITT is not set 710# CONFIG_CRC_CCITT is not set
711CONFIG_CRC16=y
652CONFIG_CRC32=y 712CONFIG_CRC32=y
653# CONFIG_LIBCRC32C is not set 713CONFIG_LIBCRC32C=y
654CONFIG_GENERIC_HARDIRQS=y 714CONFIG_ZLIB_INFLATE=y
655CONFIG_GENERIC_IRQ_PROBE=y 715CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig
new file mode 100644
index 000000000000..2bc61ca4ba08
--- /dev/null
+++ b/arch/mips/configs/rbhma4500_defconfig
@@ -0,0 +1,1259 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.14-rc2
4# Thu Oct 20 22:26:59 2005
5#
6CONFIG_MIPS=y
7
8#
9# Code maturity level options
10#
11CONFIG_EXPERIMENTAL=y
12CONFIG_CLEAN_COMPILE=y
13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
15
16#
17# General setup
18#
19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
21CONFIG_SWAP=y
22CONFIG_SYSVIPC=y
23# CONFIG_POSIX_MQUEUE is not set
24# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set
27CONFIG_HOTPLUG=y
28# CONFIG_KOBJECT_UEVENT is not set
29CONFIG_IKCONFIG=y
30CONFIG_IKCONFIG_PROC=y
31CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
38# CONFIG_FUTEX is not set
39# CONFIG_EPOLL is not set
40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
41CONFIG_SHMEM=y
42CONFIG_CC_ALIGN_FUNCTIONS=0
43CONFIG_CC_ALIGN_LABELS=0
44CONFIG_CC_ALIGN_LOOPS=0
45CONFIG_CC_ALIGN_JUMPS=0
46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
48
49#
50# Loadable module support
51#
52CONFIG_MODULES=y
53# CONFIG_MODULE_UNLOAD is not set
54CONFIG_OBSOLETE_MODPARM=y
55# CONFIG_MODVERSIONS is not set
56# CONFIG_MODULE_SRCVERSION_ALL is not set
57CONFIG_KMOD=y
58
59#
60# Machine selection
61#
62# CONFIG_MIPS_MTX1 is not set
63# CONFIG_MIPS_BOSPORUS is not set
64# CONFIG_MIPS_PB1000 is not set
65# CONFIG_MIPS_PB1100 is not set
66# CONFIG_MIPS_PB1500 is not set
67# CONFIG_MIPS_PB1550 is not set
68# CONFIG_MIPS_PB1200 is not set
69# CONFIG_MIPS_DB1000 is not set
70# CONFIG_MIPS_DB1100 is not set
71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
75# CONFIG_MIPS_COBALT is not set
76# CONFIG_MACH_DECSTATION is not set
77# CONFIG_MIPS_EV64120 is not set
78# CONFIG_MIPS_EV96100 is not set
79# CONFIG_MIPS_IVR is not set
80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
83# CONFIG_MIPS_ATLAS is not set
84# CONFIG_MIPS_MALTA is not set
85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
88# CONFIG_MOMENCO_OCELOT is not set
89# CONFIG_MOMENCO_OCELOT_3 is not set
90# CONFIG_MOMENCO_OCELOT_C is not set
91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
95# CONFIG_DDB5074 is not set
96# CONFIG_DDB5476 is not set
97# CONFIG_DDB5477 is not set
98# CONFIG_MACH_VR41XX is not set
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
101# CONFIG_SGI_IP22 is not set
102# CONFIG_SGI_IP27 is not set
103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
115# CONFIG_TOSHIBA_RBTX4927 is not set
116CONFIG_TOSHIBA_RBTX4938=y
117
118#
119# Multiplex Pin Select
120#
121CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61=y
122# CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND is not set
123# CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA is not set
124CONFIG_RWSEM_GENERIC_SPINLOCK=y
125CONFIG_GENERIC_CALIBRATE_DELAY=y
126CONFIG_DMA_NONCOHERENT=y
127CONFIG_DMA_NEED_PCI_MAP_STATE=y
128CONFIG_GENERIC_ISA_DMA=y
129CONFIG_I8259=y
130# CONFIG_CPU_BIG_ENDIAN is not set
131CONFIG_CPU_LITTLE_ENDIAN=y
132CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
133CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
134CONFIG_SWAP_IO_SPACE=y
135CONFIG_MIPS_L1_CACHE_SHIFT=5
136CONFIG_HAVE_STD_PC_SERIAL_PORT=y
137CONFIG_TOSHIBA_BOARDS=y
138
139#
140# CPU selection
141#
142# CONFIG_CPU_MIPS32_R1 is not set
143# CONFIG_CPU_MIPS32_R2 is not set
144# CONFIG_CPU_MIPS64_R1 is not set
145# CONFIG_CPU_MIPS64_R2 is not set
146# CONFIG_CPU_R3000 is not set
147# CONFIG_CPU_TX39XX is not set
148# CONFIG_CPU_VR41XX is not set
149# CONFIG_CPU_R4300 is not set
150# CONFIG_CPU_R4X00 is not set
151CONFIG_CPU_TX49XX=y
152# CONFIG_CPU_R5000 is not set
153# CONFIG_CPU_R5432 is not set
154# CONFIG_CPU_R6000 is not set
155# CONFIG_CPU_NEVADA is not set
156# CONFIG_CPU_R8000 is not set
157# CONFIG_CPU_R10000 is not set
158# CONFIG_CPU_RM7000 is not set
159# CONFIG_CPU_RM9000 is not set
160# CONFIG_CPU_SB1 is not set
161CONFIG_SYS_HAS_CPU_TX49XX=y
162CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
163CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
164CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
165
166#
167# Kernel type
168#
169CONFIG_32BIT=y
170# CONFIG_64BIT is not set
171CONFIG_PAGE_SIZE_4KB=y
172# CONFIG_PAGE_SIZE_8KB is not set
173# CONFIG_PAGE_SIZE_16KB is not set
174# CONFIG_PAGE_SIZE_64KB is not set
175# CONFIG_MIPS_MT is not set
176CONFIG_CPU_ADVANCED=y
177CONFIG_CPU_HAS_LLSC=y
178CONFIG_CPU_HAS_LLDSCD=y
179CONFIG_CPU_HAS_WB=y
180CONFIG_CPU_HAS_SYNC=y
181CONFIG_GENERIC_HARDIRQS=y
182CONFIG_GENERIC_IRQ_PROBE=y
183CONFIG_ARCH_FLATMEM_ENABLE=y
184CONFIG_SELECT_MEMORY_MODEL=y
185CONFIG_FLATMEM_MANUAL=y
186# CONFIG_DISCONTIGMEM_MANUAL is not set
187# CONFIG_SPARSEMEM_MANUAL is not set
188CONFIG_FLATMEM=y
189CONFIG_FLAT_NODE_MEM_MAP=y
190# CONFIG_SPARSEMEM_STATIC is not set
191CONFIG_PREEMPT_NONE=y
192# CONFIG_PREEMPT_VOLUNTARY is not set
193# CONFIG_PREEMPT is not set
194
195#
196# Bus options (PCI, PCMCIA, EISA, ISA, TC)
197#
198CONFIG_HW_HAS_PCI=y
199CONFIG_PCI=y
200# CONFIG_PCI_LEGACY_PROC is not set
201CONFIG_ISA=y
202CONFIG_MMU=y
203
204#
205# PCCARD (PCMCIA/CardBus) support
206#
207# CONFIG_PCCARD is not set
208
209#
210# PCI Hotplug Support
211#
212# CONFIG_HOTPLUG_PCI is not set
213
214#
215# Executable file formats
216#
217CONFIG_BINFMT_ELF=y
218# CONFIG_BINFMT_MISC is not set
219CONFIG_TRAD_SIGNALS=y
220
221#
222# Networking
223#
224CONFIG_NET=y
225
226#
227# Networking options
228#
229CONFIG_PACKET=y
230# CONFIG_PACKET_MMAP is not set
231CONFIG_UNIX=y
232# CONFIG_NET_KEY is not set
233CONFIG_INET=y
234CONFIG_IP_MULTICAST=y
235# CONFIG_IP_ADVANCED_ROUTER is not set
236CONFIG_IP_FIB_HASH=y
237CONFIG_IP_PNP=y
238# CONFIG_IP_PNP_DHCP is not set
239CONFIG_IP_PNP_BOOTP=y
240# CONFIG_IP_PNP_RARP is not set
241# CONFIG_NET_IPIP is not set
242# CONFIG_NET_IPGRE is not set
243# CONFIG_IP_MROUTE is not set
244# CONFIG_ARPD is not set
245# CONFIG_SYN_COOKIES is not set
246# CONFIG_INET_AH is not set
247# CONFIG_INET_ESP is not set
248# CONFIG_INET_IPCOMP is not set
249# CONFIG_INET_TUNNEL is not set
250CONFIG_INET_DIAG=y
251CONFIG_INET_TCP_DIAG=y
252# CONFIG_TCP_CONG_ADVANCED is not set
253CONFIG_TCP_CONG_BIC=y
254
255#
256# IP: Virtual Server Configuration
257#
258# CONFIG_IP_VS is not set
259CONFIG_IPV6=m
260# CONFIG_IPV6_PRIVACY is not set
261# CONFIG_INET6_AH is not set
262# CONFIG_INET6_ESP is not set
263# CONFIG_INET6_IPCOMP is not set
264# CONFIG_INET6_TUNNEL is not set
265# CONFIG_IPV6_TUNNEL is not set
266CONFIG_NETFILTER=y
267# CONFIG_NETFILTER_DEBUG is not set
268CONFIG_NETFILTER_NETLINK=m
269CONFIG_NETFILTER_NETLINK_QUEUE=m
270CONFIG_NETFILTER_NETLINK_LOG=m
271
272#
273# IP: Netfilter Configuration
274#
275# CONFIG_IP_NF_CONNTRACK is not set
276CONFIG_IP_NF_PPTP=m
277# CONFIG_IP_NF_QUEUE is not set
278# CONFIG_IP_NF_IPTABLES is not set
279# CONFIG_IP_NF_ARPTABLES is not set
280
281#
282# IPv6: Netfilter Configuration (EXPERIMENTAL)
283#
284# CONFIG_IP6_NF_QUEUE is not set
285# CONFIG_IP6_NF_IPTABLES is not set
286
287#
288# DCCP Configuration (EXPERIMENTAL)
289#
290# CONFIG_IP_DCCP is not set
291
292#
293# SCTP Configuration (EXPERIMENTAL)
294#
295# CONFIG_IP_SCTP is not set
296# CONFIG_ATM is not set
297# CONFIG_BRIDGE is not set
298# CONFIG_VLAN_8021Q is not set
299# CONFIG_DECNET is not set
300# CONFIG_LLC2 is not set
301# CONFIG_IPX is not set
302# CONFIG_ATALK is not set
303# CONFIG_X25 is not set
304# CONFIG_LAPB is not set
305# CONFIG_NET_DIVERT is not set
306# CONFIG_ECONET is not set
307# CONFIG_WAN_ROUTER is not set
308# CONFIG_NET_SCHED is not set
309# CONFIG_NET_CLS_ROUTE is not set
310
311#
312# Network testing
313#
314# CONFIG_NET_PKTGEN is not set
315# CONFIG_HAMRADIO is not set
316# CONFIG_IRDA is not set
317# CONFIG_BT is not set
318CONFIG_IEEE80211=m
319# CONFIG_IEEE80211_DEBUG is not set
320CONFIG_IEEE80211_CRYPT_WEP=m
321CONFIG_IEEE80211_CRYPT_CCMP=m
322CONFIG_IEEE80211_CRYPT_TKIP=m
323
324#
325# Device Drivers
326#
327
328#
329# Generic Driver Options
330#
331CONFIG_STANDALONE=y
332CONFIG_PREVENT_FIRMWARE_BUILD=y
333CONFIG_FW_LOADER=m
334
335#
336# Connector - unified userspace <-> kernelspace linker
337#
338CONFIG_CONNECTOR=m
339
340#
341# Memory Technology Devices (MTD)
342#
343CONFIG_MTD=y
344# CONFIG_MTD_DEBUG is not set
345# CONFIG_MTD_CONCAT is not set
346CONFIG_MTD_PARTITIONS=y
347# CONFIG_MTD_REDBOOT_PARTS is not set
348# CONFIG_MTD_CMDLINE_PARTS is not set
349
350#
351# User Modules And Translation Layers
352#
353CONFIG_MTD_CHAR=y
354CONFIG_MTD_BLOCK=y
355# CONFIG_FTL is not set
356# CONFIG_NFTL is not set
357# CONFIG_INFTL is not set
358
359#
360# RAM/ROM/Flash chip drivers
361#
362CONFIG_MTD_CFI=y
363# CONFIG_MTD_JEDECPROBE is not set
364CONFIG_MTD_GEN_PROBE=y
365# CONFIG_MTD_CFI_ADV_OPTIONS is not set
366CONFIG_MTD_MAP_BANK_WIDTH_1=y
367CONFIG_MTD_MAP_BANK_WIDTH_2=y
368CONFIG_MTD_MAP_BANK_WIDTH_4=y
369# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
370# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
371# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
372CONFIG_MTD_CFI_I1=y
373CONFIG_MTD_CFI_I2=y
374# CONFIG_MTD_CFI_I4 is not set
375# CONFIG_MTD_CFI_I8 is not set
376CONFIG_MTD_CFI_INTELEXT=y
377CONFIG_MTD_CFI_AMDSTD=y
378CONFIG_MTD_CFI_AMDSTD_RETRY=0
379# CONFIG_MTD_CFI_STAA is not set
380CONFIG_MTD_CFI_UTIL=y
381# CONFIG_MTD_RAM is not set
382# CONFIG_MTD_ROM is not set
383# CONFIG_MTD_ABSENT is not set
384
385#
386# Mapping drivers for chip access
387#
388# CONFIG_MTD_COMPLEX_MAPPINGS is not set
389# CONFIG_MTD_PHYSMAP is not set
390# CONFIG_MTD_PLATRAM is not set
391
392#
393# Self-contained MTD device drivers
394#
395# CONFIG_MTD_PMC551 is not set
396# CONFIG_MTD_SLRAM is not set
397# CONFIG_MTD_PHRAM is not set
398# CONFIG_MTD_MTDRAM is not set
399# CONFIG_MTD_BLKMTD is not set
400# CONFIG_MTD_BLOCK2MTD is not set
401
402#
403# Disk-On-Chip Device Drivers
404#
405# CONFIG_MTD_DOC2000 is not set
406# CONFIG_MTD_DOC2001 is not set
407# CONFIG_MTD_DOC2001PLUS is not set
408
409#
410# NAND Flash Device Drivers
411#
412# CONFIG_MTD_NAND is not set
413
414#
415# Parallel port support
416#
417# CONFIG_PARPORT is not set
418
419#
420# Plug and Play support
421#
422# CONFIG_PNP is not set
423
424#
425# Block devices
426#
427# CONFIG_BLK_CPQ_DA is not set
428# CONFIG_BLK_CPQ_CISS_DA is not set
429# CONFIG_BLK_DEV_DAC960 is not set
430# CONFIG_BLK_DEV_UMEM is not set
431# CONFIG_BLK_DEV_COW_COMMON is not set
432CONFIG_BLK_DEV_LOOP=y
433# CONFIG_BLK_DEV_CRYPTOLOOP is not set
434CONFIG_BLK_DEV_NBD=m
435# CONFIG_BLK_DEV_SX8 is not set
436# CONFIG_BLK_DEV_UB is not set
437CONFIG_BLK_DEV_RAM=y
438CONFIG_BLK_DEV_RAM_COUNT=16
439CONFIG_BLK_DEV_RAM_SIZE=8192
440CONFIG_BLK_DEV_INITRD=y
441# CONFIG_LBD is not set
442# CONFIG_CDROM_PKTCDVD is not set
443
444#
445# IO Schedulers
446#
447CONFIG_IOSCHED_NOOP=y
448CONFIG_IOSCHED_AS=y
449CONFIG_IOSCHED_DEADLINE=y
450CONFIG_IOSCHED_CFQ=y
451# CONFIG_ATA_OVER_ETH is not set
452
453#
454# ATA/ATAPI/MFM/RLL support
455#
456CONFIG_IDE=y
457CONFIG_BLK_DEV_IDE=y
458
459#
460# Please see Documentation/ide.txt for help/info on IDE drives
461#
462# CONFIG_BLK_DEV_IDE_SATA is not set
463CONFIG_BLK_DEV_IDEDISK=y
464# CONFIG_IDEDISK_MULTI_MODE is not set
465CONFIG_BLK_DEV_IDECD=y
466# CONFIG_BLK_DEV_IDETAPE is not set
467# CONFIG_BLK_DEV_IDEFLOPPY is not set
468# CONFIG_IDE_TASK_IOCTL is not set
469
470#
471# IDE chipset support/bugfixes
472#
473CONFIG_IDE_GENERIC=y
474CONFIG_BLK_DEV_IDEPCI=y
475CONFIG_IDEPCI_SHARE_IRQ=y
476# CONFIG_BLK_DEV_OFFBOARD is not set
477# CONFIG_BLK_DEV_GENERIC is not set
478# CONFIG_BLK_DEV_OPTI621 is not set
479CONFIG_BLK_DEV_IDEDMA_PCI=y
480# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
481# CONFIG_IDEDMA_PCI_AUTO is not set
482# CONFIG_BLK_DEV_AEC62XX is not set
483# CONFIG_BLK_DEV_ALI15X3 is not set
484# CONFIG_BLK_DEV_AMD74XX is not set
485# CONFIG_BLK_DEV_CMD64X is not set
486# CONFIG_BLK_DEV_TRIFLEX is not set
487# CONFIG_BLK_DEV_CY82C693 is not set
488# CONFIG_BLK_DEV_CS5520 is not set
489# CONFIG_BLK_DEV_CS5530 is not set
490# CONFIG_BLK_DEV_HPT34X is not set
491# CONFIG_BLK_DEV_HPT366 is not set
492# CONFIG_BLK_DEV_SC1200 is not set
493# CONFIG_BLK_DEV_PIIX is not set
494# CONFIG_BLK_DEV_IT821X is not set
495# CONFIG_BLK_DEV_NS87415 is not set
496# CONFIG_BLK_DEV_PDC202XX_OLD is not set
497# CONFIG_BLK_DEV_PDC202XX_NEW is not set
498# CONFIG_BLK_DEV_SVWKS is not set
499# CONFIG_BLK_DEV_SIIMAGE is not set
500# CONFIG_BLK_DEV_SLC90E66 is not set
501# CONFIG_BLK_DEV_TRM290 is not set
502# CONFIG_BLK_DEV_VIA82CXXX is not set
503# CONFIG_IDE_ARM is not set
504# CONFIG_IDE_CHIPSETS is not set
505CONFIG_BLK_DEV_IDEDMA=y
506# CONFIG_IDEDMA_IVB is not set
507# CONFIG_IDEDMA_AUTO is not set
508# CONFIG_BLK_DEV_HD is not set
509
510#
511# SCSI device support
512#
513CONFIG_RAID_ATTRS=m
514# CONFIG_SCSI is not set
515
516#
517# Old CD-ROM drivers (not SCSI, not IDE)
518#
519# CONFIG_CD_NO_IDESCSI is not set
520
521#
522# Multi-device support (RAID and LVM)
523#
524# CONFIG_MD is not set
525
526#
527# Fusion MPT device support
528#
529# CONFIG_FUSION is not set
530
531#
532# IEEE 1394 (FireWire) support
533#
534# CONFIG_IEEE1394 is not set
535
536#
537# I2O device support
538#
539# CONFIG_I2O is not set
540
541#
542# Network device support
543#
544CONFIG_NETDEVICES=y
545# CONFIG_DUMMY is not set
546# CONFIG_BONDING is not set
547# CONFIG_EQUALIZER is not set
548CONFIG_TUN=m
549
550#
551# ARCnet devices
552#
553# CONFIG_ARCNET is not set
554
555#
556# PHY device support
557#
558CONFIG_PHYLIB=m
559CONFIG_PHYCONTROL=y
560
561#
562# MII PHY device drivers
563#
564CONFIG_MARVELL_PHY=m
565CONFIG_DAVICOM_PHY=m
566CONFIG_QSEMI_PHY=m
567CONFIG_LXT_PHY=m
568CONFIG_CICADA_PHY=m
569
570#
571# Ethernet (10 or 100Mbit)
572#
573CONFIG_NET_ETHERNET=y
574# CONFIG_MII is not set
575# CONFIG_HAPPYMEAL is not set
576# CONFIG_SUNGEM is not set
577# CONFIG_NET_VENDOR_3COM is not set
578# CONFIG_NET_VENDOR_SMC is not set
579# CONFIG_NET_VENDOR_RACAL is not set
580
581#
582# Tulip family network device support
583#
584# CONFIG_NET_TULIP is not set
585# CONFIG_AT1700 is not set
586# CONFIG_DEPCA is not set
587# CONFIG_HP100 is not set
588CONFIG_NET_ISA=y
589# CONFIG_E2100 is not set
590# CONFIG_EWRK3 is not set
591# CONFIG_EEXPRESS is not set
592# CONFIG_EEXPRESS_PRO is not set
593# CONFIG_HPLAN_PLUS is not set
594# CONFIG_HPLAN is not set
595# CONFIG_LP486E is not set
596# CONFIG_ETH16I is not set
597CONFIG_NE2000=y
598# CONFIG_SEEQ8005 is not set
599CONFIG_NET_PCI=y
600# CONFIG_PCNET32 is not set
601# CONFIG_AMD8111_ETH is not set
602# CONFIG_ADAPTEC_STARFIRE is not set
603# CONFIG_AC3200 is not set
604# CONFIG_APRICOT is not set
605# CONFIG_B44 is not set
606# CONFIG_FORCEDETH is not set
607# CONFIG_CS89x0 is not set
608# CONFIG_DGRS is not set
609# CONFIG_EEPRO100 is not set
610# CONFIG_E100 is not set
611# CONFIG_FEALNX is not set
612# CONFIG_NATSEMI is not set
613# CONFIG_NE2K_PCI is not set
614# CONFIG_8139CP is not set
615# CONFIG_8139TOO is not set
616# CONFIG_SIS900 is not set
617# CONFIG_EPIC100 is not set
618# CONFIG_SUNDANCE is not set
619# CONFIG_TLAN is not set
620# CONFIG_VIA_RHINE is not set
621# CONFIG_LAN_SAA9730 is not set
622# CONFIG_NET_POCKET is not set
623
624#
625# Ethernet (1000 Mbit)
626#
627# CONFIG_ACENIC is not set
628# CONFIG_DL2K is not set
629# CONFIG_E1000 is not set
630# CONFIG_NS83820 is not set
631# CONFIG_HAMACHI is not set
632# CONFIG_YELLOWFIN is not set
633# CONFIG_R8169 is not set
634# CONFIG_SIS190 is not set
635# CONFIG_SKGE is not set
636# CONFIG_SK98LIN is not set
637# CONFIG_VIA_VELOCITY is not set
638# CONFIG_TIGON3 is not set
639# CONFIG_BNX2 is not set
640
641#
642# Ethernet (10000 Mbit)
643#
644# CONFIG_CHELSIO_T1 is not set
645# CONFIG_IXGB is not set
646# CONFIG_S2IO is not set
647
648#
649# Token Ring devices
650#
651# CONFIG_TR is not set
652
653#
654# Wireless LAN (non-hamradio)
655#
656CONFIG_NET_RADIO=y
657
658#
659# Obsolete Wireless cards support (pre-802.11)
660#
661# CONFIG_STRIP is not set
662# CONFIG_ARLAN is not set
663# CONFIG_WAVELAN is not set
664
665#
666# Wireless 802.11b ISA/PCI cards support
667#
668# CONFIG_IPW2100 is not set
669# CONFIG_IPW_DEBUG is not set
670CONFIG_IPW2200=m
671# CONFIG_AIRO is not set
672# CONFIG_HERMES is not set
673# CONFIG_ATMEL is not set
674
675#
676# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support
677#
678# CONFIG_PRISM54 is not set
679# CONFIG_HOSTAP is not set
680CONFIG_NET_WIRELESS=y
681
682#
683# Wan interfaces
684#
685# CONFIG_WAN is not set
686# CONFIG_FDDI is not set
687# CONFIG_HIPPI is not set
688CONFIG_PPP=m
689CONFIG_PPP_MULTILINK=y
690# CONFIG_PPP_FILTER is not set
691CONFIG_PPP_ASYNC=m
692CONFIG_PPP_SYNC_TTY=m
693CONFIG_PPP_DEFLATE=m
694# CONFIG_PPP_BSDCOMP is not set
695CONFIG_PPPOE=m
696# CONFIG_SLIP is not set
697# CONFIG_SHAPER is not set
698# CONFIG_NETCONSOLE is not set
699# CONFIG_NETPOLL is not set
700# CONFIG_NET_POLL_CONTROLLER is not set
701
702#
703# ISDN subsystem
704#
705# CONFIG_ISDN is not set
706
707#
708# Telephony Support
709#
710# CONFIG_PHONE is not set
711
712#
713# Input device support
714#
715CONFIG_INPUT=y
716
717#
718# Userland interfaces
719#
720CONFIG_INPUT_MOUSEDEV=y
721CONFIG_INPUT_MOUSEDEV_PSAUX=y
722CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
723CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
724# CONFIG_INPUT_JOYDEV is not set
725# CONFIG_INPUT_TSDEV is not set
726CONFIG_INPUT_EVDEV=y
727# CONFIG_INPUT_EVBUG is not set
728
729#
730# Input Device Drivers
731#
732CONFIG_INPUT_KEYBOARD=y
733CONFIG_KEYBOARD_ATKBD=y
734# CONFIG_KEYBOARD_SUNKBD is not set
735# CONFIG_KEYBOARD_LKKBD is not set
736# CONFIG_KEYBOARD_XTKBD is not set
737# CONFIG_KEYBOARD_NEWTON is not set
738CONFIG_INPUT_MOUSE=y
739CONFIG_MOUSE_PS2=y
740# CONFIG_MOUSE_SERIAL is not set
741# CONFIG_MOUSE_INPORT is not set
742# CONFIG_MOUSE_LOGIBM is not set
743# CONFIG_MOUSE_PC110PAD is not set
744# CONFIG_MOUSE_VSXXXAA is not set
745# CONFIG_INPUT_JOYSTICK is not set
746# CONFIG_INPUT_TOUCHSCREEN is not set
747# CONFIG_INPUT_MISC is not set
748
749#
750# Hardware I/O ports
751#
752CONFIG_SERIO=y
753CONFIG_SERIO_I8042=y
754CONFIG_SERIO_SERPORT=y
755# CONFIG_SERIO_PCIPS2 is not set
756CONFIG_SERIO_LIBPS2=y
757# CONFIG_SERIO_RAW is not set
758# CONFIG_GAMEPORT is not set
759
760#
761# Character devices
762#
763CONFIG_VT=y
764CONFIG_VT_CONSOLE=y
765CONFIG_HW_CONSOLE=y
766# CONFIG_SERIAL_NONSTANDARD is not set
767
768#
769# Serial drivers
770#
771# CONFIG_SERIAL_8250 is not set
772
773#
774# Non-8250 serial port support
775#
776CONFIG_HAS_TXX9_SERIAL=y
777# CONFIG_SERIAL_JSM is not set
778CONFIG_UNIX98_PTYS=y
779CONFIG_LEGACY_PTYS=y
780CONFIG_LEGACY_PTY_COUNT=256
781
782#
783# IPMI
784#
785# CONFIG_IPMI_HANDLER is not set
786
787#
788# Watchdog Cards
789#
790# CONFIG_WATCHDOG is not set
791# CONFIG_RTC is not set
792# CONFIG_GEN_RTC is not set
793# CONFIG_DTLK is not set
794# CONFIG_R3964 is not set
795# CONFIG_APPLICOM is not set
796
797#
798# Ftape, the floppy tape device driver
799#
800# CONFIG_DRM is not set
801# CONFIG_RAW_DRIVER is not set
802
803#
804# TPM devices
805#
806# CONFIG_TCG_TPM is not set
807
808#
809# I2C support
810#
811# CONFIG_I2C is not set
812
813#
814# Dallas's 1-wire bus
815#
816# CONFIG_W1 is not set
817
818#
819# Hardware Monitoring support
820#
821CONFIG_HWMON=y
822# CONFIG_HWMON_VID is not set
823# CONFIG_HWMON_DEBUG_CHIP is not set
824
825#
826# Misc devices
827#
828
829#
830# Multimedia Capabilities Port drivers
831#
832
833#
834# Multimedia devices
835#
836# CONFIG_VIDEO_DEV is not set
837
838#
839# Digital Video Broadcasting Devices
840#
841# CONFIG_DVB is not set
842
843#
844# Graphics support
845#
846CONFIG_FB=y
847CONFIG_FB_CFB_FILLRECT=y
848CONFIG_FB_CFB_COPYAREA=y
849CONFIG_FB_CFB_IMAGEBLIT=y
850CONFIG_FB_SOFT_CURSOR=y
851# CONFIG_FB_MACMODES is not set
852# CONFIG_FB_MODE_HELPERS is not set
853# CONFIG_FB_TILEBLITTING is not set
854# CONFIG_FB_CIRRUS is not set
855# CONFIG_FB_PM2 is not set
856# CONFIG_FB_CYBER2000 is not set
857# CONFIG_FB_ASILIANT is not set
858# CONFIG_FB_IMSTT is not set
859# CONFIG_FB_NVIDIA is not set
860# CONFIG_FB_RIVA is not set
861# CONFIG_FB_MATROX is not set
862# CONFIG_FB_RADEON_OLD is not set
863# CONFIG_FB_RADEON is not set
864# CONFIG_FB_ATY128 is not set
865CONFIG_FB_ATY=y
866CONFIG_FB_ATY_CT=y
867# CONFIG_FB_ATY_GENERIC_LCD is not set
868# CONFIG_FB_ATY_XL_INIT is not set
869# CONFIG_FB_ATY_GX is not set
870# CONFIG_FB_SAVAGE is not set
871# CONFIG_FB_SIS is not set
872# CONFIG_FB_NEOMAGIC is not set
873# CONFIG_FB_KYRO is not set
874# CONFIG_FB_3DFX is not set
875# CONFIG_FB_VOODOO1 is not set
876# CONFIG_FB_SMIVGX is not set
877# CONFIG_FB_CYBLA is not set
878# CONFIG_FB_TRIDENT is not set
879# CONFIG_FB_E1356 is not set
880# CONFIG_FB_S1D13XXX is not set
881# CONFIG_FB_VIRTUAL is not set
882
883#
884# Console display driver support
885#
886CONFIG_VGA_CONSOLE=y
887# CONFIG_MDA_CONSOLE is not set
888CONFIG_DUMMY_CONSOLE=y
889# CONFIG_FRAMEBUFFER_CONSOLE is not set
890
891#
892# Logo configuration
893#
894# CONFIG_LOGO is not set
895# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
896
897#
898# Sound
899#
900# CONFIG_SOUND is not set
901
902#
903# USB support
904#
905CONFIG_USB_ARCH_HAS_HCD=y
906CONFIG_USB_ARCH_HAS_OHCI=y
907CONFIG_USB=y
908# CONFIG_USB_DEBUG is not set
909
910#
911# Miscellaneous USB options
912#
913# CONFIG_USB_DEVICEFS is not set
914# CONFIG_USB_BANDWIDTH is not set
915# CONFIG_USB_DYNAMIC_MINORS is not set
916# CONFIG_USB_OTG is not set
917
918#
919# USB Host Controller Drivers
920#
921# CONFIG_USB_EHCI_HCD is not set
922# CONFIG_USB_ISP116X_HCD is not set
923# CONFIG_USB_OHCI_HCD is not set
924# CONFIG_USB_UHCI_HCD is not set
925# CONFIG_USB_SL811_HCD is not set
926
927#
928# USB Device Class drivers
929#
930# CONFIG_USB_BLUETOOTH_TTY is not set
931# CONFIG_USB_ACM is not set
932# CONFIG_USB_PRINTER is not set
933
934#
935# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
936#
937# CONFIG_USB_STORAGE is not set
938
939#
940# USB Input Devices
941#
942CONFIG_USB_HID=y
943CONFIG_USB_HIDINPUT=y
944# CONFIG_HID_FF is not set
945CONFIG_USB_HIDDEV=y
946# CONFIG_USB_AIPTEK is not set
947# CONFIG_USB_WACOM is not set
948# CONFIG_USB_ACECAD is not set
949# CONFIG_USB_KBTAB is not set
950# CONFIG_USB_POWERMATE is not set
951# CONFIG_USB_MTOUCH is not set
952# CONFIG_USB_ITMTOUCH is not set
953# CONFIG_USB_EGALAX is not set
954CONFIG_USB_YEALINK=m
955# CONFIG_USB_XPAD is not set
956# CONFIG_USB_ATI_REMOTE is not set
957# CONFIG_USB_KEYSPAN_REMOTE is not set
958# CONFIG_USB_APPLETOUCH is not set
959
960#
961# USB Imaging devices
962#
963# CONFIG_USB_MDC800 is not set
964
965#
966# USB Multimedia devices
967#
968# CONFIG_USB_DABUSB is not set
969
970#
971# Video4Linux support is needed for USB Multimedia device support
972#
973
974#
975# USB Network Adapters
976#
977# CONFIG_USB_CATC is not set
978# CONFIG_USB_KAWETH is not set
979# CONFIG_USB_PEGASUS is not set
980# CONFIG_USB_RTL8150 is not set
981# CONFIG_USB_USBNET is not set
982# CONFIG_USB_ZD1201 is not set
983CONFIG_USB_MON=y
984
985#
986# USB port drivers
987#
988
989#
990# USB Serial Converter support
991#
992# CONFIG_USB_SERIAL is not set
993
994#
995# USB Miscellaneous drivers
996#
997# CONFIG_USB_EMI62 is not set
998# CONFIG_USB_EMI26 is not set
999# CONFIG_USB_AUERSWALD is not set
1000# CONFIG_USB_RIO500 is not set
1001# CONFIG_USB_LEGOTOWER is not set
1002# CONFIG_USB_LCD is not set
1003# CONFIG_USB_LED is not set
1004# CONFIG_USB_CYTHERM is not set
1005# CONFIG_USB_PHIDGETKIT is not set
1006# CONFIG_USB_PHIDGETSERVO is not set
1007# CONFIG_USB_IDMOUSE is not set
1008# CONFIG_USB_LD is not set
1009
1010#
1011# USB DSL modem support
1012#
1013
1014#
1015# USB Gadget Support
1016#
1017# CONFIG_USB_GADGET is not set
1018
1019#
1020# MMC/SD Card support
1021#
1022# CONFIG_MMC is not set
1023
1024#
1025# InfiniBand support
1026#
1027# CONFIG_INFINIBAND is not set
1028
1029#
1030# SN Devices
1031#
1032
1033#
1034# File systems
1035#
1036CONFIG_EXT2_FS=y
1037# CONFIG_EXT2_FS_XATTR is not set
1038# CONFIG_EXT2_FS_XIP is not set
1039CONFIG_EXT3_FS=m
1040CONFIG_EXT3_FS_XATTR=y
1041# CONFIG_EXT3_FS_POSIX_ACL is not set
1042# CONFIG_EXT3_FS_SECURITY is not set
1043CONFIG_JBD=m
1044# CONFIG_JBD_DEBUG is not set
1045CONFIG_FS_MBCACHE=y
1046CONFIG_REISERFS_FS=m
1047# CONFIG_REISERFS_CHECK is not set
1048# CONFIG_REISERFS_PROC_INFO is not set
1049# CONFIG_REISERFS_FS_XATTR is not set
1050# CONFIG_JFS_FS is not set
1051# CONFIG_FS_POSIX_ACL is not set
1052CONFIG_XFS_FS=m
1053CONFIG_XFS_EXPORT=y
1054# CONFIG_XFS_QUOTA is not set
1055# CONFIG_XFS_SECURITY is not set
1056# CONFIG_XFS_POSIX_ACL is not set
1057# CONFIG_XFS_RT is not set
1058# CONFIG_MINIX_FS is not set
1059# CONFIG_ROMFS_FS is not set
1060CONFIG_INOTIFY=y
1061# CONFIG_QUOTA is not set
1062# CONFIG_DNOTIFY is not set
1063# CONFIG_AUTOFS_FS is not set
1064CONFIG_AUTOFS4_FS=m
1065CONFIG_FUSE_FS=m
1066
1067#
1068# CD-ROM/DVD Filesystems
1069#
1070CONFIG_ISO9660_FS=y
1071# CONFIG_JOLIET is not set
1072# CONFIG_ZISOFS is not set
1073# CONFIG_UDF_FS is not set
1074
1075#
1076# DOS/FAT/NT Filesystems
1077#
1078CONFIG_FAT_FS=y
1079# CONFIG_MSDOS_FS is not set
1080CONFIG_VFAT_FS=y
1081CONFIG_FAT_DEFAULT_CODEPAGE=437
1082CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1083# CONFIG_NTFS_FS is not set
1084
1085#
1086# Pseudo filesystems
1087#
1088CONFIG_PROC_FS=y
1089# CONFIG_PROC_KCORE is not set
1090CONFIG_SYSFS=y
1091CONFIG_TMPFS=y
1092# CONFIG_HUGETLB_PAGE is not set
1093CONFIG_RAMFS=y
1094CONFIG_RELAYFS_FS=m
1095
1096#
1097# Miscellaneous filesystems
1098#
1099# CONFIG_ADFS_FS is not set
1100# CONFIG_AFFS_FS is not set
1101# CONFIG_HFS_FS is not set
1102# CONFIG_HFSPLUS_FS is not set
1103# CONFIG_BEFS_FS is not set
1104# CONFIG_BFS_FS is not set
1105# CONFIG_EFS_FS is not set
1106# CONFIG_JFFS_FS is not set
1107CONFIG_JFFS2_FS=y
1108CONFIG_JFFS2_FS_DEBUG=0
1109CONFIG_JFFS2_FS_WRITEBUFFER=y
1110# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1111CONFIG_JFFS2_ZLIB=y
1112CONFIG_JFFS2_RTIME=y
1113# CONFIG_JFFS2_RUBIN is not set
1114CONFIG_CRAMFS=y
1115# CONFIG_VXFS_FS is not set
1116# CONFIG_HPFS_FS is not set
1117# CONFIG_QNX4FS_FS is not set
1118# CONFIG_SYSV_FS is not set
1119# CONFIG_UFS_FS is not set
1120
1121#
1122# Network File Systems
1123#
1124CONFIG_NFS_FS=y
1125CONFIG_NFS_V3=y
1126# CONFIG_NFS_V3_ACL is not set
1127# CONFIG_NFS_V4 is not set
1128# CONFIG_NFS_DIRECTIO is not set
1129CONFIG_NFSD=m
1130# CONFIG_NFSD_V3 is not set
1131# CONFIG_NFSD_TCP is not set
1132CONFIG_ROOT_NFS=y
1133CONFIG_LOCKD=y
1134CONFIG_LOCKD_V4=y
1135CONFIG_EXPORTFS=m
1136CONFIG_NFS_COMMON=y
1137CONFIG_SUNRPC=y
1138# CONFIG_RPCSEC_GSS_KRB5 is not set
1139# CONFIG_RPCSEC_GSS_SPKM3 is not set
1140CONFIG_SMB_FS=m
1141# CONFIG_SMB_NLS_DEFAULT is not set
1142# CONFIG_CIFS is not set
1143# CONFIG_NCP_FS is not set
1144# CONFIG_CODA_FS is not set
1145# CONFIG_AFS_FS is not set
1146# CONFIG_9P_FS is not set
1147
1148#
1149# Partition Types
1150#
1151# CONFIG_PARTITION_ADVANCED is not set
1152CONFIG_MSDOS_PARTITION=y
1153
1154#
1155# Native Language Support
1156#
1157CONFIG_NLS=y
1158CONFIG_NLS_DEFAULT="iso8859-1"
1159# CONFIG_NLS_CODEPAGE_437 is not set
1160# CONFIG_NLS_CODEPAGE_737 is not set
1161# CONFIG_NLS_CODEPAGE_775 is not set
1162# CONFIG_NLS_CODEPAGE_850 is not set
1163# CONFIG_NLS_CODEPAGE_852 is not set
1164# CONFIG_NLS_CODEPAGE_855 is not set
1165# CONFIG_NLS_CODEPAGE_857 is not set
1166# CONFIG_NLS_CODEPAGE_860 is not set
1167# CONFIG_NLS_CODEPAGE_861 is not set
1168# CONFIG_NLS_CODEPAGE_862 is not set
1169# CONFIG_NLS_CODEPAGE_863 is not set
1170# CONFIG_NLS_CODEPAGE_864 is not set
1171# CONFIG_NLS_CODEPAGE_865 is not set
1172# CONFIG_NLS_CODEPAGE_866 is not set
1173# CONFIG_NLS_CODEPAGE_869 is not set
1174# CONFIG_NLS_CODEPAGE_936 is not set
1175# CONFIG_NLS_CODEPAGE_950 is not set
1176# CONFIG_NLS_CODEPAGE_932 is not set
1177# CONFIG_NLS_CODEPAGE_949 is not set
1178# CONFIG_NLS_CODEPAGE_874 is not set
1179# CONFIG_NLS_ISO8859_8 is not set
1180# CONFIG_NLS_CODEPAGE_1250 is not set
1181# CONFIG_NLS_CODEPAGE_1251 is not set
1182# CONFIG_NLS_ASCII is not set
1183# CONFIG_NLS_ISO8859_1 is not set
1184# CONFIG_NLS_ISO8859_2 is not set
1185# CONFIG_NLS_ISO8859_3 is not set
1186# CONFIG_NLS_ISO8859_4 is not set
1187# CONFIG_NLS_ISO8859_5 is not set
1188# CONFIG_NLS_ISO8859_6 is not set
1189# CONFIG_NLS_ISO8859_7 is not set
1190# CONFIG_NLS_ISO8859_9 is not set
1191# CONFIG_NLS_ISO8859_13 is not set
1192# CONFIG_NLS_ISO8859_14 is not set
1193# CONFIG_NLS_ISO8859_15 is not set
1194# CONFIG_NLS_KOI8_R is not set
1195# CONFIG_NLS_KOI8_U is not set
1196# CONFIG_NLS_UTF8 is not set
1197
1198#
1199# Profiling support
1200#
1201# CONFIG_PROFILING is not set
1202
1203#
1204# Kernel hacking
1205#
1206# CONFIG_PRINTK_TIME is not set
1207# CONFIG_DEBUG_KERNEL is not set
1208CONFIG_LOG_BUF_SHIFT=14
1209CONFIG_CROSSCOMPILE=y
1210CONFIG_CMDLINE=""
1211
1212#
1213# Security options
1214#
1215# CONFIG_KEYS is not set
1216# CONFIG_SECURITY is not set
1217
1218#
1219# Cryptographic options
1220#
1221CONFIG_CRYPTO=y
1222CONFIG_CRYPTO_HMAC=y
1223CONFIG_CRYPTO_NULL=m
1224CONFIG_CRYPTO_MD4=m
1225CONFIG_CRYPTO_MD5=m
1226CONFIG_CRYPTO_SHA1=m
1227CONFIG_CRYPTO_SHA256=m
1228CONFIG_CRYPTO_SHA512=m
1229CONFIG_CRYPTO_WP512=m
1230CONFIG_CRYPTO_TGR192=m
1231CONFIG_CRYPTO_DES=m
1232CONFIG_CRYPTO_BLOWFISH=m
1233CONFIG_CRYPTO_TWOFISH=m
1234CONFIG_CRYPTO_SERPENT=m
1235CONFIG_CRYPTO_AES=m
1236CONFIG_CRYPTO_CAST5=m
1237CONFIG_CRYPTO_CAST6=m
1238CONFIG_CRYPTO_TEA=m
1239CONFIG_CRYPTO_ARC4=m
1240CONFIG_CRYPTO_KHAZAD=m
1241CONFIG_CRYPTO_ANUBIS=m
1242CONFIG_CRYPTO_DEFLATE=m
1243CONFIG_CRYPTO_MICHAEL_MIC=m
1244CONFIG_CRYPTO_CRC32C=m
1245# CONFIG_CRYPTO_TEST is not set
1246
1247#
1248# Hardware crypto devices
1249#
1250
1251#
1252# Library routines
1253#
1254CONFIG_CRC_CCITT=m
1255CONFIG_CRC16=m
1256CONFIG_CRC32=y
1257CONFIG_LIBCRC32C=m
1258CONFIG_ZLIB_INFLATE=y
1259CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index 17d4fce6c4c6..988a05824f01 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:09 2005 4# Thu Oct 20 22:27:03 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,11 +11,13 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24CONFIG_POSIX_MQUEUE=y 23CONFIG_POSIX_MQUEUE=y
@@ -26,14 +25,17 @@ CONFIG_BSD_PROCESS_ACCT=y
26# CONFIG_BSD_PROCESS_ACCT_V3 is not set 25# CONFIG_BSD_PROCESS_ACCT_V3 is not set
27CONFIG_SYSCTL=y 26CONFIG_SYSCTL=y
28# CONFIG_AUDIT is not set 27# CONFIG_AUDIT is not set
29CONFIG_LOG_BUF_SHIFT=14 28CONFIG_HOTPLUG=y
30# CONFIG_HOTPLUG is not set
31CONFIG_KOBJECT_UEVENT=y 29CONFIG_KOBJECT_UEVENT=y
32CONFIG_IKCONFIG=y 30CONFIG_IKCONFIG=y
33CONFIG_IKCONFIG_PROC=y 31CONFIG_IKCONFIG_PROC=y
32CONFIG_INITRAMFS_SOURCE=""
34CONFIG_EMBEDDED=y 33CONFIG_EMBEDDED=y
35CONFIG_KALLSYMS=y 34CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_EXTRA_PASS is not set 35# CONFIG_KALLSYMS_EXTRA_PASS is not set
36CONFIG_PRINTK=y
37CONFIG_BUG=y
38CONFIG_BASE_FULL=y
37CONFIG_FUTEX=y 39CONFIG_FUTEX=y
38CONFIG_EPOLL=y 40CONFIG_EPOLL=y
39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 41# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -43,6 +45,7 @@ CONFIG_CC_ALIGN_LABELS=0
43CONFIG_CC_ALIGN_LOOPS=0 45CONFIG_CC_ALIGN_LOOPS=0
44CONFIG_CC_ALIGN_JUMPS=0 46CONFIG_CC_ALIGN_JUMPS=0
45# CONFIG_TINY_SHMEM is not set 47# CONFIG_TINY_SHMEM is not set
48CONFIG_BASE_SMALL=0
46 49
47# 50#
48# Loadable module support 51# Loadable module support
@@ -58,43 +61,73 @@ CONFIG_KMOD=y
58# 61#
59# Machine selection 62# Machine selection
60# 63#
61# CONFIG_MACH_JAZZ is not set 64# CONFIG_MIPS_MTX1 is not set
62# CONFIG_MACH_VR41XX is not set 65# CONFIG_MIPS_BOSPORUS is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 66# CONFIG_MIPS_PB1000 is not set
67# CONFIG_MIPS_PB1100 is not set
68# CONFIG_MIPS_PB1500 is not set
69# CONFIG_MIPS_PB1550 is not set
70# CONFIG_MIPS_PB1200 is not set
71# CONFIG_MIPS_DB1000 is not set
72# CONFIG_MIPS_DB1100 is not set
73# CONFIG_MIPS_DB1500 is not set
74# CONFIG_MIPS_DB1550 is not set
75# CONFIG_MIPS_DB1200 is not set
76# CONFIG_MIPS_MIRAGE is not set
64# CONFIG_MIPS_COBALT is not set 77# CONFIG_MIPS_COBALT is not set
65# CONFIG_MACH_DECSTATION is not set 78# CONFIG_MACH_DECSTATION is not set
66# CONFIG_MIPS_EV64120 is not set 79# CONFIG_MIPS_EV64120 is not set
67# CONFIG_MIPS_EV96100 is not set 80# CONFIG_MIPS_EV96100 is not set
68# CONFIG_MIPS_IVR is not set 81# CONFIG_MIPS_IVR is not set
69# CONFIG_LASAT is not set
70# CONFIG_MIPS_ITE8172 is not set 82# CONFIG_MIPS_ITE8172 is not set
83# CONFIG_MACH_JAZZ is not set
84# CONFIG_LASAT is not set
71# CONFIG_MIPS_ATLAS is not set 85# CONFIG_MIPS_ATLAS is not set
72# CONFIG_MIPS_MALTA is not set 86# CONFIG_MIPS_MALTA is not set
73# CONFIG_MIPS_SEAD is not set 87# CONFIG_MIPS_SEAD is not set
88# CONFIG_MIPS_SIM is not set
89# CONFIG_MOMENCO_JAGUAR_ATX is not set
74# CONFIG_MOMENCO_OCELOT is not set 90# CONFIG_MOMENCO_OCELOT is not set
75# CONFIG_MOMENCO_OCELOT_G is not set
76# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_MOMENCO_OCELOT_3 is not set 91# CONFIG_MOMENCO_OCELOT_3 is not set
78# CONFIG_MOMENCO_JAGUAR_ATX is not set 92# CONFIG_MOMENCO_OCELOT_C is not set
79# CONFIG_PMC_YOSEMITE is not set 93# CONFIG_MOMENCO_OCELOT_G is not set
94# CONFIG_MIPS_XXS1500 is not set
95# CONFIG_PNX8550_V2PCI is not set
96# CONFIG_PNX8550_JBS is not set
80# CONFIG_DDB5074 is not set 97# CONFIG_DDB5074 is not set
81# CONFIG_DDB5476 is not set 98# CONFIG_DDB5476 is not set
82# CONFIG_DDB5477 is not set 99# CONFIG_DDB5477 is not set
83# CONFIG_NEC_OSPREY is not set 100# CONFIG_MACH_VR41XX is not set
101# CONFIG_PMC_YOSEMITE is not set
102# CONFIG_QEMU is not set
84# CONFIG_SGI_IP22 is not set 103# CONFIG_SGI_IP22 is not set
85# CONFIG_SOC_AU1X00 is not set 104# CONFIG_SGI_IP27 is not set
86# CONFIG_SIBYTE_SB1xxx_SOC is not set 105# CONFIG_SGI_IP32 is not set
106# CONFIG_SIBYTE_BIGSUR is not set
107# CONFIG_SIBYTE_SWARM is not set
108# CONFIG_SIBYTE_SENTOSA is not set
109# CONFIG_SIBYTE_RHONE is not set
110# CONFIG_SIBYTE_CARMEL is not set
111# CONFIG_SIBYTE_PTSWARM is not set
112# CONFIG_SIBYTE_LITTLESUR is not set
113# CONFIG_SIBYTE_CRHINE is not set
114# CONFIG_SIBYTE_CRHONE is not set
87CONFIG_SNI_RM200_PCI=y 115CONFIG_SNI_RM200_PCI=y
116# CONFIG_TOSHIBA_JMR3927 is not set
88# CONFIG_TOSHIBA_RBTX4927 is not set 117# CONFIG_TOSHIBA_RBTX4927 is not set
118# CONFIG_TOSHIBA_RBTX4938 is not set
89CONFIG_RWSEM_GENERIC_SPINLOCK=y 119CONFIG_RWSEM_GENERIC_SPINLOCK=y
90CONFIG_GENERIC_CALIBRATE_DELAY=y 120CONFIG_GENERIC_CALIBRATE_DELAY=y
91CONFIG_HAVE_DEC_LOCK=y
92CONFIG_ARC=y 121CONFIG_ARC=y
122CONFIG_ARCH_MAY_HAVE_PC_FDC=y
93CONFIG_DMA_NONCOHERENT=y 123CONFIG_DMA_NONCOHERENT=y
94CONFIG_DMA_NEED_PCI_MAP_STATE=y 124CONFIG_DMA_NEED_PCI_MAP_STATE=y
95CONFIG_GENERIC_ISA_DMA=y 125CONFIG_GENERIC_ISA_DMA=y
96CONFIG_I8259=y 126CONFIG_I8259=y
127# CONFIG_CPU_BIG_ENDIAN is not set
97CONFIG_CPU_LITTLE_ENDIAN=y 128CONFIG_CPU_LITTLE_ENDIAN=y
129CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
130CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
98CONFIG_ARC32=y 131CONFIG_ARC32=y
99CONFIG_BOOT_ELF32=y 132CONFIG_BOOT_ELF32=y
100CONFIG_MIPS_L1_CACHE_SHIFT=5 133CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -106,8 +139,10 @@ CONFIG_ARC_PROMLIB=y
106# 139#
107# CPU selection 140# CPU selection
108# 141#
109# CONFIG_CPU_MIPS32 is not set 142# CONFIG_CPU_MIPS32_R1 is not set
110# CONFIG_CPU_MIPS64 is not set 143# CONFIG_CPU_MIPS32_R2 is not set
144# CONFIG_CPU_MIPS64_R1 is not set
145# CONFIG_CPU_MIPS64_R2 is not set
111# CONFIG_CPU_R3000 is not set 146# CONFIG_CPU_R3000 is not set
112# CONFIG_CPU_TX39XX is not set 147# CONFIG_CPU_TX39XX is not set
113# CONFIG_CPU_VR41XX is not set 148# CONFIG_CPU_VR41XX is not set
@@ -123,24 +158,49 @@ CONFIG_CPU_R4X00=y
123# CONFIG_CPU_RM7000 is not set 158# CONFIG_CPU_RM7000 is not set
124# CONFIG_CPU_RM9000 is not set 159# CONFIG_CPU_RM9000 is not set
125# CONFIG_CPU_SB1 is not set 160# CONFIG_CPU_SB1 is not set
161CONFIG_SYS_HAS_CPU_R4X00=y
162CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
163CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
164CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
165CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
166
167#
168# Kernel type
169#
170CONFIG_32BIT=y
171# CONFIG_64BIT is not set
126CONFIG_PAGE_SIZE_4KB=y 172CONFIG_PAGE_SIZE_4KB=y
127# CONFIG_PAGE_SIZE_8KB is not set 173# CONFIG_PAGE_SIZE_8KB is not set
128# CONFIG_PAGE_SIZE_16KB is not set 174# CONFIG_PAGE_SIZE_16KB is not set
129# CONFIG_PAGE_SIZE_64KB is not set 175# CONFIG_PAGE_SIZE_64KB is not set
176# CONFIG_MIPS_MT is not set
130# CONFIG_64BIT_PHYS_ADDR is not set 177# CONFIG_64BIT_PHYS_ADDR is not set
131# CONFIG_CPU_ADVANCED is not set 178# CONFIG_CPU_ADVANCED is not set
132CONFIG_CPU_HAS_LLSC=y 179CONFIG_CPU_HAS_LLSC=y
133CONFIG_CPU_HAS_LLDSCD=y 180CONFIG_CPU_HAS_LLDSCD=y
134CONFIG_CPU_HAS_SYNC=y 181CONFIG_CPU_HAS_SYNC=y
182CONFIG_GENERIC_HARDIRQS=y
183CONFIG_GENERIC_IRQ_PROBE=y
184CONFIG_SYS_SUPPORTS_HIGHMEM=y
185CONFIG_ARCH_FLATMEM_ENABLE=y
186CONFIG_SELECT_MEMORY_MODEL=y
187CONFIG_FLATMEM_MANUAL=y
188# CONFIG_DISCONTIGMEM_MANUAL is not set
189# CONFIG_SPARSEMEM_MANUAL is not set
190CONFIG_FLATMEM=y
191CONFIG_FLAT_NODE_MEM_MAP=y
192# CONFIG_SPARSEMEM_STATIC is not set
193# CONFIG_PREEMPT_NONE is not set
194CONFIG_PREEMPT_VOLUNTARY=y
135# CONFIG_PREEMPT is not set 195# CONFIG_PREEMPT is not set
136 196
137# 197#
138# Bus options (PCI, PCMCIA, EISA, ISA, TC) 198# Bus options (PCI, PCMCIA, EISA, ISA, TC)
139# 199#
200CONFIG_HW_HAS_EISA=y
140CONFIG_HW_HAS_PCI=y 201CONFIG_HW_HAS_PCI=y
141CONFIG_PCI=y 202CONFIG_PCI=y
142CONFIG_PCI_LEGACY_PROC=y 203CONFIG_PCI_LEGACY_PROC=y
143# CONFIG_PCI_NAMES is not set
144CONFIG_ISA=y 204CONFIG_ISA=y
145# CONFIG_EISA is not set 205# CONFIG_EISA is not set
146CONFIG_MMU=y 206CONFIG_MMU=y
@@ -151,11 +211,6 @@ CONFIG_MMU=y
151# CONFIG_PCCARD is not set 211# CONFIG_PCCARD is not set
152 212
153# 213#
154# PC-card bridges
155#
156CONFIG_PCMCIA_PROBE=y
157
158#
159# PCI Hotplug Support 214# PCI Hotplug Support
160# 215#
161# CONFIG_HOTPLUG_PCI is not set 216# CONFIG_HOTPLUG_PCI is not set
@@ -168,240 +223,7 @@ CONFIG_BINFMT_MISC=m
168CONFIG_TRAD_SIGNALS=y 223CONFIG_TRAD_SIGNALS=y
169 224
170# 225#
171# Device Drivers 226# Networking
172#
173
174#
175# Generic Driver Options
176#
177CONFIG_STANDALONE=y
178CONFIG_PREVENT_FIRMWARE_BUILD=y
179# CONFIG_FW_LOADER is not set
180
181#
182# Memory Technology Devices (MTD)
183#
184# CONFIG_MTD is not set
185
186#
187# Parallel port support
188#
189CONFIG_PARPORT=m
190CONFIG_PARPORT_PC=m
191CONFIG_PARPORT_PC_CML1=m
192CONFIG_PARPORT_SERIAL=m
193# CONFIG_PARPORT_PC_FIFO is not set
194# CONFIG_PARPORT_PC_SUPERIO is not set
195# CONFIG_PARPORT_OTHER is not set
196CONFIG_PARPORT_1284=y
197
198#
199# Plug and Play support
200#
201# CONFIG_PNP is not set
202
203#
204# Block devices
205#
206CONFIG_BLK_DEV_FD=m
207# CONFIG_BLK_DEV_XD is not set
208CONFIG_PARIDE=m
209CONFIG_PARIDE_PARPORT=m
210
211#
212# Parallel IDE high-level drivers
213#
214CONFIG_PARIDE_PD=m
215CONFIG_PARIDE_PCD=m
216CONFIG_PARIDE_PF=m
217CONFIG_PARIDE_PT=m
218CONFIG_PARIDE_PG=m
219
220#
221# Parallel IDE protocol modules
222#
223CONFIG_PARIDE_ATEN=m
224CONFIG_PARIDE_BPCK=m
225CONFIG_PARIDE_BPCK6=m
226CONFIG_PARIDE_COMM=m
227CONFIG_PARIDE_DSTR=m
228CONFIG_PARIDE_FIT2=m
229CONFIG_PARIDE_FIT3=m
230CONFIG_PARIDE_EPAT=m
231# CONFIG_PARIDE_EPATC8 is not set
232CONFIG_PARIDE_EPIA=m
233CONFIG_PARIDE_FRIQ=m
234CONFIG_PARIDE_FRPW=m
235CONFIG_PARIDE_KBIC=m
236CONFIG_PARIDE_KTTI=m
237CONFIG_PARIDE_ON20=m
238CONFIG_PARIDE_ON26=m
239# CONFIG_BLK_CPQ_DA is not set
240# CONFIG_BLK_CPQ_CISS_DA is not set
241# CONFIG_BLK_DEV_DAC960 is not set
242# CONFIG_BLK_DEV_UMEM is not set
243# CONFIG_BLK_DEV_COW_COMMON is not set
244CONFIG_BLK_DEV_LOOP=m
245CONFIG_BLK_DEV_CRYPTOLOOP=m
246CONFIG_BLK_DEV_NBD=m
247CONFIG_BLK_DEV_SX8=m
248CONFIG_BLK_DEV_UB=m
249CONFIG_BLK_DEV_RAM=m
250CONFIG_BLK_DEV_RAM_COUNT=16
251CONFIG_BLK_DEV_RAM_SIZE=4096
252CONFIG_INITRAMFS_SOURCE=""
253# CONFIG_LBD is not set
254CONFIG_CDROM_PKTCDVD=m
255CONFIG_CDROM_PKTCDVD_BUFFERS=8
256# CONFIG_CDROM_PKTCDVD_WCACHE is not set
257
258#
259# IO Schedulers
260#
261CONFIG_IOSCHED_NOOP=y
262CONFIG_IOSCHED_AS=y
263CONFIG_IOSCHED_DEADLINE=y
264CONFIG_IOSCHED_CFQ=y
265CONFIG_ATA_OVER_ETH=m
266
267#
268# ATA/ATAPI/MFM/RLL support
269#
270# CONFIG_IDE is not set
271
272#
273# SCSI device support
274#
275CONFIG_SCSI=y
276CONFIG_SCSI_PROC_FS=y
277
278#
279# SCSI support type (disk, tape, CD-ROM)
280#
281CONFIG_BLK_DEV_SD=y
282CONFIG_CHR_DEV_ST=m
283# CONFIG_CHR_DEV_OSST is not set
284CONFIG_BLK_DEV_SR=m
285CONFIG_BLK_DEV_SR_VENDOR=y
286# CONFIG_CHR_DEV_SG is not set
287
288#
289# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
290#
291# CONFIG_SCSI_MULTI_LUN is not set
292CONFIG_SCSI_CONSTANTS=y
293# CONFIG_SCSI_LOGGING is not set
294
295#
296# SCSI Transport Attributes
297#
298CONFIG_SCSI_SPI_ATTRS=y
299# CONFIG_SCSI_FC_ATTRS is not set
300# CONFIG_SCSI_ISCSI_ATTRS is not set
301
302#
303# SCSI low-level drivers
304#
305# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
306# CONFIG_SCSI_3W_9XXX is not set
307# CONFIG_SCSI_7000FASST is not set
308# CONFIG_SCSI_ACARD is not set
309# CONFIG_SCSI_AHA152X is not set
310# CONFIG_SCSI_AHA1542 is not set
311# CONFIG_SCSI_AACRAID is not set
312# CONFIG_SCSI_AIC7XXX is not set
313# CONFIG_SCSI_AIC7XXX_OLD is not set
314# CONFIG_SCSI_AIC79XX is not set
315# CONFIG_SCSI_DPT_I2O is not set
316# CONFIG_SCSI_IN2000 is not set
317CONFIG_MEGARAID_NEWGEN=y
318CONFIG_MEGARAID_MM=m
319CONFIG_MEGARAID_MAILBOX=m
320# CONFIG_SCSI_SATA is not set
321# CONFIG_SCSI_BUSLOGIC is not set
322# CONFIG_SCSI_DMX3191D is not set
323# CONFIG_SCSI_DTC3280 is not set
324# CONFIG_SCSI_EATA is not set
325# CONFIG_SCSI_EATA_PIO is not set
326# CONFIG_SCSI_FUTURE_DOMAIN is not set
327# CONFIG_SCSI_GDTH is not set
328# CONFIG_SCSI_GENERIC_NCR5380 is not set
329# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
330# CONFIG_SCSI_IPS is not set
331# CONFIG_SCSI_INITIO is not set
332# CONFIG_SCSI_INIA100 is not set
333CONFIG_SCSI_PPA=m
334CONFIG_SCSI_IMM=m
335# CONFIG_SCSI_IZIP_EPP16 is not set
336# CONFIG_SCSI_IZIP_SLOW_CTR is not set
337# CONFIG_SCSI_NCR53C406A is not set
338CONFIG_SCSI_SYM53C8XX_2=y
339CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
340CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
341CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
342# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
343# CONFIG_SCSI_IPR is not set
344# CONFIG_SCSI_PAS16 is not set
345# CONFIG_SCSI_PSI240I is not set
346# CONFIG_SCSI_QLOGIC_FAS is not set
347# CONFIG_SCSI_QLOGIC_ISP is not set
348# CONFIG_SCSI_QLOGIC_FC is not set
349# CONFIG_SCSI_QLOGIC_1280 is not set
350CONFIG_SCSI_QLA2XXX=y
351# CONFIG_SCSI_QLA21XX is not set
352# CONFIG_SCSI_QLA22XX is not set
353# CONFIG_SCSI_QLA2300 is not set
354# CONFIG_SCSI_QLA2322 is not set
355# CONFIG_SCSI_QLA6312 is not set
356# CONFIG_SCSI_SYM53C416 is not set
357# CONFIG_SCSI_DC395x is not set
358# CONFIG_SCSI_DC390T is not set
359# CONFIG_SCSI_T128 is not set
360# CONFIG_SCSI_U14_34F is not set
361# CONFIG_SCSI_NSP32 is not set
362# CONFIG_SCSI_DEBUG is not set
363
364#
365# Old CD-ROM drivers (not SCSI, not IDE)
366#
367# CONFIG_CD_NO_IDESCSI is not set
368
369#
370# Multi-device support (RAID and LVM)
371#
372CONFIG_MD=y
373CONFIG_BLK_DEV_MD=m
374CONFIG_MD_LINEAR=m
375CONFIG_MD_RAID0=m
376CONFIG_MD_RAID1=m
377CONFIG_MD_RAID10=m
378CONFIG_MD_RAID5=m
379# CONFIG_MD_RAID6 is not set
380CONFIG_MD_MULTIPATH=m
381CONFIG_MD_FAULTY=m
382CONFIG_BLK_DEV_DM=m
383# CONFIG_DM_CRYPT is not set
384CONFIG_DM_SNAPSHOT=m
385CONFIG_DM_MIRROR=m
386CONFIG_DM_ZERO=m
387
388#
389# Fusion MPT device support
390#
391# CONFIG_FUSION is not set
392
393#
394# IEEE 1394 (FireWire) support
395#
396# CONFIG_IEEE1394 is not set
397
398#
399# I2O device support
400#
401# CONFIG_I2O is not set
402
403#
404# Networking support
405# 227#
406CONFIG_NET=y 228CONFIG_NET=y
407 229
@@ -410,12 +232,14 @@ CONFIG_NET=y
410# 232#
411CONFIG_PACKET=m 233CONFIG_PACKET=m
412CONFIG_PACKET_MMAP=y 234CONFIG_PACKET_MMAP=y
413CONFIG_NETLINK_DEV=m
414CONFIG_UNIX=y 235CONFIG_UNIX=y
236CONFIG_XFRM=y
237# CONFIG_XFRM_USER is not set
415CONFIG_NET_KEY=m 238CONFIG_NET_KEY=m
416CONFIG_INET=y 239CONFIG_INET=y
417CONFIG_IP_MULTICAST=y 240CONFIG_IP_MULTICAST=y
418# CONFIG_IP_ADVANCED_ROUTER is not set 241# CONFIG_IP_ADVANCED_ROUTER is not set
242CONFIG_IP_FIB_HASH=y
419# CONFIG_IP_PNP is not set 243# CONFIG_IP_PNP is not set
420CONFIG_NET_IPIP=m 244CONFIG_NET_IPIP=m
421CONFIG_NET_IPGRE=m 245CONFIG_NET_IPGRE=m
@@ -429,8 +253,10 @@ CONFIG_IP_PIMSM_V2=y
429# CONFIG_INET_ESP is not set 253# CONFIG_INET_ESP is not set
430# CONFIG_INET_IPCOMP is not set 254# CONFIG_INET_IPCOMP is not set
431CONFIG_INET_TUNNEL=m 255CONFIG_INET_TUNNEL=m
432CONFIG_IP_TCPDIAG=m 256CONFIG_INET_DIAG=y
433CONFIG_IP_TCPDIAG_IPV6=y 257CONFIG_INET_TCP_DIAG=y
258# CONFIG_TCP_CONG_ADVANCED is not set
259CONFIG_TCP_CONG_BIC=y
434 260
435# 261#
436# IP: Virtual Server Configuration 262# IP: Virtual Server Configuration
@@ -446,6 +272,9 @@ CONFIG_IPV6_TUNNEL=m
446CONFIG_NETFILTER=y 272CONFIG_NETFILTER=y
447# CONFIG_NETFILTER_DEBUG is not set 273# CONFIG_NETFILTER_DEBUG is not set
448CONFIG_BRIDGE_NETFILTER=y 274CONFIG_BRIDGE_NETFILTER=y
275CONFIG_NETFILTER_NETLINK=m
276CONFIG_NETFILTER_NETLINK_QUEUE=m
277CONFIG_NETFILTER_NETLINK_LOG=m
449 278
450# 279#
451# IP: Netfilter Configuration 280# IP: Netfilter Configuration
@@ -453,11 +282,15 @@ CONFIG_BRIDGE_NETFILTER=y
453CONFIG_IP_NF_CONNTRACK=m 282CONFIG_IP_NF_CONNTRACK=m
454# CONFIG_IP_NF_CT_ACCT is not set 283# CONFIG_IP_NF_CT_ACCT is not set
455CONFIG_IP_NF_CONNTRACK_MARK=y 284CONFIG_IP_NF_CONNTRACK_MARK=y
285CONFIG_IP_NF_CONNTRACK_EVENTS=y
286CONFIG_IP_NF_CONNTRACK_NETLINK=m
456CONFIG_IP_NF_CT_PROTO_SCTP=m 287CONFIG_IP_NF_CT_PROTO_SCTP=m
457CONFIG_IP_NF_FTP=m 288CONFIG_IP_NF_FTP=m
458CONFIG_IP_NF_IRC=m 289CONFIG_IP_NF_IRC=m
290# CONFIG_IP_NF_NETBIOS_NS is not set
459CONFIG_IP_NF_TFTP=m 291CONFIG_IP_NF_TFTP=m
460CONFIG_IP_NF_AMANDA=m 292CONFIG_IP_NF_AMANDA=m
293CONFIG_IP_NF_PPTP=m
461CONFIG_IP_NF_QUEUE=m 294CONFIG_IP_NF_QUEUE=m
462CONFIG_IP_NF_IPTABLES=m 295CONFIG_IP_NF_IPTABLES=m
463CONFIG_IP_NF_MATCH_LIMIT=m 296CONFIG_IP_NF_MATCH_LIMIT=m
@@ -482,9 +315,11 @@ CONFIG_IP_NF_MATCH_PHYSDEV=m
482CONFIG_IP_NF_MATCH_ADDRTYPE=m 315CONFIG_IP_NF_MATCH_ADDRTYPE=m
483CONFIG_IP_NF_MATCH_REALM=m 316CONFIG_IP_NF_MATCH_REALM=m
484CONFIG_IP_NF_MATCH_SCTP=m 317CONFIG_IP_NF_MATCH_SCTP=m
318CONFIG_IP_NF_MATCH_DCCP=m
485CONFIG_IP_NF_MATCH_COMMENT=m 319CONFIG_IP_NF_MATCH_COMMENT=m
486CONFIG_IP_NF_MATCH_CONNMARK=m 320CONFIG_IP_NF_MATCH_CONNMARK=m
487CONFIG_IP_NF_MATCH_HASHLIMIT=m 321CONFIG_IP_NF_MATCH_HASHLIMIT=m
322CONFIG_IP_NF_MATCH_STRING=m
488CONFIG_IP_NF_FILTER=m 323CONFIG_IP_NF_FILTER=m
489CONFIG_IP_NF_TARGET_REJECT=m 324CONFIG_IP_NF_TARGET_REJECT=m
490CONFIG_IP_NF_TARGET_LOG=m 325CONFIG_IP_NF_TARGET_LOG=m
@@ -501,12 +336,14 @@ CONFIG_IP_NF_NAT_IRC=m
501CONFIG_IP_NF_NAT_FTP=m 336CONFIG_IP_NF_NAT_FTP=m
502CONFIG_IP_NF_NAT_TFTP=m 337CONFIG_IP_NF_NAT_TFTP=m
503CONFIG_IP_NF_NAT_AMANDA=m 338CONFIG_IP_NF_NAT_AMANDA=m
339CONFIG_IP_NF_NAT_PPTP=m
504CONFIG_IP_NF_MANGLE=m 340CONFIG_IP_NF_MANGLE=m
505CONFIG_IP_NF_TARGET_TOS=m 341CONFIG_IP_NF_TARGET_TOS=m
506CONFIG_IP_NF_TARGET_ECN=m 342CONFIG_IP_NF_TARGET_ECN=m
507CONFIG_IP_NF_TARGET_DSCP=m 343CONFIG_IP_NF_TARGET_DSCP=m
508CONFIG_IP_NF_TARGET_MARK=m 344CONFIG_IP_NF_TARGET_MARK=m
509CONFIG_IP_NF_TARGET_CLASSIFY=m 345CONFIG_IP_NF_TARGET_CLASSIFY=m
346CONFIG_IP_NF_TARGET_TTL=m
510CONFIG_IP_NF_TARGET_CONNMARK=m 347CONFIG_IP_NF_TARGET_CONNMARK=m
511CONFIG_IP_NF_TARGET_CLUSTERIP=m 348CONFIG_IP_NF_TARGET_CLUSTERIP=m
512CONFIG_IP_NF_RAW=m 349CONFIG_IP_NF_RAW=m
@@ -516,7 +353,7 @@ CONFIG_IP_NF_ARPFILTER=m
516CONFIG_IP_NF_ARP_MANGLE=m 353CONFIG_IP_NF_ARP_MANGLE=m
517 354
518# 355#
519# IPv6: Netfilter Configuration 356# IPv6: Netfilter Configuration (EXPERIMENTAL)
520# 357#
521CONFIG_IP6_NF_QUEUE=m 358CONFIG_IP6_NF_QUEUE=m
522CONFIG_IP6_NF_IPTABLES=m 359CONFIG_IP6_NF_IPTABLES=m
@@ -536,8 +373,10 @@ CONFIG_IP6_NF_MATCH_EUI64=m
536CONFIG_IP6_NF_MATCH_PHYSDEV=m 373CONFIG_IP6_NF_MATCH_PHYSDEV=m
537CONFIG_IP6_NF_FILTER=m 374CONFIG_IP6_NF_FILTER=m
538CONFIG_IP6_NF_TARGET_LOG=m 375CONFIG_IP6_NF_TARGET_LOG=m
376CONFIG_IP6_NF_TARGET_REJECT=m
539CONFIG_IP6_NF_MANGLE=m 377CONFIG_IP6_NF_MANGLE=m
540CONFIG_IP6_NF_TARGET_MARK=m 378CONFIG_IP6_NF_TARGET_MARK=m
379CONFIG_IP6_NF_TARGET_HL=m
541CONFIG_IP6_NF_RAW=m 380CONFIG_IP6_NF_RAW=m
542 381
543# 382#
@@ -567,9 +406,12 @@ CONFIG_BRIDGE_EBT_MARK_T=m
567CONFIG_BRIDGE_EBT_REDIRECT=m 406CONFIG_BRIDGE_EBT_REDIRECT=m
568CONFIG_BRIDGE_EBT_SNAT=m 407CONFIG_BRIDGE_EBT_SNAT=m
569CONFIG_BRIDGE_EBT_LOG=m 408CONFIG_BRIDGE_EBT_LOG=m
570# CONFIG_BRIDGE_EBT_ULOG is not set 409CONFIG_BRIDGE_EBT_ULOG=m
571CONFIG_XFRM=y 410
572# CONFIG_XFRM_USER is not set 411#
412# DCCP Configuration (EXPERIMENTAL)
413#
414# CONFIG_IP_DCCP is not set
573 415
574# 416#
575# SCTP Configuration (EXPERIMENTAL) 417# SCTP Configuration (EXPERIMENTAL)
@@ -588,10 +430,6 @@ CONFIG_DECNET=m
588# CONFIG_NET_DIVERT is not set 430# CONFIG_NET_DIVERT is not set
589# CONFIG_ECONET is not set 431# CONFIG_ECONET is not set
590# CONFIG_WAN_ROUTER is not set 432# CONFIG_WAN_ROUTER is not set
591
592#
593# QoS and/or fair queueing
594#
595CONFIG_NET_SCHED=y 433CONFIG_NET_SCHED=y
596CONFIG_NET_SCH_CLK_JIFFIES=y 434CONFIG_NET_SCH_CLK_JIFFIES=y
597# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set 435# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
@@ -611,6 +449,7 @@ CONFIG_NET_SCH_INGRESS=m
611CONFIG_NET_QOS=y 449CONFIG_NET_QOS=y
612CONFIG_NET_ESTIMATOR=y 450CONFIG_NET_ESTIMATOR=y
613CONFIG_NET_CLS=y 451CONFIG_NET_CLS=y
452CONFIG_NET_CLS_BASIC=m
614CONFIG_NET_CLS_TCINDEX=m 453CONFIG_NET_CLS_TCINDEX=m
615CONFIG_NET_CLS_ROUTE4=m 454CONFIG_NET_CLS_ROUTE4=m
616CONFIG_NET_CLS_ROUTE=y 455CONFIG_NET_CLS_ROUTE=y
@@ -621,6 +460,7 @@ CONFIG_NET_CLS_U32=m
621# CONFIG_CLS_U32_MARK is not set 460# CONFIG_CLS_U32_MARK is not set
622CONFIG_NET_CLS_RSVP=m 461CONFIG_NET_CLS_RSVP=m
623CONFIG_NET_CLS_RSVP6=m 462CONFIG_NET_CLS_RSVP6=m
463# CONFIG_NET_EMATCH is not set
624# CONFIG_NET_CLS_ACT is not set 464# CONFIG_NET_CLS_ACT is not set
625CONFIG_NET_CLS_POLICE=y 465CONFIG_NET_CLS_POLICE=y
626 466
@@ -628,8 +468,6 @@ CONFIG_NET_CLS_POLICE=y
628# Network testing 468# Network testing
629# 469#
630# CONFIG_NET_PKTGEN is not set 470# CONFIG_NET_PKTGEN is not set
631# CONFIG_NETPOLL is not set
632# CONFIG_NET_POLL_CONTROLLER is not set
633CONFIG_HAMRADIO=y 471CONFIG_HAMRADIO=y
634 472
635# 473#
@@ -646,8 +484,6 @@ CONFIG_ROSE=m
646CONFIG_MKISS=m 484CONFIG_MKISS=m
647CONFIG_6PACK=m 485CONFIG_6PACK=m
648CONFIG_BPQETHER=m 486CONFIG_BPQETHER=m
649# CONFIG_DMASCC is not set
650# CONFIG_SCC is not set
651# CONFIG_BAYCOM_SER_FDX is not set 487# CONFIG_BAYCOM_SER_FDX is not set
652# CONFIG_BAYCOM_SER_HDX is not set 488# CONFIG_BAYCOM_SER_HDX is not set
653# CONFIG_BAYCOM_PAR is not set 489# CONFIG_BAYCOM_PAR is not set
@@ -655,12 +491,257 @@ CONFIG_BPQETHER=m
655# CONFIG_YAM is not set 491# CONFIG_YAM is not set
656# CONFIG_IRDA is not set 492# CONFIG_IRDA is not set
657# CONFIG_BT is not set 493# CONFIG_BT is not set
494CONFIG_IEEE80211=m
495# CONFIG_IEEE80211_DEBUG is not set
496CONFIG_IEEE80211_CRYPT_WEP=m
497CONFIG_IEEE80211_CRYPT_CCMP=m
498CONFIG_IEEE80211_CRYPT_TKIP=m
499
500#
501# Device Drivers
502#
503
504#
505# Generic Driver Options
506#
507CONFIG_STANDALONE=y
508CONFIG_PREVENT_FIRMWARE_BUILD=y
509CONFIG_FW_LOADER=m
510
511#
512# Connector - unified userspace <-> kernelspace linker
513#
514CONFIG_CONNECTOR=m
515
516#
517# Memory Technology Devices (MTD)
518#
519# CONFIG_MTD is not set
520
521#
522# Parallel port support
523#
524CONFIG_PARPORT=m
525CONFIG_PARPORT_PC=m
526CONFIG_PARPORT_SERIAL=m
527# CONFIG_PARPORT_PC_FIFO is not set
528# CONFIG_PARPORT_PC_SUPERIO is not set
529CONFIG_PARPORT_NOT_PC=y
530# CONFIG_PARPORT_GSC is not set
531CONFIG_PARPORT_1284=y
532
533#
534# Plug and Play support
535#
536# CONFIG_PNP is not set
537
538#
539# Block devices
540#
541CONFIG_BLK_DEV_FD=m
542CONFIG_PARIDE=m
543CONFIG_PARIDE_PARPORT=m
544
545#
546# Parallel IDE high-level drivers
547#
548CONFIG_PARIDE_PD=m
549CONFIG_PARIDE_PCD=m
550CONFIG_PARIDE_PF=m
551CONFIG_PARIDE_PT=m
552CONFIG_PARIDE_PG=m
553
554#
555# Parallel IDE protocol modules
556#
557CONFIG_PARIDE_ATEN=m
558CONFIG_PARIDE_BPCK=m
559CONFIG_PARIDE_BPCK6=m
560CONFIG_PARIDE_COMM=m
561CONFIG_PARIDE_DSTR=m
562CONFIG_PARIDE_FIT2=m
563CONFIG_PARIDE_FIT3=m
564CONFIG_PARIDE_EPAT=m
565# CONFIG_PARIDE_EPATC8 is not set
566CONFIG_PARIDE_EPIA=m
567CONFIG_PARIDE_FRIQ=m
568CONFIG_PARIDE_FRPW=m
569CONFIG_PARIDE_KBIC=m
570CONFIG_PARIDE_KTTI=m
571CONFIG_PARIDE_ON20=m
572CONFIG_PARIDE_ON26=m
573# CONFIG_BLK_CPQ_DA is not set
574# CONFIG_BLK_CPQ_CISS_DA is not set
575# CONFIG_BLK_DEV_DAC960 is not set
576# CONFIG_BLK_DEV_UMEM is not set
577# CONFIG_BLK_DEV_COW_COMMON is not set
578CONFIG_BLK_DEV_LOOP=m
579CONFIG_BLK_DEV_CRYPTOLOOP=m
580CONFIG_BLK_DEV_NBD=m
581CONFIG_BLK_DEV_SX8=m
582CONFIG_BLK_DEV_UB=m
583CONFIG_BLK_DEV_RAM=m
584CONFIG_BLK_DEV_RAM_COUNT=16
585CONFIG_BLK_DEV_RAM_SIZE=4096
586# CONFIG_LBD is not set
587CONFIG_CDROM_PKTCDVD=m
588CONFIG_CDROM_PKTCDVD_BUFFERS=8
589# CONFIG_CDROM_PKTCDVD_WCACHE is not set
590
591#
592# IO Schedulers
593#
594CONFIG_IOSCHED_NOOP=y
595CONFIG_IOSCHED_AS=y
596CONFIG_IOSCHED_DEADLINE=y
597CONFIG_IOSCHED_CFQ=y
598CONFIG_ATA_OVER_ETH=m
599
600#
601# ATA/ATAPI/MFM/RLL support
602#
603# CONFIG_IDE is not set
604
605#
606# SCSI device support
607#
608CONFIG_RAID_ATTRS=m
609CONFIG_SCSI=y
610CONFIG_SCSI_PROC_FS=y
611
612#
613# SCSI support type (disk, tape, CD-ROM)
614#
615CONFIG_BLK_DEV_SD=y
616CONFIG_CHR_DEV_ST=m
617# CONFIG_CHR_DEV_OSST is not set
618CONFIG_BLK_DEV_SR=m
619CONFIG_BLK_DEV_SR_VENDOR=y
620# CONFIG_CHR_DEV_SG is not set
621# CONFIG_CHR_DEV_SCH is not set
622
623#
624# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
625#
626# CONFIG_SCSI_MULTI_LUN is not set
627CONFIG_SCSI_CONSTANTS=y
628# CONFIG_SCSI_LOGGING is not set
629
630#
631# SCSI Transport Attributes
632#
633CONFIG_SCSI_SPI_ATTRS=y
634# CONFIG_SCSI_FC_ATTRS is not set
635CONFIG_SCSI_ISCSI_ATTRS=m
636CONFIG_SCSI_SAS_ATTRS=m
637
638#
639# SCSI low-level drivers
640#
641# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
642# CONFIG_SCSI_3W_9XXX is not set
643# CONFIG_SCSI_ACARD is not set
644# CONFIG_SCSI_AHA152X is not set
645# CONFIG_SCSI_AACRAID is not set
646# CONFIG_SCSI_AIC7XXX is not set
647# CONFIG_SCSI_AIC7XXX_OLD is not set
648# CONFIG_SCSI_AIC79XX is not set
649# CONFIG_SCSI_DPT_I2O is not set
650# CONFIG_SCSI_IN2000 is not set
651CONFIG_MEGARAID_NEWGEN=y
652CONFIG_MEGARAID_MM=m
653CONFIG_MEGARAID_MAILBOX=m
654# CONFIG_SCSI_SATA is not set
655# CONFIG_SCSI_DMX3191D is not set
656# CONFIG_SCSI_DTC3280 is not set
657# CONFIG_SCSI_FUTURE_DOMAIN is not set
658# CONFIG_SCSI_GENERIC_NCR5380 is not set
659# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
660# CONFIG_SCSI_IPS is not set
661# CONFIG_SCSI_INITIO is not set
662# CONFIG_SCSI_INIA100 is not set
663CONFIG_SCSI_PPA=m
664CONFIG_SCSI_IMM=m
665# CONFIG_SCSI_IZIP_EPP16 is not set
666# CONFIG_SCSI_IZIP_SLOW_CTR is not set
667# CONFIG_SCSI_NCR53C406A is not set
668CONFIG_SCSI_SYM53C8XX_2=y
669CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
670CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
671CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
672# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
673# CONFIG_SCSI_IPR is not set
674# CONFIG_SCSI_PAS16 is not set
675# CONFIG_SCSI_PSI240I is not set
676# CONFIG_SCSI_QLOGIC_FAS is not set
677# CONFIG_SCSI_QLOGIC_FC is not set
678# CONFIG_SCSI_QLOGIC_1280 is not set
679CONFIG_SCSI_QLA2XXX=y
680# CONFIG_SCSI_QLA21XX is not set
681# CONFIG_SCSI_QLA22XX is not set
682# CONFIG_SCSI_QLA2300 is not set
683# CONFIG_SCSI_QLA2322 is not set
684# CONFIG_SCSI_QLA6312 is not set
685# CONFIG_SCSI_QLA24XX is not set
686# CONFIG_SCSI_LPFC is not set
687# CONFIG_SCSI_SYM53C416 is not set
688# CONFIG_SCSI_DC395x is not set
689# CONFIG_SCSI_DC390T is not set
690# CONFIG_SCSI_T128 is not set
691# CONFIG_SCSI_NSP32 is not set
692# CONFIG_SCSI_DEBUG is not set
693
694#
695# Old CD-ROM drivers (not SCSI, not IDE)
696#
697# CONFIG_CD_NO_IDESCSI is not set
698
699#
700# Multi-device support (RAID and LVM)
701#
702CONFIG_MD=y
703CONFIG_BLK_DEV_MD=m
704CONFIG_MD_LINEAR=m
705CONFIG_MD_RAID0=m
706CONFIG_MD_RAID1=m
707CONFIG_MD_RAID10=m
708CONFIG_MD_RAID5=m
709# CONFIG_MD_RAID6 is not set
710CONFIG_MD_MULTIPATH=m
711CONFIG_MD_FAULTY=m
712CONFIG_BLK_DEV_DM=m
713# CONFIG_DM_CRYPT is not set
714CONFIG_DM_SNAPSHOT=m
715CONFIG_DM_MIRROR=m
716CONFIG_DM_ZERO=m
717CONFIG_DM_MULTIPATH=m
718CONFIG_DM_MULTIPATH_EMC=m
719
720#
721# Fusion MPT device support
722#
723# CONFIG_FUSION is not set
724# CONFIG_FUSION_SPI is not set
725# CONFIG_FUSION_FC is not set
726
727#
728# IEEE 1394 (FireWire) support
729#
730# CONFIG_IEEE1394 is not set
731
732#
733# I2O device support
734#
735# CONFIG_I2O is not set
736
737#
738# Network device support
739#
658CONFIG_NETDEVICES=y 740CONFIG_NETDEVICES=y
659CONFIG_DUMMY=m 741CONFIG_DUMMY=m
660CONFIG_BONDING=m 742CONFIG_BONDING=m
661CONFIG_EQUALIZER=m 743CONFIG_EQUALIZER=m
662CONFIG_TUN=m 744CONFIG_TUN=m
663CONFIG_ETHERTAP=m
664 745
665# 746#
666# ARCnet devices 747# ARCnet devices
@@ -668,6 +749,21 @@ CONFIG_ETHERTAP=m
668# CONFIG_ARCNET is not set 749# CONFIG_ARCNET is not set
669 750
670# 751#
752# PHY device support
753#
754CONFIG_PHYLIB=m
755CONFIG_PHYCONTROL=y
756
757#
758# MII PHY device drivers
759#
760CONFIG_MARVELL_PHY=m
761CONFIG_DAVICOM_PHY=m
762CONFIG_QSEMI_PHY=m
763CONFIG_LXT_PHY=m
764CONFIG_CICADA_PHY=m
765
766#
671# Ethernet (10 or 100Mbit) 767# Ethernet (10 or 100Mbit)
672# 768#
673CONFIG_NET_ETHERNET=y 769CONFIG_NET_ETHERNET=y
@@ -675,7 +771,6 @@ CONFIG_MII=y
675# CONFIG_HAPPYMEAL is not set 771# CONFIG_HAPPYMEAL is not set
676# CONFIG_SUNGEM is not set 772# CONFIG_SUNGEM is not set
677# CONFIG_NET_VENDOR_3COM is not set 773# CONFIG_NET_VENDOR_3COM is not set
678# CONFIG_LANCE is not set
679# CONFIG_NET_VENDOR_SMC is not set 774# CONFIG_NET_VENDOR_SMC is not set
680# CONFIG_NET_VENDOR_RACAL is not set 775# CONFIG_NET_VENDOR_RACAL is not set
681 776
@@ -696,7 +791,6 @@ CONFIG_NET_ISA=y
696# CONFIG_LP486E is not set 791# CONFIG_LP486E is not set
697# CONFIG_ETH16I is not set 792# CONFIG_ETH16I is not set
698CONFIG_NE2000=m 793CONFIG_NE2000=m
699# CONFIG_ZNET is not set
700# CONFIG_SEEQ8005 is not set 794# CONFIG_SEEQ8005 is not set
701CONFIG_NET_PCI=y 795CONFIG_NET_PCI=y
702CONFIG_PCNET32=y 796CONFIG_PCNET32=y
@@ -733,13 +827,17 @@ CONFIG_EEPRO100=m
733# CONFIG_HAMACHI is not set 827# CONFIG_HAMACHI is not set
734# CONFIG_YELLOWFIN is not set 828# CONFIG_YELLOWFIN is not set
735# CONFIG_R8169 is not set 829# CONFIG_R8169 is not set
830# CONFIG_SIS190 is not set
831# CONFIG_SKGE is not set
736# CONFIG_SK98LIN is not set 832# CONFIG_SK98LIN is not set
737CONFIG_VIA_VELOCITY=m 833CONFIG_VIA_VELOCITY=m
738# CONFIG_TIGON3 is not set 834# CONFIG_TIGON3 is not set
835# CONFIG_BNX2 is not set
739 836
740# 837#
741# Ethernet (10000 Mbit) 838# Ethernet (10000 Mbit)
742# 839#
840# CONFIG_CHELSIO_T1 is not set
743# CONFIG_IXGB is not set 841# CONFIG_IXGB is not set
744# CONFIG_S2IO is not set 842# CONFIG_S2IO is not set
745 843
@@ -752,6 +850,8 @@ CONFIG_VIA_VELOCITY=m
752# Wireless LAN (non-hamradio) 850# Wireless LAN (non-hamradio)
753# 851#
754# CONFIG_NET_RADIO is not set 852# CONFIG_NET_RADIO is not set
853# CONFIG_IPW_DEBUG is not set
854CONFIG_IPW2200=m
755 855
756# 856#
757# Wan interfaces 857# Wan interfaces
@@ -765,6 +865,8 @@ CONFIG_PLIP=m
765# CONFIG_NET_FC is not set 865# CONFIG_NET_FC is not set
766# CONFIG_SHAPER is not set 866# CONFIG_SHAPER is not set
767# CONFIG_NETCONSOLE is not set 867# CONFIG_NETCONSOLE is not set
868# CONFIG_NETPOLL is not set
869# CONFIG_NET_POLL_CONTROLLER is not set
768 870
769# 871#
770# ISDN subsystem 872# ISDN subsystem
@@ -794,20 +896,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
794# CONFIG_INPUT_EVBUG is not set 896# CONFIG_INPUT_EVBUG is not set
795 897
796# 898#
797# Input I/O drivers
798#
799# CONFIG_GAMEPORT is not set
800CONFIG_SOUND_GAMEPORT=y
801CONFIG_SERIO=y
802CONFIG_SERIO_I8042=y
803CONFIG_SERIO_SERPORT=y
804# CONFIG_SERIO_CT82C710 is not set
805CONFIG_SERIO_PARKBD=m
806# CONFIG_SERIO_PCIPS2 is not set
807CONFIG_SERIO_LIBPS2=y
808CONFIG_SERIO_RAW=m
809
810#
811# Input Device Drivers 899# Input Device Drivers
812# 900#
813CONFIG_INPUT_KEYBOARD=y 901CONFIG_INPUT_KEYBOARD=y
@@ -828,6 +916,18 @@ CONFIG_MOUSE_PS2=y
828# CONFIG_INPUT_MISC is not set 916# CONFIG_INPUT_MISC is not set
829 917
830# 918#
919# Hardware I/O ports
920#
921CONFIG_SERIO=y
922CONFIG_SERIO_I8042=y
923CONFIG_SERIO_SERPORT=y
924CONFIG_SERIO_PARKBD=m
925# CONFIG_SERIO_PCIPS2 is not set
926CONFIG_SERIO_LIBPS2=y
927CONFIG_SERIO_RAW=m
928# CONFIG_GAMEPORT is not set
929
930#
831# Character devices 931# Character devices
832# 932#
833CONFIG_VT=y 933CONFIG_VT=y
@@ -844,13 +944,13 @@ CONFIG_SERIAL_8250_EXTENDED=y
844# CONFIG_SERIAL_8250_MANY_PORTS is not set 944# CONFIG_SERIAL_8250_MANY_PORTS is not set
845CONFIG_SERIAL_8250_SHARE_IRQ=y 945CONFIG_SERIAL_8250_SHARE_IRQ=y
846CONFIG_SERIAL_8250_DETECT_IRQ=y 946CONFIG_SERIAL_8250_DETECT_IRQ=y
847CONFIG_SERIAL_8250_MULTIPORT=y
848CONFIG_SERIAL_8250_RSA=y 947CONFIG_SERIAL_8250_RSA=y
849 948
850# 949#
851# Non-8250 serial port support 950# Non-8250 serial port support
852# 951#
853CONFIG_SERIAL_CORE=m 952CONFIG_SERIAL_CORE=m
953# CONFIG_SERIAL_JSM is not set
854CONFIG_UNIX98_PTYS=y 954CONFIG_UNIX98_PTYS=y
855CONFIG_LEGACY_PTYS=y 955CONFIG_LEGACY_PTYS=y
856CONFIG_LEGACY_PTY_COUNT=256 956CONFIG_LEGACY_PTY_COUNT=256
@@ -881,6 +981,11 @@ CONFIG_RTC=m
881# CONFIG_RAW_DRIVER is not set 981# CONFIG_RAW_DRIVER is not set
882 982
883# 983#
984# TPM devices
985#
986# CONFIG_TCG_TPM is not set
987
988#
884# I2C support 989# I2C support
885# 990#
886# CONFIG_I2C is not set 991# CONFIG_I2C is not set
@@ -891,15 +996,26 @@ CONFIG_RTC=m
891CONFIG_W1=m 996CONFIG_W1=m
892CONFIG_W1_MATROX=m 997CONFIG_W1_MATROX=m
893CONFIG_W1_DS9490=m 998CONFIG_W1_DS9490=m
894CONFIG_W1_DS9490_BRIDGE=m 999# CONFIG_W1_DS9490_BRIDGE is not set
895CONFIG_W1_THERM=m 1000CONFIG_W1_THERM=m
896CONFIG_W1_SMEM=m 1001CONFIG_W1_SMEM=m
1002# CONFIG_W1_DS2433 is not set
1003
1004#
1005# Hardware Monitoring support
1006#
1007# CONFIG_HWMON is not set
1008# CONFIG_HWMON_VID is not set
897 1009
898# 1010#
899# Misc devices 1011# Misc devices
900# 1012#
901 1013
902# 1014#
1015# Multimedia Capabilities Port drivers
1016#
1017
1018#
903# Multimedia devices 1019# Multimedia devices
904# 1020#
905# CONFIG_VIDEO_DEV is not set 1021# CONFIG_VIDEO_DEV is not set
@@ -920,7 +1036,6 @@ CONFIG_W1_SMEM=m
920CONFIG_VGA_CONSOLE=y 1036CONFIG_VGA_CONSOLE=y
921# CONFIG_MDA_CONSOLE is not set 1037# CONFIG_MDA_CONSOLE is not set
922CONFIG_DUMMY_CONSOLE=y 1038CONFIG_DUMMY_CONSOLE=y
923# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
924 1039
925# 1040#
926# Sound 1041# Sound
@@ -930,6 +1045,8 @@ CONFIG_DUMMY_CONSOLE=y
930# 1045#
931# USB support 1046# USB support
932# 1047#
1048CONFIG_USB_ARCH_HAS_HCD=y
1049CONFIG_USB_ARCH_HAS_OHCI=y
933CONFIG_USB=m 1050CONFIG_USB=m
934# CONFIG_USB_DEBUG is not set 1051# CONFIG_USB_DEBUG is not set
935 1052
@@ -940,8 +1057,6 @@ CONFIG_USB_DEVICEFS=y
940# CONFIG_USB_BANDWIDTH is not set 1057# CONFIG_USB_BANDWIDTH is not set
941# CONFIG_USB_DYNAMIC_MINORS is not set 1058# CONFIG_USB_DYNAMIC_MINORS is not set
942# CONFIG_USB_OTG is not set 1059# CONFIG_USB_OTG is not set
943CONFIG_USB_ARCH_HAS_HCD=y
944CONFIG_USB_ARCH_HAS_OHCI=y
945 1060
946# 1061#
947# USB Host Controller Drivers 1062# USB Host Controller Drivers
@@ -949,7 +1064,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y
949CONFIG_USB_EHCI_HCD=m 1064CONFIG_USB_EHCI_HCD=m
950# CONFIG_USB_EHCI_SPLIT_ISO is not set 1065# CONFIG_USB_EHCI_SPLIT_ISO is not set
951# CONFIG_USB_EHCI_ROOT_HUB_TT is not set 1066# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
1067# CONFIG_USB_ISP116X_HCD is not set
952CONFIG_USB_OHCI_HCD=m 1068CONFIG_USB_OHCI_HCD=m
1069# CONFIG_USB_OHCI_BIG_ENDIAN is not set
1070CONFIG_USB_OHCI_LITTLE_ENDIAN=y
953CONFIG_USB_UHCI_HCD=m 1071CONFIG_USB_UHCI_HCD=m
954# CONFIG_USB_SL811_HCD is not set 1072# CONFIG_USB_SL811_HCD is not set
955 1073
@@ -965,11 +1083,10 @@ CONFIG_USB_PRINTER=m
965# 1083#
966CONFIG_USB_STORAGE=m 1084CONFIG_USB_STORAGE=m
967# CONFIG_USB_STORAGE_DEBUG is not set 1085# CONFIG_USB_STORAGE_DEBUG is not set
968# CONFIG_USB_STORAGE_RW_DETECT is not set
969CONFIG_USB_STORAGE_DATAFAB=y 1086CONFIG_USB_STORAGE_DATAFAB=y
970CONFIG_USB_STORAGE_FREECOM=y 1087CONFIG_USB_STORAGE_FREECOM=y
971CONFIG_USB_STORAGE_DPCM=y 1088CONFIG_USB_STORAGE_DPCM=y
972CONFIG_USB_STORAGE_HP8200e=y 1089# CONFIG_USB_STORAGE_USBAT is not set
973CONFIG_USB_STORAGE_SDDR09=y 1090CONFIG_USB_STORAGE_SDDR09=y
974CONFIG_USB_STORAGE_SDDR55=y 1091CONFIG_USB_STORAGE_SDDR55=y
975CONFIG_USB_STORAGE_JUMPSHOT=y 1092CONFIG_USB_STORAGE_JUMPSHOT=y
@@ -992,12 +1109,17 @@ CONFIG_USB_KBD=m
992CONFIG_USB_MOUSE=m 1109CONFIG_USB_MOUSE=m
993CONFIG_USB_AIPTEK=m 1110CONFIG_USB_AIPTEK=m
994CONFIG_USB_WACOM=m 1111CONFIG_USB_WACOM=m
1112# CONFIG_USB_ACECAD is not set
995CONFIG_USB_KBTAB=m 1113CONFIG_USB_KBTAB=m
996CONFIG_USB_POWERMATE=m 1114CONFIG_USB_POWERMATE=m
997# CONFIG_USB_MTOUCH is not set 1115# CONFIG_USB_MTOUCH is not set
1116# CONFIG_USB_ITMTOUCH is not set
998CONFIG_USB_EGALAX=m 1117CONFIG_USB_EGALAX=m
1118CONFIG_USB_YEALINK=m
999CONFIG_USB_XPAD=m 1119CONFIG_USB_XPAD=m
1000# CONFIG_USB_ATI_REMOTE is not set 1120# CONFIG_USB_ATI_REMOTE is not set
1121# CONFIG_USB_KEYSPAN_REMOTE is not set
1122# CONFIG_USB_APPLETOUCH is not set
1001 1123
1002# 1124#
1003# USB Imaging devices 1125# USB Imaging devices
@@ -1022,30 +1144,15 @@ CONFIG_USB_KAWETH=m
1022CONFIG_USB_PEGASUS=m 1144CONFIG_USB_PEGASUS=m
1023CONFIG_USB_RTL8150=m 1145CONFIG_USB_RTL8150=m
1024CONFIG_USB_USBNET=m 1146CONFIG_USB_USBNET=m
1025 1147CONFIG_USB_NET_AX8817X=m
1026# 1148CONFIG_USB_NET_CDCETHER=m
1027# USB Host-to-Host Cables 1149# CONFIG_USB_NET_GL620A is not set
1028# 1150CONFIG_USB_NET_NET1080=m
1029CONFIG_USB_ALI_M5632=y 1151# CONFIG_USB_NET_PLUSB is not set
1030CONFIG_USB_AN2720=y 1152# CONFIG_USB_NET_RNDIS_HOST is not set
1031CONFIG_USB_BELKIN=y 1153# CONFIG_USB_NET_CDC_SUBSET is not set
1032CONFIG_USB_GENESYS=y 1154CONFIG_USB_NET_ZAURUS=m
1033CONFIG_USB_NET1080=y 1155CONFIG_USB_MON=y
1034CONFIG_USB_PL2301=y
1035CONFIG_USB_KC2190=y
1036
1037#
1038# Intelligent USB Devices/Gadgets
1039#
1040CONFIG_USB_ARMLINUX=y
1041CONFIG_USB_EPSON2888=y
1042CONFIG_USB_ZAURUS=y
1043CONFIG_USB_CDCETHER=y
1044
1045#
1046# USB Network Adapters
1047#
1048CONFIG_USB_AX8817X=y
1049 1156
1050# 1157#
1051# USB port drivers 1158# USB port drivers
@@ -1057,9 +1164,11 @@ CONFIG_USB_USS720=m
1057# 1164#
1058CONFIG_USB_SERIAL=m 1165CONFIG_USB_SERIAL=m
1059CONFIG_USB_SERIAL_GENERIC=y 1166CONFIG_USB_SERIAL_GENERIC=y
1167CONFIG_USB_SERIAL_AIRPRIME=m
1060CONFIG_USB_SERIAL_BELKIN=m 1168CONFIG_USB_SERIAL_BELKIN=m
1061CONFIG_USB_SERIAL_WHITEHEAT=m 1169CONFIG_USB_SERIAL_WHITEHEAT=m
1062CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m 1170CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1171# CONFIG_USB_SERIAL_CP2101 is not set
1063CONFIG_USB_SERIAL_CYPRESS_M8=m 1172CONFIG_USB_SERIAL_CYPRESS_M8=m
1064CONFIG_USB_SERIAL_EMPEG=m 1173CONFIG_USB_SERIAL_EMPEG=m
1065CONFIG_USB_SERIAL_FTDI_SIO=m 1174CONFIG_USB_SERIAL_FTDI_SIO=m
@@ -1088,6 +1197,7 @@ CONFIG_USB_SERIAL_KLSI=m
1088CONFIG_USB_SERIAL_KOBIL_SCT=m 1197CONFIG_USB_SERIAL_KOBIL_SCT=m
1089CONFIG_USB_SERIAL_MCT_U232=m 1198CONFIG_USB_SERIAL_MCT_U232=m
1090CONFIG_USB_SERIAL_PL2303=m 1199CONFIG_USB_SERIAL_PL2303=m
1200CONFIG_USB_SERIAL_HP4X=m
1091CONFIG_USB_SERIAL_SAFE=m 1201CONFIG_USB_SERIAL_SAFE=m
1092CONFIG_USB_SERIAL_SAFE_PADDED=y 1202CONFIG_USB_SERIAL_SAFE_PADDED=y
1093# CONFIG_USB_SERIAL_TI is not set 1203# CONFIG_USB_SERIAL_TI is not set
@@ -1110,10 +1220,13 @@ CONFIG_USB_CYTHERM=m
1110CONFIG_USB_PHIDGETKIT=m 1220CONFIG_USB_PHIDGETKIT=m
1111CONFIG_USB_PHIDGETSERVO=m 1221CONFIG_USB_PHIDGETSERVO=m
1112# CONFIG_USB_IDMOUSE is not set 1222# CONFIG_USB_IDMOUSE is not set
1223CONFIG_USB_SISUSBVGA=m
1224# CONFIG_USB_SISUSBVGA_CON is not set
1225CONFIG_USB_LD=m
1113CONFIG_USB_TEST=m 1226CONFIG_USB_TEST=m
1114 1227
1115# 1228#
1116# USB ATM/DSL drivers 1229# USB DSL modem support
1117# 1230#
1118 1231
1119# 1232#
@@ -1132,10 +1245,15 @@ CONFIG_USB_TEST=m
1132# CONFIG_INFINIBAND is not set 1245# CONFIG_INFINIBAND is not set
1133 1246
1134# 1247#
1248# SN Devices
1249#
1250
1251#
1135# File systems 1252# File systems
1136# 1253#
1137CONFIG_EXT2_FS=m 1254CONFIG_EXT2_FS=m
1138# CONFIG_EXT2_FS_XATTR is not set 1255# CONFIG_EXT2_FS_XATTR is not set
1256# CONFIG_EXT2_FS_XIP is not set
1139CONFIG_EXT3_FS=y 1257CONFIG_EXT3_FS=y
1140CONFIG_EXT3_FS_XATTR=y 1258CONFIG_EXT3_FS_XATTR=y
1141# CONFIG_EXT3_FS_POSIX_ACL is not set 1259# CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -1152,17 +1270,20 @@ CONFIG_REISERFS_FS_SECURITY=y
1152# CONFIG_JFS_FS is not set 1270# CONFIG_JFS_FS is not set
1153CONFIG_FS_POSIX_ACL=y 1271CONFIG_FS_POSIX_ACL=y
1154CONFIG_XFS_FS=m 1272CONFIG_XFS_FS=m
1155# CONFIG_XFS_RT is not set 1273CONFIG_XFS_EXPORT=y
1156CONFIG_XFS_QUOTA=y 1274CONFIG_XFS_QUOTA=m
1157CONFIG_XFS_SECURITY=y 1275CONFIG_XFS_SECURITY=y
1158# CONFIG_XFS_POSIX_ACL is not set 1276# CONFIG_XFS_POSIX_ACL is not set
1277# CONFIG_XFS_RT is not set
1159CONFIG_MINIX_FS=m 1278CONFIG_MINIX_FS=m
1160CONFIG_ROMFS_FS=m 1279CONFIG_ROMFS_FS=m
1280CONFIG_INOTIFY=y
1161# CONFIG_QUOTA is not set 1281# CONFIG_QUOTA is not set
1162CONFIG_QUOTACTL=y 1282CONFIG_QUOTACTL=y
1163CONFIG_DNOTIFY=y 1283CONFIG_DNOTIFY=y
1164CONFIG_AUTOFS_FS=m 1284CONFIG_AUTOFS_FS=m
1165CONFIG_AUTOFS4_FS=m 1285CONFIG_AUTOFS4_FS=m
1286CONFIG_FUSE_FS=m
1166 1287
1167# 1288#
1168# CD-ROM/DVD Filesystems 1289# CD-ROM/DVD Filesystems
@@ -1192,12 +1313,10 @@ CONFIG_NTFS_FS=m
1192CONFIG_PROC_FS=y 1313CONFIG_PROC_FS=y
1193CONFIG_PROC_KCORE=y 1314CONFIG_PROC_KCORE=y
1194CONFIG_SYSFS=y 1315CONFIG_SYSFS=y
1195# CONFIG_DEVFS_FS is not set
1196CONFIG_DEVPTS_FS_XATTR=y
1197CONFIG_DEVPTS_FS_SECURITY=y
1198# CONFIG_TMPFS is not set 1316# CONFIG_TMPFS is not set
1199# CONFIG_HUGETLB_PAGE is not set 1317# CONFIG_HUGETLB_PAGE is not set
1200CONFIG_RAMFS=y 1318CONFIG_RAMFS=y
1319CONFIG_RELAYFS_FS=m
1201 1320
1202# 1321#
1203# Miscellaneous filesystems 1322# Miscellaneous filesystems
@@ -1224,15 +1343,18 @@ CONFIG_UFS_FS=m
1224# 1343#
1225CONFIG_NFS_FS=m 1344CONFIG_NFS_FS=m
1226CONFIG_NFS_V3=y 1345CONFIG_NFS_V3=y
1346# CONFIG_NFS_V3_ACL is not set
1227# CONFIG_NFS_V4 is not set 1347# CONFIG_NFS_V4 is not set
1228# CONFIG_NFS_DIRECTIO is not set 1348# CONFIG_NFS_DIRECTIO is not set
1229CONFIG_NFSD=m 1349CONFIG_NFSD=m
1230CONFIG_NFSD_V3=y 1350CONFIG_NFSD_V3=y
1351# CONFIG_NFSD_V3_ACL is not set
1231# CONFIG_NFSD_V4 is not set 1352# CONFIG_NFSD_V4 is not set
1232CONFIG_NFSD_TCP=y 1353CONFIG_NFSD_TCP=y
1233CONFIG_LOCKD=m 1354CONFIG_LOCKD=m
1234CONFIG_LOCKD_V4=y 1355CONFIG_LOCKD_V4=y
1235CONFIG_EXPORTFS=m 1356CONFIG_EXPORTFS=m
1357CONFIG_NFS_COMMON=y
1236CONFIG_SUNRPC=m 1358CONFIG_SUNRPC=m
1237CONFIG_SUNRPC_GSS=m 1359CONFIG_SUNRPC_GSS=m
1238CONFIG_RPCSEC_GSS_KRB5=m 1360CONFIG_RPCSEC_GSS_KRB5=m
@@ -1256,6 +1378,7 @@ CONFIG_CODA_FS=m
1256CONFIG_CODA_FS_OLD_API=y 1378CONFIG_CODA_FS_OLD_API=y
1257CONFIG_AFS_FS=m 1379CONFIG_AFS_FS=m
1258CONFIG_RXRPC=m 1380CONFIG_RXRPC=m
1381# CONFIG_9P_FS is not set
1259 1382
1260# 1383#
1261# Partition Types 1384# Partition Types
@@ -1329,7 +1452,9 @@ CONFIG_NLS_UTF8=m
1329# 1452#
1330# Kernel hacking 1453# Kernel hacking
1331# 1454#
1455# CONFIG_PRINTK_TIME is not set
1332# CONFIG_DEBUG_KERNEL is not set 1456# CONFIG_DEBUG_KERNEL is not set
1457CONFIG_LOG_BUF_SHIFT=14
1333CONFIG_CROSSCOMPILE=y 1458CONFIG_CROSSCOMPILE=y
1334CONFIG_CMDLINE="" 1459CONFIG_CMDLINE=""
1335 1460
@@ -1352,6 +1477,7 @@ CONFIG_CRYPTO_SHA1=m
1352CONFIG_CRYPTO_SHA256=m 1477CONFIG_CRYPTO_SHA256=m
1353CONFIG_CRYPTO_SHA512=m 1478CONFIG_CRYPTO_SHA512=m
1354CONFIG_CRYPTO_WP512=m 1479CONFIG_CRYPTO_WP512=m
1480CONFIG_CRYPTO_TGR192=m
1355CONFIG_CRYPTO_DES=m 1481CONFIG_CRYPTO_DES=m
1356CONFIG_CRYPTO_BLOWFISH=m 1482CONFIG_CRYPTO_BLOWFISH=m
1357CONFIG_CRYPTO_TWOFISH=m 1483CONFIG_CRYPTO_TWOFISH=m
@@ -1360,13 +1486,13 @@ CONFIG_CRYPTO_AES=m
1360CONFIG_CRYPTO_CAST5=m 1486CONFIG_CRYPTO_CAST5=m
1361CONFIG_CRYPTO_CAST6=m 1487CONFIG_CRYPTO_CAST6=m
1362CONFIG_CRYPTO_TEA=m 1488CONFIG_CRYPTO_TEA=m
1363# CONFIG_CRYPTO_ARC4 is not set 1489CONFIG_CRYPTO_ARC4=m
1364CONFIG_CRYPTO_KHAZAD=m 1490CONFIG_CRYPTO_KHAZAD=m
1365CONFIG_CRYPTO_ANUBIS=m 1491CONFIG_CRYPTO_ANUBIS=m
1366CONFIG_CRYPTO_DEFLATE=m 1492CONFIG_CRYPTO_DEFLATE=m
1367CONFIG_CRYPTO_MICHAEL_MIC=m 1493CONFIG_CRYPTO_MICHAEL_MIC=m
1368# CONFIG_CRYPTO_CRC32C is not set 1494CONFIG_CRYPTO_CRC32C=m
1369CONFIG_CRYPTO_TEST=m 1495# CONFIG_CRYPTO_TEST is not set
1370 1496
1371# 1497#
1372# Hardware crypto devices 1498# Hardware crypto devices
@@ -1376,9 +1502,12 @@ CONFIG_CRYPTO_TEST=m
1376# Library routines 1502# Library routines
1377# 1503#
1378CONFIG_CRC_CCITT=m 1504CONFIG_CRC_CCITT=m
1505CONFIG_CRC16=m
1379CONFIG_CRC32=y 1506CONFIG_CRC32=y
1380# CONFIG_LIBCRC32C is not set 1507CONFIG_LIBCRC32C=m
1381CONFIG_ZLIB_INFLATE=m 1508CONFIG_ZLIB_INFLATE=m
1382CONFIG_ZLIB_DEFLATE=m 1509CONFIG_ZLIB_DEFLATE=m
1383CONFIG_GENERIC_HARDIRQS=y 1510CONFIG_TEXTSEARCH=y
1384CONFIG_GENERIC_IRQ_PROBE=y 1511CONFIG_TEXTSEARCH_KMP=m
1512CONFIG_TEXTSEARCH_BM=m
1513CONFIG_TEXTSEARCH_FSM=m
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 1dc935f37582..4365d9c8c42e 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:10 2005 4# Thu Oct 20 22:27:05 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,30 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_LOCK_KERNEL=y 13CONFIG_LOCK_KERNEL=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=15 27CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_CPUSETS=y
31CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 32CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 33CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 38CONFIG_FUTEX=y
36CONFIG_EPOLL=y 39CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 44CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 45CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
44 48
45# 49#
46# Loadable module support 50# Loadable module support
@@ -57,32 +61,49 @@ CONFIG_STOP_MACHINE=y
57# 61#
58# Machine selection 62# Machine selection
59# 63#
60# CONFIG_MACH_JAZZ is not set 64# CONFIG_MIPS_MTX1 is not set
61# CONFIG_MACH_VR41XX is not set 65# CONFIG_MIPS_BOSPORUS is not set
62# CONFIG_TOSHIBA_JMR3927 is not set 66# CONFIG_MIPS_PB1000 is not set
67# CONFIG_MIPS_PB1100 is not set
68# CONFIG_MIPS_PB1500 is not set
69# CONFIG_MIPS_PB1550 is not set
70# CONFIG_MIPS_PB1200 is not set
71# CONFIG_MIPS_DB1000 is not set
72# CONFIG_MIPS_DB1100 is not set
73# CONFIG_MIPS_DB1500 is not set
74# CONFIG_MIPS_DB1550 is not set
75# CONFIG_MIPS_DB1200 is not set
76# CONFIG_MIPS_MIRAGE is not set
63# CONFIG_MIPS_COBALT is not set 77# CONFIG_MIPS_COBALT is not set
64# CONFIG_MACH_DECSTATION is not set 78# CONFIG_MACH_DECSTATION is not set
65# CONFIG_MIPS_EV64120 is not set 79# CONFIG_MIPS_EV64120 is not set
66# CONFIG_MIPS_EV96100 is not set 80# CONFIG_MIPS_EV96100 is not set
67# CONFIG_MIPS_IVR is not set 81# CONFIG_MIPS_IVR is not set
68# CONFIG_LASAT is not set
69# CONFIG_MIPS_ITE8172 is not set 82# CONFIG_MIPS_ITE8172 is not set
83# CONFIG_MACH_JAZZ is not set
84# CONFIG_LASAT is not set
70# CONFIG_MIPS_ATLAS is not set 85# CONFIG_MIPS_ATLAS is not set
71# CONFIG_MIPS_MALTA is not set 86# CONFIG_MIPS_MALTA is not set
72# CONFIG_MIPS_SEAD is not set 87# CONFIG_MIPS_SEAD is not set
88# CONFIG_MIPS_SIM is not set
89# CONFIG_MOMENCO_JAGUAR_ATX is not set
73# CONFIG_MOMENCO_OCELOT is not set 90# CONFIG_MOMENCO_OCELOT is not set
74# CONFIG_MOMENCO_OCELOT_G is not set
75# CONFIG_MOMENCO_OCELOT_C is not set
76# CONFIG_MOMENCO_OCELOT_3 is not set 91# CONFIG_MOMENCO_OCELOT_3 is not set
77# CONFIG_MOMENCO_JAGUAR_ATX is not set 92# CONFIG_MOMENCO_OCELOT_C is not set
78# CONFIG_PMC_YOSEMITE is not set 93# CONFIG_MOMENCO_OCELOT_G is not set
94# CONFIG_MIPS_XXS1500 is not set
95# CONFIG_PNX8550_V2PCI is not set
96# CONFIG_PNX8550_JBS is not set
79# CONFIG_DDB5074 is not set 97# CONFIG_DDB5074 is not set
80# CONFIG_DDB5476 is not set 98# CONFIG_DDB5476 is not set
81# CONFIG_DDB5477 is not set 99# CONFIG_DDB5477 is not set
82# CONFIG_NEC_OSPREY is not set 100# CONFIG_MACH_VR41XX is not set
101# CONFIG_PMC_YOSEMITE is not set
102# CONFIG_QEMU is not set
83# CONFIG_SGI_IP22 is not set 103# CONFIG_SGI_IP22 is not set
84# CONFIG_SOC_AU1X00 is not set 104# CONFIG_SGI_IP27 is not set
85CONFIG_SIBYTE_SB1xxx_SOC=y 105# CONFIG_SGI_IP32 is not set
106# CONFIG_SIBYTE_BIGSUR is not set
86CONFIG_SIBYTE_SWARM=y 107CONFIG_SIBYTE_SWARM=y
87# CONFIG_SIBYTE_SENTOSA is not set 108# CONFIG_SIBYTE_SENTOSA is not set
88# CONFIG_SIBYTE_RHONE is not set 109# CONFIG_SIBYTE_RHONE is not set
@@ -91,9 +112,12 @@ CONFIG_SIBYTE_SWARM=y
91# CONFIG_SIBYTE_LITTLESUR is not set 112# CONFIG_SIBYTE_LITTLESUR is not set
92# CONFIG_SIBYTE_CRHINE is not set 113# CONFIG_SIBYTE_CRHINE is not set
93# CONFIG_SIBYTE_CRHONE is not set 114# CONFIG_SIBYTE_CRHONE is not set
94# CONFIG_SIBYTE_UNKNOWN is not set 115# CONFIG_SNI_RM200_PCI is not set
95CONFIG_SIBYTE_BOARD=y 116# CONFIG_TOSHIBA_JMR3927 is not set
117# CONFIG_TOSHIBA_RBTX4927 is not set
118# CONFIG_TOSHIBA_RBTX4938 is not set
96CONFIG_SIBYTE_SB1250=y 119CONFIG_SIBYTE_SB1250=y
120CONFIG_SIBYTE_SB1xxx_SOC=y
97CONFIG_CPU_SB1_PASS_1=y 121CONFIG_CPU_SB1_PASS_1=y
98# CONFIG_CPU_SB1_PASS_2_1250 is not set 122# CONFIG_CPU_SB1_PASS_2_1250 is not set
99# CONFIG_CPU_SB1_PASS_2_2 is not set 123# CONFIG_CPU_SB1_PASS_2_2 is not set
@@ -102,18 +126,20 @@ CONFIG_CPU_SB1_PASS_1=y
102# CONFIG_CPU_SB1_PASS_3 is not set 126# CONFIG_CPU_SB1_PASS_3 is not set
103CONFIG_SIBYTE_HAS_LDT=y 127CONFIG_SIBYTE_HAS_LDT=y
104# CONFIG_SIMULATION is not set 128# CONFIG_SIMULATION is not set
129# CONFIG_CONFIG_SB1_CEX_ALWAYS_FATAL is not set
130# CONFIG_CONFIG_SB1_CERR_STALL is not set
105CONFIG_SIBYTE_CFE=y 131CONFIG_SIBYTE_CFE=y
106# CONFIG_SIBYTE_CFE_CONSOLE is not set 132# CONFIG_SIBYTE_CFE_CONSOLE is not set
107# CONFIG_SIBYTE_BUS_WATCHER is not set 133# CONFIG_SIBYTE_BUS_WATCHER is not set
108# CONFIG_SIBYTE_SB1250_PROF is not set 134# CONFIG_SIBYTE_SB1250_PROF is not set
109# CONFIG_SIBYTE_TBPROF is not set 135# CONFIG_SIBYTE_TBPROF is not set
110# CONFIG_SNI_RM200_PCI is not set
111# CONFIG_TOSHIBA_RBTX4927 is not set
112CONFIG_RWSEM_GENERIC_SPINLOCK=y 136CONFIG_RWSEM_GENERIC_SPINLOCK=y
113CONFIG_GENERIC_CALIBRATE_DELAY=y 137CONFIG_GENERIC_CALIBRATE_DELAY=y
114CONFIG_HAVE_DEC_LOCK=y
115CONFIG_DMA_COHERENT=y 138CONFIG_DMA_COHERENT=y
139CONFIG_CPU_BIG_ENDIAN=y
116# CONFIG_CPU_LITTLE_ENDIAN is not set 140# CONFIG_CPU_LITTLE_ENDIAN is not set
141CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
142CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
117CONFIG_SWAP_IO_SPACE=y 143CONFIG_SWAP_IO_SPACE=y
118CONFIG_BOOT_ELF32=y 144CONFIG_BOOT_ELF32=y
119CONFIG_MIPS_L1_CACHE_SHIFT=5 145CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -121,8 +147,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
121# 147#
122# CPU selection 148# CPU selection
123# 149#
124# CONFIG_CPU_MIPS32 is not set 150# CONFIG_CPU_MIPS32_R1 is not set
125# CONFIG_CPU_MIPS64 is not set 151# CONFIG_CPU_MIPS32_R2 is not set
152# CONFIG_CPU_MIPS64_R1 is not set
153# CONFIG_CPU_MIPS64_R2 is not set
126# CONFIG_CPU_R3000 is not set 154# CONFIG_CPU_R3000 is not set
127# CONFIG_CPU_TX39XX is not set 155# CONFIG_CPU_TX39XX is not set
128# CONFIG_CPU_VR41XX is not set 156# CONFIG_CPU_VR41XX is not set
@@ -138,22 +166,46 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
138# CONFIG_CPU_RM7000 is not set 166# CONFIG_CPU_RM7000 is not set
139# CONFIG_CPU_RM9000 is not set 167# CONFIG_CPU_RM9000 is not set
140CONFIG_CPU_SB1=y 168CONFIG_CPU_SB1=y
169CONFIG_SYS_HAS_CPU_SB1=y
170CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
171CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
172CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
173CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
174
175#
176# Kernel type
177#
178# CONFIG_32BIT is not set
179CONFIG_64BIT=y
141CONFIG_PAGE_SIZE_4KB=y 180CONFIG_PAGE_SIZE_4KB=y
142# CONFIG_PAGE_SIZE_8KB is not set 181# CONFIG_PAGE_SIZE_8KB is not set
143# CONFIG_PAGE_SIZE_16KB is not set 182# CONFIG_PAGE_SIZE_16KB is not set
144# CONFIG_PAGE_SIZE_64KB is not set 183# CONFIG_PAGE_SIZE_64KB is not set
145# CONFIG_SIBYTE_DMA_PAGEOPS is not set 184# CONFIG_SIBYTE_DMA_PAGEOPS is not set
146CONFIG_CPU_HAS_PREFETCH=y 185CONFIG_CPU_HAS_PREFETCH=y
186# CONFIG_MIPS_MT is not set
147CONFIG_SB1_PASS_1_WORKAROUNDS=y 187CONFIG_SB1_PASS_1_WORKAROUNDS=y
148# CONFIG_64BIT_PHYS_ADDR is not set
149# CONFIG_CPU_ADVANCED is not set
150CONFIG_CPU_HAS_LLSC=y 188CONFIG_CPU_HAS_LLSC=y
151CONFIG_CPU_HAS_LLDSCD=y 189CONFIG_CPU_HAS_LLDSCD=y
152CONFIG_CPU_HAS_SYNC=y 190CONFIG_CPU_HAS_SYNC=y
153# CONFIG_HIGHMEM is not set 191CONFIG_GENERIC_HARDIRQS=y
192CONFIG_GENERIC_IRQ_PROBE=y
193CONFIG_CPU_SUPPORTS_HIGHMEM=y
194CONFIG_SYS_SUPPORTS_HIGHMEM=y
195CONFIG_ARCH_FLATMEM_ENABLE=y
196CONFIG_SELECT_MEMORY_MODEL=y
197CONFIG_FLATMEM_MANUAL=y
198# CONFIG_DISCONTIGMEM_MANUAL is not set
199# CONFIG_SPARSEMEM_MANUAL is not set
200CONFIG_FLATMEM=y
201CONFIG_FLAT_NODE_MEM_MAP=y
202# CONFIG_SPARSEMEM_STATIC is not set
154CONFIG_SMP=y 203CONFIG_SMP=y
155CONFIG_NR_CPUS=2 204CONFIG_NR_CPUS=2
205CONFIG_PREEMPT_NONE=y
206# CONFIG_PREEMPT_VOLUNTARY is not set
156# CONFIG_PREEMPT is not set 207# CONFIG_PREEMPT is not set
208CONFIG_PREEMPT_BKL=y
157 209
158# 210#
159# Bus options (PCI, PCMCIA, EISA, ISA, TC) 211# Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -161,7 +213,6 @@ CONFIG_NR_CPUS=2
161CONFIG_HW_HAS_PCI=y 213CONFIG_HW_HAS_PCI=y
162CONFIG_PCI=y 214CONFIG_PCI=y
163CONFIG_PCI_LEGACY_PROC=y 215CONFIG_PCI_LEGACY_PROC=y
164CONFIG_PCI_NAMES=y
165CONFIG_MMU=y 216CONFIG_MMU=y
166 217
167# 218#
@@ -170,10 +221,6 @@ CONFIG_MMU=y
170# CONFIG_PCCARD is not set 221# CONFIG_PCCARD is not set
171 222
172# 223#
173# PC-card bridges
174#
175
176#
177# PCI Hotplug Support 224# PCI Hotplug Support
178# 225#
179# CONFIG_HOTPLUG_PCI is not set 226# CONFIG_HOTPLUG_PCI is not set
@@ -183,7 +230,86 @@ CONFIG_MMU=y
183# 230#
184CONFIG_BINFMT_ELF=y 231CONFIG_BINFMT_ELF=y
185# CONFIG_BINFMT_MISC is not set 232# CONFIG_BINFMT_MISC is not set
186CONFIG_TRAD_SIGNALS=y 233# CONFIG_BUILD_ELF64 is not set
234CONFIG_MIPS32_COMPAT=y
235CONFIG_COMPAT=y
236CONFIG_MIPS32_O32=y
237# CONFIG_MIPS32_N32 is not set
238CONFIG_BINFMT_ELF32=y
239
240#
241# Networking
242#
243CONFIG_NET=y
244
245#
246# Networking options
247#
248CONFIG_PACKET=y
249CONFIG_PACKET_MMAP=y
250CONFIG_UNIX=y
251CONFIG_XFRM=y
252CONFIG_XFRM_USER=m
253CONFIG_NET_KEY=y
254CONFIG_INET=y
255# CONFIG_IP_MULTICAST is not set
256# CONFIG_IP_ADVANCED_ROUTER is not set
257CONFIG_IP_FIB_HASH=y
258CONFIG_IP_PNP=y
259CONFIG_IP_PNP_DHCP=y
260CONFIG_IP_PNP_BOOTP=y
261# CONFIG_IP_PNP_RARP is not set
262# CONFIG_NET_IPIP is not set
263# CONFIG_NET_IPGRE is not set
264# CONFIG_ARPD is not set
265# CONFIG_SYN_COOKIES is not set
266# CONFIG_INET_AH is not set
267# CONFIG_INET_ESP is not set
268# CONFIG_INET_IPCOMP is not set
269CONFIG_INET_TUNNEL=m
270CONFIG_INET_DIAG=y
271CONFIG_INET_TCP_DIAG=y
272# CONFIG_TCP_CONG_ADVANCED is not set
273CONFIG_TCP_CONG_BIC=y
274# CONFIG_IPV6 is not set
275# CONFIG_NETFILTER is not set
276
277#
278# DCCP Configuration (EXPERIMENTAL)
279#
280# CONFIG_IP_DCCP is not set
281
282#
283# SCTP Configuration (EXPERIMENTAL)
284#
285# CONFIG_IP_SCTP is not set
286# CONFIG_ATM is not set
287# CONFIG_BRIDGE is not set
288# CONFIG_VLAN_8021Q is not set
289# CONFIG_DECNET is not set
290# CONFIG_LLC2 is not set
291# CONFIG_IPX is not set
292# CONFIG_ATALK is not set
293# CONFIG_X25 is not set
294# CONFIG_LAPB is not set
295# CONFIG_NET_DIVERT is not set
296# CONFIG_ECONET is not set
297# CONFIG_WAN_ROUTER is not set
298# CONFIG_NET_SCHED is not set
299# CONFIG_NET_CLS_ROUTE is not set
300
301#
302# Network testing
303#
304# CONFIG_NET_PKTGEN is not set
305# CONFIG_HAMRADIO is not set
306# CONFIG_IRDA is not set
307# CONFIG_BT is not set
308CONFIG_IEEE80211=m
309# CONFIG_IEEE80211_DEBUG is not set
310CONFIG_IEEE80211_CRYPT_WEP=m
311CONFIG_IEEE80211_CRYPT_CCMP=m
312CONFIG_IEEE80211_CRYPT_TKIP=m
187 313
188# 314#
189# Device Drivers 315# Device Drivers
@@ -194,7 +320,12 @@ CONFIG_TRAD_SIGNALS=y
194# 320#
195CONFIG_STANDALONE=y 321CONFIG_STANDALONE=y
196CONFIG_PREVENT_FIRMWARE_BUILD=y 322CONFIG_PREVENT_FIRMWARE_BUILD=y
197# CONFIG_FW_LOADER is not set 323CONFIG_FW_LOADER=m
324
325#
326# Connector - unified userspace <-> kernelspace linker
327#
328CONFIG_CONNECTOR=m
198 329
199# 330#
200# Memory Technology Devices (MTD) 331# Memory Technology Devices (MTD)
@@ -213,7 +344,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
213# 344#
214# Block devices 345# Block devices
215# 346#
216# CONFIG_BLK_DEV_FD is not set
217# CONFIG_BLK_CPQ_DA is not set 347# CONFIG_BLK_CPQ_DA is not set
218# CONFIG_BLK_CPQ_CISS_DA is not set 348# CONFIG_BLK_CPQ_CISS_DA is not set
219# CONFIG_BLK_DEV_DAC960 is not set 349# CONFIG_BLK_DEV_DAC960 is not set
@@ -226,8 +356,6 @@ CONFIG_BLK_DEV_RAM=y
226CONFIG_BLK_DEV_RAM_COUNT=16 356CONFIG_BLK_DEV_RAM_COUNT=16
227CONFIG_BLK_DEV_RAM_SIZE=9220 357CONFIG_BLK_DEV_RAM_SIZE=9220
228CONFIG_BLK_DEV_INITRD=y 358CONFIG_BLK_DEV_INITRD=y
229CONFIG_INITRAMFS_SOURCE=""
230# CONFIG_LBD is not set
231CONFIG_CDROM_PKTCDVD=m 359CONFIG_CDROM_PKTCDVD=m
232CONFIG_CDROM_PKTCDVD_BUFFERS=8 360CONFIG_CDROM_PKTCDVD_BUFFERS=8
233# CONFIG_CDROM_PKTCDVD_WCACHE is not set 361# CONFIG_CDROM_PKTCDVD_WCACHE is not set
@@ -263,7 +391,7 @@ CONFIG_BLK_DEV_IDEFLOPPY=y
263# 391#
264CONFIG_IDE_GENERIC=y 392CONFIG_IDE_GENERIC=y
265# CONFIG_BLK_DEV_IDEPCI is not set 393# CONFIG_BLK_DEV_IDEPCI is not set
266CONFIG_BLK_DEV_IDE_SWARM=y 394# CONFIG_BLK_DEV_IDE_SWARM is not set
267# CONFIG_IDE_ARM is not set 395# CONFIG_IDE_ARM is not set
268# CONFIG_BLK_DEV_IDEDMA is not set 396# CONFIG_BLK_DEV_IDEDMA is not set
269# CONFIG_IDEDMA_AUTO is not set 397# CONFIG_IDEDMA_AUTO is not set
@@ -272,6 +400,7 @@ CONFIG_BLK_DEV_IDE_SWARM=y
272# 400#
273# SCSI device support 401# SCSI device support
274# 402#
403CONFIG_RAID_ATTRS=m
275# CONFIG_SCSI is not set 404# CONFIG_SCSI is not set
276 405
277# 406#
@@ -282,6 +411,7 @@ CONFIG_BLK_DEV_IDE_SWARM=y
282# 411#
283# Fusion MPT device support 412# Fusion MPT device support
284# 413#
414# CONFIG_FUSION is not set
285 415
286# 416#
287# IEEE 1394 (FireWire) support 417# IEEE 1394 (FireWire) support
@@ -294,78 +424,13 @@ CONFIG_BLK_DEV_IDE_SWARM=y
294# CONFIG_I2O is not set 424# CONFIG_I2O is not set
295 425
296# 426#
297# Networking support 427# Network device support
298# 428#
299CONFIG_NET=y
300
301#
302# Networking options
303#
304CONFIG_PACKET=y
305CONFIG_PACKET_MMAP=y
306CONFIG_NETLINK_DEV=y
307CONFIG_UNIX=y
308CONFIG_NET_KEY=y
309CONFIG_INET=y
310# CONFIG_IP_MULTICAST is not set
311# CONFIG_IP_ADVANCED_ROUTER is not set
312CONFIG_IP_PNP=y
313CONFIG_IP_PNP_DHCP=y
314CONFIG_IP_PNP_BOOTP=y
315# CONFIG_IP_PNP_RARP is not set
316# CONFIG_NET_IPIP is not set
317# CONFIG_NET_IPGRE is not set
318# CONFIG_ARPD is not set
319# CONFIG_SYN_COOKIES is not set
320# CONFIG_INET_AH is not set
321# CONFIG_INET_ESP is not set
322# CONFIG_INET_IPCOMP is not set
323CONFIG_INET_TUNNEL=m
324CONFIG_IP_TCPDIAG=m
325# CONFIG_IP_TCPDIAG_IPV6 is not set
326# CONFIG_IPV6 is not set
327# CONFIG_NETFILTER is not set
328CONFIG_XFRM=y
329CONFIG_XFRM_USER=m
330
331#
332# SCTP Configuration (EXPERIMENTAL)
333#
334# CONFIG_IP_SCTP is not set
335# CONFIG_ATM is not set
336# CONFIG_BRIDGE is not set
337# CONFIG_VLAN_8021Q is not set
338# CONFIG_DECNET is not set
339# CONFIG_LLC2 is not set
340# CONFIG_IPX is not set
341# CONFIG_ATALK is not set
342# CONFIG_X25 is not set
343# CONFIG_LAPB is not set
344# CONFIG_NET_DIVERT is not set
345# CONFIG_ECONET is not set
346# CONFIG_WAN_ROUTER is not set
347
348#
349# QoS and/or fair queueing
350#
351# CONFIG_NET_SCHED is not set
352# CONFIG_NET_CLS_ROUTE is not set
353
354#
355# Network testing
356#
357# CONFIG_NET_PKTGEN is not set
358# CONFIG_NETPOLL is not set
359# CONFIG_NET_POLL_CONTROLLER is not set
360# CONFIG_HAMRADIO is not set
361# CONFIG_IRDA is not set
362# CONFIG_BT is not set
363CONFIG_NETDEVICES=y 429CONFIG_NETDEVICES=y
364# CONFIG_DUMMY is not set 430# CONFIG_DUMMY is not set
365# CONFIG_BONDING is not set 431# CONFIG_BONDING is not set
366# CONFIG_EQUALIZER is not set 432# CONFIG_EQUALIZER is not set
367# CONFIG_TUN is not set 433# CONFIG_TUN is not set
368# CONFIG_ETHERTAP is not set
369 434
370# 435#
371# ARCnet devices 436# ARCnet devices
@@ -373,6 +438,21 @@ CONFIG_NETDEVICES=y
373# CONFIG_ARCNET is not set 438# CONFIG_ARCNET is not set
374 439
375# 440#
441# PHY device support
442#
443CONFIG_PHYLIB=m
444CONFIG_PHYCONTROL=y
445
446#
447# MII PHY device drivers
448#
449CONFIG_MARVELL_PHY=m
450CONFIG_DAVICOM_PHY=m
451CONFIG_QSEMI_PHY=m
452CONFIG_LXT_PHY=m
453CONFIG_CICADA_PHY=m
454
455#
376# Ethernet (10 or 100Mbit) 456# Ethernet (10 or 100Mbit)
377# 457#
378CONFIG_NET_ETHERNET=y 458CONFIG_NET_ETHERNET=y
@@ -399,12 +479,16 @@ CONFIG_MII=y
399# CONFIG_YELLOWFIN is not set 479# CONFIG_YELLOWFIN is not set
400# CONFIG_R8169 is not set 480# CONFIG_R8169 is not set
401CONFIG_NET_SB1250_MAC=y 481CONFIG_NET_SB1250_MAC=y
482# CONFIG_SIS190 is not set
483# CONFIG_SKGE is not set
402# CONFIG_SK98LIN is not set 484# CONFIG_SK98LIN is not set
403# CONFIG_TIGON3 is not set 485# CONFIG_TIGON3 is not set
486# CONFIG_BNX2 is not set
404 487
405# 488#
406# Ethernet (10000 Mbit) 489# Ethernet (10000 Mbit)
407# 490#
491# CONFIG_CHELSIO_T1 is not set
408# CONFIG_IXGB is not set 492# CONFIG_IXGB is not set
409# CONFIG_S2IO is not set 493# CONFIG_S2IO is not set
410 494
@@ -417,6 +501,8 @@ CONFIG_NET_SB1250_MAC=y
417# Wireless LAN (non-hamradio) 501# Wireless LAN (non-hamradio)
418# 502#
419# CONFIG_NET_RADIO is not set 503# CONFIG_NET_RADIO is not set
504# CONFIG_IPW_DEBUG is not set
505CONFIG_IPW2200=m
420 506
421# 507#
422# Wan interfaces 508# Wan interfaces
@@ -428,6 +514,8 @@ CONFIG_NET_SB1250_MAC=y
428# CONFIG_SLIP is not set 514# CONFIG_SLIP is not set
429# CONFIG_SHAPER is not set 515# CONFIG_SHAPER is not set
430# CONFIG_NETCONSOLE is not set 516# CONFIG_NETCONSOLE is not set
517# CONFIG_NETPOLL is not set
518# CONFIG_NET_POLL_CONTROLLER is not set
431 519
432# 520#
433# ISDN subsystem 521# ISDN subsystem
@@ -445,25 +533,15 @@ CONFIG_NET_SB1250_MAC=y
445# CONFIG_INPUT is not set 533# CONFIG_INPUT is not set
446 534
447# 535#
448# Userland interfaces 536# Hardware I/O ports
449#
450
451#
452# Input I/O drivers
453# 537#
454# CONFIG_GAMEPORT is not set
455CONFIG_SOUND_GAMEPORT=y
456CONFIG_SERIO=y 538CONFIG_SERIO=y
457# CONFIG_SERIO_I8042 is not set 539# CONFIG_SERIO_I8042 is not set
458CONFIG_SERIO_SERPORT=y 540CONFIG_SERIO_SERPORT=y
459# CONFIG_SERIO_CT82C710 is not set
460# CONFIG_SERIO_PCIPS2 is not set 541# CONFIG_SERIO_PCIPS2 is not set
461# CONFIG_SERIO_LIBPS2 is not set 542# CONFIG_SERIO_LIBPS2 is not set
462CONFIG_SERIO_RAW=m 543CONFIG_SERIO_RAW=m
463 544# CONFIG_GAMEPORT is not set
464#
465# Input Device Drivers
466#
467 545
468# 546#
469# Character devices 547# Character devices
@@ -472,11 +550,13 @@ CONFIG_SERIO_RAW=m
472CONFIG_SERIAL_NONSTANDARD=y 550CONFIG_SERIAL_NONSTANDARD=y
473# CONFIG_ROCKETPORT is not set 551# CONFIG_ROCKETPORT is not set
474# CONFIG_CYCLADES is not set 552# CONFIG_CYCLADES is not set
553# CONFIG_DIGIEPCA is not set
475# CONFIG_MOXA_SMARTIO is not set 554# CONFIG_MOXA_SMARTIO is not set
476# CONFIG_ISI is not set 555# CONFIG_ISI is not set
477# CONFIG_SYNCLINK is not set
478# CONFIG_SYNCLINKMP is not set 556# CONFIG_SYNCLINKMP is not set
479# CONFIG_N_HDLC is not set 557# CONFIG_N_HDLC is not set
558# CONFIG_SPECIALIX is not set
559# CONFIG_SX is not set
480# CONFIG_STALDRV is not set 560# CONFIG_STALDRV is not set
481CONFIG_SIBYTE_SB1250_DUART=y 561CONFIG_SIBYTE_SB1250_DUART=y
482CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y 562CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y
@@ -489,6 +569,7 @@ CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y
489# 569#
490# Non-8250 serial port support 570# Non-8250 serial port support
491# 571#
572# CONFIG_SERIAL_JSM is not set
492CONFIG_UNIX98_PTYS=y 573CONFIG_UNIX98_PTYS=y
493CONFIG_LEGACY_PTYS=y 574CONFIG_LEGACY_PTYS=y
494CONFIG_LEGACY_PTY_COUNT=256 575CONFIG_LEGACY_PTY_COUNT=256
@@ -515,6 +596,11 @@ CONFIG_LEGACY_PTY_COUNT=256
515# CONFIG_RAW_DRIVER is not set 596# CONFIG_RAW_DRIVER is not set
516 597
517# 598#
599# TPM devices
600#
601# CONFIG_TCG_TPM is not set
602
603#
518# I2C support 604# I2C support
519# 605#
520# CONFIG_I2C is not set 606# CONFIG_I2C is not set
@@ -525,10 +611,20 @@ CONFIG_LEGACY_PTY_COUNT=256
525# CONFIG_W1 is not set 611# CONFIG_W1 is not set
526 612
527# 613#
614# Hardware Monitoring support
615#
616# CONFIG_HWMON is not set
617# CONFIG_HWMON_VID is not set
618
619#
528# Misc devices 620# Misc devices
529# 621#
530 622
531# 623#
624# Multimedia Capabilities Port drivers
625#
626
627#
532# Multimedia devices 628# Multimedia devices
533# 629#
534# CONFIG_VIDEO_DEV is not set 630# CONFIG_VIDEO_DEV is not set
@@ -542,7 +638,6 @@ CONFIG_LEGACY_PTY_COUNT=256
542# Graphics support 638# Graphics support
543# 639#
544# CONFIG_FB is not set 640# CONFIG_FB is not set
545# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
546 641
547# 642#
548# Sound 643# Sound
@@ -552,13 +647,9 @@ CONFIG_LEGACY_PTY_COUNT=256
552# 647#
553# USB support 648# USB support
554# 649#
555# CONFIG_USB is not set
556CONFIG_USB_ARCH_HAS_HCD=y 650CONFIG_USB_ARCH_HAS_HCD=y
557CONFIG_USB_ARCH_HAS_OHCI=y 651CONFIG_USB_ARCH_HAS_OHCI=y
558 652# CONFIG_USB is not set
559#
560# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
561#
562 653
563# 654#
564# USB Gadget Support 655# USB Gadget Support
@@ -576,12 +667,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y
576# CONFIG_INFINIBAND is not set 667# CONFIG_INFINIBAND is not set
577 668
578# 669#
670# SN Devices
671#
672
673#
579# File systems 674# File systems
580# 675#
581CONFIG_EXT2_FS=y 676CONFIG_EXT2_FS=y
582CONFIG_EXT2_FS_XATTR=y 677CONFIG_EXT2_FS_XATTR=y
583CONFIG_EXT2_FS_POSIX_ACL=y 678CONFIG_EXT2_FS_POSIX_ACL=y
584CONFIG_EXT2_FS_SECURITY=y 679CONFIG_EXT2_FS_SECURITY=y
680# CONFIG_EXT2_FS_XIP is not set
585# CONFIG_EXT3_FS is not set 681# CONFIG_EXT3_FS is not set
586# CONFIG_JBD is not set 682# CONFIG_JBD is not set
587CONFIG_FS_MBCACHE=y 683CONFIG_FS_MBCACHE=y
@@ -591,10 +687,12 @@ CONFIG_FS_POSIX_ACL=y
591# CONFIG_XFS_FS is not set 687# CONFIG_XFS_FS is not set
592# CONFIG_MINIX_FS is not set 688# CONFIG_MINIX_FS is not set
593# CONFIG_ROMFS_FS is not set 689# CONFIG_ROMFS_FS is not set
690CONFIG_INOTIFY=y
594# CONFIG_QUOTA is not set 691# CONFIG_QUOTA is not set
595CONFIG_DNOTIFY=y 692CONFIG_DNOTIFY=y
596# CONFIG_AUTOFS_FS is not set 693# CONFIG_AUTOFS_FS is not set
597# CONFIG_AUTOFS4_FS is not set 694# CONFIG_AUTOFS4_FS is not set
695CONFIG_FUSE_FS=m
598 696
599# 697#
600# CD-ROM/DVD Filesystems 698# CD-ROM/DVD Filesystems
@@ -615,11 +713,10 @@ CONFIG_DNOTIFY=y
615CONFIG_PROC_FS=y 713CONFIG_PROC_FS=y
616CONFIG_PROC_KCORE=y 714CONFIG_PROC_KCORE=y
617CONFIG_SYSFS=y 715CONFIG_SYSFS=y
618# CONFIG_DEVFS_FS is not set
619# CONFIG_DEVPTS_FS_XATTR is not set
620# CONFIG_TMPFS is not set 716# CONFIG_TMPFS is not set
621# CONFIG_HUGETLB_PAGE is not set 717# CONFIG_HUGETLB_PAGE is not set
622CONFIG_RAMFS=y 718CONFIG_RAMFS=y
719CONFIG_RELAYFS_FS=m
623 720
624# 721#
625# Miscellaneous filesystems 722# Miscellaneous filesystems
@@ -643,13 +740,14 @@ CONFIG_RAMFS=y
643# 740#
644CONFIG_NFS_FS=y 741CONFIG_NFS_FS=y
645CONFIG_NFS_V3=y 742CONFIG_NFS_V3=y
743# CONFIG_NFS_V3_ACL is not set
646# CONFIG_NFS_V4 is not set 744# CONFIG_NFS_V4 is not set
647# CONFIG_NFS_DIRECTIO is not set 745# CONFIG_NFS_DIRECTIO is not set
648# CONFIG_NFSD is not set 746# CONFIG_NFSD is not set
649CONFIG_ROOT_NFS=y 747CONFIG_ROOT_NFS=y
650CONFIG_LOCKD=y 748CONFIG_LOCKD=y
651CONFIG_LOCKD_V4=y 749CONFIG_LOCKD_V4=y
652# CONFIG_EXPORTFS is not set 750CONFIG_NFS_COMMON=y
653CONFIG_SUNRPC=y 751CONFIG_SUNRPC=y
654# CONFIG_RPCSEC_GSS_KRB5 is not set 752# CONFIG_RPCSEC_GSS_KRB5 is not set
655# CONFIG_RPCSEC_GSS_SPKM3 is not set 753# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -658,6 +756,7 @@ CONFIG_SUNRPC=y
658# CONFIG_NCP_FS is not set 756# CONFIG_NCP_FS is not set
659# CONFIG_CODA_FS is not set 757# CONFIG_CODA_FS is not set
660# CONFIG_AFS_FS is not set 758# CONFIG_AFS_FS is not set
759# CONFIG_9P_FS is not set
661 760
662# 761#
663# Partition Types 762# Partition Types
@@ -678,7 +777,9 @@ CONFIG_MSDOS_PARTITION=y
678# 777#
679# Kernel hacking 778# Kernel hacking
680# 779#
780# CONFIG_PRINTK_TIME is not set
681# CONFIG_DEBUG_KERNEL is not set 781# CONFIG_DEBUG_KERNEL is not set
782CONFIG_LOG_BUF_SHIFT=15
682CONFIG_CROSSCOMPILE=y 783CONFIG_CROSSCOMPILE=y
683CONFIG_CMDLINE="" 784CONFIG_CMDLINE=""
684# CONFIG_SB1XXX_CORELIS is not set 785# CONFIG_SB1XXX_CORELIS is not set
@@ -695,27 +796,28 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
695# 796#
696CONFIG_CRYPTO=y 797CONFIG_CRYPTO=y
697CONFIG_CRYPTO_HMAC=y 798CONFIG_CRYPTO_HMAC=y
698CONFIG_CRYPTO_NULL=y 799CONFIG_CRYPTO_NULL=m
699CONFIG_CRYPTO_MD4=y 800CONFIG_CRYPTO_MD4=m
700CONFIG_CRYPTO_MD5=y 801CONFIG_CRYPTO_MD5=m
701CONFIG_CRYPTO_SHA1=y 802CONFIG_CRYPTO_SHA1=m
702CONFIG_CRYPTO_SHA256=y 803CONFIG_CRYPTO_SHA256=m
703CONFIG_CRYPTO_SHA512=y 804CONFIG_CRYPTO_SHA512=m
704CONFIG_CRYPTO_WP512=m 805CONFIG_CRYPTO_WP512=m
705CONFIG_CRYPTO_DES=y 806CONFIG_CRYPTO_TGR192=m
706CONFIG_CRYPTO_BLOWFISH=y 807CONFIG_CRYPTO_DES=m
707CONFIG_CRYPTO_TWOFISH=y 808CONFIG_CRYPTO_BLOWFISH=m
708CONFIG_CRYPTO_SERPENT=y 809CONFIG_CRYPTO_TWOFISH=m
810CONFIG_CRYPTO_SERPENT=m
709CONFIG_CRYPTO_AES=m 811CONFIG_CRYPTO_AES=m
710# CONFIG_CRYPTO_CAST5 is not set 812CONFIG_CRYPTO_CAST5=m
711# CONFIG_CRYPTO_CAST6 is not set 813CONFIG_CRYPTO_CAST6=m
712CONFIG_CRYPTO_TEA=m 814CONFIG_CRYPTO_TEA=m
713# CONFIG_CRYPTO_ARC4 is not set 815CONFIG_CRYPTO_ARC4=m
714CONFIG_CRYPTO_KHAZAD=m 816CONFIG_CRYPTO_KHAZAD=m
715CONFIG_CRYPTO_ANUBIS=m 817CONFIG_CRYPTO_ANUBIS=m
716CONFIG_CRYPTO_DEFLATE=y 818CONFIG_CRYPTO_DEFLATE=m
717CONFIG_CRYPTO_MICHAEL_MIC=y 819CONFIG_CRYPTO_MICHAEL_MIC=m
718# CONFIG_CRYPTO_CRC32C is not set 820CONFIG_CRYPTO_CRC32C=m
719# CONFIG_CRYPTO_TEST is not set 821# CONFIG_CRYPTO_TEST is not set
720 822
721# 823#
@@ -726,9 +828,8 @@ CONFIG_CRYPTO_MICHAEL_MIC=y
726# Library routines 828# Library routines
727# 829#
728# CONFIG_CRC_CCITT is not set 830# CONFIG_CRC_CCITT is not set
831CONFIG_CRC16=m
729CONFIG_CRC32=y 832CONFIG_CRC32=y
730# CONFIG_LIBCRC32C is not set 833CONFIG_LIBCRC32C=m
731CONFIG_ZLIB_INFLATE=y 834CONFIG_ZLIB_INFLATE=m
732CONFIG_ZLIB_DEFLATE=y 835CONFIG_ZLIB_DEFLATE=m
733CONFIG_GENERIC_HARDIRQS=y
734CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig
index dd07e866b128..d835f6db1f41 100644
--- a/arch/mips/configs/sead_defconfig
+++ b/arch/mips/configs/sead_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:10 2005 4# Thu Oct 20 22:27:07 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,22 +11,26 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
22CONFIG_SWAP=y 20CONFIG_LOCALVERSION_AUTO=y
23# CONFIG_SYSVIPC is not set 21# CONFIG_SWAP is not set
22CONFIG_SYSVIPC=y
24# CONFIG_BSD_PROCESS_ACCT is not set 23# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y 24CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set
27CONFIG_LOG_BUF_SHIFT=14
28# CONFIG_HOTPLUG is not set 25# CONFIG_HOTPLUG is not set
29# CONFIG_IKCONFIG is not set 26# CONFIG_IKCONFIG is not set
27CONFIG_INITRAMFS_SOURCE=""
30CONFIG_EMBEDDED=y 28CONFIG_EMBEDDED=y
31CONFIG_KALLSYMS=y 29CONFIG_KALLSYMS=y
32# CONFIG_KALLSYMS_EXTRA_PASS is not set 30# CONFIG_KALLSYMS_EXTRA_PASS is not set
31CONFIG_PRINTK=y
32CONFIG_BUG=y
33CONFIG_BASE_FULL=y
33CONFIG_FUTEX=y 34CONFIG_FUTEX=y
34CONFIG_EPOLL=y 35CONFIG_EPOLL=y
35# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 36# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -39,6 +40,7 @@ CONFIG_CC_ALIGN_LABELS=0
39CONFIG_CC_ALIGN_LOOPS=0 40CONFIG_CC_ALIGN_LOOPS=0
40CONFIG_CC_ALIGN_JUMPS=0 41CONFIG_CC_ALIGN_JUMPS=0
41# CONFIG_TINY_SHMEM is not set 42# CONFIG_TINY_SHMEM is not set
43CONFIG_BASE_SMALL=0
42 44
43# 45#
44# Loadable module support 46# Loadable module support
@@ -48,40 +50,69 @@ CONFIG_CC_ALIGN_JUMPS=0
48# 50#
49# Machine selection 51# Machine selection
50# 52#
51# CONFIG_MACH_JAZZ is not set 53# CONFIG_MIPS_MTX1 is not set
52# CONFIG_MACH_VR41XX is not set 54# CONFIG_MIPS_BOSPORUS is not set
53# CONFIG_TOSHIBA_JMR3927 is not set 55# CONFIG_MIPS_PB1000 is not set
56# CONFIG_MIPS_PB1100 is not set
57# CONFIG_MIPS_PB1500 is not set
58# CONFIG_MIPS_PB1550 is not set
59# CONFIG_MIPS_PB1200 is not set
60# CONFIG_MIPS_DB1000 is not set
61# CONFIG_MIPS_DB1100 is not set
62# CONFIG_MIPS_DB1500 is not set
63# CONFIG_MIPS_DB1550 is not set
64# CONFIG_MIPS_DB1200 is not set
65# CONFIG_MIPS_MIRAGE is not set
54# CONFIG_MIPS_COBALT is not set 66# CONFIG_MIPS_COBALT is not set
55# CONFIG_MACH_DECSTATION is not set 67# CONFIG_MACH_DECSTATION is not set
56# CONFIG_MIPS_EV64120 is not set 68# CONFIG_MIPS_EV64120 is not set
57# CONFIG_MIPS_EV96100 is not set 69# CONFIG_MIPS_EV96100 is not set
58# CONFIG_MIPS_IVR is not set 70# CONFIG_MIPS_IVR is not set
59# CONFIG_LASAT is not set
60# CONFIG_MIPS_ITE8172 is not set 71# CONFIG_MIPS_ITE8172 is not set
72# CONFIG_MACH_JAZZ is not set
73# CONFIG_LASAT is not set
61# CONFIG_MIPS_ATLAS is not set 74# CONFIG_MIPS_ATLAS is not set
62# CONFIG_MIPS_MALTA is not set 75# CONFIG_MIPS_MALTA is not set
63CONFIG_MIPS_SEAD=y 76CONFIG_MIPS_SEAD=y
77# CONFIG_MIPS_SIM is not set
78# CONFIG_MOMENCO_JAGUAR_ATX is not set
64# CONFIG_MOMENCO_OCELOT is not set 79# CONFIG_MOMENCO_OCELOT is not set
65# CONFIG_MOMENCO_OCELOT_G is not set
66# CONFIG_MOMENCO_OCELOT_C is not set
67# CONFIG_MOMENCO_OCELOT_3 is not set 80# CONFIG_MOMENCO_OCELOT_3 is not set
68# CONFIG_MOMENCO_JAGUAR_ATX is not set 81# CONFIG_MOMENCO_OCELOT_C is not set
69# CONFIG_PMC_YOSEMITE is not set 82# CONFIG_MOMENCO_OCELOT_G is not set
83# CONFIG_MIPS_XXS1500 is not set
84# CONFIG_PNX8550_V2PCI is not set
85# CONFIG_PNX8550_JBS is not set
70# CONFIG_DDB5074 is not set 86# CONFIG_DDB5074 is not set
71# CONFIG_DDB5476 is not set 87# CONFIG_DDB5476 is not set
72# CONFIG_DDB5477 is not set 88# CONFIG_DDB5477 is not set
73# CONFIG_NEC_OSPREY is not set 89# CONFIG_MACH_VR41XX is not set
90# CONFIG_PMC_YOSEMITE is not set
91# CONFIG_QEMU is not set
74# CONFIG_SGI_IP22 is not set 92# CONFIG_SGI_IP22 is not set
75# CONFIG_SOC_AU1X00 is not set 93# CONFIG_SGI_IP27 is not set
76# CONFIG_SIBYTE_SB1xxx_SOC is not set 94# CONFIG_SGI_IP32 is not set
95# CONFIG_SIBYTE_BIGSUR is not set
96# CONFIG_SIBYTE_SWARM is not set
97# CONFIG_SIBYTE_SENTOSA is not set
98# CONFIG_SIBYTE_RHONE is not set
99# CONFIG_SIBYTE_CARMEL is not set
100# CONFIG_SIBYTE_PTSWARM is not set
101# CONFIG_SIBYTE_LITTLESUR is not set
102# CONFIG_SIBYTE_CRHINE is not set
103# CONFIG_SIBYTE_CRHONE is not set
77# CONFIG_SNI_RM200_PCI is not set 104# CONFIG_SNI_RM200_PCI is not set
105# CONFIG_TOSHIBA_JMR3927 is not set
78# CONFIG_TOSHIBA_RBTX4927 is not set 106# CONFIG_TOSHIBA_RBTX4927 is not set
107# CONFIG_TOSHIBA_RBTX4938 is not set
79CONFIG_RWSEM_GENERIC_SPINLOCK=y 108CONFIG_RWSEM_GENERIC_SPINLOCK=y
80CONFIG_GENERIC_CALIBRATE_DELAY=y 109CONFIG_GENERIC_CALIBRATE_DELAY=y
81CONFIG_HAVE_DEC_LOCK=y
82CONFIG_DMA_NONCOHERENT=y 110CONFIG_DMA_NONCOHERENT=y
83CONFIG_DMA_NEED_PCI_MAP_STATE=y 111CONFIG_DMA_NEED_PCI_MAP_STATE=y
112# CONFIG_CPU_BIG_ENDIAN is not set
84CONFIG_CPU_LITTLE_ENDIAN=y 113CONFIG_CPU_LITTLE_ENDIAN=y
114CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
115CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
85CONFIG_IRQ_CPU=y 116CONFIG_IRQ_CPU=y
86CONFIG_MIPS_BOARDS_GEN=y 117CONFIG_MIPS_BOARDS_GEN=y
87CONFIG_MIPS_L1_CACHE_SHIFT=5 118CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -89,8 +120,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
89# 120#
90# CPU selection 121# CPU selection
91# 122#
92CONFIG_CPU_MIPS32=y 123CONFIG_CPU_MIPS32_R1=y
93# CONFIG_CPU_MIPS64 is not set 124# CONFIG_CPU_MIPS32_R2 is not set
125# CONFIG_CPU_MIPS64_R1 is not set
126# CONFIG_CPU_MIPS64_R2 is not set
94# CONFIG_CPU_R3000 is not set 127# CONFIG_CPU_R3000 is not set
95# CONFIG_CPU_TX39XX is not set 128# CONFIG_CPU_TX39XX is not set
96# CONFIG_CPU_VR41XX is not set 129# CONFIG_CPU_VR41XX is not set
@@ -106,15 +139,42 @@ CONFIG_CPU_MIPS32=y
106# CONFIG_CPU_RM7000 is not set 139# CONFIG_CPU_RM7000 is not set
107# CONFIG_CPU_RM9000 is not set 140# CONFIG_CPU_RM9000 is not set
108# CONFIG_CPU_SB1 is not set 141# CONFIG_CPU_SB1 is not set
142CONFIG_SYS_HAS_CPU_MIPS32_R1=y
143CONFIG_SYS_HAS_CPU_MIPS32_R2=y
144CONFIG_SYS_HAS_CPU_MIPS64_R1=y
145CONFIG_CPU_MIPS32=y
146CONFIG_CPU_MIPSR1=y
147CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
148CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
149CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
150
151#
152# Kernel type
153#
154CONFIG_32BIT=y
155# CONFIG_64BIT is not set
109CONFIG_PAGE_SIZE_4KB=y 156CONFIG_PAGE_SIZE_4KB=y
110# CONFIG_PAGE_SIZE_8KB is not set 157# CONFIG_PAGE_SIZE_8KB is not set
111# CONFIG_PAGE_SIZE_16KB is not set 158# CONFIG_PAGE_SIZE_16KB is not set
112# CONFIG_PAGE_SIZE_64KB is not set 159# CONFIG_PAGE_SIZE_64KB is not set
113CONFIG_CPU_HAS_PREFETCH=y 160CONFIG_CPU_HAS_PREFETCH=y
161# CONFIG_MIPS_MT is not set
114# CONFIG_64BIT_PHYS_ADDR is not set 162# CONFIG_64BIT_PHYS_ADDR is not set
115# CONFIG_CPU_ADVANCED is not set 163# CONFIG_CPU_ADVANCED is not set
116CONFIG_CPU_HAS_LLSC=y 164CONFIG_CPU_HAS_LLSC=y
117CONFIG_CPU_HAS_SYNC=y 165CONFIG_CPU_HAS_SYNC=y
166CONFIG_GENERIC_HARDIRQS=y
167CONFIG_GENERIC_IRQ_PROBE=y
168CONFIG_ARCH_FLATMEM_ENABLE=y
169CONFIG_SELECT_MEMORY_MODEL=y
170CONFIG_FLATMEM_MANUAL=y
171# CONFIG_DISCONTIGMEM_MANUAL is not set
172# CONFIG_SPARSEMEM_MANUAL is not set
173CONFIG_FLATMEM=y
174CONFIG_FLAT_NODE_MEM_MAP=y
175# CONFIG_SPARSEMEM_STATIC is not set
176CONFIG_PREEMPT_NONE=y
177# CONFIG_PREEMPT_VOLUNTARY is not set
118# CONFIG_PREEMPT is not set 178# CONFIG_PREEMPT is not set
119 179
120# 180#
@@ -128,10 +188,6 @@ CONFIG_MMU=y
128# CONFIG_PCCARD is not set 188# CONFIG_PCCARD is not set
129 189
130# 190#
131# PC-card bridges
132#
133
134#
135# PCI Hotplug Support 191# PCI Hotplug Support
136# 192#
137 193
@@ -143,6 +199,11 @@ CONFIG_BINFMT_ELF=y
143CONFIG_TRAD_SIGNALS=y 199CONFIG_TRAD_SIGNALS=y
144 200
145# 201#
202# Networking
203#
204# CONFIG_NET is not set
205
206#
146# Device Drivers 207# Device Drivers
147# 208#
148 209
@@ -154,6 +215,10 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
154# CONFIG_FW_LOADER is not set 215# CONFIG_FW_LOADER is not set
155 216
156# 217#
218# Connector - unified userspace <-> kernelspace linker
219#
220
221#
157# Memory Technology Devices (MTD) 222# Memory Technology Devices (MTD)
158# 223#
159# CONFIG_MTD is not set 224# CONFIG_MTD is not set
@@ -170,7 +235,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
170# 235#
171# Block devices 236# Block devices
172# 237#
173# CONFIG_BLK_DEV_FD is not set
174# CONFIG_BLK_DEV_COW_COMMON is not set 238# CONFIG_BLK_DEV_COW_COMMON is not set
175CONFIG_BLK_DEV_LOOP=y 239CONFIG_BLK_DEV_LOOP=y
176# CONFIG_BLK_DEV_CRYPTOLOOP is not set 240# CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -178,11 +242,8 @@ CONFIG_BLK_DEV_RAM=y
178CONFIG_BLK_DEV_RAM_COUNT=16 242CONFIG_BLK_DEV_RAM_COUNT=16
179CONFIG_BLK_DEV_RAM_SIZE=18432 243CONFIG_BLK_DEV_RAM_SIZE=18432
180CONFIG_BLK_DEV_INITRD=y 244CONFIG_BLK_DEV_INITRD=y
181CONFIG_INITRAMFS_SOURCE=""
182# CONFIG_LBD is not set 245# CONFIG_LBD is not set
183CONFIG_CDROM_PKTCDVD=y 246# CONFIG_CDROM_PKTCDVD is not set
184CONFIG_CDROM_PKTCDVD_BUFFERS=8
185# CONFIG_CDROM_PKTCDVD_WCACHE is not set
186 247
187# 248#
188# IO Schedulers 249# IO Schedulers
@@ -200,6 +261,7 @@ CONFIG_IOSCHED_CFQ=y
200# 261#
201# SCSI device support 262# SCSI device support
202# 263#
264CONFIG_RAID_ATTRS=y
203# CONFIG_SCSI is not set 265# CONFIG_SCSI is not set
204 266
205# 267#
@@ -210,6 +272,7 @@ CONFIG_IOSCHED_CFQ=y
210# 272#
211# Fusion MPT device support 273# Fusion MPT device support
212# 274#
275# CONFIG_FUSION is not set
213 276
214# 277#
215# IEEE 1394 (FireWire) support 278# IEEE 1394 (FireWire) support
@@ -220,9 +283,8 @@ CONFIG_IOSCHED_CFQ=y
220# 283#
221 284
222# 285#
223# Networking support 286# Network device support
224# 287#
225# CONFIG_NET is not set
226# CONFIG_NETPOLL is not set 288# CONFIG_NETPOLL is not set
227# CONFIG_NET_POLL_CONTROLLER is not set 289# CONFIG_NET_POLL_CONTROLLER is not set
228 290
@@ -238,47 +300,18 @@ CONFIG_IOSCHED_CFQ=y
238# 300#
239# Input device support 301# Input device support
240# 302#
241CONFIG_INPUT=y 303# CONFIG_INPUT is not set
242 304
243# 305#
244# Userland interfaces 306# Hardware I/O ports
245#
246CONFIG_INPUT_MOUSEDEV=y
247CONFIG_INPUT_MOUSEDEV_PSAUX=y
248CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
249CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
250# CONFIG_INPUT_JOYDEV is not set
251# CONFIG_INPUT_TSDEV is not set
252# CONFIG_INPUT_EVDEV is not set
253# CONFIG_INPUT_EVBUG is not set
254
255#
256# Input I/O drivers
257# 307#
308# CONFIG_SERIO is not set
258# CONFIG_GAMEPORT is not set 309# CONFIG_GAMEPORT is not set
259CONFIG_SOUND_GAMEPORT=y
260CONFIG_SERIO=y
261# CONFIG_SERIO_I8042 is not set
262CONFIG_SERIO_SERPORT=y
263# CONFIG_SERIO_CT82C710 is not set
264# CONFIG_SERIO_LIBPS2 is not set
265CONFIG_SERIO_RAW=y
266
267#
268# Input Device Drivers
269#
270# CONFIG_INPUT_KEYBOARD is not set
271# CONFIG_INPUT_MOUSE is not set
272# CONFIG_INPUT_JOYSTICK is not set
273# CONFIG_INPUT_TOUCHSCREEN is not set
274# CONFIG_INPUT_MISC is not set
275 310
276# 311#
277# Character devices 312# Character devices
278# 313#
279CONFIG_VT=y 314# CONFIG_VT is not set
280CONFIG_VT_CONSOLE=y
281CONFIG_HW_CONSOLE=y
282# CONFIG_SERIAL_NONSTANDARD is not set 315# CONFIG_SERIAL_NONSTANDARD is not set
283 316
284# 317#
@@ -294,7 +327,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
294# 327#
295CONFIG_SERIAL_CORE=y 328CONFIG_SERIAL_CORE=y
296CONFIG_SERIAL_CORE_CONSOLE=y 329CONFIG_SERIAL_CORE_CONSOLE=y
297# CONFIG_UNIX98_PTYS is not set 330CONFIG_UNIX98_PTYS=y
298CONFIG_LEGACY_PTYS=y 331CONFIG_LEGACY_PTYS=y
299CONFIG_LEGACY_PTY_COUNT=256 332CONFIG_LEGACY_PTY_COUNT=256
300 333
@@ -315,10 +348,13 @@ CONFIG_LEGACY_PTY_COUNT=256
315# 348#
316# Ftape, the floppy tape device driver 349# Ftape, the floppy tape device driver
317# 350#
318# CONFIG_DRM is not set
319# CONFIG_RAW_DRIVER is not set 351# CONFIG_RAW_DRIVER is not set
320 352
321# 353#
354# TPM devices
355#
356
357#
322# I2C support 358# I2C support
323# 359#
324# CONFIG_I2C is not set 360# CONFIG_I2C is not set
@@ -329,10 +365,20 @@ CONFIG_LEGACY_PTY_COUNT=256
329# CONFIG_W1 is not set 365# CONFIG_W1 is not set
330 366
331# 367#
368# Hardware Monitoring support
369#
370# CONFIG_HWMON is not set
371# CONFIG_HWMON_VID is not set
372
373#
332# Misc devices 374# Misc devices
333# 375#
334 376
335# 377#
378# Multimedia Capabilities Port drivers
379#
380
381#
336# Multimedia devices 382# Multimedia devices
337# 383#
338# CONFIG_VIDEO_DEV is not set 384# CONFIG_VIDEO_DEV is not set
@@ -347,13 +393,6 @@ CONFIG_LEGACY_PTY_COUNT=256
347# CONFIG_FB is not set 393# CONFIG_FB is not set
348 394
349# 395#
350# Console display driver support
351#
352# CONFIG_VGA_CONSOLE is not set
353CONFIG_DUMMY_CONSOLE=y
354# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
355
356#
357# Sound 396# Sound
358# 397#
359# CONFIG_SOUND is not set 398# CONFIG_SOUND is not set
@@ -365,10 +404,6 @@ CONFIG_DUMMY_CONSOLE=y
365# CONFIG_USB_ARCH_HAS_OHCI is not set 404# CONFIG_USB_ARCH_HAS_OHCI is not set
366 405
367# 406#
368# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
369#
370
371#
372# USB Gadget Support 407# USB Gadget Support
373# 408#
374# CONFIG_USB_GADGET is not set 409# CONFIG_USB_GADGET is not set
@@ -381,28 +416,31 @@ CONFIG_DUMMY_CONSOLE=y
381# 416#
382# InfiniBand support 417# InfiniBand support
383# 418#
384# CONFIG_INFINIBAND is not set 419
420#
421# SN Devices
422#
385 423
386# 424#
387# File systems 425# File systems
388# 426#
389CONFIG_EXT2_FS=y 427CONFIG_EXT2_FS=y
390CONFIG_EXT2_FS_XATTR=y 428# CONFIG_EXT2_FS_XATTR is not set
391CONFIG_EXT2_FS_POSIX_ACL=y 429# CONFIG_EXT2_FS_XIP is not set
392CONFIG_EXT2_FS_SECURITY=y
393# CONFIG_EXT3_FS is not set 430# CONFIG_EXT3_FS is not set
394# CONFIG_JBD is not set 431# CONFIG_JBD is not set
395CONFIG_FS_MBCACHE=y
396# CONFIG_REISERFS_FS is not set 432# CONFIG_REISERFS_FS is not set
397# CONFIG_JFS_FS is not set 433# CONFIG_JFS_FS is not set
398CONFIG_FS_POSIX_ACL=y 434# CONFIG_FS_POSIX_ACL is not set
399# CONFIG_XFS_FS is not set 435# CONFIG_XFS_FS is not set
400# CONFIG_MINIX_FS is not set 436# CONFIG_MINIX_FS is not set
401# CONFIG_ROMFS_FS is not set 437# CONFIG_ROMFS_FS is not set
438CONFIG_INOTIFY=y
402# CONFIG_QUOTA is not set 439# CONFIG_QUOTA is not set
403CONFIG_DNOTIFY=y 440CONFIG_DNOTIFY=y
404# CONFIG_AUTOFS_FS is not set 441# CONFIG_AUTOFS_FS is not set
405# CONFIG_AUTOFS4_FS is not set 442# CONFIG_AUTOFS4_FS is not set
443CONFIG_FUSE_FS=y
406 444
407# 445#
408# CD-ROM/DVD Filesystems 446# CD-ROM/DVD Filesystems
@@ -423,10 +461,10 @@ CONFIG_DNOTIFY=y
423CONFIG_PROC_FS=y 461CONFIG_PROC_FS=y
424CONFIG_PROC_KCORE=y 462CONFIG_PROC_KCORE=y
425CONFIG_SYSFS=y 463CONFIG_SYSFS=y
426# CONFIG_DEVFS_FS is not set
427# CONFIG_TMPFS is not set 464# CONFIG_TMPFS is not set
428# CONFIG_HUGETLB_PAGE is not set 465# CONFIG_HUGETLB_PAGE is not set
429CONFIG_RAMFS=y 466CONFIG_RAMFS=y
467CONFIG_RELAYFS_FS=y
430 468
431# 469#
432# Miscellaneous filesystems 470# Miscellaneous filesystems
@@ -448,8 +486,18 @@ CONFIG_RAMFS=y
448# 486#
449# Partition Types 487# Partition Types
450# 488#
451# CONFIG_PARTITION_ADVANCED is not set 489CONFIG_PARTITION_ADVANCED=y
452CONFIG_MSDOS_PARTITION=y 490# CONFIG_ACORN_PARTITION is not set
491# CONFIG_OSF_PARTITION is not set
492# CONFIG_AMIGA_PARTITION is not set
493# CONFIG_ATARI_PARTITION is not set
494# CONFIG_MAC_PARTITION is not set
495# CONFIG_MSDOS_PARTITION is not set
496# CONFIG_LDM_PARTITION is not set
497# CONFIG_SGI_PARTITION is not set
498# CONFIG_ULTRIX_PARTITION is not set
499# CONFIG_SUN_PARTITION is not set
500# CONFIG_EFI_PARTITION is not set
453 501
454# 502#
455# Native Language Support 503# Native Language Support
@@ -464,15 +512,16 @@ CONFIG_MSDOS_PARTITION=y
464# 512#
465# Kernel hacking 513# Kernel hacking
466# 514#
515# CONFIG_PRINTK_TIME is not set
467# CONFIG_DEBUG_KERNEL is not set 516# CONFIG_DEBUG_KERNEL is not set
517CONFIG_LOG_BUF_SHIFT=14
468CONFIG_CROSSCOMPILE=y 518CONFIG_CROSSCOMPILE=y
469CONFIG_CMDLINE="" 519CONFIG_CMDLINE=""
470 520
471# 521#
472# Security options 522# Security options
473# 523#
474CONFIG_KEYS=y 524# CONFIG_KEYS is not set
475CONFIG_KEYS_DEBUG_PROC_KEYS=y
476# CONFIG_SECURITY is not set 525# CONFIG_SECURITY is not set
477 526
478# 527#
@@ -488,7 +537,6 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
488# Library routines 537# Library routines
489# 538#
490# CONFIG_CRC_CCITT is not set 539# CONFIG_CRC_CCITT is not set
540CONFIG_CRC16=y
491# CONFIG_CRC32 is not set 541# CONFIG_CRC32 is not set
492# CONFIG_LIBCRC32C is not set 542# CONFIG_LIBCRC32C is not set
493CONFIG_GENERIC_HARDIRQS=y
494CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index c9d3f83caf0f..bf60a17de2b0 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:12 2005 4# Thu Oct 20 22:27:10 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29# CONFIG_HOTPLUG is not set 27# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,55 +59,87 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60CONFIG_MACH_VR41XX=y 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_NEC_CMBVR4133 is not set 64# CONFIG_MIPS_PB1000 is not set
62# CONFIG_CASIO_E55 is not set 65# CONFIG_MIPS_PB1100 is not set
63# CONFIG_IBM_WORKPAD is not set 66# CONFIG_MIPS_PB1500 is not set
64CONFIG_TANBAC_TB0226=y 67# CONFIG_MIPS_PB1550 is not set
65# CONFIG_TANBAC_TB0229 is not set 68# CONFIG_MIPS_PB1200 is not set
66# CONFIG_VICTOR_MPC30X is not set 69# CONFIG_MIPS_DB1000 is not set
67# CONFIG_ZAO_CAPCELLA is not set 70# CONFIG_MIPS_DB1100 is not set
68# CONFIG_TOSHIBA_JMR3927 is not set 71# CONFIG_MIPS_DB1500 is not set
72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
69# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
70# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
71# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
72# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
73# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
74# CONFIG_LASAT is not set
75# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
76# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
77# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
78# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
79# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
80# CONFIG_MOMENCO_OCELOT_G is not set
81# CONFIG_MOMENCO_OCELOT_C is not set
82# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
83# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
84# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
85# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
86# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
87# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
88# CONFIG_NEC_OSPREY is not set 98CONFIG_MACH_VR41XX=y
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
89# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
90# CONFIG_SOC_AU1X00 is not set 102# CONFIG_SGI_IP27 is not set
91# CONFIG_SIBYTE_SB1xxx_SOC is not set 103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
92# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
93# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
117# CONFIG_NEC_CMBVR4133 is not set
118# CONFIG_CASIO_E55 is not set
119# CONFIG_IBM_WORKPAD is not set
120CONFIG_TANBAC_TB022X=y
121CONFIG_TANBAC_TB0226=y
122# CONFIG_VICTOR_MPC30X is not set
123# CONFIG_ZAO_CAPCELLA is not set
124CONFIG_PCI_VR41XX=y
125# CONFIG_VRC4173 is not set
94CONFIG_RWSEM_GENERIC_SPINLOCK=y 126CONFIG_RWSEM_GENERIC_SPINLOCK=y
95CONFIG_GENERIC_CALIBRATE_DELAY=y 127CONFIG_GENERIC_CALIBRATE_DELAY=y
96CONFIG_HAVE_DEC_LOCK=y
97CONFIG_DMA_NONCOHERENT=y 128CONFIG_DMA_NONCOHERENT=y
98CONFIG_DMA_NEED_PCI_MAP_STATE=y 129CONFIG_DMA_NEED_PCI_MAP_STATE=y
130# CONFIG_CPU_BIG_ENDIAN is not set
99CONFIG_CPU_LITTLE_ENDIAN=y 131CONFIG_CPU_LITTLE_ENDIAN=y
132CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
100CONFIG_IRQ_CPU=y 133CONFIG_IRQ_CPU=y
101CONFIG_MIPS_L1_CACHE_SHIFT=5 134CONFIG_MIPS_L1_CACHE_SHIFT=5
102 135
103# 136#
104# CPU selection 137# CPU selection
105# 138#
106# CONFIG_CPU_MIPS32 is not set 139# CONFIG_CPU_MIPS32_R1 is not set
107# CONFIG_CPU_MIPS64 is not set 140# CONFIG_CPU_MIPS32_R2 is not set
141# CONFIG_CPU_MIPS64_R1 is not set
142# CONFIG_CPU_MIPS64_R2 is not set
108# CONFIG_CPU_R3000 is not set 143# CONFIG_CPU_R3000 is not set
109# CONFIG_CPU_TX39XX is not set 144# CONFIG_CPU_TX39XX is not set
110CONFIG_CPU_VR41XX=y 145CONFIG_CPU_VR41XX=y
@@ -120,19 +155,44 @@ CONFIG_CPU_VR41XX=y
120# CONFIG_CPU_RM7000 is not set 155# CONFIG_CPU_RM7000 is not set
121# CONFIG_CPU_RM9000 is not set 156# CONFIG_CPU_RM9000 is not set
122# CONFIG_CPU_SB1 is not set 157# CONFIG_CPU_SB1 is not set
158CONFIG_SYS_HAS_CPU_VR41XX=y
159CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
160CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
161CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
162CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
163
164#
165# Kernel type
166#
167CONFIG_32BIT=y
168# CONFIG_64BIT is not set
123CONFIG_PAGE_SIZE_4KB=y 169CONFIG_PAGE_SIZE_4KB=y
124# CONFIG_PAGE_SIZE_8KB is not set 170# CONFIG_PAGE_SIZE_8KB is not set
125# CONFIG_PAGE_SIZE_16KB is not set 171# CONFIG_PAGE_SIZE_16KB is not set
126# CONFIG_PAGE_SIZE_64KB is not set 172# CONFIG_PAGE_SIZE_64KB is not set
173# CONFIG_MIPS_MT is not set
127# CONFIG_CPU_ADVANCED is not set 174# CONFIG_CPU_ADVANCED is not set
128CONFIG_CPU_HAS_SYNC=y 175CONFIG_CPU_HAS_SYNC=y
176CONFIG_GENERIC_HARDIRQS=y
177CONFIG_GENERIC_IRQ_PROBE=y
178CONFIG_ARCH_FLATMEM_ENABLE=y
179CONFIG_SELECT_MEMORY_MODEL=y
180CONFIG_FLATMEM_MANUAL=y
181# CONFIG_DISCONTIGMEM_MANUAL is not set
182# CONFIG_SPARSEMEM_MANUAL is not set
183CONFIG_FLATMEM=y
184CONFIG_FLAT_NODE_MEM_MAP=y
185# CONFIG_SPARSEMEM_STATIC is not set
186CONFIG_PREEMPT_NONE=y
187# CONFIG_PREEMPT_VOLUNTARY is not set
129# CONFIG_PREEMPT is not set 188# CONFIG_PREEMPT is not set
130 189
131# 190#
132# Bus options (PCI, PCMCIA, EISA, ISA, TC) 191# Bus options (PCI, PCMCIA, EISA, ISA, TC)
133# 192#
134CONFIG_HW_HAS_PCI=y 193CONFIG_HW_HAS_PCI=y
135# CONFIG_PCI is not set 194CONFIG_PCI=y
195# CONFIG_PCI_LEGACY_PROC is not set
136CONFIG_MMU=y 196CONFIG_MMU=y
137 197
138# 198#
@@ -141,12 +201,9 @@ CONFIG_MMU=y
141# CONFIG_PCCARD is not set 201# CONFIG_PCCARD is not set
142 202
143# 203#
144# PC-card bridges
145#
146
147#
148# PCI Hotplug Support 204# PCI Hotplug Support
149# 205#
206# CONFIG_HOTPLUG_PCI is not set
150 207
151# 208#
152# Executable file formats 209# Executable file formats
@@ -156,6 +213,87 @@ CONFIG_BINFMT_ELF=y
156CONFIG_TRAD_SIGNALS=y 213CONFIG_TRAD_SIGNALS=y
157 214
158# 215#
216# Networking
217#
218CONFIG_NET=y
219
220#
221# Networking options
222#
223CONFIG_PACKET=y
224# CONFIG_PACKET_MMAP is not set
225CONFIG_UNIX=y
226CONFIG_XFRM=y
227CONFIG_XFRM_USER=m
228# CONFIG_NET_KEY is not set
229CONFIG_INET=y
230CONFIG_IP_MULTICAST=y
231CONFIG_IP_ADVANCED_ROUTER=y
232CONFIG_ASK_IP_FIB_HASH=y
233# CONFIG_IP_FIB_TRIE is not set
234CONFIG_IP_FIB_HASH=y
235CONFIG_IP_MULTIPLE_TABLES=y
236CONFIG_IP_ROUTE_MULTIPATH=y
237# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
238CONFIG_IP_ROUTE_VERBOSE=y
239CONFIG_IP_PNP=y
240# CONFIG_IP_PNP_DHCP is not set
241CONFIG_IP_PNP_BOOTP=y
242# CONFIG_IP_PNP_RARP is not set
243# CONFIG_NET_IPIP is not set
244# CONFIG_NET_IPGRE is not set
245# CONFIG_IP_MROUTE is not set
246# CONFIG_ARPD is not set
247CONFIG_SYN_COOKIES=y
248# CONFIG_INET_AH is not set
249# CONFIG_INET_ESP is not set
250# CONFIG_INET_IPCOMP is not set
251CONFIG_INET_TUNNEL=m
252CONFIG_INET_DIAG=y
253CONFIG_INET_TCP_DIAG=y
254# CONFIG_TCP_CONG_ADVANCED is not set
255CONFIG_TCP_CONG_BIC=y
256# CONFIG_IPV6 is not set
257# CONFIG_NETFILTER is not set
258
259#
260# DCCP Configuration (EXPERIMENTAL)
261#
262# CONFIG_IP_DCCP is not set
263
264#
265# SCTP Configuration (EXPERIMENTAL)
266#
267# CONFIG_IP_SCTP is not set
268# CONFIG_ATM is not set
269# CONFIG_BRIDGE is not set
270# CONFIG_VLAN_8021Q is not set
271# CONFIG_DECNET is not set
272# CONFIG_LLC2 is not set
273# CONFIG_IPX is not set
274# CONFIG_ATALK is not set
275# CONFIG_X25 is not set
276# CONFIG_LAPB is not set
277# CONFIG_NET_DIVERT is not set
278# CONFIG_ECONET is not set
279# CONFIG_WAN_ROUTER is not set
280# CONFIG_NET_SCHED is not set
281# CONFIG_NET_CLS_ROUTE is not set
282
283#
284# Network testing
285#
286# CONFIG_NET_PKTGEN is not set
287# CONFIG_HAMRADIO is not set
288# CONFIG_IRDA is not set
289# CONFIG_BT is not set
290CONFIG_IEEE80211=m
291# CONFIG_IEEE80211_DEBUG is not set
292CONFIG_IEEE80211_CRYPT_WEP=m
293CONFIG_IEEE80211_CRYPT_CCMP=m
294CONFIG_IEEE80211_CRYPT_TKIP=m
295
296#
159# Device Drivers 297# Device Drivers
160# 298#
161 299
@@ -167,6 +305,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
167# CONFIG_FW_LOADER is not set 305# CONFIG_FW_LOADER is not set
168 306
169# 307#
308# Connector - unified userspace <-> kernelspace linker
309#
310CONFIG_CONNECTOR=m
311
312#
170# Memory Technology Devices (MTD) 313# Memory Technology Devices (MTD)
171# 314#
172# CONFIG_MTD is not set 315# CONFIG_MTD is not set
@@ -183,19 +326,21 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
183# 326#
184# Block devices 327# Block devices
185# 328#
186# CONFIG_BLK_DEV_FD is not set 329# CONFIG_BLK_CPQ_DA is not set
330# CONFIG_BLK_CPQ_CISS_DA is not set
331# CONFIG_BLK_DEV_DAC960 is not set
332# CONFIG_BLK_DEV_UMEM is not set
187# CONFIG_BLK_DEV_COW_COMMON is not set 333# CONFIG_BLK_DEV_COW_COMMON is not set
188CONFIG_BLK_DEV_LOOP=m 334CONFIG_BLK_DEV_LOOP=m
189# CONFIG_BLK_DEV_CRYPTOLOOP is not set 335# CONFIG_BLK_DEV_CRYPTOLOOP is not set
190CONFIG_BLK_DEV_NBD=m 336CONFIG_BLK_DEV_NBD=m
337# CONFIG_BLK_DEV_SX8 is not set
338# CONFIG_BLK_DEV_UB is not set
191CONFIG_BLK_DEV_RAM=m 339CONFIG_BLK_DEV_RAM=m
192CONFIG_BLK_DEV_RAM_COUNT=16 340CONFIG_BLK_DEV_RAM_COUNT=16
193CONFIG_BLK_DEV_RAM_SIZE=4096 341CONFIG_BLK_DEV_RAM_SIZE=4096
194CONFIG_INITRAMFS_SOURCE=""
195# CONFIG_LBD is not set 342# CONFIG_LBD is not set
196CONFIG_CDROM_PKTCDVD=m 343# CONFIG_CDROM_PKTCDVD is not set
197CONFIG_CDROM_PKTCDVD_BUFFERS=8
198# CONFIG_CDROM_PKTCDVD_WCACHE is not set
199 344
200# 345#
201# IO Schedulers 346# IO Schedulers
@@ -209,33 +354,12 @@ CONFIG_ATA_OVER_ETH=m
209# 354#
210# ATA/ATAPI/MFM/RLL support 355# ATA/ATAPI/MFM/RLL support
211# 356#
212CONFIG_IDE=y 357# CONFIG_IDE is not set
213CONFIG_BLK_DEV_IDE=y
214
215#
216# Please see Documentation/ide.txt for help/info on IDE drives
217#
218# CONFIG_BLK_DEV_IDE_SATA is not set
219CONFIG_BLK_DEV_IDEDISK=y
220CONFIG_IDEDISK_MULTI_MODE=y
221# CONFIG_BLK_DEV_IDECD is not set
222# CONFIG_BLK_DEV_IDETAPE is not set
223# CONFIG_BLK_DEV_IDEFLOPPY is not set
224CONFIG_BLK_DEV_IDESCSI=y
225# CONFIG_IDE_TASK_IOCTL is not set
226
227#
228# IDE chipset support/bugfixes
229#
230CONFIG_IDE_GENERIC=y
231# CONFIG_IDE_ARM is not set
232# CONFIG_BLK_DEV_IDEDMA is not set
233# CONFIG_IDEDMA_AUTO is not set
234# CONFIG_BLK_DEV_HD is not set
235 358
236# 359#
237# SCSI device support 360# SCSI device support
238# 361#
362# CONFIG_RAID_ATTRS is not set
239CONFIG_SCSI=y 363CONFIG_SCSI=y
240CONFIG_SCSI_PROC_FS=y 364CONFIG_SCSI_PROC_FS=y
241 365
@@ -245,15 +369,15 @@ CONFIG_SCSI_PROC_FS=y
245CONFIG_BLK_DEV_SD=y 369CONFIG_BLK_DEV_SD=y
246# CONFIG_CHR_DEV_ST is not set 370# CONFIG_CHR_DEV_ST is not set
247# CONFIG_CHR_DEV_OSST is not set 371# CONFIG_CHR_DEV_OSST is not set
248CONFIG_BLK_DEV_SR=y 372# CONFIG_BLK_DEV_SR is not set
249# CONFIG_BLK_DEV_SR_VENDOR is not set 373# CONFIG_CHR_DEV_SG is not set
250CONFIG_CHR_DEV_SG=y 374# CONFIG_CHR_DEV_SCH is not set
251 375
252# 376#
253# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 377# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
254# 378#
255CONFIG_SCSI_MULTI_LUN=y 379CONFIG_SCSI_MULTI_LUN=y
256CONFIG_SCSI_CONSTANTS=y 380# CONFIG_SCSI_CONSTANTS is not set
257# CONFIG_SCSI_LOGGING is not set 381# CONFIG_SCSI_LOGGING is not set
258 382
259# 383#
@@ -262,11 +386,42 @@ CONFIG_SCSI_CONSTANTS=y
262# CONFIG_SCSI_SPI_ATTRS is not set 386# CONFIG_SCSI_SPI_ATTRS is not set
263# CONFIG_SCSI_FC_ATTRS is not set 387# CONFIG_SCSI_FC_ATTRS is not set
264# CONFIG_SCSI_ISCSI_ATTRS is not set 388# CONFIG_SCSI_ISCSI_ATTRS is not set
389# CONFIG_SCSI_SAS_ATTRS is not set
265 390
266# 391#
267# SCSI low-level drivers 392# SCSI low-level drivers
268# 393#
394# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
395# CONFIG_SCSI_3W_9XXX is not set
396# CONFIG_SCSI_ACARD is not set
397# CONFIG_SCSI_AACRAID is not set
398# CONFIG_SCSI_AIC7XXX is not set
399# CONFIG_SCSI_AIC7XXX_OLD is not set
400# CONFIG_SCSI_AIC79XX is not set
401# CONFIG_SCSI_DPT_I2O is not set
402# CONFIG_MEGARAID_NEWGEN is not set
403# CONFIG_MEGARAID_LEGACY is not set
269# CONFIG_SCSI_SATA is not set 404# CONFIG_SCSI_SATA is not set
405# CONFIG_SCSI_DMX3191D is not set
406# CONFIG_SCSI_FUTURE_DOMAIN is not set
407# CONFIG_SCSI_IPS is not set
408# CONFIG_SCSI_INITIO is not set
409# CONFIG_SCSI_INIA100 is not set
410# CONFIG_SCSI_SYM53C8XX_2 is not set
411# CONFIG_SCSI_IPR is not set
412# CONFIG_SCSI_QLOGIC_FC is not set
413# CONFIG_SCSI_QLOGIC_1280 is not set
414CONFIG_SCSI_QLA2XXX=y
415# CONFIG_SCSI_QLA21XX is not set
416# CONFIG_SCSI_QLA22XX is not set
417# CONFIG_SCSI_QLA2300 is not set
418# CONFIG_SCSI_QLA2322 is not set
419# CONFIG_SCSI_QLA6312 is not set
420# CONFIG_SCSI_QLA24XX is not set
421# CONFIG_SCSI_LPFC is not set
422# CONFIG_SCSI_DC395x is not set
423# CONFIG_SCSI_DC390T is not set
424# CONFIG_SCSI_NSP32 is not set
270# CONFIG_SCSI_DEBUG is not set 425# CONFIG_SCSI_DEBUG is not set
271 426
272# 427#
@@ -277,131 +432,132 @@ CONFIG_SCSI_CONSTANTS=y
277# 432#
278# Fusion MPT device support 433# Fusion MPT device support
279# 434#
435# CONFIG_FUSION is not set
436# CONFIG_FUSION_SPI is not set
437# CONFIG_FUSION_FC is not set
280 438
281# 439#
282# IEEE 1394 (FireWire) support 440# IEEE 1394 (FireWire) support
283# 441#
442# CONFIG_IEEE1394 is not set
284 443
285# 444#
286# I2O device support 445# I2O device support
287# 446#
447# CONFIG_I2O is not set
288 448
289# 449#
290# Networking support 450# Network device support
291#
292CONFIG_NET=y
293
294#
295# Networking options
296# 451#
297CONFIG_PACKET=y 452CONFIG_NETDEVICES=y
298# CONFIG_PACKET_MMAP is not set 453# CONFIG_DUMMY is not set
299CONFIG_NETLINK_DEV=m 454# CONFIG_BONDING is not set
300CONFIG_UNIX=y 455# CONFIG_EQUALIZER is not set
301# CONFIG_NET_KEY is not set 456# CONFIG_TUN is not set
302CONFIG_INET=y
303CONFIG_IP_MULTICAST=y
304CONFIG_IP_ADVANCED_ROUTER=y
305CONFIG_IP_MULTIPLE_TABLES=y
306CONFIG_IP_ROUTE_MULTIPATH=y
307CONFIG_IP_ROUTE_VERBOSE=y
308CONFIG_IP_PNP=y
309# CONFIG_IP_PNP_DHCP is not set
310CONFIG_IP_PNP_BOOTP=y
311# CONFIG_IP_PNP_RARP is not set
312# CONFIG_NET_IPIP is not set
313# CONFIG_NET_IPGRE is not set
314# CONFIG_IP_MROUTE is not set
315# CONFIG_ARPD is not set
316CONFIG_SYN_COOKIES=y
317# CONFIG_INET_AH is not set
318# CONFIG_INET_ESP is not set
319# CONFIG_INET_IPCOMP is not set
320CONFIG_INET_TUNNEL=m
321CONFIG_IP_TCPDIAG=m
322# CONFIG_IP_TCPDIAG_IPV6 is not set
323# CONFIG_IPV6 is not set
324# CONFIG_NETFILTER is not set
325CONFIG_XFRM=y
326CONFIG_XFRM_USER=m
327 457
328# 458#
329# SCTP Configuration (EXPERIMENTAL) 459# ARCnet devices
330# 460#
331# CONFIG_IP_SCTP is not set 461# CONFIG_ARCNET is not set
332# CONFIG_ATM is not set
333# CONFIG_BRIDGE is not set
334# CONFIG_VLAN_8021Q is not set
335# CONFIG_DECNET is not set
336# CONFIG_LLC2 is not set
337# CONFIG_IPX is not set
338# CONFIG_ATALK is not set
339# CONFIG_X25 is not set
340# CONFIG_LAPB is not set
341# CONFIG_NET_DIVERT is not set
342# CONFIG_ECONET is not set
343# CONFIG_WAN_ROUTER is not set
344 462
345# 463#
346# QoS and/or fair queueing 464# PHY device support
347# 465#
348# CONFIG_NET_SCHED is not set 466CONFIG_PHYLIB=m
349# CONFIG_NET_CLS_ROUTE is not set 467CONFIG_PHYCONTROL=y
350 468
351# 469#
352# Network testing 470# MII PHY device drivers
353# 471#
354# CONFIG_NET_PKTGEN is not set 472CONFIG_MARVELL_PHY=m
355# CONFIG_NETPOLL is not set 473CONFIG_DAVICOM_PHY=m
356# CONFIG_NET_POLL_CONTROLLER is not set 474CONFIG_QSEMI_PHY=m
357# CONFIG_HAMRADIO is not set 475CONFIG_LXT_PHY=m
358# CONFIG_IRDA is not set 476CONFIG_CICADA_PHY=m
359# CONFIG_BT is not set
360CONFIG_NETDEVICES=y
361# CONFIG_DUMMY is not set
362# CONFIG_BONDING is not set
363# CONFIG_EQUALIZER is not set
364# CONFIG_TUN is not set
365# CONFIG_ETHERTAP is not set
366 477
367# 478#
368# Ethernet (10 or 100Mbit) 479# Ethernet (10 or 100Mbit)
369# 480#
370CONFIG_NET_ETHERNET=y 481CONFIG_NET_ETHERNET=y
371# CONFIG_MII is not set 482CONFIG_MII=y
483# CONFIG_HAPPYMEAL is not set
484# CONFIG_SUNGEM is not set
485# CONFIG_NET_VENDOR_3COM is not set
486
487#
488# Tulip family network device support
489#
490# CONFIG_NET_TULIP is not set
491# CONFIG_HP100 is not set
492CONFIG_NET_PCI=y
493# CONFIG_PCNET32 is not set
494# CONFIG_AMD8111_ETH is not set
495# CONFIG_ADAPTEC_STARFIRE is not set
496# CONFIG_B44 is not set
497# CONFIG_FORCEDETH is not set
498# CONFIG_DGRS is not set
499CONFIG_EEPRO100=y
500# CONFIG_E100 is not set
501# CONFIG_FEALNX is not set
502# CONFIG_NATSEMI is not set
503# CONFIG_NE2K_PCI is not set
504# CONFIG_8139CP is not set
505# CONFIG_8139TOO is not set
506# CONFIG_SIS900 is not set
507# CONFIG_EPIC100 is not set
508# CONFIG_SUNDANCE is not set
509# CONFIG_TLAN is not set
510# CONFIG_VIA_RHINE is not set
511# CONFIG_LAN_SAA9730 is not set
372 512
373# 513#
374# Ethernet (1000 Mbit) 514# Ethernet (1000 Mbit)
375# 515#
516# CONFIG_ACENIC is not set
517# CONFIG_DL2K is not set
518# CONFIG_E1000 is not set
519# CONFIG_NS83820 is not set
520# CONFIG_HAMACHI is not set
521# CONFIG_YELLOWFIN is not set
522# CONFIG_R8169 is not set
523# CONFIG_SIS190 is not set
524# CONFIG_SKGE is not set
525# CONFIG_SK98LIN is not set
526# CONFIG_VIA_VELOCITY is not set
527# CONFIG_TIGON3 is not set
528# CONFIG_BNX2 is not set
376 529
377# 530#
378# Ethernet (10000 Mbit) 531# Ethernet (10000 Mbit)
379# 532#
533# CONFIG_CHELSIO_T1 is not set
534# CONFIG_IXGB is not set
535# CONFIG_S2IO is not set
380 536
381# 537#
382# Token Ring devices 538# Token Ring devices
383# 539#
540# CONFIG_TR is not set
384 541
385# 542#
386# Wireless LAN (non-hamradio) 543# Wireless LAN (non-hamradio)
387# 544#
388# CONFIG_NET_RADIO is not set 545# CONFIG_NET_RADIO is not set
546# CONFIG_IPW2200 is not set
389 547
390# 548#
391# Wan interfaces 549# Wan interfaces
392# 550#
393# CONFIG_WAN is not set 551# CONFIG_WAN is not set
394CONFIG_PPP=m 552# CONFIG_FDDI is not set
395CONFIG_PPP_MULTILINK=y 553# CONFIG_HIPPI is not set
396# CONFIG_PPP_FILTER is not set 554# CONFIG_PPP is not set
397CONFIG_PPP_ASYNC=m
398CONFIG_PPP_SYNC_TTY=m
399CONFIG_PPP_DEFLATE=m
400CONFIG_PPP_BSDCOMP=m
401CONFIG_PPPOE=m
402# CONFIG_SLIP is not set 555# CONFIG_SLIP is not set
556# CONFIG_NET_FC is not set
403# CONFIG_SHAPER is not set 557# CONFIG_SHAPER is not set
404# CONFIG_NETCONSOLE is not set 558# CONFIG_NETCONSOLE is not set
559# CONFIG_NETPOLL is not set
560# CONFIG_NET_POLL_CONTROLLER is not set
405 561
406# 562#
407# ISDN subsystem 563# ISDN subsystem
@@ -421,28 +577,13 @@ CONFIG_INPUT=y
421# 577#
422# Userland interfaces 578# Userland interfaces
423# 579#
424CONFIG_INPUT_MOUSEDEV=y 580# CONFIG_INPUT_MOUSEDEV is not set
425CONFIG_INPUT_MOUSEDEV_PSAUX=y
426CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
427CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
428# CONFIG_INPUT_JOYDEV is not set 581# CONFIG_INPUT_JOYDEV is not set
429# CONFIG_INPUT_TSDEV is not set 582# CONFIG_INPUT_TSDEV is not set
430# CONFIG_INPUT_EVDEV is not set 583# CONFIG_INPUT_EVDEV is not set
431# CONFIG_INPUT_EVBUG is not set 584# CONFIG_INPUT_EVBUG is not set
432 585
433# 586#
434# Input I/O drivers
435#
436# CONFIG_GAMEPORT is not set
437CONFIG_SOUND_GAMEPORT=y
438CONFIG_SERIO=y
439CONFIG_SERIO_I8042=y
440CONFIG_SERIO_SERPORT=y
441# CONFIG_SERIO_CT82C710 is not set
442# CONFIG_SERIO_LIBPS2 is not set
443CONFIG_SERIO_RAW=m
444
445#
446# Input Device Drivers 587# Input Device Drivers
447# 588#
448# CONFIG_INPUT_KEYBOARD is not set 589# CONFIG_INPUT_KEYBOARD is not set
@@ -452,6 +593,12 @@ CONFIG_SERIO_RAW=m
452# CONFIG_INPUT_MISC is not set 593# CONFIG_INPUT_MISC is not set
453 594
454# 595#
596# Hardware I/O ports
597#
598# CONFIG_SERIO is not set
599# CONFIG_GAMEPORT is not set
600
601#
455# Character devices 602# Character devices
456# 603#
457CONFIG_VT=y 604CONFIG_VT=y
@@ -462,16 +609,16 @@ CONFIG_HW_CONSOLE=y
462# 609#
463# Serial drivers 610# Serial drivers
464# 611#
465CONFIG_SERIAL_8250=y 612# CONFIG_SERIAL_8250 is not set
466CONFIG_SERIAL_8250_CONSOLE=y
467CONFIG_SERIAL_8250_NR_UARTS=4
468# CONFIG_SERIAL_8250_EXTENDED is not set
469 613
470# 614#
471# Non-8250 serial port support 615# Non-8250 serial port support
472# 616#
473CONFIG_SERIAL_CORE=y 617CONFIG_SERIAL_CORE=y
474CONFIG_SERIAL_CORE_CONSOLE=y 618CONFIG_SERIAL_CORE_CONSOLE=y
619CONFIG_SERIAL_VR41XX=y
620CONFIG_SERIAL_VR41XX_CONSOLE=y
621# CONFIG_SERIAL_JSM is not set
475CONFIG_UNIX98_PTYS=y 622CONFIG_UNIX98_PTYS=y
476CONFIG_LEGACY_PTYS=y 623CONFIG_LEGACY_PTYS=y
477CONFIG_LEGACY_PTY_COUNT=256 624CONFIG_LEGACY_PTY_COUNT=256
@@ -489,14 +636,22 @@ CONFIG_LEGACY_PTY_COUNT=256
489# CONFIG_GEN_RTC is not set 636# CONFIG_GEN_RTC is not set
490# CONFIG_DTLK is not set 637# CONFIG_DTLK is not set
491# CONFIG_R3964 is not set 638# CONFIG_R3964 is not set
639# CONFIG_APPLICOM is not set
640# CONFIG_TANBAC_TB0219 is not set
492 641
493# 642#
494# Ftape, the floppy tape device driver 643# Ftape, the floppy tape device driver
495# 644#
496# CONFIG_DRM is not set 645# CONFIG_DRM is not set
646CONFIG_GPIO_VR41XX=y
497# CONFIG_RAW_DRIVER is not set 647# CONFIG_RAW_DRIVER is not set
498 648
499# 649#
650# TPM devices
651#
652# CONFIG_TCG_TPM is not set
653
654#
500# I2C support 655# I2C support
501# 656#
502# CONFIG_I2C is not set 657# CONFIG_I2C is not set
@@ -507,10 +662,20 @@ CONFIG_LEGACY_PTY_COUNT=256
507# CONFIG_W1 is not set 662# CONFIG_W1 is not set
508 663
509# 664#
665# Hardware Monitoring support
666#
667# CONFIG_HWMON is not set
668# CONFIG_HWMON_VID is not set
669
670#
510# Misc devices 671# Misc devices
511# 672#
512 673
513# 674#
675# Multimedia Capabilities Port drivers
676#
677
678#
514# Multimedia devices 679# Multimedia devices
515# 680#
516# CONFIG_VIDEO_DEV is not set 681# CONFIG_VIDEO_DEV is not set
@@ -523,48 +688,147 @@ CONFIG_LEGACY_PTY_COUNT=256
523# 688#
524# Graphics support 689# Graphics support
525# 690#
526CONFIG_FB=y 691# CONFIG_FB is not set
527# CONFIG_FB_MODE_HELPERS is not set
528# CONFIG_FB_TILEBLITTING is not set
529# CONFIG_FB_VIRTUAL is not set
530 692
531# 693#
532# Console display driver support 694# Console display driver support
533# 695#
534# CONFIG_VGA_CONSOLE is not set 696# CONFIG_VGA_CONSOLE is not set
535CONFIG_DUMMY_CONSOLE=y 697CONFIG_DUMMY_CONSOLE=y
536# CONFIG_FRAMEBUFFER_CONSOLE is not set
537 698
538# 699#
539# Logo configuration 700# Sound
540# 701#
541# CONFIG_LOGO is not set 702# CONFIG_SOUND is not set
542# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
543 703
544# 704#
545# Sound 705# USB support
546# 706#
547CONFIG_SOUND=y 707CONFIG_USB_ARCH_HAS_HCD=y
708CONFIG_USB_ARCH_HAS_OHCI=y
709CONFIG_USB=y
710# CONFIG_USB_DEBUG is not set
548 711
549# 712#
550# Advanced Linux Sound Architecture 713# Miscellaneous USB options
551# 714#
552# CONFIG_SND is not set 715CONFIG_USB_DEVICEFS=y
716# CONFIG_USB_BANDWIDTH is not set
717# CONFIG_USB_DYNAMIC_MINORS is not set
718# CONFIG_USB_OTG is not set
553 719
554# 720#
555# Open Sound System 721# USB Host Controller Drivers
556# 722#
557# CONFIG_SOUND_PRIME is not set 723CONFIG_USB_EHCI_HCD=y
724# CONFIG_USB_EHCI_SPLIT_ISO is not set
725# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
726# CONFIG_USB_ISP116X_HCD is not set
727CONFIG_USB_OHCI_HCD=y
728# CONFIG_USB_OHCI_BIG_ENDIAN is not set
729CONFIG_USB_OHCI_LITTLE_ENDIAN=y
730# CONFIG_USB_UHCI_HCD is not set
731# CONFIG_USB_SL811_HCD is not set
558 732
559# 733#
560# USB support 734# USB Device Class drivers
561# 735#
562# CONFIG_USB_ARCH_HAS_HCD is not set 736# CONFIG_USB_BLUETOOTH_TTY is not set
563# CONFIG_USB_ARCH_HAS_OHCI is not set 737# CONFIG_USB_ACM is not set
738# CONFIG_USB_PRINTER is not set
564 739
565# 740#
566# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information 741# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
567# 742#
743CONFIG_USB_STORAGE=m
744# CONFIG_USB_STORAGE_DEBUG is not set
745# CONFIG_USB_STORAGE_DATAFAB is not set
746# CONFIG_USB_STORAGE_FREECOM is not set
747# CONFIG_USB_STORAGE_DPCM is not set
748# CONFIG_USB_STORAGE_USBAT is not set
749# CONFIG_USB_STORAGE_SDDR09 is not set
750# CONFIG_USB_STORAGE_SDDR55 is not set
751# CONFIG_USB_STORAGE_JUMPSHOT is not set
752
753#
754# USB Input Devices
755#
756# CONFIG_USB_HID is not set
757
758#
759# USB HID Boot Protocol drivers
760#
761# CONFIG_USB_KBD is not set
762# CONFIG_USB_MOUSE is not set
763# CONFIG_USB_AIPTEK is not set
764# CONFIG_USB_WACOM is not set
765# CONFIG_USB_ACECAD is not set
766# CONFIG_USB_KBTAB is not set
767# CONFIG_USB_POWERMATE is not set
768# CONFIG_USB_MTOUCH is not set
769# CONFIG_USB_ITMTOUCH is not set
770# CONFIG_USB_EGALAX is not set
771# CONFIG_USB_YEALINK is not set
772# CONFIG_USB_XPAD is not set
773# CONFIG_USB_ATI_REMOTE is not set
774# CONFIG_USB_KEYSPAN_REMOTE is not set
775# CONFIG_USB_APPLETOUCH is not set
776
777#
778# USB Imaging devices
779#
780# CONFIG_USB_MDC800 is not set
781# CONFIG_USB_MICROTEK is not set
782
783#
784# USB Multimedia devices
785#
786# CONFIG_USB_DABUSB is not set
787
788#
789# Video4Linux support is needed for USB Multimedia device support
790#
791
792#
793# USB Network Adapters
794#
795# CONFIG_USB_CATC is not set
796# CONFIG_USB_KAWETH is not set
797# CONFIG_USB_PEGASUS is not set
798# CONFIG_USB_RTL8150 is not set
799# CONFIG_USB_USBNET is not set
800CONFIG_USB_MON=y
801
802#
803# USB port drivers
804#
805
806#
807# USB Serial Converter support
808#
809# CONFIG_USB_SERIAL is not set
810
811#
812# USB Miscellaneous drivers
813#
814# CONFIG_USB_EMI62 is not set
815# CONFIG_USB_EMI26 is not set
816# CONFIG_USB_AUERSWALD is not set
817# CONFIG_USB_RIO500 is not set
818# CONFIG_USB_LEGOTOWER is not set
819# CONFIG_USB_LCD is not set
820# CONFIG_USB_LED is not set
821# CONFIG_USB_CYTHERM is not set
822# CONFIG_USB_PHIDGETKIT is not set
823# CONFIG_USB_PHIDGETSERVO is not set
824# CONFIG_USB_IDMOUSE is not set
825# CONFIG_USB_SISUSBVGA is not set
826# CONFIG_USB_LD is not set
827# CONFIG_USB_TEST is not set
828
829#
830# USB DSL modem support
831#
568 832
569# 833#
570# USB Gadget Support 834# USB Gadget Support
@@ -582,39 +846,41 @@ CONFIG_SOUND=y
582# CONFIG_INFINIBAND is not set 846# CONFIG_INFINIBAND is not set
583 847
584# 848#
849# SN Devices
850#
851
852#
585# File systems 853# File systems
586# 854#
587CONFIG_EXT2_FS=y 855CONFIG_EXT2_FS=y
588# CONFIG_EXT2_FS_XATTR is not set 856# CONFIG_EXT2_FS_XATTR is not set
857# CONFIG_EXT2_FS_XIP is not set
589# CONFIG_EXT3_FS is not set 858# CONFIG_EXT3_FS is not set
590# CONFIG_JBD is not set 859# CONFIG_JBD is not set
591# CONFIG_REISERFS_FS is not set 860# CONFIG_REISERFS_FS is not set
592# CONFIG_JFS_FS is not set 861# CONFIG_JFS_FS is not set
862# CONFIG_FS_POSIX_ACL is not set
593# CONFIG_XFS_FS is not set 863# CONFIG_XFS_FS is not set
594# CONFIG_MINIX_FS is not set 864# CONFIG_MINIX_FS is not set
595CONFIG_ROMFS_FS=m 865CONFIG_ROMFS_FS=m
866CONFIG_INOTIFY=y
596# CONFIG_QUOTA is not set 867# CONFIG_QUOTA is not set
597CONFIG_DNOTIFY=y 868CONFIG_DNOTIFY=y
598# CONFIG_AUTOFS_FS is not set 869# CONFIG_AUTOFS_FS is not set
599CONFIG_AUTOFS4_FS=y 870CONFIG_AUTOFS4_FS=y
871CONFIG_FUSE_FS=m
600 872
601# 873#
602# CD-ROM/DVD Filesystems 874# CD-ROM/DVD Filesystems
603# 875#
604CONFIG_ISO9660_FS=y 876# CONFIG_ISO9660_FS is not set
605CONFIG_JOLIET=y
606CONFIG_ZISOFS=y
607CONFIG_ZISOFS_FS=y
608# CONFIG_UDF_FS is not set 877# CONFIG_UDF_FS is not set
609 878
610# 879#
611# DOS/FAT/NT Filesystems 880# DOS/FAT/NT Filesystems
612# 881#
613CONFIG_FAT_FS=m 882# CONFIG_MSDOS_FS is not set
614CONFIG_MSDOS_FS=m 883# CONFIG_VFAT_FS is not set
615CONFIG_VFAT_FS=m
616CONFIG_FAT_DEFAULT_CODEPAGE=437
617CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
618# CONFIG_NTFS_FS is not set 884# CONFIG_NTFS_FS is not set
619 885
620# 886#
@@ -623,13 +889,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
623CONFIG_PROC_FS=y 889CONFIG_PROC_FS=y
624CONFIG_PROC_KCORE=y 890CONFIG_PROC_KCORE=y
625CONFIG_SYSFS=y 891CONFIG_SYSFS=y
626# CONFIG_DEVFS_FS is not set
627CONFIG_DEVPTS_FS_XATTR=y
628CONFIG_DEVPTS_FS_SECURITY=y
629CONFIG_TMPFS=y 892CONFIG_TMPFS=y
630# CONFIG_TMPFS_XATTR is not set
631# CONFIG_HUGETLB_PAGE is not set 893# CONFIG_HUGETLB_PAGE is not set
632CONFIG_RAMFS=y 894CONFIG_RAMFS=y
895CONFIG_RELAYFS_FS=m
633 896
634# 897#
635# Miscellaneous filesystems 898# Miscellaneous filesystems
@@ -653,16 +916,19 @@ CONFIG_CRAMFS=m
653# 916#
654CONFIG_NFS_FS=y 917CONFIG_NFS_FS=y
655CONFIG_NFS_V3=y 918CONFIG_NFS_V3=y
919# CONFIG_NFS_V3_ACL is not set
656# CONFIG_NFS_V4 is not set 920# CONFIG_NFS_V4 is not set
657# CONFIG_NFS_DIRECTIO is not set 921# CONFIG_NFS_DIRECTIO is not set
658CONFIG_NFSD=m 922CONFIG_NFSD=m
659CONFIG_NFSD_V3=y 923CONFIG_NFSD_V3=y
924# CONFIG_NFSD_V3_ACL is not set
660# CONFIG_NFSD_V4 is not set 925# CONFIG_NFSD_V4 is not set
661# CONFIG_NFSD_TCP is not set 926# CONFIG_NFSD_TCP is not set
662CONFIG_ROOT_NFS=y 927CONFIG_ROOT_NFS=y
663CONFIG_LOCKD=y 928CONFIG_LOCKD=y
664CONFIG_LOCKD_V4=y 929CONFIG_LOCKD_V4=y
665CONFIG_EXPORTFS=m 930CONFIG_EXPORTFS=m
931CONFIG_NFS_COMMON=y
666CONFIG_SUNRPC=y 932CONFIG_SUNRPC=y
667# CONFIG_RPCSEC_GSS_KRB5 is not set 933# CONFIG_RPCSEC_GSS_KRB5 is not set
668# CONFIG_RPCSEC_GSS_SPKM3 is not set 934# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -673,6 +939,7 @@ CONFIG_SMB_NLS_REMOTE="cp932"
673# CONFIG_NCP_FS is not set 939# CONFIG_NCP_FS is not set
674# CONFIG_CODA_FS is not set 940# CONFIG_CODA_FS is not set
675# CONFIG_AFS_FS is not set 941# CONFIG_AFS_FS is not set
942# CONFIG_9P_FS is not set
676 943
677# 944#
678# Partition Types 945# Partition Types
@@ -732,9 +999,11 @@ CONFIG_NLS_ISO8859_1=m
732# 999#
733# Kernel hacking 1000# Kernel hacking
734# 1001#
1002# CONFIG_PRINTK_TIME is not set
735# CONFIG_DEBUG_KERNEL is not set 1003# CONFIG_DEBUG_KERNEL is not set
1004CONFIG_LOG_BUF_SHIFT=14
736CONFIG_CROSSCOMPILE=y 1005CONFIG_CROSSCOMPILE=y
737CONFIG_CMDLINE="" 1006CONFIG_CMDLINE="mem=32M console=ttyVR0,115200"
738 1007
739# 1008#
740# Security options 1009# Security options
@@ -746,7 +1015,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
746# 1015#
747# Cryptographic options 1016# Cryptographic options
748# 1017#
749# CONFIG_CRYPTO is not set 1018CONFIG_CRYPTO=y
1019CONFIG_CRYPTO_HMAC=y
1020CONFIG_CRYPTO_NULL=m
1021CONFIG_CRYPTO_MD4=m
1022CONFIG_CRYPTO_MD5=m
1023CONFIG_CRYPTO_SHA1=m
1024CONFIG_CRYPTO_SHA256=m
1025CONFIG_CRYPTO_SHA512=m
1026CONFIG_CRYPTO_WP512=m
1027CONFIG_CRYPTO_TGR192=m
1028CONFIG_CRYPTO_DES=m
1029CONFIG_CRYPTO_BLOWFISH=m
1030CONFIG_CRYPTO_TWOFISH=m
1031CONFIG_CRYPTO_SERPENT=m
1032CONFIG_CRYPTO_AES=m
1033CONFIG_CRYPTO_CAST5=m
1034CONFIG_CRYPTO_CAST6=m
1035CONFIG_CRYPTO_TEA=m
1036CONFIG_CRYPTO_ARC4=m
1037CONFIG_CRYPTO_KHAZAD=m
1038CONFIG_CRYPTO_ANUBIS=m
1039CONFIG_CRYPTO_DEFLATE=m
1040CONFIG_CRYPTO_MICHAEL_MIC=m
1041CONFIG_CRYPTO_CRC32C=m
1042# CONFIG_CRYPTO_TEST is not set
750 1043
751# 1044#
752# Hardware crypto devices 1045# Hardware crypto devices
@@ -756,9 +1049,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
756# Library routines 1049# Library routines
757# 1050#
758CONFIG_CRC_CCITT=m 1051CONFIG_CRC_CCITT=m
759# CONFIG_CRC32 is not set 1052CONFIG_CRC16=m
760# CONFIG_LIBCRC32C is not set 1053CONFIG_CRC32=m
761CONFIG_ZLIB_INFLATE=y 1054CONFIG_LIBCRC32C=m
1055CONFIG_ZLIB_INFLATE=m
762CONFIG_ZLIB_DEFLATE=m 1056CONFIG_ZLIB_DEFLATE=m
763CONFIG_GENERIC_HARDIRQS=y
764CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig
index 2cb669188aa9..ac8b64e87b8a 100644
--- a/arch/mips/configs/tb0229_defconfig
+++ b/arch/mips/configs/tb0229_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:12 2005 4# Thu Oct 20 22:27:13 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,58 +59,87 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60CONFIG_MACH_VR41XX=y 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_NEC_CMBVR4133 is not set 64# CONFIG_MIPS_PB1000 is not set
62# CONFIG_CASIO_E55 is not set 65# CONFIG_MIPS_PB1100 is not set
63# CONFIG_IBM_WORKPAD is not set 66# CONFIG_MIPS_PB1500 is not set
64# CONFIG_TANBAC_TB0226 is not set 67# CONFIG_MIPS_PB1550 is not set
65CONFIG_TANBAC_TB0229=y 68# CONFIG_MIPS_PB1200 is not set
66CONFIG_TANBAC_TB0219=y 69# CONFIG_MIPS_DB1000 is not set
67# CONFIG_VICTOR_MPC30X is not set 70# CONFIG_MIPS_DB1100 is not set
68# CONFIG_ZAO_CAPCELLA is not set 71# CONFIG_MIPS_DB1500 is not set
69CONFIG_PCI_VR41XX=y 72# CONFIG_MIPS_DB1550 is not set
70# CONFIG_VRC4173 is not set 73# CONFIG_MIPS_DB1200 is not set
71# CONFIG_TOSHIBA_JMR3927 is not set 74# CONFIG_MIPS_MIRAGE is not set
72# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
73# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
74# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
75# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
76# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
77# CONFIG_LASAT is not set
78# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
79# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
80# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
81# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
82# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
83# CONFIG_MOMENCO_OCELOT_G is not set
84# CONFIG_MOMENCO_OCELOT_C is not set
85# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
86# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
87# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
88# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
89# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
90# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
91# CONFIG_NEC_OSPREY is not set 98CONFIG_MACH_VR41XX=y
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
92# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
93# CONFIG_SOC_AU1X00 is not set 102# CONFIG_SGI_IP27 is not set
94# CONFIG_SIBYTE_SB1xxx_SOC is not set 103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
95# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
96# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
117# CONFIG_NEC_CMBVR4133 is not set
118# CONFIG_CASIO_E55 is not set
119# CONFIG_IBM_WORKPAD is not set
120CONFIG_TANBAC_TB022X=y
121# CONFIG_TANBAC_TB0226 is not set
122# CONFIG_VICTOR_MPC30X is not set
123# CONFIG_ZAO_CAPCELLA is not set
124CONFIG_PCI_VR41XX=y
125# CONFIG_VRC4173 is not set
97CONFIG_RWSEM_GENERIC_SPINLOCK=y 126CONFIG_RWSEM_GENERIC_SPINLOCK=y
98CONFIG_GENERIC_CALIBRATE_DELAY=y 127CONFIG_GENERIC_CALIBRATE_DELAY=y
99CONFIG_HAVE_DEC_LOCK=y
100CONFIG_DMA_NONCOHERENT=y 128CONFIG_DMA_NONCOHERENT=y
101CONFIG_DMA_NEED_PCI_MAP_STATE=y 129CONFIG_DMA_NEED_PCI_MAP_STATE=y
130# CONFIG_CPU_BIG_ENDIAN is not set
102CONFIG_CPU_LITTLE_ENDIAN=y 131CONFIG_CPU_LITTLE_ENDIAN=y
132CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
103CONFIG_IRQ_CPU=y 133CONFIG_IRQ_CPU=y
104CONFIG_MIPS_L1_CACHE_SHIFT=5 134CONFIG_MIPS_L1_CACHE_SHIFT=5
105 135
106# 136#
107# CPU selection 137# CPU selection
108# 138#
109# CONFIG_CPU_MIPS32 is not set 139# CONFIG_CPU_MIPS32_R1 is not set
110# CONFIG_CPU_MIPS64 is not set 140# CONFIG_CPU_MIPS32_R2 is not set
141# CONFIG_CPU_MIPS64_R1 is not set
142# CONFIG_CPU_MIPS64_R2 is not set
111# CONFIG_CPU_R3000 is not set 143# CONFIG_CPU_R3000 is not set
112# CONFIG_CPU_TX39XX is not set 144# CONFIG_CPU_TX39XX is not set
113CONFIG_CPU_VR41XX=y 145CONFIG_CPU_VR41XX=y
@@ -123,12 +155,36 @@ CONFIG_CPU_VR41XX=y
123# CONFIG_CPU_RM7000 is not set 155# CONFIG_CPU_RM7000 is not set
124# CONFIG_CPU_RM9000 is not set 156# CONFIG_CPU_RM9000 is not set
125# CONFIG_CPU_SB1 is not set 157# CONFIG_CPU_SB1 is not set
158CONFIG_SYS_HAS_CPU_VR41XX=y
159CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
160CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
161CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
162CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
163
164#
165# Kernel type
166#
167CONFIG_32BIT=y
168# CONFIG_64BIT is not set
126CONFIG_PAGE_SIZE_4KB=y 169CONFIG_PAGE_SIZE_4KB=y
127# CONFIG_PAGE_SIZE_8KB is not set 170# CONFIG_PAGE_SIZE_8KB is not set
128# CONFIG_PAGE_SIZE_16KB is not set 171# CONFIG_PAGE_SIZE_16KB is not set
129# CONFIG_PAGE_SIZE_64KB is not set 172# CONFIG_PAGE_SIZE_64KB is not set
173# CONFIG_MIPS_MT is not set
130# CONFIG_CPU_ADVANCED is not set 174# CONFIG_CPU_ADVANCED is not set
131CONFIG_CPU_HAS_SYNC=y 175CONFIG_CPU_HAS_SYNC=y
176CONFIG_GENERIC_HARDIRQS=y
177CONFIG_GENERIC_IRQ_PROBE=y
178CONFIG_ARCH_FLATMEM_ENABLE=y
179CONFIG_SELECT_MEMORY_MODEL=y
180CONFIG_FLATMEM_MANUAL=y
181# CONFIG_DISCONTIGMEM_MANUAL is not set
182# CONFIG_SPARSEMEM_MANUAL is not set
183CONFIG_FLATMEM=y
184CONFIG_FLAT_NODE_MEM_MAP=y
185# CONFIG_SPARSEMEM_STATIC is not set
186CONFIG_PREEMPT_NONE=y
187# CONFIG_PREEMPT_VOLUNTARY is not set
132# CONFIG_PREEMPT is not set 188# CONFIG_PREEMPT is not set
133 189
134# 190#
@@ -136,8 +192,7 @@ CONFIG_CPU_HAS_SYNC=y
136# 192#
137CONFIG_HW_HAS_PCI=y 193CONFIG_HW_HAS_PCI=y
138CONFIG_PCI=y 194CONFIG_PCI=y
139CONFIG_PCI_LEGACY_PROC=y 195# CONFIG_PCI_LEGACY_PROC is not set
140CONFIG_PCI_NAMES=y
141CONFIG_MMU=y 196CONFIG_MMU=y
142 197
143# 198#
@@ -146,10 +201,6 @@ CONFIG_MMU=y
146# CONFIG_PCCARD is not set 201# CONFIG_PCCARD is not set
147 202
148# 203#
149# PC-card bridges
150#
151
152#
153# PCI Hotplug Support 204# PCI Hotplug Support
154# 205#
155# CONFIG_HOTPLUG_PCI is not set 206# CONFIG_HOTPLUG_PCI is not set
@@ -162,6 +213,88 @@ CONFIG_BINFMT_ELF=y
162CONFIG_TRAD_SIGNALS=y 213CONFIG_TRAD_SIGNALS=y
163 214
164# 215#
216# Networking
217#
218CONFIG_NET=y
219
220#
221# Networking options
222#
223CONFIG_PACKET=y
224# CONFIG_PACKET_MMAP is not set
225CONFIG_UNIX=y
226CONFIG_XFRM=y
227CONFIG_XFRM_USER=m
228# CONFIG_NET_KEY is not set
229CONFIG_INET=y
230CONFIG_IP_MULTICAST=y
231CONFIG_IP_ADVANCED_ROUTER=y
232CONFIG_ASK_IP_FIB_HASH=y
233# CONFIG_IP_FIB_TRIE is not set
234CONFIG_IP_FIB_HASH=y
235CONFIG_IP_MULTIPLE_TABLES=y
236CONFIG_IP_ROUTE_MULTIPATH=y
237# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
238CONFIG_IP_ROUTE_VERBOSE=y
239CONFIG_IP_PNP=y
240# CONFIG_IP_PNP_DHCP is not set
241CONFIG_IP_PNP_BOOTP=y
242# CONFIG_IP_PNP_RARP is not set
243CONFIG_NET_IPIP=m
244CONFIG_NET_IPGRE=m
245# CONFIG_NET_IPGRE_BROADCAST is not set
246# CONFIG_IP_MROUTE is not set
247# CONFIG_ARPD is not set
248CONFIG_SYN_COOKIES=y
249# CONFIG_INET_AH is not set
250# CONFIG_INET_ESP is not set
251# CONFIG_INET_IPCOMP is not set
252CONFIG_INET_TUNNEL=m
253CONFIG_INET_DIAG=y
254CONFIG_INET_TCP_DIAG=y
255# CONFIG_TCP_CONG_ADVANCED is not set
256CONFIG_TCP_CONG_BIC=y
257# CONFIG_IPV6 is not set
258# CONFIG_NETFILTER is not set
259
260#
261# DCCP Configuration (EXPERIMENTAL)
262#
263# CONFIG_IP_DCCP is not set
264
265#
266# SCTP Configuration (EXPERIMENTAL)
267#
268# CONFIG_IP_SCTP is not set
269# CONFIG_ATM is not set
270# CONFIG_BRIDGE is not set
271# CONFIG_VLAN_8021Q is not set
272# CONFIG_DECNET is not set
273# CONFIG_LLC2 is not set
274# CONFIG_IPX is not set
275# CONFIG_ATALK is not set
276# CONFIG_X25 is not set
277# CONFIG_LAPB is not set
278# CONFIG_NET_DIVERT is not set
279# CONFIG_ECONET is not set
280# CONFIG_WAN_ROUTER is not set
281# CONFIG_NET_SCHED is not set
282# CONFIG_NET_CLS_ROUTE is not set
283
284#
285# Network testing
286#
287# CONFIG_NET_PKTGEN is not set
288# CONFIG_HAMRADIO is not set
289# CONFIG_IRDA is not set
290# CONFIG_BT is not set
291CONFIG_IEEE80211=m
292# CONFIG_IEEE80211_DEBUG is not set
293CONFIG_IEEE80211_CRYPT_WEP=m
294CONFIG_IEEE80211_CRYPT_CCMP=m
295CONFIG_IEEE80211_CRYPT_TKIP=m
296
297#
165# Device Drivers 298# Device Drivers
166# 299#
167 300
@@ -170,7 +303,12 @@ CONFIG_TRAD_SIGNALS=y
170# 303#
171CONFIG_STANDALONE=y 304CONFIG_STANDALONE=y
172CONFIG_PREVENT_FIRMWARE_BUILD=y 305CONFIG_PREVENT_FIRMWARE_BUILD=y
173# CONFIG_FW_LOADER is not set 306CONFIG_FW_LOADER=m
307
308#
309# Connector - unified userspace <-> kernelspace linker
310#
311CONFIG_CONNECTOR=m
174 312
175# 313#
176# Memory Technology Devices (MTD) 314# Memory Technology Devices (MTD)
@@ -189,7 +327,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
189# 327#
190# Block devices 328# Block devices
191# 329#
192# CONFIG_BLK_DEV_FD is not set
193# CONFIG_BLK_CPQ_DA is not set 330# CONFIG_BLK_CPQ_DA is not set
194# CONFIG_BLK_CPQ_CISS_DA is not set 331# CONFIG_BLK_CPQ_CISS_DA is not set
195# CONFIG_BLK_DEV_DAC960 is not set 332# CONFIG_BLK_DEV_DAC960 is not set
@@ -199,11 +336,11 @@ CONFIG_BLK_DEV_LOOP=m
199# CONFIG_BLK_DEV_CRYPTOLOOP is not set 336# CONFIG_BLK_DEV_CRYPTOLOOP is not set
200CONFIG_BLK_DEV_NBD=m 337CONFIG_BLK_DEV_NBD=m
201# CONFIG_BLK_DEV_SX8 is not set 338# CONFIG_BLK_DEV_SX8 is not set
339# CONFIG_BLK_DEV_UB is not set
202CONFIG_BLK_DEV_RAM=y 340CONFIG_BLK_DEV_RAM=y
203CONFIG_BLK_DEV_RAM_COUNT=16 341CONFIG_BLK_DEV_RAM_COUNT=16
204CONFIG_BLK_DEV_RAM_SIZE=4096 342CONFIG_BLK_DEV_RAM_SIZE=4096
205# CONFIG_BLK_DEV_INITRD is not set 343# CONFIG_BLK_DEV_INITRD is not set
206CONFIG_INITRAMFS_SOURCE=""
207# CONFIG_LBD is not set 344# CONFIG_LBD is not set
208CONFIG_CDROM_PKTCDVD=m 345CONFIG_CDROM_PKTCDVD=m
209CONFIG_CDROM_PKTCDVD_BUFFERS=8 346CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -226,6 +363,7 @@ CONFIG_ATA_OVER_ETH=m
226# 363#
227# SCSI device support 364# SCSI device support
228# 365#
366# CONFIG_RAID_ATTRS is not set
229# CONFIG_SCSI is not set 367# CONFIG_SCSI is not set
230 368
231# 369#
@@ -236,6 +374,7 @@ CONFIG_ATA_OVER_ETH=m
236# 374#
237# Fusion MPT device support 375# Fusion MPT device support
238# 376#
377# CONFIG_FUSION is not set
239 378
240# 379#
241# IEEE 1394 (FireWire) support 380# IEEE 1394 (FireWire) support
@@ -248,83 +387,13 @@ CONFIG_ATA_OVER_ETH=m
248# CONFIG_I2O is not set 387# CONFIG_I2O is not set
249 388
250# 389#
251# Networking support 390# Network device support
252#
253CONFIG_NET=y
254
255#
256# Networking options
257#
258CONFIG_PACKET=y
259# CONFIG_PACKET_MMAP is not set
260CONFIG_NETLINK_DEV=m
261CONFIG_UNIX=y
262# CONFIG_NET_KEY is not set
263CONFIG_INET=y
264CONFIG_IP_MULTICAST=y
265CONFIG_IP_ADVANCED_ROUTER=y
266CONFIG_IP_MULTIPLE_TABLES=y
267CONFIG_IP_ROUTE_MULTIPATH=y
268CONFIG_IP_ROUTE_VERBOSE=y
269CONFIG_IP_PNP=y
270# CONFIG_IP_PNP_DHCP is not set
271CONFIG_IP_PNP_BOOTP=y
272# CONFIG_IP_PNP_RARP is not set
273CONFIG_NET_IPIP=m
274CONFIG_NET_IPGRE=m
275# CONFIG_NET_IPGRE_BROADCAST is not set
276# CONFIG_IP_MROUTE is not set
277# CONFIG_ARPD is not set
278CONFIG_SYN_COOKIES=y
279# CONFIG_INET_AH is not set
280# CONFIG_INET_ESP is not set
281# CONFIG_INET_IPCOMP is not set
282CONFIG_INET_TUNNEL=m
283CONFIG_IP_TCPDIAG=m
284# CONFIG_IP_TCPDIAG_IPV6 is not set
285# CONFIG_IPV6 is not set
286# CONFIG_NETFILTER is not set
287CONFIG_XFRM=y
288CONFIG_XFRM_USER=m
289
290#
291# SCTP Configuration (EXPERIMENTAL)
292#
293# CONFIG_IP_SCTP is not set
294# CONFIG_ATM is not set
295# CONFIG_BRIDGE is not set
296# CONFIG_VLAN_8021Q is not set
297# CONFIG_DECNET is not set
298# CONFIG_LLC2 is not set
299# CONFIG_IPX is not set
300# CONFIG_ATALK is not set
301# CONFIG_X25 is not set
302# CONFIG_LAPB is not set
303# CONFIG_NET_DIVERT is not set
304# CONFIG_ECONET is not set
305# CONFIG_WAN_ROUTER is not set
306
307#
308# QoS and/or fair queueing
309#
310# CONFIG_NET_SCHED is not set
311# CONFIG_NET_CLS_ROUTE is not set
312
313#
314# Network testing
315# 391#
316# CONFIG_NET_PKTGEN is not set
317# CONFIG_NETPOLL is not set
318# CONFIG_NET_POLL_CONTROLLER is not set
319# CONFIG_HAMRADIO is not set
320# CONFIG_IRDA is not set
321# CONFIG_BT is not set
322CONFIG_NETDEVICES=y 392CONFIG_NETDEVICES=y
323CONFIG_DUMMY=m 393CONFIG_DUMMY=m
324# CONFIG_BONDING is not set 394# CONFIG_BONDING is not set
325# CONFIG_EQUALIZER is not set 395# CONFIG_EQUALIZER is not set
326# CONFIG_TUN is not set 396# CONFIG_TUN is not set
327# CONFIG_ETHERTAP is not set
328 397
329# 398#
330# ARCnet devices 399# ARCnet devices
@@ -332,6 +401,21 @@ CONFIG_DUMMY=m
332# CONFIG_ARCNET is not set 401# CONFIG_ARCNET is not set
333 402
334# 403#
404# PHY device support
405#
406CONFIG_PHYLIB=m
407CONFIG_PHYCONTROL=y
408
409#
410# MII PHY device drivers
411#
412CONFIG_MARVELL_PHY=m
413CONFIG_DAVICOM_PHY=m
414CONFIG_QSEMI_PHY=m
415CONFIG_LXT_PHY=m
416CONFIG_CICADA_PHY=m
417
418#
335# Ethernet (10 or 100Mbit) 419# Ethernet (10 or 100Mbit)
336# 420#
337CONFIG_NET_ETHERNET=y 421CONFIG_NET_ETHERNET=y
@@ -346,7 +430,7 @@ CONFIG_MII=y
346# CONFIG_NET_TULIP is not set 430# CONFIG_NET_TULIP is not set
347# CONFIG_HP100 is not set 431# CONFIG_HP100 is not set
348CONFIG_NET_PCI=y 432CONFIG_NET_PCI=y
349CONFIG_PCNET32=y 433# CONFIG_PCNET32 is not set
350# CONFIG_AMD8111_ETH is not set 434# CONFIG_AMD8111_ETH is not set
351# CONFIG_ADAPTEC_STARFIRE is not set 435# CONFIG_ADAPTEC_STARFIRE is not set
352# CONFIG_B44 is not set 436# CONFIG_B44 is not set
@@ -358,7 +442,11 @@ CONFIG_EEPRO100=y
358# CONFIG_NATSEMI is not set 442# CONFIG_NATSEMI is not set
359# CONFIG_NE2K_PCI is not set 443# CONFIG_NE2K_PCI is not set
360# CONFIG_8139CP is not set 444# CONFIG_8139CP is not set
361# CONFIG_8139TOO is not set 445CONFIG_8139TOO=y
446CONFIG_8139TOO_PIO=y
447# CONFIG_8139TOO_TUNE_TWISTER is not set
448# CONFIG_8139TOO_8129 is not set
449# CONFIG_8139_OLD_RX_RESET is not set
362# CONFIG_SIS900 is not set 450# CONFIG_SIS900 is not set
363# CONFIG_EPIC100 is not set 451# CONFIG_EPIC100 is not set
364# CONFIG_SUNDANCE is not set 452# CONFIG_SUNDANCE is not set
@@ -375,14 +463,19 @@ CONFIG_EEPRO100=y
375# CONFIG_NS83820 is not set 463# CONFIG_NS83820 is not set
376# CONFIG_HAMACHI is not set 464# CONFIG_HAMACHI is not set
377# CONFIG_YELLOWFIN is not set 465# CONFIG_YELLOWFIN is not set
378# CONFIG_R8169 is not set 466CONFIG_R8169=y
467# CONFIG_R8169_NAPI is not set
468# CONFIG_SIS190 is not set
469# CONFIG_SKGE is not set
379# CONFIG_SK98LIN is not set 470# CONFIG_SK98LIN is not set
380# CONFIG_VIA_VELOCITY is not set 471# CONFIG_VIA_VELOCITY is not set
381# CONFIG_TIGON3 is not set 472# CONFIG_TIGON3 is not set
473# CONFIG_BNX2 is not set
382 474
383# 475#
384# Ethernet (10000 Mbit) 476# Ethernet (10000 Mbit)
385# 477#
478# CONFIG_CHELSIO_T1 is not set
386# CONFIG_IXGB is not set 479# CONFIG_IXGB is not set
387# CONFIG_S2IO is not set 480# CONFIG_S2IO is not set
388 481
@@ -395,6 +488,8 @@ CONFIG_EEPRO100=y
395# Wireless LAN (non-hamradio) 488# Wireless LAN (non-hamradio)
396# 489#
397# CONFIG_NET_RADIO is not set 490# CONFIG_NET_RADIO is not set
491# CONFIG_IPW_DEBUG is not set
492CONFIG_IPW2200=m
398 493
399# 494#
400# Wan interfaces 495# Wan interfaces
@@ -416,6 +511,8 @@ CONFIG_SLIP_SMART=y
416CONFIG_SLIP_MODE_SLIP6=y 511CONFIG_SLIP_MODE_SLIP6=y
417# CONFIG_SHAPER is not set 512# CONFIG_SHAPER is not set
418# CONFIG_NETCONSOLE is not set 513# CONFIG_NETCONSOLE is not set
514# CONFIG_NETPOLL is not set
515# CONFIG_NET_POLL_CONTROLLER is not set
419 516
420# 517#
421# ISDN subsystem 518# ISDN subsystem
@@ -435,29 +532,13 @@ CONFIG_INPUT=y
435# 532#
436# Userland interfaces 533# Userland interfaces
437# 534#
438CONFIG_INPUT_MOUSEDEV=y 535# CONFIG_INPUT_MOUSEDEV is not set
439CONFIG_INPUT_MOUSEDEV_PSAUX=y
440CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
441CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
442# CONFIG_INPUT_JOYDEV is not set 536# CONFIG_INPUT_JOYDEV is not set
443# CONFIG_INPUT_TSDEV is not set 537# CONFIG_INPUT_TSDEV is not set
444# CONFIG_INPUT_EVDEV is not set 538# CONFIG_INPUT_EVDEV is not set
445# CONFIG_INPUT_EVBUG is not set 539# CONFIG_INPUT_EVBUG is not set
446 540
447# 541#
448# Input I/O drivers
449#
450# CONFIG_GAMEPORT is not set
451CONFIG_SOUND_GAMEPORT=y
452CONFIG_SERIO=y
453CONFIG_SERIO_I8042=y
454CONFIG_SERIO_SERPORT=y
455# CONFIG_SERIO_CT82C710 is not set
456# CONFIG_SERIO_PCIPS2 is not set
457# CONFIG_SERIO_LIBPS2 is not set
458CONFIG_SERIO_RAW=m
459
460#
461# Input Device Drivers 542# Input Device Drivers
462# 543#
463# CONFIG_INPUT_KEYBOARD is not set 544# CONFIG_INPUT_KEYBOARD is not set
@@ -467,6 +548,12 @@ CONFIG_SERIO_RAW=m
467# CONFIG_INPUT_MISC is not set 548# CONFIG_INPUT_MISC is not set
468 549
469# 550#
551# Hardware I/O ports
552#
553# CONFIG_SERIO is not set
554# CONFIG_GAMEPORT is not set
555
556#
470# Character devices 557# Character devices
471# 558#
472CONFIG_VT=y 559CONFIG_VT=y
@@ -477,16 +564,16 @@ CONFIG_HW_CONSOLE=y
477# 564#
478# Serial drivers 565# Serial drivers
479# 566#
480CONFIG_SERIAL_8250=y 567# CONFIG_SERIAL_8250 is not set
481CONFIG_SERIAL_8250_CONSOLE=y
482CONFIG_SERIAL_8250_NR_UARTS=4
483# CONFIG_SERIAL_8250_EXTENDED is not set
484 568
485# 569#
486# Non-8250 serial port support 570# Non-8250 serial port support
487# 571#
488CONFIG_SERIAL_CORE=y 572CONFIG_SERIAL_CORE=y
489CONFIG_SERIAL_CORE_CONSOLE=y 573CONFIG_SERIAL_CORE_CONSOLE=y
574CONFIG_SERIAL_VR41XX=y
575CONFIG_SERIAL_VR41XX_CONSOLE=y
576# CONFIG_SERIAL_JSM is not set
490CONFIG_UNIX98_PTYS=y 577CONFIG_UNIX98_PTYS=y
491CONFIG_LEGACY_PTYS=y 578CONFIG_LEGACY_PTYS=y
492CONFIG_LEGACY_PTY_COUNT=256 579CONFIG_LEGACY_PTY_COUNT=256
@@ -505,14 +592,21 @@ CONFIG_LEGACY_PTY_COUNT=256
505# CONFIG_DTLK is not set 592# CONFIG_DTLK is not set
506# CONFIG_R3964 is not set 593# CONFIG_R3964 is not set
507# CONFIG_APPLICOM is not set 594# CONFIG_APPLICOM is not set
595CONFIG_TANBAC_TB0219=y
508 596
509# 597#
510# Ftape, the floppy tape device driver 598# Ftape, the floppy tape device driver
511# 599#
512# CONFIG_DRM is not set 600# CONFIG_DRM is not set
601CONFIG_GPIO_VR41XX=y
513# CONFIG_RAW_DRIVER is not set 602# CONFIG_RAW_DRIVER is not set
514 603
515# 604#
605# TPM devices
606#
607# CONFIG_TCG_TPM is not set
608
609#
516# I2C support 610# I2C support
517# 611#
518# CONFIG_I2C is not set 612# CONFIG_I2C is not set
@@ -523,10 +617,20 @@ CONFIG_LEGACY_PTY_COUNT=256
523# CONFIG_W1 is not set 617# CONFIG_W1 is not set
524 618
525# 619#
620# Hardware Monitoring support
621#
622# CONFIG_HWMON is not set
623# CONFIG_HWMON_VID is not set
624
625#
526# Misc devices 626# Misc devices
527# 627#
528 628
529# 629#
630# Multimedia Capabilities Port drivers
631#
632
633#
530# Multimedia devices 634# Multimedia devices
531# 635#
532# CONFIG_VIDEO_DEV is not set 636# CONFIG_VIDEO_DEV is not set
@@ -546,7 +650,6 @@ CONFIG_LEGACY_PTY_COUNT=256
546# 650#
547# CONFIG_VGA_CONSOLE is not set 651# CONFIG_VGA_CONSOLE is not set
548CONFIG_DUMMY_CONSOLE=y 652CONFIG_DUMMY_CONSOLE=y
549# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
550 653
551# 654#
552# Sound 655# Sound
@@ -556,13 +659,122 @@ CONFIG_DUMMY_CONSOLE=y
556# 659#
557# USB support 660# USB support
558# 661#
559# CONFIG_USB is not set
560CONFIG_USB_ARCH_HAS_HCD=y 662CONFIG_USB_ARCH_HAS_HCD=y
561CONFIG_USB_ARCH_HAS_OHCI=y 663CONFIG_USB_ARCH_HAS_OHCI=y
664CONFIG_USB=m
665# CONFIG_USB_DEBUG is not set
666
667#
668# Miscellaneous USB options
669#
670CONFIG_USB_DEVICEFS=y
671# CONFIG_USB_BANDWIDTH is not set
672# CONFIG_USB_DYNAMIC_MINORS is not set
673# CONFIG_USB_OTG is not set
674
675#
676# USB Host Controller Drivers
677#
678CONFIG_USB_EHCI_HCD=m
679# CONFIG_USB_EHCI_SPLIT_ISO is not set
680# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
681# CONFIG_USB_ISP116X_HCD is not set
682CONFIG_USB_OHCI_HCD=m
683# CONFIG_USB_OHCI_BIG_ENDIAN is not set
684CONFIG_USB_OHCI_LITTLE_ENDIAN=y
685# CONFIG_USB_UHCI_HCD is not set
686# CONFIG_USB_SL811_HCD is not set
687
688#
689# USB Device Class drivers
690#
691# CONFIG_USB_BLUETOOTH_TTY is not set
692# CONFIG_USB_ACM is not set
693# CONFIG_USB_PRINTER is not set
562 694
563# 695#
564# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information 696# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
565# 697#
698# CONFIG_USB_STORAGE is not set
699
700#
701# USB Input Devices
702#
703# CONFIG_USB_HID is not set
704
705#
706# USB HID Boot Protocol drivers
707#
708# CONFIG_USB_KBD is not set
709# CONFIG_USB_MOUSE is not set
710# CONFIG_USB_AIPTEK is not set
711# CONFIG_USB_WACOM is not set
712# CONFIG_USB_ACECAD is not set
713# CONFIG_USB_KBTAB is not set
714# CONFIG_USB_POWERMATE is not set
715# CONFIG_USB_MTOUCH is not set
716# CONFIG_USB_ITMTOUCH is not set
717# CONFIG_USB_EGALAX is not set
718# CONFIG_USB_YEALINK is not set
719# CONFIG_USB_XPAD is not set
720# CONFIG_USB_ATI_REMOTE is not set
721# CONFIG_USB_KEYSPAN_REMOTE is not set
722# CONFIG_USB_APPLETOUCH is not set
723
724#
725# USB Imaging devices
726#
727# CONFIG_USB_MDC800 is not set
728
729#
730# USB Multimedia devices
731#
732# CONFIG_USB_DABUSB is not set
733
734#
735# Video4Linux support is needed for USB Multimedia device support
736#
737
738#
739# USB Network Adapters
740#
741# CONFIG_USB_CATC is not set
742# CONFIG_USB_KAWETH is not set
743# CONFIG_USB_PEGASUS is not set
744# CONFIG_USB_RTL8150 is not set
745# CONFIG_USB_USBNET is not set
746CONFIG_USB_MON=y
747
748#
749# USB port drivers
750#
751
752#
753# USB Serial Converter support
754#
755# CONFIG_USB_SERIAL is not set
756
757#
758# USB Miscellaneous drivers
759#
760# CONFIG_USB_EMI62 is not set
761# CONFIG_USB_EMI26 is not set
762# CONFIG_USB_AUERSWALD is not set
763# CONFIG_USB_RIO500 is not set
764# CONFIG_USB_LEGOTOWER is not set
765# CONFIG_USB_LCD is not set
766# CONFIG_USB_LED is not set
767# CONFIG_USB_CYTHERM is not set
768# CONFIG_USB_PHIDGETKIT is not set
769# CONFIG_USB_PHIDGETSERVO is not set
770# CONFIG_USB_IDMOUSE is not set
771# CONFIG_USB_SISUSBVGA is not set
772# CONFIG_USB_LD is not set
773# CONFIG_USB_TEST is not set
774
775#
776# USB DSL modem support
777#
566 778
567# 779#
568# USB Gadget Support 780# USB Gadget Support
@@ -580,10 +792,15 @@ CONFIG_USB_ARCH_HAS_OHCI=y
580# CONFIG_INFINIBAND is not set 792# CONFIG_INFINIBAND is not set
581 793
582# 794#
795# SN Devices
796#
797
798#
583# File systems 799# File systems
584# 800#
585CONFIG_EXT2_FS=y 801CONFIG_EXT2_FS=y
586# CONFIG_EXT2_FS_XATTR is not set 802# CONFIG_EXT2_FS_XATTR is not set
803# CONFIG_EXT2_FS_XIP is not set
587CONFIG_EXT3_FS=m 804CONFIG_EXT3_FS=m
588CONFIG_EXT3_FS_XATTR=y 805CONFIG_EXT3_FS_XATTR=y
589# CONFIG_EXT3_FS_POSIX_ACL is not set 806# CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -597,18 +814,22 @@ CONFIG_JFS_FS=m
597# CONFIG_JFS_SECURITY is not set 814# CONFIG_JFS_SECURITY is not set
598# CONFIG_JFS_DEBUG is not set 815# CONFIG_JFS_DEBUG is not set
599# CONFIG_JFS_STATISTICS is not set 816# CONFIG_JFS_STATISTICS is not set
817# CONFIG_FS_POSIX_ACL is not set
600CONFIG_XFS_FS=y 818CONFIG_XFS_FS=y
601# CONFIG_XFS_RT is not set 819CONFIG_XFS_EXPORT=y
602CONFIG_XFS_QUOTA=y 820CONFIG_XFS_QUOTA=y
603# CONFIG_XFS_SECURITY is not set 821# CONFIG_XFS_SECURITY is not set
604CONFIG_XFS_POSIX_ACL=y 822CONFIG_XFS_POSIX_ACL=y
823# CONFIG_XFS_RT is not set
605# CONFIG_MINIX_FS is not set 824# CONFIG_MINIX_FS is not set
606CONFIG_ROMFS_FS=m 825CONFIG_ROMFS_FS=m
826CONFIG_INOTIFY=y
607# CONFIG_QUOTA is not set 827# CONFIG_QUOTA is not set
608CONFIG_QUOTACTL=y 828CONFIG_QUOTACTL=y
609CONFIG_DNOTIFY=y 829CONFIG_DNOTIFY=y
610# CONFIG_AUTOFS_FS is not set 830# CONFIG_AUTOFS_FS is not set
611CONFIG_AUTOFS4_FS=y 831CONFIG_AUTOFS4_FS=y
832CONFIG_FUSE_FS=m
612 833
613# 834#
614# CD-ROM/DVD Filesystems 835# CD-ROM/DVD Filesystems
@@ -635,13 +856,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
635CONFIG_PROC_FS=y 856CONFIG_PROC_FS=y
636CONFIG_PROC_KCORE=y 857CONFIG_PROC_KCORE=y
637CONFIG_SYSFS=y 858CONFIG_SYSFS=y
638# CONFIG_DEVFS_FS is not set
639CONFIG_DEVPTS_FS_XATTR=y
640CONFIG_DEVPTS_FS_SECURITY=y
641CONFIG_TMPFS=y 859CONFIG_TMPFS=y
642# CONFIG_TMPFS_XATTR is not set
643# CONFIG_HUGETLB_PAGE is not set 860# CONFIG_HUGETLB_PAGE is not set
644CONFIG_RAMFS=y 861CONFIG_RAMFS=y
862CONFIG_RELAYFS_FS=m
645 863
646# 864#
647# Miscellaneous filesystems 865# Miscellaneous filesystems
@@ -665,16 +883,19 @@ CONFIG_CRAMFS=m
665# 883#
666CONFIG_NFS_FS=y 884CONFIG_NFS_FS=y
667CONFIG_NFS_V3=y 885CONFIG_NFS_V3=y
886# CONFIG_NFS_V3_ACL is not set
668# CONFIG_NFS_V4 is not set 887# CONFIG_NFS_V4 is not set
669# CONFIG_NFS_DIRECTIO is not set 888# CONFIG_NFS_DIRECTIO is not set
670CONFIG_NFSD=y 889CONFIG_NFSD=y
671CONFIG_NFSD_V3=y 890CONFIG_NFSD_V3=y
891# CONFIG_NFSD_V3_ACL is not set
672# CONFIG_NFSD_V4 is not set 892# CONFIG_NFSD_V4 is not set
673CONFIG_NFSD_TCP=y 893CONFIG_NFSD_TCP=y
674CONFIG_ROOT_NFS=y 894CONFIG_ROOT_NFS=y
675CONFIG_LOCKD=y 895CONFIG_LOCKD=y
676CONFIG_LOCKD_V4=y 896CONFIG_LOCKD_V4=y
677CONFIG_EXPORTFS=y 897CONFIG_EXPORTFS=y
898CONFIG_NFS_COMMON=y
678CONFIG_SUNRPC=y 899CONFIG_SUNRPC=y
679# CONFIG_RPCSEC_GSS_KRB5 is not set 900# CONFIG_RPCSEC_GSS_KRB5 is not set
680# CONFIG_RPCSEC_GSS_SPKM3 is not set 901# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -685,6 +906,7 @@ CONFIG_SMB_NLS_REMOTE="cp932"
685# CONFIG_NCP_FS is not set 906# CONFIG_NCP_FS is not set
686# CONFIG_CODA_FS is not set 907# CONFIG_CODA_FS is not set
687# CONFIG_AFS_FS is not set 908# CONFIG_AFS_FS is not set
909# CONFIG_9P_FS is not set
688 910
689# 911#
690# Partition Types 912# Partition Types
@@ -744,9 +966,11 @@ CONFIG_NLS_ISO8859_1=m
744# 966#
745# Kernel hacking 967# Kernel hacking
746# 968#
969# CONFIG_PRINTK_TIME is not set
747# CONFIG_DEBUG_KERNEL is not set 970# CONFIG_DEBUG_KERNEL is not set
971CONFIG_LOG_BUF_SHIFT=14
748CONFIG_CROSSCOMPILE=y 972CONFIG_CROSSCOMPILE=y
749CONFIG_CMDLINE="mem=64M console=ttyS0,38400 ip=bootp root=/dev/nfs" 973CONFIG_CMDLINE="mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
750 974
751# 975#
752# Security options 976# Security options
@@ -758,7 +982,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
758# 982#
759# Cryptographic options 983# Cryptographic options
760# 984#
761# CONFIG_CRYPTO is not set 985CONFIG_CRYPTO=y
986CONFIG_CRYPTO_HMAC=y
987CONFIG_CRYPTO_NULL=m
988CONFIG_CRYPTO_MD4=m
989CONFIG_CRYPTO_MD5=m
990CONFIG_CRYPTO_SHA1=m
991CONFIG_CRYPTO_SHA256=m
992CONFIG_CRYPTO_SHA512=m
993CONFIG_CRYPTO_WP512=m
994CONFIG_CRYPTO_TGR192=m
995CONFIG_CRYPTO_DES=m
996CONFIG_CRYPTO_BLOWFISH=m
997CONFIG_CRYPTO_TWOFISH=m
998CONFIG_CRYPTO_SERPENT=m
999CONFIG_CRYPTO_AES=m
1000CONFIG_CRYPTO_CAST5=m
1001CONFIG_CRYPTO_CAST6=m
1002CONFIG_CRYPTO_TEA=m
1003CONFIG_CRYPTO_ARC4=m
1004CONFIG_CRYPTO_KHAZAD=m
1005CONFIG_CRYPTO_ANUBIS=m
1006CONFIG_CRYPTO_DEFLATE=m
1007CONFIG_CRYPTO_MICHAEL_MIC=m
1008CONFIG_CRYPTO_CRC32C=m
1009# CONFIG_CRYPTO_TEST is not set
762 1010
763# 1011#
764# Hardware crypto devices 1012# Hardware crypto devices
@@ -768,9 +1016,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
768# Library routines 1016# Library routines
769# 1017#
770CONFIG_CRC_CCITT=m 1018CONFIG_CRC_CCITT=m
1019CONFIG_CRC16=m
771CONFIG_CRC32=y 1020CONFIG_CRC32=y
772# CONFIG_LIBCRC32C is not set 1021CONFIG_LIBCRC32C=m
773CONFIG_ZLIB_INFLATE=y 1022CONFIG_ZLIB_INFLATE=y
774CONFIG_ZLIB_DEFLATE=m 1023CONFIG_ZLIB_DEFLATE=m
775CONFIG_GENERIC_HARDIRQS=y
776CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index 17b9f2f65ba0..95344832d66e 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.13-mm1 3# Linux kernel version: 2.6.14-rc5-mm1
4# Thu Sep 1 22:58:34 2005 4# Tue Oct 25 00:20:22 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -19,6 +19,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32
19CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y 20CONFIG_LOCALVERSION_AUTO=y
21CONFIG_SWAP=y 21CONFIG_SWAP=y
22CONFIG_SWAP_PREFETCH=y
22CONFIG_SYSVIPC=y 23CONFIG_SYSVIPC=y
23# CONFIG_POSIX_MQUEUE is not set 24# CONFIG_POSIX_MQUEUE is not set
24# CONFIG_BSD_PROCESS_ACCT is not set 25# CONFIG_BSD_PROCESS_ACCT is not set
@@ -55,74 +56,91 @@ CONFIG_OBSOLETE_MODPARM=y
55CONFIG_MODVERSIONS=y 56CONFIG_MODVERSIONS=y
56CONFIG_MODULE_SRCVERSION_ALL=y 57CONFIG_MODULE_SRCVERSION_ALL=y
57CONFIG_KMOD=y 58CONFIG_KMOD=y
58CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
59CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
60CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
61CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
62
63#
64# Kernel type
65#
66CONFIG_32BIT=y
67# CONFIG_64BIT is not set
68 59
69# 60#
70# Machine selection 61# Machine selection
71# 62#
72# CONFIG_MACH_JAZZ is not set 63# CONFIG_MIPS_MTX1 is not set
73CONFIG_MACH_VR41XX=y 64# CONFIG_MIPS_BOSPORUS is not set
74# CONFIG_NEC_CMBVR4133 is not set 65# CONFIG_MIPS_PB1000 is not set
75# CONFIG_CASIO_E55 is not set 66# CONFIG_MIPS_PB1100 is not set
76# CONFIG_IBM_WORKPAD is not set 67# CONFIG_MIPS_PB1500 is not set
77CONFIG_TANBAC_TB022X=y 68# CONFIG_MIPS_PB1550 is not set
78# CONFIG_TANBAC_TB0226 is not set 69# CONFIG_MIPS_PB1200 is not set
79CONFIG_TANBAC_TB0287=y 70# CONFIG_MIPS_DB1000 is not set
80# CONFIG_VICTOR_MPC30X is not set 71# CONFIG_MIPS_DB1100 is not set
81# CONFIG_ZAO_CAPCELLA is not set 72# CONFIG_MIPS_DB1500 is not set
82CONFIG_PCI_VR41XX=y 73# CONFIG_MIPS_DB1550 is not set
83# CONFIG_VRC4173 is not set 74# CONFIG_MIPS_DB1200 is not set
84# CONFIG_TOSHIBA_JMR3927 is not set 75# CONFIG_MIPS_MIRAGE is not set
85# CONFIG_MIPS_COBALT is not set 76# CONFIG_MIPS_COBALT is not set
86# CONFIG_MACH_DECSTATION is not set 77# CONFIG_MACH_DECSTATION is not set
87# CONFIG_MIPS_EV64120 is not set 78# CONFIG_MIPS_EV64120 is not set
88# CONFIG_MIPS_EV96100 is not set 79# CONFIG_MIPS_EV96100 is not set
89# CONFIG_MIPS_IVR is not set 80# CONFIG_MIPS_IVR is not set
90# CONFIG_LASAT is not set
91# CONFIG_MIPS_ITE8172 is not set 81# CONFIG_MIPS_ITE8172 is not set
82# CONFIG_MACH_JAZZ is not set
83# CONFIG_LASAT is not set
92# CONFIG_MIPS_ATLAS is not set 84# CONFIG_MIPS_ATLAS is not set
93# CONFIG_MIPS_MALTA is not set 85# CONFIG_MIPS_MALTA is not set
94# CONFIG_MIPS_SEAD is not set 86# CONFIG_MIPS_SEAD is not set
87# CONFIG_MIPS_SIM is not set
88# CONFIG_MOMENCO_JAGUAR_ATX is not set
95# CONFIG_MOMENCO_OCELOT is not set 89# CONFIG_MOMENCO_OCELOT is not set
96# CONFIG_MOMENCO_OCELOT_G is not set
97# CONFIG_MOMENCO_OCELOT_C is not set
98# CONFIG_MOMENCO_OCELOT_3 is not set 90# CONFIG_MOMENCO_OCELOT_3 is not set
99# CONFIG_MOMENCO_JAGUAR_ATX is not set 91# CONFIG_MOMENCO_OCELOT_C is not set
100# CONFIG_PMC_YOSEMITE is not set 92# CONFIG_MOMENCO_OCELOT_G is not set
93# CONFIG_MIPS_XXS1500 is not set
94# CONFIG_PNX8550_V2PCI is not set
95# CONFIG_PNX8550_JBS is not set
101# CONFIG_DDB5074 is not set 96# CONFIG_DDB5074 is not set
102# CONFIG_DDB5476 is not set 97# CONFIG_DDB5476 is not set
103# CONFIG_DDB5477 is not set 98# CONFIG_DDB5477 is not set
99CONFIG_MACH_VR41XX=y
100# CONFIG_PMC_YOSEMITE is not set
104# CONFIG_QEMU is not set 101# CONFIG_QEMU is not set
105# CONFIG_SGI_IP22 is not set 102# CONFIG_SGI_IP22 is not set
106# CONFIG_SGI_IP27 is not set 103# CONFIG_SGI_IP27 is not set
107# CONFIG_SGI_IP32 is not set 104# CONFIG_SGI_IP32 is not set
108# CONFIG_SOC_AU1X00 is not set 105# CONFIG_SIBYTE_SWARM is not set
109# CONFIG_SIBYTE_SB1xxx_SOC is not set 106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
110# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
111# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
117# CONFIG_CASIO_E55 is not set
118# CONFIG_IBM_WORKPAD is not set
119# CONFIG_NEC_CMBVR4133 is not set
120CONFIG_TANBAC_TB022X=y
121# CONFIG_TANBAC_TB0226 is not set
122CONFIG_TANBAC_TB0287=y
123# CONFIG_VICTOR_MPC30X is not set
124# CONFIG_ZAO_CAPCELLA is not set
125CONFIG_PCI_VR41XX=y
126# CONFIG_VRC4173 is not set
112CONFIG_RWSEM_GENERIC_SPINLOCK=y 127CONFIG_RWSEM_GENERIC_SPINLOCK=y
113CONFIG_GENERIC_CALIBRATE_DELAY=y 128CONFIG_GENERIC_CALIBRATE_DELAY=y
114CONFIG_HAVE_DEC_LOCK=y
115CONFIG_DMA_NONCOHERENT=y 129CONFIG_DMA_NONCOHERENT=y
116CONFIG_DMA_NEED_PCI_MAP_STATE=y 130CONFIG_DMA_NEED_PCI_MAP_STATE=y
131# CONFIG_CPU_BIG_ENDIAN is not set
117CONFIG_CPU_LITTLE_ENDIAN=y 132CONFIG_CPU_LITTLE_ENDIAN=y
133CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
118CONFIG_IRQ_CPU=y 134CONFIG_IRQ_CPU=y
119CONFIG_MIPS_L1_CACHE_SHIFT=5 135CONFIG_MIPS_L1_CACHE_SHIFT=5
120 136
121# 137#
122# CPU selection 138# CPU selection
123# 139#
124# CONFIG_CPU_MIPS32 is not set 140# CONFIG_CPU_MIPS32_R1 is not set
125# CONFIG_CPU_MIPS64 is not set 141# CONFIG_CPU_MIPS32_R2 is not set
142# CONFIG_CPU_MIPS64_R1 is not set
143# CONFIG_CPU_MIPS64_R2 is not set
126# CONFIG_CPU_R3000 is not set 144# CONFIG_CPU_R3000 is not set
127# CONFIG_CPU_TX39XX is not set 145# CONFIG_CPU_TX39XX is not set
128CONFIG_CPU_VR41XX=y 146CONFIG_CPU_VR41XX=y
@@ -138,12 +156,25 @@ CONFIG_CPU_VR41XX=y
138# CONFIG_CPU_RM7000 is not set 156# CONFIG_CPU_RM7000 is not set
139# CONFIG_CPU_RM9000 is not set 157# CONFIG_CPU_RM9000 is not set
140# CONFIG_CPU_SB1 is not set 158# CONFIG_CPU_SB1 is not set
159CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
160CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
161CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
162CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
163
164#
165# Kernel type
166#
167CONFIG_32BIT=y
168# CONFIG_64BIT is not set
141CONFIG_PAGE_SIZE_4KB=y 169CONFIG_PAGE_SIZE_4KB=y
142# CONFIG_PAGE_SIZE_8KB is not set 170# CONFIG_PAGE_SIZE_8KB is not set
143# CONFIG_PAGE_SIZE_16KB is not set 171# CONFIG_PAGE_SIZE_16KB is not set
144# CONFIG_PAGE_SIZE_64KB is not set 172# CONFIG_PAGE_SIZE_64KB is not set
173# CONFIG_MIPS_MT is not set
145# CONFIG_CPU_ADVANCED is not set 174# CONFIG_CPU_ADVANCED is not set
146CONFIG_CPU_HAS_SYNC=y 175CONFIG_CPU_HAS_SYNC=y
176CONFIG_GENERIC_HARDIRQS=y
177CONFIG_GENERIC_IRQ_PROBE=y
147CONFIG_ARCH_FLATMEM_ENABLE=y 178CONFIG_ARCH_FLATMEM_ENABLE=y
148CONFIG_SELECT_MEMORY_MODEL=y 179CONFIG_SELECT_MEMORY_MODEL=y
149CONFIG_FLATMEM_MANUAL=y 180CONFIG_FLATMEM_MANUAL=y
@@ -152,6 +183,9 @@ CONFIG_FLATMEM_MANUAL=y
152CONFIG_FLATMEM=y 183CONFIG_FLATMEM=y
153CONFIG_FLAT_NODE_MEM_MAP=y 184CONFIG_FLAT_NODE_MEM_MAP=y
154# CONFIG_SPARSEMEM_STATIC is not set 185# CONFIG_SPARSEMEM_STATIC is not set
186CONFIG_SPLIT_PTLOCK_CPUS=4
187CONFIG_PREEMPT_NONE=y
188# CONFIG_PREEMPT_VOLUNTARY is not set
155# CONFIG_PREEMPT is not set 189# CONFIG_PREEMPT is not set
156 190
157# 191#
@@ -262,7 +296,6 @@ CONFIG_TCP_CONG_HTCP=m
262# Network testing 296# Network testing
263# 297#
264# CONFIG_NET_PKTGEN is not set 298# CONFIG_NET_PKTGEN is not set
265# CONFIG_NETFILTER_NETLINK is not set
266# CONFIG_HAMRADIO is not set 299# CONFIG_HAMRADIO is not set
267# CONFIG_IRDA is not set 300# CONFIG_IRDA is not set
268# CONFIG_BT is not set 301# CONFIG_BT is not set
@@ -280,6 +313,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
280# CONFIG_FW_LOADER is not set 313# CONFIG_FW_LOADER is not set
281 314
282# 315#
316# Connector - unified userspace <-> kernelspace linker
317#
318# CONFIG_CONNECTOR is not set
319
320#
283# Memory Technology Devices (MTD) 321# Memory Technology Devices (MTD)
284# 322#
285# CONFIG_MTD is not set 323# CONFIG_MTD is not set
@@ -296,7 +334,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
296# 334#
297# Block devices 335# Block devices
298# 336#
299# CONFIG_BLK_DEV_FD is not set
300# CONFIG_BLK_CPQ_DA is not set 337# CONFIG_BLK_CPQ_DA is not set
301# CONFIG_BLK_CPQ_CISS_DA is not set 338# CONFIG_BLK_CPQ_CISS_DA is not set
302# CONFIG_BLK_DEV_DAC960 is not set 339# CONFIG_BLK_DEV_DAC960 is not set
@@ -312,6 +349,7 @@ CONFIG_BLK_DEV_RAM_COUNT=16
312CONFIG_BLK_DEV_RAM_SIZE=4096 349CONFIG_BLK_DEV_RAM_SIZE=4096
313# CONFIG_BLK_DEV_INITRD is not set 350# CONFIG_BLK_DEV_INITRD is not set
314# CONFIG_LBD is not set 351# CONFIG_LBD is not set
352# CONFIG_BLK_DEV_IO_TRACE is not set
315# CONFIG_CDROM_PKTCDVD is not set 353# CONFIG_CDROM_PKTCDVD is not set
316 354
317# 355#
@@ -321,6 +359,11 @@ CONFIG_IOSCHED_NOOP=y
321CONFIG_IOSCHED_AS=y 359CONFIG_IOSCHED_AS=y
322CONFIG_IOSCHED_DEADLINE=y 360CONFIG_IOSCHED_DEADLINE=y
323CONFIG_IOSCHED_CFQ=y 361CONFIG_IOSCHED_CFQ=y
362CONFIG_DEFAULT_AS=y
363# CONFIG_DEFAULT_DEADLINE is not set
364# CONFIG_DEFAULT_CFQ is not set
365# CONFIG_DEFAULT_NOOP is not set
366CONFIG_DEFAULT_IOSCHED="anticipatory"
324# CONFIG_ATA_OVER_ETH is not set 367# CONFIG_ATA_OVER_ETH is not set
325 368
326# 369#
@@ -410,13 +453,20 @@ CONFIG_BLK_DEV_SD=y
410# CONFIG_SCSI_SPI_ATTRS is not set 453# CONFIG_SCSI_SPI_ATTRS is not set
411# CONFIG_SCSI_FC_ATTRS is not set 454# CONFIG_SCSI_FC_ATTRS is not set
412# CONFIG_SCSI_ISCSI_ATTRS is not set 455# CONFIG_SCSI_ISCSI_ATTRS is not set
456# CONFIG_SCSI_SAS_ATTRS is not set
457
458#
459# SCSI Transport Layers
460#
461# CONFIG_SAS_CLASS is not set
413 462
414# 463#
415# SCSI low-level drivers 464# SCSI low-level drivers
416# 465#
466# CONFIG_ISCSI_TCP is not set
467# CONFIG_SCSI_ARCMSR is not set
417# CONFIG_BLK_DEV_3W_XXXX_RAID is not set 468# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
418# CONFIG_SCSI_3W_9XXX is not set 469# CONFIG_SCSI_3W_9XXX is not set
419# CONFIG_SCSI_ARCMSR is not set
420# CONFIG_SCSI_ACARD is not set 470# CONFIG_SCSI_ACARD is not set
421# CONFIG_SCSI_AACRAID is not set 471# CONFIG_SCSI_AACRAID is not set
422# CONFIG_SCSI_AIC7XXX is not set 472# CONFIG_SCSI_AIC7XXX is not set
@@ -425,12 +475,10 @@ CONFIG_BLK_DEV_SD=y
425# CONFIG_SCSI_DPT_I2O is not set 475# CONFIG_SCSI_DPT_I2O is not set
426# CONFIG_MEGARAID_NEWGEN is not set 476# CONFIG_MEGARAID_NEWGEN is not set
427# CONFIG_MEGARAID_LEGACY is not set 477# CONFIG_MEGARAID_LEGACY is not set
478# CONFIG_MEGARAID_SAS is not set
428# CONFIG_SCSI_SATA is not set 479# CONFIG_SCSI_SATA is not set
429# CONFIG_SCSI_BUSLOGIC is not set
430# CONFIG_SCSI_DMX3191D is not set 480# CONFIG_SCSI_DMX3191D is not set
431# CONFIG_SCSI_EATA is not set
432# CONFIG_SCSI_FUTURE_DOMAIN is not set 481# CONFIG_SCSI_FUTURE_DOMAIN is not set
433# CONFIG_SCSI_GDTH is not set
434# CONFIG_SCSI_IPS is not set 482# CONFIG_SCSI_IPS is not set
435# CONFIG_SCSI_INITIO is not set 483# CONFIG_SCSI_INITIO is not set
436# CONFIG_SCSI_INIA100 is not set 484# CONFIG_SCSI_INIA100 is not set
@@ -462,6 +510,7 @@ CONFIG_SCSI_QLA2XXX=y
462# CONFIG_FUSION is not set 510# CONFIG_FUSION is not set
463# CONFIG_FUSION_SPI is not set 511# CONFIG_FUSION_SPI is not set
464# CONFIG_FUSION_FC is not set 512# CONFIG_FUSION_FC is not set
513# CONFIG_FUSION_SAS is not set
465 514
466# 515#
467# IEEE 1394 (FireWire) support 516# IEEE 1394 (FireWire) support
@@ -529,6 +578,7 @@ CONFIG_NET_ETHERNET=y
529CONFIG_MII=y 578CONFIG_MII=y
530# CONFIG_HAPPYMEAL is not set 579# CONFIG_HAPPYMEAL is not set
531# CONFIG_SUNGEM is not set 580# CONFIG_SUNGEM is not set
581# CONFIG_CASSINI is not set
532# CONFIG_NET_VENDOR_3COM is not set 582# CONFIG_NET_VENDOR_3COM is not set
533 583
534# 584#
@@ -572,6 +622,7 @@ CONFIG_R8169=y
572# Wireless LAN (non-hamradio) 622# Wireless LAN (non-hamradio)
573# 623#
574# CONFIG_NET_RADIO is not set 624# CONFIG_NET_RADIO is not set
625# CONFIG_HOSTAP is not set
575 626
576# 627#
577# Wan interfaces 628# Wan interfaces
@@ -682,6 +733,7 @@ CONFIG_GPIO_VR41XX=y
682# TPM devices 733# TPM devices
683# 734#
684# CONFIG_TCG_TPM is not set 735# CONFIG_TCG_TPM is not set
736# CONFIG_TELCLOCK is not set
685 737
686# 738#
687# I2C support 739# I2C support
@@ -770,12 +822,15 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
770# 822#
771# USB Device Class drivers 823# USB Device Class drivers
772# 824#
773# CONFIG_USB_BLUETOOTH_TTY is not set
774# CONFIG_USB_ACM is not set 825# CONFIG_USB_ACM is not set
775# CONFIG_USB_PRINTER is not set 826# CONFIG_USB_PRINTER is not set
776 827
777# 828#
778# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information 829# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
830#
831
832#
833# may also be needed; see USB_STORAGE Help for more information
779# 834#
780CONFIG_USB_STORAGE=m 835CONFIG_USB_STORAGE=m
781# CONFIG_USB_STORAGE_DEBUG is not set 836# CONFIG_USB_STORAGE_DEBUG is not set
@@ -891,6 +946,11 @@ CONFIG_USB_MON=y
891# 946#
892 947
893# 948#
949# EDAC - error detection and reporting (RAS)
950#
951# CONFIG_EDAC is not set
952
953#
894# Distributed Lock Manager 954# Distributed Lock Manager
895# 955#
896# CONFIG_DLM is not set 956# CONFIG_DLM is not set
@@ -901,20 +961,22 @@ CONFIG_USB_MON=y
901CONFIG_EXT2_FS=y 961CONFIG_EXT2_FS=y
902# CONFIG_EXT2_FS_XATTR is not set 962# CONFIG_EXT2_FS_XATTR is not set
903# CONFIG_EXT2_FS_XIP is not set 963# CONFIG_EXT2_FS_XIP is not set
904# CONFIG_EXT3_FS is not set 964CONFIG_EXT3_FS=y
965CONFIG_EXT3_FS_XATTR=y
966# CONFIG_EXT3_FS_POSIX_ACL is not set
967# CONFIG_EXT3_FS_SECURITY is not set
968CONFIG_JBD=y
969# CONFIG_JBD_DEBUG is not set
970CONFIG_FS_MBCACHE=y
905# CONFIG_REISER4_FS is not set 971# CONFIG_REISER4_FS is not set
906# CONFIG_REISERFS_FS is not set 972# CONFIG_REISERFS_FS is not set
907# CONFIG_JFS_FS is not set 973# CONFIG_JFS_FS is not set
908# CONFIG_FS_POSIX_ACL is not set 974# CONFIG_FS_POSIX_ACL is not set
909
910#
911# XFS support
912#
913CONFIG_XFS_FS=y 975CONFIG_XFS_FS=y
914# CONFIG_XFS_RT is not set
915CONFIG_XFS_QUOTA=y 976CONFIG_XFS_QUOTA=y
916# CONFIG_XFS_SECURITY is not set 977# CONFIG_XFS_SECURITY is not set
917CONFIG_XFS_POSIX_ACL=y 978CONFIG_XFS_POSIX_ACL=y
979# CONFIG_XFS_RT is not set
918# CONFIG_OCFS2_FS is not set 980# CONFIG_OCFS2_FS is not set
919# CONFIG_MINIX_FS is not set 981# CONFIG_MINIX_FS is not set
920CONFIG_ROMFS_FS=m 982CONFIG_ROMFS_FS=m
@@ -948,8 +1010,8 @@ CONFIG_SYSFS=y
948CONFIG_TMPFS=y 1010CONFIG_TMPFS=y
949# CONFIG_HUGETLB_PAGE is not set 1011# CONFIG_HUGETLB_PAGE is not set
950CONFIG_RAMFS=y 1012CONFIG_RAMFS=y
951# CONFIG_CONFIGFS_FS is not set
952# CONFIG_RELAYFS_FS is not set 1013# CONFIG_RELAYFS_FS is not set
1014# CONFIG_CONFIGFS_FS is not set
953 1015
954# 1016#
955# Miscellaneous filesystems 1017# Miscellaneous filesystems
@@ -1004,6 +1066,11 @@ CONFIG_MSDOS_PARTITION=y
1004# CONFIG_NLS is not set 1066# CONFIG_NLS is not set
1005 1067
1006# 1068#
1069# Profiling support
1070#
1071# CONFIG_PROFILING is not set
1072
1073#
1007# Kernel hacking 1074# Kernel hacking
1008# 1075#
1009# CONFIG_PRINTK_TIME is not set 1076# CONFIG_PRINTK_TIME is not set
@@ -1036,6 +1103,3 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
1036CONFIG_CRC32=y 1103CONFIG_CRC32=y
1037# CONFIG_LIBCRC32C is not set 1104# CONFIG_LIBCRC32C is not set
1038CONFIG_ZLIB_INFLATE=m 1105CONFIG_ZLIB_INFLATE=m
1039CONFIG_GENERIC_HARDIRQS=y
1040CONFIG_GENERIC_IRQ_PROBE=y
1041CONFIG_ISA_DMA_API=y
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index 16e07fca446f..ab13621ef3b9 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:12 2005 4# Thu Oct 20 22:27:16 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,24 +11,29 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14 27CONFIG_HOTPLUG=y
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 29# CONFIG_IKCONFIG is not set
30CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 31CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 32CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 33# CONFIG_KALLSYMS_EXTRA_PASS is not set
34CONFIG_PRINTK=y
35CONFIG_BUG=y
36CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 37CONFIG_FUTEX=y
36CONFIG_EPOLL=y 38CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 39# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 43CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 44CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
44 47
45# 48#
46# Loadable module support 49# Loadable module support
@@ -56,56 +59,84 @@ CONFIG_KMOD=y
56# 59#
57# Machine selection 60# Machine selection
58# 61#
59# CONFIG_MACH_JAZZ is not set 62# CONFIG_MIPS_MTX1 is not set
60CONFIG_MACH_VR41XX=y 63# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_NEC_CMBVR4133 is not set 64# CONFIG_MIPS_PB1000 is not set
62# CONFIG_CASIO_E55 is not set 65# CONFIG_MIPS_PB1100 is not set
63CONFIG_IBM_WORKPAD=y 66# CONFIG_MIPS_PB1500 is not set
64# CONFIG_TANBAC_TB0226 is not set 67# CONFIG_MIPS_PB1550 is not set
65# CONFIG_TANBAC_TB0229 is not set 68# CONFIG_MIPS_PB1200 is not set
66# CONFIG_VICTOR_MPC30X is not set 69# CONFIG_MIPS_DB1000 is not set
67# CONFIG_ZAO_CAPCELLA is not set 70# CONFIG_MIPS_DB1100 is not set
68CONFIG_VRC4171=y 71# CONFIG_MIPS_DB1500 is not set
69# CONFIG_TOSHIBA_JMR3927 is not set 72# CONFIG_MIPS_DB1550 is not set
73# CONFIG_MIPS_DB1200 is not set
74# CONFIG_MIPS_MIRAGE is not set
70# CONFIG_MIPS_COBALT is not set 75# CONFIG_MIPS_COBALT is not set
71# CONFIG_MACH_DECSTATION is not set 76# CONFIG_MACH_DECSTATION is not set
72# CONFIG_MIPS_EV64120 is not set 77# CONFIG_MIPS_EV64120 is not set
73# CONFIG_MIPS_EV96100 is not set 78# CONFIG_MIPS_EV96100 is not set
74# CONFIG_MIPS_IVR is not set 79# CONFIG_MIPS_IVR is not set
75# CONFIG_LASAT is not set
76# CONFIG_MIPS_ITE8172 is not set 80# CONFIG_MIPS_ITE8172 is not set
81# CONFIG_MACH_JAZZ is not set
82# CONFIG_LASAT is not set
77# CONFIG_MIPS_ATLAS is not set 83# CONFIG_MIPS_ATLAS is not set
78# CONFIG_MIPS_MALTA is not set 84# CONFIG_MIPS_MALTA is not set
79# CONFIG_MIPS_SEAD is not set 85# CONFIG_MIPS_SEAD is not set
86# CONFIG_MIPS_SIM is not set
87# CONFIG_MOMENCO_JAGUAR_ATX is not set
80# CONFIG_MOMENCO_OCELOT is not set 88# CONFIG_MOMENCO_OCELOT is not set
81# CONFIG_MOMENCO_OCELOT_G is not set
82# CONFIG_MOMENCO_OCELOT_C is not set
83# CONFIG_MOMENCO_OCELOT_3 is not set 89# CONFIG_MOMENCO_OCELOT_3 is not set
84# CONFIG_MOMENCO_JAGUAR_ATX is not set 90# CONFIG_MOMENCO_OCELOT_C is not set
85# CONFIG_PMC_YOSEMITE is not set 91# CONFIG_MOMENCO_OCELOT_G is not set
92# CONFIG_MIPS_XXS1500 is not set
93# CONFIG_PNX8550_V2PCI is not set
94# CONFIG_PNX8550_JBS is not set
86# CONFIG_DDB5074 is not set 95# CONFIG_DDB5074 is not set
87# CONFIG_DDB5476 is not set 96# CONFIG_DDB5476 is not set
88# CONFIG_DDB5477 is not set 97# CONFIG_DDB5477 is not set
89# CONFIG_NEC_OSPREY is not set 98CONFIG_MACH_VR41XX=y
99# CONFIG_PMC_YOSEMITE is not set
100# CONFIG_QEMU is not set
90# CONFIG_SGI_IP22 is not set 101# CONFIG_SGI_IP22 is not set
91# CONFIG_SOC_AU1X00 is not set 102# CONFIG_SGI_IP27 is not set
92# CONFIG_SIBYTE_SB1xxx_SOC is not set 103# CONFIG_SGI_IP32 is not set
104# CONFIG_SIBYTE_BIGSUR is not set
105# CONFIG_SIBYTE_SWARM is not set
106# CONFIG_SIBYTE_SENTOSA is not set
107# CONFIG_SIBYTE_RHONE is not set
108# CONFIG_SIBYTE_CARMEL is not set
109# CONFIG_SIBYTE_PTSWARM is not set
110# CONFIG_SIBYTE_LITTLESUR is not set
111# CONFIG_SIBYTE_CRHINE is not set
112# CONFIG_SIBYTE_CRHONE is not set
93# CONFIG_SNI_RM200_PCI is not set 113# CONFIG_SNI_RM200_PCI is not set
114# CONFIG_TOSHIBA_JMR3927 is not set
94# CONFIG_TOSHIBA_RBTX4927 is not set 115# CONFIG_TOSHIBA_RBTX4927 is not set
116# CONFIG_TOSHIBA_RBTX4938 is not set
117# CONFIG_NEC_CMBVR4133 is not set
118# CONFIG_CASIO_E55 is not set
119CONFIG_IBM_WORKPAD=y
120# CONFIG_TANBAC_TB022X is not set
121# CONFIG_VICTOR_MPC30X is not set
122# CONFIG_ZAO_CAPCELLA is not set
95CONFIG_RWSEM_GENERIC_SPINLOCK=y 123CONFIG_RWSEM_GENERIC_SPINLOCK=y
96CONFIG_GENERIC_CALIBRATE_DELAY=y 124CONFIG_GENERIC_CALIBRATE_DELAY=y
97CONFIG_HAVE_DEC_LOCK=y
98CONFIG_DMA_NONCOHERENT=y 125CONFIG_DMA_NONCOHERENT=y
99CONFIG_DMA_NEED_PCI_MAP_STATE=y 126CONFIG_DMA_NEED_PCI_MAP_STATE=y
127# CONFIG_CPU_BIG_ENDIAN is not set
100CONFIG_CPU_LITTLE_ENDIAN=y 128CONFIG_CPU_LITTLE_ENDIAN=y
129CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
101CONFIG_IRQ_CPU=y 130CONFIG_IRQ_CPU=y
102CONFIG_MIPS_L1_CACHE_SHIFT=5 131CONFIG_MIPS_L1_CACHE_SHIFT=5
103 132
104# 133#
105# CPU selection 134# CPU selection
106# 135#
107# CONFIG_CPU_MIPS32 is not set 136# CONFIG_CPU_MIPS32_R1 is not set
108# CONFIG_CPU_MIPS64 is not set 137# CONFIG_CPU_MIPS32_R2 is not set
138# CONFIG_CPU_MIPS64_R1 is not set
139# CONFIG_CPU_MIPS64_R2 is not set
109# CONFIG_CPU_R3000 is not set 140# CONFIG_CPU_R3000 is not set
110# CONFIG_CPU_TX39XX is not set 141# CONFIG_CPU_TX39XX is not set
111CONFIG_CPU_VR41XX=y 142CONFIG_CPU_VR41XX=y
@@ -121,12 +152,36 @@ CONFIG_CPU_VR41XX=y
121# CONFIG_CPU_RM7000 is not set 152# CONFIG_CPU_RM7000 is not set
122# CONFIG_CPU_RM9000 is not set 153# CONFIG_CPU_RM9000 is not set
123# CONFIG_CPU_SB1 is not set 154# CONFIG_CPU_SB1 is not set
155CONFIG_SYS_HAS_CPU_VR41XX=y
156CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
157CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
158CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
159CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
160
161#
162# Kernel type
163#
164CONFIG_32BIT=y
165# CONFIG_64BIT is not set
124CONFIG_PAGE_SIZE_4KB=y 166CONFIG_PAGE_SIZE_4KB=y
125# CONFIG_PAGE_SIZE_8KB is not set 167# CONFIG_PAGE_SIZE_8KB is not set
126# CONFIG_PAGE_SIZE_16KB is not set 168# CONFIG_PAGE_SIZE_16KB is not set
127# CONFIG_PAGE_SIZE_64KB is not set 169# CONFIG_PAGE_SIZE_64KB is not set
170# CONFIG_MIPS_MT is not set
128# CONFIG_CPU_ADVANCED is not set 171# CONFIG_CPU_ADVANCED is not set
129CONFIG_CPU_HAS_SYNC=y 172CONFIG_CPU_HAS_SYNC=y
173CONFIG_GENERIC_HARDIRQS=y
174CONFIG_GENERIC_IRQ_PROBE=y
175CONFIG_ARCH_FLATMEM_ENABLE=y
176CONFIG_SELECT_MEMORY_MODEL=y
177CONFIG_FLATMEM_MANUAL=y
178# CONFIG_DISCONTIGMEM_MANUAL is not set
179# CONFIG_SPARSEMEM_MANUAL is not set
180CONFIG_FLATMEM=y
181CONFIG_FLAT_NODE_MEM_MAP=y
182# CONFIG_SPARSEMEM_STATIC is not set
183CONFIG_PREEMPT_NONE=y
184# CONFIG_PREEMPT_VOLUNTARY is not set
130# CONFIG_PREEMPT is not set 185# CONFIG_PREEMPT is not set
131 186
132# 187#
@@ -138,11 +193,17 @@ CONFIG_MMU=y
138# 193#
139# PCCARD (PCMCIA/CardBus) support 194# PCCARD (PCMCIA/CardBus) support
140# 195#
141# CONFIG_PCCARD is not set 196CONFIG_PCCARD=y
197# CONFIG_PCMCIA_DEBUG is not set
198CONFIG_PCMCIA=y
199CONFIG_PCMCIA_LOAD_CIS=y
200CONFIG_PCMCIA_IOCTL=y
142 201
143# 202#
144# PC-card bridges 203# PC-card bridges
145# 204#
205# CONFIG_I82365 is not set
206# CONFIG_TCIC is not set
146CONFIG_PCMCIA_PROBE=y 207CONFIG_PCMCIA_PROBE=y
147 208
148# 209#
@@ -157,6 +218,78 @@ CONFIG_BINFMT_ELF=y
157CONFIG_TRAD_SIGNALS=y 218CONFIG_TRAD_SIGNALS=y
158 219
159# 220#
221# Networking
222#
223CONFIG_NET=y
224
225#
226# Networking options
227#
228CONFIG_PACKET=y
229CONFIG_PACKET_MMAP=y
230CONFIG_UNIX=y
231CONFIG_XFRM=y
232CONFIG_XFRM_USER=m
233CONFIG_NET_KEY=y
234CONFIG_INET=y
235CONFIG_IP_MULTICAST=y
236# CONFIG_IP_ADVANCED_ROUTER is not set
237CONFIG_IP_FIB_HASH=y
238# CONFIG_IP_PNP is not set
239# CONFIG_NET_IPIP is not set
240# CONFIG_NET_IPGRE is not set
241# CONFIG_IP_MROUTE is not set
242# CONFIG_ARPD is not set
243# CONFIG_SYN_COOKIES is not set
244# CONFIG_INET_AH is not set
245# CONFIG_INET_ESP is not set
246# CONFIG_INET_IPCOMP is not set
247CONFIG_INET_TUNNEL=m
248CONFIG_INET_DIAG=y
249CONFIG_INET_TCP_DIAG=y
250# CONFIG_TCP_CONG_ADVANCED is not set
251CONFIG_TCP_CONG_BIC=y
252# CONFIG_IPV6 is not set
253# CONFIG_NETFILTER is not set
254
255#
256# DCCP Configuration (EXPERIMENTAL)
257#
258# CONFIG_IP_DCCP is not set
259
260#
261# SCTP Configuration (EXPERIMENTAL)
262#
263# CONFIG_IP_SCTP is not set
264# CONFIG_ATM is not set
265# CONFIG_BRIDGE is not set
266# CONFIG_VLAN_8021Q is not set
267# CONFIG_DECNET is not set
268# CONFIG_LLC2 is not set
269# CONFIG_IPX is not set
270# CONFIG_ATALK is not set
271# CONFIG_X25 is not set
272# CONFIG_LAPB is not set
273# CONFIG_NET_DIVERT is not set
274# CONFIG_ECONET is not set
275# CONFIG_WAN_ROUTER is not set
276# CONFIG_NET_SCHED is not set
277# CONFIG_NET_CLS_ROUTE is not set
278
279#
280# Network testing
281#
282# CONFIG_NET_PKTGEN is not set
283# CONFIG_HAMRADIO is not set
284# CONFIG_IRDA is not set
285# CONFIG_BT is not set
286CONFIG_IEEE80211=m
287# CONFIG_IEEE80211_DEBUG is not set
288CONFIG_IEEE80211_CRYPT_WEP=m
289CONFIG_IEEE80211_CRYPT_CCMP=m
290CONFIG_IEEE80211_CRYPT_TKIP=m
291
292#
160# Device Drivers 293# Device Drivers
161# 294#
162 295
@@ -165,7 +298,12 @@ CONFIG_TRAD_SIGNALS=y
165# 298#
166CONFIG_STANDALONE=y 299CONFIG_STANDALONE=y
167CONFIG_PREVENT_FIRMWARE_BUILD=y 300CONFIG_PREVENT_FIRMWARE_BUILD=y
168# CONFIG_FW_LOADER is not set 301CONFIG_FW_LOADER=y
302
303#
304# Connector - unified userspace <-> kernelspace linker
305#
306CONFIG_CONNECTOR=m
169 307
170# 308#
171# Memory Technology Devices (MTD) 309# Memory Technology Devices (MTD)
@@ -185,18 +323,13 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
185# 323#
186# Block devices 324# Block devices
187# 325#
188# CONFIG_BLK_DEV_FD is not set
189# CONFIG_BLK_DEV_XD is not set
190# CONFIG_BLK_DEV_COW_COMMON is not set 326# CONFIG_BLK_DEV_COW_COMMON is not set
191# CONFIG_BLK_DEV_LOOP is not set 327# CONFIG_BLK_DEV_LOOP is not set
192# CONFIG_BLK_DEV_NBD is not set 328# CONFIG_BLK_DEV_NBD is not set
193# CONFIG_BLK_DEV_RAM is not set 329# CONFIG_BLK_DEV_RAM is not set
194CONFIG_BLK_DEV_RAM_COUNT=16 330CONFIG_BLK_DEV_RAM_COUNT=16
195CONFIG_INITRAMFS_SOURCE=""
196# CONFIG_LBD is not set 331# CONFIG_LBD is not set
197CONFIG_CDROM_PKTCDVD=m 332# CONFIG_CDROM_PKTCDVD is not set
198CONFIG_CDROM_PKTCDVD_BUFFERS=8
199# CONFIG_CDROM_PKTCDVD_WCACHE is not set
200 333
201# 334#
202# IO Schedulers 335# IO Schedulers
@@ -219,6 +352,7 @@ CONFIG_BLK_DEV_IDE=y
219# CONFIG_BLK_DEV_IDE_SATA is not set 352# CONFIG_BLK_DEV_IDE_SATA is not set
220CONFIG_BLK_DEV_IDEDISK=y 353CONFIG_BLK_DEV_IDEDISK=y
221# CONFIG_IDEDISK_MULTI_MODE is not set 354# CONFIG_IDEDISK_MULTI_MODE is not set
355CONFIG_BLK_DEV_IDECS=m
222# CONFIG_BLK_DEV_IDECD is not set 356# CONFIG_BLK_DEV_IDECD is not set
223# CONFIG_BLK_DEV_IDETAPE is not set 357# CONFIG_BLK_DEV_IDETAPE is not set
224# CONFIG_BLK_DEV_IDEFLOPPY is not set 358# CONFIG_BLK_DEV_IDEFLOPPY is not set
@@ -237,6 +371,7 @@ CONFIG_IDE_GENERIC=y
237# 371#
238# SCSI device support 372# SCSI device support
239# 373#
374# CONFIG_RAID_ATTRS is not set
240# CONFIG_SCSI is not set 375# CONFIG_SCSI is not set
241 376
242# 377#
@@ -252,6 +387,7 @@ CONFIG_IDE_GENERIC=y
252# 387#
253# Fusion MPT device support 388# Fusion MPT device support
254# 389#
390# CONFIG_FUSION is not set
255 391
256# 392#
257# IEEE 1394 (FireWire) support 393# IEEE 1394 (FireWire) support
@@ -262,76 +398,13 @@ CONFIG_IDE_GENERIC=y
262# 398#
263 399
264# 400#
265# Networking support 401# Network device support
266#
267CONFIG_NET=y
268
269# 402#
270# Networking options
271#
272CONFIG_PACKET=y
273CONFIG_PACKET_MMAP=y
274CONFIG_NETLINK_DEV=y
275CONFIG_UNIX=y
276CONFIG_NET_KEY=y
277CONFIG_INET=y
278CONFIG_IP_MULTICAST=y
279# CONFIG_IP_ADVANCED_ROUTER is not set
280# CONFIG_IP_PNP is not set
281# CONFIG_NET_IPIP is not set
282# CONFIG_NET_IPGRE is not set
283# CONFIG_IP_MROUTE is not set
284# CONFIG_ARPD is not set
285# CONFIG_SYN_COOKIES is not set
286# CONFIG_INET_AH is not set
287# CONFIG_INET_ESP is not set
288# CONFIG_INET_IPCOMP is not set
289CONFIG_INET_TUNNEL=m
290CONFIG_IP_TCPDIAG=m
291# CONFIG_IP_TCPDIAG_IPV6 is not set
292# CONFIG_IPV6 is not set
293# CONFIG_NETFILTER is not set
294CONFIG_XFRM=y
295CONFIG_XFRM_USER=m
296
297#
298# SCTP Configuration (EXPERIMENTAL)
299#
300# CONFIG_IP_SCTP is not set
301# CONFIG_ATM is not set
302# CONFIG_BRIDGE is not set
303# CONFIG_VLAN_8021Q is not set
304# CONFIG_DECNET is not set
305# CONFIG_LLC2 is not set
306# CONFIG_IPX is not set
307# CONFIG_ATALK is not set
308# CONFIG_X25 is not set
309# CONFIG_LAPB is not set
310# CONFIG_NET_DIVERT is not set
311# CONFIG_ECONET is not set
312# CONFIG_WAN_ROUTER is not set
313
314#
315# QoS and/or fair queueing
316#
317# CONFIG_NET_SCHED is not set
318# CONFIG_NET_CLS_ROUTE is not set
319
320#
321# Network testing
322#
323# CONFIG_NET_PKTGEN is not set
324# CONFIG_NETPOLL is not set
325# CONFIG_NET_POLL_CONTROLLER is not set
326# CONFIG_HAMRADIO is not set
327# CONFIG_IRDA is not set
328# CONFIG_BT is not set
329CONFIG_NETDEVICES=y 403CONFIG_NETDEVICES=y
330# CONFIG_DUMMY is not set 404# CONFIG_DUMMY is not set
331# CONFIG_BONDING is not set 405# CONFIG_BONDING is not set
332# CONFIG_EQUALIZER is not set 406# CONFIG_EQUALIZER is not set
333# CONFIG_TUN is not set 407# CONFIG_TUN is not set
334# CONFIG_ETHERTAP is not set
335 408
336# 409#
337# ARCnet devices 410# ARCnet devices
@@ -339,12 +412,26 @@ CONFIG_NETDEVICES=y
339# CONFIG_ARCNET is not set 412# CONFIG_ARCNET is not set
340 413
341# 414#
415# PHY device support
416#
417CONFIG_PHYLIB=m
418CONFIG_PHYCONTROL=y
419
420#
421# MII PHY device drivers
422#
423CONFIG_MARVELL_PHY=m
424CONFIG_DAVICOM_PHY=m
425CONFIG_QSEMI_PHY=m
426CONFIG_LXT_PHY=m
427CONFIG_CICADA_PHY=m
428
429#
342# Ethernet (10 or 100Mbit) 430# Ethernet (10 or 100Mbit)
343# 431#
344CONFIG_NET_ETHERNET=y 432CONFIG_NET_ETHERNET=y
345# CONFIG_MII is not set 433CONFIG_MII=m
346# CONFIG_NET_VENDOR_3COM is not set 434# CONFIG_NET_VENDOR_3COM is not set
347# CONFIG_LANCE is not set
348# CONFIG_NET_VENDOR_SMC is not set 435# CONFIG_NET_VENDOR_SMC is not set
349# CONFIG_NET_VENDOR_RACAL is not set 436# CONFIG_NET_VENDOR_RACAL is not set
350# CONFIG_AT1700 is not set 437# CONFIG_AT1700 is not set
@@ -373,6 +460,19 @@ CONFIG_NET_ETHERNET=y
373# CONFIG_NET_RADIO is not set 460# CONFIG_NET_RADIO is not set
374 461
375# 462#
463# PCMCIA network device support
464#
465CONFIG_NET_PCMCIA=y
466CONFIG_PCMCIA_3C589=m
467CONFIG_PCMCIA_3C574=m
468CONFIG_PCMCIA_FMVJ18X=m
469CONFIG_PCMCIA_PCNET=m
470CONFIG_PCMCIA_NMCLAN=m
471CONFIG_PCMCIA_SMC91C92=m
472CONFIG_PCMCIA_XIRC2PS=m
473CONFIG_PCMCIA_AXNET=m
474
475#
376# Wan interfaces 476# Wan interfaces
377# 477#
378# CONFIG_WAN is not set 478# CONFIG_WAN is not set
@@ -380,6 +480,8 @@ CONFIG_NET_ETHERNET=y
380# CONFIG_SLIP is not set 480# CONFIG_SLIP is not set
381# CONFIG_SHAPER is not set 481# CONFIG_SHAPER is not set
382# CONFIG_NETCONSOLE is not set 482# CONFIG_NETCONSOLE is not set
483# CONFIG_NETPOLL is not set
484# CONFIG_NET_POLL_CONTROLLER is not set
383 485
384# 486#
385# ISDN subsystem 487# ISDN subsystem
@@ -409,18 +511,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
409# CONFIG_INPUT_EVBUG is not set 511# CONFIG_INPUT_EVBUG is not set
410 512
411# 513#
412# Input I/O drivers
413#
414# CONFIG_GAMEPORT is not set
415CONFIG_SOUND_GAMEPORT=y
416CONFIG_SERIO=y
417CONFIG_SERIO_I8042=y
418CONFIG_SERIO_SERPORT=y
419# CONFIG_SERIO_CT82C710 is not set
420# CONFIG_SERIO_LIBPS2 is not set
421CONFIG_SERIO_RAW=m
422
423#
424# Input Device Drivers 514# Input Device Drivers
425# 515#
426# CONFIG_INPUT_KEYBOARD is not set 516# CONFIG_INPUT_KEYBOARD is not set
@@ -430,6 +520,16 @@ CONFIG_SERIO_RAW=m
430# CONFIG_INPUT_MISC is not set 520# CONFIG_INPUT_MISC is not set
431 521
432# 522#
523# Hardware I/O ports
524#
525CONFIG_SERIO=y
526# CONFIG_SERIO_I8042 is not set
527CONFIG_SERIO_SERPORT=y
528# CONFIG_SERIO_LIBPS2 is not set
529CONFIG_SERIO_RAW=m
530# CONFIG_GAMEPORT is not set
531
532#
433# Character devices 533# Character devices
434# 534#
435CONFIG_VT=y 535CONFIG_VT=y
@@ -440,16 +540,15 @@ CONFIG_HW_CONSOLE=y
440# 540#
441# Serial drivers 541# Serial drivers
442# 542#
443CONFIG_SERIAL_8250=y 543# CONFIG_SERIAL_8250 is not set
444CONFIG_SERIAL_8250_CONSOLE=y
445CONFIG_SERIAL_8250_NR_UARTS=4
446# CONFIG_SERIAL_8250_EXTENDED is not set
447 544
448# 545#
449# Non-8250 serial port support 546# Non-8250 serial port support
450# 547#
451CONFIG_SERIAL_CORE=y 548CONFIG_SERIAL_CORE=y
452CONFIG_SERIAL_CORE_CONSOLE=y 549CONFIG_SERIAL_CORE_CONSOLE=y
550CONFIG_SERIAL_VR41XX=y
551CONFIG_SERIAL_VR41XX_CONSOLE=y
453CONFIG_UNIX98_PTYS=y 552CONFIG_UNIX98_PTYS=y
454CONFIG_LEGACY_PTYS=y 553CONFIG_LEGACY_PTYS=y
455CONFIG_LEGACY_PTY_COUNT=256 554CONFIG_LEGACY_PTY_COUNT=256
@@ -484,10 +583,19 @@ CONFIG_WATCHDOG=y
484# 583#
485# Ftape, the floppy tape device driver 584# Ftape, the floppy tape device driver
486# 585#
487# CONFIG_DRM is not set 586
587#
588# PCMCIA character devices
589#
590# CONFIG_SYNCLINK_CS is not set
591# CONFIG_GPIO_VR41XX is not set
488# CONFIG_RAW_DRIVER is not set 592# CONFIG_RAW_DRIVER is not set
489 593
490# 594#
595# TPM devices
596#
597
598#
491# I2C support 599# I2C support
492# 600#
493# CONFIG_I2C is not set 601# CONFIG_I2C is not set
@@ -498,10 +606,20 @@ CONFIG_WATCHDOG=y
498# CONFIG_W1 is not set 606# CONFIG_W1 is not set
499 607
500# 608#
609# Hardware Monitoring support
610#
611# CONFIG_HWMON is not set
612# CONFIG_HWMON_VID is not set
613
614#
501# Misc devices 615# Misc devices
502# 616#
503 617
504# 618#
619# Multimedia Capabilities Port drivers
620#
621
622#
505# Multimedia devices 623# Multimedia devices
506# 624#
507# CONFIG_VIDEO_DEV is not set 625# CONFIG_VIDEO_DEV is not set
@@ -522,7 +640,6 @@ CONFIG_WATCHDOG=y
522# CONFIG_VGA_CONSOLE is not set 640# CONFIG_VGA_CONSOLE is not set
523# CONFIG_MDA_CONSOLE is not set 641# CONFIG_MDA_CONSOLE is not set
524CONFIG_DUMMY_CONSOLE=y 642CONFIG_DUMMY_CONSOLE=y
525# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
526 643
527# 644#
528# Sound 645# Sound
@@ -536,10 +653,6 @@ CONFIG_DUMMY_CONSOLE=y
536# CONFIG_USB_ARCH_HAS_OHCI is not set 653# CONFIG_USB_ARCH_HAS_OHCI is not set
537 654
538# 655#
539# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
540#
541
542#
543# USB Gadget Support 656# USB Gadget Support
544# 657#
545# CONFIG_USB_GADGET is not set 658# CONFIG_USB_GADGET is not set
@@ -552,7 +665,10 @@ CONFIG_DUMMY_CONSOLE=y
552# 665#
553# InfiniBand support 666# InfiniBand support
554# 667#
555# CONFIG_INFINIBAND is not set 668
669#
670# SN Devices
671#
556 672
557# 673#
558# File systems 674# File systems
@@ -561,6 +677,7 @@ CONFIG_EXT2_FS=y
561CONFIG_EXT2_FS_XATTR=y 677CONFIG_EXT2_FS_XATTR=y
562CONFIG_EXT2_FS_POSIX_ACL=y 678CONFIG_EXT2_FS_POSIX_ACL=y
563CONFIG_EXT2_FS_SECURITY=y 679CONFIG_EXT2_FS_SECURITY=y
680# CONFIG_EXT2_FS_XIP is not set
564# CONFIG_EXT3_FS is not set 681# CONFIG_EXT3_FS is not set
565# CONFIG_JBD is not set 682# CONFIG_JBD is not set
566CONFIG_FS_MBCACHE=y 683CONFIG_FS_MBCACHE=y
@@ -570,10 +687,12 @@ CONFIG_FS_POSIX_ACL=y
570# CONFIG_XFS_FS is not set 687# CONFIG_XFS_FS is not set
571# CONFIG_MINIX_FS is not set 688# CONFIG_MINIX_FS is not set
572# CONFIG_ROMFS_FS is not set 689# CONFIG_ROMFS_FS is not set
690CONFIG_INOTIFY=y
573# CONFIG_QUOTA is not set 691# CONFIG_QUOTA is not set
574CONFIG_DNOTIFY=y 692CONFIG_DNOTIFY=y
575CONFIG_AUTOFS_FS=y 693CONFIG_AUTOFS_FS=y
576CONFIG_AUTOFS4_FS=y 694CONFIG_AUTOFS4_FS=y
695CONFIG_FUSE_FS=m
577 696
578# 697#
579# CD-ROM/DVD Filesystems 698# CD-ROM/DVD Filesystems
@@ -594,12 +713,10 @@ CONFIG_AUTOFS4_FS=y
594CONFIG_PROC_FS=y 713CONFIG_PROC_FS=y
595CONFIG_PROC_KCORE=y 714CONFIG_PROC_KCORE=y
596CONFIG_SYSFS=y 715CONFIG_SYSFS=y
597# CONFIG_DEVFS_FS is not set
598CONFIG_DEVPTS_FS_XATTR=y
599CONFIG_DEVPTS_FS_SECURITY=y
600# CONFIG_TMPFS is not set 716# CONFIG_TMPFS is not set
601# CONFIG_HUGETLB_PAGE is not set 717# CONFIG_HUGETLB_PAGE is not set
602CONFIG_RAMFS=y 718CONFIG_RAMFS=y
719CONFIG_RELAYFS_FS=m
603 720
604# 721#
605# Miscellaneous filesystems 722# Miscellaneous filesystems
@@ -630,6 +747,7 @@ CONFIG_NFSD=y
630# CONFIG_NFSD_TCP is not set 747# CONFIG_NFSD_TCP is not set
631CONFIG_LOCKD=y 748CONFIG_LOCKD=y
632CONFIG_EXPORTFS=y 749CONFIG_EXPORTFS=y
750CONFIG_NFS_COMMON=y
633CONFIG_SUNRPC=y 751CONFIG_SUNRPC=y
634# CONFIG_RPCSEC_GSS_KRB5 is not set 752# CONFIG_RPCSEC_GSS_KRB5 is not set
635# CONFIG_RPCSEC_GSS_SPKM3 is not set 753# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -638,6 +756,7 @@ CONFIG_SUNRPC=y
638# CONFIG_NCP_FS is not set 756# CONFIG_NCP_FS is not set
639# CONFIG_CODA_FS is not set 757# CONFIG_CODA_FS is not set
640# CONFIG_AFS_FS is not set 758# CONFIG_AFS_FS is not set
759# CONFIG_9P_FS is not set
641 760
642# 761#
643# Partition Types 762# Partition Types
@@ -658,9 +777,11 @@ CONFIG_MSDOS_PARTITION=y
658# 777#
659# Kernel hacking 778# Kernel hacking
660# 779#
780# CONFIG_PRINTK_TIME is not set
661# CONFIG_DEBUG_KERNEL is not set 781# CONFIG_DEBUG_KERNEL is not set
782CONFIG_LOG_BUF_SHIFT=14
662CONFIG_CROSSCOMPILE=y 783CONFIG_CROSSCOMPILE=y
663CONFIG_CMDLINE="" 784CONFIG_CMDLINE="console=ttyVR0,19200 mem=16M"
664 785
665# 786#
666# Security options 787# Security options
@@ -672,7 +793,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
672# 793#
673# Cryptographic options 794# Cryptographic options
674# 795#
675# CONFIG_CRYPTO is not set 796CONFIG_CRYPTO=y
797CONFIG_CRYPTO_HMAC=y
798CONFIG_CRYPTO_NULL=m
799CONFIG_CRYPTO_MD4=m
800CONFIG_CRYPTO_MD5=m
801CONFIG_CRYPTO_SHA1=m
802CONFIG_CRYPTO_SHA256=m
803CONFIG_CRYPTO_SHA512=m
804CONFIG_CRYPTO_WP512=m
805CONFIG_CRYPTO_TGR192=m
806CONFIG_CRYPTO_DES=m
807CONFIG_CRYPTO_BLOWFISH=m
808CONFIG_CRYPTO_TWOFISH=m
809CONFIG_CRYPTO_SERPENT=m
810CONFIG_CRYPTO_AES=m
811CONFIG_CRYPTO_CAST5=m
812CONFIG_CRYPTO_CAST6=m
813CONFIG_CRYPTO_TEA=m
814CONFIG_CRYPTO_ARC4=m
815CONFIG_CRYPTO_KHAZAD=m
816CONFIG_CRYPTO_ANUBIS=m
817CONFIG_CRYPTO_DEFLATE=m
818CONFIG_CRYPTO_MICHAEL_MIC=m
819CONFIG_CRYPTO_CRC32C=m
820# CONFIG_CRYPTO_TEST is not set
676 821
677# 822#
678# Hardware crypto devices 823# Hardware crypto devices
@@ -682,7 +827,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
682# Library routines 827# Library routines
683# 828#
684# CONFIG_CRC_CCITT is not set 829# CONFIG_CRC_CCITT is not set
685# CONFIG_CRC32 is not set 830CONFIG_CRC16=m
686# CONFIG_LIBCRC32C is not set 831CONFIG_CRC32=y
687CONFIG_GENERIC_HARDIRQS=y 832CONFIG_LIBCRC32C=m
688CONFIG_GENERIC_IRQ_PROBE=y 833CONFIG_ZLIB_INFLATE=m
834CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 6d2290777ad7..5b0b7f30e205 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:49:13 2005 4# Thu Oct 20 22:27:18 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,25 +11,31 @@ CONFIG_32BIT=y
14# CONFIG_EXPERIMENTAL is not set 11# CONFIG_EXPERIMENTAL is not set
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_LOCK_KERNEL=y 13CONFIG_LOCK_KERNEL=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_BSD_PROCESS_ACCT is not set 23# CONFIG_BSD_PROCESS_ACCT is not set
25CONFIG_SYSCTL=y 24CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set 25# CONFIG_AUDIT is not set
27CONFIG_LOG_BUF_SHIFT=14 26CONFIG_HOTPLUG=y
28# CONFIG_HOTPLUG is not set
29CONFIG_KOBJECT_UEVENT=y 27CONFIG_KOBJECT_UEVENT=y
30CONFIG_IKCONFIG=y 28CONFIG_IKCONFIG=y
31CONFIG_IKCONFIG_PROC=y 29CONFIG_IKCONFIG_PROC=y
30# CONFIG_CPUSETS is not set
31CONFIG_INITRAMFS_SOURCE=""
32CONFIG_EMBEDDED=y 32CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 33CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_ALL is not set 34# CONFIG_KALLSYMS_ALL is not set
35# CONFIG_KALLSYMS_EXTRA_PASS is not set 35# CONFIG_KALLSYMS_EXTRA_PASS is not set
36CONFIG_PRINTK=y
37CONFIG_BUG=y
38CONFIG_BASE_FULL=y
36CONFIG_FUTEX=y 39CONFIG_FUTEX=y
37CONFIG_EPOLL=y 40CONFIG_EPOLL=y
38# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 41# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -42,6 +45,7 @@ CONFIG_CC_ALIGN_LABELS=0
42CONFIG_CC_ALIGN_LOOPS=0 45CONFIG_CC_ALIGN_LOOPS=0
43CONFIG_CC_ALIGN_JUMPS=0 46CONFIG_CC_ALIGN_JUMPS=0
44# CONFIG_TINY_SHMEM is not set 47# CONFIG_TINY_SHMEM is not set
48CONFIG_BASE_SMALL=0
45 49
46# 50#
47# Loadable module support 51# Loadable module support
@@ -56,34 +60,68 @@ CONFIG_STOP_MACHINE=y
56# 60#
57# Machine selection 61# Machine selection
58# 62#
59# CONFIG_MACH_JAZZ is not set 63# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 64# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 65# CONFIG_MIPS_PB1000 is not set
66# CONFIG_MIPS_PB1100 is not set
67# CONFIG_MIPS_PB1500 is not set
68# CONFIG_MIPS_PB1550 is not set
69# CONFIG_MIPS_PB1200 is not set
70# CONFIG_MIPS_DB1000 is not set
71# CONFIG_MIPS_DB1100 is not set
72# CONFIG_MIPS_DB1500 is not set
73# CONFIG_MIPS_DB1550 is not set
74# CONFIG_MIPS_DB1200 is not set
75# CONFIG_MIPS_MIRAGE is not set
76# CONFIG_MIPS_COBALT is not set
62# CONFIG_MACH_DECSTATION is not set 77# CONFIG_MACH_DECSTATION is not set
78# CONFIG_MIPS_EV64120 is not set
79# CONFIG_MIPS_EV96100 is not set
63# CONFIG_MIPS_IVR is not set 80# CONFIG_MIPS_IVR is not set
64# CONFIG_LASAT is not set
65# CONFIG_MIPS_ITE8172 is not set 81# CONFIG_MIPS_ITE8172 is not set
82# CONFIG_MACH_JAZZ is not set
83# CONFIG_LASAT is not set
66# CONFIG_MIPS_ATLAS is not set 84# CONFIG_MIPS_ATLAS is not set
67# CONFIG_MIPS_MALTA is not set 85# CONFIG_MIPS_MALTA is not set
86# CONFIG_MIPS_SEAD is not set
87# CONFIG_MIPS_SIM is not set
88# CONFIG_MOMENCO_JAGUAR_ATX is not set
68# CONFIG_MOMENCO_OCELOT is not set 89# CONFIG_MOMENCO_OCELOT is not set
69# CONFIG_MOMENCO_OCELOT_G is not set
70# CONFIG_MOMENCO_OCELOT_C is not set
71# CONFIG_MOMENCO_OCELOT_3 is not set 90# CONFIG_MOMENCO_OCELOT_3 is not set
72# CONFIG_MOMENCO_JAGUAR_ATX is not set 91# CONFIG_MOMENCO_OCELOT_C is not set
73CONFIG_PMC_YOSEMITE=y 92# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_HYPERTRANSPORT is not set 93# CONFIG_MIPS_XXS1500 is not set
94# CONFIG_PNX8550_V2PCI is not set
95# CONFIG_PNX8550_JBS is not set
96# CONFIG_DDB5074 is not set
75# CONFIG_DDB5476 is not set 97# CONFIG_DDB5476 is not set
76# CONFIG_DDB5477 is not set 98# CONFIG_DDB5477 is not set
77# CONFIG_NEC_OSPREY is not set 99# CONFIG_MACH_VR41XX is not set
100CONFIG_PMC_YOSEMITE=y
101# CONFIG_QEMU is not set
78# CONFIG_SGI_IP22 is not set 102# CONFIG_SGI_IP22 is not set
79# CONFIG_SOC_AU1X00 is not set 103# CONFIG_SGI_IP27 is not set
104# CONFIG_SGI_IP32 is not set
105# CONFIG_SIBYTE_BIGSUR is not set
106# CONFIG_SIBYTE_SWARM is not set
107# CONFIG_SIBYTE_SENTOSA is not set
108# CONFIG_SIBYTE_RHONE is not set
109# CONFIG_SIBYTE_CARMEL is not set
110# CONFIG_SIBYTE_PTSWARM is not set
111# CONFIG_SIBYTE_LITTLESUR is not set
112# CONFIG_SIBYTE_CRHINE is not set
113# CONFIG_SIBYTE_CRHONE is not set
80# CONFIG_SNI_RM200_PCI is not set 114# CONFIG_SNI_RM200_PCI is not set
115# CONFIG_TOSHIBA_JMR3927 is not set
81# CONFIG_TOSHIBA_RBTX4927 is not set 116# CONFIG_TOSHIBA_RBTX4927 is not set
117# CONFIG_TOSHIBA_RBTX4938 is not set
118# CONFIG_HYPERTRANSPORT is not set
82CONFIG_RWSEM_GENERIC_SPINLOCK=y 119CONFIG_RWSEM_GENERIC_SPINLOCK=y
83CONFIG_GENERIC_CALIBRATE_DELAY=y 120CONFIG_GENERIC_CALIBRATE_DELAY=y
84CONFIG_HAVE_DEC_LOCK=y
85CONFIG_DMA_COHERENT=y 121CONFIG_DMA_COHERENT=y
122CONFIG_CPU_BIG_ENDIAN=y
86# CONFIG_CPU_LITTLE_ENDIAN is not set 123# CONFIG_CPU_LITTLE_ENDIAN is not set
124CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
87CONFIG_IRQ_CPU=y 125CONFIG_IRQ_CPU=y
88CONFIG_IRQ_CPU_RM7K=y 126CONFIG_IRQ_CPU_RM7K=y
89CONFIG_IRQ_CPU_RM9K=y 127CONFIG_IRQ_CPU_RM9K=y
@@ -93,8 +131,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
93# 131#
94# CPU selection 132# CPU selection
95# 133#
96# CONFIG_CPU_MIPS32 is not set 134# CONFIG_CPU_MIPS32_R1 is not set
97# CONFIG_CPU_MIPS64 is not set 135# CONFIG_CPU_MIPS32_R2 is not set
136# CONFIG_CPU_MIPS64_R1 is not set
137# CONFIG_CPU_MIPS64_R2 is not set
98# CONFIG_CPU_R3000 is not set 138# CONFIG_CPU_R3000 is not set
99# CONFIG_CPU_TX39XX is not set 139# CONFIG_CPU_TX39XX is not set
100# CONFIG_CPU_VR41XX is not set 140# CONFIG_CPU_VR41XX is not set
@@ -110,20 +150,43 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
110# CONFIG_CPU_RM7000 is not set 150# CONFIG_CPU_RM7000 is not set
111CONFIG_CPU_RM9000=y 151CONFIG_CPU_RM9000=y
112# CONFIG_CPU_SB1 is not set 152# CONFIG_CPU_SB1 is not set
153CONFIG_SYS_HAS_CPU_RM9000=y
154CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
155CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
156CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
157CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
158
159#
160# Kernel type
161#
162CONFIG_32BIT=y
163# CONFIG_64BIT is not set
113CONFIG_PAGE_SIZE_4KB=y 164CONFIG_PAGE_SIZE_4KB=y
114# CONFIG_PAGE_SIZE_8KB is not set 165# CONFIG_PAGE_SIZE_8KB is not set
115# CONFIG_PAGE_SIZE_16KB is not set 166# CONFIG_PAGE_SIZE_16KB is not set
116# CONFIG_PAGE_SIZE_64KB is not set 167# CONFIG_PAGE_SIZE_64KB is not set
117CONFIG_CPU_HAS_PREFETCH=y 168CONFIG_CPU_HAS_PREFETCH=y
169# CONFIG_MIPS_MT is not set
118# CONFIG_64BIT_PHYS_ADDR is not set 170# CONFIG_64BIT_PHYS_ADDR is not set
119# CONFIG_CPU_ADVANCED is not set 171# CONFIG_CPU_ADVANCED is not set
120CONFIG_CPU_HAS_LLSC=y 172CONFIG_CPU_HAS_LLSC=y
121CONFIG_CPU_HAS_LLDSCD=y 173CONFIG_CPU_HAS_LLDSCD=y
122CONFIG_CPU_HAS_SYNC=y 174CONFIG_CPU_HAS_SYNC=y
175CONFIG_GENERIC_HARDIRQS=y
176CONFIG_GENERIC_IRQ_PROBE=y
123CONFIG_HIGHMEM=y 177CONFIG_HIGHMEM=y
178CONFIG_CPU_SUPPORTS_HIGHMEM=y
179CONFIG_SYS_SUPPORTS_HIGHMEM=y
180CONFIG_ARCH_FLATMEM_ENABLE=y
181CONFIG_FLATMEM=y
182CONFIG_FLAT_NODE_MEM_MAP=y
183# CONFIG_SPARSEMEM_STATIC is not set
124CONFIG_SMP=y 184CONFIG_SMP=y
125CONFIG_NR_CPUS=2 185CONFIG_NR_CPUS=2
186CONFIG_PREEMPT_NONE=y
187# CONFIG_PREEMPT_VOLUNTARY is not set
126# CONFIG_PREEMPT is not set 188# CONFIG_PREEMPT is not set
189CONFIG_PREEMPT_BKL=y
127 190
128# 191#
129# Bus options (PCI, PCMCIA, EISA, ISA, TC) 192# Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -131,7 +194,7 @@ CONFIG_NR_CPUS=2
131CONFIG_HW_HAS_PCI=y 194CONFIG_HW_HAS_PCI=y
132CONFIG_PCI=y 195CONFIG_PCI=y
133CONFIG_PCI_LEGACY_PROC=y 196CONFIG_PCI_LEGACY_PROC=y
134CONFIG_PCI_NAMES=y 197# CONFIG_PCI_DEBUG is not set
135CONFIG_MMU=y 198CONFIG_MMU=y
136 199
137# 200#
@@ -140,10 +203,6 @@ CONFIG_MMU=y
140# CONFIG_PCCARD is not set 203# CONFIG_PCCARD is not set
141 204
142# 205#
143# PC-card bridges
144#
145
146#
147# PCI Hotplug Support 206# PCI Hotplug Support
148# 207#
149 208
@@ -155,6 +214,69 @@ CONFIG_BINFMT_ELF=y
155CONFIG_TRAD_SIGNALS=y 214CONFIG_TRAD_SIGNALS=y
156 215
157# 216#
217# Networking
218#
219CONFIG_NET=y
220
221#
222# Networking options
223#
224CONFIG_PACKET=m
225CONFIG_PACKET_MMAP=y
226CONFIG_UNIX=y
227CONFIG_XFRM=y
228CONFIG_XFRM_USER=m
229# CONFIG_NET_KEY is not set
230CONFIG_INET=y
231# CONFIG_IP_MULTICAST is not set
232# CONFIG_IP_ADVANCED_ROUTER is not set
233CONFIG_IP_FIB_HASH=y
234CONFIG_IP_PNP=y
235# CONFIG_IP_PNP_DHCP is not set
236CONFIG_IP_PNP_BOOTP=y
237# CONFIG_IP_PNP_RARP is not set
238# CONFIG_NET_IPIP is not set
239# CONFIG_NET_IPGRE is not set
240# CONFIG_SYN_COOKIES is not set
241# CONFIG_INET_AH is not set
242# CONFIG_INET_ESP is not set
243# CONFIG_INET_IPCOMP is not set
244CONFIG_INET_TUNNEL=m
245CONFIG_INET_DIAG=y
246CONFIG_INET_TCP_DIAG=y
247# CONFIG_TCP_CONG_ADVANCED is not set
248CONFIG_TCP_CONG_BIC=y
249CONFIG_IPV6=m
250CONFIG_IPV6_PRIVACY=y
251CONFIG_INET6_AH=m
252CONFIG_INET6_ESP=m
253CONFIG_INET6_IPCOMP=m
254CONFIG_INET6_TUNNEL=m
255CONFIG_IPV6_TUNNEL=m
256# CONFIG_NETFILTER is not set
257# CONFIG_BRIDGE is not set
258# CONFIG_VLAN_8021Q is not set
259# CONFIG_DECNET is not set
260# CONFIG_LLC2 is not set
261# CONFIG_IPX is not set
262# CONFIG_ATALK is not set
263# CONFIG_NET_SCHED is not set
264# CONFIG_NET_CLS_ROUTE is not set
265
266#
267# Network testing
268#
269# CONFIG_NET_PKTGEN is not set
270# CONFIG_HAMRADIO is not set
271# CONFIG_IRDA is not set
272# CONFIG_BT is not set
273CONFIG_IEEE80211=m
274# CONFIG_IEEE80211_DEBUG is not set
275CONFIG_IEEE80211_CRYPT_WEP=m
276CONFIG_IEEE80211_CRYPT_CCMP=m
277CONFIG_IEEE80211_CRYPT_TKIP=m
278
279#
158# Device Drivers 280# Device Drivers
159# 281#
160 282
@@ -163,10 +285,15 @@ CONFIG_TRAD_SIGNALS=y
163# 285#
164CONFIG_STANDALONE=y 286CONFIG_STANDALONE=y
165CONFIG_PREVENT_FIRMWARE_BUILD=y 287CONFIG_PREVENT_FIRMWARE_BUILD=y
166# CONFIG_FW_LOADER is not set 288CONFIG_FW_LOADER=m
167# CONFIG_DEBUG_DRIVER is not set 289# CONFIG_DEBUG_DRIVER is not set
168 290
169# 291#
292# Connector - unified userspace <-> kernelspace linker
293#
294CONFIG_CONNECTOR=m
295
296#
170# Memory Technology Devices (MTD) 297# Memory Technology Devices (MTD)
171# 298#
172# CONFIG_MTD is not set 299# CONFIG_MTD is not set
@@ -183,7 +310,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
183# 310#
184# Block devices 311# Block devices
185# 312#
186# CONFIG_BLK_DEV_FD is not set
187# CONFIG_BLK_CPQ_DA is not set 313# CONFIG_BLK_CPQ_DA is not set
188# CONFIG_BLK_CPQ_CISS_DA is not set 314# CONFIG_BLK_CPQ_CISS_DA is not set
189# CONFIG_BLK_DEV_DAC960 is not set 315# CONFIG_BLK_DEV_DAC960 is not set
@@ -193,7 +319,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
193# CONFIG_BLK_DEV_SX8 is not set 319# CONFIG_BLK_DEV_SX8 is not set
194# CONFIG_BLK_DEV_RAM is not set 320# CONFIG_BLK_DEV_RAM is not set
195CONFIG_BLK_DEV_RAM_COUNT=16 321CONFIG_BLK_DEV_RAM_COUNT=16
196CONFIG_INITRAMFS_SOURCE=""
197# CONFIG_LBD is not set 322# CONFIG_LBD is not set
198CONFIG_CDROM_PKTCDVD=m 323CONFIG_CDROM_PKTCDVD=m
199CONFIG_CDROM_PKTCDVD_BUFFERS=8 324CONFIG_CDROM_PKTCDVD_BUFFERS=8
@@ -216,6 +341,7 @@ CONFIG_ATA_OVER_ETH=m
216# 341#
217# SCSI device support 342# SCSI device support
218# 343#
344CONFIG_RAID_ATTRS=m
219# CONFIG_SCSI is not set 345# CONFIG_SCSI is not set
220 346
221# 347#
@@ -226,6 +352,7 @@ CONFIG_ATA_OVER_ETH=m
226# 352#
227# Fusion MPT device support 353# Fusion MPT device support
228# 354#
355# CONFIG_FUSION is not set
229 356
230# 357#
231# IEEE 1394 (FireWire) support 358# IEEE 1394 (FireWire) support
@@ -238,59 +365,8 @@ CONFIG_ATA_OVER_ETH=m
238# CONFIG_I2O is not set 365# CONFIG_I2O is not set
239 366
240# 367#
241# Networking support 368# Network device support
242# 369#
243CONFIG_NET=y
244
245#
246# Networking options
247#
248CONFIG_PACKET=m
249CONFIG_PACKET_MMAP=y
250CONFIG_NETLINK_DEV=m
251CONFIG_UNIX=y
252# CONFIG_NET_KEY is not set
253CONFIG_INET=y
254# CONFIG_IP_MULTICAST is not set
255# CONFIG_IP_ADVANCED_ROUTER is not set
256CONFIG_IP_PNP=y
257# CONFIG_IP_PNP_DHCP is not set
258CONFIG_IP_PNP_BOOTP=y
259# CONFIG_IP_PNP_RARP is not set
260# CONFIG_NET_IPIP is not set
261# CONFIG_NET_IPGRE is not set
262# CONFIG_SYN_COOKIES is not set
263# CONFIG_INET_AH is not set
264# CONFIG_INET_ESP is not set
265# CONFIG_INET_IPCOMP is not set
266CONFIG_INET_TUNNEL=m
267CONFIG_IP_TCPDIAG=m
268# CONFIG_IP_TCPDIAG_IPV6 is not set
269# CONFIG_NETFILTER is not set
270CONFIG_XFRM=y
271CONFIG_XFRM_USER=m
272# CONFIG_BRIDGE is not set
273# CONFIG_VLAN_8021Q is not set
274# CONFIG_DECNET is not set
275# CONFIG_LLC2 is not set
276# CONFIG_IPX is not set
277# CONFIG_ATALK is not set
278
279#
280# QoS and/or fair queueing
281#
282# CONFIG_NET_SCHED is not set
283# CONFIG_NET_CLS_ROUTE is not set
284
285#
286# Network testing
287#
288# CONFIG_NET_PKTGEN is not set
289# CONFIG_NETPOLL is not set
290# CONFIG_NET_POLL_CONTROLLER is not set
291# CONFIG_HAMRADIO is not set
292# CONFIG_IRDA is not set
293# CONFIG_BT is not set
294CONFIG_NETDEVICES=y 370CONFIG_NETDEVICES=y
295# CONFIG_DUMMY is not set 371# CONFIG_DUMMY is not set
296# CONFIG_BONDING is not set 372# CONFIG_BONDING is not set
@@ -303,6 +379,21 @@ CONFIG_NETDEVICES=y
303# CONFIG_ARCNET is not set 379# CONFIG_ARCNET is not set
304 380
305# 381#
382# PHY device support
383#
384CONFIG_PHYLIB=m
385CONFIG_PHYCONTROL=y
386
387#
388# MII PHY device drivers
389#
390CONFIG_MARVELL_PHY=m
391CONFIG_DAVICOM_PHY=m
392CONFIG_QSEMI_PHY=m
393CONFIG_LXT_PHY=m
394CONFIG_CICADA_PHY=m
395
396#
306# Ethernet (10 or 100Mbit) 397# Ethernet (10 or 100Mbit)
307# 398#
308CONFIG_NET_ETHERNET=y 399CONFIG_NET_ETHERNET=y
@@ -327,13 +418,16 @@ CONFIG_MII=y
327# CONFIG_NS83820 is not set 418# CONFIG_NS83820 is not set
328# CONFIG_HAMACHI is not set 419# CONFIG_HAMACHI is not set
329# CONFIG_R8169 is not set 420# CONFIG_R8169 is not set
421# CONFIG_SIS190 is not set
330# CONFIG_SK98LIN is not set 422# CONFIG_SK98LIN is not set
331# CONFIG_TIGON3 is not set 423# CONFIG_TIGON3 is not set
424# CONFIG_BNX2 is not set
332CONFIG_TITAN_GE=y 425CONFIG_TITAN_GE=y
333 426
334# 427#
335# Ethernet (10000 Mbit) 428# Ethernet (10000 Mbit)
336# 429#
430# CONFIG_CHELSIO_T1 is not set
337# CONFIG_IXGB is not set 431# CONFIG_IXGB is not set
338# CONFIG_S2IO is not set 432# CONFIG_S2IO is not set
339 433
@@ -346,6 +440,8 @@ CONFIG_TITAN_GE=y
346# Wireless LAN (non-hamradio) 440# Wireless LAN (non-hamradio)
347# 441#
348# CONFIG_NET_RADIO is not set 442# CONFIG_NET_RADIO is not set
443# CONFIG_IPW_DEBUG is not set
444CONFIG_IPW2200=m
349 445
350# 446#
351# Wan interfaces 447# Wan interfaces
@@ -354,6 +450,8 @@ CONFIG_TITAN_GE=y
354# CONFIG_FDDI is not set 450# CONFIG_FDDI is not set
355# CONFIG_PPP is not set 451# CONFIG_PPP is not set
356# CONFIG_SLIP is not set 452# CONFIG_SLIP is not set
453# CONFIG_NETPOLL is not set
454# CONFIG_NET_POLL_CONTROLLER is not set
357 455
358# 456#
359# ISDN subsystem 457# ISDN subsystem
@@ -371,20 +469,10 @@ CONFIG_TITAN_GE=y
371# CONFIG_INPUT is not set 469# CONFIG_INPUT is not set
372 470
373# 471#
374# Userland interfaces 472# Hardware I/O ports
375#
376
377#
378# Input I/O drivers
379# 473#
380# CONFIG_GAMEPORT is not set
381CONFIG_SOUND_GAMEPORT=y
382# CONFIG_SERIO is not set 474# CONFIG_SERIO is not set
383# CONFIG_SERIO_I8042 is not set 475# CONFIG_GAMEPORT is not set
384
385#
386# Input Device Drivers
387#
388 476
389# 477#
390# Character devices 478# Character devices
@@ -405,6 +493,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
405# 493#
406CONFIG_SERIAL_CORE=y 494CONFIG_SERIAL_CORE=y
407CONFIG_SERIAL_CORE_CONSOLE=y 495CONFIG_SERIAL_CORE_CONSOLE=y
496# CONFIG_SERIAL_JSM is not set
408CONFIG_UNIX98_PTYS=y 497CONFIG_UNIX98_PTYS=y
409CONFIG_LEGACY_PTYS=y 498CONFIG_LEGACY_PTYS=y
410CONFIG_LEGACY_PTY_COUNT=256 499CONFIG_LEGACY_PTY_COUNT=256
@@ -432,6 +521,10 @@ CONFIG_GEN_RTC_X=y
432# CONFIG_RAW_DRIVER is not set 521# CONFIG_RAW_DRIVER is not set
433 522
434# 523#
524# TPM devices
525#
526
527#
435# I2C support 528# I2C support
436# 529#
437# CONFIG_I2C is not set 530# CONFIG_I2C is not set
@@ -442,10 +535,20 @@ CONFIG_GEN_RTC_X=y
442# CONFIG_W1 is not set 535# CONFIG_W1 is not set
443 536
444# 537#
538# Hardware Monitoring support
539#
540# CONFIG_HWMON is not set
541# CONFIG_HWMON_VID is not set
542
543#
445# Misc devices 544# Misc devices
446# 545#
447 546
448# 547#
548# Multimedia Capabilities Port drivers
549#
550
551#
449# Multimedia devices 552# Multimedia devices
450# 553#
451# CONFIG_VIDEO_DEV is not set 554# CONFIG_VIDEO_DEV is not set
@@ -459,7 +562,6 @@ CONFIG_GEN_RTC_X=y
459# Graphics support 562# Graphics support
460# 563#
461# CONFIG_FB is not set 564# CONFIG_FB is not set
462# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
463 565
464# 566#
465# Sound 567# Sound
@@ -469,13 +571,9 @@ CONFIG_GEN_RTC_X=y
469# 571#
470# USB support 572# USB support
471# 573#
472# CONFIG_USB is not set
473CONFIG_USB_ARCH_HAS_HCD=y 574CONFIG_USB_ARCH_HAS_HCD=y
474CONFIG_USB_ARCH_HAS_OHCI=y 575CONFIG_USB_ARCH_HAS_OHCI=y
475 576# CONFIG_USB is not set
476#
477# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
478#
479 577
480# 578#
481# USB Gadget Support 579# USB Gadget Support
@@ -493,6 +591,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y
493# CONFIG_INFINIBAND is not set 591# CONFIG_INFINIBAND is not set
494 592
495# 593#
594# SN Devices
595#
596
597#
496# File systems 598# File systems
497# 599#
498# CONFIG_EXT2_FS is not set 600# CONFIG_EXT2_FS is not set
@@ -500,13 +602,16 @@ CONFIG_USB_ARCH_HAS_OHCI=y
500# CONFIG_JBD is not set 602# CONFIG_JBD is not set
501# CONFIG_REISERFS_FS is not set 603# CONFIG_REISERFS_FS is not set
502# CONFIG_JFS_FS is not set 604# CONFIG_JFS_FS is not set
605# CONFIG_FS_POSIX_ACL is not set
503# CONFIG_XFS_FS is not set 606# CONFIG_XFS_FS is not set
504# CONFIG_MINIX_FS is not set 607# CONFIG_MINIX_FS is not set
505# CONFIG_ROMFS_FS is not set 608# CONFIG_ROMFS_FS is not set
609CONFIG_INOTIFY=y
506# CONFIG_QUOTA is not set 610# CONFIG_QUOTA is not set
507CONFIG_DNOTIFY=y 611CONFIG_DNOTIFY=y
508# CONFIG_AUTOFS_FS is not set 612# CONFIG_AUTOFS_FS is not set
509# CONFIG_AUTOFS4_FS is not set 613# CONFIG_AUTOFS4_FS is not set
614CONFIG_FUSE_FS=m
510 615
511# 616#
512# CD-ROM/DVD Filesystems 617# CD-ROM/DVD Filesystems
@@ -527,11 +632,10 @@ CONFIG_DNOTIFY=y
527CONFIG_PROC_FS=y 632CONFIG_PROC_FS=y
528CONFIG_PROC_KCORE=y 633CONFIG_PROC_KCORE=y
529CONFIG_SYSFS=y 634CONFIG_SYSFS=y
530# CONFIG_DEVPTS_FS_XATTR is not set
531CONFIG_TMPFS=y 635CONFIG_TMPFS=y
532# CONFIG_TMPFS_XATTR is not set
533# CONFIG_HUGETLB_PAGE is not set 636# CONFIG_HUGETLB_PAGE is not set
534CONFIG_RAMFS=y 637CONFIG_RAMFS=y
638CONFIG_RELAYFS_FS=m
535 639
536# 640#
537# Miscellaneous filesystems 641# Miscellaneous filesystems
@@ -552,7 +656,7 @@ CONFIG_NFS_FS=y
552# CONFIG_NFSD is not set 656# CONFIG_NFSD is not set
553CONFIG_ROOT_NFS=y 657CONFIG_ROOT_NFS=y
554CONFIG_LOCKD=y 658CONFIG_LOCKD=y
555# CONFIG_EXPORTFS is not set 659CONFIG_NFS_COMMON=y
556CONFIG_SUNRPC=y 660CONFIG_SUNRPC=y
557# CONFIG_SMB_FS is not set 661# CONFIG_SMB_FS is not set
558# CONFIG_CIFS is not set 662# CONFIG_CIFS is not set
@@ -573,8 +677,11 @@ CONFIG_MSDOS_PARTITION=y
573# 677#
574# Kernel hacking 678# Kernel hacking
575# 679#
680# CONFIG_PRINTK_TIME is not set
576CONFIG_DEBUG_KERNEL=y 681CONFIG_DEBUG_KERNEL=y
577# CONFIG_MAGIC_SYSRQ is not set 682# CONFIG_MAGIC_SYSRQ is not set
683CONFIG_LOG_BUF_SHIFT=14
684CONFIG_DETECT_SOFTLOCKUP=y
578# CONFIG_SCHEDSTATS is not set 685# CONFIG_SCHEDSTATS is not set
579# CONFIG_DEBUG_SLAB is not set 686# CONFIG_DEBUG_SLAB is not set
580# CONFIG_DEBUG_SPINLOCK is not set 687# CONFIG_DEBUG_SPINLOCK is not set
@@ -599,7 +706,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
599# 706#
600# Cryptographic options 707# Cryptographic options
601# 708#
602# CONFIG_CRYPTO is not set 709CONFIG_CRYPTO=y
710CONFIG_CRYPTO_HMAC=y
711CONFIG_CRYPTO_NULL=m
712CONFIG_CRYPTO_MD4=m
713CONFIG_CRYPTO_MD5=m
714CONFIG_CRYPTO_SHA1=m
715CONFIG_CRYPTO_SHA256=m
716CONFIG_CRYPTO_SHA512=m
717CONFIG_CRYPTO_WP512=m
718CONFIG_CRYPTO_TGR192=m
719CONFIG_CRYPTO_DES=m
720CONFIG_CRYPTO_BLOWFISH=m
721CONFIG_CRYPTO_TWOFISH=m
722CONFIG_CRYPTO_SERPENT=m
723CONFIG_CRYPTO_AES=m
724CONFIG_CRYPTO_CAST5=m
725CONFIG_CRYPTO_CAST6=m
726CONFIG_CRYPTO_TEA=m
727CONFIG_CRYPTO_ARC4=m
728CONFIG_CRYPTO_KHAZAD=m
729CONFIG_CRYPTO_ANUBIS=m
730CONFIG_CRYPTO_DEFLATE=m
731CONFIG_CRYPTO_MICHAEL_MIC=m
732CONFIG_CRYPTO_CRC32C=m
733# CONFIG_CRYPTO_TEST is not set
603 734
604# 735#
605# Hardware crypto devices 736# Hardware crypto devices
@@ -609,7 +740,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
609# Library routines 740# Library routines
610# 741#
611# CONFIG_CRC_CCITT is not set 742# CONFIG_CRC_CCITT is not set
612# CONFIG_CRC32 is not set 743CONFIG_CRC16=m
613# CONFIG_LIBCRC32C is not set 744CONFIG_CRC32=m
614CONFIG_GENERIC_HARDIRQS=y 745CONFIG_LIBCRC32C=m
615CONFIG_GENERIC_IRQ_PROBE=y 746CONFIG_ZLIB_INFLATE=m
747CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/mips/ddb5xxx/Kconfig b/arch/mips/ddb5xxx/Kconfig
new file mode 100644
index 000000000000..e9b5de49f4c2
--- /dev/null
+++ b/arch/mips/ddb5xxx/Kconfig
@@ -0,0 +1,4 @@
1config DDB5477_BUS_FREQUENCY
2 int "bus frequency (in kHZ, 0 for auto-detect)"
3 depends on DDB5477
4 default 0
diff --git a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
index 68c127cd70c9..8743ffce8653 100644
--- a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
+++ b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
@@ -209,14 +209,13 @@ static void nile4_irq_end(unsigned int irq) {
209#define nile4_irq_shutdown nile4_disable_irq 209#define nile4_irq_shutdown nile4_disable_irq
210 210
211static hw_irq_controller nile4_irq_controller = { 211static hw_irq_controller nile4_irq_controller = {
212 "nile4", 212 .typename = "nile4",
213 nile4_irq_startup, 213 .startup = nile4_irq_startup,
214 nile4_irq_shutdown, 214 .shutdown = nile4_irq_shutdown,
215 nile4_enable_irq, 215 .enable = nile4_enable_irq,
216 nile4_disable_irq, 216 .disable = nile4_disable_irq,
217 nile4_ack_irq, 217 .ack = nile4_ack_irq,
218 nile4_irq_end, 218 .end = nile4_irq_end,
219 NULL
220}; 219};
221 220
222void nile4_irq_setup(u32 base) { 221void nile4_irq_setup(u32 base) {
diff --git a/arch/mips/ddb5xxx/ddb5074/setup.c b/arch/mips/ddb5xxx/ddb5074/setup.c
index a73a5978d550..11535be265b9 100644
--- a/arch/mips/ddb5xxx/ddb5074/setup.c
+++ b/arch/mips/ddb5xxx/ddb5074/setup.c
@@ -85,7 +85,7 @@ static void __init ddb_time_init(void)
85 85
86 86
87 87
88static void __init ddb5074_setup(void) 88void __init plat_setup(void)
89{ 89{
90 set_io_port_base(NILE4_PCI_IO_BASE); 90 set_io_port_base(NILE4_PCI_IO_BASE);
91 isa_slot_offset = NILE4_PCI_MEM_BASE; 91 isa_slot_offset = NILE4_PCI_MEM_BASE;
@@ -106,8 +106,6 @@ static void __init ddb5074_setup(void)
106 panic_timeout = 180; 106 panic_timeout = 180;
107} 107}
108 108
109early_initcall(ddb5074_setup);
110
111#define USE_NILE4_SERIAL 0 109#define USE_NILE4_SERIAL 0
112 110
113#if USE_NILE4_SERIAL 111#if USE_NILE4_SERIAL
diff --git a/arch/mips/ddb5xxx/ddb5476/setup.c b/arch/mips/ddb5xxx/ddb5476/setup.c
index 71531f8146ea..f4e480a74edf 100644
--- a/arch/mips/ddb5xxx/ddb5476/setup.c
+++ b/arch/mips/ddb5xxx/ddb5476/setup.c
@@ -124,7 +124,7 @@ static struct {
124 124
125static void ddb5476_board_init(void); 125static void ddb5476_board_init(void);
126 126
127static void __init ddb5476_setup(void) 127void __init plat_setup(void)
128{ 128{
129 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); 129 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
130 130
@@ -158,8 +158,6 @@ static void __init ddb5476_setup(void)
158 ddb5476_board_init(); 158 ddb5476_board_init();
159} 159}
160 160
161early_initcall(ddb5476_setup);
162
163/* 161/*
164 * We don't trust bios. We essentially does hardware re-initialization 162 * We don't trust bios. We essentially does hardware re-initialization
165 * as complete as possible, as far as we know we can safely do. 163 * as complete as possible, as far as we know we can safely do.
diff --git a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c b/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
index a77682be01ac..f66fe5b58636 100644
--- a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
+++ b/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
@@ -53,14 +53,13 @@ static void vrc5476_irq_end(uint irq)
53} 53}
54 54
55static hw_irq_controller vrc5476_irq_controller = { 55static hw_irq_controller vrc5476_irq_controller = {
56 "vrc5476", 56 .typename = "vrc5476",
57 vrc5476_irq_startup, 57 .startup = vrc5476_irq_startup,
58 vrc5476_irq_shutdown, 58 .shutdown = vrc5476_irq_shutdown,
59 vrc5476_irq_enable, 59 .enable = vrc5476_irq_enable,
60 vrc5476_irq_disable, 60 .disable = vrc5476_irq_disable,
61 vrc5476_irq_ack, 61 .ack = vrc5476_irq_ack,
62 vrc5476_irq_end, 62 .end = vrc5476_irq_end
63 NULL /* no affinity stuff for UP */
64}; 63};
65 64
66void __init 65void __init
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
index 0d5e706207ec..5fcd5f070cdc 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
@@ -90,14 +90,13 @@ vrc5477_irq_end(unsigned int irq)
90} 90}
91 91
92hw_irq_controller vrc5477_irq_controller = { 92hw_irq_controller vrc5477_irq_controller = {
93 "vrc5477_irq", 93 .typename = "vrc5477_irq",
94 vrc5477_irq_startup, 94 .startup = vrc5477_irq_startup,
95 vrc5477_irq_shutdown, 95 .shutdown = vrc5477_irq_shutdown,
96 vrc5477_irq_enable, 96 .enable = vrc5477_irq_enable,
97 vrc5477_irq_disable, 97 .disable = vrc5477_irq_disable,
98 vrc5477_irq_ack, 98 .ack = vrc5477_irq_ack,
99 vrc5477_irq_end, 99 .end = vrc5477_irq_end
100 NULL /* no affinity stuff for UP */
101}; 100};
102 101
103void __init vrc5477_irq_init(u32 irq_base) 102void __init vrc5477_irq_init(u32 irq_base)
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c
index d62f5a789b05..81163353c4a8 100644
--- a/arch/mips/ddb5xxx/ddb5477/setup.c
+++ b/arch/mips/ddb5xxx/ddb5477/setup.c
@@ -170,7 +170,7 @@ static void ddb5477_board_init(void);
170extern struct pci_controller ddb5477_ext_controller; 170extern struct pci_controller ddb5477_ext_controller;
171extern struct pci_controller ddb5477_io_controller; 171extern struct pci_controller ddb5477_io_controller;
172 172
173static int ddb5477_setup(void) 173void __init plat_setup(void)
174{ 174{
175 /* initialize board - we don't trust the loader */ 175 /* initialize board - we don't trust the loader */
176 ddb5477_board_init(); 176 ddb5477_board_init();
@@ -193,12 +193,8 @@ static int ddb5477_setup(void)
193 193
194 register_pci_controller (&ddb5477_ext_controller); 194 register_pci_controller (&ddb5477_ext_controller);
195 register_pci_controller (&ddb5477_io_controller); 195 register_pci_controller (&ddb5477_io_controller);
196
197 return 0;
198} 196}
199 197
200early_initcall(ddb5477_setup);
201
202static void __init ddb5477_board_init(void) 198static void __init ddb5477_board_init(void)
203{ 199{
204 /* ----------- setup PDARs ------------ */ 200 /* ----------- setup PDARs ------------ */
diff --git a/arch/mips/dec/Makefile b/arch/mips/dec/Makefile
index 688757a97cb8..ed181fdc3ac9 100644
--- a/arch/mips/dec/Makefile
+++ b/arch/mips/dec/Makefile
@@ -2,8 +2,8 @@
2# Makefile for the DECstation family specific parts of the kernel 2# Makefile for the DECstation family specific parts of the kernel
3# 3#
4 4
5obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn02-irq.o reset.o \ 5obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
6 setup.o time.o 6 kn02-irq.o kn02xa-berr.o reset.o setup.o time.o
7 7
8obj-$(CONFIG_PROM_CONSOLE) += promcon.o 8obj-$(CONFIG_PROM_CONSOLE) += promcon.o
9obj-$(CONFIG_CPU_HAS_WB) += wbflush.o 9obj-$(CONFIG_CPU_HAS_WB) += wbflush.o
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 6dbce92eb068..cc24c5ed0c05 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -6,7 +6,7 @@
6 * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03), 6 * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
7 * 5900/260 (KN05) systems. 7 * 5900/260 (KN05) systems.
8 * 8 *
9 * Copyright (c) 2003 Maciej W. Rozycki 9 * Copyright (c) 2003, 2005 Maciej W. Rozycki
10 * 10 *
11 * This program is free software; you can redistribute it and/or 11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License 12 * modify it under the terms of the GNU General Public License
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/interrupt.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/sched.h> 20#include <linux/sched.h>
20#include <linux/spinlock.h> 21#include <linux/spinlock.h>
@@ -57,7 +58,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
57 58
58 const char *kind, *agent, *cycle, *event; 59 const char *kind, *agent, *cycle, *event;
59 const char *status = "", *xbit = "", *fmt = ""; 60 const char *status = "", *xbit = "", *fmt = "";
60 dma_addr_t address; 61 unsigned long address;
61 u16 syn = 0, sngl; 62 u16 syn = 0, sngl;
62 63
63 int i = 0; 64 int i = 0;
@@ -66,7 +67,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
66 u32 chksyn = *kn0x_chksyn; 67 u32 chksyn = *kn0x_chksyn;
67 int action = MIPS_BE_FATAL; 68 int action = MIPS_BE_FATAL;
68 69
69 /* For non-ECC ack ASAP, so any subsequent errors get caught. */ 70 /* For non-ECC ack ASAP, so that any subsequent errors get caught. */
70 if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID) 71 if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID)
71 dec_ecc_be_ack(); 72 dec_ecc_be_ack();
72 73
@@ -74,7 +75,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
74 75
75 if (!(erraddr & KN0X_EAR_VALID)) { 76 if (!(erraddr & KN0X_EAR_VALID)) {
76 /* No idea what happened. */ 77 /* No idea what happened. */
77 printk(KERN_ALERT "Unidentified bus error %s.\n", kind); 78 printk(KERN_ALERT "Unidentified bus error %s\n", kind);
78 return action; 79 return action;
79 } 80 }
80 81
@@ -126,7 +127,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
126 /* Ack now, no rewrite will happen. */ 127 /* Ack now, no rewrite will happen. */
127 dec_ecc_be_ack(); 128 dec_ecc_be_ack();
128 129
129 fmt = KERN_ALERT "%s" "invalid.\n"; 130 fmt = KERN_ALERT "%s" "invalid\n";
130 } else { 131 } else {
131 sngl = syn & KN0X_ESR_SNGLO; 132 sngl = syn & KN0X_ESR_SNGLO;
132 syn &= KN0X_ESR_SYNLO; 133 syn &= KN0X_ESR_SYNLO;
@@ -144,7 +145,8 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
144 } else if (!sngl) { 145 } else if (!sngl) {
145 status = dbestr; 146 status = dbestr;
146 } else { 147 } else {
147 volatile u32 *ptr = (void *)KSEG1ADDR(address); 148 volatile u32 *ptr =
149 (void *)CKSEG1ADDR(address);
148 150
149 *ptr = *ptr; /* Rewrite. */ 151 *ptr = *ptr; /* Rewrite. */
150 iob(); 152 iob();
@@ -160,12 +162,12 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
160 if (syn == 0x01) { 162 if (syn == 0x01) {
161 fmt = KERN_ALERT "%s" 163 fmt = KERN_ALERT "%s"
162 "%#04x -- %s bit error " 164 "%#04x -- %s bit error "
163 "at check bit C%s.\n"; 165 "at check bit C%s\n";
164 xbit = "X"; 166 xbit = "X";
165 } else { 167 } else {
166 fmt = KERN_ALERT "%s" 168 fmt = KERN_ALERT "%s"
167 "%#04x -- %s bit error " 169 "%#04x -- %s bit error "
168 "at check bit C%s%u.\n"; 170 "at check bit C%s%u\n";
169 } 171 }
170 i = syn >> 2; 172 i = syn >> 2;
171 } else { 173 } else {
@@ -175,16 +177,16 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
175 if (i < 32) 177 if (i < 32)
176 fmt = KERN_ALERT "%s" 178 fmt = KERN_ALERT "%s"
177 "%#04x -- %s bit error " 179 "%#04x -- %s bit error "
178 "at data bit D%s%u.\n"; 180 "at data bit D%s%u\n";
179 else 181 else
180 fmt = KERN_ALERT "%s" 182 fmt = KERN_ALERT "%s"
181 "%#04x -- %s bit error.\n"; 183 "%#04x -- %s bit error\n";
182 } 184 }
183 } 185 }
184 } 186 }
185 187
186 if (action != MIPS_BE_FIXUP) 188 if (action != MIPS_BE_FIXUP)
187 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx.\n", 189 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
188 kind, agent, cycle, event, address); 190 kind, agent, cycle, event, address);
189 191
190 if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR) 192 if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
@@ -203,11 +205,11 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs)
203 int action = dec_ecc_be_backend(regs, 0, 1); 205 int action = dec_ecc_be_backend(regs, 0, 1);
204 206
205 if (action == MIPS_BE_DISCARD) 207 if (action == MIPS_BE_DISCARD)
206 return IRQ_NONE; 208 return IRQ_HANDLED;
207 209
208 /* 210 /*
209 * FIXME: Find affected processes and kill them, otherwise we 211 * FIXME: Find the affected processes and kill them, otherwise
210 * must die. 212 * we must die.
211 * 213 *
212 * The interrupt is asynchronously delivered thus EPC and RA 214 * The interrupt is asynchronously delivered thus EPC and RA
213 * may be irrelevant, but are printed for a reference. 215 * may be irrelevant, but are printed for a reference.
@@ -225,16 +227,16 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs)
225 */ 227 */
226static inline void dec_kn02_be_init(void) 228static inline void dec_kn02_be_init(void)
227{ 229{
228 volatile u32 *csr = (void *)KN02_CSR_BASE; 230 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
229 unsigned long flags; 231 unsigned long flags;
230 232
231 kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR); 233 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
232 kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN); 234 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
233 235
234 spin_lock_irqsave(&kn02_lock, flags); 236 spin_lock_irqsave(&kn02_lock, flags);
235 237
236 /* Preset write-only bits of the Control Register cache. */ 238 /* Preset write-only bits of the Control Register cache. */
237 cached_kn02_csr = *csr | KN03_CSR_LEDS; 239 cached_kn02_csr = *csr | KN02_CSR_LEDS;
238 240
239 /* Set normal ECC detection and generation. */ 241 /* Set normal ECC detection and generation. */
240 cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN); 242 cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN);
@@ -248,11 +250,11 @@ static inline void dec_kn02_be_init(void)
248 250
249static inline void dec_kn03_be_init(void) 251static inline void dec_kn03_be_init(void)
250{ 252{
251 volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR); 253 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
252 volatile u32 *mbcs = (void *)(KN03_SLOT_BASE + KN05_MB_CSR); 254 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
253 255
254 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); 256 kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
255 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); 257 kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
256 258
257 /* 259 /*
258 * Set normal ECC detection and generation, enable ECC correction. 260 * Set normal ECC detection and generation, enable ECC correction.
@@ -264,7 +266,7 @@ static inline void dec_kn03_be_init(void)
264 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | 266 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
265 KN03_MCR_CORRECT; 267 KN03_MCR_CORRECT;
266 if (current_cpu_data.cputype == CPU_R4400SC) 268 if (current_cpu_data.cputype == CPU_R4400SC)
267 *mbcs |= KN05_MB_CSR_EE; 269 *mbcs |= KN4K_MB_CSR_EE;
268 fast_iob(); 270 fast_iob();
269} 271}
270 272
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index c89768d5c4e5..41fa372007bf 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -2,9 +2,9 @@
2 * arch/mips/dec/int-handler.S 2 * arch/mips/dec/int-handler.S
3 * 3 *
4 * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen 4 * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
5 * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki 5 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
6 * 6 *
7 * Written by Ralf Baechle and Andreas Busse, modified for DECStation 7 * Written by Ralf Baechle and Andreas Busse, modified for DECstation
8 * support by Paul Antoine and Harald Koerfgen. 8 * support by Paul Antoine and Harald Koerfgen.
9 * 9 *
10 * completly rewritten: 10 * completly rewritten:
@@ -14,11 +14,12 @@
14 * by Maciej W. Rozycki. 14 * by Maciej W. Rozycki.
15 */ 15 */
16#include <linux/config.h> 16#include <linux/config.h>
17
18#include <asm/addrspace.h>
17#include <asm/asm.h> 19#include <asm/asm.h>
18#include <asm/regdef.h>
19#include <asm/mipsregs.h> 20#include <asm/mipsregs.h>
21#include <asm/regdef.h>
20#include <asm/stackframe.h> 22#include <asm/stackframe.h>
21#include <asm/addrspace.h>
22 23
23#include <asm/dec/interrupts.h> 24#include <asm/dec/interrupts.h>
24#include <asm/dec/ioasic_addrs.h> 25#include <asm/dec/ioasic_addrs.h>
@@ -28,11 +29,14 @@
28#include <asm/dec/kn02xa.h> 29#include <asm/dec/kn02xa.h>
29#include <asm/dec/kn03.h> 30#include <asm/dec/kn03.h>
30 31
32#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
33#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
34#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
31 35
32 .text 36 .text
33 .set noreorder 37 .set noreorder
34/* 38/*
35 * decstation_handle_int: Interrupt handler for DECStations 39 * decstation_handle_int: Interrupt handler for DECstations
36 * 40 *
37 * We follow the model in the Indy interrupt code by David Miller, where he 41 * We follow the model in the Indy interrupt code by David Miller, where he
38 * says: a lot of complication here is taken away because: 42 * says: a lot of complication here is taken away because:
@@ -48,7 +52,7 @@
48 * 3) Linux only thinks in terms of all IRQs on or all IRQs 52 * 3) Linux only thinks in terms of all IRQs on or all IRQs
49 * off, nothing in between like BSD spl() brain-damage. 53 * off, nothing in between like BSD spl() brain-damage.
50 * 54 *
51 * Furthermore, the IRQs on the DECStations look basically (barring 55 * Furthermore, the IRQs on the DECstations look basically (barring
52 * software IRQs which we don't use at all) like... 56 * software IRQs which we don't use at all) like...
53 * 57 *
54 * DS2100/3100's, aka kn01, aka Pmax: 58 * DS2100/3100's, aka kn01, aka Pmax:
@@ -61,7 +65,7 @@
61 * 3 Lance Ethernet 65 * 3 Lance Ethernet
62 * 4 DZ11 serial 66 * 4 DZ11 serial
63 * 5 RTC 67 * 5 RTC
64 * 6 Memory Controller 68 * 6 Memory Controller & Video
65 * 7 FPU 69 * 7 FPU
66 * 70 *
67 * DS5000/200, aka kn02, aka 3max: 71 * DS5000/200, aka kn02, aka 3max:
diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c
new file mode 100644
index 000000000000..b9271db9bc76
--- /dev/null
+++ b/arch/mips/dec/kn01-berr.c
@@ -0,0 +1,201 @@
1/*
2 * linux/arch/mips/dec/kn01-berr.c
3 *
4 * Bus error event handling code for DECstation/DECsystem 3100
5 * and 2100 (KN01) systems equipped with parity error detection
6 * logic.
7 *
8 * Copyright (c) 2005 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/spinlock.h>
20#include <linux/types.h>
21
22#include <asm/inst.h>
23#include <asm/mipsregs.h>
24#include <asm/page.h>
25#include <asm/system.h>
26#include <asm/traps.h>
27#include <asm/uaccess.h>
28
29#include <asm/dec/kn01.h>
30
31
32/* CP0 hazard avoidance. */
33#define BARRIER \
34 __asm__ __volatile__( \
35 ".set push\n\t" \
36 ".set noreorder\n\t" \
37 "nop\n\t" \
38 ".set pop\n\t")
39
40/*
41 * Bits 7:0 of the Control Register are write-only -- the
42 * corresponding bits of the Status Register have a different
43 * meaning. Hence we use a cache. It speeds up things a bit
44 * as well.
45 *
46 * There is no default value -- it has to be initialized.
47 */
48u16 cached_kn01_csr;
49DEFINE_SPINLOCK(kn01_lock);
50
51
52static inline void dec_kn01_be_ack(void)
53{
54 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
55 unsigned long flags;
56
57 spin_lock_irqsave(&kn01_lock, flags);
58
59 *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */
60 iob();
61
62 spin_unlock_irqrestore(&kn01_lock, flags);
63}
64
65static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
66{
67 volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
68 KN01_ERRADDR);
69
70 static const char excstr[] = "exception";
71 static const char intstr[] = "interrupt";
72 static const char cpustr[] = "CPU";
73 static const char mreadstr[] = "memory read";
74 static const char readstr[] = "read";
75 static const char writestr[] = "write";
76 static const char timestr[] = "timeout";
77 static const char paritystr[] = "parity error";
78
79 int data = regs->cp0_cause & 4;
80 unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc +
81 ((regs->cp0_cause & CAUSEF_BD) != 0);
82 union mips_instruction insn;
83 unsigned long entrylo, offset;
84 long asid, entryhi, vaddr;
85
86 const char *kind, *agent, *cycle, *event;
87 unsigned long address;
88
89 u32 erraddr = *kn01_erraddr;
90 int action = MIPS_BE_FATAL;
91
92 /* Ack ASAP, so that any subsequent errors get caught. */
93 dec_kn01_be_ack();
94
95 kind = invoker ? intstr : excstr;
96
97 agent = cpustr;
98
99 if (invoker)
100 address = erraddr;
101 else {
102 /* Bloody hardware doesn't record the address for reads... */
103 if (data) {
104 /* This never faults. */
105 __get_user(insn.word, pc);
106 vaddr = regs->regs[insn.i_format.rs] +
107 insn.i_format.simmediate;
108 } else
109 vaddr = (long)pc;
110 if (KSEGX(vaddr) == CKSEG0 || KSEGX(vaddr) == CKSEG1)
111 address = CPHYSADDR(vaddr);
112 else {
113 /* Peek at what physical address the CPU used. */
114 asid = read_c0_entryhi();
115 entryhi = asid & (PAGE_SIZE - 1);
116 entryhi |= vaddr & ~(PAGE_SIZE - 1);
117 write_c0_entryhi(entryhi);
118 BARRIER;
119 tlb_probe();
120 /* No need to check for presence. */
121 tlb_read();
122 entrylo = read_c0_entrylo0();
123 write_c0_entryhi(asid);
124 offset = vaddr & (PAGE_SIZE - 1);
125 address = (entrylo & ~(PAGE_SIZE - 1)) | offset;
126 }
127 }
128
129 /* Treat low 256MB as memory, high -- as I/O. */
130 if (address < 0x10000000) {
131 cycle = mreadstr;
132 event = paritystr;
133 } else {
134 cycle = invoker ? writestr : readstr;
135 event = timestr;
136 }
137
138 if (is_fixup)
139 action = MIPS_BE_FIXUP;
140
141 if (action != MIPS_BE_FIXUP)
142 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
143 kind, agent, cycle, event, address);
144
145 return action;
146}
147
148int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
149{
150 return dec_kn01_be_backend(regs, is_fixup, 0);
151}
152
153irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
154 struct pt_regs *regs)
155{
156 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
157 int action;
158
159 if (!(*csr & KN01_CSR_MEMERR))
160 return IRQ_NONE; /* Must have been video. */
161
162 action = dec_kn01_be_backend(regs, 0, 1);
163
164 if (action == MIPS_BE_DISCARD)
165 return IRQ_HANDLED;
166
167 /*
168 * FIXME: Find the affected processes and kill them, otherwise
169 * we must die.
170 *
171 * The interrupt is asynchronously delivered thus EPC and RA
172 * may be irrelevant, but are printed for a reference.
173 */
174 printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
175 regs->cp0_epc, regs->regs[31]);
176 die("Unrecoverable bus error", regs);
177}
178
179
180void __init dec_kn01_be_init(void)
181{
182 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
183 unsigned long flags;
184
185 spin_lock_irqsave(&kn01_lock, flags);
186
187 /* Preset write-only bits of the Control Register cache. */
188 cached_kn01_csr = *csr;
189 cached_kn01_csr &= KN01_CSR_STATUS | KN01_CSR_PARDIS | KN01_CSR_TXDIS;
190 cached_kn01_csr |= KN01_CSR_LEDS;
191
192 /* Enable parity error detection. */
193 cached_kn01_csr &= ~KN01_CSR_PARDIS;
194 *csr = cached_kn01_csr;
195 iob();
196
197 spin_unlock_irqrestore(&kn01_lock, flags);
198
199 /* Clear any leftover errors from the firmware. */
200 dec_kn01_be_ack();
201}
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index e0bfcd1521e2..898bed502a34 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -4,7 +4,7 @@
4 * DECstation 5000/200 (KN02) Control and Status Register 4 * DECstation 5000/200 (KN02) Control and Status Register
5 * interrupts. 5 * interrupts.
6 * 6 *
7 * Copyright (c) 2002, 2003 Maciej W. Rozycki 7 * Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki
8 * 8 *
9 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License 10 * modify it under the terms of the GNU General Public License
@@ -37,7 +37,8 @@ static int kn02_irq_base;
37 37
38static inline void unmask_kn02_irq(unsigned int irq) 38static inline void unmask_kn02_irq(unsigned int irq)
39{ 39{
40 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 40 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
41 KN02_CSR);
41 42
42 cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16)); 43 cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
43 *csr = cached_kn02_csr; 44 *csr = cached_kn02_csr;
@@ -45,7 +46,8 @@ static inline void unmask_kn02_irq(unsigned int irq)
45 46
46static inline void mask_kn02_irq(unsigned int irq) 47static inline void mask_kn02_irq(unsigned int irq)
47{ 48{
48 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 49 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
50 KN02_CSR);
49 51
50 cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16)); 52 cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
51 *csr = cached_kn02_csr; 53 *csr = cached_kn02_csr;
@@ -105,13 +107,14 @@ static struct hw_interrupt_type kn02_irq_type = {
105 107
106void __init init_kn02_irqs(int base) 108void __init init_kn02_irqs(int base)
107{ 109{
108 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 110 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
111 KN02_CSR);
109 unsigned long flags; 112 unsigned long flags;
110 int i; 113 int i;
111 114
112 /* Mask interrupts. */ 115 /* Mask interrupts. */
113 spin_lock_irqsave(&kn02_lock, flags); 116 spin_lock_irqsave(&kn02_lock, flags);
114 cached_kn02_csr &= ~KN03_CSR_IOINTEN; 117 cached_kn02_csr &= ~KN02_CSR_IOINTEN;
115 *csr = cached_kn02_csr; 118 *csr = cached_kn02_csr;
116 iob(); 119 iob();
117 spin_unlock_irqrestore(&kn02_lock, flags); 120 spin_unlock_irqrestore(&kn02_lock, flags);
diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c
new file mode 100644
index 000000000000..6cd3f94f79fe
--- /dev/null
+++ b/arch/mips/dec/kn02xa-berr.c
@@ -0,0 +1,139 @@
1/*
2 * linux/arch/mips/dec/kn02xa-berr.c
3 *
4 * Bus error event handling code for 5000-series systems equipped
5 * with parity error detection logic, i.e. DECstation/DECsystem
6 * 5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal
7 * DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50
8 * (KN04-CA) systems.
9 *
10 * Copyright (c) 2005 Maciej W. Rozycki
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/kernel.h>
21#include <linux/types.h>
22
23#include <asm/addrspace.h>
24#include <asm/system.h>
25#include <asm/traps.h>
26
27#include <asm/dec/kn02ca.h>
28#include <asm/dec/kn02xa.h>
29#include <asm/dec/kn05.h>
30
31static inline void dec_kn02xa_be_ack(void)
32{
33 volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
34 volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
35
36 *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */
37 *mem_intr = 0; /* Any write clears the bus IRQ. */
38 iob();
39}
40
41static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
42 int invoker)
43{
44 volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
45 volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
46
47 static const char excstr[] = "exception";
48 static const char intstr[] = "interrupt";
49 static const char cpustr[] = "CPU";
50 static const char mreadstr[] = "memory read";
51 static const char readstr[] = "read";
52 static const char writestr[] = "write";
53 static const char timestr[] = "timeout";
54 static const char paritystr[] = "parity error";
55 static const char lanestat[][4] = { " OK", "BAD" };
56
57 const char *kind, *agent, *cycle, *event;
58 unsigned long address;
59
60 u32 mer = *kn02xa_mer;
61 u32 ear = *kn02xa_ear;
62 int action = MIPS_BE_FATAL;
63
64 /* Ack ASAP, so that any subsequent errors get caught. */
65 dec_kn02xa_be_ack();
66
67 kind = invoker ? intstr : excstr;
68
69 /* No DMA errors? */
70 agent = cpustr;
71
72 address = ear & KN02XA_EAR_ADDRESS;
73
74 /* Low 256MB is decoded as memory, high -- as TC. */
75 if (address < 0x10000000) {
76 cycle = mreadstr;
77 event = paritystr;
78 } else {
79 cycle = invoker ? writestr : readstr;
80 event = timestr;
81 }
82
83 if (is_fixup)
84 action = MIPS_BE_FIXUP;
85
86 if (action != MIPS_BE_FIXUP)
87 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
88 kind, agent, cycle, event, address);
89
90 if (action != MIPS_BE_FIXUP && address < 0x10000000)
91 printk(KERN_ALERT " Byte lane status %#3x -- "
92 "#3: %s, #2: %s, #1: %s, #0: %s\n",
93 (mer & KN02XA_MER_BYTERR) >> 8,
94 lanestat[(mer & KN02XA_MER_BYTERR_3) != 0],
95 lanestat[(mer & KN02XA_MER_BYTERR_2) != 0],
96 lanestat[(mer & KN02XA_MER_BYTERR_1) != 0],
97 lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]);
98
99 return action;
100}
101
102int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup)
103{
104 return dec_kn02xa_be_backend(regs, is_fixup, 0);
105}
106
107irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
108 struct pt_regs *regs)
109{
110 int action = dec_kn02xa_be_backend(regs, 0, 1);
111
112 if (action == MIPS_BE_DISCARD)
113 return IRQ_HANDLED;
114
115 /*
116 * FIXME: Find the affected processes and kill them, otherwise
117 * we must die.
118 *
119 * The interrupt is asynchronously delivered thus EPC and RA
120 * may be irrelevant, but are printed for a reference.
121 */
122 printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
123 regs->cp0_epc, regs->regs[31]);
124 die("Unrecoverable bus error", regs);
125}
126
127
128void __init dec_kn02xa_be_init(void)
129{
130 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
131
132 /* For KN04 we need to make sure EE (?) is enabled in the MB. */
133 if (current_cpu_data.cputype == CPU_R4000SC)
134 *mbcs |= KN4K_MB_CSR_EE;
135 fast_iob();
136
137 /* Clear any leftover errors from the firmware. */
138 dec_kn02xa_be_ack();
139}
diff --git a/arch/mips/dec/prom/identify.c b/arch/mips/dec/prom/identify.c
index 9380588cb15c..81d5e878ddce 100644
--- a/arch/mips/dec/prom/identify.c
+++ b/arch/mips/dec/prom/identify.c
@@ -2,7 +2,7 @@
2 * identify.c: machine identification code. 2 * identify.c: machine identification code.
3 * 3 *
4 * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine 4 * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine
5 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki 5 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
6 */ 6 */
7#include <linux/init.h> 7#include <linux/init.h>
8#include <linux/kernel.h> 8#include <linux/kernel.h>
@@ -12,6 +12,7 @@
12#include <linux/types.h> 12#include <linux/types.h>
13 13
14#include <asm/bootinfo.h> 14#include <asm/bootinfo.h>
15
15#include <asm/dec/ioasic.h> 16#include <asm/dec/ioasic.h>
16#include <asm/dec/ioasic_addrs.h> 17#include <asm/dec/ioasic_addrs.h>
17#include <asm/dec/kn01.h> 18#include <asm/dec/kn01.h>
@@ -21,6 +22,7 @@
21#include <asm/dec/kn03.h> 22#include <asm/dec/kn03.h>
22#include <asm/dec/kn230.h> 23#include <asm/dec/kn230.h>
23#include <asm/dec/prom.h> 24#include <asm/dec/prom.h>
25#include <asm/dec/system.h>
24 26
25#include "dectypes.h" 27#include "dectypes.h"
26 28
@@ -68,34 +70,44 @@ EXPORT_SYMBOL(dec_rtc_base);
68 70
69static inline void prom_init_kn01(void) 71static inline void prom_init_kn01(void)
70{ 72{
71 dec_rtc_base = (void *)KN01_RTC_BASE; 73 dec_kn_slot_base = KN01_SLOT_BASE;
72 dec_kn_slot_size = KN01_SLOT_SIZE; 74 dec_kn_slot_size = KN01_SLOT_SIZE;
75
76 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
73} 77}
74 78
75static inline void prom_init_kn230(void) 79static inline void prom_init_kn230(void)
76{ 80{
77 dec_rtc_base = (void *)KN01_RTC_BASE; 81 dec_kn_slot_base = KN01_SLOT_BASE;
78 dec_kn_slot_size = KN01_SLOT_SIZE; 82 dec_kn_slot_size = KN01_SLOT_SIZE;
83
84 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
79} 85}
80 86
81static inline void prom_init_kn02(void) 87static inline void prom_init_kn02(void)
82{ 88{
83 dec_rtc_base = (void *)KN02_RTC_BASE; 89 dec_kn_slot_base = KN02_SLOT_BASE;
84 dec_kn_slot_size = KN02_SLOT_SIZE; 90 dec_kn_slot_size = KN02_SLOT_SIZE;
91
92 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC);
85} 93}
86 94
87static inline void prom_init_kn02xa(void) 95static inline void prom_init_kn02xa(void)
88{ 96{
89 ioasic_base = (void *)KN02XA_IOASIC_BASE; 97 dec_kn_slot_base = KN02XA_SLOT_BASE;
90 dec_rtc_base = (void *)KN02XA_RTC_BASE;
91 dec_kn_slot_size = IOASIC_SLOT_SIZE; 98 dec_kn_slot_size = IOASIC_SLOT_SIZE;
99
100 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
101 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
92} 102}
93 103
94static inline void prom_init_kn03(void) 104static inline void prom_init_kn03(void)
95{ 105{
96 ioasic_base = (void *)KN03_IOASIC_BASE; 106 dec_kn_slot_base = KN03_SLOT_BASE;
97 dec_rtc_base = (void *)KN03_RTC_BASE;
98 dec_kn_slot_size = IOASIC_SLOT_SIZE; 107 dec_kn_slot_size = IOASIC_SLOT_SIZE;
108
109 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
110 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
99} 111}
100 112
101 113
diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index 60f74256e689..32a7cc7e4c65 100644
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -6,6 +6,8 @@
6 */ 6 */
7#include <linux/config.h> 7#include <linux/config.h>
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/linkage.h>
9#include <linux/smp.h> 11#include <linux/smp.h>
10#include <linux/string.h> 12#include <linux/string.h>
11#include <linux/types.h> 13#include <linux/types.h>
@@ -85,17 +87,13 @@ void __init which_prom(s32 magic, s32 *prom_vec)
85 87
86void __init prom_init(void) 88void __init prom_init(void)
87{ 89{
88 extern void dec_machine_halt(void); 90 extern void ATTRIB_NORET dec_machine_halt(void);
89 static char cpu_msg[] __initdata = 91 static char cpu_msg[] __initdata =
90 "Sorry, this kernel is compiled for a wrong CPU type!\n"; 92 "Sorry, this kernel is compiled for a wrong CPU type!\n";
91 static char r3k_msg[] __initdata =
92 "Please recompile with \"CONFIG_CPU_R3000 = y\".\n";
93 static char r4k_msg[] __initdata =
94 "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
95 s32 argc = fw_arg0; 93 s32 argc = fw_arg0;
96 s32 argv = fw_arg1; 94 s32 *argv = (void *)fw_arg1;
97 u32 magic = fw_arg2; 95 u32 magic = fw_arg2;
98 s32 prom_vec = fw_arg3; 96 s32 *prom_vec = (void *)fw_arg3;
99 97
100 /* 98 /*
101 * Determine which PROM we have 99 * Determine which PROM we have
@@ -113,6 +111,8 @@ void __init prom_init(void)
113#if defined(CONFIG_CPU_R3000) 111#if defined(CONFIG_CPU_R3000)
114 if ((current_cpu_data.cputype == CPU_R4000SC) || 112 if ((current_cpu_data.cputype == CPU_R4000SC) ||
115 (current_cpu_data.cputype == CPU_R4400SC)) { 113 (current_cpu_data.cputype == CPU_R4400SC)) {
114 static char r4k_msg[] __initdata =
115 "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
116 printk(cpu_msg); 116 printk(cpu_msg);
117 printk(r4k_msg); 117 printk(r4k_msg);
118 dec_machine_halt(); 118 dec_machine_halt();
@@ -122,6 +122,8 @@ void __init prom_init(void)
122#if defined(CONFIG_CPU_R4X00) 122#if defined(CONFIG_CPU_R4X00)
123 if ((current_cpu_data.cputype == CPU_R3000) || 123 if ((current_cpu_data.cputype == CPU_R3000) ||
124 (current_cpu_data.cputype == CPU_R3000A)) { 124 (current_cpu_data.cputype == CPU_R3000A)) {
125 static char r3k_msg[] __initdata =
126 "Please recompile with \"CONFIG_CPU_R3000 = y\".\n";
125 printk(cpu_msg); 127 printk(cpu_msg);
126 printk(r3k_msg); 128 printk(r3k_msg);
127 dec_machine_halt(); 129 dec_machine_halt();
diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c
index e4f6f26425ea..83d4556c3cb5 100644
--- a/arch/mips/dec/prom/memory.c
+++ b/arch/mips/dec/prom/memory.c
@@ -35,22 +35,22 @@ static inline void pmax_setup_memory_region(void)
35 extern char genexcept_early; 35 extern char genexcept_early;
36 36
37 /* Install exception handler */ 37 /* Install exception handler */
38 memcpy(&old_handler, (void *)(KSEG0 + 0x80), 0x80); 38 memcpy(&old_handler, (void *)(CKSEG0 + 0x80), 0x80);
39 memcpy((void *)(KSEG0 + 0x80), &genexcept_early, 0x80); 39 memcpy((void *)(CKSEG0 + 0x80), &genexcept_early, 0x80);
40 40
41 /* read unmapped and uncached (KSEG1) 41 /* read unmapped and uncached (KSEG1)
42 * DECstations have at least 4MB RAM 42 * DECstations have at least 4MB RAM
43 * Assume less than 480MB of RAM, as this is max for 5000/2xx 43 * Assume less than 480MB of RAM, as this is max for 5000/2xx
44 * FIXME this should be replaced by the first free page! 44 * FIXME this should be replaced by the first free page!
45 */ 45 */
46 for (memory_page = (unsigned char *) KSEG1 + CHUNK_SIZE; 46 for (memory_page = (unsigned char *)CKSEG1 + CHUNK_SIZE;
47 (mem_err== 0) && (memory_page < ((unsigned char *) KSEG1+0x1E000000)); 47 mem_err == 0 && memory_page < (unsigned char *)CKSEG1 + 0x1e00000;
48 memory_page += CHUNK_SIZE) { 48 memory_page += CHUNK_SIZE) {
49 dummy = *memory_page; 49 dummy = *memory_page;
50 } 50 }
51 memcpy((void *)(KSEG0 + 0x80), &old_handler, 0x80); 51 memcpy((void *)(CKSEG0 + 0x80), &old_handler, 0x80);
52 52
53 add_memory_region(0, (unsigned long)memory_page - KSEG1 - CHUNK_SIZE, 53 add_memory_region(0, (unsigned long)memory_page - CKSEG1 - CHUNK_SIZE,
54 BOOT_MEM_RAM); 54 BOOT_MEM_RAM);
55} 55}
56 56
@@ -65,7 +65,7 @@ static inline void rex_setup_memory_region(void)
65 memmap *bm; 65 memmap *bm;
66 66
67 /* some free 64k */ 67 /* some free 64k */
68 bm = (memmap *)KSEG0ADDR(0x28000); 68 bm = (memmap *)CKSEG0ADDR(0x28000);
69 69
70 bitmap_size = rex_getbitmap(bm); 70 bitmap_size = rex_getbitmap(bm);
71 71
diff --git a/arch/mips/dec/reset.c b/arch/mips/dec/reset.c
index 7e4d34d0573d..f78c6da47921 100644
--- a/arch/mips/dec/reset.c
+++ b/arch/mips/dec/reset.c
@@ -14,7 +14,7 @@ typedef void ATTRIB_NORET (* noret_func_t)(void);
14 14
15static inline void ATTRIB_NORET back_to_prom(void) 15static inline void ATTRIB_NORET back_to_prom(void)
16{ 16{
17 noret_func_t func = (void *) KSEG1ADDR(0x1fc00000); 17 noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000);
18 18
19 func(); 19 func();
20} 20}
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 6a69309baf40..9ef54fe1feaa 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -1,19 +1,20 @@
1/* 1/*
2 * Setup the interrupt stuff. 2 * System-specific setup, especially interrupts.
3 * 3 *
4 * This file is subject to the terms and conditions of the GNU General Public 4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 1998 Harald Koerfgen 8 * Copyright (C) 1998 Harald Koerfgen
9 * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki 9 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
10 */ 10 */
11#include <linux/sched.h>
12#include <linux/interrupt.h>
13#include <linux/param.h>
14#include <linux/console.h> 11#include <linux/console.h>
15#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/ioport.h>
16#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/param.h>
17#include <linux/sched.h>
17#include <linux/spinlock.h> 18#include <linux/spinlock.h>
18#include <linux/types.h> 19#include <linux/types.h>
19 20
@@ -38,6 +39,7 @@
38#include <asm/dec/kn02ca.h> 39#include <asm/dec/kn02ca.h>
39#include <asm/dec/kn03.h> 40#include <asm/dec/kn03.h>
40#include <asm/dec/kn230.h> 41#include <asm/dec/kn230.h>
42#include <asm/dec/system.h>
41 43
42 44
43extern void dec_machine_restart(char *command); 45extern void dec_machine_restart(char *command);
@@ -47,10 +49,16 @@ extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
47 49
48extern asmlinkage void decstation_handle_int(void); 50extern asmlinkage void decstation_handle_int(void);
49 51
52unsigned long dec_kn_slot_base, dec_kn_slot_size;
53
54EXPORT_SYMBOL(dec_kn_slot_base);
55EXPORT_SYMBOL(dec_kn_slot_size);
56
50spinlock_t ioasic_ssr_lock; 57spinlock_t ioasic_ssr_lock;
51 58
52volatile u32 *ioasic_base; 59volatile u32 *ioasic_base;
53unsigned long dec_kn_slot_size; 60
61EXPORT_SYMBOL(ioasic_base);
54 62
55/* 63/*
56 * IRQ routing and priority tables. Priorites are set as follows: 64 * IRQ routing and priority tables. Priorites are set as follows:
@@ -77,6 +85,9 @@ unsigned long dec_kn_slot_size;
77int dec_interrupt[DEC_NR_INTS] = { 85int dec_interrupt[DEC_NR_INTS] = {
78 [0 ... DEC_NR_INTS - 1] = -1 86 [0 ... DEC_NR_INTS - 1] = -1
79}; 87};
88
89EXPORT_SYMBOL(dec_interrupt);
90
80int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { 91int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
81 { { .i = ~0 }, { .p = dec_intr_unimplemented } }, 92 { { .i = ~0 }, { .p = dec_intr_unimplemented } },
82}; 93};
@@ -108,11 +119,20 @@ static struct irqaction haltirq = {
108/* 119/*
109 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup. 120 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
110 */ 121 */
111void __init dec_be_init(void) 122static void __init dec_be_init(void)
112{ 123{
113 switch (mips_machtype) { 124 switch (mips_machtype) {
114 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 125 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
126 board_be_handler = dec_kn01_be_handler;
127 busirq.handler = dec_kn01_be_interrupt;
115 busirq.flags |= SA_SHIRQ; 128 busirq.flags |= SA_SHIRQ;
129 dec_kn01_be_init();
130 break;
131 case MACH_DS5000_1XX: /* DS5000/1xx 3min */
132 case MACH_DS5000_XX: /* DS5000/xx Maxine */
133 board_be_handler = dec_kn02xa_be_handler;
134 busirq.handler = dec_kn02xa_be_interrupt;
135 dec_kn02xa_be_init();
116 break; 136 break;
117 case MACH_DS5000_200: /* DS5000/200 3max */ 137 case MACH_DS5000_200: /* DS5000/200 3max */
118 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 138 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
@@ -128,7 +148,7 @@ void __init dec_be_init(void)
128extern void dec_time_init(void); 148extern void dec_time_init(void);
129extern void dec_timer_setup(struct irqaction *); 149extern void dec_timer_setup(struct irqaction *);
130 150
131static void __init decstation_setup(void) 151void __init plat_setup(void)
132{ 152{
133 board_be_init = dec_be_init; 153 board_be_init = dec_be_init;
134 board_time_init = dec_time_init; 154 board_time_init = dec_time_init;
@@ -139,9 +159,10 @@ static void __init decstation_setup(void)
139 _machine_restart = dec_machine_restart; 159 _machine_restart = dec_machine_restart;
140 _machine_halt = dec_machine_halt; 160 _machine_halt = dec_machine_halt;
141 _machine_power_off = dec_machine_power_off; 161 _machine_power_off = dec_machine_power_off;
142}
143 162
144early_initcall(decstation_setup); 163 ioport_resource.start = ~0UL;
164 ioport_resource.end = 0UL;
165}
145 166
146/* 167/*
147 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin) 168 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
@@ -206,7 +227,7 @@ static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
206 { .p = cpu_all_int } }, 227 { .p = cpu_all_int } },
207}; 228};
208 229
209void __init dec_init_kn01(void) 230static void __init dec_init_kn01(void)
210{ 231{
211 /* IRQ routing. */ 232 /* IRQ routing. */
212 memcpy(&dec_interrupt, &kn01_interrupt, 233 memcpy(&dec_interrupt, &kn01_interrupt,
@@ -281,7 +302,7 @@ static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
281 { .p = cpu_all_int } }, 302 { .p = cpu_all_int } },
282}; 303};
283 304
284void __init dec_init_kn230(void) 305static void __init dec_init_kn230(void)
285{ 306{
286 /* IRQ routing. */ 307 /* IRQ routing. */
287 memcpy(&dec_interrupt, &kn230_interrupt, 308 memcpy(&dec_interrupt, &kn230_interrupt,
@@ -371,7 +392,7 @@ static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
371 { .p = kn02_all_int } }, 392 { .p = kn02_all_int } },
372}; 393};
373 394
374void __init dec_init_kn02(void) 395static void __init dec_init_kn02(void)
375{ 396{
376 /* IRQ routing. */ 397 /* IRQ routing. */
377 memcpy(&dec_interrupt, &kn02_interrupt, 398 memcpy(&dec_interrupt, &kn02_interrupt,
@@ -472,7 +493,7 @@ static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
472 { .p = asic_all_int } }, 493 { .p = asic_all_int } },
473}; 494};
474 495
475void __init dec_init_kn02ba(void) 496static void __init dec_init_kn02ba(void)
476{ 497{
477 /* IRQ routing. */ 498 /* IRQ routing. */
478 memcpy(&dec_interrupt, &kn02ba_interrupt, 499 memcpy(&dec_interrupt, &kn02ba_interrupt,
@@ -569,7 +590,7 @@ static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
569 { .p = asic_all_int } }, 590 { .p = asic_all_int } },
570}; 591};
571 592
572void __init dec_init_kn02ca(void) 593static void __init dec_init_kn02ca(void)
573{ 594{
574 /* IRQ routing. */ 595 /* IRQ routing. */
575 memcpy(&dec_interrupt, &kn02ca_interrupt, 596 memcpy(&dec_interrupt, &kn02ca_interrupt,
@@ -670,7 +691,7 @@ static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
670 { .p = asic_all_int } }, 691 { .p = asic_all_int } },
671}; 692};
672 693
673void __init dec_init_kn03(void) 694static void __init dec_init_kn03(void)
674{ 695{
675 /* IRQ routing. */ 696 /* IRQ routing. */
676 memcpy(&dec_interrupt, &kn03_interrupt, 697 memcpy(&dec_interrupt, &kn03_interrupt,
@@ -744,7 +765,3 @@ void __init arch_init_irq(void)
744 if (dec_interrupt[DEC_IRQ_HALT] >= 0) 765 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
745 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); 766 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
746} 767}
747
748EXPORT_SYMBOL(ioasic_base);
749EXPORT_SYMBOL(dec_kn_slot_size);
750EXPORT_SYMBOL(dec_interrupt);
diff --git a/arch/mips/defconfig b/arch/mips/defconfig
index 20f84b119b4c..4b585e642c2a 100644
--- a/arch/mips/defconfig
+++ b/arch/mips/defconfig
@@ -1,12 +1,9 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.14-rc2
4# Wed Jan 26 02:48:59 2005 4# Thu Oct 20 22:25:09 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_64BIT is not set
8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
@@ -14,25 +11,30 @@ CONFIG_32BIT=y
14CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
20CONFIG_LOCALVERSION_AUTO=y
22CONFIG_SWAP=y 21CONFIG_SWAP=y
23CONFIG_SYSVIPC=y 22CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set 23# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 24# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 25CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set 26# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29# CONFIG_HOTPLUG is not set 27# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 28CONFIG_KOBJECT_UEVENT=y
31CONFIG_IKCONFIG=y 29CONFIG_IKCONFIG=y
32CONFIG_IKCONFIG_PROC=y 30CONFIG_IKCONFIG_PROC=y
31CONFIG_INITRAMFS_SOURCE=""
33CONFIG_EMBEDDED=y 32CONFIG_EMBEDDED=y
34CONFIG_KALLSYMS=y 33CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_EXTRA_PASS is not set 34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
36CONFIG_FUTEX=y 38CONFIG_FUTEX=y
37CONFIG_EPOLL=y 39CONFIG_EPOLL=y
38# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -42,6 +44,7 @@ CONFIG_CC_ALIGN_LABELS=0
42CONFIG_CC_ALIGN_LOOPS=0 44CONFIG_CC_ALIGN_LOOPS=0
43CONFIG_CC_ALIGN_JUMPS=0 45CONFIG_CC_ALIGN_JUMPS=0
44# CONFIG_TINY_SHMEM is not set 46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
45 48
46# 49#
47# Loadable module support 50# Loadable module support
@@ -57,41 +60,69 @@ CONFIG_KMOD=y
57# 60#
58# Machine selection 61# Machine selection
59# 62#
60# CONFIG_MACH_JAZZ is not set 63# CONFIG_MIPS_MTX1 is not set
61# CONFIG_MACH_VR41XX is not set 64# CONFIG_MIPS_BOSPORUS is not set
62# CONFIG_TOSHIBA_JMR3927 is not set 65# CONFIG_MIPS_PB1000 is not set
66# CONFIG_MIPS_PB1100 is not set
67# CONFIG_MIPS_PB1500 is not set
68# CONFIG_MIPS_PB1550 is not set
69# CONFIG_MIPS_PB1200 is not set
70# CONFIG_MIPS_DB1000 is not set
71# CONFIG_MIPS_DB1100 is not set
72# CONFIG_MIPS_DB1500 is not set
73# CONFIG_MIPS_DB1550 is not set
74# CONFIG_MIPS_DB1200 is not set
75# CONFIG_MIPS_MIRAGE is not set
63# CONFIG_MIPS_COBALT is not set 76# CONFIG_MIPS_COBALT is not set
64# CONFIG_MACH_DECSTATION is not set 77# CONFIG_MACH_DECSTATION is not set
65# CONFIG_MIPS_EV64120 is not set 78# CONFIG_MIPS_EV64120 is not set
66# CONFIG_MIPS_EV96100 is not set 79# CONFIG_MIPS_EV96100 is not set
67# CONFIG_MIPS_IVR is not set 80# CONFIG_MIPS_IVR is not set
68# CONFIG_LASAT is not set
69# CONFIG_MIPS_ITE8172 is not set 81# CONFIG_MIPS_ITE8172 is not set
82# CONFIG_MACH_JAZZ is not set
83# CONFIG_LASAT is not set
70# CONFIG_MIPS_ATLAS is not set 84# CONFIG_MIPS_ATLAS is not set
71# CONFIG_MIPS_MALTA is not set 85# CONFIG_MIPS_MALTA is not set
72# CONFIG_MIPS_SEAD is not set 86# CONFIG_MIPS_SEAD is not set
87# CONFIG_MIPS_SIM is not set
88# CONFIG_MOMENCO_JAGUAR_ATX is not set
73# CONFIG_MOMENCO_OCELOT is not set 89# CONFIG_MOMENCO_OCELOT is not set
74# CONFIG_MOMENCO_OCELOT_G is not set
75# CONFIG_MOMENCO_OCELOT_C is not set
76# CONFIG_MOMENCO_OCELOT_3 is not set 90# CONFIG_MOMENCO_OCELOT_3 is not set
77# CONFIG_MOMENCO_JAGUAR_ATX is not set 91# CONFIG_MOMENCO_OCELOT_C is not set
78# CONFIG_PMC_YOSEMITE is not set 92# CONFIG_MOMENCO_OCELOT_G is not set
93# CONFIG_MIPS_XXS1500 is not set
94# CONFIG_PNX8550_V2PCI is not set
95# CONFIG_PNX8550_JBS is not set
79# CONFIG_DDB5074 is not set 96# CONFIG_DDB5074 is not set
80# CONFIG_DDB5476 is not set 97# CONFIG_DDB5476 is not set
81# CONFIG_DDB5477 is not set 98# CONFIG_DDB5477 is not set
82# CONFIG_NEC_OSPREY is not set 99# CONFIG_MACH_VR41XX is not set
100# CONFIG_PMC_YOSEMITE is not set
101# CONFIG_QEMU is not set
83CONFIG_SGI_IP22=y 102CONFIG_SGI_IP22=y
84# CONFIG_SOC_AU1X00 is not set 103# CONFIG_SGI_IP27 is not set
85# CONFIG_SIBYTE_SB1xxx_SOC is not set 104# CONFIG_SGI_IP32 is not set
105# CONFIG_SIBYTE_BIGSUR is not set
106# CONFIG_SIBYTE_SWARM is not set
107# CONFIG_SIBYTE_SENTOSA is not set
108# CONFIG_SIBYTE_RHONE is not set
109# CONFIG_SIBYTE_CARMEL is not set
110# CONFIG_SIBYTE_PTSWARM is not set
111# CONFIG_SIBYTE_LITTLESUR is not set
112# CONFIG_SIBYTE_CRHINE is not set
113# CONFIG_SIBYTE_CRHONE is not set
86# CONFIG_SNI_RM200_PCI is not set 114# CONFIG_SNI_RM200_PCI is not set
115# CONFIG_TOSHIBA_JMR3927 is not set
87# CONFIG_TOSHIBA_RBTX4927 is not set 116# CONFIG_TOSHIBA_RBTX4927 is not set
117# CONFIG_TOSHIBA_RBTX4938 is not set
88CONFIG_RWSEM_GENERIC_SPINLOCK=y 118CONFIG_RWSEM_GENERIC_SPINLOCK=y
89CONFIG_GENERIC_CALIBRATE_DELAY=y 119CONFIG_GENERIC_CALIBRATE_DELAY=y
90CONFIG_HAVE_DEC_LOCK=y
91CONFIG_ARC=y 120CONFIG_ARC=y
92CONFIG_DMA_NONCOHERENT=y 121CONFIG_DMA_NONCOHERENT=y
93CONFIG_DMA_NEED_PCI_MAP_STATE=y 122CONFIG_DMA_NEED_PCI_MAP_STATE=y
123CONFIG_CPU_BIG_ENDIAN=y
94# CONFIG_CPU_LITTLE_ENDIAN is not set 124# CONFIG_CPU_LITTLE_ENDIAN is not set
125CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
95CONFIG_IRQ_CPU=y 126CONFIG_IRQ_CPU=y
96CONFIG_SWAP_IO_SPACE=y 127CONFIG_SWAP_IO_SPACE=y
97CONFIG_ARC32=y 128CONFIG_ARC32=y
@@ -103,8 +134,10 @@ CONFIG_ARC_PROMLIB=y
103# 134#
104# CPU selection 135# CPU selection
105# 136#
106# CONFIG_CPU_MIPS32 is not set 137# CONFIG_CPU_MIPS32_R1 is not set
107# CONFIG_CPU_MIPS64 is not set 138# CONFIG_CPU_MIPS32_R2 is not set
139# CONFIG_CPU_MIPS64_R1 is not set
140# CONFIG_CPU_MIPS64_R2 is not set
108# CONFIG_CPU_R3000 is not set 141# CONFIG_CPU_R3000 is not set
109# CONFIG_CPU_TX39XX is not set 142# CONFIG_CPU_TX39XX is not set
110# CONFIG_CPU_VR41XX is not set 143# CONFIG_CPU_VR41XX is not set
@@ -120,22 +153,48 @@ CONFIG_CPU_R5000=y
120# CONFIG_CPU_RM7000 is not set 153# CONFIG_CPU_RM7000 is not set
121# CONFIG_CPU_RM9000 is not set 154# CONFIG_CPU_RM9000 is not set
122# CONFIG_CPU_SB1 is not set 155# CONFIG_CPU_SB1 is not set
156CONFIG_SYS_HAS_CPU_R4X00=y
157CONFIG_SYS_HAS_CPU_R5000=y
158CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
159CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
160CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
161CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
162
163#
164# Kernel type
165#
166CONFIG_32BIT=y
167# CONFIG_64BIT is not set
123CONFIG_PAGE_SIZE_4KB=y 168CONFIG_PAGE_SIZE_4KB=y
124# CONFIG_PAGE_SIZE_8KB is not set 169# CONFIG_PAGE_SIZE_8KB is not set
125# CONFIG_PAGE_SIZE_16KB is not set 170# CONFIG_PAGE_SIZE_16KB is not set
126# CONFIG_PAGE_SIZE_64KB is not set 171# CONFIG_PAGE_SIZE_64KB is not set
127CONFIG_BOARD_SCACHE=y 172CONFIG_BOARD_SCACHE=y
128CONFIG_IP22_CPU_SCACHE=y 173CONFIG_IP22_CPU_SCACHE=y
174# CONFIG_MIPS_MT is not set
129# CONFIG_64BIT_PHYS_ADDR is not set 175# CONFIG_64BIT_PHYS_ADDR is not set
130# CONFIG_CPU_ADVANCED is not set 176# CONFIG_CPU_ADVANCED is not set
131CONFIG_CPU_HAS_LLSC=y 177CONFIG_CPU_HAS_LLSC=y
132CONFIG_CPU_HAS_LLDSCD=y 178CONFIG_CPU_HAS_LLDSCD=y
133CONFIG_CPU_HAS_SYNC=y 179CONFIG_CPU_HAS_SYNC=y
180CONFIG_GENERIC_HARDIRQS=y
181CONFIG_GENERIC_IRQ_PROBE=y
182CONFIG_ARCH_FLATMEM_ENABLE=y
183CONFIG_SELECT_MEMORY_MODEL=y
184CONFIG_FLATMEM_MANUAL=y
185# CONFIG_DISCONTIGMEM_MANUAL is not set
186# CONFIG_SPARSEMEM_MANUAL is not set
187CONFIG_FLATMEM=y
188CONFIG_FLAT_NODE_MEM_MAP=y
189# CONFIG_SPARSEMEM_STATIC is not set
190# CONFIG_PREEMPT_NONE is not set
191CONFIG_PREEMPT_VOLUNTARY=y
134# CONFIG_PREEMPT is not set 192# CONFIG_PREEMPT is not set
135 193
136# 194#
137# Bus options (PCI, PCMCIA, EISA, ISA, TC) 195# Bus options (PCI, PCMCIA, EISA, ISA, TC)
138# 196#
197CONFIG_HW_HAS_EISA=y
139# CONFIG_EISA is not set 198# CONFIG_EISA is not set
140CONFIG_MMU=y 199CONFIG_MMU=y
141 200
@@ -145,10 +204,6 @@ CONFIG_MMU=y
145# CONFIG_PCCARD is not set 204# CONFIG_PCCARD is not set
146 205
147# 206#
148# PC-card bridges
149#
150
151#
152# PCI Hotplug Support 207# PCI Hotplug Support
153# 208#
154 209
@@ -160,115 +215,7 @@ CONFIG_BINFMT_MISC=m
160CONFIG_TRAD_SIGNALS=y 215CONFIG_TRAD_SIGNALS=y
161 216
162# 217#
163# Device Drivers 218# Networking
164#
165
166#
167# Generic Driver Options
168#
169CONFIG_STANDALONE=y
170CONFIG_PREVENT_FIRMWARE_BUILD=y
171# CONFIG_FW_LOADER is not set
172
173#
174# Memory Technology Devices (MTD)
175#
176# CONFIG_MTD is not set
177
178#
179# Parallel port support
180#
181# CONFIG_PARPORT is not set
182
183#
184# Plug and Play support
185#
186
187#
188# Block devices
189#
190# CONFIG_BLK_DEV_FD is not set
191# CONFIG_BLK_DEV_COW_COMMON is not set
192# CONFIG_BLK_DEV_LOOP is not set
193# CONFIG_BLK_DEV_NBD is not set
194# CONFIG_BLK_DEV_RAM is not set
195CONFIG_BLK_DEV_RAM_COUNT=16
196CONFIG_INITRAMFS_SOURCE=""
197# CONFIG_LBD is not set
198CONFIG_CDROM_PKTCDVD=m
199CONFIG_CDROM_PKTCDVD_BUFFERS=8
200# CONFIG_CDROM_PKTCDVD_WCACHE is not set
201
202#
203# IO Schedulers
204#
205CONFIG_IOSCHED_NOOP=y
206CONFIG_IOSCHED_AS=y
207CONFIG_IOSCHED_DEADLINE=y
208CONFIG_IOSCHED_CFQ=y
209CONFIG_ATA_OVER_ETH=m
210
211#
212# ATA/ATAPI/MFM/RLL support
213#
214# CONFIG_IDE is not set
215
216#
217# SCSI device support
218#
219CONFIG_SCSI=y
220CONFIG_SCSI_PROC_FS=y
221
222#
223# SCSI support type (disk, tape, CD-ROM)
224#
225CONFIG_BLK_DEV_SD=y
226CONFIG_CHR_DEV_ST=y
227# CONFIG_CHR_DEV_OSST is not set
228CONFIG_BLK_DEV_SR=y
229# CONFIG_BLK_DEV_SR_VENDOR is not set
230# CONFIG_CHR_DEV_SG is not set
231
232#
233# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
234#
235# CONFIG_SCSI_MULTI_LUN is not set
236CONFIG_SCSI_CONSTANTS=y
237# CONFIG_SCSI_LOGGING is not set
238
239#
240# SCSI Transport Attributes
241#
242CONFIG_SCSI_SPI_ATTRS=m
243# CONFIG_SCSI_FC_ATTRS is not set
244CONFIG_SCSI_ISCSI_ATTRS=m
245
246#
247# SCSI low-level drivers
248#
249CONFIG_SGIWD93_SCSI=y
250# CONFIG_SCSI_SATA is not set
251# CONFIG_SCSI_DEBUG is not set
252
253#
254# Multi-device support (RAID and LVM)
255#
256# CONFIG_MD is not set
257
258#
259# Fusion MPT device support
260#
261
262#
263# IEEE 1394 (FireWire) support
264#
265
266#
267# I2O device support
268#
269
270#
271# Networking support
272# 219#
273CONFIG_NET=y 220CONFIG_NET=y
274 221
@@ -277,12 +224,14 @@ CONFIG_NET=y
277# 224#
278CONFIG_PACKET=y 225CONFIG_PACKET=y
279CONFIG_PACKET_MMAP=y 226CONFIG_PACKET_MMAP=y
280CONFIG_NETLINK_DEV=y
281CONFIG_UNIX=y 227CONFIG_UNIX=y
228CONFIG_XFRM=y
229CONFIG_XFRM_USER=m
282CONFIG_NET_KEY=y 230CONFIG_NET_KEY=y
283CONFIG_INET=y 231CONFIG_INET=y
284CONFIG_IP_MULTICAST=y 232CONFIG_IP_MULTICAST=y
285# CONFIG_IP_ADVANCED_ROUTER is not set 233# CONFIG_IP_ADVANCED_ROUTER is not set
234CONFIG_IP_FIB_HASH=y
286CONFIG_IP_PNP=y 235CONFIG_IP_PNP=y
287# CONFIG_IP_PNP_DHCP is not set 236# CONFIG_IP_PNP_DHCP is not set
288CONFIG_IP_PNP_BOOTP=y 237CONFIG_IP_PNP_BOOTP=y
@@ -296,8 +245,10 @@ CONFIG_INET_AH=m
296CONFIG_INET_ESP=m 245CONFIG_INET_ESP=m
297CONFIG_INET_IPCOMP=m 246CONFIG_INET_IPCOMP=m
298CONFIG_INET_TUNNEL=m 247CONFIG_INET_TUNNEL=m
299CONFIG_IP_TCPDIAG=m 248CONFIG_INET_DIAG=y
300CONFIG_IP_TCPDIAG_IPV6=y 249CONFIG_INET_TCP_DIAG=y
250# CONFIG_TCP_CONG_ADVANCED is not set
251CONFIG_TCP_CONG_BIC=y
301 252
302# 253#
303# IP: Virtual Server Configuration 254# IP: Virtual Server Configuration
@@ -341,6 +292,9 @@ CONFIG_INET6_TUNNEL=m
341CONFIG_IPV6_TUNNEL=m 292CONFIG_IPV6_TUNNEL=m
342CONFIG_NETFILTER=y 293CONFIG_NETFILTER=y
343# CONFIG_NETFILTER_DEBUG is not set 294# CONFIG_NETFILTER_DEBUG is not set
295CONFIG_NETFILTER_NETLINK=m
296CONFIG_NETFILTER_NETLINK_QUEUE=m
297CONFIG_NETFILTER_NETLINK_LOG=m
344 298
345# 299#
346# IP: Netfilter Configuration 300# IP: Netfilter Configuration
@@ -348,11 +302,15 @@ CONFIG_NETFILTER=y
348CONFIG_IP_NF_CONNTRACK=m 302CONFIG_IP_NF_CONNTRACK=m
349CONFIG_IP_NF_CT_ACCT=y 303CONFIG_IP_NF_CT_ACCT=y
350CONFIG_IP_NF_CONNTRACK_MARK=y 304CONFIG_IP_NF_CONNTRACK_MARK=y
305CONFIG_IP_NF_CONNTRACK_EVENTS=y
306CONFIG_IP_NF_CONNTRACK_NETLINK=m
351# CONFIG_IP_NF_CT_PROTO_SCTP is not set 307# CONFIG_IP_NF_CT_PROTO_SCTP is not set
352CONFIG_IP_NF_FTP=m 308CONFIG_IP_NF_FTP=m
353CONFIG_IP_NF_IRC=m 309CONFIG_IP_NF_IRC=m
310# CONFIG_IP_NF_NETBIOS_NS is not set
354CONFIG_IP_NF_TFTP=m 311CONFIG_IP_NF_TFTP=m
355CONFIG_IP_NF_AMANDA=m 312CONFIG_IP_NF_AMANDA=m
313CONFIG_IP_NF_PPTP=m
356CONFIG_IP_NF_QUEUE=m 314CONFIG_IP_NF_QUEUE=m
357CONFIG_IP_NF_IPTABLES=m 315CONFIG_IP_NF_IPTABLES=m
358CONFIG_IP_NF_MATCH_LIMIT=m 316CONFIG_IP_NF_MATCH_LIMIT=m
@@ -376,9 +334,12 @@ CONFIG_IP_NF_MATCH_OWNER=m
376CONFIG_IP_NF_MATCH_ADDRTYPE=m 334CONFIG_IP_NF_MATCH_ADDRTYPE=m
377CONFIG_IP_NF_MATCH_REALM=m 335CONFIG_IP_NF_MATCH_REALM=m
378CONFIG_IP_NF_MATCH_SCTP=m 336CONFIG_IP_NF_MATCH_SCTP=m
337CONFIG_IP_NF_MATCH_DCCP=m
379CONFIG_IP_NF_MATCH_COMMENT=m 338CONFIG_IP_NF_MATCH_COMMENT=m
380CONFIG_IP_NF_MATCH_CONNMARK=m 339CONFIG_IP_NF_MATCH_CONNMARK=m
340CONFIG_IP_NF_MATCH_CONNBYTES=m
381CONFIG_IP_NF_MATCH_HASHLIMIT=m 341CONFIG_IP_NF_MATCH_HASHLIMIT=m
342CONFIG_IP_NF_MATCH_STRING=m
382CONFIG_IP_NF_FILTER=m 343CONFIG_IP_NF_FILTER=m
383CONFIG_IP_NF_TARGET_REJECT=m 344CONFIG_IP_NF_TARGET_REJECT=m
384CONFIG_IP_NF_TARGET_LOG=m 345CONFIG_IP_NF_TARGET_LOG=m
@@ -395,12 +356,14 @@ CONFIG_IP_NF_NAT_IRC=m
395CONFIG_IP_NF_NAT_FTP=m 356CONFIG_IP_NF_NAT_FTP=m
396CONFIG_IP_NF_NAT_TFTP=m 357CONFIG_IP_NF_NAT_TFTP=m
397CONFIG_IP_NF_NAT_AMANDA=m 358CONFIG_IP_NF_NAT_AMANDA=m
359CONFIG_IP_NF_NAT_PPTP=m
398CONFIG_IP_NF_MANGLE=m 360CONFIG_IP_NF_MANGLE=m
399CONFIG_IP_NF_TARGET_TOS=m 361CONFIG_IP_NF_TARGET_TOS=m
400CONFIG_IP_NF_TARGET_ECN=m 362CONFIG_IP_NF_TARGET_ECN=m
401CONFIG_IP_NF_TARGET_DSCP=m 363CONFIG_IP_NF_TARGET_DSCP=m
402CONFIG_IP_NF_TARGET_MARK=m 364CONFIG_IP_NF_TARGET_MARK=m
403CONFIG_IP_NF_TARGET_CLASSIFY=m 365CONFIG_IP_NF_TARGET_CLASSIFY=m
366CONFIG_IP_NF_TARGET_TTL=m
404CONFIG_IP_NF_TARGET_CONNMARK=m 367CONFIG_IP_NF_TARGET_CONNMARK=m
405CONFIG_IP_NF_TARGET_CLUSTERIP=m 368CONFIG_IP_NF_TARGET_CLUSTERIP=m
406CONFIG_IP_NF_RAW=m 369CONFIG_IP_NF_RAW=m
@@ -410,7 +373,7 @@ CONFIG_IP_NF_ARPFILTER=m
410CONFIG_IP_NF_ARP_MANGLE=m 373CONFIG_IP_NF_ARP_MANGLE=m
411 374
412# 375#
413# IPv6: Netfilter Configuration 376# IPv6: Netfilter Configuration (EXPERIMENTAL)
414# 377#
415CONFIG_IP6_NF_QUEUE=m 378CONFIG_IP6_NF_QUEUE=m
416CONFIG_IP6_NF_IPTABLES=m 379CONFIG_IP6_NF_IPTABLES=m
@@ -429,11 +392,16 @@ CONFIG_IP6_NF_MATCH_LENGTH=m
429CONFIG_IP6_NF_MATCH_EUI64=m 392CONFIG_IP6_NF_MATCH_EUI64=m
430CONFIG_IP6_NF_FILTER=m 393CONFIG_IP6_NF_FILTER=m
431CONFIG_IP6_NF_TARGET_LOG=m 394CONFIG_IP6_NF_TARGET_LOG=m
395CONFIG_IP6_NF_TARGET_REJECT=m
432CONFIG_IP6_NF_MANGLE=m 396CONFIG_IP6_NF_MANGLE=m
433CONFIG_IP6_NF_TARGET_MARK=m 397CONFIG_IP6_NF_TARGET_MARK=m
398CONFIG_IP6_NF_TARGET_HL=m
434CONFIG_IP6_NF_RAW=m 399CONFIG_IP6_NF_RAW=m
435CONFIG_XFRM=y 400
436CONFIG_XFRM_USER=m 401#
402# DCCP Configuration (EXPERIMENTAL)
403#
404# CONFIG_IP_DCCP is not set
437 405
438# 406#
439# SCTP Configuration (EXPERIMENTAL) 407# SCTP Configuration (EXPERIMENTAL)
@@ -456,10 +424,6 @@ CONFIG_SCTP_HMAC_MD5=y
456CONFIG_NET_DIVERT=y 424CONFIG_NET_DIVERT=y
457# CONFIG_ECONET is not set 425# CONFIG_ECONET is not set
458# CONFIG_WAN_ROUTER is not set 426# CONFIG_WAN_ROUTER is not set
459
460#
461# QoS and/or fair queueing
462#
463CONFIG_NET_SCHED=y 427CONFIG_NET_SCHED=y
464# CONFIG_NET_SCH_CLK_JIFFIES is not set 428# CONFIG_NET_SCH_CLK_JIFFIES is not set
465CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y 429CONFIG_NET_SCH_CLK_GETTIMEOFDAY=y
@@ -479,6 +443,7 @@ CONFIG_NET_SCH_INGRESS=m
479CONFIG_NET_QOS=y 443CONFIG_NET_QOS=y
480CONFIG_NET_ESTIMATOR=y 444CONFIG_NET_ESTIMATOR=y
481CONFIG_NET_CLS=y 445CONFIG_NET_CLS=y
446CONFIG_NET_CLS_BASIC=m
482CONFIG_NET_CLS_TCINDEX=m 447CONFIG_NET_CLS_TCINDEX=m
483CONFIG_NET_CLS_ROUTE4=m 448CONFIG_NET_CLS_ROUTE4=m
484CONFIG_NET_CLS_ROUTE=y 449CONFIG_NET_CLS_ROUTE=y
@@ -489,6 +454,7 @@ CONFIG_NET_CLS_U32=m
489# CONFIG_CLS_U32_MARK is not set 454# CONFIG_CLS_U32_MARK is not set
490CONFIG_NET_CLS_RSVP=m 455CONFIG_NET_CLS_RSVP=m
491CONFIG_NET_CLS_RSVP6=m 456CONFIG_NET_CLS_RSVP6=m
457# CONFIG_NET_EMATCH is not set
492# CONFIG_NET_CLS_ACT is not set 458# CONFIG_NET_CLS_ACT is not set
493CONFIG_NET_CLS_POLICE=y 459CONFIG_NET_CLS_POLICE=y
494 460
@@ -496,17 +462,153 @@ CONFIG_NET_CLS_POLICE=y
496# Network testing 462# Network testing
497# 463#
498# CONFIG_NET_PKTGEN is not set 464# CONFIG_NET_PKTGEN is not set
499# CONFIG_NETPOLL is not set
500# CONFIG_NET_POLL_CONTROLLER is not set
501# CONFIG_HAMRADIO is not set 465# CONFIG_HAMRADIO is not set
502# CONFIG_IRDA is not set 466# CONFIG_IRDA is not set
503# CONFIG_BT is not set 467# CONFIG_BT is not set
468CONFIG_IEEE80211=m
469# CONFIG_IEEE80211_DEBUG is not set
470CONFIG_IEEE80211_CRYPT_WEP=m
471CONFIG_IEEE80211_CRYPT_CCMP=m
472CONFIG_IEEE80211_CRYPT_TKIP=m
473
474#
475# Device Drivers
476#
477
478#
479# Generic Driver Options
480#
481CONFIG_STANDALONE=y
482CONFIG_PREVENT_FIRMWARE_BUILD=y
483# CONFIG_FW_LOADER is not set
484
485#
486# Connector - unified userspace <-> kernelspace linker
487#
488CONFIG_CONNECTOR=m
489
490#
491# Memory Technology Devices (MTD)
492#
493# CONFIG_MTD is not set
494
495#
496# Parallel port support
497#
498# CONFIG_PARPORT is not set
499
500#
501# Plug and Play support
502#
503
504#
505# Block devices
506#
507# CONFIG_BLK_DEV_COW_COMMON is not set
508# CONFIG_BLK_DEV_LOOP is not set
509# CONFIG_BLK_DEV_NBD is not set
510# CONFIG_BLK_DEV_RAM is not set
511CONFIG_BLK_DEV_RAM_COUNT=16
512# CONFIG_LBD is not set
513CONFIG_CDROM_PKTCDVD=m
514CONFIG_CDROM_PKTCDVD_BUFFERS=8
515# CONFIG_CDROM_PKTCDVD_WCACHE is not set
516
517#
518# IO Schedulers
519#
520CONFIG_IOSCHED_NOOP=y
521CONFIG_IOSCHED_AS=y
522CONFIG_IOSCHED_DEADLINE=y
523CONFIG_IOSCHED_CFQ=y
524CONFIG_ATA_OVER_ETH=m
525
526#
527# ATA/ATAPI/MFM/RLL support
528#
529# CONFIG_IDE is not set
530
531#
532# SCSI device support
533#
534CONFIG_RAID_ATTRS=m
535CONFIG_SCSI=y
536CONFIG_SCSI_PROC_FS=y
537
538#
539# SCSI support type (disk, tape, CD-ROM)
540#
541CONFIG_BLK_DEV_SD=y
542CONFIG_CHR_DEV_ST=y
543# CONFIG_CHR_DEV_OSST is not set
544CONFIG_BLK_DEV_SR=y
545# CONFIG_BLK_DEV_SR_VENDOR is not set
546# CONFIG_CHR_DEV_SG is not set
547CONFIG_CHR_DEV_SCH=m
548
549#
550# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
551#
552# CONFIG_SCSI_MULTI_LUN is not set
553CONFIG_SCSI_CONSTANTS=y
554# CONFIG_SCSI_LOGGING is not set
555
556#
557# SCSI Transport Attributes
558#
559CONFIG_SCSI_SPI_ATTRS=m
560# CONFIG_SCSI_FC_ATTRS is not set
561CONFIG_SCSI_ISCSI_ATTRS=m
562CONFIG_SCSI_SAS_ATTRS=m
563
564#
565# SCSI low-level drivers
566#
567CONFIG_SGIWD93_SCSI=y
568# CONFIG_SCSI_SATA is not set
569# CONFIG_SCSI_DEBUG is not set
570
571#
572# Multi-device support (RAID and LVM)
573#
574# CONFIG_MD is not set
575
576#
577# Fusion MPT device support
578#
579# CONFIG_FUSION is not set
580
581#
582# IEEE 1394 (FireWire) support
583#
584
585#
586# I2O device support
587#
588
589#
590# Network device support
591#
504CONFIG_NETDEVICES=y 592CONFIG_NETDEVICES=y
505CONFIG_DUMMY=m 593CONFIG_DUMMY=m
506CONFIG_BONDING=m 594CONFIG_BONDING=m
507CONFIG_EQUALIZER=m 595CONFIG_EQUALIZER=m
508CONFIG_TUN=m 596CONFIG_TUN=m
509CONFIG_ETHERTAP=m 597
598#
599# PHY device support
600#
601CONFIG_PHYLIB=m
602CONFIG_PHYCONTROL=y
603
604#
605# MII PHY device drivers
606#
607CONFIG_MARVELL_PHY=m
608CONFIG_DAVICOM_PHY=m
609CONFIG_QSEMI_PHY=m
610CONFIG_LXT_PHY=m
611CONFIG_CICADA_PHY=m
510 612
511# 613#
512# Ethernet (10 or 100Mbit) 614# Ethernet (10 or 100Mbit)
@@ -540,6 +642,8 @@ CONFIG_SGISEEQ=y
540# CONFIG_SLIP is not set 642# CONFIG_SLIP is not set
541# CONFIG_SHAPER is not set 643# CONFIG_SHAPER is not set
542# CONFIG_NETCONSOLE is not set 644# CONFIG_NETCONSOLE is not set
645# CONFIG_NETPOLL is not set
646# CONFIG_NET_POLL_CONTROLLER is not set
543 647
544# 648#
545# ISDN subsystem 649# ISDN subsystem
@@ -569,18 +673,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
569# CONFIG_INPUT_EVBUG is not set 673# CONFIG_INPUT_EVBUG is not set
570 674
571# 675#
572# Input I/O drivers
573#
574# CONFIG_GAMEPORT is not set
575CONFIG_SOUND_GAMEPORT=y
576CONFIG_SERIO=y
577CONFIG_SERIO_I8042=y
578CONFIG_SERIO_SERPORT=y
579# CONFIG_SERIO_CT82C710 is not set
580CONFIG_SERIO_LIBPS2=y
581CONFIG_SERIO_RAW=m
582
583#
584# Input Device Drivers 676# Input Device Drivers
585# 677#
586CONFIG_INPUT_KEYBOARD=y 678CONFIG_INPUT_KEYBOARD=y
@@ -598,6 +690,16 @@ CONFIG_MOUSE_SERIAL=m
598# CONFIG_INPUT_MISC is not set 690# CONFIG_INPUT_MISC is not set
599 691
600# 692#
693# Hardware I/O ports
694#
695CONFIG_SERIO=y
696CONFIG_SERIO_I8042=y
697CONFIG_SERIO_SERPORT=y
698CONFIG_SERIO_LIBPS2=y
699CONFIG_SERIO_RAW=m
700# CONFIG_GAMEPORT is not set
701
702#
601# Character devices 703# Character devices
602# 704#
603CONFIG_VT=y 705CONFIG_VT=y
@@ -644,11 +746,14 @@ CONFIG_SGI_DS1286=m
644# 746#
645# Ftape, the floppy tape device driver 747# Ftape, the floppy tape device driver
646# 748#
647# CONFIG_DRM is not set
648CONFIG_RAW_DRIVER=m 749CONFIG_RAW_DRIVER=m
649CONFIG_MAX_RAW_DEVS=256 750CONFIG_MAX_RAW_DEVS=256
650 751
651# 752#
753# TPM devices
754#
755
756#
652# I2C support 757# I2C support
653# 758#
654# CONFIG_I2C is not set 759# CONFIG_I2C is not set
@@ -659,10 +764,20 @@ CONFIG_MAX_RAW_DEVS=256
659# CONFIG_W1 is not set 764# CONFIG_W1 is not set
660 765
661# 766#
767# Hardware Monitoring support
768#
769# CONFIG_HWMON is not set
770# CONFIG_HWMON_VID is not set
771
772#
662# Misc devices 773# Misc devices
663# 774#
664 775
665# 776#
777# Multimedia Capabilities Port drivers
778#
779
780#
666# Multimedia devices 781# Multimedia devices
667# 782#
668# CONFIG_VIDEO_DEV is not set 783# CONFIG_VIDEO_DEV is not set
@@ -693,7 +808,6 @@ CONFIG_LOGO=y
693# CONFIG_LOGO_LINUX_VGA16 is not set 808# CONFIG_LOGO_LINUX_VGA16 is not set
694# CONFIG_LOGO_LINUX_CLUT224 is not set 809# CONFIG_LOGO_LINUX_CLUT224 is not set
695CONFIG_LOGO_SGI_CLUT224=y 810CONFIG_LOGO_SGI_CLUT224=y
696# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
697 811
698# 812#
699# Sound 813# Sound
@@ -707,10 +821,6 @@ CONFIG_LOGO_SGI_CLUT224=y
707# CONFIG_USB_ARCH_HAS_OHCI is not set 821# CONFIG_USB_ARCH_HAS_OHCI is not set
708 822
709# 823#
710# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
711#
712
713#
714# USB Gadget Support 824# USB Gadget Support
715# 825#
716# CONFIG_USB_GADGET is not set 826# CONFIG_USB_GADGET is not set
@@ -723,13 +833,17 @@ CONFIG_LOGO_SGI_CLUT224=y
723# 833#
724# InfiniBand support 834# InfiniBand support
725# 835#
726# CONFIG_INFINIBAND is not set 836
837#
838# SN Devices
839#
727 840
728# 841#
729# File systems 842# File systems
730# 843#
731CONFIG_EXT2_FS=m 844CONFIG_EXT2_FS=m
732# CONFIG_EXT2_FS_XATTR is not set 845# CONFIG_EXT2_FS_XATTR is not set
846# CONFIG_EXT2_FS_XIP is not set
733CONFIG_EXT3_FS=y 847CONFIG_EXT3_FS=y
734CONFIG_EXT3_FS_XATTR=y 848CONFIG_EXT3_FS_XATTR=y
735CONFIG_EXT3_FS_POSIX_ACL=y 849CONFIG_EXT3_FS_POSIX_ACL=y
@@ -741,12 +855,14 @@ CONFIG_FS_MBCACHE=y
741# CONFIG_JFS_FS is not set 855# CONFIG_JFS_FS is not set
742CONFIG_FS_POSIX_ACL=y 856CONFIG_FS_POSIX_ACL=y
743CONFIG_XFS_FS=m 857CONFIG_XFS_FS=m
744# CONFIG_XFS_RT is not set 858CONFIG_XFS_EXPORT=y
745CONFIG_XFS_QUOTA=y 859CONFIG_XFS_QUOTA=m
746CONFIG_XFS_SECURITY=y 860CONFIG_XFS_SECURITY=y
747# CONFIG_XFS_POSIX_ACL is not set 861# CONFIG_XFS_POSIX_ACL is not set
862# CONFIG_XFS_RT is not set
748CONFIG_MINIX_FS=m 863CONFIG_MINIX_FS=m
749# CONFIG_ROMFS_FS is not set 864# CONFIG_ROMFS_FS is not set
865CONFIG_INOTIFY=y
750CONFIG_QUOTA=y 866CONFIG_QUOTA=y
751# CONFIG_QFMT_V1 is not set 867# CONFIG_QFMT_V1 is not set
752CONFIG_QFMT_V2=m 868CONFIG_QFMT_V2=m
@@ -754,6 +870,7 @@ CONFIG_QUOTACTL=y
754CONFIG_DNOTIFY=y 870CONFIG_DNOTIFY=y
755CONFIG_AUTOFS_FS=m 871CONFIG_AUTOFS_FS=m
756CONFIG_AUTOFS4_FS=m 872CONFIG_AUTOFS4_FS=m
873CONFIG_FUSE_FS=m
757 874
758# 875#
759# CD-ROM/DVD Filesystems 876# CD-ROM/DVD Filesystems
@@ -781,12 +898,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
781CONFIG_PROC_FS=y 898CONFIG_PROC_FS=y
782CONFIG_PROC_KCORE=y 899CONFIG_PROC_KCORE=y
783CONFIG_SYSFS=y 900CONFIG_SYSFS=y
784# CONFIG_DEVFS_FS is not set
785CONFIG_DEVPTS_FS_XATTR=y
786CONFIG_DEVPTS_FS_SECURITY=y
787# CONFIG_TMPFS is not set 901# CONFIG_TMPFS is not set
788# CONFIG_HUGETLB_PAGE is not set 902# CONFIG_HUGETLB_PAGE is not set
789CONFIG_RAMFS=y 903CONFIG_RAMFS=y
904CONFIG_RELAYFS_FS=m
790 905
791# 906#
792# Miscellaneous filesystems 907# Miscellaneous filesystems
@@ -811,15 +926,20 @@ CONFIG_UFS_FS=m
811# 926#
812CONFIG_NFS_FS=m 927CONFIG_NFS_FS=m
813CONFIG_NFS_V3=y 928CONFIG_NFS_V3=y
929CONFIG_NFS_V3_ACL=y
814# CONFIG_NFS_V4 is not set 930# CONFIG_NFS_V4 is not set
815# CONFIG_NFS_DIRECTIO is not set 931# CONFIG_NFS_DIRECTIO is not set
816CONFIG_NFSD=m 932CONFIG_NFSD=m
933CONFIG_NFSD_V2_ACL=y
817CONFIG_NFSD_V3=y 934CONFIG_NFSD_V3=y
935CONFIG_NFSD_V3_ACL=y
818# CONFIG_NFSD_V4 is not set 936# CONFIG_NFSD_V4 is not set
819CONFIG_NFSD_TCP=y 937CONFIG_NFSD_TCP=y
820CONFIG_LOCKD=m 938CONFIG_LOCKD=m
821CONFIG_LOCKD_V4=y 939CONFIG_LOCKD_V4=y
822CONFIG_EXPORTFS=m 940CONFIG_EXPORTFS=m
941CONFIG_NFS_ACL_SUPPORT=m
942CONFIG_NFS_COMMON=y
823CONFIG_SUNRPC=m 943CONFIG_SUNRPC=m
824CONFIG_SUNRPC_GSS=m 944CONFIG_SUNRPC_GSS=m
825CONFIG_RPCSEC_GSS_KRB5=m 945CONFIG_RPCSEC_GSS_KRB5=m
@@ -835,6 +955,7 @@ CONFIG_CIFS=m
835CONFIG_CODA_FS=m 955CONFIG_CODA_FS=m
836# CONFIG_CODA_FS_OLD_API is not set 956# CONFIG_CODA_FS_OLD_API is not set
837# CONFIG_AFS_FS is not set 957# CONFIG_AFS_FS is not set
958# CONFIG_9P_FS is not set
838 959
839# 960#
840# Partition Types 961# Partition Types
@@ -908,7 +1029,9 @@ CONFIG_NLS_UTF8=m
908# 1029#
909# Kernel hacking 1030# Kernel hacking
910# 1031#
1032# CONFIG_PRINTK_TIME is not set
911# CONFIG_DEBUG_KERNEL is not set 1033# CONFIG_DEBUG_KERNEL is not set
1034CONFIG_LOG_BUF_SHIFT=14
912CONFIG_CROSSCOMPILE=y 1035CONFIG_CROSSCOMPILE=y
913CONFIG_CMDLINE="" 1036CONFIG_CMDLINE=""
914 1037
@@ -931,6 +1054,7 @@ CONFIG_CRYPTO_SHA1=m
931CONFIG_CRYPTO_SHA256=m 1054CONFIG_CRYPTO_SHA256=m
932CONFIG_CRYPTO_SHA512=m 1055CONFIG_CRYPTO_SHA512=m
933CONFIG_CRYPTO_WP512=m 1056CONFIG_CRYPTO_WP512=m
1057CONFIG_CRYPTO_TGR192=m
934CONFIG_CRYPTO_DES=m 1058CONFIG_CRYPTO_DES=m
935CONFIG_CRYPTO_BLOWFISH=m 1059CONFIG_CRYPTO_BLOWFISH=m
936CONFIG_CRYPTO_TWOFISH=m 1060CONFIG_CRYPTO_TWOFISH=m
@@ -942,10 +1066,10 @@ CONFIG_CRYPTO_TEA=m
942CONFIG_CRYPTO_ARC4=m 1066CONFIG_CRYPTO_ARC4=m
943CONFIG_CRYPTO_KHAZAD=m 1067CONFIG_CRYPTO_KHAZAD=m
944CONFIG_CRYPTO_ANUBIS=m 1068CONFIG_CRYPTO_ANUBIS=m
945CONFIG_CRYPTO_DEFLATE=y 1069CONFIG_CRYPTO_DEFLATE=m
946CONFIG_CRYPTO_MICHAEL_MIC=m 1070CONFIG_CRYPTO_MICHAEL_MIC=m
947CONFIG_CRYPTO_CRC32C=m 1071CONFIG_CRYPTO_CRC32C=m
948CONFIG_CRYPTO_TEST=m 1072# CONFIG_CRYPTO_TEST is not set
949 1073
950# 1074#
951# Hardware crypto devices 1075# Hardware crypto devices
@@ -955,9 +1079,12 @@ CONFIG_CRYPTO_TEST=m
955# Library routines 1079# Library routines
956# 1080#
957# CONFIG_CRC_CCITT is not set 1081# CONFIG_CRC_CCITT is not set
1082CONFIG_CRC16=m
958CONFIG_CRC32=m 1083CONFIG_CRC32=m
959CONFIG_LIBCRC32C=m 1084CONFIG_LIBCRC32C=m
960CONFIG_ZLIB_INFLATE=y 1085CONFIG_ZLIB_INFLATE=m
961CONFIG_ZLIB_DEFLATE=y 1086CONFIG_ZLIB_DEFLATE=m
962CONFIG_GENERIC_HARDIRQS=y 1087CONFIG_TEXTSEARCH=y
963CONFIG_GENERIC_IRQ_PROBE=y 1088CONFIG_TEXTSEARCH_KMP=m
1089CONFIG_TEXTSEARCH_BM=m
1090CONFIG_TEXTSEARCH_FSM=m
diff --git a/arch/mips/galileo-boards/ev96100/setup.c b/arch/mips/galileo-boards/ev96100/setup.c
index 28bd908c6d55..78dbb18edeb8 100644
--- a/arch/mips/galileo-boards/ev96100/setup.c
+++ b/arch/mips/galileo-boards/ev96100/setup.c
@@ -55,7 +55,7 @@ extern void mips_reboot_setup(void);
55 55
56unsigned char mac_0_1[12]; 56unsigned char mac_0_1[12];
57 57
58static void __init ev96100_setup(void) 58void __init plat_setup(void)
59{ 59{
60 unsigned int config = read_c0_config(); 60 unsigned int config = read_c0_config();
61 unsigned int status = read_c0_status(); 61 unsigned int status = read_c0_status();
@@ -142,8 +142,6 @@ static void __init ev96100_setup(void)
142 tmp = GT_READ(GT_PCI0_CFGDATA_OFS); 142 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
143} 143}
144 144
145early_initcall(ev96100_setup);
146
147unsigned short get_gt_devid(void) 145unsigned short get_gt_devid(void)
148{ 146{
149 u32 gt_devid; 147 u32 gt_devid;
diff --git a/arch/mips/gt64120/ev64120/Kconfig b/arch/mips/gt64120/ev64120/Kconfig
new file mode 100644
index 000000000000..d691762cb0f7
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/Kconfig
@@ -0,0 +1,3 @@
1config EVB_PCI1
2 bool "Enable Second PCI (PCI1)"
3 depends on MIPS_EV64120
diff --git a/arch/mips/gt64120/ev64120/setup.c b/arch/mips/gt64120/ev64120/setup.c
index dba0961400cc..98b5a96cc039 100644
--- a/arch/mips/gt64120/ev64120/setup.c
+++ b/arch/mips/gt64120/ev64120/setup.c
@@ -69,7 +69,7 @@ unsigned long __init prom_free_prom_memory(void)
69 */ 69 */
70extern void gt64120_time_init(void); 70extern void gt64120_time_init(void);
71 71
72static void __init ev64120_setup(void) 72void __init plat_setup(void)
73{ 73{
74 _machine_restart = galileo_machine_restart; 74 _machine_restart = galileo_machine_restart;
75 _machine_halt = galileo_machine_halt; 75 _machine_halt = galileo_machine_halt;
@@ -79,8 +79,6 @@ static void __init ev64120_setup(void)
79 set_io_port_base(KSEG1); 79 set_io_port_base(KSEG1);
80} 80}
81 81
82early_initcall(ev64120_setup);
83
84const char *get_system_type(void) 82const char *get_system_type(void)
85{ 83{
86 return "Galileo EV64120A"; 84 return "Galileo EV64120A";
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
index d610f8c17c81..0d07c33112d0 100644
--- a/arch/mips/gt64120/momenco_ocelot/setup.c
+++ b/arch/mips/gt64120/momenco_ocelot/setup.c
@@ -150,7 +150,7 @@ void PMON_v2_setup()
150 gt64120_base = 0xe0000000; 150 gt64120_base = 0xe0000000;
151} 151}
152 152
153static void __init momenco_ocelot_setup(void) 153void __init plat_setup(void)
154{ 154{
155 void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); 155 void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
156 unsigned int tmpword; 156 unsigned int tmpword;
@@ -307,8 +307,6 @@ static void __init momenco_ocelot_setup(void)
307 GT_WRITE(GT_DEV_B3_OFS, 0xfef73); 307 GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
308} 308}
309 309
310early_initcall(momenco_ocelot_setup);
311
312extern int rm7k_tcache_enabled; 310extern int rm7k_tcache_enabled;
313/* 311/*
314 * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() 312 * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
diff --git a/arch/mips/ite-boards/Kconfig b/arch/mips/ite-boards/Kconfig
new file mode 100644
index 000000000000..a6d59ad8f846
--- /dev/null
+++ b/arch/mips/ite-boards/Kconfig
@@ -0,0 +1,8 @@
1config IT8172_REVC
2 bool "Support for older IT8172 (Rev C)"
3 depends on MIPS_ITE8172
4 help
5 Say Y here to support the older, Revision C version of the Integrated
6 Technology Express, Inc. ITE8172 SBC. Vendor page at
7 <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
8 board at <http://www.mvista.com/partners/semiconductor/ite.html>.
diff --git a/arch/mips/ite-boards/generic/irq.c b/arch/mips/ite-boards/generic/irq.c
index cb71b9024d6f..e67f96129491 100644
--- a/arch/mips/ite-boards/generic/irq.c
+++ b/arch/mips/ite-boards/generic/irq.c
@@ -138,14 +138,13 @@ static void end_ite_irq(unsigned int irq)
138} 138}
139 139
140static struct hw_interrupt_type it8172_irq_type = { 140static struct hw_interrupt_type it8172_irq_type = {
141 "ITE8172", 141 .typename = "ITE8172",
142 startup_ite_irq, 142 .startup = startup_ite_irq,
143 shutdown_ite_irq, 143 .shutdown = shutdown_ite_irq,
144 enable_it8172_irq, 144 .enable = enable_it8172_irq,
145 disable_it8172_irq, 145 .disable = disable_it8172_irq,
146 mask_and_ack_ite_irq, 146 .ack = mask_and_ack_ite_irq,
147 end_ite_irq, 147 .end = end_ite_irq,
148 NULL
149}; 148};
150 149
151 150
@@ -159,13 +158,13 @@ static void ack_none(unsigned int irq) { }
159#define end_none enable_none 158#define end_none enable_none
160 159
161static struct hw_interrupt_type cp0_irq_type = { 160static struct hw_interrupt_type cp0_irq_type = {
162 "CP0 Count", 161 .typename = "CP0 Count",
163 startup_none, 162 .startup = startup_none,
164 shutdown_none, 163 .shutdown = shutdown_none,
165 enable_none, 164 .enable = enable_none,
166 disable_none, 165 .disable = disable_none,
167 ack_none, 166 .ack = ack_none,
168 end_none 167 .end = end_none
169}; 168};
170 169
171void enable_cpu_timer(void) 170void enable_cpu_timer(void)
@@ -182,7 +181,6 @@ void __init arch_init_irq(void)
182 int i; 181 int i;
183 unsigned long flags; 182 unsigned long flags;
184 183
185 memset(irq_desc, 0, sizeof(irq_desc));
186 set_except_vector(0, it8172_IRQ); 184 set_except_vector(0, it8172_IRQ);
187 185
188 /* mask all interrupts */ 186 /* mask all interrupts */
diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c
index a5f6d84bc181..062429dd7ca0 100644
--- a/arch/mips/ite-boards/generic/it8172_setup.c
+++ b/arch/mips/ite-boards/generic/it8172_setup.c
@@ -105,7 +105,7 @@ void __init it8172_init_ram_resource(unsigned long memsize)
105 it8172_resources.ram.end = memsize; 105 it8172_resources.ram.end = memsize;
106} 106}
107 107
108static void __init it8172_setup(void) 108void __init plat_setup(void)
109{ 109{
110 unsigned short dsr; 110 unsigned short dsr;
111 char *argptr; 111 char *argptr;
@@ -251,8 +251,6 @@ static void __init it8172_setup(void)
251#endif /* CONFIG_IT8172_SCR1 */ 251#endif /* CONFIG_IT8172_SCR1 */
252} 252}
253 253
254early_initcall(it8172_setup);
255
256#ifdef CONFIG_SERIO_I8042 254#ifdef CONFIG_SERIO_I8042
257/* 255/*
258 * According to the ITE Special BIOS Note for waking up the 256 * According to the ITE Special BIOS Note for waking up the
diff --git a/arch/mips/jazz/Kconfig b/arch/mips/jazz/Kconfig
new file mode 100644
index 000000000000..1f372b0d2559
--- /dev/null
+++ b/arch/mips/jazz/Kconfig
@@ -0,0 +1,33 @@
1config ACER_PICA_61
2 bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)"
3 depends on MACH_JAZZ && EXPERIMENTAL
4 select DMA_NONCOHERENT
5 select SYS_SUPPORTS_LITTLE_ENDIAN
6 help
7 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
8 kernel that runs on these, say Y here. For details about Linux on
9 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
10 <http://www.linux-mips.org/>.
11
12config MIPS_MAGNUM_4000
13 bool "Support for MIPS Magnum 4000"
14 depends on MACH_JAZZ
15 select DMA_NONCOHERENT
16 select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL
17 select SYS_SUPPORTS_LITTLE_ENDIAN
18 help
19 This is a machine with a R4000 100 MHz CPU. To compile a Linux
20 kernel that runs on these, say Y here. For details about Linux on
21 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
22 <http://www.linux-mips.org/>.
23
24config OLIVETTI_M700
25 bool "Support for Olivetti M700-10"
26 depends on MACH_JAZZ
27 select DMA_NONCOHERENT
28 select SYS_SUPPORTS_LITTLE_ENDIAN
29 help
30 This is a machine with a R4000 100 MHz CPU. To compile a Linux
31 kernel that runs on these, say Y here. For details about Linux on
32 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
33 <http://www.linux-mips.org/>.
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 0b608fa98d5a..b309b1bcf2e8 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -58,14 +58,13 @@ static void end_r4030_irq(unsigned int irq)
58} 58}
59 59
60static struct hw_interrupt_type r4030_irq_type = { 60static struct hw_interrupt_type r4030_irq_type = {
61 "R4030", 61 .typename = "R4030",
62 startup_r4030_irq, 62 .startup = startup_r4030_irq,
63 shutdown_r4030_irq, 63 .shutdown = shutdown_r4030_irq,
64 enable_r4030_irq, 64 .enable = enable_r4030_irq,
65 disable_r4030_irq, 65 .disable = disable_r4030_irq,
66 mask_and_ack_r4030_irq, 66 .ack = mask_and_ack_r4030_irq,
67 end_r4030_irq, 67 .end = end_r4030_irq,
68 NULL
69}; 68};
70 69
71void __init init_r4030_ints(void) 70void __init init_r4030_ints(void)
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index fccb06fe209d..044df9d4ab7c 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -50,7 +50,7 @@ static struct resource jazz_io_resources[] = {
50 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, 50 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
51}; 51};
52 52
53static void __init jazz_setup(void) 53void __init plat_setup(void)
54{ 54{
55 int i; 55 int i;
56 56
@@ -97,5 +97,3 @@ static void __init jazz_setup(void)
97 97
98 vdma_init(); 98 vdma_init();
99} 99}
100
101early_initcall(jazz_setup);
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index b9799b86fc79..7cbe14483f13 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -412,13 +412,13 @@ void __init arch_init_irq(void)
412} 412}
413 413
414static hw_irq_controller jmr3927_irq_controller = { 414static hw_irq_controller jmr3927_irq_controller = {
415 "jmr3927_irq", 415 .typename = "jmr3927_irq",
416 jmr3927_irq_startup, 416 .startup = jmr3927_irq_startup,
417 jmr3927_irq_shutdown, 417 .shutdown = jmr3927_irq_shutdown,
418 jmr3927_irq_enable, 418 .enable = jmr3927_irq_enable,
419 jmr3927_irq_disable, 419 .disable = jmr3927_irq_disable,
420 jmr3927_irq_ack, 420 .ack = jmr3927_irq_ack,
421 jmr3927_irq_end, 421 .end = jmr3927_irq_end,
422}; 422};
423 423
424void jmr3927_irq_init(u32 irq_base) 424void jmr3927_irq_init(u32 irq_base)
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index 32039bb2f440..3e2fbdc66097 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -44,6 +44,11 @@
44#include <linux/ioport.h> 44#include <linux/ioport.h>
45#include <linux/param.h> /* for HZ */ 45#include <linux/param.h> /* for HZ */
46#include <linux/delay.h> 46#include <linux/delay.h>
47#ifdef CONFIG_SERIAL_TXX9
48#include <linux/tty.h>
49#include <linux/serial.h>
50#include <linux/serial_core.h>
51#endif
47 52
48#include <asm/addrspace.h> 53#include <asm/addrspace.h>
49#include <asm/time.h> 54#include <asm/time.h>
@@ -193,7 +198,7 @@ static void jmr3927_board_init(void);
193extern struct resource pci_io_resource; 198extern struct resource pci_io_resource;
194extern struct resource pci_mem_resource; 199extern struct resource pci_mem_resource;
195 200
196static void __init jmr3927_setup(void) 201void __init plat_setup(void)
197{ 202{
198 char *argptr; 203 char *argptr;
199 204
@@ -211,8 +216,8 @@ static void __init jmr3927_setup(void)
211 */ 216 */
212 ioport_resource.start = pci_io_resource.start; 217 ioport_resource.start = pci_io_resource.start;
213 ioport_resource.end = pci_io_resource.end; 218 ioport_resource.end = pci_io_resource.end;
214 iomem_resource.start = pci_mem_resource.start; 219 iomem_resource.start = 0;
215 iomem_resource.end = pci_mem_resource.end; 220 iomem_resource.end = 0xffffffff;
216 221
217 /* Reboot on panic */ 222 /* Reboot on panic */
218 panic_timeout = 180; 223 panic_timeout = 180;
@@ -265,18 +270,35 @@ static void __init jmr3927_setup(void)
265 strcat(argptr, " ip=bootp"); 270 strcat(argptr, " ip=bootp");
266 } 271 }
267 272
268#ifdef CONFIG_TXX927_SERIAL_CONSOLE 273#ifdef CONFIG_SERIAL_TXX9
274 {
275 extern int early_serial_txx9_setup(struct uart_port *port);
276 int i;
277 struct uart_port req;
278 for(i = 0; i < 2; i++) {
279 memset(&req, 0, sizeof(req));
280 req.line = i;
281 req.iotype = UPIO_MEM;
282 req.membase = (char *)TX3927_SIO_REG(i);
283 req.mapbase = TX3927_SIO_REG(i);
284 req.irq = i == 0 ?
285 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
286 if (i == 0)
287 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
288 req.uartclk = JMR3927_IMCLK;
289 early_serial_txx9_setup(&req);
290 }
291 }
292#ifdef CONFIG_SERIAL_TXX9_CONSOLE
269 argptr = prom_getcmdline(); 293 argptr = prom_getcmdline();
270 if ((argptr = strstr(argptr, "console=")) == NULL) { 294 if ((argptr = strstr(argptr, "console=")) == NULL) {
271 argptr = prom_getcmdline(); 295 argptr = prom_getcmdline();
272 strcat(argptr, " console=ttyS1,115200"); 296 strcat(argptr, " console=ttyS1,115200");
273 } 297 }
274#endif 298#endif
299#endif
275} 300}
276 301
277early_initcall(jmr3927_setup);
278
279
280static void tx3927_setup(void); 302static void tx3927_setup(void);
281 303
282#ifdef CONFIG_PCI 304#ifdef CONFIG_PCI
@@ -335,7 +357,7 @@ static void __init jmr3927_board_init(void)
335 jmr3927_io_dipsw()); 357 jmr3927_io_dipsw());
336} 358}
337 359
338static void __init tx3927_setup(void) 360void __init plat_setup(void)
339{ 361{
340 int i; 362 int i;
341 363
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index d3303584fbd1..72f2126ad19d 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -11,11 +11,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
11binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ 11binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
12 irix5sys.o sysirix.o 12 irix5sys.o sysirix.o
13 13
14ifdef CONFIG_MODULES 14obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
15obj-y += mips_ksyms.o module.o
16obj-$(CONFIG_32BIT) += module-elf32.o
17obj-$(CONFIG_64BIT) += module-elf64.o
18endif
19 15
20obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o 16obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
21obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o 17obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
@@ -38,12 +34,18 @@ obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
38 34
39obj-$(CONFIG_SMP) += smp.o 35obj-$(CONFIG_SMP) += smp.o
40 36
37obj-$(CONFIG_MIPS_MT_SMP) += smp_mt.o
38
39obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
40obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
41
41obj-$(CONFIG_NO_ISA) += dma-no-isa.o 42obj-$(CONFIG_NO_ISA) += dma-no-isa.o
42obj-$(CONFIG_I8259) += i8259.o 43obj-$(CONFIG_I8259) += i8259.o
43obj-$(CONFIG_IRQ_CPU) += irq_cpu.o 44obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
44obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o 45obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
45obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o 46obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
46obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o 47obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o
48obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o
47 49
48obj-$(CONFIG_32BIT) += scall32-o32.o 50obj-$(CONFIG_32BIT) += scall32-o32.o
49obj-$(CONFIG_64BIT) += scall64-64.o 51obj-$(CONFIG_64BIT) += scall64-64.o
@@ -57,8 +59,6 @@ obj-$(CONFIG_PROC_FS) += proc.o
57 59
58obj-$(CONFIG_64BIT) += cpu-bugs64.o 60obj-$(CONFIG_64BIT) += cpu-bugs64.o
59 61
60obj-$(CONFIG_GEN_RTC) += genrtc.o
61
62CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) 62CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
63CFLAGS_ioctl32.o += -Ifs/ 63CFLAGS_ioctl32.o += -Ifs/
64 64
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 2c11abb5a406..ca6b03c773be 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -95,6 +95,7 @@ void output_thread_info_defines(void)
95 offset("#define TI_PRE_COUNT ", struct thread_info, preempt_count); 95 offset("#define TI_PRE_COUNT ", struct thread_info, preempt_count);
96 offset("#define TI_ADDR_LIMIT ", struct thread_info, addr_limit); 96 offset("#define TI_ADDR_LIMIT ", struct thread_info, addr_limit);
97 offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block); 97 offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block);
98 offset("#define TI_TP_VALUE ", struct thread_info, tp_value);
98 constant("#define _THREAD_SIZE_ORDER ", THREAD_SIZE_ORDER); 99 constant("#define _THREAD_SIZE_ORDER ", THREAD_SIZE_ORDER);
99 constant("#define _THREAD_SIZE ", THREAD_SIZE); 100 constant("#define _THREAD_SIZE ", THREAD_SIZE);
100 constant("#define _THREAD_MASK ", THREAD_MASK); 101 constant("#define _THREAD_MASK ", THREAD_MASK);
@@ -240,6 +241,7 @@ void output_mm_defines(void)
240 linefeed; 241 linefeed;
241} 242}
242 243
244#ifdef CONFIG_32BIT
243void output_sc_defines(void) 245void output_sc_defines(void)
244{ 246{
245 text("/* Linux sigcontext offsets. */"); 247 text("/* Linux sigcontext offsets. */");
@@ -251,10 +253,29 @@ void output_sc_defines(void)
251 offset("#define SC_STATUS ", struct sigcontext, sc_status); 253 offset("#define SC_STATUS ", struct sigcontext, sc_status);
252 offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); 254 offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr);
253 offset("#define SC_FPC_EIR ", struct sigcontext, sc_fpc_eir); 255 offset("#define SC_FPC_EIR ", struct sigcontext, sc_fpc_eir);
254 offset("#define SC_CAUSE ", struct sigcontext, sc_cause); 256 offset("#define SC_HI1 ", struct sigcontext, sc_hi1);
255 offset("#define SC_BADVADDR ", struct sigcontext, sc_badvaddr); 257 offset("#define SC_LO1 ", struct sigcontext, sc_lo1);
258 offset("#define SC_HI2 ", struct sigcontext, sc_hi2);
259 offset("#define SC_LO2 ", struct sigcontext, sc_lo2);
260 offset("#define SC_HI3 ", struct sigcontext, sc_hi3);
261 offset("#define SC_LO3 ", struct sigcontext, sc_lo3);
256 linefeed; 262 linefeed;
257} 263}
264#endif
265
266#ifdef CONFIG_64BIT
267void output_sc_defines(void)
268{
269 text("/* Linux sigcontext offsets. */");
270 offset("#define SC_REGS ", struct sigcontext, sc_regs);
271 offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs);
272 offset("#define SC_MDHI ", struct sigcontext, sc_hi);
273 offset("#define SC_MDLO ", struct sigcontext, sc_lo);
274 offset("#define SC_PC ", struct sigcontext, sc_pc);
275 offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr);
276 linefeed;
277}
278#endif
258 279
259#ifdef CONFIG_MIPS32_COMPAT 280#ifdef CONFIG_MIPS32_COMPAT
260void output_sc32_defines(void) 281void output_sc32_defines(void)
diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c
index 6b645fbb1ddc..d8e2674a1543 100644
--- a/arch/mips/kernel/binfmt_elfn32.c
+++ b/arch/mips/kernel/binfmt_elfn32.c
@@ -52,7 +52,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
52 52
53#include <asm/processor.h> 53#include <asm/processor.h>
54#include <linux/module.h> 54#include <linux/module.h>
55#include <linux/config.h>
56#include <linux/elfcore.h> 55#include <linux/elfcore.h>
57#include <linux/compat.h> 56#include <linux/compat.h>
58 57
@@ -116,4 +115,7 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)");
116#undef MODULE_DESCRIPTION 115#undef MODULE_DESCRIPTION
117#undef MODULE_AUTHOR 116#undef MODULE_AUTHOR
118 117
118#undef TASK_SIZE
119#define TASK_SIZE TASK_SIZE32
120
119#include "../../../fs/binfmt_elf.c" 121#include "../../../fs/binfmt_elf.c"
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index b4075e99c452..cec5f327e360 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -54,7 +54,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
54 54
55#include <asm/processor.h> 55#include <asm/processor.h>
56#include <linux/module.h> 56#include <linux/module.h>
57#include <linux/config.h>
58#include <linux/elfcore.h> 57#include <linux/elfcore.h>
59#include <linux/compat.h> 58#include <linux/compat.h>
60 59
@@ -98,7 +97,7 @@ struct elf_prpsinfo32
98#define init_elf_binfmt init_elf32_binfmt 97#define init_elf_binfmt init_elf32_binfmt
99 98
100#define jiffies_to_timeval jiffies_to_compat_timeval 99#define jiffies_to_timeval jiffies_to_compat_timeval
101static __inline__ void 100static inline void
102jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) 101jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
103{ 102{
104 /* 103 /*
@@ -113,21 +112,26 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
113#undef ELF_CORE_COPY_REGS 112#undef ELF_CORE_COPY_REGS
114#define ELF_CORE_COPY_REGS(_dest,_regs) elf32_core_copy_regs(_dest,_regs); 113#define ELF_CORE_COPY_REGS(_dest,_regs) elf32_core_copy_regs(_dest,_regs);
115 114
116void elf32_core_copy_regs(elf_gregset_t _dest, struct pt_regs *_regs) 115void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs)
117{ 116{
118 int i; 117 int i;
119 118
120 memset(_dest, 0, sizeof(elf_gregset_t)); 119 for (i = 0; i < EF_R0; i++)
121 120 grp[i] = 0;
122 /* XXXKW the 6 is from EF_REG0 in gdb/gdb/mips-linux-tdep.c, include/asm-mips/reg.h */ 121 grp[EF_R0] = 0;
123 for (i=6; i<38; i++) 122 for (i = 1; i <= 31; i++)
124 _dest[i] = (elf_greg_t) _regs->regs[i-6]; 123 grp[EF_R0 + i] = (elf_greg_t) regs->regs[i];
125 _dest[i++] = (elf_greg_t) _regs->lo; 124 grp[EF_R26] = 0;
126 _dest[i++] = (elf_greg_t) _regs->hi; 125 grp[EF_R27] = 0;
127 _dest[i++] = (elf_greg_t) _regs->cp0_epc; 126 grp[EF_LO] = (elf_greg_t) regs->lo;
128 _dest[i++] = (elf_greg_t) _regs->cp0_badvaddr; 127 grp[EF_HI] = (elf_greg_t) regs->hi;
129 _dest[i++] = (elf_greg_t) _regs->cp0_status; 128 grp[EF_CP0_EPC] = (elf_greg_t) regs->cp0_epc;
130 _dest[i++] = (elf_greg_t) _regs->cp0_cause; 129 grp[EF_CP0_BADVADDR] = (elf_greg_t) regs->cp0_badvaddr;
130 grp[EF_CP0_STATUS] = (elf_greg_t) regs->cp0_status;
131 grp[EF_CP0_CAUSE] = (elf_greg_t) regs->cp0_cause;
132#ifdef EF_UNUSED0
133 grp[EF_UNUSED0] = 0;
134#endif
131} 135}
132 136
133MODULE_DESCRIPTION("Binary format loader for compatibility with o32 Linux/MIPS binaries"); 137MODULE_DESCRIPTION("Binary format loader for compatibility with o32 Linux/MIPS binaries");
@@ -136,4 +140,7 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)");
136#undef MODULE_DESCRIPTION 140#undef MODULE_DESCRIPTION
137#undef MODULE_AUTHOR 141#undef MODULE_AUTHOR
138 142
143#undef TASK_SIZE
144#define TASK_SIZE TASK_SIZE32
145
139#include "../../../fs/binfmt_elf.c" 146#include "../../../fs/binfmt_elf.c"
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 01117e977a7f..374de839558d 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -12,6 +12,7 @@
12#include <asm/branch.h> 12#include <asm/branch.h>
13#include <asm/cpu.h> 13#include <asm/cpu.h>
14#include <asm/cpu-features.h> 14#include <asm/cpu-features.h>
15#include <asm/fpu.h>
15#include <asm/inst.h> 16#include <asm/inst.h>
16#include <asm/ptrace.h> 17#include <asm/ptrace.h>
17#include <asm/uaccess.h> 18#include <asm/uaccess.h>
@@ -21,7 +22,7 @@
21 */ 22 */
22int __compute_return_epc(struct pt_regs *regs) 23int __compute_return_epc(struct pt_regs *regs)
23{ 24{
24 unsigned int *addr, bit, fcr31; 25 unsigned int *addr, bit, fcr31, dspcontrol;
25 long epc; 26 long epc;
26 union mips_instruction insn; 27 union mips_instruction insn;
27 28
@@ -98,6 +99,18 @@ int __compute_return_epc(struct pt_regs *regs)
98 epc += 8; 99 epc += 8;
99 regs->cp0_epc = epc; 100 regs->cp0_epc = epc;
100 break; 101 break;
102 case bposge32_op:
103 if (!cpu_has_dsp)
104 goto sigill;
105
106 dspcontrol = rddsp(0x01);
107
108 if (dspcontrol >= 32) {
109 epc = epc + 4 + (insn.i_format.simmediate << 2);
110 } else
111 epc += 8;
112 regs->cp0_epc = epc;
113 break;
101 } 114 }
102 break; 115 break;
103 116
@@ -161,10 +174,13 @@ int __compute_return_epc(struct pt_regs *regs)
161 * And now the FPA/cp1 branch instructions. 174 * And now the FPA/cp1 branch instructions.
162 */ 175 */
163 case cop1_op: 176 case cop1_op:
164 if (!cpu_has_fpu) 177 preempt_disable();
165 fcr31 = current->thread.fpu.soft.fcr31; 178 if (is_fpu_owner())
166 else
167 asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 179 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
180 else
181 fcr31 = current->thread.fpu.hard.fcr31;
182 preempt_enable();
183
168 bit = (insn.i_format.rt >> 2); 184 bit = (insn.i_format.rt >> 2);
169 bit += (bit != 0); 185 bit += (bit != 0);
170 bit += 23; 186 bit += 23;
@@ -196,4 +212,9 @@ unaligned:
196 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); 212 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
197 force_sig(SIGBUS, current); 213 force_sig(SIGBUS, current);
198 return -EFAULT; 214 return -EFAULT;
215
216sigill:
217 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
218 force_sig(SIGBUS, current);
219 return -EFAULT;
199} 220}
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 7685f8baf3f0..a263fb7a3971 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -2,9 +2,9 @@
2 * Processor capabilities determination functions. 2 * Processor capabilities determination functions.
3 * 3 *
4 * Copyright (C) xxxx the Anonymous 4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 2003 Maciej W. Rozycki 5 * Copyright (C) 2003, 2004 Maciej W. Rozycki
6 * Copyright (C) 1994 - 2003 Ralf Baechle 6 * Copyright (C) 1994 - 2003 Ralf Baechle
7 * Copyright (C) 2001 MIPS Inc. 7 * Copyright (C) 2001, 2004 MIPS Inc.
8 * 8 *
9 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License 10 * modify it under the terms of the GNU General Public License
@@ -17,7 +17,6 @@
17#include <linux/ptrace.h> 17#include <linux/ptrace.h>
18#include <linux/stddef.h> 18#include <linux/stddef.h>
19 19
20#include <asm/bugs.h>
21#include <asm/cpu.h> 20#include <asm/cpu.h>
22#include <asm/fpu.h> 21#include <asm/fpu.h>
23#include <asm/mipsregs.h> 22#include <asm/mipsregs.h>
@@ -51,36 +50,48 @@ static void r4k_wait(void)
51 ".set\tmips0"); 50 ".set\tmips0");
52} 51}
53 52
54/* 53/* The Au1xxx wait is available only if using 32khz counter or
55 * The Au1xxx wait is available only if we run CONFIG_PM and 54 * external timer source, but specifically not CP0 Counter. */
56 * the timer setup found we had a 32KHz counter available. 55int allow_au1k_wait;
57 * There are still problems with functions that may call au1k_wait
58 * directly, but that will be discovered pretty quickly.
59 */
60extern void (*au1k_wait_ptr)(void);
61 56
62void au1k_wait(void) 57static void au1k_wait(void)
63{ 58{
64#ifdef CONFIG_PM
65 /* using the wait instruction makes CP0 counter unusable */ 59 /* using the wait instruction makes CP0 counter unusable */
66 __asm__(".set\tmips3\n\t" 60 __asm__(".set mips3\n\t"
61 "cache 0x14, 0(%0)\n\t"
62 "cache 0x14, 32(%0)\n\t"
63 "sync\n\t"
64 "nop\n\t"
67 "wait\n\t" 65 "wait\n\t"
68 "nop\n\t" 66 "nop\n\t"
69 "nop\n\t" 67 "nop\n\t"
70 "nop\n\t" 68 "nop\n\t"
71 "nop\n\t" 69 "nop\n\t"
72 ".set\tmips0"); 70 ".set mips0\n\t"
73#else 71 : : "r" (au1k_wait));
74 __asm__("nop\n\t"
75 "nop");
76#endif
77} 72}
78 73
74static int __initdata nowait = 0;
75
76int __init wait_disable(char *s)
77{
78 nowait = 1;
79
80 return 1;
81}
82
83__setup("nowait", wait_disable);
84
79static inline void check_wait(void) 85static inline void check_wait(void)
80{ 86{
81 struct cpuinfo_mips *c = &current_cpu_data; 87 struct cpuinfo_mips *c = &current_cpu_data;
82 88
83 printk("Checking for 'wait' instruction... "); 89 printk("Checking for 'wait' instruction... ");
90 if (nowait) {
91 printk (" disabled.\n");
92 return;
93 }
94
84 switch (c->cputype) { 95 switch (c->cputype) {
85 case CPU_R3081: 96 case CPU_R3081:
86 case CPU_R3081E: 97 case CPU_R3081E:
@@ -109,22 +120,22 @@ static inline void check_wait(void)
109/* case CPU_20KC:*/ 120/* case CPU_20KC:*/
110 case CPU_24K: 121 case CPU_24K:
111 case CPU_25KF: 122 case CPU_25KF:
123 case CPU_34K:
124 case CPU_PR4450:
112 cpu_wait = r4k_wait; 125 cpu_wait = r4k_wait;
113 printk(" available.\n"); 126 printk(" available.\n");
114 break; 127 break;
115#ifdef CONFIG_PM
116 case CPU_AU1000: 128 case CPU_AU1000:
117 case CPU_AU1100: 129 case CPU_AU1100:
118 case CPU_AU1500: 130 case CPU_AU1500:
119 if (au1k_wait_ptr != NULL) { 131 case CPU_AU1550:
120 cpu_wait = au1k_wait_ptr; 132 case CPU_AU1200:
133 if (allow_au1k_wait) {
134 cpu_wait = au1k_wait;
121 printk(" available.\n"); 135 printk(" available.\n");
122 } 136 } else
123 else {
124 printk(" unavailable.\n"); 137 printk(" unavailable.\n");
125 }
126 break; 138 break;
127#endif
128 default: 139 default:
129 printk(" unavailable.\n"); 140 printk(" unavailable.\n");
130 break; 141 break;
@@ -180,7 +191,7 @@ static inline int __cpu_has_fpu(void)
180 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 191 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
181} 192}
182 193
183#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \ 194#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
184 | MIPS_CPU_COUNTER) 195 | MIPS_CPU_COUNTER)
185 196
186static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 197static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
@@ -189,7 +200,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
189 case PRID_IMP_R2000: 200 case PRID_IMP_R2000:
190 c->cputype = CPU_R2000; 201 c->cputype = CPU_R2000;
191 c->isa_level = MIPS_CPU_ISA_I; 202 c->isa_level = MIPS_CPU_ISA_I;
192 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; 203 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
204 MIPS_CPU_NOFPUEX;
193 if (__cpu_has_fpu()) 205 if (__cpu_has_fpu())
194 c->options |= MIPS_CPU_FPU; 206 c->options |= MIPS_CPU_FPU;
195 c->tlbsize = 64; 207 c->tlbsize = 64;
@@ -203,7 +215,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
203 else 215 else
204 c->cputype = CPU_R3000; 216 c->cputype = CPU_R3000;
205 c->isa_level = MIPS_CPU_ISA_I; 217 c->isa_level = MIPS_CPU_ISA_I;
206 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; 218 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
219 MIPS_CPU_NOFPUEX;
207 if (__cpu_has_fpu()) 220 if (__cpu_has_fpu())
208 c->options |= MIPS_CPU_FPU; 221 c->options |= MIPS_CPU_FPU;
209 c->tlbsize = 64; 222 c->tlbsize = 64;
@@ -266,7 +279,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
266 case PRID_IMP_R4600: 279 case PRID_IMP_R4600:
267 c->cputype = CPU_R4600; 280 c->cputype = CPU_R4600;
268 c->isa_level = MIPS_CPU_ISA_III; 281 c->isa_level = MIPS_CPU_ISA_III;
269 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 282 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
283 MIPS_CPU_LLSC;
270 c->tlbsize = 48; 284 c->tlbsize = 48;
271 break; 285 break;
272 #if 0 286 #if 0
@@ -285,7 +299,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
285 #endif 299 #endif
286 case PRID_IMP_TX39: 300 case PRID_IMP_TX39:
287 c->isa_level = MIPS_CPU_ISA_I; 301 c->isa_level = MIPS_CPU_ISA_I;
288 c->options = MIPS_CPU_TLB; 302 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
289 303
290 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 304 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
291 c->cputype = CPU_TX3927; 305 c->cputype = CPU_TX3927;
@@ -421,74 +435,147 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
421 } 435 }
422} 436}
423 437
424static inline void decode_config1(struct cpuinfo_mips *c) 438static inline unsigned int decode_config0(struct cpuinfo_mips *c)
425{ 439{
426 unsigned long config0 = read_c0_config(); 440 unsigned int config0;
427 unsigned long config1; 441 int isa;
442
443 config0 = read_c0_config();
428 444
429 if ((config0 & (1 << 31)) == 0) 445 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
430 return; /* actually wort a panic() */ 446 c->options |= MIPS_CPU_TLB;
447 isa = (config0 & MIPS_CONF_AT) >> 13;
448 switch (isa) {
449 case 0:
450 c->isa_level = MIPS_CPU_ISA_M32;
451 break;
452 case 2:
453 c->isa_level = MIPS_CPU_ISA_M64;
454 break;
455 default:
456 panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
457 }
458
459 return config0 & MIPS_CONF_M;
460}
461
462static inline unsigned int decode_config1(struct cpuinfo_mips *c)
463{
464 unsigned int config1;
431 465
432 /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
433 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
434 MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
435 MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
436 config1 = read_c0_config1(); 466 config1 = read_c0_config1();
437 if (config1 & (1 << 3)) 467
468 if (config1 & MIPS_CONF1_MD)
469 c->ases |= MIPS_ASE_MDMX;
470 if (config1 & MIPS_CONF1_WR)
438 c->options |= MIPS_CPU_WATCH; 471 c->options |= MIPS_CPU_WATCH;
439 if (config1 & (1 << 2)) 472 if (config1 & MIPS_CONF1_CA)
440 c->options |= MIPS_CPU_MIPS16; 473 c->ases |= MIPS_ASE_MIPS16;
441 if (config1 & (1 << 1)) 474 if (config1 & MIPS_CONF1_EP)
442 c->options |= MIPS_CPU_EJTAG; 475 c->options |= MIPS_CPU_EJTAG;
443 if (config1 & 1) { 476 if (config1 & MIPS_CONF1_FP) {
444 c->options |= MIPS_CPU_FPU; 477 c->options |= MIPS_CPU_FPU;
445 c->options |= MIPS_CPU_32FPR; 478 c->options |= MIPS_CPU_32FPR;
446 } 479 }
480 if (cpu_has_tlb)
481 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
482
483 return config1 & MIPS_CONF_M;
484}
485
486static inline unsigned int decode_config2(struct cpuinfo_mips *c)
487{
488 unsigned int config2;
489
490 config2 = read_c0_config2();
491
492 if (config2 & MIPS_CONF2_SL)
493 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
494
495 return config2 & MIPS_CONF_M;
496}
497
498static inline unsigned int decode_config3(struct cpuinfo_mips *c)
499{
500 unsigned int config3;
501
502 config3 = read_c0_config3();
503
504 if (config3 & MIPS_CONF3_SM)
505 c->ases |= MIPS_ASE_SMARTMIPS;
506 if (config3 & MIPS_CONF3_DSP)
507 c->ases |= MIPS_ASE_DSP;
508 if (config3 & MIPS_CONF3_VINT)
509 c->options |= MIPS_CPU_VINT;
510 if (config3 & MIPS_CONF3_VEIC)
511 c->options |= MIPS_CPU_VEIC;
512 if (config3 & MIPS_CONF3_MT)
513 c->ases |= MIPS_ASE_MIPSMT;
514
515 return config3 & MIPS_CONF_M;
516}
517
518static inline void decode_configs(struct cpuinfo_mips *c)
519{
520 /* MIPS32 or MIPS64 compliant CPU. */
521 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
522 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
523
447 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 524 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
448 525
449 c->tlbsize = ((config1 >> 25) & 0x3f) + 1; 526 /* Read Config registers. */
527 if (!decode_config0(c))
528 return; /* actually worth a panic() */
529 if (!decode_config1(c))
530 return;
531 if (!decode_config2(c))
532 return;
533 if (!decode_config3(c))
534 return;
450} 535}
451 536
452static inline void cpu_probe_mips(struct cpuinfo_mips *c) 537static inline void cpu_probe_mips(struct cpuinfo_mips *c)
453{ 538{
454 decode_config1(c); 539 decode_configs(c);
455 switch (c->processor_id & 0xff00) { 540 switch (c->processor_id & 0xff00) {
456 case PRID_IMP_4KC: 541 case PRID_IMP_4KC:
457 c->cputype = CPU_4KC; 542 c->cputype = CPU_4KC;
458 c->isa_level = MIPS_CPU_ISA_M32;
459 break; 543 break;
460 case PRID_IMP_4KEC: 544 case PRID_IMP_4KEC:
461 c->cputype = CPU_4KEC; 545 c->cputype = CPU_4KEC;
462 c->isa_level = MIPS_CPU_ISA_M32; 546 break;
547 case PRID_IMP_4KECR2:
548 c->cputype = CPU_4KEC;
463 break; 549 break;
464 case PRID_IMP_4KSC: 550 case PRID_IMP_4KSC:
551 case PRID_IMP_4KSD:
465 c->cputype = CPU_4KSC; 552 c->cputype = CPU_4KSC;
466 c->isa_level = MIPS_CPU_ISA_M32;
467 break; 553 break;
468 case PRID_IMP_5KC: 554 case PRID_IMP_5KC:
469 c->cputype = CPU_5KC; 555 c->cputype = CPU_5KC;
470 c->isa_level = MIPS_CPU_ISA_M64;
471 break; 556 break;
472 case PRID_IMP_20KC: 557 case PRID_IMP_20KC:
473 c->cputype = CPU_20KC; 558 c->cputype = CPU_20KC;
474 c->isa_level = MIPS_CPU_ISA_M64;
475 break; 559 break;
476 case PRID_IMP_24K: 560 case PRID_IMP_24K:
561 case PRID_IMP_24KE:
477 c->cputype = CPU_24K; 562 c->cputype = CPU_24K;
478 c->isa_level = MIPS_CPU_ISA_M32;
479 break; 563 break;
480 case PRID_IMP_25KF: 564 case PRID_IMP_25KF:
481 c->cputype = CPU_25KF; 565 c->cputype = CPU_25KF;
482 c->isa_level = MIPS_CPU_ISA_M64;
483 /* Probe for L2 cache */ 566 /* Probe for L2 cache */
484 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 567 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
485 break; 568 break;
569 case PRID_IMP_34K:
570 c->cputype = CPU_34K;
571 c->isa_level = MIPS_CPU_ISA_M32;
572 break;
486 } 573 }
487} 574}
488 575
489static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) 576static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
490{ 577{
491 decode_config1(c); 578 decode_configs(c);
492 switch (c->processor_id & 0xff00) { 579 switch (c->processor_id & 0xff00) {
493 case PRID_IMP_AU1_REV1: 580 case PRID_IMP_AU1_REV1:
494 case PRID_IMP_AU1_REV2: 581 case PRID_IMP_AU1_REV2:
@@ -505,50 +592,70 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
505 case 3: 592 case 3:
506 c->cputype = CPU_AU1550; 593 c->cputype = CPU_AU1550;
507 break; 594 break;
595 case 4:
596 c->cputype = CPU_AU1200;
597 break;
508 default: 598 default:
509 panic("Unknown Au Core!"); 599 panic("Unknown Au Core!");
510 break; 600 break;
511 } 601 }
512 c->isa_level = MIPS_CPU_ISA_M32;
513 break; 602 break;
514 } 603 }
515} 604}
516 605
517static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) 606static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
518{ 607{
519 decode_config1(c); 608 decode_configs(c);
609
610 /*
611 * For historical reasons the SB1 comes with it's own variant of
612 * cache code which eventually will be folded into c-r4k.c. Until
613 * then we pretend it's got it's own cache architecture.
614 */
615 c->options &= ~MIPS_CPU_4K_CACHE;
616 c->options |= MIPS_CPU_SB1_CACHE;
617
520 switch (c->processor_id & 0xff00) { 618 switch (c->processor_id & 0xff00) {
521 case PRID_IMP_SB1: 619 case PRID_IMP_SB1:
522 c->cputype = CPU_SB1; 620 c->cputype = CPU_SB1;
523 c->isa_level = MIPS_CPU_ISA_M64; 621#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
524 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
525 MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
526 MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
527 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
528#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
529 /* FPU in pass1 is known to have issues. */ 622 /* FPU in pass1 is known to have issues. */
530 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 623 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
531#endif 624#endif
532 break; 625 break;
626 case PRID_IMP_SB1A:
627 c->cputype = CPU_SB1A;
628 break;
533 } 629 }
534} 630}
535 631
536static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) 632static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
537{ 633{
538 decode_config1(c); 634 decode_configs(c);
539 switch (c->processor_id & 0xff00) { 635 switch (c->processor_id & 0xff00) {
540 case PRID_IMP_SR71000: 636 case PRID_IMP_SR71000:
541 c->cputype = CPU_SR71000; 637 c->cputype = CPU_SR71000;
542 c->isa_level = MIPS_CPU_ISA_M64;
543 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
544 MIPS_CPU_4KTLB | MIPS_CPU_FPU |
545 MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
546 c->scache.ways = 8; 638 c->scache.ways = 8;
547 c->tlbsize = 64; 639 c->tlbsize = 64;
548 break; 640 break;
549 } 641 }
550} 642}
551 643
644static inline void cpu_probe_philips(struct cpuinfo_mips *c)
645{
646 decode_configs(c);
647 switch (c->processor_id & 0xff00) {
648 case PRID_IMP_PR4450:
649 c->cputype = CPU_PR4450;
650 c->isa_level = MIPS_CPU_ISA_M32;
651 break;
652 default:
653 panic("Unknown Philips Core!"); /* REVISIT: die? */
654 break;
655 }
656}
657
658
552__init void cpu_probe(void) 659__init void cpu_probe(void)
553{ 660{
554 struct cpuinfo_mips *c = &current_cpu_data; 661 struct cpuinfo_mips *c = &current_cpu_data;
@@ -571,15 +678,24 @@ __init void cpu_probe(void)
571 case PRID_COMP_SIBYTE: 678 case PRID_COMP_SIBYTE:
572 cpu_probe_sibyte(c); 679 cpu_probe_sibyte(c);
573 break; 680 break;
574
575 case PRID_COMP_SANDCRAFT: 681 case PRID_COMP_SANDCRAFT:
576 cpu_probe_sandcraft(c); 682 cpu_probe_sandcraft(c);
577 break; 683 break;
684 case PRID_COMP_PHILIPS:
685 cpu_probe_philips(c);
686 break;
578 default: 687 default:
579 c->cputype = CPU_UNKNOWN; 688 c->cputype = CPU_UNKNOWN;
580 } 689 }
581 if (c->options & MIPS_CPU_FPU) 690 if (c->options & MIPS_CPU_FPU) {
582 c->fpu_id = cpu_get_fpu_id(); 691 c->fpu_id = cpu_get_fpu_id();
692
693 if (c->isa_level == MIPS_CPU_ISA_M32 ||
694 c->isa_level == MIPS_CPU_ISA_M64) {
695 if (c->fpu_id & MIPS_FPIR_3D)
696 c->ases |= MIPS_ASE_MIPS3D;
697 }
698 }
583} 699}
584 700
585__init void cpu_report(void) 701__init void cpu_report(void)
diff --git a/arch/mips/kernel/dma-no-isa.c b/arch/mips/kernel/dma-no-isa.c
new file mode 100644
index 000000000000..6df8b07741e3
--- /dev/null
+++ b/arch/mips/kernel/dma-no-isa.c
@@ -0,0 +1,28 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 by Ralf Baechle
7 *
8 * Dummy ISA DMA functions for systems that don't have ISA but share drivers
9 * with ISA such as legacy free PCI.
10 */
11#include <linux/errno.h>
12#include <linux/module.h>
13#include <linux/spinlock.h>
14
15DEFINE_SPINLOCK(dma_spin_lock);
16
17int request_dma(unsigned int dmanr, const char * device_id)
18{
19 return -EINVAL;
20}
21
22void free_dma(unsigned int dmanr)
23{
24}
25
26EXPORT_SYMBOL(dma_spin_lock);
27EXPORT_SYMBOL(request_dma);
28EXPORT_SYMBOL(free_dma);
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index 5eb429137e06..83c87fe4ee4f 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -19,11 +19,11 @@
19#include <asm/war.h> 19#include <asm/war.h>
20 20
21#ifdef CONFIG_PREEMPT 21#ifdef CONFIG_PREEMPT
22 .macro preempt_stop reg=t0 22 .macro preempt_stop
23 .endm 23 .endm
24#else 24#else
25 .macro preempt_stop reg=t0 25 .macro preempt_stop
26 local_irq_disable \reg 26 local_irq_disable
27 .endm 27 .endm
28#define resume_kernel restore_all 28#define resume_kernel restore_all
29#endif 29#endif
@@ -37,17 +37,18 @@ FEXPORT(ret_from_irq)
37 andi t0, t0, KU_USER 37 andi t0, t0, KU_USER
38 beqz t0, resume_kernel 38 beqz t0, resume_kernel
39 39
40FEXPORT(resume_userspace) 40resume_userspace:
41 local_irq_disable t0 # make sure we dont miss an 41 local_irq_disable # make sure we dont miss an
42 # interrupt setting need_resched 42 # interrupt setting need_resched
43 # between sampling and return 43 # between sampling and return
44 LONG_L a2, TI_FLAGS($28) # current->work 44 LONG_L a2, TI_FLAGS($28) # current->work
45 andi a2, _TIF_WORK_MASK # (ignoring syscall_trace) 45 andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace)
46 bnez a2, work_pending 46 bnez t0, work_pending
47 j restore_all 47 j restore_all
48 48
49#ifdef CONFIG_PREEMPT 49#ifdef CONFIG_PREEMPT
50ENTRY(resume_kernel) 50resume_kernel:
51 local_irq_disable
51 lw t0, TI_PRE_COUNT($28) 52 lw t0, TI_PRE_COUNT($28)
52 bnez t0, restore_all 53 bnez t0, restore_all
53need_resched: 54need_resched:
@@ -57,12 +58,7 @@ need_resched:
57 LONG_L t0, PT_STATUS(sp) # Interrupts off? 58 LONG_L t0, PT_STATUS(sp) # Interrupts off?
58 andi t0, 1 59 andi t0, 1
59 beqz t0, restore_all 60 beqz t0, restore_all
60 li t0, PREEMPT_ACTIVE 61 jal preempt_schedule_irq
61 sw t0, TI_PRE_COUNT($28)
62 local_irq_enable t0
63 jal schedule
64 sw zero, TI_PRE_COUNT($28)
65 local_irq_disable t0
66 b need_resched 62 b need_resched
67#endif 63#endif
68 64
@@ -88,13 +84,13 @@ FEXPORT(restore_partial) # restore partial frame
88 RESTORE_SP_AND_RET 84 RESTORE_SP_AND_RET
89 .set at 85 .set at
90 86
91FEXPORT(work_pending) 87work_pending:
92 andi t0, a2, _TIF_NEED_RESCHED 88 andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS
93 beqz t0, work_notifysig 89 beqz t0, work_notifysig
94work_resched: 90work_resched:
95 jal schedule 91 jal schedule
96 92
97 local_irq_disable t0 # make sure need_resched and 93 local_irq_disable # make sure need_resched and
98 # signals dont change between 94 # signals dont change between
99 # sampling and return 95 # sampling and return
100 LONG_L a2, TI_FLAGS($28) 96 LONG_L a2, TI_FLAGS($28)
@@ -109,15 +105,14 @@ work_notifysig: # deal with pending signals and
109 move a0, sp 105 move a0, sp
110 li a1, 0 106 li a1, 0
111 jal do_notify_resume # a2 already loaded 107 jal do_notify_resume # a2 already loaded
112 j restore_all 108 j resume_userspace
113 109
114FEXPORT(syscall_exit_work_partial) 110FEXPORT(syscall_exit_work_partial)
115 SAVE_STATIC 111 SAVE_STATIC
116FEXPORT(syscall_exit_work) 112syscall_exit_work:
117 LONG_L t0, TI_FLAGS($28) 113 li t0, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
118 li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT 114 and t0, a2 # a2 is preloaded with TI_FLAGS
119 and t0, t1 115 beqz t0, work_pending # trace bit set?
120 beqz t0, work_pending # trace bit is set
121 local_irq_enable # could let do_syscall_trace() 116 local_irq_enable # could let do_syscall_trace()
122 # call schedule() instead 117 # call schedule() instead
123 move a0, sp 118 move a0, sp
@@ -128,28 +123,25 @@ FEXPORT(syscall_exit_work)
128/* 123/*
129 * Common spurious interrupt handler. 124 * Common spurious interrupt handler.
130 */ 125 */
131 .text
132 .align 5
133LEAF(spurious_interrupt) 126LEAF(spurious_interrupt)
134 /* 127 /*
135 * Someone tried to fool us by sending an interrupt but we 128 * Someone tried to fool us by sending an interrupt but we
136 * couldn't find a cause for it. 129 * couldn't find a cause for it.
137 */ 130 */
131 PTR_LA t1, irq_err_count
138#ifdef CONFIG_SMP 132#ifdef CONFIG_SMP
139 lui t1, %hi(irq_err_count) 1331: ll t0, (t1)
1401: ll t0, %lo(irq_err_count)(t1)
141 addiu t0, 1 134 addiu t0, 1
142 sc t0, %lo(irq_err_count)(t1) 135 sc t0, (t1)
143#if R10000_LLSC_WAR 136#if R10000_LLSC_WAR
144 beqzl t0, 1b 137 beqzl t0, 1b
145#else 138#else
146 beqz t0, 1b 139 beqz t0, 1b
147#endif 140#endif
148#else 141#else
149 lui t1, %hi(irq_err_count) 142 lw t0, (t1)
150 lw t0, %lo(irq_err_count)(t1)
151 addiu t0, 1 143 addiu t0, 1
152 sw t0, %lo(irq_err_count)(t1) 144 sw t0, (t1)
153#endif 145#endif
154 j ret_from_irq 146 j ret_from_irq
155 END(spurious_interrupt) 147 END(spurious_interrupt)
diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S
index 512bedbfa7b9..83b8986f9401 100644
--- a/arch/mips/kernel/gdb-low.S
+++ b/arch/mips/kernel/gdb-low.S
@@ -52,16 +52,15 @@
52 /* 52 /*
53 * Called from user mode, go somewhere else. 53 * Called from user mode, go somewhere else.
54 */ 54 */
55 lui k1, %hi(saved_vectors)
56 mfc0 k0, CP0_CAUSE 55 mfc0 k0, CP0_CAUSE
57 andi k0, k0, 0x7c 56 andi k0, k0, 0x7c
58 add k1, k1, k0 57 add k1, k1, k0
59 lw k0, %lo(saved_vectors)(k1) 58 PTR_L k0, saved_vectors(k1)
60 jr k0 59 jr k0
61 nop 60 nop
621: 611:
63 move k0, sp 62 move k0, sp
64 subu sp, k1, GDB_FR_SIZE*2 # see comment above 63 PTR_SUBU sp, k1, GDB_FR_SIZE*2 # see comment above
65 LONG_S k0, GDB_FR_REG29(sp) 64 LONG_S k0, GDB_FR_REG29(sp)
66 LONG_S $2, GDB_FR_REG2(sp) 65 LONG_S $2, GDB_FR_REG2(sp)
67 66
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
index d3fd1ab14274..96d18c43dca0 100644
--- a/arch/mips/kernel/gdb-stub.c
+++ b/arch/mips/kernel/gdb-stub.c
@@ -176,8 +176,10 @@ int kgdb_enabled;
176/* 176/*
177 * spin locks for smp case 177 * spin locks for smp case
178 */ 178 */
179static spinlock_t kgdb_lock = SPIN_LOCK_UNLOCKED; 179static DEFINE_SPINLOCK(kgdb_lock);
180static spinlock_t kgdb_cpulock[NR_CPUS] = { [0 ... NR_CPUS-1] = SPIN_LOCK_UNLOCKED}; 180static raw_spinlock_t kgdb_cpulock[NR_CPUS] = {
181 [0 ... NR_CPUS-1] = __RAW_SPIN_LOCK_UNLOCKED;
182};
181 183
182/* 184/*
183 * BUFMAX defines the maximum number of characters in inbound/outbound buffers 185 * BUFMAX defines the maximum number of characters in inbound/outbound buffers
@@ -637,29 +639,32 @@ static struct gdb_bp_save async_bp;
637 * and only one can be active at a time. 639 * and only one can be active at a time.
638 */ 640 */
639extern spinlock_t smp_call_lock; 641extern spinlock_t smp_call_lock;
642
640void set_async_breakpoint(unsigned long *epc) 643void set_async_breakpoint(unsigned long *epc)
641{ 644{
642 /* skip breaking into userland */ 645 /* skip breaking into userland */
643 if ((*epc & 0x80000000) == 0) 646 if ((*epc & 0x80000000) == 0)
644 return; 647 return;
645 648
649#ifdef CONFIG_SMP
646 /* avoid deadlock if someone is make IPC */ 650 /* avoid deadlock if someone is make IPC */
647 if (spin_is_locked(&smp_call_lock)) 651 if (spin_is_locked(&smp_call_lock))
648 return; 652 return;
653#endif
649 654
650 async_bp.addr = *epc; 655 async_bp.addr = *epc;
651 *epc = (unsigned long)async_breakpoint; 656 *epc = (unsigned long)async_breakpoint;
652} 657}
653 658
654void kgdb_wait(void *arg) 659static void kgdb_wait(void *arg)
655{ 660{
656 unsigned flags; 661 unsigned flags;
657 int cpu = smp_processor_id(); 662 int cpu = smp_processor_id();
658 663
659 local_irq_save(flags); 664 local_irq_save(flags);
660 665
661 spin_lock(&kgdb_cpulock[cpu]); 666 __raw_spin_lock(&kgdb_cpulock[cpu]);
662 spin_unlock(&kgdb_cpulock[cpu]); 667 __raw_spin_unlock(&kgdb_cpulock[cpu]);
663 668
664 local_irq_restore(flags); 669 local_irq_restore(flags);
665} 670}
@@ -707,7 +712,7 @@ void handle_exception (struct gdb_regs *regs)
707 * acquire the CPU spinlocks 712 * acquire the CPU spinlocks
708 */ 713 */
709 for (i = num_online_cpus()-1; i >= 0; i--) 714 for (i = num_online_cpus()-1; i >= 0; i--)
710 if (spin_trylock(&kgdb_cpulock[i]) == 0) 715 if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0)
711 panic("kgdb: couldn't get cpulock %d\n", i); 716 panic("kgdb: couldn't get cpulock %d\n", i);
712 717
713 /* 718 /*
@@ -982,7 +987,7 @@ finish_kgdb:
982exit_kgdb_exception: 987exit_kgdb_exception:
983 /* release locks so other CPUs can go */ 988 /* release locks so other CPUs can go */
984 for (i = num_online_cpus()-1; i >= 0; i--) 989 for (i = num_online_cpus()-1; i >= 0; i--)
985 spin_unlock(&kgdb_cpulock[i]); 990 __raw_spin_unlock(&kgdb_cpulock[i]);
986 spin_unlock(&kgdb_lock); 991 spin_unlock(&kgdb_lock);
987 992
988 __flush_cache_all(); 993 __flush_cache_all();
@@ -1036,12 +1041,12 @@ void adel(void)
1036 * malloc is needed by gdb client in "call func()", even a private one 1041 * malloc is needed by gdb client in "call func()", even a private one
1037 * will make gdb happy 1042 * will make gdb happy
1038 */ 1043 */
1039static void *malloc(size_t size) 1044static void * __attribute_used__ malloc(size_t size)
1040{ 1045{
1041 return kmalloc(size, GFP_ATOMIC); 1046 return kmalloc(size, GFP_ATOMIC);
1042} 1047}
1043 1048
1044static void free(void *where) 1049static void __attribute_used__ free (void *where)
1045{ 1050{
1046 kfree(where); 1051 kfree(where);
1047} 1052}
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index e7f6c1b90806..aa18a8b7b380 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -82,7 +82,7 @@ NESTED(except_vec3_r4000, 0, sp)
82 li k0, 14<<2 82 li k0, 14<<2
83 beq k1, k0, handle_vcei 83 beq k1, k0, handle_vcei
84#ifdef CONFIG_64BIT 84#ifdef CONFIG_64BIT
85 dsll k1, k1, 1 85 dsll k1, k1, 1
86#endif 86#endif
87 .set pop 87 .set pop
88 PTR_L k0, exception_handlers(k1) 88 PTR_L k0, exception_handlers(k1)
@@ -90,17 +90,17 @@ NESTED(except_vec3_r4000, 0, sp)
90 90
91 /* 91 /*
92 * Big shit, we now may have two dirty primary cache lines for the same 92 * Big shit, we now may have two dirty primary cache lines for the same
93 * physical address. We can savely invalidate the line pointed to by 93 * physical address. We can safely invalidate the line pointed to by
94 * c0_badvaddr because after return from this exception handler the 94 * c0_badvaddr because after return from this exception handler the
95 * load / store will be re-executed. 95 * load / store will be re-executed.
96 */ 96 */
97handle_vced: 97handle_vced:
98 DMFC0 k0, CP0_BADVADDR 98 MFC0 k0, CP0_BADVADDR
99 li k1, -4 # Is this ... 99 li k1, -4 # Is this ...
100 and k0, k1 # ... really needed? 100 and k0, k1 # ... really needed?
101 mtc0 zero, CP0_TAGLO 101 mtc0 zero, CP0_TAGLO
102 cache Index_Store_Tag_D,(k0) 102 cache Index_Store_Tag_D, (k0)
103 cache Hit_Writeback_Inv_SD,(k0) 103 cache Hit_Writeback_Inv_SD, (k0)
104#ifdef CONFIG_PROC_FS 104#ifdef CONFIG_PROC_FS
105 PTR_LA k0, vced_count 105 PTR_LA k0, vced_count
106 lw k1, (k0) 106 lw k1, (k0)
@@ -148,6 +148,38 @@ NESTED(except_vec_ejtag_debug, 0, sp)
148 __FINIT 148 __FINIT
149 149
150/* 150/*
151 * Vectored interrupt handler.
152 * This prototype is copied to ebase + n*IntCtl.VS and patched
153 * to invoke the handler
154 */
155NESTED(except_vec_vi, 0, sp)
156 SAVE_SOME
157 SAVE_AT
158 .set push
159 .set noreorder
160EXPORT(except_vec_vi_lui)
161 lui v0, 0 /* Patched */
162 j except_vec_vi_handler
163EXPORT(except_vec_vi_ori)
164 ori v0, 0 /* Patched */
165 .set pop
166 END(except_vec_vi)
167EXPORT(except_vec_vi_end)
168
169/*
170 * Common Vectored Interrupt code
171 * Complete the register saves and invoke the handler which is passed in $v0
172 */
173NESTED(except_vec_vi_handler, 0, sp)
174 SAVE_TEMP
175 SAVE_STATIC
176 CLI
177 move a0, sp
178 jalr v0
179 j ret_from_irq
180 END(except_vec_vi_handler)
181
182/*
151 * EJTAG debug exception handler. 183 * EJTAG debug exception handler.
152 */ 184 */
153NESTED(ejtag_debug_handler, PT_SIZE, sp) 185NESTED(ejtag_debug_handler, PT_SIZE, sp)
@@ -291,6 +323,8 @@ NESTED(nmi_handler, PT_SIZE, sp)
291 BUILD_HANDLER mdmx mdmx sti silent /* #22 */ 323 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
292 BUILD_HANDLER watch watch sti verbose /* #23 */ 324 BUILD_HANDLER watch watch sti verbose /* #23 */
293 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ 325 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
326 BUILD_HANDLER mt mt sti verbose /* #25 */
327 BUILD_HANDLER dsp dsp sti silent /* #26 */
294 BUILD_HANDLER reserved reserved sti verbose /* others */ 328 BUILD_HANDLER reserved reserved sti verbose /* others */
295 329
296#ifdef CONFIG_64BIT 330#ifdef CONFIG_64BIT
diff --git a/arch/mips/kernel/genrtc.c b/arch/mips/kernel/genrtc.c
deleted file mode 100644
index 71416e7bbbaa..000000000000
--- a/arch/mips/kernel/genrtc.c
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * A glue layer that provides RTC read/write to drivers/char/genrtc.c driver
3 * based on MIPS internal RTC routines. It does take care locking
4 * issues so that we are SMP/Preemption safe.
5 *
6 * Copyright (C) 2004 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 *
9 * Please read the COPYING file for all license details.
10 */
11
12#include <linux/spinlock.h>
13
14#include <asm/rtc.h>
15#include <asm/time.h>
16
17static DEFINE_SPINLOCK(mips_rtc_lock);
18
19unsigned int get_rtc_time(struct rtc_time *time)
20{
21 unsigned long nowtime;
22
23 spin_lock(&mips_rtc_lock);
24 nowtime = rtc_get_time();
25 to_tm(nowtime, time);
26 time->tm_year -= 1900;
27 spin_unlock(&mips_rtc_lock);
28
29 return RTC_24H;
30}
31
32int set_rtc_time(struct rtc_time *time)
33{
34 unsigned long nowtime;
35 int ret;
36
37 spin_lock(&mips_rtc_lock);
38 nowtime = mktime(time->tm_year+1900, time->tm_mon+1,
39 time->tm_mday, time->tm_hour, time->tm_min,
40 time->tm_sec);
41 ret = rtc_set_time(nowtime);
42 spin_unlock(&mips_rtc_lock);
43
44 return ret;
45}
46
47unsigned int get_rtc_ss(void)
48{
49 struct rtc_time h;
50
51 get_rtc_time(&h);
52 return h.tm_sec;
53}
54
55int get_rtc_pll(struct rtc_pll_info *pll)
56{
57 return -EINVAL;
58}
59
60int set_rtc_pll(struct rtc_pll_info *pll)
61{
62 return -EINVAL;
63}
64
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 2a1b45d66f04..2e9122a4213a 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -22,11 +22,8 @@
22#include <asm/page.h> 22#include <asm/page.h>
23#include <asm/mipsregs.h> 23#include <asm/mipsregs.h>
24#include <asm/stackframe.h> 24#include <asm/stackframe.h>
25#ifdef CONFIG_SGI_IP27 25
26#include <asm/sn/addrs.h> 26#include <kernel-entry-init.h>
27#include <asm/sn/sn0/hubni.h>
28#include <asm/sn/klkernvars.h>
29#endif
30 27
31 .macro ARC64_TWIDDLE_PC 28 .macro ARC64_TWIDDLE_PC
32#if defined(CONFIG_ARC64) || defined(CONFIG_MAPPED_KERNEL) 29#if defined(CONFIG_ARC64) || defined(CONFIG_MAPPED_KERNEL)
@@ -38,18 +35,6 @@
38#endif 35#endif
39 .endm 36 .endm
40 37
41#ifdef CONFIG_SGI_IP27
42 /*
43 * outputs the local nasid into res. IP27 stuff.
44 */
45 .macro GET_NASID_ASM res
46 dli \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
47 ld \res, (\res)
48 and \res, NSRI_NODEID_MASK
49 dsrl \res, NSRI_NODEID_SHFT
50 .endm
51#endif /* CONFIG_SGI_IP27 */
52
53 /* 38 /*
54 * inputs are the text nasid in t1, data nasid in t2. 39 * inputs are the text nasid in t1, data nasid in t2.
55 */ 40 */
@@ -131,16 +116,21 @@
131EXPORT(stext) # used for profiling 116EXPORT(stext) # used for profiling
132EXPORT(_stext) 117EXPORT(_stext)
133 118
119#if defined(CONFIG_QEMU) || defined(CONFIG_MIPS_SIM)
120 /*
121 * Give us a fighting chance of running if execution beings at the
122 * kernel load address. This is needed because this platform does
123 * not have a ELF loader yet.
124 */
125 j kernel_entry
126#endif
134 __INIT 127 __INIT
135 128
136NESTED(kernel_entry, 16, sp) # kernel entry point 129NESTED(kernel_entry, 16, sp) # kernel entry point
137 setup_c0_status_pri
138 130
139#ifdef CONFIG_SGI_IP27 131 kernel_entry_setup # cpu specific setup
140 GET_NASID_ASM t1 132
141 move t2, t1 # text and data are here 133 setup_c0_status_pri
142 MAPPED_KERNEL_SETUP_TLB
143#endif /* IP27 */
144 134
145 ARC64_TWIDDLE_PC 135 ARC64_TWIDDLE_PC
146 136
@@ -157,6 +147,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
157 LONG_S a2, fw_arg2 147 LONG_S a2, fw_arg2
158 LONG_S a3, fw_arg3 148 LONG_S a3, fw_arg3
159 149
150 MTC0 zero, CP0_CONTEXT # clear context register
160 PTR_LA $28, init_thread_union 151 PTR_LA $28, init_thread_union
161 PTR_ADDIU sp, $28, _THREAD_SIZE - 32 152 PTR_ADDIU sp, $28, _THREAD_SIZE - 32
162 set_saved_sp sp, t0, t1 153 set_saved_sp sp, t0, t1
@@ -165,6 +156,10 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
165 j start_kernel 156 j start_kernel
166 END(kernel_entry) 157 END(kernel_entry)
167 158
159#ifdef CONFIG_QEMU
160 __INIT
161#endif
162
168#ifdef CONFIG_SMP 163#ifdef CONFIG_SMP
169/* 164/*
170 * SMP slave cpus entry point. Board specific code for bootstrap calls this 165 * SMP slave cpus entry point. Board specific code for bootstrap calls this
@@ -172,20 +167,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
172 */ 167 */
173NESTED(smp_bootstrap, 16, sp) 168NESTED(smp_bootstrap, 16, sp)
174 setup_c0_status_sec 169 setup_c0_status_sec
175 170 smp_slave_setup
176#ifdef CONFIG_SGI_IP27
177 GET_NASID_ASM t1
178 dli t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
179 KLDIR_OFF_POINTER + CAC_BASE
180 dsll t1, NASID_SHFT
181 or t0, t0, t1
182 ld t0, 0(t0) # t0 points to kern_vars struct
183 lh t1, KV_RO_NASID_OFFSET(t0)
184 lh t2, KV_RW_NASID_OFFSET(t0)
185 MAPPED_KERNEL_SETUP_TLB
186 ARC64_TWIDDLE_PC
187#endif /* CONFIG_SGI_IP27 */
188
189 j start_secondary 171 j start_secondary
190 END(smp_bootstrap) 172 END(smp_bootstrap)
191#endif /* CONFIG_SMP */ 173#endif /* CONFIG_SMP */
@@ -200,19 +182,13 @@ NESTED(smp_bootstrap, 16, sp)
200 .comm fw_arg2, SZREG, SZREG 182 .comm fw_arg2, SZREG, SZREG
201 .comm fw_arg3, SZREG, SZREG 183 .comm fw_arg3, SZREG, SZREG
202 184
203 .macro page name, order=0 185 .macro page name, order
204 .globl \name 186 .comm \name, (_PAGE_SIZE << \order), (_PAGE_SIZE << \order)
205\name: .size \name, (_PAGE_SIZE << \order)
206 .org . + (_PAGE_SIZE << \order)
207 .type \name, @object
208 .endm 187 .endm
209 188
210 .data
211 .align PAGE_SHIFT
212
213 /* 189 /*
214 * ... but on 64-bit we've got three-level pagetables with a 190 * On 64-bit we've got three-level pagetables with a slightly
215 * slightly different layout ... 191 * different layout ...
216 */ 192 */
217 page swapper_pg_dir, _PGD_ORDER 193 page swapper_pg_dir, _PGD_ORDER
218#ifdef CONFIG_64BIT 194#ifdef CONFIG_64BIT
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 447759201d1d..b974ac9057f6 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -31,7 +31,7 @@ void disable_8259A_irq(unsigned int irq);
31 * moves to arch independent land 31 * moves to arch independent land
32 */ 32 */
33 33
34spinlock_t DEFINE_SPINLOCK(i8259A_lock); 34DEFINE_SPINLOCK(i8259A_lock);
35 35
36static void end_8259A_irq (unsigned int irq) 36static void end_8259A_irq (unsigned int irq)
37{ 37{
@@ -52,14 +52,13 @@ static unsigned int startup_8259A_irq(unsigned int irq)
52} 52}
53 53
54static struct hw_interrupt_type i8259A_irq_type = { 54static struct hw_interrupt_type i8259A_irq_type = {
55 "XT-PIC", 55 .typename = "XT-PIC",
56 startup_8259A_irq, 56 .startup = startup_8259A_irq,
57 shutdown_8259A_irq, 57 .shutdown = shutdown_8259A_irq,
58 enable_8259A_irq, 58 .enable = enable_8259A_irq,
59 disable_8259A_irq, 59 .disable = disable_8259A_irq,
60 mask_and_ack_8259A, 60 .ack = mask_and_ack_8259A,
61 end_8259A_irq, 61 .end = end_8259A_irq,
62 NULL
63}; 62};
64 63
65/* 64/*
@@ -308,7 +307,7 @@ static struct resource pic2_io_resource = {
308 307
309/* 308/*
310 * On systems with i8259-style interrupt controllers we assume for 309 * On systems with i8259-style interrupt controllers we assume for
311 * driver compatibility reasons interrupts 0 - 15 to be the i8295 310 * driver compatibility reasons interrupts 0 - 15 to be the i8259
312 * interrupts even if the hardware uses a different interrupt numbering. 311 * interrupts even if the hardware uses a different interrupt numbering.
313 */ 312 */
314void __init init_i8259_irqs (void) 313void __init init_i8259_irqs (void)
@@ -322,7 +321,7 @@ void __init init_i8259_irqs (void)
322 321
323 for (i = 0; i < 16; i++) { 322 for (i = 0; i < 16; i++) {
324 irq_desc[i].status = IRQ_DISABLED; 323 irq_desc[i].status = IRQ_DISABLED;
325 irq_desc[i].action = 0; 324 irq_desc[i].action = NULL;
326 irq_desc[i].depth = 1; 325 irq_desc[i].depth = 1;
327 irq_desc[i].handler = &i8259A_irq_type; 326 irq_desc[i].handler = &i8259A_irq_type;
328 } 327 }
diff --git a/arch/mips/kernel/ioctl32.c b/arch/mips/kernel/ioctl32.c
index c069719ff0d8..ed9b2da510be 100644
--- a/arch/mips/kernel/ioctl32.c
+++ b/arch/mips/kernel/ioctl32.c
@@ -41,12 +41,6 @@ IOCTL_TABLE_START
41#define DECLARES 41#define DECLARES
42#include "compat_ioctl.c" 42#include "compat_ioctl.c"
43 43
44#ifdef CONFIG_SIBYTE_TBPROF
45COMPATIBLE_IOCTL(SBPROF_ZBSTART)
46COMPATIBLE_IOCTL(SBPROF_ZBSTOP)
47COMPATIBLE_IOCTL(SBPROF_ZBWAITFULL)
48#endif /* CONFIG_SIBYTE_TBPROF */
49
50/*HANDLE_IOCTL(RTC_IRQP_READ, w_long) 44/*HANDLE_IOCTL(RTC_IRQP_READ, w_long)
51COMPATIBLE_IOCTL(RTC_IRQP_SET) 45COMPATIBLE_IOCTL(RTC_IRQP_SET)
52HANDLE_IOCTL(RTC_EPOCH_READ, w_long) 46HANDLE_IOCTL(RTC_EPOCH_READ, w_long)
diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c
index 4af20cd91f9f..99262fe64560 100644
--- a/arch/mips/kernel/irixelf.c
+++ b/arch/mips/kernel/irixelf.c
@@ -8,7 +8,7 @@
8 * 8 *
9 * Copyright (C) 1993 - 1994 Eric Youngdale <ericy@cais.com> 9 * Copyright (C) 1993 - 1994 Eric Youngdale <ericy@cais.com>
10 * Copyright (C) 1996 - 2004 David S. Miller <dm@engr.sgi.com> 10 * Copyright (C) 1996 - 2004 David S. Miller <dm@engr.sgi.com>
11 * Copyright (C) 2004 Steven J. Hill <sjhill@realitydiluted.com> 11 * Copyright (C) 2004 - 2005 Steven J. Hill <sjhill@realitydiluted.com>
12 */ 12 */
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/fs.h> 14#include <linux/fs.h>
@@ -31,15 +31,16 @@
31#include <linux/elfcore.h> 31#include <linux/elfcore.h>
32#include <linux/smp_lock.h> 32#include <linux/smp_lock.h>
33 33
34#include <asm/uaccess.h>
35#include <asm/mipsregs.h> 34#include <asm/mipsregs.h>
35#include <asm/namei.h>
36#include <asm/prctl.h> 36#include <asm/prctl.h>
37#include <asm/uaccess.h>
37 38
38#define DLINFO_ITEMS 12 39#define DLINFO_ITEMS 12
39 40
40#include <linux/elf.h> 41#include <linux/elf.h>
41 42
42#undef DEBUG_ELF 43#undef DEBUG
43 44
44static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs); 45static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs);
45static int load_irix_library(struct file *); 46static int load_irix_library(struct file *);
@@ -55,7 +56,7 @@ static struct linux_binfmt irix_format = {
55#define elf_addr_t unsigned long 56#define elf_addr_t unsigned long
56#endif 57#endif
57 58
58#ifdef DEBUG_ELF 59#ifdef DEBUG
59/* Debugging routines. */ 60/* Debugging routines. */
60static char *get_elf_p_type(Elf32_Word p_type) 61static char *get_elf_p_type(Elf32_Word p_type)
61{ 62{
@@ -120,7 +121,7 @@ static void dump_phdrs(struct elf_phdr *ep, int pnum)
120 print_phdr(i, ep); 121 print_phdr(i, ep);
121 } 122 }
122} 123}
123#endif /* (DEBUG_ELF) */ 124#endif /* DEBUG */
124 125
125static void set_brk(unsigned long start, unsigned long end) 126static void set_brk(unsigned long start, unsigned long end)
126{ 127{
@@ -146,20 +147,20 @@ static void padzero(unsigned long elf_bss)
146 nbyte = elf_bss & (PAGE_SIZE-1); 147 nbyte = elf_bss & (PAGE_SIZE-1);
147 if (nbyte) { 148 if (nbyte) {
148 nbyte = PAGE_SIZE - nbyte; 149 nbyte = PAGE_SIZE - nbyte;
149 clear_user((void *) elf_bss, nbyte); 150 clear_user((void __user *) elf_bss, nbyte);
150 } 151 }
151} 152}
152 153
153unsigned long * create_irix_tables(char * p, int argc, int envc, 154static unsigned long * create_irix_tables(char * p, int argc, int envc,
154 struct elfhdr * exec, unsigned int load_addr, 155 struct elfhdr * exec, unsigned int load_addr,
155 unsigned int interp_load_addr, 156 unsigned int interp_load_addr, struct pt_regs *regs,
156 struct pt_regs *regs, struct elf_phdr *ephdr) 157 struct elf_phdr *ephdr)
157{ 158{
158 elf_addr_t *argv; 159 elf_addr_t *argv;
159 elf_addr_t *envp; 160 elf_addr_t *envp;
160 elf_addr_t *sp, *csp; 161 elf_addr_t *sp, *csp;
161 162
162#ifdef DEBUG_ELF 163#ifdef DEBUG
163 printk("create_irix_tables: p[%p] argc[%d] envc[%d] " 164 printk("create_irix_tables: p[%p] argc[%d] envc[%d] "
164 "load_addr[%08x] interp_load_addr[%08x]\n", 165 "load_addr[%08x] interp_load_addr[%08x]\n",
165 p, argc, envc, load_addr, interp_load_addr); 166 p, argc, envc, load_addr, interp_load_addr);
@@ -248,14 +249,13 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
248 last_bss = 0; 249 last_bss = 0;
249 error = load_addr = 0; 250 error = load_addr = 0;
250 251
251#ifdef DEBUG_ELF 252#ifdef DEBUG
252 print_elfhdr(interp_elf_ex); 253 print_elfhdr(interp_elf_ex);
253#endif 254#endif
254 255
255 /* First of all, some simple consistency checks */ 256 /* First of all, some simple consistency checks */
256 if ((interp_elf_ex->e_type != ET_EXEC && 257 if ((interp_elf_ex->e_type != ET_EXEC &&
257 interp_elf_ex->e_type != ET_DYN) || 258 interp_elf_ex->e_type != ET_DYN) ||
258 !irix_elf_check_arch(interp_elf_ex) ||
259 !interpreter->f_op->mmap) { 259 !interpreter->f_op->mmap) {
260 printk("IRIX interp has bad e_type %d\n", interp_elf_ex->e_type); 260 printk("IRIX interp has bad e_type %d\n", interp_elf_ex->e_type);
261 return 0xffffffff; 261 return 0xffffffff;
@@ -290,7 +290,7 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
290 (char *) elf_phdata, 290 (char *) elf_phdata,
291 sizeof(struct elf_phdr) * interp_elf_ex->e_phnum); 291 sizeof(struct elf_phdr) * interp_elf_ex->e_phnum);
292 292
293#ifdef DEBUG_ELF 293#ifdef DEBUG
294 dump_phdrs(elf_phdata, interp_elf_ex->e_phnum); 294 dump_phdrs(elf_phdata, interp_elf_ex->e_phnum);
295#endif 295#endif
296 296
@@ -306,13 +306,11 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
306 elf_type |= MAP_FIXED; 306 elf_type |= MAP_FIXED;
307 vaddr = eppnt->p_vaddr; 307 vaddr = eppnt->p_vaddr;
308 308
309#ifdef DEBUG_ELF 309 pr_debug("INTERP do_mmap(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ",
310 printk("INTERP do_mmap(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ",
311 interpreter, vaddr, 310 interpreter, vaddr,
312 (unsigned long) (eppnt->p_filesz + (eppnt->p_vaddr & 0xfff)), 311 (unsigned long) (eppnt->p_filesz + (eppnt->p_vaddr & 0xfff)),
313 (unsigned long) elf_prot, (unsigned long) elf_type, 312 (unsigned long) elf_prot, (unsigned long) elf_type,
314 (unsigned long) (eppnt->p_offset & 0xfffff000)); 313 (unsigned long) (eppnt->p_offset & 0xfffff000));
315#endif
316 down_write(&current->mm->mmap_sem); 314 down_write(&current->mm->mmap_sem);
317 error = do_mmap(interpreter, vaddr, 315 error = do_mmap(interpreter, vaddr,
318 eppnt->p_filesz + (eppnt->p_vaddr & 0xfff), 316 eppnt->p_filesz + (eppnt->p_vaddr & 0xfff),
@@ -324,14 +322,10 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
324 printk("Aieee IRIX interp mmap error=%d\n", error); 322 printk("Aieee IRIX interp mmap error=%d\n", error);
325 break; /* Real error */ 323 break; /* Real error */
326 } 324 }
327#ifdef DEBUG_ELF 325 pr_debug("error=%08lx ", (unsigned long) error);
328 printk("error=%08lx ", (unsigned long) error);
329#endif
330 if(!load_addr && interp_elf_ex->e_type == ET_DYN) { 326 if(!load_addr && interp_elf_ex->e_type == ET_DYN) {
331 load_addr = error; 327 load_addr = error;
332#ifdef DEBUG_ELF 328 pr_debug("load_addr = error ");
333 printk("load_addr = error ");
334#endif
335 } 329 }
336 330
337 /* Find the end of the file mapping for this phdr, and keep 331 /* Find the end of the file mapping for this phdr, and keep
@@ -345,17 +339,13 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
345 */ 339 */
346 k = eppnt->p_memsz + eppnt->p_vaddr; 340 k = eppnt->p_memsz + eppnt->p_vaddr;
347 if(k > last_bss) last_bss = k; 341 if(k > last_bss) last_bss = k;
348#ifdef DEBUG_ELF 342 pr_debug("\n");
349 printk("\n");
350#endif
351 } 343 }
352 } 344 }
353 345
354 /* Now use mmap to map the library into memory. */ 346 /* Now use mmap to map the library into memory. */
355 if(error < 0 && error > -1024) { 347 if(error < 0 && error > -1024) {
356#ifdef DEBUG_ELF 348 pr_debug("got error %d\n", error);
357 printk("got error %d\n", error);
358#endif
359 kfree(elf_phdata); 349 kfree(elf_phdata);
360 return 0xffffffff; 350 return 0xffffffff;
361 } 351 }
@@ -365,16 +355,12 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
365 * that there are zero-mapped pages up to and including the 355 * that there are zero-mapped pages up to and including the
366 * last bss page. 356 * last bss page.
367 */ 357 */
368#ifdef DEBUG_ELF 358 pr_debug("padzero(%08lx) ", (unsigned long) (elf_bss));
369 printk("padzero(%08lx) ", (unsigned long) (elf_bss));
370#endif
371 padzero(elf_bss); 359 padzero(elf_bss);
372 len = (elf_bss + 0xfff) & 0xfffff000; /* What we have mapped so far */ 360 len = (elf_bss + 0xfff) & 0xfffff000; /* What we have mapped so far */
373 361
374#ifdef DEBUG_ELF 362 pr_debug("last_bss[%08lx] len[%08lx]\n", (unsigned long) last_bss,
375 printk("last_bss[%08lx] len[%08lx]\n", (unsigned long) last_bss, 363 (unsigned long) len);
376 (unsigned long) len);
377#endif
378 364
379 /* Map the last of the bss segment */ 365 /* Map the last of the bss segment */
380 if (last_bss > len) { 366 if (last_bss > len) {
@@ -396,12 +382,7 @@ static int verify_binary(struct elfhdr *ehp, struct linux_binprm *bprm)
396 382
397 /* First of all, some simple consistency checks */ 383 /* First of all, some simple consistency checks */
398 if((ehp->e_type != ET_EXEC && ehp->e_type != ET_DYN) || 384 if((ehp->e_type != ET_EXEC && ehp->e_type != ET_DYN) ||
399 !irix_elf_check_arch(ehp) || !bprm->file->f_op->mmap) { 385 !bprm->file->f_op->mmap) {
400 return -ENOEXEC;
401 }
402
403 /* Only support MIPS ARCH2 or greater IRIX binaries for now. */
404 if(!(ehp->e_flags & EF_MIPS_ARCH) && !(ehp->e_flags & 0x04)) {
405 return -ENOEXEC; 386 return -ENOEXEC;
406 } 387 }
407 388
@@ -411,16 +392,17 @@ static int verify_binary(struct elfhdr *ehp, struct linux_binprm *bprm)
411 * XXX all registers as 64bits on cpu's capable of this at 392 * XXX all registers as 64bits on cpu's capable of this at
412 * XXX exception time plus frob the XTLB exception vector. 393 * XXX exception time plus frob the XTLB exception vector.
413 */ 394 */
414 if((ehp->e_flags & 0x20)) { 395 if((ehp->e_flags & EF_MIPS_ABI2))
415 return -ENOEXEC; 396 return -ENOEXEC;
416 }
417 397
418 return 0; /* It's ok. */ 398 return 0;
419} 399}
420 400
421#define IRIX_INTERP_PREFIX "/usr/gnemul/irix" 401/*
422 402 * This is where the detailed check is performed. Irix binaries
423/* Look for an IRIX ELF interpreter. */ 403 * use interpreters with 'libc.so' in the name, so this function
404 * can differentiate between Linux and Irix binaries.
405 */
424static inline int look_for_irix_interpreter(char **name, 406static inline int look_for_irix_interpreter(char **name,
425 struct file **interpreter, 407 struct file **interpreter,
426 struct elfhdr *interp_elf_ex, 408 struct elfhdr *interp_elf_ex,
@@ -440,12 +422,11 @@ static inline int look_for_irix_interpreter(char **name,
440 if (*name != NULL) 422 if (*name != NULL)
441 goto out; 423 goto out;
442 424
443 *name = kmalloc((epp->p_filesz + strlen(IRIX_INTERP_PREFIX)), 425 *name = kmalloc(epp->p_filesz + strlen(IRIX_EMUL), GFP_KERNEL);
444 GFP_KERNEL);
445 if (!*name) 426 if (!*name)
446 return -ENOMEM; 427 return -ENOMEM;
447 428
448 strcpy(*name, IRIX_INTERP_PREFIX); 429 strcpy(*name, IRIX_EMUL);
449 retval = kernel_read(bprm->file, epp->p_offset, (*name + 16), 430 retval = kernel_read(bprm->file, epp->p_offset, (*name + 16),
450 epp->p_filesz); 431 epp->p_filesz);
451 if (retval < 0) 432 if (retval < 0)
@@ -562,7 +543,7 @@ static inline int map_interpreter(struct elf_phdr *epp, struct elfhdr *ihp,
562 * process and the system, here we map the page and fill the 543 * process and the system, here we map the page and fill the
563 * structure 544 * structure
564 */ 545 */
565void irix_map_prda_page (void) 546static void irix_map_prda_page(void)
566{ 547{
567 unsigned long v; 548 unsigned long v;
568 struct prda *pp; 549 struct prda *pp;
@@ -601,14 +582,33 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs)
601 582
602 load_addr = 0; 583 load_addr = 0;
603 has_interp = has_ephdr = 0; 584 has_interp = has_ephdr = 0;
604 elf_ihdr = elf_ephdr = 0; 585 elf_ihdr = elf_ephdr = NULL;
605 elf_ex = *((struct elfhdr *) bprm->buf); 586 elf_ex = *((struct elfhdr *) bprm->buf);
606 retval = -ENOEXEC; 587 retval = -ENOEXEC;
607 588
608 if (verify_binary(&elf_ex, bprm)) 589 if (verify_binary(&elf_ex, bprm))
609 goto out; 590 goto out;
610 591
611#ifdef DEBUG_ELF 592 /*
593 * Telling -o32 static binaries from Linux and Irix apart from each
594 * other is difficult. There are 2 differences to be noted for static
595 * binaries from the 2 operating systems:
596 *
597 * 1) Irix binaries have their .text section before their .init
598 * section. Linux binaries are just the opposite.
599 *
600 * 2) Irix binaries usually have <= 12 sections and Linux
601 * binaries have > 20.
602 *
603 * We will use Method #2 since Method #1 would require us to read in
604 * the section headers which is way too much overhead. This appears
605 * to work for everything we have ran into so far. If anyone has a
606 * better method to tell the binaries apart, I'm listening.
607 */
608 if (elf_ex.e_shnum > 20)
609 goto out;
610
611#ifdef DEBUG
612 print_elfhdr(&elf_ex); 612 print_elfhdr(&elf_ex);
613#endif 613#endif
614 614
@@ -623,11 +623,10 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs)
623 } 623 }
624 624
625 retval = kernel_read(bprm->file, elf_ex.e_phoff, (char *)elf_phdata, size); 625 retval = kernel_read(bprm->file, elf_ex.e_phoff, (char *)elf_phdata, size);
626
627 if (retval < 0) 626 if (retval < 0)
628 goto out_free_ph; 627 goto out_free_ph;
629 628
630#ifdef DEBUG_ELF 629#ifdef DEBUG
631 dump_phdrs(elf_phdata, elf_ex.e_phnum); 630 dump_phdrs(elf_phdata, elf_ex.e_phnum);
632#endif 631#endif
633 632
@@ -644,9 +643,8 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs)
644 break; 643 break;
645 }; 644 };
646 } 645 }
647#ifdef DEBUG_ELF 646
648 printk("\n"); 647 pr_debug("\n");
649#endif
650 648
651 elf_bss = 0; 649 elf_bss = 0;
652 elf_brk = 0; 650 elf_brk = 0;
@@ -657,12 +655,19 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs)
657 end_code = 0; 655 end_code = 0;
658 end_data = 0; 656 end_data = 0;
659 657
660 retval = look_for_irix_interpreter(&elf_interpreter, 658 /*
661 &interpreter, 659 * If we get a return value, we change the value to be ENOEXEC
660 * so that we can exit gracefully and the main binary format
661 * search loop in 'fs/exec.c' will move onto the next handler
662 * which should be the normal ELF binary handler.
663 */
664 retval = look_for_irix_interpreter(&elf_interpreter, &interpreter,
662 &interp_elf_ex, elf_phdata, bprm, 665 &interp_elf_ex, elf_phdata, bprm,
663 elf_ex.e_phnum); 666 elf_ex.e_phnum);
664 if (retval) 667 if (retval) {
668 retval = -ENOEXEC;
665 goto out_free_file; 669 goto out_free_file;
670 }
666 671
667 if (elf_interpreter) { 672 if (elf_interpreter) {
668 retval = verify_irix_interpreter(&interp_elf_ex); 673 retval = verify_irix_interpreter(&interp_elf_ex);
@@ -746,18 +751,16 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs)
746 * IRIX maps a page at 0x200000 which holds some system 751 * IRIX maps a page at 0x200000 which holds some system
747 * information. Programs depend on this. 752 * information. Programs depend on this.
748 */ 753 */
749 irix_map_prda_page (); 754 irix_map_prda_page();
750 755
751 padzero(elf_bss); 756 padzero(elf_bss);
752 757
753#ifdef DEBUG_ELF 758 pr_debug("(start_brk) %lx\n" , (long) current->mm->start_brk);
754 printk("(start_brk) %lx\n" , (long) current->mm->start_brk); 759 pr_debug("(end_code) %lx\n" , (long) current->mm->end_code);
755 printk("(end_code) %lx\n" , (long) current->mm->end_code); 760 pr_debug("(start_code) %lx\n" , (long) current->mm->start_code);
756 printk("(start_code) %lx\n" , (long) current->mm->start_code); 761 pr_debug("(end_data) %lx\n" , (long) current->mm->end_data);
757 printk("(end_data) %lx\n" , (long) current->mm->end_data); 762 pr_debug("(start_stack) %lx\n" , (long) current->mm->start_stack);
758 printk("(start_stack) %lx\n" , (long) current->mm->start_stack); 763 pr_debug("(brk) %lx\n" , (long) current->mm->brk);
759 printk("(brk) %lx\n" , (long) current->mm->brk);
760#endif
761 764
762#if 0 /* XXX No fucking way dude... */ 765#if 0 /* XXX No fucking way dude... */
763 /* Why this, you ask??? Well SVr4 maps page 0 as read-only, 766 /* Why this, you ask??? Well SVr4 maps page 0 as read-only,
@@ -782,8 +785,7 @@ out_free_dentry:
782 allow_write_access(interpreter); 785 allow_write_access(interpreter);
783 fput(interpreter); 786 fput(interpreter);
784out_free_interp: 787out_free_interp:
785 if (elf_interpreter) 788 kfree(elf_interpreter);
786 kfree(elf_interpreter);
787out_free_file: 789out_free_file:
788out_free_ph: 790out_free_ph:
789 kfree (elf_phdata); 791 kfree (elf_phdata);
@@ -813,7 +815,7 @@ static int load_irix_library(struct file *file)
813 815
814 /* First of all, some simple consistency checks. */ 816 /* First of all, some simple consistency checks. */
815 if(elf_ex.e_type != ET_EXEC || elf_ex.e_phnum > 2 || 817 if(elf_ex.e_type != ET_EXEC || elf_ex.e_phnum > 2 ||
816 !irix_elf_check_arch(&elf_ex) || !file->f_op->mmap) 818 !file->f_op->mmap)
817 return -ENOEXEC; 819 return -ENOEXEC;
818 820
819 /* Now read in all of the header information. */ 821 /* Now read in all of the header information. */
@@ -874,35 +876,36 @@ static int load_irix_library(struct file *file)
874 * phdrs there are in the USER_PHDRP array. We return the vaddr the 876 * phdrs there are in the USER_PHDRP array. We return the vaddr the
875 * first phdr was successfully mapped to. 877 * first phdr was successfully mapped to.
876 */ 878 */
877unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt) 879unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt)
878{ 880{
879 struct elf_phdr *hp; 881 unsigned long type, vaddr, filesz, offset, flags;
882 struct elf_phdr __user *hp;
880 struct file *filp; 883 struct file *filp;
881 int i, retval; 884 int i, retval;
882 885
883#ifdef DEBUG_ELF 886 pr_debug("irix_mapelf: fd[%d] user_phdrp[%p] cnt[%d]\n",
884 printk("irix_mapelf: fd[%d] user_phdrp[%p] cnt[%d]\n", 887 fd, user_phdrp, cnt);
885 fd, user_phdrp, cnt);
886#endif
887 888
888 /* First get the verification out of the way. */ 889 /* First get the verification out of the way. */
889 hp = user_phdrp; 890 hp = user_phdrp;
890 if (!access_ok(VERIFY_READ, hp, (sizeof(struct elf_phdr) * cnt))) { 891 if (!access_ok(VERIFY_READ, hp, (sizeof(struct elf_phdr) * cnt))) {
891#ifdef DEBUG_ELF 892 pr_debug("irix_mapelf: bad pointer to ELF PHDR!\n");
892 printk("irix_mapelf: access_ok fails!\n"); 893
893#endif
894 return -EFAULT; 894 return -EFAULT;
895 } 895 }
896 896
897#ifdef DEBUG_ELF 897#ifdef DEBUG
898 dump_phdrs(user_phdrp, cnt); 898 dump_phdrs(user_phdrp, cnt);
899#endif 899#endif
900 900
901 for(i = 0; i < cnt; i++, hp++) 901 for (i = 0; i < cnt; i++, hp++) {
902 if(hp->p_type != PT_LOAD) { 902 if (__get_user(type, &hp->p_type))
903 return -EFAULT;
904 if (type != PT_LOAD) {
903 printk("irix_mapelf: One section is not PT_LOAD!\n"); 905 printk("irix_mapelf: One section is not PT_LOAD!\n");
904 return -ENOEXEC; 906 return -ENOEXEC;
905 } 907 }
908 }
906 909
907 filp = fget(fd); 910 filp = fget(fd);
908 if (!filp) 911 if (!filp)
@@ -917,29 +920,40 @@ unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt)
917 for(i = 0; i < cnt; i++, hp++) { 920 for(i = 0; i < cnt; i++, hp++) {
918 int prot; 921 int prot;
919 922
920 prot = (hp->p_flags & PF_R) ? PROT_READ : 0; 923 retval = __get_user(vaddr, &hp->p_vaddr);
921 prot |= (hp->p_flags & PF_W) ? PROT_WRITE : 0; 924 retval |= __get_user(filesz, &hp->p_filesz);
922 prot |= (hp->p_flags & PF_X) ? PROT_EXEC : 0; 925 retval |= __get_user(offset, &hp->p_offset);
926 retval |= __get_user(flags, &hp->p_flags);
927 if (retval)
928 return retval;
929
930 prot = (flags & PF_R) ? PROT_READ : 0;
931 prot |= (flags & PF_W) ? PROT_WRITE : 0;
932 prot |= (flags & PF_X) ? PROT_EXEC : 0;
933
923 down_write(&current->mm->mmap_sem); 934 down_write(&current->mm->mmap_sem);
924 retval = do_mmap(filp, (hp->p_vaddr & 0xfffff000), 935 retval = do_mmap(filp, (vaddr & 0xfffff000),
925 (hp->p_filesz + (hp->p_vaddr & 0xfff)), 936 (filesz + (vaddr & 0xfff)),
926 prot, (MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE), 937 prot, (MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE),
927 (hp->p_offset & 0xfffff000)); 938 (offset & 0xfffff000));
928 up_write(&current->mm->mmap_sem); 939 up_write(&current->mm->mmap_sem);
929 940
930 if(retval != (hp->p_vaddr & 0xfffff000)) { 941 if (retval != (vaddr & 0xfffff000)) {
931 printk("irix_mapelf: do_mmap fails with %d!\n", retval); 942 printk("irix_mapelf: do_mmap fails with %d!\n", retval);
932 fput(filp); 943 fput(filp);
933 return retval; 944 return retval;
934 } 945 }
935 } 946 }
936 947
937#ifdef DEBUG_ELF 948 pr_debug("irix_mapelf: Success, returning %08lx\n",
938 printk("irix_mapelf: Success, returning %08lx\n", 949 (unsigned long) user_phdrp->p_vaddr);
939 (unsigned long) user_phdrp->p_vaddr); 950
940#endif
941 fput(filp); 951 fput(filp);
942 return user_phdrp->p_vaddr; 952
953 if (__get_user(vaddr, &user_phdrp->p_vaddr))
954 return -EFAULT;
955
956 return vaddr;
943} 957}
944 958
945/* 959/*
@@ -952,9 +966,9 @@ unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt)
952/* These are the only things you should do on a core-file: use only these 966/* These are the only things you should do on a core-file: use only these
953 * functions to write out all the necessary info. 967 * functions to write out all the necessary info.
954 */ 968 */
955static int dump_write(struct file *file, const void *addr, int nr) 969static int dump_write(struct file *file, const void __user *addr, int nr)
956{ 970{
957 return file->f_op->write(file, addr, nr, &file->f_pos) == nr; 971 return file->f_op->write(file, (const char __user *) addr, nr, &file->f_pos) == nr;
958} 972}
959 973
960static int dump_seek(struct file *file, off_t off) 974static int dump_seek(struct file *file, off_t off)
@@ -1073,7 +1087,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
1073 /* Count what's needed to dump, up to the limit of coredump size. */ 1087 /* Count what's needed to dump, up to the limit of coredump size. */
1074 segs = 0; 1088 segs = 0;
1075 size = 0; 1089 size = 0;
1076 for(vma = current->mm->mmap; vma != NULL; vma = vma->vm_next) { 1090 for (vma = current->mm->mmap; vma != NULL; vma = vma->vm_next) {
1077 if (maydump(vma)) 1091 if (maydump(vma))
1078 { 1092 {
1079 int sz = vma->vm_end-vma->vm_start; 1093 int sz = vma->vm_end-vma->vm_start;
@@ -1187,9 +1201,9 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
1187 1201
1188 len = current->mm->arg_end - current->mm->arg_start; 1202 len = current->mm->arg_end - current->mm->arg_start;
1189 len = len >= ELF_PRARGSZ ? ELF_PRARGSZ : len; 1203 len = len >= ELF_PRARGSZ ? ELF_PRARGSZ : len;
1190 copy_from_user(&psinfo.pr_psargs, 1204 (void *) copy_from_user(&psinfo.pr_psargs,
1191 (const char *)current->mm->arg_start, len); 1205 (const char __user *)current->mm->arg_start, len);
1192 for(i = 0; i < len; i++) 1206 for (i = 0; i < len; i++)
1193 if (psinfo.pr_psargs[i] == 0) 1207 if (psinfo.pr_psargs[i] == 0)
1194 psinfo.pr_psargs[i] = ' '; 1208 psinfo.pr_psargs[i] = ' ';
1195 psinfo.pr_psargs[len] = 0; 1209 psinfo.pr_psargs[len] = 0;
@@ -1256,8 +1270,10 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
1256 phdr.p_memsz = sz; 1270 phdr.p_memsz = sz;
1257 offset += phdr.p_filesz; 1271 offset += phdr.p_filesz;
1258 phdr.p_flags = vma->vm_flags & VM_READ ? PF_R : 0; 1272 phdr.p_flags = vma->vm_flags & VM_READ ? PF_R : 0;
1259 if (vma->vm_flags & VM_WRITE) phdr.p_flags |= PF_W; 1273 if (vma->vm_flags & VM_WRITE)
1260 if (vma->vm_flags & VM_EXEC) phdr.p_flags |= PF_X; 1274 phdr.p_flags |= PF_W;
1275 if (vma->vm_flags & VM_EXEC)
1276 phdr.p_flags |= PF_X;
1261 phdr.p_align = PAGE_SIZE; 1277 phdr.p_align = PAGE_SIZE;
1262 1278
1263 DUMP_WRITE(&phdr, sizeof(phdr)); 1279 DUMP_WRITE(&phdr, sizeof(phdr));
@@ -1283,7 +1299,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
1283#ifdef DEBUG 1299#ifdef DEBUG
1284 printk("elf_core_dump: writing %08lx %lx\n", addr, len); 1300 printk("elf_core_dump: writing %08lx %lx\n", addr, len);
1285#endif 1301#endif
1286 DUMP_WRITE((void *)addr, len); 1302 DUMP_WRITE((void __user *)addr, len);
1287 } 1303 }
1288 1304
1289 if ((off_t) file->f_pos != offset) { 1305 if ((off_t) file->f_pos != offset) {
@@ -1299,7 +1315,7 @@ end_coredump:
1299 1315
1300static int __init init_irix_binfmt(void) 1316static int __init init_irix_binfmt(void)
1301{ 1317{
1302 int init_inventory(void); 1318 extern int init_inventory(void);
1303 extern asmlinkage unsigned long sys_call_table; 1319 extern asmlinkage unsigned long sys_call_table;
1304 extern asmlinkage unsigned long sys_call_table_irix5; 1320 extern asmlinkage unsigned long sys_call_table_irix5;
1305 1321
@@ -1318,7 +1334,9 @@ static int __init init_irix_binfmt(void)
1318 1334
1319static void __exit exit_irix_binfmt(void) 1335static void __exit exit_irix_binfmt(void)
1320{ 1336{
1321 /* Remove the IRIX ELF loaders. */ 1337 /*
1338 * Remove the Irix ELF loader.
1339 */
1322 unregister_binfmt(&irix_format); 1340 unregister_binfmt(&irix_format);
1323} 1341}
1324 1342
diff --git a/arch/mips/kernel/irixinv.c b/arch/mips/kernel/irixinv.c
index 60aa98cd1791..de8584f62311 100644
--- a/arch/mips/kernel/irixinv.c
+++ b/arch/mips/kernel/irixinv.c
@@ -30,10 +30,10 @@ void add_to_inventory (int class, int type, int controller, int unit, int state)
30 inventory_items++; 30 inventory_items++;
31} 31}
32 32
33int dump_inventory_to_user (void *userbuf, int size) 33int dump_inventory_to_user (void __user *userbuf, int size)
34{ 34{
35 inventory_t *inv = &inventory [0]; 35 inventory_t *inv = &inventory [0];
36 inventory_t *user = userbuf; 36 inventory_t __user *user = userbuf;
37 int v; 37 int v;
38 38
39 if (!access_ok(VERIFY_WRITE, userbuf, size)) 39 if (!access_ok(VERIFY_WRITE, userbuf, size))
@@ -41,7 +41,8 @@ int dump_inventory_to_user (void *userbuf, int size)
41 41
42 for (v = 0; v < inventory_items; v++){ 42 for (v = 0; v < inventory_items; v++){
43 inv = &inventory [v]; 43 inv = &inventory [v];
44 copy_to_user (user, inv, sizeof (inventory_t)); 44 if (copy_to_user (user, inv, sizeof (inventory_t)))
45 return -EFAULT;
45 user++; 46 user++;
46 } 47 }
47 return inventory_items * sizeof (inventory_t); 48 return inventory_items * sizeof (inventory_t);
diff --git a/arch/mips/kernel/irixioctl.c b/arch/mips/kernel/irixioctl.c
index 3cdc22346f4c..e2863821a3dd 100644
--- a/arch/mips/kernel/irixioctl.c
+++ b/arch/mips/kernel/irixioctl.c
@@ -59,7 +59,7 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg)
59{ 59{
60 struct tty_struct *tp, *rtp; 60 struct tty_struct *tp, *rtp;
61 mm_segment_t old_fs; 61 mm_segment_t old_fs;
62 int error = 0; 62 int i, error = 0;
63 63
64#ifdef DEBUG_IOCTLS 64#ifdef DEBUG_IOCTLS
65 printk("[%s:%d] irix_ioctl(%d, ", current->comm, current->pid, fd); 65 printk("[%s:%d] irix_ioctl(%d, ", current->comm, current->pid, fd);
@@ -74,12 +74,13 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg)
74 74
75 case 0x0000540d: { 75 case 0x0000540d: {
76 struct termios kt; 76 struct termios kt;
77 struct irix_termios *it = (struct irix_termios *) arg; 77 struct irix_termios __user *it =
78 (struct irix_termios __user *) arg;
78 79
79#ifdef DEBUG_IOCTLS 80#ifdef DEBUG_IOCTLS
80 printk("TCGETS, %08lx) ", arg); 81 printk("TCGETS, %08lx) ", arg);
81#endif 82#endif
82 if(!access_ok(VERIFY_WRITE, it, sizeof(*it))) { 83 if (!access_ok(VERIFY_WRITE, it, sizeof(*it))) {
83 error = -EFAULT; 84 error = -EFAULT;
84 break; 85 break;
85 } 86 }
@@ -88,13 +89,14 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg)
88 set_fs(old_fs); 89 set_fs(old_fs);
89 if (error) 90 if (error)
90 break; 91 break;
91 __put_user(kt.c_iflag, &it->c_iflag); 92
92 __put_user(kt.c_oflag, &it->c_oflag); 93 error = __put_user(kt.c_iflag, &it->c_iflag);
93 __put_user(kt.c_cflag, &it->c_cflag); 94 error |= __put_user(kt.c_oflag, &it->c_oflag);
94 __put_user(kt.c_lflag, &it->c_lflag); 95 error |= __put_user(kt.c_cflag, &it->c_cflag);
95 for(error = 0; error < NCCS; error++) 96 error |= __put_user(kt.c_lflag, &it->c_lflag);
96 __put_user(kt.c_cc[error], &it->c_cc[error]); 97
97 error = 0; 98 for (i = 0; i < NCCS; i++)
99 error |= __put_user(kt.c_cc[i], &it->c_cc[i]);
98 break; 100 break;
99 } 101 }
100 102
@@ -112,14 +114,19 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg)
112 old_fs = get_fs(); set_fs(get_ds()); 114 old_fs = get_fs(); set_fs(get_ds());
113 error = sys_ioctl(fd, TCGETS, (unsigned long) &kt); 115 error = sys_ioctl(fd, TCGETS, (unsigned long) &kt);
114 set_fs(old_fs); 116 set_fs(old_fs);
115 if(error) 117 if (error)
118 break;
119
120 error = __get_user(kt.c_iflag, &it->c_iflag);
121 error |= __get_user(kt.c_oflag, &it->c_oflag);
122 error |= __get_user(kt.c_cflag, &it->c_cflag);
123 error |= __get_user(kt.c_lflag, &it->c_lflag);
124
125 for (i = 0; i < NCCS; i++)
126 error |= __get_user(kt.c_cc[i], &it->c_cc[i]);
127
128 if (error)
116 break; 129 break;
117 __get_user(kt.c_iflag, &it->c_iflag);
118 __get_user(kt.c_oflag, &it->c_oflag);
119 __get_user(kt.c_cflag, &it->c_cflag);
120 __get_user(kt.c_lflag, &it->c_lflag);
121 for(error = 0; error < NCCS; error++)
122 __get_user(kt.c_cc[error], &it->c_cc[error]);
123 old_fs = get_fs(); set_fs(get_ds()); 130 old_fs = get_fs(); set_fs(get_ds());
124 error = sys_ioctl(fd, TCSETS, (unsigned long) &kt); 131 error = sys_ioctl(fd, TCSETS, (unsigned long) &kt);
125 set_fs(old_fs); 132 set_fs(old_fs);
@@ -153,7 +160,7 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg)
153#ifdef DEBUG_IOCTLS 160#ifdef DEBUG_IOCTLS
154 printk("rtp->session=%d ", rtp->session); 161 printk("rtp->session=%d ", rtp->session);
155#endif 162#endif
156 error = put_user(rtp->session, (unsigned long *) arg); 163 error = put_user(rtp->session, (unsigned long __user *) arg);
157 break; 164 break;
158 165
159 case 0x746e: 166 case 0x746e:
@@ -195,50 +202,32 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg)
195 break; 202 break;
196 203
197 case 0x8004667e: 204 case 0x8004667e:
198#ifdef DEBUG_IOCTLS
199 printk("FIONBIO, %08lx) arg=%d ", arg, *(int *)arg);
200#endif
201 error = sys_ioctl(fd, FIONBIO, arg); 205 error = sys_ioctl(fd, FIONBIO, arg);
202 break; 206 break;
203 207
204 case 0x80047476: 208 case 0x80047476:
205#ifdef DEBUG_IOCTLS
206 printk("TIOCSPGRP, %08lx) arg=%d ", arg, *(int *)arg);
207#endif
208 error = sys_ioctl(fd, TIOCSPGRP, arg); 209 error = sys_ioctl(fd, TIOCSPGRP, arg);
209 break; 210 break;
210 211
211 case 0x8020690c: 212 case 0x8020690c:
212#ifdef DEBUG_IOCTLS
213 printk("SIOCSIFADDR, %08lx) arg=%d ", arg, *(int *)arg);
214#endif
215 error = sys_ioctl(fd, SIOCSIFADDR, arg); 213 error = sys_ioctl(fd, SIOCSIFADDR, arg);
216 break; 214 break;
217 215
218 case 0x80206910: 216 case 0x80206910:
219#ifdef DEBUG_IOCTLS
220 printk("SIOCSIFFLAGS, %08lx) arg=%d ", arg, *(int *)arg);
221#endif
222 error = sys_ioctl(fd, SIOCSIFFLAGS, arg); 217 error = sys_ioctl(fd, SIOCSIFFLAGS, arg);
223 break; 218 break;
224 219
225 case 0xc0206911: 220 case 0xc0206911:
226#ifdef DEBUG_IOCTLS
227 printk("SIOCGIFFLAGS, %08lx) arg=%d ", arg, *(int *)arg);
228#endif
229 error = sys_ioctl(fd, SIOCGIFFLAGS, arg); 221 error = sys_ioctl(fd, SIOCGIFFLAGS, arg);
230 break; 222 break;
231 223
232 case 0xc020691b: 224 case 0xc020691b:
233#ifdef DEBUG_IOCTLS
234 printk("SIOCGIFMETRIC, %08lx) arg=%d ", arg, *(int *)arg);
235#endif
236 error = sys_ioctl(fd, SIOCGIFMETRIC, arg); 225 error = sys_ioctl(fd, SIOCGIFMETRIC, arg);
237 break; 226 break;
238 227
239 default: { 228 default: {
240#ifdef DEBUG_MISSING_IOCTL 229#ifdef DEBUG_MISSING_IOCTL
241 char *msg = "Unimplemented IOCTL cmd tell linux@engr.sgi.com\n"; 230 char *msg = "Unimplemented IOCTL cmd tell linux-mips@linux-mips.org\n";
242 231
243#ifdef DEBUG_IOCTLS 232#ifdef DEBUG_IOCTLS
244 printk("UNIMP_IOCTL, %08lx)\n", arg); 233 printk("UNIMP_IOCTL, %08lx)\n", arg);
diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c
index eff89322ba50..908e63684208 100644
--- a/arch/mips/kernel/irixsig.c
+++ b/arch/mips/kernel/irixsig.c
@@ -76,36 +76,39 @@ static inline void dump_irix5_sigctx(struct sigctx_irix5 *c)
76} 76}
77#endif 77#endif
78 78
79static void setup_irix_frame(struct k_sigaction *ka, struct pt_regs *regs, 79static int setup_irix_frame(struct k_sigaction *ka, struct pt_regs *regs,
80 int signr, sigset_t *oldmask) 80 int signr, sigset_t *oldmask)
81{ 81{
82 struct sigctx_irix5 __user *ctx;
82 unsigned long sp; 83 unsigned long sp;
83 struct sigctx_irix5 *ctx; 84 int error, i;
84 int i;
85 85
86 sp = regs->regs[29]; 86 sp = regs->regs[29];
87 sp -= sizeof(struct sigctx_irix5); 87 sp -= sizeof(struct sigctx_irix5);
88 sp &= ~(0xf); 88 sp &= ~(0xf);
89 ctx = (struct sigctx_irix5 *) sp; 89 ctx = (struct sigctx_irix5 __user *) sp;
90 if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))) 90 if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx)))
91 goto segv_and_exit; 91 goto segv_and_exit;
92 92
93 __put_user(0, &ctx->weird_fpu_thing); 93 error = __put_user(0, &ctx->weird_fpu_thing);
94 __put_user(~(0x00000001), &ctx->rmask); 94 error |= __put_user(~(0x00000001), &ctx->rmask);
95 __put_user(0, &ctx->regs[0]); 95 error |= __put_user(0, &ctx->regs[0]);
96 for(i = 1; i < 32; i++) 96 for(i = 1; i < 32; i++)
97 __put_user((u64) regs->regs[i], &ctx->regs[i]); 97 error |= __put_user((u64) regs->regs[i], &ctx->regs[i]);
98
99 error |= __put_user((u64) regs->hi, &ctx->hi);
100 error |= __put_user((u64) regs->lo, &ctx->lo);
101 error |= __put_user((u64) regs->cp0_epc, &ctx->pc);
102 error |= __put_user(!!used_math(), &ctx->usedfp);
103 error |= __put_user((u64) regs->cp0_cause, &ctx->cp0_cause);
104 error |= __put_user((u64) regs->cp0_badvaddr, &ctx->cp0_badvaddr);
98 105
99 __put_user((u64) regs->hi, &ctx->hi); 106 error |= __put_user(0, &ctx->sstk_flags); /* XXX sigstack unimp... todo... */
100 __put_user((u64) regs->lo, &ctx->lo);
101 __put_user((u64) regs->cp0_epc, &ctx->pc);
102 __put_user(!!used_math(), &ctx->usedfp);
103 __put_user((u64) regs->cp0_cause, &ctx->cp0_cause);
104 __put_user((u64) regs->cp0_badvaddr, &ctx->cp0_badvaddr);
105 107
106 __put_user(0, &ctx->sstk_flags); /* XXX sigstack unimp... todo... */ 108 error |= __copy_to_user(&ctx->sigset, oldmask, sizeof(irix_sigset_t)) ? -EFAULT : 0;
107 109
108 __copy_to_user(&ctx->sigset, oldmask, sizeof(irix_sigset_t)); 110 if (error)
111 goto segv_and_exit;
109 112
110#ifdef DEBUG_SIG 113#ifdef DEBUG_SIG
111 dump_irix5_sigctx(ctx); 114 dump_irix5_sigctx(ctx);
@@ -117,13 +120,14 @@ static void setup_irix_frame(struct k_sigaction *ka, struct pt_regs *regs,
117 regs->regs[7] = (unsigned long) ka->sa.sa_handler; 120 regs->regs[7] = (unsigned long) ka->sa.sa_handler;
118 regs->regs[25] = regs->cp0_epc = (unsigned long) ka->sa_restorer; 121 regs->regs[25] = regs->cp0_epc = (unsigned long) ka->sa_restorer;
119 122
120 return; 123 return 1;
121 124
122segv_and_exit: 125segv_and_exit:
123 force_sigsegv(signr, current); 126 force_sigsegv(signr, current);
127 return 0;
124} 128}
125 129
126static void inline 130static int inline
127setup_irix_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, 131setup_irix_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
128 int signr, sigset_t *oldmask, siginfo_t *info) 132 int signr, sigset_t *oldmask, siginfo_t *info)
129{ 133{
@@ -131,9 +135,11 @@ setup_irix_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
131 do_exit(SIGSEGV); 135 do_exit(SIGSEGV);
132} 136}
133 137
134static inline void handle_signal(unsigned long sig, siginfo_t *info, 138static inline int handle_signal(unsigned long sig, siginfo_t *info,
135 struct k_sigaction *ka, sigset_t *oldset, struct pt_regs * regs) 139 struct k_sigaction *ka, sigset_t *oldset, struct pt_regs * regs)
136{ 140{
141 int ret;
142
137 switch(regs->regs[0]) { 143 switch(regs->regs[0]) {
138 case ERESTARTNOHAND: 144 case ERESTARTNOHAND:
139 regs->regs[2] = EINTR; 145 regs->regs[2] = EINTR;
@@ -151,9 +157,9 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info,
151 regs->regs[0] = 0; /* Don't deal with this again. */ 157 regs->regs[0] = 0; /* Don't deal with this again. */
152 158
153 if (ka->sa.sa_flags & SA_SIGINFO) 159 if (ka->sa.sa_flags & SA_SIGINFO)
154 setup_irix_rt_frame(ka, regs, sig, oldset, info); 160 ret = setup_irix_rt_frame(ka, regs, sig, oldset, info);
155 else 161 else
156 setup_irix_frame(ka, regs, sig, oldset); 162 ret = setup_irix_frame(ka, regs, sig, oldset);
157 163
158 spin_lock_irq(&current->sighand->siglock); 164 spin_lock_irq(&current->sighand->siglock);
159 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 165 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
@@ -161,6 +167,8 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info,
161 sigaddset(&current->blocked,sig); 167 sigaddset(&current->blocked,sig);
162 recalc_sigpending(); 168 recalc_sigpending();
163 spin_unlock_irq(&current->sighand->siglock); 169 spin_unlock_irq(&current->sighand->siglock);
170
171 return ret;
164} 172}
165 173
166asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs) 174asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs)
@@ -184,10 +192,8 @@ asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs)
184 oldset = &current->blocked; 192 oldset = &current->blocked;
185 193
186 signr = get_signal_to_deliver(&info, &ka, regs, NULL); 194 signr = get_signal_to_deliver(&info, &ka, regs, NULL);
187 if (signr > 0) { 195 if (signr > 0)
188 handle_signal(signr, &info, &ka, oldset, regs); 196 return handle_signal(signr, &info, &ka, oldset, regs);
189 return 1;
190 }
191 197
192no_signal: 198no_signal:
193 /* 199 /*
@@ -208,10 +214,11 @@ no_signal:
208asmlinkage void 214asmlinkage void
209irix_sigreturn(struct pt_regs *regs) 215irix_sigreturn(struct pt_regs *regs)
210{ 216{
211 struct sigctx_irix5 *context, *magic; 217 struct sigctx_irix5 __user *context, *magic;
212 unsigned long umask, mask; 218 unsigned long umask, mask;
213 u64 *fregs; 219 u64 *fregs;
214 int sig, i, base = 0; 220 u32 usedfp;
221 int error, sig, i, base = 0;
215 sigset_t blocked; 222 sigset_t blocked;
216 223
217 /* Always make any pending restarted system calls return -EINTR */ 224 /* Always make any pending restarted system calls return -EINTR */
@@ -220,8 +227,8 @@ irix_sigreturn(struct pt_regs *regs)
220 if (regs->regs[2] == 1000) 227 if (regs->regs[2] == 1000)
221 base = 1; 228 base = 1;
222 229
223 context = (struct sigctx_irix5 *) regs->regs[base + 4]; 230 context = (struct sigctx_irix5 __user *) regs->regs[base + 4];
224 magic = (struct sigctx_irix5 *) regs->regs[base + 5]; 231 magic = (struct sigctx_irix5 __user *) regs->regs[base + 5];
225 sig = (int) regs->regs[base + 6]; 232 sig = (int) regs->regs[base + 6];
226#ifdef DEBUG_SIG 233#ifdef DEBUG_SIG
227 printk("[%s:%d] IRIX sigreturn(scp[%p],ucp[%p],sig[%d])\n", 234 printk("[%s:%d] IRIX sigreturn(scp[%p],ucp[%p],sig[%d])\n",
@@ -236,25 +243,31 @@ irix_sigreturn(struct pt_regs *regs)
236 dump_irix5_sigctx(context); 243 dump_irix5_sigctx(context);
237#endif 244#endif
238 245
239 __get_user(regs->cp0_epc, &context->pc); 246 error = __get_user(regs->cp0_epc, &context->pc);
240 umask = context->rmask; mask = 2; 247 error |= __get_user(umask, &context->rmask);
248
249 mask = 2;
241 for (i = 1; i < 32; i++, mask <<= 1) { 250 for (i = 1; i < 32; i++, mask <<= 1) {
242 if(umask & mask) 251 if (umask & mask)
243 __get_user(regs->regs[i], &context->regs[i]); 252 error |= __get_user(regs->regs[i], &context->regs[i]);
244 } 253 }
245 __get_user(regs->hi, &context->hi); 254 error |= __get_user(regs->hi, &context->hi);
246 __get_user(regs->lo, &context->lo); 255 error |= __get_user(regs->lo, &context->lo);
247 256
248 if ((umask & 1) && context->usedfp) { 257 error |= __get_user(usedfp, &context->usedfp);
258 if ((umask & 1) && usedfp) {
249 fregs = (u64 *) &current->thread.fpu; 259 fregs = (u64 *) &current->thread.fpu;
260
250 for(i = 0; i < 32; i++) 261 for(i = 0; i < 32; i++)
251 fregs[i] = (u64) context->fpregs[i]; 262 error |= __get_user(fregs[i], &context->fpregs[i]);
252 __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr); 263 error |= __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr);
253 } 264 }
254 265
255 /* XXX do sigstack crapola here... XXX */ 266 /* XXX do sigstack crapola here... XXX */
256 267
257 if (__copy_from_user(&blocked, &context->sigset, sizeof(blocked))) 268 error |= __copy_from_user(&blocked, &context->sigset, sizeof(blocked)) ? -EFAULT : 0;
269
270 if (error)
258 goto badframe; 271 goto badframe;
259 272
260 sigdelsetmask(&blocked, ~_BLOCKABLE); 273 sigdelsetmask(&blocked, ~_BLOCKABLE);
@@ -296,8 +309,8 @@ static inline void dump_sigact_irix5(struct sigact_irix5 *p)
296#endif 309#endif
297 310
298asmlinkage int 311asmlinkage int
299irix_sigaction(int sig, const struct sigaction *act, 312irix_sigaction(int sig, const struct sigaction __user *act,
300 struct sigaction *oact, void *trampoline) 313 struct sigaction __user *oact, void __user *trampoline)
301{ 314{
302 struct k_sigaction new_ka, old_ka; 315 struct k_sigaction new_ka, old_ka;
303 int ret; 316 int ret;
@@ -311,12 +324,16 @@ irix_sigaction(int sig, const struct sigaction *act,
311#endif 324#endif
312 if (act) { 325 if (act) {
313 sigset_t mask; 326 sigset_t mask;
314 if (!access_ok(VERIFY_READ, act, sizeof(*act)) || 327 int err;
315 __get_user(new_ka.sa.sa_handler, &act->sa_handler) || 328
316 __get_user(new_ka.sa.sa_flags, &act->sa_flags)) 329 if (!access_ok(VERIFY_READ, act, sizeof(*act)))
317 return -EFAULT; 330 return -EFAULT;
331 err = __get_user(new_ka.sa.sa_handler, &act->sa_handler);
332 err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags);
318 333
319 __copy_from_user(&mask, &act->sa_mask, sizeof(sigset_t)); 334 err |= __copy_from_user(&mask, &act->sa_mask, sizeof(sigset_t)) ? -EFAULT : 0;
335 if (err)
336 return err;
320 337
321 /* 338 /*
322 * Hmmm... methinks IRIX libc always passes a valid trampoline 339 * Hmmm... methinks IRIX libc always passes a valid trampoline
@@ -330,30 +347,37 @@ irix_sigaction(int sig, const struct sigaction *act,
330 ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); 347 ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
331 348
332 if (!ret && oact) { 349 if (!ret && oact) {
333 if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || 350 int err;
334 __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || 351
335 __put_user(old_ka.sa.sa_flags, &oact->sa_flags)) 352 if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)))
353 return -EFAULT;
354
355 err = __put_user(old_ka.sa.sa_handler, &oact->sa_handler);
356 err |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
357 err |= __copy_to_user(&oact->sa_mask, &old_ka.sa.sa_mask,
358 sizeof(sigset_t)) ? -EFAULT : 0;
359 if (err)
336 return -EFAULT; 360 return -EFAULT;
337 __copy_to_user(&old_ka.sa.sa_mask, &oact->sa_mask,
338 sizeof(sigset_t));
339 } 361 }
340 362
341 return ret; 363 return ret;
342} 364}
343 365
344asmlinkage int irix_sigpending(irix_sigset_t *set) 366asmlinkage int irix_sigpending(irix_sigset_t __user *set)
345{ 367{
346 return do_sigpending(set, sizeof(*set)); 368 return do_sigpending(set, sizeof(*set));
347} 369}
348 370
349asmlinkage int irix_sigprocmask(int how, irix_sigset_t *new, irix_sigset_t *old) 371asmlinkage int irix_sigprocmask(int how, irix_sigset_t __user *new,
372 irix_sigset_t __user *old)
350{ 373{
351 sigset_t oldbits, newbits; 374 sigset_t oldbits, newbits;
352 375
353 if (new) { 376 if (new) {
354 if (!access_ok(VERIFY_READ, new, sizeof(*new))) 377 if (!access_ok(VERIFY_READ, new, sizeof(*new)))
355 return -EFAULT; 378 return -EFAULT;
356 __copy_from_user(&newbits, new, sizeof(unsigned long)*4); 379 if (__copy_from_user(&newbits, new, sizeof(unsigned long)*4))
380 return -EFAULT;
357 sigdelsetmask(&newbits, ~_BLOCKABLE); 381 sigdelsetmask(&newbits, ~_BLOCKABLE);
358 382
359 spin_lock_irq(&current->sighand->siglock); 383 spin_lock_irq(&current->sighand->siglock);
@@ -381,20 +405,19 @@ asmlinkage int irix_sigprocmask(int how, irix_sigset_t *new, irix_sigset_t *old)
381 recalc_sigpending(); 405 recalc_sigpending();
382 spin_unlock_irq(&current->sighand->siglock); 406 spin_unlock_irq(&current->sighand->siglock);
383 } 407 }
384 if(old) { 408 if (old)
385 if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) 409 return copy_to_user(old, &current->blocked,
386 return -EFAULT; 410 sizeof(unsigned long)*4) ? -EFAULT : 0;
387 __copy_to_user(old, &current->blocked, sizeof(unsigned long)*4);
388 }
389 411
390 return 0; 412 return 0;
391} 413}
392 414
393asmlinkage int irix_sigsuspend(struct pt_regs *regs) 415asmlinkage int irix_sigsuspend(struct pt_regs *regs)
394{ 416{
395 sigset_t *uset, saveset, newset; 417 sigset_t saveset, newset;
418 sigset_t __user *uset;
396 419
397 uset = (sigset_t *) regs->regs[4]; 420 uset = (sigset_t __user *) regs->regs[4];
398 if (copy_from_user(&newset, uset, sizeof(sigset_t))) 421 if (copy_from_user(&newset, uset, sizeof(sigset_t)))
399 return -EFAULT; 422 return -EFAULT;
400 sigdelsetmask(&newset, ~_BLOCKABLE); 423 sigdelsetmask(&newset, ~_BLOCKABLE);
@@ -440,12 +463,13 @@ struct irix5_siginfo {
440 } stuff; 463 } stuff;
441}; 464};
442 465
443asmlinkage int irix_sigpoll_sys(unsigned long *set, struct irix5_siginfo *info, 466asmlinkage int irix_sigpoll_sys(unsigned long __user *set,
444 struct timespec *tp) 467 struct irix5_siginfo __user *info, struct timespec __user *tp)
445{ 468{
446 long expire = MAX_SCHEDULE_TIMEOUT; 469 long expire = MAX_SCHEDULE_TIMEOUT;
447 sigset_t kset; 470 sigset_t kset;
448 int i, sig, error, timeo = 0; 471 int i, sig, error, timeo = 0;
472 struct timespec ktp;
449 473
450#ifdef DEBUG_SIG 474#ifdef DEBUG_SIG
451 printk("[%s:%d] irix_sigpoll_sys(%p,%p,%p)\n", 475 printk("[%s:%d] irix_sigpoll_sys(%p,%p,%p)\n",
@@ -456,14 +480,8 @@ asmlinkage int irix_sigpoll_sys(unsigned long *set, struct irix5_siginfo *info,
456 if (!set) 480 if (!set)
457 return -EINVAL; 481 return -EINVAL;
458 482
459 if (!access_ok(VERIFY_READ, set, sizeof(kset))) { 483 if (copy_from_user(&kset, set, sizeof(set)))
460 error = -EFAULT; 484 return -EFAULT;
461 goto out;
462 }
463
464 __copy_from_user(&kset, set, sizeof(set));
465 if (error)
466 goto out;
467 485
468 if (info && clear_user(info, sizeof(*info))) { 486 if (info && clear_user(info, sizeof(*info))) {
469 error = -EFAULT; 487 error = -EFAULT;
@@ -471,19 +489,21 @@ asmlinkage int irix_sigpoll_sys(unsigned long *set, struct irix5_siginfo *info,
471 } 489 }
472 490
473 if (tp) { 491 if (tp) {
474 if (!access_ok(VERIFY_READ, tp, sizeof(*tp))) 492 if (copy_from_user(&ktp, tp, sizeof(*tp)))
475 return -EFAULT; 493 return -EFAULT;
476 if (!tp->tv_sec && !tp->tv_nsec) { 494
477 error = -EINVAL; 495 if (!ktp.tv_sec && !ktp.tv_nsec)
478 goto out; 496 return -EINVAL;
479 } 497
480 expire = timespec_to_jiffies(tp) + (tp->tv_sec||tp->tv_nsec); 498 expire = timespec_to_jiffies(&ktp) +
499 (ktp.tv_sec || ktp.tv_nsec);
481 } 500 }
482 501
483 while(1) { 502 while(1) {
484 long tmp = 0; 503 long tmp = 0;
485 504
486 expire = schedule_timeout_interruptible(expire); 505 current->state = TASK_INTERRUPTIBLE;
506 expire = schedule_timeout(expire);
487 507
488 for (i=0; i<=4; i++) 508 for (i=0; i<=4; i++)
489 tmp |= (current->pending.signal.sig[i] & kset.sig[i]); 509 tmp |= (current->pending.signal.sig[i] & kset.sig[i]);
@@ -500,15 +520,14 @@ asmlinkage int irix_sigpoll_sys(unsigned long *set, struct irix5_siginfo *info,
500 if (timeo) 520 if (timeo)
501 return -EAGAIN; 521 return -EAGAIN;
502 522
503 for(sig = 1; i <= 65 /* IRIX_NSIG */; sig++) { 523 for (sig = 1; i <= 65 /* IRIX_NSIG */; sig++) {
504 if (sigismember (&kset, sig)) 524 if (sigismember (&kset, sig))
505 continue; 525 continue;
506 if (sigismember (&current->pending.signal, sig)) { 526 if (sigismember (&current->pending.signal, sig)) {
507 /* XXX need more than this... */ 527 /* XXX need more than this... */
508 if (info) 528 if (info)
509 info->sig = sig; 529 return copy_to_user(&info->sig, &sig, sizeof(sig));
510 error = 0; 530 return 0;
511 goto out;
512 } 531 }
513 } 532 }
514 533
@@ -534,8 +553,9 @@ extern int getrusage(struct task_struct *, int, struct rusage __user *);
534 553
535#define W_MASK (W_EXITED | W_TRAPPED | W_STOPPED | W_CONT | W_NOHANG) 554#define W_MASK (W_EXITED | W_TRAPPED | W_STOPPED | W_CONT | W_NOHANG)
536 555
537asmlinkage int irix_waitsys(int type, int pid, struct irix5_siginfo *info, 556asmlinkage int irix_waitsys(int type, int pid,
538 int options, struct rusage *ru) 557 struct irix5_siginfo __user *info, int options,
558 struct rusage __user *ru)
539{ 559{
540 int flag, retval; 560 int flag, retval;
541 DECLARE_WAITQUEUE(wait, current); 561 DECLARE_WAITQUEUE(wait, current);
@@ -543,28 +563,22 @@ asmlinkage int irix_waitsys(int type, int pid, struct irix5_siginfo *info,
543 struct task_struct *p; 563 struct task_struct *p;
544 struct list_head *_p; 564 struct list_head *_p;
545 565
546 if (!info) { 566 if (!info)
547 retval = -EINVAL; 567 return -EINVAL;
548 goto out; 568
549 } 569 if (!access_ok(VERIFY_WRITE, info, sizeof(*info)))
550 if (!access_ok(VERIFY_WRITE, info, sizeof(*info))) { 570 return -EFAULT;
551 retval = -EFAULT; 571
552 goto out; 572 if (ru)
553 } 573 if (!access_ok(VERIFY_WRITE, ru, sizeof(*ru)))
554 if (ru) { 574 return -EFAULT;
555 if (!access_ok(VERIFY_WRITE, ru, sizeof(*ru))) { 575
556 retval = -EFAULT; 576 if (options & ~W_MASK)
557 goto out; 577 return -EINVAL;
558 } 578
559 } 579 if (type != IRIX_P_PID && type != IRIX_P_PGID && type != IRIX_P_ALL)
560 if (options & ~(W_MASK)) { 580 return -EINVAL;
561 retval = -EINVAL; 581
562 goto out;
563 }
564 if (type != IRIX_P_PID && type != IRIX_P_PGID && type != IRIX_P_ALL) {
565 retval = -EINVAL;
566 goto out;
567 }
568 add_wait_queue(&current->signal->wait_chldexit, &wait); 582 add_wait_queue(&current->signal->wait_chldexit, &wait);
569repeat: 583repeat:
570 flag = 0; 584 flag = 0;
@@ -595,18 +609,20 @@ repeat:
595 add_parent(p, p->parent); 609 add_parent(p, p->parent);
596 write_unlock_irq(&tasklist_lock); 610 write_unlock_irq(&tasklist_lock);
597 retval = ru ? getrusage(p, RUSAGE_BOTH, ru) : 0; 611 retval = ru ? getrusage(p, RUSAGE_BOTH, ru) : 0;
598 if (!retval && ru) { 612 if (retval)
599 retval |= __put_user(SIGCHLD, &info->sig); 613 goto end_waitsys;
600 retval |= __put_user(0, &info->code); 614
601 retval |= __put_user(p->pid, &info->stuff.procinfo.pid); 615 retval = __put_user(SIGCHLD, &info->sig);
602 retval |= __put_user((p->exit_code >> 8) & 0xff, 616 retval |= __put_user(0, &info->code);
603 &info->stuff.procinfo.procdata.child.status); 617 retval |= __put_user(p->pid, &info->stuff.procinfo.pid);
604 retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime); 618 retval |= __put_user((p->exit_code >> 8) & 0xff,
605 retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime); 619 &info->stuff.procinfo.procdata.child.status);
606 } 620 retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime);
607 if (!retval) { 621 retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime);
608 p->exit_code = 0; 622 if (retval)
609 } 623 goto end_waitsys;
624
625 p->exit_code = 0;
610 goto end_waitsys; 626 goto end_waitsys;
611 627
612 case EXIT_ZOMBIE: 628 case EXIT_ZOMBIE:
@@ -614,16 +630,18 @@ repeat:
614 current->signal->cstime += p->stime + p->signal->cstime; 630 current->signal->cstime += p->stime + p->signal->cstime;
615 if (ru != NULL) 631 if (ru != NULL)
616 getrusage(p, RUSAGE_BOTH, ru); 632 getrusage(p, RUSAGE_BOTH, ru);
617 __put_user(SIGCHLD, &info->sig); 633 retval = __put_user(SIGCHLD, &info->sig);
618 __put_user(1, &info->code); /* CLD_EXITED */ 634 retval |= __put_user(1, &info->code); /* CLD_EXITED */
619 __put_user(p->pid, &info->stuff.procinfo.pid); 635 retval |= __put_user(p->pid, &info->stuff.procinfo.pid);
620 __put_user((p->exit_code >> 8) & 0xff, 636 retval |= __put_user((p->exit_code >> 8) & 0xff,
621 &info->stuff.procinfo.procdata.child.status); 637 &info->stuff.procinfo.procdata.child.status);
622 __put_user(p->utime, 638 retval |= __put_user(p->utime,
623 &info->stuff.procinfo.procdata.child.utime); 639 &info->stuff.procinfo.procdata.child.utime);
624 __put_user(p->stime, 640 retval |= __put_user(p->stime,
625 &info->stuff.procinfo.procdata.child.stime); 641 &info->stuff.procinfo.procdata.child.stime);
626 retval = 0; 642 if (retval)
643 return retval;
644
627 if (p->real_parent != p->parent) { 645 if (p->real_parent != p->parent) {
628 write_lock_irq(&tasklist_lock); 646 write_lock_irq(&tasklist_lock);
629 remove_parent(p); 647 remove_parent(p);
@@ -656,7 +674,6 @@ end_waitsys:
656 current->state = TASK_RUNNING; 674 current->state = TASK_RUNNING;
657 remove_wait_queue(&current->signal->wait_chldexit, &wait); 675 remove_wait_queue(&current->signal->wait_chldexit, &wait);
658 676
659out:
660 return retval; 677 return retval;
661} 678}
662 679
@@ -675,39 +692,39 @@ struct irix5_context {
675 692
676asmlinkage int irix_getcontext(struct pt_regs *regs) 693asmlinkage int irix_getcontext(struct pt_regs *regs)
677{ 694{
678 int i, base = 0; 695 int error, i, base = 0;
679 struct irix5_context *ctx; 696 struct irix5_context __user *ctx;
680 unsigned long flags; 697 unsigned long flags;
681 698
682 if (regs->regs[2] == 1000) 699 if (regs->regs[2] == 1000)
683 base = 1; 700 base = 1;
684 ctx = (struct irix5_context *) regs->regs[base + 4]; 701 ctx = (struct irix5_context __user *) regs->regs[base + 4];
685 702
686#ifdef DEBUG_SIG 703#ifdef DEBUG_SIG
687 printk("[%s:%d] irix_getcontext(%p)\n", 704 printk("[%s:%d] irix_getcontext(%p)\n",
688 current->comm, current->pid, ctx); 705 current->comm, current->pid, ctx);
689#endif 706#endif
690 707
691 if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))) 708 if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx)));
692 return -EFAULT; 709 return -EFAULT;
693 710
694 __put_user(current->thread.irix_oldctx, &ctx->link); 711 error = __put_user(current->thread.irix_oldctx, &ctx->link);
695 712
696 __copy_to_user(&ctx->sigmask, &current->blocked, sizeof(irix_sigset_t)); 713 error |= __copy_to_user(&ctx->sigmask, &current->blocked, sizeof(irix_sigset_t)) ? -EFAULT : 0;
697 714
698 /* XXX Do sigstack stuff someday... */ 715 /* XXX Do sigstack stuff someday... */
699 __put_user(0, &ctx->stack.sp); 716 error |= __put_user(0, &ctx->stack.sp);
700 __put_user(0, &ctx->stack.size); 717 error |= __put_user(0, &ctx->stack.size);
701 __put_user(0, &ctx->stack.flags); 718 error |= __put_user(0, &ctx->stack.flags);
702 719
703 __put_user(0, &ctx->weird_graphics_thing); 720 error |= __put_user(0, &ctx->weird_graphics_thing);
704 __put_user(0, &ctx->regs[0]); 721 error |= __put_user(0, &ctx->regs[0]);
705 for (i = 1; i < 32; i++) 722 for (i = 1; i < 32; i++)
706 __put_user(regs->regs[i], &ctx->regs[i]); 723 error |= __put_user(regs->regs[i], &ctx->regs[i]);
707 __put_user(regs->lo, &ctx->regs[32]); 724 error |= __put_user(regs->lo, &ctx->regs[32]);
708 __put_user(regs->hi, &ctx->regs[33]); 725 error |= __put_user(regs->hi, &ctx->regs[33]);
709 __put_user(regs->cp0_cause, &ctx->regs[34]); 726 error |= __put_user(regs->cp0_cause, &ctx->regs[34]);
710 __put_user(regs->cp0_epc, &ctx->regs[35]); 727 error |= __put_user(regs->cp0_epc, &ctx->regs[35]);
711 728
712 flags = 0x0f; 729 flags = 0x0f;
713 if (!used_math()) { 730 if (!used_math()) {
@@ -716,119 +733,124 @@ asmlinkage int irix_getcontext(struct pt_regs *regs)
716 /* XXX wheee... */ 733 /* XXX wheee... */
717 printk("Wheee, no code for saving IRIX FPU context yet.\n"); 734 printk("Wheee, no code for saving IRIX FPU context yet.\n");
718 } 735 }
719 __put_user(flags, &ctx->flags); 736 error |= __put_user(flags, &ctx->flags);
720 737
721 return 0; 738 return error;
722} 739}
723 740
724asmlinkage unsigned long irix_setcontext(struct pt_regs *regs) 741asmlinkage void irix_setcontext(struct pt_regs *regs)
725{ 742{
726 int error, base = 0; 743 struct irix5_context __user *ctx;
727 struct irix5_context *ctx; 744 int err, base = 0;
745 u32 flags;
728 746
729 if(regs->regs[2] == 1000) 747 if (regs->regs[2] == 1000)
730 base = 1; 748 base = 1;
731 ctx = (struct irix5_context *) regs->regs[base + 4]; 749 ctx = (struct irix5_context __user *) regs->regs[base + 4];
732 750
733#ifdef DEBUG_SIG 751#ifdef DEBUG_SIG
734 printk("[%s:%d] irix_setcontext(%p)\n", 752 printk("[%s:%d] irix_setcontext(%p)\n",
735 current->comm, current->pid, ctx); 753 current->comm, current->pid, ctx);
736#endif 754#endif
737 755
738 if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))) { 756 if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx)))
739 error = -EFAULT; 757 goto segv_and_exit;
740 goto out;
741 }
742 758
743 if (ctx->flags & 0x02) { 759 err = __get_user(flags, &ctx->flags);
760 if (flags & 0x02) {
744 /* XXX sigstack garbage, todo... */ 761 /* XXX sigstack garbage, todo... */
745 printk("Wheee, cannot do sigstack stuff in setcontext\n"); 762 printk("Wheee, cannot do sigstack stuff in setcontext\n");
746 } 763 }
747 764
748 if (ctx->flags & 0x04) { 765 if (flags & 0x04) {
749 int i; 766 int i;
750 767
751 /* XXX extra control block stuff... todo... */ 768 /* XXX extra control block stuff... todo... */
752 for(i = 1; i < 32; i++) 769 for (i = 1; i < 32; i++)
753 regs->regs[i] = ctx->regs[i]; 770 err |= __get_user(regs->regs[i], &ctx->regs[i]);
754 regs->lo = ctx->regs[32]; 771 err |= __get_user(regs->lo, &ctx->regs[32]);
755 regs->hi = ctx->regs[33]; 772 err |= __get_user(regs->hi, &ctx->regs[33]);
756 regs->cp0_epc = ctx->regs[35]; 773 err |= __get_user(regs->cp0_epc, &ctx->regs[35]);
757 } 774 }
758 775
759 if (ctx->flags & 0x08) { 776 if (flags & 0x08)
760 /* XXX fpu context, blah... */ 777 /* XXX fpu context, blah... */
761 printk("Wheee, cannot restore FPU context yet...\n"); 778 printk(KERN_ERR "Wheee, cannot restore FPU context yet...\n");
762 }
763 current->thread.irix_oldctx = ctx->link;
764 error = regs->regs[2];
765 779
766out: 780 err |= __get_user(current->thread.irix_oldctx, &ctx->link);
767 return error; 781 if (err)
782 goto segv_and_exit;
783
784 /*
785 * Don't let your children do this ...
786 */
787 if (current_thread_info()->flags & TIF_SYSCALL_TRACE)
788 do_syscall_trace(regs, 1);
789 __asm__ __volatile__(
790 "move\t$29,%0\n\t"
791 "j\tsyscall_exit"
792 :/* no outputs */
793 :"r" (&regs));
794 /* Unreached */
795
796segv_and_exit:
797 force_sigsegv(SIGSEGV, current);
768} 798}
769 799
770struct irix_sigstack { unsigned long sp; int status; }; 800struct irix_sigstack {
801 unsigned long sp;
802 int status;
803};
771 804
772asmlinkage int irix_sigstack(struct irix_sigstack *new, struct irix_sigstack *old) 805asmlinkage int irix_sigstack(struct irix_sigstack __user *new,
806 struct irix_sigstack __user *old)
773{ 807{
774 int error = -EFAULT;
775
776#ifdef DEBUG_SIG 808#ifdef DEBUG_SIG
777 printk("[%s:%d] irix_sigstack(%p,%p)\n", 809 printk("[%s:%d] irix_sigstack(%p,%p)\n",
778 current->comm, current->pid, new, old); 810 current->comm, current->pid, new, old);
779#endif 811#endif
780 if(new) { 812 if (new) {
781 if (!access_ok(VERIFY_READ, new, sizeof(*new))) 813 if (!access_ok(VERIFY_READ, new, sizeof(*new)))
782 goto out; 814 return -EFAULT;
783 } 815 }
784 816
785 if(old) { 817 if (old) {
786 if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) 818 if (!access_ok(VERIFY_WRITE, old, sizeof(*old)))
787 goto out; 819 return -EFAULT;
788 } 820 }
789 error = 0;
790 821
791out: 822 return 0;
792 return error;
793} 823}
794 824
795struct irix_sigaltstack { unsigned long sp; int size; int status; }; 825struct irix_sigaltstack { unsigned long sp; int size; int status; };
796 826
797asmlinkage int irix_sigaltstack(struct irix_sigaltstack *new, 827asmlinkage int irix_sigaltstack(struct irix_sigaltstack __user *new,
798 struct irix_sigaltstack *old) 828 struct irix_sigaltstack __user *old)
799{ 829{
800 int error = -EFAULT;
801
802#ifdef DEBUG_SIG 830#ifdef DEBUG_SIG
803 printk("[%s:%d] irix_sigaltstack(%p,%p)\n", 831 printk("[%s:%d] irix_sigaltstack(%p,%p)\n",
804 current->comm, current->pid, new, old); 832 current->comm, current->pid, new, old);
805#endif 833#endif
806 if (new) { 834 if (new)
807 if (!access_ok(VERIFY_READ, new, sizeof(*new))) 835 if (!access_ok(VERIFY_READ, new, sizeof(*new)))
808 goto out; 836 return -EFAULT;
809 }
810 837
811 if (old) { 838 if (old) {
812 if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) 839 if (!access_ok(VERIFY_WRITE, old, sizeof(*old)))
813 goto out; 840 return -EFAULT;
814 } 841 }
815 error = 0;
816
817out:
818 error = 0;
819 842
820 return error; 843 return 0;
821} 844}
822 845
823struct irix_procset { 846struct irix_procset {
824 int cmd, ltype, lid, rtype, rid; 847 int cmd, ltype, lid, rtype, rid;
825}; 848};
826 849
827asmlinkage int irix_sigsendset(struct irix_procset *pset, int sig) 850asmlinkage int irix_sigsendset(struct irix_procset __user *pset, int sig)
828{ 851{
829 if (!access_ok(VERIFY_READ, pset, sizeof(*pset))) 852 if (!access_ok(VERIFY_READ, pset, sizeof(*pset)))
830 return -EFAULT; 853 return -EFAULT;
831
832#ifdef DEBUG_SIG 854#ifdef DEBUG_SIG
833 printk("[%s:%d] irix_sigsendset([%d,%d,%d,%d,%d],%d)\n", 855 printk("[%s:%d] irix_sigsendset([%d,%d,%d,%d,%d],%d)\n",
834 current->comm, current->pid, 856 current->comm, current->pid,
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 43c00ac0b88d..3f653c7cfbf3 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -74,7 +74,7 @@ static void disable_msc_irq(unsigned int irq)
74static void level_mask_and_ack_msc_irq(unsigned int irq) 74static void level_mask_and_ack_msc_irq(unsigned int irq)
75{ 75{
76 mask_msc_irq(irq); 76 mask_msc_irq(irq);
77 if (!cpu_has_ei) 77 if (!cpu_has_veic)
78 MSCIC_WRITE(MSC01_IC_EOI, 0); 78 MSCIC_WRITE(MSC01_IC_EOI, 0);
79} 79}
80 80
@@ -84,7 +84,7 @@ static void level_mask_and_ack_msc_irq(unsigned int irq)
84static void edge_mask_and_ack_msc_irq(unsigned int irq) 84static void edge_mask_and_ack_msc_irq(unsigned int irq)
85{ 85{
86 mask_msc_irq(irq); 86 mask_msc_irq(irq);
87 if (!cpu_has_ei) 87 if (!cpu_has_veic)
88 MSCIC_WRITE(MSC01_IC_EOI, 0); 88 MSCIC_WRITE(MSC01_IC_EOI, 0);
89 else { 89 else {
90 u32 r; 90 u32 r;
@@ -129,25 +129,23 @@ msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
129#define shutdown_msc_irq disable_msc_irq 129#define shutdown_msc_irq disable_msc_irq
130 130
131struct hw_interrupt_type msc_levelirq_type = { 131struct hw_interrupt_type msc_levelirq_type = {
132 "SOC-it-Level", 132 .typename = "SOC-it-Level",
133 startup_msc_irq, 133 .startup = startup_msc_irq,
134 shutdown_msc_irq, 134 .shutdown = shutdown_msc_irq,
135 enable_msc_irq, 135 .enable = enable_msc_irq,
136 disable_msc_irq, 136 .disable = disable_msc_irq,
137 level_mask_and_ack_msc_irq, 137 .ack = level_mask_and_ack_msc_irq,
138 end_msc_irq, 138 .end = end_msc_irq,
139 NULL
140}; 139};
141 140
142struct hw_interrupt_type msc_edgeirq_type = { 141struct hw_interrupt_type msc_edgeirq_type = {
143 "SOC-it-Edge", 142 .typename = "SOC-it-Edge",
144 startup_msc_irq, 143 .startup =startup_msc_irq,
145 shutdown_msc_irq, 144 .shutdown = shutdown_msc_irq,
146 enable_msc_irq, 145 .enable = enable_msc_irq,
147 disable_msc_irq, 146 .disable = disable_msc_irq,
148 edge_mask_and_ack_msc_irq, 147 .ack = edge_mask_and_ack_msc_irq,
149 end_msc_irq, 148 .end = end_msc_irq,
150 NULL
151}; 149};
152 150
153 151
@@ -168,14 +166,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
168 switch (imp->im_type) { 166 switch (imp->im_type) {
169 case MSC01_IRQ_EDGE: 167 case MSC01_IRQ_EDGE:
170 irq_desc[base+n].handler = &msc_edgeirq_type; 168 irq_desc[base+n].handler = &msc_edgeirq_type;
171 if (cpu_has_ei) 169 if (cpu_has_veic)
172 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 170 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
173 else 171 else
174 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 172 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
175 break; 173 break;
176 case MSC01_IRQ_LEVEL: 174 case MSC01_IRQ_LEVEL:
177 irq_desc[base+n].handler = &msc_levelirq_type; 175 irq_desc[base+n].handler = &msc_levelirq_type;
178 if (cpu_has_ei) 176 if (cpu_has_veic)
179 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 177 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
180 else 178 else
181 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl); 179 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index 088bbbc869e6..0ac067f45cf5 100644
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -135,14 +135,13 @@ void ll_mv64340_irq(struct pt_regs *regs)
135#define shutdown_mv64340_irq disable_mv64340_irq 135#define shutdown_mv64340_irq disable_mv64340_irq
136 136
137struct hw_interrupt_type mv64340_irq_type = { 137struct hw_interrupt_type mv64340_irq_type = {
138 "MV-64340", 138 .typename = "MV-64340",
139 startup_mv64340_irq, 139 .startup = startup_mv64340_irq,
140 shutdown_mv64340_irq, 140 .shutdown = shutdown_mv64340_irq,
141 enable_mv64340_irq, 141 .enable = enable_mv64340_irq,
142 disable_mv64340_irq, 142 .disable = disable_mv64340_irq,
143 mask_and_ack_mv64340_irq, 143 .ack = mask_and_ack_mv64340_irq,
144 end_mv64340_irq, 144 .end = end_mv64340_irq,
145 NULL
146}; 145};
147 146
148void __init mv64340_irq_init(unsigned int base) 147void __init mv64340_irq_init(unsigned int base)
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index f5d779fd0355..0b130c5ac5d9 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -72,13 +72,13 @@ static void rm7k_cpu_irq_end(unsigned int irq)
72} 72}
73 73
74static hw_irq_controller rm7k_irq_controller = { 74static hw_irq_controller rm7k_irq_controller = {
75 "RM7000", 75 .typename = "RM7000",
76 rm7k_cpu_irq_startup, 76 .startup = rm7k_cpu_irq_startup,
77 rm7k_cpu_irq_shutdown, 77 .shutdown = rm7k_cpu_irq_shutdown,
78 rm7k_cpu_irq_enable, 78 .enable = rm7k_cpu_irq_enable,
79 rm7k_cpu_irq_disable, 79 .disable = rm7k_cpu_irq_disable,
80 rm7k_cpu_irq_ack, 80 .ack = rm7k_cpu_irq_ack,
81 rm7k_cpu_irq_end, 81 .end = rm7k_cpu_irq_end,
82}; 82};
83 83
84void __init rm7k_cpu_irq_init(int base) 84void __init rm7k_cpu_irq_init(int base)
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index bdd130296256..9b5f20c32acb 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -106,23 +106,23 @@ static void rm9k_cpu_irq_end(unsigned int irq)
106} 106}
107 107
108static hw_irq_controller rm9k_irq_controller = { 108static hw_irq_controller rm9k_irq_controller = {
109 "RM9000", 109 .typename = "RM9000",
110 rm9k_cpu_irq_startup, 110 .startup = rm9k_cpu_irq_startup,
111 rm9k_cpu_irq_shutdown, 111 .shutdown = rm9k_cpu_irq_shutdown,
112 rm9k_cpu_irq_enable, 112 .enable = rm9k_cpu_irq_enable,
113 rm9k_cpu_irq_disable, 113 .disable = rm9k_cpu_irq_disable,
114 rm9k_cpu_irq_ack, 114 .ack = rm9k_cpu_irq_ack,
115 rm9k_cpu_irq_end, 115 .end = rm9k_cpu_irq_end,
116}; 116};
117 117
118static hw_irq_controller rm9k_perfcounter_irq = { 118static hw_irq_controller rm9k_perfcounter_irq = {
119 "RM9000", 119 .typename = "RM9000",
120 rm9k_perfcounter_irq_startup, 120 .startup = rm9k_perfcounter_irq_startup,
121 rm9k_perfcounter_irq_shutdown, 121 .shutdown = rm9k_perfcounter_irq_shutdown,
122 rm9k_cpu_irq_enable, 122 .enable = rm9k_cpu_irq_enable,
123 rm9k_cpu_irq_disable, 123 .disable = rm9k_cpu_irq_disable,
124 rm9k_cpu_irq_ack, 124 .ack = rm9k_cpu_irq_ack,
125 rm9k_cpu_irq_end, 125 .end = rm9k_cpu_irq_end,
126}; 126};
127 127
128unsigned int rm9000_perfcount_irq; 128unsigned int rm9000_perfcount_irq;
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 2b936cf1ef70..5db67e31ec1a 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -3,6 +3,8 @@
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * 4 *
5 * Copyright (C) 2001 Ralf Baechle 5 * Copyright (C) 2001 Ralf Baechle
6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Author: Maciej W. Rozycki <macro@mips.com>
6 * 8 *
7 * This file define the irq handler for MIPS CPU interrupts. 9 * This file define the irq handler for MIPS CPU interrupts.
8 * 10 *
@@ -31,19 +33,21 @@
31 33
32#include <asm/irq_cpu.h> 34#include <asm/irq_cpu.h>
33#include <asm/mipsregs.h> 35#include <asm/mipsregs.h>
36#include <asm/mipsmtregs.h>
34#include <asm/system.h> 37#include <asm/system.h>
35 38
36static int mips_cpu_irq_base; 39static int mips_cpu_irq_base;
37 40
38static inline void unmask_mips_irq(unsigned int irq) 41static inline void unmask_mips_irq(unsigned int irq)
39{ 42{
40 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
41 set_c0_status(0x100 << (irq - mips_cpu_irq_base)); 43 set_c0_status(0x100 << (irq - mips_cpu_irq_base));
44 irq_enable_hazard();
42} 45}
43 46
44static inline void mask_mips_irq(unsigned int irq) 47static inline void mask_mips_irq(unsigned int irq)
45{ 48{
46 clear_c0_status(0x100 << (irq - mips_cpu_irq_base)); 49 clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
50 irq_disable_hazard();
47} 51}
48 52
49static inline void mips_cpu_irq_enable(unsigned int irq) 53static inline void mips_cpu_irq_enable(unsigned int irq)
@@ -52,6 +56,7 @@ static inline void mips_cpu_irq_enable(unsigned int irq)
52 56
53 local_irq_save(flags); 57 local_irq_save(flags);
54 unmask_mips_irq(irq); 58 unmask_mips_irq(irq);
59 back_to_back_c0_hazard();
55 local_irq_restore(flags); 60 local_irq_restore(flags);
56} 61}
57 62
@@ -61,6 +66,7 @@ static void mips_cpu_irq_disable(unsigned int irq)
61 66
62 local_irq_save(flags); 67 local_irq_save(flags);
63 mask_mips_irq(irq); 68 mask_mips_irq(irq);
69 back_to_back_c0_hazard();
64 local_irq_restore(flags); 70 local_irq_restore(flags);
65} 71}
66 72
@@ -71,7 +77,7 @@ static unsigned int mips_cpu_irq_startup(unsigned int irq)
71 return 0; 77 return 0;
72} 78}
73 79
74#define mips_cpu_irq_shutdown mips_cpu_irq_disable 80#define mips_cpu_irq_shutdown mips_cpu_irq_disable
75 81
76/* 82/*
77 * While we ack the interrupt interrupts are disabled and thus we don't need 83 * While we ack the interrupt interrupts are disabled and thus we don't need
@@ -79,9 +85,6 @@ static unsigned int mips_cpu_irq_startup(unsigned int irq)
79 */ 85 */
80static void mips_cpu_irq_ack(unsigned int irq) 86static void mips_cpu_irq_ack(unsigned int irq)
81{ 87{
82 /* Only necessary for soft interrupts */
83 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
84
85 mask_mips_irq(irq); 88 mask_mips_irq(irq);
86} 89}
87 90
@@ -92,22 +95,82 @@ static void mips_cpu_irq_end(unsigned int irq)
92} 95}
93 96
94static hw_irq_controller mips_cpu_irq_controller = { 97static hw_irq_controller mips_cpu_irq_controller = {
95 "MIPS", 98 .typename = "MIPS",
96 mips_cpu_irq_startup, 99 .startup = mips_cpu_irq_startup,
97 mips_cpu_irq_shutdown, 100 .shutdown = mips_cpu_irq_shutdown,
98 mips_cpu_irq_enable, 101 .enable = mips_cpu_irq_enable,
99 mips_cpu_irq_disable, 102 .disable = mips_cpu_irq_disable,
100 mips_cpu_irq_ack, 103 .ack = mips_cpu_irq_ack,
101 mips_cpu_irq_end, 104 .end = mips_cpu_irq_end,
102 NULL /* no affinity stuff for UP */
103}; 105};
104 106
107/*
108 * Basically the same as above but taking care of all the MT stuff
109 */
110
111#define unmask_mips_mt_irq unmask_mips_irq
112#define mask_mips_mt_irq mask_mips_irq
113#define mips_mt_cpu_irq_enable mips_cpu_irq_enable
114#define mips_mt_cpu_irq_disable mips_cpu_irq_disable
115
116static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
117{
118 unsigned int vpflags = dvpe();
119
120 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
121 evpe(vpflags);
122 mips_mt_cpu_irq_enable(irq);
123
124 return 0;
125}
126
127#define mips_mt_cpu_irq_shutdown mips_mt_cpu_irq_disable
128
129/*
130 * While we ack the interrupt interrupts are disabled and thus we don't need
131 * to deal with concurrency issues. Same for mips_cpu_irq_end.
132 */
133static void mips_mt_cpu_irq_ack(unsigned int irq)
134{
135 unsigned int vpflags = dvpe();
136 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
137 evpe(vpflags);
138 mask_mips_mt_irq(irq);
139}
140
141#define mips_mt_cpu_irq_end mips_cpu_irq_end
142
143static hw_irq_controller mips_mt_cpu_irq_controller = {
144 .typename = "MIPS",
145 .startup = mips_mt_cpu_irq_startup,
146 .shutdown = mips_mt_cpu_irq_shutdown,
147 .enable = mips_mt_cpu_irq_enable,
148 .disable = mips_mt_cpu_irq_disable,
149 .ack = mips_mt_cpu_irq_ack,
150 .end = mips_mt_cpu_irq_end,
151};
105 152
106void __init mips_cpu_irq_init(int irq_base) 153void __init mips_cpu_irq_init(int irq_base)
107{ 154{
108 int i; 155 int i;
109 156
110 for (i = irq_base; i < irq_base + 8; i++) { 157 /* Mask interrupts. */
158 clear_c0_status(ST0_IM);
159 clear_c0_cause(CAUSEF_IP);
160
161 /*
162 * Only MT is using the software interrupts currently, so we just
163 * leave them uninitialized for other processors.
164 */
165 if (cpu_has_mipsmt)
166 for (i = irq_base; i < irq_base + 2; i++) {
167 irq_desc[i].status = IRQ_DISABLED;
168 irq_desc[i].action = NULL;
169 irq_desc[i].depth = 1;
170 irq_desc[i].handler = &mips_mt_cpu_irq_controller;
171 }
172
173 for (i = irq_base + 2; i < irq_base + 8; i++) {
111 irq_desc[i].status = IRQ_DISABLED; 174 irq_desc[i].status = IRQ_DISABLED;
112 irq_desc[i].action = NULL; 175 irq_desc[i].action = NULL;
113 irq_desc[i].depth = 1; 176 irq_desc[i].depth = 1;
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index ece4564919d8..330cf84d21fe 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -215,81 +215,32 @@ sys32_readdir(unsigned int fd, void * dirent32, unsigned int count)
215 return(n); 215 return(n);
216} 216}
217 217
218struct rusage32 { 218asmlinkage int
219 struct compat_timeval ru_utime; 219sys32_waitpid(compat_pid_t pid, unsigned int *stat_addr, int options)
220 struct compat_timeval ru_stime;
221 int ru_maxrss;
222 int ru_ixrss;
223 int ru_idrss;
224 int ru_isrss;
225 int ru_minflt;
226 int ru_majflt;
227 int ru_nswap;
228 int ru_inblock;
229 int ru_oublock;
230 int ru_msgsnd;
231 int ru_msgrcv;
232 int ru_nsignals;
233 int ru_nvcsw;
234 int ru_nivcsw;
235};
236
237static int
238put_rusage (struct rusage32 *ru, struct rusage *r)
239{ 220{
240 int err; 221 return compat_sys_wait4(pid, stat_addr, options, NULL);
241
242 if (!access_ok(VERIFY_WRITE, ru, sizeof *ru))
243 return -EFAULT;
244
245 err = __put_user (r->ru_utime.tv_sec, &ru->ru_utime.tv_sec);
246 err |= __put_user (r->ru_utime.tv_usec, &ru->ru_utime.tv_usec);
247 err |= __put_user (r->ru_stime.tv_sec, &ru->ru_stime.tv_sec);
248 err |= __put_user (r->ru_stime.tv_usec, &ru->ru_stime.tv_usec);
249 err |= __put_user (r->ru_maxrss, &ru->ru_maxrss);
250 err |= __put_user (r->ru_ixrss, &ru->ru_ixrss);
251 err |= __put_user (r->ru_idrss, &ru->ru_idrss);
252 err |= __put_user (r->ru_isrss, &ru->ru_isrss);
253 err |= __put_user (r->ru_minflt, &ru->ru_minflt);
254 err |= __put_user (r->ru_majflt, &ru->ru_majflt);
255 err |= __put_user (r->ru_nswap, &ru->ru_nswap);
256 err |= __put_user (r->ru_inblock, &ru->ru_inblock);
257 err |= __put_user (r->ru_oublock, &ru->ru_oublock);
258 err |= __put_user (r->ru_msgsnd, &ru->ru_msgsnd);
259 err |= __put_user (r->ru_msgrcv, &ru->ru_msgrcv);
260 err |= __put_user (r->ru_nsignals, &ru->ru_nsignals);
261 err |= __put_user (r->ru_nvcsw, &ru->ru_nvcsw);
262 err |= __put_user (r->ru_nivcsw, &ru->ru_nivcsw);
263
264 return err;
265} 222}
266 223
267asmlinkage int 224asmlinkage long
268sys32_wait4(compat_pid_t pid, unsigned int * stat_addr, int options, 225sysn32_waitid(int which, compat_pid_t pid,
269 struct rusage32 * ru) 226 siginfo_t __user *uinfo, int options,
227 struct compat_rusage __user *uru)
270{ 228{
271 if (!ru) 229 struct rusage ru;
272 return sys_wait4(pid, stat_addr, options, NULL); 230 long ret;
273 else { 231 mm_segment_t old_fs = get_fs();
274 struct rusage r;
275 int ret;
276 unsigned int status;
277 mm_segment_t old_fs = get_fs();
278 232
279 set_fs(KERNEL_DS); 233 set_fs (KERNEL_DS);
280 ret = sys_wait4(pid, stat_addr ? &status : NULL, options, &r); 234 ret = sys_waitid(which, pid, uinfo, options,
281 set_fs(old_fs); 235 uru ? (struct rusage __user *) &ru : NULL);
282 if (put_rusage (ru, &r)) return -EFAULT; 236 set_fs (old_fs);
283 if (stat_addr && put_user (status, stat_addr)) 237
284 return -EFAULT; 238 if (ret < 0 || uinfo->si_signo == 0)
285 return ret; 239 return ret;
286 }
287}
288 240
289asmlinkage int 241 if (uru)
290sys32_waitpid(compat_pid_t pid, unsigned int *stat_addr, int options) 242 ret = put_compat_rusage(&ru, uru);
291{ 243 return ret;
292 return sys32_wait4(pid, stat_addr, options, NULL);
293} 244}
294 245
295struct sysinfo32 { 246struct sysinfo32 {
@@ -1467,3 +1418,80 @@ asmlinkage long sys32_socketcall(int call, unsigned int *args32)
1467 } 1418 }
1468 return err; 1419 return err;
1469} 1420}
1421
1422struct sigevent32 {
1423 u32 sigev_value;
1424 u32 sigev_signo;
1425 u32 sigev_notify;
1426 u32 payload[(64 / 4) - 3];
1427};
1428
1429extern asmlinkage long
1430sys_timer_create(clockid_t which_clock,
1431 struct sigevent __user *timer_event_spec,
1432 timer_t __user * created_timer_id);
1433
1434long
1435sys32_timer_create(u32 clock, struct sigevent32 __user *se32, timer_t __user *timer_id)
1436{
1437 struct sigevent __user *p = NULL;
1438 if (se32) {
1439 struct sigevent se;
1440 p = compat_alloc_user_space(sizeof(struct sigevent));
1441 memset(&se, 0, sizeof(struct sigevent));
1442 if (get_user(se.sigev_value.sival_int, &se32->sigev_value) ||
1443 __get_user(se.sigev_signo, &se32->sigev_signo) ||
1444 __get_user(se.sigev_notify, &se32->sigev_notify) ||
1445 __copy_from_user(&se._sigev_un._pad, &se32->payload,
1446 sizeof(se32->payload)) ||
1447 copy_to_user(p, &se, sizeof(se)))
1448 return -EFAULT;
1449 }
1450 return sys_timer_create(clock, p, timer_id);
1451}
1452
1453asmlinkage long
1454sysn32_rt_sigtimedwait(const sigset_t __user *uthese,
1455 siginfo_t __user *uinfo,
1456 const struct compat_timespec __user *uts32,
1457 size_t sigsetsize)
1458{
1459 struct timespec __user *uts = NULL;
1460
1461 if (uts32) {
1462 struct timespec ts;
1463 uts = compat_alloc_user_space(sizeof(struct timespec));
1464 if (get_user(ts.tv_sec, &uts32->tv_sec) ||
1465 get_user(ts.tv_nsec, &uts32->tv_nsec) ||
1466 copy_to_user (uts, &ts, sizeof (ts)))
1467 return -EFAULT;
1468 }
1469 return sys_rt_sigtimedwait(uthese, uinfo, uts, sigsetsize);
1470}
1471
1472save_static_function(sys32_clone);
1473__attribute_used__ noinline static int
1474_sys32_clone(nabi_no_regargs struct pt_regs regs)
1475{
1476 unsigned long clone_flags;
1477 unsigned long newsp;
1478 int __user *parent_tidptr, *child_tidptr;
1479
1480 clone_flags = regs.regs[4];
1481 newsp = regs.regs[5];
1482 if (!newsp)
1483 newsp = regs.regs[29];
1484 parent_tidptr = (int *) regs.regs[6];
1485
1486 /* Use __dummy4 instead of getting it off the stack, so that
1487 syscall() works. */
1488 child_tidptr = (int __user *) __dummy4;
1489 return do_fork(clone_flags, newsp, &regs, 0,
1490 parent_tidptr, child_tidptr);
1491}
1492
1493extern asmlinkage void sys_set_thread_area(u32 addr);
1494asmlinkage void sys32_set_thread_area(u32 addr)
1495{
1496 sys_set_thread_area(AA(addr));
1497}
diff --git a/arch/mips/kernel/module-elf32.c b/arch/mips/kernel/module-elf32.c
deleted file mode 100644
index ffd216d6d6dc..000000000000
--- a/arch/mips/kernel/module-elf32.c
+++ /dev/null
@@ -1,250 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 *
16 * Copyright (C) 2001 Rusty Russell.
17 * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
18 */
19
20#undef DEBUG
21
22#include <linux/moduleloader.h>
23#include <linux/elf.h>
24#include <linux/vmalloc.h>
25#include <linux/slab.h>
26#include <linux/fs.h>
27#include <linux/string.h>
28#include <linux/kernel.h>
29
30struct mips_hi16 {
31 struct mips_hi16 *next;
32 Elf32_Addr *addr;
33 Elf32_Addr value;
34};
35
36static struct mips_hi16 *mips_hi16_list;
37
38void *module_alloc(unsigned long size)
39{
40 if (size == 0)
41 return NULL;
42 return vmalloc(size);
43}
44
45
46/* Free memory returned from module_alloc */
47void module_free(struct module *mod, void *module_region)
48{
49 vfree(module_region);
50 /* FIXME: If module_region == mod->init_region, trim exception
51 table entries. */
52}
53
54int module_frob_arch_sections(Elf_Ehdr *hdr,
55 Elf_Shdr *sechdrs,
56 char *secstrings,
57 struct module *mod)
58{
59 return 0;
60}
61
62static int apply_r_mips_none(struct module *me, uint32_t *location,
63 Elf32_Addr v)
64{
65 return 0;
66}
67
68static int apply_r_mips_32(struct module *me, uint32_t *location,
69 Elf32_Addr v)
70{
71 *location += v;
72
73 return 0;
74}
75
76static int apply_r_mips_26(struct module *me, uint32_t *location,
77 Elf32_Addr v)
78{
79 if (v % 4) {
80 printk(KERN_ERR "module %s: dangerous relocation\n", me->name);
81 return -ENOEXEC;
82 }
83
84 if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
85 printk(KERN_ERR
86 "module %s: relocation overflow\n",
87 me->name);
88 return -ENOEXEC;
89 }
90
91 *location = (*location & ~0x03ffffff) |
92 ((*location + (v >> 2)) & 0x03ffffff);
93
94 return 0;
95}
96
97static int apply_r_mips_hi16(struct module *me, uint32_t *location,
98 Elf32_Addr v)
99{
100 struct mips_hi16 *n;
101
102 /*
103 * We cannot relocate this one now because we don't know the value of
104 * the carry we need to add. Save the information, and let LO16 do the
105 * actual relocation.
106 */
107 n = kmalloc(sizeof *n, GFP_KERNEL);
108 if (!n)
109 return -ENOMEM;
110
111 n->addr = location;
112 n->value = v;
113 n->next = mips_hi16_list;
114 mips_hi16_list = n;
115
116 return 0;
117}
118
119static int apply_r_mips_lo16(struct module *me, uint32_t *location,
120 Elf32_Addr v)
121{
122 unsigned long insnlo = *location;
123 Elf32_Addr val, vallo;
124
125 /* Sign extend the addend we extract from the lo insn. */
126 vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
127
128 if (mips_hi16_list != NULL) {
129 struct mips_hi16 *l;
130
131 l = mips_hi16_list;
132 while (l != NULL) {
133 struct mips_hi16 *next;
134 unsigned long insn;
135
136 /*
137 * The value for the HI16 had best be the same.
138 */
139 if (v != l->value)
140 goto out_danger;
141
142 /*
143 * Do the HI16 relocation. Note that we actually don't
144 * need to know anything about the LO16 itself, except
145 * where to find the low 16 bits of the addend needed
146 * by the LO16.
147 */
148 insn = *l->addr;
149 val = ((insn & 0xffff) << 16) + vallo;
150 val += v;
151
152 /*
153 * Account for the sign extension that will happen in
154 * the low bits.
155 */
156 val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff;
157
158 insn = (insn & ~0xffff) | val;
159 *l->addr = insn;
160
161 next = l->next;
162 kfree(l);
163 l = next;
164 }
165
166 mips_hi16_list = NULL;
167 }
168
169 /*
170 * Ok, we're done with the HI16 relocs. Now deal with the LO16.
171 */
172 val = v + vallo;
173 insnlo = (insnlo & ~0xffff) | (val & 0xffff);
174 *location = insnlo;
175
176 return 0;
177
178out_danger:
179 printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name);
180
181 return -ENOEXEC;
182}
183
184static int (*reloc_handlers[]) (struct module *me, uint32_t *location,
185 Elf32_Addr v) = {
186 [R_MIPS_NONE] = apply_r_mips_none,
187 [R_MIPS_32] = apply_r_mips_32,
188 [R_MIPS_26] = apply_r_mips_26,
189 [R_MIPS_HI16] = apply_r_mips_hi16,
190 [R_MIPS_LO16] = apply_r_mips_lo16
191};
192
193int apply_relocate(Elf32_Shdr *sechdrs,
194 const char *strtab,
195 unsigned int symindex,
196 unsigned int relsec,
197 struct module *me)
198{
199 Elf32_Rel *rel = (void *) sechdrs[relsec].sh_addr;
200 Elf32_Sym *sym;
201 uint32_t *location;
202 unsigned int i;
203 Elf32_Addr v;
204 int res;
205
206 pr_debug("Applying relocate section %u to %u\n", relsec,
207 sechdrs[relsec].sh_info);
208
209 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
210 Elf32_Word r_info = rel[i].r_info;
211
212 /* This is where to make the change */
213 location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
214 + rel[i].r_offset;
215 /* This is the symbol it is referring to */
216 sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
217 + ELF32_R_SYM(r_info);
218 if (!sym->st_value) {
219 printk(KERN_WARNING "%s: Unknown symbol %s\n",
220 me->name, strtab + sym->st_name);
221 return -ENOENT;
222 }
223
224 v = sym->st_value;
225
226 res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v);
227 if (res)
228 return res;
229 }
230
231 return 0;
232}
233
234int apply_relocate_add(Elf32_Shdr *sechdrs,
235 const char *strtab,
236 unsigned int symindex,
237 unsigned int relsec,
238 struct module *me)
239{
240 /*
241 * Current binutils always generate .rela relocations. Keep smiling
242 * if it's empty, abort otherwise.
243 */
244 if (!sechdrs[relsec].sh_size)
245 return 0;
246
247 printk(KERN_ERR "module %s: ADD RELOCATION unsupported\n",
248 me->name);
249 return -ENOEXEC;
250}
diff --git a/arch/mips/kernel/module-elf64.c b/arch/mips/kernel/module-elf64.c
deleted file mode 100644
index e804792ee1ee..000000000000
--- a/arch/mips/kernel/module-elf64.c
+++ /dev/null
@@ -1,274 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 *
16 * Copyright (C) 2001 Rusty Russell.
17 * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
18 */
19
20#undef DEBUG
21
22#include <linux/moduleloader.h>
23#include <linux/elf.h>
24#include <linux/vmalloc.h>
25#include <linux/slab.h>
26#include <linux/fs.h>
27#include <linux/string.h>
28#include <linux/kernel.h>
29
30struct mips_hi16 {
31 struct mips_hi16 *next;
32 Elf32_Addr *addr;
33 Elf64_Addr value;
34};
35
36static struct mips_hi16 *mips_hi16_list;
37
38void *module_alloc(unsigned long size)
39{
40 if (size == 0)
41 return NULL;
42 return vmalloc(size);
43}
44
45
46/* Free memory returned from module_alloc */
47void module_free(struct module *mod, void *module_region)
48{
49 vfree(module_region);
50 /* FIXME: If module_region == mod->init_region, trim exception
51 table entries. */
52}
53
54int module_frob_arch_sections(Elf_Ehdr *hdr,
55 Elf_Shdr *sechdrs,
56 char *secstrings,
57 struct module *mod)
58{
59 return 0;
60}
61
62int apply_relocate(Elf64_Shdr *sechdrs,
63 const char *strtab,
64 unsigned int symindex,
65 unsigned int relsec,
66 struct module *me)
67{
68 /*
69 * We don't want to deal with REL relocations - RELA is so much saner.
70 */
71 if (!sechdrs[relsec].sh_size)
72 return 0;
73
74 printk(KERN_ERR "module %s: REL relocation unsupported\n",
75 me->name);
76 return -ENOEXEC;
77}
78
79static int apply_r_mips_none(struct module *me, uint32_t *location,
80 Elf64_Addr v)
81{
82 return 0;
83}
84
85static int apply_r_mips_32(struct module *me, uint32_t *location,
86 Elf64_Addr v)
87{
88 *location = v;
89
90 return 0;
91}
92
93static int apply_r_mips_26(struct module *me, uint32_t *location,
94 Elf64_Addr v)
95{
96 if (v % 4) {
97 printk(KERN_ERR "module %s: dangerous relocation\n", me->name);
98 return -ENOEXEC;
99 }
100
101 if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
102 printk(KERN_ERR
103 "module %s: relocation overflow\n",
104 me->name);
105 return -ENOEXEC;
106 }
107
108 *location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff);
109
110 return 0;
111}
112
113static int apply_r_mips_hi16(struct module *me, uint32_t *location,
114 Elf64_Addr v)
115{
116 struct mips_hi16 *n;
117
118 /*
119 * We cannot relocate this one now because we don't know the value of
120 * the carry we need to add. Save the information, and let LO16 do the
121 * actual relocation.
122 */
123 n = kmalloc(sizeof *n, GFP_KERNEL);
124 if (!n)
125 return -ENOMEM;
126
127 n->addr = location;
128 n->value = v;
129 n->next = mips_hi16_list;
130 mips_hi16_list = n;
131
132 return 0;
133}
134
135static int apply_r_mips_lo16(struct module *me, uint32_t *location,
136 Elf64_Addr v)
137{
138 unsigned long insnlo = *location;
139 Elf32_Addr val, vallo;
140
141 /* Sign extend the addend we extract from the lo insn. */
142 vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
143
144 if (mips_hi16_list != NULL) {
145 struct mips_hi16 *l;
146
147 l = mips_hi16_list;
148 while (l != NULL) {
149 struct mips_hi16 *next;
150 unsigned long insn;
151
152 /*
153 * The value for the HI16 had best be the same.
154 */
155 if (v != l->value)
156 goto out_danger;
157
158 /*
159 * Do the HI16 relocation. Note that we actually don't
160 * need to know anything about the LO16 itself, except
161 * where to find the low 16 bits of the addend needed
162 * by the LO16.
163 */
164 insn = *l->addr;
165 val = ((insn & 0xffff) << 16) + vallo;
166 val += v;
167
168 /*
169 * Account for the sign extension that will happen in
170 * the low bits.
171 */
172 val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff;
173
174 insn = (insn & ~0xffff) | val;
175 *l->addr = insn;
176
177 next = l->next;
178 kfree(l);
179 l = next;
180 }
181
182 mips_hi16_list = NULL;
183 }
184
185 /*
186 * Ok, we're done with the HI16 relocs. Now deal with the LO16.
187 */
188 insnlo = (insnlo & ~0xffff) | (v & 0xffff);
189 *location = insnlo;
190
191 return 0;
192
193out_danger:
194 printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name);
195
196 return -ENOEXEC;
197}
198
199static int apply_r_mips_64(struct module *me, uint32_t *location,
200 Elf64_Addr v)
201{
202 *(uint64_t *) location = v;
203
204 return 0;
205}
206
207
208static int apply_r_mips_higher(struct module *me, uint32_t *location,
209 Elf64_Addr v)
210{
211 *location = (*location & 0xffff0000) |
212 ((((long long) v + 0x80008000LL) >> 32) & 0xffff);
213
214 return 0;
215}
216
217static int apply_r_mips_highest(struct module *me, uint32_t *location,
218 Elf64_Addr v)
219{
220 *location = (*location & 0xffff0000) |
221 ((((long long) v + 0x800080008000LL) >> 48) & 0xffff);
222
223 return 0;
224}
225
226static int (*reloc_handlers[]) (struct module *me, uint32_t *location,
227 Elf64_Addr v) = {
228 [R_MIPS_NONE] = apply_r_mips_none,
229 [R_MIPS_32] = apply_r_mips_32,
230 [R_MIPS_26] = apply_r_mips_26,
231 [R_MIPS_HI16] = apply_r_mips_hi16,
232 [R_MIPS_LO16] = apply_r_mips_lo16,
233 [R_MIPS_64] = apply_r_mips_64,
234 [R_MIPS_HIGHER] = apply_r_mips_higher,
235 [R_MIPS_HIGHEST] = apply_r_mips_highest
236};
237
238int apply_relocate_add(Elf64_Shdr *sechdrs,
239 const char *strtab,
240 unsigned int symindex,
241 unsigned int relsec,
242 struct module *me)
243{
244 Elf64_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr;
245 Elf64_Sym *sym;
246 uint32_t *location;
247 unsigned int i;
248 Elf64_Addr v;
249 int res;
250
251 pr_debug("Applying relocate section %u to %u\n", relsec,
252 sechdrs[relsec].sh_info);
253
254 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
255 /* This is where to make the change */
256 location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
257 + rel[i].r_offset;
258 /* This is the symbol it is referring to */
259 sym = (Elf64_Sym *)sechdrs[symindex].sh_addr + rel[i].r_sym;
260 if (!sym->st_value) {
261 printk(KERN_WARNING "%s: Unknown symbol %s\n",
262 me->name, strtab + sym->st_name);
263 return -ENOENT;
264 }
265
266 v = sym->st_value;
267
268 res = reloc_handlers[rel[i].r_type](me, location, v);
269 if (res)
270 return res;
271 }
272
273 return 0;
274}
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index 458af3c7a639..e54a7f442f8a 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -1,9 +1,345 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 *
16 * Copyright (C) 2001 Rusty Russell.
17 * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
18 * Copyright (C) 2005 Thiemo Seufer
19 */
20
21#undef DEBUG
22
23#include <linux/moduleloader.h>
24#include <linux/elf.h>
25#include <linux/vmalloc.h>
26#include <linux/slab.h>
27#include <linux/fs.h>
28#include <linux/string.h>
29#include <linux/kernel.h>
1#include <linux/module.h> 30#include <linux/module.h>
2#include <linux/spinlock.h> 31#include <linux/spinlock.h>
3 32
33struct mips_hi16 {
34 struct mips_hi16 *next;
35 Elf_Addr *addr;
36 Elf_Addr value;
37};
38
39static struct mips_hi16 *mips_hi16_list;
40
4static LIST_HEAD(dbe_list); 41static LIST_HEAD(dbe_list);
5static DEFINE_SPINLOCK(dbe_lock); 42static DEFINE_SPINLOCK(dbe_lock);
6 43
44void *module_alloc(unsigned long size)
45{
46 if (size == 0)
47 return NULL;
48 return vmalloc(size);
49}
50
51/* Free memory returned from module_alloc */
52void module_free(struct module *mod, void *module_region)
53{
54 vfree(module_region);
55 /* FIXME: If module_region == mod->init_region, trim exception
56 table entries. */
57}
58
59int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
60 char *secstrings, struct module *mod)
61{
62 return 0;
63}
64
65static int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v)
66{
67 return 0;
68}
69
70static int apply_r_mips_32_rel(struct module *me, u32 *location, Elf_Addr v)
71{
72 *location += v;
73
74 return 0;
75}
76
77static int apply_r_mips_32_rela(struct module *me, u32 *location, Elf_Addr v)
78{
79 *location = v;
80
81 return 0;
82}
83
84static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v)
85{
86 if (v % 4) {
87 printk(KERN_ERR "module %s: dangerous relocation\n", me->name);
88 return -ENOEXEC;
89 }
90
91 if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
92 printk(KERN_ERR
93 "module %s: relocation overflow\n",
94 me->name);
95 return -ENOEXEC;
96 }
97
98 *location = (*location & ~0x03ffffff) |
99 ((*location + (v >> 2)) & 0x03ffffff);
100
101 return 0;
102}
103
104static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v)
105{
106 if (v % 4) {
107 printk(KERN_ERR "module %s: dangerous relocation\n", me->name);
108 return -ENOEXEC;
109 }
110
111 if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
112 printk(KERN_ERR
113 "module %s: relocation overflow\n",
114 me->name);
115 return -ENOEXEC;
116 }
117
118 *location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff);
119
120 return 0;
121}
122
123static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v)
124{
125 struct mips_hi16 *n;
126
127 /*
128 * We cannot relocate this one now because we don't know the value of
129 * the carry we need to add. Save the information, and let LO16 do the
130 * actual relocation.
131 */
132 n = kmalloc(sizeof *n, GFP_KERNEL);
133 if (!n)
134 return -ENOMEM;
135
136 n->addr = (Elf_Addr *)location;
137 n->value = v;
138 n->next = mips_hi16_list;
139 mips_hi16_list = n;
140
141 return 0;
142}
143
144static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v)
145{
146 *location = (*location & 0xffff0000) |
147 ((((long long) v + 0x8000LL) >> 16) & 0xffff);
148
149 return 0;
150}
151
152static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
153{
154 unsigned long insnlo = *location;
155 Elf_Addr val, vallo;
156
157 /* Sign extend the addend we extract from the lo insn. */
158 vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
159
160 if (mips_hi16_list != NULL) {
161 struct mips_hi16 *l;
162
163 l = mips_hi16_list;
164 while (l != NULL) {
165 struct mips_hi16 *next;
166 unsigned long insn;
167
168 /*
169 * The value for the HI16 had best be the same.
170 */
171 if (v != l->value)
172 goto out_danger;
173
174 /*
175 * Do the HI16 relocation. Note that we actually don't
176 * need to know anything about the LO16 itself, except
177 * where to find the low 16 bits of the addend needed
178 * by the LO16.
179 */
180 insn = *l->addr;
181 val = ((insn & 0xffff) << 16) + vallo;
182 val += v;
183
184 /*
185 * Account for the sign extension that will happen in
186 * the low bits.
187 */
188 val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff;
189
190 insn = (insn & ~0xffff) | val;
191 *l->addr = insn;
192
193 next = l->next;
194 kfree(l);
195 l = next;
196 }
197
198 mips_hi16_list = NULL;
199 }
200
201 /*
202 * Ok, we're done with the HI16 relocs. Now deal with the LO16.
203 */
204 val = v + vallo;
205 insnlo = (insnlo & ~0xffff) | (val & 0xffff);
206 *location = insnlo;
207
208 return 0;
209
210out_danger:
211 printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name);
212
213 return -ENOEXEC;
214}
215
216static int apply_r_mips_lo16_rela(struct module *me, u32 *location, Elf_Addr v)
217{
218 *location = (*location & 0xffff0000) | (v & 0xffff);
219
220 return 0;
221}
222
223static int apply_r_mips_64_rela(struct module *me, u32 *location, Elf_Addr v)
224{
225 *(Elf_Addr *)location = v;
226
227 return 0;
228}
229
230static int apply_r_mips_higher_rela(struct module *me, u32 *location,
231 Elf_Addr v)
232{
233 *location = (*location & 0xffff0000) |
234 ((((long long) v + 0x80008000LL) >> 32) & 0xffff);
235
236 return 0;
237}
238
239static int apply_r_mips_highest_rela(struct module *me, u32 *location,
240 Elf_Addr v)
241{
242 *location = (*location & 0xffff0000) |
243 ((((long long) v + 0x800080008000LL) >> 48) & 0xffff);
244
245 return 0;
246}
247
248static int (*reloc_handlers_rel[]) (struct module *me, u32 *location,
249 Elf_Addr v) = {
250 [R_MIPS_NONE] = apply_r_mips_none,
251 [R_MIPS_32] = apply_r_mips_32_rel,
252 [R_MIPS_26] = apply_r_mips_26_rel,
253 [R_MIPS_HI16] = apply_r_mips_hi16_rel,
254 [R_MIPS_LO16] = apply_r_mips_lo16_rel
255};
256
257static int (*reloc_handlers_rela[]) (struct module *me, u32 *location,
258 Elf_Addr v) = {
259 [R_MIPS_NONE] = apply_r_mips_none,
260 [R_MIPS_32] = apply_r_mips_32_rela,
261 [R_MIPS_26] = apply_r_mips_26_rela,
262 [R_MIPS_HI16] = apply_r_mips_hi16_rela,
263 [R_MIPS_LO16] = apply_r_mips_lo16_rela,
264 [R_MIPS_64] = apply_r_mips_64_rela,
265 [R_MIPS_HIGHER] = apply_r_mips_higher_rela,
266 [R_MIPS_HIGHEST] = apply_r_mips_highest_rela
267};
268
269int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
270 unsigned int symindex, unsigned int relsec,
271 struct module *me)
272{
273 Elf_Mips_Rel *rel = (void *) sechdrs[relsec].sh_addr;
274 Elf_Sym *sym;
275 u32 *location;
276 unsigned int i;
277 Elf_Addr v;
278 int res;
279
280 pr_debug("Applying relocate section %u to %u\n", relsec,
281 sechdrs[relsec].sh_info);
282
283 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
284 /* This is where to make the change */
285 location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
286 + rel[i].r_offset;
287 /* This is the symbol it is referring to */
288 sym = (Elf_Sym *)sechdrs[symindex].sh_addr
289 + ELF_MIPS_R_SYM(rel[i]);
290 if (!sym->st_value) {
291 printk(KERN_WARNING "%s: Unknown symbol %s\n",
292 me->name, strtab + sym->st_name);
293 return -ENOENT;
294 }
295
296 v = sym->st_value;
297
298 res = reloc_handlers_rel[ELF_MIPS_R_TYPE(rel[i])](me, location, v);
299 if (res)
300 return res;
301 }
302
303 return 0;
304}
305
306int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
307 unsigned int symindex, unsigned int relsec,
308 struct module *me)
309{
310 Elf_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr;
311 Elf_Sym *sym;
312 u32 *location;
313 unsigned int i;
314 Elf_Addr v;
315 int res;
316
317 pr_debug("Applying relocate section %u to %u\n", relsec,
318 sechdrs[relsec].sh_info);
319
320 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
321 /* This is where to make the change */
322 location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
323 + rel[i].r_offset;
324 /* This is the symbol it is referring to */
325 sym = (Elf_Sym *)sechdrs[symindex].sh_addr
326 + ELF_MIPS_R_SYM(rel[i]);
327 if (!sym->st_value) {
328 printk(KERN_WARNING "%s: Unknown symbol %s\n",
329 me->name, strtab + sym->st_name);
330 return -ENOENT;
331 }
332
333 v = sym->st_value + rel[i].r_addend;
334
335 res = reloc_handlers_rela[ELF_MIPS_R_TYPE(rel[i])](me, location, v);
336 if (res)
337 return res;
338 }
339
340 return 0;
341}
342
7/* Given an address, look for it in the module exception tables. */ 343/* Given an address, look for it in the module exception tables. */
8const struct exception_table_entry *search_module_dbetables(unsigned long addr) 344const struct exception_table_entry *search_module_dbetables(unsigned long addr)
9{ 345{
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 0f159f30e894..86fe15b273cd 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -2,7 +2,8 @@
2 * linux/arch/mips/kernel/proc.c 2 * linux/arch/mips/kernel/proc.c
3 * 3 *
4 * Copyright (C) 1995, 1996, 2001 Ralf Baechle 4 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
5 * Copyright (C) 2001 MIPS Technologies, Inc. 5 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
6 * Copyright (C) 2004 Maciej W. Rozycki
6 */ 7 */
7#include <linux/config.h> 8#include <linux/config.h>
8#include <linux/delay.h> 9#include <linux/delay.h>
@@ -19,63 +20,69 @@
19unsigned int vced_count, vcei_count; 20unsigned int vced_count, vcei_count;
20 21
21static const char *cpu_name[] = { 22static const char *cpu_name[] = {
22 [CPU_UNKNOWN] "unknown", 23 [CPU_UNKNOWN] = "unknown",
23 [CPU_R2000] "R2000", 24 [CPU_R2000] = "R2000",
24 [CPU_R3000] "R3000", 25 [CPU_R3000] = "R3000",
25 [CPU_R3000A] "R3000A", 26 [CPU_R3000A] = "R3000A",
26 [CPU_R3041] "R3041", 27 [CPU_R3041] = "R3041",
27 [CPU_R3051] "R3051", 28 [CPU_R3051] = "R3051",
28 [CPU_R3052] "R3052", 29 [CPU_R3052] = "R3052",
29 [CPU_R3081] "R3081", 30 [CPU_R3081] = "R3081",
30 [CPU_R3081E] "R3081E", 31 [CPU_R3081E] = "R3081E",
31 [CPU_R4000PC] "R4000PC", 32 [CPU_R4000PC] = "R4000PC",
32 [CPU_R4000SC] "R4000SC", 33 [CPU_R4000SC] = "R4000SC",
33 [CPU_R4000MC] "R4000MC", 34 [CPU_R4000MC] = "R4000MC",
34 [CPU_R4200] "R4200", 35 [CPU_R4200] = "R4200",
35 [CPU_R4400PC] "R4400PC", 36 [CPU_R4400PC] = "R4400PC",
36 [CPU_R4400SC] "R4400SC", 37 [CPU_R4400SC] = "R4400SC",
37 [CPU_R4400MC] "R4400MC", 38 [CPU_R4400MC] = "R4400MC",
38 [CPU_R4600] "R4600", 39 [CPU_R4600] = "R4600",
39 [CPU_R6000] "R6000", 40 [CPU_R6000] = "R6000",
40 [CPU_R6000A] "R6000A", 41 [CPU_R6000A] = "R6000A",
41 [CPU_R8000] "R8000", 42 [CPU_R8000] = "R8000",
42 [CPU_R10000] "R10000", 43 [CPU_R10000] = "R10000",
43 [CPU_R12000] "R12000", 44 [CPU_R12000] = "R12000",
44 [CPU_R4300] "R4300", 45 [CPU_R4300] = "R4300",
45 [CPU_R4650] "R4650", 46 [CPU_R4650] = "R4650",
46 [CPU_R4700] "R4700", 47 [CPU_R4700] = "R4700",
47 [CPU_R5000] "R5000", 48 [CPU_R5000] = "R5000",
48 [CPU_R5000A] "R5000A", 49 [CPU_R5000A] = "R5000A",
49 [CPU_R4640] "R4640", 50 [CPU_R4640] = "R4640",
50 [CPU_NEVADA] "Nevada", 51 [CPU_NEVADA] = "Nevada",
51 [CPU_RM7000] "RM7000", 52 [CPU_RM7000] = "RM7000",
52 [CPU_RM9000] "RM9000", 53 [CPU_RM9000] = "RM9000",
53 [CPU_R5432] "R5432", 54 [CPU_R5432] = "R5432",
54 [CPU_4KC] "MIPS 4Kc", 55 [CPU_4KC] = "MIPS 4Kc",
55 [CPU_5KC] "MIPS 5Kc", 56 [CPU_5KC] = "MIPS 5Kc",
56 [CPU_R4310] "R4310", 57 [CPU_R4310] = "R4310",
57 [CPU_SB1] "SiByte SB1", 58 [CPU_SB1] = "SiByte SB1",
58 [CPU_TX3912] "TX3912", 59 [CPU_SB1A] = "SiByte SB1A",
59 [CPU_TX3922] "TX3922", 60 [CPU_TX3912] = "TX3912",
60 [CPU_TX3927] "TX3927", 61 [CPU_TX3922] = "TX3922",
61 [CPU_AU1000] "Au1000", 62 [CPU_TX3927] = "TX3927",
62 [CPU_AU1500] "Au1500", 63 [CPU_AU1000] = "Au1000",
63 [CPU_4KEC] "MIPS 4KEc", 64 [CPU_AU1500] = "Au1500",
64 [CPU_4KSC] "MIPS 4KSc", 65 [CPU_AU1100] = "Au1100",
65 [CPU_VR41XX] "NEC Vr41xx", 66 [CPU_AU1550] = "Au1550",
66 [CPU_R5500] "R5500", 67 [CPU_AU1200] = "Au1200",
67 [CPU_TX49XX] "TX49xx", 68 [CPU_4KEC] = "MIPS 4KEc",
68 [CPU_20KC] "MIPS 20Kc", 69 [CPU_4KSC] = "MIPS 4KSc",
69 [CPU_24K] "MIPS 24K", 70 [CPU_VR41XX] = "NEC Vr41xx",
70 [CPU_25KF] "MIPS 25Kf", 71 [CPU_R5500] = "R5500",
71 [CPU_VR4111] "NEC VR4111", 72 [CPU_TX49XX] = "TX49xx",
72 [CPU_VR4121] "NEC VR4121", 73 [CPU_20KC] = "MIPS 20Kc",
73 [CPU_VR4122] "NEC VR4122", 74 [CPU_24K] = "MIPS 24K",
74 [CPU_VR4131] "NEC VR4131", 75 [CPU_25KF] = "MIPS 25Kf",
75 [CPU_VR4133] "NEC VR4133", 76 [CPU_34K] = "MIPS 34K",
76 [CPU_VR4181] "NEC VR4181", 77 [CPU_VR4111] = "NEC VR4111",
77 [CPU_VR4181A] "NEC VR4181A", 78 [CPU_VR4121] = "NEC VR4121",
78 [CPU_SR71000] "Sandcraft SR71000" 79 [CPU_VR4122] = "NEC VR4122",
80 [CPU_VR4131] = "NEC VR4131",
81 [CPU_VR4133] = "NEC VR4133",
82 [CPU_VR4181] = "NEC VR4181",
83 [CPU_VR4181A] = "NEC VR4181A",
84 [CPU_SR71000] = "Sandcraft SR71000",
85 [CPU_PR4450] = "Philips PR4450",
79}; 86};
80 87
81 88
@@ -105,8 +112,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
105 (version >> 4) & 0x0f, version & 0x0f, 112 (version >> 4) & 0x0f, version & 0x0f,
106 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); 113 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
107 seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", 114 seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
108 loops_per_jiffy / (500000/HZ), 115 cpu_data[n].udelay_val / (500000/HZ),
109 (loops_per_jiffy / (5000/HZ)) % 100); 116 (cpu_data[n].udelay_val / (5000/HZ)) % 100);
110 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); 117 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
111 seq_printf(m, "microsecond timers\t: %s\n", 118 seq_printf(m, "microsecond timers\t: %s\n",
112 cpu_has_counter ? "yes" : "no"); 119 cpu_has_counter ? "yes" : "no");
@@ -115,6 +122,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
115 cpu_has_divec ? "yes" : "no"); 122 cpu_has_divec ? "yes" : "no");
116 seq_printf(m, "hardware watchpoint\t: %s\n", 123 seq_printf(m, "hardware watchpoint\t: %s\n",
117 cpu_has_watch ? "yes" : "no"); 124 cpu_has_watch ? "yes" : "no");
125 seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
126 cpu_has_mips16 ? " mips16" : "",
127 cpu_has_mdmx ? " mdmx" : "",
128 cpu_has_mips3d ? " mips3d" : "",
129 cpu_has_smartmips ? " smartmips" : "",
130 cpu_has_dsp ? " dsp" : "",
131 cpu_has_mipsmt ? " mt" : ""
132 );
118 133
119 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", 134 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
120 cpu_has_vce ? "%u" : "not available"); 135 cpu_has_vce ? "%u" : "not available");
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index e4f2f8011387..4fe3d5715c41 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -25,8 +25,10 @@
25#include <linux/init.h> 25#include <linux/init.h>
26#include <linux/completion.h> 26#include <linux/completion.h>
27 27
28#include <asm/abi.h>
28#include <asm/bootinfo.h> 29#include <asm/bootinfo.h>
29#include <asm/cpu.h> 30#include <asm/cpu.h>
31#include <asm/dsp.h>
30#include <asm/fpu.h> 32#include <asm/fpu.h>
31#include <asm/pgtable.h> 33#include <asm/pgtable.h>
32#include <asm/system.h> 34#include <asm/system.h>
@@ -39,14 +41,6 @@
39#include <asm/inst.h> 41#include <asm/inst.h>
40 42
41/* 43/*
42 * We use this if we don't have any better idle routine..
43 * (This to kill: kernel/platform.c.
44 */
45void default_idle (void)
46{
47}
48
49/*
50 * The idle thread. There's no useful work to be done, so just try to conserve 44 * The idle thread. There's no useful work to be done, so just try to conserve
51 * power and have a low exit latency (ie sit in a loop waiting for somebody to 45 * power and have a low exit latency (ie sit in a loop waiting for somebody to
52 * say that they'd like to reschedule) 46 * say that they'd like to reschedule)
@@ -62,6 +56,54 @@ ATTRIB_NORET void cpu_idle(void)
62 } 56 }
63} 57}
64 58
59extern int do_signal(sigset_t *oldset, struct pt_regs *regs);
60extern int do_signal32(sigset_t *oldset, struct pt_regs *regs);
61
62/*
63 * Native o32 and N64 ABI without DSP ASE
64 */
65extern int setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
66 int signr, sigset_t *set);
67extern int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
68 int signr, sigset_t *set, siginfo_t *info);
69
70struct mips_abi mips_abi = {
71 .do_signal = do_signal,
72#ifdef CONFIG_TRAD_SIGNALS
73 .setup_frame = setup_frame,
74#endif
75 .setup_rt_frame = setup_rt_frame
76};
77
78#ifdef CONFIG_MIPS32_O32
79/*
80 * o32 compatibility on 64-bit kernels, without DSP ASE
81 */
82extern int setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
83 int signr, sigset_t *set);
84extern int setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
85 int signr, sigset_t *set, siginfo_t *info);
86
87struct mips_abi mips_abi_32 = {
88 .do_signal = do_signal32,
89 .setup_frame = setup_frame_32,
90 .setup_rt_frame = setup_rt_frame_32
91};
92#endif /* CONFIG_MIPS32_O32 */
93
94#ifdef CONFIG_MIPS32_N32
95/*
96 * N32 on 64-bit kernels, without DSP ASE
97 */
98extern int setup_rt_frame_n32(struct k_sigaction * ka, struct pt_regs *regs,
99 int signr, sigset_t *set, siginfo_t *info);
100
101struct mips_abi mips_abi_n32 = {
102 .do_signal = do_signal,
103 .setup_rt_frame = setup_rt_frame_n32
104};
105#endif /* CONFIG_MIPS32_N32 */
106
65asmlinkage void ret_from_fork(void); 107asmlinkage void ret_from_fork(void);
66 108
67void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) 109void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
@@ -78,6 +120,8 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
78 regs->cp0_status = status; 120 regs->cp0_status = status;
79 clear_used_math(); 121 clear_used_math();
80 lose_fpu(); 122 lose_fpu();
123 if (cpu_has_dsp)
124 __init_dsp();
81 regs->cp0_epc = pc; 125 regs->cp0_epc = pc;
82 regs->regs[29] = sp; 126 regs->regs[29] = sp;
83 current_thread_info()->addr_limit = USER_DS; 127 current_thread_info()->addr_limit = USER_DS;
@@ -97,14 +141,17 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
97 struct thread_info *ti = p->thread_info; 141 struct thread_info *ti = p->thread_info;
98 struct pt_regs *childregs; 142 struct pt_regs *childregs;
99 long childksp; 143 long childksp;
144 p->set_child_tid = p->clear_child_tid = NULL;
100 145
101 childksp = (unsigned long)ti + THREAD_SIZE - 32; 146 childksp = (unsigned long)ti + THREAD_SIZE - 32;
102 147
103 preempt_disable(); 148 preempt_disable();
104 149
105 if (is_fpu_owner()) { 150 if (is_fpu_owner())
106 save_fp(p); 151 save_fp(p);
107 } 152
153 if (cpu_has_dsp)
154 save_dsp(p);
108 155
109 preempt_enable(); 156 preempt_enable();
110 157
@@ -142,6 +189,9 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
142 childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); 189 childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
143 clear_tsk_thread_flag(p, TIF_USEDFPU); 190 clear_tsk_thread_flag(p, TIF_USEDFPU);
144 191
192 if (clone_flags & CLONE_SETTLS)
193 ti->tp_value = regs->regs[7];
194
145 return 0; 195 return 0;
146} 196}
147 197
@@ -175,6 +225,14 @@ void dump_regs(elf_greg_t *gp, struct pt_regs *regs)
175#endif 225#endif
176} 226}
177 227
228int dump_task_regs (struct task_struct *tsk, elf_gregset_t *regs)
229{
230 struct thread_info *ti = tsk->thread_info;
231 long ksp = (unsigned long)ti + THREAD_SIZE - 32;
232 dump_regs(&(*regs)[0], (struct pt_regs *) ksp - 1);
233 return 1;
234}
235
178int dump_task_fpu (struct task_struct *t, elf_fpregset_t *fpr) 236int dump_task_fpu (struct task_struct *t, elf_fpregset_t *fpr)
179{ 237{
180 memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu)); 238 memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu));
@@ -211,22 +269,48 @@ long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
211 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL, NULL); 269 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
212} 270}
213 271
214struct mips_frame_info { 272static struct mips_frame_info {
273 void *func;
274 int omit_fp; /* compiled without fno-omit-frame-pointer */
215 int frame_offset; 275 int frame_offset;
216 int pc_offset; 276 int pc_offset;
277} schedule_frame, mfinfo[] = {
278 { schedule, 0 }, /* must be first */
279 /* arch/mips/kernel/semaphore.c */
280 { __down, 1 },
281 { __down_interruptible, 1 },
282 /* kernel/sched.c */
283#ifdef CONFIG_PREEMPT
284 { preempt_schedule, 0 },
285#endif
286 { wait_for_completion, 0 },
287 { interruptible_sleep_on, 0 },
288 { interruptible_sleep_on_timeout, 0 },
289 { sleep_on, 0 },
290 { sleep_on_timeout, 0 },
291 { yield, 0 },
292 { io_schedule, 0 },
293 { io_schedule_timeout, 0 },
294#if defined(CONFIG_SMP) && defined(CONFIG_PREEMPT)
295 { __preempt_spin_lock, 0 },
296 { __preempt_write_lock, 0 },
297#endif
298 /* kernel/timer.c */
299 { schedule_timeout, 1 },
300/* { nanosleep_restart, 1 }, */
301 /* lib/rwsem-spinlock.c */
302 { __down_read, 1 },
303 { __down_write, 1 },
217}; 304};
218static struct mips_frame_info schedule_frame; 305
219static struct mips_frame_info schedule_timeout_frame;
220static struct mips_frame_info sleep_on_frame;
221static struct mips_frame_info sleep_on_timeout_frame;
222static struct mips_frame_info wait_for_completion_frame;
223static int mips_frame_info_initialized; 306static int mips_frame_info_initialized;
224static int __init get_frame_info(struct mips_frame_info *info, void *func) 307static int __init get_frame_info(struct mips_frame_info *info)
225{ 308{
226 int i; 309 int i;
310 void *func = info->func;
227 union mips_instruction *ip = (union mips_instruction *)func; 311 union mips_instruction *ip = (union mips_instruction *)func;
228 info->pc_offset = -1; 312 info->pc_offset = -1;
229 info->frame_offset = -1; 313 info->frame_offset = info->omit_fp ? 0 : -1;
230 for (i = 0; i < 128; i++, ip++) { 314 for (i = 0; i < 128; i++, ip++) {
231 /* if jal, jalr, jr, stop. */ 315 /* if jal, jalr, jr, stop. */
232 if (ip->j_format.opcode == jal_op || 316 if (ip->j_format.opcode == jal_op ||
@@ -247,14 +331,16 @@ static int __init get_frame_info(struct mips_frame_info *info, void *func)
247 /* sw / sd $ra, offset($sp) */ 331 /* sw / sd $ra, offset($sp) */
248 if (ip->i_format.rt == 31) { 332 if (ip->i_format.rt == 31) {
249 if (info->pc_offset != -1) 333 if (info->pc_offset != -1)
250 break; 334 continue;
251 info->pc_offset = 335 info->pc_offset =
252 ip->i_format.simmediate / sizeof(long); 336 ip->i_format.simmediate / sizeof(long);
253 } 337 }
254 /* sw / sd $s8, offset($sp) */ 338 /* sw / sd $s8, offset($sp) */
255 if (ip->i_format.rt == 30) { 339 if (ip->i_format.rt == 30) {
340//#if 0 /* gcc 3.4 does aggressive optimization... */
256 if (info->frame_offset != -1) 341 if (info->frame_offset != -1)
257 break; 342 continue;
343//#endif
258 info->frame_offset = 344 info->frame_offset =
259 ip->i_format.simmediate / sizeof(long); 345 ip->i_format.simmediate / sizeof(long);
260 } 346 }
@@ -272,13 +358,25 @@ static int __init get_frame_info(struct mips_frame_info *info, void *func)
272 358
273static int __init frame_info_init(void) 359static int __init frame_info_init(void)
274{ 360{
275 mips_frame_info_initialized = 361 int i, found;
276 !get_frame_info(&schedule_frame, schedule) && 362 for (i = 0; i < ARRAY_SIZE(mfinfo); i++)
277 !get_frame_info(&schedule_timeout_frame, schedule_timeout) && 363 if (get_frame_info(&mfinfo[i]))
278 !get_frame_info(&sleep_on_frame, sleep_on) && 364 return -1;
279 !get_frame_info(&sleep_on_timeout_frame, sleep_on_timeout) && 365 schedule_frame = mfinfo[0];
280 !get_frame_info(&wait_for_completion_frame, wait_for_completion); 366 /* bubble sort */
281 367 do {
368 struct mips_frame_info tmp;
369 found = 0;
370 for (i = 1; i < ARRAY_SIZE(mfinfo); i++) {
371 if (mfinfo[i-1].func > mfinfo[i].func) {
372 tmp = mfinfo[i];
373 mfinfo[i] = mfinfo[i-1];
374 mfinfo[i-1] = tmp;
375 found = 1;
376 }
377 }
378 } while (found);
379 mips_frame_info_initialized = 1;
282 return 0; 380 return 0;
283} 381}
284 382
@@ -303,60 +401,39 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
303/* get_wchan - a maintenance nightmare^W^Wpain in the ass ... */ 401/* get_wchan - a maintenance nightmare^W^Wpain in the ass ... */
304unsigned long get_wchan(struct task_struct *p) 402unsigned long get_wchan(struct task_struct *p)
305{ 403{
404 unsigned long stack_page;
306 unsigned long frame, pc; 405 unsigned long frame, pc;
307 406
308 if (!p || p == current || p->state == TASK_RUNNING) 407 if (!p || p == current || p->state == TASK_RUNNING)
309 return 0; 408 return 0;
310 409
311 if (!mips_frame_info_initialized) 410 stack_page = (unsigned long)p->thread_info;
411 if (!stack_page || !mips_frame_info_initialized)
312 return 0; 412 return 0;
413
313 pc = thread_saved_pc(p); 414 pc = thread_saved_pc(p);
314 if (!in_sched_functions(pc)) 415 if (!in_sched_functions(pc))
315 goto out; 416 return pc;
316
317 if (pc >= (unsigned long) sleep_on_timeout)
318 goto schedule_timeout_caller;
319 if (pc >= (unsigned long) sleep_on)
320 goto schedule_caller;
321 if (pc >= (unsigned long) interruptible_sleep_on_timeout)
322 goto schedule_timeout_caller;
323 if (pc >= (unsigned long)interruptible_sleep_on)
324 goto schedule_caller;
325 if (pc >= (unsigned long)wait_for_completion)
326 goto schedule_caller;
327 goto schedule_timeout_caller;
328
329schedule_caller:
330 frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset];
331 if (pc >= (unsigned long) sleep_on)
332 pc = ((unsigned long *)frame)[sleep_on_frame.pc_offset];
333 else
334 pc = ((unsigned long *)frame)[wait_for_completion_frame.pc_offset];
335 goto out;
336 417
337schedule_timeout_caller:
338 /*
339 * The schedule_timeout frame
340 */
341 frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset]; 418 frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset];
419 do {
420 int i;
342 421
343 /* 422 if (frame < stack_page || frame > stack_page + THREAD_SIZE - 32)
344 * frame now points to sleep_on_timeout's frame 423 return 0;
345 */
346 pc = ((unsigned long *)frame)[schedule_timeout_frame.pc_offset];
347
348 if (in_sched_functions(pc)) {
349 /* schedule_timeout called by [interruptible_]sleep_on_timeout */
350 frame = ((unsigned long *)frame)[schedule_timeout_frame.frame_offset];
351 pc = ((unsigned long *)frame)[sleep_on_timeout_frame.pc_offset];
352 }
353 424
354out: 425 for (i = ARRAY_SIZE(mfinfo) - 1; i >= 0; i--) {
426 if (pc >= (unsigned long) mfinfo[i].func)
427 break;
428 }
429 if (i < 0)
430 break;
355 431
356#ifdef CONFIG_64BIT 432 if (mfinfo[i].omit_fp)
357 if (current->thread.mflags & MF_32BIT_REGS) /* Kludge for 32-bit ps */ 433 break;
358 pc &= 0xffffffffUL; 434 pc = ((unsigned long *)frame)[mfinfo[i].pc_offset];
359#endif 435 frame = ((unsigned long *)frame)[mfinfo[i].frame_offset];
436 } while (in_sched_functions(pc));
360 437
361 return pc; 438 return pc;
362} 439}
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 0b571a5b4b83..fcceab8f2e00 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -28,14 +28,18 @@
28#include <linux/security.h> 28#include <linux/security.h>
29#include <linux/signal.h> 29#include <linux/signal.h>
30 30
31#include <asm/byteorder.h>
31#include <asm/cpu.h> 32#include <asm/cpu.h>
33#include <asm/dsp.h>
32#include <asm/fpu.h> 34#include <asm/fpu.h>
33#include <asm/mipsregs.h> 35#include <asm/mipsregs.h>
36#include <asm/mipsmtregs.h>
34#include <asm/pgtable.h> 37#include <asm/pgtable.h>
35#include <asm/page.h> 38#include <asm/page.h>
36#include <asm/system.h> 39#include <asm/system.h>
37#include <asm/uaccess.h> 40#include <asm/uaccess.h>
38#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
42#include <asm/reg.h>
39 43
40/* 44/*
41 * Called by kernel/ptrace.c when detaching.. 45 * Called by kernel/ptrace.c when detaching..
@@ -47,6 +51,129 @@ void ptrace_disable(struct task_struct *child)
47 /* Nothing to do.. */ 51 /* Nothing to do.. */
48} 52}
49 53
54/*
55 * Read a general register set. We always use the 64-bit format, even
56 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
57 * Registers are sign extended to fill the available space.
58 */
59int ptrace_getregs (struct task_struct *child, __s64 __user *data)
60{
61 struct pt_regs *regs;
62 int i;
63
64 if (!access_ok(VERIFY_WRITE, data, 38 * 8))
65 return -EIO;
66
67 regs = (struct pt_regs *) ((unsigned long) child->thread_info +
68 THREAD_SIZE - 32 - sizeof(struct pt_regs));
69
70 for (i = 0; i < 32; i++)
71 __put_user (regs->regs[i], data + i);
72 __put_user (regs->lo, data + EF_LO - EF_R0);
73 __put_user (regs->hi, data + EF_HI - EF_R0);
74 __put_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
75 __put_user (regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
76 __put_user (regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
77 __put_user (regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
78
79 return 0;
80}
81
82/*
83 * Write a general register set. As for PTRACE_GETREGS, we always use
84 * the 64-bit format. On a 32-bit kernel only the lower order half
85 * (according to endianness) will be used.
86 */
87int ptrace_setregs (struct task_struct *child, __s64 __user *data)
88{
89 struct pt_regs *regs;
90 int i;
91
92 if (!access_ok(VERIFY_READ, data, 38 * 8))
93 return -EIO;
94
95 regs = (struct pt_regs *) ((unsigned long) child->thread_info +
96 THREAD_SIZE - 32 - sizeof(struct pt_regs));
97
98 for (i = 0; i < 32; i++)
99 __get_user (regs->regs[i], data + i);
100 __get_user (regs->lo, data + EF_LO - EF_R0);
101 __get_user (regs->hi, data + EF_HI - EF_R0);
102 __get_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
103
104 /* badvaddr, status, and cause may not be written. */
105
106 return 0;
107}
108
109int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
110{
111 int i;
112
113 if (!access_ok(VERIFY_WRITE, data, 33 * 8))
114 return -EIO;
115
116 if (tsk_used_math(child)) {
117 fpureg_t *fregs = get_fpu_regs(child);
118 for (i = 0; i < 32; i++)
119 __put_user (fregs[i], i + (__u64 __user *) data);
120 } else {
121 for (i = 0; i < 32; i++)
122 __put_user ((__u64) -1, i + (__u64 __user *) data);
123 }
124
125 if (cpu_has_fpu) {
126 unsigned int flags, tmp;
127
128 __put_user (child->thread.fpu.hard.fcr31, data + 64);
129
130 preempt_disable();
131 if (cpu_has_mipsmt) {
132 unsigned int vpflags = dvpe();
133 flags = read_c0_status();
134 __enable_fpu();
135 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
136 write_c0_status(flags);
137 evpe(vpflags);
138 } else {
139 flags = read_c0_status();
140 __enable_fpu();
141 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
142 write_c0_status(flags);
143 }
144 preempt_enable();
145 __put_user (tmp, data + 65);
146 } else {
147 __put_user (child->thread.fpu.soft.fcr31, data + 64);
148 __put_user ((__u32) 0, data + 65);
149 }
150
151 return 0;
152}
153
154int ptrace_setfpregs (struct task_struct *child, __u32 __user *data)
155{
156 fpureg_t *fregs;
157 int i;
158
159 if (!access_ok(VERIFY_READ, data, 33 * 8))
160 return -EIO;
161
162 fregs = get_fpu_regs(child);
163
164 for (i = 0; i < 32; i++)
165 __get_user (fregs[i], i + (__u64 __user *) data);
166
167 if (cpu_has_fpu)
168 __get_user (child->thread.fpu.hard.fcr31, data + 64);
169 else
170 __get_user (child->thread.fpu.soft.fcr31, data + 64);
171
172 /* FIR may not be written. */
173
174 return 0;
175}
176
50asmlinkage int sys_ptrace(long request, long pid, long addr, long data) 177asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
51{ 178{
52 struct task_struct *child; 179 struct task_struct *child;
@@ -103,7 +230,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
103 ret = -EIO; 230 ret = -EIO;
104 if (copied != sizeof(tmp)) 231 if (copied != sizeof(tmp))
105 break; 232 break;
106 ret = put_user(tmp,(unsigned long *) data); 233 ret = put_user(tmp,(unsigned long __user *) data);
107 break; 234 break;
108 } 235 }
109 236
@@ -169,18 +296,53 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
169 if (!cpu_has_fpu) 296 if (!cpu_has_fpu)
170 break; 297 break;
171 298
172 flags = read_c0_status(); 299 preempt_disable();
173 __enable_fpu(); 300 if (cpu_has_mipsmt) {
174 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 301 unsigned int vpflags = dvpe();
175 write_c0_status(flags); 302 flags = read_c0_status();
303 __enable_fpu();
304 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
305 write_c0_status(flags);
306 evpe(vpflags);
307 } else {
308 flags = read_c0_status();
309 __enable_fpu();
310 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
311 write_c0_status(flags);
312 }
313 preempt_enable();
314 break;
315 }
316 case DSP_BASE ... DSP_BASE + 5: {
317 dspreg_t *dregs;
318
319 if (!cpu_has_dsp) {
320 tmp = 0;
321 ret = -EIO;
322 goto out_tsk;
323 }
324 if (child->thread.dsp.used_dsp) {
325 dregs = __get_dsp_regs(child);
326 tmp = (unsigned long) (dregs[addr - DSP_BASE]);
327 } else {
328 tmp = -1; /* DSP registers yet used */
329 }
176 break; 330 break;
177 } 331 }
332 case DSP_CONTROL:
333 if (!cpu_has_dsp) {
334 tmp = 0;
335 ret = -EIO;
336 goto out_tsk;
337 }
338 tmp = child->thread.dsp.dspcontrol;
339 break;
178 default: 340 default:
179 tmp = 0; 341 tmp = 0;
180 ret = -EIO; 342 ret = -EIO;
181 goto out_tsk; 343 goto out_tsk;
182 } 344 }
183 ret = put_user(tmp, (unsigned long *) data); 345 ret = put_user(tmp, (unsigned long __user *) data);
184 break; 346 break;
185 } 347 }
186 348
@@ -247,6 +409,25 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
247 else 409 else
248 child->thread.fpu.soft.fcr31 = data; 410 child->thread.fpu.soft.fcr31 = data;
249 break; 411 break;
412 case DSP_BASE ... DSP_BASE + 5: {
413 dspreg_t *dregs;
414
415 if (!cpu_has_dsp) {
416 ret = -EIO;
417 break;
418 }
419
420 dregs = __get_dsp_regs(child);
421 dregs[addr - DSP_BASE] = data;
422 break;
423 }
424 case DSP_CONTROL:
425 if (!cpu_has_dsp) {
426 ret = -EIO;
427 break;
428 }
429 child->thread.dsp.dspcontrol = data;
430 break;
250 default: 431 default:
251 /* The rest are not allowed. */ 432 /* The rest are not allowed. */
252 ret = -EIO; 433 ret = -EIO;
@@ -255,6 +436,22 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
255 break; 436 break;
256 } 437 }
257 438
439 case PTRACE_GETREGS:
440 ret = ptrace_getregs (child, (__u64 __user *) data);
441 break;
442
443 case PTRACE_SETREGS:
444 ret = ptrace_setregs (child, (__u64 __user *) data);
445 break;
446
447 case PTRACE_GETFPREGS:
448 ret = ptrace_getfpregs (child, (__u32 __user *) data);
449 break;
450
451 case PTRACE_SETFPREGS:
452 ret = ptrace_setfpregs (child, (__u32 __user *) data);
453 break;
454
258 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ 455 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
259 case PTRACE_CONT: { /* restart after signal. */ 456 case PTRACE_CONT: { /* restart after signal. */
260 ret = -EIO; 457 ret = -EIO;
@@ -289,6 +486,11 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
289 ret = ptrace_detach(child, data); 486 ret = ptrace_detach(child, data);
290 break; 487 break;
291 488
489 case PTRACE_GET_THREAD_AREA:
490 ret = put_user(child->thread_info->tp_value,
491 (unsigned long __user *) data);
492 break;
493
292 default: 494 default:
293 ret = ptrace_request(child, request, addr, data); 495 ret = ptrace_request(child, request, addr, data);
294 break; 496 break;
@@ -303,21 +505,14 @@ out:
303 505
304static inline int audit_arch(void) 506static inline int audit_arch(void)
305{ 507{
306#ifdef CONFIG_CPU_LITTLE_ENDIAN 508 int arch = EM_MIPS;
307#ifdef CONFIG_64BIT
308 if (!(current->thread.mflags & MF_32BIT_REGS))
309 return AUDIT_ARCH_MIPSEL64;
310#endif /* MIPS64 */
311 return AUDIT_ARCH_MIPSEL;
312
313#else /* big endian... */
314#ifdef CONFIG_64BIT 509#ifdef CONFIG_64BIT
315 if (!(current->thread.mflags & MF_32BIT_REGS)) 510 arch |= __AUDIT_ARCH_64BIT;
316 return AUDIT_ARCH_MIPS64; 511#endif
317#endif /* MIPS64 */ 512#if defined(__LITTLE_ENDIAN)
318 return AUDIT_ARCH_MIPS; 513 arch |= __AUDIT_ARCH_LE;
319 514#endif
320#endif /* endian */ 515 return arch;
321} 516}
322 517
323/* 518/*
@@ -327,12 +522,13 @@ static inline int audit_arch(void)
327asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) 522asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
328{ 523{
329 if (unlikely(current->audit_context) && entryexit) 524 if (unlikely(current->audit_context) && entryexit)
330 audit_syscall_exit(current, AUDITSC_RESULT(regs->regs[2]), regs->regs[2]); 525 audit_syscall_exit(current, AUDITSC_RESULT(regs->regs[2]),
526 regs->regs[2]);
331 527
332 if (!test_thread_flag(TIF_SYSCALL_TRACE))
333 goto out;
334 if (!(current->ptrace & PT_PTRACED)) 528 if (!(current->ptrace & PT_PTRACED))
335 goto out; 529 goto out;
530 if (!test_thread_flag(TIF_SYSCALL_TRACE))
531 goto out;
336 532
337 /* The 0x80 provides a way for the tracing parent to distinguish 533 /* The 0x80 provides a way for the tracing parent to distinguish
338 between a syscall stop and SIGTRAP delivery */ 534 between a syscall stop and SIGTRAP delivery */
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index eee207969c21..9a9b04972132 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -24,17 +24,24 @@
24#include <linux/smp_lock.h> 24#include <linux/smp_lock.h>
25#include <linux/user.h> 25#include <linux/user.h>
26#include <linux/security.h> 26#include <linux/security.h>
27#include <linux/signal.h>
28 27
29#include <asm/cpu.h> 28#include <asm/cpu.h>
29#include <asm/dsp.h>
30#include <asm/fpu.h> 30#include <asm/fpu.h>
31#include <asm/mipsregs.h> 31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/page.h> 34#include <asm/page.h>
34#include <asm/system.h> 35#include <asm/system.h>
35#include <asm/uaccess.h> 36#include <asm/uaccess.h>
36#include <asm/bootinfo.h> 37#include <asm/bootinfo.h>
37 38
39int ptrace_getregs (struct task_struct *child, __s64 __user *data);
40int ptrace_setregs (struct task_struct *child, __s64 __user *data);
41
42int ptrace_getfpregs (struct task_struct *child, __u32 __user *data);
43int ptrace_setfpregs (struct task_struct *child, __u32 __user *data);
44
38/* 45/*
39 * Tracing a 32-bit process with a 64-bit strace and vice versa will not 46 * Tracing a 32-bit process with a 64-bit strace and vice versa will not
40 * work. I don't know how to fix this. 47 * work. I don't know how to fix this.
@@ -99,6 +106,35 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
99 break; 106 break;
100 } 107 }
101 108
109 /*
110 * Read 4 bytes of the other process' storage
111 * data is a pointer specifying where the user wants the
112 * 4 bytes copied into
113 * addr is a pointer in the user's storage that contains an 8 byte
114 * address in the other process of the 4 bytes that is to be read
115 * (this is run in a 32-bit process looking at a 64-bit process)
116 * when I and D space are separate, these will need to be fixed.
117 */
118 case PTRACE_PEEKTEXT_3264:
119 case PTRACE_PEEKDATA_3264: {
120 u32 tmp;
121 int copied;
122 u32 __user * addrOthers;
123
124 ret = -EIO;
125
126 /* Get the addr in the other process that we want to read */
127 if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
128 break;
129
130 copied = access_process_vm(child, (u64)addrOthers, &tmp,
131 sizeof(tmp), 0);
132 if (copied != sizeof(tmp))
133 break;
134 ret = put_user(tmp, (u32 __user *) (unsigned long) data);
135 break;
136 }
137
102 /* Read the word at location addr in the USER area. */ 138 /* Read the word at location addr in the USER area. */
103 case PTRACE_PEEKUSR: { 139 case PTRACE_PEEKUSR: {
104 struct pt_regs *regs; 140 struct pt_regs *regs;
@@ -156,12 +192,44 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
156 if (!cpu_has_fpu) 192 if (!cpu_has_fpu)
157 break; 193 break;
158 194
159 flags = read_c0_status(); 195 preempt_disable();
160 __enable_fpu(); 196 if (cpu_has_mipsmt) {
161 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 197 unsigned int vpflags = dvpe();
162 write_c0_status(flags); 198 flags = read_c0_status();
199 __enable_fpu();
200 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
201 write_c0_status(flags);
202 evpe(vpflags);
203 } else {
204 flags = read_c0_status();
205 __enable_fpu();
206 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
207 write_c0_status(flags);
208 }
209 preempt_enable();
163 break; 210 break;
164 } 211 }
212 case DSP_BASE ... DSP_BASE + 5:
213 if (!cpu_has_dsp) {
214 tmp = 0;
215 ret = -EIO;
216 goto out_tsk;
217 }
218 if (child->thread.dsp.used_dsp) {
219 dspreg_t *dregs = __get_dsp_regs(child);
220 tmp = (unsigned long) (dregs[addr - DSP_BASE]);
221 } else {
222 tmp = -1; /* DSP registers yet used */
223 }
224 break;
225 case DSP_CONTROL:
226 if (!cpu_has_dsp) {
227 tmp = 0;
228 ret = -EIO;
229 goto out_tsk;
230 }
231 tmp = child->thread.dsp.dspcontrol;
232 break;
165 default: 233 default:
166 tmp = 0; 234 tmp = 0;
167 ret = -EIO; 235 ret = -EIO;
@@ -181,6 +249,31 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
181 ret = -EIO; 249 ret = -EIO;
182 break; 250 break;
183 251
252 /*
253 * Write 4 bytes into the other process' storage
254 * data is the 4 bytes that the user wants written
255 * addr is a pointer in the user's storage that contains an
256 * 8 byte address in the other process where the 4 bytes
257 * that is to be written
258 * (this is run in a 32-bit process looking at a 64-bit process)
259 * when I and D space are separate, these will need to be fixed.
260 */
261 case PTRACE_POKETEXT_3264:
262 case PTRACE_POKEDATA_3264: {
263 u32 __user * addrOthers;
264
265 /* Get the addr in the other process that we want to write into */
266 ret = -EIO;
267 if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
268 break;
269 ret = 0;
270 if (access_process_vm(child, (u64)addrOthers, &data,
271 sizeof(data), 1) == sizeof(data))
272 break;
273 ret = -EIO;
274 break;
275 }
276
184 case PTRACE_POKEUSR: { 277 case PTRACE_POKEUSR: {
185 struct pt_regs *regs; 278 struct pt_regs *regs;
186 ret = 0; 279 ret = 0;
@@ -231,6 +324,22 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
231 else 324 else
232 child->thread.fpu.soft.fcr31 = data; 325 child->thread.fpu.soft.fcr31 = data;
233 break; 326 break;
327 case DSP_BASE ... DSP_BASE + 5:
328 if (!cpu_has_dsp) {
329 ret = -EIO;
330 break;
331 }
332
333 dspreg_t *dregs = __get_dsp_regs(child);
334 dregs[addr - DSP_BASE] = data;
335 break;
336 case DSP_CONTROL:
337 if (!cpu_has_dsp) {
338 ret = -EIO;
339 break;
340 }
341 child->thread.dsp.dspcontrol = data;
342 break;
234 default: 343 default:
235 /* The rest are not allowed. */ 344 /* The rest are not allowed. */
236 ret = -EIO; 345 ret = -EIO;
@@ -239,6 +348,22 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
239 break; 348 break;
240 } 349 }
241 350
351 case PTRACE_GETREGS:
352 ret = ptrace_getregs (child, (__u64 __user *) (__u64) data);
353 break;
354
355 case PTRACE_SETREGS:
356 ret = ptrace_setregs (child, (__u64 __user *) (__u64) data);
357 break;
358
359 case PTRACE_GETFPREGS:
360 ret = ptrace_getfpregs (child, (__u32 __user *) (__u64) data);
361 break;
362
363 case PTRACE_SETFPREGS:
364 ret = ptrace_setfpregs (child, (__u32 __user *) (__u64) data);
365 break;
366
242 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ 367 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
243 case PTRACE_CONT: { /* restart after signal. */ 368 case PTRACE_CONT: { /* restart after signal. */
244 ret = -EIO; 369 ret = -EIO;
@@ -269,10 +394,25 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
269 wake_up_process(child); 394 wake_up_process(child);
270 break; 395 break;
271 396
397 case PTRACE_GET_THREAD_AREA:
398 ret = put_user(child->thread_info->tp_value,
399 (unsigned int __user *) (unsigned long) data);
400 break;
401
272 case PTRACE_DETACH: /* detach a process that was attached. */ 402 case PTRACE_DETACH: /* detach a process that was attached. */
273 ret = ptrace_detach(child, data); 403 ret = ptrace_detach(child, data);
274 break; 404 break;
275 405
406 case PTRACE_GETEVENTMSG:
407 ret = put_user(child->ptrace_message,
408 (unsigned int __user *) (unsigned long) data);
409 break;
410
411 case PTRACE_GET_THREAD_AREA_3264:
412 ret = put_user(child->thread_info->tp_value,
413 (unsigned long __user *) (unsigned long) data);
414 break;
415
276 default: 416 default:
277 ret = ptrace_request(child, request, addr, data); 417 ret = ptrace_request(child, request, addr, data);
278 break; 418 break;
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 1a14c6b18829..283a98508fc8 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -32,7 +32,7 @@
32 32
33 .set noreorder 33 .set noreorder
34 .set mips3 34 .set mips3
35 /* Save floating point context */ 35
36LEAF(_save_fp_context) 36LEAF(_save_fp_context)
37 cfc1 t1, fcr31 37 cfc1 t1, fcr31
38 38
@@ -74,9 +74,6 @@ LEAF(_save_fp_context)
74 EX sdc1 $f28, SC_FPREGS+224(a0) 74 EX sdc1 $f28, SC_FPREGS+224(a0)
75 EX sdc1 $f30, SC_FPREGS+240(a0) 75 EX sdc1 $f30, SC_FPREGS+240(a0)
76 EX sw t1, SC_FPC_CSR(a0) 76 EX sw t1, SC_FPC_CSR(a0)
77 cfc1 t0, $0 # implementation/version
78 EX sw t0, SC_FPC_EIR(a0)
79
80 jr ra 77 jr ra
81 li v0, 0 # success 78 li v0, 0 # success
82 END(_save_fp_context) 79 END(_save_fp_context)
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
new file mode 100644
index 000000000000..8c81f3cb4e2d
--- /dev/null
+++ b/arch/mips/kernel/rtlx.c
@@ -0,0 +1,341 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/fs.h>
22#include <linux/init.h>
23#include <asm/uaccess.h>
24#include <linux/slab.h>
25#include <linux/list.h>
26#include <linux/vmalloc.h>
27#include <linux/elf.h>
28#include <linux/seq_file.h>
29#include <linux/syscalls.h>
30#include <linux/moduleloader.h>
31#include <linux/interrupt.h>
32#include <linux/poll.h>
33#include <linux/sched.h>
34#include <linux/wait.h>
35#include <asm/mipsmtregs.h>
36#include <asm/cacheflush.h>
37#include <asm/atomic.h>
38#include <asm/cpu.h>
39#include <asm/processor.h>
40#include <asm/system.h>
41#include <asm/rtlx.h>
42
43#define RTLX_MAJOR 64
44#define RTLX_TARG_VPE 1
45
46struct rtlx_info *rtlx;
47static int major;
48static char module_name[] = "rtlx";
49static inline int spacefree(int read, int write, int size);
50
51static struct chan_waitqueues {
52 wait_queue_head_t rt_queue;
53 wait_queue_head_t lx_queue;
54} channel_wqs[RTLX_CHANNELS];
55
56static struct irqaction irq;
57static int irq_num;
58
59extern void *vpe_get_shared(int index);
60
61static void rtlx_dispatch(struct pt_regs *regs)
62{
63 do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ, regs);
64}
65
66irqreturn_t rtlx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
67{
68 irqreturn_t r = IRQ_HANDLED;
69 int i;
70
71 for (i = 0; i < RTLX_CHANNELS; i++) {
72 struct rtlx_channel *chan = &rtlx->channel[i];
73
74 if (chan->lx_read != chan->lx_write)
75 wake_up_interruptible(&channel_wqs[i].lx_queue);
76 }
77
78 return r;
79}
80
81void dump_rtlx(void)
82{
83 int i;
84
85 printk("id 0x%lx state %d\n", rtlx->id, rtlx->state);
86
87 for (i = 0; i < RTLX_CHANNELS; i++) {
88 struct rtlx_channel *chan = &rtlx->channel[i];
89
90 printk(" rt_state %d lx_state %d buffer_size %d\n",
91 chan->rt_state, chan->lx_state, chan->buffer_size);
92
93 printk(" rt_read %d rt_write %d\n",
94 chan->rt_read, chan->rt_write);
95
96 printk(" lx_read %d lx_write %d\n",
97 chan->lx_read, chan->lx_write);
98
99 printk(" rt_buffer <%s>\n", chan->rt_buffer);
100 printk(" lx_buffer <%s>\n", chan->lx_buffer);
101 }
102}
103
104/* call when we have the address of the shared structure from the SP side. */
105static int rtlx_init(struct rtlx_info *rtlxi)
106{
107 int i;
108
109 if (rtlxi->id != RTLX_ID) {
110 printk(KERN_WARNING "no valid RTLX id at 0x%p\n", rtlxi);
111 return (-ENOEXEC);
112 }
113
114 /* initialise the wait queues */
115 for (i = 0; i < RTLX_CHANNELS; i++) {
116 init_waitqueue_head(&channel_wqs[i].rt_queue);
117 init_waitqueue_head(&channel_wqs[i].lx_queue);
118 }
119
120 /* set up for interrupt handling */
121 memset(&irq, 0, sizeof(struct irqaction));
122
123 if (cpu_has_vint) {
124 set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch);
125 }
126
127 irq_num = MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ;
128 irq.handler = rtlx_interrupt;
129 irq.flags = SA_INTERRUPT;
130 irq.name = "RTLX";
131 irq.dev_id = rtlx;
132 setup_irq(irq_num, &irq);
133
134 rtlx = rtlxi;
135 return (0);
136}
137
138/* only allow one open process at a time to open each channel */
139static int rtlx_open(struct inode *inode, struct file *filp)
140{
141 int minor, ret;
142 struct rtlx_channel *chan;
143
144 /* assume only 1 device at the mo. */
145 minor = MINOR(inode->i_rdev);
146
147 if (rtlx == NULL) {
148 struct rtlx_info **p;
149 if( (p = vpe_get_shared(RTLX_TARG_VPE)) == NULL) {
150 printk(" vpe_get_shared is NULL. Has an SP program been loaded?\n");
151 return (-EFAULT);
152 }
153
154 if (*p == NULL) {
155 printk(" vpe_shared %p %p\n", p, *p);
156 return (-EFAULT);
157 }
158
159 if ((ret = rtlx_init(*p)) < 0)
160 return (ret);
161 }
162
163 chan = &rtlx->channel[minor];
164
165 /* already open? */
166 if (chan->lx_state == RTLX_STATE_OPENED)
167 return (-EBUSY);
168
169 chan->lx_state = RTLX_STATE_OPENED;
170 return (0);
171}
172
173static int rtlx_release(struct inode *inode, struct file *filp)
174{
175 int minor;
176
177 minor = MINOR(inode->i_rdev);
178 rtlx->channel[minor].lx_state = RTLX_STATE_UNUSED;
179 return (0);
180}
181
182static unsigned int rtlx_poll(struct file *file, poll_table * wait)
183{
184 int minor;
185 unsigned int mask = 0;
186 struct rtlx_channel *chan;
187
188 minor = MINOR(file->f_dentry->d_inode->i_rdev);
189 chan = &rtlx->channel[minor];
190
191 poll_wait(file, &channel_wqs[minor].rt_queue, wait);
192 poll_wait(file, &channel_wqs[minor].lx_queue, wait);
193
194 /* data available to read? */
195 if (chan->lx_read != chan->lx_write)
196 mask |= POLLIN | POLLRDNORM;
197
198 /* space to write */
199 if (spacefree(chan->rt_read, chan->rt_write, chan->buffer_size))
200 mask |= POLLOUT | POLLWRNORM;
201
202 return (mask);
203}
204
205static ssize_t rtlx_read(struct file *file, char __user * buffer, size_t count,
206 loff_t * ppos)
207{
208 size_t fl = 0L;
209 int minor;
210 struct rtlx_channel *lx;
211 DECLARE_WAITQUEUE(wait, current);
212
213 minor = MINOR(file->f_dentry->d_inode->i_rdev);
214 lx = &rtlx->channel[minor];
215
216 /* data available? */
217 if (lx->lx_write == lx->lx_read) {
218 if (file->f_flags & O_NONBLOCK)
219 return (0); // -EAGAIN makes cat whinge
220
221 /* go to sleep */
222 add_wait_queue(&channel_wqs[minor].lx_queue, &wait);
223 set_current_state(TASK_INTERRUPTIBLE);
224
225 while (lx->lx_write == lx->lx_read)
226 schedule();
227
228 set_current_state(TASK_RUNNING);
229 remove_wait_queue(&channel_wqs[minor].lx_queue, &wait);
230
231 /* back running */
232 }
233
234 /* find out how much in total */
235 count = min( count,
236 (size_t)(lx->lx_write + lx->buffer_size - lx->lx_read) % lx->buffer_size);
237
238 /* then how much from the read pointer onwards */
239 fl = min( count, (size_t)lx->buffer_size - lx->lx_read);
240
241 copy_to_user (buffer, &lx->lx_buffer[lx->lx_read], fl);
242
243 /* and if there is anything left at the beginning of the buffer */
244 if ( count - fl )
245 copy_to_user (buffer + fl, lx->lx_buffer, count - fl);
246
247 /* update the index */
248 lx->lx_read += count;
249 lx->lx_read %= lx->buffer_size;
250
251 return (count);
252}
253
254static inline int spacefree(int read, int write, int size)
255{
256 if (read == write) {
257 /* never fill the buffer completely, so indexes are always equal if empty
258 and only empty, or !equal if data available */
259 return (size - 1);
260 }
261
262 return ((read + size - write) % size) - 1;
263}
264
265static ssize_t rtlx_write(struct file *file, const char __user * buffer,
266 size_t count, loff_t * ppos)
267{
268 int minor;
269 struct rtlx_channel *rt;
270 size_t fl;
271 DECLARE_WAITQUEUE(wait, current);
272
273 minor = MINOR(file->f_dentry->d_inode->i_rdev);
274 rt = &rtlx->channel[minor];
275
276 /* any space left... */
277 if (!spacefree(rt->rt_read, rt->rt_write, rt->buffer_size)) {
278
279 if (file->f_flags & O_NONBLOCK)
280 return (-EAGAIN);
281
282 add_wait_queue(&channel_wqs[minor].rt_queue, &wait);
283 set_current_state(TASK_INTERRUPTIBLE);
284
285 while (!spacefree(rt->rt_read, rt->rt_write, rt->buffer_size))
286 schedule();
287
288 set_current_state(TASK_RUNNING);
289 remove_wait_queue(&channel_wqs[minor].rt_queue, &wait);
290 }
291
292 /* total number of bytes to copy */
293 count = min( count, (size_t)spacefree(rt->rt_read, rt->rt_write, rt->buffer_size) );
294
295 /* first bit from write pointer to the end of the buffer, or count */
296 fl = min(count, (size_t) rt->buffer_size - rt->rt_write);
297
298 copy_from_user(&rt->rt_buffer[rt->rt_write], buffer, fl);
299
300 /* if there's any left copy to the beginning of the buffer */
301 if( count - fl )
302 copy_from_user(rt->rt_buffer, buffer + fl, count - fl);
303
304 rt->rt_write += count;
305 rt->rt_write %= rt->buffer_size;
306
307 return(count);
308}
309
310static struct file_operations rtlx_fops = {
311 .owner = THIS_MODULE,
312 .open = rtlx_open,
313 .release = rtlx_release,
314 .write = rtlx_write,
315 .read = rtlx_read,
316 .poll = rtlx_poll
317};
318
319static int rtlx_module_init(void)
320{
321 if ((major = register_chrdev(RTLX_MAJOR, module_name, &rtlx_fops)) < 0) {
322 printk("rtlx_module_init: unable to register device\n");
323 return (-EBUSY);
324 }
325
326 if (major == 0)
327 major = RTLX_MAJOR;
328
329 return (0);
330}
331
332static void rtlx_module_exit(void)
333{
334 unregister_chrdev(major, module_name);
335}
336
337module_init(rtlx_module_init);
338module_exit(rtlx_module_exit);
339MODULE_DESCRIPTION("MIPS RTLX");
340MODULE_AUTHOR("Elizabeth Clarke, MIPS Technologies, Inc");
341MODULE_LICENSE("GPL");
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 17b5030fb6ea..4dd8e8b4fbc2 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -578,7 +578,7 @@ einval: li v0, -EINVAL
578 sys sys_fremovexattr 2 /* 4235 */ 578 sys sys_fremovexattr 2 /* 4235 */
579 sys sys_tkill 2 579 sys sys_tkill 2
580 sys sys_sendfile64 5 580 sys sys_sendfile64 5
581 sys sys_futex 2 581 sys sys_futex 6
582 sys sys_sched_setaffinity 3 582 sys sys_sched_setaffinity 3
583 sys sys_sched_getaffinity 3 /* 4240 */ 583 sys sys_sched_getaffinity 3 /* 4240 */
584 sys sys_io_setup 2 584 sys sys_io_setup 2
@@ -587,7 +587,7 @@ einval: li v0, -EINVAL
587 sys sys_io_submit 3 587 sys sys_io_submit 3
588 sys sys_io_cancel 3 /* 4245 */ 588 sys sys_io_cancel 3 /* 4245 */
589 sys sys_exit_group 1 589 sys sys_exit_group 1
590 sys sys_lookup_dcookie 3 590 sys sys_lookup_dcookie 4
591 sys sys_epoll_create 1 591 sys sys_epoll_create 1
592 sys sys_epoll_ctl 4 592 sys sys_epoll_ctl 4
593 sys sys_epoll_wait 3 /* 4250 */ 593 sys sys_epoll_wait 3 /* 4250 */
@@ -618,12 +618,15 @@ einval: li v0, -EINVAL
618 sys sys_mq_notify 2 /* 4275 */ 618 sys sys_mq_notify 2 /* 4275 */
619 sys sys_mq_getsetattr 3 619 sys sys_mq_getsetattr 3
620 sys sys_ni_syscall 0 /* sys_vserver */ 620 sys sys_ni_syscall 0 /* sys_vserver */
621 sys sys_waitid 4 621 sys sys_waitid 5
622 sys sys_ni_syscall 0 /* available, was setaltroot */ 622 sys sys_ni_syscall 0 /* available, was setaltroot */
623 sys sys_add_key 5 623 sys sys_add_key 5 /* 4280 */
624 sys sys_request_key 4 624 sys sys_request_key 4
625 sys sys_keyctl 5 625 sys sys_keyctl 5
626 626 sys sys_set_thread_area 1
627 sys sys_inotify_init 0
628 sys sys_inotify_add_watch 3 /* 4285 */
629 sys sys_inotify_rm_watch 2
627 .endm 630 .endm
628 631
629 /* We pre-compute the number of _instruction_ bytes needed to 632 /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index ffb22a2068bf..9085838d6ce3 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -449,3 +449,7 @@ sys_call_table:
449 PTR sys_add_key 449 PTR sys_add_key
450 PTR sys_request_key /* 5240 */ 450 PTR sys_request_key /* 5240 */
451 PTR sys_keyctl 451 PTR sys_keyctl
452 PTR sys_set_thread_area
453 PTR sys_inotify_init
454 PTR sys_inotify_add_watch
455 PTR sys_inotify_rm_watch /* 5245 */
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index e52049c87bc3..7e66eb823bf6 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -176,7 +176,7 @@ EXPORT(sysn32_call_table)
176 PTR sys_fork 176 PTR sys_fork
177 PTR sys32_execve 177 PTR sys32_execve
178 PTR sys_exit 178 PTR sys_exit
179 PTR sys32_wait4 179 PTR compat_sys_wait4
180 PTR sys_kill /* 6060 */ 180 PTR sys_kill /* 6060 */
181 PTR sys32_newuname 181 PTR sys32_newuname
182 PTR sys_semget 182 PTR sys_semget
@@ -216,7 +216,7 @@ EXPORT(sysn32_call_table)
216 PTR compat_sys_getrusage 216 PTR compat_sys_getrusage
217 PTR sys32_sysinfo 217 PTR sys32_sysinfo
218 PTR compat_sys_times 218 PTR compat_sys_times
219 PTR sys_ptrace 219 PTR sys32_ptrace
220 PTR sys_getuid /* 6100 */ 220 PTR sys_getuid /* 6100 */
221 PTR sys_syslog 221 PTR sys_syslog
222 PTR sys_getgid 222 PTR sys_getgid
@@ -243,14 +243,14 @@ EXPORT(sysn32_call_table)
243 PTR sys_capget 243 PTR sys_capget
244 PTR sys_capset 244 PTR sys_capset
245 PTR sys32_rt_sigpending /* 6125 */ 245 PTR sys32_rt_sigpending /* 6125 */
246 PTR compat_sys_rt_sigtimedwait 246 PTR sysn32_rt_sigtimedwait
247 PTR sys32_rt_sigqueueinfo 247 PTR sys_rt_sigqueueinfo
248 PTR sys32_rt_sigsuspend 248 PTR sys32_rt_sigsuspend
249 PTR sys32_sigaltstack 249 PTR sys32_sigaltstack
250 PTR compat_sys_utime /* 6130 */ 250 PTR compat_sys_utime /* 6130 */
251 PTR sys_mknod 251 PTR sys_mknod
252 PTR sys32_personality 252 PTR sys32_personality
253 PTR sys_ustat 253 PTR sys32_ustat
254 PTR compat_sys_statfs 254 PTR compat_sys_statfs
255 PTR compat_sys_fstatfs /* 6135 */ 255 PTR compat_sys_fstatfs /* 6135 */
256 PTR sys_sysfs 256 PTR sys_sysfs
@@ -329,7 +329,7 @@ EXPORT(sysn32_call_table)
329 PTR sys_epoll_wait 329 PTR sys_epoll_wait
330 PTR sys_remap_file_pages /* 6210 */ 330 PTR sys_remap_file_pages /* 6210 */
331 PTR sysn32_rt_sigreturn 331 PTR sysn32_rt_sigreturn
332 PTR sys_fcntl 332 PTR compat_sys_fcntl64
333 PTR sys_set_tid_address 333 PTR sys_set_tid_address
334 PTR sys_restart_syscall 334 PTR sys_restart_syscall
335 PTR sys_semtimedop /* 6215 */ 335 PTR sys_semtimedop /* 6215 */
@@ -337,15 +337,15 @@ EXPORT(sysn32_call_table)
337 PTR compat_sys_statfs64 337 PTR compat_sys_statfs64
338 PTR compat_sys_fstatfs64 338 PTR compat_sys_fstatfs64
339 PTR sys_sendfile64 339 PTR sys_sendfile64
340 PTR sys_timer_create /* 6220 */ 340 PTR sys32_timer_create /* 6220 */
341 PTR sys_timer_settime 341 PTR compat_sys_timer_settime
342 PTR sys_timer_gettime 342 PTR compat_sys_timer_gettime
343 PTR sys_timer_getoverrun 343 PTR sys_timer_getoverrun
344 PTR sys_timer_delete 344 PTR sys_timer_delete
345 PTR sys_clock_settime /* 6225 */ 345 PTR compat_sys_clock_settime /* 6225 */
346 PTR sys_clock_gettime 346 PTR compat_sys_clock_gettime
347 PTR sys_clock_getres 347 PTR compat_sys_clock_getres
348 PTR sys_clock_nanosleep 348 PTR compat_sys_clock_nanosleep
349 PTR sys_tgkill 349 PTR sys_tgkill
350 PTR compat_sys_utimes /* 6230 */ 350 PTR compat_sys_utimes /* 6230 */
351 PTR sys_ni_syscall /* sys_mbind */ 351 PTR sys_ni_syscall /* sys_mbind */
@@ -358,8 +358,12 @@ EXPORT(sysn32_call_table)
358 PTR compat_sys_mq_notify 358 PTR compat_sys_mq_notify
359 PTR compat_sys_mq_getsetattr 359 PTR compat_sys_mq_getsetattr
360 PTR sys_ni_syscall /* 6240, sys_vserver */ 360 PTR sys_ni_syscall /* 6240, sys_vserver */
361 PTR sys_waitid 361 PTR sysn32_waitid
362 PTR sys_ni_syscall /* available, was setaltroot */ 362 PTR sys_ni_syscall /* available, was setaltroot */
363 PTR sys_add_key 363 PTR sys_add_key
364 PTR sys_request_key 364 PTR sys_request_key
365 PTR sys_keyctl /* 6245 */ 365 PTR sys_keyctl /* 6245 */
366 PTR sys_set_thread_area
367 PTR sys_inotify_init
368 PTR sys_inotify_add_watch
369 PTR sys_inotify_rm_watch
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 739f3998d76b..5a16401e443a 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -316,13 +316,13 @@ sys_call_table:
316 PTR sys_vhangup 316 PTR sys_vhangup
317 PTR sys_ni_syscall /* was sys_idle */ 317 PTR sys_ni_syscall /* was sys_idle */
318 PTR sys_ni_syscall /* sys_vm86 */ 318 PTR sys_ni_syscall /* sys_vm86 */
319 PTR sys32_wait4 319 PTR compat_sys_wait4
320 PTR sys_swapoff /* 4115 */ 320 PTR sys_swapoff /* 4115 */
321 PTR sys32_sysinfo 321 PTR sys32_sysinfo
322 PTR sys32_ipc 322 PTR sys32_ipc
323 PTR sys_fsync 323 PTR sys_fsync
324 PTR sys32_sigreturn 324 PTR sys32_sigreturn
325 PTR sys_clone /* 4120 */ 325 PTR sys32_clone /* 4120 */
326 PTR sys_setdomainname 326 PTR sys_setdomainname
327 PTR sys32_newuname 327 PTR sys32_newuname
328 PTR sys_ni_syscall /* sys_modify_ldt */ 328 PTR sys_ni_syscall /* sys_modify_ldt */
@@ -391,7 +391,7 @@ sys_call_table:
391 PTR sys_getresuid 391 PTR sys_getresuid
392 PTR sys_ni_syscall /* was query_module */ 392 PTR sys_ni_syscall /* was query_module */
393 PTR sys_poll 393 PTR sys_poll
394 PTR sys_nfsservctl 394 PTR compat_sys_nfsservctl
395 PTR sys_setresgid /* 4190 */ 395 PTR sys_setresgid /* 4190 */
396 PTR sys_getresgid 396 PTR sys_getresgid
397 PTR sys_prctl 397 PTR sys_prctl
@@ -459,7 +459,7 @@ sys_call_table:
459 PTR sys_fadvise64_64 459 PTR sys_fadvise64_64
460 PTR compat_sys_statfs64 /* 4255 */ 460 PTR compat_sys_statfs64 /* 4255 */
461 PTR compat_sys_fstatfs64 461 PTR compat_sys_fstatfs64
462 PTR sys_timer_create 462 PTR sys32_timer_create
463 PTR compat_sys_timer_settime 463 PTR compat_sys_timer_settime
464 PTR compat_sys_timer_gettime 464 PTR compat_sys_timer_gettime
465 PTR sys_timer_getoverrun /* 4260 */ 465 PTR sys_timer_getoverrun /* 4260 */
@@ -480,9 +480,13 @@ sys_call_table:
480 PTR compat_sys_mq_notify /* 4275 */ 480 PTR compat_sys_mq_notify /* 4275 */
481 PTR compat_sys_mq_getsetattr 481 PTR compat_sys_mq_getsetattr
482 PTR sys_ni_syscall /* sys_vserver */ 482 PTR sys_ni_syscall /* sys_vserver */
483 PTR sys_waitid 483 PTR sys32_waitid
484 PTR sys_ni_syscall /* available, was setaltroot */ 484 PTR sys_ni_syscall /* available, was setaltroot */
485 PTR sys_add_key /* 4280 */ 485 PTR sys_add_key /* 4280 */
486 PTR sys_request_key 486 PTR sys_request_key
487 PTR sys_keyctl 487 PTR sys_keyctl
488 PTR sys_set_thread_area
489 PTR sys_inotify_init
490 PTR sys_inotify_add_watch /* 4285 */
491 PTR sys_inotify_rm_watch
488 .size sys_call_table,.-sys_call_table 492 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/semaphore.c b/arch/mips/kernel/semaphore.c
index 9c40fe5a8e8d..1265358cdca1 100644
--- a/arch/mips/kernel/semaphore.c
+++ b/arch/mips/kernel/semaphore.c
@@ -42,24 +42,28 @@ static inline int __sem_update_count(struct semaphore *sem, int incr)
42 42
43 if (cpu_has_llsc && R10000_LLSC_WAR) { 43 if (cpu_has_llsc && R10000_LLSC_WAR) {
44 __asm__ __volatile__( 44 __asm__ __volatile__(
45 "1: ll %0, %2 \n" 45 " .set mips3 \n"
46 "1: ll %0, %2 # __sem_update_count \n"
46 " sra %1, %0, 31 \n" 47 " sra %1, %0, 31 \n"
47 " not %1 \n" 48 " not %1 \n"
48 " and %1, %0, %1 \n" 49 " and %1, %0, %1 \n"
49 " add %1, %1, %3 \n" 50 " addu %1, %1, %3 \n"
50 " sc %1, %2 \n" 51 " sc %1, %2 \n"
51 " beqzl %1, 1b \n" 52 " beqzl %1, 1b \n"
53 " .set mips0 \n"
52 : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) 54 : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count)
53 : "r" (incr), "m" (sem->count)); 55 : "r" (incr), "m" (sem->count));
54 } else if (cpu_has_llsc) { 56 } else if (cpu_has_llsc) {
55 __asm__ __volatile__( 57 __asm__ __volatile__(
56 "1: ll %0, %2 \n" 58 " .set mips3 \n"
59 "1: ll %0, %2 # __sem_update_count \n"
57 " sra %1, %0, 31 \n" 60 " sra %1, %0, 31 \n"
58 " not %1 \n" 61 " not %1 \n"
59 " and %1, %0, %1 \n" 62 " and %1, %0, %1 \n"
60 " add %1, %1, %3 \n" 63 " addu %1, %1, %3 \n"
61 " sc %1, %2 \n" 64 " sc %1, %2 \n"
62 " beqz %1, 1b \n" 65 " beqz %1, 1b \n"
66 " .set mips0 \n"
63 : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) 67 : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count)
64 : "r" (incr), "m" (sem->count)); 68 : "r" (incr), "m" (sem->count));
65 } else { 69 } else {
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 12b531c295c4..d86affa21278 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -37,12 +37,13 @@
37 37
38#include <asm/addrspace.h> 38#include <asm/addrspace.h>
39#include <asm/bootinfo.h> 39#include <asm/bootinfo.h>
40#include <asm/cache.h>
40#include <asm/cpu.h> 41#include <asm/cpu.h>
41#include <asm/sections.h> 42#include <asm/sections.h>
42#include <asm/setup.h> 43#include <asm/setup.h>
43#include <asm/system.h> 44#include <asm/system.h>
44 45
45struct cpuinfo_mips cpu_data[NR_CPUS]; 46struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly;
46 47
47EXPORT_SYMBOL(cpu_data); 48EXPORT_SYMBOL(cpu_data);
48 49
@@ -62,8 +63,8 @@ EXPORT_SYMBOL(PCI_DMA_BUS_IS_PHYS);
62 * 63 *
63 * These are initialized so they are in the .data section 64 * These are initialized so they are in the .data section
64 */ 65 */
65unsigned long mips_machtype = MACH_UNKNOWN; 66unsigned long mips_machtype __read_mostly = MACH_UNKNOWN;
66unsigned long mips_machgroup = MACH_GROUP_UNKNOWN; 67unsigned long mips_machgroup __read_mostly = MACH_GROUP_UNKNOWN;
67 68
68EXPORT_SYMBOL(mips_machtype); 69EXPORT_SYMBOL(mips_machtype);
69EXPORT_SYMBOL(mips_machgroup); 70EXPORT_SYMBOL(mips_machgroup);
@@ -77,7 +78,7 @@ static char command_line[CL_SIZE];
77 * mips_io_port_base is the begin of the address space to which x86 style 78 * mips_io_port_base is the begin of the address space to which x86 style
78 * I/O ports are mapped. 79 * I/O ports are mapped.
79 */ 80 */
80const unsigned long mips_io_port_base = -1; 81const unsigned long mips_io_port_base __read_mostly = -1;
81EXPORT_SYMBOL(mips_io_port_base); 82EXPORT_SYMBOL(mips_io_port_base);
82 83
83/* 84/*
@@ -510,31 +511,7 @@ static inline void resource_init(void)
510#undef MAXMEM 511#undef MAXMEM
511#undef MAXMEM_PFN 512#undef MAXMEM_PFN
512 513
513static int __initdata earlyinit_debug; 514extern void plat_setup(void);
514
515static int __init earlyinit_debug_setup(char *str)
516{
517 earlyinit_debug = 1;
518 return 1;
519}
520__setup("earlyinit_debug", earlyinit_debug_setup);
521
522extern initcall_t __earlyinitcall_start, __earlyinitcall_end;
523
524static void __init do_earlyinitcalls(void)
525{
526 initcall_t *call, *start, *end;
527
528 start = &__earlyinitcall_start;
529 end = &__earlyinitcall_end;
530
531 for (call = start; call < end; call++) {
532 if (earlyinit_debug)
533 printk("calling earlyinitcall 0x%p\n", *call);
534
535 (*call)();
536 }
537}
538 515
539void __init setup_arch(char **cmdline_p) 516void __init setup_arch(char **cmdline_p)
540{ 517{
@@ -551,7 +528,7 @@ void __init setup_arch(char **cmdline_p)
551#endif 528#endif
552 529
553 /* call board setup routine */ 530 /* call board setup routine */
554 do_earlyinitcalls(); 531 plat_setup();
555 532
556 strlcpy(command_line, arcs_cmdline, sizeof(command_line)); 533 strlcpy(command_line, arcs_cmdline, sizeof(command_line));
557 strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE); 534 strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
@@ -573,3 +550,12 @@ int __init fpu_disable(char *s)
573} 550}
574 551
575__setup("nofpu", fpu_disable); 552__setup("nofpu", fpu_disable);
553
554int __init dsp_disable(char *s)
555{
556 cpu_data[0].ases &= ~MIPS_ASE_DSP;
557
558 return 1;
559}
560
561__setup("nodsp", dsp_disable);
diff --git a/arch/mips/kernel/signal-common.h b/arch/mips/kernel/signal-common.h
index f9234df53253..0f66ae5838b9 100644
--- a/arch/mips/kernel/signal-common.h
+++ b/arch/mips/kernel/signal-common.h
@@ -8,13 +8,14 @@
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */ 9 */
10 10
11#include <linux/config.h>
12
11static inline int 13static inline int
12setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc) 14setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
13{ 15{
14 int err = 0; 16 int err = 0;
15 17
16 err |= __put_user(regs->cp0_epc, &sc->sc_pc); 18 err |= __put_user(regs->cp0_epc, &sc->sc_pc);
17 err |= __put_user(regs->cp0_status, &sc->sc_status);
18 19
19#define save_gp_reg(i) do { \ 20#define save_gp_reg(i) do { \
20 err |= __put_user(regs->regs[i], &sc->sc_regs[i]); \ 21 err |= __put_user(regs->regs[i], &sc->sc_regs[i]); \
@@ -30,10 +31,32 @@ setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
30 save_gp_reg(31); 31 save_gp_reg(31);
31#undef save_gp_reg 32#undef save_gp_reg
32 33
34#ifdef CONFIG_32BIT
33 err |= __put_user(regs->hi, &sc->sc_mdhi); 35 err |= __put_user(regs->hi, &sc->sc_mdhi);
34 err |= __put_user(regs->lo, &sc->sc_mdlo); 36 err |= __put_user(regs->lo, &sc->sc_mdlo);
35 err |= __put_user(regs->cp0_cause, &sc->sc_cause); 37 if (cpu_has_dsp) {
36 err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr); 38 err |= __put_user(mfhi1(), &sc->sc_hi1);
39 err |= __put_user(mflo1(), &sc->sc_lo1);
40 err |= __put_user(mfhi2(), &sc->sc_hi2);
41 err |= __put_user(mflo2(), &sc->sc_lo2);
42 err |= __put_user(mfhi3(), &sc->sc_hi3);
43 err |= __put_user(mflo3(), &sc->sc_lo3);
44 err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
45 }
46#endif
47#ifdef CONFIG_64BIT
48 err |= __put_user(regs->hi, &sc->sc_hi[0]);
49 err |= __put_user(regs->lo, &sc->sc_lo[0]);
50 if (cpu_has_dsp) {
51 err |= __put_user(mfhi1(), &sc->sc_hi[1]);
52 err |= __put_user(mflo1(), &sc->sc_lo[1]);
53 err |= __put_user(mfhi2(), &sc->sc_hi[2]);
54 err |= __put_user(mflo2(), &sc->sc_lo[2]);
55 err |= __put_user(mfhi3(), &sc->sc_hi[3]);
56 err |= __put_user(mflo3(), &sc->sc_lo[3]);
57 err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
58 }
59#endif
37 60
38 err |= __put_user(!!used_math(), &sc->sc_used_math); 61 err |= __put_user(!!used_math(), &sc->sc_used_math);
39 62
@@ -61,15 +84,40 @@ out:
61static inline int 84static inline int
62restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) 85restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
63{ 86{
64 int err = 0;
65 unsigned int used_math; 87 unsigned int used_math;
88 unsigned long treg;
89 int err = 0;
66 90
67 /* Always make any pending restarted system calls return -EINTR */ 91 /* Always make any pending restarted system calls return -EINTR */
68 current_thread_info()->restart_block.fn = do_no_restart_syscall; 92 current_thread_info()->restart_block.fn = do_no_restart_syscall;
69 93
70 err |= __get_user(regs->cp0_epc, &sc->sc_pc); 94 err |= __get_user(regs->cp0_epc, &sc->sc_pc);
95#ifdef CONFIG_32BIT
71 err |= __get_user(regs->hi, &sc->sc_mdhi); 96 err |= __get_user(regs->hi, &sc->sc_mdhi);
72 err |= __get_user(regs->lo, &sc->sc_mdlo); 97 err |= __get_user(regs->lo, &sc->sc_mdlo);
98 if (cpu_has_dsp) {
99 err |= __get_user(treg, &sc->sc_hi1); mthi1(treg);
100 err |= __get_user(treg, &sc->sc_lo1); mtlo1(treg);
101 err |= __get_user(treg, &sc->sc_hi2); mthi2(treg);
102 err |= __get_user(treg, &sc->sc_lo2); mtlo2(treg);
103 err |= __get_user(treg, &sc->sc_hi3); mthi3(treg);
104 err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg);
105 err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK);
106 }
107#endif
108#ifdef CONFIG_64BIT
109 err |= __get_user(regs->hi, &sc->sc_hi[0]);
110 err |= __get_user(regs->lo, &sc->sc_lo[0]);
111 if (cpu_has_dsp) {
112 err |= __get_user(treg, &sc->sc_hi[1]); mthi1(treg);
113 err |= __get_user(treg, &sc->sc_lo[1]); mthi1(treg);
114 err |= __get_user(treg, &sc->sc_hi[2]); mthi2(treg);
115 err |= __get_user(treg, &sc->sc_lo[2]); mthi2(treg);
116 err |= __get_user(treg, &sc->sc_hi[3]); mthi3(treg);
117 err |= __get_user(treg, &sc->sc_lo[3]); mthi3(treg);
118 err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK);
119 }
120#endif
73 121
74#define restore_gp_reg(i) do { \ 122#define restore_gp_reg(i) do { \
75 err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \ 123 err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \
@@ -112,7 +160,7 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
112static inline void * 160static inline void *
113get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) 161get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
114{ 162{
115 unsigned long sp, almask; 163 unsigned long sp;
116 164
117 /* Default to using normal stack */ 165 /* Default to using normal stack */
118 sp = regs->regs[29]; 166 sp = regs->regs[29];
@@ -128,10 +176,32 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
128 if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0)) 176 if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0))
129 sp = current->sas_ss_sp + current->sas_ss_size; 177 sp = current->sas_ss_sp + current->sas_ss_size;
130 178
131 if (PLAT_TRAMPOLINE_STUFF_LINE) 179 return (void *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? 32 : ALMASK));
132 almask = ~(PLAT_TRAMPOLINE_STUFF_LINE - 1); 180}
133 else 181
134 almask = ALMASK; 182static inline int install_sigtramp(unsigned int __user *tramp,
183 unsigned int syscall)
184{
185 int err;
186
187 /*
188 * Set up the return code ...
189 *
190 * li v0, __NR__foo_sigreturn
191 * syscall
192 */
193
194 err = __put_user(0x24020000 + syscall, tramp + 0);
195 err |= __put_user(0x0000000c , tramp + 1);
196 if (ICACHE_REFILLS_WORKAROUND_WAR) {
197 err |= __put_user(0, tramp + 2);
198 err |= __put_user(0, tramp + 3);
199 err |= __put_user(0, tramp + 4);
200 err |= __put_user(0, tramp + 5);
201 err |= __put_user(0, tramp + 6);
202 err |= __put_user(0, tramp + 7);
203 }
204 flush_cache_sigtramp((unsigned long) tramp);
135 205
136 return (void *)((sp - frame_size) & almask); 206 return err;
137} 207}
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 0209c1dd1429..9202a17db8f7 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -8,6 +8,7 @@
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */ 9 */
10#include <linux/config.h> 10#include <linux/config.h>
11#include <linux/cache.h>
11#include <linux/sched.h> 12#include <linux/sched.h>
12#include <linux/mm.h> 13#include <linux/mm.h>
13#include <linux/personality.h> 14#include <linux/personality.h>
@@ -21,6 +22,7 @@
21#include <linux/unistd.h> 22#include <linux/unistd.h>
22#include <linux/compiler.h> 23#include <linux/compiler.h>
23 24
25#include <asm/abi.h>
24#include <asm/asm.h> 26#include <asm/asm.h>
25#include <linux/bitops.h> 27#include <linux/bitops.h>
26#include <asm/cacheflush.h> 28#include <asm/cacheflush.h>
@@ -29,6 +31,7 @@
29#include <asm/uaccess.h> 31#include <asm/uaccess.h>
30#include <asm/ucontext.h> 32#include <asm/ucontext.h>
31#include <asm/cpu-features.h> 33#include <asm/cpu-features.h>
34#include <asm/war.h>
32 35
33#include "signal-common.h" 36#include "signal-common.h"
34 37
@@ -36,7 +39,7 @@
36 39
37#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) 40#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
38 41
39static int do_signal(sigset_t *oldset, struct pt_regs *regs); 42int do_signal(sigset_t *oldset, struct pt_regs *regs);
40 43
41/* 44/*
42 * Atomically swap in the new signal mask, and wait for a signal. 45 * Atomically swap in the new signal mask, and wait for a signal.
@@ -47,9 +50,10 @@ save_static_function(sys_sigsuspend);
47__attribute_used__ noinline static int 50__attribute_used__ noinline static int
48_sys_sigsuspend(nabi_no_regargs struct pt_regs regs) 51_sys_sigsuspend(nabi_no_regargs struct pt_regs regs)
49{ 52{
50 sigset_t *uset, saveset, newset; 53 sigset_t saveset, newset;
54 sigset_t __user *uset;
51 55
52 uset = (sigset_t *) regs.regs[4]; 56 uset = (sigset_t __user *) regs.regs[4];
53 if (copy_from_user(&newset, uset, sizeof(sigset_t))) 57 if (copy_from_user(&newset, uset, sizeof(sigset_t)))
54 return -EFAULT; 58 return -EFAULT;
55 sigdelsetmask(&newset, ~_BLOCKABLE); 59 sigdelsetmask(&newset, ~_BLOCKABLE);
@@ -75,7 +79,8 @@ save_static_function(sys_rt_sigsuspend);
75__attribute_used__ noinline static int 79__attribute_used__ noinline static int
76_sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) 80_sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
77{ 81{
78 sigset_t *unewset, saveset, newset; 82 sigset_t saveset, newset;
83 sigset_t __user *unewset;
79 size_t sigsetsize; 84 size_t sigsetsize;
80 85
81 /* XXX Don't preclude handling different sized sigset_t's. */ 86 /* XXX Don't preclude handling different sized sigset_t's. */
@@ -83,7 +88,7 @@ _sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
83 if (sigsetsize != sizeof(sigset_t)) 88 if (sigsetsize != sizeof(sigset_t))
84 return -EINVAL; 89 return -EINVAL;
85 90
86 unewset = (sigset_t *) regs.regs[4]; 91 unewset = (sigset_t __user *) regs.regs[4];
87 if (copy_from_user(&newset, unewset, sizeof(newset))) 92 if (copy_from_user(&newset, unewset, sizeof(newset)))
88 return -EFAULT; 93 return -EFAULT;
89 sigdelsetmask(&newset, ~_BLOCKABLE); 94 sigdelsetmask(&newset, ~_BLOCKABLE);
@@ -147,33 +152,46 @@ asmlinkage int sys_sigaction(int sig, const struct sigaction *act,
147 152
148asmlinkage int sys_sigaltstack(nabi_no_regargs struct pt_regs regs) 153asmlinkage int sys_sigaltstack(nabi_no_regargs struct pt_regs regs)
149{ 154{
150 const stack_t *uss = (const stack_t *) regs.regs[4]; 155 const stack_t __user *uss = (const stack_t __user *) regs.regs[4];
151 stack_t *uoss = (stack_t *) regs.regs[5]; 156 stack_t __user *uoss = (stack_t __user *) regs.regs[5];
152 unsigned long usp = regs.regs[29]; 157 unsigned long usp = regs.regs[29];
153 158
154 return do_sigaltstack(uss, uoss, usp); 159 return do_sigaltstack(uss, uoss, usp);
155} 160}
156 161
157#if PLAT_TRAMPOLINE_STUFF_LINE 162/*
158#define __tramp __attribute__((aligned(PLAT_TRAMPOLINE_STUFF_LINE))) 163 * Horribly complicated - with the bloody RM9000 workarounds enabled
159#else 164 * the signal trampolines is moving to the end of the structure so we can
160#define __tramp 165 * increase the alignment without breaking software compatibility.
161#endif 166 */
162
163#ifdef CONFIG_TRAD_SIGNALS 167#ifdef CONFIG_TRAD_SIGNALS
164struct sigframe { 168struct sigframe {
165 u32 sf_ass[4]; /* argument save space for o32 */ 169 u32 sf_ass[4]; /* argument save space for o32 */
166 u32 sf_code[2] __tramp; /* signal trampoline */ 170#if ICACHE_REFILLS_WORKAROUND_WAR
167 struct sigcontext sf_sc __tramp; 171 u32 sf_pad[2];
172#else
173 u32 sf_code[2]; /* signal trampoline */
174#endif
175 struct sigcontext sf_sc;
168 sigset_t sf_mask; 176 sigset_t sf_mask;
177#if ICACHE_REFILLS_WORKAROUND_WAR
178 u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */
179#endif
169}; 180};
170#endif 181#endif
171 182
172struct rt_sigframe { 183struct rt_sigframe {
173 u32 rs_ass[4]; /* argument save space for o32 */ 184 u32 rs_ass[4]; /* argument save space for o32 */
174 u32 rs_code[2] __tramp; /* signal trampoline */ 185#if ICACHE_REFILLS_WORKAROUND_WAR
175 struct siginfo rs_info __tramp; 186 u32 rs_pad[2];
187#else
188 u32 rs_code[2]; /* signal trampoline */
189#endif
190 struct siginfo rs_info;
176 struct ucontext rs_uc; 191 struct ucontext rs_uc;
192#if ICACHE_REFILLS_WORKAROUND_WAR
193 u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */
194#endif
177}; 195};
178 196
179#ifdef CONFIG_TRAD_SIGNALS 197#ifdef CONFIG_TRAD_SIGNALS
@@ -214,7 +232,7 @@ _sys_sigreturn(nabi_no_regargs struct pt_regs regs)
214badframe: 232badframe:
215 force_sig(SIGSEGV, current); 233 force_sig(SIGSEGV, current);
216} 234}
217#endif 235#endif /* CONFIG_TRAD_SIGNALS */
218 236
219save_static_function(sys_rt_sigreturn); 237save_static_function(sys_rt_sigreturn);
220__attribute_used__ noinline static void 238__attribute_used__ noinline static void
@@ -260,7 +278,7 @@ badframe:
260} 278}
261 279
262#ifdef CONFIG_TRAD_SIGNALS 280#ifdef CONFIG_TRAD_SIGNALS
263static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs, 281int setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
264 int signr, sigset_t *set) 282 int signr, sigset_t *set)
265{ 283{
266 struct sigframe *frame; 284 struct sigframe *frame;
@@ -270,17 +288,7 @@ static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
270 if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) 288 if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame)))
271 goto give_sigsegv; 289 goto give_sigsegv;
272 290
273 /* 291 install_sigtramp(frame->sf_code, __NR_sigreturn);
274 * Set up the return code ...
275 *
276 * li v0, __NR_sigreturn
277 * syscall
278 */
279 if (PLAT_TRAMPOLINE_STUFF_LINE)
280 __clear_user(frame->sf_code, PLAT_TRAMPOLINE_STUFF_LINE);
281 err |= __put_user(0x24020000 + __NR_sigreturn, frame->sf_code + 0);
282 err |= __put_user(0x0000000c , frame->sf_code + 1);
283 flush_cache_sigtramp((unsigned long) frame->sf_code);
284 292
285 err |= setup_sigcontext(regs, &frame->sf_sc); 293 err |= setup_sigcontext(regs, &frame->sf_sc);
286 err |= __copy_to_user(&frame->sf_mask, set, sizeof(*set)); 294 err |= __copy_to_user(&frame->sf_mask, set, sizeof(*set));
@@ -309,14 +317,15 @@ static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
309 current->comm, current->pid, 317 current->comm, current->pid,
310 frame, regs->cp0_epc, frame->regs[31]); 318 frame, regs->cp0_epc, frame->regs[31]);
311#endif 319#endif
312 return; 320 return 1;
313 321
314give_sigsegv: 322give_sigsegv:
315 force_sigsegv(signr, current); 323 force_sigsegv(signr, current);
324 return 0;
316} 325}
317#endif 326#endif
318 327
319static void inline setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, 328int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
320 int signr, sigset_t *set, siginfo_t *info) 329 int signr, sigset_t *set, siginfo_t *info)
321{ 330{
322 struct rt_sigframe *frame; 331 struct rt_sigframe *frame;
@@ -326,17 +335,7 @@ static void inline setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
326 if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) 335 if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame)))
327 goto give_sigsegv; 336 goto give_sigsegv;
328 337
329 /* 338 install_sigtramp(frame->rs_code, __NR_rt_sigreturn);
330 * Set up the return code ...
331 *
332 * li v0, __NR_rt_sigreturn
333 * syscall
334 */
335 if (PLAT_TRAMPOLINE_STUFF_LINE)
336 __clear_user(frame->rs_code, PLAT_TRAMPOLINE_STUFF_LINE);
337 err |= __put_user(0x24020000 + __NR_rt_sigreturn, frame->rs_code + 0);
338 err |= __put_user(0x0000000c , frame->rs_code + 1);
339 flush_cache_sigtramp((unsigned long) frame->rs_code);
340 339
341 /* Create siginfo. */ 340 /* Create siginfo. */
342 err |= copy_siginfo_to_user(&frame->rs_info, info); 341 err |= copy_siginfo_to_user(&frame->rs_info, info);
@@ -378,18 +377,21 @@ static void inline setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
378 current->comm, current->pid, 377 current->comm, current->pid,
379 frame, regs->cp0_epc, regs->regs[31]); 378 frame, regs->cp0_epc, regs->regs[31]);
380#endif 379#endif
381 return; 380 return 1;
382 381
383give_sigsegv: 382give_sigsegv:
384 force_sigsegv(signr, current); 383 force_sigsegv(signr, current);
384 return 0;
385} 385}
386 386
387extern void setup_rt_frame_n32(struct k_sigaction * ka, 387extern void setup_rt_frame_n32(struct k_sigaction * ka,
388 struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info); 388 struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info);
389 389
390static inline void handle_signal(unsigned long sig, siginfo_t *info, 390static inline int handle_signal(unsigned long sig, siginfo_t *info,
391 struct k_sigaction *ka, sigset_t *oldset, struct pt_regs *regs) 391 struct k_sigaction *ka, sigset_t *oldset, struct pt_regs *regs)
392{ 392{
393 int ret;
394
393 switch(regs->regs[0]) { 395 switch(regs->regs[0]) {
394 case ERESTART_RESTARTBLOCK: 396 case ERESTART_RESTARTBLOCK:
395 case ERESTARTNOHAND: 397 case ERESTARTNOHAND:
@@ -408,22 +410,10 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info,
408 410
409 regs->regs[0] = 0; /* Don't deal with this again. */ 411 regs->regs[0] = 0; /* Don't deal with this again. */
410 412
411#ifdef CONFIG_TRAD_SIGNALS 413 if (sig_uses_siginfo(ka))
412 if (ka->sa.sa_flags & SA_SIGINFO) { 414 ret = current->thread.abi->setup_rt_frame(ka, regs, sig, oldset, info);
413#else
414 if (1) {
415#endif
416#ifdef CONFIG_MIPS32_N32
417 if ((current->thread.mflags & MF_ABI_MASK) == MF_N32)
418 setup_rt_frame_n32 (ka, regs, sig, oldset, info);
419 else
420#endif
421 setup_rt_frame(ka, regs, sig, oldset, info);
422 }
423#ifdef CONFIG_TRAD_SIGNALS
424 else 415 else
425 setup_frame(ka, regs, sig, oldset); 416 ret = current->thread.abi->setup_frame(ka, regs, sig, oldset);
426#endif
427 417
428 spin_lock_irq(&current->sighand->siglock); 418 spin_lock_irq(&current->sighand->siglock);
429 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 419 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
@@ -431,23 +421,16 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info,
431 sigaddset(&current->blocked,sig); 421 sigaddset(&current->blocked,sig);
432 recalc_sigpending(); 422 recalc_sigpending();
433 spin_unlock_irq(&current->sighand->siglock); 423 spin_unlock_irq(&current->sighand->siglock);
434}
435 424
436extern int do_signal32(sigset_t *oldset, struct pt_regs *regs); 425 return ret;
437extern int do_irix_signal(sigset_t *oldset, struct pt_regs *regs); 426}
438 427
439static int do_signal(sigset_t *oldset, struct pt_regs *regs) 428int do_signal(sigset_t *oldset, struct pt_regs *regs)
440{ 429{
441 struct k_sigaction ka; 430 struct k_sigaction ka;
442 siginfo_t info; 431 siginfo_t info;
443 int signr; 432 int signr;
444 433
445#ifdef CONFIG_BINFMT_ELF32
446 if ((current->thread.mflags & MF_ABI_MASK) == MF_O32) {
447 return do_signal32(oldset, regs);
448 }
449#endif
450
451 /* 434 /*
452 * We want the common case to go fast, which is why we may in certain 435 * We want the common case to go fast, which is why we may in certain
453 * cases get here from kernel mode. Just return without doing anything 436 * cases get here from kernel mode. Just return without doing anything
@@ -463,10 +446,8 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs)
463 oldset = &current->blocked; 446 oldset = &current->blocked;
464 447
465 signr = get_signal_to_deliver(&info, &ka, regs, NULL); 448 signr = get_signal_to_deliver(&info, &ka, regs, NULL);
466 if (signr > 0) { 449 if (signr > 0)
467 handle_signal(signr, &info, &ka, oldset, regs); 450 return handle_signal(signr, &info, &ka, oldset, regs);
468 return 1;
469 }
470 451
471no_signal: 452no_signal:
472 /* 453 /*
@@ -499,18 +480,6 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, sigset_t *oldset,
499{ 480{
500 /* deal with pending signal delivery */ 481 /* deal with pending signal delivery */
501 if (thread_info_flags & _TIF_SIGPENDING) { 482 if (thread_info_flags & _TIF_SIGPENDING) {
502#ifdef CONFIG_BINFMT_ELF32 483 current->thread.abi->do_signal(oldset, regs);
503 if (likely((current->thread.mflags & MF_ABI_MASK) == MF_O32)) {
504 do_signal32(oldset, regs);
505 return;
506 }
507#endif
508#ifdef CONFIG_BINFMT_IRIX
509 if (unlikely(current->personality != PER_LINUX)) {
510 do_irix_signal(oldset, regs);
511 return;
512 }
513#endif
514 do_signal(oldset, regs);
515 } 484 }
516} 485}
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 8ddfbd8d425a..dbe821303125 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -7,6 +7,7 @@
7 * Copyright (C) 1994 - 2000 Ralf Baechle 7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */ 9 */
10#include <linux/cache.h>
10#include <linux/sched.h> 11#include <linux/sched.h>
11#include <linux/mm.h> 12#include <linux/mm.h>
12#include <linux/smp.h> 13#include <linux/smp.h>
@@ -21,6 +22,7 @@
21#include <linux/suspend.h> 22#include <linux/suspend.h>
22#include <linux/compiler.h> 23#include <linux/compiler.h>
23 24
25#include <asm/abi.h>
24#include <asm/asm.h> 26#include <asm/asm.h>
25#include <linux/bitops.h> 27#include <linux/bitops.h>
26#include <asm/cacheflush.h> 28#include <asm/cacheflush.h>
@@ -29,6 +31,7 @@
29#include <asm/ucontext.h> 31#include <asm/ucontext.h>
30#include <asm/system.h> 32#include <asm/system.h>
31#include <asm/fpu.h> 33#include <asm/fpu.h>
34#include <asm/war.h>
32 35
33#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3) 36#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3)
34 37
@@ -76,8 +79,10 @@ typedef struct compat_siginfo {
76 79
77 /* POSIX.1b timers */ 80 /* POSIX.1b timers */
78 struct { 81 struct {
79 unsigned int _timer1; 82 timer_t _tid; /* timer id */
80 unsigned int _timer2; 83 int _overrun; /* overrun count */
84 compat_sigval_t _sigval;/* same as below */
85 int _sys_private; /* not to be passed to user */
81 } _timer; 86 } _timer;
82 87
83 /* POSIX.1b signals */ 88 /* POSIX.1b signals */
@@ -259,11 +264,12 @@ asmlinkage int sys32_sigaction(int sig, const struct sigaction32 *act,
259 264
260 if (act) { 265 if (act) {
261 old_sigset_t mask; 266 old_sigset_t mask;
267 s32 handler;
262 268
263 if (!access_ok(VERIFY_READ, act, sizeof(*act))) 269 if (!access_ok(VERIFY_READ, act, sizeof(*act)))
264 return -EFAULT; 270 return -EFAULT;
265 err |= __get_user((u32)(u64)new_ka.sa.sa_handler, 271 err |= __get_user(handler, &act->sa_handler);
266 &act->sa_handler); 272 new_ka.sa.sa_handler = (void*)(s64)handler;
267 err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); 273 err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags);
268 err |= __get_user(mask, &act->sa_mask.sig[0]); 274 err |= __get_user(mask, &act->sa_mask.sig[0]);
269 if (err) 275 if (err)
@@ -331,8 +337,9 @@ asmlinkage int sys32_sigaltstack(nabi_no_regargs struct pt_regs regs)
331 337
332static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc) 338static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc)
333{ 339{
340 u32 used_math;
334 int err = 0; 341 int err = 0;
335 __u32 used_math; 342 s32 treg;
336 343
337 /* Always make any pending restarted system calls return -EINTR */ 344 /* Always make any pending restarted system calls return -EINTR */
338 current_thread_info()->restart_block.fn = do_no_restart_syscall; 345 current_thread_info()->restart_block.fn = do_no_restart_syscall;
@@ -340,6 +347,15 @@ static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc)
340 err |= __get_user(regs->cp0_epc, &sc->sc_pc); 347 err |= __get_user(regs->cp0_epc, &sc->sc_pc);
341 err |= __get_user(regs->hi, &sc->sc_mdhi); 348 err |= __get_user(regs->hi, &sc->sc_mdhi);
342 err |= __get_user(regs->lo, &sc->sc_mdlo); 349 err |= __get_user(regs->lo, &sc->sc_mdlo);
350 if (cpu_has_dsp) {
351 err |= __get_user(treg, &sc->sc_hi1); mthi1(treg);
352 err |= __get_user(treg, &sc->sc_lo1); mtlo1(treg);
353 err |= __get_user(treg, &sc->sc_hi2); mthi2(treg);
354 err |= __get_user(treg, &sc->sc_lo2); mtlo2(treg);
355 err |= __get_user(treg, &sc->sc_hi3); mthi3(treg);
356 err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg);
357 err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK);
358 }
343 359
344#define restore_gp_reg(i) do { \ 360#define restore_gp_reg(i) do { \
345 err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \ 361 err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \
@@ -378,16 +394,30 @@ static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc)
378 394
379struct sigframe { 395struct sigframe {
380 u32 sf_ass[4]; /* argument save space for o32 */ 396 u32 sf_ass[4]; /* argument save space for o32 */
397#if ICACHE_REFILLS_WORKAROUND_WAR
398 u32 sf_pad[2];
399#else
381 u32 sf_code[2]; /* signal trampoline */ 400 u32 sf_code[2]; /* signal trampoline */
401#endif
382 struct sigcontext32 sf_sc; 402 struct sigcontext32 sf_sc;
383 sigset_t sf_mask; 403 sigset_t sf_mask;
404#if ICACHE_REFILLS_WORKAROUND_WAR
405 u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */
406#endif
384}; 407};
385 408
386struct rt_sigframe32 { 409struct rt_sigframe32 {
387 u32 rs_ass[4]; /* argument save space for o32 */ 410 u32 rs_ass[4]; /* argument save space for o32 */
411#if ICACHE_REFILLS_WORKAROUND_WAR
412 u32 rs_pad[2];
413#else
388 u32 rs_code[2]; /* signal trampoline */ 414 u32 rs_code[2]; /* signal trampoline */
415#endif
389 compat_siginfo_t rs_info; 416 compat_siginfo_t rs_info;
390 struct ucontext32 rs_uc; 417 struct ucontext32 rs_uc;
418#if ICACHE_REFILLS_WORKAROUND_WAR
419 u32 rs_code[8] __attribute__((aligned(32))); /* signal trampoline */
420#endif
391}; 421};
392 422
393int copy_siginfo_to_user32(compat_siginfo_t *to, siginfo_t *from) 423int copy_siginfo_to_user32(compat_siginfo_t *to, siginfo_t *from)
@@ -411,6 +441,11 @@ int copy_siginfo_to_user32(compat_siginfo_t *to, siginfo_t *from)
411 err |= __copy_to_user(&to->_sifields._pad, &from->_sifields._pad, SI_PAD_SIZE); 441 err |= __copy_to_user(&to->_sifields._pad, &from->_sifields._pad, SI_PAD_SIZE);
412 else { 442 else {
413 switch (from->si_code >> 16) { 443 switch (from->si_code >> 16) {
444 case __SI_TIMER >> 16:
445 err |= __put_user(from->si_tid, &to->si_tid);
446 err |= __put_user(from->si_overrun, &to->si_overrun);
447 err |= __put_user(from->si_int, &to->si_int);
448 break;
414 case __SI_CHLD >> 16: 449 case __SI_CHLD >> 16:
415 err |= __put_user(from->si_utime, &to->si_utime); 450 err |= __put_user(from->si_utime, &to->si_utime);
416 err |= __put_user(from->si_stime, &to->si_stime); 451 err |= __put_user(from->si_stime, &to->si_stime);
@@ -480,6 +515,7 @@ __attribute_used__ noinline static void
480_sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) 515_sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
481{ 516{
482 struct rt_sigframe32 *frame; 517 struct rt_sigframe32 *frame;
518 mm_segment_t old_fs;
483 sigset_t set; 519 sigset_t set;
484 stack_t st; 520 stack_t st;
485 s32 sp; 521 s32 sp;
@@ -510,7 +546,10 @@ _sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
510 546
511 /* It is more difficult to avoid calling this function than to 547 /* It is more difficult to avoid calling this function than to
512 call it and ignore errors. */ 548 call it and ignore errors. */
549 old_fs = get_fs();
550 set_fs (KERNEL_DS);
513 do_sigaltstack(&st, NULL, regs.regs[29]); 551 do_sigaltstack(&st, NULL, regs.regs[29]);
552 set_fs (old_fs);
514 553
515 /* 554 /*
516 * Don't let your children do this ... 555 * Don't let your children do this ...
@@ -550,8 +589,15 @@ static inline int setup_sigcontext32(struct pt_regs *regs,
550 589
551 err |= __put_user(regs->hi, &sc->sc_mdhi); 590 err |= __put_user(regs->hi, &sc->sc_mdhi);
552 err |= __put_user(regs->lo, &sc->sc_mdlo); 591 err |= __put_user(regs->lo, &sc->sc_mdlo);
553 err |= __put_user(regs->cp0_cause, &sc->sc_cause); 592 if (cpu_has_dsp) {
554 err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr); 593 err |= __put_user(rddsp(DSP_MASK), &sc->sc_hi1);
594 err |= __put_user(mfhi1(), &sc->sc_hi1);
595 err |= __put_user(mflo1(), &sc->sc_lo1);
596 err |= __put_user(mfhi2(), &sc->sc_hi2);
597 err |= __put_user(mflo2(), &sc->sc_lo2);
598 err |= __put_user(mfhi3(), &sc->sc_hi3);
599 err |= __put_user(mflo3(), &sc->sc_lo3);
600 }
555 601
556 err |= __put_user(!!used_math(), &sc->sc_used_math); 602 err |= __put_user(!!used_math(), &sc->sc_used_math);
557 603
@@ -601,7 +647,7 @@ static inline void *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
601 return (void *)((sp - frame_size) & ALMASK); 647 return (void *)((sp - frame_size) & ALMASK);
602} 648}
603 649
604static inline void setup_frame(struct k_sigaction * ka, struct pt_regs *regs, 650void setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
605 int signr, sigset_t *set) 651 int signr, sigset_t *set)
606{ 652{
607 struct sigframe *frame; 653 struct sigframe *frame;
@@ -654,9 +700,7 @@ give_sigsegv:
654 force_sigsegv(signr, current); 700 force_sigsegv(signr, current);
655} 701}
656 702
657static inline void setup_rt_frame(struct k_sigaction * ka, 703void setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info)
658 struct pt_regs *regs, int signr,
659 sigset_t *set, siginfo_t *info)
660{ 704{
661 struct rt_sigframe32 *frame; 705 struct rt_sigframe32 *frame;
662 int err = 0; 706 int err = 0;
@@ -725,9 +769,11 @@ give_sigsegv:
725 force_sigsegv(signr, current); 769 force_sigsegv(signr, current);
726} 770}
727 771
728static inline void handle_signal(unsigned long sig, siginfo_t *info, 772static inline int handle_signal(unsigned long sig, siginfo_t *info,
729 struct k_sigaction *ka, sigset_t *oldset, struct pt_regs * regs) 773 struct k_sigaction *ka, sigset_t *oldset, struct pt_regs * regs)
730{ 774{
775 int ret;
776
731 switch (regs->regs[0]) { 777 switch (regs->regs[0]) {
732 case ERESTART_RESTARTBLOCK: 778 case ERESTART_RESTARTBLOCK:
733 case ERESTARTNOHAND: 779 case ERESTARTNOHAND:
@@ -747,9 +793,9 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info,
747 regs->regs[0] = 0; /* Don't deal with this again. */ 793 regs->regs[0] = 0; /* Don't deal with this again. */
748 794
749 if (ka->sa.sa_flags & SA_SIGINFO) 795 if (ka->sa.sa_flags & SA_SIGINFO)
750 setup_rt_frame(ka, regs, sig, oldset, info); 796 ret = current->thread.abi->setup_rt_frame(ka, regs, sig, oldset, info);
751 else 797 else
752 setup_frame(ka, regs, sig, oldset); 798 ret = current->thread.abi->setup_frame(ka, regs, sig, oldset);
753 799
754 spin_lock_irq(&current->sighand->siglock); 800 spin_lock_irq(&current->sighand->siglock);
755 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 801 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
@@ -757,6 +803,8 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info,
757 sigaddset(&current->blocked,sig); 803 sigaddset(&current->blocked,sig);
758 recalc_sigpending(); 804 recalc_sigpending();
759 spin_unlock_irq(&current->sighand->siglock); 805 spin_unlock_irq(&current->sighand->siglock);
806
807 return ret;
760} 808}
761 809
762int do_signal32(sigset_t *oldset, struct pt_regs *regs) 810int do_signal32(sigset_t *oldset, struct pt_regs *regs)
@@ -780,10 +828,8 @@ int do_signal32(sigset_t *oldset, struct pt_regs *regs)
780 oldset = &current->blocked; 828 oldset = &current->blocked;
781 829
782 signr = get_signal_to_deliver(&info, &ka, regs, NULL); 830 signr = get_signal_to_deliver(&info, &ka, regs, NULL);
783 if (signr > 0) { 831 if (signr > 0)
784 handle_signal(signr, &info, &ka, oldset, regs); 832 return handle_signal(signr, &info, &ka, oldset, regs);
785 return 1;
786 }
787 833
788no_signal: 834no_signal:
789 /* 835 /*
@@ -819,12 +865,13 @@ asmlinkage int sys32_rt_sigaction(int sig, const struct sigaction32 *act,
819 goto out; 865 goto out;
820 866
821 if (act) { 867 if (act) {
868 s32 handler;
822 int err = 0; 869 int err = 0;
823 870
824 if (!access_ok(VERIFY_READ, act, sizeof(*act))) 871 if (!access_ok(VERIFY_READ, act, sizeof(*act)))
825 return -EFAULT; 872 return -EFAULT;
826 err |= __get_user((u32)(u64)new_sa.sa.sa_handler, 873 err |= __get_user(handler, &act->sa_handler);
827 &act->sa_handler); 874 new_sa.sa.sa_handler = (void*)(s64)handler;
828 err |= __get_user(new_sa.sa.sa_flags, &act->sa_flags); 875 err |= __get_user(new_sa.sa.sa_flags, &act->sa_flags);
829 err |= get_sigset(&new_sa.sa.sa_mask, &act->sa_mask); 876 err |= get_sigset(&new_sa.sa.sa_mask, &act->sa_mask);
830 if (err) 877 if (err)
@@ -902,3 +949,30 @@ asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t *uinfo)
902 set_fs (old_fs); 949 set_fs (old_fs);
903 return ret; 950 return ret;
904} 951}
952
953asmlinkage long
954sys32_waitid(int which, compat_pid_t pid,
955 compat_siginfo_t __user *uinfo, int options,
956 struct compat_rusage __user *uru)
957{
958 siginfo_t info;
959 struct rusage ru;
960 long ret;
961 mm_segment_t old_fs = get_fs();
962
963 info.si_signo = 0;
964 set_fs (KERNEL_DS);
965 ret = sys_waitid(which, pid, (siginfo_t __user *) &info, options,
966 uru ? (struct rusage __user *) &ru : NULL);
967 set_fs (old_fs);
968
969 if (ret < 0 || info.si_signo == 0)
970 return ret;
971
972 if (uru && (ret = put_compat_rusage(&ru, uru)))
973 return ret;
974
975 BUG_ON(info.si_code & __SI_MASK);
976 info.si_code |= __SI_CHLD;
977 return copy_siginfo_to_user32(uinfo, &info);
978}
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index 3544208d4b4b..ec61b2670ba6 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -15,6 +15,8 @@
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18#include <linux/cache.h>
19#include <linux/sched.h>
18#include <linux/sched.h> 20#include <linux/sched.h>
19#include <linux/mm.h> 21#include <linux/mm.h>
20#include <linux/smp.h> 22#include <linux/smp.h>
@@ -36,6 +38,7 @@
36#include <asm/system.h> 38#include <asm/system.h>
37#include <asm/fpu.h> 39#include <asm/fpu.h>
38#include <asm/cpu-features.h> 40#include <asm/cpu-features.h>
41#include <asm/war.h>
39 42
40#include "signal-common.h" 43#include "signal-common.h"
41 44
@@ -62,17 +65,18 @@ struct ucontextn32 {
62 sigset_t uc_sigmask; /* mask last for extensibility */ 65 sigset_t uc_sigmask; /* mask last for extensibility */
63}; 66};
64 67
65#if PLAT_TRAMPOLINE_STUFF_LINE
66#define __tramp __attribute__((aligned(PLAT_TRAMPOLINE_STUFF_LINE)))
67#else
68#define __tramp
69#endif
70
71struct rt_sigframe_n32 { 68struct rt_sigframe_n32 {
72 u32 rs_ass[4]; /* argument save space for o32 */ 69 u32 rs_ass[4]; /* argument save space for o32 */
73 u32 rs_code[2] __tramp; /* signal trampoline */ 70#if ICACHE_REFILLS_WORKAROUND_WAR
74 struct siginfo rs_info __tramp; 71 u32 rs_pad[2];
72#else
73 u32 rs_code[2]; /* signal trampoline */
74#endif
75 struct siginfo rs_info;
75 struct ucontextn32 rs_uc; 76 struct ucontextn32 rs_uc;
77#if ICACHE_REFILLS_WORKAROUND_WAR
78 u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */
79#endif
76}; 80};
77 81
78save_static_function(sysn32_rt_sigreturn); 82save_static_function(sysn32_rt_sigreturn);
@@ -126,7 +130,7 @@ badframe:
126 force_sig(SIGSEGV, current); 130 force_sig(SIGSEGV, current);
127} 131}
128 132
129void setup_rt_frame_n32(struct k_sigaction * ka, 133int setup_rt_frame_n32(struct k_sigaction * ka,
130 struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) 134 struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info)
131{ 135{
132 struct rt_sigframe_n32 *frame; 136 struct rt_sigframe_n32 *frame;
@@ -137,17 +141,7 @@ void setup_rt_frame_n32(struct k_sigaction * ka,
137 if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) 141 if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame)))
138 goto give_sigsegv; 142 goto give_sigsegv;
139 143
140 /* 144 install_sigtramp(frame->rs_code, __NR_N32_rt_sigreturn);
141 * Set up the return code ...
142 *
143 * li v0, __NR_rt_sigreturn
144 * syscall
145 */
146 if (PLAT_TRAMPOLINE_STUFF_LINE)
147 __clear_user(frame->rs_code, PLAT_TRAMPOLINE_STUFF_LINE);
148 err |= __put_user(0x24020000 + __NR_N32_rt_sigreturn, frame->rs_code + 0);
149 err |= __put_user(0x0000000c , frame->rs_code + 1);
150 flush_cache_sigtramp((unsigned long) frame->rs_code);
151 145
152 /* Create siginfo. */ 146 /* Create siginfo. */
153 err |= copy_siginfo_to_user(&frame->rs_info, info); 147 err |= copy_siginfo_to_user(&frame->rs_info, info);
@@ -190,8 +184,9 @@ void setup_rt_frame_n32(struct k_sigaction * ka,
190 current->comm, current->pid, 184 current->comm, current->pid,
191 frame, regs->cp0_epc, regs->regs[31]); 185 frame, regs->cp0_epc, regs->regs[31]);
192#endif 186#endif
193 return; 187 return 1;
194 188
195give_sigsegv: 189give_sigsegv:
196 force_sigsegv(signr, current); 190 force_sigsegv(signr, current);
191 return 0;
197} 192}
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index af5cd3b8a396..fcacf1aae98a 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -50,7 +50,6 @@ static void smp_tune_scheduling (void)
50{ 50{
51 struct cache_desc *cd = &current_cpu_data.scache; 51 struct cache_desc *cd = &current_cpu_data.scache;
52 unsigned long cachesize; /* kB */ 52 unsigned long cachesize; /* kB */
53 unsigned long bandwidth = 350; /* MB/s */
54 unsigned long cpu_khz; 53 unsigned long cpu_khz;
55 54
56 /* 55 /*
@@ -121,7 +120,19 @@ struct call_data_struct *call_data;
121 * or are or have executed. 120 * or are or have executed.
122 * 121 *
123 * You must not call this function with disabled interrupts or from a 122 * You must not call this function with disabled interrupts or from a
124 * hardware interrupt handler or from a bottom half handler. 123 * hardware interrupt handler or from a bottom half handler:
124 *
125 * CPU A CPU B
126 * Disable interrupts
127 * smp_call_function()
128 * Take call_lock
129 * Send IPIs
130 * Wait for all cpus to acknowledge IPI
131 * CPU A has not responded, spin waiting
132 * for cpu A to respond, holding call_lock
133 * smp_call_function()
134 * Spin waiting for call_lock
135 * Deadlock Deadlock
125 */ 136 */
126int smp_call_function (void (*func) (void *info), void *info, int retry, 137int smp_call_function (void (*func) (void *info), void *info, int retry,
127 int wait) 138 int wait)
@@ -130,6 +141,11 @@ int smp_call_function (void (*func) (void *info), void *info, int retry,
130 int i, cpus = num_online_cpus() - 1; 141 int i, cpus = num_online_cpus() - 1;
131 int cpu = smp_processor_id(); 142 int cpu = smp_processor_id();
132 143
144 /*
145 * Can die spectacularly if this CPU isn't yet marked online
146 */
147 BUG_ON(!cpu_online(cpu));
148
133 if (!cpus) 149 if (!cpus)
134 return 0; 150 return 0;
135 151
@@ -214,7 +230,6 @@ void __init smp_cpus_done(unsigned int max_cpus)
214/* called from main before smp_init() */ 230/* called from main before smp_init() */
215void __init smp_prepare_cpus(unsigned int max_cpus) 231void __init smp_prepare_cpus(unsigned int max_cpus)
216{ 232{
217 cpu_data[0].udelay_val = loops_per_jiffy;
218 init_new_context(current, &init_mm); 233 init_new_context(current, &init_mm);
219 current_thread_info()->cpu = 0; 234 current_thread_info()->cpu = 0;
220 smp_tune_scheduling(); 235 smp_tune_scheduling();
@@ -236,23 +251,28 @@ void __devinit smp_prepare_boot_cpu(void)
236} 251}
237 252
238/* 253/*
239 * Startup the CPU with this logical number 254 * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu
255 * and keep control until "cpu_online(cpu)" is set. Note: cpu is
256 * physical, not logical.
240 */ 257 */
241static int __init do_boot_cpu(int cpu) 258int __devinit __cpu_up(unsigned int cpu)
242{ 259{
243 struct task_struct *idle; 260 struct task_struct *idle;
244 261
245 /* 262 /*
263 * Processor goes to start_secondary(), sets online flag
246 * The following code is purely to make sure 264 * The following code is purely to make sure
247 * Linux can schedule processes on this slave. 265 * Linux can schedule processes on this slave.
248 */ 266 */
249 idle = fork_idle(cpu); 267 idle = fork_idle(cpu);
250 if (IS_ERR(idle)) 268 if (IS_ERR(idle))
251 panic("failed fork for CPU %d\n", cpu); 269 panic(KERN_ERR "Fork failed for CPU %d", cpu);
252 270
253 prom_boot_secondary(cpu, idle); 271 prom_boot_secondary(cpu, idle);
254 272
255 /* XXXKW timeout */ 273 /*
274 * Trust is futile. We should really have timeouts ...
275 */
256 while (!cpu_isset(cpu, cpu_callin_map)) 276 while (!cpu_isset(cpu, cpu_callin_map))
257 udelay(100); 277 udelay(100);
258 278
@@ -261,23 +281,6 @@ static int __init do_boot_cpu(int cpu)
261 return 0; 281 return 0;
262} 282}
263 283
264/*
265 * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu
266 * and keep control until "cpu_online(cpu)" is set. Note: cpu is
267 * physical, not logical.
268 */
269int __devinit __cpu_up(unsigned int cpu)
270{
271 int ret;
272
273 /* Processor goes to start_secondary(), sets online flag */
274 ret = do_boot_cpu(cpu);
275 if (ret < 0)
276 return ret;
277
278 return 0;
279}
280
281/* Not really SMP stuff ... */ 284/* Not really SMP stuff ... */
282int setup_profiling_timer(unsigned int multiplier) 285int setup_profiling_timer(unsigned int multiplier)
283{ 286{
diff --git a/arch/mips/kernel/smp_mt.c b/arch/mips/kernel/smp_mt.c
new file mode 100644
index 000000000000..d429544ba4bc
--- /dev/null
+++ b/arch/mips/kernel/smp_mt.c
@@ -0,0 +1,366 @@
1/*
2 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * Elizabeth Clarke (beth@mips.com)
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 */
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/cpumask.h>
23#include <linux/interrupt.h>
24#include <linux/compiler.h>
25
26#include <asm/atomic.h>
27#include <asm/cpu.h>
28#include <asm/processor.h>
29#include <asm/system.h>
30#include <asm/hardirq.h>
31#include <asm/mmu_context.h>
32#include <asm/smp.h>
33#include <asm/time.h>
34#include <asm/mipsregs.h>
35#include <asm/mipsmtregs.h>
36#include <asm/cacheflush.h>
37#include <asm/mips-boards/maltaint.h>
38
39#define MIPS_CPU_IPI_RESCHED_IRQ 0
40#define MIPS_CPU_IPI_CALL_IRQ 1
41
42static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
43
44#if 0
45static void dump_mtregisters(int vpe, int tc)
46{
47 printk("vpe %d tc %d\n", vpe, tc);
48
49 settc(tc);
50
51 printk(" c0 status 0x%lx\n", read_vpe_c0_status());
52 printk(" vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol());
53 printk(" vpeconf0 0x%lx\n", read_vpe_c0_vpeconf0());
54 printk(" tcstatus 0x%lx\n", read_tc_c0_tcstatus());
55 printk(" tcrestart 0x%lx\n", read_tc_c0_tcrestart());
56 printk(" tcbind 0x%lx\n", read_tc_c0_tcbind());
57 printk(" tchalt 0x%lx\n", read_tc_c0_tchalt());
58}
59#endif
60
61void __init sanitize_tlb_entries(void)
62{
63 int i, tlbsiz;
64 unsigned long mvpconf0, ncpu;
65
66 if (!cpu_has_mipsmt)
67 return;
68
69 set_c0_mvpcontrol(MVPCONTROL_VPC);
70
71 /* Disable TLB sharing */
72 clear_c0_mvpcontrol(MVPCONTROL_STLB);
73
74 mvpconf0 = read_c0_mvpconf0();
75
76 printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0,
77 (mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT,
78 (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT);
79
80 tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT;
81 ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
82
83 printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu);
84
85 if (tlbsiz > 0) {
86 /* share them out across the vpe's */
87 tlbsiz /= ncpu;
88
89 printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz);
90
91 for (i = 0; i < ncpu; i++) {
92 settc(i);
93
94 if (i == 0)
95 write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25));
96 else
97 write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) |
98 (tlbsiz << 25));
99 }
100 }
101
102 clear_c0_mvpcontrol(MVPCONTROL_VPC);
103}
104
105#if 0
106/*
107 * Use c0_MVPConf0 to find out how many CPUs are available, setting up
108 * phys_cpu_present_map and the logical/physical mappings.
109 */
110void __init prom_build_cpu_map(void)
111{
112 int i, num, ncpus;
113
114 cpus_clear(phys_cpu_present_map);
115
116 /* assume we boot on cpu 0.... */
117 cpu_set(0, phys_cpu_present_map);
118 __cpu_number_map[0] = 0;
119 __cpu_logical_map[0] = 0;
120
121 if (cpu_has_mipsmt) {
122 ncpus = ((read_c0_mvpconf0() & (MVPCONF0_PVPE)) >> MVPCONF0_PVPE_SHIFT) + 1;
123 for (i=1, num=0; i< NR_CPUS && i<ncpus; i++) {
124 cpu_set(i, phys_cpu_present_map);
125 __cpu_number_map[i] = ++num;
126 __cpu_logical_map[num] = i;
127 }
128
129 printk(KERN_INFO "%i available secondary CPU(s)\n", num);
130 }
131}
132#endif
133
134static void ipi_resched_dispatch (struct pt_regs *regs)
135{
136 do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ, regs);
137}
138
139static void ipi_call_dispatch (struct pt_regs *regs)
140{
141 do_IRQ(MIPS_CPU_IPI_CALL_IRQ, regs);
142}
143
144irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs)
145{
146 return IRQ_HANDLED;
147}
148
149irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs)
150{
151 smp_call_function_interrupt();
152
153 return IRQ_HANDLED;
154}
155
156static struct irqaction irq_resched = {
157 .handler = ipi_resched_interrupt,
158 .flags = SA_INTERRUPT,
159 .name = "IPI_resched"
160};
161
162static struct irqaction irq_call = {
163 .handler = ipi_call_interrupt,
164 .flags = SA_INTERRUPT,
165 .name = "IPI_call"
166};
167
168/*
169 * Common setup before any secondaries are started
170 * Make sure all CPU's are in a sensible state before we boot any of the
171 * secondarys
172 */
173void prom_prepare_cpus(unsigned int max_cpus)
174{
175 unsigned long val;
176 int i, num;
177
178 if (!cpu_has_mipsmt)
179 return;
180
181 /* disable MT so we can configure */
182 dvpe();
183 dmt();
184
185 /* Put MVPE's into 'configuration state' */
186 set_c0_mvpcontrol(MVPCONTROL_VPC);
187
188 val = read_c0_mvpconf0();
189
190 /* we'll always have more TC's than VPE's, so loop setting everything
191 to a sensible state */
192 for (i = 0, num = 0; i <= ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT); i++) {
193 settc(i);
194
195 /* VPE's */
196 if (i <= ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) {
197
198 /* deactivate all but vpe0 */
199 if (i != 0) {
200 unsigned long tmp = read_vpe_c0_vpeconf0();
201
202 tmp &= ~VPECONF0_VPA;
203
204 /* master VPE */
205 tmp |= VPECONF0_MVP;
206 write_vpe_c0_vpeconf0(tmp);
207
208 /* Record this as available CPU */
209 if (i < max_cpus) {
210 cpu_set(i, phys_cpu_present_map);
211 __cpu_number_map[i] = ++num;
212 __cpu_logical_map[num] = i;
213 }
214 }
215
216 /* disable multi-threading with TC's */
217 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
218
219 if (i != 0) {
220 write_vpe_c0_status((read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
221 write_vpe_c0_cause(read_vpe_c0_cause() & ~CAUSEF_IP);
222
223 /* set config to be the same as vpe0, particularly kseg0 coherency alg */
224 write_vpe_c0_config( read_c0_config());
225 }
226
227 }
228
229 /* TC's */
230
231 if (i != 0) {
232 unsigned long tmp;
233
234 /* bind a TC to each VPE, May as well put all excess TC's
235 on the last VPE */
236 if ( i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1) )
237 write_tc_c0_tcbind(read_tc_c0_tcbind() | ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) );
238 else {
239 write_tc_c0_tcbind( read_tc_c0_tcbind() | i);
240
241 /* and set XTC */
242 write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | (i << VPECONF0_XTC_SHIFT));
243 }
244
245 tmp = read_tc_c0_tcstatus();
246
247 /* mark not allocated and not dynamically allocatable */
248 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
249 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
250 write_tc_c0_tcstatus(tmp);
251
252 write_tc_c0_tchalt(TCHALT_H);
253 }
254 }
255
256 /* Release config state */
257 clear_c0_mvpcontrol(MVPCONTROL_VPC);
258
259 /* We'll wait until starting the secondaries before starting MVPE */
260
261 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
262
263 /* set up ipi interrupts */
264 if (cpu_has_vint) {
265 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
266 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
267 }
268
269 cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
270 cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ;
271
272 setup_irq(cpu_ipi_resched_irq, &irq_resched);
273 setup_irq(cpu_ipi_call_irq, &irq_call);
274
275 /* need to mark IPI's as IRQ_PER_CPU */
276 irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU;
277 irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU;
278}
279
280/*
281 * Setup the PC, SP, and GP of a secondary processor and start it
282 * running!
283 * smp_bootstrap is the place to resume from
284 * __KSTK_TOS(idle) is apparently the stack pointer
285 * (unsigned long)idle->thread_info the gp
286 * assumes a 1:1 mapping of TC => VPE
287 */
288void prom_boot_secondary(int cpu, struct task_struct *idle)
289{
290 dvpe();
291 set_c0_mvpcontrol(MVPCONTROL_VPC);
292
293 settc(cpu);
294
295 /* restart */
296 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
297
298 /* enable the tc this vpe/cpu will be running */
299 write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);
300
301 write_tc_c0_tchalt(0);
302
303 /* enable the VPE */
304 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
305
306 /* stack pointer */
307 write_tc_gpr_sp( __KSTK_TOS(idle));
308
309 /* global pointer */
310 write_tc_gpr_gp((unsigned long)idle->thread_info);
311
312 flush_icache_range((unsigned long)idle->thread_info,
313 (unsigned long)idle->thread_info +
314 sizeof(struct thread_info));
315
316 /* finally out of configuration and into chaos */
317 clear_c0_mvpcontrol(MVPCONTROL_VPC);
318
319 evpe(EVPE_ENABLE);
320}
321
322void prom_init_secondary(void)
323{
324 write_c0_status((read_c0_status() & ~ST0_IM ) |
325 (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7));
326}
327
328void prom_smp_finish(void)
329{
330 write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
331
332 local_irq_enable();
333}
334
335void prom_cpus_done(void)
336{
337}
338
339void core_send_ipi(int cpu, unsigned int action)
340{
341 int i;
342 unsigned long flags;
343 int vpflags;
344
345 local_irq_save (flags);
346
347 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
348
349 switch (action) {
350 case SMP_CALL_FUNCTION:
351 i = C_SW1;
352 break;
353
354 case SMP_RESCHEDULE_YOURSELF:
355 default:
356 i = C_SW0;
357 break;
358 }
359
360 /* 1:1 mapping of vpe and tc... */
361 settc(cpu);
362 write_vpe_c0_cause(read_vpe_c0_cause() | i);
363 evpe(vpflags);
364
365 local_irq_restore(flags);
366}
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 21e3e13a4b44..ee98eeb65e85 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -7,6 +7,7 @@
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc. 8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 */ 9 */
10#include <linux/config.h>
10#include <linux/a.out.h> 11#include <linux/a.out.h>
11#include <linux/errno.h> 12#include <linux/errno.h>
12#include <linux/linkage.h> 13#include <linux/linkage.h>
@@ -26,6 +27,7 @@
26#include <linux/msg.h> 27#include <linux/msg.h>
27#include <linux/shm.h> 28#include <linux/shm.h>
28#include <linux/compiler.h> 29#include <linux/compiler.h>
30#include <linux/module.h>
29 31
30#include <asm/branch.h> 32#include <asm/branch.h>
31#include <asm/cachectl.h> 33#include <asm/cachectl.h>
@@ -56,6 +58,8 @@ out:
56 58
57unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */ 59unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */
58 60
61EXPORT_SYMBOL(shm_align_mask);
62
59#define COLOUR_ALIGN(addr,pgoff) \ 63#define COLOUR_ALIGN(addr,pgoff) \
60 ((((addr) + shm_align_mask) & ~shm_align_mask) + \ 64 ((((addr) + shm_align_mask) & ~shm_align_mask) + \
61 (((pgoff) << PAGE_SHIFT) & shm_align_mask)) 65 (((pgoff) << PAGE_SHIFT) & shm_align_mask))
@@ -173,14 +177,28 @@ _sys_clone(nabi_no_regargs struct pt_regs regs)
173{ 177{
174 unsigned long clone_flags; 178 unsigned long clone_flags;
175 unsigned long newsp; 179 unsigned long newsp;
176 int *parent_tidptr, *child_tidptr; 180 int __user *parent_tidptr, *child_tidptr;
177 181
178 clone_flags = regs.regs[4]; 182 clone_flags = regs.regs[4];
179 newsp = regs.regs[5]; 183 newsp = regs.regs[5];
180 if (!newsp) 184 if (!newsp)
181 newsp = regs.regs[29]; 185 newsp = regs.regs[29];
182 parent_tidptr = (int *) regs.regs[6]; 186 parent_tidptr = (int __user *) regs.regs[6];
183 child_tidptr = (int *) regs.regs[7]; 187#ifdef CONFIG_32BIT
188 /* We need to fetch the fifth argument off the stack. */
189 child_tidptr = NULL;
190 if (clone_flags & (CLONE_CHILD_SETTID | CLONE_CHILD_CLEARTID)) {
191 int __user *__user *usp = (int __user *__user *) regs.regs[29];
192 if (regs.regs[2] == __NR_syscall) {
193 if (get_user (child_tidptr, &usp[5]))
194 return -EFAULT;
195 }
196 else if (get_user (child_tidptr, &usp[4]))
197 return -EFAULT;
198 }
199#else
200 child_tidptr = (int __user *) regs.regs[8];
201#endif
184 return do_fork(clone_flags, newsp, &regs, 0, 202 return do_fork(clone_flags, newsp, &regs, 0,
185 parent_tidptr, child_tidptr); 203 parent_tidptr, child_tidptr);
186} 204}
@@ -242,6 +260,16 @@ asmlinkage int sys_olduname(struct oldold_utsname * name)
242 return error; 260 return error;
243} 261}
244 262
263void sys_set_thread_area(unsigned long addr)
264{
265 struct thread_info *ti = current->thread_info;
266
267 ti->tp_value = addr;
268
269 /* If some future MIPS implementation has this register in hardware,
270 * we will need to update it here (and in context switches). */
271}
272
245asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3) 273asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
246{ 274{
247 int tmp, len; 275 int tmp, len;
diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c
index 7ae4af476974..52924f8ce23c 100644
--- a/arch/mips/kernel/sysirix.c
+++ b/arch/mips/kernel/sysirix.c
@@ -73,32 +73,30 @@ asmlinkage int irix_sysmp(struct pt_regs *regs)
73} 73}
74 74
75/* The prctl commands. */ 75/* The prctl commands. */
76#define PR_MAXPROCS 1 /* Tasks/user. */ 76#define PR_MAXPROCS 1 /* Tasks/user. */
77#define PR_ISBLOCKED 2 /* If blocked, return 1. */ 77#define PR_ISBLOCKED 2 /* If blocked, return 1. */
78#define PR_SETSTACKSIZE 3 /* Set largest task stack size. */ 78#define PR_SETSTACKSIZE 3 /* Set largest task stack size. */
79#define PR_GETSTACKSIZE 4 /* Get largest task stack size. */ 79#define PR_GETSTACKSIZE 4 /* Get largest task stack size. */
80#define PR_MAXPPROCS 5 /* Num parallel tasks. */ 80#define PR_MAXPPROCS 5 /* Num parallel tasks. */
81#define PR_UNBLKONEXEC 6 /* When task exec/exit's, unblock. */ 81#define PR_UNBLKONEXEC 6 /* When task exec/exit's, unblock. */
82#define PR_SETEXITSIG 8 /* When task exit's, set signal. */ 82#define PR_SETEXITSIG 8 /* When task exit's, set signal. */
83#define PR_RESIDENT 9 /* Make task unswappable. */ 83#define PR_RESIDENT 9 /* Make task unswappable. */
84#define PR_ATTACHADDR 10 /* (Re-)Connect a vma to a task. */ 84#define PR_ATTACHADDR 10 /* (Re-)Connect a vma to a task. */
85#define PR_DETACHADDR 11 /* Disconnect a vma from a task. */ 85#define PR_DETACHADDR 11 /* Disconnect a vma from a task. */
86#define PR_TERMCHILD 12 /* When parent sleeps with fishes, kill child. */ 86#define PR_TERMCHILD 12 /* Kill child if the parent dies. */
87#define PR_GETSHMASK 13 /* Get the sproc() share mask. */ 87#define PR_GETSHMASK 13 /* Get the sproc() share mask. */
88#define PR_GETNSHARE 14 /* Number of share group members. */ 88#define PR_GETNSHARE 14 /* Number of share group members. */
89#define PR_COREPID 15 /* Add task pid to name when it core. */ 89#define PR_COREPID 15 /* Add task pid to name when it core. */
90#define PR_ATTACHADDRPERM 16 /* (Re-)Connect vma, with specified prot. */ 90#define PR_ATTACHADDRPERM 16 /* (Re-)Connect vma, with specified prot. */
91#define PR_PTHREADEXIT 17 /* Kill a pthread without prejudice. */ 91#define PR_PTHREADEXIT 17 /* Kill a pthread, only for IRIX 6.[234] */
92 92
93asmlinkage int irix_prctl(struct pt_regs *regs) 93asmlinkage int irix_prctl(unsigned option, ...)
94{ 94{
95 unsigned long cmd; 95 va_list args;
96 int error = 0, base = 0; 96 int error = 0;
97 97
98 if (regs->regs[2] == 1000) 98 va_start(args, option);
99 base = 1; 99 switch (option) {
100 cmd = regs->regs[base + 4];
101 switch (cmd) {
102 case PR_MAXPROCS: 100 case PR_MAXPROCS:
103 printk("irix_prctl[%s:%d]: Wants PR_MAXPROCS\n", 101 printk("irix_prctl[%s:%d]: Wants PR_MAXPROCS\n",
104 current->comm, current->pid); 102 current->comm, current->pid);
@@ -111,7 +109,7 @@ asmlinkage int irix_prctl(struct pt_regs *regs)
111 printk("irix_prctl[%s:%d]: Wants PR_ISBLOCKED\n", 109 printk("irix_prctl[%s:%d]: Wants PR_ISBLOCKED\n",
112 current->comm, current->pid); 110 current->comm, current->pid);
113 read_lock(&tasklist_lock); 111 read_lock(&tasklist_lock);
114 task = find_task_by_pid(regs->regs[base + 5]); 112 task = find_task_by_pid(va_arg(args, pid_t));
115 error = -ESRCH; 113 error = -ESRCH;
116 if (error) 114 if (error)
117 error = (task->run_list.next != NULL); 115 error = (task->run_list.next != NULL);
@@ -121,7 +119,7 @@ asmlinkage int irix_prctl(struct pt_regs *regs)
121 } 119 }
122 120
123 case PR_SETSTACKSIZE: { 121 case PR_SETSTACKSIZE: {
124 long value = regs->regs[base + 5]; 122 long value = va_arg(args, long);
125 123
126 printk("irix_prctl[%s:%d]: Wants PR_SETSTACKSIZE<%08lx>\n", 124 printk("irix_prctl[%s:%d]: Wants PR_SETSTACKSIZE<%08lx>\n",
127 current->comm, current->pid, (unsigned long) value); 125 current->comm, current->pid, (unsigned long) value);
@@ -222,24 +220,20 @@ asmlinkage int irix_prctl(struct pt_regs *regs)
222 error = -EINVAL; 220 error = -EINVAL;
223 break; 221 break;
224 222
225 case PR_PTHREADEXIT:
226 printk("irix_prctl[%s:%d]: Wants PR_PTHREADEXIT\n",
227 current->comm, current->pid);
228 do_exit(regs->regs[base + 5]);
229
230 default: 223 default:
231 printk("irix_prctl[%s:%d]: Non-existant opcode %d\n", 224 printk("irix_prctl[%s:%d]: Non-existant opcode %d\n",
232 current->comm, current->pid, (int)cmd); 225 current->comm, current->pid, option);
233 error = -EINVAL; 226 error = -EINVAL;
234 break; 227 break;
235 } 228 }
229 va_end(args);
236 230
237 return error; 231 return error;
238} 232}
239 233
240#undef DEBUG_PROCGRPS 234#undef DEBUG_PROCGRPS
241 235
242extern unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt); 236extern unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt);
243extern int getrusage(struct task_struct *p, int who, struct rusage __user *ru); 237extern int getrusage(struct task_struct *p, int who, struct rusage __user *ru);
244extern char *prom_getenv(char *name); 238extern char *prom_getenv(char *name);
245extern long prom_setenv(char *name, char *value); 239extern long prom_setenv(char *name, char *value);
@@ -276,23 +270,19 @@ asmlinkage int irix_syssgi(struct pt_regs *regs)
276 cmd = regs->regs[base + 4]; 270 cmd = regs->regs[base + 4];
277 switch(cmd) { 271 switch(cmd) {
278 case SGI_SYSID: { 272 case SGI_SYSID: {
279 char *buf = (char *) regs->regs[base + 5]; 273 char __user *buf = (char __user *) regs->regs[base + 5];
280 274
281 /* XXX Use ethernet addr.... */ 275 /* XXX Use ethernet addr.... */
282 retval = clear_user(buf, 64); 276 retval = clear_user(buf, 64) ? -EFAULT : 0;
283 break; 277 break;
284 } 278 }
285#if 0 279#if 0
286 case SGI_RDNAME: { 280 case SGI_RDNAME: {
287 int pid = (int) regs->regs[base + 5]; 281 int pid = (int) regs->regs[base + 5];
288 char *buf = (char *) regs->regs[base + 6]; 282 char __user *buf = (char __user *) regs->regs[base + 6];
289 struct task_struct *p; 283 struct task_struct *p;
290 char tcomm[sizeof(current->comm)]; 284 char tcomm[sizeof(current->comm)];
291 285
292 if (!access_ok(VERIFY_WRITE, buf, sizeof(tcomm))) {
293 retval = -EFAULT;
294 break;
295 }
296 read_lock(&tasklist_lock); 286 read_lock(&tasklist_lock);
297 p = find_task_by_pid(pid); 287 p = find_task_by_pid(pid);
298 if (!p) { 288 if (!p) {
@@ -304,34 +294,28 @@ asmlinkage int irix_syssgi(struct pt_regs *regs)
304 read_unlock(&tasklist_lock); 294 read_unlock(&tasklist_lock);
305 295
306 /* XXX Need to check sizes. */ 296 /* XXX Need to check sizes. */
307 copy_to_user(buf, tcomm, sizeof(tcomm)); 297 retval = copy_to_user(buf, tcomm, sizeof(tcomm)) ? -EFAULT : 0;
308 retval = 0;
309 break; 298 break;
310 } 299 }
311 300
312 case SGI_GETNVRAM: { 301 case SGI_GETNVRAM: {
313 char *name = (char *) regs->regs[base+5]; 302 char __user *name = (char __user *) regs->regs[base+5];
314 char *buf = (char *) regs->regs[base+6]; 303 char __user *buf = (char __user *) regs->regs[base+6];
315 char *value; 304 char *value;
316 return -EINVAL; /* til I fix it */ 305 return -EINVAL; /* til I fix it */
317 if (!access_ok(VERIFY_WRITE, buf, 128)) {
318 retval = -EFAULT;
319 break;
320 }
321 value = prom_getenv(name); /* PROM lock? */ 306 value = prom_getenv(name); /* PROM lock? */
322 if (!value) { 307 if (!value) {
323 retval = -EINVAL; 308 retval = -EINVAL;
324 break; 309 break;
325 } 310 }
326 /* Do I strlen() for the length? */ 311 /* Do I strlen() for the length? */
327 copy_to_user(buf, value, 128); 312 retval = copy_to_user(buf, value, 128) ? -EFAULT : 0;
328 retval = 0;
329 break; 313 break;
330 } 314 }
331 315
332 case SGI_SETNVRAM: { 316 case SGI_SETNVRAM: {
333 char *name = (char *) regs->regs[base+5]; 317 char __user *name = (char __user *) regs->regs[base+5];
334 char *value = (char *) regs->regs[base+6]; 318 char __user *value = (char __user *) regs->regs[base+6];
335 return -EINVAL; /* til I fix it */ 319 return -EINVAL; /* til I fix it */
336 retval = prom_setenv(name, value); 320 retval = prom_setenv(name, value);
337 /* XXX make sure retval conforms to syssgi(2) */ 321 /* XXX make sure retval conforms to syssgi(2) */
@@ -407,16 +391,16 @@ asmlinkage int irix_syssgi(struct pt_regs *regs)
407 391
408 case SGI_SETGROUPS: 392 case SGI_SETGROUPS:
409 retval = sys_setgroups((int) regs->regs[base + 5], 393 retval = sys_setgroups((int) regs->regs[base + 5],
410 (gid_t *) regs->regs[base + 6]); 394 (gid_t __user *) regs->regs[base + 6]);
411 break; 395 break;
412 396
413 case SGI_GETGROUPS: 397 case SGI_GETGROUPS:
414 retval = sys_getgroups((int) regs->regs[base + 5], 398 retval = sys_getgroups((int) regs->regs[base + 5],
415 (gid_t *) regs->regs[base + 6]); 399 (gid_t __user *) regs->regs[base + 6]);
416 break; 400 break;
417 401
418 case SGI_RUSAGE: { 402 case SGI_RUSAGE: {
419 struct rusage *ru = (struct rusage *) regs->regs[base + 6]; 403 struct rusage __user *ru = (struct rusage __user *) regs->regs[base + 6];
420 404
421 switch((int) regs->regs[base + 5]) { 405 switch((int) regs->regs[base + 5]) {
422 case 0: 406 case 0:
@@ -453,7 +437,7 @@ asmlinkage int irix_syssgi(struct pt_regs *regs)
453 437
454 case SGI_ELFMAP: 438 case SGI_ELFMAP:
455 retval = irix_mapelf((int) regs->regs[base + 5], 439 retval = irix_mapelf((int) regs->regs[base + 5],
456 (struct elf_phdr *) regs->regs[base + 6], 440 (struct elf_phdr __user *) regs->regs[base + 6],
457 (int) regs->regs[base + 7]); 441 (int) regs->regs[base + 7]);
458 break; 442 break;
459 443
@@ -468,24 +452,24 @@ asmlinkage int irix_syssgi(struct pt_regs *regs)
468 452
469 case SGI_PHYSP: { 453 case SGI_PHYSP: {
470 unsigned long addr = regs->regs[base + 5]; 454 unsigned long addr = regs->regs[base + 5];
471 int *pageno = (int *) (regs->regs[base + 6]); 455 int __user *pageno = (int __user *) (regs->regs[base + 6]);
472 struct mm_struct *mm = current->mm; 456 struct mm_struct *mm = current->mm;
473 pgd_t *pgdp; 457 pgd_t *pgdp;
458 pud_t *pudp;
474 pmd_t *pmdp; 459 pmd_t *pmdp;
475 pte_t *ptep; 460 pte_t *ptep;
476 461
477 if (!access_ok(VERIFY_WRITE, pageno, sizeof(int)))
478 return -EFAULT;
479
480 down_read(&mm->mmap_sem); 462 down_read(&mm->mmap_sem);
481 pgdp = pgd_offset(mm, addr); 463 pgdp = pgd_offset(mm, addr);
482 pmdp = pmd_offset(pgdp, addr); 464 pudp = pud_offset(pgdp, addr);
465 pmdp = pmd_offset(pudp, addr);
483 ptep = pte_offset(pmdp, addr); 466 ptep = pte_offset(pmdp, addr);
484 retval = -EINVAL; 467 retval = -EINVAL;
485 if (ptep) { 468 if (ptep) {
486 pte_t pte = *ptep; 469 pte_t pte = *ptep;
487 470
488 if (pte_val(pte) & (_PAGE_VALID | _PAGE_PRESENT)) { 471 if (pte_val(pte) & (_PAGE_VALID | _PAGE_PRESENT)) {
472 /* b0rked on 64-bit */
489 retval = put_user((pte_val(pte) & PAGE_MASK) >> 473 retval = put_user((pte_val(pte) & PAGE_MASK) >>
490 PAGE_SHIFT, pageno); 474 PAGE_SHIFT, pageno);
491 } 475 }
@@ -496,7 +480,7 @@ asmlinkage int irix_syssgi(struct pt_regs *regs)
496 480
497 case SGI_INVENT: { 481 case SGI_INVENT: {
498 int arg1 = (int) regs->regs [base + 5]; 482 int arg1 = (int) regs->regs [base + 5];
499 void *buffer = (void *) regs->regs [base + 6]; 483 void __user *buffer = (void __user *) regs->regs [base + 6];
500 int count = (int) regs->regs [base + 7]; 484 int count = (int) regs->regs [base + 7];
501 485
502 switch (arg1) { 486 switch (arg1) {
@@ -692,8 +676,8 @@ asmlinkage int irix_pause(void)
692} 676}
693 677
694/* XXX need more than this... */ 678/* XXX need more than this... */
695asmlinkage int irix_mount(char *dev_name, char *dir_name, unsigned long flags, 679asmlinkage int irix_mount(char __user *dev_name, char __user *dir_name,
696 char *type, void *data, int datalen) 680 unsigned long flags, char __user *type, void __user *data, int datalen)
697{ 681{
698 printk("[%s:%d] irix_mount(%p,%p,%08lx,%p,%p,%d)\n", 682 printk("[%s:%d] irix_mount(%p,%p,%08lx,%p,%p,%d)\n",
699 current->comm, current->pid, 683 current->comm, current->pid,
@@ -708,8 +692,8 @@ struct irix_statfs {
708 char f_fname[6], f_fpack[6]; 692 char f_fname[6], f_fpack[6];
709}; 693};
710 694
711asmlinkage int irix_statfs(const char *path, struct irix_statfs *buf, 695asmlinkage int irix_statfs(const char __user *path,
712 int len, int fs_type) 696 struct irix_statfs __user *buf, int len, int fs_type)
713{ 697{
714 struct nameidata nd; 698 struct nameidata nd;
715 struct kstatfs kbuf; 699 struct kstatfs kbuf;
@@ -724,6 +708,7 @@ asmlinkage int irix_statfs(const char *path, struct irix_statfs *buf,
724 error = -EFAULT; 708 error = -EFAULT;
725 goto out; 709 goto out;
726 } 710 }
711
727 error = user_path_walk(path, &nd); 712 error = user_path_walk(path, &nd);
728 if (error) 713 if (error)
729 goto out; 714 goto out;
@@ -732,18 +717,17 @@ asmlinkage int irix_statfs(const char *path, struct irix_statfs *buf,
732 if (error) 717 if (error)
733 goto dput_and_out; 718 goto dput_and_out;
734 719
735 __put_user(kbuf.f_type, &buf->f_type); 720 error = __put_user(kbuf.f_type, &buf->f_type);
736 __put_user(kbuf.f_bsize, &buf->f_bsize); 721 error |= __put_user(kbuf.f_bsize, &buf->f_bsize);
737 __put_user(kbuf.f_frsize, &buf->f_frsize); 722 error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
738 __put_user(kbuf.f_blocks, &buf->f_blocks); 723 error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
739 __put_user(kbuf.f_bfree, &buf->f_bfree); 724 error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
740 __put_user(kbuf.f_files, &buf->f_files); 725 error |= __put_user(kbuf.f_files, &buf->f_files);
741 __put_user(kbuf.f_ffree, &buf->f_ffree); 726 error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
742 for (i = 0; i < 6; i++) { 727 for (i = 0; i < 6; i++) {
743 __put_user(0, &buf->f_fname[i]); 728 error |= __put_user(0, &buf->f_fname[i]);
744 __put_user(0, &buf->f_fpack[i]); 729 error |= __put_user(0, &buf->f_fpack[i]);
745 } 730 }
746 error = 0;
747 731
748dput_and_out: 732dput_and_out:
749 path_release(&nd); 733 path_release(&nd);
@@ -751,7 +735,7 @@ out:
751 return error; 735 return error;
752} 736}
753 737
754asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs *buf) 738asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs __user *buf)
755{ 739{
756 struct kstatfs kbuf; 740 struct kstatfs kbuf;
757 struct file *file; 741 struct file *file;
@@ -761,6 +745,7 @@ asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs *buf)
761 error = -EFAULT; 745 error = -EFAULT;
762 goto out; 746 goto out;
763 } 747 }
748
764 if (!(file = fget(fd))) { 749 if (!(file = fget(fd))) {
765 error = -EBADF; 750 error = -EBADF;
766 goto out; 751 goto out;
@@ -770,16 +755,17 @@ asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs *buf)
770 if (error) 755 if (error)
771 goto out_f; 756 goto out_f;
772 757
773 __put_user(kbuf.f_type, &buf->f_type); 758 error = __put_user(kbuf.f_type, &buf->f_type);
774 __put_user(kbuf.f_bsize, &buf->f_bsize); 759 error |= __put_user(kbuf.f_bsize, &buf->f_bsize);
775 __put_user(kbuf.f_frsize, &buf->f_frsize); 760 error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
776 __put_user(kbuf.f_blocks, &buf->f_blocks); 761 error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
777 __put_user(kbuf.f_bfree, &buf->f_bfree); 762 error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
778 __put_user(kbuf.f_files, &buf->f_files); 763 error |= __put_user(kbuf.f_files, &buf->f_files);
779 __put_user(kbuf.f_ffree, &buf->f_ffree); 764 error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
780 for(i = 0; i < 6; i++) { 765
781 __put_user(0, &buf->f_fname[i]); 766 for (i = 0; i < 6; i++) {
782 __put_user(0, &buf->f_fpack[i]); 767 error |= __put_user(0, &buf->f_fname[i]);
768 error |= __put_user(0, &buf->f_fpack[i]);
783 } 769 }
784 770
785out_f: 771out_f:
@@ -806,14 +792,15 @@ asmlinkage int irix_setpgrp(int flags)
806 return error; 792 return error;
807} 793}
808 794
809asmlinkage int irix_times(struct tms * tbuf) 795asmlinkage int irix_times(struct tms __user *tbuf)
810{ 796{
811 int err = 0; 797 int err = 0;
812 798
813 if (tbuf) { 799 if (tbuf) {
814 if (!access_ok(VERIFY_WRITE,tbuf,sizeof *tbuf)) 800 if (!access_ok(VERIFY_WRITE,tbuf,sizeof *tbuf))
815 return -EFAULT; 801 return -EFAULT;
816 err |= __put_user(current->utime, &tbuf->tms_utime); 802
803 err = __put_user(current->utime, &tbuf->tms_utime);
817 err |= __put_user(current->stime, &tbuf->tms_stime); 804 err |= __put_user(current->stime, &tbuf->tms_stime);
818 err |= __put_user(current->signal->cutime, &tbuf->tms_cutime); 805 err |= __put_user(current->signal->cutime, &tbuf->tms_cutime);
819 err |= __put_user(current->signal->cstime, &tbuf->tms_cstime); 806 err |= __put_user(current->signal->cstime, &tbuf->tms_cstime);
@@ -829,13 +816,13 @@ asmlinkage int irix_exec(struct pt_regs *regs)
829 816
830 if(regs->regs[2] == 1000) 817 if(regs->regs[2] == 1000)
831 base = 1; 818 base = 1;
832 filename = getname((char *) (long)regs->regs[base + 4]); 819 filename = getname((char __user *) (long)regs->regs[base + 4]);
833 error = PTR_ERR(filename); 820 error = PTR_ERR(filename);
834 if (IS_ERR(filename)) 821 if (IS_ERR(filename))
835 return error; 822 return error;
836 823
837 error = do_execve(filename, (char **) (long)regs->regs[base + 5], 824 error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5],
838 (char **) 0, regs); 825 NULL, regs);
839 putname(filename); 826 putname(filename);
840 827
841 return error; 828 return error;
@@ -848,12 +835,12 @@ asmlinkage int irix_exece(struct pt_regs *regs)
848 835
849 if (regs->regs[2] == 1000) 836 if (regs->regs[2] == 1000)
850 base = 1; 837 base = 1;
851 filename = getname((char *) (long)regs->regs[base + 4]); 838 filename = getname((char __user *) (long)regs->regs[base + 4]);
852 error = PTR_ERR(filename); 839 error = PTR_ERR(filename);
853 if (IS_ERR(filename)) 840 if (IS_ERR(filename))
854 return error; 841 return error;
855 error = do_execve(filename, (char **) (long)regs->regs[base + 5], 842 error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5],
856 (char **) (long)regs->regs[base + 6], regs); 843 (char __user * __user *) (long)regs->regs[base + 6], regs);
857 putname(filename); 844 putname(filename);
858 845
859 return error; 846 return error;
@@ -909,22 +896,17 @@ asmlinkage int irix_socket(int family, int type, int protocol)
909 return sys_socket(family, type, protocol); 896 return sys_socket(family, type, protocol);
910} 897}
911 898
912asmlinkage int irix_getdomainname(char *name, int len) 899asmlinkage int irix_getdomainname(char __user *name, int len)
913{ 900{
914 int error; 901 int err;
915
916 if (!access_ok(VERIFY_WRITE, name, len))
917 return -EFAULT;
918 902
919 down_read(&uts_sem); 903 down_read(&uts_sem);
920 if (len > __NEW_UTS_LEN) 904 if (len > __NEW_UTS_LEN)
921 len = __NEW_UTS_LEN; 905 len = __NEW_UTS_LEN;
922 error = 0; 906 err = copy_to_user(name, system_utsname.domainname, len) ? -EFAULT : 0;
923 if (copy_to_user(name, system_utsname.domainname, len))
924 error = -EFAULT;
925 up_read(&uts_sem); 907 up_read(&uts_sem);
926 908
927 return error; 909 return err;
928} 910}
929 911
930asmlinkage unsigned long irix_getpagesize(void) 912asmlinkage unsigned long irix_getpagesize(void)
@@ -940,12 +922,13 @@ asmlinkage int irix_msgsys(int opcode, unsigned long arg0, unsigned long arg1,
940 case 0: 922 case 0:
941 return sys_msgget((key_t) arg0, (int) arg1); 923 return sys_msgget((key_t) arg0, (int) arg1);
942 case 1: 924 case 1:
943 return sys_msgctl((int) arg0, (int) arg1, (struct msqid_ds *)arg2); 925 return sys_msgctl((int) arg0, (int) arg1,
926 (struct msqid_ds __user *)arg2);
944 case 2: 927 case 2:
945 return sys_msgrcv((int) arg0, (struct msgbuf *) arg1, 928 return sys_msgrcv((int) arg0, (struct msgbuf __user *) arg1,
946 (size_t) arg2, (long) arg3, (int) arg4); 929 (size_t) arg2, (long) arg3, (int) arg4);
947 case 3: 930 case 3:
948 return sys_msgsnd((int) arg0, (struct msgbuf *) arg1, 931 return sys_msgsnd((int) arg0, (struct msgbuf __user *) arg1,
949 (size_t) arg2, (int) arg3); 932 (size_t) arg2, (int) arg3);
950 default: 933 default:
951 return -EINVAL; 934 return -EINVAL;
@@ -957,12 +940,13 @@ asmlinkage int irix_shmsys(int opcode, unsigned long arg0, unsigned long arg1,
957{ 940{
958 switch (opcode) { 941 switch (opcode) {
959 case 0: 942 case 0:
960 return do_shmat((int) arg0, (char *)arg1, (int) arg2, 943 return do_shmat((int) arg0, (char __user *) arg1, (int) arg2,
961 (unsigned long *) arg3); 944 (unsigned long *) arg3);
962 case 1: 945 case 1:
963 return sys_shmctl((int)arg0, (int)arg1, (struct shmid_ds *)arg2); 946 return sys_shmctl((int)arg0, (int)arg1,
947 (struct shmid_ds __user *)arg2);
964 case 2: 948 case 2:
965 return sys_shmdt((char *)arg0); 949 return sys_shmdt((char __user *)arg0);
966 case 3: 950 case 3:
967 return sys_shmget((key_t) arg0, (int) arg1, (int) arg2); 951 return sys_shmget((key_t) arg0, (int) arg1, (int) arg2);
968 default: 952 default:
@@ -980,7 +964,7 @@ asmlinkage int irix_semsys(int opcode, unsigned long arg0, unsigned long arg1,
980 case 1: 964 case 1:
981 return sys_semget((key_t) arg0, (int) arg1, (int) arg2); 965 return sys_semget((key_t) arg0, (int) arg1, (int) arg2);
982 case 2: 966 case 2:
983 return sys_semop((int) arg0, (struct sembuf *)arg1, 967 return sys_semop((int) arg0, (struct sembuf __user *)arg1,
984 (unsigned int) arg2); 968 (unsigned int) arg2);
985 default: 969 default:
986 return -EINVAL; 970 return -EINVAL;
@@ -998,15 +982,16 @@ static inline loff_t llseek(struct file *file, loff_t offset, int origin)
998 lock_kernel(); 982 lock_kernel();
999 retval = fn(file, offset, origin); 983 retval = fn(file, offset, origin);
1000 unlock_kernel(); 984 unlock_kernel();
985
1001 return retval; 986 return retval;
1002} 987}
1003 988
1004asmlinkage int irix_lseek64(int fd, int _unused, int offhi, int offlow, 989asmlinkage int irix_lseek64(int fd, int _unused, int offhi, int offlow,
1005 int origin) 990 int origin)
1006{ 991{
1007 int retval;
1008 struct file * file; 992 struct file * file;
1009 loff_t offset; 993 loff_t offset;
994 int retval;
1010 995
1011 retval = -EBADF; 996 retval = -EBADF;
1012 file = fget(fd); 997 file = fget(fd);
@@ -1031,12 +1016,12 @@ asmlinkage int irix_sginap(int ticks)
1031 return 0; 1016 return 0;
1032} 1017}
1033 1018
1034asmlinkage int irix_sgikopt(char *istring, char *ostring, int len) 1019asmlinkage int irix_sgikopt(char __user *istring, char __user *ostring, int len)
1035{ 1020{
1036 return -EINVAL; 1021 return -EINVAL;
1037} 1022}
1038 1023
1039asmlinkage int irix_gettimeofday(struct timeval *tv) 1024asmlinkage int irix_gettimeofday(struct timeval __user *tv)
1040{ 1025{
1041 time_t sec; 1026 time_t sec;
1042 long nsec, seq; 1027 long nsec, seq;
@@ -1077,7 +1062,7 @@ asmlinkage unsigned long irix_mmap32(unsigned long addr, size_t len, int prot,
1077 1062
1078 if (max_size > file->f_dentry->d_inode->i_size) { 1063 if (max_size > file->f_dentry->d_inode->i_size) {
1079 old_pos = sys_lseek (fd, max_size - 1, 0); 1064 old_pos = sys_lseek (fd, max_size - 1, 0);
1080 sys_write (fd, "", 1); 1065 sys_write (fd, (void __user *) "", 1);
1081 sys_lseek (fd, old_pos, 0); 1066 sys_lseek (fd, old_pos, 0);
1082 } 1067 }
1083 } 1068 }
@@ -1102,7 +1087,7 @@ asmlinkage int irix_madvise(unsigned long addr, int len, int behavior)
1102 return -EINVAL; 1087 return -EINVAL;
1103} 1088}
1104 1089
1105asmlinkage int irix_pagelock(char *addr, int len, int op) 1090asmlinkage int irix_pagelock(char __user *addr, int len, int op)
1106{ 1091{
1107 printk("[%s:%d] Wheee.. irix_pagelock(%p,%d,%d)\n", 1092 printk("[%s:%d] Wheee.. irix_pagelock(%p,%d,%d)\n",
1108 current->comm, current->pid, addr, len, op); 1093 current->comm, current->pid, addr, len, op);
@@ -1142,7 +1127,7 @@ asmlinkage int irix_BSDsetpgrp(int pid, int pgrp)
1142 return error; 1127 return error;
1143} 1128}
1144 1129
1145asmlinkage int irix_systeminfo(int cmd, char *buf, int cnt) 1130asmlinkage int irix_systeminfo(int cmd, char __user *buf, int cnt)
1146{ 1131{
1147 printk("[%s:%d] Wheee.. irix_systeminfo(%d,%p,%d)\n", 1132 printk("[%s:%d] Wheee.. irix_systeminfo(%d,%p,%d)\n",
1148 current->comm, current->pid, cmd, buf, cnt); 1133 current->comm, current->pid, cmd, buf, cnt);
@@ -1158,14 +1143,14 @@ struct iuname {
1158 char _unused3[257], _unused4[257], _unused5[257]; 1143 char _unused3[257], _unused4[257], _unused5[257];
1159}; 1144};
1160 1145
1161asmlinkage int irix_uname(struct iuname *buf) 1146asmlinkage int irix_uname(struct iuname __user *buf)
1162{ 1147{
1163 down_read(&uts_sem); 1148 down_read(&uts_sem);
1164 if (copy_to_user(system_utsname.sysname, buf->sysname, 65) 1149 if (copy_from_user(system_utsname.sysname, buf->sysname, 65)
1165 || copy_to_user(system_utsname.nodename, buf->nodename, 65) 1150 || copy_from_user(system_utsname.nodename, buf->nodename, 65)
1166 || copy_to_user(system_utsname.release, buf->release, 65) 1151 || copy_from_user(system_utsname.release, buf->release, 65)
1167 || copy_to_user(system_utsname.version, buf->version, 65) 1152 || copy_from_user(system_utsname.version, buf->version, 65)
1168 || copy_to_user(system_utsname.machine, buf->machine, 65)) { 1153 || copy_from_user(system_utsname.machine, buf->machine, 65)) {
1169 return -EFAULT; 1154 return -EFAULT;
1170 } 1155 }
1171 up_read(&uts_sem); 1156 up_read(&uts_sem);
@@ -1175,7 +1160,7 @@ asmlinkage int irix_uname(struct iuname *buf)
1175 1160
1176#undef DEBUG_XSTAT 1161#undef DEBUG_XSTAT
1177 1162
1178static int irix_xstat32_xlate(struct kstat *stat, void *ubuf) 1163static int irix_xstat32_xlate(struct kstat *stat, void __user *ubuf)
1179{ 1164{
1180 struct xstat32 { 1165 struct xstat32 {
1181 u32 st_dev, st_pad1[3], st_ino, st_mode, st_nlink, st_uid, st_gid; 1166 u32 st_dev, st_pad1[3], st_ino, st_mode, st_nlink, st_uid, st_gid;
@@ -1215,7 +1200,7 @@ static int irix_xstat32_xlate(struct kstat *stat, void *ubuf)
1215 return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0; 1200 return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0;
1216} 1201}
1217 1202
1218static int irix_xstat64_xlate(struct kstat *stat, void *ubuf) 1203static int irix_xstat64_xlate(struct kstat *stat, void __user *ubuf)
1219{ 1204{
1220 struct xstat64 { 1205 struct xstat64 {
1221 u32 st_dev; s32 st_pad1[3]; 1206 u32 st_dev; s32 st_pad1[3];
@@ -1265,7 +1250,7 @@ static int irix_xstat64_xlate(struct kstat *stat, void *ubuf)
1265 return copy_to_user(ubuf, &ks, sizeof(ks)) ? -EFAULT : 0; 1250 return copy_to_user(ubuf, &ks, sizeof(ks)) ? -EFAULT : 0;
1266} 1251}
1267 1252
1268asmlinkage int irix_xstat(int version, char *filename, struct stat *statbuf) 1253asmlinkage int irix_xstat(int version, char __user *filename, struct stat __user *statbuf)
1269{ 1254{
1270 int retval; 1255 int retval;
1271 struct kstat stat; 1256 struct kstat stat;
@@ -1291,7 +1276,7 @@ asmlinkage int irix_xstat(int version, char *filename, struct stat *statbuf)
1291 return retval; 1276 return retval;
1292} 1277}
1293 1278
1294asmlinkage int irix_lxstat(int version, char *filename, struct stat *statbuf) 1279asmlinkage int irix_lxstat(int version, char __user *filename, struct stat __user *statbuf)
1295{ 1280{
1296 int error; 1281 int error;
1297 struct kstat stat; 1282 struct kstat stat;
@@ -1318,7 +1303,7 @@ asmlinkage int irix_lxstat(int version, char *filename, struct stat *statbuf)
1318 return error; 1303 return error;
1319} 1304}
1320 1305
1321asmlinkage int irix_fxstat(int version, int fd, struct stat *statbuf) 1306asmlinkage int irix_fxstat(int version, int fd, struct stat __user *statbuf)
1322{ 1307{
1323 int error; 1308 int error;
1324 struct kstat stat; 1309 struct kstat stat;
@@ -1344,7 +1329,7 @@ asmlinkage int irix_fxstat(int version, int fd, struct stat *statbuf)
1344 return error; 1329 return error;
1345} 1330}
1346 1331
1347asmlinkage int irix_xmknod(int ver, char *filename, int mode, unsigned dev) 1332asmlinkage int irix_xmknod(int ver, char __user *filename, int mode, unsigned dev)
1348{ 1333{
1349 int retval; 1334 int retval;
1350 printk("[%s:%d] Wheee.. irix_xmknod(%d,%s,%x,%x)\n", 1335 printk("[%s:%d] Wheee.. irix_xmknod(%d,%s,%x,%x)\n",
@@ -1364,7 +1349,7 @@ asmlinkage int irix_xmknod(int ver, char *filename, int mode, unsigned dev)
1364 return retval; 1349 return retval;
1365} 1350}
1366 1351
1367asmlinkage int irix_swapctl(int cmd, char *arg) 1352asmlinkage int irix_swapctl(int cmd, char __user *arg)
1368{ 1353{
1369 printk("[%s:%d] Wheee.. irix_swapctl(%d,%p)\n", 1354 printk("[%s:%d] Wheee.. irix_swapctl(%d,%p)\n",
1370 current->comm, current->pid, cmd, arg); 1355 current->comm, current->pid, cmd, arg);
@@ -1380,7 +1365,7 @@ struct irix_statvfs {
1380 char f_fstr[32]; u32 f_filler[16]; 1365 char f_fstr[32]; u32 f_filler[16];
1381}; 1366};
1382 1367
1383asmlinkage int irix_statvfs(char *fname, struct irix_statvfs *buf) 1368asmlinkage int irix_statvfs(char __user *fname, struct irix_statvfs __user *buf)
1384{ 1369{
1385 struct nameidata nd; 1370 struct nameidata nd;
1386 struct kstatfs kbuf; 1371 struct kstatfs kbuf;
@@ -1388,10 +1373,9 @@ asmlinkage int irix_statvfs(char *fname, struct irix_statvfs *buf)
1388 1373
1389 printk("[%s:%d] Wheee.. irix_statvfs(%s,%p)\n", 1374 printk("[%s:%d] Wheee.. irix_statvfs(%s,%p)\n",
1390 current->comm, current->pid, fname, buf); 1375 current->comm, current->pid, fname, buf);
1391 if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) { 1376 if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs)))
1392 error = -EFAULT; 1377 return -EFAULT;
1393 goto out; 1378
1394 }
1395 error = user_path_walk(fname, &nd); 1379 error = user_path_walk(fname, &nd);
1396 if (error) 1380 if (error)
1397 goto out; 1381 goto out;
@@ -1399,27 +1383,25 @@ asmlinkage int irix_statvfs(char *fname, struct irix_statvfs *buf)
1399 if (error) 1383 if (error)
1400 goto dput_and_out; 1384 goto dput_and_out;
1401 1385
1402 __put_user(kbuf.f_bsize, &buf->f_bsize); 1386 error |= __put_user(kbuf.f_bsize, &buf->f_bsize);
1403 __put_user(kbuf.f_frsize, &buf->f_frsize); 1387 error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
1404 __put_user(kbuf.f_blocks, &buf->f_blocks); 1388 error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
1405 __put_user(kbuf.f_bfree, &buf->f_bfree); 1389 error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
1406 __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ 1390 error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
1407 __put_user(kbuf.f_files, &buf->f_files); 1391 error |= __put_user(kbuf.f_files, &buf->f_files);
1408 __put_user(kbuf.f_ffree, &buf->f_ffree); 1392 error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
1409 __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ 1393 error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
1410#ifdef __MIPSEB__ 1394#ifdef __MIPSEB__
1411 __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); 1395 error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
1412#else 1396#else
1413 __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); 1397 error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
1414#endif 1398#endif
1415 for (i = 0; i < 16; i++) 1399 for (i = 0; i < 16; i++)
1416 __put_user(0, &buf->f_basetype[i]); 1400 error |= __put_user(0, &buf->f_basetype[i]);
1417 __put_user(0, &buf->f_flag); 1401 error |= __put_user(0, &buf->f_flag);
1418 __put_user(kbuf.f_namelen, &buf->f_namemax); 1402 error |= __put_user(kbuf.f_namelen, &buf->f_namemax);
1419 for (i = 0; i < 32; i++) 1403 for (i = 0; i < 32; i++)
1420 __put_user(0, &buf->f_fstr[i]); 1404 error |= __put_user(0, &buf->f_fstr[i]);
1421
1422 error = 0;
1423 1405
1424dput_and_out: 1406dput_and_out:
1425 path_release(&nd); 1407 path_release(&nd);
@@ -1427,7 +1409,7 @@ out:
1427 return error; 1409 return error;
1428} 1410}
1429 1411
1430asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs *buf) 1412asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs __user *buf)
1431{ 1413{
1432 struct kstatfs kbuf; 1414 struct kstatfs kbuf;
1433 struct file *file; 1415 struct file *file;
@@ -1436,10 +1418,9 @@ asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs *buf)
1436 printk("[%s:%d] Wheee.. irix_fstatvfs(%d,%p)\n", 1418 printk("[%s:%d] Wheee.. irix_fstatvfs(%d,%p)\n",
1437 current->comm, current->pid, fd, buf); 1419 current->comm, current->pid, fd, buf);
1438 1420
1439 if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) { 1421 if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs)))
1440 error = -EFAULT; 1422 return -EFAULT;
1441 goto out; 1423
1442 }
1443 if (!(file = fget(fd))) { 1424 if (!(file = fget(fd))) {
1444 error = -EBADF; 1425 error = -EBADF;
1445 goto out; 1426 goto out;
@@ -1448,24 +1429,24 @@ asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs *buf)
1448 if (error) 1429 if (error)
1449 goto out_f; 1430 goto out_f;
1450 1431
1451 __put_user(kbuf.f_bsize, &buf->f_bsize); 1432 error = __put_user(kbuf.f_bsize, &buf->f_bsize);
1452 __put_user(kbuf.f_frsize, &buf->f_frsize); 1433 error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
1453 __put_user(kbuf.f_blocks, &buf->f_blocks); 1434 error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
1454 __put_user(kbuf.f_bfree, &buf->f_bfree); 1435 error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
1455 __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ 1436 error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
1456 __put_user(kbuf.f_files, &buf->f_files); 1437 error |= __put_user(kbuf.f_files, &buf->f_files);
1457 __put_user(kbuf.f_ffree, &buf->f_ffree); 1438 error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
1458 __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ 1439 error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
1459#ifdef __MIPSEB__ 1440#ifdef __MIPSEB__
1460 __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); 1441 error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
1461#else 1442#else
1462 __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); 1443 error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
1463#endif 1444#endif
1464 for(i = 0; i < 16; i++) 1445 for(i = 0; i < 16; i++)
1465 __put_user(0, &buf->f_basetype[i]); 1446 error |= __put_user(0, &buf->f_basetype[i]);
1466 __put_user(0, &buf->f_flag); 1447 error |= __put_user(0, &buf->f_flag);
1467 __put_user(kbuf.f_namelen, &buf->f_namemax); 1448 error |= __put_user(kbuf.f_namelen, &buf->f_namemax);
1468 __clear_user(&buf->f_fstr, sizeof(buf->f_fstr)); 1449 error |= __clear_user(&buf->f_fstr, sizeof(buf->f_fstr)) ? -EFAULT : 0;
1469 1450
1470out_f: 1451out_f:
1471 fput(file); 1452 fput(file);
@@ -1489,7 +1470,7 @@ asmlinkage int irix_sigqueue(int pid, int sig, int code, int val)
1489 return -EINVAL; 1470 return -EINVAL;
1490} 1471}
1491 1472
1492asmlinkage int irix_truncate64(char *name, int pad, int size1, int size2) 1473asmlinkage int irix_truncate64(char __user *name, int pad, int size1, int size2)
1493{ 1474{
1494 int retval; 1475 int retval;
1495 1476
@@ -1522,6 +1503,7 @@ asmlinkage int irix_mmap64(struct pt_regs *regs)
1522 int len, prot, flags, fd, off1, off2, error, base = 0; 1503 int len, prot, flags, fd, off1, off2, error, base = 0;
1523 unsigned long addr, pgoff, *sp; 1504 unsigned long addr, pgoff, *sp;
1524 struct file *file = NULL; 1505 struct file *file = NULL;
1506 int err;
1525 1507
1526 if (regs->regs[2] == 1000) 1508 if (regs->regs[2] == 1000)
1527 base = 1; 1509 base = 1;
@@ -1531,36 +1513,31 @@ asmlinkage int irix_mmap64(struct pt_regs *regs)
1531 prot = regs->regs[base + 6]; 1513 prot = regs->regs[base + 6];
1532 if (!base) { 1514 if (!base) {
1533 flags = regs->regs[base + 7]; 1515 flags = regs->regs[base + 7];
1534 if (!access_ok(VERIFY_READ, sp, (4 * sizeof(unsigned long)))) { 1516 if (!access_ok(VERIFY_READ, sp, (4 * sizeof(unsigned long))))
1535 error = -EFAULT; 1517 return -EFAULT;
1536 goto out;
1537 }
1538 fd = sp[0]; 1518 fd = sp[0];
1539 __get_user(off1, &sp[1]); 1519 err = __get_user(off1, &sp[1]);
1540 __get_user(off2, &sp[2]); 1520 err |= __get_user(off2, &sp[2]);
1541 } else { 1521 } else {
1542 if (!access_ok(VERIFY_READ, sp, (5 * sizeof(unsigned long)))) { 1522 if (!access_ok(VERIFY_READ, sp, (5 * sizeof(unsigned long))))
1543 error = -EFAULT; 1523 return -EFAULT;
1544 goto out; 1524 err = __get_user(flags, &sp[0]);
1545 } 1525 err |= __get_user(fd, &sp[1]);
1546 __get_user(flags, &sp[0]); 1526 err |= __get_user(off1, &sp[2]);
1547 __get_user(fd, &sp[1]); 1527 err |= __get_user(off2, &sp[3]);
1548 __get_user(off1, &sp[2]);
1549 __get_user(off2, &sp[3]);
1550 } 1528 }
1551 1529
1552 if (off1 & PAGE_MASK) { 1530 if (err)
1553 error = -EOVERFLOW; 1531 return err;
1554 goto out; 1532
1555 } 1533 if (off1 & PAGE_MASK)
1534 return -EOVERFLOW;
1556 1535
1557 pgoff = (off1 << (32 - PAGE_SHIFT)) | (off2 >> PAGE_SHIFT); 1536 pgoff = (off1 << (32 - PAGE_SHIFT)) | (off2 >> PAGE_SHIFT);
1558 1537
1559 if (!(flags & MAP_ANONYMOUS)) { 1538 if (!(flags & MAP_ANONYMOUS)) {
1560 if (!(file = fget(fd))) { 1539 if (!(file = fget(fd)))
1561 error = -EBADF; 1540 return -EBADF;
1562 goto out;
1563 }
1564 1541
1565 /* Ok, bad taste hack follows, try to think in something else 1542 /* Ok, bad taste hack follows, try to think in something else
1566 when reading this */ 1543 when reading this */
@@ -1570,7 +1547,7 @@ asmlinkage int irix_mmap64(struct pt_regs *regs)
1570 1547
1571 if (max_size > file->f_dentry->d_inode->i_size) { 1548 if (max_size > file->f_dentry->d_inode->i_size) {
1572 old_pos = sys_lseek (fd, max_size - 1, 0); 1549 old_pos = sys_lseek (fd, max_size - 1, 0);
1573 sys_write (fd, "", 1); 1550 sys_write (fd, (void __user *) "", 1);
1574 sys_lseek (fd, old_pos, 0); 1551 sys_lseek (fd, old_pos, 0);
1575 } 1552 }
1576 } 1553 }
@@ -1585,7 +1562,6 @@ asmlinkage int irix_mmap64(struct pt_regs *regs)
1585 if (file) 1562 if (file)
1586 fput(file); 1563 fput(file);
1587 1564
1588out:
1589 return error; 1565 return error;
1590} 1566}
1591 1567
@@ -1597,7 +1573,7 @@ asmlinkage int irix_dmi(struct pt_regs *regs)
1597 return -EINVAL; 1573 return -EINVAL;
1598} 1574}
1599 1575
1600asmlinkage int irix_pread(int fd, char *buf, int cnt, int off64, 1576asmlinkage int irix_pread(int fd, char __user *buf, int cnt, int off64,
1601 int off1, int off2) 1577 int off1, int off2)
1602{ 1578{
1603 printk("[%s:%d] Wheee.. irix_pread(%d,%p,%d,%d,%d,%d)\n", 1579 printk("[%s:%d] Wheee.. irix_pread(%d,%p,%d,%d,%d,%d)\n",
@@ -1606,7 +1582,7 @@ asmlinkage int irix_pread(int fd, char *buf, int cnt, int off64,
1606 return -EINVAL; 1582 return -EINVAL;
1607} 1583}
1608 1584
1609asmlinkage int irix_pwrite(int fd, char *buf, int cnt, int off64, 1585asmlinkage int irix_pwrite(int fd, char __user *buf, int cnt, int off64,
1610 int off1, int off2) 1586 int off1, int off2)
1611{ 1587{
1612 printk("[%s:%d] Wheee.. irix_pwrite(%d,%p,%d,%d,%d,%d)\n", 1588 printk("[%s:%d] Wheee.. irix_pwrite(%d,%p,%d,%d,%d,%d)\n",
@@ -1638,7 +1614,7 @@ struct irix_statvfs64 {
1638 u32 f_filler[16]; 1614 u32 f_filler[16];
1639}; 1615};
1640 1616
1641asmlinkage int irix_statvfs64(char *fname, struct irix_statvfs64 *buf) 1617asmlinkage int irix_statvfs64(char __user *fname, struct irix_statvfs64 __user *buf)
1642{ 1618{
1643 struct nameidata nd; 1619 struct nameidata nd;
1644 struct kstatfs kbuf; 1620 struct kstatfs kbuf;
@@ -1650,6 +1626,7 @@ asmlinkage int irix_statvfs64(char *fname, struct irix_statvfs64 *buf)
1650 error = -EFAULT; 1626 error = -EFAULT;
1651 goto out; 1627 goto out;
1652 } 1628 }
1629
1653 error = user_path_walk(fname, &nd); 1630 error = user_path_walk(fname, &nd);
1654 if (error) 1631 if (error)
1655 goto out; 1632 goto out;
@@ -1657,27 +1634,25 @@ asmlinkage int irix_statvfs64(char *fname, struct irix_statvfs64 *buf)
1657 if (error) 1634 if (error)
1658 goto dput_and_out; 1635 goto dput_and_out;
1659 1636
1660 __put_user(kbuf.f_bsize, &buf->f_bsize); 1637 error = __put_user(kbuf.f_bsize, &buf->f_bsize);
1661 __put_user(kbuf.f_frsize, &buf->f_frsize); 1638 error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
1662 __put_user(kbuf.f_blocks, &buf->f_blocks); 1639 error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
1663 __put_user(kbuf.f_bfree, &buf->f_bfree); 1640 error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
1664 __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ 1641 error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
1665 __put_user(kbuf.f_files, &buf->f_files); 1642 error |= __put_user(kbuf.f_files, &buf->f_files);
1666 __put_user(kbuf.f_ffree, &buf->f_ffree); 1643 error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
1667 __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ 1644 error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
1668#ifdef __MIPSEB__ 1645#ifdef __MIPSEB__
1669 __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); 1646 error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
1670#else 1647#else
1671 __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); 1648 error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
1672#endif 1649#endif
1673 for(i = 0; i < 16; i++) 1650 for(i = 0; i < 16; i++)
1674 __put_user(0, &buf->f_basetype[i]); 1651 error |= __put_user(0, &buf->f_basetype[i]);
1675 __put_user(0, &buf->f_flag); 1652 error |= __put_user(0, &buf->f_flag);
1676 __put_user(kbuf.f_namelen, &buf->f_namemax); 1653 error |= __put_user(kbuf.f_namelen, &buf->f_namemax);
1677 for(i = 0; i < 32; i++) 1654 for(i = 0; i < 32; i++)
1678 __put_user(0, &buf->f_fstr[i]); 1655 error |= __put_user(0, &buf->f_fstr[i]);
1679
1680 error = 0;
1681 1656
1682dput_and_out: 1657dput_and_out:
1683 path_release(&nd); 1658 path_release(&nd);
@@ -1685,7 +1660,7 @@ out:
1685 return error; 1660 return error;
1686} 1661}
1687 1662
1688asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs *buf) 1663asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs __user *buf)
1689{ 1664{
1690 struct kstatfs kbuf; 1665 struct kstatfs kbuf;
1691 struct file *file; 1666 struct file *file;
@@ -1706,24 +1681,24 @@ asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs *buf)
1706 if (error) 1681 if (error)
1707 goto out_f; 1682 goto out_f;
1708 1683
1709 __put_user(kbuf.f_bsize, &buf->f_bsize); 1684 error = __put_user(kbuf.f_bsize, &buf->f_bsize);
1710 __put_user(kbuf.f_frsize, &buf->f_frsize); 1685 error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
1711 __put_user(kbuf.f_blocks, &buf->f_blocks); 1686 error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
1712 __put_user(kbuf.f_bfree, &buf->f_bfree); 1687 error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
1713 __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ 1688 error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
1714 __put_user(kbuf.f_files, &buf->f_files); 1689 error |= __put_user(kbuf.f_files, &buf->f_files);
1715 __put_user(kbuf.f_ffree, &buf->f_ffree); 1690 error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
1716 __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ 1691 error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
1717#ifdef __MIPSEB__ 1692#ifdef __MIPSEB__
1718 __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); 1693 error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
1719#else 1694#else
1720 __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); 1695 error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
1721#endif 1696#endif
1722 for(i = 0; i < 16; i++) 1697 for(i = 0; i < 16; i++)
1723 __put_user(0, &buf->f_basetype[i]); 1698 error |= __put_user(0, &buf->f_basetype[i]);
1724 __put_user(0, &buf->f_flag); 1699 error |= __put_user(0, &buf->f_flag);
1725 __put_user(kbuf.f_namelen, &buf->f_namemax); 1700 error |= __put_user(kbuf.f_namelen, &buf->f_namemax);
1726 __clear_user(buf->f_fstr, sizeof(buf->f_fstr[i])); 1701 error |= __clear_user(buf->f_fstr, sizeof(buf->f_fstr[i])) ? -EFAULT : 0;
1727 1702
1728out_f: 1703out_f:
1729 fput(file); 1704 fput(file);
@@ -1731,9 +1706,9 @@ out:
1731 return error; 1706 return error;
1732} 1707}
1733 1708
1734asmlinkage int irix_getmountid(char *fname, unsigned long *midbuf) 1709asmlinkage int irix_getmountid(char __user *fname, unsigned long __user *midbuf)
1735{ 1710{
1736 int err = 0; 1711 int err;
1737 1712
1738 printk("[%s:%d] irix_getmountid(%s, %p)\n", 1713 printk("[%s:%d] irix_getmountid(%s, %p)\n",
1739 current->comm, current->pid, fname, midbuf); 1714 current->comm, current->pid, fname, midbuf);
@@ -1746,7 +1721,7 @@ asmlinkage int irix_getmountid(char *fname, unsigned long *midbuf)
1746 * fsid of the filesystem to try and make the right decision, but 1721 * fsid of the filesystem to try and make the right decision, but
1747 * we don't have this so for now. XXX 1722 * we don't have this so for now. XXX
1748 */ 1723 */
1749 err |= __put_user(0, &midbuf[0]); 1724 err = __put_user(0, &midbuf[0]);
1750 err |= __put_user(0, &midbuf[1]); 1725 err |= __put_user(0, &midbuf[1]);
1751 err |= __put_user(0, &midbuf[2]); 1726 err |= __put_user(0, &midbuf[2]);
1752 err |= __put_user(0, &midbuf[3]); 1727 err |= __put_user(0, &midbuf[3]);
@@ -1773,8 +1748,8 @@ struct irix_dirent32 {
1773}; 1748};
1774 1749
1775struct irix_dirent32_callback { 1750struct irix_dirent32_callback {
1776 struct irix_dirent32 *current_dir; 1751 struct irix_dirent32 __user *current_dir;
1777 struct irix_dirent32 *previous; 1752 struct irix_dirent32 __user *previous;
1778 int count; 1753 int count;
1779 int error; 1754 int error;
1780}; 1755};
@@ -1782,13 +1757,13 @@ struct irix_dirent32_callback {
1782#define NAME_OFFSET32(de) ((int) ((de)->d_name - (char *) (de))) 1757#define NAME_OFFSET32(de) ((int) ((de)->d_name - (char *) (de)))
1783#define ROUND_UP32(x) (((x)+sizeof(u32)-1) & ~(sizeof(u32)-1)) 1758#define ROUND_UP32(x) (((x)+sizeof(u32)-1) & ~(sizeof(u32)-1))
1784 1759
1785static int irix_filldir32(void *__buf, const char *name, int namlen, 1760static int irix_filldir32(void *__buf, const char *name,
1786 loff_t offset, ino_t ino, unsigned int d_type) 1761 int namlen, loff_t offset, ino_t ino, unsigned int d_type)
1787{ 1762{
1788 struct irix_dirent32 *dirent; 1763 struct irix_dirent32 __user *dirent;
1789 struct irix_dirent32_callback *buf = 1764 struct irix_dirent32_callback *buf = __buf;
1790 (struct irix_dirent32_callback *)__buf;
1791 unsigned short reclen = ROUND_UP32(NAME_OFFSET32(dirent) + namlen + 1); 1765 unsigned short reclen = ROUND_UP32(NAME_OFFSET32(dirent) + namlen + 1);
1766 int err = 0;
1792 1767
1793#ifdef DEBUG_GETDENTS 1768#ifdef DEBUG_GETDENTS
1794 printk("\nirix_filldir32[reclen<%d>namlen<%d>count<%d>]", 1769 printk("\nirix_filldir32[reclen<%d>namlen<%d>count<%d>]",
@@ -1799,25 +1774,26 @@ static int irix_filldir32(void *__buf, const char *name, int namlen,
1799 return -EINVAL; 1774 return -EINVAL;
1800 dirent = buf->previous; 1775 dirent = buf->previous;
1801 if (dirent) 1776 if (dirent)
1802 __put_user(offset, &dirent->d_off); 1777 err = __put_user(offset, &dirent->d_off);
1803 dirent = buf->current_dir; 1778 dirent = buf->current_dir;
1804 buf->previous = dirent; 1779 err |= __put_user(dirent, &buf->previous);
1805 __put_user(ino, &dirent->d_ino); 1780 err |= __put_user(ino, &dirent->d_ino);
1806 __put_user(reclen, &dirent->d_reclen); 1781 err |= __put_user(reclen, &dirent->d_reclen);
1807 copy_to_user(dirent->d_name, name, namlen); 1782 err |= copy_to_user((char __user *)dirent->d_name, name, namlen) ? -EFAULT : 0;
1808 __put_user(0, &dirent->d_name[namlen]); 1783 err |= __put_user(0, &dirent->d_name[namlen]);
1809 ((char *) dirent) += reclen; 1784 dirent = (struct irix_dirent32 __user *) ((char __user *) dirent + reclen);
1785
1810 buf->current_dir = dirent; 1786 buf->current_dir = dirent;
1811 buf->count -= reclen; 1787 buf->count -= reclen;
1812 1788
1813 return 0; 1789 return err;
1814} 1790}
1815 1791
1816asmlinkage int irix_ngetdents(unsigned int fd, void * dirent, 1792asmlinkage int irix_ngetdents(unsigned int fd, void __user * dirent,
1817 unsigned int count, int *eob) 1793 unsigned int count, int __user *eob)
1818{ 1794{
1819 struct file *file; 1795 struct file *file;
1820 struct irix_dirent32 *lastdirent; 1796 struct irix_dirent32 __user *lastdirent;
1821 struct irix_dirent32_callback buf; 1797 struct irix_dirent32_callback buf;
1822 int error; 1798 int error;
1823 1799
@@ -1830,7 +1806,7 @@ asmlinkage int irix_ngetdents(unsigned int fd, void * dirent,
1830 if (!file) 1806 if (!file)
1831 goto out; 1807 goto out;
1832 1808
1833 buf.current_dir = (struct irix_dirent32 *) dirent; 1809 buf.current_dir = (struct irix_dirent32 __user *) dirent;
1834 buf.previous = NULL; 1810 buf.previous = NULL;
1835 buf.count = count; 1811 buf.count = count;
1836 buf.error = 0; 1812 buf.error = 0;
@@ -1870,8 +1846,8 @@ struct irix_dirent64 {
1870}; 1846};
1871 1847
1872struct irix_dirent64_callback { 1848struct irix_dirent64_callback {
1873 struct irix_dirent64 *curr; 1849 struct irix_dirent64 __user *curr;
1874 struct irix_dirent64 *previous; 1850 struct irix_dirent64 __user *previous;
1875 int count; 1851 int count;
1876 int error; 1852 int error;
1877}; 1853};
@@ -1879,37 +1855,44 @@ struct irix_dirent64_callback {
1879#define NAME_OFFSET64(de) ((int) ((de)->d_name - (char *) (de))) 1855#define NAME_OFFSET64(de) ((int) ((de)->d_name - (char *) (de)))
1880#define ROUND_UP64(x) (((x)+sizeof(u64)-1) & ~(sizeof(u64)-1)) 1856#define ROUND_UP64(x) (((x)+sizeof(u64)-1) & ~(sizeof(u64)-1))
1881 1857
1882static int irix_filldir64(void * __buf, const char * name, int namlen, 1858static int irix_filldir64(void *__buf, const char *name,
1883 loff_t offset, ino_t ino, unsigned int d_type) 1859 int namlen, loff_t offset, ino_t ino, unsigned int d_type)
1884{ 1860{
1885 struct irix_dirent64 *dirent; 1861 struct irix_dirent64 __user *dirent;
1886 struct irix_dirent64_callback * buf = 1862 struct irix_dirent64_callback * buf = __buf;
1887 (struct irix_dirent64_callback *) __buf;
1888 unsigned short reclen = ROUND_UP64(NAME_OFFSET64(dirent) + namlen + 1); 1863 unsigned short reclen = ROUND_UP64(NAME_OFFSET64(dirent) + namlen + 1);
1864 int err = 0;
1889 1865
1890 buf->error = -EINVAL; /* only used if we fail.. */ 1866 if (!access_ok(VERIFY_WRITE, buf, sizeof(*buf)))
1867 return -EFAULT;
1868
1869 if (__put_user(-EINVAL, &buf->error)) /* only used if we fail.. */
1870 return -EFAULT;
1891 if (reclen > buf->count) 1871 if (reclen > buf->count)
1892 return -EINVAL; 1872 return -EINVAL;
1893 dirent = buf->previous; 1873 dirent = buf->previous;
1894 if (dirent) 1874 if (dirent)
1895 __put_user(offset, &dirent->d_off); 1875 err = __put_user(offset, &dirent->d_off);
1896 dirent = buf->curr; 1876 dirent = buf->curr;
1897 buf->previous = dirent; 1877 buf->previous = dirent;
1898 __put_user(ino, &dirent->d_ino); 1878 err |= __put_user(ino, &dirent->d_ino);
1899 __put_user(reclen, &dirent->d_reclen); 1879 err |= __put_user(reclen, &dirent->d_reclen);
1900 __copy_to_user(dirent->d_name, name, namlen); 1880 err |= __copy_to_user((char __user *)dirent->d_name, name, namlen)
1901 __put_user(0, &dirent->d_name[namlen]); 1881 ? -EFAULT : 0;
1902 ((char *) dirent) += reclen; 1882 err |= __put_user(0, &dirent->d_name[namlen]);
1883
1884 dirent = (struct irix_dirent64 __user *) ((char __user *) dirent + reclen);
1885
1903 buf->curr = dirent; 1886 buf->curr = dirent;
1904 buf->count -= reclen; 1887 buf->count -= reclen;
1905 1888
1906 return 0; 1889 return err;
1907} 1890}
1908 1891
1909asmlinkage int irix_getdents64(int fd, void *dirent, int cnt) 1892asmlinkage int irix_getdents64(int fd, void __user *dirent, int cnt)
1910{ 1893{
1911 struct file *file; 1894 struct file *file;
1912 struct irix_dirent64 *lastdirent; 1895 struct irix_dirent64 __user *lastdirent;
1913 struct irix_dirent64_callback buf; 1896 struct irix_dirent64_callback buf;
1914 int error; 1897 int error;
1915 1898
@@ -1929,7 +1912,7 @@ asmlinkage int irix_getdents64(int fd, void *dirent, int cnt)
1929 if (cnt < (sizeof(struct irix_dirent64) + 255)) 1912 if (cnt < (sizeof(struct irix_dirent64) + 255))
1930 goto out_f; 1913 goto out_f;
1931 1914
1932 buf.curr = (struct irix_dirent64 *) dirent; 1915 buf.curr = (struct irix_dirent64 __user *) dirent;
1933 buf.previous = NULL; 1916 buf.previous = NULL;
1934 buf.count = cnt; 1917 buf.count = cnt;
1935 buf.error = 0; 1918 buf.error = 0;
@@ -1941,7 +1924,8 @@ asmlinkage int irix_getdents64(int fd, void *dirent, int cnt)
1941 error = buf.error; 1924 error = buf.error;
1942 goto out_f; 1925 goto out_f;
1943 } 1926 }
1944 lastdirent->d_off = (u64) file->f_pos; 1927 if (put_user(file->f_pos, &lastdirent->d_off))
1928 return -EFAULT;
1945#ifdef DEBUG_GETDENTS 1929#ifdef DEBUG_GETDENTS
1946 printk("returning %d\n", cnt - buf.count); 1930 printk("returning %d\n", cnt - buf.count);
1947#endif 1931#endif
@@ -1953,10 +1937,10 @@ out:
1953 return error; 1937 return error;
1954} 1938}
1955 1939
1956asmlinkage int irix_ngetdents64(int fd, void *dirent, int cnt, int *eob) 1940asmlinkage int irix_ngetdents64(int fd, void __user *dirent, int cnt, int *eob)
1957{ 1941{
1958 struct file *file; 1942 struct file *file;
1959 struct irix_dirent64 *lastdirent; 1943 struct irix_dirent64 __user *lastdirent;
1960 struct irix_dirent64_callback buf; 1944 struct irix_dirent64_callback buf;
1961 int error; 1945 int error;
1962 1946
@@ -1978,7 +1962,7 @@ asmlinkage int irix_ngetdents64(int fd, void *dirent, int cnt, int *eob)
1978 goto out_f; 1962 goto out_f;
1979 1963
1980 *eob = 0; 1964 *eob = 0;
1981 buf.curr = (struct irix_dirent64 *) dirent; 1965 buf.curr = (struct irix_dirent64 __user *) dirent;
1982 buf.previous = NULL; 1966 buf.previous = NULL;
1983 buf.count = cnt; 1967 buf.count = cnt;
1984 buf.error = 0; 1968 buf.error = 0;
@@ -1990,7 +1974,8 @@ asmlinkage int irix_ngetdents64(int fd, void *dirent, int cnt, int *eob)
1990 error = buf.error; 1974 error = buf.error;
1991 goto out_f; 1975 goto out_f;
1992 } 1976 }
1993 lastdirent->d_off = (u64) file->f_pos; 1977 if (put_user(file->f_pos, &lastdirent->d_off))
1978 return -EFAULT;
1994#ifdef DEBUG_GETDENTS 1979#ifdef DEBUG_GETDENTS
1995 printk("eob=%d returning %d\n", *eob, cnt - buf.count); 1980 printk("eob=%d returning %d\n", *eob, cnt - buf.count);
1996#endif 1981#endif
@@ -2053,14 +2038,14 @@ out:
2053 return retval; 2038 return retval;
2054} 2039}
2055 2040
2056asmlinkage int irix_utssys(char *inbuf, int arg, int type, char *outbuf) 2041asmlinkage int irix_utssys(char __user *inbuf, int arg, int type, char __user *outbuf)
2057{ 2042{
2058 int retval; 2043 int retval;
2059 2044
2060 switch(type) { 2045 switch(type) {
2061 case 0: 2046 case 0:
2062 /* uname() */ 2047 /* uname() */
2063 retval = irix_uname((struct iuname *)inbuf); 2048 retval = irix_uname((struct iuname __user *)inbuf);
2064 goto out; 2049 goto out;
2065 2050
2066 case 2: 2051 case 2:
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 0dd0df7a3b04..a24651dfaaba 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -11,6 +11,7 @@
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14#include <linux/config.h>
14#include <linux/types.h> 15#include <linux/types.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
16#include <linux/init.h> 17#include <linux/init.h>
@@ -25,6 +26,7 @@
25#include <linux/module.h> 26#include <linux/module.h>
26 27
27#include <asm/bootinfo.h> 28#include <asm/bootinfo.h>
29#include <asm/cache.h>
28#include <asm/compiler.h> 30#include <asm/compiler.h>
29#include <asm/cpu.h> 31#include <asm/cpu.h>
30#include <asm/cpu-features.h> 32#include <asm/cpu-features.h>
@@ -76,7 +78,7 @@ int (*rtc_set_mmss)(unsigned long);
76static unsigned int sll32_usecs_per_cycle; 78static unsigned int sll32_usecs_per_cycle;
77 79
78/* how many counter cycles in a jiffy */ 80/* how many counter cycles in a jiffy */
79static unsigned long cycles_per_jiffy; 81static unsigned long cycles_per_jiffy __read_mostly;
80 82
81/* Cycle counter value at the previous timer interrupt.. */ 83/* Cycle counter value at the previous timer interrupt.. */
82static unsigned int timerhi, timerlo; 84static unsigned int timerhi, timerlo;
@@ -98,7 +100,10 @@ static unsigned int null_hpt_read(void)
98 return 0; 100 return 0;
99} 101}
100 102
101static void null_hpt_init(unsigned int count) { /* nothing */ } 103static void null_hpt_init(unsigned int count)
104{
105 /* nothing */
106}
102 107
103 108
104/* 109/*
@@ -108,8 +113,10 @@ static void c0_timer_ack(void)
108{ 113{
109 unsigned int count; 114 unsigned int count;
110 115
116#ifndef CONFIG_SOC_PNX8550 /* pnx8550 resets to zero */
111 /* Ack this timer interrupt and set the next one. */ 117 /* Ack this timer interrupt and set the next one. */
112 expirelo += cycles_per_jiffy; 118 expirelo += cycles_per_jiffy;
119#endif
113 write_c0_compare(expirelo); 120 write_c0_compare(expirelo);
114 121
115 /* Check to see if we have missed any timer interrupts. */ 122 /* Check to see if we have missed any timer interrupts. */
@@ -224,7 +231,6 @@ int do_settimeofday(struct timespec *tv)
224 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); 231 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
225 232
226 ntp_clear(); 233 ntp_clear();
227
228 write_sequnlock_irq(&xtime_lock); 234 write_sequnlock_irq(&xtime_lock);
229 clock_was_set(); 235 clock_was_set();
230 return 0; 236 return 0;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index a53b1ed7b386..6f3ff9690686 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -9,7 +9,7 @@
9 * Copyright (C) 1999 Silicon Graphics, Inc. 9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki 12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
13 */ 13 */
14#include <linux/config.h> 14#include <linux/config.h>
15#include <linux/init.h> 15#include <linux/init.h>
@@ -20,12 +20,16 @@
20#include <linux/smp_lock.h> 20#include <linux/smp_lock.h>
21#include <linux/spinlock.h> 21#include <linux/spinlock.h>
22#include <linux/kallsyms.h> 22#include <linux/kallsyms.h>
23#include <linux/bootmem.h>
23 24
24#include <asm/bootinfo.h> 25#include <asm/bootinfo.h>
25#include <asm/branch.h> 26#include <asm/branch.h>
26#include <asm/break.h> 27#include <asm/break.h>
27#include <asm/cpu.h> 28#include <asm/cpu.h>
29#include <asm/dsp.h>
28#include <asm/fpu.h> 30#include <asm/fpu.h>
31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h>
29#include <asm/module.h> 33#include <asm/module.h>
30#include <asm/pgtable.h> 34#include <asm/pgtable.h>
31#include <asm/ptrace.h> 35#include <asm/ptrace.h>
@@ -54,14 +58,19 @@ extern asmlinkage void handle_tr(void);
54extern asmlinkage void handle_fpe(void); 58extern asmlinkage void handle_fpe(void);
55extern asmlinkage void handle_mdmx(void); 59extern asmlinkage void handle_mdmx(void);
56extern asmlinkage void handle_watch(void); 60extern asmlinkage void handle_watch(void);
61extern asmlinkage void handle_mt(void);
62extern asmlinkage void handle_dsp(void);
57extern asmlinkage void handle_mcheck(void); 63extern asmlinkage void handle_mcheck(void);
58extern asmlinkage void handle_reserved(void); 64extern asmlinkage void handle_reserved(void);
59 65
60extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, 66extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
61 struct mips_fpu_soft_struct *ctx); 67 struct mips_fpu_soft_struct *ctx);
62 68
63void (*board_be_init)(void); 69void (*board_be_init)(void);
64int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 70int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
71void (*board_nmi_handler_setup)(void);
72void (*board_ejtag_handler_setup)(void);
73void (*board_bind_eic_interrupt)(int irq, int regset);
65 74
66/* 75/*
67 * These constant is for searching for possible module text segments. 76 * These constant is for searching for possible module text segments.
@@ -201,32 +210,47 @@ void show_regs(struct pt_regs *regs)
201 210
202 printk("Status: %08x ", (uint32_t) regs->cp0_status); 211 printk("Status: %08x ", (uint32_t) regs->cp0_status);
203 212
204 if (regs->cp0_status & ST0_KX) 213 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
205 printk("KX "); 214 if (regs->cp0_status & ST0_KUO)
206 if (regs->cp0_status & ST0_SX) 215 printk("KUo ");
207 printk("SX "); 216 if (regs->cp0_status & ST0_IEO)
208 if (regs->cp0_status & ST0_UX) 217 printk("IEo ");
209 printk("UX "); 218 if (regs->cp0_status & ST0_KUP)
210 switch (regs->cp0_status & ST0_KSU) { 219 printk("KUp ");
211 case KSU_USER: 220 if (regs->cp0_status & ST0_IEP)
212 printk("USER "); 221 printk("IEp ");
213 break; 222 if (regs->cp0_status & ST0_KUC)
214 case KSU_SUPERVISOR: 223 printk("KUc ");
215 printk("SUPERVISOR "); 224 if (regs->cp0_status & ST0_IEC)
216 break; 225 printk("IEc ");
217 case KSU_KERNEL: 226 } else {
218 printk("KERNEL "); 227 if (regs->cp0_status & ST0_KX)
219 break; 228 printk("KX ");
220 default: 229 if (regs->cp0_status & ST0_SX)
221 printk("BAD_MODE "); 230 printk("SX ");
222 break; 231 if (regs->cp0_status & ST0_UX)
232 printk("UX ");
233 switch (regs->cp0_status & ST0_KSU) {
234 case KSU_USER:
235 printk("USER ");
236 break;
237 case KSU_SUPERVISOR:
238 printk("SUPERVISOR ");
239 break;
240 case KSU_KERNEL:
241 printk("KERNEL ");
242 break;
243 default:
244 printk("BAD_MODE ");
245 break;
246 }
247 if (regs->cp0_status & ST0_ERL)
248 printk("ERL ");
249 if (regs->cp0_status & ST0_EXL)
250 printk("EXL ");
251 if (regs->cp0_status & ST0_IE)
252 printk("IE ");
223 } 253 }
224 if (regs->cp0_status & ST0_ERL)
225 printk("ERL ");
226 if (regs->cp0_status & ST0_EXL)
227 printk("EXL ");
228 if (regs->cp0_status & ST0_IE)
229 printk("IE ");
230 printk("\n"); 254 printk("\n");
231 255
232 printk("Cause : %08x\n", cause); 256 printk("Cause : %08x\n", cause);
@@ -252,29 +276,18 @@ void show_registers(struct pt_regs *regs)
252 276
253static DEFINE_SPINLOCK(die_lock); 277static DEFINE_SPINLOCK(die_lock);
254 278
255NORET_TYPE void __die(const char * str, struct pt_regs * regs, 279NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
256 const char * file, const char * func, unsigned long line)
257{ 280{
258 static int die_counter; 281 static int die_counter;
259 282
260 console_verbose(); 283 console_verbose();
261 spin_lock_irq(&die_lock); 284 spin_lock_irq(&die_lock);
262 printk("%s", str); 285 printk("%s[#%d]:\n", str, ++die_counter);
263 if (file && func)
264 printk(" in %s:%s, line %ld", file, func, line);
265 printk("[#%d]:\n", ++die_counter);
266 show_registers(regs); 286 show_registers(regs);
267 spin_unlock_irq(&die_lock); 287 spin_unlock_irq(&die_lock);
268 do_exit(SIGSEGV); 288 do_exit(SIGSEGV);
269} 289}
270 290
271void __die_if_kernel(const char * str, struct pt_regs * regs,
272 const char * file, const char * func, unsigned long line)
273{
274 if (!user_mode(regs))
275 __die(str, regs, file, func, line);
276}
277
278extern const struct exception_table_entry __start___dbe_table[]; 291extern const struct exception_table_entry __start___dbe_table[];
279extern const struct exception_table_entry __stop___dbe_table[]; 292extern const struct exception_table_entry __stop___dbe_table[];
280 293
@@ -339,9 +352,9 @@ asmlinkage void do_be(struct pt_regs *regs)
339 352
340static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) 353static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
341{ 354{
342 unsigned int *epc; 355 unsigned int __user *epc;
343 356
344 epc = (unsigned int *) regs->cp0_epc + 357 epc = (unsigned int __user *) regs->cp0_epc +
345 ((regs->cp0_cause & CAUSEF_BD) != 0); 358 ((regs->cp0_cause & CAUSEF_BD) != 0);
346 if (!get_user(*opcode, epc)) 359 if (!get_user(*opcode, epc))
347 return 0; 360 return 0;
@@ -360,6 +373,10 @@ static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
360#define OFFSET 0x0000ffff 373#define OFFSET 0x0000ffff
361#define LL 0xc0000000 374#define LL 0xc0000000
362#define SC 0xe0000000 375#define SC 0xe0000000
376#define SPEC3 0x7c000000
377#define RD 0x0000f800
378#define FUNC 0x0000003f
379#define RDHWR 0x0000003b
363 380
364/* 381/*
365 * The ll_bit is cleared by r*_switch.S 382 * The ll_bit is cleared by r*_switch.S
@@ -371,7 +388,7 @@ static struct task_struct *ll_task = NULL;
371 388
372static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) 389static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
373{ 390{
374 unsigned long value, *vaddr; 391 unsigned long value, __user *vaddr;
375 long offset; 392 long offset;
376 int signal = 0; 393 int signal = 0;
377 394
@@ -385,7 +402,8 @@ static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
385 offset <<= 16; 402 offset <<= 16;
386 offset >>= 16; 403 offset >>= 16;
387 404
388 vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset); 405 vaddr = (unsigned long __user *)
406 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
389 407
390 if ((unsigned long)vaddr & 3) { 408 if ((unsigned long)vaddr & 3) {
391 signal = SIGBUS; 409 signal = SIGBUS;
@@ -407,9 +425,10 @@ static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
407 425
408 preempt_enable(); 426 preempt_enable();
409 427
428 compute_return_epc(regs);
429
410 regs->regs[(opcode & RT) >> 16] = value; 430 regs->regs[(opcode & RT) >> 16] = value;
411 431
412 compute_return_epc(regs);
413 return; 432 return;
414 433
415sig: 434sig:
@@ -418,7 +437,8 @@ sig:
418 437
419static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) 438static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
420{ 439{
421 unsigned long *vaddr, reg; 440 unsigned long __user *vaddr;
441 unsigned long reg;
422 long offset; 442 long offset;
423 int signal = 0; 443 int signal = 0;
424 444
@@ -432,7 +452,8 @@ static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
432 offset <<= 16; 452 offset <<= 16;
433 offset >>= 16; 453 offset >>= 16;
434 454
435 vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset); 455 vaddr = (unsigned long __user *)
456 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
436 reg = (opcode & RT) >> 16; 457 reg = (opcode & RT) >> 16;
437 458
438 if ((unsigned long)vaddr & 3) { 459 if ((unsigned long)vaddr & 3) {
@@ -443,9 +464,9 @@ static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
443 preempt_disable(); 464 preempt_disable();
444 465
445 if (ll_bit == 0 || ll_task != current) { 466 if (ll_bit == 0 || ll_task != current) {
467 compute_return_epc(regs);
446 regs->regs[reg] = 0; 468 regs->regs[reg] = 0;
447 preempt_enable(); 469 preempt_enable();
448 compute_return_epc(regs);
449 return; 470 return;
450 } 471 }
451 472
@@ -456,9 +477,9 @@ static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
456 goto sig; 477 goto sig;
457 } 478 }
458 479
480 compute_return_epc(regs);
459 regs->regs[reg] = 1; 481 regs->regs[reg] = 1;
460 482
461 compute_return_epc(regs);
462 return; 483 return;
463 484
464sig: 485sig:
@@ -491,6 +512,37 @@ static inline int simulate_llsc(struct pt_regs *regs)
491 return -EFAULT; /* Strange things going on ... */ 512 return -EFAULT; /* Strange things going on ... */
492} 513}
493 514
515/*
516 * Simulate trapping 'rdhwr' instructions to provide user accessible
517 * registers not implemented in hardware. The only current use of this
518 * is the thread area pointer.
519 */
520static inline int simulate_rdhwr(struct pt_regs *regs)
521{
522 struct thread_info *ti = current->thread_info;
523 unsigned int opcode;
524
525 if (unlikely(get_insn_opcode(regs, &opcode)))
526 return -EFAULT;
527
528 if (unlikely(compute_return_epc(regs)))
529 return -EFAULT;
530
531 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
532 int rd = (opcode & RD) >> 11;
533 int rt = (opcode & RT) >> 16;
534 switch (rd) {
535 case 29:
536 regs->regs[rt] = ti->tp_value;
537 break;
538 default:
539 return -EFAULT;
540 }
541 }
542
543 return 0;
544}
545
494asmlinkage void do_ov(struct pt_regs *regs) 546asmlinkage void do_ov(struct pt_regs *regs)
495{ 547{
496 siginfo_t info; 548 siginfo_t info;
@@ -498,7 +550,7 @@ asmlinkage void do_ov(struct pt_regs *regs)
498 info.si_code = FPE_INTOVF; 550 info.si_code = FPE_INTOVF;
499 info.si_signo = SIGFPE; 551 info.si_signo = SIGFPE;
500 info.si_errno = 0; 552 info.si_errno = 0;
501 info.si_addr = (void *)regs->cp0_epc; 553 info.si_addr = (void __user *) regs->cp0_epc;
502 force_sig_info(SIGFPE, &info, current); 554 force_sig_info(SIGFPE, &info, current);
503} 555}
504 556
@@ -512,6 +564,14 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
512 564
513 preempt_disable(); 565 preempt_disable();
514 566
567#ifdef CONFIG_PREEMPT
568 if (!is_fpu_owner()) {
569 /* We might lose fpu before disabling preempt... */
570 own_fpu();
571 BUG_ON(!used_math());
572 restore_fp(current);
573 }
574#endif
515 /* 575 /*
516 * Unimplemented operation exception. If we've got the full 576 * Unimplemented operation exception. If we've got the full
517 * software emulator on-board, let's use it... 577 * software emulator on-board, let's use it...
@@ -523,11 +583,18 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
523 * a bit extreme for what should be an infrequent event. 583 * a bit extreme for what should be an infrequent event.
524 */ 584 */
525 save_fp(current); 585 save_fp(current);
586 /* Ensure 'resume' not overwrite saved fp context again. */
587 lose_fpu();
588
589 preempt_enable();
526 590
527 /* Run the emulator */ 591 /* Run the emulator */
528 sig = fpu_emulator_cop1Handler (0, regs, 592 sig = fpu_emulator_cop1Handler (regs,
529 &current->thread.fpu.soft); 593 &current->thread.fpu.soft);
530 594
595 preempt_disable();
596
597 own_fpu(); /* Using the FPU again. */
531 /* 598 /*
532 * We can't allow the emulated instruction to leave any of 599 * We can't allow the emulated instruction to leave any of
533 * the cause bit set in $fcr31. 600 * the cause bit set in $fcr31.
@@ -584,7 +651,7 @@ asmlinkage void do_bp(struct pt_regs *regs)
584 info.si_code = FPE_INTOVF; 651 info.si_code = FPE_INTOVF;
585 info.si_signo = SIGFPE; 652 info.si_signo = SIGFPE;
586 info.si_errno = 0; 653 info.si_errno = 0;
587 info.si_addr = (void *)regs->cp0_epc; 654 info.si_addr = (void __user *) regs->cp0_epc;
588 force_sig_info(SIGFPE, &info, current); 655 force_sig_info(SIGFPE, &info, current);
589 break; 656 break;
590 default: 657 default:
@@ -621,7 +688,7 @@ asmlinkage void do_tr(struct pt_regs *regs)
621 info.si_code = FPE_INTOVF; 688 info.si_code = FPE_INTOVF;
622 info.si_signo = SIGFPE; 689 info.si_signo = SIGFPE;
623 info.si_errno = 0; 690 info.si_errno = 0;
624 info.si_addr = (void *)regs->cp0_epc; 691 info.si_addr = (void __user *) regs->cp0_epc;
625 force_sig_info(SIGFPE, &info, current); 692 force_sig_info(SIGFPE, &info, current);
626 break; 693 break;
627 default: 694 default:
@@ -637,6 +704,9 @@ asmlinkage void do_ri(struct pt_regs *regs)
637 if (!simulate_llsc(regs)) 704 if (!simulate_llsc(regs))
638 return; 705 return;
639 706
707 if (!simulate_rdhwr(regs))
708 return;
709
640 force_sig(SIGILL, current); 710 force_sig(SIGILL, current);
641} 711}
642 712
@@ -650,11 +720,13 @@ asmlinkage void do_cpu(struct pt_regs *regs)
650 720
651 switch (cpid) { 721 switch (cpid) {
652 case 0: 722 case 0:
653 if (cpu_has_llsc) 723 if (!cpu_has_llsc)
654 break; 724 if (!simulate_llsc(regs))
725 return;
655 726
656 if (!simulate_llsc(regs)) 727 if (!simulate_rdhwr(regs))
657 return; 728 return;
729
658 break; 730 break;
659 731
660 case 1: 732 case 1:
@@ -668,15 +740,15 @@ asmlinkage void do_cpu(struct pt_regs *regs)
668 set_used_math(); 740 set_used_math();
669 } 741 }
670 742
743 preempt_enable();
744
671 if (!cpu_has_fpu) { 745 if (!cpu_has_fpu) {
672 int sig = fpu_emulator_cop1Handler(0, regs, 746 int sig = fpu_emulator_cop1Handler(regs,
673 &current->thread.fpu.soft); 747 &current->thread.fpu.soft);
674 if (sig) 748 if (sig)
675 force_sig(sig, current); 749 force_sig(sig, current);
676 } 750 }
677 751
678 preempt_enable();
679
680 return; 752 return;
681 753
682 case 2: 754 case 2:
@@ -716,6 +788,22 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
716 (regs->cp0_status & ST0_TS) ? "" : "not "); 788 (regs->cp0_status & ST0_TS) ? "" : "not ");
717} 789}
718 790
791asmlinkage void do_mt(struct pt_regs *regs)
792{
793 die_if_kernel("MIPS MT Thread exception in kernel", regs);
794
795 force_sig(SIGILL, current);
796}
797
798
799asmlinkage void do_dsp(struct pt_regs *regs)
800{
801 if (cpu_has_dsp)
802 panic("Unexpected DSP exception\n");
803
804 force_sig(SIGILL, current);
805}
806
719asmlinkage void do_reserved(struct pt_regs *regs) 807asmlinkage void do_reserved(struct pt_regs *regs)
720{ 808{
721 /* 809 /*
@@ -728,6 +816,12 @@ asmlinkage void do_reserved(struct pt_regs *regs)
728 (regs->cp0_cause & 0x7f) >> 2); 816 (regs->cp0_cause & 0x7f) >> 2);
729} 817}
730 818
819asmlinkage void do_default_vi(struct pt_regs *regs)
820{
821 show_regs(regs);
822 panic("Caught unexpected vectored interrupt.");
823}
824
731/* 825/*
732 * Some MIPS CPUs can enable/disable for cache parity detection, but do 826 * Some MIPS CPUs can enable/disable for cache parity detection, but do
733 * it different ways. 827 * it different ways.
@@ -736,16 +830,12 @@ static inline void parity_protection_init(void)
736{ 830{
737 switch (current_cpu_data.cputype) { 831 switch (current_cpu_data.cputype) {
738 case CPU_24K: 832 case CPU_24K:
739 /* 24K cache parity not currently implemented in FPGA */
740 printk(KERN_INFO "Disable cache parity protection for "
741 "MIPS 24K CPU.\n");
742 write_c0_ecc(read_c0_ecc() & ~0x80000000);
743 break;
744 case CPU_5KC: 833 case CPU_5KC:
745 /* Set the PE bit (bit 31) in the c0_ecc register. */ 834 write_c0_ecc(0x80000000);
746 printk(KERN_INFO "Enable cache parity protection for " 835 back_to_back_c0_hazard();
747 "MIPS 5KC/24K CPUs.\n"); 836 /* Set the PE bit (bit 31) in the c0_errctl register. */
748 write_c0_ecc(read_c0_ecc() | 0x80000000); 837 printk(KERN_INFO "Cache parity protection %sabled\n",
838 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
749 break; 839 break;
750 case CPU_20KC: 840 case CPU_20KC:
751 case CPU_25KF: 841 case CPU_25KF:
@@ -783,7 +873,7 @@ asmlinkage void cache_parity_error(void)
783 reg_val & (1<<22) ? "E0 " : ""); 873 reg_val & (1<<22) ? "E0 " : "");
784 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 874 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
785 875
786#if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64) 876#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
787 if (reg_val & (1<<22)) 877 if (reg_val & (1<<22))
788 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 878 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
789 879
@@ -840,7 +930,11 @@ void nmi_exception_handler(struct pt_regs *regs)
840 while(1) ; 930 while(1) ;
841} 931}
842 932
933#define VECTORSPACING 0x100 /* for EI/VI mode */
934
935unsigned long ebase;
843unsigned long exception_handlers[32]; 936unsigned long exception_handlers[32];
937unsigned long vi_handlers[64];
844 938
845/* 939/*
846 * As a side effect of the way this is implemented we're limited 940 * As a side effect of the way this is implemented we're limited
@@ -854,13 +948,156 @@ void *set_except_vector(int n, void *addr)
854 948
855 exception_handlers[n] = handler; 949 exception_handlers[n] = handler;
856 if (n == 0 && cpu_has_divec) { 950 if (n == 0 && cpu_has_divec) {
857 *(volatile u32 *)(CAC_BASE + 0x200) = 0x08000000 | 951 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
858 (0x03ffffff & (handler >> 2)); 952 (0x03ffffff & (handler >> 2));
859 flush_icache_range(CAC_BASE + 0x200, CAC_BASE + 0x204); 953 flush_icache_range(ebase + 0x200, ebase + 0x204);
860 } 954 }
861 return (void *)old_handler; 955 return (void *)old_handler;
862} 956}
863 957
958#ifdef CONFIG_CPU_MIPSR2
959/*
960 * Shadow register allocation
961 * FIXME: SMP...
962 */
963
964/* MIPSR2 shadow register sets */
965struct shadow_registers {
966 spinlock_t sr_lock; /* */
967 int sr_supported; /* Number of shadow register sets supported */
968 int sr_allocated; /* Bitmap of allocated shadow registers */
969} shadow_registers;
970
971void mips_srs_init(void)
972{
973#ifdef CONFIG_CPU_MIPSR2_SRS
974 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
975 printk ("%d MIPSR2 register sets available\n", shadow_registers.sr_supported);
976#else
977 shadow_registers.sr_supported = 1;
978#endif
979 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
980 spin_lock_init(&shadow_registers.sr_lock);
981}
982
983int mips_srs_max(void)
984{
985 return shadow_registers.sr_supported;
986}
987
988int mips_srs_alloc (void)
989{
990 struct shadow_registers *sr = &shadow_registers;
991 unsigned long flags;
992 int set;
993
994 spin_lock_irqsave(&sr->sr_lock, flags);
995
996 for (set = 0; set < sr->sr_supported; set++) {
997 if ((sr->sr_allocated & (1 << set)) == 0) {
998 sr->sr_allocated |= 1 << set;
999 spin_unlock_irqrestore(&sr->sr_lock, flags);
1000 return set;
1001 }
1002 }
1003
1004 /* None available */
1005 spin_unlock_irqrestore(&sr->sr_lock, flags);
1006 return -1;
1007}
1008
1009void mips_srs_free (int set)
1010{
1011 struct shadow_registers *sr = &shadow_registers;
1012 unsigned long flags;
1013
1014 spin_lock_irqsave(&sr->sr_lock, flags);
1015 sr->sr_allocated &= ~(1 << set);
1016 spin_unlock_irqrestore(&sr->sr_lock, flags);
1017}
1018
1019void *set_vi_srs_handler (int n, void *addr, int srs)
1020{
1021 unsigned long handler;
1022 unsigned long old_handler = vi_handlers[n];
1023 u32 *w;
1024 unsigned char *b;
1025
1026 if (!cpu_has_veic && !cpu_has_vint)
1027 BUG();
1028
1029 if (addr == NULL) {
1030 handler = (unsigned long) do_default_vi;
1031 srs = 0;
1032 }
1033 else
1034 handler = (unsigned long) addr;
1035 vi_handlers[n] = (unsigned long) addr;
1036
1037 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1038
1039 if (srs >= mips_srs_max())
1040 panic("Shadow register set %d not supported", srs);
1041
1042 if (cpu_has_veic) {
1043 if (board_bind_eic_interrupt)
1044 board_bind_eic_interrupt (n, srs);
1045 }
1046 else if (cpu_has_vint) {
1047 /* SRSMap is only defined if shadow sets are implemented */
1048 if (mips_srs_max() > 1)
1049 change_c0_srsmap (0xf << n*4, srs << n*4);
1050 }
1051
1052 if (srs == 0) {
1053 /*
1054 * If no shadow set is selected then use the default handler
1055 * that does normal register saving and a standard interrupt exit
1056 */
1057
1058 extern char except_vec_vi, except_vec_vi_lui;
1059 extern char except_vec_vi_ori, except_vec_vi_end;
1060 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1061 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1062 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1063
1064 if (handler_len > VECTORSPACING) {
1065 /*
1066 * Sigh... panicing won't help as the console
1067 * is probably not configured :(
1068 */
1069 panic ("VECTORSPACING too small");
1070 }
1071
1072 memcpy (b, &except_vec_vi, handler_len);
1073 w = (u32 *)(b + lui_offset);
1074 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1075 w = (u32 *)(b + ori_offset);
1076 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1077 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1078 }
1079 else {
1080 /*
1081 * In other cases jump directly to the interrupt handler
1082 *
1083 * It is the handlers responsibility to save registers if required
1084 * (eg hi/lo) and return from the exception using "eret"
1085 */
1086 w = (u32 *)b;
1087 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1088 *w = 0;
1089 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1090 }
1091
1092 return (void *)old_handler;
1093}
1094
1095void *set_vi_handler (int n, void *addr)
1096{
1097 return set_vi_srs_handler (n, addr, 0);
1098}
1099#endif
1100
864/* 1101/*
865 * This is used by native signal handling 1102 * This is used by native signal handling
866 */ 1103 */
@@ -912,6 +1149,7 @@ static inline void signal32_init(void)
912 1149
913extern void cpu_cache_init(void); 1150extern void cpu_cache_init(void);
914extern void tlb_init(void); 1151extern void tlb_init(void);
1152extern void flush_tlb_handlers(void);
915 1153
916void __init per_cpu_trap_init(void) 1154void __init per_cpu_trap_init(void)
917{ 1155{
@@ -929,15 +1167,32 @@ void __init per_cpu_trap_init(void)
929#endif 1167#endif
930 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1168 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
931 status_set |= ST0_XX; 1169 status_set |= ST0_XX;
932 change_c0_status(ST0_CU|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1170 change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
933 status_set); 1171 status_set);
934 1172
1173 if (cpu_has_dsp)
1174 set_c0_status(ST0_MX);
1175
1176#ifdef CONFIG_CPU_MIPSR2
1177 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1178#endif
1179
935 /* 1180 /*
936 * Some MIPS CPUs have a dedicated interrupt vector which reduces the 1181 * Interrupt handling.
937 * interrupt processing overhead. Use it where available.
938 */ 1182 */
939 if (cpu_has_divec) 1183 if (cpu_has_veic || cpu_has_vint) {
940 set_c0_cause(CAUSEF_IV); 1184 write_c0_ebase (ebase);
1185 /* Setting vector spacing enables EI/VI mode */
1186 change_c0_intctl (0x3e0, VECTORSPACING);
1187 }
1188 if (cpu_has_divec) {
1189 if (cpu_has_mipsmt) {
1190 unsigned int vpflags = dvpe();
1191 set_c0_cause(CAUSEF_IV);
1192 evpe(vpflags);
1193 } else
1194 set_c0_cause(CAUSEF_IV);
1195 }
941 1196
942 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1197 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
943 TLBMISS_HANDLER_SETUP(); 1198 TLBMISS_HANDLER_SETUP();
@@ -951,13 +1206,41 @@ void __init per_cpu_trap_init(void)
951 tlb_init(); 1206 tlb_init();
952} 1207}
953 1208
1209/* Install CPU exception handler */
1210void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1211{
1212 memcpy((void *)(ebase + offset), addr, size);
1213 flush_icache_range(ebase + offset, ebase + offset + size);
1214}
1215
1216/* Install uncached CPU exception handler */
1217void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1218{
1219#ifdef CONFIG_32BIT
1220 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1221#endif
1222#ifdef CONFIG_64BIT
1223 unsigned long uncached_ebase = TO_UNCAC(ebase);
1224#endif
1225
1226 memcpy((void *)(uncached_ebase + offset), addr, size);
1227}
1228
954void __init trap_init(void) 1229void __init trap_init(void)
955{ 1230{
956 extern char except_vec3_generic, except_vec3_r4000; 1231 extern char except_vec3_generic, except_vec3_r4000;
957 extern char except_vec_ejtag_debug;
958 extern char except_vec4; 1232 extern char except_vec4;
959 unsigned long i; 1233 unsigned long i;
960 1234
1235 if (cpu_has_veic || cpu_has_vint)
1236 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1237 else
1238 ebase = CAC_BASE;
1239
1240#ifdef CONFIG_CPU_MIPSR2
1241 mips_srs_init();
1242#endif
1243
961 per_cpu_trap_init(); 1244 per_cpu_trap_init();
962 1245
963 /* 1246 /*
@@ -965,7 +1248,7 @@ void __init trap_init(void)
965 * This will be overriden later as suitable for a particular 1248 * This will be overriden later as suitable for a particular
966 * configuration. 1249 * configuration.
967 */ 1250 */
968 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1251 set_handler(0x180, &except_vec3_generic, 0x80);
969 1252
970 /* 1253 /*
971 * Setup default vectors 1254 * Setup default vectors
@@ -977,8 +1260,8 @@ void __init trap_init(void)
977 * Copy the EJTAG debug exception vector handler code to it's final 1260 * Copy the EJTAG debug exception vector handler code to it's final
978 * destination. 1261 * destination.
979 */ 1262 */
980 if (cpu_has_ejtag) 1263 if (cpu_has_ejtag && board_ejtag_handler_setup)
981 memcpy((void *)(CAC_BASE + 0x300), &except_vec_ejtag_debug, 0x80); 1264 board_ejtag_handler_setup ();
982 1265
983 /* 1266 /*
984 * Only some CPUs have the watch exceptions. 1267 * Only some CPUs have the watch exceptions.
@@ -987,11 +1270,15 @@ void __init trap_init(void)
987 set_except_vector(23, handle_watch); 1270 set_except_vector(23, handle_watch);
988 1271
989 /* 1272 /*
990 * Some MIPS CPUs have a dedicated interrupt vector which reduces the 1273 * Initialise interrupt handlers
991 * interrupt processing overhead. Use it where available.
992 */ 1274 */
993 if (cpu_has_divec) 1275 if (cpu_has_veic || cpu_has_vint) {
994 memcpy((void *)(CAC_BASE + 0x200), &except_vec4, 0x8); 1276 int nvec = cpu_has_veic ? 64 : 8;
1277 for (i = 0; i < nvec; i++)
1278 set_vi_handler (i, NULL);
1279 }
1280 else if (cpu_has_divec)
1281 set_handler(0x200, &except_vec4, 0x8);
995 1282
996 /* 1283 /*
997 * Some CPUs can enable/disable for cache parity detection, but does 1284 * Some CPUs can enable/disable for cache parity detection, but does
@@ -1023,21 +1310,6 @@ void __init trap_init(void)
1023 set_except_vector(11, handle_cpu); 1310 set_except_vector(11, handle_cpu);
1024 set_except_vector(12, handle_ov); 1311 set_except_vector(12, handle_ov);
1025 set_except_vector(13, handle_tr); 1312 set_except_vector(13, handle_tr);
1026 set_except_vector(22, handle_mdmx);
1027
1028 if (cpu_has_fpu && !cpu_has_nofpuex)
1029 set_except_vector(15, handle_fpe);
1030
1031 if (cpu_has_mcheck)
1032 set_except_vector(24, handle_mcheck);
1033
1034 if (cpu_has_vce)
1035 /* Special exception: R4[04]00 uses also the divec space. */
1036 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1037 else if (cpu_has_4kex)
1038 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1039 else
1040 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1041 1313
1042 if (current_cpu_data.cputype == CPU_R6000 || 1314 if (current_cpu_data.cputype == CPU_R6000 ||
1043 current_cpu_data.cputype == CPU_R6000A) { 1315 current_cpu_data.cputype == CPU_R6000A) {
@@ -1053,10 +1325,37 @@ void __init trap_init(void)
1053 //set_except_vector(15, handle_ndc); 1325 //set_except_vector(15, handle_ndc);
1054 } 1326 }
1055 1327
1328
1329 if (board_nmi_handler_setup)
1330 board_nmi_handler_setup();
1331
1332 if (cpu_has_fpu && !cpu_has_nofpuex)
1333 set_except_vector(15, handle_fpe);
1334
1335 set_except_vector(22, handle_mdmx);
1336
1337 if (cpu_has_mcheck)
1338 set_except_vector(24, handle_mcheck);
1339
1340 if (cpu_has_mipsmt)
1341 set_except_vector(25, handle_mt);
1342
1343 if (cpu_has_dsp)
1344 set_except_vector(26, handle_dsp);
1345
1346 if (cpu_has_vce)
1347 /* Special exception: R4[04]00 uses also the divec space. */
1348 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1349 else if (cpu_has_4kex)
1350 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1351 else
1352 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1353
1056 signal_init(); 1354 signal_init();
1057#ifdef CONFIG_MIPS32_COMPAT 1355#ifdef CONFIG_MIPS32_COMPAT
1058 signal32_init(); 1356 signal32_init();
1059#endif 1357#endif
1060 1358
1061 flush_icache_range(CAC_BASE, CAC_BASE + 0x400); 1359 flush_icache_range(ebase, ebase + 0x400);
1360 flush_tlb_handlers();
1062} 1361}
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 36c5212e0928..5b5a3736cbbc 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -94,7 +94,7 @@ unsigned long unaligned_instructions;
94#endif 94#endif
95 95
96static inline int emulate_load_store_insn(struct pt_regs *regs, 96static inline int emulate_load_store_insn(struct pt_regs *regs,
97 void *addr, unsigned long pc, 97 void __user *addr, unsigned int __user *pc,
98 unsigned long **regptr, unsigned long *newvalue) 98 unsigned long **regptr, unsigned long *newvalue)
99{ 99{
100 union mips_instruction insn; 100 union mips_instruction insn;
@@ -107,7 +107,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
107 /* 107 /*
108 * This load never faults. 108 * This load never faults.
109 */ 109 */
110 __get_user(insn.word, (unsigned int *)pc); 110 __get_user(insn.word, pc);
111 111
112 switch (insn.i_format.opcode) { 112 switch (insn.i_format.opcode) {
113 /* 113 /*
@@ -494,8 +494,8 @@ asmlinkage void do_ade(struct pt_regs *regs)
494{ 494{
495 unsigned long *regptr, newval; 495 unsigned long *regptr, newval;
496 extern int do_dsemulret(struct pt_regs *); 496 extern int do_dsemulret(struct pt_regs *);
497 unsigned int __user *pc;
497 mm_segment_t seg; 498 mm_segment_t seg;
498 unsigned long pc;
499 499
500 /* 500 /*
501 * Address errors may be deliberately induced by the FPU emulator to 501 * Address errors may be deliberately induced by the FPU emulator to
@@ -515,7 +515,7 @@ asmlinkage void do_ade(struct pt_regs *regs)
515 if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1)) 515 if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1))
516 goto sigbus; 516 goto sigbus;
517 517
518 pc = exception_epc(regs); 518 pc = (unsigned int __user *) exception_epc(regs);
519 if ((current->thread.mflags & MF_FIXADE) == 0) 519 if ((current->thread.mflags & MF_FIXADE) == 0)
520 goto sigbus; 520 goto sigbus;
521 521
@@ -526,7 +526,7 @@ asmlinkage void do_ade(struct pt_regs *regs)
526 seg = get_fs(); 526 seg = get_fs();
527 if (!user_mode(regs)) 527 if (!user_mode(regs))
528 set_fs(KERNEL_DS); 528 set_fs(KERNEL_DS);
529 if (!emulate_load_store_insn(regs, (void *)regs->cp0_badvaddr, pc, 529 if (!emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc,
530 &regptr, &newval)) { 530 &regptr, &newval)) {
531 compute_return_epc(regs); 531 compute_return_epc(regs);
532 /* 532 /*
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 482ac310c937..25cc856d8e7e 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -54,13 +54,6 @@ SECTIONS
54 54
55 *(.data) 55 *(.data)
56 56
57 /* Align the initial ramdisk image (INITRD) on page boundaries. */
58 . = ALIGN(4096);
59 __rd_start = .;
60 *(.initrd)
61 . = ALIGN(4096);
62 __rd_end = .;
63
64 CONSTRUCTORS 57 CONSTRUCTORS
65 } 58 }
66 _gp = . + 0x8000; 59 _gp = . + 0x8000;
@@ -96,12 +89,6 @@ SECTIONS
96 .init.setup : { *(.init.setup) } 89 .init.setup : { *(.init.setup) }
97 __setup_end = .; 90 __setup_end = .;
98 91
99 .early_initcall.init : {
100 __earlyinitcall_start = .;
101 *(.initcall.early1.init)
102 }
103 __earlyinitcall_end = .;
104
105 __initcall_start = .; 92 __initcall_start = .;
106 .initcall.init : { 93 .initcall.init : {
107 *(.initcall1.init) 94 *(.initcall1.init)
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
new file mode 100644
index 000000000000..97fefcc9dbe7
--- /dev/null
+++ b/arch/mips/kernel/vpe.c
@@ -0,0 +1,1296 @@
1/*
2 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18
19/*
20 * VPE support module
21 *
22 * Provides support for loading a MIPS SP program on VPE1.
23 * The SP enviroment is rather simple, no tlb's. It needs to be relocatable
24 * (or partially linked). You should initialise your stack in the startup
25 * code. This loader looks for the symbol __start and sets up
26 * execution to resume from there. The MIPS SDE kit contains suitable examples.
27 *
28 * To load and run, simply cat a SP 'program file' to /dev/vpe1.
29 * i.e cat spapp >/dev/vpe1.
30 *
31 * You'll need to have the following device files.
32 * mknod /dev/vpe0 c 63 0
33 * mknod /dev/vpe1 c 63 1
34 */
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/fs.h>
39#include <linux/init.h>
40#include <asm/uaccess.h>
41#include <linux/slab.h>
42#include <linux/list.h>
43#include <linux/vmalloc.h>
44#include <linux/elf.h>
45#include <linux/seq_file.h>
46#include <linux/syscalls.h>
47#include <linux/moduleloader.h>
48#include <linux/interrupt.h>
49#include <linux/poll.h>
50#include <linux/bootmem.h>
51#include <asm/mipsregs.h>
52#include <asm/mipsmtregs.h>
53#include <asm/cacheflush.h>
54#include <asm/atomic.h>
55#include <asm/cpu.h>
56#include <asm/processor.h>
57#include <asm/system.h>
58
59typedef void *vpe_handle;
60
61// defined here because the kernel module loader doesn't have
62// anything to do with it.
63#define SHN_MIPS_SCOMMON 0xff03
64
65#ifndef ARCH_SHF_SMALL
66#define ARCH_SHF_SMALL 0
67#endif
68
69/* If this is set, the section belongs in the init part of the module */
70#define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1))
71
72// temp number,
73#define VPE_MAJOR 63
74
75static char module_name[] = "vpe";
76static int major = 0;
77
78/* grab the likely amount of memory we will need. */
79#ifdef CONFIG_MIPS_VPE_LOADER_TOM
80#define P_SIZE (2 * 1024 * 1024)
81#else
82/* add an overhead to the max kmalloc size for non-striped symbols/etc */
83#define P_SIZE (256 * 1024)
84#endif
85
86#define MAX_VPES 16
87
88enum vpe_state {
89 VPE_STATE_UNUSED = 0,
90 VPE_STATE_INUSE,
91 VPE_STATE_RUNNING
92};
93
94enum tc_state {
95 TC_STATE_UNUSED = 0,
96 TC_STATE_INUSE,
97 TC_STATE_RUNNING,
98 TC_STATE_DYNAMIC
99};
100
101struct vpe;
102typedef struct tc {
103 enum tc_state state;
104 int index;
105
106 /* parent VPE */
107 struct vpe *pvpe;
108
109 /* The list of TC's with this VPE */
110 struct list_head tc;
111
112 /* The global list of tc's */
113 struct list_head list;
114} tc_t;
115
116typedef struct vpe {
117 enum vpe_state state;
118
119 /* (device) minor associated with this vpe */
120 int minor;
121
122 /* elfloader stuff */
123 void *load_addr;
124 u32 len;
125 char *pbuffer;
126 u32 plen;
127
128 unsigned long __start;
129
130 /* tc's associated with this vpe */
131 struct list_head tc;
132
133 /* The list of vpe's */
134 struct list_head list;
135
136 /* shared symbol address */
137 void *shared_ptr;
138} vpe_t;
139
140struct vpecontrol_ {
141 /* Virtual processing elements */
142 struct list_head vpe_list;
143
144 /* Thread contexts */
145 struct list_head tc_list;
146} vpecontrol;
147
148static void release_progmem(void *ptr);
149static void dump_vpe(vpe_t * v);
150extern void save_gp_address(unsigned int secbase, unsigned int rel);
151
152/* get the vpe associated with this minor */
153struct vpe *get_vpe(int minor)
154{
155 struct vpe *v;
156
157 list_for_each_entry(v, &vpecontrol.vpe_list, list) {
158 if (v->minor == minor)
159 return v;
160 }
161
162 printk(KERN_DEBUG "VPE: get_vpe minor %d not found\n", minor);
163 return NULL;
164}
165
166/* get the vpe associated with this minor */
167struct tc *get_tc(int index)
168{
169 struct tc *t;
170
171 list_for_each_entry(t, &vpecontrol.tc_list, list) {
172 if (t->index == index)
173 return t;
174 }
175
176 printk(KERN_DEBUG "VPE: get_tc index %d not found\n", index);
177
178 return NULL;
179}
180
181struct tc *get_tc_unused(void)
182{
183 struct tc *t;
184
185 list_for_each_entry(t, &vpecontrol.tc_list, list) {
186 if (t->state == TC_STATE_UNUSED)
187 return t;
188 }
189
190 printk(KERN_DEBUG "VPE: All TC's are in use\n");
191
192 return NULL;
193}
194
195/* allocate a vpe and associate it with this minor (or index) */
196struct vpe *alloc_vpe(int minor)
197{
198 struct vpe *v;
199
200 if ((v = kmalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL) {
201 printk(KERN_WARNING "VPE: alloc_vpe no mem\n");
202 return NULL;
203 }
204
205 memset(v, 0, sizeof(struct vpe));
206
207 INIT_LIST_HEAD(&v->tc);
208 list_add_tail(&v->list, &vpecontrol.vpe_list);
209
210 v->minor = minor;
211 return v;
212}
213
214/* allocate a tc. At startup only tc0 is running, all other can be halted. */
215struct tc *alloc_tc(int index)
216{
217 struct tc *t;
218
219 if ((t = kmalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) {
220 printk(KERN_WARNING "VPE: alloc_tc no mem\n");
221 return NULL;
222 }
223
224 memset(t, 0, sizeof(struct tc));
225
226 INIT_LIST_HEAD(&t->tc);
227 list_add_tail(&t->list, &vpecontrol.tc_list);
228
229 t->index = index;
230
231 return t;
232}
233
234/* clean up and free everything */
235void release_vpe(struct vpe *v)
236{
237 list_del(&v->list);
238 if (v->load_addr)
239 release_progmem(v);
240 kfree(v);
241}
242
243void dump_mtregs(void)
244{
245 unsigned long val;
246
247 val = read_c0_config3();
248 printk("config3 0x%lx MT %ld\n", val,
249 (val & CONFIG3_MT) >> CONFIG3_MT_SHIFT);
250
251 val = read_c0_mvpconf0();
252 printk("mvpconf0 0x%lx, PVPE %ld PTC %ld M %ld\n", val,
253 (val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT,
254 val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT);
255
256 val = read_c0_mvpcontrol();
257 printk("MVPControl 0x%lx, STLB %ld VPC %ld EVP %ld\n", val,
258 (val & MVPCONTROL_STLB) >> MVPCONTROL_STLB_SHIFT,
259 (val & MVPCONTROL_VPC) >> MVPCONTROL_VPC_SHIFT,
260 (val & MVPCONTROL_EVP));
261
262 val = read_c0_vpeconf0();
263 printk("VPEConf0 0x%lx MVP %ld\n", val,
264 (val & VPECONF0_MVP) >> VPECONF0_MVP_SHIFT);
265}
266
267/* Find some VPE program space */
268static void *alloc_progmem(u32 len)
269{
270#ifdef CONFIG_MIPS_VPE_LOADER_TOM
271 /* this means you must tell linux to use less memory than you physically have */
272 return (void *)((max_pfn * PAGE_SIZE) + KSEG0);
273#else
274 // simple grab some mem for now
275 return kmalloc(len, GFP_KERNEL);
276#endif
277}
278
279static void release_progmem(void *ptr)
280{
281#ifndef CONFIG_MIPS_VPE_LOADER_TOM
282 kfree(ptr);
283#endif
284}
285
286/* Update size with this section: return offset. */
287static long get_offset(unsigned long *size, Elf_Shdr * sechdr)
288{
289 long ret;
290
291 ret = ALIGN(*size, sechdr->sh_addralign ? : 1);
292 *size = ret + sechdr->sh_size;
293 return ret;
294}
295
296/* Lay out the SHF_ALLOC sections in a way not dissimilar to how ld
297 might -- code, read-only data, read-write data, small data. Tally
298 sizes, and place the offsets into sh_entsize fields: high bit means it
299 belongs in init. */
300static void layout_sections(struct module *mod, const Elf_Ehdr * hdr,
301 Elf_Shdr * sechdrs, const char *secstrings)
302{
303 static unsigned long const masks[][2] = {
304 /* NOTE: all executable code must be the first section
305 * in this array; otherwise modify the text_size
306 * finder in the two loops below */
307 {SHF_EXECINSTR | SHF_ALLOC, ARCH_SHF_SMALL},
308 {SHF_ALLOC, SHF_WRITE | ARCH_SHF_SMALL},
309 {SHF_WRITE | SHF_ALLOC, ARCH_SHF_SMALL},
310 {ARCH_SHF_SMALL | SHF_ALLOC, 0}
311 };
312 unsigned int m, i;
313
314 for (i = 0; i < hdr->e_shnum; i++)
315 sechdrs[i].sh_entsize = ~0UL;
316
317 for (m = 0; m < ARRAY_SIZE(masks); ++m) {
318 for (i = 0; i < hdr->e_shnum; ++i) {
319 Elf_Shdr *s = &sechdrs[i];
320
321 // || strncmp(secstrings + s->sh_name, ".init", 5) == 0)
322 if ((s->sh_flags & masks[m][0]) != masks[m][0]
323 || (s->sh_flags & masks[m][1])
324 || s->sh_entsize != ~0UL)
325 continue;
326 s->sh_entsize = get_offset(&mod->core_size, s);
327 }
328
329 if (m == 0)
330 mod->core_text_size = mod->core_size;
331
332 }
333}
334
335
336/* from module-elf32.c, but subverted a little */
337
338struct mips_hi16 {
339 struct mips_hi16 *next;
340 Elf32_Addr *addr;
341 Elf32_Addr value;
342};
343
344static struct mips_hi16 *mips_hi16_list;
345static unsigned int gp_offs, gp_addr;
346
347static int apply_r_mips_none(struct module *me, uint32_t *location,
348 Elf32_Addr v)
349{
350 return 0;
351}
352
353static int apply_r_mips_gprel16(struct module *me, uint32_t *location,
354 Elf32_Addr v)
355{
356 int rel;
357
358 if( !(*location & 0xffff) ) {
359 rel = (int)v - gp_addr;
360 }
361 else {
362 /* .sbss + gp(relative) + offset */
363 /* kludge! */
364 rel = (int)(short)((int)v + gp_offs +
365 (int)(short)(*location & 0xffff) - gp_addr);
366 }
367
368 if( (rel > 32768) || (rel < -32768) ) {
369 printk(KERN_ERR
370 "apply_r_mips_gprel16: relative address out of range 0x%x %d\n",
371 rel, rel);
372 return -ENOEXEC;
373 }
374
375 *location = (*location & 0xffff0000) | (rel & 0xffff);
376
377 return 0;
378}
379
380static int apply_r_mips_pc16(struct module *me, uint32_t *location,
381 Elf32_Addr v)
382{
383 int rel;
384 rel = (((unsigned int)v - (unsigned int)location));
385 rel >>= 2; // because the offset is in _instructions_ not bytes.
386 rel -= 1; // and one instruction less due to the branch delay slot.
387
388 if( (rel > 32768) || (rel < -32768) ) {
389 printk(KERN_ERR
390 "apply_r_mips_pc16: relative address out of range 0x%x\n", rel);
391 return -ENOEXEC;
392 }
393
394 *location = (*location & 0xffff0000) | (rel & 0xffff);
395
396 return 0;
397}
398
399static int apply_r_mips_32(struct module *me, uint32_t *location,
400 Elf32_Addr v)
401{
402 *location += v;
403
404 return 0;
405}
406
407static int apply_r_mips_26(struct module *me, uint32_t *location,
408 Elf32_Addr v)
409{
410 if (v % 4) {
411 printk(KERN_ERR "module %s: dangerous relocation mod4\n", me->name);
412 return -ENOEXEC;
413 }
414
415/* Not desperately convinced this is a good check of an overflow condition
416 anyway. But it gets in the way of handling undefined weak symbols which
417 we want to set to zero.
418 if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
419 printk(KERN_ERR
420 "module %s: relocation overflow\n",
421 me->name);
422 return -ENOEXEC;
423 }
424*/
425
426 *location = (*location & ~0x03ffffff) |
427 ((*location + (v >> 2)) & 0x03ffffff);
428 return 0;
429}
430
431static int apply_r_mips_hi16(struct module *me, uint32_t *location,
432 Elf32_Addr v)
433{
434 struct mips_hi16 *n;
435
436 /*
437 * We cannot relocate this one now because we don't know the value of
438 * the carry we need to add. Save the information, and let LO16 do the
439 * actual relocation.
440 */
441 n = kmalloc(sizeof *n, GFP_KERNEL);
442 if (!n)
443 return -ENOMEM;
444
445 n->addr = location;
446 n->value = v;
447 n->next = mips_hi16_list;
448 mips_hi16_list = n;
449
450 return 0;
451}
452
453static int apply_r_mips_lo16(struct module *me, uint32_t *location,
454 Elf32_Addr v)
455{
456 unsigned long insnlo = *location;
457 Elf32_Addr val, vallo;
458
459 /* Sign extend the addend we extract from the lo insn. */
460 vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
461
462 if (mips_hi16_list != NULL) {
463 struct mips_hi16 *l;
464
465 l = mips_hi16_list;
466 while (l != NULL) {
467 struct mips_hi16 *next;
468 unsigned long insn;
469
470 /*
471 * The value for the HI16 had best be the same.
472 */
473 if (v != l->value) {
474 printk("%d != %d\n", v, l->value);
475 goto out_danger;
476 }
477
478
479 /*
480 * Do the HI16 relocation. Note that we actually don't
481 * need to know anything about the LO16 itself, except
482 * where to find the low 16 bits of the addend needed
483 * by the LO16.
484 */
485 insn = *l->addr;
486 val = ((insn & 0xffff) << 16) + vallo;
487 val += v;
488
489 /*
490 * Account for the sign extension that will happen in
491 * the low bits.
492 */
493 val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff;
494
495 insn = (insn & ~0xffff) | val;
496 *l->addr = insn;
497
498 next = l->next;
499 kfree(l);
500 l = next;
501 }
502
503 mips_hi16_list = NULL;
504 }
505
506 /*
507 * Ok, we're done with the HI16 relocs. Now deal with the LO16.
508 */
509 val = v + vallo;
510 insnlo = (insnlo & ~0xffff) | (val & 0xffff);
511 *location = insnlo;
512
513 return 0;
514
515out_danger:
516 printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name);
517
518 return -ENOEXEC;
519}
520
521static int (*reloc_handlers[]) (struct module *me, uint32_t *location,
522 Elf32_Addr v) = {
523 [R_MIPS_NONE] = apply_r_mips_none,
524 [R_MIPS_32] = apply_r_mips_32,
525 [R_MIPS_26] = apply_r_mips_26,
526 [R_MIPS_HI16] = apply_r_mips_hi16,
527 [R_MIPS_LO16] = apply_r_mips_lo16,
528 [R_MIPS_GPREL16] = apply_r_mips_gprel16,
529 [R_MIPS_PC16] = apply_r_mips_pc16
530};
531
532
533int apply_relocations(Elf32_Shdr *sechdrs,
534 const char *strtab,
535 unsigned int symindex,
536 unsigned int relsec,
537 struct module *me)
538{
539 Elf32_Rel *rel = (void *) sechdrs[relsec].sh_addr;
540 Elf32_Sym *sym;
541 uint32_t *location;
542 unsigned int i;
543 Elf32_Addr v;
544 int res;
545
546 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
547 Elf32_Word r_info = rel[i].r_info;
548
549 /* This is where to make the change */
550 location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
551 + rel[i].r_offset;
552 /* This is the symbol it is referring to */
553 sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
554 + ELF32_R_SYM(r_info);
555
556 if (!sym->st_value) {
557 printk(KERN_DEBUG "%s: undefined weak symbol %s\n",
558 me->name, strtab + sym->st_name);
559 /* just print the warning, dont barf */
560 }
561
562 v = sym->st_value;
563
564 res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v);
565 if( res ) {
566 printk(KERN_DEBUG
567 "relocation error 0x%x sym refer <%s> value 0x%x "
568 "type 0x%x r_info 0x%x\n",
569 (unsigned int)location, strtab + sym->st_name, v,
570 r_info, ELF32_R_TYPE(r_info));
571 }
572
573 if (res)
574 return res;
575 }
576
577 return 0;
578}
579
580void save_gp_address(unsigned int secbase, unsigned int rel)
581{
582 gp_addr = secbase + rel;
583 gp_offs = gp_addr - (secbase & 0xffff0000);
584}
585/* end module-elf32.c */
586
587
588
589/* Change all symbols so that sh_value encodes the pointer directly. */
590static int simplify_symbols(Elf_Shdr * sechdrs,
591 unsigned int symindex,
592 const char *strtab,
593 const char *secstrings,
594 unsigned int nsecs, struct module *mod)
595{
596 Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr;
597 unsigned long secbase, bssbase = 0;
598 unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym);
599 int ret = 0, size;
600
601 /* find the .bss section for COMMON symbols */
602 for (i = 0; i < nsecs; i++) {
603 if (strncmp(secstrings + sechdrs[i].sh_name, ".bss", 4) == 0)
604 bssbase = sechdrs[i].sh_addr;
605 }
606
607 for (i = 1; i < n; i++) {
608 switch (sym[i].st_shndx) {
609 case SHN_COMMON:
610 /* Allocate space for the symbol in the .bss section. st_value is currently size.
611 We want it to have the address of the symbol. */
612
613 size = sym[i].st_value;
614 sym[i].st_value = bssbase;
615
616 bssbase += size;
617 break;
618
619 case SHN_ABS:
620 /* Don't need to do anything */
621 break;
622
623 case SHN_UNDEF:
624 /* ret = -ENOENT; */
625 break;
626
627 case SHN_MIPS_SCOMMON:
628
629 printk(KERN_DEBUG
630 "simplify_symbols: ignoring SHN_MIPS_SCOMMON symbol <%s> st_shndx %d\n",
631 strtab + sym[i].st_name, sym[i].st_shndx);
632
633 // .sbss section
634 break;
635
636 default:
637 secbase = sechdrs[sym[i].st_shndx].sh_addr;
638
639 if (strncmp(strtab + sym[i].st_name, "_gp", 3) == 0) {
640 save_gp_address(secbase, sym[i].st_value);
641 }
642
643 sym[i].st_value += secbase;
644 break;
645 }
646
647 }
648
649 return ret;
650}
651
652#ifdef DEBUG_ELFLOADER
653static void dump_elfsymbols(Elf_Shdr * sechdrs, unsigned int symindex,
654 const char *strtab, struct module *mod)
655{
656 Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr;
657 unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym);
658
659 printk(KERN_DEBUG "dump_elfsymbols: n %d\n", n);
660 for (i = 1; i < n; i++) {
661 printk(KERN_DEBUG " i %d name <%s> 0x%x\n", i,
662 strtab + sym[i].st_name, sym[i].st_value);
663 }
664}
665#endif
666
667static void dump_tc(struct tc *t)
668{
669 printk(KERN_WARNING "VPE: TC index %d TCStatus 0x%lx halt 0x%lx\n",
670 t->index, read_tc_c0_tcstatus(), read_tc_c0_tchalt());
671 printk(KERN_WARNING "VPE: tcrestart 0x%lx\n", read_tc_c0_tcrestart());
672}
673
674static void dump_tclist(void)
675{
676 struct tc *t;
677
678 list_for_each_entry(t, &vpecontrol.tc_list, list) {
679 dump_tc(t);
680 }
681}
682
683/* We are prepared so configure and start the VPE... */
684int vpe_run(vpe_t * v)
685{
686 unsigned long val;
687 struct tc *t;
688
689 /* check we are the Master VPE */
690 val = read_c0_vpeconf0();
691 if (!(val & VPECONF0_MVP)) {
692 printk(KERN_WARNING
693 "VPE: only Master VPE's are allowed to configure MT\n");
694 return -1;
695 }
696
697 /* disable MT (using dvpe) */
698 dvpe();
699
700 /* Put MVPE's into 'configuration state' */
701 set_c0_mvpcontrol(MVPCONTROL_VPC);
702
703 if (!list_empty(&v->tc)) {
704 if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) {
705 printk(KERN_WARNING "VPE: TC %d is already in use.\n",
706 t->index);
707 return -ENOEXEC;
708 }
709 } else {
710 printk(KERN_WARNING "VPE: No TC's associated with VPE %d\n",
711 v->minor);
712 return -ENOEXEC;
713 }
714
715 settc(t->index);
716
717 val = read_vpe_c0_vpeconf0();
718
719 /* should check it is halted, and not activated */
720 if ((read_tc_c0_tcstatus() & TCSTATUS_A) || !(read_tc_c0_tchalt() & TCHALT_H)) {
721 printk(KERN_WARNING "VPE: TC %d is already doing something!\n",
722 t->index);
723
724 dump_tclist();
725 return -ENOEXEC;
726 }
727
728 /* Write the address we want it to start running from in the TCPC register. */
729 write_tc_c0_tcrestart((unsigned long)v->__start);
730
731 /* write the sivc_info address to tccontext */
732 write_tc_c0_tccontext((unsigned long)0);
733
734 /* Set up the XTC bit in vpeconf0 to point at our tc */
735 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (t->index << VPECONF0_XTC_SHIFT));
736
737 /* mark the TC as activated, not interrupt exempt and not dynamically allocatable */
738 val = read_tc_c0_tcstatus();
739 val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A;
740 write_tc_c0_tcstatus(val);
741
742 write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H);
743
744 /* set up VPE1 */
745 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); // no multiple TC's
746 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); // enable this VPE
747
748 /*
749 * The sde-kit passes 'memsize' to __start in $a3, so set something
750 * here...
751 * Or set $a3 (register 7) to zero and define DFLT_STACK_SIZE and
752 * DFLT_HEAP_SIZE when you compile your program
753 */
754
755 mttgpr(7, 0);
756
757 /* set config to be the same as vpe0, particularly kseg0 coherency alg */
758 write_vpe_c0_config(read_c0_config());
759
760 /* clear out any left overs from a previous program */
761 write_vpe_c0_cause(0);
762
763 /* take system out of configuration state */
764 clear_c0_mvpcontrol(MVPCONTROL_VPC);
765
766 /* clear interrupts enabled IE, ERL, EXL, and KSU from c0 status */
767 write_vpe_c0_status(read_vpe_c0_status() & ~(ST0_ERL | ST0_KSU | ST0_IE | ST0_EXL));
768
769 /* set it running */
770 evpe(EVPE_ENABLE);
771
772 return 0;
773}
774
775static unsigned long find_vpe_symbols(vpe_t * v, Elf_Shdr * sechdrs,
776 unsigned int symindex, const char *strtab,
777 struct module *mod)
778{
779 Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr;
780 unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym);
781
782 for (i = 1; i < n; i++) {
783 if (strcmp(strtab + sym[i].st_name, "__start") == 0) {
784 v->__start = sym[i].st_value;
785 }
786
787 if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) {
788 v->shared_ptr = (void *)sym[i].st_value;
789 }
790 }
791
792 return 0;
793}
794
795/* Allocates a VPE with some program code space(the load address), copies the contents
796 of the program (p)buffer performing relocatations/etc, free's it when finished.
797*/
798int vpe_elfload(vpe_t * v)
799{
800 Elf_Ehdr *hdr;
801 Elf_Shdr *sechdrs;
802 long err = 0;
803 char *secstrings, *strtab = NULL;
804 unsigned int len, i, symindex = 0, strindex = 0;
805
806 struct module mod; // so we can re-use the relocations code
807
808 memset(&mod, 0, sizeof(struct module));
809 strcpy(mod.name, "VPE dummy prog module");
810
811 hdr = (Elf_Ehdr *) v->pbuffer;
812 len = v->plen;
813
814 /* Sanity checks against insmoding binaries or wrong arch,
815 weird elf version */
816 if (memcmp(hdr->e_ident, ELFMAG, 4) != 0
817 || hdr->e_type != ET_REL || !elf_check_arch(hdr)
818 || hdr->e_shentsize != sizeof(*sechdrs)) {
819 printk(KERN_WARNING
820 "VPE program, wrong arch or weird elf version\n");
821
822 return -ENOEXEC;
823 }
824
825 if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) {
826 printk(KERN_ERR "VPE program length %u truncated\n", len);
827 return -ENOEXEC;
828 }
829
830 /* Convenience variables */
831 sechdrs = (void *)hdr + hdr->e_shoff;
832 secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
833 sechdrs[0].sh_addr = 0;
834
835 /* And these should exist, but gcc whinges if we don't init them */
836 symindex = strindex = 0;
837
838 for (i = 1; i < hdr->e_shnum; i++) {
839
840 if (sechdrs[i].sh_type != SHT_NOBITS
841 && len < sechdrs[i].sh_offset + sechdrs[i].sh_size) {
842 printk(KERN_ERR "VPE program length %u truncated\n",
843 len);
844 return -ENOEXEC;
845 }
846
847 /* Mark all sections sh_addr with their address in the
848 temporary image. */
849 sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset;
850
851 /* Internal symbols and strings. */
852 if (sechdrs[i].sh_type == SHT_SYMTAB) {
853 symindex = i;
854 strindex = sechdrs[i].sh_link;
855 strtab = (char *)hdr + sechdrs[strindex].sh_offset;
856 }
857 }
858
859 layout_sections(&mod, hdr, sechdrs, secstrings);
860
861 v->load_addr = alloc_progmem(mod.core_size);
862 memset(v->load_addr, 0, mod.core_size);
863
864 printk("VPE elf_loader: loading to %p\n", v->load_addr);
865
866 for (i = 0; i < hdr->e_shnum; i++) {
867 void *dest;
868
869 if (!(sechdrs[i].sh_flags & SHF_ALLOC))
870 continue;
871
872 dest = v->load_addr + sechdrs[i].sh_entsize;
873
874 if (sechdrs[i].sh_type != SHT_NOBITS)
875 memcpy(dest, (void *)sechdrs[i].sh_addr,
876 sechdrs[i].sh_size);
877 /* Update sh_addr to point to copy in image. */
878 sechdrs[i].sh_addr = (unsigned long)dest;
879 }
880
881 /* Fix up syms, so that st_value is a pointer to location. */
882 err =
883 simplify_symbols(sechdrs, symindex, strtab, secstrings,
884 hdr->e_shnum, &mod);
885 if (err < 0) {
886 printk(KERN_WARNING "VPE: unable to simplify symbols\n");
887 goto cleanup;
888 }
889
890 /* Now do relocations. */
891 for (i = 1; i < hdr->e_shnum; i++) {
892 const char *strtab = (char *)sechdrs[strindex].sh_addr;
893 unsigned int info = sechdrs[i].sh_info;
894
895 /* Not a valid relocation section? */
896 if (info >= hdr->e_shnum)
897 continue;
898
899 /* Don't bother with non-allocated sections */
900 if (!(sechdrs[info].sh_flags & SHF_ALLOC))
901 continue;
902
903 if (sechdrs[i].sh_type == SHT_REL)
904 err =
905 apply_relocations(sechdrs, strtab, symindex, i, &mod);
906 else if (sechdrs[i].sh_type == SHT_RELA)
907 err = apply_relocate_add(sechdrs, strtab, symindex, i,
908 &mod);
909 if (err < 0) {
910 printk(KERN_WARNING
911 "vpe_elfload: error in relocations err %ld\n",
912 err);
913 goto cleanup;
914 }
915 }
916
917 /* make sure it's physically written out */
918 flush_icache_range((unsigned long)v->load_addr,
919 (unsigned long)v->load_addr + v->len);
920
921 if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) {
922
923 printk(KERN_WARNING
924 "VPE: program doesn't contain __start or vpe_shared symbols\n");
925 err = -ENOEXEC;
926 }
927
928 printk(" elf loaded\n");
929
930cleanup:
931 return err;
932}
933
934static void dump_vpe(vpe_t * v)
935{
936 struct tc *t;
937
938 printk(KERN_DEBUG "VPEControl 0x%lx\n", read_vpe_c0_vpecontrol());
939 printk(KERN_DEBUG "VPEConf0 0x%lx\n", read_vpe_c0_vpeconf0());
940
941 list_for_each_entry(t, &vpecontrol.tc_list, list) {
942 dump_tc(t);
943 }
944}
945
946/* checks for VPE is unused and gets ready to load program */
947static int vpe_open(struct inode *inode, struct file *filp)
948{
949 int minor;
950 vpe_t *v;
951
952 /* assume only 1 device at the mo. */
953 if ((minor = MINOR(inode->i_rdev)) != 1) {
954 printk(KERN_WARNING "VPE: only vpe1 is supported\n");
955 return -ENODEV;
956 }
957
958 if ((v = get_vpe(minor)) == NULL) {
959 printk(KERN_WARNING "VPE: unable to get vpe\n");
960 return -ENODEV;
961 }
962
963 if (v->state != VPE_STATE_UNUSED) {
964 unsigned long tmp;
965 struct tc *t;
966
967 printk(KERN_WARNING "VPE: device %d already in use\n", minor);
968
969 dvpe();
970 dump_vpe(v);
971
972 printk(KERN_WARNING "VPE: re-initialising %d\n", minor);
973
974 release_progmem(v->load_addr);
975
976 t = get_tc(minor);
977 settc(minor);
978 tmp = read_tc_c0_tcstatus();
979
980 /* mark not allocated and not dynamically allocatable */
981 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
982 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
983 write_tc_c0_tcstatus(tmp);
984
985 write_tc_c0_tchalt(TCHALT_H);
986
987 }
988
989 // allocate it so when we get write ops we know it's expected.
990 v->state = VPE_STATE_INUSE;
991
992 /* this of-course trashes what was there before... */
993 v->pbuffer = vmalloc(P_SIZE);
994 v->plen = P_SIZE;
995 v->load_addr = NULL;
996 v->len = 0;
997
998 return 0;
999}
1000
1001static int vpe_release(struct inode *inode, struct file *filp)
1002{
1003 int minor, ret = 0;
1004 vpe_t *v;
1005 Elf_Ehdr *hdr;
1006
1007 minor = MINOR(inode->i_rdev);
1008 if ((v = get_vpe(minor)) == NULL)
1009 return -ENODEV;
1010
1011 // simple case of fire and forget, so tell the VPE to run...
1012
1013 hdr = (Elf_Ehdr *) v->pbuffer;
1014 if (memcmp(hdr->e_ident, ELFMAG, 4) == 0) {
1015 if (vpe_elfload(v) >= 0)
1016 vpe_run(v);
1017 else {
1018 printk(KERN_WARNING "VPE: ELF load failed.\n");
1019 ret = -ENOEXEC;
1020 }
1021 } else {
1022 printk(KERN_WARNING "VPE: only elf files are supported\n");
1023 ret = -ENOEXEC;
1024 }
1025
1026 // cleanup any temp buffers
1027 if (v->pbuffer)
1028 vfree(v->pbuffer);
1029 v->plen = 0;
1030 return ret;
1031}
1032
1033static ssize_t vpe_write(struct file *file, const char __user * buffer,
1034 size_t count, loff_t * ppos)
1035{
1036 int minor;
1037 size_t ret = count;
1038 vpe_t *v;
1039
1040 minor = MINOR(file->f_dentry->d_inode->i_rdev);
1041 if ((v = get_vpe(minor)) == NULL)
1042 return -ENODEV;
1043
1044 if (v->pbuffer == NULL) {
1045 printk(KERN_ERR "vpe_write: no pbuffer\n");
1046 return -ENOMEM;
1047 }
1048
1049 if ((count + v->len) > v->plen) {
1050 printk(KERN_WARNING
1051 "VPE Loader: elf size too big. Perhaps strip uneeded symbols\n");
1052 return -ENOMEM;
1053 }
1054
1055 count -= copy_from_user(v->pbuffer + v->len, buffer, count);
1056 if (!count) {
1057 printk("vpe_write: copy_to_user failed\n");
1058 return -EFAULT;
1059 }
1060
1061 v->len += count;
1062 return ret;
1063}
1064
1065static struct file_operations vpe_fops = {
1066 .owner = THIS_MODULE,
1067 .open = vpe_open,
1068 .release = vpe_release,
1069 .write = vpe_write
1070};
1071
1072/* module wrapper entry points */
1073/* give me a vpe */
1074vpe_handle vpe_alloc(void)
1075{
1076 int i;
1077 struct vpe *v;
1078
1079 /* find a vpe */
1080 for (i = 1; i < MAX_VPES; i++) {
1081 if ((v = get_vpe(i)) != NULL) {
1082 v->state = VPE_STATE_INUSE;
1083 return v;
1084 }
1085 }
1086 return NULL;
1087}
1088
1089EXPORT_SYMBOL(vpe_alloc);
1090
1091/* start running from here */
1092int vpe_start(vpe_handle vpe, unsigned long start)
1093{
1094 struct vpe *v = vpe;
1095
1096 v->__start = start;
1097 return vpe_run(v);
1098}
1099
1100EXPORT_SYMBOL(vpe_start);
1101
1102/* halt it for now */
1103int vpe_stop(vpe_handle vpe)
1104{
1105 struct vpe *v = vpe;
1106 struct tc *t;
1107 unsigned int evpe_flags;
1108
1109 evpe_flags = dvpe();
1110
1111 if ((t = list_entry(v->tc.next, struct tc, tc)) != NULL) {
1112
1113 settc(t->index);
1114 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
1115 }
1116
1117 evpe(evpe_flags);
1118
1119 return 0;
1120}
1121
1122EXPORT_SYMBOL(vpe_stop);
1123
1124/* I've done with it thank you */
1125int vpe_free(vpe_handle vpe)
1126{
1127 struct vpe *v = vpe;
1128 struct tc *t;
1129 unsigned int evpe_flags;
1130
1131 if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) {
1132 return -ENOEXEC;
1133 }
1134
1135 evpe_flags = dvpe();
1136
1137 /* Put MVPE's into 'configuration state' */
1138 set_c0_mvpcontrol(MVPCONTROL_VPC);
1139
1140 settc(t->index);
1141 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
1142
1143 /* mark the TC unallocated and halt'ed */
1144 write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A);
1145 write_tc_c0_tchalt(TCHALT_H);
1146
1147 v->state = VPE_STATE_UNUSED;
1148
1149 clear_c0_mvpcontrol(MVPCONTROL_VPC);
1150 evpe(evpe_flags);
1151
1152 return 0;
1153}
1154
1155EXPORT_SYMBOL(vpe_free);
1156
1157void *vpe_get_shared(int index)
1158{
1159 struct vpe *v;
1160
1161 if ((v = get_vpe(index)) == NULL) {
1162 printk(KERN_WARNING "vpe: invalid vpe index %d\n", index);
1163 return NULL;
1164 }
1165
1166 return v->shared_ptr;
1167}
1168
1169EXPORT_SYMBOL(vpe_get_shared);
1170
1171static int __init vpe_module_init(void)
1172{
1173 struct vpe *v = NULL;
1174 struct tc *t;
1175 unsigned long val;
1176 int i;
1177
1178 if (!cpu_has_mipsmt) {
1179 printk("VPE loader: not a MIPS MT capable processor\n");
1180 return -ENODEV;
1181 }
1182
1183 if ((major = register_chrdev(VPE_MAJOR, module_name, &vpe_fops) < 0)) {
1184 printk("VPE loader: unable to register character device\n");
1185 return -EBUSY;
1186 }
1187
1188 if (major == 0)
1189 major = VPE_MAJOR;
1190
1191 dmt();
1192 dvpe();
1193
1194 /* Put MVPE's into 'configuration state' */
1195 set_c0_mvpcontrol(MVPCONTROL_VPC);
1196
1197 /* dump_mtregs(); */
1198
1199 INIT_LIST_HEAD(&vpecontrol.vpe_list);
1200 INIT_LIST_HEAD(&vpecontrol.tc_list);
1201
1202 val = read_c0_mvpconf0();
1203 for (i = 0; i < ((val & MVPCONF0_PTC) + 1); i++) {
1204 t = alloc_tc(i);
1205
1206 /* VPE's */
1207 if (i < ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1) {
1208 settc(i);
1209
1210 if ((v = alloc_vpe(i)) == NULL) {
1211 printk(KERN_WARNING "VPE: unable to allocate VPE\n");
1212 return -ENODEV;
1213 }
1214
1215 list_add(&t->tc, &v->tc); /* add the tc to the list of this vpe's tc's. */
1216
1217 /* deactivate all but vpe0 */
1218 if (i != 0) {
1219 unsigned long tmp = read_vpe_c0_vpeconf0();
1220
1221 tmp &= ~VPECONF0_VPA;
1222
1223 /* master VPE */
1224 tmp |= VPECONF0_MVP;
1225 write_vpe_c0_vpeconf0(tmp);
1226 }
1227
1228 /* disable multi-threading with TC's */
1229 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
1230
1231 if (i != 0) {
1232 write_vpe_c0_status((read_c0_status() &
1233 ~(ST0_IM | ST0_IE | ST0_KSU))
1234 | ST0_CU0);
1235
1236 /* set config to be the same as vpe0, particularly kseg0 coherency alg */
1237 write_vpe_c0_config(read_c0_config());
1238 }
1239
1240 }
1241
1242 /* TC's */
1243 t->pvpe = v; /* set the parent vpe */
1244
1245 if (i != 0) {
1246 unsigned long tmp;
1247
1248 /* tc 0 will of course be running.... */
1249 if (i == 0)
1250 t->state = TC_STATE_RUNNING;
1251
1252 settc(i);
1253
1254 /* bind a TC to each VPE, May as well put all excess TC's
1255 on the last VPE */
1256 if (i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1))
1257 write_tc_c0_tcbind(read_tc_c0_tcbind() |
1258 ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
1259 else
1260 write_tc_c0_tcbind(read_tc_c0_tcbind() | i);
1261
1262 tmp = read_tc_c0_tcstatus();
1263
1264 /* mark not allocated and not dynamically allocatable */
1265 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
1266 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
1267 write_tc_c0_tcstatus(tmp);
1268
1269 write_tc_c0_tchalt(TCHALT_H);
1270 }
1271 }
1272
1273 /* release config state */
1274 clear_c0_mvpcontrol(MVPCONTROL_VPC);
1275
1276 return 0;
1277}
1278
1279static void __exit vpe_module_exit(void)
1280{
1281 struct vpe *v, *n;
1282
1283 list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) {
1284 if (v->state != VPE_STATE_UNUSED) {
1285 release_vpe(v);
1286 }
1287 }
1288
1289 unregister_chrdev(major, module_name);
1290}
1291
1292module_init(vpe_module_init);
1293module_exit(vpe_module_exit);
1294MODULE_DESCRIPTION("MIPS VPE Loader");
1295MODULE_AUTHOR("Elizabeth Clarke, MIPS Technologies, Inc");
1296MODULE_LICENSE("GPL");
diff --git a/arch/mips/lasat/Kconfig b/arch/mips/lasat/Kconfig
new file mode 100644
index 000000000000..1d2ee8a9be13
--- /dev/null
+++ b/arch/mips/lasat/Kconfig
@@ -0,0 +1,15 @@
1config PICVUE
2 tristate "PICVUE LCD display driver"
3 depends on LASAT
4
5config PICVUE_PROC
6 tristate "PICVUE LCD display driver /proc interface"
7 depends on PICVUE
8
9config DS1603
10 bool "DS1603 RTC driver"
11 depends on LASAT
12
13config LASAT_SYSCTL
14 bool "LASAT sysctl interface"
15 depends on LASAT
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index c90da1639440..852a41901a5e 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -71,14 +71,13 @@ static void end_lasat_irq(unsigned int irq)
71} 71}
72 72
73static struct hw_interrupt_type lasat_irq_type = { 73static struct hw_interrupt_type lasat_irq_type = {
74 "Lasat", 74 .typename = "Lasat",
75 startup_lasat_irq, 75 .startup = startup_lasat_irq,
76 shutdown_lasat_irq, 76 .shutdown = shutdown_lasat_irq,
77 enable_lasat_irq, 77 .enable = enable_lasat_irq,
78 disable_lasat_irq, 78 .disable = disable_lasat_irq,
79 mask_and_ack_lasat_irq, 79 .ack = mask_and_ack_lasat_irq,
80 end_lasat_irq, 80 .end = end_lasat_irq,
81 NULL
82}; 81};
83 82
84static inline int ls1bit32(unsigned int x) 83static inline int ls1bit32(unsigned int x)
diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c
index f2604fab9a99..dcd819d57dae 100644
--- a/arch/mips/lasat/setup.c
+++ b/arch/mips/lasat/setup.c
@@ -155,7 +155,7 @@ void __init serial_init(void)
155} 155}
156#endif 156#endif
157 157
158static int __init lasat_setup(void) 158void __init plat_setup(void)
159{ 159{
160 int i; 160 int i;
161 lasat_misc = &lasat_misc_info[mips_machtype]; 161 lasat_misc = &lasat_misc_info[mips_machtype];
@@ -185,8 +185,4 @@ static int __init lasat_setup(void)
185 change_c0_status(ST0_BEV,0); 185 change_c0_status(ST0_BEV,0);
186 186
187 prom_printf("Lasat specific initialization complete\n"); 187 prom_printf("Lasat specific initialization complete\n");
188
189 return 0;
190} 188}
191
192early_initcall(lasat_setup);
diff --git a/arch/mips/lib-32/dump_tlb.c b/arch/mips/lib-32/dump_tlb.c
index 019ac8f005d7..46519f4331eb 100644
--- a/arch/mips/lib-32/dump_tlb.c
+++ b/arch/mips/lib-32/dump_tlb.c
@@ -20,16 +20,25 @@
20static inline const char *msk2str(unsigned int mask) 20static inline const char *msk2str(unsigned int mask)
21{ 21{
22 switch (mask) { 22 switch (mask) {
23 case PM_4K: return "4kb"; 23 case PM_4K:
24 case PM_16K: return "16kb"; 24 return "4kb";
25 case PM_64K: return "64kb"; 25 case PM_16K:
26 case PM_256K: return "256kb"; 26 return "16kb";
27 case PM_64K:
28 return "64kb";
29 case PM_256K:
30 return "256kb";
27#ifndef CONFIG_CPU_VR41XX 31#ifndef CONFIG_CPU_VR41XX
28 case PM_1M: return "1Mb"; 32 case PM_1M:
29 case PM_4M: return "4Mb"; 33 return "1Mb";
30 case PM_16M: return "16Mb"; 34 case PM_4M:
31 case PM_64M: return "64Mb"; 35 return "4Mb";
32 case PM_256M: return "256Mb"; 36 case PM_16M:
37 return "16Mb";
38 case PM_64M:
39 return "64Mb";
40 case PM_256M:
41 return "256Mb";
33#endif 42#endif
34 } 43 }
35 44
@@ -47,7 +56,7 @@ void dump_tlb(int first, int last)
47 unsigned int pagemask, c0, c1, asid; 56 unsigned int pagemask, c0, c1, asid;
48 unsigned long long entrylo0, entrylo1; 57 unsigned long long entrylo0, entrylo1;
49 unsigned long entryhi; 58 unsigned long entryhi;
50 int i; 59 int i;
51 60
52 asid = read_c0_entryhi() & 0xff; 61 asid = read_c0_entryhi() & 0xff;
53 62
@@ -58,7 +67,7 @@ void dump_tlb(int first, int last)
58 tlb_read(); 67 tlb_read();
59 BARRIER(); 68 BARRIER();
60 pagemask = read_c0_pagemask(); 69 pagemask = read_c0_pagemask();
61 entryhi = read_c0_entryhi(); 70 entryhi = read_c0_entryhi();
62 entrylo0 = read_c0_entrylo0(); 71 entrylo0 = read_c0_entrylo0();
63 entrylo1 = read_c0_entrylo1(); 72 entrylo1 = read_c0_entrylo1();
64 73
@@ -78,13 +87,11 @@ void dump_tlb(int first, int last)
78 printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n", 87 printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n",
79 (entrylo0 << 6) & PAGE_MASK, c0, 88 (entrylo0 << 6) & PAGE_MASK, c0,
80 (entrylo0 & 4) ? 1 : 0, 89 (entrylo0 & 4) ? 1 : 0,
81 (entrylo0 & 2) ? 1 : 0, 90 (entrylo0 & 2) ? 1 : 0, (entrylo0 & 1));
82 (entrylo0 & 1));
83 printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n", 91 printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n",
84 (entrylo1 << 6) & PAGE_MASK, c1, 92 (entrylo1 << 6) & PAGE_MASK, c1,
85 (entrylo1 & 4) ? 1 : 0, 93 (entrylo1 & 4) ? 1 : 0,
86 (entrylo1 & 2) ? 1 : 0, 94 (entrylo1 & 2) ? 1 : 0, (entrylo1 & 1));
87 (entrylo1 & 1));
88 printk("\n"); 95 printk("\n");
89 } 96 }
90 } 97 }
@@ -99,7 +106,7 @@ void dump_tlb_all(void)
99 106
100void dump_tlb_wired(void) 107void dump_tlb_wired(void)
101{ 108{
102 int wired; 109 int wired;
103 110
104 wired = read_c0_wired(); 111 wired = read_c0_wired();
105 printk("Wired: %d", wired); 112 printk("Wired: %d", wired);
@@ -138,9 +145,10 @@ void dump_tlb_nonwired(void)
138 145
139void dump_list_process(struct task_struct *t, void *address) 146void dump_list_process(struct task_struct *t, void *address)
140{ 147{
141 pgd_t *page_dir, *pgd; 148 pgd_t *page_dir, *pgd;
142 pmd_t *pmd; 149 pud_t *pud;
143 pte_t *pte, page; 150 pmd_t *pmd;
151 pte_t *pte, page;
144 unsigned long addr, val; 152 unsigned long addr, val;
145 153
146 addr = (unsigned long) address; 154 addr = (unsigned long) address;
@@ -152,21 +160,27 @@ void dump_list_process(struct task_struct *t, void *address)
152 160
153 if (addr > KSEG0) 161 if (addr > KSEG0)
154 page_dir = pgd_offset_k(0); 162 page_dir = pgd_offset_k(0);
155 else 163 else if (t->mm) {
156 page_dir = pgd_offset(t->mm, 0); 164 page_dir = pgd_offset(t->mm, 0);
157 printk("page_dir == %08x\n", (unsigned int) page_dir); 165 printk("page_dir == %08x\n", (unsigned int) page_dir);
166 } else
167 printk("Current thread has no mm\n");
158 168
159 if (addr > KSEG0) 169 if (addr > KSEG0)
160 pgd = pgd_offset_k(addr); 170 pgd = pgd_offset_k(addr);
161 else 171 else if (t->mm) {
162 pgd = pgd_offset(t->mm, addr); 172 pgd = pgd_offset(t->mm, addr);
163 printk("pgd == %08x, ", (unsigned int) pgd); 173 printk("pgd == %08x, ", (unsigned int) pgd);
174 pud = pud_offset(pgd, addr);
175 printk("pud == %08x, ", (unsigned int) pud);
164 176
165 pmd = pmd_offset(pgd, addr); 177 pmd = pmd_offset(pud, addr);
166 printk("pmd == %08x, ", (unsigned int) pmd); 178 printk("pmd == %08x, ", (unsigned int) pmd);
167 179
168 pte = pte_offset(pmd, addr); 180 pte = pte_offset(pmd, addr);
169 printk("pte == %08x, ", (unsigned int) pte); 181 printk("pte == %08x, ", (unsigned int) pte);
182 } else
183 printk("Current thread has no mm\n");
170 184
171 page = *pte; 185 page = *pte;
172#ifdef CONFIG_64BIT_PHYS_ADDR 186#ifdef CONFIG_64BIT_PHYS_ADDR
@@ -176,14 +190,22 @@ void dump_list_process(struct task_struct *t, void *address)
176#endif 190#endif
177 191
178 val = pte_val(page); 192 val = pte_val(page);
179 if (val & _PAGE_PRESENT) printk("present "); 193 if (val & _PAGE_PRESENT)
180 if (val & _PAGE_READ) printk("read "); 194 printk("present ");
181 if (val & _PAGE_WRITE) printk("write "); 195 if (val & _PAGE_READ)
182 if (val & _PAGE_ACCESSED) printk("accessed "); 196 printk("read ");
183 if (val & _PAGE_MODIFIED) printk("modified "); 197 if (val & _PAGE_WRITE)
184 if (val & _PAGE_R4KBUG) printk("r4kbug "); 198 printk("write ");
185 if (val & _PAGE_GLOBAL) printk("global "); 199 if (val & _PAGE_ACCESSED)
186 if (val & _PAGE_VALID) printk("valid "); 200 printk("accessed ");
201 if (val & _PAGE_MODIFIED)
202 printk("modified ");
203 if (val & _PAGE_R4KBUG)
204 printk("r4kbug ");
205 if (val & _PAGE_GLOBAL)
206 printk("global ");
207 if (val & _PAGE_VALID)
208 printk("valid ");
187 printk("\n"); 209 printk("\n");
188} 210}
189 211
@@ -194,14 +216,16 @@ void dump_list_current(void *address)
194 216
195unsigned int vtop(void *address) 217unsigned int vtop(void *address)
196{ 218{
197 pgd_t *pgd; 219 pgd_t *pgd;
198 pmd_t *pmd; 220 pud_t *pud;
199 pte_t *pte; 221 pmd_t *pmd;
222 pte_t *pte;
200 unsigned int addr, paddr; 223 unsigned int addr, paddr;
201 224
202 addr = (unsigned long) address; 225 addr = (unsigned long) address;
203 pgd = pgd_offset(current->mm, addr); 226 pgd = pgd_offset(current->mm, addr);
204 pmd = pmd_offset(pgd, addr); 227 pud = pud_offset(pgd, addr);
228 pmd = pmd_offset(pud, addr);
205 pte = pte_offset(pmd, addr); 229 pte = pte_offset(pmd, addr);
206 paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK; 230 paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK;
207 paddr |= (addr & ~PAGE_MASK); 231 paddr |= (addr & ~PAGE_MASK);
@@ -214,9 +238,9 @@ void dump16(unsigned long *p)
214 int i; 238 int i;
215 239
216 for (i = 0; i < 8; i++) { 240 for (i = 0; i < 8; i++) {
217 printk("*%08lx == %08lx, ", (unsigned long)p, *p); 241 printk("*%08lx == %08lx, ", (unsigned long) p, *p);
218 p++; 242 p++;
219 printk("*%08lx == %08lx\n", (unsigned long)p, *p); 243 printk("*%08lx == %08lx\n", (unsigned long) p, *p);
220 p++; 244 p++;
221 } 245 }
222} 246}
diff --git a/arch/mips/lib-32/r3k_dump_tlb.c b/arch/mips/lib-32/r3k_dump_tlb.c
index a878224004e5..4f2cb74f0766 100644
--- a/arch/mips/lib-32/r3k_dump_tlb.c
+++ b/arch/mips/lib-32/r3k_dump_tlb.c
@@ -105,6 +105,7 @@ void dump_tlb_nonwired(void)
105void dump_list_process(struct task_struct *t, void *address) 105void dump_list_process(struct task_struct *t, void *address)
106{ 106{
107 pgd_t *page_dir, *pgd; 107 pgd_t *page_dir, *pgd;
108 pud_t *pud;
108 pmd_t *pmd; 109 pmd_t *pmd;
109 pte_t *pte, page; 110 pte_t *pte, page;
110 unsigned int addr; 111 unsigned int addr;
@@ -121,7 +122,10 @@ void dump_list_process(struct task_struct *t, void *address)
121 pgd = pgd_offset(t->mm, addr); 122 pgd = pgd_offset(t->mm, addr);
122 printk("pgd == %08x, ", (unsigned int) pgd); 123 printk("pgd == %08x, ", (unsigned int) pgd);
123 124
124 pmd = pmd_offset(pgd, addr); 125 pud = pud_offset(pgd, addr);
126 printk("pud == %08x, ", (unsigned int) pud);
127
128 pmd = pmd_offset(pud, addr);
125 printk("pmd == %08x, ", (unsigned int) pmd); 129 printk("pmd == %08x, ", (unsigned int) pmd);
126 130
127 pte = pte_offset(pmd, addr); 131 pte = pte_offset(pmd, addr);
@@ -149,13 +153,15 @@ void dump_list_current(void *address)
149unsigned int vtop(void *address) 153unsigned int vtop(void *address)
150{ 154{
151 pgd_t *pgd; 155 pgd_t *pgd;
156 pud_t *pud;
152 pmd_t *pmd; 157 pmd_t *pmd;
153 pte_t *pte; 158 pte_t *pte;
154 unsigned int addr, paddr; 159 unsigned int addr, paddr;
155 160
156 addr = (unsigned long) address; 161 addr = (unsigned long) address;
157 pgd = pgd_offset(current->mm, addr); 162 pgd = pgd_offset(current->mm, addr);
158 pmd = pmd_offset(pgd, addr); 163 pud = pud_offset(pgd, addr);
164 pmd = pmd_offset(pud, addr);
159 pte = pte_offset(pmd, addr); 165 pte = pte_offset(pmd, addr);
160 paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK; 166 paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK;
161 paddr |= (addr & ~PAGE_MASK); 167 paddr |= (addr & ~PAGE_MASK);
diff --git a/arch/mips/lib-64/dump_tlb.c b/arch/mips/lib-64/dump_tlb.c
index 42f88e055b4c..11a5f015f040 100644
--- a/arch/mips/lib-64/dump_tlb.c
+++ b/arch/mips/lib-64/dump_tlb.c
@@ -140,6 +140,7 @@ void dump_tlb_nonwired(void)
140void dump_list_process(struct task_struct *t, void *address) 140void dump_list_process(struct task_struct *t, void *address)
141{ 141{
142 pgd_t *page_dir, *pgd; 142 pgd_t *page_dir, *pgd;
143 pud_t *pud;
143 pmd_t *pmd; 144 pmd_t *pmd;
144 pte_t *pte, page; 145 pte_t *pte, page;
145 unsigned long addr, val; 146 unsigned long addr, val;
@@ -155,7 +156,10 @@ void dump_list_process(struct task_struct *t, void *address)
155 pgd = pgd_offset(t->mm, addr); 156 pgd = pgd_offset(t->mm, addr);
156 printk("pgd == %016lx\n", (unsigned long) pgd); 157 printk("pgd == %016lx\n", (unsigned long) pgd);
157 158
158 pmd = pmd_offset(pgd, addr); 159 pud = pud_offset(pgd, addr);
160 printk("pud == %016lx\n", (unsigned long) pud);
161
162 pmd = pmd_offset(pud, addr);
159 printk("pmd == %016lx\n", (unsigned long) pmd); 163 printk("pmd == %016lx\n", (unsigned long) pmd);
160 164
161 pte = pte_offset(pmd, addr); 165 pte = pte_offset(pmd, addr);
@@ -184,13 +188,15 @@ void dump_list_current(void *address)
184unsigned int vtop(void *address) 188unsigned int vtop(void *address)
185{ 189{
186 pgd_t *pgd; 190 pgd_t *pgd;
191 pud_t *pud;
187 pmd_t *pmd; 192 pmd_t *pmd;
188 pte_t *pte; 193 pte_t *pte;
189 unsigned int addr, paddr; 194 unsigned int addr, paddr;
190 195
191 addr = (unsigned long) address; 196 addr = (unsigned long) address;
192 pgd = pgd_offset(current->mm, addr); 197 pgd = pgd_offset(current->mm, addr);
193 pmd = pmd_offset(pgd, addr); 198 pud = pud_offset(pgd, addr);
199 pmd = pmd_offset(pud, addr);
194 pte = pte_offset(pmd, addr); 200 pte = pte_offset(pmd, addr);
195 paddr = (CKSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK; 201 paddr = (CKSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK;
196 paddr |= (addr & ~PAGE_MASK); 202 paddr |= (addr & ~PAGE_MASK);
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 037303412909..cf12caf80774 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -2,8 +2,8 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial_copy.o memcpy.o promlib.o \ 5lib-y += csum_partial_copy.o memcpy.o promlib.o strlen_user.o strncpy_user.o \
6 strlen_user.o strncpy_user.o strnlen_user.o 6 strnlen_user.o uncached.o
7 7
8obj-y += iomap.o 8obj-y += iomap.o
9 9
diff --git a/arch/mips/lib/csum_partial_copy.c b/arch/mips/lib/csum_partial_copy.c
index ffed0a6a1c16..6e9f366f961d 100644
--- a/arch/mips/lib/csum_partial_copy.c
+++ b/arch/mips/lib/csum_partial_copy.c
@@ -16,8 +16,8 @@
16/* 16/*
17 * copy while checksumming, otherwise like csum_partial 17 * copy while checksumming, otherwise like csum_partial
18 */ 18 */
19unsigned int csum_partial_copy_nocheck(const unsigned char *src, unsigned char *dst, 19unsigned int csum_partial_copy_nocheck(const unsigned char *src,
20 int len, unsigned int sum) 20 unsigned char *dst, int len, unsigned int sum)
21{ 21{
22 /* 22 /*
23 * It's 2:30 am and I don't feel like doing it real ... 23 * It's 2:30 am and I don't feel like doing it real ...
@@ -33,8 +33,8 @@ unsigned int csum_partial_copy_nocheck(const unsigned char *src, unsigned char *
33 * Copy from userspace and compute checksum. If we catch an exception 33 * Copy from userspace and compute checksum. If we catch an exception
34 * then zero the rest of the buffer. 34 * then zero the rest of the buffer.
35 */ 35 */
36unsigned int csum_partial_copy_from_user (const unsigned char *src, unsigned char *dst, 36unsigned int csum_partial_copy_from_user (const unsigned char __user *src,
37 int len, unsigned int sum, int *err_ptr) 37 unsigned char *dst, int len, unsigned int sum, int *err_ptr)
38{ 38{
39 int missing; 39 int missing;
40 40
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index a78865f76547..7f9aafa4d80e 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -13,6 +13,21 @@
13 * Mnemonic names for arguments to memcpy/__copy_user 13 * Mnemonic names for arguments to memcpy/__copy_user
14 */ 14 */
15#include <linux/config.h> 15#include <linux/config.h>
16
17/*
18 * Hack to resolve longstanding prefetch issue
19 *
20 * Prefetching may be fatal on some systems if we're prefetching beyond the
21 * end of memory on some systems. It's also a seriously bad idea on non
22 * dma-coherent systems.
23 */
24#if !defined(CONFIG_DMA_COHERENT) || !defined(CONFIG_DMA_IP27)
25#undef CONFIG_CPU_HAS_PREFETCH
26#endif
27#ifdef CONFIG_MIPS_MALTA
28#undef CONFIG_CPU_HAS_PREFETCH
29#endif
30
16#include <asm/asm.h> 31#include <asm/asm.h>
17#include <asm/asm-offsets.h> 32#include <asm/asm-offsets.h>
18#include <asm/regdef.h> 33#include <asm/regdef.h>
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
new file mode 100644
index 000000000000..98ce89f8068b
--- /dev/null
+++ b/arch/mips/lib/uncached.c
@@ -0,0 +1,76 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 Thiemo Seufer
7 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
8 * Author: Maciej W. Rozycki <macro@mips.com>
9 */
10
11#include <linux/init.h>
12
13#include <asm/addrspace.h>
14#include <asm/bug.h>
15
16#ifndef CKSEG2
17#define CKSEG2 CKSSEG
18#endif
19#ifndef TO_PHYS_MASK
20#define TO_PHYS_MASK -1
21#endif
22
23/*
24 * FUNC is executed in one of the uncached segments, depending on its
25 * original address as follows:
26 *
27 * 1. If the original address is in CKSEG0 or CKSEG1, then the uncached
28 * segment used is CKSEG1.
29 * 2. If the original address is in XKPHYS, then the uncached segment
30 * used is XKPHYS(2).
31 * 3. Otherwise it's a bug.
32 *
33 * The same remapping is done with the stack pointer. Stack handling
34 * works because we don't handle stack arguments or more complex return
35 * values, so we can avoid sharing the same stack area between a cached
36 * and the uncached mode.
37 */
38unsigned long __init run_uncached(void *func)
39{
40 register long sp __asm__("$sp");
41 register long ret __asm__("$2");
42 long lfunc = (long)func, ufunc;
43 long usp;
44
45 if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
46 usp = CKSEG1ADDR(sp);
47 else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0LL, 0) &&
48 (long long)sp < (long long)PHYS_TO_XKPHYS(8LL, 0))
49 usp = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED,
50 XKPHYS_TO_PHYS((long long)sp));
51 else {
52 BUG();
53 usp = sp;
54 }
55 if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2)
56 ufunc = CKSEG1ADDR(lfunc);
57 else if ((long long)lfunc >= (long long)PHYS_TO_XKPHYS(0LL, 0) &&
58 (long long)lfunc < (long long)PHYS_TO_XKPHYS(8LL, 0))
59 ufunc = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED,
60 XKPHYS_TO_PHYS((long long)lfunc));
61 else {
62 BUG();
63 ufunc = lfunc;
64 }
65
66 __asm__ __volatile__ (
67 " move $16, $sp\n"
68 " move $sp, %1\n"
69 " jalr %2\n"
70 " move $sp, $16"
71 : "=r" (ret)
72 : "r" (usp), "r" (ufunc)
73 : "$16", "$31");
74
75 return ret;
76}
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 99c550632d44..aa5818a0d884 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -70,7 +70,7 @@ static int fpux_emu(struct pt_regs *,
70 70
71/* Further private data for which no space exists in mips_fpu_soft_struct */ 71/* Further private data for which no space exists in mips_fpu_soft_struct */
72 72
73struct mips_fpu_emulator_private fpuemuprivate; 73struct mips_fpu_emulator_stats fpuemustats;
74 74
75/* Control registers */ 75/* Control registers */
76 76
@@ -79,7 +79,17 @@ struct mips_fpu_emulator_private fpuemuprivate;
79 79
80/* Convert Mips rounding mode (0..3) to IEEE library modes. */ 80/* Convert Mips rounding mode (0..3) to IEEE library modes. */
81static const unsigned char ieee_rm[4] = { 81static const unsigned char ieee_rm[4] = {
82 IEEE754_RN, IEEE754_RZ, IEEE754_RU, IEEE754_RD 82 [FPU_CSR_RN] = IEEE754_RN,
83 [FPU_CSR_RZ] = IEEE754_RZ,
84 [FPU_CSR_RU] = IEEE754_RU,
85 [FPU_CSR_RD] = IEEE754_RD,
86};
87/* Convert IEEE library modes to Mips rounding mode (0..3). */
88static const unsigned char mips_rm[4] = {
89 [IEEE754_RN] = FPU_CSR_RN,
90 [IEEE754_RZ] = FPU_CSR_RZ,
91 [IEEE754_RD] = FPU_CSR_RD,
92 [IEEE754_RU] = FPU_CSR_RU,
83}; 93};
84 94
85#if __mips >= 4 95#if __mips >= 4
@@ -196,11 +206,11 @@ static int isBranchInstr(mips_instruction * i)
196static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) 206static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
197{ 207{
198 mips_instruction ir; 208 mips_instruction ir;
199 vaddr_t emulpc, contpc; 209 void * emulpc, *contpc;
200 unsigned int cond; 210 unsigned int cond;
201 211
202 if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) { 212 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
203 fpuemuprivate.stats.errors++; 213 fpuemustats.errors++;
204 return SIGBUS; 214 return SIGBUS;
205 } 215 }
206 216
@@ -221,41 +231,39 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
221 * Linux MIPS branch emulator operates on context, updating the 231 * Linux MIPS branch emulator operates on context, updating the
222 * cp0_epc. 232 * cp0_epc.
223 */ 233 */
224 emulpc = REG_TO_VA(xcp->cp0_epc + 4); /* Snapshot emulation target */ 234 emulpc = (void *) (xcp->cp0_epc + 4); /* Snapshot emulation target */
225 235
226 if (__compute_return_epc(xcp)) { 236 if (__compute_return_epc(xcp)) {
227#ifdef CP1DBG 237#ifdef CP1DBG
228 printk("failed to emulate branch at %p\n", 238 printk("failed to emulate branch at %p\n",
229 REG_TO_VA(xcp->cp0_epc)); 239 (void *) (xcp->cp0_epc));
230#endif 240#endif
231 return SIGILL; 241 return SIGILL;
232 } 242 }
233 if (get_user(ir, (mips_instruction *) emulpc)) { 243 if (get_user(ir, (mips_instruction __user *) emulpc)) {
234 fpuemuprivate.stats.errors++; 244 fpuemustats.errors++;
235 return SIGBUS; 245 return SIGBUS;
236 } 246 }
237 /* __compute_return_epc() will have updated cp0_epc */ 247 /* __compute_return_epc() will have updated cp0_epc */
238 contpc = REG_TO_VA xcp->cp0_epc; 248 contpc = (void *) xcp->cp0_epc;
239 /* In order not to confuse ptrace() et al, tweak context */ 249 /* In order not to confuse ptrace() et al, tweak context */
240 xcp->cp0_epc = VA_TO_REG emulpc - 4; 250 xcp->cp0_epc = (unsigned long) emulpc - 4;
241 } 251 } else {
242 else { 252 emulpc = (void *) xcp->cp0_epc;
243 emulpc = REG_TO_VA xcp->cp0_epc; 253 contpc = (void *) (xcp->cp0_epc + 4);
244 contpc = REG_TO_VA(xcp->cp0_epc + 4);
245 } 254 }
246 255
247 emul: 256 emul:
248 fpuemuprivate.stats.emulated++; 257 fpuemustats.emulated++;
249 switch (MIPSInst_OPCODE(ir)) { 258 switch (MIPSInst_OPCODE(ir)) {
250#ifndef SINGLE_ONLY_FPU
251 case ldc1_op:{ 259 case ldc1_op:{
252 u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 260 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
253 MIPSInst_SIMM(ir)); 261 MIPSInst_SIMM(ir));
254 u64 val; 262 u64 val;
255 263
256 fpuemuprivate.stats.loads++; 264 fpuemustats.loads++;
257 if (get_user(val, va)) { 265 if (get_user(val, va)) {
258 fpuemuprivate.stats.errors++; 266 fpuemustats.errors++;
259 return SIGBUS; 267 return SIGBUS;
260 } 268 }
261 DITOREG(val, MIPSInst_RT(ir)); 269 DITOREG(val, MIPSInst_RT(ir));
@@ -263,55 +271,42 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
263 } 271 }
264 272
265 case sdc1_op:{ 273 case sdc1_op:{
266 u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 274 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
267 MIPSInst_SIMM(ir)); 275 MIPSInst_SIMM(ir));
268 u64 val; 276 u64 val;
269 277
270 fpuemuprivate.stats.stores++; 278 fpuemustats.stores++;
271 DIFROMREG(val, MIPSInst_RT(ir)); 279 DIFROMREG(val, MIPSInst_RT(ir));
272 if (put_user(val, va)) { 280 if (put_user(val, va)) {
273 fpuemuprivate.stats.errors++; 281 fpuemustats.errors++;
274 return SIGBUS; 282 return SIGBUS;
275 } 283 }
276 break; 284 break;
277 } 285 }
278#endif
279 286
280 case lwc1_op:{ 287 case lwc1_op:{
281 u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 288 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
282 MIPSInst_SIMM(ir)); 289 MIPSInst_SIMM(ir));
283 u32 val; 290 u32 val;
284 291
285 fpuemuprivate.stats.loads++; 292 fpuemustats.loads++;
286 if (get_user(val, va)) { 293 if (get_user(val, va)) {
287 fpuemuprivate.stats.errors++; 294 fpuemustats.errors++;
288 return SIGBUS; 295 return SIGBUS;
289 } 296 }
290#ifdef SINGLE_ONLY_FPU
291 if (MIPSInst_RT(ir) & 1) {
292 /* illegal register in single-float mode */
293 return SIGILL;
294 }
295#endif
296 SITOREG(val, MIPSInst_RT(ir)); 297 SITOREG(val, MIPSInst_RT(ir));
297 break; 298 break;
298 } 299 }
299 300
300 case swc1_op:{ 301 case swc1_op:{
301 u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 302 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
302 MIPSInst_SIMM(ir)); 303 MIPSInst_SIMM(ir));
303 u32 val; 304 u32 val;
304 305
305 fpuemuprivate.stats.stores++; 306 fpuemustats.stores++;
306#ifdef SINGLE_ONLY_FPU
307 if (MIPSInst_RT(ir) & 1) {
308 /* illegal register in single-float mode */
309 return SIGILL;
310 }
311#endif
312 SIFROMREG(val, MIPSInst_RT(ir)); 307 SIFROMREG(val, MIPSInst_RT(ir));
313 if (put_user(val, va)) { 308 if (put_user(val, va)) {
314 fpuemuprivate.stats.errors++; 309 fpuemustats.errors++;
315 return SIGBUS; 310 return SIGBUS;
316 } 311 }
317 break; 312 break;
@@ -320,7 +315,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
320 case cop1_op: 315 case cop1_op:
321 switch (MIPSInst_RS(ir)) { 316 switch (MIPSInst_RS(ir)) {
322 317
323#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 318#if defined(__mips64)
324 case dmfc_op: 319 case dmfc_op:
325 /* copregister fs -> gpr[rt] */ 320 /* copregister fs -> gpr[rt] */
326 if (MIPSInst_RT(ir) != 0) { 321 if (MIPSInst_RT(ir) != 0) {
@@ -337,12 +332,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
337 332
338 case mfc_op: 333 case mfc_op:
339 /* copregister rd -> gpr[rt] */ 334 /* copregister rd -> gpr[rt] */
340#ifdef SINGLE_ONLY_FPU
341 if (MIPSInst_RD(ir) & 1) {
342 /* illegal register in single-float mode */
343 return SIGILL;
344 }
345#endif
346 if (MIPSInst_RT(ir) != 0) { 335 if (MIPSInst_RT(ir) != 0) {
347 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 336 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
348 MIPSInst_RD(ir)); 337 MIPSInst_RD(ir));
@@ -351,12 +340,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
351 340
352 case mtc_op: 341 case mtc_op:
353 /* copregister rd <- rt */ 342 /* copregister rd <- rt */
354#ifdef SINGLE_ONLY_FPU
355 if (MIPSInst_RD(ir) & 1) {
356 /* illegal register in single-float mode */
357 return SIGILL;
358 }
359#endif
360 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 343 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
361 break; 344 break;
362 345
@@ -369,9 +352,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
369 } 352 }
370 if (MIPSInst_RD(ir) == FPCREG_CSR) { 353 if (MIPSInst_RD(ir) == FPCREG_CSR) {
371 value = ctx->fcr31; 354 value = ctx->fcr31;
355 value = (value & ~0x3) | mips_rm[value & 0x3];
372#ifdef CSRTRACE 356#ifdef CSRTRACE
373 printk("%p gpr[%d]<-csr=%08x\n", 357 printk("%p gpr[%d]<-csr=%08x\n",
374 REG_TO_VA(xcp->cp0_epc), 358 (void *) (xcp->cp0_epc),
375 MIPSInst_RT(ir), value); 359 MIPSInst_RT(ir), value);
376#endif 360#endif
377 } 361 }
@@ -398,14 +382,13 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
398 if (MIPSInst_RD(ir) == FPCREG_CSR) { 382 if (MIPSInst_RD(ir) == FPCREG_CSR) {
399#ifdef CSRTRACE 383#ifdef CSRTRACE
400 printk("%p gpr[%d]->csr=%08x\n", 384 printk("%p gpr[%d]->csr=%08x\n",
401 REG_TO_VA(xcp->cp0_epc), 385 (void *) (xcp->cp0_epc),
402 MIPSInst_RT(ir), value); 386 MIPSInst_RT(ir), value);
403#endif 387#endif
404 ctx->fcr31 = value; 388 value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
405 /* copy new rounding mode and 389 ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
406 flush bit to ieee library state! */ 390 /* convert to ieee library modes */
407 ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0; 391 ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3];
408 ieee754_csr.rm = ieee_rm[value & 0x3];
409 } 392 }
410 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 393 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
411 return SIGFPE; 394 return SIGFPE;
@@ -445,20 +428,20 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
445 * instruction 428 * instruction
446 */ 429 */
447 xcp->cp0_epc += 4; 430 xcp->cp0_epc += 4;
448 contpc = REG_TO_VA 431 contpc = (void *)
449 (xcp->cp0_epc + 432 (xcp->cp0_epc +
450 (MIPSInst_SIMM(ir) << 2)); 433 (MIPSInst_SIMM(ir) << 2));
451 434
452 if (get_user(ir, (mips_instruction *) 435 if (get_user(ir,
453 REG_TO_VA xcp->cp0_epc)) { 436 (mips_instruction __user *) xcp->cp0_epc)) {
454 fpuemuprivate.stats.errors++; 437 fpuemustats.errors++;
455 return SIGBUS; 438 return SIGBUS;
456 } 439 }
457 440
458 switch (MIPSInst_OPCODE(ir)) { 441 switch (MIPSInst_OPCODE(ir)) {
459 case lwc1_op: 442 case lwc1_op:
460 case swc1_op: 443 case swc1_op:
461#if (__mips >= 2 || __mips64) && !defined(SINGLE_ONLY_FPU) 444#if (__mips >= 2 || defined(__mips64))
462 case ldc1_op: 445 case ldc1_op:
463 case sdc1_op: 446 case sdc1_op:
464#endif 447#endif
@@ -480,7 +463,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
480 * Single step the non-cp1 463 * Single step the non-cp1
481 * instruction in the dslot 464 * instruction in the dslot
482 */ 465 */
483 return mips_dsemul(xcp, ir, VA_TO_REG contpc); 466 return mips_dsemul(xcp, ir, (unsigned long) contpc);
484 } 467 }
485 else { 468 else {
486 /* branch not taken */ 469 /* branch not taken */
@@ -539,8 +522,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
539 } 522 }
540 523
541 /* we did it !! */ 524 /* we did it !! */
542 xcp->cp0_epc = VA_TO_REG(contpc); 525 xcp->cp0_epc = (unsigned long) contpc;
543 xcp->cp0_cause &= ~CAUSEF_BD; 526 xcp->cp0_cause &= ~CAUSEF_BD;
527
544 return 0; 528 return 0;
545} 529}
546 530
@@ -570,7 +554,7 @@ static const unsigned char cmptab[8] = {
570static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \ 554static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \
571 ieee754##p t) \ 555 ieee754##p t) \
572{ \ 556{ \
573 struct ieee754_csr ieee754_csr_save; \ 557 struct _ieee754_csr ieee754_csr_save; \
574 s = f1 (s, t); \ 558 s = f1 (s, t); \
575 ieee754_csr_save = ieee754_csr; \ 559 ieee754_csr_save = ieee754_csr; \
576 s = f2 (s, r); \ 560 s = f2 (s, r); \
@@ -616,54 +600,38 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
616{ 600{
617 unsigned rcsr = 0; /* resulting csr */ 601 unsigned rcsr = 0; /* resulting csr */
618 602
619 fpuemuprivate.stats.cp1xops++; 603 fpuemustats.cp1xops++;
620 604
621 switch (MIPSInst_FMA_FFMT(ir)) { 605 switch (MIPSInst_FMA_FFMT(ir)) {
622 case s_fmt:{ /* 0 */ 606 case s_fmt:{ /* 0 */
623 607
624 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp); 608 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
625 ieee754sp fd, fr, fs, ft; 609 ieee754sp fd, fr, fs, ft;
626 u32 *va; 610 u32 __user *va;
627 u32 val; 611 u32 val;
628 612
629 switch (MIPSInst_FUNC(ir)) { 613 switch (MIPSInst_FUNC(ir)) {
630 case lwxc1_op: 614 case lwxc1_op:
631 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 615 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
632 xcp->regs[MIPSInst_FT(ir)]); 616 xcp->regs[MIPSInst_FT(ir)]);
633 617
634 fpuemuprivate.stats.loads++; 618 fpuemustats.loads++;
635 if (get_user(val, va)) { 619 if (get_user(val, va)) {
636 fpuemuprivate.stats.errors++; 620 fpuemustats.errors++;
637 return SIGBUS; 621 return SIGBUS;
638 } 622 }
639#ifdef SINGLE_ONLY_FPU
640 if (MIPSInst_FD(ir) & 1) {
641 /* illegal register in single-float
642 * mode
643 */
644 return SIGILL;
645 }
646#endif
647 SITOREG(val, MIPSInst_FD(ir)); 623 SITOREG(val, MIPSInst_FD(ir));
648 break; 624 break;
649 625
650 case swxc1_op: 626 case swxc1_op:
651 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 627 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
652 xcp->regs[MIPSInst_FT(ir)]); 628 xcp->regs[MIPSInst_FT(ir)]);
653 629
654 fpuemuprivate.stats.stores++; 630 fpuemustats.stores++;
655#ifdef SINGLE_ONLY_FPU
656 if (MIPSInst_FS(ir) & 1) {
657 /* illegal register in single-float
658 * mode
659 */
660 return SIGILL;
661 }
662#endif
663 631
664 SIFROMREG(val, MIPSInst_FS(ir)); 632 SIFROMREG(val, MIPSInst_FS(ir));
665 if (put_user(val, va)) { 633 if (put_user(val, va)) {
666 fpuemuprivate.stats.errors++; 634 fpuemustats.errors++;
667 return SIGBUS; 635 return SIGBUS;
668 } 636 }
669 break; 637 break;
@@ -699,8 +667,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
699 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 667 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
700 668
701 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 669 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
702 if (ieee754_csr.nod)
703 ctx->fcr31 |= 0x1000000;
704 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 670 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
705 /*printk ("SIGFPE: fpu csr = %08x\n", 671 /*printk ("SIGFPE: fpu csr = %08x\n",
706 ctx->fcr31); */ 672 ctx->fcr31); */
@@ -715,34 +681,33 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
715 break; 681 break;
716 } 682 }
717 683
718#ifndef SINGLE_ONLY_FPU
719 case d_fmt:{ /* 1 */ 684 case d_fmt:{ /* 1 */
720 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp); 685 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
721 ieee754dp fd, fr, fs, ft; 686 ieee754dp fd, fr, fs, ft;
722 u64 *va; 687 u64 __user *va;
723 u64 val; 688 u64 val;
724 689
725 switch (MIPSInst_FUNC(ir)) { 690 switch (MIPSInst_FUNC(ir)) {
726 case ldxc1_op: 691 case ldxc1_op:
727 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 692 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
728 xcp->regs[MIPSInst_FT(ir)]); 693 xcp->regs[MIPSInst_FT(ir)]);
729 694
730 fpuemuprivate.stats.loads++; 695 fpuemustats.loads++;
731 if (get_user(val, va)) { 696 if (get_user(val, va)) {
732 fpuemuprivate.stats.errors++; 697 fpuemustats.errors++;
733 return SIGBUS; 698 return SIGBUS;
734 } 699 }
735 DITOREG(val, MIPSInst_FD(ir)); 700 DITOREG(val, MIPSInst_FD(ir));
736 break; 701 break;
737 702
738 case sdxc1_op: 703 case sdxc1_op:
739 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 704 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
740 xcp->regs[MIPSInst_FT(ir)]); 705 xcp->regs[MIPSInst_FT(ir)]);
741 706
742 fpuemuprivate.stats.stores++; 707 fpuemustats.stores++;
743 DIFROMREG(val, MIPSInst_FS(ir)); 708 DIFROMREG(val, MIPSInst_FS(ir));
744 if (put_user(val, va)) { 709 if (put_user(val, va)) {
745 fpuemuprivate.stats.errors++; 710 fpuemustats.errors++;
746 return SIGBUS; 711 return SIGBUS;
747 } 712 }
748 break; 713 break;
@@ -773,7 +738,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
773 } 738 }
774 break; 739 break;
775 } 740 }
776#endif
777 741
778 case 0x7: /* 7 */ 742 case 0x7: /* 7 */
779 if (MIPSInst_FUNC(ir) != pfetch_op) { 743 if (MIPSInst_FUNC(ir) != pfetch_op) {
@@ -810,7 +774,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
810#endif 774#endif
811 } rv; /* resulting value */ 775 } rv; /* resulting value */
812 776
813 fpuemuprivate.stats.cp1ops++; 777 fpuemustats.cp1ops++;
814 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 778 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
815 case s_fmt:{ /* 0 */ 779 case s_fmt:{ /* 0 */
816 union { 780 union {
@@ -834,7 +798,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
834 goto scopbop; 798 goto scopbop;
835 799
836 /* unary ops */ 800 /* unary ops */
837#if __mips >= 2 || __mips64 801#if __mips >= 2 || defined(__mips64)
838 case fsqrt_op: 802 case fsqrt_op:
839 handler.u = ieee754sp_sqrt; 803 handler.u = ieee754sp_sqrt;
840 goto scopuop; 804 goto scopuop;
@@ -913,9 +877,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
913 case fcvts_op: 877 case fcvts_op:
914 return SIGILL; /* not defined */ 878 return SIGILL; /* not defined */
915 case fcvtd_op:{ 879 case fcvtd_op:{
916#ifdef SINGLE_ONLY_FPU
917 return SIGILL; /* not defined */
918#else
919 ieee754sp fs; 880 ieee754sp fs;
920 881
921 SPFROMREG(fs, MIPSInst_FS(ir)); 882 SPFROMREG(fs, MIPSInst_FS(ir));
@@ -923,7 +884,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
923 rfmt = d_fmt; 884 rfmt = d_fmt;
924 goto copcsr; 885 goto copcsr;
925 } 886 }
926#endif
927 case fcvtw_op:{ 887 case fcvtw_op:{
928 ieee754sp fs; 888 ieee754sp fs;
929 889
@@ -933,7 +893,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
933 goto copcsr; 893 goto copcsr;
934 } 894 }
935 895
936#if __mips >= 2 || __mips64 896#if __mips >= 2 || defined(__mips64)
937 case fround_op: 897 case fround_op:
938 case ftrunc_op: 898 case ftrunc_op:
939 case fceil_op: 899 case fceil_op:
@@ -950,7 +910,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
950 } 910 }
951#endif /* __mips >= 2 */ 911#endif /* __mips >= 2 */
952 912
953#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 913#if defined(__mips64)
954 case fcvtl_op:{ 914 case fcvtl_op:{
955 ieee754sp fs; 915 ieee754sp fs;
956 916
@@ -974,7 +934,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
974 rfmt = l_fmt; 934 rfmt = l_fmt;
975 goto copcsr; 935 goto copcsr;
976 } 936 }
977#endif /* __mips64 && !fpu(single) */ 937#endif /* defined(__mips64) */
978 938
979 default: 939 default:
980 if (MIPSInst_FUNC(ir) >= fcmp_op) { 940 if (MIPSInst_FUNC(ir) >= fcmp_op) {
@@ -1001,7 +961,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1001 break; 961 break;
1002 } 962 }
1003 963
1004#ifndef SINGLE_ONLY_FPU
1005 case d_fmt:{ 964 case d_fmt:{
1006 union { 965 union {
1007 ieee754dp(*b) (ieee754dp, ieee754dp); 966 ieee754dp(*b) (ieee754dp, ieee754dp);
@@ -1024,7 +983,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1024 goto dcopbop; 983 goto dcopbop;
1025 984
1026 /* unary ops */ 985 /* unary ops */
1027#if __mips >= 2 || __mips64 986#if __mips >= 2 || defined(__mips64)
1028 case fsqrt_op: 987 case fsqrt_op:
1029 handler.u = ieee754dp_sqrt; 988 handler.u = ieee754dp_sqrt;
1030 goto dcopuop; 989 goto dcopuop;
@@ -1108,7 +1067,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1108 goto copcsr; 1067 goto copcsr;
1109 } 1068 }
1110 1069
1111#if __mips >= 2 || __mips64 1070#if __mips >= 2 || defined(__mips64)
1112 case fround_op: 1071 case fround_op:
1113 case ftrunc_op: 1072 case ftrunc_op:
1114 case fceil_op: 1073 case fceil_op:
@@ -1125,7 +1084,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1125 } 1084 }
1126#endif 1085#endif
1127 1086
1128#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 1087#if defined(__mips64)
1129 case fcvtl_op:{ 1088 case fcvtl_op:{
1130 ieee754dp fs; 1089 ieee754dp fs;
1131 1090
@@ -1149,7 +1108,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1149 rfmt = l_fmt; 1108 rfmt = l_fmt;
1150 goto copcsr; 1109 goto copcsr;
1151 } 1110 }
1152#endif /* __mips >= 3 && !fpu(single) */ 1111#endif /* __mips >= 3 */
1153 1112
1154 default: 1113 default:
1155 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1114 if (MIPSInst_FUNC(ir) >= fcmp_op) {
@@ -1177,7 +1136,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1177 } 1136 }
1178 break; 1137 break;
1179 } 1138 }
1180#endif /* ifndef SINGLE_ONLY_FPU */
1181 1139
1182 case w_fmt:{ 1140 case w_fmt:{
1183 ieee754sp fs; 1141 ieee754sp fs;
@@ -1189,21 +1147,19 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1189 rv.s = ieee754sp_fint(fs.bits); 1147 rv.s = ieee754sp_fint(fs.bits);
1190 rfmt = s_fmt; 1148 rfmt = s_fmt;
1191 goto copcsr; 1149 goto copcsr;
1192#ifndef SINGLE_ONLY_FPU
1193 case fcvtd_op: 1150 case fcvtd_op:
1194 /* convert word to double precision real */ 1151 /* convert word to double precision real */
1195 SPFROMREG(fs, MIPSInst_FS(ir)); 1152 SPFROMREG(fs, MIPSInst_FS(ir));
1196 rv.d = ieee754dp_fint(fs.bits); 1153 rv.d = ieee754dp_fint(fs.bits);
1197 rfmt = d_fmt; 1154 rfmt = d_fmt;
1198 goto copcsr; 1155 goto copcsr;
1199#endif
1200 default: 1156 default:
1201 return SIGILL; 1157 return SIGILL;
1202 } 1158 }
1203 break; 1159 break;
1204 } 1160 }
1205 1161
1206#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 1162#if defined(__mips64)
1207 case l_fmt:{ 1163 case l_fmt:{
1208 switch (MIPSInst_FUNC(ir)) { 1164 switch (MIPSInst_FUNC(ir)) {
1209 case fcvts_op: 1165 case fcvts_op:
@@ -1256,18 +1212,16 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1256 ctx->fcr31 &= ~cond; 1212 ctx->fcr31 &= ~cond;
1257 break; 1213 break;
1258 } 1214 }
1259#ifndef SINGLE_ONLY_FPU
1260 case d_fmt: 1215 case d_fmt:
1261 DPTOREG(rv.d, MIPSInst_FD(ir)); 1216 DPTOREG(rv.d, MIPSInst_FD(ir));
1262 break; 1217 break;
1263#endif
1264 case s_fmt: 1218 case s_fmt:
1265 SPTOREG(rv.s, MIPSInst_FD(ir)); 1219 SPTOREG(rv.s, MIPSInst_FD(ir));
1266 break; 1220 break;
1267 case w_fmt: 1221 case w_fmt:
1268 SITOREG(rv.w, MIPSInst_FD(ir)); 1222 SITOREG(rv.w, MIPSInst_FD(ir));
1269 break; 1223 break;
1270#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 1224#if defined(__mips64)
1271 case l_fmt: 1225 case l_fmt:
1272 DITOREG(rv.l, MIPSInst_FD(ir)); 1226 DITOREG(rv.l, MIPSInst_FD(ir));
1273 break; 1227 break;
@@ -1279,10 +1233,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1279 return 0; 1233 return 0;
1280} 1234}
1281 1235
1282int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, 1236int fpu_emulator_cop1Handler(struct pt_regs *xcp,
1283 struct mips_fpu_soft_struct *ctx) 1237 struct mips_fpu_soft_struct *ctx)
1284{ 1238{
1285 gpreg_t oldepc, prevepc; 1239 unsigned long oldepc, prevepc;
1286 mips_instruction insn; 1240 mips_instruction insn;
1287 int sig = 0; 1241 int sig = 0;
1288 1242
@@ -1290,19 +1244,24 @@ int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
1290 do { 1244 do {
1291 prevepc = xcp->cp0_epc; 1245 prevepc = xcp->cp0_epc;
1292 1246
1293 if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) { 1247 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1294 fpuemuprivate.stats.errors++; 1248 fpuemustats.errors++;
1295 return SIGBUS; 1249 return SIGBUS;
1296 } 1250 }
1297 if (insn == 0) 1251 if (insn == 0)
1298 xcp->cp0_epc += 4; /* skip nops */ 1252 xcp->cp0_epc += 4; /* skip nops */
1299 else { 1253 else {
1300 /* Update ieee754_csr. Only relevant if we have a 1254 /*
1301 h/w FPU */ 1255 * The 'ieee754_csr' is an alias of
1302 ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0; 1256 * ctx->fcr31. No need to copy ctx->fcr31 to
1303 ieee754_csr.rm = ieee_rm[ctx->fcr31 & 0x3]; 1257 * ieee754_csr. But ieee754_csr.rm is ieee
1304 ieee754_csr.cx = (ctx->fcr31 >> 12) & 0x1f; 1258 * library modes. (not mips rounding mode)
1259 */
1260 /* convert to ieee library modes */
1261 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1305 sig = cop1Emulate(xcp, ctx); 1262 sig = cop1Emulate(xcp, ctx);
1263 /* revert to mips rounding mode */
1264 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1306 } 1265 }
1307 1266
1308 if (cpu_has_fpu) 1267 if (cpu_has_fpu)
diff --git a/arch/mips/math-emu/dp_sqrt.c b/arch/mips/math-emu/dp_sqrt.c
index c35e871ae975..032328c49888 100644
--- a/arch/mips/math-emu/dp_sqrt.c
+++ b/arch/mips/math-emu/dp_sqrt.c
@@ -37,7 +37,7 @@ static const unsigned table[] = {
37 37
38ieee754dp ieee754dp_sqrt(ieee754dp x) 38ieee754dp ieee754dp_sqrt(ieee754dp x)
39{ 39{
40 struct ieee754_csr oldcsr; 40 struct _ieee754_csr oldcsr;
41 ieee754dp y, z, t; 41 ieee754dp y, z, t;
42 unsigned scalx, yh; 42 unsigned scalx, yh;
43 COMPXDP; 43 COMPXDP;
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index aa989c2246da..8079f3d1eca0 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -28,9 +28,6 @@
28#endif 28#endif
29#define __mips 4 29#define __mips 4
30 30
31extern struct mips_fpu_emulator_private fpuemuprivate;
32
33
34/* 31/*
35 * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when 32 * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when
36 * we have to emulate the instruction in a COP1 branch delay slot. Do 33 * we have to emulate the instruction in a COP1 branch delay slot. Do
@@ -52,10 +49,10 @@ struct emuframe {
52 mips_instruction emul; 49 mips_instruction emul;
53 mips_instruction badinst; 50 mips_instruction badinst;
54 mips_instruction cookie; 51 mips_instruction cookie;
55 gpreg_t epc; 52 unsigned long epc;
56}; 53};
57 54
58int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc) 55int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
59{ 56{
60 extern asmlinkage void handle_dsemulret(void); 57 extern asmlinkage void handle_dsemulret(void);
61 mips_instruction *dsemul_insns; 58 mips_instruction *dsemul_insns;
@@ -91,7 +88,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
91 */ 88 */
92 89
93 /* Ensure that the two instructions are in the same cache line */ 90 /* Ensure that the two instructions are in the same cache line */
94 dsemul_insns = (mips_instruction *) REG_TO_VA ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); 91 dsemul_insns = (mips_instruction *) ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
95 fr = (struct emuframe *) dsemul_insns; 92 fr = (struct emuframe *) dsemul_insns;
96 93
97 /* Verify that the stack pointer is not competely insane */ 94 /* Verify that the stack pointer is not competely insane */
@@ -104,11 +101,11 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
104 err |= __put_user(cpc, &fr->epc); 101 err |= __put_user(cpc, &fr->epc);
105 102
106 if (unlikely(err)) { 103 if (unlikely(err)) {
107 fpuemuprivate.stats.errors++; 104 fpuemustats.errors++;
108 return SIGBUS; 105 return SIGBUS;
109 } 106 }
110 107
111 regs->cp0_epc = VA_TO_REG & fr->emul; 108 regs->cp0_epc = (unsigned long) &fr->emul;
112 109
113 flush_cache_sigtramp((unsigned long)&fr->badinst); 110 flush_cache_sigtramp((unsigned long)&fr->badinst);
114 111
@@ -118,7 +115,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
118int do_dsemulret(struct pt_regs *xcp) 115int do_dsemulret(struct pt_regs *xcp)
119{ 116{
120 struct emuframe *fr; 117 struct emuframe *fr;
121 gpreg_t epc; 118 unsigned long epc;
122 u32 insn, cookie; 119 u32 insn, cookie;
123 int err = 0; 120 int err = 0;
124 121
@@ -141,7 +138,7 @@ int do_dsemulret(struct pt_regs *xcp)
141 err |= __get_user(cookie, &fr->cookie); 138 err |= __get_user(cookie, &fr->cookie);
142 139
143 if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { 140 if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) {
144 fpuemuprivate.stats.errors++; 141 fpuemustats.errors++;
145 return 0; 142 return 0;
146 } 143 }
147 144
diff --git a/arch/mips/math-emu/dsemul.h b/arch/mips/math-emu/dsemul.h
index dbd85f95268d..091f0e76730f 100644
--- a/arch/mips/math-emu/dsemul.h
+++ b/arch/mips/math-emu/dsemul.h
@@ -1,11 +1,5 @@
1typedef long gpreg_t; 1extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc);
2typedef void *vaddr_t; 2extern int do_dsemulret(struct pt_regs *xcp);
3
4#define REG_TO_VA (vaddr_t)
5#define VA_TO_REG (gpreg_t)
6
7int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc);
8int do_dsemulret(struct pt_regs *xcp);
9 3
10/* Instruction which will always cause an address error */ 4/* Instruction which will always cause an address error */
11#define AdELOAD 0x8c000001 /* lw $0,1($0) */ 5#define AdELOAD 0x8c000001 /* lw $0,1($0) */
diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c
index f0a364adbf34..a93c45dbdefd 100644
--- a/arch/mips/math-emu/ieee754.c
+++ b/arch/mips/math-emu/ieee754.c
@@ -31,6 +31,8 @@
31 31
32 32
33#include "ieee754int.h" 33#include "ieee754int.h"
34#include "ieee754sp.h"
35#include "ieee754dp.h"
34 36
35#define DP_EBIAS 1023 37#define DP_EBIAS 1023
36#define DP_EMIN (-1022) 38#define DP_EMIN (-1022)
@@ -40,20 +42,6 @@
40#define SP_EMIN (-126) 42#define SP_EMIN (-126)
41#define SP_EMAX 127 43#define SP_EMAX 127
42 44
43/* indexed by class */
44const char *const ieee754_cname[] = {
45 "Normal",
46 "Zero",
47 "Denormal",
48 "Infinity",
49 "QNaN",
50 "SNaN",
51};
52
53/* the control status register
54*/
55struct ieee754_csr ieee754_csr;
56
57/* special constants 45/* special constants
58*/ 46*/
59 47
diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h
index b8772f46972d..171f177c0f88 100644
--- a/arch/mips/math-emu/ieee754.h
+++ b/arch/mips/math-emu/ieee754.h
@@ -1,13 +1,8 @@
1/* single and double precision fp ops
2 * missing extended precision.
3*/
4/* 1/*
5 * MIPS floating point support 2 * MIPS floating point support
6 * Copyright (C) 1994-2000 Algorithmics Ltd. 3 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * http://www.algor.co.uk 4 * http://www.algor.co.uk
8 * 5 *
9 * ########################################################################
10 *
11 * This program is free software; you can distribute it and/or modify it 6 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as 7 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
@@ -21,20 +16,18 @@
21 * with this program; if not, write to the Free Software Foundation, Inc., 16 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * 18 *
24 * ########################################################################
25 */
26
27/**************************************************************************
28 * Nov 7, 2000 19 * Nov 7, 2000
29 * Modification to allow integration with Linux kernel 20 * Modification to allow integration with Linux kernel
30 * 21 *
31 * Kevin D. Kissell, kevink@mips.com and Carsten Langgard, carstenl@mips.com 22 * Kevin D. Kissell, kevink@mips.com and Carsten Langgard, carstenl@mips.com
32 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 23 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
33 *************************************************************************/ 24 */
25#ifndef __ARCH_MIPS_MATH_EMU_IEEE754_H
26#define __ARCH_MIPS_MATH_EMU_IEEE754_H
34 27
35#ifdef __KERNEL__ 28#include <asm/byteorder.h>
36/* Going from Algorithmics to Linux native environment, add this */
37#include <linux/types.h> 29#include <linux/types.h>
30#include <linux/sched.h>
38 31
39/* 32/*
40 * Not very pretty, but the Linux kernel's normal va_list definition 33 * Not very pretty, but the Linux kernel's normal va_list definition
@@ -44,18 +37,7 @@
44#include <stdarg.h> 37#include <stdarg.h>
45#endif 38#endif
46 39
47#else 40#ifdef __LITTLE_ENDIAN
48
49/* Note that __KERNEL__ is taken to mean Linux kernel */
50
51#if #system(OpenBSD)
52#include <machine/types.h>
53#endif
54#include <machine/endian.h>
55
56#endif /* __KERNEL__ */
57
58#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__)
59struct ieee754dp_konst { 41struct ieee754dp_konst {
60 unsigned mantlo:32; 42 unsigned mantlo:32;
61 unsigned manthi:20; 43 unsigned manthi:20;
@@ -86,13 +68,14 @@ typedef union _ieee754sp {
86} ieee754sp; 68} ieee754sp;
87#endif 69#endif
88 70
89#if (defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN) || defined(__MIPSEB__) 71#ifdef __BIG_ENDIAN
90struct ieee754dp_konst { 72struct ieee754dp_konst {
91 unsigned sign:1; 73 unsigned sign:1;
92 unsigned bexp:11; 74 unsigned bexp:11;
93 unsigned manthi:20; 75 unsigned manthi:20;
94 unsigned mantlo:32; 76 unsigned mantlo:32;
95}; 77};
78
96typedef union _ieee754dp { 79typedef union _ieee754dp {
97 struct ieee754dp_konst oparts; 80 struct ieee754dp_konst oparts;
98 struct { 81 struct {
@@ -222,7 +205,6 @@ ieee754dp ieee754dp_sqrt(ieee754dp x);
222#define IEEE754_CLASS_INF 0x03 205#define IEEE754_CLASS_INF 0x03
223#define IEEE754_CLASS_SNAN 0x04 206#define IEEE754_CLASS_SNAN 0x04
224#define IEEE754_CLASS_QNAN 0x05 207#define IEEE754_CLASS_QNAN 0x05
225extern const char *const ieee754_cname[];
226 208
227/* exception numbers */ 209/* exception numbers */
228#define IEEE754_INEXACT 0x01 210#define IEEE754_INEXACT 0x01
@@ -251,93 +233,109 @@ extern const char *const ieee754_cname[];
251 233
252/* "normal" comparisons 234/* "normal" comparisons
253*/ 235*/
254static __inline int ieee754sp_eq(ieee754sp x, ieee754sp y) 236static inline int ieee754sp_eq(ieee754sp x, ieee754sp y)
255{ 237{
256 return ieee754sp_cmp(x, y, IEEE754_CEQ, 0); 238 return ieee754sp_cmp(x, y, IEEE754_CEQ, 0);
257} 239}
258 240
259static __inline int ieee754sp_ne(ieee754sp x, ieee754sp y) 241static inline int ieee754sp_ne(ieee754sp x, ieee754sp y)
260{ 242{
261 return ieee754sp_cmp(x, y, 243 return ieee754sp_cmp(x, y,
262 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0); 244 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0);
263} 245}
264 246
265static __inline int ieee754sp_lt(ieee754sp x, ieee754sp y) 247static inline int ieee754sp_lt(ieee754sp x, ieee754sp y)
266{ 248{
267 return ieee754sp_cmp(x, y, IEEE754_CLT, 0); 249 return ieee754sp_cmp(x, y, IEEE754_CLT, 0);
268} 250}
269 251
270static __inline int ieee754sp_le(ieee754sp x, ieee754sp y) 252static inline int ieee754sp_le(ieee754sp x, ieee754sp y)
271{ 253{
272 return ieee754sp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0); 254 return ieee754sp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0);
273} 255}
274 256
275static __inline int ieee754sp_gt(ieee754sp x, ieee754sp y) 257static inline int ieee754sp_gt(ieee754sp x, ieee754sp y)
276{ 258{
277 return ieee754sp_cmp(x, y, IEEE754_CGT, 0); 259 return ieee754sp_cmp(x, y, IEEE754_CGT, 0);
278} 260}
279 261
280 262
281static __inline int ieee754sp_ge(ieee754sp x, ieee754sp y) 263static inline int ieee754sp_ge(ieee754sp x, ieee754sp y)
282{ 264{
283 return ieee754sp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0); 265 return ieee754sp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0);
284} 266}
285 267
286static __inline int ieee754dp_eq(ieee754dp x, ieee754dp y) 268static inline int ieee754dp_eq(ieee754dp x, ieee754dp y)
287{ 269{
288 return ieee754dp_cmp(x, y, IEEE754_CEQ, 0); 270 return ieee754dp_cmp(x, y, IEEE754_CEQ, 0);
289} 271}
290 272
291static __inline int ieee754dp_ne(ieee754dp x, ieee754dp y) 273static inline int ieee754dp_ne(ieee754dp x, ieee754dp y)
292{ 274{
293 return ieee754dp_cmp(x, y, 275 return ieee754dp_cmp(x, y,
294 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0); 276 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0);
295} 277}
296 278
297static __inline int ieee754dp_lt(ieee754dp x, ieee754dp y) 279static inline int ieee754dp_lt(ieee754dp x, ieee754dp y)
298{ 280{
299 return ieee754dp_cmp(x, y, IEEE754_CLT, 0); 281 return ieee754dp_cmp(x, y, IEEE754_CLT, 0);
300} 282}
301 283
302static __inline int ieee754dp_le(ieee754dp x, ieee754dp y) 284static inline int ieee754dp_le(ieee754dp x, ieee754dp y)
303{ 285{
304 return ieee754dp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0); 286 return ieee754dp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0);
305} 287}
306 288
307static __inline int ieee754dp_gt(ieee754dp x, ieee754dp y) 289static inline int ieee754dp_gt(ieee754dp x, ieee754dp y)
308{ 290{
309 return ieee754dp_cmp(x, y, IEEE754_CGT, 0); 291 return ieee754dp_cmp(x, y, IEEE754_CGT, 0);
310} 292}
311 293
312static __inline int ieee754dp_ge(ieee754dp x, ieee754dp y) 294static inline int ieee754dp_ge(ieee754dp x, ieee754dp y)
313{ 295{
314 return ieee754dp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0); 296 return ieee754dp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0);
315} 297}
316 298
317 299
318/* like strtod 300/*
319*/ 301 * Like strtod
302 */
320ieee754dp ieee754dp_fstr(const char *s, char **endp); 303ieee754dp ieee754dp_fstr(const char *s, char **endp);
321char *ieee754dp_tstr(ieee754dp x, int prec, int fmt, int af); 304char *ieee754dp_tstr(ieee754dp x, int prec, int fmt, int af);
322 305
323 306
324/* the control status register 307/*
325*/ 308 * The control status register
326struct ieee754_csr { 309 */
327 unsigned pad:13; 310struct _ieee754_csr {
311#ifdef __BIG_ENDIAN
312 unsigned pad0:7;
328 unsigned nod:1; /* set 1 for no denormalised numbers */ 313 unsigned nod:1; /* set 1 for no denormalised numbers */
329 unsigned cx:5; /* exceptions this operation */ 314 unsigned c:1; /* condition */
315 unsigned pad1:5;
316 unsigned cx:6; /* exceptions this operation */
330 unsigned mx:5; /* exception enable mask */ 317 unsigned mx:5; /* exception enable mask */
331 unsigned sx:5; /* exceptions total */ 318 unsigned sx:5; /* exceptions total */
332 unsigned rm:2; /* current rounding mode */ 319 unsigned rm:2; /* current rounding mode */
320#endif
321#ifdef __LITTLE_ENDIAN
322 unsigned rm:2; /* current rounding mode */
323 unsigned sx:5; /* exceptions total */
324 unsigned mx:5; /* exception enable mask */
325 unsigned cx:6; /* exceptions this operation */
326 unsigned pad1:5;
327 unsigned c:1; /* condition */
328 unsigned nod:1; /* set 1 for no denormalised numbers */
329 unsigned pad0:7;
330#endif
333}; 331};
334extern struct ieee754_csr ieee754_csr; 332#define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.soft.fcr31))
335 333
336static __inline unsigned ieee754_getrm(void) 334static inline unsigned ieee754_getrm(void)
337{ 335{
338 return (ieee754_csr.rm); 336 return (ieee754_csr.rm);
339} 337}
340static __inline unsigned ieee754_setrm(unsigned rm) 338static inline unsigned ieee754_setrm(unsigned rm)
341{ 339{
342 return (ieee754_csr.rm = rm); 340 return (ieee754_csr.rm = rm);
343} 341}
@@ -345,14 +343,14 @@ static __inline unsigned ieee754_setrm(unsigned rm)
345/* 343/*
346 * get current exceptions 344 * get current exceptions
347 */ 345 */
348static __inline unsigned ieee754_getcx(void) 346static inline unsigned ieee754_getcx(void)
349{ 347{
350 return (ieee754_csr.cx); 348 return (ieee754_csr.cx);
351} 349}
352 350
353/* test for current exception condition 351/* test for current exception condition
354 */ 352 */
355static __inline int ieee754_cxtest(unsigned n) 353static inline int ieee754_cxtest(unsigned n)
356{ 354{
357 return (ieee754_csr.cx & n); 355 return (ieee754_csr.cx & n);
358} 356}
@@ -360,21 +358,21 @@ static __inline int ieee754_cxtest(unsigned n)
360/* 358/*
361 * get sticky exceptions 359 * get sticky exceptions
362 */ 360 */
363static __inline unsigned ieee754_getsx(void) 361static inline unsigned ieee754_getsx(void)
364{ 362{
365 return (ieee754_csr.sx); 363 return (ieee754_csr.sx);
366} 364}
367 365
368/* clear sticky conditions 366/* clear sticky conditions
369*/ 367*/
370static __inline unsigned ieee754_clrsx(void) 368static inline unsigned ieee754_clrsx(void)
371{ 369{
372 return (ieee754_csr.sx = 0); 370 return (ieee754_csr.sx = 0);
373} 371}
374 372
375/* test for sticky exception condition 373/* test for sticky exception condition
376 */ 374 */
377static __inline int ieee754_sxtest(unsigned n) 375static inline int ieee754_sxtest(unsigned n)
378{ 376{
379 return (ieee754_csr.sx & n); 377 return (ieee754_csr.sx & n);
380} 378}
@@ -406,52 +404,34 @@ extern const struct ieee754sp_konst __ieee754sp_spcvals[];
406#define ieee754dp_spcvals ((const ieee754dp *)__ieee754dp_spcvals) 404#define ieee754dp_spcvals ((const ieee754dp *)__ieee754dp_spcvals)
407#define ieee754sp_spcvals ((const ieee754sp *)__ieee754sp_spcvals) 405#define ieee754sp_spcvals ((const ieee754sp *)__ieee754sp_spcvals)
408 406
409/* return infinity with given sign 407/*
410*/ 408 * Return infinity with given sign
411#define ieee754dp_inf(sn) \ 409 */
412 (ieee754dp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) 410#define ieee754dp_inf(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)])
413#define ieee754dp_zero(sn) \ 411#define ieee754dp_zero(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PZERO+(sn)])
414 (ieee754dp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) 412#define ieee754dp_one(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PONE+(sn)])
415#define ieee754dp_one(sn) \ 413#define ieee754dp_ten(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PTEN+(sn)])
416 (ieee754dp_spcvals[IEEE754_SPCVAL_PONE+(sn)]) 414#define ieee754dp_indef() (ieee754dp_spcvals[IEEE754_SPCVAL_INDEF])
417#define ieee754dp_ten(sn) \ 415#define ieee754dp_max(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMAX+(sn)])
418 (ieee754dp_spcvals[IEEE754_SPCVAL_PTEN+(sn)]) 416#define ieee754dp_min(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMIN+(sn)])
419#define ieee754dp_indef() \ 417#define ieee754dp_mind(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMIND+(sn)])
420 (ieee754dp_spcvals[IEEE754_SPCVAL_INDEF]) 418#define ieee754dp_1e31() (ieee754dp_spcvals[IEEE754_SPCVAL_P1E31])
421#define ieee754dp_max(sn) \ 419#define ieee754dp_1e63() (ieee754dp_spcvals[IEEE754_SPCVAL_P1E63])
422 (ieee754dp_spcvals[IEEE754_SPCVAL_PMAX+(sn)]) 420
423#define ieee754dp_min(sn) \ 421#define ieee754sp_inf(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)])
424 (ieee754dp_spcvals[IEEE754_SPCVAL_PMIN+(sn)]) 422#define ieee754sp_zero(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)])
425#define ieee754dp_mind(sn) \ 423#define ieee754sp_one(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PONE+(sn)])
426 (ieee754dp_spcvals[IEEE754_SPCVAL_PMIND+(sn)]) 424#define ieee754sp_ten(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PTEN+(sn)])
427#define ieee754dp_1e31() \ 425#define ieee754sp_indef() (ieee754sp_spcvals[IEEE754_SPCVAL_INDEF])
428 (ieee754dp_spcvals[IEEE754_SPCVAL_P1E31]) 426#define ieee754sp_max(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMAX+(sn)])
429#define ieee754dp_1e63() \ 427#define ieee754sp_min(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMIN+(sn)])
430 (ieee754dp_spcvals[IEEE754_SPCVAL_P1E63]) 428#define ieee754sp_mind(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMIND+(sn)])
431 429#define ieee754sp_1e31() (ieee754sp_spcvals[IEEE754_SPCVAL_P1E31])
432#define ieee754sp_inf(sn) \ 430#define ieee754sp_1e63() (ieee754sp_spcvals[IEEE754_SPCVAL_P1E63])
433 (ieee754sp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) 431
434#define ieee754sp_zero(sn) \ 432/*
435 (ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) 433 * Indefinite integer value
436#define ieee754sp_one(sn) \ 434 */
437 (ieee754sp_spcvals[IEEE754_SPCVAL_PONE+(sn)])
438#define ieee754sp_ten(sn) \
439 (ieee754sp_spcvals[IEEE754_SPCVAL_PTEN+(sn)])
440#define ieee754sp_indef() \
441 (ieee754sp_spcvals[IEEE754_SPCVAL_INDEF])
442#define ieee754sp_max(sn) \
443 (ieee754sp_spcvals[IEEE754_SPCVAL_PMAX+(sn)])
444#define ieee754sp_min(sn) \
445 (ieee754sp_spcvals[IEEE754_SPCVAL_PMIN+(sn)])
446#define ieee754sp_mind(sn) \
447 (ieee754sp_spcvals[IEEE754_SPCVAL_PMIND+(sn)])
448#define ieee754sp_1e31() \
449 (ieee754sp_spcvals[IEEE754_SPCVAL_P1E31])
450#define ieee754sp_1e63() \
451 (ieee754sp_spcvals[IEEE754_SPCVAL_P1E63])
452
453/* indefinite integer value
454*/
455#define ieee754si_indef() INT_MAX 435#define ieee754si_indef() INT_MAX
456#ifdef LONG_LONG_MAX 436#ifdef LONG_LONG_MAX
457#define ieee754di_indef() LONG_LONG_MAX 437#define ieee754di_indef() LONG_LONG_MAX
@@ -487,3 +467,5 @@ extern void ieee754_xcpt(struct ieee754xctx *xcp);
487/* compat */ 467/* compat */
488#define ieee754dp_fix(x) ieee754dp_tint(x) 468#define ieee754dp_fix(x) ieee754dp_tint(x)
489#define ieee754sp_fix(x) ieee754sp_tint(x) 469#define ieee754sp_fix(x) ieee754sp_tint(x)
470
471#endif /* __ARCH_MIPS_MATH_EMU_IEEE754_H */
diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c
index 4002f0cf79f3..d187ab71c2ff 100644
--- a/arch/mips/math-emu/kernel_linkage.c
+++ b/arch/mips/math-emu/kernel_linkage.c
@@ -27,8 +27,6 @@
27 27
28#include <asm/fpu_emulator.h> 28#include <asm/fpu_emulator.h>
29 29
30extern struct mips_fpu_emulator_private fpuemuprivate;
31
32#define SIGNALLING_NAN 0x7ff800007ff80000LL 30#define SIGNALLING_NAN 0x7ff800007ff80000LL
33 31
34void fpu_emulator_init_fpu(void) 32void fpu_emulator_init_fpu(void)
@@ -65,7 +63,6 @@ int fpu_emulator_save_context(struct sigcontext *sc)
65 &sc->sc_fpregs[i]); 63 &sc->sc_fpregs[i]);
66 } 64 }
67 err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 65 err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
68 err |= __put_user(fpuemuprivate.eir, &sc->sc_fpc_eir);
69 66
70 return err; 67 return err;
71} 68}
@@ -81,7 +78,6 @@ int fpu_emulator_restore_context(struct sigcontext *sc)
81 &sc->sc_fpregs[i]); 78 &sc->sc_fpregs[i]);
82 } 79 }
83 err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 80 err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
84 err |= __get_user(fpuemuprivate.eir, &sc->sc_fpc_eir);
85 81
86 return err; 82 return err;
87} 83}
@@ -102,7 +98,6 @@ int fpu_emulator_save_context32(struct sigcontext32 *sc)
102 &sc->sc_fpregs[i]); 98 &sc->sc_fpregs[i]);
103 } 99 }
104 err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 100 err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
105 err |= __put_user(fpuemuprivate.eir, &sc->sc_fpc_eir);
106 101
107 return err; 102 return err;
108} 103}
@@ -118,7 +113,6 @@ int fpu_emulator_restore_context32(struct sigcontext32 *sc)
118 &sc->sc_fpregs[i]); 113 &sc->sc_fpregs[i]);
119 } 114 }
120 err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 115 err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
121 err |= __get_user(fpuemuprivate.eir, &sc->sc_fpc_eir);
122 116
123 return err; 117 return err;
124} 118}
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 19d4b0792460..bc0ebc69bfb3 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -76,14 +76,13 @@ static void end_atlas_irq(unsigned int irq)
76} 76}
77 77
78static struct hw_interrupt_type atlas_irq_type = { 78static struct hw_interrupt_type atlas_irq_type = {
79 "Atlas", 79 .typename = "Atlas",
80 startup_atlas_irq, 80 .startup = startup_atlas_irq,
81 shutdown_atlas_irq, 81 .shutdown = shutdown_atlas_irq,
82 enable_atlas_irq, 82 .enable = enable_atlas_irq,
83 disable_atlas_irq, 83 .disable = disable_atlas_irq,
84 mask_and_ack_atlas_irq, 84 .ack = mask_and_ack_atlas_irq,
85 end_atlas_irq, 85 .end = end_atlas_irq,
86 NULL
87}; 86};
88 87
89static inline int ls1bit32(unsigned int x) 88static inline int ls1bit32(unsigned int x)
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index 0a1dd9bbc02e..625843b30bed 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -50,8 +50,10 @@ const char *get_system_type(void)
50 return "MIPS Atlas"; 50 return "MIPS Atlas";
51} 51}
52 52
53static int __init atlas_setup(void) 53void __init plat_setup(void)
54{ 54{
55 mips_pcibios_init();
56
55 ioport_resource.end = 0x7fffffff; 57 ioport_resource.end = 0x7fffffff;
56 58
57 serial_init (); 59 serial_init ();
@@ -64,12 +66,8 @@ static int __init atlas_setup(void)
64 board_time_init = mips_time_init; 66 board_time_init = mips_time_init;
65 board_timer_setup = mips_timer_setup; 67 board_timer_setup = mips_timer_setup;
66 rtc_get_time = mips_rtc_get_time; 68 rtc_get_time = mips_rtc_get_time;
67
68 return 0;
69} 69}
70 70
71early_initcall(atlas_setup);
72
73static void __init serial_init(void) 71static void __init serial_init(void)
74{ 72{
75#ifdef CONFIG_SERIAL_8250 73#ifdef CONFIG_SERIAL_8250
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 311155d1d3ed..eab5a705e989 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
4 * 6 *
5 * This program is free software; you can distribute it and/or modify it 7 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 8 * under the terms of the GNU General Public License (Version 2) as
@@ -22,18 +24,19 @@
22#include <linux/string.h> 24#include <linux/string.h>
23#include <linux/kernel.h> 25#include <linux/kernel.h>
24 26
25#include <asm/io.h>
26#include <asm/bootinfo.h> 27#include <asm/bootinfo.h>
28#include <asm/gt64120.h>
29#include <asm/io.h>
30#include <asm/system.h>
31#include <asm/cacheflush.h>
32#include <asm/traps.h>
33
27#include <asm/mips-boards/prom.h> 34#include <asm/mips-boards/prom.h>
28#include <asm/mips-boards/generic.h> 35#include <asm/mips-boards/generic.h>
29#ifdef CONFIG_MIPS_GT64120
30#include <asm/gt64120.h>
31#endif
32#include <asm/mips-boards/msc01_pci.h>
33#include <asm/mips-boards/bonito64.h> 36#include <asm/mips-boards/bonito64.h>
34#ifdef CONFIG_MIPS_MALTA 37#include <asm/mips-boards/msc01_pci.h>
38
35#include <asm/mips-boards/malta.h> 39#include <asm/mips-boards/malta.h>
36#endif
37 40
38#ifdef CONFIG_KGDB 41#ifdef CONFIG_KGDB
39extern int rs_kgdb_hook(int, int); 42extern int rs_kgdb_hook(int, int);
@@ -223,8 +226,34 @@ void __init kgdb_config (void)
223} 226}
224#endif 227#endif
225 228
229void __init mips_nmi_setup (void)
230{
231 void *base;
232 extern char except_vec_nmi;
233
234 base = cpu_has_veic ?
235 (void *)(CAC_BASE + 0xa80) :
236 (void *)(CAC_BASE + 0x380);
237 memcpy(base, &except_vec_nmi, 0x80);
238 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
239}
240
241void __init mips_ejtag_setup (void)
242{
243 void *base;
244 extern char except_vec_ejtag_debug;
245
246 base = cpu_has_veic ?
247 (void *)(CAC_BASE + 0xa00) :
248 (void *)(CAC_BASE + 0x300);
249 memcpy(base, &except_vec_ejtag_debug, 0x80);
250 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
251}
252
226void __init prom_init(void) 253void __init prom_init(void)
227{ 254{
255 u32 start, map, mask, data;
256
228 prom_argc = fw_arg0; 257 prom_argc = fw_arg0;
229 _prom_argv = (int *) fw_arg1; 258 _prom_argv = (int *) fw_arg1;
230 _prom_envp = (int *) fw_arg2; 259 _prom_envp = (int *) fw_arg2;
@@ -266,12 +295,15 @@ void __init prom_init(void)
266#else 295#else
267 GT_WRITE(GT_PCI0_CMD_OFS, 0); 296 GT_WRITE(GT_PCI0_CMD_OFS, 0);
268#endif 297#endif
298 /* Fix up PCI I/O mapping if necessary (for Atlas). */
299 start = GT_READ(GT_PCI0IOLD_OFS);
300 map = GT_READ(GT_PCI0IOREMAP_OFS);
301 if ((start & map) != 0) {
302 map &= ~start;
303 GT_WRITE(GT_PCI0IOREMAP_OFS, map);
304 }
269 305
270#ifdef CONFIG_MIPS_MALTA
271 set_io_port_base(MALTA_GT_PORT_BASE); 306 set_io_port_base(MALTA_GT_PORT_BASE);
272#else
273 set_io_port_base((unsigned long)ioremap(0, 0x20000000));
274#endif
275 break; 307 break;
276 308
277 case MIPS_REVISION_CORID_CORE_EMUL_BON: 309 case MIPS_REVISION_CORID_CORE_EMUL_BON:
@@ -300,18 +332,21 @@ void __init prom_init(void)
300 BONITO_BONGENCFG_BYTESWAP; 332 BONITO_BONGENCFG_BYTESWAP;
301#endif 333#endif
302 334
303#ifdef CONFIG_MIPS_MALTA
304 set_io_port_base(MALTA_BONITO_PORT_BASE); 335 set_io_port_base(MALTA_BONITO_PORT_BASE);
305#else
306 set_io_port_base((unsigned long)ioremap(0, 0x20000000));
307#endif
308 break; 336 break;
309 337
310 case MIPS_REVISION_CORID_CORE_MSC: 338 case MIPS_REVISION_CORID_CORE_MSC:
311 case MIPS_REVISION_CORID_CORE_FPGA2: 339 case MIPS_REVISION_CORID_CORE_FPGA2:
340 case MIPS_REVISION_CORID_CORE_FPGA3:
312 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 341 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
313 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 342 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
314 343
344 mb();
345 MSC_READ(MSC01_PCI_CFG, data);
346 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
347 wmb();
348
349 /* Fix up lane swapping. */
315#ifdef CONFIG_CPU_LITTLE_ENDIAN 350#ifdef CONFIG_CPU_LITTLE_ENDIAN
316 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 351 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
317#else 352#else
@@ -320,12 +355,23 @@ void __init prom_init(void)
320 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 355 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
321 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 356 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
322#endif 357#endif
358 /* Fix up target memory mapping. */
359 MSC_READ(MSC01_PCI_BAR0, mask);
360 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
361
362 /* Don't handle target retries indefinitely. */
363 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
364 MSC01_PCI_CFG_MAXRTRY_MSK)
365 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
366 MSC01_PCI_CFG_MAXRTRY_SHF)) |
367 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
368 MSC01_PCI_CFG_MAXRTRY_SHF);
369
370 wmb();
371 MSC_WRITE(MSC01_PCI_CFG, data);
372 mb();
323 373
324#ifdef CONFIG_MIPS_MALTA
325 set_io_port_base(MALTA_MSC_PORT_BASE); 374 set_io_port_base(MALTA_MSC_PORT_BASE);
326#else
327 set_io_port_base((unsigned long)ioremap(0, 0x20000000));
328#endif
329 break; 375 break;
330 376
331 default: 377 default:
@@ -334,6 +380,9 @@ void __init prom_init(void)
334 while(1); /* We die here... */ 380 while(1); /* We die here... */
335 } 381 }
336#endif 382#endif
383 board_nmi_handler_setup = mips_nmi_setup;
384 board_ejtag_handler_setup = mips_ejtag_setup;
385
337 prom_printf("\nLINUX started...\n"); 386 prom_printf("\nLINUX started...\n");
338 prom_init_cmdline(); 387 prom_init_cmdline();
339 prom_meminit(); 388 prom_meminit();
diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c
index 5ae2b43e4c2e..2c8afd77a20b 100644
--- a/arch/mips/mips-boards/generic/memory.c
+++ b/arch/mips/mips-boards/generic/memory.c
@@ -22,6 +22,7 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/mm.h> 23#include <linux/mm.h>
24#include <linux/bootmem.h> 24#include <linux/bootmem.h>
25#include <linux/string.h>
25 26
26#include <asm/bootinfo.h> 27#include <asm/bootinfo.h>
27#include <asm/page.h> 28#include <asm/page.h>
@@ -55,18 +56,30 @@ struct prom_pmemblock * __init prom_getmdesc(void)
55{ 56{
56 char *memsize_str; 57 char *memsize_str;
57 unsigned int memsize; 58 unsigned int memsize;
59 char cmdline[CL_SIZE], *ptr;
58 60
59 memsize_str = prom_getenv("memsize"); 61 /* Check the command line first for a memsize directive */
60 if (!memsize_str) { 62 strcpy(cmdline, arcs_cmdline);
61 prom_printf("memsize not set in boot prom, set to default (32Mb)\n"); 63 ptr = strstr(cmdline, "memsize=");
62 memsize = 0x02000000; 64 if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
63 } else { 65 ptr = strstr(ptr, " memsize=");
66
67 if (ptr) {
68 memsize = memparse(ptr + 8, &ptr);
69 }
70 else {
71 /* otherwise look in the environment */
72 memsize_str = prom_getenv("memsize");
73 if (!memsize_str) {
74 prom_printf("memsize not set in boot prom, set to default (32Mb)\n");
75 memsize = 0x02000000;
76 } else {
64#ifdef DEBUG 77#ifdef DEBUG
65 prom_printf("prom_memsize = %s\n", memsize_str); 78 prom_printf("prom_memsize = %s\n", memsize_str);
66#endif 79#endif
67 memsize = simple_strtol(memsize_str, NULL, 0); 80 memsize = simple_strtol(memsize_str, NULL, 0);
81 }
68 } 82 }
69
70 memset(mdesc, 0, sizeof(mdesc)); 83 memset(mdesc, 0, sizeof(mdesc));
71 84
72 mdesc[0].type = yamon_dontuse; 85 mdesc[0].type = yamon_dontuse;
diff --git a/arch/mips/mips-boards/generic/mipsIRQ.S b/arch/mips/mips-boards/generic/mipsIRQ.S
index 131f49bccb20..a397ecb872d6 100644
--- a/arch/mips/mips-boards/generic/mipsIRQ.S
+++ b/arch/mips/mips-boards/generic/mipsIRQ.S
@@ -29,6 +29,20 @@
29#include <asm/regdef.h> 29#include <asm/regdef.h>
30#include <asm/stackframe.h> 30#include <asm/stackframe.h>
31 31
32#ifdef CONFIG_MIPS_ATLAS
33#include <asm/mips-boards/atlasint.h>
34#define CASCADE_IRQ MIPSCPU_INT_ATLAS
35#define CASCADE_DISPATCH atlas_hw0_irqdispatch
36#endif
37#ifdef CONFIG_MIPS_MALTA
38#include <asm/mips-boards/maltaint.h>
39#define CASCADE_IRQ MIPSCPU_INT_I8259A
40#define CASCADE_DISPATCH malta_hw0_irqdispatch
41#endif
42#ifdef CONFIG_MIPS_SEAD
43#include <asm/mips-boards/seadint.h>
44#endif
45
32/* A lot of complication here is taken away because: 46/* A lot of complication here is taken away because:
33 * 47 *
34 * 1) We handle one interrupt and return, sitting in a loop and moving across 48 * 1) We handle one interrupt and return, sitting in a loop and moving across
@@ -80,74 +94,62 @@
80 94
81 mfc0 s0, CP0_CAUSE # get irq bits 95 mfc0 s0, CP0_CAUSE # get irq bits
82 mfc0 s1, CP0_STATUS # get irq mask 96 mfc0 s1, CP0_STATUS # get irq mask
97 andi s0, ST0_IM # CAUSE.CE may be non-zero!
83 and s0, s1 98 and s0, s1
84 99
85 /* First we check for r4k counter/timer IRQ. */ 100#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
86 andi a0, s0, CAUSEF_IP7 101 .set mips32
87 beq a0, zero, 1f 102 clz a0, s0
88 andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt 103 .set mips0
104 negu a0
105 addu a0, 31-CAUSEB_IP
106 bltz a0, spurious
107#else
108 beqz s0, spurious
109 li a0, 7
89 110
90 /* Wheee, a timer interrupt. */ 111 and t0, s0, 0xf000
91 move a0, sp 112 sltiu t0, t0, 1
92 jal mips_timer_interrupt 113 sll t0, 2
93 nop 114 subu a0, t0
115 sll s0, t0
94 116
95 j ret_from_irq 117 and t0, s0, 0xc000
96 nop 118 sltiu t0, t0, 1
119 sll t0, 1
120 subu a0, t0
121 sll s0, t0
97 122
981: 123 and t0, s0, 0x8000
99#if defined(CONFIG_MIPS_SEAD) 124 sltiu t0, t0, 1
100 beq a0, zero, 1f 125 # sll t0, 0
101 andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt 126 subu a0, t0
102#else 127 # sll s0, t0
103 beq a0, zero, 1f # delay slot, check hw3 interrupt
104 andi a0, s0, CAUSEF_IP5
105#endif 128#endif
106 129
107 /* Wheee, combined hardware level zero interrupt. */ 130#ifdef CASCADE_IRQ
108#if defined(CONFIG_MIPS_ATLAS) 131 li a1, CASCADE_IRQ
109 jal atlas_hw0_irqdispatch 132 bne a0, a1, 1f
110#elif defined(CONFIG_MIPS_MALTA) 133 addu a0, MIPSCPU_INT_BASE
111 jal malta_hw0_irqdispatch
112#elif defined(CONFIG_MIPS_SEAD)
113 jal sead_hw0_irqdispatch
114#else
115#error "MIPS board not supported\n"
116#endif
117 move a0, sp # delay slot
118 134
119 j ret_from_irq 135 jal CASCADE_DISPATCH
120 nop # delay slot 136 move a0, sp
121 137
1221:
123#if defined(CONFIG_MIPS_SEAD)
124 beq a0, zero, 1f
125 andi a0, s0, CAUSEF_IP5 # delay slot, check hw3 interrupt
126 jal sead_hw1_irqdispatch
127 move a0, sp # delay slot
128 j ret_from_irq
129 nop # delay slot
1301:
131#endif
132#if defined(CONFIG_MIPS_MALTA)
133 beq a0, zero, 1f # check hw3 (coreHI) interrupt
134 nop
135 jal corehi_irqdispatch
136 move a0, sp
137 j ret_from_irq 138 j ret_from_irq
138 nop 139 nop
1391: 1401:
141#else
142 addu a0, MIPSCPU_INT_BASE
140#endif 143#endif
141 /* 144
142 * Here by mistake? This is possible, what can happen is that by the 145 jal do_IRQ
143 * time we take the exception the IRQ pin goes low, so just leave if 146 move a1, sp
144 * this is the case.
145 */
146 move a1,s0
147 PRINT("Got interrupt: c0_cause = %08x\n")
148 mfc0 a1, CP0_EPC
149 PRINT("c0_epc = %08x\n")
150 147
151 j ret_from_irq 148 j ret_from_irq
152 nop 149 nop
150
151
152spurious:
153 j spurious_interrupt
154 nop
153 END(mipsIRQ) 155 END(mipsIRQ)
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index 92c34bda02ae..1f6f9df74ab2 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
4 * 6 *
5 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
6 * 8 *
@@ -19,65 +21,46 @@
19 * 21 *
20 * MIPS boards specific PCI support. 22 * MIPS boards specific PCI support.
21 */ 23 */
22#include <linux/config.h>
23#include <linux/types.h> 24#include <linux/types.h>
24#include <linux/pci.h> 25#include <linux/pci.h>
25#include <linux/kernel.h> 26#include <linux/kernel.h>
26#include <linux/init.h> 27#include <linux/init.h>
27 28
28#include <asm/mips-boards/generic.h>
29#include <asm/gt64120.h> 29#include <asm/gt64120.h>
30
31#include <asm/mips-boards/generic.h>
30#include <asm/mips-boards/bonito64.h> 32#include <asm/mips-boards/bonito64.h>
31#include <asm/mips-boards/msc01_pci.h> 33#include <asm/mips-boards/msc01_pci.h>
32#ifdef CONFIG_MIPS_MALTA
33#include <asm/mips-boards/malta.h>
34#endif
35 34
36static struct resource bonito64_mem_resource = { 35static struct resource bonito64_mem_resource = {
37 .name = "Bonito PCI MEM", 36 .name = "Bonito PCI MEM",
38 .start = 0x10000000UL,
39 .end = 0x1bffffffUL,
40 .flags = IORESOURCE_MEM, 37 .flags = IORESOURCE_MEM,
41}; 38};
42 39
43static struct resource bonito64_io_resource = { 40static struct resource bonito64_io_resource = {
44 .name = "Bonito IO MEM", 41 .name = "Bonito PCI I/O",
45 .start = 0x00002000UL, /* avoid conflicts with YAMON allocated I/O addresses */ 42 .start = 0x00000000UL,
46 .end = 0x000fffffUL, 43 .end = 0x000fffffUL,
47 .flags = IORESOURCE_IO, 44 .flags = IORESOURCE_IO,
48}; 45};
49 46
50static struct resource gt64120_mem_resource = { 47static struct resource gt64120_mem_resource = {
51 .name = "GT64120 PCI MEM", 48 .name = "GT-64120 PCI MEM",
52 .start = 0x10000000UL,
53 .end = 0x1bdfffffUL,
54 .flags = IORESOURCE_MEM, 49 .flags = IORESOURCE_MEM,
55}; 50};
56 51
57static struct resource gt64120_io_resource = { 52static struct resource gt64120_io_resource = {
58 .name = "GT64120 IO MEM", 53 .name = "GT-64120 PCI I/O",
59#ifdef CONFIG_MIPS_ATLAS
60 .start = 0x18000000UL,
61 .end = 0x181fffffUL,
62#endif
63#ifdef CONFIG_MIPS_MALTA
64 .start = 0x00002000UL,
65 .end = 0x001fffffUL,
66#endif
67 .flags = IORESOURCE_IO, 54 .flags = IORESOURCE_IO,
68}; 55};
69 56
70static struct resource msc_mem_resource = { 57static struct resource msc_mem_resource = {
71 .name = "MSC PCI MEM", 58 .name = "MSC PCI MEM",
72 .start = 0x10000000UL,
73 .end = 0x1fffffffUL,
74 .flags = IORESOURCE_MEM, 59 .flags = IORESOURCE_MEM,
75}; 60};
76 61
77static struct resource msc_io_resource = { 62static struct resource msc_io_resource = {
78 .name = "MSC IO MEM", 63 .name = "MSC PCI I/O",
79 .start = 0x00002000UL,
80 .end = 0x007fffffUL,
81 .flags = IORESOURCE_IO, 64 .flags = IORESOURCE_IO,
82}; 65};
83 66
@@ -89,7 +72,6 @@ static struct pci_controller bonito64_controller = {
89 .pci_ops = &bonito64_pci_ops, 72 .pci_ops = &bonito64_pci_ops,
90 .io_resource = &bonito64_io_resource, 73 .io_resource = &bonito64_io_resource,
91 .mem_resource = &bonito64_mem_resource, 74 .mem_resource = &bonito64_mem_resource,
92 .mem_offset = 0x10000000UL,
93 .io_offset = 0x00000000UL, 75 .io_offset = 0x00000000UL,
94}; 76};
95 77
@@ -97,21 +79,18 @@ static struct pci_controller gt64120_controller = {
97 .pci_ops = &gt64120_pci_ops, 79 .pci_ops = &gt64120_pci_ops,
98 .io_resource = &gt64120_io_resource, 80 .io_resource = &gt64120_io_resource,
99 .mem_resource = &gt64120_mem_resource, 81 .mem_resource = &gt64120_mem_resource,
100 .mem_offset = 0x00000000UL,
101 .io_offset = 0x00000000UL,
102}; 82};
103 83
104static struct pci_controller msc_controller = { 84static struct pci_controller msc_controller = {
105 .pci_ops = &msc_pci_ops, 85 .pci_ops = &msc_pci_ops,
106 .io_resource = &msc_io_resource, 86 .io_resource = &msc_io_resource,
107 .mem_resource = &msc_mem_resource, 87 .mem_resource = &msc_mem_resource,
108 .mem_offset = 0x10000000UL,
109 .io_offset = 0x00000000UL,
110}; 88};
111 89
112static int __init pcibios_init(void) 90void __init mips_pcibios_init(void)
113{ 91{
114 struct pci_controller *controller; 92 struct pci_controller *controller;
93 unsigned long start, end, map, start1, end1, map1, map2, map3, mask;
115 94
116 switch (mips_revision_corid) { 95 switch (mips_revision_corid) {
117 case MIPS_REVISION_CORID_QED_RM5261: 96 case MIPS_REVISION_CORID_QED_RM5261:
@@ -130,34 +109,140 @@ static int __init pcibios_init(void)
130 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ 109 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
131 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ 110 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
132 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ 111 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
133 GT_PCI0_CFGADDR_CONFIGEN_BIT ); 112 GT_PCI0_CFGADDR_CONFIGEN_BIT);
134 113
135 /* Perform the write */ 114 /* Perform the write */
136 GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); 115 GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
137 116
117 /* Set up resource ranges from the controller's registers. */
118 start = GT_READ(GT_PCI0M0LD_OFS);
119 end = GT_READ(GT_PCI0M0HD_OFS);
120 map = GT_READ(GT_PCI0M0REMAP_OFS);
121 end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
122 start1 = GT_READ(GT_PCI0M1LD_OFS);
123 end1 = GT_READ(GT_PCI0M1HD_OFS);
124 map1 = GT_READ(GT_PCI0M1REMAP_OFS);
125 end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
126 /* Cannot support multiple windows, use the wider. */
127 if (end1 - start1 > end - start) {
128 start = start1;
129 end = end1;
130 map = map1;
131 }
132 mask = ~(start ^ end);
133 /* We don't support remapping with a discontiguous mask. */
134 BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
135 mask != ~((mask & -mask) - 1));
136 gt64120_mem_resource.start = start;
137 gt64120_mem_resource.end = end;
138 gt64120_controller.mem_offset = (start & mask) - (map & mask);
139 /* Addresses are 36-bit, so do shifts in the destinations. */
140 gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
141 gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
142 gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
143 gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
144
145 start = GT_READ(GT_PCI0IOLD_OFS);
146 end = GT_READ(GT_PCI0IOHD_OFS);
147 map = GT_READ(GT_PCI0IOREMAP_OFS);
148 end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
149 mask = ~(start ^ end);
150 /* We don't support remapping with a discontiguous mask. */
151 BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
152 mask != ~((mask & -mask) - 1));
153 gt64120_io_resource.start = map & mask;
154 gt64120_io_resource.end = (map & mask) | ~mask;
155 gt64120_controller.io_offset = 0;
156 /* Addresses are 36-bit, so do shifts in the destinations. */
157 gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
158 gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
159 gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
160
138 controller = &gt64120_controller; 161 controller = &gt64120_controller;
139 break; 162 break;
140 163
141 case MIPS_REVISION_CORID_BONITO64: 164 case MIPS_REVISION_CORID_BONITO64:
142 case MIPS_REVISION_CORID_CORE_20K: 165 case MIPS_REVISION_CORID_CORE_20K:
143 case MIPS_REVISION_CORID_CORE_EMUL_BON: 166 case MIPS_REVISION_CORID_CORE_EMUL_BON:
167 /* Set up resource ranges from the controller's registers. */
168 map = BONITO_PCIMAP;
169 map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
170 BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
171 map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
172 BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
173 map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
174 BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
175 /* Combine as many adjacent windows as possible. */
176 map = map1;
177 start = BONITO_PCILO0_BASE;
178 end = 1;
179 if (map3 == map2 + 1) {
180 map = map2;
181 start = BONITO_PCILO1_BASE;
182 end++;
183 }
184 if (map2 == map1 + 1) {
185 map = map1;
186 start = BONITO_PCILO0_BASE;
187 end++;
188 }
189 bonito64_mem_resource.start = start;
190 bonito64_mem_resource.end = start +
191 BONITO_PCIMAP_WINBASE(end) - 1;
192 bonito64_controller.mem_offset = start -
193 BONITO_PCIMAP_WINBASE(map);
194
144 controller = &bonito64_controller; 195 controller = &bonito64_controller;
145 break; 196 break;
146 197
147 case MIPS_REVISION_CORID_CORE_MSC: 198 case MIPS_REVISION_CORID_CORE_MSC:
148 case MIPS_REVISION_CORID_CORE_FPGA2: 199 case MIPS_REVISION_CORID_CORE_FPGA2:
200 case MIPS_REVISION_CORID_CORE_FPGA3:
149 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 201 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
202 /* Set up resource ranges from the controller's registers. */
203 MSC_READ(MSC01_PCI_SC2PMBASL, start);
204 MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
205 MSC_READ(MSC01_PCI_SC2PMMAPL, map);
206 msc_mem_resource.start = start & mask;
207 msc_mem_resource.end = (start & mask) | ~mask;
208 msc_controller.mem_offset = (start & mask) - (map & mask);
209
210 MSC_READ(MSC01_PCI_SC2PIOBASL, start);
211 MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
212 MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
213 msc_io_resource.start = map & mask;
214 msc_io_resource.end = (map & mask) | ~mask;
215 msc_controller.io_offset = 0;
216 ioport_resource.end = ~mask;
217
218 /* If ranges overlap I/O takes precedence. */
219 start = start & mask;
220 end = start | ~mask;
221 if ((start >= msc_mem_resource.start &&
222 start <= msc_mem_resource.end) ||
223 (end >= msc_mem_resource.start &&
224 end <= msc_mem_resource.end)) {
225 /* Use the larger space. */
226 start = max(start, msc_mem_resource.start);
227 end = min(end, msc_mem_resource.end);
228 if (start - msc_mem_resource.start >=
229 msc_mem_resource.end - end)
230 msc_mem_resource.end = start - 1;
231 else
232 msc_mem_resource.start = end + 1;
233 }
234
150 controller = &msc_controller; 235 controller = &msc_controller;
151 break; 236 break;
152 default: 237 default:
153 return 1; 238 return;
154 } 239 }
155 240
241 if (controller->io_resource->start < 0x00001000UL) /* FIXME */
242 controller->io_resource->start = 0x00001000UL;
243
244 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
156 ioport_resource.end = controller->io_resource->end; 245 ioport_resource.end = controller->io_resource->end;
157 246
158 register_pci_controller (controller); 247 register_pci_controller (controller);
159
160 return 0;
161} 248}
162
163early_initcall(pcibios_init);
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 16315444dd5a..72a12d931cba 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -31,22 +31,21 @@
31 31
32#include <asm/mipsregs.h> 32#include <asm/mipsregs.h>
33#include <asm/ptrace.h> 33#include <asm/ptrace.h>
34#include <asm/hardirq.h>
35#include <asm/irq.h>
34#include <asm/div64.h> 36#include <asm/div64.h>
35#include <asm/cpu.h> 37#include <asm/cpu.h>
36#include <asm/time.h> 38#include <asm/time.h>
37#include <asm/mc146818-time.h> 39#include <asm/mc146818-time.h>
40#include <asm/msc01_ic.h>
38 41
39#include <asm/mips-boards/generic.h> 42#include <asm/mips-boards/generic.h>
40#include <asm/mips-boards/prom.h> 43#include <asm/mips-boards/prom.h>
44#include <asm/mips-boards/maltaint.h>
45#include <asm/mc146818-time.h>
41 46
42unsigned long cpu_khz; 47unsigned long cpu_khz;
43 48
44#if defined(CONFIG_MIPS_SEAD)
45#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ5)
46#else
47#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
48#endif
49
50#if defined(CONFIG_MIPS_ATLAS) 49#if defined(CONFIG_MIPS_ATLAS)
51static char display_string[] = " LINUX ON ATLAS "; 50static char display_string[] = " LINUX ON ATLAS ";
52#endif 51#endif
@@ -59,20 +58,61 @@ static char display_string[] = " LINUX ON SEAD ";
59static unsigned int display_count = 0; 58static unsigned int display_count = 0;
60#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) 59#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
61 60
62#define MIPS_CPU_TIMER_IRQ (NR_IRQS-1)
63
64static unsigned int timer_tick_count=0; 61static unsigned int timer_tick_count=0;
62static int mips_cpu_timer_irq;
65 63
66void mips_timer_interrupt(struct pt_regs *regs) 64static inline void scroll_display_message(void)
67{ 65{
68 if ((timer_tick_count++ % HZ) == 0) { 66 if ((timer_tick_count++ % HZ) == 0) {
69 mips_display_message(&display_string[display_count++]); 67 mips_display_message(&display_string[display_count++]);
70 if (display_count == MAX_DISPLAY_COUNT) 68 if (display_count == MAX_DISPLAY_COUNT)
71 display_count = 0; 69 display_count = 0;
70 }
71}
72
73static void mips_timer_dispatch (struct pt_regs *regs)
74{
75 do_IRQ (mips_cpu_timer_irq, regs);
76}
72 77
78irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
79{
80#ifdef CONFIG_SMP
81 int cpu = smp_processor_id();
82
83 if (cpu == 0) {
84 /*
85 * CPU 0 handles the global timer interrupt job and process accounting
86 * resets count/compare registers to trigger next timer int.
87 */
88 (void) timer_interrupt(irq, dev_id, regs);
89 scroll_display_message();
90 }
91 else {
92 /* Everyone else needs to reset the timer int here as
93 ll_local_timer_interrupt doesn't */
94 /*
95 * FIXME: need to cope with counter underflow.
96 * More support needs to be added to kernel/time for
97 * counter/timer interrupts on multiple CPU's
98 */
99 write_c0_compare (read_c0_count() + (mips_hpt_frequency/HZ));
100 /*
101 * other CPUs should do profiling and process accounting
102 */
103 local_timer_interrupt (irq, dev_id, regs);
73 } 104 }
74 105
75 ll_timer_interrupt(MIPS_CPU_TIMER_IRQ, regs); 106 return IRQ_HANDLED;
107#else
108 irqreturn_t r;
109
110 r = timer_interrupt(irq, dev_id, regs);
111
112 scroll_display_message();
113
114 return r;
115#endif
76} 116}
77 117
78/* 118/*
@@ -140,10 +180,8 @@ void __init mips_time_init(void)
140 180
141 local_irq_save(flags); 181 local_irq_save(flags);
142 182
143#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
144 /* Set Data mode - binary. */ 183 /* Set Data mode - binary. */
145 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); 184 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
146#endif
147 185
148 est_freq = estimate_cpu_frequency (); 186 est_freq = estimate_cpu_frequency ();
149 187
@@ -157,11 +195,29 @@ void __init mips_time_init(void)
157 195
158void __init mips_timer_setup(struct irqaction *irq) 196void __init mips_timer_setup(struct irqaction *irq)
159{ 197{
198 if (cpu_has_veic) {
199 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
200 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
201 }
202 else {
203 if (cpu_has_vint)
204 set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
205 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
206 }
207
208
160 /* we are using the cpu counter for timer interrupts */ 209 /* we are using the cpu counter for timer interrupts */
161 irq->handler = no_action; /* we use our own handler */ 210 irq->handler = mips_timer_interrupt; /* we use our own handler */
162 setup_irq(MIPS_CPU_TIMER_IRQ, irq); 211 setup_irq(mips_cpu_timer_irq, irq);
212
213#ifdef CONFIG_SMP
214 /* irq_desc(riptor) is a global resource, when the interrupt overlaps
215 on seperate cpu's the first one tries to handle the second interrupt.
216 The effect is that the int remains disabled on the second cpu.
217 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
218 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
219#endif
163 220
164 /* to generate the first timer interrupt */ 221 /* to generate the first timer interrupt */
165 write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); 222 write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
166 set_c0_status(ALLINTS);
167} 223}
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index dd2db35966bc..d06dc5ad6c9e 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -30,6 +30,7 @@
30#include <linux/random.h> 30#include <linux/random.h>
31 31
32#include <asm/i8259.h> 32#include <asm/i8259.h>
33#include <asm/irq_cpu.h>
33#include <asm/io.h> 34#include <asm/io.h>
34#include <asm/mips-boards/malta.h> 35#include <asm/mips-boards/malta.h>
35#include <asm/mips-boards/maltaint.h> 36#include <asm/mips-boards/maltaint.h>
@@ -37,8 +38,10 @@
37#include <asm/gt64120.h> 38#include <asm/gt64120.h>
38#include <asm/mips-boards/generic.h> 39#include <asm/mips-boards/generic.h>
39#include <asm/mips-boards/msc01_pci.h> 40#include <asm/mips-boards/msc01_pci.h>
41#include <asm/msc01_ic.h>
40 42
41extern asmlinkage void mipsIRQ(void); 43extern asmlinkage void mipsIRQ(void);
44extern void mips_timer_interrupt(void);
42 45
43static DEFINE_SPINLOCK(mips_irq_lock); 46static DEFINE_SPINLOCK(mips_irq_lock);
44 47
@@ -54,6 +57,7 @@ static inline int mips_pcibios_iack(void)
54 switch(mips_revision_corid) { 57 switch(mips_revision_corid) {
55 case MIPS_REVISION_CORID_CORE_MSC: 58 case MIPS_REVISION_CORID_CORE_MSC:
56 case MIPS_REVISION_CORID_CORE_FPGA2: 59 case MIPS_REVISION_CORID_CORE_FPGA2:
60 case MIPS_REVISION_CORID_CORE_FPGA3:
57 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 61 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
58 MSC_READ(MSC01_PCI_IACK, irq); 62 MSC_READ(MSC01_PCI_IACK, irq);
59 irq &= 0xff; 63 irq &= 0xff;
@@ -91,88 +95,86 @@ static inline int mips_pcibios_iack(void)
91 return irq; 95 return irq;
92} 96}
93 97
94static inline int get_int(int *irq) 98static inline int get_int(void)
95{ 99{
96 unsigned long flags; 100 unsigned long flags;
97 101 int irq;
98 spin_lock_irqsave(&mips_irq_lock, flags); 102 spin_lock_irqsave(&mips_irq_lock, flags);
99 103
100 *irq = mips_pcibios_iack(); 104 irq = mips_pcibios_iack();
101 105
102 /* 106 /*
103 * IRQ7 is used to detect spurious interrupts. 107 * The only way we can decide if an interrupt is spurious
104 * The interrupt acknowledge cycle returns IRQ7, if no 108 * is by checking the 8259 registers. This needs a spinlock
105 * interrupts is requested. 109 * on an SMP system, so leave it up to the generic code...
106 * We can differentiate between this situation and a
107 * "Normal" IRQ7 by reading the ISR.
108 */ 110 */
109 if (*irq == 7)
110 {
111 outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR,
112 PIIX4_ICTLR1_OCW3);
113 if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) {
114 spin_unlock_irqrestore(&mips_irq_lock, flags);
115 printk("We got a spurious interrupt from PIIX4.\n");
116 atomic_inc(&irq_err_count);
117 return -1; /* Spurious interrupt. */
118 }
119 }
120 111
121 spin_unlock_irqrestore(&mips_irq_lock, flags); 112 spin_unlock_irqrestore(&mips_irq_lock, flags);
122 113
123 return 0; 114 return irq;
124} 115}
125 116
126void malta_hw0_irqdispatch(struct pt_regs *regs) 117void malta_hw0_irqdispatch(struct pt_regs *regs)
127{ 118{
128 int irq; 119 int irq;
129 120
130 if (get_int(&irq)) 121 irq = get_int();
131 return; /* interrupt has already been cleared */ 122 if (irq < 0)
123 return; /* interrupt has already been cleared */
132 124
133 do_IRQ(irq, regs); 125 do_IRQ(MALTA_INT_BASE+irq, regs);
134} 126}
135 127
136void corehi_irqdispatch(struct pt_regs *regs) 128void corehi_irqdispatch(struct pt_regs *regs)
137{ 129{
138 unsigned int data,datahi; 130 unsigned int intrcause,datalo,datahi;
139 131 unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;
140 /* Mask out corehi interrupt. */
141 clear_c0_status(IE_IRQ3);
142 132
143 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); 133 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
144 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n" 134 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
145, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr); 135, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
136
137 /* Read all the registers and then print them as there is a
138 problem with interspersed printk's upsetting the Bonito controller.
139 Do it for the others too.
140 */
141
146 switch(mips_revision_corid) { 142 switch(mips_revision_corid) {
147 case MIPS_REVISION_CORID_CORE_MSC: 143 case MIPS_REVISION_CORID_CORE_MSC:
148 case MIPS_REVISION_CORID_CORE_FPGA2: 144 case MIPS_REVISION_CORID_CORE_FPGA2:
149 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 145 case MIPS_REVISION_CORID_CORE_FPGA3:
146 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
147 ll_msc_irq(regs);
150 break; 148 break;
151 case MIPS_REVISION_CORID_QED_RM5261: 149 case MIPS_REVISION_CORID_QED_RM5261:
152 case MIPS_REVISION_CORID_CORE_LV: 150 case MIPS_REVISION_CORID_CORE_LV:
153 case MIPS_REVISION_CORID_CORE_FPGA: 151 case MIPS_REVISION_CORID_CORE_FPGA:
154 case MIPS_REVISION_CORID_CORE_FPGAR2: 152 case MIPS_REVISION_CORID_CORE_FPGAR2:
155 data = GT_READ(GT_INTRCAUSE_OFS); 153 intrcause = GT_READ(GT_INTRCAUSE_OFS);
156 printk("GT_INTRCAUSE = %08x\n", data); 154 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
157 data = GT_READ(GT_CPUERR_ADDRLO_OFS);
158 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); 155 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
159 printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, data); 156 printk("GT_INTRCAUSE = %08x\n", intrcause);
157 printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
160 break; 158 break;
161 case MIPS_REVISION_CORID_BONITO64: 159 case MIPS_REVISION_CORID_BONITO64:
162 case MIPS_REVISION_CORID_CORE_20K: 160 case MIPS_REVISION_CORID_CORE_20K:
163 case MIPS_REVISION_CORID_CORE_EMUL_BON: 161 case MIPS_REVISION_CORID_CORE_EMUL_BON:
164 data = BONITO_INTISR; 162 pcibadaddr = BONITO_PCIBADADDR;
165 printk("BONITO_INTISR = %08x\n", data); 163 pcimstat = BONITO_PCIMSTAT;
166 data = BONITO_INTEN; 164 intisr = BONITO_INTISR;
167 printk("BONITO_INTEN = %08x\n", data); 165 inten = BONITO_INTEN;
168 data = BONITO_INTPOL; 166 intpol = BONITO_INTPOL;
169 printk("BONITO_INTPOL = %08x\n", data); 167 intedge = BONITO_INTEDGE;
170 data = BONITO_INTEDGE; 168 intsteer = BONITO_INTSTEER;
171 printk("BONITO_INTEDGE = %08x\n", data); 169 pcicmd = BONITO_PCICMD;
172 data = BONITO_INTSTEER; 170 printk("BONITO_INTISR = %08x\n", intisr);
173 printk("BONITO_INTSTEER = %08x\n", data); 171 printk("BONITO_INTEN = %08x\n", inten);
174 data = BONITO_PCICMD; 172 printk("BONITO_INTPOL = %08x\n", intpol);
175 printk("BONITO_PCICMD = %08x\n", data); 173 printk("BONITO_INTEDGE = %08x\n", intedge);
174 printk("BONITO_INTSTEER = %08x\n", intsteer);
175 printk("BONITO_PCICMD = %08x\n", pcicmd);
176 printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
177 printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
176 break; 178 break;
177 } 179 }
178 180
@@ -180,8 +182,71 @@ void corehi_irqdispatch(struct pt_regs *regs)
180 die("CoreHi interrupt", regs); 182 die("CoreHi interrupt", regs);
181} 183}
182 184
185static struct irqaction i8259irq = {
186 .handler = no_action,
187 .name = "XT-PIC cascade"
188};
189
190static struct irqaction corehi_irqaction = {
191 .handler = no_action,
192 .name = "CoreHi"
193};
194
195msc_irqmap_t __initdata msc_irqmap[] = {
196 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
197 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
198};
199int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);
200
201msc_irqmap_t __initdata msc_eicirqmap[] = {
202 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
203 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
204 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
205 {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
206 {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
207 {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
208 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
209 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
210 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
211 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
212};
213int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
214
183void __init arch_init_irq(void) 215void __init arch_init_irq(void)
184{ 216{
185 set_except_vector(0, mipsIRQ); 217 set_except_vector(0, mipsIRQ);
186 init_i8259_irqs(); 218 init_i8259_irqs();
219
220 if (!cpu_has_veic)
221 mips_cpu_irq_init (MIPSCPU_INT_BASE);
222
223 switch(mips_revision_corid) {
224 case MIPS_REVISION_CORID_CORE_MSC:
225 case MIPS_REVISION_CORID_CORE_FPGA2:
226 case MIPS_REVISION_CORID_CORE_FPGA3:
227 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
228 if (cpu_has_veic)
229 init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
230 else
231 init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
232 }
233
234 if (cpu_has_veic) {
235 set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
236 set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
237 setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
238 setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
239 }
240 else if (cpu_has_vint) {
241 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
242 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
243
244 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
245 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
246 }
247 else {
248 set_except_vector(0, mipsIRQ);
249 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
250 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
251 }
187} 252}
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index df6db6419ae9..2209e8a9de34 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -111,10 +111,12 @@ void __init fd_activate(void)
111} 111}
112#endif 112#endif
113 113
114static int __init malta_setup(void) 114void __init plat_setup(void)
115{ 115{
116 unsigned int i; 116 unsigned int i;
117 117
118 mips_pcibios_init();
119
118 /* Request I/O space for devices used on the Malta board. */ 120 /* Request I/O space for devices used on the Malta board. */
119 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) 121 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
120 request_resource(&ioport_resource, standard_io_resources+i); 122 request_resource(&ioport_resource, standard_io_resources+i);
@@ -224,8 +226,4 @@ static int __init malta_setup(void)
224 board_time_init = mips_time_init; 226 board_time_init = mips_time_init;
225 board_timer_setup = mips_timer_setup; 227 board_timer_setup = mips_timer_setup;
226 rtc_get_time = mips_rtc_get_time; 228 rtc_get_time = mips_rtc_get_time;
227
228 return 0;
229} 229}
230
231early_initcall(malta_setup);
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index e5109657ed5a..e1dd7e009750 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -2,6 +2,7 @@
2 * Carsten Langgaard, carstenl@mips.com 2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. 3 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
4 * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) 4 * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
5 * Copyright (C) 2004 Maciej W. Rozycki
5 * 6 *
6 * This program is free software; you can distribute it and/or modify it 7 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as 8 * under the terms of the GNU General Public License (Version 2) as
@@ -21,7 +22,9 @@
21 */ 22 */
22#include <linux/init.h> 23#include <linux/init.h>
23#include <linux/irq.h> 24#include <linux/irq.h>
24#include <linux/interrupt.h> 25
26#include <asm/irq_cpu.h>
27#include <asm/system.h>
25 28
26#include <asm/mips-boards/seadint.h> 29#include <asm/mips-boards/seadint.h>
27 30
@@ -39,13 +42,8 @@ asmlinkage void sead_hw1_irqdispatch(struct pt_regs *regs)
39 42
40void __init arch_init_irq(void) 43void __init arch_init_irq(void)
41{ 44{
42 /* 45 mips_cpu_irq_init(0);
43 * Mask out all interrupt
44 */
45 clear_c0_status(0x0000ff00);
46 46
47 /* Now safe to set the exception vector. */ 47 /* Now safe to set the exception vector. */
48 set_except_vector(0, mipsIRQ); 48 set_except_vector(0, mipsIRQ);
49
50 mips_cpu_irq_init(0);
51} 49}
diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c
index 29892b88a4fc..de90bec5505e 100644
--- a/arch/mips/mips-boards/sead/sead_setup.c
+++ b/arch/mips/mips-boards/sead/sead_setup.c
@@ -57,8 +57,6 @@ static void __init sead_setup(void)
57 mips_reboot_setup(); 57 mips_reboot_setup();
58} 58}
59 59
60early_initcall(sead_setup);
61
62static void __init serial_init(void) 60static void __init serial_init(void)
63{ 61{
64#ifdef CONFIG_SERIAL_8250 62#ifdef CONFIG_SERIAL_8250
diff --git a/arch/mips/mips-boards/sim/Makefile b/arch/mips/mips-boards/sim/Makefile
new file mode 100644
index 000000000000..5b977de4ecff
--- /dev/null
+++ b/arch/mips/mips-boards/sim/Makefile
@@ -0,0 +1,20 @@
1#
2# Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3#
4# This program is free software; you can distribute it and/or modify it
5# under the terms of the GNU General Public License (Version 2) as
6# published by the Free Software Foundation.
7#
8# This program is distributed in the hope it will be useful, but WITHOUT
9# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11# for more details.
12#
13# You should have received a copy of the GNU General Public License along
14# with this program; if not, write to the Free Software Foundation, Inc.,
15# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16#
17
18obj-y := sim_setup.o sim_mem.o sim_time.o sim_printf.o sim_int.o sim_irq.o \
19 sim_cmdline.o
20obj-$(CONFIG_SMP) += sim_smp.o
diff --git a/arch/mips/mips-boards/sim/cmdline.c b/arch/mips/mips-boards/sim/cmdline.c
new file mode 100644
index 000000000000..fef9fbd8e710
--- /dev/null
+++ b/arch/mips/mips-boards/sim/cmdline.c
@@ -0,0 +1,59 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Kernel command line creation using the prom monitor (YAMON) argc/argv.
19 */
20#include <linux/init.h>
21#include <linux/string.h>
22
23#include <asm/bootinfo.h>
24
25extern int prom_argc;
26extern int *_prom_argv;
27
28/*
29 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
30 * This macro take care of sign extension.
31 */
32#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
33
34char arcs_cmdline[CL_SIZE];
35
36char * __init prom_getcmdline(void)
37{
38 return &(arcs_cmdline[0]);
39}
40
41
42void __init prom_init_cmdline(void)
43{
44 char *cp;
45 int actr;
46
47 actr = 1; /* Always ignore argv[0] */
48
49 cp = &(arcs_cmdline[0]);
50 while(actr < prom_argc) {
51 strcpy(cp, prom_argv(actr));
52 cp += strlen(prom_argv(actr));
53 *cp++ = ' ';
54 actr++;
55 }
56 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
57 --cp;
58 *cp = '\0';
59}
diff --git a/arch/mips/mips-boards/sim/sim_IRQ.c b/arch/mips/mips-boards/sim/sim_IRQ.c
new file mode 100644
index 000000000000..9987a85aabeb
--- /dev/null
+++ b/arch/mips/mips-boards/sim/sim_IRQ.c
@@ -0,0 +1,148 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Interrupt exception dispatch code.
19 */
20#include <linux/config.h>
21
22#include <asm/asm.h>
23#include <asm/mipsregs.h>
24#include <asm/regdef.h>
25#include <asm/stackframe.h>
26
27/* A lot of complication here is taken away because:
28 *
29 * 1) We handle one interrupt and return, sitting in a loop and moving across
30 * all the pending IRQ bits in the cause register is _NOT_ the answer, the
31 * common case is one pending IRQ so optimize in that direction.
32 *
33 * 2) We need not check against bits in the status register IRQ mask, that
34 * would make this routine slow as hell.
35 *
36 * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
37 * between like BSD spl() brain-damage.
38 *
39 * Furthermore, the IRQs on the MIPS board look basically (barring software
40 * IRQs which we don't use at all and all external interrupt sources are
41 * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
42 *
43 * MIPS IRQ Source
44 * -------- ------
45 * 0 Software (ignored)
46 * 1 Software (ignored)
47 * 2 Combined hardware interrupt (hw0)
48 * 3 Hardware (ignored)
49 * 4 Hardware (ignored)
50 * 5 Hardware (ignored)
51 * 6 Hardware (ignored)
52 * 7 R4k timer (what we use)
53 *
54 * Note: On the SEAD board thing are a little bit different.
55 * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
56 * wired to UART1.
57 *
58 * We handle the IRQ according to _our_ priority which is:
59 *
60 * Highest ---- R4k Timer
61 * Lowest ---- Combined hardware interrupt
62 *
63 * then we just return, if multiple IRQs are pending then we will just take
64 * another exception, big deal.
65 */
66
67 .text
68 .set noreorder
69 .set noat
70 .align 5
71 NESTED(mipsIRQ, PT_SIZE, sp)
72 SAVE_ALL
73 CLI
74 .set at
75
76 mfc0 s0, CP0_CAUSE # get irq bits
77 mfc0 s1, CP0_STATUS # get irq mask
78 and s0, s1
79
80 /* First we check for r4k counter/timer IRQ. */
81 andi a0, s0, CAUSEF_IP7
82 beq a0, zero, 1f
83 andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
84
85 /* Wheee, a timer interrupt. */
86 move a0, sp
87 jal mips_timer_interrupt
88 nop
89
90 j ret_from_irq
91 nop
92
931:
94#if defined(CONFIG_MIPS_SEAD)
95 beq a0, zero, 1f
96 andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt
97#else
98 beq a0, zero, 1f # delay slot, check hw3 interrupt
99 andi a0, s0, CAUSEF_IP5
100#endif
101
102 /* Wheee, combined hardware level zero interrupt. */
103#if defined(CONFIG_MIPS_ATLAS)
104 jal atlas_hw0_irqdispatch
105#elif defined(CONFIG_MIPS_MALTA)
106 jal malta_hw0_irqdispatch
107#elif defined(CONFIG_MIPS_SEAD)
108 jal sead_hw0_irqdispatch
109#else
110#error "MIPS board not supported\n"
111#endif
112 move a0, sp # delay slot
113
114 j ret_from_irq
115 nop # delay slot
116
1171:
118#if defined(CONFIG_MIPS_SEAD)
119 beq a0, zero, 1f
120 andi a0, s0, CAUSEF_IP5 # delay slot, check hw3 interrupt
121 jal sead_hw1_irqdispatch
122 move a0, sp # delay slot
123 j ret_from_irq
124 nop # delay slot
1251:
126#endif
127#if defined(CONFIG_MIPS_MALTA)
128 beq a0, zero, 1f # check hw3 (coreHI) interrupt
129 nop
130 jal corehi_irqdispatch
131 move a0, sp
132 j ret_from_irq
133 nop
1341:
135#endif
136 /*
137 * Here by mistake? This is possible, what can happen is that by the
138 * time we take the exception the IRQ pin goes low, so just leave if
139 * this is the case.
140 */
141 move a1,s0
142 PRINT("Got interrupt: c0_cause = %08x\n")
143 mfc0 a1, CP0_EPC
144 PRINT("c0_epc = %08x\n")
145
146 j ret_from_irq
147 nop
148 END(mipsIRQ)
diff --git a/arch/mips/mips-boards/sim/sim_cmdline.c b/arch/mips/mips-boards/sim/sim_cmdline.c
new file mode 100644
index 000000000000..9df37c6fca36
--- /dev/null
+++ b/arch/mips/mips-boards/sim/sim_cmdline.c
@@ -0,0 +1,33 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18#include <linux/init.h>
19#include <linux/string.h>
20#include <asm/bootinfo.h>
21
22extern char arcs_cmdline[];
23
24char * __init prom_getcmdline(void)
25{
26 return arcs_cmdline;
27}
28
29
30void __init prom_init_cmdline(void)
31{
32 /* nothing to do */
33}
diff --git a/arch/mips/mips-boards/sim/sim_int.c b/arch/mips/mips-boards/sim/sim_int.c
new file mode 100644
index 000000000000..a4d0a2c05031
--- /dev/null
+++ b/arch/mips/mips-boards/sim/sim_int.c
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18#include <linux/init.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/interrupt.h>
22#include <linux/kernel_stat.h>
23#include <asm/mips-boards/simint.h>
24
25
26extern void mips_cpu_irq_init(int);
27
28extern asmlinkage void simIRQ(void);
29
30asmlinkage void sim_hw0_irqdispatch(struct pt_regs *regs)
31{
32 do_IRQ(2, regs);
33}
34
35void __init arch_init_irq(void)
36{
37 /* Now safe to set the exception vector. */
38 set_except_vector(0, simIRQ);
39
40 mips_cpu_irq_init(MIPSCPU_INT_BASE);
41}
diff --git a/arch/mips/mips-boards/sim/sim_irq.S b/arch/mips/mips-boards/sim/sim_irq.S
new file mode 100644
index 000000000000..835f0387fcd4
--- /dev/null
+++ b/arch/mips/mips-boards/sim/sim_irq.S
@@ -0,0 +1,99 @@
1/*
2 * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 * Interrupt exception dispatch code.
18 *
19 */
20#include <linux/config.h>
21
22#include <asm/asm.h>
23#include <asm/mipsregs.h>
24#include <asm/regdef.h>
25#include <asm/stackframe.h>
26
27#include <asm/mips-boards/simint.h>
28
29
30 .text
31 .set noreorder
32 .set noat
33 .align 5
34 NESTED(simIRQ, PT_SIZE, sp)
35 SAVE_ALL
36 CLI
37 .set at
38
39 mfc0 s0, CP0_CAUSE # get irq bits
40 mfc0 s1, CP0_STATUS # get irq mask
41 andi s0, ST0_IM # CAUSE.CE may be non-zero!
42 and s0, s1
43
44#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
45 .set mips32
46 clz a0, s0
47 .set mips0
48 negu a0
49 addu a0, 31-CAUSEB_IP
50 bltz a0, spurious
51#else
52 beqz s0, spurious
53 li a0, 7
54
55 and t0, s0, 0xf000
56 sltiu t0, t0, 1
57 sll t0, 2
58 subu a0, t0
59 sll s0, t0
60
61 and t0, s0, 0xc000
62 sltiu t0, t0, 1
63 sll t0, 1
64 subu a0, t0
65 sll s0, t0
66
67 and t0, s0, 0x8000
68 sltiu t0, t0, 1
69 # sll t0, 0
70 subu a0, t0
71 # sll s0, t0
72#endif
73
74#ifdef CASCADE_IRQ
75 li a1, CASCADE_IRQ
76 bne a0, a1, 1f
77 addu a0, MIPSCPU_INT_BASE
78
79 jal CASCADE_DISPATCH
80 move a0, sp
81
82 j ret_from_irq
83 nop
841:
85#else
86 addu a0, MIPSCPU_INT_BASE
87#endif
88
89 jal do_IRQ
90 move a1, sp
91
92 j ret_from_irq
93 nop
94
95
96spurious:
97 j spurious_interrupt
98 nop
99 END(simIRQ)
diff --git a/arch/mips/mips-boards/sim/sim_mem.c b/arch/mips/mips-boards/sim/sim_mem.c
new file mode 100644
index 000000000000..0dbd7435bb2a
--- /dev/null
+++ b/arch/mips/mips-boards/sim/sim_mem.c
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18#include <linux/init.h>
19#include <linux/mm.h>
20#include <linux/bootmem.h>
21
22#include <asm/bootinfo.h>
23#include <asm/page.h>
24
25#include <asm/mips-boards/prom.h>
26
27/*#define DEBUG*/
28
29enum simmem_memtypes {
30 simmem_reserved = 0,
31 simmem_free,
32};
33struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
34
35#ifdef DEBUG
36static char *mtypes[3] = {
37 "SIM reserved memory",
38 "SIM free memory",
39};
40#endif
41
42/* References to section boundaries */
43extern char _end;
44
45#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
46
47
48struct prom_pmemblock * __init prom_getmdesc(void)
49{
50 unsigned int memsize;
51
52 memsize = 0x02000000;
53 prom_printf("Setting default memory size 0x%08x\n", memsize);
54
55 memset(mdesc, 0, sizeof(mdesc));
56
57 mdesc[0].type = simmem_reserved;
58 mdesc[0].base = 0x00000000;
59 mdesc[0].size = 0x00001000;
60
61 mdesc[1].type = simmem_free;
62 mdesc[1].base = 0x00001000;
63 mdesc[1].size = 0x000ff000;
64
65 mdesc[2].type = simmem_reserved;
66 mdesc[2].base = 0x00100000;
67 mdesc[2].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[2].base;
68
69 mdesc[3].type = simmem_free;
70 mdesc[3].base = CPHYSADDR(PFN_ALIGN(&_end));
71 mdesc[3].size = memsize - mdesc[3].base;
72
73 return &mdesc[0];
74}
75
76static int __init prom_memtype_classify (unsigned int type)
77{
78 switch (type) {
79 case simmem_free:
80 return BOOT_MEM_RAM;
81 case simmem_reserved:
82 default:
83 return BOOT_MEM_RESERVED;
84 }
85}
86
87void __init prom_meminit(void)
88{
89 struct prom_pmemblock *p;
90
91 p = prom_getmdesc();
92
93 while (p->size) {
94 long type;
95 unsigned long base, size;
96
97 type = prom_memtype_classify (p->type);
98 base = p->base;
99 size = p->size;
100
101 add_memory_region(base, size, type);
102 p++;
103 }
104}
105
106unsigned long __init prom_free_prom_memory(void)
107{
108 int i;
109 unsigned long freed = 0;
110 unsigned long addr;
111
112 for (i = 0; i < boot_mem_map.nr_map; i++) {
113 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
114 continue;
115
116 addr = boot_mem_map.map[i].addr;
117 while (addr < boot_mem_map.map[i].addr
118 + boot_mem_map.map[i].size) {
119 ClearPageReserved(virt_to_page(__va(addr)));
120 set_page_count(virt_to_page(__va(addr)), 1);
121 free_page((unsigned long)__va(addr));
122 addr += PAGE_SIZE;
123 freed += PAGE_SIZE;
124 }
125 }
126 printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
127
128 return freed;
129}
diff --git a/arch/mips/mips-boards/sim/sim_printf.c b/arch/mips/mips-boards/sim/sim_printf.c
new file mode 100644
index 000000000000..3ee5a0b501a6
--- /dev/null
+++ b/arch/mips/mips-boards/sim/sim_printf.c
@@ -0,0 +1,74 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Putting things on the screen/serial line using YAMONs facilities.
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/serial_reg.h>
23#include <linux/spinlock.h>
24#include <asm/io.h>
25#include <asm/system.h>
26
27static inline unsigned int serial_in(int offset)
28{
29 return inb(0x3f8 + offset);
30}
31
32static inline void serial_out(int offset, int value)
33{
34 outb(value, 0x3f8 + offset);
35}
36
37int putPromChar(char c)
38{
39 while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
40 ;
41
42 serial_out(UART_TX, c);
43
44 return 1;
45}
46
47char getPromChar(void)
48{
49 while (!(serial_in(UART_LSR) & 1))
50 ;
51
52 return serial_in(UART_RX);
53}
54
55void prom_printf(char *fmt, ...)
56{
57 va_list args;
58 int l;
59 char *p, *buf_end;
60 char buf[1024];
61
62 va_start(args, fmt);
63 l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */
64 va_end(args);
65
66 buf_end = buf + l;
67
68 for (p = buf; p < buf_end; p++) {
69 /* Crude cr/nl handling is better than none */
70 if (*p == '\n')
71 putPromChar('\r');
72 putPromChar(*p);
73 }
74}
diff --git a/arch/mips/mips-boards/sim/sim_setup.c b/arch/mips/mips-boards/sim/sim_setup.c
new file mode 100644
index 000000000000..485d5a58d9cf
--- /dev/null
+++ b/arch/mips/mips-boards/sim/sim_setup.c
@@ -0,0 +1,101 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18
19#include <linux/config.h>
20#include <linux/init.h>
21#include <linux/string.h>
22#include <linux/kernel.h>
23#include <linux/ioport.h>
24#include <linux/tty.h>
25#include <linux/serial.h>
26#include <linux/serial_core.h>
27
28#include <asm/cpu.h>
29#include <asm/bootinfo.h>
30#include <asm/irq.h>
31#include <asm/mips-boards/generic.h>
32#include <asm/mips-boards/prom.h>
33#include <asm/serial.h>
34#include <asm/io.h>
35#include <asm/time.h>
36#include <asm/mips-boards/sim.h>
37#include <asm/mips-boards/simint.h>
38
39
40extern void sim_time_init(void);
41extern void sim_timer_setup(struct irqaction *irq);
42static void __init serial_init(void);
43unsigned int _isbonito = 0;
44
45extern void __init sanitize_tlb_entries(void);
46
47
48const char *get_system_type(void)
49{
50 return "MIPSsim";
51}
52
53void __init plat_setup(void)
54{
55 set_io_port_base(0xbfd00000);
56
57 serial_init();
58
59 board_time_init = sim_time_init;
60 board_timer_setup = sim_timer_setup;
61 prom_printf("Linux started...\n");
62
63#ifdef CONFIG_MT_SMP
64 sanitize_tlb_entries();
65#endif
66}
67
68void prom_init(void)
69{
70 set_io_port_base(0xbfd00000);
71
72 prom_printf("\nLINUX started...\n");
73 prom_init_cmdline();
74 prom_meminit();
75}
76
77
78static void __init serial_init(void)
79{
80#ifdef CONFIG_SERIAL_8250
81 struct uart_port s;
82
83 memset(&s, 0, sizeof(s));
84
85 s.iobase = 0x3f8;
86
87 /* hardware int 4 - the serial int, is CPU int 6
88 but poll for now */
89 s.irq = 0;
90 s.uartclk = BASE_BAUD * 16;
91 s.flags = ASYNC_BOOT_AUTOCONF | UPF_SKIP_TEST;
92 s.iotype = SERIAL_IO_PORT | ASYNC_SKIP_TEST;
93 s.regshift = 0;
94 s.timeout = 4;
95
96 if (early_serial_setup(&s) != 0) {
97 prom_printf(KERN_ERR "Serial setup failed!\n");
98 }
99
100#endif
101}
diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mips-boards/sim/sim_smp.c
new file mode 100644
index 000000000000..19824359f5de
--- /dev/null
+++ b/arch/mips/mips-boards/sim/sim_smp.c
@@ -0,0 +1,151 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18/*
19 * Simulator Platform-specific hooks for SMP operation
20 */
21#include <linux/config.h>
22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/cpumask.h>
25#include <linux/interrupt.h>
26#include <asm/atomic.h>
27#include <asm/cpu.h>
28#include <asm/processor.h>
29#include <asm/system.h>
30#include <asm/hardirq.h>
31#include <asm/mmu_context.h>
32#include <asm/smp.h>
33#ifdef CONFIG_MIPS_MT_SMTC
34#include <asm/smtc_ipi.h>
35#endif /* CONFIG_MIPS_MT_SMTC */
36
37/* VPE/SMP Prototype implements platform interfaces directly */
38#if !defined(CONFIG_MIPS_MT_SMP)
39
40/*
41 * Cause the specified action to be performed on a targeted "CPU"
42 */
43
44void core_send_ipi(int cpu, unsigned int action)
45{
46#ifdef CONFIG_MIPS_MT_SMTC
47 void smtc_send_ipi(int, int, unsigned int);
48
49 smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
50#endif /* CONFIG_MIPS_MT_SMTC */
51/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
52
53}
54
55/*
56 * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
57 */
58
59void __init prom_build_cpu_map(void)
60{
61#ifdef CONFIG_MIPS_MT_SMTC
62 extern int mipsmt_build_cpu_map(int startslot);
63 int nextslot;
64
65 cpus_clear(phys_cpu_present_map);
66
67 /* Register the boot CPU */
68
69 smp_prepare_boot_cpu();
70
71 /*
72 * As of November, 2004, MIPSsim only simulates one core
73 * at a time. However, that core may be a MIPS MT core
74 * with multiple virtual processors and thread contexts.
75 */
76
77 if (read_c0_config3() & (1<<2)) {
78 nextslot = mipsmt_build_cpu_map(1);
79 }
80#endif /* CONFIG_MIPS_MT_SMTC */
81}
82
83/*
84 * Platform "CPU" startup hook
85 */
86
87void prom_boot_secondary(int cpu, struct task_struct *idle)
88{
89#ifdef CONFIG_MIPS_MT_SMTC
90 extern void smtc_boot_secondary(int cpu, struct task_struct *t);
91
92 smtc_boot_secondary(cpu, idle);
93#endif /* CONFIG_MIPS_MT_SMTC */
94}
95
96/*
97 * Post-config but pre-boot cleanup entry point
98 */
99
100void prom_init_secondary(void)
101{
102#ifdef CONFIG_MIPS_MT_SMTC
103 void smtc_init_secondary(void);
104
105 smtc_init_secondary();
106#endif /* CONFIG_MIPS_MT_SMTC */
107}
108
109/*
110 * Platform SMP pre-initialization
111 */
112
113void prom_prepare_cpus(unsigned int max_cpus)
114{
115#ifdef CONFIG_MIPS_MT_SMTC
116 void mipsmt_prepare_cpus(int c);
117 /*
118 * As noted above, we can assume a single CPU for now
119 * but it may be multithreaded.
120 */
121
122 if (read_c0_config3() & (1<<2)) {
123 mipsmt_prepare_cpus(max_cpus);
124 }
125#endif /* CONFIG_MIPS_MT_SMTC */
126}
127
128/*
129 * SMP initialization finalization entry point
130 */
131
132void prom_smp_finish(void)
133{
134#ifdef CONFIG_MIPS_MT_SMTC
135 void smtc_smp_finish(void);
136
137 smtc_smp_finish();
138#endif /* CONFIG_MIPS_MT_SMTC */
139}
140
141/*
142 * Hook for after all CPUs are online
143 */
144
145void prom_cpus_done(void)
146{
147#ifdef CONFIG_MIPS_MT_SMTC
148
149#endif /* CONFIG_MIPS_MT_SMTC */
150}
151#endif /* CONFIG_MIPS32R2_MT_SMP */
diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c
new file mode 100644
index 000000000000..18b968c696d1
--- /dev/null
+++ b/arch/mips/mips-boards/sim/sim_time.c
@@ -0,0 +1,215 @@
1#include <linux/types.h>
2#include <linux/config.h>
3#include <linux/init.h>
4#include <linux/kernel_stat.h>
5#include <linux/sched.h>
6#include <linux/spinlock.h>
7
8#include <asm/mipsregs.h>
9#include <asm/ptrace.h>
10#include <asm/hardirq.h>
11#include <asm/div64.h>
12#include <asm/cpu.h>
13#include <asm/time.h>
14
15#include <linux/interrupt.h>
16#include <linux/mc146818rtc.h>
17#include <linux/timex.h>
18#include <asm/mipsregs.h>
19#include <asm/ptrace.h>
20#include <asm/hardirq.h>
21#include <asm/irq.h>
22#include <asm/div64.h>
23#include <asm/cpu.h>
24#include <asm/time.h>
25#include <asm/mc146818-time.h>
26#include <asm/msc01_ic.h>
27
28#include <asm/mips-boards/generic.h>
29#include <asm/mips-boards/prom.h>
30#include <asm/mips-boards/simint.h>
31#include <asm/mc146818-time.h>
32#include <asm/smp.h>
33
34
35unsigned long cpu_khz;
36
37extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs);
38
39irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
40{
41#ifdef CONFIG_SMP
42 int cpu = smp_processor_id();
43
44 /*
45 * CPU 0 handles the global timer interrupt job
46 * resets count/compare registers to trigger next timer int.
47 */
48#ifndef CONFIG_MIPS_MT_SMTC
49 if (cpu == 0) {
50 timer_interrupt(irq, dev_id, regs);
51 }
52 else {
53 /* Everyone else needs to reset the timer int here as
54 ll_local_timer_interrupt doesn't */
55 /*
56 * FIXME: need to cope with counter underflow.
57 * More support needs to be added to kernel/time for
58 * counter/timer interrupts on multiple CPU's
59 */
60 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
61 }
62#else /* SMTC */
63 /*
64 * In SMTC system, one Count/Compare set exists per VPE.
65 * Which TC within a VPE gets the interrupt is essentially
66 * random - we only know that it shouldn't be one with
67 * IXMT set. Whichever TC gets the interrupt needs to
68 * send special interprocessor interrupts to the other
69 * TCs to make sure that they schedule, etc.
70 *
71 * That code is specific to the SMTC kernel, not to
72 * the simulation platform, so it's invoked from
73 * the general MIPS timer_interrupt routine.
74 *
75 * We have a problem in that the interrupt vector code
76 * had to turn off the timer IM bit to avoid redundant
77 * entries, but we may never get to mips_cpu_irq_end
78 * to turn it back on again if the scheduler gets
79 * involved. So we clear the pending timer here,
80 * and re-enable the mask...
81 */
82
83 int vpflags = dvpe();
84 write_c0_compare (read_c0_count() - 1);
85 clear_c0_cause(0x100 << MIPSCPU_INT_CPUCTR);
86 set_c0_status(0x100 << MIPSCPU_INT_CPUCTR);
87 irq_enable_hazard();
88 evpe(vpflags);
89
90 if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id, regs);
91 else write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
92 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
93
94#endif /* CONFIG_MIPS_MT_SMTC */
95
96 /*
97 * every CPU should do profiling and process accounting
98 */
99 local_timer_interrupt (irq, dev_id, regs);
100 return IRQ_HANDLED;
101#else
102 return timer_interrupt (irq, dev_id, regs);
103#endif
104}
105
106
107
108/*
109 * Estimate CPU frequency. Sets mips_counter_frequency as a side-effect
110 */
111static unsigned int __init estimate_cpu_frequency(void)
112{
113 unsigned int prid = read_c0_prid() & 0xffff00;
114 unsigned int count;
115
116#if 1
117 /*
118 * hardwire the board frequency to 12MHz.
119 */
120
121 if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
122 (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
123 count = 12000000;
124 else
125 count = 6000000;
126#else
127 unsigned int flags;
128
129 local_irq_save(flags);
130
131 /* Start counter exactly on falling edge of update flag */
132 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
133 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
134
135 /* Start r4k counter. */
136 write_c0_count(0);
137
138 /* Read counter exactly on falling edge of update flag */
139 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
140 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
141
142 count = read_c0_count();
143
144 /* restore interrupts */
145 local_irq_restore(flags);
146#endif
147
148 mips_hpt_frequency = count;
149
150 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
151 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
152 count *= 2;
153
154 count += 5000; /* round */
155 count -= count%10000;
156
157 return count;
158}
159
160void __init sim_time_init(void)
161{
162 unsigned int est_freq, flags;
163
164 local_irq_save(flags);
165
166
167 /* Set Data mode - binary. */
168 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
169
170
171 est_freq = estimate_cpu_frequency ();
172
173 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
174 (est_freq%1000000)*100/1000000);
175
176 cpu_khz = est_freq / 1000;
177
178 local_irq_restore(flags);
179}
180
181static int mips_cpu_timer_irq;
182
183static void mips_timer_dispatch (struct pt_regs *regs)
184{
185 do_IRQ (mips_cpu_timer_irq, regs);
186}
187
188
189void __init sim_timer_setup(struct irqaction *irq)
190{
191 if (cpu_has_veic) {
192 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
193 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
194 }
195 else {
196 if (cpu_has_vint)
197 set_vi_handler(MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
198 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
199 }
200
201 /* we are using the cpu counter for timer interrupts */
202 irq->handler = sim_timer_interrupt;
203 setup_irq(mips_cpu_timer_irq, irq);
204
205#ifdef CONFIG_SMP
206 /* irq_desc(riptor) is a global resource, when the interrupt overlaps
207 on seperate cpu's the first one tries to handle the second interrupt.
208 The effect is that the int remains disabled on the second cpu.
209 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
210 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
211#endif
212
213 /* to generate the first timer interrupt */
214 write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
215}
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index b56a0abdc3d4..b0178da019f0 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o
22obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 22obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
23obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 23obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
24obj-$(CONFIG_CPU_SB1) += c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \ 24obj-$(CONFIG_CPU_SB1) += c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \
25 tlb-sb1.o 25 tlb-r4k.o
26obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o 26obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o
27obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 27obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
28obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 28obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index c659f99eb39a..27f4fa25e8c9 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -221,12 +221,14 @@ static inline unsigned long get_phys_page (unsigned long addr,
221 struct mm_struct *mm) 221 struct mm_struct *mm)
222{ 222{
223 pgd_t *pgd; 223 pgd_t *pgd;
224 pud_t *pud;
224 pmd_t *pmd; 225 pmd_t *pmd;
225 pte_t *pte; 226 pte_t *pte;
226 unsigned long physpage; 227 unsigned long physpage;
227 228
228 pgd = pgd_offset(mm, addr); 229 pgd = pgd_offset(mm, addr);
229 pmd = pmd_offset(pgd, addr); 230 pud = pud_offset(pgd, addr);
231 pmd = pmd_offset(pud, addr);
230 pte = pte_offset(pmd, addr); 232 pte = pte_offset(pmd, addr);
231 233
232 if ((physpage = pte_val(*pte)) & _PAGE_VALID) 234 if ((physpage = pte_val(*pte)) & _PAGE_VALID)
@@ -317,7 +319,7 @@ static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
317 r3k_flush_dcache_range(start, start + size); 319 r3k_flush_dcache_range(start, start + size);
318} 320}
319 321
320void __init ld_mmu_r23000(void) 322void __init r3k_cache_init(void)
321{ 323{
322 extern void build_clear_page(void); 324 extern void build_clear_page(void);
323 extern void build_copy_page(void); 325 extern void build_copy_page(void);
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 5ea84bc98c6a..38223b44d962 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -16,6 +16,7 @@
16 16
17#include <asm/bcache.h> 17#include <asm/bcache.h>
18#include <asm/bootinfo.h> 18#include <asm/bootinfo.h>
19#include <asm/cache.h>
19#include <asm/cacheops.h> 20#include <asm/cacheops.h>
20#include <asm/cpu.h> 21#include <asm/cpu.h>
21#include <asm/cpu-features.h> 22#include <asm/cpu-features.h>
@@ -26,8 +27,14 @@
26#include <asm/system.h> 27#include <asm/system.h>
27#include <asm/mmu_context.h> 28#include <asm/mmu_context.h>
28#include <asm/war.h> 29#include <asm/war.h>
30#include <asm/cacheflush.h> /* for run_uncached() */
29 31
30static unsigned long icache_size, dcache_size, scache_size; 32/*
33 * Must die.
34 */
35static unsigned long icache_size __read_mostly;
36static unsigned long dcache_size __read_mostly;
37static unsigned long scache_size __read_mostly;
31 38
32/* 39/*
33 * Dummy cache handling routines for machines without boardcaches 40 * Dummy cache handling routines for machines without boardcaches
@@ -43,8 +50,8 @@ static struct bcache_ops no_sc_ops = {
43 50
44struct bcache_ops *bcops = &no_sc_ops; 51struct bcache_ops *bcops = &no_sc_ops;
45 52
46#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010) 53#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
47#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x2020) 54#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
48 55
49#define R4600_HIT_CACHEOP_WAR_IMPL \ 56#define R4600_HIT_CACHEOP_WAR_IMPL \
50do { \ 57do { \
@@ -190,12 +197,12 @@ static inline void r4k_blast_icache_page_indexed_setup(void)
190 if (ic_lsize == 16) 197 if (ic_lsize == 16)
191 r4k_blast_icache_page_indexed = blast_icache16_page_indexed; 198 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
192 else if (ic_lsize == 32) { 199 else if (ic_lsize == 32) {
193 if (TX49XX_ICACHE_INDEX_INV_WAR) 200 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
194 r4k_blast_icache_page_indexed =
195 tx49_blast_icache32_page_indexed;
196 else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
197 r4k_blast_icache_page_indexed = 201 r4k_blast_icache_page_indexed =
198 blast_icache32_r4600_v1_page_indexed; 202 blast_icache32_r4600_v1_page_indexed;
203 else if (TX49XX_ICACHE_INDEX_INV_WAR)
204 r4k_blast_icache_page_indexed =
205 tx49_blast_icache32_page_indexed;
199 else 206 else
200 r4k_blast_icache_page_indexed = 207 r4k_blast_icache_page_indexed =
201 blast_icache32_page_indexed; 208 blast_icache32_page_indexed;
@@ -361,24 +368,33 @@ static void r4k_flush_cache_mm(struct mm_struct *mm)
361 368
362struct flush_cache_page_args { 369struct flush_cache_page_args {
363 struct vm_area_struct *vma; 370 struct vm_area_struct *vma;
364 unsigned long page; 371 unsigned long addr;
365}; 372};
366 373
367static inline void local_r4k_flush_cache_page(void *args) 374static inline void local_r4k_flush_cache_page(void *args)
368{ 375{
369 struct flush_cache_page_args *fcp_args = args; 376 struct flush_cache_page_args *fcp_args = args;
370 struct vm_area_struct *vma = fcp_args->vma; 377 struct vm_area_struct *vma = fcp_args->vma;
371 unsigned long page = fcp_args->page; 378 unsigned long addr = fcp_args->addr;
372 int exec = vma->vm_flags & VM_EXEC; 379 int exec = vma->vm_flags & VM_EXEC;
373 struct mm_struct *mm = vma->vm_mm; 380 struct mm_struct *mm = vma->vm_mm;
374 pgd_t *pgdp; 381 pgd_t *pgdp;
382 pud_t *pudp;
375 pmd_t *pmdp; 383 pmd_t *pmdp;
376 pte_t *ptep; 384 pte_t *ptep;
377 385
378 page &= PAGE_MASK; 386 /*
379 pgdp = pgd_offset(mm, page); 387 * If ownes no valid ASID yet, cannot possibly have gotten
380 pmdp = pmd_offset(pgdp, page); 388 * this page into the cache.
381 ptep = pte_offset(pmdp, page); 389 */
390 if (cpu_context(smp_processor_id(), mm) == 0)
391 return;
392
393 addr &= PAGE_MASK;
394 pgdp = pgd_offset(mm, addr);
395 pudp = pud_offset(pgdp, addr);
396 pmdp = pmd_offset(pudp, addr);
397 ptep = pte_offset(pmdp, addr);
382 398
383 /* 399 /*
384 * If the page isn't marked valid, the page cannot possibly be 400 * If the page isn't marked valid, the page cannot possibly be
@@ -395,12 +411,12 @@ static inline void local_r4k_flush_cache_page(void *args)
395 */ 411 */
396 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { 412 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
397 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 413 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
398 r4k_blast_dcache_page(page); 414 r4k_blast_dcache_page(addr);
399 if (exec && !cpu_icache_snoops_remote_store) 415 if (exec && !cpu_icache_snoops_remote_store)
400 r4k_blast_scache_page(page); 416 r4k_blast_scache_page(addr);
401 } 417 }
402 if (exec) 418 if (exec)
403 r4k_blast_icache_page(page); 419 r4k_blast_icache_page(addr);
404 420
405 return; 421 return;
406 } 422 }
@@ -409,36 +425,30 @@ static inline void local_r4k_flush_cache_page(void *args)
409 * Do indexed flush, too much work to get the (possible) TLB refills 425 * Do indexed flush, too much work to get the (possible) TLB refills
410 * to work correctly. 426 * to work correctly.
411 */ 427 */
412 page = INDEX_BASE + (page & (dcache_size - 1)); 428 addr = INDEX_BASE + (addr & (dcache_size - 1));
413 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 429 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
414 r4k_blast_dcache_page_indexed(page); 430 r4k_blast_dcache_page_indexed(addr);
415 if (exec && !cpu_icache_snoops_remote_store) 431 if (exec && !cpu_icache_snoops_remote_store)
416 r4k_blast_scache_page_indexed(page); 432 r4k_blast_scache_page_indexed(addr);
417 } 433 }
418 if (exec) { 434 if (exec) {
419 if (cpu_has_vtag_icache) { 435 if (cpu_has_vtag_icache) {
420 int cpu = smp_processor_id(); 436 int cpu = smp_processor_id();
421 437
422 if (cpu_context(cpu, vma->vm_mm) != 0) 438 if (cpu_context(cpu, mm) != 0)
423 drop_mmu_context(vma->vm_mm, cpu); 439 drop_mmu_context(mm, cpu);
424 } else 440 } else
425 r4k_blast_icache_page_indexed(page); 441 r4k_blast_icache_page_indexed(addr);
426 } 442 }
427} 443}
428 444
429static void r4k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn) 445static void r4k_flush_cache_page(struct vm_area_struct *vma,
446 unsigned long addr, unsigned long pfn)
430{ 447{
431 struct flush_cache_page_args args; 448 struct flush_cache_page_args args;
432 449
433 /*
434 * If ownes no valid ASID yet, cannot possibly have gotten
435 * this page into the cache.
436 */
437 if (cpu_context(smp_processor_id(), vma->vm_mm) == 0)
438 return;
439
440 args.vma = vma; 450 args.vma = vma;
441 args.page = page; 451 args.addr = addr;
442 452
443 on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); 453 on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
444} 454}
@@ -454,16 +464,16 @@ static void r4k_flush_data_cache_page(unsigned long addr)
454} 464}
455 465
456struct flush_icache_range_args { 466struct flush_icache_range_args {
457 unsigned long start; 467 unsigned long __user start;
458 unsigned long end; 468 unsigned long __user end;
459}; 469};
460 470
461static inline void local_r4k_flush_icache_range(void *args) 471static inline void local_r4k_flush_icache_range(void *args)
462{ 472{
463 struct flush_icache_range_args *fir_args = args; 473 struct flush_icache_range_args *fir_args = args;
464 unsigned long dc_lsize = current_cpu_data.dcache.linesz; 474 unsigned long dc_lsize = cpu_dcache_line_size();
465 unsigned long ic_lsize = current_cpu_data.icache.linesz; 475 unsigned long ic_lsize = cpu_icache_line_size();
466 unsigned long sc_lsize = current_cpu_data.scache.linesz; 476 unsigned long sc_lsize = cpu_scache_line_size();
467 unsigned long start = fir_args->start; 477 unsigned long start = fir_args->start;
468 unsigned long end = fir_args->end; 478 unsigned long end = fir_args->end;
469 unsigned long addr, aend; 479 unsigned long addr, aend;
@@ -472,6 +482,7 @@ static inline void local_r4k_flush_icache_range(void *args)
472 if (end - start > dcache_size) { 482 if (end - start > dcache_size) {
473 r4k_blast_dcache(); 483 r4k_blast_dcache();
474 } else { 484 } else {
485 R4600_HIT_CACHEOP_WAR_IMPL;
475 addr = start & ~(dc_lsize - 1); 486 addr = start & ~(dc_lsize - 1);
476 aend = (end - 1) & ~(dc_lsize - 1); 487 aend = (end - 1) & ~(dc_lsize - 1);
477 488
@@ -492,7 +503,7 @@ static inline void local_r4k_flush_icache_range(void *args)
492 aend = (end - 1) & ~(sc_lsize - 1); 503 aend = (end - 1) & ~(sc_lsize - 1);
493 504
494 while (1) { 505 while (1) {
495 /* Hit_Writeback_Inv_D */ 506 /* Hit_Writeback_Inv_SD */
496 protected_writeback_scache_line(addr); 507 protected_writeback_scache_line(addr);
497 if (addr == aend) 508 if (addr == aend)
498 break; 509 break;
@@ -517,7 +528,8 @@ static inline void local_r4k_flush_icache_range(void *args)
517 } 528 }
518} 529}
519 530
520static void r4k_flush_icache_range(unsigned long start, unsigned long end) 531static void r4k_flush_icache_range(unsigned long __user start,
532 unsigned long __user end)
521{ 533{
522 struct flush_icache_range_args args; 534 struct flush_icache_range_args args;
523 535
@@ -525,6 +537,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
525 args.end = end; 537 args.end = end;
526 538
527 on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); 539 on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
540 instruction_hazard();
528} 541}
529 542
530/* 543/*
@@ -613,7 +626,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
613 BUG_ON(size == 0); 626 BUG_ON(size == 0);
614 627
615 if (cpu_has_subset_pcaches) { 628 if (cpu_has_subset_pcaches) {
616 unsigned long sc_lsize = current_cpu_data.scache.linesz; 629 unsigned long sc_lsize = cpu_scache_line_size();
617 630
618 if (size >= scache_size) { 631 if (size >= scache_size) {
619 r4k_blast_scache(); 632 r4k_blast_scache();
@@ -639,7 +652,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
639 if (size >= dcache_size) { 652 if (size >= dcache_size) {
640 r4k_blast_dcache(); 653 r4k_blast_dcache();
641 } else { 654 } else {
642 unsigned long dc_lsize = current_cpu_data.dcache.linesz; 655 unsigned long dc_lsize = cpu_dcache_line_size();
643 656
644 R4600_HIT_CACHEOP_WAR_IMPL; 657 R4600_HIT_CACHEOP_WAR_IMPL;
645 a = addr & ~(dc_lsize - 1); 658 a = addr & ~(dc_lsize - 1);
@@ -663,7 +676,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
663 BUG_ON(size == 0); 676 BUG_ON(size == 0);
664 677
665 if (cpu_has_subset_pcaches) { 678 if (cpu_has_subset_pcaches) {
666 unsigned long sc_lsize = current_cpu_data.scache.linesz; 679 unsigned long sc_lsize = cpu_scache_line_size();
667 680
668 if (size >= scache_size) { 681 if (size >= scache_size) {
669 r4k_blast_scache(); 682 r4k_blast_scache();
@@ -684,7 +697,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
684 if (size >= dcache_size) { 697 if (size >= dcache_size) {
685 r4k_blast_dcache(); 698 r4k_blast_dcache();
686 } else { 699 } else {
687 unsigned long dc_lsize = current_cpu_data.dcache.linesz; 700 unsigned long dc_lsize = cpu_dcache_line_size();
688 701
689 R4600_HIT_CACHEOP_WAR_IMPL; 702 R4600_HIT_CACHEOP_WAR_IMPL;
690 a = addr & ~(dc_lsize - 1); 703 a = addr & ~(dc_lsize - 1);
@@ -708,9 +721,9 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
708 */ 721 */
709static void local_r4k_flush_cache_sigtramp(void * arg) 722static void local_r4k_flush_cache_sigtramp(void * arg)
710{ 723{
711 unsigned long ic_lsize = current_cpu_data.icache.linesz; 724 unsigned long ic_lsize = cpu_icache_line_size();
712 unsigned long dc_lsize = current_cpu_data.dcache.linesz; 725 unsigned long dc_lsize = cpu_dcache_line_size();
713 unsigned long sc_lsize = current_cpu_data.scache.linesz; 726 unsigned long sc_lsize = cpu_scache_line_size();
714 unsigned long addr = (unsigned long) arg; 727 unsigned long addr = (unsigned long) arg;
715 728
716 R4600_HIT_CACHEOP_WAR_IMPL; 729 R4600_HIT_CACHEOP_WAR_IMPL;
@@ -762,6 +775,7 @@ static inline void rm7k_erratum31(void)
762 775
763 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { 776 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
764 __asm__ __volatile__ ( 777 __asm__ __volatile__ (
778 ".set push\n\t"
765 ".set noreorder\n\t" 779 ".set noreorder\n\t"
766 ".set mips3\n\t" 780 ".set mips3\n\t"
767 "cache\t%1, 0(%0)\n\t" 781 "cache\t%1, 0(%0)\n\t"
@@ -776,8 +790,7 @@ static inline void rm7k_erratum31(void)
776 "cache\t%1, 0x1000(%0)\n\t" 790 "cache\t%1, 0x1000(%0)\n\t"
777 "cache\t%1, 0x2000(%0)\n\t" 791 "cache\t%1, 0x2000(%0)\n\t"
778 "cache\t%1, 0x3000(%0)\n\t" 792 "cache\t%1, 0x3000(%0)\n\t"
779 ".set\tmips0\n\t" 793 ".set pop\n"
780 ".set\treorder\n\t"
781 : 794 :
782 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); 795 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
783 } 796 }
@@ -1011,9 +1024,19 @@ static void __init probe_pcache(void)
1011 * normally they'd suffer from aliases but magic in the hardware deals 1024 * normally they'd suffer from aliases but magic in the hardware deals
1012 * with that for us so we don't need to take care ourselves. 1025 * with that for us so we don't need to take care ourselves.
1013 */ 1026 */
1014 if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000) 1027 switch (c->cputype) {
1015 if (c->dcache.waysize > PAGE_SIZE) 1028 case CPU_20KC:
1016 c->dcache.flags |= MIPS_CACHE_ALIASES; 1029 case CPU_25KF:
1030 case CPU_R10000:
1031 case CPU_R12000:
1032 case CPU_SB1:
1033 break;
1034 case CPU_24K:
1035 if (!(read_c0_config7() & (1 << 16)))
1036 default:
1037 if (c->dcache.waysize > PAGE_SIZE)
1038 c->dcache.flags |= MIPS_CACHE_ALIASES;
1039 }
1017 1040
1018 switch (c->cputype) { 1041 switch (c->cputype) {
1019 case CPU_20KC: 1042 case CPU_20KC:
@@ -1024,7 +1047,11 @@ static void __init probe_pcache(void)
1024 c->icache.flags |= MIPS_CACHE_VTAG; 1047 c->icache.flags |= MIPS_CACHE_VTAG;
1025 break; 1048 break;
1026 1049
1050 case CPU_AU1000:
1027 case CPU_AU1500: 1051 case CPU_AU1500:
1052 case CPU_AU1100:
1053 case CPU_AU1550:
1054 case CPU_AU1200:
1028 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1055 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1029 break; 1056 break;
1030 } 1057 }
@@ -1102,7 +1129,6 @@ static int __init probe_scache(void)
1102 return 1; 1129 return 1;
1103} 1130}
1104 1131
1105typedef int (*probe_func_t)(unsigned long);
1106extern int r5k_sc_init(void); 1132extern int r5k_sc_init(void);
1107extern int rm7k_sc_init(void); 1133extern int rm7k_sc_init(void);
1108 1134
@@ -1110,7 +1136,6 @@ static void __init setup_scache(void)
1110{ 1136{
1111 struct cpuinfo_mips *c = &current_cpu_data; 1137 struct cpuinfo_mips *c = &current_cpu_data;
1112 unsigned int config = read_c0_config(); 1138 unsigned int config = read_c0_config();
1113 probe_func_t probe_scache_kseg1;
1114 int sc_present = 0; 1139 int sc_present = 0;
1115 1140
1116 /* 1141 /*
@@ -1123,8 +1148,7 @@ static void __init setup_scache(void)
1123 case CPU_R4000MC: 1148 case CPU_R4000MC:
1124 case CPU_R4400SC: 1149 case CPU_R4400SC:
1125 case CPU_R4400MC: 1150 case CPU_R4400MC:
1126 probe_scache_kseg1 = (probe_func_t) (CKSEG1ADDR(&probe_scache)); 1151 sc_present = run_uncached(probe_scache);
1127 sc_present = probe_scache_kseg1(config);
1128 if (sc_present) 1152 if (sc_present)
1129 c->options |= MIPS_CPU_CACHE_CDEX_S; 1153 c->options |= MIPS_CPU_CACHE_CDEX_S;
1130 break; 1154 break;
@@ -1198,7 +1222,7 @@ static inline void coherency_setup(void)
1198 } 1222 }
1199} 1223}
1200 1224
1201void __init ld_mmu_r4xx0(void) 1225void __init r4k_cache_init(void)
1202{ 1226{
1203 extern void build_clear_page(void); 1227 extern void build_clear_page(void);
1204 extern void build_copy_page(void); 1228 extern void build_copy_page(void);
@@ -1206,15 +1230,11 @@ void __init ld_mmu_r4xx0(void)
1206 struct cpuinfo_mips *c = &current_cpu_data; 1230 struct cpuinfo_mips *c = &current_cpu_data;
1207 1231
1208 /* Default cache error handler for R4000 and R5000 family */ 1232 /* Default cache error handler for R4000 and R5000 family */
1209 memcpy((void *)(CAC_BASE + 0x100), &except_vec2_generic, 0x80); 1233 set_uncached_handler (0x100, &except_vec2_generic, 0x80);
1210 memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
1211 1234
1212 probe_pcache(); 1235 probe_pcache();
1213 setup_scache(); 1236 setup_scache();
1214 1237
1215 if (c->dcache.sets * c->dcache.ways > PAGE_SIZE)
1216 c->dcache.flags |= MIPS_CACHE_ALIASES;
1217
1218 r4k_blast_dcache_page_setup(); 1238 r4k_blast_dcache_page_setup();
1219 r4k_blast_dcache_page_indexed_setup(); 1239 r4k_blast_dcache_page_indexed_setup();
1220 r4k_blast_dcache_setup(); 1240 r4k_blast_dcache_setup();
@@ -1252,9 +1272,8 @@ void __init ld_mmu_r4xx0(void)
1252 _dma_cache_inv = r4k_dma_cache_inv; 1272 _dma_cache_inv = r4k_dma_cache_inv;
1253#endif 1273#endif
1254 1274
1255 __flush_cache_all();
1256 coherency_setup();
1257
1258 build_clear_page(); 1275 build_clear_page();
1259 build_copy_page(); 1276 build_copy_page();
1277 local_r4k___flush_cache_all(NULL);
1278 coherency_setup();
1260} 1279}
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index 502f68c664b2..2f08b535f20e 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -235,7 +235,7 @@ static inline void __sb1_flush_icache_range(unsigned long start,
235/* 235/*
236 * Invalidate all caches on this CPU 236 * Invalidate all caches on this CPU
237 */ 237 */
238static void local_sb1___flush_cache_all(void) 238static void __attribute_used__ local_sb1___flush_cache_all(void)
239{ 239{
240 __sb1_writeback_inv_dcache_all(); 240 __sb1_writeback_inv_dcache_all();
241 __sb1_flush_icache_all(); 241 __sb1_flush_icache_all();
@@ -492,19 +492,17 @@ static __init void probe_cache_sizes(void)
492} 492}
493 493
494/* 494/*
495 * This is called from loadmmu.c. We have to set up all the 495 * This is called from cache.c. We have to set up all the
496 * memory management function pointers, as well as initialize 496 * memory management function pointers, as well as initialize
497 * the caches and tlbs 497 * the caches and tlbs
498 */ 498 */
499void ld_mmu_sb1(void) 499void sb1_cache_init(void)
500{ 500{
501 extern char except_vec2_sb1; 501 extern char except_vec2_sb1;
502 extern char handle_vec2_sb1; 502 extern char handle_vec2_sb1;
503 503
504 /* Special cache error handler for SB1 */ 504 /* Special cache error handler for SB1 */
505 memcpy((void *)(CAC_BASE + 0x100), &except_vec2_sb1, 0x80); 505 set_uncached_handler (0x100, &except_vec2_sb1, 0x80);
506 memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_sb1, 0x80);
507 memcpy((void *)CKSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80);
508 506
509 probe_cache_sizes(); 507 probe_cache_sizes();
510 508
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index ff5afab64b2f..0a97a9434eba 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -167,15 +167,16 @@ static void tx39_flush_cache_mm(struct mm_struct *mm)
167static void tx39_flush_cache_range(struct vm_area_struct *vma, 167static void tx39_flush_cache_range(struct vm_area_struct *vma,
168 unsigned long start, unsigned long end) 168 unsigned long start, unsigned long end)
169{ 169{
170 struct mm_struct *mm = vma->vm_mm; 170 int exec;
171 171
172 if (!cpu_has_dc_aliases) 172 if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
173 return; 173 return;
174 174
175 if (cpu_context(smp_processor_id(), mm) != 0) { 175 exec = vma->vm_flags & VM_EXEC;
176 if (cpu_has_dc_aliases || exec)
176 tx39_blast_dcache(); 177 tx39_blast_dcache();
178 if (exec)
177 tx39_blast_icache(); 179 tx39_blast_icache();
178 }
179} 180}
180 181
181static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn) 182static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
@@ -183,6 +184,7 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
183 int exec = vma->vm_flags & VM_EXEC; 184 int exec = vma->vm_flags & VM_EXEC;
184 struct mm_struct *mm = vma->vm_mm; 185 struct mm_struct *mm = vma->vm_mm;
185 pgd_t *pgdp; 186 pgd_t *pgdp;
187 pud_t *pudp;
186 pmd_t *pmdp; 188 pmd_t *pmdp;
187 pte_t *ptep; 189 pte_t *ptep;
188 190
@@ -195,7 +197,8 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
195 197
196 page &= PAGE_MASK; 198 page &= PAGE_MASK;
197 pgdp = pgd_offset(mm, page); 199 pgdp = pgd_offset(mm, page);
198 pmdp = pmd_offset(pgdp, page); 200 pudp = pud_offset(pgdp, page);
201 pmdp = pmd_offset(pudp, page);
199 ptep = pte_offset(pmdp, page); 202 ptep = pte_offset(pmdp, page);
200 203
201 /* 204 /*
@@ -407,7 +410,7 @@ static __init void tx39_probe_cache(void)
407 } 410 }
408} 411}
409 412
410void __init ld_mmu_tx39(void) 413void __init tx39_cache_init(void)
411{ 414{
412 extern void build_clear_page(void); 415 extern void build_clear_page(void);
413 extern void build_copy_page(void); 416 extern void build_copy_page(void);
@@ -490,4 +493,5 @@ void __init ld_mmu_tx39(void)
490 493
491 build_clear_page(); 494 build_clear_page();
492 build_copy_page(); 495 build_copy_page();
496 tx39h_flush_icache_all();
493} 497}
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 1d95cdb77bed..314701a66b13 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -23,8 +23,10 @@ void (*__flush_cache_all)(void);
23void (*flush_cache_mm)(struct mm_struct *mm); 23void (*flush_cache_mm)(struct mm_struct *mm);
24void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, 24void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
25 unsigned long end); 25 unsigned long end);
26void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); 26void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
27void (*flush_icache_range)(unsigned long start, unsigned long end); 27 unsigned long pfn);
28void (*flush_icache_range)(unsigned long __user start,
29 unsigned long __user end);
28void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); 30void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page);
29 31
30/* MIPS specific cache operations */ 32/* MIPS specific cache operations */
@@ -32,6 +34,8 @@ void (*flush_cache_sigtramp)(unsigned long addr);
32void (*flush_data_cache_page)(unsigned long addr); 34void (*flush_data_cache_page)(unsigned long addr);
33void (*flush_icache_all)(void); 35void (*flush_icache_all)(void);
34 36
37EXPORT_SYMBOL(flush_data_cache_page);
38
35#ifdef CONFIG_DMA_NONCOHERENT 39#ifdef CONFIG_DMA_NONCOHERENT
36 40
37/* DMA cache operations. */ 41/* DMA cache operations. */
@@ -49,10 +53,12 @@ EXPORT_SYMBOL(_dma_cache_inv);
49 * We could optimize the case where the cache argument is not BCACHE but 53 * We could optimize the case where the cache argument is not BCACHE but
50 * that seems very atypical use ... 54 * that seems very atypical use ...
51 */ 55 */
52asmlinkage int sys_cacheflush(unsigned long addr, unsigned long int bytes, 56asmlinkage int sys_cacheflush(unsigned long __user addr,
53 unsigned int cache) 57 unsigned long bytes, unsigned int cache)
54{ 58{
55 if (!access_ok(VERIFY_WRITE, (void *) addr, bytes)) 59 if (bytes == 0)
60 return 0;
61 if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes))
56 return -EFAULT; 62 return -EFAULT;
57 63
58 flush_icache_range(addr, addr + bytes); 64 flush_icache_range(addr, addr + bytes);
@@ -100,58 +106,48 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address,
100 } 106 }
101} 107}
102 108
103extern void ld_mmu_r23000(void); 109#define __weak __attribute__((weak))
104extern void ld_mmu_r4xx0(void); 110
105extern void ld_mmu_tx39(void); 111static char cache_panic[] __initdata = "Yeee, unsupported cache architecture.";
106extern void ld_mmu_r6000(void);
107extern void ld_mmu_tfp(void);
108extern void ld_mmu_andes(void);
109extern void ld_mmu_sb1(void);
110 112
111void __init cpu_cache_init(void) 113void __init cpu_cache_init(void)
112{ 114{
113 if (cpu_has_4ktlb) { 115 if (cpu_has_3k_cache) {
114#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \ 116 extern void __weak r3k_cache_init(void);
115 defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \ 117
116 defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \ 118 r3k_cache_init();
117 defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32) || \ 119 return;
118 defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \ 120 }
119 defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000) 121 if (cpu_has_6k_cache) {
120 ld_mmu_r4xx0(); 122 extern void __weak r6k_cache_init(void);
121#endif 123
122 } else switch (current_cpu_data.cputype) { 124 r6k_cache_init();
123#ifdef CONFIG_CPU_R3000 125 return;
124 case CPU_R2000: 126 }
125 case CPU_R3000: 127 if (cpu_has_4k_cache) {
126 case CPU_R3000A: 128 extern void __weak r4k_cache_init(void);
127 case CPU_R3081E: 129
128 ld_mmu_r23000(); 130 r4k_cache_init();
129 break; 131 return;
130#endif
131#ifdef CONFIG_CPU_TX39XX
132 case CPU_TX3912:
133 case CPU_TX3922:
134 case CPU_TX3927:
135 ld_mmu_tx39();
136 break;
137#endif
138#ifdef CONFIG_CPU_R10000
139 case CPU_R10000:
140 case CPU_R12000:
141 ld_mmu_r4xx0();
142 break;
143#endif
144#ifdef CONFIG_CPU_SB1
145 case CPU_SB1:
146 ld_mmu_sb1();
147 break;
148#endif
149
150 case CPU_R8000:
151 panic("R8000 is unsupported");
152 break;
153
154 default:
155 panic("Yeee, unsupported cache architecture.");
156 } 132 }
133 if (cpu_has_8k_cache) {
134 extern void __weak r8k_cache_init(void);
135
136 r8k_cache_init();
137 return;
138 }
139 if (cpu_has_tx39_cache) {
140 extern void __weak tx39_cache_init(void);
141
142 tx39_cache_init();
143 return;
144 }
145 if (cpu_has_sb1_cache) {
146 extern void __weak sb1_cache_init(void);
147
148 sb1_cache_init();
149 return;
150 }
151
152 panic(cache_panic);
157} 153}
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 7166ffe63502..1cf3c6006ccd 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -19,13 +19,19 @@
19#include <linux/sched.h> 19#include <linux/sched.h>
20#include <asm/mipsregs.h> 20#include <asm/mipsregs.h>
21#include <asm/sibyte/sb1250.h> 21#include <asm/sibyte/sb1250.h>
22#include <asm/sibyte/sb1250_regs.h>
22 23
23#ifndef CONFIG_SIBYTE_BUS_WATCHER 24#if !defined(CONFIG_SIBYTE_BUS_WATCHER) || defined(CONFIG_SIBYTE_BW_TRACE)
24#include <asm/io.h> 25#include <asm/io.h>
25#include <asm/sibyte/sb1250_regs.h>
26#include <asm/sibyte/sb1250_scd.h> 26#include <asm/sibyte/sb1250_scd.h>
27#endif 27#endif
28 28
29/*
30 * We'd like to dump the L2_ECC_TAG register on errors, but errata make
31 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
32 */
33#undef DUMP_L2_ECC_TAG_ON_ERROR
34
29/* SB1 definitions */ 35/* SB1 definitions */
30 36
31/* XXX should come from config1 XXX */ 37/* XXX should come from config1 XXX */
@@ -139,12 +145,18 @@ static inline void breakout_cerrd(unsigned int val)
139static void check_bus_watcher(void) 145static void check_bus_watcher(void)
140{ 146{
141 uint32_t status, l2_err, memio_err; 147 uint32_t status, l2_err, memio_err;
148#ifdef DUMP_L2_ECC_TAG_ON_ERROR
149 uint64_t l2_tag;
150#endif
142 151
143 /* Destructive read, clears register and interrupt */ 152 /* Destructive read, clears register and interrupt */
144 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); 153 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
145 /* Bit 31 is always on, but there's no #define for that */ 154 /* Bit 31 is always on, but there's no #define for that */
146 if (status & ~(1UL << 31)) { 155 if (status & ~(1UL << 31)) {
147 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); 156 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
157#ifdef DUMP_L2_ECC_TAG_ON_ERROR
158 l2_tag = in64(IO_SPACE_BASE | A_L2_ECC_TAG);
159#endif
148 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); 160 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
149 prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); 161 prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
150 prom_printf("\nLast recorded signature:\n"); 162 prom_printf("\nLast recorded signature:\n");
@@ -153,6 +165,9 @@ static void check_bus_watcher(void)
153 (int)(G_SCD_BERR_TID(status) >> 6), 165 (int)(G_SCD_BERR_TID(status) >> 6),
154 (int)G_SCD_BERR_RID(status), 166 (int)G_SCD_BERR_RID(status),
155 (int)G_SCD_BERR_DCODE(status)); 167 (int)G_SCD_BERR_DCODE(status));
168#ifdef DUMP_L2_ECC_TAG_ON_ERROR
169 prom_printf("Last L2 tag w/ bad ECC: %016llx\n", l2_tag);
170#endif
156 } else { 171 } else {
157 prom_printf("Bus watcher indicates no error\n"); 172 prom_printf("Bus watcher indicates no error\n");
158 } 173 }
@@ -166,6 +181,16 @@ asmlinkage void sb1_cache_error(void)
166 uint64_t cerr_dpa; 181 uint64_t cerr_dpa;
167 uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res; 182 uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res;
168 183
184#ifdef CONFIG_SIBYTE_BW_TRACE
185 /* Freeze the trace buffer now */
186#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
187 csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG);
188#else
189 csr_out32(M_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG);
190#endif
191 prom_printf("Trace buffer frozen\n");
192#endif
193
169 prom_printf("Cache error exception on CPU %x:\n", 194 prom_printf("Cache error exception on CPU %x:\n",
170 (read_c0_prid() >> 25) & 0x7); 195 (read_c0_prid() >> 25) & 0x7);
171 196
@@ -229,11 +254,19 @@ asmlinkage void sb1_cache_error(void)
229 254
230 check_bus_watcher(); 255 check_bus_watcher();
231 256
232 while (1);
233 /* 257 /*
234 * This tends to make things get really ugly; let's just stall instead. 258 * Calling panic() when a fatal cache error occurs scrambles the
235 * panic("Can't handle the cache error!"); 259 * state of the system (and the cache), making it difficult to
260 * investigate after the fact. However, if you just stall the CPU,
261 * the other CPU may keep on running, which is typically very
262 * undesirable.
236 */ 263 */
264#ifdef CONFIG_SB1_CERR_STALL
265 while (1)
266 ;
267#else
268 panic("unhandled cache error");
269#endif
237} 270}
238 271
239 272
@@ -434,7 +467,8 @@ static struct dc_state dc_states[] = {
434}; 467};
435 468
436#define DC_TAG_VALID(state) \ 469#define DC_TAG_VALID(state) \
437 (((state) == 0xf) || ((state) == 0x13) || ((state) == 0x19) || ((state == 0x16)) || ((state) == 0x1c)) 470 (((state) == 0x0) || ((state) == 0xf) || ((state) == 0x13) || \
471 ((state) == 0x19) || ((state) == 0x16) || ((state) == 0x1c))
438 472
439static char *dc_state_str(unsigned char state) 473static char *dc_state_str(unsigned char state)
440{ 474{
@@ -505,6 +539,7 @@ static uint32_t extract_dc(unsigned short addr, int data)
505 uint64_t datalo; 539 uint64_t datalo;
506 uint32_t datalohi, datalolo, datahi; 540 uint32_t datalohi, datalolo, datahi;
507 int offset; 541 int offset;
542 char bad_ecc = 0;
508 543
509 for (offset = 0; offset < 4; offset++) { 544 for (offset = 0; offset < 4; offset++) {
510 /* Index-load-data-D */ 545 /* Index-load-data-D */
@@ -525,8 +560,7 @@ static uint32_t extract_dc(unsigned short addr, int data)
525 ecc = dc_ecc(datalo); 560 ecc = dc_ecc(datalo);
526 if (ecc != datahi) { 561 if (ecc != datahi) {
527 int bits = 0; 562 int bits = 0;
528 prom_printf(" ** bad ECC (%02x %02x) ->", 563 bad_ecc |= 1 << (3-offset);
529 datahi, ecc);
530 ecc ^= datahi; 564 ecc ^= datahi;
531 while (ecc) { 565 while (ecc) {
532 if (ecc & 1) bits++; 566 if (ecc & 1) bits++;
@@ -537,6 +571,10 @@ static uint32_t extract_dc(unsigned short addr, int data)
537 prom_printf(" %02X-%016llX", datahi, datalo); 571 prom_printf(" %02X-%016llX", datahi, datalo);
538 } 572 }
539 prom_printf("\n"); 573 prom_printf("\n");
574 if (bad_ecc)
575 prom_printf(" dwords w/ bad ECC: %d %d %d %d\n",
576 !!(bad_ecc & 8), !!(bad_ecc & 4),
577 !!(bad_ecc & 2), !!(bad_ecc & 1));
540 } 578 }
541 } 579 }
542 return res; 580 return res;
diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S
index 2c3a23aa88c3..0e71580774ff 100644
--- a/arch/mips/mm/cex-sb1.S
+++ b/arch/mips/mm/cex-sb1.S
@@ -64,6 +64,10 @@ LEAF(except_vec2_sb1)
64 sd k0,0x170($0) 64 sd k0,0x170($0)
65 sd k1,0x178($0) 65 sd k1,0x178($0)
66 66
67#if CONFIG_SB1_CEX_ALWAYS_FATAL
68 j handle_vec2_sb1
69 nop
70#else
67 /* 71 /*
68 * M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell 72 * M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell
69 * if we can fast-path out of here for a h/w-recovered error. 73 * if we can fast-path out of here for a h/w-recovered error.
@@ -134,6 +138,7 @@ unrecoverable:
134 /* Unrecoverable Icache or Dcache error; log it and/or fail */ 138 /* Unrecoverable Icache or Dcache error; log it and/or fail */
135 j handle_vec2_sb1 139 j handle_vec2_sb1
136 nop 140 nop
141#endif
137 142
138END(except_vec2_sb1) 143END(except_vec2_sb1)
139 144
diff --git a/arch/mips/mm/dma-coherent.c b/arch/mips/mm/dma-coherent.c
index a617f8c327e8..f6b3c722230c 100644
--- a/arch/mips/mm/dma-coherent.c
+++ b/arch/mips/mm/dma-coherent.c
@@ -9,10 +9,10 @@
9 */ 9 */
10#include <linux/config.h> 10#include <linux/config.h>
11#include <linux/types.h> 11#include <linux/types.h>
12#include <linux/dma-mapping.h>
12#include <linux/mm.h> 13#include <linux/mm.h>
13#include <linux/module.h> 14#include <linux/module.h>
14#include <linux/string.h> 15#include <linux/string.h>
15#include <linux/pci.h>
16 16
17#include <asm/cache.h> 17#include <asm/cache.h>
18#include <asm/io.h> 18#include <asm/io.h>
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 4ce02028a292..cd4ea8474f89 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -105,22 +105,7 @@ dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
105{ 105{
106 unsigned long addr = (unsigned long) ptr; 106 unsigned long addr = (unsigned long) ptr;
107 107
108 switch (direction) { 108 __dma_sync(addr, size, direction);
109 case DMA_TO_DEVICE:
110 dma_cache_wback(addr, size);
111 break;
112
113 case DMA_FROM_DEVICE:
114 dma_cache_inv(addr, size);
115 break;
116
117 case DMA_BIDIRECTIONAL:
118 dma_cache_wback_inv(addr, size);
119 break;
120
121 default:
122 BUG();
123 }
124 109
125 return virt_to_phys(ptr); 110 return virt_to_phys(ptr);
126} 111}
@@ -133,22 +118,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
133 unsigned long addr; 118 unsigned long addr;
134 addr = dma_addr + PAGE_OFFSET; 119 addr = dma_addr + PAGE_OFFSET;
135 120
136 switch (direction) { 121 //__dma_sync(addr, size, direction);
137 case DMA_TO_DEVICE:
138 //dma_cache_wback(addr, size);
139 break;
140
141 case DMA_FROM_DEVICE:
142 //dma_cache_inv(addr, size);
143 break;
144
145 case DMA_BIDIRECTIONAL:
146 //dma_cache_wback_inv(addr, size);
147 break;
148
149 default:
150 BUG();
151 }
152} 122}
153 123
154EXPORT_SYMBOL(dma_unmap_single); 124EXPORT_SYMBOL(dma_unmap_single);
@@ -164,10 +134,11 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
164 unsigned long addr; 134 unsigned long addr;
165 135
166 addr = (unsigned long) page_address(sg->page); 136 addr = (unsigned long) page_address(sg->page);
167 if (addr) 137 if (addr) {
168 __dma_sync(addr + sg->offset, sg->length, direction); 138 __dma_sync(addr + sg->offset, sg->length, direction);
169 sg->dma_address = (dma_addr_t) 139 sg->dma_address = (dma_addr_t)page_to_phys(sg->page)
170 (page_to_phys(sg->page) + sg->offset); 140 + sg->offset;
141 }
171 } 142 }
172 143
173 return nents; 144 return nents;
@@ -218,9 +189,8 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
218 189
219 for (i = 0; i < nhwentries; i++, sg++) { 190 for (i = 0; i < nhwentries; i++, sg++) {
220 addr = (unsigned long) page_address(sg->page); 191 addr = (unsigned long) page_address(sg->page);
221 if (!addr) 192 if (addr)
222 continue; 193 __dma_sync(addr + sg->offset, sg->length, direction);
223 dma_cache_wback_inv(addr + sg->offset, sg->length);
224 } 194 }
225} 195}
226 196
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index ec8077c74e9c..2d9624fd10ec 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -25,6 +25,7 @@
25#include <asm/system.h> 25#include <asm/system.h>
26#include <asm/uaccess.h> 26#include <asm/uaccess.h>
27#include <asm/ptrace.h> 27#include <asm/ptrace.h>
28#include <asm/highmem.h> /* For VMALLOC_END */
28 29
29/* 30/*
30 * This routine handles page faults. It determines the address, 31 * This routine handles page faults. It determines the address,
@@ -57,7 +58,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
57 * only copy the information from the master page table, 58 * only copy the information from the master page table,
58 * nothing more. 59 * nothing more.
59 */ 60 */
60 if (unlikely(address >= VMALLOC_START)) 61 if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END))
61 goto vmalloc_fault; 62 goto vmalloc_fault;
62 63
63 /* 64 /*
@@ -140,7 +141,7 @@ bad_area_nosemaphore:
140 info.si_signo = SIGSEGV; 141 info.si_signo = SIGSEGV;
141 info.si_errno = 0; 142 info.si_errno = 0;
142 /* info.si_code has been set above */ 143 /* info.si_code has been set above */
143 info.si_addr = (void *) address; 144 info.si_addr = (void __user *) address;
144 force_sig_info(SIGSEGV, &info, tsk); 145 force_sig_info(SIGSEGV, &info, tsk);
145 return; 146 return;
146 } 147 }
@@ -196,7 +197,7 @@ do_sigbus:
196 info.si_signo = SIGBUS; 197 info.si_signo = SIGBUS;
197 info.si_errno = 0; 198 info.si_errno = 0;
198 info.si_code = BUS_ADRERR; 199 info.si_code = BUS_ADRERR;
199 info.si_addr = (void *) address; 200 info.si_addr = (void __user *) address;
200 force_sig_info(SIGBUS, &info, tsk); 201 force_sig_info(SIGBUS, &info, tsk);
201 202
202 return; 203 return;
@@ -212,6 +213,7 @@ vmalloc_fault:
212 */ 213 */
213 int offset = __pgd_offset(address); 214 int offset = __pgd_offset(address);
214 pgd_t *pgd, *pgd_k; 215 pgd_t *pgd, *pgd_k;
216 pud_t *pud, *pud_k;
215 pmd_t *pmd, *pmd_k; 217 pmd_t *pmd, *pmd_k;
216 pte_t *pte_k; 218 pte_t *pte_k;
217 219
@@ -222,8 +224,13 @@ vmalloc_fault:
222 goto no_context; 224 goto no_context;
223 set_pgd(pgd, *pgd_k); 225 set_pgd(pgd, *pgd_k);
224 226
225 pmd = pmd_offset(pgd, address); 227 pud = pud_offset(pgd, address);
226 pmd_k = pmd_offset(pgd_k, address); 228 pud_k = pud_offset(pgd_k, address);
229 if (!pud_present(*pud_k))
230 goto no_context;
231
232 pmd = pmd_offset(pud, address);
233 pmd_k = pmd_offset(pud_k, address);
227 if (!pmd_present(*pmd_k)) 234 if (!pmd_present(*pmd_k))
228 goto no_context; 235 goto no_context;
229 set_pmd(pmd, *pmd_k); 236 set_pmd(pmd, *pmd_k);
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index dd5e2e31885b..1f7b37b38f5c 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -83,6 +83,25 @@ void __kunmap_atomic(void *kvaddr, enum km_type type)
83 preempt_check_resched(); 83 preempt_check_resched();
84} 84}
85 85
86/*
87 * This is the same as kmap_atomic() but can map memory that doesn't
88 * have a struct page associated with it.
89 */
90void *kmap_atomic_pfn(unsigned long pfn, enum km_type type)
91{
92 enum fixed_addresses idx;
93 unsigned long vaddr;
94
95 inc_preempt_count();
96
97 idx = type + KM_TYPE_NR*smp_processor_id();
98 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
99 set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot));
100 flush_tlb_one(vaddr);
101
102 return (void*) vaddr;
103}
104
86struct page *__kmap_atomic_to_page(void *ptr) 105struct page *__kmap_atomic_to_page(void *ptr)
87{ 106{
88 unsigned long idx, vaddr = (unsigned long)ptr; 107 unsigned long idx, vaddr = (unsigned long)ptr;
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index dc6830b10fab..f75ab748e8cd 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -83,7 +83,7 @@ pte_t *kmap_pte;
83pgprot_t kmap_prot; 83pgprot_t kmap_prot;
84 84
85#define kmap_get_fixmap_pte(vaddr) \ 85#define kmap_get_fixmap_pte(vaddr) \
86 pte_offset_kernel(pmd_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)) 86 pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr))
87 87
88static void __init kmap_init(void) 88static void __init kmap_init(void)
89{ 89{
@@ -96,36 +96,42 @@ static void __init kmap_init(void)
96 kmap_prot = PAGE_KERNEL; 96 kmap_prot = PAGE_KERNEL;
97} 97}
98 98
99#ifdef CONFIG_64BIT 99#ifdef CONFIG_32BIT
100static void __init fixrange_init(unsigned long start, unsigned long end, 100void __init fixrange_init(unsigned long start, unsigned long end,
101 pgd_t *pgd_base) 101 pgd_t *pgd_base)
102{ 102{
103 pgd_t *pgd; 103 pgd_t *pgd;
104 pud_t *pud;
104 pmd_t *pmd; 105 pmd_t *pmd;
105 pte_t *pte; 106 pte_t *pte;
106 int i, j; 107 int i, j, k;
107 unsigned long vaddr; 108 unsigned long vaddr;
108 109
109 vaddr = start; 110 vaddr = start;
110 i = __pgd_offset(vaddr); 111 i = __pgd_offset(vaddr);
111 j = __pmd_offset(vaddr); 112 j = __pud_offset(vaddr);
113 k = __pmd_offset(vaddr);
112 pgd = pgd_base + i; 114 pgd = pgd_base + i;
113 115
114 for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) { 116 for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) {
115 pmd = (pmd_t *)pgd; 117 pud = (pud_t *)pgd;
116 for (; (j < PTRS_PER_PMD) && (vaddr != end); pmd++, j++) { 118 for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) {
117 if (pmd_none(*pmd)) { 119 pmd = (pmd_t *)pud;
118 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); 120 for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) {
119 set_pmd(pmd, __pmd(pte)); 121 if (pmd_none(*pmd)) {
120 if (pte != pte_offset_kernel(pmd, 0)) 122 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
121 BUG(); 123 set_pmd(pmd, __pmd(pte));
124 if (pte != pte_offset_kernel(pmd, 0))
125 BUG();
126 }
127 vaddr += PMD_SIZE;
122 } 128 }
123 vaddr += PMD_SIZE; 129 k = 0;
124 } 130 }
125 j = 0; 131 j = 0;
126 } 132 }
127} 133}
128#endif /* CONFIG_64BIT */ 134#endif /* CONFIG_32BIT */
129#endif /* CONFIG_HIGHMEM */ 135#endif /* CONFIG_HIGHMEM */
130 136
131#ifndef CONFIG_NEED_MULTIPLE_NODES 137#ifndef CONFIG_NEED_MULTIPLE_NODES
diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index adf352273f63..9c44ca70befa 100644
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -79,9 +79,14 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr,
79 BUG(); 79 BUG();
80 spin_lock(&init_mm.page_table_lock); 80 spin_lock(&init_mm.page_table_lock);
81 do { 81 do {
82 pud_t *pud;
82 pmd_t *pmd; 83 pmd_t *pmd;
83 pmd = pmd_alloc(&init_mm, dir, address); 84
84 error = -ENOMEM; 85 error = -ENOMEM;
86 pud = pud_alloc(&init_mm, dir, address);
87 if (!pud)
88 break;
89 pmd = pmd_alloc(&init_mm, pud, address);
85 if (!pmd) 90 if (!pmd)
86 break; 91 break;
87 if (remap_area_pmd(pmd, address, end - address, 92 if (remap_area_pmd(pmd, address, end - address,
@@ -97,15 +102,6 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr,
97} 102}
98 103
99/* 104/*
100 * Allow physical addresses to be fixed up to help 36 bit peripherals.
101 */
102phys_t __attribute__ ((weak))
103fixup_bigphys_addr(phys_t phys_addr, phys_t size)
104{
105 return phys_addr;
106}
107
108/*
109 * Generic mapping function (not visible outside): 105 * Generic mapping function (not visible outside):
110 */ 106 */
111 107
@@ -121,7 +117,7 @@ fixup_bigphys_addr(phys_t phys_addr, phys_t size)
121 117
122#define IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) 118#define IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
123 119
124void * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags) 120void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
125{ 121{
126 struct vm_struct * area; 122 struct vm_struct * area;
127 unsigned long offset; 123 unsigned long offset;
@@ -141,7 +137,7 @@ void * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
141 */ 137 */
142 if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) && 138 if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) &&
143 flags == _CACHE_UNCACHED) 139 flags == _CACHE_UNCACHED)
144 return (void *) KSEG1ADDR(phys_addr); 140 return (void __iomem *) CKSEG1ADDR(phys_addr);
145 141
146 /* 142 /*
147 * Don't allow anybody to remap normal RAM that we're using.. 143 * Don't allow anybody to remap normal RAM that we're using..
@@ -177,10 +173,10 @@ void * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
177 return NULL; 173 return NULL;
178 } 174 }
179 175
180 return (void *) (offset + (char *)addr); 176 return (void __iomem *) (offset + (char *)addr);
181} 177}
182 178
183#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == KSEG1) 179#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
184 180
185void __iounmap(volatile void __iomem *addr) 181void __iounmap(volatile void __iomem *addr)
186{ 182{
@@ -190,10 +186,8 @@ void __iounmap(volatile void __iomem *addr)
190 return; 186 return;
191 187
192 p = remove_vm_area((void *) (PAGE_MASK & (unsigned long __force) addr)); 188 p = remove_vm_area((void *) (PAGE_MASK & (unsigned long __force) addr));
193 if (!p) { 189 if (!p)
194 printk(KERN_ERR "iounmap: bad address %p\n", addr); 190 printk(KERN_ERR "iounmap: bad address %p\n", addr);
195 return;
196 }
197 191
198 kfree(p); 192 kfree(p);
199} 193}
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index 9f8b16541577..f51e180072e3 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -25,7 +25,10 @@
25#include <asm/cpu.h> 25#include <asm/cpu.h>
26#include <asm/war.h> 26#include <asm/war.h>
27 27
28#define half_scache_line_size() (cpu_scache_line_size() >> 1) 28#define half_scache_line_size() (cpu_scache_line_size() >> 1)
29#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
30#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
31
29 32
30/* 33/*
31 * Maximum sizes: 34 * Maximum sizes:
@@ -198,15 +201,15 @@ static inline void build_cdex_p(void)
198 if (store_offset & (cpu_dcache_line_size() - 1)) 201 if (store_offset & (cpu_dcache_line_size() - 1))
199 return; 202 return;
200 203
201 if (R4600_V1_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2010)) { 204 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
202 build_nop(); 205 build_nop();
203 build_nop(); 206 build_nop();
204 build_nop(); 207 build_nop();
205 build_nop(); 208 build_nop();
206 } 209 }
207 210
208 if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020)) 211 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
209 build_insn_word(0x8c200000); /* lw $zero, ($at) */ 212 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
210 213
211 mi.c_format.opcode = cache_op; 214 mi.c_format.opcode = cache_op;
212 mi.c_format.rs = 4; /* $a0 */ 215 mi.c_format.rs = 4; /* $a0 */
@@ -361,7 +364,7 @@ void __init build_clear_page(void)
361 364
362 build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0)); 365 build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0));
363 366
364 if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020)) 367 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
365 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ 368 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
366 369
367dest = label(); 370dest = label();
@@ -404,9 +407,6 @@ dest = label();
404 407
405 build_jr_ra(); 408 build_jr_ra();
406 409
407 flush_icache_range((unsigned long)&clear_page_array,
408 (unsigned long) epc);
409
410 BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array)); 410 BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));
411} 411}
412 412
@@ -420,7 +420,7 @@ void __init build_copy_page(void)
420 420
421 build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0)); 421 build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0));
422 422
423 if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020)) 423 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
424 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ 424 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
425 425
426dest = label(); 426dest = label();
@@ -482,8 +482,5 @@ dest = label();
482 482
483 build_jr_ra(); 483 build_jr_ra();
484 484
485 flush_icache_range((unsigned long)&copy_page_array,
486 (unsigned long) epc);
487
488 BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array)); 485 BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));
489} 486}
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index 1b6df7133c1e..148c65b9cd8b 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -60,7 +60,8 @@ static inline void clear_page_cpu(void *page)
60 " .set noreorder \n" 60 " .set noreorder \n"
61#ifdef CONFIG_CPU_HAS_PREFETCH 61#ifdef CONFIG_CPU_HAS_PREFETCH
62 " daddiu %0, %0, 128 \n" 62 " daddiu %0, %0, 128 \n"
63 " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n" /* Prefetch the first 4 lines */ 63 " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n"
64 /* Prefetch the first 4 lines */
64 " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%0) \n" 65 " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%0) \n"
65 " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%0) \n" 66 " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%0) \n"
66 " pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%0) \n" 67 " pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%0) \n"
@@ -106,7 +107,8 @@ static inline void copy_page_cpu(void *to, void *from)
106#ifdef CONFIG_CPU_HAS_PREFETCH 107#ifdef CONFIG_CPU_HAS_PREFETCH
107 " daddiu %0, %0, 128 \n" 108 " daddiu %0, %0, 128 \n"
108 " daddiu %1, %1, 128 \n" 109 " daddiu %1, %1, 128 \n"
109 " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n" /* Prefetch the first 4 lines */ 110 " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n"
111 /* Prefetch the first 4 lines */
110 " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%1)\n" 112 " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%1)\n"
111 " pref " SB1_PREF_LOAD_STREAMED_HINT ", -96(%0)\n" 113 " pref " SB1_PREF_LOAD_STREAMED_HINT ", -96(%0)\n"
112 " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%1)\n" 114 " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%1)\n"
@@ -207,66 +209,73 @@ typedef struct dmadscr_s {
207 u64 pad_b; 209 u64 pad_b;
208} dmadscr_t; 210} dmadscr_t;
209 211
210static dmadscr_t page_descr[NR_CPUS] __attribute__((aligned(SMP_CACHE_BYTES))); 212static dmadscr_t page_descr[DM_NUM_CHANNELS]
213 __attribute__((aligned(SMP_CACHE_BYTES)));
211 214
212void sb1_dma_init(void) 215void sb1_dma_init(void)
213{ 216{
214 int cpu = smp_processor_id(); 217 int i;
215 u64 base_val = CPHYSADDR(&page_descr[cpu]) | V_DM_DSCR_BASE_RINGSZ(1);
216 218
217 bus_writeq(base_val, 219 for (i = 0; i < DM_NUM_CHANNELS; i++) {
218 (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); 220 const u64 base_val = CPHYSADDR(&page_descr[i]) |
219 bus_writeq(base_val | M_DM_DSCR_BASE_RESET, 221 V_DM_DSCR_BASE_RINGSZ(1);
220 (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); 222 volatile void *base_reg =
221 bus_writeq(base_val | M_DM_DSCR_BASE_ENABL, 223 IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
222 (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); 224
225 __raw_writeq(base_val, base_reg);
226 __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg);
227 __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg);
228 }
223} 229}
224 230
225void clear_page(void *page) 231void clear_page(void *page)
226{ 232{
227 int cpu = smp_processor_id(); 233 u64 to_phys = CPHYSADDR(page);
234 unsigned int cpu = smp_processor_id();
228 235
229 /* if the page is above Kseg0, use old way */ 236 /* if the page is not in KSEG0, use old way */
230 if ((long)KSEGX(page) != (long)CKSEG0) 237 if ((long)KSEGX(page) != (long)CKSEG0)
231 return clear_page_cpu(page); 238 return clear_page_cpu(page);
232 239
233 page_descr[cpu].dscr_a = CPHYSADDR(page) | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; 240 page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM |
241 M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
234 page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); 242 page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
235 bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); 243 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
236 244
237 /* 245 /*
238 * Don't really want to do it this way, but there's no 246 * Don't really want to do it this way, but there's no
239 * reliable way to delay completion detection. 247 * reliable way to delay completion detection.
240 */ 248 */
241 while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & 249 while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
242 M_DM_DSCR_BASE_INTERRUPT)))) 250 & M_DM_DSCR_BASE_INTERRUPT))
243 ; 251 ;
244 bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); 252 __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
245} 253}
246 254
247void copy_page(void *to, void *from) 255void copy_page(void *to, void *from)
248{ 256{
249 unsigned long from_phys = CPHYSADDR(from); 257 u64 from_phys = CPHYSADDR(from);
250 unsigned long to_phys = CPHYSADDR(to); 258 u64 to_phys = CPHYSADDR(to);
251 int cpu = smp_processor_id(); 259 unsigned int cpu = smp_processor_id();
252 260
253 /* if either page is above Kseg0, use old way */ 261 /* if any page is not in KSEG0, use old way */
254 if ((long)KSEGX(to) != (long)CKSEG0 262 if ((long)KSEGX(to) != (long)CKSEG0
255 || (long)KSEGX(from) != (long)CKSEG0) 263 || (long)KSEGX(from) != (long)CKSEG0)
256 return copy_page_cpu(to, from); 264 return copy_page_cpu(to, from);
257 265
258 page_descr[cpu].dscr_a = CPHYSADDR(to_phys) | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; 266 page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST |
259 page_descr[cpu].dscr_b = CPHYSADDR(from_phys) | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); 267 M_DM_DSCRA_INTERRUPT;
260 bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); 268 page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
269 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
261 270
262 /* 271 /*
263 * Don't really want to do it this way, but there's no 272 * Don't really want to do it this way, but there's no
264 * reliable way to delay completion detection. 273 * reliable way to delay completion detection.
265 */ 274 */
266 while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & 275 while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
267 M_DM_DSCR_BASE_INTERRUPT)))) 276 & M_DM_DSCR_BASE_INTERRUPT))
268 ; 277 ;
269 bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); 278 __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
270} 279}
271 280
272#else /* !CONFIG_SIBYTE_DMA_PAGEOPS */ 281#else /* !CONFIG_SIBYTE_DMA_PAGEOPS */
diff --git a/arch/mips/mm/pgtable-32.c b/arch/mips/mm/pgtable-32.c
index 4f07f81e8500..4a3c4919e314 100644
--- a/arch/mips/mm/pgtable-32.c
+++ b/arch/mips/mm/pgtable-32.c
@@ -10,6 +10,7 @@
10#include <linux/mm.h> 10#include <linux/mm.h>
11#include <linux/bootmem.h> 11#include <linux/bootmem.h>
12#include <linux/highmem.h> 12#include <linux/highmem.h>
13#include <asm/fixmap.h>
13#include <asm/pgtable.h> 14#include <asm/pgtable.h>
14 15
15void pgd_init(unsigned long page) 16void pgd_init(unsigned long page)
@@ -29,42 +30,12 @@ void pgd_init(unsigned long page)
29 } 30 }
30} 31}
31 32
32#ifdef CONFIG_HIGHMEM
33static void __init fixrange_init (unsigned long start, unsigned long end,
34 pgd_t *pgd_base)
35{
36 pgd_t *pgd;
37 pmd_t *pmd;
38 pte_t *pte;
39 int i, j;
40 unsigned long vaddr;
41
42 vaddr = start;
43 i = __pgd_offset(vaddr);
44 j = __pmd_offset(vaddr);
45 pgd = pgd_base + i;
46
47 for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) {
48 pmd = (pmd_t *)pgd;
49 for (; (j < PTRS_PER_PMD) && (vaddr != end); pmd++, j++) {
50 if (pmd_none(*pmd)) {
51 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
52 set_pmd(pmd, __pmd((unsigned long)pte));
53 if (pte != pte_offset_kernel(pmd, 0))
54 BUG();
55 }
56 vaddr += PMD_SIZE;
57 }
58 j = 0;
59 }
60}
61#endif
62
63void __init pagetable_init(void) 33void __init pagetable_init(void)
64{ 34{
65#ifdef CONFIG_HIGHMEM 35#ifdef CONFIG_HIGHMEM
66 unsigned long vaddr; 36 unsigned long vaddr;
67 pgd_t *pgd, *pgd_base; 37 pgd_t *pgd, *pgd_base;
38 pud_t *pud;
68 pmd_t *pmd; 39 pmd_t *pmd;
69 pte_t *pte; 40 pte_t *pte;
70#endif 41#endif
@@ -90,7 +61,8 @@ void __init pagetable_init(void)
90 fixrange_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base); 61 fixrange_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base);
91 62
92 pgd = swapper_pg_dir + __pgd_offset(vaddr); 63 pgd = swapper_pg_dir + __pgd_offset(vaddr);
93 pmd = pmd_offset(pgd, vaddr); 64 pud = pud_offset(pgd, vaddr);
65 pmd = pmd_offset(pud, vaddr);
94 pte = pte_offset_kernel(pmd, vaddr); 66 pte = pte_offset_kernel(pmd, vaddr);
95 pkmap_page_table = pte; 67 pkmap_page_table = pte;
96#endif 68#endif
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index 4e92f931aaba..9e8ff8badb19 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -15,6 +15,7 @@
15#include <asm/cacheops.h> 15#include <asm/cacheops.h>
16#include <asm/mipsregs.h> 16#include <asm/mipsregs.h>
17#include <asm/processor.h> 17#include <asm/processor.h>
18#include <asm/cacheflush.h> /* for run_uncached() */
18 19
19/* Primary cache parameters. */ 20/* Primary cache parameters. */
20#define sc_lsize 32 21#define sc_lsize 32
@@ -96,25 +97,13 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
96} 97}
97 98
98/* 99/*
99 * This function is executed in the uncached segment CKSEG1. 100 * This function is executed in uncached address space.
100 * It must not touch the stack, because the stack pointer still points
101 * into CKSEG0.
102 *
103 * Three options:
104 * - Write it in assembly and guarantee that we don't use the stack.
105 * - Disable caching for CKSEG0 before calling it.
106 * - Pray that GCC doesn't randomly start using the stack.
107 *
108 * This being Linux, we obviously take the least sane of those options -
109 * following DaveM's lead in c-r4k.c
110 *
111 * It seems we get our kicks from relying on unguaranteed behaviour in GCC
112 */ 101 */
113static __init void __rm7k_sc_enable(void) 102static __init void __rm7k_sc_enable(void)
114{ 103{
115 int i; 104 int i;
116 105
117 set_c0_config(1 << 3); /* CONF_SE */ 106 set_c0_config(RM7K_CONF_SE);
118 107
119 write_c0_taglo(0); 108 write_c0_taglo(0);
120 write_c0_taghi(0); 109 write_c0_taghi(0);
@@ -127,24 +116,22 @@ static __init void __rm7k_sc_enable(void)
127 ".set mips0\n\t" 116 ".set mips0\n\t"
128 ".set reorder" 117 ".set reorder"
129 : 118 :
130 : "r" (KSEG0ADDR(i)), "i" (Index_Store_Tag_SD)); 119 : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
131 } 120 }
132} 121}
133 122
134static __init void rm7k_sc_enable(void) 123static __init void rm7k_sc_enable(void)
135{ 124{
136 void (*func)(void) = (void *) KSEG1ADDR(&__rm7k_sc_enable); 125 if (read_c0_config() & RM7K_CONF_SE)
137
138 if (read_c0_config() & 0x08) /* CONF_SE */
139 return; 126 return;
140 127
141 printk(KERN_INFO "Enabling secondary cache..."); 128 printk(KERN_INFO "Enabling secondary cache...\n");
142 func(); 129 run_uncached(__rm7k_sc_enable);
143} 130}
144 131
145static void rm7k_sc_disable(void) 132static void rm7k_sc_disable(void)
146{ 133{
147 clear_c0_config(1<<3); /* CONF_SE */ 134 clear_c0_config(RM7K_CONF_SE);
148} 135}
149 136
150struct bcache_ops rm7k_sc_ops = { 137struct bcache_ops rm7k_sc_ops = {
@@ -158,19 +145,19 @@ void __init rm7k_sc_init(void)
158{ 145{
159 unsigned int config = read_c0_config(); 146 unsigned int config = read_c0_config();
160 147
161 if ((config >> 31) & 1) /* Bit 31 set -> no S-Cache */ 148 if ((config & RM7K_CONF_SC))
162 return; 149 return;
163 150
164 printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n", 151 printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
165 (scache_size >> 10), sc_lsize); 152 (scache_size >> 10), sc_lsize);
166 153
167 if (!((config >> 3) & 1)) /* CONF_SE */ 154 if (!(config & RM7K_CONF_SE))
168 rm7k_sc_enable(); 155 rm7k_sc_enable();
169 156
170 /* 157 /*
171 * While we're at it let's deal with the tertiary cache. 158 * While we're at it let's deal with the tertiary cache.
172 */ 159 */
173 if (!((config >> 17) & 1)) { 160 if (!(config & RM7K_CONF_TC)) {
174 161
175 /* 162 /*
176 * We can't enable the L3 cache yet. There may be board-specific 163 * We can't enable the L3 cache yet. There may be board-specific
@@ -183,9 +170,9 @@ void __init rm7k_sc_init(void)
183 * to probe it. 170 * to probe it.
184 */ 171 */
185 printk(KERN_INFO "Tertiary cache present, %s enabled\n", 172 printk(KERN_INFO "Tertiary cache present, %s enabled\n",
186 config&(1<<12) ? "already" : "not (yet)"); 173 (config & RM7K_CONF_TE) ? "already" : "not (yet)");
187 174
188 if ((config >> 12) & 1) 175 if ((config & RM7K_CONF_TE))
189 rm7k_tcache_enabled = 1; 176 rm7k_tcache_enabled = 1;
190 } 177 }
191 178
diff --git a/arch/mips/mm/tlb-andes.c b/arch/mips/mm/tlb-andes.c
index 167e08e9661a..3f422a849c41 100644
--- a/arch/mips/mm/tlb-andes.c
+++ b/arch/mips/mm/tlb-andes.c
@@ -195,6 +195,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
195{ 195{
196 unsigned long flags; 196 unsigned long flags;
197 pgd_t *pgdp; 197 pgd_t *pgdp;
198 pud_t *pudp;
198 pmd_t *pmdp; 199 pmd_t *pmdp;
199 pte_t *ptep; 200 pte_t *ptep;
200 int idx, pid; 201 int idx, pid;
@@ -220,7 +221,8 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
220 write_c0_entryhi(address | (pid)); 221 write_c0_entryhi(address | (pid));
221 pgdp = pgd_offset(vma->vm_mm, address); 222 pgdp = pgd_offset(vma->vm_mm, address);
222 tlb_probe(); 223 tlb_probe();
223 pmdp = pmd_offset(pgdp, address); 224 pudp = pud_offset(pgdp, address);
225 pmdp = pmd_offset(pudp, address);
224 idx = read_c0_index(); 226 idx = read_c0_index();
225 ptep = pte_offset_map(pmdp, address); 227 ptep = pte_offset_map(pmdp, address);
226 write_c0_entrylo0(pte_val(*ptep++) >> 6); 228 write_c0_entrylo0(pte_val(*ptep++) >> 6);
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 59d38bc05b69..8297970f0bb1 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -21,6 +21,12 @@
21 21
22extern void build_tlb_refill_handler(void); 22extern void build_tlb_refill_handler(void);
23 23
24/*
25 * Make sure all entries differ. If they're not different
26 * MIPS32 will take revenge ...
27 */
28#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
29
24/* CP0 hazard avoidance. */ 30/* CP0 hazard avoidance. */
25#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ 31#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
26 "nop; nop; nop; nop; nop; nop;\n\t" \ 32 "nop; nop; nop; nop; nop; nop;\n\t" \
@@ -42,11 +48,8 @@ void local_flush_tlb_all(void)
42 48
43 /* Blast 'em all away. */ 49 /* Blast 'em all away. */
44 while (entry < current_cpu_data.tlbsize) { 50 while (entry < current_cpu_data.tlbsize) {
45 /* 51 /* Make sure all entries differ. */
46 * Make sure all entries differ. If they're not different 52 write_c0_entryhi(UNIQUE_ENTRYHI(entry));
47 * MIPS32 will take revenge ...
48 */
49 write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
50 write_c0_index(entry); 53 write_c0_index(entry);
51 mtc0_tlbw_hazard(); 54 mtc0_tlbw_hazard();
52 tlb_write_indexed(); 55 tlb_write_indexed();
@@ -57,12 +60,21 @@ void local_flush_tlb_all(void)
57 local_irq_restore(flags); 60 local_irq_restore(flags);
58} 61}
59 62
63/* All entries common to a mm share an asid. To effectively flush
64 these entries, we just bump the asid. */
60void local_flush_tlb_mm(struct mm_struct *mm) 65void local_flush_tlb_mm(struct mm_struct *mm)
61{ 66{
62 int cpu = smp_processor_id(); 67 int cpu;
68
69 preempt_disable();
63 70
64 if (cpu_context(cpu, mm) != 0) 71 cpu = smp_processor_id();
65 drop_mmu_context(mm,cpu); 72
73 if (cpu_context(cpu, mm) != 0) {
74 drop_mmu_context(mm, cpu);
75 }
76
77 preempt_enable();
66} 78}
67 79
68void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 80void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
@@ -75,9 +87,9 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
75 unsigned long flags; 87 unsigned long flags;
76 int size; 88 int size;
77 89
78 local_irq_save(flags);
79 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 90 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
80 size = (size + 1) >> 1; 91 size = (size + 1) >> 1;
92 local_irq_save(flags);
81 if (size <= current_cpu_data.tlbsize/2) { 93 if (size <= current_cpu_data.tlbsize/2) {
82 int oldpid = read_c0_entryhi(); 94 int oldpid = read_c0_entryhi();
83 int newpid = cpu_asid(cpu, mm); 95 int newpid = cpu_asid(cpu, mm);
@@ -99,8 +111,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
99 if (idx < 0) 111 if (idx < 0)
100 continue; 112 continue;
101 /* Make sure all entries differ. */ 113 /* Make sure all entries differ. */
102 write_c0_entryhi(CKSEG0 + 114 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
103 (idx << (PAGE_SHIFT + 1)));
104 mtc0_tlbw_hazard(); 115 mtc0_tlbw_hazard();
105 tlb_write_indexed(); 116 tlb_write_indexed();
106 } 117 }
@@ -118,9 +129,9 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
118 unsigned long flags; 129 unsigned long flags;
119 int size; 130 int size;
120 131
121 local_irq_save(flags);
122 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 132 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
123 size = (size + 1) >> 1; 133 size = (size + 1) >> 1;
134 local_irq_save(flags);
124 if (size <= current_cpu_data.tlbsize / 2) { 135 if (size <= current_cpu_data.tlbsize / 2) {
125 int pid = read_c0_entryhi(); 136 int pid = read_c0_entryhi();
126 137
@@ -142,7 +153,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
142 if (idx < 0) 153 if (idx < 0)
143 continue; 154 continue;
144 /* Make sure all entries differ. */ 155 /* Make sure all entries differ. */
145 write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1))); 156 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
146 mtc0_tlbw_hazard(); 157 mtc0_tlbw_hazard();
147 tlb_write_indexed(); 158 tlb_write_indexed();
148 } 159 }
@@ -176,7 +187,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
176 if (idx < 0) 187 if (idx < 0)
177 goto finish; 188 goto finish;
178 /* Make sure all entries differ. */ 189 /* Make sure all entries differ. */
179 write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1))); 190 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
180 mtc0_tlbw_hazard(); 191 mtc0_tlbw_hazard();
181 tlb_write_indexed(); 192 tlb_write_indexed();
182 tlbw_use_hazard(); 193 tlbw_use_hazard();
@@ -197,8 +208,8 @@ void local_flush_tlb_one(unsigned long page)
197 int oldpid, idx; 208 int oldpid, idx;
198 209
199 local_irq_save(flags); 210 local_irq_save(flags);
200 page &= (PAGE_MASK << 1);
201 oldpid = read_c0_entryhi(); 211 oldpid = read_c0_entryhi();
212 page &= (PAGE_MASK << 1);
202 write_c0_entryhi(page); 213 write_c0_entryhi(page);
203 mtc0_tlbw_hazard(); 214 mtc0_tlbw_hazard();
204 tlb_probe(); 215 tlb_probe();
@@ -208,7 +219,7 @@ void local_flush_tlb_one(unsigned long page)
208 write_c0_entrylo1(0); 219 write_c0_entrylo1(0);
209 if (idx >= 0) { 220 if (idx >= 0) {
210 /* Make sure all entries differ. */ 221 /* Make sure all entries differ. */
211 write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1))); 222 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
212 mtc0_tlbw_hazard(); 223 mtc0_tlbw_hazard();
213 tlb_write_indexed(); 224 tlb_write_indexed();
214 tlbw_use_hazard(); 225 tlbw_use_hazard();
@@ -227,6 +238,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
227{ 238{
228 unsigned long flags; 239 unsigned long flags;
229 pgd_t *pgdp; 240 pgd_t *pgdp;
241 pud_t *pudp;
230 pmd_t *pmdp; 242 pmd_t *pmdp;
231 pte_t *ptep; 243 pte_t *ptep;
232 int idx, pid; 244 int idx, pid;
@@ -237,35 +249,34 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
237 if (current->active_mm != vma->vm_mm) 249 if (current->active_mm != vma->vm_mm)
238 return; 250 return;
239 251
240 pid = read_c0_entryhi() & ASID_MASK;
241
242 local_irq_save(flags); 252 local_irq_save(flags);
253
254 pid = read_c0_entryhi() & ASID_MASK;
243 address &= (PAGE_MASK << 1); 255 address &= (PAGE_MASK << 1);
244 write_c0_entryhi(address | pid); 256 write_c0_entryhi(address | pid);
245 pgdp = pgd_offset(vma->vm_mm, address); 257 pgdp = pgd_offset(vma->vm_mm, address);
246 mtc0_tlbw_hazard(); 258 mtc0_tlbw_hazard();
247 tlb_probe(); 259 tlb_probe();
248 BARRIER; 260 BARRIER;
249 pmdp = pmd_offset(pgdp, address); 261 pudp = pud_offset(pgdp, address);
262 pmdp = pmd_offset(pudp, address);
250 idx = read_c0_index(); 263 idx = read_c0_index();
251 ptep = pte_offset_map(pmdp, address); 264 ptep = pte_offset_map(pmdp, address);
252 265
253 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 266#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
254 write_c0_entrylo0(ptep->pte_high); 267 write_c0_entrylo0(ptep->pte_high);
255 ptep++; 268 ptep++;
256 write_c0_entrylo1(ptep->pte_high); 269 write_c0_entrylo1(ptep->pte_high);
257#else 270#else
258 write_c0_entrylo0(pte_val(*ptep++) >> 6); 271 write_c0_entrylo0(pte_val(*ptep++) >> 6);
259 write_c0_entrylo1(pte_val(*ptep) >> 6); 272 write_c0_entrylo1(pte_val(*ptep) >> 6);
260#endif 273#endif
261 write_c0_entryhi(address | pid);
262 mtc0_tlbw_hazard(); 274 mtc0_tlbw_hazard();
263 if (idx < 0) 275 if (idx < 0)
264 tlb_write_random(); 276 tlb_write_random();
265 else 277 else
266 tlb_write_indexed(); 278 tlb_write_indexed();
267 tlbw_use_hazard(); 279 tlbw_use_hazard();
268 write_c0_entryhi(pid);
269 local_irq_restore(flags); 280 local_irq_restore(flags);
270} 281}
271 282
@@ -357,7 +368,8 @@ __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
357 old_pagemask = read_c0_pagemask(); 368 old_pagemask = read_c0_pagemask();
358 wired = read_c0_wired(); 369 wired = read_c0_wired();
359 if (--temp_tlb_entry < wired) { 370 if (--temp_tlb_entry < wired) {
360 printk(KERN_WARNING "No TLB space left for add_temporary_entry\n"); 371 printk(KERN_WARNING
372 "No TLB space left for add_temporary_entry\n");
361 ret = -ENOSPC; 373 ret = -ENOSPC;
362 goto out; 374 goto out;
363 } 375 }
@@ -388,7 +400,7 @@ static void __init probe_tlb(unsigned long config)
388 * is not supported, we assume R4k style. Cpu probing already figured 400 * is not supported, we assume R4k style. Cpu probing already figured
389 * out the number of tlb entries. 401 * out the number of tlb entries.
390 */ 402 */
391 if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY) 403 if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY)
392 return; 404 return;
393 405
394 reg = read_c0_config1(); 406 reg = read_c0_config1();
diff --git a/arch/mips/mm/tlb-sb1.c b/arch/mips/mm/tlb-sb1.c
deleted file mode 100644
index 6256cafcf3a2..000000000000
--- a/arch/mips/mm/tlb-sb1.c
+++ /dev/null
@@ -1,376 +0,0 @@
1/*
2 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
3 * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org)
4 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20#include <linux/init.h>
21#include <asm/mmu_context.h>
22#include <asm/bootinfo.h>
23#include <asm/cpu.h>
24
25extern void build_tlb_refill_handler(void);
26
27#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
28
29/* Dump the current entry* and pagemask registers */
30static inline void dump_cur_tlb_regs(void)
31{
32 unsigned int entryhihi, entryhilo, entrylo0hi, entrylo0lo, entrylo1hi;
33 unsigned int entrylo1lo, pagemask;
34
35 __asm__ __volatile__ (
36 ".set push \n"
37 ".set noreorder \n"
38 ".set mips64 \n"
39 ".set noat \n"
40 " tlbr \n"
41 " dmfc0 $1, $10 \n"
42 " dsrl32 %0, $1, 0 \n"
43 " sll %1, $1, 0 \n"
44 " dmfc0 $1, $2 \n"
45 " dsrl32 %2, $1, 0 \n"
46 " sll %3, $1, 0 \n"
47 " dmfc0 $1, $3 \n"
48 " dsrl32 %4, $1, 0 \n"
49 " sll %5, $1, 0 \n"
50 " mfc0 %6, $5 \n"
51 ".set pop \n"
52 : "=r" (entryhihi), "=r" (entryhilo),
53 "=r" (entrylo0hi), "=r" (entrylo0lo),
54 "=r" (entrylo1hi), "=r" (entrylo1lo),
55 "=r" (pagemask));
56
57 printk("%08X%08X %08X%08X %08X%08X %08X",
58 entryhihi, entryhilo,
59 entrylo0hi, entrylo0lo,
60 entrylo1hi, entrylo1lo,
61 pagemask);
62}
63
64void sb1_dump_tlb(void)
65{
66 unsigned long old_ctx;
67 unsigned long flags;
68 int entry;
69 local_irq_save(flags);
70 old_ctx = read_c0_entryhi();
71 printk("Current TLB registers state:\n"
72 " EntryHi EntryLo0 EntryLo1 PageMask Index\n"
73 "--------------------------------------------------------------------\n");
74 dump_cur_tlb_regs();
75 printk(" %08X\n", read_c0_index());
76 printk("\n\nFull TLB Dump:\n"
77 "Idx EntryHi EntryLo0 EntryLo1 PageMask\n"
78 "--------------------------------------------------------------\n");
79 for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
80 write_c0_index(entry);
81 printk("\n%02i ", entry);
82 dump_cur_tlb_regs();
83 }
84 printk("\n");
85 write_c0_entryhi(old_ctx);
86 local_irq_restore(flags);
87}
88
89void local_flush_tlb_all(void)
90{
91 unsigned long flags;
92 unsigned long old_ctx;
93 int entry;
94
95 local_irq_save(flags);
96 /* Save old context and create impossible VPN2 value */
97 old_ctx = read_c0_entryhi() & ASID_MASK;
98 write_c0_entrylo0(0);
99 write_c0_entrylo1(0);
100
101 entry = read_c0_wired();
102 while (entry < current_cpu_data.tlbsize) {
103 write_c0_entryhi(UNIQUE_ENTRYHI(entry));
104 write_c0_index(entry);
105 tlb_write_indexed();
106 entry++;
107 }
108 write_c0_entryhi(old_ctx);
109 local_irq_restore(flags);
110}
111
112
113/*
114 * Use a bogus region of memory (starting at 0) to sanitize the TLB's.
115 * Use increments of the maximum page size (16MB), and check for duplicate
116 * entries before doing a given write. Then, when we're safe from collisions
117 * with the firmware, go back and give all the entries invalid addresses with
118 * the normal flush routine. Wired entries will be killed as well!
119 */
120static void __init sb1_sanitize_tlb(void)
121{
122 int entry;
123 long addr = 0;
124
125 long inc = 1<<24; /* 16MB */
126 /* Save old context and create impossible VPN2 value */
127 write_c0_entrylo0(0);
128 write_c0_entrylo1(0);
129 for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
130 do {
131 addr += inc;
132 write_c0_entryhi(addr);
133 tlb_probe();
134 } while ((int)(read_c0_index()) >= 0);
135 write_c0_index(entry);
136 tlb_write_indexed();
137 }
138 /* Now that we know we're safe from collisions, we can safely flush
139 the TLB with the "normal" routine. */
140 local_flush_tlb_all();
141}
142
143void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
144 unsigned long end)
145{
146 struct mm_struct *mm = vma->vm_mm;
147 unsigned long flags;
148 int cpu;
149
150 local_irq_save(flags);
151 cpu = smp_processor_id();
152 if (cpu_context(cpu, mm) != 0) {
153 int size;
154 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
155 size = (size + 1) >> 1;
156 if (size <= (current_cpu_data.tlbsize/2)) {
157 int oldpid = read_c0_entryhi() & ASID_MASK;
158 int newpid = cpu_asid(cpu, mm);
159
160 start &= (PAGE_MASK << 1);
161 end += ((PAGE_SIZE << 1) - 1);
162 end &= (PAGE_MASK << 1);
163 while (start < end) {
164 int idx;
165
166 write_c0_entryhi(start | newpid);
167 start += (PAGE_SIZE << 1);
168 tlb_probe();
169 idx = read_c0_index();
170 write_c0_entrylo0(0);
171 write_c0_entrylo1(0);
172 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
173 if (idx < 0)
174 continue;
175 tlb_write_indexed();
176 }
177 write_c0_entryhi(oldpid);
178 } else {
179 drop_mmu_context(mm, cpu);
180 }
181 }
182 local_irq_restore(flags);
183}
184
185void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
186{
187 unsigned long flags;
188 int size;
189
190 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
191 size = (size + 1) >> 1;
192
193 local_irq_save(flags);
194 if (size <= (current_cpu_data.tlbsize/2)) {
195 int pid = read_c0_entryhi();
196
197 start &= (PAGE_MASK << 1);
198 end += ((PAGE_SIZE << 1) - 1);
199 end &= (PAGE_MASK << 1);
200
201 while (start < end) {
202 int idx;
203
204 write_c0_entryhi(start);
205 start += (PAGE_SIZE << 1);
206 tlb_probe();
207 idx = read_c0_index();
208 write_c0_entrylo0(0);
209 write_c0_entrylo1(0);
210 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
211 if (idx < 0)
212 continue;
213 tlb_write_indexed();
214 }
215 write_c0_entryhi(pid);
216 } else {
217 local_flush_tlb_all();
218 }
219 local_irq_restore(flags);
220}
221
222void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
223{
224 unsigned long flags;
225 int cpu = smp_processor_id();
226
227 local_irq_save(flags);
228 if (cpu_context(cpu, vma->vm_mm) != 0) {
229 int oldpid, newpid, idx;
230 newpid = cpu_asid(cpu, vma->vm_mm);
231 page &= (PAGE_MASK << 1);
232 oldpid = read_c0_entryhi() & ASID_MASK;
233 write_c0_entryhi(page | newpid);
234 tlb_probe();
235 idx = read_c0_index();
236 write_c0_entrylo0(0);
237 write_c0_entrylo1(0);
238 if (idx < 0)
239 goto finish;
240 /* Make sure all entries differ. */
241 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
242 tlb_write_indexed();
243 finish:
244 write_c0_entryhi(oldpid);
245 }
246 local_irq_restore(flags);
247}
248
249/*
250 * Remove one kernel space TLB entry. This entry is assumed to be marked
251 * global so we don't do the ASID thing.
252 */
253void local_flush_tlb_one(unsigned long page)
254{
255 unsigned long flags;
256 int oldpid, idx;
257
258 page &= (PAGE_MASK << 1);
259 oldpid = read_c0_entryhi() & ASID_MASK;
260
261 local_irq_save(flags);
262 write_c0_entryhi(page);
263 tlb_probe();
264 idx = read_c0_index();
265 if (idx >= 0) {
266 /* Make sure all entries differ. */
267 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
268 write_c0_entrylo0(0);
269 write_c0_entrylo1(0);
270 tlb_write_indexed();
271 }
272
273 write_c0_entryhi(oldpid);
274 local_irq_restore(flags);
275}
276
277/* All entries common to a mm share an asid. To effectively flush
278 these entries, we just bump the asid. */
279void local_flush_tlb_mm(struct mm_struct *mm)
280{
281 int cpu;
282
283 preempt_disable();
284
285 cpu = smp_processor_id();
286
287 if (cpu_context(cpu, mm) != 0) {
288 drop_mmu_context(mm, cpu);
289 }
290
291 preempt_enable();
292}
293
294/* Stolen from mips32 routines */
295
296void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
297{
298 unsigned long flags;
299 pgd_t *pgdp;
300 pmd_t *pmdp;
301 pte_t *ptep;
302 int idx, pid;
303
304 /*
305 * Handle debugger faulting in for debugee.
306 */
307 if (current->active_mm != vma->vm_mm)
308 return;
309
310 local_irq_save(flags);
311
312 pid = read_c0_entryhi() & ASID_MASK;
313 address &= (PAGE_MASK << 1);
314 write_c0_entryhi(address | (pid));
315 pgdp = pgd_offset(vma->vm_mm, address);
316 tlb_probe();
317 pmdp = pmd_offset(pgdp, address);
318 idx = read_c0_index();
319 ptep = pte_offset_map(pmdp, address);
320 write_c0_entrylo0(pte_val(*ptep++) >> 6);
321 write_c0_entrylo1(pte_val(*ptep) >> 6);
322 if (idx < 0) {
323 tlb_write_random();
324 } else {
325 tlb_write_indexed();
326 }
327 local_irq_restore(flags);
328}
329
330void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
331 unsigned long entryhi, unsigned long pagemask)
332{
333 unsigned long flags;
334 unsigned long wired;
335 unsigned long old_pagemask;
336 unsigned long old_ctx;
337
338 local_irq_save(flags);
339 old_ctx = read_c0_entryhi() & 0xff;
340 old_pagemask = read_c0_pagemask();
341 wired = read_c0_wired();
342 write_c0_wired(wired + 1);
343 write_c0_index(wired);
344
345 write_c0_pagemask(pagemask);
346 write_c0_entryhi(entryhi);
347 write_c0_entrylo0(entrylo0);
348 write_c0_entrylo1(entrylo1);
349 tlb_write_indexed();
350
351 write_c0_entryhi(old_ctx);
352 write_c0_pagemask(old_pagemask);
353
354 local_flush_tlb_all();
355 local_irq_restore(flags);
356}
357
358/*
359 * This is called from loadmmu.c. We have to set up all the
360 * memory management function pointers, as well as initialize
361 * the caches and tlbs
362 */
363void tlb_init(void)
364{
365 write_c0_pagemask(PM_DEFAULT_MASK);
366 write_c0_wired(0);
367
368 /*
369 * We don't know what state the firmware left the TLB's in, so this is
370 * the ultra-conservative way to flush the TLB's and avoid machine
371 * check exceptions due to duplicate TLB entries
372 */
373 sb1_sanitize_tlb();
374
375 build_tlb_refill_handler();
376}
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 6569be3983c7..0f9485806bac 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -6,6 +6,7 @@
6 * Synthesize TLB refill handlers at runtime. 6 * Synthesize TLB refill handlers at runtime.
7 * 7 *
8 * Copyright (C) 2004,2005 by Thiemo Seufer 8 * Copyright (C) 2004,2005 by Thiemo Seufer
9 * Copyright (C) 2005 Maciej W. Rozycki
9 */ 10 */
10 11
11#include <stdarg.h> 12#include <stdarg.h>
@@ -91,7 +92,7 @@ enum opcode {
91 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, 92 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
92 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 93 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
93 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, 94 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
94 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, 95 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
95 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, 96 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
96 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, 97 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
97 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, 98 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
@@ -134,7 +135,6 @@ static __initdata struct insn insn_table[] = {
134 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, 135 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE },
135 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, 136 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE },
136 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, 137 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE },
137 { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE },
138 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, 138 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD },
139 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, 139 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 },
140 { insn_j, M(j_op,0,0,0,0,0), JIMM }, 140 { insn_j, M(j_op,0,0,0,0,0), JIMM },
@@ -366,7 +366,6 @@ I_u2u1u3(_dsll);
366I_u2u1u3(_dsll32); 366I_u2u1u3(_dsll32);
367I_u2u1u3(_dsra); 367I_u2u1u3(_dsra);
368I_u2u1u3(_dsrl); 368I_u2u1u3(_dsrl);
369I_u2u1u3(_dsrl32);
370I_u3u1u2(_dsubu); 369I_u3u1u2(_dsubu);
371I_0(_eret); 370I_0(_eret);
372I_u1(_j); 371I_u1(_j);
@@ -412,7 +411,6 @@ enum label_id {
412 label_nopage_tlbm, 411 label_nopage_tlbm,
413 label_smp_pgtable_change, 412 label_smp_pgtable_change,
414 label_r3000_write_probe_fail, 413 label_r3000_write_probe_fail,
415 label_r3000_write_probe_ok
416}; 414};
417 415
418struct label { 416struct label {
@@ -445,7 +443,6 @@ L_LA(_nopage_tlbs)
445L_LA(_nopage_tlbm) 443L_LA(_nopage_tlbm)
446L_LA(_smp_pgtable_change) 444L_LA(_smp_pgtable_change)
447L_LA(_r3000_write_probe_fail) 445L_LA(_r3000_write_probe_fail)
448L_LA(_r3000_write_probe_ok)
449 446
450/* convenience macros for instructions */ 447/* convenience macros for instructions */
451#ifdef CONFIG_64BIT 448#ifdef CONFIG_64BIT
@@ -490,7 +487,7 @@ L_LA(_r3000_write_probe_ok)
490static __init int __attribute__((unused)) in_compat_space_p(long addr) 487static __init int __attribute__((unused)) in_compat_space_p(long addr)
491{ 488{
492 /* Is this address in 32bit compat space? */ 489 /* Is this address in 32bit compat space? */
493 return (((addr) & 0xffffffff00000000) == 0xffffffff00000000); 490 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
494} 491}
495 492
496static __init int __attribute__((unused)) rel_highest(long val) 493static __init int __attribute__((unused)) rel_highest(long val)
@@ -734,7 +731,7 @@ static void __init build_r3000_tlb_refill_handler(void)
734 if (p > tlb_handler + 32) 731 if (p > tlb_handler + 32)
735 panic("TLB refill handler space exceeded"); 732 panic("TLB refill handler space exceeded");
736 733
737 printk("Synthesized TLB handler (%u instructions).\n", 734 printk("Synthesized TLB refill handler (%u instructions).\n",
738 (unsigned int)(p - tlb_handler)); 735 (unsigned int)(p - tlb_handler));
739#ifdef DEBUG_TLB 736#ifdef DEBUG_TLB
740 { 737 {
@@ -746,7 +743,6 @@ static void __init build_r3000_tlb_refill_handler(void)
746#endif 743#endif
747 744
748 memcpy((void *)CAC_BASE, tlb_handler, 0x80); 745 memcpy((void *)CAC_BASE, tlb_handler, 0x80);
749 flush_icache_range(CAC_BASE, CAC_BASE + 0x80);
750} 746}
751 747
752/* 748/*
@@ -783,6 +779,8 @@ static __initdata u32 final_handler[64];
783static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p) 779static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p)
784{ 780{
785 switch (current_cpu_data.cputype) { 781 switch (current_cpu_data.cputype) {
782 /* Found by experiment: R4600 v2.0 needs this, too. */
783 case CPU_R4600:
786 case CPU_R5000: 784 case CPU_R5000:
787 case CPU_R5000A: 785 case CPU_R5000A:
788 case CPU_NEVADA: 786 case CPU_NEVADA:
@@ -834,12 +832,20 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
834 case CPU_R4700: 832 case CPU_R4700:
835 case CPU_R5000: 833 case CPU_R5000:
836 case CPU_R5000A: 834 case CPU_R5000A:
835 i_nop(p);
836 tlbw(p);
837 i_nop(p);
838 break;
839
840 case CPU_R4300:
837 case CPU_5KC: 841 case CPU_5KC:
838 case CPU_TX49XX: 842 case CPU_TX49XX:
839 case CPU_AU1000: 843 case CPU_AU1000:
840 case CPU_AU1100: 844 case CPU_AU1100:
841 case CPU_AU1500: 845 case CPU_AU1500:
842 case CPU_AU1550: 846 case CPU_AU1550:
847 case CPU_AU1200:
848 case CPU_PR4450:
843 i_nop(p); 849 i_nop(p);
844 tlbw(p); 850 tlbw(p);
845 break; 851 break;
@@ -848,6 +854,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
848 case CPU_R12000: 854 case CPU_R12000:
849 case CPU_4KC: 855 case CPU_4KC:
850 case CPU_SB1: 856 case CPU_SB1:
857 case CPU_SB1A:
851 case CPU_4KSC: 858 case CPU_4KSC:
852 case CPU_20KC: 859 case CPU_20KC:
853 case CPU_25KF: 860 case CPU_25KF:
@@ -875,6 +882,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
875 882
876 case CPU_4KEC: 883 case CPU_4KEC:
877 case CPU_24K: 884 case CPU_24K:
885 case CPU_34K:
878 i_ehb(p); 886 i_ehb(p);
879 tlbw(p); 887 tlbw(p);
880 break; 888 break;
@@ -911,6 +919,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
911 919
912 case CPU_VR4131: 920 case CPU_VR4131:
913 case CPU_VR4133: 921 case CPU_VR4133:
922 case CPU_R5432:
914 i_nop(p); 923 i_nop(p);
915 i_nop(p); 924 i_nop(p);
916 tlbw(p); 925 tlbw(p);
@@ -942,34 +951,29 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
942 /* No i_nop needed here, since the next insn doesn't touch TMP. */ 951 /* No i_nop needed here, since the next insn doesn't touch TMP. */
943 952
944#ifdef CONFIG_SMP 953#ifdef CONFIG_SMP
954# ifdef CONFIG_BUILD_ELF64
945 /* 955 /*
946 * 64 bit SMP has the lower part of &pgd_current[smp_processor_id()] 956 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
947 * stored in CONTEXT. 957 * stored in CONTEXT.
948 */ 958 */
949 if (in_compat_space_p(pgdc)) { 959 i_dmfc0(p, ptr, C0_CONTEXT);
950 i_dmfc0(p, ptr, C0_CONTEXT); 960 i_dsrl(p, ptr, ptr, 23);
951 i_dsra(p, ptr, ptr, 23); 961 i_LA_mostly(p, tmp, pgdc);
952 i_ld(p, ptr, 0, ptr); 962 i_daddu(p, ptr, ptr, tmp);
953 } else { 963 i_dmfc0(p, tmp, C0_BADVADDR);
954#ifdef CONFIG_BUILD_ELF64 964 i_ld(p, ptr, rel_lo(pgdc), ptr);
955 i_dmfc0(p, ptr, C0_CONTEXT); 965# else
956 i_dsrl(p, ptr, ptr, 23); 966 /*
957 i_dsll(p, ptr, ptr, 3); 967 * 64 bit SMP running in compat space has the lower part of
958 i_LA_mostly(p, tmp, pgdc); 968 * &pgd_current[smp_processor_id()] stored in CONTEXT.
959 i_daddu(p, ptr, ptr, tmp); 969 */
960 i_dmfc0(p, tmp, C0_BADVADDR); 970 if (!in_compat_space_p(pgdc))
961 i_ld(p, ptr, rel_lo(pgdc), ptr); 971 panic("Invalid page directory address!");
962#else 972
963 i_dmfc0(p, ptr, C0_CONTEXT); 973 i_dmfc0(p, ptr, C0_CONTEXT);
964 i_lui(p, tmp, rel_highest(pgdc)); 974 i_dsra(p, ptr, ptr, 23);
965 i_dsll(p, ptr, ptr, 9); 975 i_ld(p, ptr, 0, ptr);
966 i_daddiu(p, tmp, tmp, rel_higher(pgdc)); 976# endif
967 i_dsrl32(p, ptr, ptr, 0);
968 i_and(p, ptr, ptr, tmp);
969 i_dmfc0(p, tmp, C0_BADVADDR);
970 i_ld(p, ptr, 0, ptr);
971#endif
972 }
973#else 977#else
974 i_LA_mostly(p, ptr, pgdc); 978 i_LA_mostly(p, ptr, pgdc);
975 i_ld(p, ptr, rel_lo(pgdc), ptr); 979 i_ld(p, ptr, rel_lo(pgdc), ptr);
@@ -1026,7 +1030,6 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1026 i_mfc0(p, ptr, C0_CONTEXT); 1030 i_mfc0(p, ptr, C0_CONTEXT);
1027 i_LA_mostly(p, tmp, pgdc); 1031 i_LA_mostly(p, tmp, pgdc);
1028 i_srl(p, ptr, ptr, 23); 1032 i_srl(p, ptr, ptr, 23);
1029 i_sll(p, ptr, ptr, 2);
1030 i_addu(p, ptr, tmp, ptr); 1033 i_addu(p, ptr, tmp, ptr);
1031#else 1034#else
1032 i_LA_mostly(p, ptr, pgdc); 1035 i_LA_mostly(p, ptr, pgdc);
@@ -1245,13 +1248,19 @@ static void __init build_r4000_tlb_refill_handler(void)
1245 { 1248 {
1246 int i; 1249 int i;
1247 1250
1248 for (i = 0; i < 64; i++) 1251 f = final_handler;
1249 printk("%08x\n", final_handler[i]); 1252#ifdef CONFIG_64BIT
1253 if (final_len > 32)
1254 final_len = 64;
1255 else
1256 f = final_handler + 32;
1257#endif /* CONFIG_64BIT */
1258 for (i = 0; i < final_len; i++)
1259 printk("%08x\n", f[i]);
1250 } 1260 }
1251#endif 1261#endif
1252 1262
1253 memcpy((void *)CAC_BASE, final_handler, 0x100); 1263 memcpy((void *)CAC_BASE, final_handler, 0x100);
1254 flush_icache_range(CAC_BASE, CAC_BASE + 0x100);
1255} 1264}
1256 1265
1257/* 1266/*
@@ -1277,37 +1286,41 @@ u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE];
1277u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; 1286u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE];
1278 1287
1279static void __init 1288static void __init
1280iPTE_LW(u32 **p, struct label **l, unsigned int pte, int offset, 1289iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr)
1281 unsigned int ptr)
1282{ 1290{
1283#ifdef CONFIG_SMP 1291#ifdef CONFIG_SMP
1284# ifdef CONFIG_64BIT_PHYS_ADDR 1292# ifdef CONFIG_64BIT_PHYS_ADDR
1285 if (cpu_has_64bits) 1293 if (cpu_has_64bits)
1286 i_lld(p, pte, offset, ptr); 1294 i_lld(p, pte, 0, ptr);
1287 else 1295 else
1288# endif 1296# endif
1289 i_LL(p, pte, offset, ptr); 1297 i_LL(p, pte, 0, ptr);
1290#else 1298#else
1291# ifdef CONFIG_64BIT_PHYS_ADDR 1299# ifdef CONFIG_64BIT_PHYS_ADDR
1292 if (cpu_has_64bits) 1300 if (cpu_has_64bits)
1293 i_ld(p, pte, offset, ptr); 1301 i_ld(p, pte, 0, ptr);
1294 else 1302 else
1295# endif 1303# endif
1296 i_LW(p, pte, offset, ptr); 1304 i_LW(p, pte, 0, ptr);
1297#endif 1305#endif
1298} 1306}
1299 1307
1300static void __init 1308static void __init
1301iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, int offset, 1309iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr,
1302 unsigned int ptr) 1310 unsigned int mode)
1303{ 1311{
1312#ifdef CONFIG_64BIT_PHYS_ADDR
1313 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1314#endif
1315
1316 i_ori(p, pte, pte, mode);
1304#ifdef CONFIG_SMP 1317#ifdef CONFIG_SMP
1305# ifdef CONFIG_64BIT_PHYS_ADDR 1318# ifdef CONFIG_64BIT_PHYS_ADDR
1306 if (cpu_has_64bits) 1319 if (cpu_has_64bits)
1307 i_scd(p, pte, offset, ptr); 1320 i_scd(p, pte, 0, ptr);
1308 else 1321 else
1309# endif 1322# endif
1310 i_SC(p, pte, offset, ptr); 1323 i_SC(p, pte, 0, ptr);
1311 1324
1312 if (r10000_llsc_war()) 1325 if (r10000_llsc_war())
1313 il_beqzl(p, r, pte, label_smp_pgtable_change); 1326 il_beqzl(p, r, pte, label_smp_pgtable_change);
@@ -1318,7 +1331,7 @@ iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, int offset,
1318 if (!cpu_has_64bits) { 1331 if (!cpu_has_64bits) {
1319 /* no i_nop needed */ 1332 /* no i_nop needed */
1320 i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1333 i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1321 i_ori(p, pte, pte, _PAGE_VALID); 1334 i_ori(p, pte, pte, hwmode);
1322 i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1335 i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1323 il_beqz(p, r, pte, label_smp_pgtable_change); 1336 il_beqz(p, r, pte, label_smp_pgtable_change);
1324 /* no i_nop needed */ 1337 /* no i_nop needed */
@@ -1331,15 +1344,15 @@ iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, int offset,
1331#else 1344#else
1332# ifdef CONFIG_64BIT_PHYS_ADDR 1345# ifdef CONFIG_64BIT_PHYS_ADDR
1333 if (cpu_has_64bits) 1346 if (cpu_has_64bits)
1334 i_sd(p, pte, offset, ptr); 1347 i_sd(p, pte, 0, ptr);
1335 else 1348 else
1336# endif 1349# endif
1337 i_SW(p, pte, offset, ptr); 1350 i_SW(p, pte, 0, ptr);
1338 1351
1339# ifdef CONFIG_64BIT_PHYS_ADDR 1352# ifdef CONFIG_64BIT_PHYS_ADDR
1340 if (!cpu_has_64bits) { 1353 if (!cpu_has_64bits) {
1341 i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1354 i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1342 i_ori(p, pte, pte, _PAGE_VALID); 1355 i_ori(p, pte, pte, hwmode);
1343 i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1356 i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1344 i_lw(p, pte, 0, ptr); 1357 i_lw(p, pte, 0, ptr);
1345 } 1358 }
@@ -1359,7 +1372,7 @@ build_pte_present(u32 **p, struct label **l, struct reloc **r,
1359 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1372 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1360 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1373 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1361 il_bnez(p, r, pte, lid); 1374 il_bnez(p, r, pte, lid);
1362 iPTE_LW(p, l, pte, 0, ptr); 1375 iPTE_LW(p, l, pte, ptr);
1363} 1376}
1364 1377
1365/* Make PTE valid, store result in PTR. */ 1378/* Make PTE valid, store result in PTR. */
@@ -1367,8 +1380,9 @@ static void __init
1367build_make_valid(u32 **p, struct reloc **r, unsigned int pte, 1380build_make_valid(u32 **p, struct reloc **r, unsigned int pte,
1368 unsigned int ptr) 1381 unsigned int ptr)
1369{ 1382{
1370 i_ori(p, pte, pte, _PAGE_VALID | _PAGE_ACCESSED); 1383 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1371 iPTE_SW(p, r, pte, 0, ptr); 1384
1385 iPTE_SW(p, r, pte, ptr, mode);
1372} 1386}
1373 1387
1374/* 1388/*
@@ -1382,7 +1396,7 @@ build_pte_writable(u32 **p, struct label **l, struct reloc **r,
1382 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1396 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1383 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1397 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1384 il_bnez(p, r, pte, lid); 1398 il_bnez(p, r, pte, lid);
1385 iPTE_LW(p, l, pte, 0, ptr); 1399 iPTE_LW(p, l, pte, ptr);
1386} 1400}
1387 1401
1388/* Make PTE writable, update software status bits as well, then store 1402/* Make PTE writable, update software status bits as well, then store
@@ -1392,9 +1406,10 @@ static void __init
1392build_make_write(u32 **p, struct reloc **r, unsigned int pte, 1406build_make_write(u32 **p, struct reloc **r, unsigned int pte,
1393 unsigned int ptr) 1407 unsigned int ptr)
1394{ 1408{
1395 i_ori(p, pte, pte, 1409 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1396 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 1410 | _PAGE_DIRTY);
1397 iPTE_SW(p, r, pte, 0, ptr); 1411
1412 iPTE_SW(p, r, pte, ptr, mode);
1398} 1413}
1399 1414
1400/* 1415/*
@@ -1407,41 +1422,48 @@ build_pte_modifiable(u32 **p, struct label **l, struct reloc **r,
1407{ 1422{
1408 i_andi(p, pte, pte, _PAGE_WRITE); 1423 i_andi(p, pte, pte, _PAGE_WRITE);
1409 il_beqz(p, r, pte, lid); 1424 il_beqz(p, r, pte, lid);
1410 iPTE_LW(p, l, pte, 0, ptr); 1425 iPTE_LW(p, l, pte, ptr);
1411} 1426}
1412 1427
1413/* 1428/*
1414 * R3000 style TLB load/store/modify handlers. 1429 * R3000 style TLB load/store/modify handlers.
1415 */ 1430 */
1416 1431
1417/* This places the pte in the page table at PTR into ENTRYLO0. */ 1432/*
1433 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1434 * Then it returns.
1435 */
1418static void __init 1436static void __init
1419build_r3000_pte_reload(u32 **p, unsigned int ptr) 1437build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1420{ 1438{
1421 i_lw(p, ptr, 0, ptr); 1439 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1422 i_nop(p); /* load delay */ 1440 i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1423 i_mtc0(p, ptr, C0_ENTRYLO0); 1441 i_tlbwi(p);
1424 i_nop(p); /* cp0 delay */ 1442 i_jr(p, tmp);
1443 i_rfe(p); /* branch delay */
1425} 1444}
1426 1445
1427/* 1446/*
1428 * The index register may have the probe fail bit set, 1447 * This places the pte into ENTRYLO0 and writes it with tlbwi
1429 * because we would trap on access kseg2, i.e. without refill. 1448 * or tlbwr as appropriate. This is because the index register
1449 * may have the probe fail bit set as a result of a trap on a
1450 * kseg2 access, i.e. without refill. Then it returns.
1430 */ 1451 */
1431static void __init 1452static void __init
1432build_r3000_tlb_write(u32 **p, struct label **l, struct reloc **r, 1453build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r,
1433 unsigned int tmp) 1454 unsigned int pte, unsigned int tmp)
1434{ 1455{
1435 i_mfc0(p, tmp, C0_INDEX); 1456 i_mfc0(p, tmp, C0_INDEX);
1436 i_nop(p); /* cp0 delay */ 1457 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1437 il_bltz(p, r, tmp, label_r3000_write_probe_fail); 1458 il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1438 i_nop(p); /* branch delay */ 1459 i_mfc0(p, tmp, C0_EPC); /* branch delay */
1439 i_tlbwi(p); 1460 i_tlbwi(p); /* cp0 delay */
1440 il_b(p, r, label_r3000_write_probe_ok); 1461 i_jr(p, tmp);
1441 i_nop(p); /* branch delay */ 1462 i_rfe(p); /* branch delay */
1442 l_r3000_write_probe_fail(l, *p); 1463 l_r3000_write_probe_fail(l, *p);
1443 i_tlbwr(p); 1464 i_tlbwr(p); /* cp0 delay */
1444 l_r3000_write_probe_ok(l, *p); 1465 i_jr(p, tmp);
1466 i_rfe(p); /* branch delay */
1445} 1467}
1446 1468
1447static void __init 1469static void __init
@@ -1461,17 +1483,7 @@ build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1461 i_andi(p, pte, pte, 0xffc); /* load delay */ 1483 i_andi(p, pte, pte, 0xffc); /* load delay */
1462 i_addu(p, ptr, ptr, pte); 1484 i_addu(p, ptr, ptr, pte);
1463 i_lw(p, pte, 0, ptr); 1485 i_lw(p, pte, 0, ptr);
1464 i_nop(p); /* load delay */ 1486 i_tlbp(p); /* load delay */
1465 i_tlbp(p);
1466}
1467
1468static void __init
1469build_r3000_tlbchange_handler_tail(u32 **p, unsigned int tmp)
1470{
1471 i_mfc0(p, tmp, C0_EPC);
1472 i_nop(p); /* cp0 delay */
1473 i_jr(p, tmp);
1474 i_rfe(p); /* branch delay */
1475} 1487}
1476 1488
1477static void __init build_r3000_tlb_load_handler(void) 1489static void __init build_r3000_tlb_load_handler(void)
@@ -1486,10 +1498,9 @@ static void __init build_r3000_tlb_load_handler(void)
1486 1498
1487 build_r3000_tlbchange_handler_head(&p, K0, K1); 1499 build_r3000_tlbchange_handler_head(&p, K0, K1);
1488 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1500 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
1501 i_nop(&p); /* load delay */
1489 build_make_valid(&p, &r, K0, K1); 1502 build_make_valid(&p, &r, K0, K1);
1490 build_r3000_pte_reload(&p, K1); 1503 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1491 build_r3000_tlb_write(&p, &l, &r, K0);
1492 build_r3000_tlbchange_handler_tail(&p, K0);
1493 1504
1494 l_nopage_tlbl(&l, p); 1505 l_nopage_tlbl(&l, p);
1495 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1506 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
@@ -1506,13 +1517,10 @@ static void __init build_r3000_tlb_load_handler(void)
1506 { 1517 {
1507 int i; 1518 int i;
1508 1519
1509 for (i = 0; i < FASTPATH_SIZE; i++) 1520 for (i = 0; i < (p - handle_tlbl); i++)
1510 printk("%08x\n", handle_tlbl[i]); 1521 printk("%08x\n", handle_tlbl[i]);
1511 } 1522 }
1512#endif 1523#endif
1513
1514 flush_icache_range((unsigned long)handle_tlbl,
1515 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
1516} 1524}
1517 1525
1518static void __init build_r3000_tlb_store_handler(void) 1526static void __init build_r3000_tlb_store_handler(void)
@@ -1527,10 +1535,9 @@ static void __init build_r3000_tlb_store_handler(void)
1527 1535
1528 build_r3000_tlbchange_handler_head(&p, K0, K1); 1536 build_r3000_tlbchange_handler_head(&p, K0, K1);
1529 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1537 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
1538 i_nop(&p); /* load delay */
1530 build_make_write(&p, &r, K0, K1); 1539 build_make_write(&p, &r, K0, K1);
1531 build_r3000_pte_reload(&p, K1); 1540 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1532 build_r3000_tlb_write(&p, &l, &r, K0);
1533 build_r3000_tlbchange_handler_tail(&p, K0);
1534 1541
1535 l_nopage_tlbs(&l, p); 1542 l_nopage_tlbs(&l, p);
1536 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1543 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
@@ -1547,13 +1554,10 @@ static void __init build_r3000_tlb_store_handler(void)
1547 { 1554 {
1548 int i; 1555 int i;
1549 1556
1550 for (i = 0; i < FASTPATH_SIZE; i++) 1557 for (i = 0; i < (p - handle_tlbs); i++)
1551 printk("%08x\n", handle_tlbs[i]); 1558 printk("%08x\n", handle_tlbs[i]);
1552 } 1559 }
1553#endif 1560#endif
1554
1555 flush_icache_range((unsigned long)handle_tlbs,
1556 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
1557} 1561}
1558 1562
1559static void __init build_r3000_tlb_modify_handler(void) 1563static void __init build_r3000_tlb_modify_handler(void)
@@ -1568,10 +1572,9 @@ static void __init build_r3000_tlb_modify_handler(void)
1568 1572
1569 build_r3000_tlbchange_handler_head(&p, K0, K1); 1573 build_r3000_tlbchange_handler_head(&p, K0, K1);
1570 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1574 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
1575 i_nop(&p); /* load delay */
1571 build_make_write(&p, &r, K0, K1); 1576 build_make_write(&p, &r, K0, K1);
1572 build_r3000_pte_reload(&p, K1); 1577 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1573 i_tlbwi(&p);
1574 build_r3000_tlbchange_handler_tail(&p, K0);
1575 1578
1576 l_nopage_tlbm(&l, p); 1579 l_nopage_tlbm(&l, p);
1577 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1580 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
@@ -1588,13 +1591,10 @@ static void __init build_r3000_tlb_modify_handler(void)
1588 { 1591 {
1589 int i; 1592 int i;
1590 1593
1591 for (i = 0; i < FASTPATH_SIZE; i++) 1594 for (i = 0; i < (p - handle_tlbm); i++)
1592 printk("%08x\n", handle_tlbm[i]); 1595 printk("%08x\n", handle_tlbm[i]);
1593 } 1596 }
1594#endif 1597#endif
1595
1596 flush_icache_range((unsigned long)handle_tlbm,
1597 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
1598} 1598}
1599 1599
1600/* 1600/*
@@ -1620,7 +1620,7 @@ build_r4000_tlbchange_handler_head(u32 **p, struct label **l,
1620#ifdef CONFIG_SMP 1620#ifdef CONFIG_SMP
1621 l_smp_pgtable_change(l, *p); 1621 l_smp_pgtable_change(l, *p);
1622# endif 1622# endif
1623 iPTE_LW(p, l, pte, 0, ptr); /* get even pte */ 1623 iPTE_LW(p, l, pte, ptr); /* get even pte */
1624 build_tlb_probe_entry(p); 1624 build_tlb_probe_entry(p);
1625} 1625}
1626 1626
@@ -1680,13 +1680,10 @@ static void __init build_r4000_tlb_load_handler(void)
1680 { 1680 {
1681 int i; 1681 int i;
1682 1682
1683 for (i = 0; i < FASTPATH_SIZE; i++) 1683 for (i = 0; i < (p - handle_tlbl); i++)
1684 printk("%08x\n", handle_tlbl[i]); 1684 printk("%08x\n", handle_tlbl[i]);
1685 } 1685 }
1686#endif 1686#endif
1687
1688 flush_icache_range((unsigned long)handle_tlbl,
1689 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
1690} 1687}
1691 1688
1692static void __init build_r4000_tlb_store_handler(void) 1689static void __init build_r4000_tlb_store_handler(void)
@@ -1719,13 +1716,10 @@ static void __init build_r4000_tlb_store_handler(void)
1719 { 1716 {
1720 int i; 1717 int i;
1721 1718
1722 for (i = 0; i < FASTPATH_SIZE; i++) 1719 for (i = 0; i < (p - handle_tlbs); i++)
1723 printk("%08x\n", handle_tlbs[i]); 1720 printk("%08x\n", handle_tlbs[i]);
1724 } 1721 }
1725#endif 1722#endif
1726
1727 flush_icache_range((unsigned long)handle_tlbs,
1728 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
1729} 1723}
1730 1724
1731static void __init build_r4000_tlb_modify_handler(void) 1725static void __init build_r4000_tlb_modify_handler(void)
@@ -1759,13 +1753,10 @@ static void __init build_r4000_tlb_modify_handler(void)
1759 { 1753 {
1760 int i; 1754 int i;
1761 1755
1762 for (i = 0; i < FASTPATH_SIZE; i++) 1756 for (i = 0; i < (p - handle_tlbm); i++)
1763 printk("%08x\n", handle_tlbm[i]); 1757 printk("%08x\n", handle_tlbm[i]);
1764 } 1758 }
1765#endif 1759#endif
1766
1767 flush_icache_range((unsigned long)handle_tlbm,
1768 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
1769} 1760}
1770 1761
1771void __init build_tlb_refill_handler(void) 1762void __init build_tlb_refill_handler(void)
@@ -1813,3 +1804,13 @@ void __init build_tlb_refill_handler(void)
1813 } 1804 }
1814 } 1805 }
1815} 1806}
1807
1808void __init flush_tlb_handlers(void)
1809{
1810 flush_icache_range((unsigned long)handle_tlbl,
1811 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
1812 flush_icache_range((unsigned long)handle_tlbs,
1813 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
1814 flush_icache_range((unsigned long)handle_tlbm,
1815 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
1816}
diff --git a/arch/mips/momentum/Kconfig b/arch/mips/momentum/Kconfig
new file mode 100644
index 000000000000..70a61cf7174d
--- /dev/null
+++ b/arch/mips/momentum/Kconfig
@@ -0,0 +1,6 @@
1config JAGUAR_DMALOW
2 bool "Low DMA Mode"
3 depends on MOMENCO_JAGUAR_ATX
4 help
5 Select to Y if jump JP5 is set on your board, N otherwise. Normally
6 the jumper is set, so if you feel unsafe, just say Y.
diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c
index 14ae2e713585..aae7a802767a 100644
--- a/arch/mips/momentum/jaguar_atx/prom.c
+++ b/arch/mips/momentum/jaguar_atx/prom.c
@@ -236,8 +236,9 @@ void __init prom_init(void)
236#endif 236#endif
237} 237}
238 238
239void __init prom_free_prom_memory(void) 239unsigned long __init prom_free_prom_memory(void)
240{ 240{
241 return 0;
241} 242}
242 243
243void __init prom_fixup_mem_map(unsigned long start, unsigned long end) 244void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
index 90288cf2b1e0..768bf4406452 100644
--- a/arch/mips/momentum/jaguar_atx/setup.c
+++ b/arch/mips/momentum/jaguar_atx/setup.c
@@ -351,7 +351,7 @@ static __init int __init ja_pci_init(void)
351 351
352arch_initcall(ja_pci_init); 352arch_initcall(ja_pci_init);
353 353
354static int __init momenco_jaguar_atx_setup(void) 354void __init plat_setup(void)
355{ 355{
356 unsigned int tmpword; 356 unsigned int tmpword;
357 357
@@ -467,8 +467,4 @@ static int __init momenco_jaguar_atx_setup(void)
467 467
468 } 468 }
469#endif 469#endif
470
471 return 0;
472} 470}
473
474early_initcall(momenco_jaguar_atx_setup);
diff --git a/arch/mips/momentum/ocelot_3/prom.c b/arch/mips/momentum/ocelot_3/prom.c
index c4fa9c525faa..9803daa2a792 100644
--- a/arch/mips/momentum/ocelot_3/prom.c
+++ b/arch/mips/momentum/ocelot_3/prom.c
@@ -239,8 +239,9 @@ void __init prom_init(void)
239#endif 239#endif
240} 240}
241 241
242void __init prom_free_prom_memory(void) 242unsigned long __init prom_free_prom_memory(void)
243{ 243{
244 return 0;
244} 245}
245 246
246void __init prom_fixup_mem_map(unsigned long start, unsigned long end) 247void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c
index ce2efcbab7aa..a7803e08f9db 100644
--- a/arch/mips/momentum/ocelot_3/setup.c
+++ b/arch/mips/momentum/ocelot_3/setup.c
@@ -307,7 +307,7 @@ static __init int __init ja_pci_init(void)
307 307
308arch_initcall(ja_pci_init); 308arch_initcall(ja_pci_init);
309 309
310static int __init momenco_ocelot_3_setup(void) 310void __init plat_setup(void)
311{ 311{
312 unsigned int tmpword; 312 unsigned int tmpword;
313 313
@@ -391,8 +391,4 @@ static int __init momenco_ocelot_3_setup(void)
391 391
392 /* Support for 128 MB memory */ 392 /* Support for 128 MB memory */
393 add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM); 393 add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM);
394
395 return 0;
396} 394}
397
398early_initcall(momenco_ocelot_3_setup);
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index dea48b3ad687..bd885785e2f9 100644
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -129,14 +129,13 @@ void ll_cpci_irq(struct pt_regs *regs)
129#define shutdown_cpci_irq disable_cpci_irq 129#define shutdown_cpci_irq disable_cpci_irq
130 130
131struct hw_interrupt_type cpci_irq_type = { 131struct hw_interrupt_type cpci_irq_type = {
132 "CPCI/FPGA", 132 .typename = "CPCI/FPGA",
133 startup_cpci_irq, 133 .startup = startup_cpci_irq,
134 shutdown_cpci_irq, 134 .shutdown = shutdown_cpci_irq,
135 enable_cpci_irq, 135 .enable = enable_cpci_irq,
136 disable_cpci_irq, 136 .disable = disable_cpci_irq,
137 mask_and_ack_cpci_irq, 137 .ack = mask_and_ack_cpci_irq,
138 end_cpci_irq, 138 .end = end_cpci_irq,
139 NULL
140}; 139};
141 140
142void cpci_irq_init(void) 141void cpci_irq_init(void)
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c
index 844ddd06349b..ce70fc96f160 100644
--- a/arch/mips/momentum/ocelot_c/setup.c
+++ b/arch/mips/momentum/ocelot_c/setup.c
@@ -222,7 +222,7 @@ void momenco_time_init(void)
222 rtc_set_time = m48t37y_set_time; 222 rtc_set_time = m48t37y_set_time;
223} 223}
224 224
225static void __init momenco_ocelot_c_setup(void) 225void __init plat_setup(void)
226{ 226{
227 unsigned int tmpword; 227 unsigned int tmpword;
228 228
@@ -340,8 +340,6 @@ static void __init momenco_ocelot_c_setup(void)
340 } 340 }
341} 341}
342 342
343early_initcall(momenco_ocelot_c_setup);
344
345#ifndef CONFIG_64BIT 343#ifndef CONFIG_64BIT
346/* This needs to be one of the first initcalls, because no I/O port access 344/* This needs to be one of the first initcalls, because no I/O port access
347 can work before this */ 345 can work before this */
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index ebe1507b17df..755bde5146be 100644
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -122,14 +122,13 @@ void ll_uart_irq(struct pt_regs *regs)
122#define shutdown_uart_irq disable_uart_irq 122#define shutdown_uart_irq disable_uart_irq
123 123
124struct hw_interrupt_type uart_irq_type = { 124struct hw_interrupt_type uart_irq_type = {
125 "UART/FPGA", 125 .typename = "UART/FPGA",
126 startup_uart_irq, 126 .startup = startup_uart_irq,
127 shutdown_uart_irq, 127 .shutdown = shutdown_uart_irq,
128 enable_uart_irq, 128 .enable = enable_uart_irq,
129 disable_uart_irq, 129 .disable = disable_uart_irq,
130 mask_and_ack_uart_irq, 130 .ack = mask_and_ack_uart_irq,
131 end_uart_irq, 131 .end = end_uart_irq,
132 NULL
133}; 132};
134 133
135void uart_irq_init(void) 134void uart_irq_init(void)
diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c
index 38a78ab8c830..6336751391c3 100644
--- a/arch/mips/momentum/ocelot_g/setup.c
+++ b/arch/mips/momentum/ocelot_g/setup.c
@@ -160,7 +160,7 @@ static void __init setup_l3cache(unsigned long size)
160 printk("Done\n"); 160 printk("Done\n");
161} 161}
162 162
163static int __init momenco_ocelot_g_setup(void) 163void __init plat_setup(void)
164{ 164{
165 void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache); 165 void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
166 unsigned int tmpword; 166 unsigned int tmpword;
@@ -240,12 +240,8 @@ static int __init momenco_ocelot_g_setup(void)
240 240
241 /* FIXME: Fix up the DiskOnChip mapping */ 241 /* FIXME: Fix up the DiskOnChip mapping */
242 MV_WRITE(0x468, 0xfef73); 242 MV_WRITE(0x468, 0xfef73);
243
244 return 0;
245} 243}
246 244
247early_initcall(momenco_ocelot_g_setup);
248
249/* This needs to be one of the first initcalls, because no I/O port access 245/* This needs to be one of the first initcalls, because no I/O port access
250 can work before this */ 246 can work before this */
251 247
diff --git a/arch/mips/oprofile/Kconfig b/arch/mips/oprofile/Kconfig
index 19d37730b664..55feaf798596 100644
--- a/arch/mips/oprofile/Kconfig
+++ b/arch/mips/oprofile/Kconfig
@@ -11,7 +11,7 @@ config PROFILING
11 11
12config OPROFILE 12config OPROFILE
13 tristate "OProfile system profiling (EXPERIMENTAL)" 13 tristate "OProfile system profiling (EXPERIMENTAL)"
14 depends on PROFILING 14 depends on PROFILING && EXPERIMENTAL
15 help 15 help
16 OProfile is a profiling system capable of profiling the 16 OProfile is a profiling system capable of profiling the
17 whole system, include the kernel, kernel modules, libraries, 17 whole system, include the kernel, kernel modules, libraries,
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index ab65ce3d471a..dd2cc42f1b6d 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -3,7 +3,8 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2004 by Ralf Baechle 6 * Copyright (C) 2004, 2005 Ralf Baechle
7 * Copyright (C) 2005 MIPS Technologies, Inc.
7 */ 8 */
8#include <linux/errno.h> 9#include <linux/errno.h>
9#include <linux/init.h> 10#include <linux/init.h>
@@ -45,10 +46,10 @@ static int op_mips_create_files(struct super_block * sb, struct dentry * root)
45 oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled); 46 oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled);
46 oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event); 47 oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event);
47 oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count); 48 oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count);
48 /* Dummies. */
49 oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel); 49 oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel);
50 oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user); 50 oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user);
51 oprofilefs_create_ulong(sb, dir, "exl", &ctr[i].exl); 51 oprofilefs_create_ulong(sb, dir, "exl", &ctr[i].exl);
52 /* Dummy. */
52 oprofilefs_create_ulong(sb, dir, "unit_mask", &ctr[i].unit_mask); 53 oprofilefs_create_ulong(sb, dir, "unit_mask", &ctr[i].unit_mask);
53 } 54 }
54 55
@@ -68,9 +69,10 @@ static void op_mips_stop(void)
68 on_each_cpu(model->cpu_stop, NULL, 0, 1); 69 on_each_cpu(model->cpu_stop, NULL, 0, 1);
69} 70}
70 71
71void __init oprofile_arch_init(struct oprofile_operations *ops) 72int __init oprofile_arch_init(struct oprofile_operations *ops)
72{ 73{
73 struct op_mips_model *lmodel = NULL; 74 struct op_mips_model *lmodel = NULL;
75 int res;
74 76
75 switch (current_cpu_data.cputype) { 77 switch (current_cpu_data.cputype) {
76 case CPU_24K: 78 case CPU_24K:
@@ -83,21 +85,25 @@ void __init oprofile_arch_init(struct oprofile_operations *ops)
83 }; 85 };
84 86
85 if (!lmodel) 87 if (!lmodel)
86 return; 88 return -ENODEV;
87 89
88 if (lmodel->init()) 90 res = lmodel->init();
89 return; 91 if (res)
92 return res;
90 93
91 model = lmodel; 94 model = lmodel;
92 95
93 ops->create_files = op_mips_create_files; 96 ops->create_files = op_mips_create_files;
94 ops->setup = op_mips_setup; 97 ops->setup = op_mips_setup;
95 ops->start = op_mips_start; 98 //ops->shutdown = op_mips_shutdown;
96 ops->stop = op_mips_stop; 99 ops->start = op_mips_start;
97 ops->cpu_type = lmodel->cpu_type; 100 ops->stop = op_mips_stop;
101 ops->cpu_type = lmodel->cpu_type;
98 102
99 printk(KERN_INFO "oprofile: using %s performance monitoring.\n", 103 printk(KERN_INFO "oprofile: using %s performance monitoring.\n",
100 lmodel->cpu_type); 104 lmodel->cpu_type);
105
106 return 0;
101} 107}
102 108
103void oprofile_arch_exit(void) 109void oprofile_arch_exit(void)
diff --git a/arch/mips/oprofile/op_impl.h b/arch/mips/oprofile/op_impl.h
index 9f5cdff041be..f0121557047d 100644
--- a/arch/mips/oprofile/op_impl.h
+++ b/arch/mips/oprofile/op_impl.h
@@ -10,6 +10,11 @@
10#ifndef OP_IMPL_H 10#ifndef OP_IMPL_H
11#define OP_IMPL_H 1 11#define OP_IMPL_H 1
12 12
13struct pt_regs;
14
15extern void null_perf_irq(struct pt_regs *regs);
16extern void (*perf_irq)(struct pt_regs *regs);
17
13/* Per-counter configuration as set via oprofilefs. */ 18/* Per-counter configuration as set via oprofilefs. */
14struct op_counter_config { 19struct op_counter_config {
15 unsigned long enabled; 20 unsigned long enabled;
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
new file mode 100644
index 000000000000..d36b64dfcb2f
--- /dev/null
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -0,0 +1,215 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004, 2005 by Ralf Baechle
7 * Copyright (C) 2005 by MIPS Technologies, Inc.
8 */
9#include <linux/oprofile.h>
10#include <linux/interrupt.h>
11#include <linux/smp.h>
12
13#include "op_impl.h"
14
15#define M_PERFCTL_EXL (1UL << 0)
16#define M_PERFCTL_KERNEL (1UL << 1)
17#define M_PERFCTL_SUPERVISOR (1UL << 2)
18#define M_PERFCTL_USER (1UL << 3)
19#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
20#define M_PERFCTL_EVENT(event) ((event) << 5)
21#define M_PERFCTL_WIDE (1UL << 30)
22#define M_PERFCTL_MORE (1UL << 31)
23
24#define M_COUNTER_OVERFLOW (1UL << 31)
25
26struct op_mips_model op_model_mipsxx;
27
28static struct mipsxx_register_config {
29 unsigned int control[4];
30 unsigned int counter[4];
31} reg;
32
33/* Compute all of the registers in preparation for enabling profiling. */
34
35static void mipsxx_reg_setup(struct op_counter_config *ctr)
36{
37 unsigned int counters = op_model_mipsxx.num_counters;
38 int i;
39
40 /* Compute the performance counter control word. */
41 /* For now count kernel and user mode */
42 for (i = 0; i < counters; i++) {
43 reg.control[i] = 0;
44 reg.counter[i] = 0;
45
46 if (!ctr[i].enabled)
47 continue;
48
49 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
50 M_PERFCTL_INTERRUPT_ENABLE;
51 if (ctr[i].kernel)
52 reg.control[i] |= M_PERFCTL_KERNEL;
53 if (ctr[i].user)
54 reg.control[i] |= M_PERFCTL_USER;
55 if (ctr[i].exl)
56 reg.control[i] |= M_PERFCTL_EXL;
57 reg.counter[i] = 0x80000000 - ctr[i].count;
58 }
59}
60
61/* Program all of the registers in preparation for enabling profiling. */
62
63static void mipsxx_cpu_setup (void *args)
64{
65 unsigned int counters = op_model_mipsxx.num_counters;
66
67 switch (counters) {
68 case 4:
69 write_c0_perfctrl3(0);
70 write_c0_perfcntr3(reg.counter[3]);
71 case 3:
72 write_c0_perfctrl2(0);
73 write_c0_perfcntr2(reg.counter[2]);
74 case 2:
75 write_c0_perfctrl1(0);
76 write_c0_perfcntr1(reg.counter[1]);
77 case 1:
78 write_c0_perfctrl0(0);
79 write_c0_perfcntr0(reg.counter[0]);
80 }
81}
82
83/* Start all counters on current CPU */
84static void mipsxx_cpu_start(void *args)
85{
86 unsigned int counters = op_model_mipsxx.num_counters;
87
88 switch (counters) {
89 case 4:
90 write_c0_perfctrl3(reg.control[3]);
91 case 3:
92 write_c0_perfctrl2(reg.control[2]);
93 case 2:
94 write_c0_perfctrl1(reg.control[1]);
95 case 1:
96 write_c0_perfctrl0(reg.control[0]);
97 }
98}
99
100/* Stop all counters on current CPU */
101static void mipsxx_cpu_stop(void *args)
102{
103 unsigned int counters = op_model_mipsxx.num_counters;
104
105 switch (counters) {
106 case 4:
107 write_c0_perfctrl3(0);
108 case 3:
109 write_c0_perfctrl2(0);
110 case 2:
111 write_c0_perfctrl1(0);
112 case 1:
113 write_c0_perfctrl0(0);
114 }
115}
116
117static void mipsxx_perfcount_handler(struct pt_regs *regs)
118{
119 unsigned int counters = op_model_mipsxx.num_counters;
120 unsigned int control;
121 unsigned int counter;
122
123 switch (counters) {
124#define HANDLE_COUNTER(n) \
125 case n + 1: \
126 control = read_c0_perfctrl ## n(); \
127 counter = read_c0_perfcntr ## n(); \
128 if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
129 (counter & M_COUNTER_OVERFLOW)) { \
130 oprofile_add_sample(regs, n); \
131 write_c0_perfcntr ## n(reg.counter[n]); \
132 }
133 HANDLE_COUNTER(3)
134 HANDLE_COUNTER(2)
135 HANDLE_COUNTER(1)
136 HANDLE_COUNTER(0)
137 }
138}
139
140#define M_CONFIG1_PC (1 << 4)
141
142static inline int n_counters(void)
143{
144 if (!(read_c0_config1() & M_CONFIG1_PC))
145 return 0;
146 if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
147 return 1;
148 if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
149 return 2;
150 if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
151 return 3;
152
153 return 4;
154}
155
156static inline void reset_counters(int counters)
157{
158 switch (counters) {
159 case 4:
160 write_c0_perfctrl3(0);
161 write_c0_perfcntr3(0);
162 case 3:
163 write_c0_perfctrl2(0);
164 write_c0_perfcntr2(0);
165 case 2:
166 write_c0_perfctrl1(0);
167 write_c0_perfcntr1(0);
168 case 1:
169 write_c0_perfctrl0(0);
170 write_c0_perfcntr0(0);
171 }
172}
173
174static int __init mipsxx_init(void)
175{
176 int counters;
177
178 counters = n_counters();
179 if (counters == 0)
180 return -ENODEV;
181
182 reset_counters(counters);
183
184 op_model_mipsxx.num_counters = counters;
185 switch (current_cpu_data.cputype) {
186 case CPU_24K:
187 op_model_mipsxx.cpu_type = "mips/24K";
188 break;
189
190 default:
191 printk(KERN_ERR "Profiling unsupported for this CPU\n");
192
193 return -ENODEV;
194 }
195
196 perf_irq = mipsxx_perfcount_handler;
197
198 return 0;
199}
200
201static void mipsxx_exit(void)
202{
203 reset_counters(op_model_mipsxx.num_counters);
204
205 perf_irq = null_perf_irq;
206}
207
208struct op_mips_model op_model_mipsxx = {
209 .reg_setup = mipsxx_reg_setup,
210 .cpu_setup = mipsxx_cpu_setup,
211 .init = mipsxx_init,
212 .exit = mipsxx_exit,
213 .cpu_start = mipsxx_cpu_start,
214 .cpu_stop = mipsxx_cpu_stop,
215};
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
index bee47793cb1a..9b75e41c78ef 100644
--- a/arch/mips/oprofile/op_model_rm9000.c
+++ b/arch/mips/oprofile/op_model_rm9000.c
@@ -5,6 +5,7 @@
5 * 5 *
6 * Copyright (C) 2004 by Ralf Baechle 6 * Copyright (C) 2004 by Ralf Baechle
7 */ 7 */
8#include <linux/init.h>
8#include <linux/oprofile.h> 9#include <linux/oprofile.h>
9#include <linux/interrupt.h> 10#include <linux/interrupt.h>
10#include <linux/smp.h> 11#include <linux/smp.h>
@@ -114,7 +115,7 @@ static irqreturn_t rm9000_perfcount_handler(int irq, void * dev_id,
114 return IRQ_HANDLED; 115 return IRQ_HANDLED;
115} 116}
116 117
117static int rm9000_init(void) 118static int __init rm9000_init(void)
118{ 119{
119 return request_irq(rm9000_perfcount_irq, rm9000_perfcount_handler, 120 return request_irq(rm9000_perfcount_irq, rm9000_perfcount_handler,
120 0, "Perfcounter", NULL); 121 0, "Perfcounter", NULL);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 83d81c9cdc2b..7b7468304022 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_MIPS_ITE8172) += fixup-ite8172g.o
34obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o 34obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o
35obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 35obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
36obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 36obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
37obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
37obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 38obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
38obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o 39obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o
39obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o 40obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
@@ -45,11 +46,13 @@ obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
45obj-$(CONFIG_SGI_IP27) += pci-ip27.o 46obj-$(CONFIG_SGI_IP27) += pci-ip27.o
46obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o 47obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o
47obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o 48obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
49obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
48obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o 50obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o
49obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o 51obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
50obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o 52obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
51obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o 53obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
52obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o 54obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o
53obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o 55obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o
56obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
54obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 57obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
55obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 58obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c
index 2406835833d6..87920b245931 100644
--- a/arch/mips/pci/fixup-atlas.c
+++ b/arch/mips/pci/fixup-atlas.c
@@ -1,14 +1,37 @@
1/*
2 * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
3 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
4 * Author: Maciej W. Rozycki <macro@mips.com>
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 */
1#include <linux/config.h> 19#include <linux/config.h>
2#include <linux/init.h> 20#include <linux/init.h>
3#include <linux/pci.h> 21#include <linux/pci.h>
22
4#include <asm/mips-boards/atlasint.h> 23#include <asm/mips-boards/atlasint.h>
5 24
6#define INTD ATLASINT_INTD 25#define PCIA ATLASINT_PCIA
7#define INTC ATLASINT_INTC 26#define PCIB ATLASINT_PCIB
8#define INTB ATLASINT_INTB 27#define PCIC ATLASINT_PCIC
28#define PCID ATLASINT_PCID
9#define INTA ATLASINT_INTA 29#define INTA ATLASINT_INTA
10#define SCSI ATLASINT_SCSI 30#define INTB ATLASINT_INTB
11#define ETH ATLASINT_ETH 31#define ETH ATLASINT_ETH
32#define INTC ATLASINT_INTC
33#define SCSI ATLASINT_SCSI
34#define INTD ATLASINT_INTD
12 35
13static char irq_tab[][5] __initdata = { 36static char irq_tab[][5] __initdata = {
14 /* INTA INTB INTC INTD */ 37 /* INTA INTB INTC INTD */
@@ -27,13 +50,13 @@ static char irq_tab[][5] __initdata = {
27 {0, 0, 0, 0, 0 }, /* 12: Unused */ 50 {0, 0, 0, 0, 0 }, /* 12: Unused */
28 {0, 0, 0, 0, 0 }, /* 13: Unused */ 51 {0, 0, 0, 0, 0 }, /* 13: Unused */
29 {0, 0, 0, 0, 0 }, /* 14: Unused */ 52 {0, 0, 0, 0, 0 }, /* 14: Unused */
30 {0, 0, 0, 0, 0 }, /* 15: Unused */ 53 {0, PCIA, PCIB, PCIC, PCID }, /* 15: cPCI (behind 21150) */
31 {0, SCSI, 0, 0, 0 }, /* 16: SYM53C810A SCSI */ 54 {0, SCSI, 0, 0, 0 }, /* 16: SYM53C810A SCSI */
32 {0, 0, 0, 0, 0 }, /* 17: Core */ 55 {0, 0, 0, 0, 0 }, /* 17: Core */
33 {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot 1 */ 56 {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot */
34 {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Ethernet */ 57 {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Eth. et al. */
35 {0, 0, 0, 0, 0 }, /* 20: PCI Slot 3 */ 58 {0, 0, 0, 0, 0 }, /* 20: Unused */
36 {0, 0, 0, 0, 0 } /* 21: PCI Slot 4 */ 59 {0, 0, 0, 0, 0 } /* 21: Unused */
37}; 60};
38 61
39int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 62int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c
index 39fe2b16fcec..c2f8304fe55b 100644
--- a/arch/mips/pci/fixup-au1000.c
+++ b/arch/mips/pci/fixup-au1000.c
@@ -26,7 +26,6 @@
26 * with this program; if not, write to the Free Software Foundation, Inc., 26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */ 28 */
29#include <linux/config.h>
30#include <linux/types.h> 29#include <linux/types.h>
31#include <linux/pci.h> 30#include <linux/pci.h>
32#include <linux/kernel.h> 31#include <linux/kernel.h>
@@ -34,82 +33,7 @@
34 33
35#include <asm/mach-au1x00/au1000.h> 34#include <asm/mach-au1x00/au1000.h>
36 35
37/* 36extern char irq_tab_alchemy[][5];
38 * Shortcut
39 */
40#ifdef CONFIG_SOC_AU1500
41#define INTA AU1000_PCI_INTA
42#define INTB AU1000_PCI_INTB
43#define INTC AU1000_PCI_INTC
44#define INTD AU1000_PCI_INTD
45#endif
46
47#ifdef CONFIG_SOC_AU1550
48#define INTA AU1550_PCI_INTA
49#define INTB AU1550_PCI_INTB
50#define INTC AU1550_PCI_INTC
51#define INTD AU1550_PCI_INTD
52#endif
53
54#define INTX 0xFF /* not valid */
55
56#ifdef CONFIG_MIPS_DB1500
57static char irq_tab_alchemy[][5] __initdata = {
58 [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT371 */
59 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
60};
61#endif
62
63#ifdef CONFIG_MIPS_BOSPORUS
64static char irq_tab_alchemy[][5] __initdata = {
65 [11] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 11 - miniPCI */
66 [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - SN1741 */
67 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
68};
69#endif
70
71#ifdef CONFIG_MIPS_MIRAGE
72static char irq_tab_alchemy[][5] __initdata = {
73 [11] = { -1, INTD, INTX, INTX, INTX}, /* IDSEL 11 - SMI VGX */
74 [12] = { -1, INTX, INTX, INTC, INTX}, /* IDSEL 12 - PNX1300 */
75 [13] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 13 - miniPCI */
76};
77#endif
78
79#ifdef CONFIG_MIPS_DB1550
80static char irq_tab_alchemy[][5] __initdata = {
81 [11] = { -1, INTC, INTX, INTX, INTX}, /* IDSEL 11 - on-board HPT371 */
82 [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
83 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
84};
85#endif
86
87#ifdef CONFIG_MIPS_PB1500
88static char irq_tab_alchemy[][5] __initdata = {
89 [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT370 */
90 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
91};
92#endif
93
94#ifdef CONFIG_MIPS_PB1550
95static char irq_tab_alchemy[][5] __initdata = {
96 [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
97 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
98};
99#endif
100
101#ifdef CONFIG_MIPS_MTX1
102static char irq_tab_alchemy[][5] __initdata = {
103 [0] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */
104 [1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
105 [2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */
106 [3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
107 [4] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 04 - AdapterC-Slot0 (top) */
108 [5] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
109 [6] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 06 - AdapterD-Slot0 (top) */
110 [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
111};
112#endif
113 37
114int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 38int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
115{ 39{
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 57e1ca2116bb..909292f50d06 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -21,6 +21,20 @@
21 21
22extern int cobalt_board_id; 22extern int cobalt_board_id;
23 23
24static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
25{
26 if (dev->devfn == PCI_DEVFN(0, 0) &&
27 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
28
29 dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
30
31 printk(KERN_INFO "Galileo: fixed bridge class\n");
32 }
33}
34
35DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
36 qube_raq_galileo_early_fixup);
37
24static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) 38static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
25{ 39{
26 unsigned short cfgword; 40 unsigned short cfgword;
@@ -48,6 +62,9 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
48{ 62{
49 unsigned short galileo_id; 63 unsigned short galileo_id;
50 64
65 if (dev->devfn != PCI_DEVFN(0, 0))
66 return;
67
51 /* Fix PCI latency-timer and cache-line-size values in Galileo 68 /* Fix PCI latency-timer and cache-line-size values in Galileo
52 * host bridge. 69 * host bridge.
53 */ 70 */
@@ -55,6 +72,13 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
55 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); 72 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
56 73
57 /* 74 /*
75 * The code described by the comment below has been removed
76 * as it causes bus mastering by the Ethernet controllers
77 * to break under any kind of network load. We always set
78 * the retry timeouts to their maximum.
79 *
80 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
81 *
58 * On all machines prior to Q2, we had the STOP line disconnected 82 * On all machines prior to Q2, we had the STOP line disconnected
59 * from Galileo to VIA on PCI. The new Galileo does not function 83 * from Galileo to VIA on PCI. The new Galileo does not function
60 * correctly unless we have it connected. 84 * correctly unless we have it connected.
@@ -64,21 +88,43 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
64 */ 88 */
65 pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id); 89 pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
66 galileo_id &= 0xff; /* mask off class info */ 90 galileo_id &= 0xff; /* mask off class info */
91
92 printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
93
94#if 0
67 if (galileo_id >= 0x10) { 95 if (galileo_id >= 0x10) {
68 /* New Galileo, assumes PCI stop line to VIA is connected. */ 96 /* New Galileo, assumes PCI stop line to VIA is connected. */
69 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); 97 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
70 } else if (galileo_id == 0x1 || galileo_id == 0x2) { 98 } else if (galileo_id == 0x1 || galileo_id == 0x2)
99#endif
100 {
71 signed int timeo; 101 signed int timeo;
72 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ 102 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
73 timeo = GALILEO_INL(GT_PCI0_TOR_OFS); 103 timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
74 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ 104 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
75 GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS); 105 GALILEO_OUTL(
106 (0xff << 16) | /* retry count */
107 (0xff << 8) | /* timeout 1 */
108 0xff, /* timeout 0 */
109 GT_PCI0_TOR_OFS);
110
111 /* enable PCI retry exceeded interrupt */
112 GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
76 } 113 }
77} 114}
78 115
79DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, 116DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
80 qube_raq_galileo_fixup); 117 qube_raq_galileo_fixup);
81 118
119static char irq_tab_qube1[] __initdata = {
120 [COBALT_PCICONF_CPU] = 0,
121 [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ,
122 [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
123 [COBALT_PCICONF_VIA] = 0,
124 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
125 [COBALT_PCICONF_ETH1] = 0
126};
127
82static char irq_tab_cobalt[] __initdata = { 128static char irq_tab_cobalt[] __initdata = {
83 [COBALT_PCICONF_CPU] = 0, 129 [COBALT_PCICONF_CPU] = 0,
84 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, 130 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
@@ -99,6 +145,9 @@ static char irq_tab_raq2[] __initdata = {
99 145
100int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 146int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
101{ 147{
148 if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
149 return irq_tab_qube1[slot];
150
102 if (cobalt_board_id == COBALT_BRD_ID_RAQ2) 151 if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
103 return irq_tab_raq2[slot]; 152 return irq_tab_raq2[slot];
104 153
diff --git a/arch/mips/pci/fixup-pnx8550.c b/arch/mips/pci/fixup-pnx8550.c
new file mode 100644
index 000000000000..4256b3b30b77
--- /dev/null
+++ b/arch/mips/pci/fixup-pnx8550.c
@@ -0,0 +1,57 @@
1/*
2 * Philips PNX8550 pci fixups.
3 *
4 * Copyright 2005 Embedded Alley Solutions, Inc
5 * source@embeddealley.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/types.h>
21#include <linux/pci.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24
25#include <asm/mach-pnx8550/pci.h>
26#include <asm/mach-pnx8550/int.h>
27
28
29#undef DEBUG
30#ifdef DEBUG
31#define DBG(x...) printk(x)
32#else
33#define DBG(x...)
34#endif
35
36extern char irq_tab_jbs[][5];
37
38void __init pcibios_fixup_resources(struct pci_dev *dev)
39{
40 /* no need to fixup IO resources */
41}
42
43void __init pcibios_fixup(void)
44{
45 /* nothing to do here */
46}
47
48int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
49{
50 return irq_tab_jbs[slot][pin];
51}
52
53/* Do platform specific device initialization at pci_enable_device() time */
54int pcibios_plat_dev_init(struct pci_dev *dev)
55{
56 return 0;
57}
diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c
new file mode 100644
index 000000000000..f455520ada88
--- /dev/null
+++ b/arch/mips/pci/fixup-tx4938.c
@@ -0,0 +1,92 @@
1/*
2 * Toshiba rbtx4938 pci routines
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/tx4938/rbtx4938.h>
18
19extern struct pci_controller tx4938_pci_controller[];
20
21int pci_get_irq(struct pci_dev *dev, int pin)
22{
23 int irq = pin;
24 u8 slot = PCI_SLOT(dev->devfn);
25 struct pci_controller *controller = (struct pci_controller *)dev->sysdata;
26
27 if (controller == &tx4938_pci_controller[1]) {
28 /* TX4938 PCIC1 */
29 switch (slot) {
30 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
31 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL)
32 return RBTX4938_IRQ_IRC + TX4938_IR_ETH0;
33 break;
34 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
35 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL)
36 return RBTX4938_IRQ_IRC + TX4938_IR_ETH1;
37 break;
38 }
39 return 0;
40 }
41
42 /* IRQ rotation */
43 irq--; /* 0-3 */
44 if (dev->bus->parent == NULL &&
45 (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) {
46 /* PCI CardSlot (IDSEL=A23) */
47 /* PCIA => PCIA (IDSEL=A23) */
48 irq = (irq + 0 + slot) % 4;
49 } else {
50 /* PCI Backplane */
51 irq = (irq + 33 - slot) % 4;
52 }
53 irq++; /* 1-4 */
54
55 switch (irq) {
56 case 1:
57 irq = RBTX4938_IRQ_IOC_PCIA;
58 break;
59 case 2:
60 irq = RBTX4938_IRQ_IOC_PCIB;
61 break;
62 case 3:
63 irq = RBTX4938_IRQ_IOC_PCIC;
64 break;
65 case 4:
66 irq = RBTX4938_IRQ_IOC_PCID;
67 break;
68 }
69 return irq;
70}
71
72int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
73{
74 unsigned char irq = 0;
75
76 irq = pci_get_irq(dev, pin);
77
78 printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n",
79 dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn),
80 PCI_FUNC(dev->devfn), irq);
81
82 return irq;
83}
84
85/*
86 * Do platform specific device initialization at pci_enable_device() time
87 */
88int pcibios_plat_dev_init(struct pci_dev *dev)
89{
90 return 0;
91}
92
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
index c1c91ca0f9c2..be1420126c42 100644
--- a/arch/mips/pci/ops-au1000.c
+++ b/arch/mips/pci/ops-au1000.c
@@ -50,11 +50,6 @@
50 50
51int (*board_pci_idsel)(unsigned int devsel, int assert); 51int (*board_pci_idsel)(unsigned int devsel, int assert);
52 52
53/* CP0 hazard avoidance. */
54#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
55 "nop; nop; nop; nop;\t" \
56 ".set reorder\n\t")
57
58void mod_wired_entry(int entry, unsigned long entrylo0, 53void mod_wired_entry(int entry, unsigned long entrylo0,
59 unsigned long entrylo1, unsigned long entryhi, 54 unsigned long entrylo1, unsigned long entryhi,
60 unsigned long pagemask) 55 unsigned long pagemask)
@@ -66,16 +61,12 @@ void mod_wired_entry(int entry, unsigned long entrylo0,
66 old_ctx = read_c0_entryhi() & 0xff; 61 old_ctx = read_c0_entryhi() & 0xff;
67 old_pagemask = read_c0_pagemask(); 62 old_pagemask = read_c0_pagemask();
68 write_c0_index(entry); 63 write_c0_index(entry);
69 BARRIER;
70 write_c0_pagemask(pagemask); 64 write_c0_pagemask(pagemask);
71 write_c0_entryhi(entryhi); 65 write_c0_entryhi(entryhi);
72 write_c0_entrylo0(entrylo0); 66 write_c0_entrylo0(entrylo0);
73 write_c0_entrylo1(entrylo1); 67 write_c0_entrylo1(entrylo1);
74 BARRIER;
75 tlb_write_indexed(); 68 tlb_write_indexed();
76 BARRIER;
77 write_c0_entryhi(old_ctx); 69 write_c0_entryhi(old_ctx);
78 BARRIER;
79 write_c0_pagemask(old_pagemask); 70 write_c0_pagemask(old_pagemask);
80} 71}
81 72
@@ -128,9 +119,8 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
128 last_entryLo0 = last_entryLo1 = 0xffffffff; 119 last_entryLo0 = last_entryLo1 = 0xffffffff;
129 } 120 }
130 121
131 /* Since the Au1xxx doesn't do the idsel timing exactly to spec, 122 /* Allow board vendors to implement their own off-chip idsel.
132 * many board vendors implement their own off-chip idsel, so call 123 * If it doesn't succeed, may as well bail out at this point.
133 * it now. If it doesn't succeed, may as well bail out at this point.
134 */ 124 */
135 if (board_pci_idsel) { 125 if (board_pci_idsel) {
136 if (board_pci_idsel(device, 1) == 0) { 126 if (board_pci_idsel(device, 1) == 0) {
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 4b4e086a7eb1..dc35270b65a2 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
4 * 6 *
5 * This program is free software; you can distribute it and/or modify it 7 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 8 * under the terms of the GNU General Public License (Version 2) as
@@ -17,7 +19,6 @@
17 * 19 *
18 * MIPS boards specific PCI support. 20 * MIPS boards specific PCI support.
19 */ 21 */
20#include <linux/config.h>
21#include <linux/types.h> 22#include <linux/types.h>
22#include <linux/pci.h> 23#include <linux/pci.h>
23#include <linux/kernel.h> 24#include <linux/kernel.h>
@@ -57,13 +58,6 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
57 return -1; 58 return -1;
58 } 59 }
59 60
60#ifdef CONFIG_MIPS_BOARDS_GEN
61 if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
62 /* MIPS Core boards have Bonito connected as device 17 */
63 return -1;
64 }
65#endif
66
67 /* Clear cause register bits */ 61 /* Clear cause register bits */
68 BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR | 62 BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
69 BONITO_PCICMD_MTABORT_CLR); 63 BONITO_PCICMD_MTABORT_CLR);
diff --git a/arch/mips/pci/ops-gt64111.c b/arch/mips/pci/ops-gt64111.c
index c5b0fc184c2a..c1807934768d 100644
--- a/arch/mips/pci/ops-gt64111.c
+++ b/arch/mips/pci/ops-gt64111.c
@@ -18,15 +18,15 @@
18#include <asm/cobalt/cobalt.h> 18#include <asm/cobalt/cobalt.h>
19 19
20/* 20/*
21 * Accessing device 31 hangs the GT64120. Not sure if this will also hang 21 * Device 31 on the GT64111 is used to generate PCI special
22 * the GT64111, let's be paranoid for now. 22 * cycles, so we shouldn't expected to find a device there ...
23 */ 23 */
24static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn) 24static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn)
25{ 25{
26 if (bus->number == 0 && devfn == PCI_DEVFN(31, 0)) 26 if (bus->number == 0 && PCI_SLOT(devfn) < 31)
27 return -1; 27 return 0;
28 28
29 return 0; 29 return -1;
30} 30}
31 31
32static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn, 32static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
diff --git a/arch/mips/pci/ops-gt64120.c b/arch/mips/pci/ops-gt64120.c
index 7b99dfa33dfc..6335844d607a 100644
--- a/arch/mips/pci/ops-gt64120.c
+++ b/arch/mips/pci/ops-gt64120.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
4 * 6 *
5 * This program is free software; you can distribute it and/or modify it 7 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 8 * under the terms of the GNU General Public License (Version 2) as
@@ -43,10 +45,6 @@ static int gt64120_pcibios_config_access(unsigned char access_type,
43 unsigned char busnum = bus->number; 45 unsigned char busnum = bus->number;
44 u32 intr; 46 u32 intr;
45 47
46 if ((busnum == 0) && (PCI_SLOT(devfn) == 0))
47 /* Galileo itself is devfn 0, don't move it around */
48 return -1;
49
50 if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0))) 48 if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
51 return -1; /* Because of a bug in the galileo (for slot 31). */ 49 return -1; /* Because of a bug in the galileo (for slot 31). */
52 50
diff --git a/arch/mips/pci/ops-msc.c b/arch/mips/pci/ops-msc.c
index 7bc099643a9d..5d9fbb0f4670 100644
--- a/arch/mips/pci/ops-msc.c
+++ b/arch/mips/pci/ops-msc.c
@@ -21,7 +21,6 @@
21 * MIPS boards specific PCI support. 21 * MIPS boards specific PCI support.
22 * 22 *
23 */ 23 */
24#include <linux/config.h>
25#include <linux/types.h> 24#include <linux/types.h>
26#include <linux/pci.h> 25#include <linux/pci.h>
27#include <linux/kernel.h> 26#include <linux/kernel.h>
@@ -49,34 +48,17 @@ static int msc_pcibios_config_access(unsigned char access_type,
49 struct pci_bus *bus, unsigned int devfn, int where, u32 * data) 48 struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
50{ 49{
51 unsigned char busnum = bus->number; 50 unsigned char busnum = bus->number;
52 unsigned char type;
53 u32 intr; 51 u32 intr;
54 52
55#ifdef CONFIG_MIPS_BOARDS_GEN
56 if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
57 /* MIPS Core boards have SOCit connected as device 17 */
58 return -1;
59 }
60#endif
61
62 /* Clear status register bits. */ 53 /* Clear status register bits. */
63 MSC_WRITE(MSC01_PCI_INTSTAT, 54 MSC_WRITE(MSC01_PCI_INTSTAT,
64 (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)); 55 (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
65 56
66 /* Setup address */
67 if (busnum == 0)
68 type = 0; /* Type 0 */
69 else
70 type = 1; /* Type 1 */
71
72 MSC_WRITE(MSC01_PCI_CFGADDR, 57 MSC_WRITE(MSC01_PCI_CFGADDR,
73 ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) | 58 ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
74 (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) 59 (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) |
75 | (PCI_FUNC(devfn) << 60 (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) |
76 MSC01_PCI_CFGADDR_FNUM_SHF) | ((where / 61 ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
77 4) <<
78 MSC01_PCI_CFGADDR_RNUM_SHF)
79 | (type)));
80 62
81 /* Perform access */ 63 /* Perform access */
82 if (access_type == PCI_ACCESS_WRITE) 64 if (access_type == PCI_ACCESS_WRITE)
@@ -86,15 +68,12 @@ static int msc_pcibios_config_access(unsigned char access_type,
86 68
87 /* Detect Master/Target abort */ 69 /* Detect Master/Target abort */
88 MSC_READ(MSC01_PCI_INTSTAT, intr); 70 MSC_READ(MSC01_PCI_INTSTAT, intr);
89 if (intr & (MSC01_PCI_INTCFG_MA_BIT | 71 if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) {
90 MSC01_PCI_INTCFG_TA_BIT)) {
91 /* Error occurred */ 72 /* Error occurred */
92 73
93 /* Clear bits */ 74 /* Clear bits */
94 MSC_READ(MSC01_PCI_INTSTAT, intr);
95 MSC_WRITE(MSC01_PCI_INTSTAT, 75 MSC_WRITE(MSC01_PCI_INTSTAT,
96 (MSC01_PCI_INTCFG_MA_BIT | 76 (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
97 MSC01_PCI_INTCFG_TA_BIT));
98 77
99 return -1; 78 return -1;
100 } 79 }
diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c
index a7169928b351..a8d38dc8c504 100644
--- a/arch/mips/pci/ops-nile4.c
+++ b/arch/mips/pci/ops-nile4.c
@@ -15,7 +15,7 @@
15 15
16volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE; 16volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
17 17
18static spinlock_t nile4_pci_lock; 18static DEFINE_SPINLOCK(nile4_pci_lock);
19 19
20static int nile4_pcibios_config_access(unsigned char access_type, 20static int nile4_pcibios_config_access(unsigned char access_type,
21 struct pci_bus *bus, unsigned int devfn, int where, u32 * val) 21 struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c
new file mode 100644
index 000000000000..454b65cc3354
--- /dev/null
+++ b/arch/mips/pci/ops-pnx8550.c
@@ -0,0 +1,284 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 *
5 * 2.6 port, Embedded Alley Solutions, Inc
6 *
7 * Based on:
8 * Author: source@mvista.com
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 */
23#include <linux/types.h>
24#include <linux/pci.h>
25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/vmalloc.h>
28#include <linux/delay.h>
29
30#include <asm/mach-pnx8550/pci.h>
31#include <asm/mach-pnx8550/glb.h>
32#include <asm/debug.h>
33
34
35static inline void clear_status(void)
36{
37 unsigned long pci_stat;
38
39 pci_stat = inl(PCI_BASE | PCI_GPPM_STATUS);
40 outl(pci_stat, PCI_BASE | PCI_GPPM_ICLR);
41}
42
43static inline unsigned int
44calc_cfg_addr(struct pci_bus *bus, unsigned int devfn, int where)
45{
46 unsigned int addr;
47
48 addr = ((bus->number > 0) ? (((bus->number & 0xff) << PCI_CFG_BUS_SHIFT) | 1) : 0);
49 addr |= ((devfn & 0xff) << PCI_CFG_FUNC_SHIFT) | (where & 0xfc);
50
51 return addr;
52}
53
54static int
55config_access(unsigned int pci_cmd, struct pci_bus *bus, unsigned int devfn, int where, unsigned int pci_mode, unsigned int *val)
56{
57 unsigned int flags;
58 unsigned long loops = 0;
59 unsigned long ioaddr = calc_cfg_addr(bus, devfn, where);
60
61 local_irq_save(flags);
62 /*Clear pending interrupt status */
63 if (inl(PCI_BASE | PCI_GPPM_STATUS)) {
64 clear_status();
65 while (!(inl(PCI_BASE | PCI_GPPM_STATUS) == 0)) ;
66 }
67
68 outl(ioaddr, PCI_BASE | PCI_GPPM_ADDR);
69
70 if ((pci_cmd == PCI_CMD_IOW) || (pci_cmd == PCI_CMD_CONFIG_WRITE))
71 outl(*val, PCI_BASE | PCI_GPPM_WDAT);
72
73 outl(INIT_PCI_CYCLE | pci_cmd | (pci_mode & PCI_BYTE_ENABLE_MASK),
74 PCI_BASE | PCI_GPPM_CTRL);
75
76 loops =
77 ((loops_per_jiffy *
78 PCI_IO_JIFFIES_TIMEOUT) >> (PCI_IO_JIFFIES_SHIFT));
79 while (1) {
80 if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_DONE) {
81 if ((pci_cmd == PCI_CMD_IOR) ||
82 (pci_cmd == PCI_CMD_CONFIG_READ))
83 *val = inl(PCI_BASE | PCI_GPPM_RDAT);
84 clear_status();
85 local_irq_restore(flags);
86 return PCIBIOS_SUCCESSFUL;
87 } else if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_R_MABORT) {
88 break;
89 }
90
91 loops--;
92 if (loops == 0) {
93 printk("%s : Arbiter Locked.\n", __FUNCTION__);
94 }
95 }
96
97 clear_status();
98 if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_IOW)) {
99 printk("%s timeout (GPPM_CTRL=%X) ioaddr %lX pci_cmd %X\n",
100 __FUNCTION__, inl(PCI_BASE | PCI_GPPM_CTRL), ioaddr,
101 pci_cmd);
102 }
103
104 if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_CONFIG_READ))
105 *val = 0xffffffff;
106 local_irq_restore(flags);
107 return PCIBIOS_DEVICE_NOT_FOUND;
108}
109
110/*
111 * We can't address 8 and 16 bit words directly. Instead we have to
112 * read/write a 32bit word and mask/modify the data we actually want.
113 */
114static int
115read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
116{
117 unsigned int data = 0;
118 int err;
119
120 if (bus == 0)
121 return -1;
122
123 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
124 switch (where & 0x03) {
125 case 0:
126 *val = (unsigned char)(data & 0x000000ff);
127 break;
128 case 1:
129 *val = (unsigned char)((data & 0x0000ff00) >> 8);
130 break;
131 case 2:
132 *val = (unsigned char)((data & 0x00ff0000) >> 16);
133 break;
134 case 3:
135 *val = (unsigned char)((data & 0xff000000) >> 24);
136 break;
137 }
138
139 return err;
140}
141
142static int
143read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
144{
145 unsigned int data = 0;
146 int err;
147
148 if (bus == 0)
149 return -1;
150
151 if (where & 0x01)
152 return PCIBIOS_BAD_REGISTER_NUMBER;
153
154 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(3 << (where & 3)), &data);
155 switch (where & 0x02) {
156 case 0:
157 *val = (unsigned short)(data & 0x0000ffff);
158 break;
159 case 2:
160 *val = (unsigned short)((data & 0xffff0000) >> 16);
161 break;
162 }
163
164 return err;
165}
166
167static int
168read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
169{
170 int err;
171 if (bus == 0)
172 return -1;
173
174 if (where & 0x03)
175 return PCIBIOS_BAD_REGISTER_NUMBER;
176
177 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, 0, val);
178
179 return err;
180}
181
182static int
183write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
184{
185 unsigned int data = (unsigned int)val;
186 int err;
187
188 if (bus == 0)
189 return -1;
190
191 switch (where & 0x03) {
192 case 1:
193 data = (data << 8);
194 break;
195 case 2:
196 data = (data << 16);
197 break;
198 case 3:
199 data = (data << 24);
200 break;
201 default:
202 break;
203 }
204
205 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
206
207 return err;
208}
209
210static int
211write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
212{
213 unsigned int data = (unsigned int)val;
214 int err;
215
216 if (bus == 0)
217 return -1;
218
219 if (where & 0x01)
220 return PCIBIOS_BAD_REGISTER_NUMBER;
221
222 switch (where & 0x02) {
223 case 2:
224 data = (data << 16);
225 break;
226 default:
227 break;
228 }
229 err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(3 << (where & 3)), &data);
230
231 return err;
232}
233
234static int
235write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
236{
237 int err;
238 if (bus == 0)
239 return -1;
240
241 if (where & 0x03)
242 return PCIBIOS_BAD_REGISTER_NUMBER;
243
244 err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, 0, &val);
245
246 return err;
247}
248
249static int config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
250{
251 switch (size) {
252 case 1: {
253 u8 _val;
254 int rc = read_config_byte(bus, devfn, where, &_val);
255 *val = _val;
256 return rc;
257 }
258 case 2: {
259 u16 _val;
260 int rc = read_config_word(bus, devfn, where, &_val);
261 *val = _val;
262 return rc;
263 }
264 default:
265 return read_config_dword(bus, devfn, where, val);
266 }
267}
268
269static int config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
270{
271 switch (size) {
272 case 1:
273 return write_config_byte(bus, devfn, where, (u8) val);
274 case 2:
275 return write_config_word(bus, devfn, where, (u16) val);
276 default:
277 return write_config_dword(bus, devfn, where, val);
278 }
279}
280
281struct pci_ops pnx8550_pci_ops = {
282 config_read,
283 config_write
284};
diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c
new file mode 100644
index 000000000000..4c0dcfce5297
--- /dev/null
+++ b/arch/mips/pci/ops-tx4938.c
@@ -0,0 +1,198 @@
1/*
2 * Define the pci_ops for the Toshiba rbtx4938
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/addrspace.h>
18#include <asm/tx4938/rbtx4938.h>
19
20/* initialize in setup */
21struct resource pci_io_resource = {
22 .name = "pci IO space",
23 .start = 0,
24 .end = 0,
25 .flags = IORESOURCE_IO
26};
27
28/* initialize in setup */
29struct resource pci_mem_resource = {
30 .name = "pci memory space",
31 .start = 0,
32 .end = 0,
33 .flags = IORESOURCE_MEM
34};
35
36struct resource tx4938_pcic1_pci_io_resource = {
37 .name = "PCI1 IO",
38 .start = 0,
39 .end = 0,
40 .flags = IORESOURCE_IO
41};
42struct resource tx4938_pcic1_pci_mem_resource = {
43 .name = "PCI1 mem",
44 .start = 0,
45 .end = 0,
46 .flags = IORESOURCE_MEM
47};
48
49static int mkaddr(int bus, int dev_fn, int where, int *flagsp)
50{
51 if (bus > 0) {
52 /* Type 1 configuration */
53 tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
54 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
55 } else {
56 if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0))
57 return -1;
58
59 /* Type 0 configuration */
60 tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
61 ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
62 }
63 /* clear M_ABORT and Disable M_ABORT Int. */
64 tx4938_pcicptr->pcistatus =
65 (tx4938_pcicptr->pcistatus & 0x0000ffff) |
66 (PCI_STATUS_REC_MASTER_ABORT << 16);
67 tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
68
69 return 0;
70}
71
72static int check_abort(int flags)
73{
74 int code = PCIBIOS_SUCCESSFUL;
75 /* wait write cycle completion before checking error status */
76 while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
77 ;
78 if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
79 tx4938_pcicptr->pcistatus =
80 (tx4938_pcicptr->
81 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
82 << 16);
83 tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
84 code = PCIBIOS_DEVICE_NOT_FOUND;
85 }
86 return code;
87}
88
89static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
90 int where, int size, u32 * val)
91{
92 int flags, retval, dev, busno, func;
93
94 dev = PCI_SLOT(devfn);
95 func = PCI_FUNC(devfn);
96
97 /* check if the bus is top-level */
98 if (bus->parent != NULL)
99 busno = bus->number;
100 else {
101 busno = 0;
102 }
103
104 if (mkaddr(busno, devfn, where, &flags))
105 return -1;
106
107 switch (size) {
108 case 1:
109 *val = *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
110#ifdef __BIG_ENDIAN
111 ((where & 3) ^ 3));
112#else
113 (where & 3));
114#endif
115 break;
116 case 2:
117 *val = *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
118#ifdef __BIG_ENDIAN
119 ((where & 3) ^ 2));
120#else
121 (where & 3));
122#endif
123 break;
124 case 4:
125 *val = tx4938_pcicptr->g2pcfgdata;
126 break;
127 }
128
129 retval = check_abort(flags);
130 if (retval == PCIBIOS_DEVICE_NOT_FOUND)
131 *val = 0xffffffff;
132
133 return retval;
134}
135
136static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
137 int size, u32 val)
138{
139 int flags, dev, busno, func;
140
141 busno = bus->number;
142 dev = PCI_SLOT(devfn);
143 func = PCI_FUNC(devfn);
144
145 /* check if the bus is top-level */
146 if (bus->parent != NULL) {
147 busno = bus->number;
148 } else {
149 busno = 0;
150 }
151
152 if (mkaddr(busno, devfn, where, &flags))
153 return -1;
154
155 switch (size) {
156 case 1:
157 *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
158#ifdef __BIG_ENDIAN
159 ((where & 3) ^ 3)) = val;
160#else
161 (where & 3)) = val;
162#endif
163 break;
164 case 2:
165 *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
166#ifdef __BIG_ENDIAN
167 ((where & 0x3) ^ 0x2)) = val;
168#else
169 (where & 3)) = val;
170#endif
171 break;
172 case 4:
173 tx4938_pcicptr->g2pcfgdata = val;
174 break;
175 }
176
177 return check_abort(flags);
178}
179
180struct pci_ops tx4938_pci_ops = {
181 tx4938_pcibios_read_config,
182 tx4938_pcibios_write_config
183};
184
185struct pci_controller tx4938_pci_controller[] = {
186 /* h/w only supports devices 0x00 to 0x14 */
187 {
188 .pci_ops = &tx4938_pci_ops,
189 .io_resource = &pci_io_resource,
190 .mem_resource = &pci_mem_resource,
191 },
192 /* h/w only supports devices 0x00 to 0x14 */
193 {
194 .pci_ops = &tx4938_pci_ops,
195 .io_resource = &tx4938_pcic1_pci_io_resource,
196 .mem_resource = &tx4938_pcic1_pci_mem_resource,
197 }
198};
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
new file mode 100644
index 000000000000..f194b4e4f86a
--- /dev/null
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -0,0 +1,265 @@
1/*
2 * Copyright (C) 2001,2002,2005 Broadcom Corporation
3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20/*
21 * BCM1x80/1x55-specific PCI support
22 *
23 * This module provides the glue between Linux's PCI subsystem
24 * and the hardware. We basically provide glue for accessing
25 * configuration space, and set up the translation for I/O
26 * space accesses.
27 *
28 * To access configuration space, we use ioremap. In the 32-bit
29 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
30 * kernel mapped memory. Hopefully neither of these should be a huge
31 * problem.
32 *
33 * XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED.
34 */
35#include <linux/config.h>
36#include <linux/types.h>
37#include <linux/pci.h>
38#include <linux/kernel.h>
39#include <linux/init.h>
40#include <linux/mm.h>
41#include <linux/console.h>
42#include <linux/tty.h>
43
44#include <asm/sibyte/bcm1480_regs.h>
45#include <asm/sibyte/bcm1480_scd.h>
46#include <asm/sibyte/board.h>
47#include <asm/io.h>
48
49/*
50 * Macros for calculating offsets into config space given a device
51 * structure or dev/fun/reg
52 */
53#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
54#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where)
55
56static void *cfg_space;
57
58#define PCI_BUS_ENABLED 1
59#define PCI_DEVICE_MODE 2
60
61static int bcm1480_bus_status = 0;
62
63#define PCI_BRIDGE_DEVICE 0
64
65/*
66 * Read/write 32-bit values in config space.
67 */
68static inline u32 READCFG32(u32 addr)
69{
70 return *(u32 *)(cfg_space + (addr&~3));
71}
72
73static inline void WRITECFG32(u32 addr, u32 data)
74{
75 *(u32 *)(cfg_space + (addr & ~3)) = data;
76}
77
78int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
79{
80 return dev->irq;
81}
82
83/* Do platform specific device initialization at pci_enable_device() time */
84int pcibios_plat_dev_init(struct pci_dev *dev)
85{
86 return 0;
87}
88
89/*
90 * Some checks before doing config cycles:
91 * In PCI Device Mode, hide everything on bus 0 except the LDT host
92 * bridge. Otherwise, access is controlled by bridge MasterEn bits.
93 */
94static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)
95{
96 u32 devno;
97
98 if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
99 return 0;
100
101 if (bus->number == 0) {
102 devno = PCI_SLOT(devfn);
103 if (bcm1480_bus_status & PCI_DEVICE_MODE)
104 return 0;
105 else
106 return 1;
107 } else
108 return 1;
109}
110
111/*
112 * Read/write access functions for various sizes of values
113 * in config space. Return all 1's for disallowed accesses
114 * for a kludgy but adequate simulation of master aborts.
115 */
116
117static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn,
118 int where, int size, u32 * val)
119{
120 u32 data = 0;
121
122 if ((size == 2) && (where & 1))
123 return PCIBIOS_BAD_REGISTER_NUMBER;
124 else if ((size == 4) && (where & 3))
125 return PCIBIOS_BAD_REGISTER_NUMBER;
126
127 if (bcm1480_pci_can_access(bus, devfn))
128 data = READCFG32(CFGADDR(bus, devfn, where));
129 else
130 data = 0xFFFFFFFF;
131
132 if (size == 1)
133 *val = (data >> ((where & 3) << 3)) & 0xff;
134 else if (size == 2)
135 *val = (data >> ((where & 3) << 3)) & 0xffff;
136 else
137 *val = data;
138
139 return PCIBIOS_SUCCESSFUL;
140}
141
142static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
143 int where, int size, u32 val)
144{
145 u32 cfgaddr = CFGADDR(bus, devfn, where);
146 u32 data = 0;
147
148 if ((size == 2) && (where & 1))
149 return PCIBIOS_BAD_REGISTER_NUMBER;
150 else if ((size == 4) && (where & 3))
151 return PCIBIOS_BAD_REGISTER_NUMBER;
152
153 if (!bcm1480_pci_can_access(bus, devfn))
154 return PCIBIOS_BAD_REGISTER_NUMBER;
155
156 data = READCFG32(cfgaddr);
157
158 if (size == 1)
159 data = (data & ~(0xff << ((where & 3) << 3))) |
160 (val << ((where & 3) << 3));
161 else if (size == 2)
162 data = (data & ~(0xffff << ((where & 3) << 3))) |
163 (val << ((where & 3) << 3));
164 else
165 data = val;
166
167 WRITECFG32(cfgaddr, data);
168
169 return PCIBIOS_SUCCESSFUL;
170}
171
172struct pci_ops bcm1480_pci_ops = {
173 bcm1480_pcibios_read,
174 bcm1480_pcibios_write,
175};
176
177static struct resource bcm1480_mem_resource = {
178 .name = "BCM1480 PCI MEM",
179 .start = 0x30000000UL,
180 .end = 0x3fffffffUL,
181 .flags = IORESOURCE_MEM,
182};
183
184static struct resource bcm1480_io_resource = {
185 .name = "BCM1480 PCI I/O",
186 .start = 0x2c000000UL,
187 .end = 0x2dffffffUL,
188 .flags = IORESOURCE_IO,
189};
190
191struct pci_controller bcm1480_controller = {
192 .pci_ops = &bcm1480_pci_ops,
193 .mem_resource = &bcm1480_mem_resource,
194 .io_resource = &bcm1480_io_resource,
195};
196
197
198static int __init bcm1480_pcibios_init(void)
199{
200 uint32_t cmdreg;
201 uint64_t reg;
202 extern int pci_probe_only;
203
204 /* CFE will assign PCI resources */
205 pci_probe_only = 1;
206
207 /* Avoid ISA compat ranges. */
208 PCIBIOS_MIN_IO = 0x00008000UL;
209 PCIBIOS_MIN_MEM = 0x01000000UL;
210
211 /* Set I/O resource limits. - unlimited for now to accomodate HT */
212 ioport_resource.end = 0xffffffffUL;
213 iomem_resource.end = 0xffffffffUL;
214
215 cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024);
216
217 /*
218 * See if the PCI bus has been configured by the firmware.
219 */
220 reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
221 if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
222 bcm1480_bus_status |= PCI_DEVICE_MODE;
223 } else {
224 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
225 PCI_COMMAND));
226 if (!(cmdreg & PCI_COMMAND_MASTER)) {
227 printk
228 ("PCI: Skipping PCI probe. Bus is not initialized.\n");
229 iounmap(cfg_space);
230 return 1; /* XXX */
231 }
232 bcm1480_bus_status |= PCI_BUS_ENABLED;
233 }
234
235 /* turn on ExpMemEn */
236 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
237 printk("PCIFeatureCtrl = %x\n", cmdreg);
238 WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40),
239 cmdreg | 0x10);
240 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
241 printk("PCIFeatureCtrl = %x\n", cmdreg);
242
243 /*
244 * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
245 * space. Use "match bytes" policy to make everything look
246 * little-endian. So, you need to also set
247 * CONFIG_SWAP_IO_SPACE, but this is the combination that
248 * works correctly with most of Linux's drivers.
249 * XXX ehs: Should this happen in PCI Device mode?
250 */
251
252 set_io_port_base((unsigned long)
253 ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536));
254 isa_slot_offset = (unsigned long)
255 ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);
256
257 register_pci_controller(&bcm1480_controller);
258
259#ifdef CONFIG_VGA_CONSOLE
260 take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1);
261#endif
262 return 0;
263}
264
265arch_initcall(bcm1480_pcibios_init);
diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c
new file mode 100644
index 000000000000..aca4a2e7a1c6
--- /dev/null
+++ b/arch/mips/pci/pci-bcm1480ht.c
@@ -0,0 +1,224 @@
1/*
2 * Copyright (C) 2001,2002,2005 Broadcom Corporation
3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20/*
21 * BCM1480/1455-specific HT support (looking like PCI)
22 *
23 * This module provides the glue between Linux's PCI subsystem
24 * and the hardware. We basically provide glue for accessing
25 * configuration space, and set up the translation for I/O
26 * space accesses.
27 *
28 * To access configuration space, we use ioremap. In the 32-bit
29 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
30 * kernel mapped memory. Hopefully neither of these should be a huge
31 * problem.
32 *
33 */
34#include <linux/config.h>
35#include <linux/types.h>
36#include <linux/pci.h>
37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/mm.h>
40#include <linux/console.h>
41#include <linux/tty.h>
42
43#include <asm/sibyte/bcm1480_regs.h>
44#include <asm/sibyte/bcm1480_scd.h>
45#include <asm/sibyte/board.h>
46#include <asm/io.h>
47
48/*
49 * Macros for calculating offsets into config space given a device
50 * structure or dev/fun/reg
51 */
52#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
53#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where)
54
55static void *ht_cfg_space;
56
57#define PCI_BUS_ENABLED 1
58#define PCI_DEVICE_MODE 2
59
60static int bcm1480ht_bus_status = 0;
61
62#define PCI_BRIDGE_DEVICE 0
63#define HT_BRIDGE_DEVICE 1
64
65/*
66 * HT's level-sensitive interrupts require EOI, which is generated
67 * through a 4MB memory-mapped region
68 */
69unsigned long ht_eoi_space;
70
71/*
72 * Read/write 32-bit values in config space.
73 */
74static inline u32 READCFG32(u32 addr)
75{
76 return *(u32 *)(ht_cfg_space + (addr&~3));
77}
78
79static inline void WRITECFG32(u32 addr, u32 data)
80{
81 *(u32 *)(ht_cfg_space + (addr & ~3)) = data;
82}
83
84/*
85 * Some checks before doing config cycles:
86 * In PCI Device Mode, hide everything on bus 0 except the LDT host
87 * bridge. Otherwise, access is controlled by bridge MasterEn bits.
88 */
89static int bcm1480ht_can_access(struct pci_bus *bus, int devfn)
90{
91 u32 devno;
92
93 if (!(bcm1480ht_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
94 return 0;
95
96 if (bus->number == 0) {
97 devno = PCI_SLOT(devfn);
98 if (bcm1480ht_bus_status & PCI_DEVICE_MODE)
99 return 0;
100 }
101 return 1;
102}
103
104/*
105 * Read/write access functions for various sizes of values
106 * in config space. Return all 1's for disallowed accesses
107 * for a kludgy but adequate simulation of master aborts.
108 */
109
110static int bcm1480ht_pcibios_read(struct pci_bus *bus, unsigned int devfn,
111 int where, int size, u32 * val)
112{
113 u32 data = 0;
114
115 if ((size == 2) && (where & 1))
116 return PCIBIOS_BAD_REGISTER_NUMBER;
117 else if ((size == 4) && (where & 3))
118 return PCIBIOS_BAD_REGISTER_NUMBER;
119
120 if (bcm1480ht_can_access(bus, devfn))
121 data = READCFG32(CFGADDR(bus, devfn, where));
122 else
123 data = 0xFFFFFFFF;
124
125 if (size == 1)
126 *val = (data >> ((where & 3) << 3)) & 0xff;
127 else if (size == 2)
128 *val = (data >> ((where & 3) << 3)) & 0xffff;
129 else
130 *val = data;
131
132 return PCIBIOS_SUCCESSFUL;
133}
134
135static int bcm1480ht_pcibios_write(struct pci_bus *bus, unsigned int devfn,
136 int where, int size, u32 val)
137{
138 u32 cfgaddr = CFGADDR(bus, devfn, where);
139 u32 data = 0;
140
141 if ((size == 2) && (where & 1))
142 return PCIBIOS_BAD_REGISTER_NUMBER;
143 else if ((size == 4) && (where & 3))
144 return PCIBIOS_BAD_REGISTER_NUMBER;
145
146 if (!bcm1480ht_can_access(bus, devfn))
147 return PCIBIOS_BAD_REGISTER_NUMBER;
148
149 data = READCFG32(cfgaddr);
150
151 if (size == 1)
152 data = (data & ~(0xff << ((where & 3) << 3))) |
153 (val << ((where & 3) << 3));
154 else if (size == 2)
155 data = (data & ~(0xffff << ((where & 3) << 3))) |
156 (val << ((where & 3) << 3));
157 else
158 data = val;
159
160 WRITECFG32(cfgaddr, data);
161
162 return PCIBIOS_SUCCESSFUL;
163}
164
165static int bcm1480ht_pcibios_get_busno(void)
166{
167 return 0;
168}
169
170struct pci_ops bcm1480ht_pci_ops = {
171 .read = bcm1480ht_pcibios_read,
172 .write = bcm1480ht_pcibios_write,
173};
174
175static struct resource bcm1480ht_mem_resource = {
176 .name = "BCM1480 HT MEM",
177 .start = 0x40000000UL,
178 .end = 0x5fffffffUL,
179 .flags = IORESOURCE_MEM,
180};
181
182static struct resource bcm1480ht_io_resource = {
183 .name = "BCM1480 HT I/O",
184 .start = 0x00000000UL,
185 .end = 0x01ffffffUL,
186 .flags = IORESOURCE_IO,
187};
188
189struct pci_controller bcm1480ht_controller = {
190 .pci_ops = &bcm1480ht_pci_ops,
191 .mem_resource = &bcm1480ht_mem_resource,
192 .io_resource = &bcm1480ht_io_resource,
193 .index = 1,
194 .get_busno = bcm1480ht_pcibios_get_busno,
195};
196
197static int __init bcm1480ht_pcibios_init(void)
198{
199 uint32_t cmdreg;
200
201 ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024);
202
203 /*
204 * See if the PCI bus has been configured by the firmware.
205 */
206 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
207 PCI_COMMAND));
208 if (!(cmdreg & PCI_COMMAND_MASTER)) {
209 printk("HT: Skipping HT probe. Bus is not initialized.\n");
210 iounmap(ht_cfg_space);
211 return 1; /* XXX */
212 }
213 bcm1480ht_bus_status |= PCI_BUS_ENABLED;
214
215 ht_eoi_space = (unsigned long)
216 ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES,
217 4 * 1024 * 1024);
218
219 register_pci_controller(&bcm1480ht_controller);
220
221 return 0;
222}
223
224arch_initcall(bcm1480ht_pcibios_init);
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 068e0e508e15..efc96ce99eeb 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -485,5 +485,12 @@ static void __init pci_fixup_ioc3(struct pci_dev *d)
485 pci_disable_swapping(d); 485 pci_disable_swapping(d);
486} 486}
487 487
488int pcibus_to_node(struct pci_bus *bus)
489{
490 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
491
492 return bc->nasid;
493}
494
488DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 495DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
489 pci_fixup_ioc3); 496 pci_fixup_ioc3);
diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c
index 000dc6af6cd3..180af89bcb1e 100644
--- a/arch/mips/pci/pci-ip32.c
+++ b/arch/mips/pci/pci-ip32.c
@@ -136,7 +136,9 @@ static int __init mace_init(void)
136 BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0, 136 BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
137 "MACE PCI error", NULL)); 137 "MACE PCI error", NULL));
138 138
139 ioport_resource.end = mace_pci_io_resource.end; 139 iomem_resource = mace_pci_mem_resource;
140 ioport_resource = mace_pci_io_resource;
141
140 register_pci_controller(&mace_pci_controller); 142 register_pci_controller(&mace_pci_controller);
141 143
142 return 0; 144 return 0;
diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c
index ae3cc4b254b5..88fb191ad2eb 100644
--- a/arch/mips/pci/pci-lasat.c
+++ b/arch/mips/pci/pci-lasat.c
@@ -7,12 +7,8 @@
7 */ 7 */
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/interrupt.h>
11#include <linux/pci.h> 10#include <linux/pci.h>
12#include <linux/types.h> 11#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <asm/bootinfo.h> 12#include <asm/bootinfo.h>
17 13
18extern struct pci_ops nile4_pci_ops; 14extern struct pci_ops nile4_pci_ops;
@@ -20,14 +16,14 @@ extern struct pci_ops gt64120_pci_ops;
20static struct resource lasat_pci_mem_resource = { 16static struct resource lasat_pci_mem_resource = {
21 .name = "LASAT PCI MEM", 17 .name = "LASAT PCI MEM",
22 .start = 0x18000000, 18 .start = 0x18000000,
23 .end = 0x19FFFFFF, 19 .end = 0x19ffffff,
24 .flags = IORESOURCE_MEM, 20 .flags = IORESOURCE_MEM,
25}; 21};
26 22
27static struct resource lasat_pci_io_resource = { 23static struct resource lasat_pci_io_resource = {
28 .name = "LASAT PCI IO", 24 .name = "LASAT PCI IO",
29 .start = 0x1a000000, 25 .start = 0x1a000000,
30 .end = 0x1bFFFFFF, 26 .end = 0x1bffffff,
31 .flags = IORESOURCE_IO, 27 .flags = IORESOURCE_IO,
32}; 28};
33 29
@@ -38,23 +34,25 @@ static struct pci_controller lasat_pci_controller = {
38 34
39static int __init lasat_pci_setup(void) 35static int __init lasat_pci_setup(void)
40{ 36{
41 printk("PCI: starting\n"); 37 printk("PCI: starting\n");
42 38
43 switch (mips_machtype) { 39 switch (mips_machtype) {
44 case MACH_LASAT_100: 40 case MACH_LASAT_100:
45 lasat_pci_controller.pci_ops = &gt64120_pci_ops; 41 lasat_pci_controller.pci_ops = &gt64120_pci_ops;
46 break; 42 break;
47 case MACH_LASAT_200: 43 case MACH_LASAT_200:
48 lasat_pci_controller.pci_ops = &nile4_pci_ops; 44 lasat_pci_controller.pci_ops = &nile4_pci_ops;
49 break; 45 break;
50 default: 46 default:
51 panic("pcibios_init: mips_machtype incorrect"); 47 panic("pcibios_init: mips_machtype incorrect");
52 } 48 }
53 49
54 register_pci_controller(&lasat_pci_controller); 50 register_pci_controller(&lasat_pci_controller);
55 return 0; 51
52 return 0;
56} 53}
57early_initcall(lasat_pci_setup); 54
55arch_initcall(lasat_pci_setup);
58 56
59#define LASATINT_ETH1 0 57#define LASATINT_ETH1 0
60#define LASATINT_ETH0 1 58#define LASATINT_ETH0 1
@@ -68,24 +66,22 @@ early_initcall(lasat_pci_setup);
68 66
69int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 67int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
70{ 68{
71 switch (slot) { 69 switch (slot) {
72 case 1: 70 case 1:
73 return LASATINT_PCIA; /* Expansion Module 0 */ 71 case 2:
74 case 2: 72 case 3:
75 return LASATINT_PCIB; /* Expansion Module 1 */ 73 return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4);
76 case 3: 74 case 4:
77 return LASATINT_PCIC; /* Expansion Module 2 */ 75 return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */
78 case 4: 76 case 5:
79 return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */ 77 return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */
80 case 5: 78 case 6:
81 return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */ 79 return LASATINT_HDC; /* IDE controller */
82 case 6: 80 default:
83 return LASATINT_HDC; /* IDE controller */ 81 return 0xff; /* Illegal */
84 default: 82 }
85 return 0xff; /* Illegal */
86 }
87 83
88 return -1; 84 return -1;
89} 85}
90 86
91/* Do platform specific device initialization at pci_enable_device() time */ 87/* Do platform specific device initialization at pci_enable_device() time */
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index a8d499b0a36f..21402ffd7c98 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -127,15 +127,20 @@ static int __init pcibios_init(void)
127 if (!hose->iommu) 127 if (!hose->iommu)
128 PCI_DMA_BUS_IS_PHYS = 1; 128 PCI_DMA_BUS_IS_PHYS = 1;
129 129
130 if (hose->get_busno && pci_probe_only)
131 next_busno = (*hose->get_busno)();
132
130 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 133 bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
131 hose->bus = bus; 134 hose->bus = bus;
132 hose->need_domain_info = need_domain_info; 135 hose->need_domain_info = need_domain_info;
133 next_busno = bus->subordinate + 1; 136 if (bus) {
134 /* Don't allow 8-bit bus number overflow inside the hose - 137 next_busno = bus->subordinate + 1;
135 reserve some space for bridges. */ 138 /* Don't allow 8-bit bus number overflow inside the hose -
136 if (next_busno > 224) { 139 reserve some space for bridges. */
137 next_busno = 0; 140 if (next_busno > 224) {
138 need_domain_info = 1; 141 next_busno = 0;
142 need_domain_info = 1;
143 }
139 } 144 }
140 continue; 145 continue;
141 146
@@ -164,7 +169,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask)
164 169
165 pci_read_config_word(dev, PCI_COMMAND, &cmd); 170 pci_read_config_word(dev, PCI_COMMAND, &cmd);
166 old_cmd = cmd; 171 old_cmd = cmd;
167 for(idx=0; idx<6; idx++) { 172 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
168 /* Only set up the requested stuff */ 173 /* Only set up the requested stuff */
169 if (!(mask & (1<<idx))) 174 if (!(mask & (1<<idx)))
170 continue; 175 continue;
diff --git a/arch/mips/philips/pnx8550/common/Kconfig b/arch/mips/philips/pnx8550/common/Kconfig
new file mode 100644
index 000000000000..072572d173cc
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/Kconfig
@@ -0,0 +1 @@
# Place holder
diff --git a/arch/mips/philips/pnx8550/common/Makefile b/arch/mips/philips/pnx8550/common/Makefile
new file mode 100644
index 000000000000..6e38f3bc443c
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/Makefile
@@ -0,0 +1,27 @@
1#
2# Per Hallsmark, per.hallsmark@mvista.com
3#
4# ########################################################################
5#
6# This program is free software; you can distribute it and/or modify it
7# under the terms of the GNU General Public License (Version 2) as
8# published by the Free Software Foundation.
9#
10# This program is distributed in the hope it will be useful, but WITHOUT
11# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13# for more details.
14#
15# You should have received a copy of the GNU General Public License along
16# with this program; if not, write to the Free Software Foundation, Inc.,
17# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18#
19# #######################################################################
20#
21# Makefile for the PNX8550 specific kernel interface routines
22# under Linux.
23#
24
25obj-y := setup.o prom.o mipsIRQ.o int.o reset.o time.o proc.o platform.o
26obj-$(CONFIG_PCI) += pci.o
27obj-$(CONFIG_KGDB) += gdb_hook.o
diff --git a/arch/mips/philips/pnx8550/common/gdb_hook.c b/arch/mips/philips/pnx8550/common/gdb_hook.c
new file mode 100644
index 000000000000..ad4624f6d9bc
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/gdb_hook.c
@@ -0,0 +1,109 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * This is the interface to the remote debugger stub.
23 *
24 */
25#include <linux/types.h>
26#include <linux/serial.h>
27#include <linux/serialP.h>
28#include <linux/serial_reg.h>
29#include <linux/serial_ip3106.h>
30
31#include <asm/serial.h>
32#include <asm/io.h>
33
34#include <uart.h>
35
36static struct serial_state rs_table[IP3106_NR_PORTS] = {
37};
38static struct async_struct kdb_port_info = {0};
39
40void rs_kgdb_hook(int tty_no)
41{
42 struct serial_state *ser = &rs_table[tty_no];
43
44 kdb_port_info.state = ser;
45 kdb_port_info.magic = SERIAL_MAGIC;
46 kdb_port_info.port = tty_no;
47 kdb_port_info.flags = ser->flags;
48
49 /*
50 * Clear all interrupts
51 */
52 /* Clear all the transmitter FIFO counters (pointer and status) */
53 ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST;
54 /* Clear all the receiver FIFO counters (pointer and status) */
55 ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST;
56 /* Clear all interrupts */
57 ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX |
58 IP3106_UART_INT_ALLTX;
59
60 /*
61 * Now, initialize the UART
62 */
63 ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT;
64 ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud
65}
66
67int putDebugChar(char c)
68{
69 /* Wait until FIFO not full */
70 while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16)
71 ;
72 /* Send one char */
73 ip3106_fifo(UART_BASE, kdb_port_info.port) = c;
74
75 return 1;
76}
77
78char getDebugChar(void)
79{
80 char ch;
81
82 /* Wait until there is a char in the FIFO */
83 while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) &
84 IP3106_UART_FIFO_RXFIFO) >> 8))
85 ;
86 /* Read one char */
87 ch = ip3106_fifo(UART_BASE, kdb_port_info.port) &
88 IP3106_UART_FIFO_RBRTHR;
89 /* Advance the RX FIFO read pointer */
90 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT;
91 return (ch);
92}
93
94void rs_disable_debug_interrupts(void)
95{
96 ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */
97}
98
99void rs_enable_debug_interrupts(void)
100{
101 /* Clear all the transmitter FIFO counters (pointer and status) */
102 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST;
103 /* Clear all the receiver FIFO counters (pointer and status) */
104 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST;
105 /* Clear all interrupts */
106 ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX |
107 IP3106_UART_INT_ALLTX;
108 ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */
109}
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
new file mode 100644
index 000000000000..546144988bf5
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -0,0 +1,293 @@
1/*
2 *
3 * Copyright (C) 2005 Embedded Alley Solutions, Inc
4 * Ported to 2.6.
5 *
6 * Per Hallsmark, per.hallsmark@mvista.com
7 * Copyright (C) 2000, 2001 MIPS Technologies, Inc.
8 * Copyright (C) 2001 Ralf Baechle
9 *
10 * Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com
11 *
12 * This program is free software; you can distribute it and/or modify it
13 * under the terms of the GNU General Public License (Version 2) as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 *
25 */
26#include <linux/config.h>
27#include <linux/init.h>
28#include <linux/irq.h>
29#include <linux/sched.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/kernel_stat.h>
33#include <linux/random.h>
34#include <linux/module.h>
35
36#include <asm/io.h>
37#include <asm/gdb-stub.h>
38#include <int.h>
39#include <uart.h>
40
41extern asmlinkage void cp0_irqdispatch(void);
42
43static DEFINE_SPINLOCK(irq_lock);
44
45/* default prio for interrupts */
46/* first one is a no-no so therefore always prio 0 (disabled) */
47static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
48 0, 1, 1, 1, 1, 15, 1, 1, 1, 1, // 0 - 9
49 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 10 - 19
50 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 20 - 29
51 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 30 - 39
52 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 40 - 49
53 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, // 50 - 59
54 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 60 - 69
55 1 // 70
56};
57
58void hw0_irqdispatch(int irq, struct pt_regs *regs)
59{
60 /* find out which interrupt */
61 irq = PNX8550_GIC_VECTOR_0 >> 3;
62
63 if (irq == 0) {
64 printk("hw0_irqdispatch: irq 0, spurious interrupt?\n");
65 return;
66 }
67 do_IRQ(PNX8550_INT_GIC_MIN + irq, regs);
68}
69
70
71void timer_irqdispatch(int irq, struct pt_regs *regs)
72{
73 irq = (0x01c0 & read_c0_config7()) >> 6;
74
75 if (irq == 0) {
76 printk("timer_irqdispatch: irq 0, spurious interrupt?\n");
77 return;
78 }
79
80 if (irq & 0x1) {
81 do_IRQ(PNX8550_INT_TIMER1, regs);
82 }
83 if (irq & 0x2) {
84 do_IRQ(PNX8550_INT_TIMER2, regs);
85 }
86 if (irq & 0x4) {
87 do_IRQ(PNX8550_INT_TIMER3, regs);
88 }
89}
90
91static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
92{
93 unsigned long status = read_c0_status();
94
95 status &= ~((clr_mask & 0xFF) << 8);
96 status |= (set_mask & 0xFF) << 8;
97
98 write_c0_status(status);
99}
100
101static inline void mask_gic_int(unsigned int irq_nr)
102{
103 /* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */
104 PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */
105}
106
107static inline void unmask_gic_int(unsigned int irq_nr)
108{
109 /* set prio mask to lower four bits and enable interrupt */
110 PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr];
111}
112
113static inline void mask_irq(unsigned int irq_nr)
114{
115 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
116 modify_cp0_intmask(1 << irq_nr, 0);
117 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
118 (irq_nr <= PNX8550_INT_GIC_MAX)) {
119 mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
120 } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
121 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
122 modify_cp0_intmask(1 << 7, 0);
123 } else {
124 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
125 }
126}
127
128static inline void unmask_irq(unsigned int irq_nr)
129{
130 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
131 modify_cp0_intmask(0, 1 << irq_nr);
132 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
133 (irq_nr <= PNX8550_INT_GIC_MAX)) {
134 unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
135 } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
136 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
137 modify_cp0_intmask(0, 1 << 7);
138 } else {
139 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
140 }
141}
142
143#define pnx8550_disable pnx8550_ack
144static void pnx8550_ack(unsigned int irq)
145{
146 unsigned long flags;
147
148 spin_lock_irqsave(&irq_lock, flags);
149 mask_irq(irq);
150 spin_unlock_irqrestore(&irq_lock, flags);
151}
152
153#define pnx8550_enable pnx8550_unmask
154static void pnx8550_unmask(unsigned int irq)
155{
156 unsigned long flags;
157
158 spin_lock_irqsave(&irq_lock, flags);
159 unmask_irq(irq);
160 spin_unlock_irqrestore(&irq_lock, flags);
161}
162
163static unsigned int startup_irq(unsigned int irq_nr)
164{
165 pnx8550_unmask(irq_nr);
166 return 0;
167}
168
169static void shutdown_irq(unsigned int irq_nr)
170{
171 pnx8550_ack(irq_nr);
172 return;
173}
174
175int pnx8550_set_gic_priority(int irq, int priority)
176{
177 int gic_irq = irq-PNX8550_INT_GIC_MIN;
178 int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf;
179
180 gic_prio[gic_irq] = priority;
181 PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]);
182
183 return prev_priority;
184}
185
186static inline void mask_and_ack_level_irq(unsigned int irq)
187{
188 pnx8550_disable(irq);
189 return;
190}
191
192static void end_irq(unsigned int irq)
193{
194 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
195 pnx8550_enable(irq);
196 }
197}
198
199static struct hw_interrupt_type level_irq_type = {
200 .typename = "PNX Level IRQ",
201 .startup = startup_irq,
202 .shutdown = shutdown_irq,
203 .enable = pnx8550_enable,
204 .disable = pnx8550_disable,
205 .ack = mask_and_ack_level_irq,
206 .end = end_irq,
207};
208
209static struct irqaction gic_action = {
210 .handler = no_action,
211 .flags = SA_INTERRUPT,
212 .name = "GIC",
213};
214
215static struct irqaction timer_action = {
216 .handler = no_action,
217 .flags = SA_INTERRUPT,
218 .name = "Timer",
219};
220
221void __init arch_init_irq(void)
222{
223 int i;
224 int configPR;
225
226 /* init of cp0 interrupts */
227 set_except_vector(0, cp0_irqdispatch);
228
229 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
230 irq_desc[i].handler = &level_irq_type;
231 pnx8550_ack(i); /* mask the irq just in case */
232 }
233
234 /* init of GIC/IPC interrupts */
235 /* should be done before cp0 since cp0 init enables the GIC int */
236 for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) {
237 int gic_int_line = i - PNX8550_INT_GIC_MIN;
238 if (gic_int_line == 0 )
239 continue; // don't fiddle with int 0
240 /*
241 * enable change of TARGET, ENABLE and ACTIVE_LOW bits
242 * set TARGET 0 to route through hw0 interrupt
243 * set ACTIVE_LOW 0 active high (correct?)
244 *
245 * We really should setup an interrupt description table
246 * to do this nicely.
247 * Note, PCI INTA is active low on the bus, but inverted
248 * in the GIC, so to us it's active high.
249 */
250#ifdef CONFIG_PNX8550_V2PCI
251 if (gic_int_line == (PNX8550_INT_GPIO0 - PNX8550_INT_GIC_MIN)) {
252 /* PCI INT through gpio 8, which is setup in
253 * pnx8550_setup.c and routed to GPIO
254 * Interrupt Level 0 (GPIO Connection 58).
255 * Set it active low. */
256
257 PNX8550_GIC_REQ(gic_int_line) = 0x1E020000;
258 } else
259#endif
260 {
261 PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
262 }
263
264 /* mask/priority is still 0 so we will not get any
265 * interrupts until it is unmasked */
266
267 irq_desc[i].handler = &level_irq_type;
268 }
269
270 /* Priority level 0 */
271 PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0;
272
273 /* Set int vector table address */
274 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
275
276 irq_desc[MIPS_CPU_GIC_IRQ].handler = &level_irq_type;
277 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
278
279 /* init of Timer interrupts */
280 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) {
281 irq_desc[i].handler = &level_irq_type;
282 }
283
284 /* Stop Timer 1-3 */
285 configPR = read_c0_config7();
286 configPR |= 0x00000038;
287 write_c0_config7(configPR);
288
289 irq_desc[MIPS_CPU_TIMER_IRQ].handler = &level_irq_type;
290 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
291}
292
293EXPORT_SYMBOL(pnx8550_set_gic_priority);
diff --git a/arch/mips/philips/pnx8550/common/mipsIRQ.S b/arch/mips/philips/pnx8550/common/mipsIRQ.S
new file mode 100644
index 000000000000..338bffda3fab
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/mipsIRQ.S
@@ -0,0 +1,76 @@
1/*
2 * Copyright (c) 2002 Philips, Inc. All rights.
3 * Copyright (c) 2002 Red Hat, Inc. All rights.
4 *
5 * This software may be freely redistributed under the terms of the
6 * GNU General Public License.
7 *
8 * You should have received a copy of the GNU General Public License
9 * along with this program; if not, write to the Free Software
10 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
11 *
12 * Based upon arch/mips/galileo-boards/ev64240/int-handler.S
13 *
14 */
15#include <asm/asm.h>
16#include <asm/mipsregs.h>
17#include <asm/addrspace.h>
18#include <asm/regdef.h>
19#include <asm/stackframe.h>
20
21/*
22 * cp0_irqdispatch
23 *
24 * Code to handle in-core interrupt exception.
25 */
26
27 .align 5
28 .set reorder
29 .set noat
30 NESTED(cp0_irqdispatch, PT_SIZE, sp)
31 SAVE_ALL
32 CLI
33 .set at
34 mfc0 t0,CP0_CAUSE
35 mfc0 t2,CP0_STATUS
36
37 and t0,t2
38
39 andi t1,t0,STATUSF_IP2 /* int0 hardware line */
40 bnez t1,ll_hw0_irq
41 nop
42
43 andi t1,t0,STATUSF_IP7 /* int5 hardware line */
44 bnez t1,ll_timer_irq
45 nop
46
47 /* wrong alarm or masked ... */
48
49 j spurious_interrupt
50 nop
51 END(cp0_irqdispatch)
52
53 .align 5
54 .set reorder
55ll_hw0_irq:
56 li a0,2
57 move a1,sp
58 jal hw0_irqdispatch
59 nop
60 j ret_from_irq
61 nop
62
63 .align 5
64 .set reorder
65ll_timer_irq:
66 mfc0 t3,CP0_CONFIG,7
67 andi t4,t3,0x01c0
68 beqz t4,ll_timer_out
69 nop
70 li a0,7
71 move a1,sp
72 jal timer_irqdispatch
73 nop
74
75ll_timer_out: j ret_from_irq
76 nop
diff --git a/arch/mips/philips/pnx8550/common/pci.c b/arch/mips/philips/pnx8550/common/pci.c
new file mode 100644
index 000000000000..baa6905f649f
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/pci.c
@@ -0,0 +1,133 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 *
5 * Author: source@mvista.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/types.h>
21#include <linux/pci.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24
25#include <pci.h>
26#include <glb.h>
27#include <nand.h>
28
29static struct resource pci_io_resource = {
30 "pci IO space",
31 (u32)(PNX8550_PCIIO + 0x1000), /* reserve regacy I/O space */
32 (u32)(PNX8550_PCIIO + PNX8550_PCIIO_SIZE),
33 IORESOURCE_IO
34};
35
36static struct resource pci_mem_resource = {
37 "pci memory space",
38 (u32)(PNX8550_PCIMEM),
39 (u32)(PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1),
40 IORESOURCE_MEM
41};
42
43extern struct pci_ops pnx8550_pci_ops;
44
45static struct pci_controller pnx8550_controller = {
46 .pci_ops = &pnx8550_pci_ops,
47 .io_resource = &pci_io_resource,
48 .mem_resource = &pci_mem_resource,
49};
50
51/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
52static inline unsigned long get_system_mem_size(void)
53{
54 /* Read IP2031_RANK0_ADDR_LO */
55 unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
56 /* Read IP2031_RANK1_ADDR_HI */
57 unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
58
59 return dram_r1_hi - dram_r0_lo + 1;
60}
61
62static int __init pnx8550_pci_setup(void)
63{
64 int pci_mem_code;
65 int mem_size = get_system_mem_size() >> 20;
66
67 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
68 Bit 1:Enable DAC Powerdown
69 -> 0:DACs are enabled and are working normally
70 1:DACs are powerdown
71 Bit 0:Enable of PCI inta output
72 -> 0 = Disable PCI inta output
73 1 = Enable PCI inta output
74 */
75 PNX8550_GLB2_ENAB_INTA_O = 0;
76
77 /* Calc the PCI mem size code */
78 if (mem_size >= 128)
79 pci_mem_code = SIZE_128M;
80 else if (mem_size >= 64)
81 pci_mem_code = SIZE_64M;
82 else if (mem_size >= 32)
83 pci_mem_code = SIZE_32M;
84 else
85 pci_mem_code = SIZE_16M;
86
87 /* Set PCI_XIO registers */
88 outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO);
89 outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI);
90 outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO);
91 outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI);
92
93 /* Send memory transaction via PCI_BASE2 */
94 outl(0x00000001, PCI_BASE | PCI_IO);
95
96 /* Unlock the setup register */
97 outl(0xca, PCI_BASE | PCI_UNLOCKREG);
98
99 /*
100 * BAR0 of PNX8550 (pci base 10) must be zero in order for ide
101 * to work, and in order for bus_to_baddr to work without any
102 * hacks.
103 */
104 outl(0x00000000, PCI_BASE | PCI_BASE10);
105
106 /*
107 *These two bars are set by default or the boot code.
108 * However, it's safer to set them here so we're not boot
109 * code dependent.
110 */
111 outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */
112 outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */
113
114 outl(PCI_EN_TA |
115 PCI_EN_PCI2MMI |
116 PCI_EN_XIO |
117 PCI_SETUP_BASE18_SIZE(SIZE_32M) |
118 PCI_SETUP_BASE18_EN |
119 PCI_SETUP_BASE14_EN |
120 PCI_SETUP_BASE10_PREF |
121 PCI_SETUP_BASE10_SIZE(pci_mem_code) |
122 PCI_SETUP_CFGMANAGE_EN |
123 PCI_SETUP_PCIARB_EN,
124 PCI_BASE |
125 PCI_SETUP); /* PCI_SETUP */
126 outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */
127
128 register_pci_controller(&pnx8550_controller);
129
130 return 0;
131}
132
133arch_initcall(pnx8550_pci_setup);
diff --git a/arch/mips/philips/pnx8550/common/platform.c b/arch/mips/philips/pnx8550/common/platform.c
new file mode 100644
index 000000000000..8aa9bd65b45e
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/platform.c
@@ -0,0 +1,135 @@
1/*
2 * Platform device support for Philips PNX8550 SoCs
3 *
4 * Copyright 2005, Embedded Alley Solutions, Inc
5 *
6 * Based on arch/mips/au1000/common/platform.c
7 * Platform device support for Au1x00 SoCs.
8 *
9 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15#include <linux/device.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/resource.h>
19#include <linux/serial.h>
20#include <linux/serial_ip3106.h>
21
22#include <int.h>
23#include <usb.h>
24#include <uart.h>
25
26extern struct uart_ops ip3106_pops;
27
28static struct resource pnx8550_usb_ohci_resources[] = {
29 [0] = {
30 .start = PNX8550_USB_OHCI_OP_BASE,
31 .end = PNX8550_USB_OHCI_OP_BASE +
32 PNX8550_USB_OHCI_OP_LEN,
33 .flags = IORESOURCE_MEM,
34 },
35 [1] = {
36 .start = PNX8550_INT_USB,
37 .end = PNX8550_INT_USB,
38 .flags = IORESOURCE_IRQ,
39 },
40};
41
42static struct resource pnx8550_uart_resources[] = {
43 [0] = {
44 .start = PNX8550_UART_PORT0,
45 .end = PNX8550_UART_PORT0 + 0xfff,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = PNX8550_UART_INT(0),
50 .end = PNX8550_UART_INT(0),
51 .flags = IORESOURCE_IRQ,
52 },
53 [2] = {
54 .start = PNX8550_UART_PORT1,
55 .end = PNX8550_UART_PORT1 + 0xfff,
56 .flags = IORESOURCE_MEM,
57 },
58 [3] = {
59 .start = PNX8550_UART_INT(1),
60 .end = PNX8550_UART_INT(1),
61 .flags = IORESOURCE_IRQ,
62 },
63};
64
65struct ip3106_port ip3106_ports[] = {
66 [0] = {
67 .port = {
68 .type = PORT_IP3106,
69 .iotype = SERIAL_IO_MEM,
70 .membase = (void __iomem *)PNX8550_UART_PORT0,
71 .mapbase = PNX8550_UART_PORT0,
72 .irq = PNX8550_UART_INT(0),
73 .uartclk = 3692300,
74 .fifosize = 16,
75 .ops = &ip3106_pops,
76 .flags = ASYNC_BOOT_AUTOCONF,
77 .line = 0,
78 },
79 },
80 [1] = {
81 .port = {
82 .type = PORT_IP3106,
83 .iotype = SERIAL_IO_MEM,
84 .membase = (void __iomem *)PNX8550_UART_PORT1,
85 .mapbase = PNX8550_UART_PORT1,
86 .irq = PNX8550_UART_INT(1),
87 .uartclk = 3692300,
88 .fifosize = 16,
89 .ops = &ip3106_pops,
90 .flags = ASYNC_BOOT_AUTOCONF,
91 .line = 1,
92 },
93 },
94};
95
96/* The dmamask must be set for OHCI to work */
97static u64 ohci_dmamask = ~(u32)0;
98
99static u64 uart_dmamask = ~(u32)0;
100
101static struct platform_device pnx8550_usb_ohci_device = {
102 .name = "pnx8550-ohci",
103 .id = -1,
104 .dev = {
105 .dma_mask = &ohci_dmamask,
106 .coherent_dma_mask = 0xffffffff,
107 },
108 .num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources),
109 .resource = pnx8550_usb_ohci_resources,
110};
111
112static struct platform_device pnx8550_uart_device = {
113 .name = "ip3106-uart",
114 .id = -1,
115 .dev = {
116 .dma_mask = &uart_dmamask,
117 .coherent_dma_mask = 0xffffffff,
118 .platform_data = ip3106_ports,
119 },
120 .num_resources = ARRAY_SIZE(pnx8550_uart_resources),
121 .resource = pnx8550_uart_resources,
122};
123
124static struct platform_device *pnx8550_platform_devices[] __initdata = {
125 &pnx8550_usb_ohci_device,
126 &pnx8550_uart_device,
127};
128
129int pnx8550_platform_init(void)
130{
131 return platform_add_devices(pnx8550_platform_devices,
132 ARRAY_SIZE(pnx8550_platform_devices));
133}
134
135arch_initcall(pnx8550_platform_init);
diff --git a/arch/mips/philips/pnx8550/common/proc.c b/arch/mips/philips/pnx8550/common/proc.c
new file mode 100644
index 000000000000..72a016767e09
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/proc.c
@@ -0,0 +1,113 @@
1/*
2 * This program is free software; you can distribute it and/or modify it
3 * under the terms of the GNU General Public License (Version 2) as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
9 * for more details.
10 *
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
14 */
15#include <linux/init.h>
16#include <linux/proc_fs.h>
17#include <linux/irq.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/interrupt.h>
21#include <linux/kernel_stat.h>
22#include <linux/random.h>
23
24#include <asm/io.h>
25#include <asm/gdb-stub.h>
26#include <int.h>
27#include <uart.h>
28
29
30static int pnx8550_timers_read (char* page, char** start, off_t offset, int count, int* eof, void* data)
31{
32 int len = 0;
33 int configPR = read_c0_config7();
34
35 if (offset==0) {
36 len += sprintf(&page[len],"Timer: count, compare, tc, status\n");
37 len += sprintf(&page[len]," 1: %11i, %8i, %1i, %s\n",
38 read_c0_count(), read_c0_compare(),
39 (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on");
40 len += sprintf(&page[len]," 2: %11i, %8i, %1i, %s\n",
41 read_c0_count2(), read_c0_compare2(),
42 (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on");
43 len += sprintf(&page[len]," 3: %11i, %8i, %1i, %s\n",
44 read_c0_count3(), read_c0_compare3(),
45 (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on");
46 }
47
48 return len;
49}
50
51static int pnx8550_registers_read (char* page, char** start, off_t offset, int count, int* eof, void* data)
52{
53 int len = 0;
54
55 if (offset==0) {
56 len += sprintf(&page[len],"config1: %#10.8x\n",read_c0_config1());
57 len += sprintf(&page[len],"config2: %#10.8x\n",read_c0_config2());
58 len += sprintf(&page[len],"config3: %#10.8x\n",read_c0_config3());
59 len += sprintf(&page[len],"configPR: %#10.8x\n",read_c0_config7());
60 len += sprintf(&page[len],"status: %#10.8x\n",read_c0_status());
61 len += sprintf(&page[len],"cause: %#10.8x\n",read_c0_cause());
62 len += sprintf(&page[len],"count: %#10.8x\n",read_c0_count());
63 len += sprintf(&page[len],"count_2: %#10.8x\n",read_c0_count2());
64 len += sprintf(&page[len],"count_3: %#10.8x\n",read_c0_count3());
65 len += sprintf(&page[len],"compare: %#10.8x\n",read_c0_compare());
66 len += sprintf(&page[len],"compare_2: %#10.8x\n",read_c0_compare2());
67 len += sprintf(&page[len],"compare_3: %#10.8x\n",read_c0_compare3());
68 }
69
70 return len;
71}
72
73static struct proc_dir_entry* pnx8550_dir = NULL;
74static struct proc_dir_entry* pnx8550_timers = NULL;
75static struct proc_dir_entry* pnx8550_registers = NULL;
76
77static int pnx8550_proc_init( void )
78{
79
80 // Create /proc/pnx8550
81 pnx8550_dir = create_proc_entry("pnx8550", S_IFDIR|S_IRUGO, NULL);
82 if (pnx8550_dir){
83 pnx8550_dir->nlink = 1;
84 }
85 else {
86 printk(KERN_ERR "Can't create pnx8550 proc dir\n");
87 return -1;
88 }
89
90 // Create /proc/pnx8550/timers
91 pnx8550_timers = create_proc_entry("timers", S_IFREG|S_IRUGO, pnx8550_dir );
92 if (pnx8550_timers){
93 pnx8550_timers->nlink = 1;
94 pnx8550_timers->read_proc = pnx8550_timers_read;
95 }
96 else {
97 printk(KERN_ERR "Can't create pnx8550 timers proc file\n");
98 }
99
100 // Create /proc/pnx8550/registers
101 pnx8550_registers = create_proc_entry("registers", S_IFREG|S_IRUGO, pnx8550_dir );
102 if (pnx8550_registers){
103 pnx8550_registers->nlink = 1;
104 pnx8550_registers->read_proc = pnx8550_registers_read;
105 }
106 else {
107 printk(KERN_ERR "Can't create pnx8550 registers proc file\n");
108 }
109
110 return 0;
111}
112
113__initcall(pnx8550_proc_init);
diff --git a/arch/mips/philips/pnx8550/common/prom.c b/arch/mips/philips/pnx8550/common/prom.c
new file mode 100644
index 000000000000..70aac9759412
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/prom.c
@@ -0,0 +1,138 @@
1/*
2 *
3 * Per Hallsmark, per.hallsmark@mvista.com
4 *
5 * Based on jmr3927/common/prom.c
6 *
7 * 2004 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/string.h>
16#include <linux/serial_ip3106.h>
17
18#include <asm/bootinfo.h>
19#include <uart.h>
20
21/* #define DEBUG_CMDLINE */
22
23extern int prom_argc;
24extern char **prom_argv, **prom_envp;
25
26typedef struct
27{
28 char *name;
29/* char *val; */
30}t_env_var;
31
32
33char * prom_getcmdline(void)
34{
35 return &(arcs_cmdline[0]);
36}
37
38void prom_init_cmdline(void)
39{
40 char *cp;
41 int actr;
42
43 actr = 1; /* Always ignore argv[0] */
44
45 cp = &(arcs_cmdline[0]);
46 while(actr < prom_argc) {
47 strcpy(cp, prom_argv[actr]);
48 cp += strlen(prom_argv[actr]);
49 *cp++ = ' ';
50 actr++;
51 }
52 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
53 --cp;
54 *cp = '\0';
55}
56
57char *prom_getenv(char *envname)
58{
59 /*
60 * Return a pointer to the given environment variable.
61 * Environment variables are stored in the form of "memsize=64".
62 */
63
64 t_env_var *env = (t_env_var *)prom_envp;
65 int i;
66
67 i = strlen(envname);
68
69 while(env->name) {
70 if(strncmp(envname, env->name, i) == 0) {
71 return(env->name + strlen(envname) + 1);
72 }
73 env++;
74 }
75 return(NULL);
76}
77
78inline unsigned char str2hexnum(unsigned char c)
79{
80 if(c >= '0' && c <= '9')
81 return c - '0';
82 if(c >= 'a' && c <= 'f')
83 return c - 'a' + 10;
84 if(c >= 'A' && c <= 'F')
85 return c - 'A' + 10;
86 return 0; /* foo */
87}
88
89inline void str2eaddr(unsigned char *ea, unsigned char *str)
90{
91 int i;
92
93 for(i = 0; i < 6; i++) {
94 unsigned char num;
95
96 if((*str == '.') || (*str == ':'))
97 str++;
98 num = str2hexnum(*str++) << 4;
99 num |= (str2hexnum(*str++));
100 ea[i] = num;
101 }
102}
103
104int get_ethernet_addr(char *ethernet_addr)
105{
106 char *ethaddr_str;
107
108 ethaddr_str = prom_getenv("ethaddr");
109 if (!ethaddr_str) {
110 printk("ethaddr not set in boot prom\n");
111 return -1;
112 }
113 str2eaddr(ethernet_addr, ethaddr_str);
114 return 0;
115}
116
117unsigned long __init prom_free_prom_memory(void)
118{
119 return 0;
120}
121
122extern int pnx8550_console_port;
123
124/* used by prom_printf */
125void prom_putchar(char c)
126{
127 if (pnx8550_console_port != -1) {
128 /* Wait until FIFO not full */
129 while( ((ip3106_fifo(UART_BASE, pnx8550_console_port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16)
130 ;
131 /* Send one char */
132 ip3106_fifo(UART_BASE, pnx8550_console_port) = c;
133 }
134}
135
136EXPORT_SYMBOL(prom_getcmdline);
137EXPORT_SYMBOL(get_ethernet_addr);
138EXPORT_SYMBOL(str2eaddr);
diff --git a/arch/mips/philips/pnx8550/common/reset.c b/arch/mips/philips/pnx8550/common/reset.c
new file mode 100644
index 000000000000..7b2cbc5b2c7c
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/reset.c
@@ -0,0 +1,49 @@
1/*.
2 *
3 * ########################################################################
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * ########################################################################
19 *
20 * Reset the PNX8550 board.
21 *
22 */
23#include <linux/slab.h>
24#include <asm/reboot.h>
25#include <glb.h>
26
27void pnx8550_machine_restart(char *command)
28{
29 char head[] = "************* Machine restart *************";
30 char foot[] = "*******************************************";
31
32 printk("\n\n");
33 printk("%s\n", head);
34 if (command != NULL)
35 printk("* %s\n", command);
36 printk("%s\n", foot);
37
38 PNX8550_RST_CTL = PNX8550_RST_DO_SW_RST;
39}
40
41void pnx8550_machine_halt(void)
42{
43 printk("*** Machine halt. (Not implemented) ***\n");
44}
45
46void pnx8550_machine_power_off(void)
47{
48 printk("*** Machine power off. (Not implemented) ***\n");
49}
diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c
new file mode 100644
index 000000000000..ee6bf72094f6
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/setup.c
@@ -0,0 +1,149 @@
1/*
2 *
3 * 2.6 port, Embedded Alley Solutions, Inc
4 *
5 * Based on Per Hallsmark, per.hallsmark@mvista.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/config.h>
21#include <linux/init.h>
22#include <linux/sched.h>
23#include <linux/ioport.h>
24#include <linux/mm.h>
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/serial_ip3106.h>
28
29#include <asm/cpu.h>
30#include <asm/bootinfo.h>
31#include <asm/irq.h>
32#include <asm/mipsregs.h>
33#include <asm/reboot.h>
34#include <asm/pgtable.h>
35#include <asm/time.h>
36
37#include <glb.h>
38#include <int.h>
39#include <pci.h>
40#include <uart.h>
41#include <nand.h>
42
43extern void prom_printf(char *fmt, ...);
44
45extern void __init board_setup(void);
46extern void pnx8550_machine_restart(char *);
47extern void pnx8550_machine_halt(void);
48extern void pnx8550_machine_power_off(void);
49extern struct resource ioport_resource;
50extern struct resource iomem_resource;
51extern void (*board_time_init)(void);
52extern void pnx8550_time_init(void);
53extern void (*board_timer_setup)(struct irqaction *irq);
54extern void pnx8550_timer_setup(struct irqaction *irq);
55extern void rs_kgdb_hook(int tty_no);
56extern void prom_printf(char *fmt, ...);
57extern char *prom_getcmdline(void);
58
59struct resource standard_io_resources[] = {
60 {"dma1", 0x00, 0x1f, IORESOURCE_BUSY},
61 {"timer", 0x40, 0x5f, IORESOURCE_BUSY},
62 {"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY},
63 {"dma2", 0xc0, 0xdf, IORESOURCE_BUSY},
64};
65
66#define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource))
67
68extern struct resource pci_io_resource;
69extern struct resource pci_mem_resource;
70
71/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
72unsigned long get_system_mem_size(void)
73{
74 /* Read IP2031_RANK0_ADDR_LO */
75 unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
76 /* Read IP2031_RANK1_ADDR_HI */
77 unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
78
79 return dram_r1_hi - dram_r0_lo + 1;
80}
81
82int pnx8550_console_port = -1;
83
84void __init plat_setup(void)
85{
86 int i;
87 char* argptr;
88
89 board_setup(); /* board specific setup */
90
91 _machine_restart = pnx8550_machine_restart;
92 _machine_halt = pnx8550_machine_halt;
93 _machine_power_off = pnx8550_machine_power_off;
94
95 board_time_init = pnx8550_time_init;
96 board_timer_setup = pnx8550_timer_setup;
97
98 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
99 Bit 1:Enable DAC Powerdown
100 -> 0:DACs are enabled and are working normally
101 1:DACs are powerdown
102 Bit 0:Enable of PCI inta output
103 -> 0 = Disable PCI inta output
104 1 = Enable PCI inta output
105 */
106 PNX8550_GLB2_ENAB_INTA_O = 0;
107
108 /* IO/MEM resources. */
109 set_io_port_base(KSEG1);
110 ioport_resource.start = 0;
111 ioport_resource.end = ~0;
112 iomem_resource.start = 0;
113 iomem_resource.end = ~0;
114
115 /* Request I/O space for devices on this board */
116 for (i = 0; i < STANDARD_IO_RESOURCES; i++)
117 request_resource(&ioport_resource, standard_io_resources + i);
118
119 /* Place the Mode Control bit for GPIO pin 16 in primary function */
120 /* Pin 16 is used by UART1, UA1_TX */
121 outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) |
122 (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT),
123 PNX8550_GPIO_MC1);
124
125 argptr = prom_getcmdline();
126 if ((argptr = strstr(argptr, "console=ttyS")) != NULL) {
127 argptr += strlen("console=ttyS");
128 pnx8550_console_port = *argptr == '0' ? 0 : 1;
129
130 /* We must initialize the UART (console) before prom_printf */
131 /* Set LCR to 8-bit and BAUD to 38400 (no 5) */
132 ip3106_lcr(UART_BASE, pnx8550_console_port) =
133 IP3106_UART_LCR_8BIT;
134 ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
135 }
136
137#ifdef CONFIG_KGDB
138 argptr = prom_getcmdline();
139 if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
140 int line;
141 argptr += strlen("kgdb=ttyS");
142 line = *argptr == '0' ? 0 : 1;
143 rs_kgdb_hook(line);
144 prom_printf("KGDB: Using ttyS%i for session, "
145 "please connect your debugger\n", line ? 1 : 0);
146 }
147#endif
148 return;
149}
diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c
new file mode 100644
index 000000000000..70664ea96b92
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/time.c
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2001, 2002, 2003 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * Common time service routines for MIPS machines. See
6 * Documents/MIPS/README.txt.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/sched.h>
17#include <linux/param.h>
18#include <linux/time.h>
19#include <linux/timer.h>
20#include <linux/smp.h>
21#include <linux/kernel_stat.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25
26#include <asm/bootinfo.h>
27#include <asm/cpu.h>
28#include <asm/time.h>
29#include <asm/hardirq.h>
30#include <asm/div64.h>
31#include <asm/debug.h>
32
33#include <int.h>
34#include <cm.h>
35
36extern unsigned int mips_hpt_frequency;
37
38/*
39 * pnx8550_time_init() - it does the following things:
40 *
41 * 1) board_time_init() -
42 * a) (optional) set up RTC routines,
43 * b) (optional) calibrate and set the mips_hpt_frequency
44 * (only needed if you intended to use fixed_rate_gettimeoffset
45 * or use cpu counter as timer interrupt source)
46 */
47
48void pnx8550_time_init(void)
49{
50 unsigned int n;
51 unsigned int m;
52 unsigned int p;
53 unsigned int pow2p;
54
55 /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */
56 /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */
57
58 n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16;
59 m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8;
60 p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2;
61 pow2p = (1 << p);
62
63 db_assert(m != 0 && pow2p != 0);
64
65 /*
66 * Compute the frequency as in the PNX8550 User Manual 1.0, p.186
67 * (a.k.a. 8-10). Divide by HZ for a timer offset that results in
68 * HZ timer interrupts per second.
69 */
70 mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
71}
72
73/*
74 * pnx8550_timer_setup() - it does the following things:
75 *
76 * 5) board_timer_setup() -
77 * a) (optional) over-write any choices made above by time_init().
78 * b) machine specific code should setup the timer irqaction.
79 * c) enable the timer interrupt
80 */
81
82void __init pnx8550_timer_setup(struct irqaction *irq)
83{
84 int configPR;
85
86 setup_irq(PNX8550_INT_TIMER1, irq);
87
88 /* Start timer1 */
89 configPR = read_c0_config7();
90 configPR &= ~0x00000008;
91 write_c0_config7(configPR);
92
93 /* Timer 2 stop */
94 configPR = read_c0_config7();
95 configPR |= 0x00000010;
96 write_c0_config7(configPR);
97
98 write_c0_count2(0);
99 write_c0_compare2(0xffffffff);
100
101 /* Timer 3 stop */
102 configPR = read_c0_config7();
103 configPR |= 0x00000020;
104 write_c0_config7(configPR);
105}
diff --git a/arch/mips/philips/pnx8550/jbs/Makefile b/arch/mips/philips/pnx8550/jbs/Makefile
new file mode 100644
index 000000000000..e8228dbca8f6
--- /dev/null
+++ b/arch/mips/philips/pnx8550/jbs/Makefile
@@ -0,0 +1,4 @@
1
2# Makefile for the Philips JBS Board.
3
4lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/philips/pnx8550/jbs/board_setup.c b/arch/mips/philips/pnx8550/jbs/board_setup.c
new file mode 100644
index 000000000000..f92826e0096d
--- /dev/null
+++ b/arch/mips/philips/pnx8550/jbs/board_setup.c
@@ -0,0 +1,65 @@
1/*
2 * JBS Specific board startup routines.
3 *
4 * Copyright 2005, Embedded Alley Solutions, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#include <linux/init.h>
27#include <linux/sched.h>
28#include <linux/ioport.h>
29#include <linux/mm.h>
30#include <linux/console.h>
31#include <linux/mc146818rtc.h>
32#include <linux/delay.h>
33
34#include <asm/cpu.h>
35#include <asm/bootinfo.h>
36#include <asm/irq.h>
37#include <asm/mipsregs.h>
38#include <asm/reboot.h>
39#include <asm/pgtable.h>
40
41#include <glb.h>
42
43/* CP0 hazard avoidance. */
44#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
45 "nop; nop; nop; nop; nop; nop;\n\t" \
46 ".set reorder\n\t")
47
48void __init board_setup(void)
49{
50 unsigned long config0, configpr;
51
52 config0 = read_c0_config();
53
54 /* clear all three cache coherency fields */
55 config0 &= ~(0x7 | (7<<25) | (7<<28));
56 config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
57 (CONF_CM_DEFAULT<<28));
58 write_c0_config(config0);
59 BARRIER;
60
61 configpr = read_c0_config7();
62 configpr |= (1<<19); /* enable tlb */
63 write_c0_config7(configpr);
64 BARRIER;
65}
diff --git a/arch/mips/philips/pnx8550/jbs/init.c b/arch/mips/philips/pnx8550/jbs/init.c
new file mode 100644
index 000000000000..85f449174bc3
--- /dev/null
+++ b/arch/mips/philips/pnx8550/jbs/init.c
@@ -0,0 +1,57 @@
1/*
2 *
3 * Copyright 2005 Embedded Alley Solutions, Inc
4 * source@embeddedalley.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/init.h>
28#include <linux/mm.h>
29#include <linux/sched.h>
30#include <linux/bootmem.h>
31#include <asm/addrspace.h>
32#include <asm/bootinfo.h>
33#include <linux/string.h>
34#include <linux/kernel.h>
35
36int prom_argc;
37char **prom_argv, **prom_envp;
38extern void __init prom_init_cmdline(void);
39extern char *prom_getenv(char *envname);
40
41const char *get_system_type(void)
42{
43 return "Philips PNX8550/JBS";
44}
45
46void __init prom_init(void)
47{
48
49 unsigned long memsize;
50
51 mips_machgroup = MACH_GROUP_PHILIPS;
52 mips_machtype = MACH_PHILIPS_JBS;
53
54 //memsize = 0x02800000; /* Trimedia uses memory above */
55 memsize = 0x08000000; /* Trimedia uses memory above */
56 add_memory_region(0, memsize, BOOT_MEM_RAM);
57}
diff --git a/arch/mips/philips/pnx8550/jbs/irqmap.c b/arch/mips/philips/pnx8550/jbs/irqmap.c
new file mode 100644
index 000000000000..f78e0423dc98
--- /dev/null
+++ b/arch/mips/philips/pnx8550/jbs/irqmap.c
@@ -0,0 +1,36 @@
1/*
2 * Philips JBS board irqmap.
3 *
4 * Copyright 2005 Embedded Alley Solutions, Inc
5 * source@embeddealley.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <int.h>
30
31char irq_tab_jbs[][5] __initdata = {
32 [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
33 [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
34 [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
35};
36
diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig
new file mode 100644
index 000000000000..24d514c9dff9
--- /dev/null
+++ b/arch/mips/pmc-sierra/Kconfig
@@ -0,0 +1,3 @@
1config HYPERTRANSPORT
2 bool "Hypertransport Support for PMC-Sierra Yosemite"
3 depends on PMC_YOSEMITE
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
index c19f01a32045..a31288335fba 100644
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
+++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
@@ -34,7 +34,6 @@
34#include <linux/pci.h> 34#include <linux/pci.h>
35#include <linux/kernel.h> 35#include <linux/kernel.h>
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <linux/version.h>
38#include <asm/pci.h> 37#include <asm/pci.h>
39#include <asm/io.h> 38#include <asm/io.h>
40#include <linux/init.h> 39#include <linux/init.h>
diff --git a/arch/mips/pmc-sierra/yosemite/ht-irq.c b/arch/mips/pmc-sierra/yosemite/ht-irq.c
index d22c9ffe4914..5aec4057314e 100644
--- a/arch/mips/pmc-sierra/yosemite/ht-irq.c
+++ b/arch/mips/pmc-sierra/yosemite/ht-irq.c
@@ -26,7 +26,6 @@
26#include <linux/types.h> 26#include <linux/types.h>
27#include <linux/pci.h> 27#include <linux/pci.h>
28#include <linux/kernel.h> 28#include <linux/kernel.h>
29#include <linux/version.h>
30#include <linux/init.h> 29#include <linux/init.h>
31#include <asm/pci.h> 30#include <asm/pci.h>
32 31
diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c
index dad228d3a220..54b65a80abf5 100644
--- a/arch/mips/pmc-sierra/yosemite/ht.c
+++ b/arch/mips/pmc-sierra/yosemite/ht.c
@@ -28,7 +28,6 @@
28#include <linux/pci.h> 28#include <linux/pci.h>
29#include <linux/kernel.h> 29#include <linux/kernel.h>
30#include <linux/slab.h> 30#include <linux/slab.h>
31#include <linux/version.h>
32#include <asm/pci.h> 31#include <asm/pci.h>
33#include <asm/io.h> 32#include <asm/io.h>
34 33
diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c
index 1fb3e697948d..555bfacf7647 100644
--- a/arch/mips/pmc-sierra/yosemite/prom.c
+++ b/arch/mips/pmc-sierra/yosemite/prom.c
@@ -132,8 +132,9 @@ void __init prom_init(void)
132 prom_grab_secondary(); 132 prom_grab_secondary();
133} 133}
134 134
135void __init prom_free_prom_memory(void) 135unsigned long __init prom_free_prom_memory(void)
136{ 136{
137 return 0;
137} 138}
138 139
139void __init prom_fixup_mem_map(unsigned long start, unsigned long end) 140void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c
index 7225bbf20ce4..bdc2ab55bed6 100644
--- a/arch/mips/pmc-sierra/yosemite/setup.c
+++ b/arch/mips/pmc-sierra/yosemite/setup.c
@@ -212,7 +212,7 @@ static void __init py_late_time_init(void)
212 py_rtc_setup(); 212 py_rtc_setup();
213} 213}
214 214
215static int __init pmc_yosemite_setup(void) 215void __init plat_setup(void)
216{ 216{
217 board_time_init = yosemite_time_init; 217 board_time_init = yosemite_time_init;
218 late_time_init = py_late_time_init; 218 late_time_init = py_late_time_init;
@@ -228,8 +228,4 @@ static int __init pmc_yosemite_setup(void)
228 OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR); 228 OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR);
229 OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0); 229 OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0);
230#endif 230#endif
231
232 return 0;
233} 231}
234
235early_initcall(pmc_yosemite_setup);
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index 1d3b0734c78c..0527170d6adb 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -9,7 +9,7 @@ extern void (*mips_hpt_init)(unsigned int);
9 9
10#define LAUNCHSTACK_SIZE 256 10#define LAUNCHSTACK_SIZE 256
11 11
12static spinlock_t launch_lock __initdata; 12static __initdata DEFINE_SPINLOCK(launch_lock);
13 13
14static unsigned long secondary_sp __initdata; 14static unsigned long secondary_sp __initdata;
15static unsigned long secondary_gp __initdata; 15static unsigned long secondary_gp __initdata;
diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c
index 1a80eee8cd35..022eb1af6db1 100644
--- a/arch/mips/qemu/q-setup.c
+++ b/arch/mips/qemu/q-setup.c
@@ -4,6 +4,11 @@
4 4
5#define QEMU_PORT_BASE 0xb4000000 5#define QEMU_PORT_BASE 0xb4000000
6 6
7const char *get_system_type(void)
8{
9 return "Qemu";
10}
11
7static void __init qemu_timer_setup(struct irqaction *irq) 12static void __init qemu_timer_setup(struct irqaction *irq)
8{ 13{
9 /* set the clock to 100 Hz */ 14 /* set the clock to 100 Hz */
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index fa0e719c5bd1..b19820110aa3 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -29,6 +29,7 @@
29#include <linux/sched.h> 29#include <linux/sched.h>
30#include <linux/interrupt.h> 30#include <linux/interrupt.h>
31#include <linux/delay.h> 31#include <linux/delay.h>
32#include <asm/io.h>
32#include <asm/irq.h> 33#include <asm/irq.h>
33#include <asm/mipsregs.h> 34#include <asm/mipsregs.h>
34#include <asm/addrspace.h> 35#include <asm/addrspace.h>
@@ -37,42 +38,29 @@
37#include <asm/sgi/mc.h> 38#include <asm/sgi/mc.h>
38#include <asm/sgi/ip22.h> 39#include <asm/sgi/ip22.h>
39 40
40#define EISA_MAX_SLOTS 4 41/* I2 has four EISA slots. */
42#define IP22_EISA_MAX_SLOTS 4
41#define EISA_MAX_IRQ 16 43#define EISA_MAX_IRQ 16
42 44
43#define EISA_TO_PHYS(x) (0x00080000 | (x)) 45#define EIU_MODE_REG 0x0001ffc0
44#define EISA_TO_KSEG1(x) ((void *) KSEG1ADDR(EISA_TO_PHYS((x)))) 46#define EIU_STAT_REG 0x0001ffc4
45 47#define EIU_PREMPT_REG 0x0001ffc8
46#define EIU_MODE_REG 0x0009ffc0 48#define EIU_QUIET_REG 0x0001ffcc
47#define EIU_STAT_REG 0x0009ffc4 49#define EIU_INTRPT_ACK 0x00010004
48#define EIU_PREMPT_REG 0x0009ffc8 50
49#define EIU_QUIET_REG 0x0009ffcc 51static char __init *decode_eisa_sig(unsigned long addr)
50#define EIU_INTRPT_ACK 0x00090004
51
52#define EISA_DMA1_STATUS 8
53#define EISA_INT1_CTRL 0x20
54#define EISA_INT1_MASK 0x21
55#define EISA_INT2_CTRL 0xA0
56#define EISA_INT2_MASK 0xA1
57#define EISA_DMA2_STATUS 0xD0
58#define EISA_DMA2_WRITE_SINGLE 0xD4
59#define EISA_EXT_NMI_RESET_CTRL 0x461
60#define EISA_INT1_EDGE_LEVEL 0x4D0
61#define EISA_INT2_EDGE_LEVEL 0x4D1
62#define EISA_VENDOR_ID_OFFSET 0xC80
63
64#define EIU_WRITE_32(x,y) { *((u32 *) KSEG1ADDR(x)) = (u32) (y); mb(); }
65#define EIU_READ_8(x) *((u8 *) KSEG1ADDR(x))
66#define EISA_WRITE_8(x,y) { *((u8 *) EISA_TO_KSEG1(x)) = (u8) (y); mb(); }
67#define EISA_READ_8(x) *((u8 *) EISA_TO_KSEG1(x))
68
69static char *decode_eisa_sig(u8 * sig)
70{ 52{
71 static char sig_str[8]; 53 static char sig_str[EISA_SIG_LEN];
72 u16 rev; 54 u8 sig[4];
55 u16 rev;
56 int i;
57
58 for (i = 0; i < 4; i++) {
59 sig[i] = inb (addr + i);
73 60
74 if (sig[0] & 0x80) 61 if (!i && (sig[0] & 0x80))
75 return NULL; 62 return NULL;
63 }
76 64
77 sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1); 65 sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1);
78 sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1); 66 sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1);
@@ -83,23 +71,26 @@ static char *decode_eisa_sig(u8 * sig)
83 return sig_str; 71 return sig_str;
84} 72}
85 73
86static void ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs) 74static irqreturn_t ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs)
87{ 75{
88 u8 eisa_irq; 76 u8 eisa_irq;
89 u8 dma1, dma2; 77 u8 dma1, dma2;
90 78
91 eisa_irq = EIU_READ_8(EIU_INTRPT_ACK); 79 eisa_irq = inb(EIU_INTRPT_ACK);
92 dma1 = EISA_READ_8(EISA_DMA1_STATUS); 80 dma1 = inb(EISA_DMA1_STATUS);
93 dma2 = EISA_READ_8(EISA_DMA2_STATUS); 81 dma2 = inb(EISA_DMA2_STATUS);
94
95 if (eisa_irq >= EISA_MAX_IRQ) {
96 /* Oops, Bad Stuff Happened... */
97 printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq);
98 82
99 EISA_WRITE_8(EISA_INT2_CTRL, 0x20); 83 if (eisa_irq < EISA_MAX_IRQ) {
100 EISA_WRITE_8(EISA_INT1_CTRL, 0x20);
101 } else
102 do_IRQ(eisa_irq, regs); 84 do_IRQ(eisa_irq, regs);
85 return IRQ_HANDLED;
86 }
87
88 /* Oops, Bad Stuff Happened... */
89 printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq);
90
91 outb(0x20, EISA_INT2_CTRL);
92 outb(0x20, EISA_INT1_CTRL);
93 return IRQ_NONE;
103} 94}
104 95
105static void enable_eisa1_irq(unsigned int irq) 96static void enable_eisa1_irq(unsigned int irq)
@@ -109,9 +100,9 @@ static void enable_eisa1_irq(unsigned int irq)
109 100
110 local_irq_save(flags); 101 local_irq_save(flags);
111 102
112 mask = EISA_READ_8(EISA_INT1_MASK); 103 mask = inb(EISA_INT1_MASK);
113 mask &= ~((u8) (1 << irq)); 104 mask &= ~((u8) (1 << irq));
114 EISA_WRITE_8(EISA_INT1_MASK, mask); 105 outb(mask, EISA_INT1_MASK);
115 106
116 local_irq_restore(flags); 107 local_irq_restore(flags);
117} 108}
@@ -122,9 +113,9 @@ static unsigned int startup_eisa1_irq(unsigned int irq)
122 113
123 /* Only use edge interrupts for EISA */ 114 /* Only use edge interrupts for EISA */
124 115
125 edge = EISA_READ_8(EISA_INT1_EDGE_LEVEL); 116 edge = inb(EISA_INT1_EDGE_LEVEL);
126 edge &= ~((u8) (1 << irq)); 117 edge &= ~((u8) (1 << irq));
127 EISA_WRITE_8(EISA_INT1_EDGE_LEVEL, edge); 118 outb(edge, EISA_INT1_EDGE_LEVEL);
128 119
129 enable_eisa1_irq(irq); 120 enable_eisa1_irq(irq);
130 return 0; 121 return 0;
@@ -134,9 +125,9 @@ static void disable_eisa1_irq(unsigned int irq)
134{ 125{
135 u8 mask; 126 u8 mask;
136 127
137 mask = EISA_READ_8(EISA_INT1_MASK); 128 mask = inb(EISA_INT1_MASK);
138 mask |= ((u8) (1 << irq)); 129 mask |= ((u8) (1 << irq));
139 EISA_WRITE_8(EISA_INT1_MASK, mask); 130 outb(mask, EISA_INT1_MASK);
140} 131}
141 132
142#define shutdown_eisa1_irq disable_eisa1_irq 133#define shutdown_eisa1_irq disable_eisa1_irq
@@ -145,7 +136,7 @@ static void mask_and_ack_eisa1_irq(unsigned int irq)
145{ 136{
146 disable_eisa1_irq(irq); 137 disable_eisa1_irq(irq);
147 138
148 EISA_WRITE_8(EISA_INT1_CTRL, 0x20); 139 outb(0x20, EISA_INT1_CTRL);
149} 140}
150 141
151static void end_eisa1_irq(unsigned int irq) 142static void end_eisa1_irq(unsigned int irq)
@@ -171,9 +162,9 @@ static void enable_eisa2_irq(unsigned int irq)
171 162
172 local_irq_save(flags); 163 local_irq_save(flags);
173 164
174 mask = EISA_READ_8(EISA_INT2_MASK); 165 mask = inb(EISA_INT2_MASK);
175 mask &= ~((u8) (1 << (irq - 8))); 166 mask &= ~((u8) (1 << (irq - 8)));
176 EISA_WRITE_8(EISA_INT2_MASK, mask); 167 outb(mask, EISA_INT2_MASK);
177 168
178 local_irq_restore(flags); 169 local_irq_restore(flags);
179} 170}
@@ -184,9 +175,9 @@ static unsigned int startup_eisa2_irq(unsigned int irq)
184 175
185 /* Only use edge interrupts for EISA */ 176 /* Only use edge interrupts for EISA */
186 177
187 edge = EISA_READ_8(EISA_INT2_EDGE_LEVEL); 178 edge = inb(EISA_INT2_EDGE_LEVEL);
188 edge &= ~((u8) (1 << (irq - 8))); 179 edge &= ~((u8) (1 << (irq - 8)));
189 EISA_WRITE_8(EISA_INT2_EDGE_LEVEL, edge); 180 outb(edge, EISA_INT2_EDGE_LEVEL);
190 181
191 enable_eisa2_irq(irq); 182 enable_eisa2_irq(irq);
192 return 0; 183 return 0;
@@ -196,9 +187,9 @@ static void disable_eisa2_irq(unsigned int irq)
196{ 187{
197 u8 mask; 188 u8 mask;
198 189
199 mask = EISA_READ_8(EISA_INT2_MASK); 190 mask = inb(EISA_INT2_MASK);
200 mask |= ((u8) (1 << (irq - 8))); 191 mask |= ((u8) (1 << (irq - 8)));
201 EISA_WRITE_8(EISA_INT2_MASK, mask); 192 outb(mask, EISA_INT2_MASK);
202} 193}
203 194
204#define shutdown_eisa2_irq disable_eisa2_irq 195#define shutdown_eisa2_irq disable_eisa2_irq
@@ -207,8 +198,7 @@ static void mask_and_ack_eisa2_irq(unsigned int irq)
207{ 198{
208 disable_eisa2_irq(irq); 199 disable_eisa2_irq(irq);
209 200
210 EISA_WRITE_8(EISA_INT2_CTRL, 0x20); 201 outb(0x20, EISA_INT2_CTRL);
211 EISA_WRITE_8(EISA_INT1_CTRL, 0x20);
212} 202}
213 203
214static void end_eisa2_irq(unsigned int irq) 204static void end_eisa2_irq(unsigned int irq)
@@ -241,7 +231,6 @@ int __init ip22_eisa_init(void)
241{ 231{
242 int i, c; 232 int i, c;
243 char *str; 233 char *str;
244 u8 *slot_addr;
245 234
246 if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) { 235 if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) {
247 printk(KERN_INFO "EISA: bus not present.\n"); 236 printk(KERN_INFO "EISA: bus not present.\n");
@@ -249,11 +238,8 @@ int __init ip22_eisa_init(void)
249 } 238 }
250 239
251 printk(KERN_INFO "EISA: Probing bus...\n"); 240 printk(KERN_INFO "EISA: Probing bus...\n");
252 for (c = 0, i = 1; i <= EISA_MAX_SLOTS; i++) { 241 for (c = 0, i = 1; i <= IP22_EISA_MAX_SLOTS; i++) {
253 slot_addr = 242 if ((str = decode_eisa_sig(0x1000 * i + EISA_VENDOR_ID_OFFSET))) {
254 (u8 *) EISA_TO_KSEG1((0x1000 * i) +
255 EISA_VENDOR_ID_OFFSET);
256 if ((str = decode_eisa_sig(slot_addr))) {
257 printk(KERN_INFO "EISA: slot %d : %s detected.\n", 243 printk(KERN_INFO "EISA: slot %d : %s detected.\n",
258 i, str); 244 i, str);
259 c++; 245 c++;
@@ -268,25 +254,25 @@ int __init ip22_eisa_init(void)
268 Please wave your favorite dead chicken over the busses */ 254 Please wave your favorite dead chicken over the busses */
269 255
270 /* First say hello to the EIU */ 256 /* First say hello to the EIU */
271 EIU_WRITE_32(EIU_PREMPT_REG, 0x0000FFFF); 257 outl(0x0000FFFF, EIU_PREMPT_REG);
272 EIU_WRITE_32(EIU_QUIET_REG, 1); 258 outl(1, EIU_QUIET_REG);
273 EIU_WRITE_32(EIU_MODE_REG, 0x40f3c07F); 259 outl(0x40f3c07F, EIU_MODE_REG);
274 260
275 /* Now be nice to the EISA chipset */ 261 /* Now be nice to the EISA chipset */
276 EISA_WRITE_8(EISA_EXT_NMI_RESET_CTRL, 1); 262 outb(1, EISA_EXT_NMI_RESET_CTRL);
277 for (i = 0; i < 10000; i++); /* Wait long enough for the dust to settle */ 263 udelay(50); /* Wait long enough for the dust to settle */
278 EISA_WRITE_8(EISA_EXT_NMI_RESET_CTRL, 0); 264 outb(0, EISA_EXT_NMI_RESET_CTRL);
279 EISA_WRITE_8(EISA_INT1_CTRL, 0x11); 265 outb(0x11, EISA_INT1_CTRL);
280 EISA_WRITE_8(EISA_INT2_CTRL, 0x11); 266 outb(0x11, EISA_INT2_CTRL);
281 EISA_WRITE_8(EISA_INT1_MASK, 0); 267 outb(0, EISA_INT1_MASK);
282 EISA_WRITE_8(EISA_INT2_MASK, 8); 268 outb(8, EISA_INT2_MASK);
283 EISA_WRITE_8(EISA_INT1_MASK, 4); 269 outb(4, EISA_INT1_MASK);
284 EISA_WRITE_8(EISA_INT2_MASK, 2); 270 outb(2, EISA_INT2_MASK);
285 EISA_WRITE_8(EISA_INT1_MASK, 1); 271 outb(1, EISA_INT1_MASK);
286 EISA_WRITE_8(EISA_INT2_MASK, 1); 272 outb(1, EISA_INT2_MASK);
287 EISA_WRITE_8(EISA_INT1_MASK, 0xfb); 273 outb(0xfb, EISA_INT1_MASK);
288 EISA_WRITE_8(EISA_INT2_MASK, 0xff); 274 outb(0xff, EISA_INT2_MASK);
289 EISA_WRITE_8(EISA_DMA2_WRITE_SINGLE, 0); 275 outb(0, EISA_DMA2_WRITE_SINGLE);
290 276
291 for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) { 277 for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
292 irq_desc[i].status = IRQ_DISABLED; 278 irq_desc[i].status = IRQ_DISABLED;
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index 0e96a5d67993..5e59b4c8876b 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -53,7 +53,7 @@ EXPORT_SYMBOL(ip22_do_break);
53extern void ip22_be_init(void) __init; 53extern void ip22_be_init(void) __init;
54extern void ip22_time_init(void) __init; 54extern void ip22_time_init(void) __init;
55 55
56static int __init ip22_setup(void) 56void __init plat_setup(void)
57{ 57{
58 char *ctype; 58 char *ctype;
59 59
@@ -137,8 +137,4 @@ static int __init ip22_setup(void)
137 } 137 }
138 } 138 }
139#endif 139#endif
140
141 return 0;
142} 140}
143
144early_initcall(ip22_setup);
diff --git a/arch/mips/sgi-ip27/Kconfig b/arch/mips/sgi-ip27/Kconfig
new file mode 100644
index 000000000000..7b0bc4437243
--- /dev/null
+++ b/arch/mips/sgi-ip27/Kconfig
@@ -0,0 +1,54 @@
1#config SGI_SN0_XXL
2# bool "IP27 XXL"
3# depends on SGI_IP27
4# This options adds support for userspace processes upto 16TB size.
5# Normally the limit is just .5TB.
6
7config SGI_SN0_N_MODE
8 bool "IP27 N-Mode"
9 depends on SGI_IP27
10 help
11 The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be
12 configured in either N-Modes which allows for more nodes or M-Mode
13 which allows for more memory. Your system is most probably
14 running in M-Mode, so you should say N here.
15
16config ARCH_DISCONTIGMEM_ENABLE
17 bool
18 default y if SGI_IP27
19 help
20 Say Y to upport efficient handling of discontiguous physical memory,
21 for architectures which are either NUMA (Non-Uniform Memory Access)
22 or have huge holes in the physical address space for other reasons.
23 See <file:Documentation/vm/numa> for more.
24
25config NUMA
26 bool "NUMA Support"
27 depends on SGI_IP27
28 help
29 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
30 Access). This option is for configuring high-end multiprocessor
31 server machines. If in doubt, say N.
32
33config MAPPED_KERNEL
34 bool "Mapped kernel support"
35 depends on SGI_IP27
36 help
37 Change the way a Linux kernel is loaded into memory on a MIPS64
38 machine. This is required in order to support text replication and
39 NUMA. If you need to understand it, read the source code.
40
41config REPLICATE_KTEXT
42 bool "Kernel text replication support"
43 depends on SGI_IP27
44 help
45 Say Y here to enable replicating the kernel text across multiple
46 nodes in a NUMA cluster. This trades memory for speed.
47
48config REPLICATE_EXHANDLERS
49 bool "Exception handler replication support"
50 depends on SGI_IP27
51 help
52 Say Y here to enable replicating the kernel exception handlers
53 across multiple nodes in a NUMA cluster. This trades memory for
54 speed.
diff --git a/arch/mips/sgi-ip27/ip27-console.c b/arch/mips/sgi-ip27/ip27-console.c
index d97f5b5ef844..3e1ac299b804 100644
--- a/arch/mips/sgi-ip27/ip27-console.c
+++ b/arch/mips/sgi-ip27/ip27-console.c
@@ -30,8 +30,10 @@
30static inline struct ioc3_uartregs *console_uart(void) 30static inline struct ioc3_uartregs *console_uart(void)
31{ 31{
32 struct ioc3 *ioc3; 32 struct ioc3 *ioc3;
33 nasid_t nasid;
33 34
34 ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(get_nasid())->memory_base; 35 nasid = (master_nasid == INVALID_NASID) ? get_nasid() : master_nasid;
36 ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(nasid)->memory_base;
35 37
36 return &ioc3->sregs.uarta; 38 return &ioc3->sregs.uarta;
37} 39}
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index 6dcee5c46c74..8651a0e75404 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -56,12 +56,12 @@ static void __init per_hub_init(cnodeid_t cnode)
56{ 56{
57 struct hub_data *hub = hub_data(cnode); 57 struct hub_data *hub = hub_data(cnode);
58 nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode); 58 nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode);
59 int i;
59 60
60 cpu_set(smp_processor_id(), hub->h_cpus); 61 cpu_set(smp_processor_id(), hub->h_cpus);
61 62
62 if (test_and_set_bit(cnode, hub_init_mask)) 63 if (test_and_set_bit(cnode, hub_init_mask))
63 return; 64 return;
64
65 /* 65 /*
66 * Set CRB timeout at 5ms, (< PI timeout of 10ms) 66 * Set CRB timeout at 5ms, (< PI timeout of 10ms)
67 */ 67 */
@@ -88,6 +88,24 @@ static void __init per_hub_init(cnodeid_t cnode)
88 __flush_cache_all(); 88 __flush_cache_all();
89 } 89 }
90#endif 90#endif
91
92 /*
93 * Some interrupts are reserved by hardware or by software convention.
94 * Mark these as reserved right away so they won't be used accidently
95 * later.
96 */
97 for (i = 0; i <= BASE_PCI_IRQ; i++) {
98 __set_bit(i, hub->irq_alloc_mask);
99 LOCAL_HUB_CLR_INTR(INT_PEND0_BASELVL + i);
100 }
101
102 __set_bit(IP_PEND0_6_63, hub->irq_alloc_mask);
103 LOCAL_HUB_S(PI_INT_PEND_MOD, IP_PEND0_6_63);
104
105 for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) {
106 __set_bit(i, hub->irq_alloc_mask);
107 LOCAL_HUB_CLR_INTR(INT_PEND1_BASELVL + i);
108 }
91} 109}
92 110
93void __init per_cpu_init(void) 111void __init per_cpu_init(void)
@@ -104,30 +122,12 @@ void __init per_cpu_init(void)
104 122
105 clear_c0_status(ST0_IM); 123 clear_c0_status(ST0_IM);
106 124
125 per_hub_init(cnode);
126
107 for (i = 0; i < LEVELS_PER_SLICE; i++) 127 for (i = 0; i < LEVELS_PER_SLICE; i++)
108 si->level_to_irq[i] = -1; 128 si->level_to_irq[i] = -1;
109 129
110 /* 130 /*
111 * Some interrupts are reserved by hardware or by software convention.
112 * Mark these as reserved right away so they won't be used accidently
113 * later.
114 */
115 for (i = 0; i <= BASE_PCI_IRQ; i++) {
116 __set_bit(i, si->irq_alloc_mask);
117 LOCAL_HUB_S(PI_INT_PEND_MOD, i);
118 }
119
120 __set_bit(IP_PEND0_6_63, si->irq_alloc_mask);
121 LOCAL_HUB_S(PI_INT_PEND_MOD, IP_PEND0_6_63);
122
123 for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) {
124 __set_bit(i, si->irq_alloc_mask + 1);
125 LOCAL_HUB_S(PI_INT_PEND_MOD, i);
126 }
127
128 LOCAL_HUB_L(PI_INT_PEND0);
129
130 /*
131 * We use this so we can find the local hub's data as fast as only 131 * We use this so we can find the local hub's data as fast as only
132 * possible. 132 * possible.
133 */ 133 */
@@ -140,8 +140,6 @@ void __init per_cpu_init(void)
140 install_cpu_nmi_handler(cputoslice(cpu)); 140 install_cpu_nmi_handler(cputoslice(cpu));
141 141
142 set_c0_status(SRB_DEV0 | SRB_DEV1); 142 set_c0_status(SRB_DEV0 | SRB_DEV1);
143
144 per_hub_init(cnode);
145} 143}
146 144
147/* 145/*
@@ -198,7 +196,7 @@ extern void ip27_setup_console(void);
198extern void ip27_time_init(void); 196extern void ip27_time_init(void);
199extern void ip27_reboot_setup(void); 197extern void ip27_reboot_setup(void);
200 198
201static int __init ip27_setup(void) 199void __init plat_setup(void)
202{ 200{
203 hubreg_t p, e, n_mode; 201 hubreg_t p, e, n_mode;
204 nasid_t nid; 202 nasid_t nid;
@@ -245,8 +243,4 @@ static int __init ip27_setup(void)
245 set_io_port_base(IO_BASE); 243 set_io_port_base(IO_BASE);
246 244
247 board_time_init = ip27_time_init; 245 board_time_init = ip27_time_init;
248
249 return 0;
250} 246}
251
252early_initcall(ip27_setup);
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 61817a18aed2..73e5e52781d8 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -5,6 +5,9 @@
5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
6 * Copyright (C) 1999 - 2001 Kanoj Sarcar 6 * Copyright (C) 1999 - 2001 Kanoj Sarcar
7 */ 7 */
8
9#undef DEBUG
10
8#include <linux/config.h> 11#include <linux/config.h>
9#include <linux/init.h> 12#include <linux/init.h>
10#include <linux/irq.h> 13#include <linux/irq.h>
@@ -14,11 +17,11 @@
14#include <linux/types.h> 17#include <linux/types.h>
15#include <linux/interrupt.h> 18#include <linux/interrupt.h>
16#include <linux/ioport.h> 19#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/timex.h> 20#include <linux/timex.h>
19#include <linux/slab.h> 21#include <linux/slab.h>
20#include <linux/random.h> 22#include <linux/random.h>
21#include <linux/smp_lock.h> 23#include <linux/smp_lock.h>
24#include <linux/kernel.h>
22#include <linux/kernel_stat.h> 25#include <linux/kernel_stat.h>
23#include <linux/delay.h> 26#include <linux/delay.h>
24#include <linux/bitops.h> 27#include <linux/bitops.h>
@@ -37,13 +40,6 @@
37#include <asm/sn/hub.h> 40#include <asm/sn/hub.h>
38#include <asm/sn/intr.h> 41#include <asm/sn/intr.h>
39 42
40#undef DEBUG_IRQ
41#ifdef DEBUG_IRQ
42#define DBG(x...) printk(x)
43#else
44#define DBG(x...)
45#endif
46
47/* 43/*
48 * Linux has a controller-independent x86 interrupt architecture. 44 * Linux has a controller-independent x86 interrupt architecture.
49 * every controller has a 'controller-template', that is used 45 * every controller has a 'controller-template', that is used
@@ -74,14 +70,15 @@ extern int irq_to_slot[];
74 70
75static inline int alloc_level(int cpu, int irq) 71static inline int alloc_level(int cpu, int irq)
76{ 72{
73 struct hub_data *hub = hub_data(cpu_to_node(cpu));
77 struct slice_data *si = cpu_data[cpu].data; 74 struct slice_data *si = cpu_data[cpu].data;
78 int level; /* pre-allocated entries */ 75 int level;
79 76
80 level = find_first_zero_bit(si->irq_alloc_mask, LEVELS_PER_SLICE); 77 level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
81 if (level >= LEVELS_PER_SLICE) 78 if (level >= LEVELS_PER_SLICE)
82 panic("Cpu %d flooded with devices\n", cpu); 79 panic("Cpu %d flooded with devices\n", cpu);
83 80
84 __set_bit(level, si->irq_alloc_mask); 81 __set_bit(level, hub->irq_alloc_mask);
85 si->level_to_irq[level] = irq; 82 si->level_to_irq[level] = irq;
86 83
87 return level; 84 return level;
@@ -216,9 +213,11 @@ static int intr_connect_level(int cpu, int bit)
216{ 213{
217 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 214 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
218 struct slice_data *si = cpu_data[cpu].data; 215 struct slice_data *si = cpu_data[cpu].data;
216 unsigned long flags;
219 217
220 __set_bit(bit, si->irq_enable_mask); 218 set_bit(bit, si->irq_enable_mask);
221 219
220 local_irq_save(flags);
222 if (!cputoslice(cpu)) { 221 if (!cputoslice(cpu)) {
223 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); 222 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
224 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); 223 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
@@ -226,6 +225,7 @@ static int intr_connect_level(int cpu, int bit)
226 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); 225 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
227 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); 226 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
228 } 227 }
228 local_irq_restore(flags);
229 229
230 return 0; 230 return 0;
231} 231}
@@ -235,7 +235,7 @@ static int intr_disconnect_level(int cpu, int bit)
235 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 235 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
236 struct slice_data *si = cpu_data[cpu].data; 236 struct slice_data *si = cpu_data[cpu].data;
237 237
238 __clear_bit(bit, si->irq_enable_mask); 238 clear_bit(bit, si->irq_enable_mask);
239 239
240 if (!cputoslice(cpu)) { 240 if (!cputoslice(cpu)) {
241 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); 241 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
@@ -261,7 +261,7 @@ static unsigned int startup_bridge_irq(unsigned int irq)
261 bc = IRQ_TO_BRIDGE(irq); 261 bc = IRQ_TO_BRIDGE(irq);
262 bridge = bc->base; 262 bridge = bc->base;
263 263
264 DBG("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin); 264 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin);
265 /* 265 /*
266 * "map" irq to a swlevel greater than 6 since the first 6 bits 266 * "map" irq to a swlevel greater than 6 since the first 6 bits
267 * of INT_PEND0 are taken 267 * of INT_PEND0 are taken
@@ -298,12 +298,13 @@ static unsigned int startup_bridge_irq(unsigned int irq)
298static void shutdown_bridge_irq(unsigned int irq) 298static void shutdown_bridge_irq(unsigned int irq)
299{ 299{
300 struct bridge_controller *bc = IRQ_TO_BRIDGE(irq); 300 struct bridge_controller *bc = IRQ_TO_BRIDGE(irq);
301 struct hub_data *hub = hub_data(cpu_to_node(bc->irq_cpu));
301 bridge_t *bridge = bc->base; 302 bridge_t *bridge = bc->base;
302 struct slice_data *si = cpu_data[bc->irq_cpu].data; 303 struct slice_data *si = cpu_data[bc->irq_cpu].data;
303 int pin, swlevel; 304 int pin, swlevel;
304 cpuid_t cpu; 305 cpuid_t cpu;
305 306
306 DBG("bridge_shutdown: irq 0x%x\n", irq); 307 pr_debug("bridge_shutdown: irq 0x%x\n", irq);
307 pin = SLOT_FROM_PCI_IRQ(irq); 308 pin = SLOT_FROM_PCI_IRQ(irq);
308 309
309 /* 310 /*
@@ -313,7 +314,7 @@ static void shutdown_bridge_irq(unsigned int irq)
313 swlevel = find_level(&cpu, irq); 314 swlevel = find_level(&cpu, irq);
314 intr_disconnect_level(cpu, swlevel); 315 intr_disconnect_level(cpu, swlevel);
315 316
316 __clear_bit(swlevel, si->irq_alloc_mask); 317 __clear_bit(swlevel, hub->irq_alloc_mask);
317 si->level_to_irq[swlevel] = -1; 318 si->level_to_irq[swlevel] = -1;
318 319
319 bridge->b_int_enable &= ~(1 << pin); 320 bridge->b_int_enable &= ~(1 << pin);
@@ -433,25 +434,24 @@ void install_ipi(void)
433 int slice = LOCAL_HUB_L(PI_CPU_NUM); 434 int slice = LOCAL_HUB_L(PI_CPU_NUM);
434 int cpu = smp_processor_id(); 435 int cpu = smp_processor_id();
435 struct slice_data *si = cpu_data[cpu].data; 436 struct slice_data *si = cpu_data[cpu].data;
436 hubreg_t mask, set; 437 struct hub_data *hub = hub_data(cpu_to_node(cpu));
438 int resched, call;
439
440 resched = CPU_RESCHED_A_IRQ + slice;
441 __set_bit(resched, hub->irq_alloc_mask);
442 __set_bit(resched, si->irq_enable_mask);
443 LOCAL_HUB_CLR_INTR(resched);
444
445 call = CPU_CALL_A_IRQ + slice;
446 __set_bit(call, hub->irq_alloc_mask);
447 __set_bit(call, si->irq_enable_mask);
448 LOCAL_HUB_CLR_INTR(call);
437 449
438 if (slice == 0) { 450 if (slice == 0) {
439 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ); 451 LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]);
440 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ); 452 LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]);
441 mask = LOCAL_HUB_L(PI_INT_MASK0_A); /* Slice A */
442 set = (1UL << CPU_RESCHED_A_IRQ) | (1UL << CPU_CALL_A_IRQ);
443 mask |= set;
444 si->irq_enable_mask[0] |= set;
445 si->irq_alloc_mask[0] |= set;
446 LOCAL_HUB_S(PI_INT_MASK0_A, mask);
447 } else { 453 } else {
448 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ); 454 LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]);
449 LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ); 455 LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]);
450 mask = LOCAL_HUB_L(PI_INT_MASK0_B); /* Slice B */
451 set = (1UL << CPU_RESCHED_B_IRQ) | (1UL << CPU_CALL_B_IRQ);
452 mask |= set;
453 si->irq_enable_mask[1] |= set;
454 si->irq_alloc_mask[1] |= set;
455 LOCAL_HUB_S(PI_INT_MASK0_B, mask);
456 } 456 }
457} 457}
diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
index 17f768cba94f..3a8291b7d26d 100644
--- a/arch/mips/sgi-ip27/ip27-smp.c
+++ b/arch/mips/sgi-ip27/ip27-smp.c
@@ -127,37 +127,28 @@ void cpu_node_probe(void)
127 printk("Discovered %d cpus on %d nodes\n", highest + 1, num_online_nodes()); 127 printk("Discovered %d cpus on %d nodes\n", highest + 1, num_online_nodes());
128} 128}
129 129
130static void intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend, 130static __init void intr_clear_all(nasid_t nasid)
131 int base_level)
132{ 131{
133 volatile hubreg_t bits;
134 int i; 132 int i;
135 133
136 /* Check pending interrupts */
137 if ((bits = HUB_L(pend)) != 0)
138 for (i = 0; i < N_INTPEND_BITS; i++)
139 if (bits & (1 << i))
140 LOCAL_HUB_CLR_INTR(base_level + i);
141}
142
143static void intr_clear_all(nasid_t nasid)
144{
145 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, 0); 134 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, 0);
146 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, 0); 135 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, 0);
147 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, 0); 136 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, 0);
148 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, 0); 137 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, 0);
149 intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND0), 138
150 INT_PEND0_BASELVL); 139 for (i = 0; i < 128; i++)
151 intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND1), 140 REMOTE_HUB_CLR_INTR(nasid, i);
152 INT_PEND1_BASELVL);
153} 141}
154 142
155void __init prom_prepare_cpus(unsigned int max_cpus) 143void __init prom_prepare_cpus(unsigned int max_cpus)
156{ 144{
157 cnodeid_t cnode; 145 cnodeid_t cnode;
158 146
159 for_each_online_node(cnode) 147 for_each_online_node(cnode) {
148 if (cnode == 0)
149 continue;
160 intr_clear_all(COMPACT_TO_NASID_NODEID(cnode)); 150 intr_clear_all(COMPACT_TO_NASID_NODEID(cnode));
151 }
161 152
162 replicate_kernel_text(); 153 replicate_kernel_text();
163 154
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index fc3a8e90d763..2eb22d692ed9 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -163,14 +163,13 @@ static void end_cpu_irq(unsigned int irq)
163#define mask_and_ack_cpu_irq disable_cpu_irq 163#define mask_and_ack_cpu_irq disable_cpu_irq
164 164
165static struct hw_interrupt_type ip32_cpu_interrupt = { 165static struct hw_interrupt_type ip32_cpu_interrupt = {
166 "IP32 CPU", 166 .typename = "IP32 CPU",
167 startup_cpu_irq, 167 .startup = startup_cpu_irq,
168 shutdown_cpu_irq, 168 .shutdown = shutdown_cpu_irq,
169 enable_cpu_irq, 169 .enable = enable_cpu_irq,
170 disable_cpu_irq, 170 .disable = disable_cpu_irq,
171 mask_and_ack_cpu_irq, 171 .ack = mask_and_ack_cpu_irq,
172 end_cpu_irq, 172 .end = end_cpu_irq,
173 NULL
174}; 173};
175 174
176/* 175/*
@@ -234,14 +233,13 @@ static void end_crime_irq(unsigned int irq)
234#define shutdown_crime_irq disable_crime_irq 233#define shutdown_crime_irq disable_crime_irq
235 234
236static struct hw_interrupt_type ip32_crime_interrupt = { 235static struct hw_interrupt_type ip32_crime_interrupt = {
237 "IP32 CRIME", 236 .typename = "IP32 CRIME",
238 startup_crime_irq, 237 .startup = startup_crime_irq,
239 shutdown_crime_irq, 238 .shutdown = shutdown_crime_irq,
240 enable_crime_irq, 239 .enable = enable_crime_irq,
241 disable_crime_irq, 240 .disable = disable_crime_irq,
242 mask_and_ack_crime_irq, 241 .ack = mask_and_ack_crime_irq,
243 end_crime_irq, 242 .end = end_crime_irq,
244 NULL
245}; 243};
246 244
247/* 245/*
@@ -294,14 +292,13 @@ static void end_macepci_irq(unsigned int irq)
294#define mask_and_ack_macepci_irq disable_macepci_irq 292#define mask_and_ack_macepci_irq disable_macepci_irq
295 293
296static struct hw_interrupt_type ip32_macepci_interrupt = { 294static struct hw_interrupt_type ip32_macepci_interrupt = {
297 "IP32 MACE PCI", 295 .typename = "IP32 MACE PCI",
298 startup_macepci_irq, 296 .startup = startup_macepci_irq,
299 shutdown_macepci_irq, 297 .shutdown = shutdown_macepci_irq,
300 enable_macepci_irq, 298 .enable = enable_macepci_irq,
301 disable_macepci_irq, 299 .disable = disable_macepci_irq,
302 mask_and_ack_macepci_irq, 300 .ack = mask_and_ack_macepci_irq,
303 end_macepci_irq, 301 .end = end_macepci_irq,
304 NULL
305}; 302};
306 303
307/* This is used for MACE ISA interrupts. That means bits 4-6 in the 304/* This is used for MACE ISA interrupts. That means bits 4-6 in the
@@ -425,14 +422,13 @@ static void end_maceisa_irq(unsigned irq)
425#define shutdown_maceisa_irq disable_maceisa_irq 422#define shutdown_maceisa_irq disable_maceisa_irq
426 423
427static struct hw_interrupt_type ip32_maceisa_interrupt = { 424static struct hw_interrupt_type ip32_maceisa_interrupt = {
428 "IP32 MACE ISA", 425 .typename = "IP32 MACE ISA",
429 startup_maceisa_irq, 426 .startup = startup_maceisa_irq,
430 shutdown_maceisa_irq, 427 .shutdown = shutdown_maceisa_irq,
431 enable_maceisa_irq, 428 .enable = enable_maceisa_irq,
432 disable_maceisa_irq, 429 .disable = disable_maceisa_irq,
433 mask_and_ack_maceisa_irq, 430 .ack = mask_and_ack_maceisa_irq,
434 end_maceisa_irq, 431 .end = end_maceisa_irq,
435 NULL
436}; 432};
437 433
438/* This is used for regular non-ISA, non-PCI MACE interrupts. That means 434/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
@@ -476,14 +472,13 @@ static void end_mace_irq(unsigned int irq)
476#define mask_and_ack_mace_irq disable_mace_irq 472#define mask_and_ack_mace_irq disable_mace_irq
477 473
478static struct hw_interrupt_type ip32_mace_interrupt = { 474static struct hw_interrupt_type ip32_mace_interrupt = {
479 "IP32 MACE", 475 .typename = "IP32 MACE",
480 startup_mace_irq, 476 .startup = startup_mace_irq,
481 shutdown_mace_irq, 477 .shutdown = shutdown_mace_irq,
482 enable_mace_irq, 478 .enable = enable_mace_irq,
483 disable_mace_irq, 479 .disable = disable_mace_irq,
484 mask_and_ack_mace_irq, 480 .ack = mask_and_ack_mace_irq,
485 end_mace_irq, 481 .end = end_mace_irq,
486 NULL
487}; 482};
488 483
489static void ip32_unknown_interrupt(struct pt_regs *regs) 484static void ip32_unknown_interrupt(struct pt_regs *regs)
diff --git a/arch/mips/sgi-ip32/ip32-memory.c b/arch/mips/sgi-ip32/ip32-memory.c
index fc76ca92bab9..d37d40a3cdae 100644
--- a/arch/mips/sgi-ip32/ip32-memory.c
+++ b/arch/mips/sgi-ip32/ip32-memory.c
@@ -36,8 +36,8 @@ void __init prom_meminit (void)
36 if (base + size > (256 << 20)) 36 if (base + size > (256 << 20))
37 base += CRIME_HI_MEM_BASE; 37 base += CRIME_HI_MEM_BASE;
38 38
39 printk("CRIME MC: bank %u base 0x%016lx size %luMB\n", 39 printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n",
40 bank, base, size); 40 bank, base, size >> 20);
41 add_memory_region (base, size, BOOT_MEM_RAM); 41 add_memory_region (base, size, BOOT_MEM_RAM);
42 } 42 }
43} 43}
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
index 8d270be58224..d10a269aeae1 100644
--- a/arch/mips/sgi-ip32/ip32-setup.c
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -92,7 +92,7 @@ void __init ip32_timer_setup(struct irqaction *irq)
92 setup_irq(IP32_R4K_TIMER_IRQ, irq); 92 setup_irq(IP32_R4K_TIMER_IRQ, irq);
93} 93}
94 94
95static int __init ip32_setup(void) 95void __init plat_setup(void)
96{ 96{
97 board_be_init = ip32_be_init; 97 board_be_init = ip32_be_init;
98 98
@@ -152,8 +152,4 @@ static int __init ip32_setup(void)
152 } 152 }
153 } 153 }
154#endif 154#endif
155
156 return 0;
157} 155}
158
159early_initcall(ip32_setup);
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
new file mode 100644
index 000000000000..de46f62ac462
--- /dev/null
+++ b/arch/mips/sibyte/Kconfig
@@ -0,0 +1,161 @@
1config SIBYTE_SB1250
2 bool
3 select HW_HAS_PCI
4 select SIBYTE_HAS_LDT
5 select SIBYTE_SB1xxx_SOC
6
7config SIBYTE_BCM1120
8 bool
9 select SIBYTE_BCM112X
10 select SIBYTE_SB1xxx_SOC
11
12config SIBYTE_BCM1125
13 bool
14 select HW_HAS_PCI
15 select SIBYTE_BCM112X
16 select SIBYTE_SB1xxx_SOC
17
18config SIBYTE_BCM1125H
19 bool
20 select HW_HAS_PCI
21 select SIBYTE_BCM112X
22 select SIBYTE_HAS_LDT
23 select SIBYTE_SB1xxx_SOC
24
25config SIBYTE_BCM112X
26 bool
27 select SIBYTE_SB1xxx_SOC
28
29config SIBYTE_BCM1x80
30 bool
31 select HW_HAS_PCI
32 select SIBYTE_SB1xxx_SOC
33
34config SIBYTE_BCM1x55
35 bool
36 select HW_HAS_PCI
37 select SIBYTE_SB1xxx_SOC
38
39config SIBYTE_SB1xxx_SOC
40 bool
41 depends on EXPERIMENTAL
42 select DMA_COHERENT
43 select SIBYTE_CFE
44 select SWAP_IO_SPACE
45 select SYS_SUPPORTS_32BIT_KERNEL
46 select SYS_SUPPORTS_64BIT_KERNEL
47
48choice
49 prompt "SiByte SOC Stepping"
50 depends on SIBYTE_SB1xxx_SOC
51
52config CPU_SB1_PASS_1
53 bool "1250 Pass1"
54 depends on SIBYTE_SB1250
55 select CPU_HAS_PREFETCH
56
57config CPU_SB1_PASS_2_1250
58 bool "1250 An"
59 depends on SIBYTE_SB1250
60 select CPU_SB1_PASS_2
61 help
62 Also called BCM1250 Pass 2
63
64config CPU_SB1_PASS_2_2
65 bool "1250 Bn"
66 depends on SIBYTE_SB1250
67 select CPU_HAS_PREFETCH
68 help
69 Also called BCM1250 Pass 2.2
70
71config CPU_SB1_PASS_4
72 bool "1250 Cn"
73 depends on SIBYTE_SB1250
74 select CPU_HAS_PREFETCH
75 help
76 Also called BCM1250 Pass 3
77
78config CPU_SB1_PASS_2_112x
79 bool "112x Hybrid"
80 depends on SIBYTE_BCM112X
81 select CPU_SB1_PASS_2
82
83config CPU_SB1_PASS_3
84 bool "112x An"
85 depends on SIBYTE_BCM112X
86 select CPU_HAS_PREFETCH
87
88endchoice
89
90config CPU_SB1_PASS_2
91 bool
92
93config SIBYTE_HAS_LDT
94 bool
95 depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
96 default y
97
98config SIMULATION
99 bool "Running under simulation"
100 depends on SIBYTE_SB1xxx_SOC
101 help
102 Build a kernel suitable for running under the GDB simulator.
103 Primarily adjusts the kernel's notion of time.
104
105config CONFIG_SB1_CEX_ALWAYS_FATAL
106 bool "All cache exceptions considered fatal (no recovery attempted)"
107 depends on SIBYTE_SB1xxx_SOC
108
109config CONFIG_SB1_CERR_STALL
110 bool "Stall (rather than panic) on fatal cache error"
111 depends on SIBYTE_SB1xxx_SOC
112
113config SIBYTE_CFE
114 bool "Booting from CFE"
115 depends on SIBYTE_SB1xxx_SOC
116 help
117 Make use of the CFE API for enumerating available memory,
118 controlling secondary CPUs, and possibly console output.
119
120config SIBYTE_CFE_CONSOLE
121 bool "Use firmware console"
122 depends on SIBYTE_CFE
123 help
124 Use the CFE API's console write routines during boot. Other console
125 options (VT console, sb1250 duart console, etc.) should not be
126 configured.
127
128config SIBYTE_STANDALONE
129 bool
130 depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
131 default y
132
133config SIBYTE_STANDALONE_RAM_SIZE
134 int "Memory size (in megabytes)"
135 depends on SIBYTE_STANDALONE
136 default "32"
137
138config SIBYTE_BUS_WATCHER
139 bool "Support for Bus Watcher statistics"
140 depends on SIBYTE_SB1xxx_SOC
141 help
142 Handle and keep statistics on the bus error interrupts (COR_ECC,
143 BAD_ECC, IO_BUS).
144
145config SIBYTE_BW_TRACE
146 bool "Capture bus trace before bus error"
147 depends on SIBYTE_BUS_WATCHER
148 help
149 Run a continuous bus trace, dumping the raw data as soon as
150 a ZBbus error is detected. Cannot work if ZBbus profiling
151 is turned on, and also will interfere with JTAG-based trace
152 buffer activity. Raw buffer data is dumped to console, and
153 must be processed off-line.
154
155config SIBYTE_SB1250_PROF
156 bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
157 depends on SIBYTE_SB1xxx_SOC
158
159config SIBYTE_TBPROF
160 bool "Support for ZBbus profiling"
161 depends on SIBYTE_SB1xxx_SOC
diff --git a/arch/mips/sibyte/bcm1480/Makefile b/arch/mips/sibyte/bcm1480/Makefile
new file mode 100644
index 000000000000..538d5a51ae94
--- /dev/null
+++ b/arch/mips/sibyte/bcm1480/Makefile
@@ -0,0 +1,5 @@
1obj-y := setup.o irq.o irq_handler.o time.o
2
3obj-$(CONFIG_SMP) += smp.o
4
5EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
new file mode 100644
index 000000000000..b2a1ba5d23df
--- /dev/null
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -0,0 +1,476 @@
1/*
2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#include <linux/config.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/linkage.h>
22#include <linux/interrupt.h>
23#include <linux/spinlock.h>
24#include <linux/mm.h>
25#include <linux/slab.h>
26#include <linux/kernel_stat.h>
27
28#include <asm/errno.h>
29#include <asm/signal.h>
30#include <asm/system.h>
31#include <asm/ptrace.h>
32#include <asm/io.h>
33
34#include <asm/sibyte/bcm1480_regs.h>
35#include <asm/sibyte/bcm1480_int.h>
36#include <asm/sibyte/bcm1480_scd.h>
37
38#include <asm/sibyte/sb1250_uart.h>
39#include <asm/sibyte/sb1250.h>
40
41/*
42 * These are the routines that handle all the low level interrupt stuff.
43 * Actions handled here are: initialization of the interrupt map, requesting of
44 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
45 * for interrupt lines
46 */
47
48
49#define shutdown_bcm1480_irq disable_bcm1480_irq
50static void end_bcm1480_irq(unsigned int irq);
51static void enable_bcm1480_irq(unsigned int irq);
52static void disable_bcm1480_irq(unsigned int irq);
53static unsigned int startup_bcm1480_irq(unsigned int irq);
54static void ack_bcm1480_irq(unsigned int irq);
55#ifdef CONFIG_SMP
56static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
57#endif
58
59#ifdef CONFIG_PCI
60extern unsigned long ht_eoi_space;
61#endif
62
63#ifdef CONFIG_KGDB
64#include <asm/gdb-stub.h>
65extern void breakpoint(void);
66static int kgdb_irq;
67#ifdef CONFIG_GDB_CONSOLE
68extern void register_gdb_console(void);
69#endif
70
71/* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */
72static int kgdb_flag = 1;
73static int __init nokgdb(char *str)
74{
75 kgdb_flag = 0;
76 return 1;
77}
78__setup("nokgdb", nokgdb);
79
80/* Default to UART1 */
81int kgdb_port = 1;
82#ifdef CONFIG_SIBYTE_SB1250_DUART
83extern char sb1250_duart_present[];
84#endif
85#endif
86
87static struct hw_interrupt_type bcm1480_irq_type = {
88 .typename = "BCM1480-IMR",
89 .startup = startup_bcm1480_irq,
90 .shutdown = shutdown_bcm1480_irq,
91 .enable = enable_bcm1480_irq,
92 .disable = disable_bcm1480_irq,
93 .ack = ack_bcm1480_irq,
94 .end = end_bcm1480_irq,
95#ifdef CONFIG_SMP
96 .set_affinity = bcm1480_set_affinity
97#endif
98};
99
100/* Store the CPU id (not the logical number) */
101int bcm1480_irq_owner[BCM1480_NR_IRQS];
102
103DEFINE_SPINLOCK(bcm1480_imr_lock);
104
105void bcm1480_mask_irq(int cpu, int irq)
106{
107 unsigned long flags;
108 u64 cur_ints,hl_spacing;
109
110 spin_lock_irqsave(&bcm1480_imr_lock, flags);
111 hl_spacing = 0;
112 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
113 hl_spacing = BCM1480_IMR_HL_SPACING;
114 irq -= BCM1480_NR_IRQS_HALF;
115 }
116 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
117 cur_ints |= (((u64) 1) << irq);
118 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
119 spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
120}
121
122void bcm1480_unmask_irq(int cpu, int irq)
123{
124 unsigned long flags;
125 u64 cur_ints,hl_spacing;
126
127 spin_lock_irqsave(&bcm1480_imr_lock, flags);
128 hl_spacing = 0;
129 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
130 hl_spacing = BCM1480_IMR_HL_SPACING;
131 irq -= BCM1480_NR_IRQS_HALF;
132 }
133 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
134 cur_ints &= ~(((u64) 1) << irq);
135 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
136 spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
137}
138
139#ifdef CONFIG_SMP
140static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
141{
142 int i = 0, old_cpu, cpu, int_on;
143 u64 cur_ints;
144 irq_desc_t *desc = irq_desc + irq;
145 unsigned long flags;
146 unsigned int irq_dirty;
147
148 i = first_cpu(mask);
149 if (next_cpu(i, mask) <= NR_CPUS) {
150 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
151 return;
152 }
153
154 /* Convert logical CPU to physical CPU */
155 cpu = cpu_logical_map(i);
156
157 /* Protect against other affinity changers and IMR manipulation */
158 spin_lock_irqsave(&desc->lock, flags);
159 spin_lock(&bcm1480_imr_lock);
160
161 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
162 old_cpu = bcm1480_irq_owner[irq];
163 irq_dirty = irq;
164 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
165 irq_dirty -= BCM1480_NR_IRQS_HALF;
166 }
167
168 int k;
169 for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
170 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
171 int_on = !(cur_ints & (((u64) 1) << irq_dirty));
172 if (int_on) {
173 /* If it was on, mask it */
174 cur_ints |= (((u64) 1) << irq_dirty);
175 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
176 }
177 bcm1480_irq_owner[irq] = cpu;
178 if (int_on) {
179 /* unmask for the new CPU */
180 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
181 cur_ints &= ~(((u64) 1) << irq_dirty);
182 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
183 }
184 }
185 spin_unlock(&bcm1480_imr_lock);
186 spin_unlock_irqrestore(&desc->lock, flags);
187}
188#endif
189
190
191/* Defined in arch/mips/sibyte/bcm1480/irq_handler.S */
192extern void bcm1480_irq_handler(void);
193
194/*****************************************************************************/
195
196static unsigned int startup_bcm1480_irq(unsigned int irq)
197{
198 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
199
200 return 0; /* never anything pending */
201}
202
203
204static void disable_bcm1480_irq(unsigned int irq)
205{
206 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
207}
208
209static void enable_bcm1480_irq(unsigned int irq)
210{
211 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
212}
213
214
215static void ack_bcm1480_irq(unsigned int irq)
216{
217 u64 pending;
218 unsigned int irq_dirty;
219
220 /*
221 * If the interrupt was an HT interrupt, now is the time to
222 * clear it. NOTE: we assume the HT bridge was set up to
223 * deliver the interrupts to all CPUs (which makes affinity
224 * changing easier for us)
225 */
226 irq_dirty = irq;
227 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
228 irq_dirty -= BCM1480_NR_IRQS_HALF;
229 }
230 int k;
231 for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
232 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
233 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
234 pending &= ((u64)1 << (irq_dirty));
235 if (pending) {
236#ifdef CONFIG_SMP
237 int i;
238 for (i=0; i<NR_CPUS; i++) {
239 /*
240 * Clear for all CPUs so an affinity switch
241 * doesn't find an old status
242 */
243 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
244 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
245 }
246#else
247 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
248#endif
249
250 /*
251 * Generate EOI. For Pass 1 parts, EOI is a nop. For
252 * Pass 2, the LDT world may be edge-triggered, but
253 * this EOI shouldn't hurt. If they are
254 * level-sensitive, the EOI is required.
255 */
256#ifdef CONFIG_PCI
257 if (ht_eoi_space)
258 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
259#endif
260 }
261 }
262 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
263}
264
265
266static void end_bcm1480_irq(unsigned int irq)
267{
268 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
269 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
270 }
271}
272
273
274void __init init_bcm1480_irqs(void)
275{
276 int i;
277
278 for (i = 0; i < NR_IRQS; i++) {
279 irq_desc[i].status = IRQ_DISABLED;
280 irq_desc[i].action = 0;
281 irq_desc[i].depth = 1;
282 if (i < BCM1480_NR_IRQS) {
283 irq_desc[i].handler = &bcm1480_irq_type;
284 bcm1480_irq_owner[i] = 0;
285 } else {
286 irq_desc[i].handler = &no_irq_type;
287 }
288 }
289}
290
291
292static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id,
293 struct pt_regs *regs)
294{
295 return IRQ_NONE;
296}
297
298static struct irqaction bcm1480_dummy_action = {
299 .handler = bcm1480_dummy_handler,
300 .flags = 0,
301 .mask = CPU_MASK_NONE,
302 .name = "bcm1480-private",
303 .next = NULL,
304 .dev_id = 0
305};
306
307int bcm1480_steal_irq(int irq)
308{
309 irq_desc_t *desc = irq_desc + irq;
310 unsigned long flags;
311 int retval = 0;
312
313 if (irq >= BCM1480_NR_IRQS)
314 return -EINVAL;
315
316 spin_lock_irqsave(&desc->lock,flags);
317 /* Don't allow sharing at all for these */
318 if (desc->action != NULL)
319 retval = -EBUSY;
320 else {
321 desc->action = &bcm1480_dummy_action;
322 desc->depth = 0;
323 }
324 spin_unlock_irqrestore(&desc->lock,flags);
325 return 0;
326}
327
328/*
329 * init_IRQ is called early in the boot sequence from init/main.c. It
330 * is responsible for setting up the interrupt mapper and installing the
331 * handler that will be responsible for dispatching interrupts to the
332 * "right" place.
333 */
334/*
335 * For now, map all interrupts to IP[2]. We could save
336 * some cycles by parceling out system interrupts to different
337 * IP lines, but keep it simple for bringup. We'll also direct
338 * all interrupts to a single CPU; we should probably route
339 * PCI and LDT to one cpu and everything else to the other
340 * to balance the load a bit.
341 *
342 * On the second cpu, everything is set to IP5, which is
343 * ignored, EXCEPT the mailbox interrupt. That one is
344 * set to IP[2] so it is handled. This is needed so we
345 * can do cross-cpu function calls, as requred by SMP
346 */
347
348#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
349#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
350#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
351#define IMR_IP5_VAL K_BCM1480_INT_MAP_I3
352#define IMR_IP6_VAL K_BCM1480_INT_MAP_I4
353
354void __init arch_init_irq(void)
355{
356
357 unsigned int i, cpu;
358 u64 tmp;
359 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
360 STATUSF_IP1 | STATUSF_IP0;
361
362 /* Default everything to IP2 */
363 /* Start with _high registers which has no bit 0 interrupt source */
364 for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */
365 for (cpu = 0; cpu < 4; cpu++) {
366 __raw_writeq(IMR_IP2_VAL,
367 IOADDR(A_BCM1480_IMR_REGISTER(cpu,
368 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
369 }
370 }
371
372 /* Now do _low registers */
373 for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
374 for (cpu = 0; cpu < 4; cpu++) {
375 __raw_writeq(IMR_IP2_VAL,
376 IOADDR(A_BCM1480_IMR_REGISTER(cpu,
377 R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
378 }
379 }
380
381 init_bcm1480_irqs();
382
383 /*
384 * Map the high 16 bits of mailbox_0 registers to IP[3], for
385 * inter-cpu messages
386 */
387 /* Was I1 */
388 for (cpu = 0; cpu < 4; cpu++) {
389 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
390 (K_BCM1480_INT_MBOX_0_0 << 3)));
391 }
392
393
394 /* Clear the mailboxes. The firmware may leave them dirty */
395 for (cpu = 0; cpu < 4; cpu++) {
396 __raw_writeq(0xffffffffffffffffULL,
397 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
398 __raw_writeq(0xffffffffffffffffULL,
399 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
400 }
401
402
403 /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
404 tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
405 for (cpu = 0; cpu < 4; cpu++) {
406 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
407 }
408 tmp = ~((u64) 0);
409 for (cpu = 0; cpu < 4; cpu++) {
410 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
411 }
412
413 bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0);
414
415 /*
416 * Note that the timer interrupts are also mapped, but this is
417 * done in bcm1480_time_init(). Also, the profiling driver
418 * does its own management of IP7.
419 */
420
421#ifdef CONFIG_KGDB
422 imask |= STATUSF_IP6;
423#endif
424 /* Enable necessary IPs, disable the rest */
425 change_c0_status(ST0_IM, imask);
426 set_except_vector(0, bcm1480_irq_handler);
427
428#ifdef CONFIG_KGDB
429 if (kgdb_flag) {
430 kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
431
432#ifdef CONFIG_SIBYTE_SB1250_DUART
433 sb1250_duart_present[kgdb_port] = 0;
434#endif
435 /* Setup uart 1 settings, mapper */
436 /* QQQ FIXME */
437 __raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port));
438
439 bcm1480_steal_irq(kgdb_irq);
440 __raw_writeq(IMR_IP6_VAL,
441 IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
442 (kgdb_irq<<3));
443 bcm1480_unmask_irq(0, kgdb_irq);
444
445#ifdef CONFIG_GDB_CONSOLE
446 register_gdb_console();
447#endif
448 prom_printf("Waiting for GDB on UART port %d\n", kgdb_port);
449 set_debug_traps();
450 breakpoint();
451 }
452#endif
453}
454
455#ifdef CONFIG_KGDB
456
457#include <linux/delay.h>
458
459#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
460#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
461
462void bcm1480_kgdb_interrupt(struct pt_regs *regs)
463{
464 /*
465 * Clear break-change status (allow some time for the remote
466 * host to stop the break, since we would see another
467 * interrupt on the end-of-break too)
468 */
469 kstat.irqs[smp_processor_id()][kgdb_irq]++;
470 mdelay(500);
471 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
472 M_DUART_RX_EN | M_DUART_TX_EN);
473 set_async_breakpoint(&regs->cp0_epc);
474}
475
476#endif /* CONFIG_KGDB */
diff --git a/arch/mips/sibyte/bcm1480/irq_handler.S b/arch/mips/sibyte/bcm1480/irq_handler.S
new file mode 100644
index 000000000000..408db88d050f
--- /dev/null
+++ b/arch/mips/sibyte/bcm1480/irq_handler.S
@@ -0,0 +1,165 @@
1/*
2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/*
20 * bcm1480_irq_handler() is the routine that is actually called when an
21 * interrupt occurs. It is installed as the exception vector handler in
22 * init_IRQ() in arch/mips/sibyte/bcm1480/irq.c
23 *
24 * In the handle we figure out which interrupts need handling, and use that
25 * to call the dispatcher, which will take care of actually calling
26 * registered handlers
27 *
28 * Note that we take care of all raised interrupts in one go at the handler.
29 * This is more BSDish than the Indy code, and also, IMHO, more sane.
30 */
31#include <linux/config.h>
32
33#include <asm/addrspace.h>
34#include <asm/asm.h>
35#include <asm/mipsregs.h>
36#include <asm/regdef.h>
37#include <asm/stackframe.h>
38#include <asm/sibyte/sb1250_defs.h>
39#include <asm/sibyte/bcm1480_regs.h>
40#include <asm/sibyte/bcm1480_int.h>
41
42/*
43 * What a pain. We have to be really careful saving the upper 32 bits of any
44 * register across function calls if we don't want them trashed--since were
45 * running in -o32, the calling routing never saves the full 64 bits of a
46 * register across a function call. Being the interrupt handler, we're
47 * guaranteed that interrupts are disabled during this code so we don't have
48 * to worry about random interrupts blasting the high 32 bits.
49 */
50
51 .text
52 .set push
53 .set noreorder
54 .set noat
55 .set mips64
56 #.set mips4
57 .align 5
58 NESTED(bcm1480_irq_handler, PT_SIZE, sp)
59 SAVE_ALL
60 CLI
61
62#ifdef CONFIG_SIBYTE_BCM1480_PROF
63 /* Set compare to count to silence count/compare timer interrupts */
64 mfc0 t1, CP0_COUNT
65 mtc0 t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */
66#endif
67 /* Read cause */
68 mfc0 s0, CP0_CAUSE
69
70#ifdef CONFIG_SIBYTE_BCM1480_PROF
71 /* Cpu performance counter interrupt is routed to IP[7] */
72 andi t1, s0, CAUSEF_IP7
73 beqz t1, 0f
74 srl t1, s0, (CAUSEB_BD-2) /* Shift BD bit to bit 2 */
75 and t1, t1, 0x4 /* mask to get just BD bit */
76#ifdef CONFIG_MIPS64
77 dmfc0 a0, CP0_EPC
78 daddu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */
79#else
80 mfc0 a0, CP0_EPC
81 addu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */
82#endif
83 jal sbprof_cpu_intr
84 nop
85 j ret_from_irq
86 nop
870:
88#endif
89
90 /* Timer interrupt is routed to IP[4] */
91 andi t1, s0, CAUSEF_IP4
92 beqz t1, 1f
93 nop
94 jal bcm1480_timer_interrupt
95 move a0, sp /* Pass the registers along */
96 j ret_from_irq
97 nop /* delay slot */
981:
99
100#ifdef CONFIG_SMP
101 /* Mailbox interrupt is routed to IP[3] */
102 andi t1, s0, CAUSEF_IP3
103 beqz t1, 2f
104 nop
105 jal bcm1480_mailbox_interrupt
106 move a0, sp
107 j ret_from_irq
108 nop /* delay slot */
1092:
110#endif
111
112#ifdef CONFIG_KGDB
113 /* KGDB (uart 1) interrupt is routed to IP[6] */
114 andi t1, s0, CAUSEF_IP6
115 beqz t1, 3f
116 nop /* delay slot */
117 jal bcm1480_kgdb_interrupt
118 move a0, sp
119 j ret_from_irq
120 nop /* delay slot */
1213:
122#endif
123
124 and t1, s0, CAUSEF_IP2
125 beqz t1, 9f
126 nop
127
128 /*
129 * Default...we've hit an IP[2] interrupt, which means we've got
130 * to check the 1480 interrupt registers to figure out what to do
131 * Need to detect which CPU we're on, now that smp_affinity is
132 * supported.
133 */
134 PTR_LA v0, CKSEG1 + A_BCM1480_IMR_CPU0_BASE
135#ifdef CONFIG_SMP
136 lw t1, TI_CPU($28)
137 sll t1, t1, BCM1480_IMR_REGISTER_SPACING_SHIFT
138 addu v0, v0, t1
139#endif
140
141 /* Read IP[2] status (get both high and low halves of status) */
142 ld s0, R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H(v0)
143 ld s1, R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L(v0)
144
145 move s2, zero /* intr number */
146 li s3, 64
147
148 beqz s0, 9f /* No interrupts. Return. */
149 move a1, sp
150
151 xori s4, s0, 1 /* if s0 (_H) == 1, it's a low intr, so... */
152 movz s2, s3, s4 /* start the intr number at 64, and */
153 movz s0, s1, s4 /* look at the low status value. */
154
155 dclz s1, s0 /* Find the next interrupt. */
156 dsubu a0, zero, s1
157 daddiu a0, a0, 63
158 jal do_IRQ
159 daddu a0, a0, s2
160
1619: j ret_from_irq
162 nop
163
164 .set pop
165 END(bcm1480_irq_handler)
diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c
new file mode 100644
index 000000000000..d90a0b87874c
--- /dev/null
+++ b/arch/mips/sibyte/bcm1480/setup.c
@@ -0,0 +1,136 @@
1/*
2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#include <linux/config.h>
19#include <linux/kernel.h>
20#include <linux/reboot.h>
21#include <linux/string.h>
22
23#include <asm/bootinfo.h>
24#include <asm/mipsregs.h>
25#include <asm/io.h>
26#include <asm/sibyte/sb1250.h>
27
28#include <asm/sibyte/bcm1480_regs.h>
29#include <asm/sibyte/bcm1480_scd.h>
30#include <asm/sibyte/sb1250_scd.h>
31
32unsigned int sb1_pass;
33unsigned int soc_pass;
34unsigned int soc_type;
35unsigned int periph_rev;
36unsigned int zbbus_mhz;
37
38static unsigned int part_type;
39
40static char *soc_str;
41static char *pass_str;
42
43static inline int setup_bcm1x80_bcm1x55(void);
44
45/* Setup code likely to be common to all SiByte platforms */
46
47static inline int sys_rev_decode(void)
48{
49 int ret = 0;
50
51 switch (soc_type) {
52 case K_SYS_SOC_TYPE_BCM1x80:
53 if (part_type == K_SYS_PART_BCM1480)
54 soc_str = "BCM1480";
55 else if (part_type == K_SYS_PART_BCM1280)
56 soc_str = "BCM1280";
57 else
58 soc_str = "BCM1x80";
59 ret = setup_bcm1x80_bcm1x55();
60 break;
61
62 case K_SYS_SOC_TYPE_BCM1x55:
63 if (part_type == K_SYS_PART_BCM1455)
64 soc_str = "BCM1455";
65 else if (part_type == K_SYS_PART_BCM1255)
66 soc_str = "BCM1255";
67 else
68 soc_str = "BCM1x55";
69 ret = setup_bcm1x80_bcm1x55();
70 break;
71
72 default:
73 prom_printf("Unknown part type %x\n", part_type);
74 ret = 1;
75 break;
76 }
77 return ret;
78}
79
80static inline int setup_bcm1x80_bcm1x55(void)
81{
82 int ret = 0;
83
84 switch (soc_pass) {
85 case K_SYS_REVISION_BCM1480_S0:
86 periph_rev = 1;
87 pass_str = "S0 (pass1)";
88 break;
89 case K_SYS_REVISION_BCM1480_A1:
90 periph_rev = 1;
91 pass_str = "A1 (pass1)";
92 break;
93 case K_SYS_REVISION_BCM1480_A2:
94 periph_rev = 1;
95 pass_str = "A2 (pass1)";
96 break;
97 case K_SYS_REVISION_BCM1480_A3:
98 periph_rev = 1;
99 pass_str = "A3 (pass1)";
100 break;
101 case K_SYS_REVISION_BCM1480_B0:
102 periph_rev = 1;
103 pass_str = "B0 (pass2)";
104 break;
105 default:
106 prom_printf("Unknown %s rev %x\n", soc_str, soc_pass);
107 periph_rev = 1;
108 pass_str = "Unknown Revision";
109 break;
110 }
111 return ret;
112}
113
114void bcm1480_setup(void)
115{
116 uint64_t sys_rev;
117 int plldiv;
118
119 sb1_pass = read_c0_prid() & 0xff;
120 sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
121 soc_type = SYS_SOC_TYPE(sys_rev);
122 part_type = G_SYS_PART(sys_rev);
123 soc_pass = G_SYS_REVISION(sys_rev);
124
125 if (sys_rev_decode()) {
126 prom_printf("Restart after failure to identify SiByte chip\n");
127 machine_restart(NULL);
128 }
129
130 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
131 zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
132
133 prom_printf("Broadcom SiByte %s %s @ %d MHz (SB-1A rev %d)\n",
134 soc_str, pass_str, zbbus_mhz * 2, sb1_pass);
135 prom_printf("Board type: %s\n", get_system_type());
136}
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
new file mode 100644
index 000000000000..584a4b33faac
--- /dev/null
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -0,0 +1,110 @@
1/*
2 * Copyright (C) 2001,2002,2004 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/smp.h>
22#include <linux/kernel_stat.h>
23
24#include <asm/mmu_context.h>
25#include <asm/io.h>
26#include <asm/sibyte/sb1250.h>
27#include <asm/sibyte/bcm1480_regs.h>
28#include <asm/sibyte/bcm1480_int.h>
29
30extern void smp_call_function_interrupt(void);
31
32/*
33 * These are routines for dealing with the bcm1480 smp capabilities
34 * independent of board/firmware
35 */
36
37static void *mailbox_0_set_regs[] = {
38 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
39 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
40 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
41 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
42};
43
44static void *mailbox_0_clear_regs[] = {
45 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
46 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
47 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
48 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
49};
50
51static void *mailbox_0_regs[] = {
52 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
53 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
54 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
55 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
56};
57
58/*
59 * SMP init and finish on secondary CPUs
60 */
61void bcm1480_smp_init(void)
62{
63 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
64 STATUSF_IP1 | STATUSF_IP0;
65
66 /* Set interrupt mask, but don't enable */
67 change_c0_status(ST0_IM, imask);
68}
69
70void bcm1480_smp_finish(void)
71{
72 extern void bcm1480_time_init(void);
73 bcm1480_time_init();
74 local_irq_enable();
75}
76
77/*
78 * These are routines for dealing with the sb1250 smp capabilities
79 * independent of board/firmware
80 */
81
82/*
83 * Simple enough; everything is set up, so just poke the appropriate mailbox
84 * register, and we should be set
85 */
86void core_send_ipi(int cpu, unsigned int action)
87{
88 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]);
89}
90
91void bcm1480_mailbox_interrupt(struct pt_regs *regs)
92{
93 int cpu = smp_processor_id();
94 unsigned int action;
95
96 kstat_this_cpu.irqs[K_BCM1480_INT_MBOX_0_0]++;
97 /* Load the mailbox register to figure out what we're supposed to do */
98 action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff;
99
100 /* Clear the mailbox to clear the interrupt */
101 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]);
102
103 /*
104 * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the
105 * interrupt will do the reschedule for us
106 */
107
108 if (action & SMP_CALL_FUNCTION)
109 smp_call_function_interrupt();
110}
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
new file mode 100644
index 000000000000..e545752695a1
--- /dev/null
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -0,0 +1,138 @@
1/*
2 * Copyright (C) 2000,2001,2004 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/*
20 * These are routines to set up and handle interrupts from the
21 * bcm1480 general purpose timer 0. We're using the timer as a
22 * system clock, so we set it up to run at 100 Hz. On every
23 * interrupt, we update our idea of what the time of day is,
24 * then call do_timer() in the architecture-independent kernel
25 * code to do general bookkeeping (e.g. update jiffies, run
26 * bottom halves, etc.)
27 */
28#include <linux/config.h>
29#include <linux/interrupt.h>
30#include <linux/sched.h>
31#include <linux/spinlock.h>
32#include <linux/kernel_stat.h>
33
34#include <asm/irq.h>
35#include <asm/ptrace.h>
36#include <asm/addrspace.h>
37#include <asm/time.h>
38#include <asm/io.h>
39
40#include <asm/sibyte/bcm1480_regs.h>
41#include <asm/sibyte/sb1250_regs.h>
42#include <asm/sibyte/bcm1480_int.h>
43#include <asm/sibyte/bcm1480_scd.h>
44
45#include <asm/sibyte/sb1250.h>
46
47
48#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
49#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
50#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
51
52extern int bcm1480_steal_irq(int irq);
53
54void bcm1480_time_init(void)
55{
56 int cpu = smp_processor_id();
57 int irq = K_BCM1480_INT_TIMER_0+cpu;
58
59 /* Only have 4 general purpose timers */
60 if (cpu > 3) {
61 BUG();
62 }
63
64 if (!cpu) {
65 /* Use our own gettimeoffset() routine */
66 do_gettimeoffset = bcm1480_gettimeoffset;
67 }
68
69 bcm1480_mask_irq(cpu, irq);
70
71 /* Map the timer interrupt to ip[4] of this cpu */
72 __raw_writeq(IMR_IP4_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H)
73 + (irq<<3)));
74
75 /* the general purpose timer ticks at 1 Mhz independent of the rest of the system */
76 /* Disable the timer and set up the count */
77 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
78 __raw_writeq(
79#ifndef CONFIG_SIMULATION
80 1000000/HZ
81#else
82 50000/HZ
83#endif
84 , IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
85
86 /* Set the timer running */
87 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
88 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
89
90 bcm1480_unmask_irq(cpu, irq);
91 bcm1480_steal_irq(irq);
92 /*
93 * This interrupt is "special" in that it doesn't use the request_irq
94 * way to hook the irq line. The timer interrupt is initialized early
95 * enough to make this a major pain, and it's also firing enough to
96 * warrant a bit of special case code. bcm1480_timer_interrupt is
97 * called directly from irq_handler.S when IP[4] is set during an
98 * interrupt
99 */
100}
101
102#include <asm/sibyte/sb1250.h>
103
104void bcm1480_timer_interrupt(struct pt_regs *regs)
105{
106 int cpu = smp_processor_id();
107 int irq = K_BCM1480_INT_TIMER_0+cpu;
108
109 /* Reset the timer */
110 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
111 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
112
113 /*
114 * CPU 0 handles the global timer interrupt job
115 */
116 if (cpu == 0) {
117 ll_timer_interrupt(irq, regs);
118 }
119
120 /*
121 * every CPU should do profiling and process accouting
122 */
123 ll_local_timer_interrupt(irq, regs);
124}
125
126/*
127 * We use our own do_gettimeoffset() instead of the generic one,
128 * because the generic one does not work for SMP case.
129 * In addition, since we use general timer 0 for system time,
130 * we can get accurate intra-jiffy offset without calibration.
131 */
132unsigned long bcm1480_gettimeoffset(void)
133{
134 unsigned long count =
135 __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
136
137 return 1000000/HZ - count;
138}
diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c
index e44ce1a9eea9..e8485124b8fc 100644
--- a/arch/mips/sibyte/cfe/smp.c
+++ b/arch/mips/sibyte/cfe/smp.c
@@ -70,8 +70,15 @@ void prom_boot_secondary(int cpu, struct task_struct *idle)
70 */ 70 */
71void prom_init_secondary(void) 71void prom_init_secondary(void)
72{ 72{
73#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
74 extern void bcm1480_smp_init(void);
75 bcm1480_smp_init();
76#elif defined(CONFIG_SIBYTE_SB1250)
73 extern void sb1250_smp_init(void); 77 extern void sb1250_smp_init(void);
74 sb1250_smp_init(); 78 sb1250_smp_init();
79#else
80#error invalid SMP configuration
81#endif
75} 82}
76 83
77/* 84/*
@@ -80,8 +87,15 @@ void prom_init_secondary(void)
80 */ 87 */
81void prom_smp_finish(void) 88void prom_smp_finish(void)
82{ 89{
90#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
91 extern void bcm1480_smp_finish(void);
92 bcm1480_smp_finish();
93#elif defined(CONFIG_SIBYTE_SB1250)
83 extern void sb1250_smp_finish(void); 94 extern void sb1250_smp_finish(void);
84 sb1250_smp_finish(); 95 sb1250_smp_finish();
96#else
97#error invalid SMP configuration
98#endif
85} 99}
86 100
87/* 101/*
diff --git a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
index 7f813ae9eaff..992e0d8dbb67 100644
--- a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
+++ b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
@@ -28,6 +28,8 @@
28#include <linux/fs.h> 28#include <linux/fs.h>
29#include <linux/errno.h> 29#include <linux/errno.h>
30#include <linux/reboot.h> 30#include <linux/reboot.h>
31#include <linux/smp_lock.h>
32#include <linux/wait.h>
31#include <asm/uaccess.h> 33#include <asm/uaccess.h>
32#include <asm/io.h> 34#include <asm/io.h>
33#include <asm/sibyte/sb1250.h> 35#include <asm/sibyte/sb1250.h>
@@ -64,24 +66,25 @@ static void arm_tb(void)
64 u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL; 66 u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
65 /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to 67 /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
66 trigger start of trace. XXX vary sampling period */ 68 trigger start of trace. XXX vary sampling period */
67 bus_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); 69 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
68 scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG)); 70 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
69 /* Unfortunately, in Pass 2 we must clear all counters to knock down 71 /* Unfortunately, in Pass 2 we must clear all counters to knock down
70 a previous interrupt request. This means that bus profiling 72 a previous interrupt request. This means that bus profiling
71 requires ALL of the SCD perf counters. */ 73 requires ALL of the SCD perf counters. */
72 bus_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is 74 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
73 M_SPC_CFG_ENABLE | // enable counting 75 // keep counters 0,2,3 as is
74 M_SPC_CFG_CLEAR | // clear all counters 76 M_SPC_CFG_ENABLE | // enable counting
75 V_SPC_CFG_SRC1(1), // counter 1 counts cycles 77 M_SPC_CFG_CLEAR | // clear all counters
76 IOADDR(A_SCD_PERF_CNT_CFG)); 78 V_SPC_CFG_SRC1(1), // counter 1 counts cycles
77 bus_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); 79 IOADDR(A_SCD_PERF_CNT_CFG));
80 __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
78 /* Reset the trace buffer */ 81 /* Reset the trace buffer */
79 bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); 82 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
80#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT) 83#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
81 /* XXXKW may want to expose control to the data-collector */ 84 /* XXXKW may want to expose control to the data-collector */
82 tb_options |= M_SCD_TRACE_CFG_FORCECNT; 85 tb_options |= M_SCD_TRACE_CFG_FORCECNT;
83#endif 86#endif
84 bus_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); 87 __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
85 sbp.tb_armed = 1; 88 sbp.tb_armed = 1;
86} 89}
87 90
@@ -93,23 +96,30 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs)
93 /* XXX should use XKPHYS to make writes bypass L2 */ 96 /* XXX should use XKPHYS to make writes bypass L2 */
94 u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++]; 97 u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
95 /* Read out trace */ 98 /* Read out trace */
96 bus_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG)); 99 __raw_writeq(M_SCD_TRACE_CFG_START_READ,
100 IOADDR(A_SCD_TRACE_CFG));
97 __asm__ __volatile__ ("sync" : : : "memory"); 101 __asm__ __volatile__ ("sync" : : : "memory");
98 /* Loop runs backwards because bundles are read out in reverse order */ 102 /* Loop runs backwards because bundles are read out in reverse order */
99 for (i = 256 * 6; i > 0; i -= 6) { 103 for (i = 256 * 6; i > 0; i -= 6) {
100 // Subscripts decrease to put bundle in the order 104 // Subscripts decrease to put bundle in the order
101 // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi 105 // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
102 p[i-1] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi 106 p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
103 p[i-2] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo 107 // read t2 hi
104 p[i-3] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi 108 p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
105 p[i-4] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo 109 // read t2 lo
106 p[i-5] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi 110 p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
107 p[i-6] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo 111 // read t1 hi
112 p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
113 // read t1 lo
114 p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
115 // read t0 hi
116 p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
117 // read t0 lo
108 } 118 }
109 if (!sbp.tb_enable) { 119 if (!sbp.tb_enable) {
110 DBG(printk(DEVNAME ": tb_intr shutdown\n")); 120 DBG(printk(DEVNAME ": tb_intr shutdown\n"));
111 bus_writeq(M_SCD_TRACE_CFG_RESET, 121 __raw_writeq(M_SCD_TRACE_CFG_RESET,
112 IOADDR(A_SCD_TRACE_CFG)); 122 IOADDR(A_SCD_TRACE_CFG));
113 sbp.tb_armed = 0; 123 sbp.tb_armed = 0;
114 wake_up(&sbp.tb_sync); 124 wake_up(&sbp.tb_sync);
115 } else { 125 } else {
@@ -118,7 +128,7 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs)
118 } else { 128 } else {
119 /* No more trace buffer samples */ 129 /* No more trace buffer samples */
120 DBG(printk(DEVNAME ": tb_intr full\n")); 130 DBG(printk(DEVNAME ": tb_intr full\n"));
121 bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); 131 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
122 sbp.tb_armed = 0; 132 sbp.tb_armed = 0;
123 if (!sbp.tb_enable) { 133 if (!sbp.tb_enable) {
124 wake_up(&sbp.tb_sync); 134 wake_up(&sbp.tb_sync);
@@ -152,13 +162,11 @@ int sbprof_zbprof_start(struct file *filp)
152 return -EBUSY; 162 return -EBUSY;
153 } 163 }
154 /* Make sure there isn't a perf-cnt interrupt waiting */ 164 /* Make sure there isn't a perf-cnt interrupt waiting */
155 scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG)); 165 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
156 /* Disable and clear counters, override SRC_1 */ 166 /* Disable and clear counters, override SRC_1 */
157 bus_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | 167 __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
158 M_SPC_CFG_ENABLE | 168 M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
159 M_SPC_CFG_CLEAR | 169 IOADDR(A_SCD_PERF_CNT_CFG));
160 V_SPC_CFG_SRC1(1),
161 IOADDR(A_SCD_PERF_CNT_CFG));
162 170
163 /* We grab this interrupt to prevent others from trying to use 171 /* We grab this interrupt to prevent others from trying to use
164 it, even though we don't want to service the interrupts 172 it, even though we don't want to service the interrupts
@@ -172,55 +180,55 @@ int sbprof_zbprof_start(struct file *filp)
172 /* I need the core to mask these, but the interrupt mapper to 180 /* I need the core to mask these, but the interrupt mapper to
173 pass them through. I am exploiting my knowledge that 181 pass them through. I am exploiting my knowledge that
174 cp0_status masks out IP[5]. krw */ 182 cp0_status masks out IP[5]. krw */
175 bus_writeq(K_INT_MAP_I3, 183 __raw_writeq(K_INT_MAP_I3,
176 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 184 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
177 (K_INT_PERF_CNT << 3))); 185 (K_INT_PERF_CNT << 3)));
178 186
179 /* Initialize address traps */ 187 /* Initialize address traps */
180 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); 188 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
181 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); 189 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
182 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); 190 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
183 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); 191 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
184 192
185 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); 193 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
186 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); 194 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
187 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); 195 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
188 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); 196 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
189 197
190 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); 198 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
191 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); 199 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
192 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); 200 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
193 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); 201 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
194 202
195 /* Initialize Trace Event 0-7 */ 203 /* Initialize Trace Event 0-7 */
196 // when interrupt 204 // when interrupt
197 bus_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); 205 __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
198 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); 206 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
199 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); 207 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
200 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); 208 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
201 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); 209 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
202 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); 210 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
203 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); 211 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
204 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); 212 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
205 213
206 /* Initialize Trace Sequence 0-7 */ 214 /* Initialize Trace Sequence 0-7 */
207 // Start on event 0 (interrupt) 215 // Start on event 0 (interrupt)
208 bus_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, 216 __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
209 IOADDR(A_SCD_TRACE_SEQUENCE_0)); 217 IOADDR(A_SCD_TRACE_SEQUENCE_0));
210 // dsamp when d used | asamp when a used 218 // dsamp when d used | asamp when a used
211 bus_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | 219 __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
212 K_SCD_TRSEQ_TRIGGER_ALL, 220 K_SCD_TRSEQ_TRIGGER_ALL,
213 IOADDR(A_SCD_TRACE_SEQUENCE_1)); 221 IOADDR(A_SCD_TRACE_SEQUENCE_1));
214 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); 222 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
215 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); 223 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
216 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); 224 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
217 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); 225 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
218 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); 226 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
219 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); 227 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
220 228
221 /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ 229 /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
222 bus_writeq((1ULL << K_INT_PERF_CNT), 230 __raw_writeq(1ULL << K_INT_PERF_CNT,
223 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); 231 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
224 232
225 arm_tb(); 233 arm_tb();
226 234
@@ -231,6 +239,7 @@ int sbprof_zbprof_start(struct file *filp)
231 239
232int sbprof_zbprof_stop(void) 240int sbprof_zbprof_stop(void)
233{ 241{
242 DEFINE_WAIT(wait);
234 DBG(printk(DEVNAME ": stopping\n")); 243 DBG(printk(DEVNAME ": stopping\n"));
235 244
236 if (sbp.tb_enable) { 245 if (sbp.tb_enable) {
@@ -240,7 +249,9 @@ int sbprof_zbprof_stop(void)
240 this sleep happens. */ 249 this sleep happens. */
241 if (sbp.tb_armed) { 250 if (sbp.tb_armed) {
242 DBG(printk(DEVNAME ": wait for disarm\n")); 251 DBG(printk(DEVNAME ": wait for disarm\n"));
243 interruptible_sleep_on(&sbp.tb_sync); 252 prepare_to_wait(&sbp.tb_sync, &wait, TASK_INTERRUPTIBLE);
253 schedule();
254 finish_wait(&sbp.tb_sync, &wait);
244 DBG(printk(DEVNAME ": disarm complete\n")); 255 DBG(printk(DEVNAME ": disarm complete\n"));
245 } 256 }
246 free_irq(K_INT_TRACE_FREEZE, &sbp); 257 free_irq(K_INT_TRACE_FREEZE, &sbp);
@@ -333,13 +344,13 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
333 return count; 344 return count;
334} 345}
335 346
336static int sbprof_tb_ioctl(struct inode *inode, 347static long sbprof_tb_ioctl(struct file *filp,
337 struct file *filp, 348 unsigned int command,
338 unsigned int command, 349 unsigned long arg)
339 unsigned long arg)
340{ 350{
341 int error = 0; 351 int error = 0;
342 352
353 lock_kernel();
343 switch (command) { 354 switch (command) {
344 case SBPROF_ZBSTART: 355 case SBPROF_ZBSTART:
345 error = sbprof_zbprof_start(filp); 356 error = sbprof_zbprof_start(filp);
@@ -348,13 +359,17 @@ static int sbprof_tb_ioctl(struct inode *inode,
348 error = sbprof_zbprof_stop(); 359 error = sbprof_zbprof_stop();
349 break; 360 break;
350 case SBPROF_ZBWAITFULL: 361 case SBPROF_ZBWAITFULL:
351 interruptible_sleep_on(&sbp.tb_read); 362 DEFINE_WAIT(wait);
363 prepare_to_wait(&sbp.tb_read, &wait, TASK_INTERRUPTIBLE);
364 schedule();
365 finish_wait(&sbp.tb_read, &wait);
352 /* XXXKW check if interrupted? */ 366 /* XXXKW check if interrupted? */
353 return put_user(TB_FULL, (int *) arg); 367 return put_user(TB_FULL, (int *) arg);
354 default: 368 default:
355 error = -EINVAL; 369 error = -EINVAL;
356 break; 370 break;
357 } 371 }
372 unlock_kernel();
358 373
359 return error; 374 return error;
360} 375}
@@ -364,7 +379,8 @@ static struct file_operations sbprof_tb_fops = {
364 .open = sbprof_tb_open, 379 .open = sbprof_tb_open,
365 .release = sbprof_tb_release, 380 .release = sbprof_tb_release,
366 .read = sbprof_tb_read, 381 .read = sbprof_tb_read,
367 .ioctl = sbprof_tb_ioctl, 382 .unlocked_ioctl = sbprof_tb_ioctl,
383 .compat_ioctl = sbprof_tb_ioctl,
368 .mmap = NULL, 384 .mmap = NULL,
369}; 385};
370 386
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c
index 1a97e3127aeb..482dee054e68 100644
--- a/arch/mips/sibyte/sb1250/bus_watcher.c
+++ b/arch/mips/sibyte/sb1250/bus_watcher.c
@@ -189,7 +189,7 @@ static irqreturn_t sibyte_bw_int(int irq, void *data, struct pt_regs *regs)
189 189
190 for (i=0; i<256*6; i++) 190 for (i=0; i<256*6; i++)
191 printk("%016llx\n", 191 printk("%016llx\n",
192 (unsigned long long)bus_readq(IOADDR(A_SCD_TRACE_READ))); 192 (long long)__raw_readq(IOADDR(A_SCD_TRACE_READ)));
193 193
194 csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); 194 csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
195 csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); 195 csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG));
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 2725b263cced..589537bfcc3d 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -53,7 +53,7 @@ static void disable_sb1250_irq(unsigned int irq);
53static unsigned int startup_sb1250_irq(unsigned int irq); 53static unsigned int startup_sb1250_irq(unsigned int irq);
54static void ack_sb1250_irq(unsigned int irq); 54static void ack_sb1250_irq(unsigned int irq);
55#ifdef CONFIG_SMP 55#ifdef CONFIG_SMP
56static void sb1250_set_affinity(unsigned int irq, unsigned long mask); 56static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
57#endif 57#endif
58 58
59#ifdef CONFIG_SIBYTE_HAS_LDT 59#ifdef CONFIG_SIBYTE_HAS_LDT
@@ -71,17 +71,15 @@ extern char sb1250_duart_present[];
71#endif 71#endif
72 72
73static struct hw_interrupt_type sb1250_irq_type = { 73static struct hw_interrupt_type sb1250_irq_type = {
74 "SB1250-IMR", 74 .typename = "SB1250-IMR",
75 startup_sb1250_irq, 75 .startup = startup_sb1250_irq,
76 shutdown_sb1250_irq, 76 .shutdown = shutdown_sb1250_irq,
77 enable_sb1250_irq, 77 .enable = enable_sb1250_irq,
78 disable_sb1250_irq, 78 .disable = disable_sb1250_irq,
79 ack_sb1250_irq, 79 .ack = ack_sb1250_irq,
80 end_sb1250_irq, 80 .end = end_sb1250_irq,
81#ifdef CONFIG_SMP 81#ifdef CONFIG_SMP
82 sb1250_set_affinity 82 .set_affinity = sb1250_set_affinity
83#else
84 NULL
85#endif 83#endif
86}; 84};
87 85
@@ -96,11 +94,11 @@ void sb1250_mask_irq(int cpu, int irq)
96 u64 cur_ints; 94 u64 cur_ints;
97 95
98 spin_lock_irqsave(&sb1250_imr_lock, flags); 96 spin_lock_irqsave(&sb1250_imr_lock, flags);
99 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + 97 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
100 R_IMR_INTERRUPT_MASK)); 98 R_IMR_INTERRUPT_MASK));
101 cur_ints |= (((u64) 1) << irq); 99 cur_ints |= (((u64) 1) << irq);
102 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + 100 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
103 R_IMR_INTERRUPT_MASK)); 101 R_IMR_INTERRUPT_MASK));
104 spin_unlock_irqrestore(&sb1250_imr_lock, flags); 102 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
105} 103}
106 104
@@ -110,32 +108,25 @@ void sb1250_unmask_irq(int cpu, int irq)
110 u64 cur_ints; 108 u64 cur_ints;
111 109
112 spin_lock_irqsave(&sb1250_imr_lock, flags); 110 spin_lock_irqsave(&sb1250_imr_lock, flags);
113 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + 111 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
114 R_IMR_INTERRUPT_MASK)); 112 R_IMR_INTERRUPT_MASK));
115 cur_ints &= ~(((u64) 1) << irq); 113 cur_ints &= ~(((u64) 1) << irq);
116 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + 114 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
117 R_IMR_INTERRUPT_MASK)); 115 R_IMR_INTERRUPT_MASK));
118 spin_unlock_irqrestore(&sb1250_imr_lock, flags); 116 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
119} 117}
120 118
121#ifdef CONFIG_SMP 119#ifdef CONFIG_SMP
122static void sb1250_set_affinity(unsigned int irq, unsigned long mask) 120static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
123{ 121{
124 int i = 0, old_cpu, cpu, int_on; 122 int i = 0, old_cpu, cpu, int_on;
125 u64 cur_ints; 123 u64 cur_ints;
126 irq_desc_t *desc = irq_desc + irq; 124 irq_desc_t *desc = irq_desc + irq;
127 unsigned long flags; 125 unsigned long flags;
128 126
129 while (mask) { 127 i = first_cpu(mask);
130 if (mask & 1) {
131 mask >>= 1;
132 break;
133 }
134 mask >>= 1;
135 i++;
136 }
137 128
138 if (mask) { 129 if (cpus_weight(mask) > 1) {
139 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); 130 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
140 return; 131 return;
141 } 132 }
@@ -149,23 +140,23 @@ static void sb1250_set_affinity(unsigned int irq, unsigned long mask)
149 140
150 /* Swizzle each CPU's IMR (but leave the IP selection alone) */ 141 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
151 old_cpu = sb1250_irq_owner[irq]; 142 old_cpu = sb1250_irq_owner[irq];
152 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(old_cpu) + 143 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
153 R_IMR_INTERRUPT_MASK)); 144 R_IMR_INTERRUPT_MASK));
154 int_on = !(cur_ints & (((u64) 1) << irq)); 145 int_on = !(cur_ints & (((u64) 1) << irq));
155 if (int_on) { 146 if (int_on) {
156 /* If it was on, mask it */ 147 /* If it was on, mask it */
157 cur_ints |= (((u64) 1) << irq); 148 cur_ints |= (((u64) 1) << irq);
158 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + 149 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
159 R_IMR_INTERRUPT_MASK)); 150 R_IMR_INTERRUPT_MASK));
160 } 151 }
161 sb1250_irq_owner[irq] = cpu; 152 sb1250_irq_owner[irq] = cpu;
162 if (int_on) { 153 if (int_on) {
163 /* unmask for the new CPU */ 154 /* unmask for the new CPU */
164 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + 155 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
165 R_IMR_INTERRUPT_MASK)); 156 R_IMR_INTERRUPT_MASK));
166 cur_ints &= ~(((u64) 1) << irq); 157 cur_ints &= ~(((u64) 1) << irq);
167 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + 158 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
168 R_IMR_INTERRUPT_MASK)); 159 R_IMR_INTERRUPT_MASK));
169 } 160 }
170 spin_unlock(&sb1250_imr_lock); 161 spin_unlock(&sb1250_imr_lock);
171 spin_unlock_irqrestore(&desc->lock, flags); 162 spin_unlock_irqrestore(&desc->lock, flags);
@@ -208,8 +199,8 @@ static void ack_sb1250_irq(unsigned int irq)
208 * deliver the interrupts to all CPUs (which makes affinity 199 * deliver the interrupts to all CPUs (which makes affinity
209 * changing easier for us) 200 * changing easier for us)
210 */ 201 */
211 pending = bus_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], 202 pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
212 R_IMR_LDT_INTERRUPT))); 203 R_IMR_LDT_INTERRUPT)));
213 pending &= ((u64)1 << (irq)); 204 pending &= ((u64)1 << (irq));
214 if (pending) { 205 if (pending) {
215 int i; 206 int i;
@@ -224,8 +215,8 @@ static void ack_sb1250_irq(unsigned int irq)
224 * Clear for all CPUs so an affinity switch 215 * Clear for all CPUs so an affinity switch
225 * doesn't find an old status 216 * doesn't find an old status
226 */ 217 */
227 bus_writeq(pending, 218 __raw_writeq(pending,
228 IOADDR(A_IMR_REGISTER(cpu, 219 IOADDR(A_IMR_REGISTER(cpu,
229 R_IMR_LDT_INTERRUPT_CLR))); 220 R_IMR_LDT_INTERRUPT_CLR)));
230 } 221 }
231 222
@@ -340,12 +331,14 @@ void __init arch_init_irq(void)
340 331
341 /* Default everything to IP2 */ 332 /* Default everything to IP2 */
342 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ 333 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
343 bus_writeq(IMR_IP2_VAL, 334 __raw_writeq(IMR_IP2_VAL,
344 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 335 IOADDR(A_IMR_REGISTER(0,
345 (i << 3))); 336 R_IMR_INTERRUPT_MAP_BASE) +
346 bus_writeq(IMR_IP2_VAL, 337 (i << 3)));
347 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + 338 __raw_writeq(IMR_IP2_VAL,
348 (i << 3))); 339 IOADDR(A_IMR_REGISTER(1,
340 R_IMR_INTERRUPT_MAP_BASE) +
341 (i << 3)));
349 } 342 }
350 343
351 init_sb1250_irqs(); 344 init_sb1250_irqs();
@@ -355,23 +348,23 @@ void __init arch_init_irq(void)
355 * inter-cpu messages 348 * inter-cpu messages
356 */ 349 */
357 /* Was I1 */ 350 /* Was I1 */
358 bus_writeq(IMR_IP3_VAL, 351 __raw_writeq(IMR_IP3_VAL,
359 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 352 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
360 (K_INT_MBOX_0 << 3))); 353 (K_INT_MBOX_0 << 3)));
361 bus_writeq(IMR_IP3_VAL, 354 __raw_writeq(IMR_IP3_VAL,
362 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + 355 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
363 (K_INT_MBOX_0 << 3))); 356 (K_INT_MBOX_0 << 3)));
364 357
365 /* Clear the mailboxes. The firmware may leave them dirty */ 358 /* Clear the mailboxes. The firmware may leave them dirty */
366 bus_writeq(0xffffffffffffffffULL, 359 __raw_writeq(0xffffffffffffffffULL,
367 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); 360 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
368 bus_writeq(0xffffffffffffffffULL, 361 __raw_writeq(0xffffffffffffffffULL,
369 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); 362 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
370 363
371 /* Mask everything except the mailbox registers for both cpus */ 364 /* Mask everything except the mailbox registers for both cpus */
372 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); 365 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
373 bus_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); 366 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
374 bus_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); 367 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
375 368
376 sb1250_steal_irq(K_INT_MBOX_0); 369 sb1250_steal_irq(K_INT_MBOX_0);
377 370
@@ -396,12 +389,14 @@ void __init arch_init_irq(void)
396 sb1250_duart_present[kgdb_port] = 0; 389 sb1250_duart_present[kgdb_port] = 0;
397#endif 390#endif
398 /* Setup uart 1 settings, mapper */ 391 /* Setup uart 1 settings, mapper */
399 bus_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port))); 392 __raw_writeq(M_DUART_IMR_BRK,
393 IOADDR(A_DUART_IMRREG(kgdb_port)));
400 394
401 sb1250_steal_irq(kgdb_irq); 395 sb1250_steal_irq(kgdb_irq);
402 bus_writeq(IMR_IP6_VAL, 396 __raw_writeq(IMR_IP6_VAL,
403 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 397 IOADDR(A_IMR_REGISTER(0,
404 (kgdb_irq<<3))); 398 R_IMR_INTERRUPT_MAP_BASE) +
399 (kgdb_irq << 3)));
405 sb1250_unmask_irq(0, kgdb_irq); 400 sb1250_unmask_irq(0, kgdb_irq);
406 } 401 }
407#endif 402#endif
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index f8c605be96c7..df2e266c700c 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -153,7 +153,7 @@ void sb1250_setup(void)
153 int bad_config = 0; 153 int bad_config = 0;
154 154
155 sb1_pass = read_c0_prid() & 0xff; 155 sb1_pass = read_c0_prid() & 0xff;
156 sys_rev = bus_readq(IOADDR(A_SCD_SYSTEM_REVISION)); 156 sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
157 soc_type = SYS_SOC_TYPE(sys_rev); 157 soc_type = SYS_SOC_TYPE(sys_rev);
158 soc_pass = G_SYS_REVISION(sys_rev); 158 soc_pass = G_SYS_REVISION(sys_rev);
159 159
@@ -162,7 +162,7 @@ void sb1250_setup(void)
162 machine_restart(NULL); 162 machine_restart(NULL);
163 } 163 }
164 164
165 plldiv = G_SYS_PLL_DIV(bus_readq(IOADDR(A_SCD_SYSTEM_CFG))); 165 plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
166 zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); 166 zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
167 167
168 prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n", 168 prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n",
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
index be91b3990952..f859db02d3c9 100644
--- a/arch/mips/sibyte/sb1250/smp.c
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -29,18 +29,18 @@
29#include <asm/sibyte/sb1250_int.h> 29#include <asm/sibyte/sb1250_int.h>
30 30
31static void *mailbox_set_regs[] = { 31static void *mailbox_set_regs[] = {
32 (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), 32 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
33 (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU) 33 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
34}; 34};
35 35
36static void *mailbox_clear_regs[] = { 36static void *mailbox_clear_regs[] = {
37 (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), 37 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
38 (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU) 38 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
39}; 39};
40 40
41static void *mailbox_regs[] = { 41static void *mailbox_regs[] = {
42 (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), 42 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
43 (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU) 43 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
44}; 44};
45 45
46/* 46/*
@@ -73,7 +73,7 @@ void sb1250_smp_finish(void)
73 */ 73 */
74void core_send_ipi(int cpu, unsigned int action) 74void core_send_ipi(int cpu, unsigned int action)
75{ 75{
76 bus_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); 76 __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
77} 77}
78 78
79void sb1250_mailbox_interrupt(struct pt_regs *regs) 79void sb1250_mailbox_interrupt(struct pt_regs *regs)
@@ -83,10 +83,10 @@ void sb1250_mailbox_interrupt(struct pt_regs *regs)
83 83
84 kstat_this_cpu.irqs[K_INT_MBOX_0]++; 84 kstat_this_cpu.irqs[K_INT_MBOX_0]++;
85 /* Load the mailbox register to figure out what we're supposed to do */ 85 /* Load the mailbox register to figure out what we're supposed to do */
86 action = (__bus_readq(mailbox_regs[cpu]) >> 48) & 0xffff; 86 action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff;
87 87
88 /* Clear the mailbox to clear the interrupt */ 88 /* Clear the mailbox to clear the interrupt */
89 __bus_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); 89 ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
90 90
91 /* 91 /*
92 * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the 92 * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 8b4c848c907b..511c89d65f38 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -67,24 +67,24 @@ void sb1250_time_init(void)
67 sb1250_mask_irq(cpu, irq); 67 sb1250_mask_irq(cpu, irq);
68 68
69 /* Map the timer interrupt to ip[4] of this cpu */ 69 /* Map the timer interrupt to ip[4] of this cpu */
70 bus_writeq(IMR_IP4_VAL, 70 __raw_writeq(IMR_IP4_VAL,
71 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + 71 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
72 (irq << 3))); 72 (irq << 3)));
73 73
74 /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ 74 /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
75 /* Disable the timer and set up the count */ 75 /* Disable the timer and set up the count */
76 bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 76 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
77#ifdef CONFIG_SIMULATION 77#ifdef CONFIG_SIMULATION
78 bus_writeq(50000 / HZ, 78 __raw_writeq(50000 / HZ,
79 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); 79 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
80#else 80#else
81 bus_writeq(1000000/HZ, 81 __raw_writeq(1000000 / HZ,
82 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); 82 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
83#endif 83#endif
84 84
85 /* Set the timer running */ 85 /* Set the timer running */
86 bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 86 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
87 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 87 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
88 88
89 sb1250_unmask_irq(cpu, irq); 89 sb1250_unmask_irq(cpu, irq);
90 sb1250_steal_irq(irq); 90 sb1250_steal_irq(irq);
@@ -100,25 +100,25 @@ void sb1250_time_init(void)
100 100
101void sb1250_timer_interrupt(struct pt_regs *regs) 101void sb1250_timer_interrupt(struct pt_regs *regs)
102{ 102{
103 extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs);
104 int cpu = smp_processor_id(); 103 int cpu = smp_processor_id();
105 int irq = K_INT_TIMER_0 + cpu; 104 int irq = K_INT_TIMER_0 + cpu;
106 105
107 /* Reset the timer */ 106 /* Reset the timer */
108 __bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 107 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
109 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 108 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
110 109
111 /*
112 * CPU 0 handles the global timer interrupt job
113 */
114 if (cpu == 0) { 110 if (cpu == 0) {
111 /*
112 * CPU 0 handles the global timer interrupt job
113 */
115 ll_timer_interrupt(irq, regs); 114 ll_timer_interrupt(irq, regs);
116 } 115 }
117 116 else {
118 /* 117 /*
119 * every CPU should do profiling and process accouting 118 * other CPUs should just do profiling and process accounting
120 */ 119 */
121 ll_local_timer_interrupt(irq, regs); 120 ll_local_timer_interrupt(irq, regs);
121 }
122} 122}
123 123
124/* 124/*
@@ -130,7 +130,7 @@ void sb1250_timer_interrupt(struct pt_regs *regs)
130unsigned long sb1250_gettimeoffset(void) 130unsigned long sb1250_gettimeoffset(void)
131{ 131{
132 unsigned long count = 132 unsigned long count =
133 bus_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); 133 __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
134 134
135 return 1000000/HZ - count; 135 return 1000000/HZ - count;
136 } 136 }
diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c
index a686bb716ec6..5b4fc26c1b36 100644
--- a/arch/mips/sibyte/swarm/rtc_m41t81.c
+++ b/arch/mips/sibyte/swarm/rtc_m41t81.c
@@ -82,59 +82,60 @@
82#define M41T81REG_SQW 0x13 /* square wave register */ 82#define M41T81REG_SQW 0x13 /* square wave register */
83 83
84#define M41T81_CCR_ADDRESS 0x68 84#define M41T81_CCR_ADDRESS 0x68
85#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) 85
86#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
86 87
87static int m41t81_read(uint8_t addr) 88static int m41t81_read(uint8_t addr)
88{ 89{
89 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 90 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
90 ; 91 ;
91 92
92 bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); 93 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
93 bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE), 94 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE,
94 SMB_CSR(R_SMB_START)); 95 SMB_CSR(R_SMB_START));
95 96
96 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 97 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
97 ; 98 ;
98 99
99 bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), 100 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
100 SMB_CSR(R_SMB_START)); 101 SMB_CSR(R_SMB_START));
101 102
102 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 103 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
103 ; 104 ;
104 105
105 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 106 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
106 /* Clear error bit by writing a 1 */ 107 /* Clear error bit by writing a 1 */
107 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 108 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
108 return -1; 109 return -1;
109 } 110 }
110 111
111 return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); 112 return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
112} 113}
113 114
114static int m41t81_write(uint8_t addr, int b) 115static int m41t81_write(uint8_t addr, int b)
115{ 116{
116 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 117 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
117 ; 118 ;
118 119
119 bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD)); 120 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
120 bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA)); 121 __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA));
121 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, 122 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
122 SMB_CSR(R_SMB_START)); 123 SMB_CSR(R_SMB_START));
123 124
124 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 125 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
125 ; 126 ;
126 127
127 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 128 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
128 /* Clear error bit by writing a 1 */ 129 /* Clear error bit by writing a 1 */
129 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 130 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
130 return -1; 131 return -1;
131 } 132 }
132 133
133 /* read the same byte again to make sure it is written */ 134 /* read the same byte again to make sure it is written */
134 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, 135 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
135 SMB_CSR(R_SMB_START)); 136 SMB_CSR(R_SMB_START));
136 137
137 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 138 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
138 ; 139 ;
139 140
140 return 0; 141 return 0;
diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c
index 981d21f16e64..d9ff9323f24e 100644
--- a/arch/mips/sibyte/swarm/rtc_xicor1241.c
+++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c
@@ -57,52 +57,52 @@
57 57
58#define X1241_CCR_ADDRESS 0x6F 58#define X1241_CCR_ADDRESS 0x6F
59 59
60#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) 60#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
61 61
62static int xicor_read(uint8_t addr) 62static int xicor_read(uint8_t addr)
63{ 63{
64 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 64 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
65 ; 65 ;
66 66
67 bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); 67 __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
68 bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); 68 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
69 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), 69 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
70 SMB_CSR(R_SMB_START)); 70 SMB_CSR(R_SMB_START));
71 71
72 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 72 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
73 ; 73 ;
74 74
75 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), 75 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
76 SMB_CSR(R_SMB_START)); 76 SMB_CSR(R_SMB_START));
77 77
78 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 78 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
79 ; 79 ;
80 80
81 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 81 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
82 /* Clear error bit by writing a 1 */ 82 /* Clear error bit by writing a 1 */
83 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 83 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
84 return -1; 84 return -1;
85 } 85 }
86 86
87 return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); 87 return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
88} 88}
89 89
90static int xicor_write(uint8_t addr, int b) 90static int xicor_write(uint8_t addr, int b)
91{ 91{
92 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 92 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
93 ; 93 ;
94 94
95 bus_writeq(addr, SMB_CSR(R_SMB_CMD)); 95 __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
96 bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); 96 __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
97 bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, 97 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
98 SMB_CSR(R_SMB_START)); 98 SMB_CSR(R_SMB_START));
99 99
100 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 100 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
101 ; 101 ;
102 102
103 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 103 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
104 /* Clear error bit by writing a 1 */ 104 /* Clear error bit by writing a 1 */
105 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 105 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
106 return -1; 106 return -1;
107 } else { 107 } else {
108 return 0; 108 return 0;
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index 4daeaa413def..b614ca0ddb69 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation 2 * Copyright (C) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation
3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
@@ -39,11 +39,23 @@
39#include <asm/time.h> 39#include <asm/time.h>
40#include <asm/traps.h> 40#include <asm/traps.h>
41#include <asm/sibyte/sb1250.h> 41#include <asm/sibyte/sb1250.h>
42#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
43#include <asm/sibyte/bcm1480_regs.h>
44#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
42#include <asm/sibyte/sb1250_regs.h> 45#include <asm/sibyte/sb1250_regs.h>
46#else
47#error invalid SiByte board configuation
48#endif
43#include <asm/sibyte/sb1250_genbus.h> 49#include <asm/sibyte/sb1250_genbus.h>
44#include <asm/sibyte/board.h> 50#include <asm/sibyte/board.h>
45 51
52#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
53extern void bcm1480_setup(void);
54#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
46extern void sb1250_setup(void); 55extern void sb1250_setup(void);
56#else
57#error invalid SiByte board configuation
58#endif
47 59
48extern int xicor_probe(void); 60extern int xicor_probe(void);
49extern int xicor_set_time(unsigned long); 61extern int xicor_set_time(unsigned long);
@@ -66,27 +78,34 @@ void __init swarm_timer_setup(struct irqaction *irq)
66 */ 78 */
67 79
68 /* We only need to setup the generic timer */ 80 /* We only need to setup the generic timer */
69 sb1250_time_init(); 81#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
82 bcm1480_time_init();
83#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
84 sb1250_time_init();
85#else
86#error invalid SiByte board configuation
87#endif
70} 88}
71 89
72int swarm_be_handler(struct pt_regs *regs, int is_fixup) 90int swarm_be_handler(struct pt_regs *regs, int is_fixup)
73{ 91{
74 if (!is_fixup && (regs->cp0_cause & 4)) { 92 if (!is_fixup && (regs->cp0_cause & 4)) {
75 /* Data bus error - print PA */ 93 /* Data bus error - print PA */
76#ifdef CONFIG_64BIT 94 printk("DBE physical address: %010Lx\n",
77 printk("DBE physical address: %010lx\n",
78 __read_64bit_c0_register($26, 1)); 95 __read_64bit_c0_register($26, 1));
79#else
80 printk("DBE physical address: %010llx\n",
81 __read_64bit_c0_split($26, 1));
82#endif
83 } 96 }
84 return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); 97 return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
85} 98}
86 99
87static int __init swarm_setup(void) 100void __init plat_setup(void)
88{ 101{
102#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
103 bcm1480_setup();
104#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
89 sb1250_setup(); 105 sb1250_setup();
106#else
107#error invalid SiByte board configuation
108#endif
90 109
91 panic_timeout = 5; /* For debug. */ 110 panic_timeout = 5; /* For debug. */
92 111
@@ -133,12 +152,8 @@ static int __init swarm_setup(void)
133 }; 152 };
134 /* XXXKW for CFE, get lines/cols from environment */ 153 /* XXXKW for CFE, get lines/cols from environment */
135#endif 154#endif
136
137 return 0;
138} 155}
139 156
140early_initcall(swarm_setup);
141
142#ifdef LEDS_PHYS 157#ifdef LEDS_PHYS
143 158
144#ifdef CONFIG_SIBYTE_CARMEL 159#ifdef CONFIG_SIBYTE_CARMEL
diff --git a/arch/mips/sibyte/swarm/time.c b/arch/mips/sibyte/swarm/time.c
index c1f1a9defeeb..97c73c793c35 100644
--- a/arch/mips/sibyte/swarm/time.c
+++ b/arch/mips/sibyte/swarm/time.c
@@ -79,48 +79,48 @@ static unsigned int usec_bias = 0;
79 79
80static int xicor_read(uint8_t addr) 80static int xicor_read(uint8_t addr)
81{ 81{
82 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 82 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
83 ; 83 ;
84 84
85 bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); 85 __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
86 bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); 86 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
87 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), 87 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
88 SMB_CSR(R_SMB_START)); 88 SMB_CSR(R_SMB_START));
89 89
90 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 90 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
91 ; 91 ;
92 92
93 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), 93 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
94 SMB_CSR(R_SMB_START)); 94 SMB_CSR(R_SMB_START));
95 95
96 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 96 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
97 ; 97 ;
98 98
99 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 99 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
100 /* Clear error bit by writing a 1 */ 100 /* Clear error bit by writing a 1 */
101 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 101 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
102 return -1; 102 return -1;
103 } 103 }
104 104
105 return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); 105 return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
106} 106}
107 107
108static int xicor_write(uint8_t addr, int b) 108static int xicor_write(uint8_t addr, int b)
109{ 109{
110 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 110 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
111 ; 111 ;
112 112
113 bus_writeq(addr, SMB_CSR(R_SMB_CMD)); 113 __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
114 bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); 114 __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
115 bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, 115 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
116 SMB_CSR(R_SMB_START)); 116 SMB_CSR(R_SMB_START));
117 117
118 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 118 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
119 ; 119 ;
120 120
121 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 121 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
122 /* Clear error bit by writing a 1 */ 122 /* Clear error bit by writing a 1 */
123 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 123 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
124 return -1; 124 return -1;
125 } else { 125 } else {
126 return 0; 126 return 0;
@@ -228,8 +228,8 @@ void __init swarm_time_init(void)
228 /* Establish communication with the Xicor 1241 RTC */ 228 /* Establish communication with the Xicor 1241 RTC */
229 /* XXXKW how do I share the SMBus with the I2C subsystem? */ 229 /* XXXKW how do I share the SMBus with the I2C subsystem? */
230 230
231 bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); 231 __raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ));
232 bus_writeq(0, SMB_CSR(R_SMB_CONTROL)); 232 __raw_writeq(0, SMB_CSR(R_SMB_CONTROL));
233 233
234 if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { 234 if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) {
235 printk("x1241: couldn't detect on SWARM SMBus 1\n"); 235 printk("x1241: couldn't detect on SWARM SMBus 1\n");
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 141a310d74d8..952038aa4b90 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -58,14 +58,13 @@ static void end_pciasic_irq(unsigned int irq)
58} 58}
59 59
60static struct hw_interrupt_type pciasic_irq_type = { 60static struct hw_interrupt_type pciasic_irq_type = {
61 "ASIC-PCI", 61 .typename = "ASIC-PCI",
62 startup_pciasic_irq, 62 .startup = startup_pciasic_irq,
63 shutdown_pciasic_irq, 63 .shutdown = shutdown_pciasic_irq,
64 enable_pciasic_irq, 64 .enable = enable_pciasic_irq,
65 disable_pciasic_irq, 65 .disable = disable_pciasic_irq,
66 mask_and_ack_pciasic_irq, 66 .ack = mask_and_ack_pciasic_irq,
67 end_pciasic_irq, 67 .end = end_pciasic_irq,
68 NULL
69}; 68};
70 69
71/* 70/*
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index 1b3f8a0903e1..262c85680709 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -167,7 +167,7 @@ static inline void sni_pcimt_time_init(void)
167 rtc_set_time = mc146818_set_rtc_mmss; 167 rtc_set_time = mc146818_set_rtc_mmss;
168} 168}
169 169
170static int __init sni_rm200_pci_setup(void) 170void __init plat_setup(void)
171{ 171{
172 sni_pcimt_detect(); 172 sni_pcimt_detect();
173 sni_pcimt_sc_init(); 173 sni_pcimt_sc_init();
@@ -196,8 +196,4 @@ static int __init sni_rm200_pci_setup(void)
196#ifdef CONFIG_PCI 196#ifdef CONFIG_PCI
197 register_pci_controller(&sni_controller); 197 register_pci_controller(&sni_controller);
198#endif 198#endif
199
200 return 0;
201} 199}
202
203early_initcall(sni_rm200_pci_setup);
diff --git a/arch/mips/tx4927/Kconfig b/arch/mips/tx4927/Kconfig
new file mode 100644
index 000000000000..5fbbe12e0fc1
--- /dev/null
+++ b/arch/mips/tx4927/Kconfig
@@ -0,0 +1,3 @@
1config TOSHIBA_FPCIB0
2 bool "FPCIB0 Backplane Support"
3 depends on TOSHIBA_RBTX4927
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
index 26d7c53612a8..77c3b66fb959 100644
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -64,7 +64,7 @@ static void tx4927_write_buffer_flush(void)
64} 64}
65 65
66 66
67static void __init tx4927_setup(void) 67void __init plat_setup(void)
68{ 68{
69 board_time_init = tx4927_time_init; 69 board_time_init = tx4927_time_init;
70 board_timer_setup = tx4927_timer_setup; 70 board_timer_setup = tx4927_timer_setup;
@@ -76,12 +76,8 @@ static void __init tx4927_setup(void)
76 toshiba_rbtx4927_setup(); 76 toshiba_rbtx4927_setup();
77 } 77 }
78#endif 78#endif
79
80 return;
81} 79}
82 80
83early_initcall(tx4927_setup);
84
85void __init tx4927_time_init(void) 81void __init tx4927_time_init(void)
86{ 82{
87 83
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index fc0720599fd9..990fcb294bab 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -77,6 +77,11 @@
77#include <linux/hdreg.h> 77#include <linux/hdreg.h>
78#include <linux/ide.h> 78#include <linux/ide.h>
79#endif 79#endif
80#ifdef CONFIG_SERIAL_TXX9
81#include <linux/tty.h>
82#include <linux/serial.h>
83#include <linux/serial_core.h>
84#endif
80 85
81#undef TOSHIBA_RBTX4927_SETUP_DEBUG 86#undef TOSHIBA_RBTX4927_SETUP_DEBUG
82 87
@@ -920,12 +925,30 @@ void __init toshiba_rbtx4927_setup(void)
920 925
921#endif /* CONFIG_PCI */ 926#endif /* CONFIG_PCI */
922 927
928#ifdef CONFIG_SERIAL_TXX9
929 {
930 extern int early_serial_txx9_setup(struct uart_port *port);
931 int i;
932 struct uart_port req;
933 for(i = 0; i < 2; i++) {
934 memset(&req, 0, sizeof(req));
935 req.line = i;
936 req.iotype = UPIO_MEM;
937 req.membase = (char *)(0xff1ff300 + i * 0x100);
938 req.mapbase = 0xff1ff300 + i * 0x100;
939 req.irq = 32 + i;
940 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
941 req.uartclk = 50000000;
942 early_serial_txx9_setup(&req);
943 }
944 }
923#ifdef CONFIG_SERIAL_TXX9_CONSOLE 945#ifdef CONFIG_SERIAL_TXX9_CONSOLE
924 argptr = prom_getcmdline(); 946 argptr = prom_getcmdline();
925 if (strstr(argptr, "console=") == NULL) { 947 if (strstr(argptr, "console=") == NULL) {
926 strcat(argptr, " console=ttyS0,38400"); 948 strcat(argptr, " console=ttyS0,38400");
927 } 949 }
928#endif 950#endif
951#endif
929 952
930#ifdef CONFIG_ROOT_NFS 953#ifdef CONFIG_ROOT_NFS
931 argptr = prom_getcmdline(); 954 argptr = prom_getcmdline();
diff --git a/arch/mips/tx4938/Kconfig b/arch/mips/tx4938/Kconfig
new file mode 100644
index 000000000000..d90e9cd85138
--- /dev/null
+++ b/arch/mips/tx4938/Kconfig
@@ -0,0 +1,24 @@
1if TOSHIBA_RBTX4938
2
3comment "Multiplex Pin Select"
4choice
5 prompt "PIO[58:61]"
6 default TOSHIBA_RBTX4938_MPLEX_PIO58_61
7
8config TOSHIBA_RBTX4938_MPLEX_PIO58_61
9 bool "PIO"
10config TOSHIBA_RBTX4938_MPLEX_NAND
11 bool "NAND"
12config TOSHIBA_RBTX4938_MPLEX_ATA
13 bool "ATA"
14
15endchoice
16
17config TX4938_NAND_BOOT
18 depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND
19 bool "NAND Boot Support (EXPERIMENTAL)"
20 help
21 This is only for Toshiba RBTX4938 reference board, which has NAND IPL.
22 Select this option if you need to use NAND boot.
23
24endif
diff --git a/arch/mips/tx4938/common/Makefile b/arch/mips/tx4938/common/Makefile
new file mode 100644
index 000000000000..74c95c5bcdbf
--- /dev/null
+++ b/arch/mips/tx4938/common/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for common code for Toshiba TX4927 based systems
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8
9obj-y += prom.o setup.o irq.o irq_handler.o rtc_rx5c348.o
10obj-$(CONFIG_KGDB) += dbgio.o
11
diff --git a/arch/mips/tx4938/common/dbgio.c b/arch/mips/tx4938/common/dbgio.c
new file mode 100644
index 000000000000..bea59ff1842a
--- /dev/null
+++ b/arch/mips/tx4938/common/dbgio.c
@@ -0,0 +1,50 @@
1/*
2 * linux/arch/mips/tx4938/common/dbgio.c
3 *
4 * kgdb interface for gdb
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2005 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 * Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
32 */
33
34#include <asm/mipsregs.h>
35#include <asm/system.h>
36#include <asm/tx4938/tx4938_mips.h>
37
38extern u8 txx9_sio_kdbg_rd(void);
39extern int txx9_sio_kdbg_wr( u8 ch );
40
41u8 getDebugChar(void)
42{
43 return (txx9_sio_kdbg_rd());
44}
45
46int putDebugChar(u8 byte)
47{
48 return (txx9_sio_kdbg_wr(byte));
49}
50
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
new file mode 100644
index 000000000000..4f90d7faf634
--- /dev/null
+++ b/arch/mips/tx4938/common/irq.c
@@ -0,0 +1,424 @@
1/*
2 * linux/arch/mps/tx4938/common/irq.c
3 *
4 * Common tx4938 irq handler
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14#include <linux/errno.h>
15#include <linux/init.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/signal.h>
19#include <linux/sched.h>
20#include <linux/types.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/timex.h>
24#include <linux/slab.h>
25#include <linux/random.h>
26#include <linux/irq.h>
27#include <asm/bitops.h>
28#include <asm/bootinfo.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/mipsregs.h>
32#include <asm/system.h>
33#include <asm/tx4938/rbtx4938.h>
34
35/**********************************************************************************/
36/* Forwad definitions for all pic's */
37/**********************************************************************************/
38
39static unsigned int tx4938_irq_cp0_startup(unsigned int irq);
40static void tx4938_irq_cp0_shutdown(unsigned int irq);
41static void tx4938_irq_cp0_enable(unsigned int irq);
42static void tx4938_irq_cp0_disable(unsigned int irq);
43static void tx4938_irq_cp0_mask_and_ack(unsigned int irq);
44static void tx4938_irq_cp0_end(unsigned int irq);
45
46static unsigned int tx4938_irq_pic_startup(unsigned int irq);
47static void tx4938_irq_pic_shutdown(unsigned int irq);
48static void tx4938_irq_pic_enable(unsigned int irq);
49static void tx4938_irq_pic_disable(unsigned int irq);
50static void tx4938_irq_pic_mask_and_ack(unsigned int irq);
51static void tx4938_irq_pic_end(unsigned int irq);
52
53/**********************************************************************************/
54/* Kernel structs for all pic's */
55/**********************************************************************************/
56DEFINE_SPINLOCK(tx4938_cp0_lock);
57DEFINE_SPINLOCK(tx4938_pic_lock);
58
59#define TX4938_CP0_NAME "TX4938-CP0"
60static struct hw_interrupt_type tx4938_irq_cp0_type = {
61 .typename = TX4938_CP0_NAME,
62 .startup = tx4938_irq_cp0_startup,
63 .shutdown = tx4938_irq_cp0_shutdown,
64 .enable = tx4938_irq_cp0_enable,
65 .disable = tx4938_irq_cp0_disable,
66 .ack = tx4938_irq_cp0_mask_and_ack,
67 .end = tx4938_irq_cp0_end,
68 .set_affinity = NULL
69};
70
71#define TX4938_PIC_NAME "TX4938-PIC"
72static struct hw_interrupt_type tx4938_irq_pic_type = {
73 .typename = TX4938_PIC_NAME,
74 .startup = tx4938_irq_pic_startup,
75 .shutdown = tx4938_irq_pic_shutdown,
76 .enable = tx4938_irq_pic_enable,
77 .disable = tx4938_irq_pic_disable,
78 .ack = tx4938_irq_pic_mask_and_ack,
79 .end = tx4938_irq_pic_end,
80 .set_affinity = NULL
81};
82
83static struct irqaction tx4938_irq_pic_action = {
84 .handler = no_action,
85 .flags = 0,
86 .mask = CPU_MASK_NONE,
87 .name = TX4938_PIC_NAME
88};
89
90/**********************************************************************************/
91/* Functions for cp0 */
92/**********************************************************************************/
93
94#define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) )
95
96static void __init
97tx4938_irq_cp0_init(void)
98{
99 int i;
100
101 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) {
102 irq_desc[i].status = IRQ_DISABLED;
103 irq_desc[i].action = 0;
104 irq_desc[i].depth = 1;
105 irq_desc[i].handler = &tx4938_irq_cp0_type;
106 }
107
108 return;
109}
110
111static unsigned int
112tx4938_irq_cp0_startup(unsigned int irq)
113{
114 tx4938_irq_cp0_enable(irq);
115
116 return (0);
117}
118
119static void
120tx4938_irq_cp0_shutdown(unsigned int irq)
121{
122 tx4938_irq_cp0_disable(irq);
123}
124
125static void
126tx4938_irq_cp0_enable(unsigned int irq)
127{
128 unsigned long flags;
129
130 spin_lock_irqsave(&tx4938_cp0_lock, flags);
131
132 set_c0_status(tx4938_irq_cp0_mask(irq));
133
134 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
135}
136
137static void
138tx4938_irq_cp0_disable(unsigned int irq)
139{
140 unsigned long flags;
141
142 spin_lock_irqsave(&tx4938_cp0_lock, flags);
143
144 clear_c0_status(tx4938_irq_cp0_mask(irq));
145
146 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
147
148 return;
149}
150
151static void
152tx4938_irq_cp0_mask_and_ack(unsigned int irq)
153{
154 tx4938_irq_cp0_disable(irq);
155
156 return;
157}
158
159static void
160tx4938_irq_cp0_end(unsigned int irq)
161{
162 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
163 tx4938_irq_cp0_enable(irq);
164 }
165
166 return;
167}
168
169/**********************************************************************************/
170/* Functions for pic */
171/**********************************************************************************/
172
173u32
174tx4938_irq_pic_addr(int irq)
175{
176 /* MVMCP -- need to formulize this */
177 irq -= TX4938_IRQ_PIC_BEG;
178
179 switch (irq) {
180 case 17:
181 case 16:
182 case 1:
183 case 0:{
184 return (TX4938_MKA(TX4938_IRC_IRLVL0));
185 }
186 case 19:
187 case 18:
188 case 3:
189 case 2:{
190 return (TX4938_MKA(TX4938_IRC_IRLVL1));
191 }
192 case 21:
193 case 20:
194 case 5:
195 case 4:{
196 return (TX4938_MKA(TX4938_IRC_IRLVL2));
197 }
198 case 23:
199 case 22:
200 case 7:
201 case 6:{
202 return (TX4938_MKA(TX4938_IRC_IRLVL3));
203 }
204 case 25:
205 case 24:
206 case 9:
207 case 8:{
208 return (TX4938_MKA(TX4938_IRC_IRLVL4));
209 }
210 case 27:
211 case 26:
212 case 11:
213 case 10:{
214 return (TX4938_MKA(TX4938_IRC_IRLVL5));
215 }
216 case 29:
217 case 28:
218 case 13:
219 case 12:{
220 return (TX4938_MKA(TX4938_IRC_IRLVL6));
221 }
222 case 31:
223 case 30:
224 case 15:
225 case 14:{
226 return (TX4938_MKA(TX4938_IRC_IRLVL7));
227 }
228 }
229
230 return (0);
231}
232
233u32
234tx4938_irq_pic_mask(int irq)
235{
236 /* MVMCP -- need to formulize this */
237 irq -= TX4938_IRQ_PIC_BEG;
238
239 switch (irq) {
240 case 31:
241 case 29:
242 case 27:
243 case 25:
244 case 23:
245 case 21:
246 case 19:
247 case 17:{
248 return (0x07000000);
249 }
250 case 30:
251 case 28:
252 case 26:
253 case 24:
254 case 22:
255 case 20:
256 case 18:
257 case 16:{
258 return (0x00070000);
259 }
260 case 15:
261 case 13:
262 case 11:
263 case 9:
264 case 7:
265 case 5:
266 case 3:
267 case 1:{
268 return (0x00000700);
269 }
270 case 14:
271 case 12:
272 case 10:
273 case 8:
274 case 6:
275 case 4:
276 case 2:
277 case 0:{
278 return (0x00000007);
279 }
280 }
281 return (0x00000000);
282}
283
284static void
285tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
286{
287 unsigned long val = 0;
288
289 val = TX4938_RD(pic_reg);
290 val &= (~clr_bits);
291 val |= (set_bits);
292 TX4938_WR(pic_reg, val);
293 mmiowb();
294 TX4938_RD(pic_reg);
295
296 return;
297}
298
299static void __init
300tx4938_irq_pic_init(void)
301{
302 unsigned long flags;
303 int i;
304
305 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) {
306 irq_desc[i].status = IRQ_DISABLED;
307 irq_desc[i].action = 0;
308 irq_desc[i].depth = 2;
309 irq_desc[i].handler = &tx4938_irq_pic_type;
310 }
311
312 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
313
314 spin_lock_irqsave(&tx4938_pic_lock, flags);
315
316 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
317 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
318
319 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
320
321 return;
322}
323
324static unsigned int
325tx4938_irq_pic_startup(unsigned int irq)
326{
327 tx4938_irq_pic_enable(irq);
328
329 return (0);
330}
331
332static void
333tx4938_irq_pic_shutdown(unsigned int irq)
334{
335 tx4938_irq_pic_disable(irq);
336
337 return;
338}
339
340static void
341tx4938_irq_pic_enable(unsigned int irq)
342{
343 unsigned long flags;
344
345 spin_lock_irqsave(&tx4938_pic_lock, flags);
346
347 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
348 tx4938_irq_pic_mask(irq));
349
350 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
351
352 return;
353}
354
355static void
356tx4938_irq_pic_disable(unsigned int irq)
357{
358 unsigned long flags;
359
360 spin_lock_irqsave(&tx4938_pic_lock, flags);
361
362 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
363 tx4938_irq_pic_mask(irq), 0);
364
365 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
366
367 return;
368}
369
370static void
371tx4938_irq_pic_mask_and_ack(unsigned int irq)
372{
373 tx4938_irq_pic_disable(irq);
374
375 return;
376}
377
378static void
379tx4938_irq_pic_end(unsigned int irq)
380{
381 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
382 tx4938_irq_pic_enable(irq);
383 }
384
385 return;
386}
387
388/**********************************************************************************/
389/* Main init functions */
390/**********************************************************************************/
391
392void __init
393tx4938_irq_init(void)
394{
395 extern asmlinkage void tx4938_irq_handler(void);
396
397 tx4938_irq_cp0_init();
398 tx4938_irq_pic_init();
399 set_except_vector(0, tx4938_irq_handler);
400
401 return;
402}
403
404int
405tx4938_irq_nested(void)
406{
407 int sw_irq = 0;
408 u32 level2;
409
410 level2 = TX4938_RD(0xff1ff6a0);
411 if ((level2 & 0x10000) == 0) {
412 level2 &= 0x1f;
413 sw_irq = TX4938_IRQ_PIC_BEG + level2;
414 if (sw_irq == 26) {
415 {
416 extern int toshiba_rbtx4938_irq_nested(int sw_irq);
417 sw_irq = toshiba_rbtx4938_irq_nested(sw_irq);
418 }
419 }
420 }
421
422 wbflush();
423 return (sw_irq);
424}
diff --git a/arch/mips/tx4938/common/irq_handler.S b/arch/mips/tx4938/common/irq_handler.S
new file mode 100644
index 000000000000..1b2f72bac42d
--- /dev/null
+++ b/arch/mips/tx4938/common/irq_handler.S
@@ -0,0 +1,84 @@
1/*
2 * linux/arch/mips/tx4938/common/handler.S
3 *
4 * Primary interrupt handler for tx4938 based systems
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14#include <asm/asm.h>
15#include <asm/mipsregs.h>
16#include <asm/addrspace.h>
17#include <asm/regdef.h>
18#include <asm/stackframe.h>
19#include <asm/tx4938/rbtx4938.h>
20
21
22 .align 5
23 NESTED(tx4938_irq_handler, PT_SIZE, sp)
24 SAVE_ALL
25 CLI
26 .set at
27
28 mfc0 t0, CP0_CAUSE
29 mfc0 t1, CP0_STATUS
30 and t0, t1
31
32 andi t1, t0, STATUSF_IP7 /* cpu timer */
33 bnez t1, ll_ip7
34
35 /* IP6..IP3 multiplexed -- do not use */
36
37 andi t1, t0, STATUSF_IP2 /* tx4938 pic */
38 bnez t1, ll_ip2
39
40 andi t1, t0, STATUSF_IP1 /* user line 1 */
41 bnez t1, ll_ip1
42
43 andi t1, t0, STATUSF_IP0 /* user line 0 */
44 bnez t1, ll_ip0
45
46 .set reorder
47
48 nop
49 END(tx4938_irq_handler)
50
51 .align 5
52
53
54ll_ip7:
55 li a0, TX4938_IRQ_CPU_TIMER
56 move a1, sp
57 jal do_IRQ
58 j ret_from_irq
59
60
61ll_ip2:
62 jal tx4938_irq_nested
63 nop
64 beqz v0, goto_spurious_interrupt
65 nop
66 move a0, v0
67 move a1, sp
68 jal do_IRQ
69 j ret_from_irq
70
71goto_spurious_interrupt:
72 j ret_from_irq
73
74ll_ip1:
75 li a0, TX4938_IRQ_USER1
76 move a1, sp
77 jal do_IRQ
78 j ret_from_irq
79
80ll_ip0:
81 li a0, TX4938_IRQ_USER0
82 move a1, sp
83 jal do_IRQ
84 j ret_from_irq
diff --git a/arch/mips/tx4938/common/prom.c b/arch/mips/tx4938/common/prom.c
new file mode 100644
index 000000000000..3189a65f7d7e
--- /dev/null
+++ b/arch/mips/tx4938/common/prom.c
@@ -0,0 +1,129 @@
1/*
2 * linux/arch/mips/tx4938/common/prom.c
3 *
4 * common tx4938 memory interface
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/bootmem.h>
19
20#include <asm/addrspace.h>
21#include <asm/bootinfo.h>
22#include <asm/tx4938/tx4938.h>
23
24static unsigned int __init
25tx4938_process_sdccr(u64 * addr)
26{
27 u64 val;
28 unsigned int sdccr_ce;
29 unsigned int sdccr_rs;
30 unsigned int sdccr_cs;
31 unsigned int sdccr_mw;
32 unsigned int rs = 0;
33 unsigned int cs = 0;
34 unsigned int mw = 0;
35 unsigned int bc = 4;
36 unsigned int msize = 0;
37
38 val = (*((vu64 *) (addr)));
39
40 /* MVMCP -- need #defs for these bits masks */
41 sdccr_ce = ((val & (1 << 10)) >> 10);
42 sdccr_rs = ((val & (3 << 5)) >> 5);
43 sdccr_cs = ((val & (7 << 2)) >> 2);
44 sdccr_mw = ((val & (1 << 0)) >> 0);
45
46 if (sdccr_ce) {
47 switch (sdccr_rs) {
48 case 0:{
49 rs = 2048;
50 break;
51 }
52 case 1:{
53 rs = 4096;
54 break;
55 }
56 case 2:{
57 rs = 8192;
58 break;
59 }
60 default:{
61 rs = 0;
62 break;
63 }
64 }
65 switch (sdccr_cs) {
66 case 0:{
67 cs = 256;
68 break;
69 }
70 case 1:{
71 cs = 512;
72 break;
73 }
74 case 2:{
75 cs = 1024;
76 break;
77 }
78 case 3:{
79 cs = 2048;
80 break;
81 }
82 case 4:{
83 cs = 4096;
84 break;
85 }
86 default:{
87 cs = 0;
88 break;
89 }
90 }
91 switch (sdccr_mw) {
92 case 0:{
93 mw = 8;
94 break;
95 } /* 8 bytes = 64 bits */
96 case 1:{
97 mw = 4;
98 break;
99 } /* 4 bytes = 32 bits */
100 }
101 }
102
103 /* bytes per chip MB per chip bank count */
104 msize = (((rs * cs * mw) / (1024 * 1024)) * (bc));
105
106 /* MVMCP -- bc hard coded to 4 from table 9.3.1 */
107 /* boad supports bc=2 but no way to detect */
108
109 return (msize);
110}
111
112unsigned int __init
113tx4938_get_mem_size(void)
114{
115 unsigned int c0;
116 unsigned int c1;
117 unsigned int c2;
118 unsigned int c3;
119 unsigned int total;
120
121 /* MVMCP -- need #defs for these registers */
122 c0 = tx4938_process_sdccr((u64 *) 0xff1f8000);
123 c1 = tx4938_process_sdccr((u64 *) 0xff1f8008);
124 c2 = tx4938_process_sdccr((u64 *) 0xff1f8010);
125 c3 = tx4938_process_sdccr((u64 *) 0xff1f8018);
126 total = c0 + c1 + c2 + c3;
127
128 return (total);
129}
diff --git a/arch/mips/tx4938/common/rtc_rx5c348.c b/arch/mips/tx4938/common/rtc_rx5c348.c
new file mode 100644
index 000000000000..d249edbb6af4
--- /dev/null
+++ b/arch/mips/tx4938/common/rtc_rx5c348.c
@@ -0,0 +1,202 @@
1/*
2 * RTC routines for RICOH Rx5C348 SPI chip.
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/string.h>
15#include <linux/rtc.h>
16#include <linux/time.h>
17#include <asm/time.h>
18#include <asm/tx4938/spi.h>
19
20#define EPOCH 2000
21
22/* registers */
23#define Rx5C348_REG_SECOND 0
24#define Rx5C348_REG_MINUTE 1
25#define Rx5C348_REG_HOUR 2
26#define Rx5C348_REG_WEEK 3
27#define Rx5C348_REG_DAY 4
28#define Rx5C348_REG_MONTH 5
29#define Rx5C348_REG_YEAR 6
30#define Rx5C348_REG_ADJUST 7
31#define Rx5C348_REG_ALARM_W_MIN 8
32#define Rx5C348_REG_ALARM_W_HOUR 9
33#define Rx5C348_REG_ALARM_W_WEEK 10
34#define Rx5C348_REG_ALARM_D_MIN 11
35#define Rx5C348_REG_ALARM_D_HOUR 12
36#define Rx5C348_REG_CTL1 14
37#define Rx5C348_REG_CTL2 15
38
39/* register bits */
40#define Rx5C348_BIT_PM 0x20 /* REG_HOUR */
41#define Rx5C348_BIT_Y2K 0x80 /* REG_MONTH */
42#define Rx5C348_BIT_24H 0x20 /* REG_CTL1 */
43#define Rx5C348_BIT_XSTP 0x10 /* REG_CTL2 */
44
45/* commands */
46#define Rx5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */
47#define Rx5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */
48#define Rx5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */
49#define Rx5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */
50
51static struct spi_dev_desc srtc_dev_desc = {
52 .baud = 1000000, /* 1.0Mbps @ Vdd 2.0V */
53 .tcss = 31,
54 .tcsh = 1,
55 .tcsr = 62,
56 /* 31us for Tcss (62us for Tcsr) is required for carry operation) */
57 .byteorder = 1, /* MSB-First */
58 .polarity = 0, /* High-Active */
59 .phase = 1, /* Shift-Then-Sample */
60
61};
62static int srtc_chipid;
63static int srtc_24h;
64
65static inline int
66spi_rtc_io(unsigned char *inbuf, unsigned char *outbuf, unsigned int count)
67{
68 unsigned char *inbufs[1], *outbufs[1];
69 unsigned int incounts[2], outcounts[2];
70 inbufs[0] = inbuf;
71 incounts[0] = count;
72 incounts[1] = 0;
73 outbufs[0] = outbuf;
74 outcounts[0] = count;
75 outcounts[1] = 0;
76 return txx9_spi_io(srtc_chipid, &srtc_dev_desc,
77 inbufs, incounts, outbufs, outcounts, 0);
78}
79
80/*
81 * Conversion between binary and BCD.
82 */
83#ifndef BCD_TO_BIN
84#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
85#endif
86
87#ifndef BIN_TO_BCD
88#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
89#endif
90
91/* RTC-dependent code for time.c */
92
93static int
94rtc_rx5c348_set_time(unsigned long t)
95{
96 unsigned char inbuf[8];
97 struct rtc_time tm;
98 u8 year, month, day, hour, minute, second, century;
99
100 /* convert */
101 to_tm(t, &tm);
102
103 year = tm.tm_year % 100;
104 month = tm.tm_mon+1; /* tm_mon starts from 0 to 11 */
105 day = tm.tm_mday;
106 hour = tm.tm_hour;
107 minute = tm.tm_min;
108 second = tm.tm_sec;
109 century = tm.tm_year / 100;
110
111 inbuf[0] = Rx5C348_CMD_MW(Rx5C348_REG_SECOND);
112 BIN_TO_BCD(second);
113 inbuf[1] = second;
114 BIN_TO_BCD(minute);
115 inbuf[2] = minute;
116
117 if (srtc_24h) {
118 BIN_TO_BCD(hour);
119 inbuf[3] = hour;
120 } else {
121 /* hour 0 is AM12, noon is PM12 */
122 inbuf[3] = 0;
123 if (hour >= 12)
124 inbuf[3] = Rx5C348_BIT_PM;
125 hour = (hour + 11) % 12 + 1;
126 BIN_TO_BCD(hour);
127 inbuf[3] |= hour;
128 }
129 inbuf[4] = 0; /* ignore week */
130 BIN_TO_BCD(day);
131 inbuf[5] = day;
132 BIN_TO_BCD(month);
133 inbuf[6] = month;
134 if (century >= 20)
135 inbuf[6] |= Rx5C348_BIT_Y2K;
136 BIN_TO_BCD(year);
137 inbuf[7] = year;
138 /* write in one transfer to avoid data inconsistency */
139 return spi_rtc_io(inbuf, NULL, 8);
140}
141
142static unsigned long
143rtc_rx5c348_get_time(void)
144{
145 unsigned char inbuf[8], outbuf[8];
146 unsigned int year, month, day, hour, minute, second;
147
148 inbuf[0] = Rx5C348_CMD_MR(Rx5C348_REG_SECOND);
149 memset(inbuf + 1, 0, 7);
150 /* read in one transfer to avoid data inconsistency */
151 if (spi_rtc_io(inbuf, outbuf, 8))
152 return 0;
153 second = outbuf[1];
154 BCD_TO_BIN(second);
155 minute = outbuf[2];
156 BCD_TO_BIN(minute);
157 if (srtc_24h) {
158 hour = outbuf[3];
159 BCD_TO_BIN(hour);
160 } else {
161 hour = outbuf[3] & ~Rx5C348_BIT_PM;
162 BCD_TO_BIN(hour);
163 hour %= 12;
164 if (outbuf[3] & Rx5C348_BIT_PM)
165 hour += 12;
166 }
167 day = outbuf[5];
168 BCD_TO_BIN(day);
169 month = outbuf[6] & ~Rx5C348_BIT_Y2K;
170 BCD_TO_BIN(month);
171 year = outbuf[7];
172 BCD_TO_BIN(year);
173 year += EPOCH;
174
175 return mktime(year, month, day, hour, minute, second);
176}
177
178void __init
179rtc_rx5c348_init(int chipid)
180{
181 unsigned char inbuf[2], outbuf[2];
182 srtc_chipid = chipid;
183 /* turn on RTC if it is not on */
184 inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL2);
185 inbuf[1] = 0;
186 spi_rtc_io(inbuf, outbuf, 2);
187 if (outbuf[1] & Rx5C348_BIT_XSTP) {
188 inbuf[0] = Rx5C348_CMD_W(Rx5C348_REG_CTL2);
189 inbuf[1] = 0;
190 spi_rtc_io(inbuf, NULL, 2);
191 }
192
193 inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL1);
194 inbuf[1] = 0;
195 spi_rtc_io(inbuf, outbuf, 2);
196 if (outbuf[1] & Rx5C348_BIT_24H)
197 srtc_24h = 1;
198
199 /* set the function pointers */
200 rtc_get_time = rtc_rx5c348_get_time;
201 rtc_set_time = rtc_rx5c348_set_time;
202}
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
new file mode 100644
index 000000000000..fc992953bf95
--- /dev/null
+++ b/arch/mips/tx4938/common/setup.c
@@ -0,0 +1,91 @@
1/*
2 * linux/arch/mips/tx4938/common/setup.c
3 *
4 * common tx4938 setup routines
5 *
6 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
7 * terms of the GNU General Public License version 2. This program is
8 * licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 */
13
14#include <linux/errno.h>
15#include <linux/init.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/signal.h>
19#include <linux/sched.h>
20#include <linux/types.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/timex.h>
24#include <linux/slab.h>
25#include <linux/random.h>
26#include <linux/irq.h>
27#include <asm/bitops.h>
28#include <asm/bootinfo.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/mipsregs.h>
32#include <asm/system.h>
33#include <asm/time.h>
34#include <asm/time.h>
35#include <asm/tx4938/rbtx4938.h>
36
37extern void toshiba_rbtx4938_setup(void);
38extern void rbtx4938_time_init(void);
39
40void __init tx4938_setup(void);
41void __init tx4938_time_init(void);
42void __init tx4938_timer_setup(struct irqaction *irq);
43void dump_cp0(char *key);
44
45void (*__wbflush) (void);
46
47static void
48tx4938_write_buffer_flush(void)
49{
50 mmiowb();
51
52 __asm__ __volatile__(
53 ".set push\n\t"
54 ".set noreorder\n\t"
55 "lw $0,%0\n\t"
56 "nop\n\t"
57 ".set pop"
58 : /* no output */
59 : "m" (*(int *)KSEG1)
60 : "memory");
61}
62
63void __init
64plat_setup(void)
65{
66 board_time_init = tx4938_time_init;
67 board_timer_setup = tx4938_timer_setup;
68 __wbflush = tx4938_write_buffer_flush;
69 toshiba_rbtx4938_setup();
70}
71
72void __init
73tx4938_time_init(void)
74{
75 rbtx4938_time_init();
76}
77
78void __init
79tx4938_timer_setup(struct irqaction *irq)
80{
81 u32 count;
82 u32 c1;
83 u32 c2;
84
85 setup_irq(TX4938_IRQ_CPU_TIMER, irq);
86
87 c1 = read_c0_count();
88 count = c1 + (mips_hpt_frequency / HZ);
89 write_c0_compare(count);
90 c2 = read_c0_count();
91}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/Makefile b/arch/mips/tx4938/toshiba_rbtx4938/Makefile
new file mode 100644
index 000000000000..226941279d75
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for common code for Toshiba TX4927 based systems
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8
9obj-y += prom.o setup.o irq.o spi_eeprom.o spi_txx9.o
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
new file mode 100644
index 000000000000..230f5a93c2e6
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -0,0 +1,244 @@
1/*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c
3 *
4 * Toshiba RBTX4938 specific interrupt handlers
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14
15/*
16IRQ Device
17
1816 TX4938-CP0/00 Software 0
1917 TX4938-CP0/01 Software 1
2018 TX4938-CP0/02 Cascade TX4938-CP0
2119 TX4938-CP0/03 Multiplexed -- do not use
2220 TX4938-CP0/04 Multiplexed -- do not use
2321 TX4938-CP0/05 Multiplexed -- do not use
2422 TX4938-CP0/06 Multiplexed -- do not use
2523 TX4938-CP0/07 CPU TIMER
26
2724 TX4938-PIC/00
2825 TX4938-PIC/01
2926 TX4938-PIC/02 Cascade RBTX4938-IOC
3027 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet
3128 TX4938-PIC/04
3229 TX4938-PIC/05 TX4938 ETH1
3330 TX4938-PIC/06 TX4938 ETH0
3431 TX4938-PIC/07
3532 TX4938-PIC/08 TX4938 SIO 0
3633 TX4938-PIC/09 TX4938 SIO 1
3734 TX4938-PIC/10 TX4938 DMA0
3835 TX4938-PIC/11 TX4938 DMA1
3936 TX4938-PIC/12 TX4938 DMA2
4037 TX4938-PIC/13 TX4938 DMA3
4138 TX4938-PIC/14
4239 TX4938-PIC/15
4340 TX4938-PIC/16 TX4938 PCIC
4441 TX4938-PIC/17 TX4938 TMR0
4542 TX4938-PIC/18 TX4938 TMR1
4643 TX4938-PIC/19 TX4938 TMR2
4744 TX4938-PIC/20
4845 TX4938-PIC/21
4946 TX4938-PIC/22 TX4938 PCIERR
5047 TX4938-PIC/23
5148 TX4938-PIC/24
5249 TX4938-PIC/25
5350 TX4938-PIC/26
5451 TX4938-PIC/27
5552 TX4938-PIC/28
5653 TX4938-PIC/29
5754 TX4938-PIC/30
5855 TX4938-PIC/31 TX4938 SPI
59
6056 RBTX4938-IOC/00 PCI-D
6157 RBTX4938-IOC/01 PCI-C
6258 RBTX4938-IOC/02 PCI-B
6359 RBTX4938-IOC/03 PCI-A
6460 RBTX4938-IOC/04 RTC
6561 RBTX4938-IOC/05 ATA
6662 RBTX4938-IOC/06 MODEM
6763 RBTX4938-IOC/07 SWINT
68*/
69#include <linux/init.h>
70#include <linux/kernel.h>
71#include <linux/types.h>
72#include <linux/mm.h>
73#include <linux/swap.h>
74#include <linux/ioport.h>
75#include <linux/sched.h>
76#include <linux/interrupt.h>
77#include <linux/pci.h>
78#include <linux/timex.h>
79#include <asm/bootinfo.h>
80#include <asm/page.h>
81#include <asm/io.h>
82#include <asm/irq.h>
83#include <asm/processor.h>
84#include <asm/ptrace.h>
85#include <asm/reboot.h>
86#include <asm/time.h>
87#include <linux/version.h>
88#include <linux/bootmem.h>
89#include <asm/tx4938/rbtx4938.h>
90
91static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq);
92static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq);
93static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
94static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
95static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq);
96static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq);
97
98DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock);
99
100#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
101static struct hw_interrupt_type toshiba_rbtx4938_irq_ioc_type = {
102 .typename = TOSHIBA_RBTX4938_IOC_NAME,
103 .startup = toshiba_rbtx4938_irq_ioc_startup,
104 .shutdown = toshiba_rbtx4938_irq_ioc_shutdown,
105 .enable = toshiba_rbtx4938_irq_ioc_enable,
106 .disable = toshiba_rbtx4938_irq_ioc_disable,
107 .ack = toshiba_rbtx4938_irq_ioc_mask_and_ack,
108 .end = toshiba_rbtx4938_irq_ioc_end,
109 .set_affinity = NULL
110};
111
112#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
113#define TOSHIBA_RBTX4938_IOC_INTR_STAT 0xb7f0200a
114
115int
116toshiba_rbtx4938_irq_nested(int sw_irq)
117{
118 u8 level3;
119
120 level3 = reg_rd08(TOSHIBA_RBTX4938_IOC_INTR_STAT) & 0xff;
121 if (level3) {
122 /* must use fls so onboard ATA has priority */
123 sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;
124 }
125
126 wbflush();
127 return sw_irq;
128}
129
130static struct irqaction toshiba_rbtx4938_irq_ioc_action = {
131 .handler = no_action,
132 .flags = 0,
133 .mask = CPU_MASK_NONE,
134 .name = TOSHIBA_RBTX4938_IOC_NAME,
135};
136
137/**********************************************************************************/
138/* Functions for ioc */
139/**********************************************************************************/
140static void __init
141toshiba_rbtx4938_irq_ioc_init(void)
142{
143 int i;
144
145 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
146 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) {
147 irq_desc[i].status = IRQ_DISABLED;
148 irq_desc[i].action = 0;
149 irq_desc[i].depth = 3;
150 irq_desc[i].handler = &toshiba_rbtx4938_irq_ioc_type;
151 }
152
153 setup_irq(RBTX4938_IRQ_IOCINT,
154 &toshiba_rbtx4938_irq_ioc_action);
155}
156
157static unsigned int
158toshiba_rbtx4938_irq_ioc_startup(unsigned int irq)
159{
160 toshiba_rbtx4938_irq_ioc_enable(irq);
161
162 return 0;
163}
164
165static void
166toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq)
167{
168 toshiba_rbtx4938_irq_ioc_disable(irq);
169}
170
171static void
172toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
173{
174 unsigned long flags;
175 volatile unsigned char v;
176
177 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
178
179 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
180 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
181 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
182 mmiowb();
183 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
184
185 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
186}
187
188static void
189toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
190{
191 unsigned long flags;
192 volatile unsigned char v;
193
194 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
195
196 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
197 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
198 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
199 mmiowb();
200 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
201
202 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
203}
204
205static void
206toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq)
207{
208 toshiba_rbtx4938_irq_ioc_disable(irq);
209}
210
211static void
212toshiba_rbtx4938_irq_ioc_end(unsigned int irq)
213{
214 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
215 toshiba_rbtx4938_irq_ioc_enable(irq);
216 }
217}
218
219extern void __init txx9_spi_irqinit(int irc_irq);
220
221void __init arch_init_irq(void)
222{
223 extern void tx4938_irq_init(void);
224
225 /* Now, interrupt control disabled, */
226 /* all IRC interrupts are masked, */
227 /* all IRC interrupt mode are Low Active. */
228
229 /* mask all IOC interrupts */
230 *rbtx4938_imask_ptr = 0;
231
232 /* clear SoftInt interrupts */
233 *rbtx4938_softint_ptr = 0;
234 tx4938_irq_init();
235 toshiba_rbtx4938_irq_ioc_init();
236 /* Onboard 10M Ether: High Active */
237 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000040);
238
239 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_SPI_SEL) {
240 txx9_spi_irqinit(RBTX4938_IRQ_IRC_SPI);
241 }
242
243 wbflush();
244}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/prom.c b/arch/mips/tx4938/toshiba_rbtx4938/prom.c
new file mode 100644
index 000000000000..7df8b32ba265
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/prom.c
@@ -0,0 +1,78 @@
1/*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c
3 *
4 * rbtx4938 specific prom routines
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14
15#include <linux/config.h>
16#include <linux/init.h>
17#include <linux/mm.h>
18#include <linux/sched.h>
19#include <linux/bootmem.h>
20
21#include <asm/addrspace.h>
22#include <asm/bootinfo.h>
23#include <asm/tx4938/tx4938.h>
24
25void __init prom_init_cmdline(void)
26{
27 int argc = (int) fw_arg0;
28 char **argv = (char **) fw_arg1;
29 int i;
30
31 /* ignore all built-in args if any f/w args given */
32 if (argc > 1) {
33 *arcs_cmdline = '\0';
34 }
35
36 for (i = 1; i < argc; i++) {
37 if (i != 1) {
38 strcat(arcs_cmdline, " ");
39 }
40 strcat(arcs_cmdline, argv[i]);
41 }
42}
43
44void __init prom_init(void)
45{
46 extern int tx4938_get_mem_size(void);
47 int msize;
48#ifndef CONFIG_TX4938_NAND_BOOT
49 prom_init_cmdline();
50#endif
51 mips_machgroup = MACH_GROUP_TOSHIBA;
52 mips_machtype = MACH_TOSHIBA_RBTX4938;
53
54 msize = tx4938_get_mem_size();
55 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
56
57 return;
58}
59
60unsigned long __init prom_free_prom_memory(void)
61{
62 return 0;
63}
64
65void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
66{
67 return;
68}
69
70const char *get_system_type(void)
71{
72 return "Toshiba RBTX4938";
73}
74
75char * __init prom_getcmdline(void)
76{
77 return &(arcs_cmdline[0]);
78}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
new file mode 100644
index 000000000000..9f1dcc8ca5a3
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -0,0 +1,1035 @@
1/*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c
3 *
4 * Setup pointers to hardware-dependent routines.
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/types.h>
17#include <linux/ioport.h>
18#include <linux/proc_fs.h>
19#include <linux/delay.h>
20#include <linux/interrupt.h>
21#include <linux/console.h>
22#include <linux/pci.h>
23#include <asm/wbflush.h>
24#include <asm/reboot.h>
25#include <asm/irq.h>
26#include <asm/time.h>
27#include <asm/uaccess.h>
28#include <asm/io.h>
29#include <asm/bootinfo.h>
30#include <asm/tx4938/rbtx4938.h>
31#ifdef CONFIG_SERIAL_TXX9
32#include <linux/tty.h>
33#include <linux/serial.h>
34#include <linux/serial_core.h>
35#endif
36
37extern void rbtx4938_time_init(void) __init;
38extern char * __init prom_getcmdline(void);
39static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
40
41/* These functions are used for rebooting or halting the machine*/
42extern void rbtx4938_machine_restart(char *command);
43extern void rbtx4938_machine_halt(void);
44extern void rbtx4938_machine_power_off(void);
45
46/* clocks */
47unsigned int txx9_master_clock;
48unsigned int txx9_cpu_clock;
49unsigned int txx9_gbus_clock;
50
51unsigned long rbtx4938_ce_base[8];
52unsigned long rbtx4938_ce_size[8];
53int txboard_pci66_mode;
54static int tx4938_pcic_trdyto; /* default: disabled */
55static int tx4938_pcic_retryto; /* default: disabled */
56static int tx4938_ccfg_toeon = 1;
57
58struct tx4938_pcic_reg *pcicptrs[4] = {
59 tx4938_pcicptr /* default setting for TX4938 */
60};
61
62static struct {
63 unsigned long base;
64 unsigned long size;
65} phys_regions[16] __initdata;
66static int num_phys_regions __initdata;
67
68#define PHYS_REGION_MINSIZE 0x10000
69
70void rbtx4938_machine_halt(void)
71{
72 printk(KERN_NOTICE "System Halted\n");
73 local_irq_disable();
74
75 while (1)
76 __asm__(".set\tmips3\n\t"
77 "wait\n\t"
78 ".set\tmips0");
79}
80
81void rbtx4938_machine_power_off(void)
82{
83 rbtx4938_machine_halt();
84 /* no return */
85}
86
87void rbtx4938_machine_restart(char *command)
88{
89 local_irq_disable();
90
91 printk("Rebooting...");
92 *rbtx4938_softresetlock_ptr = 1;
93 *rbtx4938_sfvol_ptr = 1;
94 *rbtx4938_softreset_ptr = 1;
95 wbflush();
96
97 while(1);
98}
99
100void __init
101txboard_add_phys_region(unsigned long base, unsigned long size)
102{
103 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
104 printk("phys_region overflow\n");
105 return;
106 }
107 phys_regions[num_phys_regions].base = base;
108 phys_regions[num_phys_regions].size = size;
109 num_phys_regions++;
110}
111unsigned long __init
112txboard_find_free_phys_region(unsigned long begin, unsigned long end,
113 unsigned long size)
114{
115 unsigned long base;
116 int i;
117
118 for (base = begin / size * size; base < end; base += size) {
119 for (i = 0; i < num_phys_regions; i++) {
120 if (phys_regions[i].size &&
121 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
122 base + (size - 1) >= phys_regions[i].base)
123 break;
124 }
125 if (i == num_phys_regions)
126 return base;
127 }
128 return 0;
129}
130unsigned long __init
131txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
132 unsigned long *size)
133{
134 unsigned long sz, base;
135 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
136 base = txboard_find_free_phys_region(begin, end, sz);
137 if (base) {
138 *size = sz;
139 return base;
140 }
141 }
142 return 0;
143}
144unsigned long __init
145txboard_request_phys_region_range(unsigned long begin, unsigned long end,
146 unsigned long size)
147{
148 unsigned long base;
149 base = txboard_find_free_phys_region(begin, end, size);
150 if (base)
151 txboard_add_phys_region(base, size);
152 return base;
153}
154unsigned long __init
155txboard_request_phys_region(unsigned long size)
156{
157 unsigned long base;
158 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
159 base = txboard_find_free_phys_region(begin, end, size);
160 if (base)
161 txboard_add_phys_region(base, size);
162 return base;
163}
164unsigned long __init
165txboard_request_phys_region_shrink(unsigned long *size)
166{
167 unsigned long base;
168 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
169 base = txboard_find_free_phys_region_shrink(begin, end, size);
170 if (base)
171 txboard_add_phys_region(base, *size);
172 return base;
173}
174
175#ifdef CONFIG_PCI
176void __init
177tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
178 struct pci_controller *channel,
179 unsigned long pci_io_base,
180 int extarb)
181{
182 int i;
183
184 /* Disable All Initiator Space */
185 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
186 TX4938_PCIC_PCICCFG_G2PMEN(1)|
187 TX4938_PCIC_PCICCFG_G2PMEN(2)|
188 TX4938_PCIC_PCICCFG_G2PIOEN);
189
190 /* GB->PCI mappings */
191 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
192 pcicptr->g2piogbase = pci_io_base |
193#ifdef __BIG_ENDIAN
194 TX4938_PCIC_G2PIOGBASE_ECHG
195#else
196 TX4938_PCIC_G2PIOGBASE_BSDIS
197#endif
198 ;
199 pcicptr->g2piopbase = 0;
200 for (i = 0; i < 3; i++) {
201 pcicptr->g2pmmask[i] = 0;
202 pcicptr->g2pmgbase[i] = 0;
203 pcicptr->g2pmpbase[i] = 0;
204 }
205 if (channel->mem_resource->end) {
206 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
207 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
208#ifdef __BIG_ENDIAN
209 TX4938_PCIC_G2PMnGBASE_ECHG
210#else
211 TX4938_PCIC_G2PMnGBASE_BSDIS
212#endif
213 ;
214 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
215 }
216 /* PCI->GB mappings (I/O 256B) */
217 pcicptr->p2giopbase = 0; /* 256B */
218 pcicptr->p2giogbase = 0;
219 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
220 pcicptr->p2gm0plbase = 0;
221 pcicptr->p2gm0pubase = 0;
222 pcicptr->p2gmgbase[0] = 0 |
223 TX4938_PCIC_P2GMnGBASE_TMEMEN |
224#ifdef __BIG_ENDIAN
225 TX4938_PCIC_P2GMnGBASE_TECHG
226#else
227 TX4938_PCIC_P2GMnGBASE_TBSDIS
228#endif
229 ;
230 /* PCI->GB mappings (MEM 16MB) */
231 pcicptr->p2gm1plbase = 0xffffffff;
232 pcicptr->p2gm1pubase = 0xffffffff;
233 pcicptr->p2gmgbase[1] = 0;
234 /* PCI->GB mappings (MEM 1MB) */
235 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
236 pcicptr->p2gmgbase[2] = 0;
237
238 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
239 /* Enable Initiator Memory Space */
240 if (channel->mem_resource->end)
241 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
242 /* Enable Initiator I/O Space */
243 if (channel->io_resource->end)
244 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
245 /* Enable Initiator Config */
246 pcicptr->pciccfg |=
247 TX4938_PCIC_PCICCFG_ICAEN |
248 TX4938_PCIC_PCICCFG_TCAR;
249
250 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
251 pcicptr->pcicfg1 = 0;
252
253 pcicptr->g2ptocnt &= ~0xffff;
254
255 if (tx4938_pcic_trdyto >= 0) {
256 pcicptr->g2ptocnt &= ~0xff;
257 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
258 }
259
260 if (tx4938_pcic_retryto >= 0) {
261 pcicptr->g2ptocnt &= ~0xff00;
262 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
263 }
264
265 /* Clear All Local Bus Status */
266 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
267 /* Enable All Local Bus Interrupts */
268 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
269 /* Clear All Initiator Status */
270 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
271 /* Enable All Initiator Interrupts */
272 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
273 /* Clear All PCI Status Error */
274 pcicptr->pcistatus =
275 (pcicptr->pcistatus & 0x0000ffff) |
276 (TX4938_PCIC_PCISTATUS_ALL << 16);
277 /* Enable All PCI Status Error Interrupts */
278 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
279
280 if (!extarb) {
281 /* Reset Bus Arbiter */
282 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
283 pcicptr->pbabm = 0;
284 /* Enable Bus Arbiter */
285 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
286 }
287
288 /* PCIC Int => IRC IRQ16 */
289 pcicptr->pcicfg2 =
290 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
291
292 pcicptr->pcistatus = PCI_COMMAND_MASTER |
293 PCI_COMMAND_MEMORY |
294 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
295}
296
297int __init
298tx4938_report_pciclk(void)
299{
300 unsigned long pcode = TX4938_REV_PCODE();
301 int pciclk = 0;
302 printk("TX%lx PCIC --%s PCICLK:",
303 pcode,
304 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
305 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
306
307 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
308 case TX4938_CCFG_PCIDIVMODE_4:
309 pciclk = txx9_cpu_clock / 4; break;
310 case TX4938_CCFG_PCIDIVMODE_4_5:
311 pciclk = txx9_cpu_clock * 2 / 9; break;
312 case TX4938_CCFG_PCIDIVMODE_5:
313 pciclk = txx9_cpu_clock / 5; break;
314 case TX4938_CCFG_PCIDIVMODE_5_5:
315 pciclk = txx9_cpu_clock * 2 / 11; break;
316 case TX4938_CCFG_PCIDIVMODE_8:
317 pciclk = txx9_cpu_clock / 8; break;
318 case TX4938_CCFG_PCIDIVMODE_9:
319 pciclk = txx9_cpu_clock / 9; break;
320 case TX4938_CCFG_PCIDIVMODE_10:
321 pciclk = txx9_cpu_clock / 10; break;
322 case TX4938_CCFG_PCIDIVMODE_11:
323 pciclk = txx9_cpu_clock / 11; break;
324 }
325 printk("Internal(%dMHz)", pciclk / 1000000);
326 } else {
327 printk("External");
328 pciclk = -1;
329 }
330 printk("\n");
331 return pciclk;
332}
333
334void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
335{
336 pcicptrs[ch] = pcicptr;
337}
338
339struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
340{
341 return pcicptrs[ch];
342}
343
344static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
345 int top_bus, int busnr, int devfn)
346{
347 static struct pci_dev dev;
348 static struct pci_bus bus;
349
350 dev.sysdata = (void *)hose;
351 dev.devfn = devfn;
352 bus.number = busnr;
353 bus.ops = hose->pci_ops;
354 bus.parent = NULL;
355 dev.bus = &bus;
356
357 return &dev;
358}
359
360#define EARLY_PCI_OP(rw, size, type) \
361static int early_##rw##_config_##size(struct pci_controller *hose, \
362 int top_bus, int bus, int devfn, int offset, type value) \
363{ \
364 return pci_##rw##_config_##size( \
365 fake_pci_dev(hose, top_bus, bus, devfn), \
366 offset, value); \
367}
368
369EARLY_PCI_OP(read, word, u16 *)
370
371int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
372{
373 u32 pci_devfn;
374 unsigned short vid;
375 int devfn_start = 0;
376 int devfn_stop = 0xff;
377 int cap66 = -1;
378 u16 stat;
379
380 printk("PCI: Checking 66MHz capabilities...\n");
381
382 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
383 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
384 PCI_VENDOR_ID, &vid);
385
386 if (vid == 0xffff) continue;
387
388 /* check 66MHz capability */
389 if (cap66 < 0)
390 cap66 = 1;
391 if (cap66) {
392 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
393 PCI_STATUS, &stat);
394 if (!(stat & PCI_STATUS_66MHZ)) {
395 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
396 current_bus, pci_devfn);
397 cap66 = 0;
398 break;
399 }
400 }
401 }
402 return cap66 > 0;
403}
404
405int __init
406tx4938_pciclk66_setup(void)
407{
408 int pciclk;
409
410 /* Assert M66EN */
411 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
412 /* Double PCICLK (if possible) */
413 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
414 unsigned int pcidivmode =
415 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
416 switch (pcidivmode) {
417 case TX4938_CCFG_PCIDIVMODE_8:
418 case TX4938_CCFG_PCIDIVMODE_4:
419 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
420 pciclk = txx9_cpu_clock / 4;
421 break;
422 case TX4938_CCFG_PCIDIVMODE_9:
423 case TX4938_CCFG_PCIDIVMODE_4_5:
424 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
425 pciclk = txx9_cpu_clock * 2 / 9;
426 break;
427 case TX4938_CCFG_PCIDIVMODE_10:
428 case TX4938_CCFG_PCIDIVMODE_5:
429 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
430 pciclk = txx9_cpu_clock / 5;
431 break;
432 case TX4938_CCFG_PCIDIVMODE_11:
433 case TX4938_CCFG_PCIDIVMODE_5_5:
434 default:
435 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
436 pciclk = txx9_cpu_clock * 2 / 11;
437 break;
438 }
439 tx4938_ccfgptr->ccfg =
440 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
441 | pcidivmode;
442 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
443 (unsigned long)tx4938_ccfgptr->ccfg);
444 } else {
445 pciclk = -1;
446 }
447 return pciclk;
448}
449
450extern struct pci_controller tx4938_pci_controller[];
451static int __init tx4938_pcibios_init(void)
452{
453 unsigned long mem_base[2];
454 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
455 unsigned long io_base[2];
456 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
457 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
458 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
459
460 PCIBIOS_MIN_IO = 0x00001000UL;
461 PCIBIOS_MIN_MEM = 0x01000000UL;
462
463 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
464 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
465
466 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
467 (unsigned short)(tx4938_pcicptr->pciid >> 16),
468 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
469 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
470 extarb ? "External" : "Internal");
471
472 /* setup PCI area */
473 tx4938_pci_controller[0].io_resource->start = io_base[0];
474 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
475 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
476 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
477
478 set_tx4938_pcicptr(0, tx4938_pcicptr);
479
480 register_pci_controller(&tx4938_pci_controller[0]);
481
482 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
483 printk("TX4938_CCFG_PCI66 already configured\n");
484 txboard_pci66_mode = -1; /* already configured */
485 }
486
487 /* Reset PCI Bus */
488 *rbtx4938_pcireset_ptr = 0;
489 /* Reset PCIC */
490 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
491 if (txboard_pci66_mode > 0)
492 tx4938_pciclk66_setup();
493 mdelay(10);
494 /* clear PCIC reset */
495 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
496 *rbtx4938_pcireset_ptr = 1;
497 wbflush();
498 tx4938_report_pcic_status1(tx4938_pcicptr);
499
500 tx4938_report_pciclk();
501 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
502 if (txboard_pci66_mode == 0 &&
503 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
504 /* Reset PCI Bus */
505 *rbtx4938_pcireset_ptr = 0;
506 /* Reset PCIC */
507 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
508 tx4938_pciclk66_setup();
509 mdelay(10);
510 /* clear PCIC reset */
511 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
512 *rbtx4938_pcireset_ptr = 1;
513 wbflush();
514 /* Reinitialize PCIC */
515 tx4938_report_pciclk();
516 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
517 }
518
519 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
520 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
521 /* Reset PCIC1 */
522 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
523 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
524 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
525 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
526 else
527 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
528 mdelay(10);
529 /* clear PCIC1 reset */
530 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
531 tx4938_report_pcic_status1(tx4938_pcic1ptr);
532
533 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
534 (unsigned short)(tx4938_pcic1ptr->pciid >> 16),
535 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
536 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
537 printk("%s PCICLK:%dMHz\n",
538 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
539 txx9_gbus_clock /
540 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
541 1000000);
542
543 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
544 tx4938_pci_controller[1].io_resource->start =
545 io_base[1] - io_base[0];
546 tx4938_pci_controller[1].io_resource->end =
547 io_base[1] - io_base[0] + io_size[1] - 1;
548 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
549 tx4938_pci_controller[1].mem_resource->end =
550 mem_base[1] + mem_size[1] - 1;
551 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
552
553 register_pci_controller(&tx4938_pci_controller[1]);
554
555 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
556
557 /* map ioport 0 to PCI I/O space address 0 */
558 set_io_port_base(KSEG1 + io_base[0]);
559
560 return 0;
561}
562
563arch_initcall(tx4938_pcibios_init);
564
565#endif /* CONFIG_PCI */
566
567/* SPI support */
568
569/* chip select for SPI devices */
570#define SEEPROM1_CS 7 /* PIO7 */
571#define SEEPROM2_CS 0 /* IOC */
572#define SEEPROM3_CS 1 /* IOC */
573#define SRTC_CS 2 /* IOC */
574
575static int rbtx4938_spi_cs_func(int chipid, int on)
576{
577 unsigned char bit;
578 switch (chipid) {
579 case RBTX4938_SEEPROM1_CHIPID:
580 if (on)
581 tx4938_pioptr->dout &= ~(1 << SEEPROM1_CS);
582 else
583 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
584 return 0;
585 break;
586 case RBTX4938_SEEPROM2_CHIPID:
587 bit = (1 << SEEPROM2_CS);
588 break;
589 case RBTX4938_SEEPROM3_CHIPID:
590 bit = (1 << SEEPROM3_CS);
591 break;
592 case RBTX4938_SRTC_CHIPID:
593 bit = (1 << SRTC_CS);
594 break;
595 default:
596 return -ENODEV;
597 }
598 /* bit1,2,4 are low active, bit3 is high active */
599 *rbtx4938_spics_ptr =
600 (*rbtx4938_spics_ptr & ~bit) |
601 ((on ? (bit ^ 0x0b) : ~(bit ^ 0x0b)) & bit);
602 return 0;
603}
604
605#ifdef CONFIG_PCI
606extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
607
608int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr)
609{
610 struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata;
611 static unsigned char dat[17];
612 static int read_dat = 0;
613 int ch = 0;
614
615 if (channel != &tx4938_pci_controller[1])
616 return -ENODEV;
617 /* TX4938 PCIC1 */
618 switch (PCI_SLOT(dev->devfn)) {
619 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
620 ch = 0;
621 break;
622 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
623 ch = 1;
624 break;
625 default:
626 return -ENODEV;
627 }
628 if (!read_dat) {
629 unsigned char sum;
630 int i;
631 read_dat = 1;
632 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
633 if (spi_eeprom_read(RBTX4938_SEEPROM1_CHIPID,
634 0, dat, sizeof(dat))) {
635 printk(KERN_ERR "seeprom: read error.\n");
636 } else {
637 if (strcmp(dat, "MAC") != 0)
638 printk(KERN_WARNING "seeprom: bad signature.\n");
639 for (i = 0, sum = 0; i < sizeof(dat); i++)
640 sum += dat[i];
641 if (sum)
642 printk(KERN_WARNING "seeprom: bad checksum.\n");
643 }
644 }
645 memcpy(addr, &dat[4 + 6 * ch], 6);
646 return 0;
647}
648#endif /* CONFIG_PCI */
649
650extern void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on));
651static void __init rbtx4938_spi_setup(void)
652{
653 /* set SPI_SEL */
654 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
655 /* chip selects for SPI devices */
656 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
657 tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
658 txx9_spi_init(TX4938_SPI_REG, rbtx4938_spi_cs_func);
659}
660
661static struct resource rbtx4938_fpga_resource;
662
663static char pcode_str[8];
664static struct resource tx4938_reg_resource = {
665 pcode_str, TX4938_REG_BASE, TX4938_REG_BASE+TX4938_REG_SIZE, IORESOURCE_MEM
666};
667
668void __init tx4938_board_setup(void)
669{
670 int i;
671 unsigned long divmode;
672 int cpuclk = 0;
673 unsigned long pcode = TX4938_REV_PCODE();
674
675 ioport_resource.start = 0x1000;
676 ioport_resource.end = 0xffffffff;
677 iomem_resource.start = 0x1000;
678 iomem_resource.end = 0xffffffff; /* expand to 4GB */
679
680 sprintf(pcode_str, "TX%lx", pcode);
681 /* SDRAMC,EBUSC are configured by PROM */
682 for (i = 0; i < 8; i++) {
683 if (!(tx4938_ebuscptr->cr[i] & 0x8))
684 continue; /* disabled */
685 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
686 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
687 }
688
689 /* clocks */
690 if (txx9_master_clock) {
691 /* calculate gbus_clock and cpu_clock from master_clock */
692 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
693 switch (divmode) {
694 case TX4938_CCFG_DIVMODE_8:
695 case TX4938_CCFG_DIVMODE_10:
696 case TX4938_CCFG_DIVMODE_12:
697 case TX4938_CCFG_DIVMODE_16:
698 case TX4938_CCFG_DIVMODE_18:
699 txx9_gbus_clock = txx9_master_clock * 4; break;
700 default:
701 txx9_gbus_clock = txx9_master_clock;
702 }
703 switch (divmode) {
704 case TX4938_CCFG_DIVMODE_2:
705 case TX4938_CCFG_DIVMODE_8:
706 cpuclk = txx9_gbus_clock * 2; break;
707 case TX4938_CCFG_DIVMODE_2_5:
708 case TX4938_CCFG_DIVMODE_10:
709 cpuclk = txx9_gbus_clock * 5 / 2; break;
710 case TX4938_CCFG_DIVMODE_3:
711 case TX4938_CCFG_DIVMODE_12:
712 cpuclk = txx9_gbus_clock * 3; break;
713 case TX4938_CCFG_DIVMODE_4:
714 case TX4938_CCFG_DIVMODE_16:
715 cpuclk = txx9_gbus_clock * 4; break;
716 case TX4938_CCFG_DIVMODE_4_5:
717 case TX4938_CCFG_DIVMODE_18:
718 cpuclk = txx9_gbus_clock * 9 / 2; break;
719 }
720 txx9_cpu_clock = cpuclk;
721 } else {
722 if (txx9_cpu_clock == 0) {
723 txx9_cpu_clock = 300000000; /* 300MHz */
724 }
725 /* calculate gbus_clock and master_clock from cpu_clock */
726 cpuclk = txx9_cpu_clock;
727 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
728 switch (divmode) {
729 case TX4938_CCFG_DIVMODE_2:
730 case TX4938_CCFG_DIVMODE_8:
731 txx9_gbus_clock = cpuclk / 2; break;
732 case TX4938_CCFG_DIVMODE_2_5:
733 case TX4938_CCFG_DIVMODE_10:
734 txx9_gbus_clock = cpuclk * 2 / 5; break;
735 case TX4938_CCFG_DIVMODE_3:
736 case TX4938_CCFG_DIVMODE_12:
737 txx9_gbus_clock = cpuclk / 3; break;
738 case TX4938_CCFG_DIVMODE_4:
739 case TX4938_CCFG_DIVMODE_16:
740 txx9_gbus_clock = cpuclk / 4; break;
741 case TX4938_CCFG_DIVMODE_4_5:
742 case TX4938_CCFG_DIVMODE_18:
743 txx9_gbus_clock = cpuclk * 2 / 9; break;
744 }
745 switch (divmode) {
746 case TX4938_CCFG_DIVMODE_8:
747 case TX4938_CCFG_DIVMODE_10:
748 case TX4938_CCFG_DIVMODE_12:
749 case TX4938_CCFG_DIVMODE_16:
750 case TX4938_CCFG_DIVMODE_18:
751 txx9_master_clock = txx9_gbus_clock / 4; break;
752 default:
753 txx9_master_clock = txx9_gbus_clock;
754 }
755 }
756 /* change default value to udelay/mdelay take reasonable time */
757 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
758
759 /* CCFG */
760 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
761 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
762 /* clear PCIC1 reset */
763 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
764 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
765
766 /* enable Timeout BusError */
767 if (tx4938_ccfg_toeon)
768 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
769
770 /* DMA selection */
771 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
772
773 /* Use external clock for external arbiter */
774 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
775 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
776
777 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
778 pcode_str,
779 cpuclk / 1000000, txx9_master_clock / 1000000,
780 (unsigned long)tx4938_ccfgptr->crir,
781 tx4938_ccfgptr->ccfg,
782 tx4938_ccfgptr->pcfg);
783
784 printk("%s SDRAMC --", pcode_str);
785 for (i = 0; i < 4; i++) {
786 unsigned long long cr = tx4938_sdramcptr->cr[i];
787 unsigned long ram_base, ram_size;
788 if (!((unsigned long)cr & 0x00000400))
789 continue; /* disabled */
790 ram_base = (unsigned long)(cr >> 49) << 21;
791 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
792 if (ram_base >= 0x20000000)
793 continue; /* high memory (ignore) */
794 printk(" CR%d:%016Lx", i, cr);
795 txboard_add_phys_region(ram_base, ram_size);
796 }
797 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
798
799 /* SRAM */
800 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
801 unsigned int size = 0x800;
802 unsigned long base =
803 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
804 txboard_add_phys_region(base, size);
805 }
806
807 /* IRC */
808 /* disable interrupt control */
809 tx4938_ircptr->cer = 0;
810
811 /* TMR */
812 /* disable all timers */
813 for (i = 0; i < TX4938_NR_TMR; i++) {
814 tx4938_tmrptr(i)->tcr = 0x00000020;
815 tx4938_tmrptr(i)->tisr = 0;
816 tx4938_tmrptr(i)->cpra = 0xffffffff;
817 tx4938_tmrptr(i)->itmr = 0;
818 tx4938_tmrptr(i)->ccdr = 0;
819 tx4938_tmrptr(i)->pgmr = 0;
820 }
821
822 /* enable DMA */
823 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
824 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
825
826 /* PIO */
827 tx4938_pioptr->maskcpu = 0;
828 tx4938_pioptr->maskext = 0;
829
830 /* TX4938 internal registers */
831 if (request_resource(&iomem_resource, &tx4938_reg_resource))
832 printk("request resource for internal registers failed\n");
833}
834
835#ifdef CONFIG_PCI
836static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
837{
838 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
839 unsigned long g2pstatus = pcicptr->g2pstatus;
840 unsigned long pcicstatus = pcicptr->pcicstatus;
841 static struct {
842 unsigned long flag;
843 const char *str;
844 } pcistat_tbl[] = {
845 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
846 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
847 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
848 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
849 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
850 { PCI_STATUS_PARITY, "MasterParityError" },
851 }, g2pstat_tbl[] = {
852 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
853 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
854 }, pcicstat_tbl[] = {
855 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
856 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
857 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
858 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
859 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
860 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
861 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
862 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
863 };
864 int i;
865
866 printk("pcistat:%04x(", pcistatus);
867 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
868 if (pcistatus & pcistat_tbl[i].flag)
869 printk("%s ", pcistat_tbl[i].str);
870 printk("), g2pstatus:%08lx(", g2pstatus);
871 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
872 if (g2pstatus & g2pstat_tbl[i].flag)
873 printk("%s ", g2pstat_tbl[i].str);
874 printk("), pcicstatus:%08lx(", pcicstatus);
875 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
876 if (pcicstatus & pcicstat_tbl[i].flag)
877 printk("%s ", pcicstat_tbl[i].str);
878 printk(")\n");
879}
880
881void tx4938_report_pcic_status(void)
882{
883 int i;
884 struct tx4938_pcic_reg *pcicptr;
885 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
886 tx4938_report_pcic_status1(pcicptr);
887}
888
889#endif /* CONFIG_PCI */
890
891/* We use onchip r4k counter or TMR timer as our system wide timer
892 * interrupt running at 100HZ. */
893
894extern void __init rtc_rx5c348_init(int chipid);
895void __init rbtx4938_time_init(void)
896{
897 rtc_rx5c348_init(RBTX4938_SRTC_CHIPID);
898 mips_hpt_frequency = txx9_cpu_clock / 2;
899}
900
901void __init toshiba_rbtx4938_setup(void)
902{
903 unsigned long long pcfg;
904 char *argptr;
905
906 iomem_resource.end = 0xffffffff; /* 4GB */
907
908 if (txx9_master_clock == 0)
909 txx9_master_clock = 25000000; /* 25MHz */
910 tx4938_board_setup();
911 /* setup irq stuff */
912 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000); /* irq trigger */
913 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000); /* irq trigger */
914 /* setup serial stuff */
915 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
916 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
917
918#ifndef CONFIG_PCI
919 set_io_port_base(RBTX4938_ETHER_BASE);
920#endif
921
922#ifdef CONFIG_SERIAL_TXX9
923 {
924 extern int early_serial_txx9_setup(struct uart_port *port);
925 int i;
926 struct uart_port req;
927 for(i = 0; i < 2; i++) {
928 memset(&req, 0, sizeof(req));
929 req.line = i;
930 req.iotype = UPIO_MEM;
931 req.membase = (char *)(0xff1ff300 + i * 0x100);
932 req.mapbase = 0xff1ff300 + i * 0x100;
933 req.irq = 32 + i;
934 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
935 req.uartclk = 50000000;
936 early_serial_txx9_setup(&req);
937 }
938 }
939#ifdef CONFIG_SERIAL_TXX9_CONSOLE
940 argptr = prom_getcmdline();
941 if (strstr(argptr, "console=") == NULL) {
942 strcat(argptr, " console=ttyS0,38400");
943 }
944#endif
945#endif
946
947#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
948 printk("PIOSEL: disabling both ata and nand selection\n");
949 local_irq_disable();
950 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
951#endif
952
953#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
954 printk("PIOSEL: enabling nand selection\n");
955 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
956 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
957#endif
958
959#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
960 printk("PIOSEL: enabling ata selection\n");
961 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
962 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
963#endif
964
965#ifdef CONFIG_IP_PNP
966 argptr = prom_getcmdline();
967 if (strstr(argptr, "ip=") == NULL) {
968 strcat(argptr, " ip=any");
969 }
970#endif
971
972
973#ifdef CONFIG_FB
974 {
975 conswitchp = &dummy_con;
976 }
977#endif
978
979 rbtx4938_spi_setup();
980 pcfg = tx4938_ccfgptr->pcfg; /* updated */
981 /* fixup piosel */
982 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
983 TX4938_PCFG_ATA_SEL) {
984 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
985 }
986 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
987 TX4938_PCFG_NDF_SEL) {
988 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
989 }
990 else {
991 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
992 }
993
994 rbtx4938_fpga_resource.name = "FPGA Registers";
995 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
996 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
997 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
998 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
999 printk("request resource for fpga failed\n");
1000
1001 /* disable all OnBoard I/O interrupts */
1002 *rbtx4938_imask_ptr = 0;
1003
1004 _machine_restart = rbtx4938_machine_restart;
1005 _machine_halt = rbtx4938_machine_halt;
1006 _machine_power_off = rbtx4938_machine_power_off;
1007
1008 *rbtx4938_led_ptr = 0xff;
1009 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
1010 printk(" DIPSW:%02x,%02x\n",
1011 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
1012}
1013
1014#ifdef CONFIG_PROC_FS
1015extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid);
1016static int __init tx4938_spi_proc_setup(void)
1017{
1018 struct proc_dir_entry *tx4938_spi_eeprom_dir;
1019
1020 tx4938_spi_eeprom_dir = proc_mkdir("spi_eeprom", 0);
1021
1022 if (!tx4938_spi_eeprom_dir)
1023 return -ENOMEM;
1024
1025 /* don't allow user access to RBTX4938_SEEPROM1_CHIPID
1026 * as it contains eth0 and eth1 MAC addresses
1027 */
1028 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM2_CHIPID);
1029 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM3_CHIPID);
1030
1031 return 0;
1032}
1033
1034__initcall(tx4938_spi_proc_setup);
1035#endif
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c
new file mode 100644
index 000000000000..951a208ee9b3
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c
@@ -0,0 +1,219 @@
1/*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/config.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/proc_fs.h>
16#include <linux/spinlock.h>
17#include <asm/tx4938/spi.h>
18#include <asm/tx4938/tx4938.h>
19
20/* ATMEL 250x0 instructions */
21#define ATMEL_WREN 0x06
22#define ATMEL_WRDI 0x04
23#define ATMEL_RDSR 0x05
24#define ATMEL_WRSR 0x01
25#define ATMEL_READ 0x03
26#define ATMEL_WRITE 0x02
27
28#define ATMEL_SR_BSY 0x01
29#define ATMEL_SR_WEN 0x02
30#define ATMEL_SR_BP0 0x04
31#define ATMEL_SR_BP1 0x08
32
33DEFINE_SPINLOCK(spi_eeprom_lock);
34
35static struct spi_dev_desc seeprom_dev_desc = {
36 .baud = 1500000, /* 1.5Mbps */
37 .tcss = 1,
38 .tcsh = 1,
39 .tcsr = 1,
40 .byteorder = 1, /* MSB-First */
41 .polarity = 0, /* High-Active */
42 .phase = 0, /* Sample-Then-Shift */
43
44};
45static inline int
46spi_eeprom_io(int chipid,
47 unsigned char **inbufs, unsigned int *incounts,
48 unsigned char **outbufs, unsigned int *outcounts)
49{
50 return txx9_spi_io(chipid, &seeprom_dev_desc,
51 inbufs, incounts, outbufs, outcounts, 0);
52}
53
54int spi_eeprom_write_enable(int chipid, int enable)
55{
56 unsigned char inbuf[1];
57 unsigned char *inbufs[1];
58 unsigned int incounts[2];
59 unsigned long flags;
60 int stat;
61 inbuf[0] = enable ? ATMEL_WREN : ATMEL_WRDI;
62 inbufs[0] = inbuf;
63 incounts[0] = sizeof(inbuf);
64 incounts[1] = 0;
65 spin_lock_irqsave(&spi_eeprom_lock, flags);
66 stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL);
67 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
68 return stat;
69}
70
71static int spi_eeprom_read_status_nolock(int chipid)
72{
73 unsigned char inbuf[2], outbuf[2];
74 unsigned char *inbufs[1], *outbufs[1];
75 unsigned int incounts[2], outcounts[2];
76 int stat;
77 inbuf[0] = ATMEL_RDSR;
78 inbuf[1] = 0;
79 inbufs[0] = inbuf;
80 incounts[0] = sizeof(inbuf);
81 incounts[1] = 0;
82 outbufs[0] = outbuf;
83 outcounts[0] = sizeof(outbuf);
84 outcounts[1] = 0;
85 stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts);
86 if (stat < 0)
87 return stat;
88 return outbuf[1];
89}
90
91int spi_eeprom_read_status(int chipid)
92{
93 unsigned long flags;
94 int stat;
95 spin_lock_irqsave(&spi_eeprom_lock, flags);
96 stat = spi_eeprom_read_status_nolock(chipid);
97 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
98 return stat;
99}
100
101int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len)
102{
103 unsigned char inbuf[2];
104 unsigned char *inbufs[2], *outbufs[2];
105 unsigned int incounts[2], outcounts[3];
106 unsigned long flags;
107 int stat;
108 inbuf[0] = ATMEL_READ;
109 inbuf[1] = address;
110 inbufs[0] = inbuf;
111 inbufs[1] = NULL;
112 incounts[0] = sizeof(inbuf);
113 incounts[1] = 0;
114 outbufs[0] = NULL;
115 outbufs[1] = buf;
116 outcounts[0] = 2;
117 outcounts[1] = len;
118 outcounts[2] = 0;
119 spin_lock_irqsave(&spi_eeprom_lock, flags);
120 stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts);
121 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
122 return stat;
123}
124
125int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len)
126{
127 unsigned char inbuf[2];
128 unsigned char *inbufs[2];
129 unsigned int incounts[3];
130 unsigned long flags;
131 int i, stat;
132
133 if (address / 8 != (address + len - 1) / 8)
134 return -EINVAL;
135 stat = spi_eeprom_write_enable(chipid, 1);
136 if (stat < 0)
137 return stat;
138 stat = spi_eeprom_read_status(chipid);
139 if (stat < 0)
140 return stat;
141 if (!(stat & ATMEL_SR_WEN))
142 return -EPERM;
143
144 inbuf[0] = ATMEL_WRITE;
145 inbuf[1] = address;
146 inbufs[0] = inbuf;
147 inbufs[1] = buf;
148 incounts[0] = sizeof(inbuf);
149 incounts[1] = len;
150 incounts[2] = 0;
151 spin_lock_irqsave(&spi_eeprom_lock, flags);
152 stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL);
153 if (stat < 0)
154 goto unlock_return;
155
156 /* write start. max 10ms */
157 for (i = 10; i > 0; i--) {
158 int stat = spi_eeprom_read_status_nolock(chipid);
159 if (stat < 0)
160 goto unlock_return;
161 if (!(stat & ATMEL_SR_BSY))
162 break;
163 mdelay(1);
164 }
165 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
166 if (i == 0)
167 return -EIO;
168 return len;
169 unlock_return:
170 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
171 return stat;
172}
173
174#ifdef CONFIG_PROC_FS
175#define MAX_SIZE 0x80 /* for ATMEL 25010 */
176static int spi_eeprom_read_proc(char *page, char **start, off_t off,
177 int count, int *eof, void *data)
178{
179 unsigned int size = MAX_SIZE;
180 if (spi_eeprom_read((int)data, 0, (unsigned char *)page, size) < 0)
181 size = 0;
182 return size;
183}
184
185static int spi_eeprom_write_proc(struct file *file, const char *buffer,
186 unsigned long count, void *data)
187{
188 unsigned int size = MAX_SIZE;
189 int i;
190 if (file->f_pos >= size)
191 return -EIO;
192 if (file->f_pos + count > size)
193 count = size - file->f_pos;
194 for (i = 0; i < count; i += 8) {
195 int len = count - i < 8 ? count - i : 8;
196 if (spi_eeprom_write((int)data, file->f_pos,
197 (unsigned char *)buffer, len) < 0) {
198 count = -EIO;
199 break;
200 }
201 buffer += len;
202 file->f_pos += len;
203 }
204 return count;
205}
206
207__init void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid)
208{
209 struct proc_dir_entry *entry;
210 char name[128];
211 sprintf(name, "seeprom-%d", chipid);
212 entry = create_proc_entry(name, 0600, dir);
213 if (entry) {
214 entry->read_proc = spi_eeprom_read_proc;
215 entry->write_proc = spi_eeprom_write_proc;
216 entry->data = (void *)chipid;
217 }
218}
219#endif /* CONFIG_PROC_FS */
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
new file mode 100644
index 000000000000..fae3136f462d
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
@@ -0,0 +1,159 @@
1/*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/errno.h>
15#include <linux/interrupt.h>
16#include <linux/module.h>
17#include <linux/sched.h>
18#include <linux/spinlock.h>
19#include <linux/wait.h>
20#include <asm/tx4938/spi.h>
21#include <asm/tx4938/tx4938.h>
22
23static int (*txx9_spi_cs_func)(int chipid, int on);
24static DEFINE_SPINLOCK(txx9_spi_lock);
25
26extern unsigned int txx9_gbus_clock;
27
28#define SPI_FIFO_SIZE 4
29
30void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on))
31{
32 txx9_spi_cs_func = cs_func;
33 /* enter config mode */
34 tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
35}
36
37static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait);
38static void txx9_spi_interrupt(int irq, void *dev_id, struct pt_regs *regs)
39{
40 /* disable rx intr */
41 tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE;
42 wake_up(&txx9_spi_wait);
43}
44static struct irqaction txx9_spi_action = {
45 txx9_spi_interrupt, 0, 0, "spi", NULL, NULL,
46};
47
48void __init txx9_spi_irqinit(int irc_irq)
49{
50 setup_irq(irc_irq, &txx9_spi_action);
51}
52
53int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
54 unsigned char **inbufs, unsigned int *incounts,
55 unsigned char **outbufs, unsigned int *outcounts,
56 int cansleep)
57{
58 unsigned int incount, outcount;
59 unsigned char *inp, *outp;
60 int ret;
61 unsigned long flags;
62
63 spin_lock_irqsave(&txx9_spi_lock, flags);
64 if ((tx4938_spiptr->mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE) {
65 spin_unlock_irqrestore(&txx9_spi_lock, flags);
66 return -EBUSY;
67 }
68 /* enter config mode */
69 tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
70 tx4938_spiptr->cr0 =
71 (desc->byteorder ? TXx9_SPCR0_SBOS : 0) |
72 (desc->polarity ? TXx9_SPCR0_SPOL : 0) |
73 (desc->phase ? TXx9_SPCR0_SPHA : 0) |
74 0x08;
75 tx4938_spiptr->cr1 =
76 (((TXX9_IMCLK + desc->baud) / (2 * desc->baud) - 1) << 8) |
77 0x08 /* 8 bit only */;
78 /* enter active mode */
79 tx4938_spiptr->mcr = TXx9_SPMCR_ACTIVE;
80 spin_unlock_irqrestore(&txx9_spi_lock, flags);
81
82 /* CS ON */
83 if ((ret = txx9_spi_cs_func(chipid, 1)) < 0) {
84 spin_unlock_irqrestore(&txx9_spi_lock, flags);
85 return ret;
86 }
87 udelay(desc->tcss);
88
89 /* do scatter IO */
90 inp = inbufs ? *inbufs : NULL;
91 outp = outbufs ? *outbufs : NULL;
92 incount = 0;
93 outcount = 0;
94 while (1) {
95 unsigned char data;
96 unsigned int count;
97 int i;
98 if (!incount) {
99 incount = incounts ? *incounts++ : 0;
100 inp = (incount && inbufs) ? *inbufs++ : NULL;
101 }
102 if (!outcount) {
103 outcount = outcounts ? *outcounts++ : 0;
104 outp = (outcount && outbufs) ? *outbufs++ : NULL;
105 }
106 if (!inp && !outp)
107 break;
108 count = SPI_FIFO_SIZE;
109 if (incount)
110 count = min(count, incount);
111 if (outcount)
112 count = min(count, outcount);
113
114 /* now tx must be idle... */
115 while (!(tx4938_spiptr->sr & TXx9_SPSR_SIDLE))
116 ;
117
118 tx4938_spiptr->cr0 =
119 (tx4938_spiptr->cr0 & ~TXx9_SPCR0_RXIFL_MASK) |
120 ((count - 1) << 12);
121 if (cansleep) {
122 /* enable rx intr */
123 tx4938_spiptr->cr0 |= TXx9_SPCR0_RBSIE;
124 }
125 /* send */
126 for (i = 0; i < count; i++)
127 tx4938_spiptr->dr = inp ? *inp++ : 0;
128 /* wait all rx data */
129 if (cansleep) {
130 wait_event(txx9_spi_wait,
131 tx4938_spiptr->sr & TXx9_SPSR_SRRDY);
132 } else {
133 while (!(tx4938_spiptr->sr & TXx9_SPSR_RBSI))
134 ;
135 }
136 /* receive */
137 for (i = 0; i < count; i++) {
138 data = tx4938_spiptr->dr;
139 if (outp)
140 *outp++ = data;
141 }
142 if (incount)
143 incount -= count;
144 if (outcount)
145 outcount -= count;
146 }
147
148 /* CS OFF */
149 udelay(desc->tcsh);
150 txx9_spi_cs_func(chipid, 0);
151 udelay(desc->tcsr);
152
153 spin_lock_irqsave(&txx9_spi_lock, flags);
154 /* enter config mode */
155 tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
156 spin_unlock_irqrestore(&txx9_spi_lock, flags);
157
158 return 0;
159}
diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig
new file mode 100644
index 000000000000..a7add16c9aa4
--- /dev/null
+++ b/arch/mips/vr41xx/Kconfig
@@ -0,0 +1,88 @@
1config CASIO_E55
2 bool "Support for CASIO CASSIOPEIA E-10/15/55/65"
3 depends on MACH_VR41XX
4 select DMA_NONCOHERENT
5 select IRQ_CPU
6 select ISA
7 select SYS_SUPPORTS_LITTLE_ENDIAN
8
9config IBM_WORKPAD
10 bool "Support for IBM WorkPad z50"
11 depends on MACH_VR41XX
12 select DMA_NONCOHERENT
13 select IRQ_CPU
14 select ISA
15 select SYS_SUPPORTS_LITTLE_ENDIAN
16
17config NEC_CMBVR4133
18 bool "Support for NEC CMB-VR4133"
19 depends on MACH_VR41XX
20 select CPU_VR41XX
21 select DMA_NONCOHERENT
22 select IRQ_CPU
23 select HW_HAS_PCI
24
25config ROCKHOPPER
26 bool "Support for Rockhopper baseboard"
27 depends on NEC_CMBVR4133
28 select I8259
29 select HAVE_STD_PC_SERIAL_PORT
30
31config TANBAC_TB022X
32 bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
33 depends on MACH_VR41XX
34 select DMA_NONCOHERENT
35 select HW_HAS_PCI
36 select IRQ_CPU
37 select SYS_SUPPORTS_LITTLE_ENDIAN
38 help
39 The TANBAC VR4131 multichip module(TB0225) and
40 the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms
41 manufactured by TANBAC.
42 Please refer to <http://www.tanbac.co.jp/>
43 about VR4131 multichip module and VR4131DIMM.
44
45config TANBAC_TB0226
46 bool "Support for TANBAC Mbase(TB0226)"
47 depends on TANBAC_TB022X
48 select GPIO_VR41XX
49 help
50 The TANBAC Mbase(TB0226) is a MIPS-based platform
51 manufactured by TANBAC.
52 Please refer to <http://www.tanbac.co.jp/> about Mbase.
53
54config TANBAC_TB0287
55 bool "Support for TANBAC Mini-ITX DIMM base(TB0287)"
56 depends on TANBAC_TB022X
57 help
58 The TANBAC Mini-ITX DIMM base(TB0287) is a MIPS-based platform
59 manufactured by TANBAC.
60 Please refer to <http://www.tanbac.co.jp/> about Mini-ITX DIMM base.
61
62config VICTOR_MPC30X
63 bool "Support for Victor MP-C303/304"
64 depends on MACH_VR41XX
65 select DMA_NONCOHERENT
66 select HW_HAS_PCI
67 select IRQ_CPU
68 select SYS_SUPPORTS_LITTLE_ENDIAN
69
70config ZAO_CAPCELLA
71 bool "Support for ZAO Networks Capcella"
72 depends on MACH_VR41XX
73 select DMA_NONCOHERENT
74 select HW_HAS_PCI
75 select IRQ_CPU
76 select SYS_SUPPORTS_LITTLE_ENDIAN
77
78config PCI_VR41XX
79 bool "Add PCI control unit support of NEC VR4100 series"
80 depends on MACH_VR41XX && HW_HAS_PCI
81 default y
82 select PCI
83
84config VRC4173
85 tristate "Add NEC VRC4173 companion chip support"
86 depends on MACH_VR41XX && PCI_VR41XX
87 help
88 The NEC VRC4173 is a companion chip for NEC VR4122/VR4131.
diff --git a/arch/mips/vr41xx/common/cmu.c b/arch/mips/vr41xx/common/cmu.c
index fcd3cb8cdd9d..d758e432961b 100644
--- a/arch/mips/vr41xx/common/cmu.c
+++ b/arch/mips/vr41xx/common/cmu.c
@@ -69,7 +69,7 @@
69 69
70static void __iomem *cmu_base; 70static void __iomem *cmu_base;
71static uint16_t cmuclkmsk, cmuclkmsk2; 71static uint16_t cmuclkmsk, cmuclkmsk2;
72static spinlock_t cmu_lock; 72static DEFINE_SPINLOCK(cmu_lock);
73 73
74#define cmu_read(offset) readw(cmu_base + (offset)) 74#define cmu_read(offset) readw(cmu_base + (offset))
75#define cmu_write(offset, value) writew((value), cmu_base + (offset)) 75#define cmu_write(offset, value) writew((value), cmu_base + (offset))
diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c
index e03be896cbc4..578f6496ffd4 100644
--- a/arch/mips/vr41xx/common/init.c
+++ b/arch/mips/vr41xx/common/init.c
@@ -58,6 +58,14 @@ static void __init timer_init(void)
58 board_timer_setup = setup_timer_irq; 58 board_timer_setup = setup_timer_irq;
59} 59}
60 60
61void __init plat_setup(void)
62{
63 vr41xx_calculate_clock_frequency();
64
65 timer_init();
66 iomem_resource_init();
67}
68
61void __init prom_init(void) 69void __init prom_init(void)
62{ 70{
63 int argc, i; 71 int argc, i;
@@ -71,12 +79,6 @@ void __init prom_init(void)
71 if (i < (argc - 1)) 79 if (i < (argc - 1))
72 strcat(arcs_cmdline, " "); 80 strcat(arcs_cmdline, " ");
73 } 81 }
74
75 vr41xx_calculate_clock_frequency();
76
77 timer_init();
78
79 iomem_resource_init();
80} 82}
81 83
82unsigned long __init prom_free_prom_memory (void) 84unsigned long __init prom_free_prom_memory (void)
diff --git a/arch/mips/vr41xx/common/vrc4173.c b/arch/mips/vr41xx/common/vrc4173.c
index ba58764ef8ea..462a9af30eef 100644
--- a/arch/mips/vr41xx/common/vrc4173.c
+++ b/arch/mips/vr41xx/common/vrc4173.c
@@ -81,8 +81,8 @@ EXPORT_SYMBOL(vrc4173_io_offset);
81static int vrc4173_initialized; 81static int vrc4173_initialized;
82static uint16_t vrc4173_cmuclkmsk; 82static uint16_t vrc4173_cmuclkmsk;
83static uint16_t vrc4173_selectreg; 83static uint16_t vrc4173_selectreg;
84static spinlock_t vrc4173_cmu_lock; 84static DEFINE_SPINLOCK(vrc4173_cmu_lock);
85static spinlock_t vrc4173_giu_lock; 85static DEFINE_SPINLOCK(vrc4173_giu_lock);
86 86
87static inline void set_cmusrst(uint16_t val) 87static inline void set_cmusrst(uint16_t val)
88{ 88{
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/setup.c b/arch/mips/vr41xx/nec-cmbvr4133/setup.c
index db686ce42e85..53272a5c3cbe 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/setup.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/setup.c
@@ -56,7 +56,7 @@ static struct mtd_partition cmbvr4133_mtd_parts[] = {
56 56
57extern void i8259_init(void); 57extern void i8259_init(void);
58 58
59static int __init nec_cmbvr4133_setup(void) 59static void __init nec_cmbvr4133_setup(void)
60{ 60{
61#ifdef CONFIG_ROCKHOPPER 61#ifdef CONFIG_ROCKHOPPER
62 extern void disable_pcnet(void); 62 extern void disable_pcnet(void);
@@ -90,7 +90,4 @@ static int __init nec_cmbvr4133_setup(void)
90#ifdef CONFIG_ROCKHOPPER 90#ifdef CONFIG_ROCKHOPPER
91 i8259_init(); 91 i8259_init();
92#endif 92#endif
93 return 0;
94} 93}
95
96early_initcall(nec_cmbvr4133_setup);
diff --git a/drivers/char/lcd.c b/drivers/char/lcd.c
index b77161146144..29963d8be667 100644
--- a/drivers/char/lcd.c
+++ b/drivers/char/lcd.c
@@ -575,8 +575,8 @@ static inline int button_pressed(void)
575 575
576static int lcd_waiters = 0; 576static int lcd_waiters = 0;
577 577
578static long lcd_read(struct inode *inode, struct file *file, char *buf, 578static ssize_t lcd_read(struct file *file, char *buf,
579 unsigned long count) 579 size_t count, loff_t *ofs)
580{ 580{
581 long buttons_now; 581 long buttons_now;
582 582
diff --git a/drivers/char/lcd.h b/drivers/char/lcd.h
index 878a95280e87..a8d4ae737158 100644
--- a/drivers/char/lcd.h
+++ b/drivers/char/lcd.h
@@ -22,7 +22,7 @@ static int timeout(volatile unsigned long);
22#define MAX_IDLE_TIME 120 22#define MAX_IDLE_TIME 120
23 23
24struct lcd_display { 24struct lcd_display {
25 unsigned long buttons; 25 unsigned buttons;
26 int size1; 26 int size1;
27 int size2; 27 int size2;
28 unsigned char line1[LCD_CHARS_PER_LINE]; 28 unsigned char line1[LCD_CHARS_PER_LINE];
diff --git a/drivers/char/qtronix.c b/drivers/char/qtronix.c
index 40a3cf62e1a8..601d09baf9d7 100644
--- a/drivers/char/qtronix.c
+++ b/drivers/char/qtronix.c
@@ -591,6 +591,11 @@ static int __init psaux_init(void)
591 return retval; 591 return retval;
592 592
593 queue = (struct aux_queue *) kmalloc(sizeof(*queue), GFP_KERNEL); 593 queue = (struct aux_queue *) kmalloc(sizeof(*queue), GFP_KERNEL);
594 if (!queue) {
595 misc_deregister(&psaux_mouse);
596 return -ENOMEM;
597 }
598
594 memset(queue, 0, sizeof(*queue)); 599 memset(queue, 0, sizeof(*queue));
595 queue->head = queue->tail = 0; 600 queue->head = queue->tail = 0;
596 init_waitqueue_head(&queue->proc_list); 601 init_waitqueue_head(&queue->proc_list);
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 1cadd2c3cadd..a737886e39d1 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -778,6 +778,35 @@ config BLK_DEV_IDE_PMAC_BLINK
778 This option enables the use of the sleep LED as a hard drive 778 This option enables the use of the sleep LED as a hard drive
779 activity LED. 779 activity LED.
780 780
781config BLK_DEV_IDE_AU1XXX
782 bool "IDE for AMD Alchemy Au1200"
783 depends on SOC_AU1200
784choice
785 prompt "IDE Mode for AMD Alchemy Au1200"
786 default CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
787 depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX
788
789config BLK_DEV_IDE_AU1XXX_PIO_DBDMA
790 bool "PIO+DbDMA IDE for AMD Alchemy Au1200"
791
792config BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
793 bool "MDMA2+DbDMA IDE for AMD Alchemy Au1200"
794 depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX
795endchoice
796
797config BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
798 bool "Enable burstable Mode on DbDMA"
799 default false
800 depends BLK_DEV_IDE_AU1XXX
801 help
802 This option enable the burstable Flag on DbDMA controller
803 (cf. "AMD Alchemy 'Au1200' Processor Data Book - PRELIMINARY").
804
805config BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ
806 int "Maximum transfer size (KB) per request (up to 128)"
807 default "128"
808 depends BLK_DEV_IDE_AU1XXX
809
781config IDE_ARM 810config IDE_ARM
782 def_bool ARM && (ARCH_A5K || ARCH_CLPS7500 || ARCH_RPC || ARCH_SHARK) 811 def_bool ARM && (ARCH_A5K || ARCH_CLPS7500 || ARCH_RPC || ARCH_SHARK)
783 812
@@ -1013,7 +1042,7 @@ config BLK_DEV_UMC8672
1013endif 1042endif
1014 1043
1015config BLK_DEV_IDEDMA 1044config BLK_DEV_IDEDMA
1016 def_bool BLK_DEV_IDEDMA_PCI || BLK_DEV_IDEDMA_PMAC || BLK_DEV_IDEDMA_ICS 1045 def_bool BLK_DEV_IDEDMA_PCI || BLK_DEV_IDEDMA_PMAC || BLK_DEV_IDEDMA_ICS || BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
1017 1046
1018config IDEDMA_IVB 1047config IDEDMA_IVB
1019 bool "IGNORE word93 Validation BITS" 1048 bool "IGNORE word93 Validation BITS"
diff --git a/drivers/ide/ide-proc.c b/drivers/ide/ide-proc.c
index 4063d2c34e3d..84665e2ba3c8 100644
--- a/drivers/ide/ide-proc.c
+++ b/drivers/ide/ide-proc.c
@@ -64,6 +64,7 @@ static int proc_ide_read_imodel
64 case ide_cy82c693: name = "cy82c693"; break; 64 case ide_cy82c693: name = "cy82c693"; break;
65 case ide_4drives: name = "4drives"; break; 65 case ide_4drives: name = "4drives"; break;
66 case ide_pmac: name = "mac-io"; break; 66 case ide_pmac: name = "mac-io"; break;
67 case ide_au1xxx: name = "au1xxx"; break;
67 default: name = "(unknown)"; break; 68 default: name = "(unknown)"; break;
68 } 69 }
69 len = sprintf(page, "%s\n", name); 70 len = sprintf(page, "%s\n", name);
diff --git a/drivers/ide/mips/au1xxx-ide.c b/drivers/ide/mips/au1xxx-ide.c
new file mode 100644
index 000000000000..2b6327c576b9
--- /dev/null
+++ b/drivers/ide/mips/au1xxx-ide.c
@@ -0,0 +1,1250 @@
1/*
2 * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005
3 *
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
6 *
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
8 *
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
12 * version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
31 */
32#undef REALLY_SLOW_IO /* most systems can safely undef this */
33
34#include <linux/config.h> /* for CONFIG_BLK_DEV_IDEPCI */
35#include <linux/types.h>
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/delay.h>
39#include <linux/timer.h>
40#include <linux/mm.h>
41#include <linux/ioport.h>
42#include <linux/hdreg.h>
43#include <linux/init.h>
44#include <linux/ide.h>
45#include <linux/sysdev.h>
46
47#include <linux/dma-mapping.h>
48
49#include <asm/io.h>
50#include <asm/mach-au1x00/au1xxx.h>
51#include <asm/mach-au1x00/au1xxx_dbdma.h>
52
53#if CONFIG_PM
54#include <asm/mach-au1x00/au1xxx_pm.h>
55#endif
56
57#include <asm/mach-au1x00/au1xxx_ide.h>
58
59#define DRV_NAME "au1200-ide"
60#define DRV_VERSION "1.0"
61#define DRV_AUTHOR "AMD PCS / Pete Popov <ppopov@embeddedalley.com>"
62#define DRV_DESC "Au1200 IDE"
63
64static _auide_hwif auide_hwif;
65static spinlock_t ide_tune_drive_spin_lock = SPIN_LOCK_UNLOCKED;
66static spinlock_t ide_tune_chipset_spin_lock = SPIN_LOCK_UNLOCKED;
67static int dbdma_init_done = 0;
68
69/*
70 * local I/O functions
71 */
72u8 auide_inb(unsigned long port)
73{
74 return (au_readb(port));
75}
76
77u16 auide_inw(unsigned long port)
78{
79 return (au_readw(port));
80}
81
82u32 auide_inl(unsigned long port)
83{
84 return (au_readl(port));
85}
86
87void auide_insw(unsigned long port, void *addr, u32 count)
88{
89#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
90
91 _auide_hwif *ahwif = &auide_hwif;
92 chan_tab_t *ctp;
93 au1x_ddma_desc_t *dp;
94
95 if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
96 DDMA_FLAGS_NOIE)) {
97 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
98 return;
99 }
100 ctp = *((chan_tab_t **)ahwif->rx_chan);
101 dp = ctp->cur_ptr;
102 while (dp->dscr_cmd0 & DSCR_CMD0_V)
103 ;
104 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
105#else
106 while (count--)
107 {
108 *(u16 *)addr = au_readw(port);
109 addr +=2 ;
110 }
111#endif
112}
113
114void auide_insl(unsigned long port, void *addr, u32 count)
115{
116 while (count--)
117 {
118 *(u32 *)addr = au_readl(port);
119 /* NOTE: For IDE interfaces over PCMCIA,
120 * 32-bit access does not work
121 */
122 addr += 4;
123 }
124}
125
126void auide_outb(u8 addr, unsigned long port)
127{
128 return (au_writeb(addr, port));
129}
130
131void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
132{
133 return (au_writeb(addr, port));
134}
135
136void auide_outw(u16 addr, unsigned long port)
137{
138 return (au_writew(addr, port));
139}
140
141void auide_outl(u32 addr, unsigned long port)
142{
143 return (au_writel(addr, port));
144}
145
146void auide_outsw(unsigned long port, void *addr, u32 count)
147{
148#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
149 _auide_hwif *ahwif = &auide_hwif;
150 chan_tab_t *ctp;
151 au1x_ddma_desc_t *dp;
152
153 if(!put_source_flags(ahwif->tx_chan, (void*)addr,
154 count << 1, DDMA_FLAGS_NOIE)) {
155 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
156 return;
157 }
158 ctp = *((chan_tab_t **)ahwif->tx_chan);
159 dp = ctp->cur_ptr;
160 while (dp->dscr_cmd0 & DSCR_CMD0_V)
161 ;
162 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
163#else
164 while (count--)
165 {
166 au_writew(*(u16 *)addr, port);
167 addr += 2;
168 }
169#endif
170}
171
172void auide_outsl(unsigned long port, void *addr, u32 count)
173{
174 while (count--)
175 {
176 au_writel(*(u32 *)addr, port);
177 /* NOTE: For IDE interfaces over PCMCIA,
178 * 32-bit access does not work
179 */
180 addr += 4;
181 }
182}
183
184static void auide_tune_drive(ide_drive_t *drive, byte pio)
185{
186 int mem_sttime;
187 int mem_stcfg;
188 unsigned long flags;
189 u8 speed;
190
191 /* get the best pio mode for the drive */
192 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
193
194 printk("%s: setting Au1XXX IDE to PIO mode%d\n",
195 drive->name, pio);
196
197 spin_lock_irqsave(&ide_tune_drive_spin_lock, flags);
198
199 mem_sttime = 0;
200 mem_stcfg = au_readl(MEM_STCFG2);
201
202 /* set pio mode! */
203 switch(pio) {
204 case 0:
205 /* set timing parameters for RCS2# */
206 mem_sttime = SBC_IDE_PIO0_TWCS
207 | SBC_IDE_PIO0_TCSH
208 | SBC_IDE_PIO0_TCSOFF
209 | SBC_IDE_PIO0_TWP
210 | SBC_IDE_PIO0_TCSW
211 | SBC_IDE_PIO0_TPM
212 | SBC_IDE_PIO0_TA;
213 /* set configuration for RCS2# */
214 mem_stcfg |= TS_MASK;
215 mem_stcfg &= ~TCSOE_MASK;
216 mem_stcfg &= ~TOECS_MASK;
217 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
218
219 au_writel(mem_sttime,MEM_STTIME2);
220 au_writel(mem_stcfg,MEM_STCFG2);
221 break;
222
223 case 1:
224 /* set timing parameters for RCS2# */
225 mem_sttime = SBC_IDE_PIO1_TWCS
226 | SBC_IDE_PIO1_TCSH
227 | SBC_IDE_PIO1_TCSOFF
228 | SBC_IDE_PIO1_TWP
229 | SBC_IDE_PIO1_TCSW
230 | SBC_IDE_PIO1_TPM
231 | SBC_IDE_PIO1_TA;
232 /* set configuration for RCS2# */
233 mem_stcfg |= TS_MASK;
234 mem_stcfg &= ~TCSOE_MASK;
235 mem_stcfg &= ~TOECS_MASK;
236 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
237 break;
238
239 case 2:
240 /* set timing parameters for RCS2# */
241 mem_sttime = SBC_IDE_PIO2_TWCS
242 | SBC_IDE_PIO2_TCSH
243 | SBC_IDE_PIO2_TCSOFF
244 | SBC_IDE_PIO2_TWP
245 | SBC_IDE_PIO2_TCSW
246 | SBC_IDE_PIO2_TPM
247 | SBC_IDE_PIO2_TA;
248 /* set configuration for RCS2# */
249 mem_stcfg &= ~TS_MASK;
250 mem_stcfg &= ~TCSOE_MASK;
251 mem_stcfg &= ~TOECS_MASK;
252 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
253 break;
254
255 case 3:
256 /* set timing parameters for RCS2# */
257 mem_sttime = SBC_IDE_PIO3_TWCS
258 | SBC_IDE_PIO3_TCSH
259 | SBC_IDE_PIO3_TCSOFF
260 | SBC_IDE_PIO3_TWP
261 | SBC_IDE_PIO3_TCSW
262 | SBC_IDE_PIO3_TPM
263 | SBC_IDE_PIO3_TA;
264 /* set configuration for RCS2# */
265 mem_stcfg |= TS_MASK;
266 mem_stcfg &= ~TS_MASK;
267 mem_stcfg &= ~TCSOE_MASK;
268 mem_stcfg &= ~TOECS_MASK;
269 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
270
271 break;
272
273 case 4:
274 /* set timing parameters for RCS2# */
275 mem_sttime = SBC_IDE_PIO4_TWCS
276 | SBC_IDE_PIO4_TCSH
277 | SBC_IDE_PIO4_TCSOFF
278 | SBC_IDE_PIO4_TWP
279 | SBC_IDE_PIO4_TCSW
280 | SBC_IDE_PIO4_TPM
281 | SBC_IDE_PIO4_TA;
282 /* set configuration for RCS2# */
283 mem_stcfg &= ~TS_MASK;
284 mem_stcfg &= ~TCSOE_MASK;
285 mem_stcfg &= ~TOECS_MASK;
286 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
287 break;
288 }
289
290 au_writel(mem_sttime,MEM_STTIME2);
291 au_writel(mem_stcfg,MEM_STCFG2);
292
293 spin_unlock_irqrestore(&ide_tune_drive_spin_lock, flags);
294
295 speed = pio + XFER_PIO_0;
296 ide_config_drive_speed(drive, speed);
297}
298
299static int auide_tune_chipset (ide_drive_t *drive, u8 speed)
300{
301 u8 mode = 0;
302 int mem_sttime;
303 int mem_stcfg;
304 unsigned long flags;
305#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
306 struct hd_driveid *id = drive->id;
307
308 /*
309 * Now see what the current drive is capable of,
310 * selecting UDMA only if the mate said it was ok.
311 */
312 if (id && (id->capability & 1) && drive->autodma &&
313 !__ide_dma_bad_drive(drive)) {
314 if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) {
315 if (id->dma_mword & 4)
316 mode = XFER_MW_DMA_2;
317 else if (id->dma_mword & 2)
318 mode = XFER_MW_DMA_1;
319 else if (id->dma_mword & 1)
320 mode = XFER_MW_DMA_0;
321 }
322 }
323#endif
324
325 spin_lock_irqsave(&ide_tune_chipset_spin_lock, flags);
326
327 mem_sttime = 0;
328 mem_stcfg = au_readl(MEM_STCFG2);
329
330 switch(speed) {
331 case XFER_PIO_4:
332 case XFER_PIO_3:
333 case XFER_PIO_2:
334 case XFER_PIO_1:
335 case XFER_PIO_0:
336 auide_tune_drive(drive, (speed - XFER_PIO_0));
337 break;
338#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
339 case XFER_MW_DMA_2:
340 /* set timing parameters for RCS2# */
341 mem_sttime = SBC_IDE_MDMA2_TWCS
342 | SBC_IDE_MDMA2_TCSH
343 | SBC_IDE_MDMA2_TCSOFF
344 | SBC_IDE_MDMA2_TWP
345 | SBC_IDE_MDMA2_TCSW
346 | SBC_IDE_MDMA2_TPM
347 | SBC_IDE_MDMA2_TA;
348 /* set configuration for RCS2# */
349 mem_stcfg &= ~TS_MASK;
350 mem_stcfg &= ~TCSOE_MASK;
351 mem_stcfg &= ~TOECS_MASK;
352 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
353
354 mode = XFER_MW_DMA_2;
355 break;
356 case XFER_MW_DMA_1:
357 /* set timing parameters for RCS2# */
358 mem_sttime = SBC_IDE_MDMA1_TWCS
359 | SBC_IDE_MDMA1_TCSH
360 | SBC_IDE_MDMA1_TCSOFF
361 | SBC_IDE_MDMA1_TWP
362 | SBC_IDE_MDMA1_TCSW
363 | SBC_IDE_MDMA1_TPM
364 | SBC_IDE_MDMA1_TA;
365 /* set configuration for RCS2# */
366 mem_stcfg &= ~TS_MASK;
367 mem_stcfg &= ~TCSOE_MASK;
368 mem_stcfg &= ~TOECS_MASK;
369 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
370
371 mode = XFER_MW_DMA_1;
372 break;
373 case XFER_MW_DMA_0:
374 /* set timing parameters for RCS2# */
375 mem_sttime = SBC_IDE_MDMA0_TWCS
376 | SBC_IDE_MDMA0_TCSH
377 | SBC_IDE_MDMA0_TCSOFF
378 | SBC_IDE_MDMA0_TWP
379 | SBC_IDE_MDMA0_TCSW
380 | SBC_IDE_MDMA0_TPM
381 | SBC_IDE_MDMA0_TA;
382 /* set configuration for RCS2# */
383 mem_stcfg |= TS_MASK;
384 mem_stcfg &= ~TCSOE_MASK;
385 mem_stcfg &= ~TOECS_MASK;
386 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
387
388 mode = XFER_MW_DMA_0;
389 break;
390#endif
391 default:
392 return 1;
393 }
394
395 /*
396 * Tell the drive to switch to the new mode; abort on failure.
397 */
398 if (!mode || ide_config_drive_speed(drive, mode))
399 {
400 return 1; /* failure */
401 }
402
403
404 au_writel(mem_sttime,MEM_STTIME2);
405 au_writel(mem_stcfg,MEM_STCFG2);
406
407 spin_unlock_irqrestore(&ide_tune_chipset_spin_lock, flags);
408
409 return 0;
410}
411
412/*
413 * Multi-Word DMA + DbDMA functions
414 */
415#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
416
417static int in_drive_list(struct hd_driveid *id,
418 const struct drive_list_entry *drive_table)
419{
420 for ( ; drive_table->id_model ; drive_table++){
421 if ((!strcmp(drive_table->id_model, id->model)) &&
422 ((strstr(drive_table->id_firmware, id->fw_rev)) ||
423 (!strcmp(drive_table->id_firmware, "ALL")))
424 )
425 return 1;
426 }
427 return 0;
428}
429
430static int auide_build_sglist(ide_drive_t *drive, struct request *rq)
431{
432 ide_hwif_t *hwif = drive->hwif;
433 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
434 struct scatterlist *sg = hwif->sg_table;
435
436 ide_map_sg(drive, rq);
437
438 if (rq_data_dir(rq) == READ)
439 hwif->sg_dma_direction = DMA_FROM_DEVICE;
440 else
441 hwif->sg_dma_direction = DMA_TO_DEVICE;
442
443 return dma_map_sg(ahwif->dev, sg, hwif->sg_nents,
444 hwif->sg_dma_direction);
445}
446
447static int auide_build_dmatable(ide_drive_t *drive)
448{
449 int i, iswrite, count = 0;
450 ide_hwif_t *hwif = HWIF(drive);
451
452 struct request *rq = HWGROUP(drive)->rq;
453
454 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
455 struct scatterlist *sg;
456
457 iswrite = (rq_data_dir(rq) == WRITE);
458 /* Save for interrupt context */
459 ahwif->drive = drive;
460
461 /* Build sglist */
462 hwif->sg_nents = i = auide_build_sglist(drive, rq);
463
464 if (!i)
465 return 0;
466
467 /* fill the descriptors */
468 sg = hwif->sg_table;
469 while (i && sg_dma_len(sg)) {
470 u32 cur_addr;
471 u32 cur_len;
472
473 cur_addr = sg_dma_address(sg);
474 cur_len = sg_dma_len(sg);
475
476 while (cur_len) {
477 u32 flags = DDMA_FLAGS_NOIE;
478 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
479
480 if (++count >= PRD_ENTRIES) {
481 printk(KERN_WARNING "%s: DMA table too small\n",
482 drive->name);
483 goto use_pio_instead;
484 }
485
486 /* Lets enable intr for the last descriptor only */
487 if (1==i)
488 flags = DDMA_FLAGS_IE;
489 else
490 flags = DDMA_FLAGS_NOIE;
491
492 if (iswrite) {
493 if(!put_source_flags(ahwif->tx_chan,
494 (void*)(page_address(sg->page)
495 + sg->offset),
496 tc, flags)) {
497 printk(KERN_ERR "%s failed %d\n",
498 __FUNCTION__, __LINE__);
499 }
500 } else
501 {
502 if(!put_dest_flags(ahwif->rx_chan,
503 (void*)(page_address(sg->page)
504 + sg->offset),
505 tc, flags)) {
506 printk(KERN_ERR "%s failed %d\n",
507 __FUNCTION__, __LINE__);
508 }
509 }
510
511 cur_addr += tc;
512 cur_len -= tc;
513 }
514 sg++;
515 i--;
516 }
517
518 if (count)
519 return 1;
520
521use_pio_instead:
522 dma_unmap_sg(ahwif->dev,
523 hwif->sg_table,
524 hwif->sg_nents,
525 hwif->sg_dma_direction);
526
527 return 0; /* revert to PIO for this request */
528}
529
530static int auide_dma_end(ide_drive_t *drive)
531{
532 ide_hwif_t *hwif = HWIF(drive);
533 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
534
535 if (hwif->sg_nents) {
536 dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
537 hwif->sg_dma_direction);
538 hwif->sg_nents = 0;
539 }
540
541 return 0;
542}
543
544static void auide_dma_start(ide_drive_t *drive )
545{
546// printk("%s\n", __FUNCTION__);
547}
548
549ide_startstop_t auide_dma_intr(ide_drive_t *drive)
550{
551 //printk("%s\n", __FUNCTION__);
552
553 u8 stat = 0, dma_stat = 0;
554
555 dma_stat = HWIF(drive)->ide_dma_end(drive);
556 stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */
557 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
558 if (!dma_stat) {
559 struct request *rq = HWGROUP(drive)->rq;
560
561 ide_end_request(drive, 1, rq->nr_sectors);
562 return ide_stopped;
563 }
564 printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n",
565 drive->name, dma_stat);
566 }
567 return ide_error(drive, "dma_intr", stat);
568}
569
570static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
571{
572 //printk("%s\n", __FUNCTION__);
573
574 /* issue cmd to drive */
575 ide_execute_command(drive, command, &auide_dma_intr,
576 (2*WAIT_CMD), NULL);
577}
578
579static int auide_dma_setup(ide_drive_t *drive)
580{
581// printk("%s\n", __FUNCTION__);
582
583 if (drive->media != ide_disk)
584 return 1;
585
586 if (!auide_build_dmatable(drive))
587 /* try PIO instead of DMA */
588 return 1;
589
590 drive->waiting_for_dma = 1;
591
592 return 0;
593}
594
595static int auide_dma_check(ide_drive_t *drive)
596{
597// printk("%s\n", __FUNCTION__);
598
599#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
600 if( !dbdma_init_done ){
601 auide_hwif.white_list = in_drive_list(drive->id,
602 dma_white_list);
603 auide_hwif.black_list = in_drive_list(drive->id,
604 dma_black_list);
605 auide_hwif.drive = drive;
606 auide_ddma_init(&auide_hwif);
607 dbdma_init_done = 1;
608 }
609#endif
610
611 /* Is the drive in our DMA black list? */
612 if ( auide_hwif.black_list ) {
613 drive->using_dma = 0;
614 printk("%s found in dma_blacklist[]! Disabling DMA.\n",
615 drive->id->model);
616 }
617 else
618 drive->using_dma = 1;
619
620 return HWIF(drive)->ide_dma_host_on(drive);
621}
622
623static int auide_dma_test_irq(ide_drive_t *drive)
624{
625// printk("%s\n", __FUNCTION__);
626
627 if (!drive->waiting_for_dma)
628 printk(KERN_WARNING "%s: ide_dma_test_irq \
629 called while not waiting\n", drive->name);
630
631 /* If dbdma didn't execute the STOP command yet, the
632 * active bit is still set
633 */
634 drive->waiting_for_dma++;
635 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
636 printk(KERN_WARNING "%s: timeout waiting for ddma to \
637 complete\n", drive->name);
638 return 1;
639 }
640 udelay(10);
641 return 0;
642}
643
644static int auide_dma_host_on(ide_drive_t *drive)
645{
646// printk("%s\n", __FUNCTION__);
647 return 0;
648}
649
650static int auide_dma_on(ide_drive_t *drive)
651{
652// printk("%s\n", __FUNCTION__);
653 drive->using_dma = 1;
654 return auide_dma_host_on(drive);
655}
656
657
658static int auide_dma_host_off(ide_drive_t *drive)
659{
660// printk("%s\n", __FUNCTION__);
661 return 0;
662}
663
664static int auide_dma_off_quietly(ide_drive_t *drive)
665{
666// printk("%s\n", __FUNCTION__);
667 drive->using_dma = 0;
668 return auide_dma_host_off(drive);
669}
670
671static int auide_dma_lostirq(ide_drive_t *drive)
672{
673// printk("%s\n", __FUNCTION__);
674
675 printk(KERN_ERR "%s: IRQ lost\n", drive->name);
676 return 0;
677}
678
679static void auide_ddma_tx_callback(int irq, void *param, struct pt_regs *regs)
680{
681// printk("%s\n", __FUNCTION__);
682
683 _auide_hwif *ahwif = (_auide_hwif*)param;
684 ahwif->drive->waiting_for_dma = 0;
685 return;
686}
687
688static void auide_ddma_rx_callback(int irq, void *param, struct pt_regs *regs)
689{
690// printk("%s\n", __FUNCTION__);
691
692 _auide_hwif *ahwif = (_auide_hwif*)param;
693 ahwif->drive->waiting_for_dma = 0;
694 return;
695}
696
697static int auide_dma_timeout(ide_drive_t *drive)
698{
699// printk("%s\n", __FUNCTION__);
700
701 printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
702
703 if (HWIF(drive)->ide_dma_test_irq(drive))
704 return 0;
705
706 return HWIF(drive)->ide_dma_end(drive);
707}
708#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
709
710
711static int auide_ddma_init( _auide_hwif *auide )
712{
713// printk("%s\n", __FUNCTION__);
714
715 dbdev_tab_t source_dev_tab;
716#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
717 dbdev_tab_t target_dev_tab;
718 ide_hwif_t *hwif = auide->hwif;
719 char warning_output [2][80];
720 int i;
721#endif
722
723 /* Add our custom device to DDMA device table */
724 /* Create our new device entries in the table */
725#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
726 source_dev_tab.dev_id = AU1XXX_ATA_DDMA_REQ;
727
728 if( auide->white_list || auide->black_list ){
729 source_dev_tab.dev_tsize = 8;
730 source_dev_tab.dev_devwidth = 32;
731 source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
732 source_dev_tab.dev_intlevel = 0;
733 source_dev_tab.dev_intpolarity = 0;
734
735 /* init device table for target - static bus controller - */
736 target_dev_tab.dev_id = DSCR_CMD0_ALWAYS;
737 target_dev_tab.dev_tsize = 8;
738 target_dev_tab.dev_devwidth = 32;
739 target_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
740 target_dev_tab.dev_intlevel = 0;
741 target_dev_tab.dev_intpolarity = 0;
742 target_dev_tab.dev_flags = DEV_FLAGS_ANYUSE;
743 }
744 else{
745 source_dev_tab.dev_tsize = 1;
746 source_dev_tab.dev_devwidth = 16;
747 source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
748 source_dev_tab.dev_intlevel = 0;
749 source_dev_tab.dev_intpolarity = 0;
750
751 /* init device table for target - static bus controller - */
752 target_dev_tab.dev_id = DSCR_CMD0_ALWAYS;
753 target_dev_tab.dev_tsize = 1;
754 target_dev_tab.dev_devwidth = 16;
755 target_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
756 target_dev_tab.dev_intlevel = 0;
757 target_dev_tab.dev_intpolarity = 0;
758 target_dev_tab.dev_flags = DEV_FLAGS_ANYUSE;
759
760 sprintf(&warning_output[0][0],
761 "%s is not on ide driver white list.",
762 auide_hwif.drive->id->model);
763 for ( i=strlen(&warning_output[0][0]) ; i<76; i++ ){
764 sprintf(&warning_output[0][i]," ");
765 }
766
767 sprintf(&warning_output[1][0],
768 "To add %s please read 'Documentation/mips/AU1xxx_IDE.README'.",
769 auide_hwif.drive->id->model);
770 for ( i=strlen(&warning_output[1][0]) ; i<76; i++ ){
771 sprintf(&warning_output[1][i]," ");
772 }
773
774 printk("\n****************************************");
775 printk("****************************************\n");
776 printk("* %s *\n",&warning_output[0][0]);
777 printk("* Switch to safe MWDMA Mode! ");
778 printk(" *\n");
779 printk("* %s *\n",&warning_output[1][0]);
780 printk("****************************************");
781 printk("****************************************\n\n");
782 }
783#else
784 source_dev_tab.dev_id = DSCR_CMD0_ALWAYS;
785 source_dev_tab.dev_tsize = 8;
786 source_dev_tab.dev_devwidth = 32;
787 source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
788 source_dev_tab.dev_intlevel = 0;
789 source_dev_tab.dev_intpolarity = 0;
790#endif
791
792#if CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
793 /* set flags for tx channel */
794 source_dev_tab.dev_flags = DEV_FLAGS_OUT
795 | DEV_FLAGS_SYNC
796 | DEV_FLAGS_BURSTABLE;
797 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
798 /* set flags for rx channel */
799 source_dev_tab.dev_flags = DEV_FLAGS_IN
800 | DEV_FLAGS_SYNC
801 | DEV_FLAGS_BURSTABLE;
802 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
803#else
804 /* set flags for tx channel */
805 source_dev_tab.dev_flags = DEV_FLAGS_OUT | DEV_FLAGS_SYNC;
806 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
807 /* set flags for rx channel */
808 source_dev_tab.dev_flags = DEV_FLAGS_IN | DEV_FLAGS_SYNC;
809 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
810#endif
811
812#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
813
814 auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
815
816 /* Get a channel for TX */
817 auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
818 auide->tx_dev_id,
819 auide_ddma_tx_callback,
820 (void*)auide);
821 /* Get a channel for RX */
822 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
823 auide->target_dev_id,
824 auide_ddma_rx_callback,
825 (void*)auide);
826#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
827 /*
828 * Note: if call back is not enabled, update ctp->cur_ptr manually
829 */
830 auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
831 auide->tx_dev_id,
832 NULL,
833 (void*)auide);
834 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
835 DSCR_CMD0_ALWAYS,
836 NULL,
837 (void*)auide);
838#endif
839 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
840 NUM_DESCRIPTORS);
841 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
842 NUM_DESCRIPTORS);
843
844#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
845 hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
846 PRD_ENTRIES * PRD_BYTES, /* 1 Page */
847 &hwif->dmatable_dma, GFP_KERNEL);
848
849 auide->sg_table = kmalloc(sizeof(struct scatterlist) * PRD_ENTRIES,
850 GFP_KERNEL|GFP_DMA);
851 if (auide->sg_table == NULL) {
852 return -ENOMEM;
853 }
854#endif
855 au1xxx_dbdma_start( auide->tx_chan );
856 au1xxx_dbdma_start( auide->rx_chan );
857 return 0;
858}
859
860static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
861{
862 int i;
863#define ide_ioreg_t unsigned long
864 ide_ioreg_t *ata_regs = hw->io_ports;
865
866 /* fixme */
867 for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
868 *ata_regs++ = (ide_ioreg_t) ahwif->regbase
869 + (ide_ioreg_t)(i << AU1XXX_ATA_REG_OFFSET);
870 }
871
872 /* set the Alternative Status register */
873 *ata_regs = (ide_ioreg_t) ahwif->regbase
874 + (ide_ioreg_t)(14 << AU1XXX_ATA_REG_OFFSET);
875}
876
877static int au_ide_probe(struct device *dev)
878{
879 struct platform_device *pdev = to_platform_device(dev);
880 _auide_hwif *ahwif = &auide_hwif;
881 ide_hwif_t *hwif;
882 struct resource *res;
883 int ret = 0;
884
885#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
886 char *mode = "MWDMA2";
887#elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
888 char *mode = "PIO+DDMA(offload)";
889#endif
890
891 memset(&auide_hwif, 0, sizeof(_auide_hwif));
892 auide_hwif.dev = 0;
893
894 ahwif->dev = dev;
895 ahwif->irq = platform_get_irq(pdev, 0);
896
897 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
898
899 if (res == NULL) {
900 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
901 ret = -ENODEV;
902 goto out;
903 }
904
905 if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
906 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
907 ret = -EBUSY;
908 goto out;
909 }
910
911 ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
912 if (ahwif->regbase == 0) {
913 ret = -ENOMEM;
914 goto out;
915 }
916
917 hwif = &ide_hwifs[pdev->id];
918 hw_regs_t *hw = &hwif->hw;
919 hwif->irq = hw->irq = ahwif->irq;
920 hwif->chipset = ide_au1xxx;
921
922 auide_setup_ports(hw, ahwif);
923 memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
924
925#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ
926 hwif->rqsize = CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ;
927 hwif->rqsize = ((hwif->rqsize > AU1XXX_ATA_RQSIZE)
928 || (hwif->rqsize < 32)) ? AU1XXX_ATA_RQSIZE : hwif->rqsize;
929#else /* if kernel config is not set */
930 hwif->rqsize = AU1XXX_ATA_RQSIZE;
931#endif
932
933 hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
934#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
935 hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */
936 hwif->swdma_mask = 0x07;
937#else
938 hwif->mwdma_mask = 0x0;
939 hwif->swdma_mask = 0x0;
940#endif
941 //hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
942 hwif->noprobe = 0;
943 hwif->drives[0].unmask = 1;
944 hwif->drives[1].unmask = 1;
945
946 /* hold should be on in all cases */
947 hwif->hold = 1;
948 hwif->mmio = 2;
949
950 /* set up local I/O function entry points */
951 hwif->INB = auide_inb;
952 hwif->INW = auide_inw;
953 hwif->INL = auide_inl;
954 hwif->INSW = auide_insw;
955 hwif->INSL = auide_insl;
956 hwif->OUTB = auide_outb;
957 hwif->OUTBSYNC = auide_outbsync;
958 hwif->OUTW = auide_outw;
959 hwif->OUTL = auide_outl;
960 hwif->OUTSW = auide_outsw;
961 hwif->OUTSL = auide_outsl;
962
963 hwif->tuneproc = &auide_tune_drive;
964 hwif->speedproc = &auide_tune_chipset;
965
966#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
967 hwif->ide_dma_off_quietly = &auide_dma_off_quietly;
968 hwif->ide_dma_timeout = &auide_dma_timeout;
969
970 hwif->ide_dma_check = &auide_dma_check;
971 hwif->dma_exec_cmd = &auide_dma_exec_cmd;
972 hwif->dma_start = &auide_dma_start;
973 hwif->ide_dma_end = &auide_dma_end;
974 hwif->dma_setup = &auide_dma_setup;
975 hwif->ide_dma_test_irq = &auide_dma_test_irq;
976 hwif->ide_dma_host_off = &auide_dma_host_off;
977 hwif->ide_dma_host_on = &auide_dma_host_on;
978 hwif->ide_dma_lostirq = &auide_dma_lostirq;
979 hwif->ide_dma_on = &auide_dma_on;
980
981 hwif->autodma = 1;
982 hwif->drives[0].autodma = hwif->autodma;
983 hwif->drives[1].autodma = hwif->autodma;
984 hwif->atapi_dma = 1;
985 hwif->drives[0].using_dma = 1;
986 hwif->drives[1].using_dma = 1;
987#else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
988 hwif->autodma = 0;
989 hwif->channel = 0;
990 hwif->hold = 1;
991 hwif->select_data = 0; /* no chipset-specific code */
992 hwif->config_data = 0; /* no chipset-specific code */
993
994 hwif->drives[0].autodma = 0;
995 hwif->drives[0].drive_data = 0; /* no drive data */
996 hwif->drives[0].using_dma = 0;
997 hwif->drives[0].waiting_for_dma = 0;
998 hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */
999 /* secondary hdd not supported */
1000 hwif->drives[1].autodma = 0;
1001
1002 hwif->drives[1].drive_data = 0;
1003 hwif->drives[1].using_dma = 0;
1004 hwif->drives[1].waiting_for_dma = 0;
1005 hwif->drives[1].autotune = 2; /* 1=autotune, 2=noautotune, 0=default */
1006#endif
1007 hwif->drives[0].io_32bit = 0; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */
1008 hwif->drives[1].io_32bit = 0; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */
1009
1010 /*Register Driver with PM Framework*/
1011#ifdef CONFIG_PM
1012 auide_hwif.pm.lock = SPIN_LOCK_UNLOCKED;
1013 auide_hwif.pm.stopped = 0;
1014
1015 auide_hwif.pm.dev = new_au1xxx_power_device( "ide",
1016 &au1200ide_pm_callback,
1017 NULL);
1018 if ( auide_hwif.pm.dev == NULL )
1019 printk(KERN_INFO "Unable to create a power management \
1020 device entry for the au1200-IDE.\n");
1021 else
1022 printk(KERN_INFO "Power management device entry for the \
1023 au1200-IDE loaded.\n");
1024#endif
1025
1026 auide_hwif.hwif = hwif;
1027 hwif->hwif_data = &auide_hwif;
1028
1029#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
1030 auide_ddma_init(&auide_hwif);
1031 dbdma_init_done = 1;
1032#endif
1033
1034 probe_hwif_init(hwif);
1035 dev_set_drvdata(dev, hwif);
1036
1037 printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
1038
1039out:
1040 return ret;
1041}
1042
1043static int au_ide_remove(struct device *dev)
1044{
1045 struct platform_device *pdev = to_platform_device(dev);
1046 struct resource *res;
1047 ide_hwif_t *hwif = dev_get_drvdata(dev);
1048 _auide_hwif *ahwif = &auide_hwif;
1049
1050 ide_unregister(hwif - ide_hwifs);
1051
1052 iounmap((void *)ahwif->regbase);
1053
1054 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1055 release_mem_region(res->start, res->end - res->start);
1056
1057 return 0;
1058}
1059
1060static struct device_driver au1200_ide_driver = {
1061 .name = "au1200-ide",
1062 .bus = &platform_bus_type,
1063 .probe = au_ide_probe,
1064 .remove = au_ide_remove,
1065};
1066
1067static int __init au_ide_init(void)
1068{
1069 return driver_register(&au1200_ide_driver);
1070}
1071
1072static void __init au_ide_exit(void)
1073{
1074 driver_unregister(&au1200_ide_driver);
1075}
1076
1077#ifdef CONFIG_PM
1078int au1200ide_pm_callback( au1xxx_power_dev_t *dev,\
1079 au1xxx_request_t request, void *data) {
1080
1081 unsigned int d, err = 0;
1082 unsigned long flags;
1083
1084 spin_lock_irqsave(auide_hwif.pm.lock, flags);
1085
1086 switch (request){
1087 case AU1XXX_PM_SLEEP:
1088 err = au1xxxide_pm_sleep(dev);
1089 break;
1090 case AU1XXX_PM_WAKEUP:
1091 d = *((unsigned int*)data);
1092 if ( d > 0 && d <= 99) {
1093 err = au1xxxide_pm_standby(dev);
1094 }
1095 else {
1096 err = au1xxxide_pm_resume(dev);
1097 }
1098 break;
1099 case AU1XXX_PM_GETSTATUS:
1100 err = au1xxxide_pm_getstatus(dev);
1101 break;
1102 case AU1XXX_PM_ACCESS:
1103 err = au1xxxide_pm_access(dev);
1104 break;
1105 case AU1XXX_PM_IDLE:
1106 err = au1xxxide_pm_idle(dev);
1107 break;
1108 case AU1XXX_PM_CLEANUP:
1109 err = au1xxxide_pm_cleanup(dev);
1110 break;
1111 default:
1112 err = -1;
1113 break;
1114 }
1115
1116 spin_unlock_irqrestore(auide_hwif.pm.lock, flags);
1117
1118 return err;
1119}
1120
1121static int au1xxxide_pm_standby( au1xxx_power_dev_t *dev ) {
1122 return 0;
1123}
1124
1125static int au1xxxide_pm_sleep( au1xxx_power_dev_t *dev ) {
1126
1127 int retval;
1128 ide_hwif_t *hwif = auide_hwif.hwif;
1129 struct request rq;
1130 struct request_pm_state rqpm;
1131 ide_task_t args;
1132
1133 if(auide_hwif.pm.stopped)
1134 return -1;
1135
1136 /*
1137 * wait until hard disc is ready
1138 */
1139 if ( wait_for_ready(&hwif->drives[0], 35000) ) {
1140 printk("Wait for drive sleep timeout!\n");
1141 retval = -1;
1142 }
1143
1144 /*
1145 * sequenz to tell the high level ide driver that pm is resuming
1146 */
1147 memset(&rq, 0, sizeof(rq));
1148 memset(&rqpm, 0, sizeof(rqpm));
1149 memset(&args, 0, sizeof(args));
1150 rq.flags = REQ_PM_SUSPEND;
1151 rq.special = &args;
1152 rq.pm = &rqpm;
1153 rqpm.pm_step = ide_pm_state_start_suspend;
1154 rqpm.pm_state = PMSG_SUSPEND;
1155
1156 retval = ide_do_drive_cmd(&hwif->drives[0], &rq, ide_wait);
1157
1158 if (wait_for_ready (&hwif->drives[0], 35000)) {
1159 printk("Wait for drive sleep timeout!\n");
1160 retval = -1;
1161 }
1162
1163 /*
1164 * stop dbdma channels
1165 */
1166 au1xxx_dbdma_reset(auide_hwif.tx_chan);
1167 au1xxx_dbdma_reset(auide_hwif.rx_chan);
1168
1169 auide_hwif.pm.stopped = 1;
1170
1171 return retval;
1172}
1173
1174static int au1xxxide_pm_resume( au1xxx_power_dev_t *dev ) {
1175
1176 int retval;
1177 ide_hwif_t *hwif = auide_hwif.hwif;
1178 struct request rq;
1179 struct request_pm_state rqpm;
1180 ide_task_t args;
1181
1182 if(!auide_hwif.pm.stopped)
1183 return -1;
1184
1185 /*
1186 * start dbdma channels
1187 */
1188 au1xxx_dbdma_start(auide_hwif.tx_chan);
1189 au1xxx_dbdma_start(auide_hwif.rx_chan);
1190
1191 /*
1192 * wait until hard disc is ready
1193 */
1194 if (wait_for_ready ( &hwif->drives[0], 35000)) {
1195 printk("Wait for drive wake up timeout!\n");
1196 retval = -1;
1197 }
1198
1199 /*
1200 * sequenz to tell the high level ide driver that pm is resuming
1201 */
1202 memset(&rq, 0, sizeof(rq));
1203 memset(&rqpm, 0, sizeof(rqpm));
1204 memset(&args, 0, sizeof(args));
1205 rq.flags = REQ_PM_RESUME;
1206 rq.special = &args;
1207 rq.pm = &rqpm;
1208 rqpm.pm_step = ide_pm_state_start_resume;
1209 rqpm.pm_state = PMSG_ON;
1210
1211 retval = ide_do_drive_cmd(&hwif->drives[0], &rq, ide_head_wait);
1212
1213 /*
1214 * wait for hard disc
1215 */
1216 if ( wait_for_ready(&hwif->drives[0], 35000) ) {
1217 printk("Wait for drive wake up timeout!\n");
1218 retval = -1;
1219 }
1220
1221 auide_hwif.pm.stopped = 0;
1222
1223 return retval;
1224}
1225
1226static int au1xxxide_pm_getstatus( au1xxx_power_dev_t *dev ) {
1227 return dev->cur_state;
1228}
1229
1230static int au1xxxide_pm_access( au1xxx_power_dev_t *dev ) {
1231 if (dev->cur_state != AWAKE_STATE)
1232 return 0;
1233 else
1234 return -1;
1235}
1236
1237static int au1xxxide_pm_idle( au1xxx_power_dev_t *dev ) {
1238 return 0;
1239}
1240
1241static int au1xxxide_pm_cleanup( au1xxx_power_dev_t *dev ) {
1242 return 0;
1243}
1244#endif /* CONFIG_PM */
1245
1246MODULE_LICENSE("GPL");
1247MODULE_DESCRIPTION("AU1200 IDE driver");
1248
1249module_init(au_ide_init);
1250module_exit(au_ide_exit);
diff --git a/drivers/media/video/indycam.c b/drivers/media/video/indycam.c
index b2b0384cd4b9..26dd06ec89a2 100644
--- a/drivers/media/video/indycam.c
+++ b/drivers/media/video/indycam.c
@@ -9,16 +9,16 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/delay.h> 12#include <linux/delay.h>
15#include <linux/errno.h> 13#include <linux/errno.h>
16#include <linux/fs.h> 14#include <linux/fs.h>
15#include <linux/init.h>
17#include <linux/kernel.h> 16#include <linux/kernel.h>
18#include <linux/major.h> 17#include <linux/major.h>
19#include <linux/slab.h> 18#include <linux/module.h>
20#include <linux/mm.h> 19#include <linux/mm.h>
21#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/slab.h>
22 22
23#include <linux/videodev.h> 23#include <linux/videodev.h>
24/* IndyCam decodes stream of photons into digital image representation ;-) */ 24/* IndyCam decodes stream of photons into digital image representation ;-) */
@@ -44,8 +44,6 @@ MODULE_LICENSE("GPL");
44#define indycam_regdump(client) 44#define indycam_regdump(client)
45#endif 45#endif
46 46
47#define VINO_ADAPTER (I2C_ALGO_SGI | I2C_HW_SGI_VINO)
48
49struct indycam { 47struct indycam {
50 struct i2c_client *client; 48 struct i2c_client *client;
51 int version; 49 int version;
@@ -300,7 +298,7 @@ out_free_client:
300static int indycam_probe(struct i2c_adapter *adap) 298static int indycam_probe(struct i2c_adapter *adap)
301{ 299{
302 /* Indy specific crap */ 300 /* Indy specific crap */
303 if (adap->id == VINO_ADAPTER) 301 if (adap->id == I2C_HW_SGI_VINO)
304 return indycam_attach(adap, INDYCAM_ADDR, 0); 302 return indycam_attach(adap, INDYCAM_ADDR, 0);
305 /* Feel free to add probe here :-) */ 303 /* Feel free to add probe here :-) */
306 return -ENODEV; 304 return -ENODEV;
diff --git a/drivers/media/video/saa7191.c b/drivers/media/video/saa7191.c
index 454f5c1199b4..3ddbb62312be 100644
--- a/drivers/media/video/saa7191.c
+++ b/drivers/media/video/saa7191.c
@@ -9,16 +9,16 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/delay.h> 12#include <linux/delay.h>
15#include <linux/errno.h> 13#include <linux/errno.h>
16#include <linux/fs.h> 14#include <linux/fs.h>
15#include <linux/init.h>
17#include <linux/kernel.h> 16#include <linux/kernel.h>
18#include <linux/major.h> 17#include <linux/major.h>
19#include <linux/slab.h> 18#include <linux/module.h>
20#include <linux/mm.h> 19#include <linux/mm.h>
21#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/slab.h>
22 22
23#include <linux/videodev.h> 23#include <linux/videodev.h>
24#include <linux/video_decoder.h> 24#include <linux/video_decoder.h>
@@ -33,8 +33,6 @@ MODULE_VERSION(SAA7191_MODULE_VERSION);
33MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>"); 33MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>");
34MODULE_LICENSE("GPL"); 34MODULE_LICENSE("GPL");
35 35
36#define VINO_ADAPTER (I2C_ALGO_SGI | I2C_HW_SGI_VINO)
37
38struct saa7191 { 36struct saa7191 {
39 struct i2c_client *client; 37 struct i2c_client *client;
40 38
@@ -337,7 +335,7 @@ out_free_client:
337static int saa7191_probe(struct i2c_adapter *adap) 335static int saa7191_probe(struct i2c_adapter *adap)
338{ 336{
339 /* Always connected to VINO */ 337 /* Always connected to VINO */
340 if (adap->id == VINO_ADAPTER) 338 if (adap->id == I2C_HW_SGI_VINO)
341 return saa7191_attach(adap, SAA7191_ADDR, 0); 339 return saa7191_attach(adap, SAA7191_ADDR, 0);
342 /* Feel free to add probe here :-) */ 340 /* Feel free to add probe here :-) */
343 return -ENODEV; 341 return -ENODEV;
@@ -364,7 +362,7 @@ static int saa7191_command(struct i2c_client *client, unsigned int cmd,
364 362
365 cap->flags = VIDEO_DECODER_PAL | VIDEO_DECODER_NTSC | 363 cap->flags = VIDEO_DECODER_PAL | VIDEO_DECODER_NTSC |
366 VIDEO_DECODER_SECAM | VIDEO_DECODER_AUTO; 364 VIDEO_DECODER_SECAM | VIDEO_DECODER_AUTO;
367 cap->inputs = (client->adapter->id == VINO_ADAPTER) ? 2 : 1; 365 cap->inputs = (client->adapter->id == I2C_HW_SGI_VINO) ? 2 : 1;
368 cap->outputs = 1; 366 cap->outputs = 1;
369 break; 367 break;
370 } 368 }
@@ -422,7 +420,7 @@ static int saa7191_command(struct i2c_client *client, unsigned int cmd,
422 int *iarg = arg; 420 int *iarg = arg;
423 421
424 switch (client->adapter->id) { 422 switch (client->adapter->id) {
425 case VINO_ADAPTER: 423 case I2C_HW_SGI_VINO:
426 return saa7191_set_input(client, *iarg); 424 return saa7191_set_input(client, *iarg);
427 default: 425 default:
428 if (*iarg != 0) 426 if (*iarg != 0)
diff --git a/drivers/media/video/vino.c b/drivers/media/video/vino.c
index d8a0f763ca10..ed4394e854ab 100644
--- a/drivers/media/video/vino.c
+++ b/drivers/media/video/vino.c
@@ -26,14 +26,15 @@
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/delay.h> 28#include <linux/delay.h>
29#include <linux/dma-mapping.h>
29#include <linux/errno.h> 30#include <linux/errno.h>
30#include <linux/fs.h> 31#include <linux/fs.h>
32#include <linux/interrupt.h>
31#include <linux/kernel.h> 33#include <linux/kernel.h>
32#include <linux/mm.h> 34#include <linux/mm.h>
33#include <linux/interrupt.h>
34#include <linux/dma-mapping.h>
35#include <linux/time.h>
36#include <linux/moduleparam.h> 35#include <linux/moduleparam.h>
36#include <linux/time.h>
37#include <linux/version.h>
37 38
38#ifdef CONFIG_KMOD 39#ifdef CONFIG_KMOD
39#include <linux/kmod.h> 40#include <linux/kmod.h>
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 4991bbd054f3..c483a863b116 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -60,4 +60,13 @@ config MMC_WBSD
60 60
61 If unsure, say N. 61 If unsure, say N.
62 62
63config MMC_AU1X
64 tristate "Alchemy AU1XX0 MMC Card Interface support"
65 depends on SOC_AU1X00 && MMC
66 help
67 This selects the AMD Alchemy(R) Multimedia card interface.
68 iIf you have a Alchemy platform with a MMC slot, say Y or M here.
69
70 If unsure, say N.
71
63endmenu 72endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 89510c2086c7..e351e71146e9 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_MMC_BLOCK) += mmc_block.o
18obj-$(CONFIG_MMC_ARMMMCI) += mmci.o 18obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
19obj-$(CONFIG_MMC_PXA) += pxamci.o 19obj-$(CONFIG_MMC_PXA) += pxamci.o
20obj-$(CONFIG_MMC_WBSD) += wbsd.o 20obj-$(CONFIG_MMC_WBSD) += wbsd.o
21obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
21 22
22mmc_core-y := mmc.o mmc_queue.o mmc_sysfs.o 23mmc_core-y := mmc.o mmc_queue.o mmc_sysfs.o
diff --git a/drivers/mmc/au1xmmc.c b/drivers/mmc/au1xmmc.c
new file mode 100644
index 000000000000..aaf04638054e
--- /dev/null
+++ b/drivers/mmc/au1xmmc.c
@@ -0,0 +1,1026 @@
1/*
2 * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver
3 *
4 * Copyright (c) 2005, Advanced Micro Devices, Inc.
5 *
6 * Developed with help from the 2.4.30 MMC AU1XXX controller including
7 * the following copyright notices:
8 * Copyright (c) 2003-2004 Embedded Edge, LLC.
9 * Portions Copyright (C) 2002 Embedix, Inc
10 * Copyright 2002 Hewlett-Packard Company
11
12 * 2.6 version of this driver inspired by:
13 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14 * All Rights Reserved.
15 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16 * All Rights Reserved.
17 *
18
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 */
23
24/* Why is a timer used to detect insert events?
25 *
26 * From the AU1100 MMC application guide:
27 * If the Au1100-based design is intended to support both MultiMediaCards
28 * and 1- or 4-data bit SecureDigital cards, then the solution is to
29 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30 * In doing so, a MMC card never enters SPI-mode communications,
31 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32 * (the low to high transition will not occur).
33 *
34 * So we use the timer to check the status manually.
35 */
36
37#include <linux/config.h>
38#include <linux/module.h>
39#include <linux/init.h>
40#include <linux/device.h>
41#include <linux/mm.h>
42#include <linux/interrupt.h>
43#include <linux/dma-mapping.h>
44
45#include <linux/mmc/host.h>
46#include <linux/mmc/protocol.h>
47#include <asm/io.h>
48#include <asm/mach-au1x00/au1000.h>
49#include <asm/mach-au1x00/au1xxx_dbdma.h>
50#include <asm/mach-au1x00/au1100_mmc.h>
51#include <asm/scatterlist.h>
52
53#include <au1xxx.h>
54#include "au1xmmc.h"
55
56#define DRIVER_NAME "au1xxx-mmc"
57
58/* Set this to enable special debugging macros */
59/* #define MMC_DEBUG */
60
61#ifdef MMC_DEBUG
62#define DEBUG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
63#else
64#define DEBUG(fmt, idx, args...)
65#endif
66
67const struct {
68 u32 iobase;
69 u32 tx_devid, rx_devid;
70 u16 bcsrpwr;
71 u16 bcsrstatus;
72 u16 wpstatus;
73} au1xmmc_card_table[] = {
74 { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0,
75 BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP },
76#ifndef CONFIG_MIPS_DB1200
77 { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1,
78 BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP }
79#endif
80};
81
82#define AU1XMMC_CONTROLLER_COUNT \
83 (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))
84
85/* This array stores pointers for the hosts (used by the IRQ handler) */
86struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT];
87static int dma = 1;
88
89#ifdef MODULE
90MODULE_PARM(dma, "i");
91MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)");
92#endif
93
94static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
95{
96 u32 val = au_readl(HOST_CONFIG(host));
97 val |= mask;
98 au_writel(val, HOST_CONFIG(host));
99 au_sync();
100}
101
102static inline void FLUSH_FIFO(struct au1xmmc_host *host)
103{
104 u32 val = au_readl(HOST_CONFIG2(host));
105
106 au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
107 au_sync_delay(1);
108
109 /* SEND_STOP will turn off clock control - this re-enables it */
110 val &= ~SD_CONFIG2_DF;
111
112 au_writel(val, HOST_CONFIG2(host));
113 au_sync();
114}
115
116static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
117{
118 u32 val = au_readl(HOST_CONFIG(host));
119 val &= ~mask;
120 au_writel(val, HOST_CONFIG(host));
121 au_sync();
122}
123
124static inline void SEND_STOP(struct au1xmmc_host *host)
125{
126
127 /* We know the value of CONFIG2, so avoid a read we don't need */
128 u32 mask = SD_CONFIG2_EN;
129
130 WARN_ON(host->status != HOST_S_DATA);
131 host->status = HOST_S_STOP;
132
133 au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
134 au_sync();
135
136 /* Send the stop commmand */
137 au_writel(STOP_CMD, HOST_CMD(host));
138}
139
140static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
141{
142
143 u32 val = au1xmmc_card_table[host->id].bcsrpwr;
144
145 bcsr->board &= ~val;
146 if (state) bcsr->board |= val;
147
148 au_sync_delay(1);
149}
150
151static inline int au1xmmc_card_inserted(struct au1xmmc_host *host)
152{
153 return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus)
154 ? 1 : 0;
155}
156
157static inline int au1xmmc_card_readonly(struct au1xmmc_host *host)
158{
159 return (bcsr->status & au1xmmc_card_table[host->id].wpstatus)
160 ? 1 : 0;
161}
162
163static void au1xmmc_finish_request(struct au1xmmc_host *host)
164{
165
166 struct mmc_request *mrq = host->mrq;
167
168 host->mrq = NULL;
169 host->flags &= HOST_F_ACTIVE;
170
171 host->dma.len = 0;
172 host->dma.dir = 0;
173
174 host->pio.index = 0;
175 host->pio.offset = 0;
176 host->pio.len = 0;
177
178 host->status = HOST_S_IDLE;
179
180 bcsr->disk_leds |= (1 << 8);
181
182 mmc_request_done(host->mmc, mrq);
183}
184
185static void au1xmmc_tasklet_finish(unsigned long param)
186{
187 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
188 au1xmmc_finish_request(host);
189}
190
191static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
192 struct mmc_command *cmd)
193{
194
195 u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
196
197 switch(cmd->flags) {
198 case MMC_RSP_R1:
199 mmccmd |= SD_CMD_RT_1;
200 break;
201 case MMC_RSP_R1B:
202 mmccmd |= SD_CMD_RT_1B;
203 break;
204 case MMC_RSP_R2:
205 mmccmd |= SD_CMD_RT_2;
206 break;
207 case MMC_RSP_R3:
208 mmccmd |= SD_CMD_RT_3;
209 break;
210 }
211
212 switch(cmd->opcode) {
213 case MMC_READ_SINGLE_BLOCK:
214 case SD_APP_SEND_SCR:
215 mmccmd |= SD_CMD_CT_2;
216 break;
217 case MMC_READ_MULTIPLE_BLOCK:
218 mmccmd |= SD_CMD_CT_4;
219 break;
220 case MMC_WRITE_BLOCK:
221 mmccmd |= SD_CMD_CT_1;
222 break;
223
224 case MMC_WRITE_MULTIPLE_BLOCK:
225 mmccmd |= SD_CMD_CT_3;
226 break;
227 case MMC_STOP_TRANSMISSION:
228 mmccmd |= SD_CMD_CT_7;
229 break;
230 }
231
232 au_writel(cmd->arg, HOST_CMDARG(host));
233 au_sync();
234
235 if (wait)
236 IRQ_OFF(host, SD_CONFIG_CR);
237
238 au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
239 au_sync();
240
241 /* Wait for the command to go on the line */
242
243 while(1) {
244 if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
245 break;
246 }
247
248 /* Wait for the command to come back */
249
250 if (wait) {
251 u32 status = au_readl(HOST_STATUS(host));
252
253 while(!(status & SD_STATUS_CR))
254 status = au_readl(HOST_STATUS(host));
255
256 /* Clear the CR status */
257 au_writel(SD_STATUS_CR, HOST_STATUS(host));
258
259 IRQ_ON(host, SD_CONFIG_CR);
260 }
261
262 return MMC_ERR_NONE;
263}
264
265static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
266{
267
268 struct mmc_request *mrq = host->mrq;
269 struct mmc_data *data;
270 u32 crc;
271
272 WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
273
274 if (host->mrq == NULL)
275 return;
276
277 data = mrq->cmd->data;
278
279 if (status == 0)
280 status = au_readl(HOST_STATUS(host));
281
282 /* The transaction is really over when the SD_STATUS_DB bit is clear */
283
284 while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
285 status = au_readl(HOST_STATUS(host));
286
287 data->error = MMC_ERR_NONE;
288 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
289
290 /* Process any errors */
291
292 crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
293 if (host->flags & HOST_F_XMIT)
294 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
295
296 if (crc)
297 data->error = MMC_ERR_BADCRC;
298
299 /* Clear the CRC bits */
300 au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
301
302 data->bytes_xfered = 0;
303
304 if (data->error == MMC_ERR_NONE) {
305 if (host->flags & HOST_F_DMA) {
306 u32 chan = DMA_CHANNEL(host);
307
308 chan_tab_t *c = *((chan_tab_t **) chan);
309 au1x_dma_chan_t *cp = c->chan_ptr;
310 data->bytes_xfered = cp->ddma_bytecnt;
311 }
312 else
313 data->bytes_xfered =
314 (data->blocks * (1 << data->blksz_bits)) -
315 host->pio.len;
316 }
317
318 au1xmmc_finish_request(host);
319}
320
321static void au1xmmc_tasklet_data(unsigned long param)
322{
323 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
324
325 u32 status = au_readl(HOST_STATUS(host));
326 au1xmmc_data_complete(host, status);
327}
328
329#define AU1XMMC_MAX_TRANSFER 8
330
331static void au1xmmc_send_pio(struct au1xmmc_host *host)
332{
333
334 struct mmc_data *data = 0;
335 int sg_len, max, count = 0;
336 unsigned char *sg_ptr;
337 u32 status = 0;
338 struct scatterlist *sg;
339
340 data = host->mrq->data;
341
342 if (!(host->flags & HOST_F_XMIT))
343 return;
344
345 /* This is the pointer to the data buffer */
346 sg = &data->sg[host->pio.index];
347 sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
348
349 /* This is the space left inside the buffer */
350 sg_len = data->sg[host->pio.index].length - host->pio.offset;
351
352 /* Check to if we need less then the size of the sg_buffer */
353
354 max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
355 if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
356
357 for(count = 0; count < max; count++ ) {
358 unsigned char val;
359
360 status = au_readl(HOST_STATUS(host));
361
362 if (!(status & SD_STATUS_TH))
363 break;
364
365 val = *sg_ptr++;
366
367 au_writel((unsigned long) val, HOST_TXPORT(host));
368 au_sync();
369 }
370
371 host->pio.len -= count;
372 host->pio.offset += count;
373
374 if (count == sg_len) {
375 host->pio.index++;
376 host->pio.offset = 0;
377 }
378
379 if (host->pio.len == 0) {
380 IRQ_OFF(host, SD_CONFIG_TH);
381
382 if (host->flags & HOST_F_STOP)
383 SEND_STOP(host);
384
385 tasklet_schedule(&host->data_task);
386 }
387}
388
389static void au1xmmc_receive_pio(struct au1xmmc_host *host)
390{
391
392 struct mmc_data *data = 0;
393 int sg_len = 0, max = 0, count = 0;
394 unsigned char *sg_ptr = 0;
395 u32 status = 0;
396 struct scatterlist *sg;
397
398 data = host->mrq->data;
399
400 if (!(host->flags & HOST_F_RECV))
401 return;
402
403 max = host->pio.len;
404
405 if (host->pio.index < host->dma.len) {
406 sg = &data->sg[host->pio.index];
407 sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
408
409 /* This is the space left inside the buffer */
410 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
411
412 /* Check to if we need less then the size of the sg_buffer */
413 if (sg_len < max) max = sg_len;
414 }
415
416 if (max > AU1XMMC_MAX_TRANSFER)
417 max = AU1XMMC_MAX_TRANSFER;
418
419 for(count = 0; count < max; count++ ) {
420 u32 val;
421 status = au_readl(HOST_STATUS(host));
422
423 if (!(status & SD_STATUS_NE))
424 break;
425
426 if (status & SD_STATUS_RC) {
427 DEBUG("RX CRC Error [%d + %d].\n", host->id,
428 host->pio.len, count);
429 break;
430 }
431
432 if (status & SD_STATUS_RO) {
433 DEBUG("RX Overrun [%d + %d]\n", host->id,
434 host->pio.len, count);
435 break;
436 }
437 else if (status & SD_STATUS_RU) {
438 DEBUG("RX Underrun [%d + %d]\n", host->id,
439 host->pio.len, count);
440 break;
441 }
442
443 val = au_readl(HOST_RXPORT(host));
444
445 if (sg_ptr)
446 *sg_ptr++ = (unsigned char) (val & 0xFF);
447 }
448
449 host->pio.len -= count;
450 host->pio.offset += count;
451
452 if (sg_len && count == sg_len) {
453 host->pio.index++;
454 host->pio.offset = 0;
455 }
456
457 if (host->pio.len == 0) {
458 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
459 IRQ_OFF(host, SD_CONFIG_NE);
460
461 if (host->flags & HOST_F_STOP)
462 SEND_STOP(host);
463
464 tasklet_schedule(&host->data_task);
465 }
466}
467
468/* static void au1xmmc_cmd_complete
469 This is called when a command has been completed - grab the response
470 and check for errors. Then start the data transfer if it is indicated.
471*/
472
473static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
474{
475
476 struct mmc_request *mrq = host->mrq;
477 struct mmc_command *cmd;
478 int trans;
479
480 if (!host->mrq)
481 return;
482
483 cmd = mrq->cmd;
484 cmd->error = MMC_ERR_NONE;
485
486 if ((cmd->flags & MMC_RSP_MASK) == MMC_RSP_SHORT) {
487
488 /* Techincally, we should be getting all 48 bits of the response
489 * (SD_RESP1 + SD_RESP2), but because our response omits the CRC,
490 * our data ends up being shifted 8 bits to the right. In this case,
491 * that means that the OSR data starts at bit 31, so we can just
492 * read RESP0 and return that
493 */
494
495 cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
496 }
497 else if ((cmd->flags & MMC_RSP_MASK) == MMC_RSP_LONG) {
498 u32 r[4];
499 int i;
500
501 r[0] = au_readl(host->iobase + SD_RESP3);
502 r[1] = au_readl(host->iobase + SD_RESP2);
503 r[2] = au_readl(host->iobase + SD_RESP1);
504 r[3] = au_readl(host->iobase + SD_RESP0);
505
506 /* The CRC is omitted from the response, so really we only got
507 * 120 bytes, but the engine expects 128 bits, so we have to shift
508 * things up
509 */
510
511 for(i = 0; i < 4; i++) {
512 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
513 if (i != 3) cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
514 }
515 }
516
517 /* Figure out errors */
518
519 if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
520 cmd->error = MMC_ERR_BADCRC;
521
522 trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
523
524 if (!trans || cmd->error != MMC_ERR_NONE) {
525
526 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
527 tasklet_schedule(&host->finish_task);
528 return;
529 }
530
531 host->status = HOST_S_DATA;
532
533 if (host->flags & HOST_F_DMA) {
534 u32 channel = DMA_CHANNEL(host);
535
536 /* Start the DMA as soon as the buffer gets something in it */
537
538 if (host->flags & HOST_F_RECV) {
539 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
540
541 while((status & mask) != mask)
542 status = au_readl(HOST_STATUS(host));
543 }
544
545 au1xxx_dbdma_start(channel);
546 }
547}
548
549static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
550{
551
552 unsigned int pbus = get_au1x00_speed();
553 unsigned int divisor;
554 u32 config;
555
556 /* From databook:
557 divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
558 */
559
560 pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
561 pbus /= 2;
562
563 divisor = ((pbus / rate) / 2) - 1;
564
565 config = au_readl(HOST_CONFIG(host));
566
567 config &= ~(SD_CONFIG_DIV);
568 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
569
570 au_writel(config, HOST_CONFIG(host));
571 au_sync();
572}
573
574static int
575au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
576{
577
578 int datalen = data->blocks * (1 << data->blksz_bits);
579
580 if (dma != 0)
581 host->flags |= HOST_F_DMA;
582
583 if (data->flags & MMC_DATA_READ)
584 host->flags |= HOST_F_RECV;
585 else
586 host->flags |= HOST_F_XMIT;
587
588 if (host->mrq->stop)
589 host->flags |= HOST_F_STOP;
590
591 host->dma.dir = DMA_BIDIRECTIONAL;
592
593 host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
594 data->sg_len, host->dma.dir);
595
596 if (host->dma.len == 0)
597 return MMC_ERR_TIMEOUT;
598
599 au_writel((1 << data->blksz_bits) - 1, HOST_BLKSIZE(host));
600
601 if (host->flags & HOST_F_DMA) {
602 int i;
603 u32 channel = DMA_CHANNEL(host);
604
605 au1xxx_dbdma_stop(channel);
606
607 for(i = 0; i < host->dma.len; i++) {
608 u32 ret = 0, flags = DDMA_FLAGS_NOIE;
609 struct scatterlist *sg = &data->sg[i];
610 int sg_len = sg->length;
611
612 int len = (datalen > sg_len) ? sg_len : datalen;
613
614 if (i == host->dma.len - 1)
615 flags = DDMA_FLAGS_IE;
616
617 if (host->flags & HOST_F_XMIT){
618 ret = au1xxx_dbdma_put_source_flags(channel,
619 (void *) (page_address(sg->page) +
620 sg->offset),
621 len, flags);
622 }
623 else {
624 ret = au1xxx_dbdma_put_dest_flags(channel,
625 (void *) (page_address(sg->page) +
626 sg->offset),
627 len, flags);
628 }
629
630 if (!ret)
631 goto dataerr;
632
633 datalen -= len;
634 }
635 }
636 else {
637 host->pio.index = 0;
638 host->pio.offset = 0;
639 host->pio.len = datalen;
640
641 if (host->flags & HOST_F_XMIT)
642 IRQ_ON(host, SD_CONFIG_TH);
643 else
644 IRQ_ON(host, SD_CONFIG_NE);
645 //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
646 }
647
648 return MMC_ERR_NONE;
649
650 dataerr:
651 dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir);
652 return MMC_ERR_TIMEOUT;
653}
654
655/* static void au1xmmc_request
656 This actually starts a command or data transaction
657*/
658
659static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
660{
661
662 struct au1xmmc_host *host = mmc_priv(mmc);
663 int ret = MMC_ERR_NONE;
664
665 WARN_ON(irqs_disabled());
666 WARN_ON(host->status != HOST_S_IDLE);
667
668 host->mrq = mrq;
669 host->status = HOST_S_CMD;
670
671 bcsr->disk_leds &= ~(1 << 8);
672
673 if (mrq->data) {
674 FLUSH_FIFO(host);
675 ret = au1xmmc_prepare_data(host, mrq->data);
676 }
677
678 if (ret == MMC_ERR_NONE)
679 ret = au1xmmc_send_command(host, 0, mrq->cmd);
680
681 if (ret != MMC_ERR_NONE) {
682 mrq->cmd->error = ret;
683 au1xmmc_finish_request(host);
684 }
685}
686
687static void au1xmmc_reset_controller(struct au1xmmc_host *host)
688{
689
690 /* Apply the clock */
691 au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
692 au_sync_delay(1);
693
694 au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
695 au_sync_delay(5);
696
697 au_writel(~0, HOST_STATUS(host));
698 au_sync();
699
700 au_writel(0, HOST_BLKSIZE(host));
701 au_writel(0x001fffff, HOST_TIMEOUT(host));
702 au_sync();
703
704 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
705 au_sync();
706
707 au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
708 au_sync_delay(1);
709
710 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
711 au_sync();
712
713 /* Configure interrupts */
714 au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
715 au_sync();
716}
717
718
719static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
720{
721 struct au1xmmc_host *host = mmc_priv(mmc);
722
723 DEBUG("set_ios (power=%u, clock=%uHz, vdd=%u, mode=%u)\n",
724 host->id, ios->power_mode, ios->clock, ios->vdd,
725 ios->bus_mode);
726
727 if (ios->power_mode == MMC_POWER_OFF)
728 au1xmmc_set_power(host, 0);
729 else if (ios->power_mode == MMC_POWER_ON) {
730 au1xmmc_set_power(host, 1);
731 }
732
733 if (ios->clock && ios->clock != host->clock) {
734 au1xmmc_set_clock(host, ios->clock);
735 host->clock = ios->clock;
736 }
737}
738
739static void au1xmmc_dma_callback(int irq, void *dev_id, struct pt_regs *regs)
740{
741 struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;
742 u32 status;
743
744 /* Avoid spurious interrupts */
745
746 if (!host->mrq)
747 return;
748
749 if (host->flags & HOST_F_STOP)
750 SEND_STOP(host);
751
752 tasklet_schedule(&host->data_task);
753}
754
755#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
756#define STATUS_DATA_IN (SD_STATUS_NE)
757#define STATUS_DATA_OUT (SD_STATUS_TH)
758
759static irqreturn_t au1xmmc_irq(int irq, void *dev_id, struct pt_regs *regs)
760{
761
762 u32 status;
763 int i, ret = 0;
764
765 disable_irq(AU1100_SD_IRQ);
766
767 for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
768 struct au1xmmc_host * host = au1xmmc_hosts[i];
769 u32 handled = 1;
770
771 status = au_readl(HOST_STATUS(host));
772
773 if (host->mrq && (status & STATUS_TIMEOUT)) {
774 if (status & SD_STATUS_RAT)
775 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
776
777 else if (status & SD_STATUS_DT)
778 host->mrq->data->error = MMC_ERR_TIMEOUT;
779
780 /* In PIO mode, interrupts might still be enabled */
781 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
782
783 //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
784 tasklet_schedule(&host->finish_task);
785 }
786#if 0
787 else if (status & SD_STATUS_DD) {
788
789 /* Sometimes we get a DD before a NE in PIO mode */
790
791 if (!(host->flags & HOST_F_DMA) &&
792 (status & SD_STATUS_NE))
793 au1xmmc_receive_pio(host);
794 else {
795 au1xmmc_data_complete(host, status);
796 //tasklet_schedule(&host->data_task);
797 }
798 }
799#endif
800 else if (status & (SD_STATUS_CR)) {
801 if (host->status == HOST_S_CMD)
802 au1xmmc_cmd_complete(host,status);
803 }
804 else if (!(host->flags & HOST_F_DMA)) {
805 if ((host->flags & HOST_F_XMIT) &&
806 (status & STATUS_DATA_OUT))
807 au1xmmc_send_pio(host);
808 else if ((host->flags & HOST_F_RECV) &&
809 (status & STATUS_DATA_IN))
810 au1xmmc_receive_pio(host);
811 }
812 else if (status & 0x203FBC70) {
813 DEBUG("Unhandled status %8.8x\n", host->id, status);
814 handled = 0;
815 }
816
817 au_writel(status, HOST_STATUS(host));
818 au_sync();
819
820 ret |= handled;
821 }
822
823 enable_irq(AU1100_SD_IRQ);
824 return ret;
825}
826
827static void au1xmmc_poll_event(unsigned long arg)
828{
829 struct au1xmmc_host *host = (struct au1xmmc_host *) arg;
830
831 int card = au1xmmc_card_inserted(host);
832 int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
833
834 if (card != controller) {
835 host->flags &= ~HOST_F_ACTIVE;
836 if (card) host->flags |= HOST_F_ACTIVE;
837 mmc_detect_change(host->mmc, 0);
838 }
839
840 if (host->mrq != NULL) {
841 u32 status = au_readl(HOST_STATUS(host));
842 DEBUG("PENDING - %8.8x\n", host->id, status);
843 }
844
845 mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
846}
847
848static dbdev_tab_t au1xmmc_mem_dbdev =
849{
850 DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0
851};
852
853static void au1xmmc_init_dma(struct au1xmmc_host *host)
854{
855
856 u32 rxchan, txchan;
857
858 int txid = au1xmmc_card_table[host->id].tx_devid;
859 int rxid = au1xmmc_card_table[host->id].rx_devid;
860
861 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
862 of 8 bits. And since devices are shared, we need to create
863 our own to avoid freaking out other devices
864 */
865
866 int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
867
868 txchan = au1xxx_dbdma_chan_alloc(memid, txid,
869 au1xmmc_dma_callback, (void *) host);
870
871 rxchan = au1xxx_dbdma_chan_alloc(rxid, memid,
872 au1xmmc_dma_callback, (void *) host);
873
874 au1xxx_dbdma_set_devwidth(txchan, 8);
875 au1xxx_dbdma_set_devwidth(rxchan, 8);
876
877 au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT);
878 au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT);
879
880 host->tx_chan = txchan;
881 host->rx_chan = rxchan;
882}
883
884struct mmc_host_ops au1xmmc_ops = {
885 .request = au1xmmc_request,
886 .set_ios = au1xmmc_set_ios,
887};
888
889static int au1xmmc_probe(struct device *dev)
890{
891
892 int i, ret = 0;
893
894 /* THe interrupt is shared among all controllers */
895 ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, SA_INTERRUPT, "MMC", 0);
896
897 if (ret) {
898 printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n",
899 AU1100_SD_IRQ, ret);
900 return -ENXIO;
901 }
902
903 disable_irq(AU1100_SD_IRQ);
904
905 for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
906 struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), dev);
907 struct au1xmmc_host *host = 0;
908
909 if (!mmc) {
910 printk(DRIVER_NAME "ERROR: no mem for host %d\n", i);
911 au1xmmc_hosts[i] = 0;
912 continue;
913 }
914
915 mmc->ops = &au1xmmc_ops;
916
917 mmc->f_min = 450000;
918 mmc->f_max = 24000000;
919
920 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
921 mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
922
923 mmc->ocr_avail = AU1XMMC_OCR;
924
925 host = mmc_priv(mmc);
926 host->mmc = mmc;
927
928 host->id = i;
929 host->iobase = au1xmmc_card_table[host->id].iobase;
930 host->clock = 0;
931 host->power_mode = MMC_POWER_OFF;
932
933 host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0;
934 host->status = HOST_S_IDLE;
935
936 init_timer(&host->timer);
937
938 host->timer.function = au1xmmc_poll_event;
939 host->timer.data = (unsigned long) host;
940 host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
941
942 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
943 (unsigned long) host);
944
945 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
946 (unsigned long) host);
947
948 spin_lock_init(&host->lock);
949
950 if (dma != 0)
951 au1xmmc_init_dma(host);
952
953 au1xmmc_reset_controller(host);
954
955 mmc_add_host(mmc);
956 au1xmmc_hosts[i] = host;
957
958 add_timer(&host->timer);
959
960 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n",
961 host->id, host->iobase, dma ? "dma" : "pio");
962 }
963
964 enable_irq(AU1100_SD_IRQ);
965
966 return 0;
967}
968
969static int au1xmmc_remove(struct device *dev)
970{
971
972 int i;
973
974 disable_irq(AU1100_SD_IRQ);
975
976 for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
977 struct au1xmmc_host *host = au1xmmc_hosts[i];
978 if (!host) continue;
979
980 tasklet_kill(&host->data_task);
981 tasklet_kill(&host->finish_task);
982
983 del_timer_sync(&host->timer);
984 au1xmmc_set_power(host, 0);
985
986 mmc_remove_host(host->mmc);
987
988 au1xxx_dbdma_chan_free(host->tx_chan);
989 au1xxx_dbdma_chan_free(host->rx_chan);
990
991 au_writel(0x0, HOST_ENABLE(host));
992 au_sync();
993 }
994
995 free_irq(AU1100_SD_IRQ, 0);
996 return 0;
997}
998
999static struct device_driver au1xmmc_driver = {
1000 .name = DRIVER_NAME,
1001 .bus = &platform_bus_type,
1002 .probe = au1xmmc_probe,
1003 .remove = au1xmmc_remove,
1004 .suspend = NULL,
1005 .resume = NULL
1006};
1007
1008static int __init au1xmmc_init(void)
1009{
1010 return driver_register(&au1xmmc_driver);
1011}
1012
1013static void __exit au1xmmc_exit(void)
1014{
1015 driver_unregister(&au1xmmc_driver);
1016}
1017
1018module_init(au1xmmc_init);
1019module_exit(au1xmmc_exit);
1020
1021#ifdef MODULE
1022MODULE_AUTHOR("Advanced Micro Devices, Inc");
1023MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1024MODULE_LICENSE("GPL");
1025#endif
1026
diff --git a/drivers/mmc/au1xmmc.h b/drivers/mmc/au1xmmc.h
new file mode 100644
index 000000000000..341cbdf0baca
--- /dev/null
+++ b/drivers/mmc/au1xmmc.h
@@ -0,0 +1,96 @@
1#ifndef _AU1XMMC_H_
2#define _AU1XMMC_H_
3
4/* Hardware definitions */
5
6#define AU1XMMC_DESCRIPTOR_COUNT 1
7#define AU1XMMC_DESCRIPTOR_SIZE 2048
8
9#define AU1XMMC_OCR ( MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
10 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
11 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
12
13/* Easy access macros */
14
15#define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
16#define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
17#define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
18#define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
19#define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
20#define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
21#define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
22#define HOST_CMD(h) ((h)->iobase + SD_CMD)
23#define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
24#define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
25#define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
26
27#define DMA_CHANNEL(h) \
28 ( ((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
29
30/* This gives us a hard value for the stop command that we can write directly
31 * to the command register
32 */
33
34#define STOP_CMD (SD_CMD_RT_1B|SD_CMD_CT_7|(0xC << SD_CMD_CI_SHIFT)|SD_CMD_GO)
35
36/* This is the set of interrupts that we configure by default */
37
38#if 0
39#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_DD | \
40 SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I)
41#endif
42
43#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | \
44 SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I)
45/* The poll event (looking for insert/remove events runs twice a second */
46#define AU1XMMC_DETECT_TIMEOUT (HZ/2)
47
48struct au1xmmc_host {
49 struct mmc_host *mmc;
50 struct mmc_request *mrq;
51
52 u32 id;
53
54 u32 flags;
55 u32 iobase;
56 u32 clock;
57 u32 bus_width;
58 u32 power_mode;
59
60 int status;
61
62 struct {
63 int len;
64 int dir;
65 } dma;
66
67 struct {
68 int index;
69 int offset;
70 int len;
71 } pio;
72
73 u32 tx_chan;
74 u32 rx_chan;
75
76 struct timer_list timer;
77 struct tasklet_struct finish_task;
78 struct tasklet_struct data_task;
79
80 spinlock_t lock;
81};
82
83/* Status flags used by the host structure */
84
85#define HOST_F_XMIT 0x0001
86#define HOST_F_RECV 0x0002
87#define HOST_F_DMA 0x0010
88#define HOST_F_ACTIVE 0x0100
89#define HOST_F_STOP 0x1000
90
91#define HOST_S_IDLE 0x0001
92#define HOST_S_CMD 0x0002
93#define HOST_S_DATA 0x0003
94#define HOST_S_STOP 0x0004
95
96#endif
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index a41fbb38fdcb..77ecee7f987b 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -42,9 +42,11 @@ pxa2xx_core-y += soc_common.o pxa2xx_base.o
42au1x00_ss-y += au1000_generic.o 42au1x00_ss-y += au1000_generic.o
43au1x00_ss-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o 43au1x00_ss-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o
44au1x00_ss-$(CONFIG_MIPS_PB1100) += au1000_pb1x00.o 44au1x00_ss-$(CONFIG_MIPS_PB1100) += au1000_pb1x00.o
45au1x00_ss-$(CONFIG_MIPS_PB1200) += au1000_db1x00.o
45au1x00_ss-$(CONFIG_MIPS_PB1500) += au1000_pb1x00.o 46au1x00_ss-$(CONFIG_MIPS_PB1500) += au1000_pb1x00.o
46au1x00_ss-$(CONFIG_MIPS_DB1000) += au1000_db1x00.o 47au1x00_ss-$(CONFIG_MIPS_DB1000) += au1000_db1x00.o
47au1x00_ss-$(CONFIG_MIPS_DB1100) += au1000_db1x00.o 48au1x00_ss-$(CONFIG_MIPS_DB1100) += au1000_db1x00.o
49au1x00_ss-$(CONFIG_MIPS_DB1200) += au1000_db1x00.o
48au1x00_ss-$(CONFIG_MIPS_DB1500) += au1000_db1x00.o 50au1x00_ss-$(CONFIG_MIPS_DB1500) += au1000_db1x00.o
49au1x00_ss-$(CONFIG_MIPS_DB1550) += au1000_db1x00.o 51au1x00_ss-$(CONFIG_MIPS_DB1550) += au1000_db1x00.o
50au1x00_ss-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o 52au1x00_ss-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o
diff --git a/drivers/pcmcia/au1000_db1x00.c b/drivers/pcmcia/au1000_db1x00.c
index 42cf8bfbcc98..24cfee1a412c 100644
--- a/drivers/pcmcia/au1000_db1x00.c
+++ b/drivers/pcmcia/au1000_db1x00.c
@@ -40,7 +40,15 @@
40#include <asm/irq.h> 40#include <asm/irq.h>
41#include <asm/signal.h> 41#include <asm/signal.h>
42#include <asm/mach-au1x00/au1000.h> 42#include <asm/mach-au1x00/au1000.h>
43#include <asm/mach-db1x00/db1x00.h> 43
44#if defined(CONFIG_MIPS_DB1200)
45 #include <db1200.h>
46#elif defined(CONFIG_MIPS_PB1200)
47 #include <pb1200.h>
48#else
49 #include <asm/mach-db1x00/db1x00.h>
50 static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
51#endif
44 52
45#include "au1000_generic.h" 53#include "au1000_generic.h"
46 54
@@ -50,7 +58,6 @@
50#define debug(x,args...) 58#define debug(x,args...)
51#endif 59#endif
52 60
53static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
54 61
55struct au1000_pcmcia_socket au1000_pcmcia_socket[PCMCIA_NUM_SOCKS]; 62struct au1000_pcmcia_socket au1000_pcmcia_socket[PCMCIA_NUM_SOCKS];
56extern int au1x00_pcmcia_socket_probe(struct device *, struct pcmcia_low_level *, int, int); 63extern int au1x00_pcmcia_socket_probe(struct device *, struct pcmcia_low_level *, int, int);
@@ -59,6 +66,8 @@ static int db1x00_pcmcia_hw_init(struct au1000_pcmcia_socket *skt)
59{ 66{
60#ifdef CONFIG_MIPS_DB1550 67#ifdef CONFIG_MIPS_DB1550
61 skt->irq = skt->nr ? AU1000_GPIO_5 : AU1000_GPIO_3; 68 skt->irq = skt->nr ? AU1000_GPIO_5 : AU1000_GPIO_3;
69#elif defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200)
70 skt->irq = skt->nr ? BOARD_PC1_INT : BOARD_PC0_INT;
62#else 71#else
63 skt->irq = skt->nr ? AU1000_GPIO_5 : AU1000_GPIO_2; 72 skt->irq = skt->nr ? AU1000_GPIO_5 : AU1000_GPIO_2;
64#endif 73#endif
@@ -85,11 +94,19 @@ db1x00_pcmcia_socket_state(struct au1000_pcmcia_socket *skt, struct pcmcia_state
85 switch (skt->nr) { 94 switch (skt->nr) {
86 case 0: 95 case 0:
87 vs = bcsr->status & 0x3; 96 vs = bcsr->status & 0x3;
97#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200)
98 inserted = BOARD_CARD_INSERTED(0);
99#else
88 inserted = !(bcsr->status & (1<<4)); 100 inserted = !(bcsr->status & (1<<4));
101#endif
89 break; 102 break;
90 case 1: 103 case 1:
91 vs = (bcsr->status & 0xC)>>2; 104 vs = (bcsr->status & 0xC)>>2;
105#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200)
106 inserted = BOARD_CARD_INSERTED(1);
107#else
92 inserted = !(bcsr->status & (1<<5)); 108 inserted = !(bcsr->status & (1<<5));
109#endif
93 break; 110 break;
94 default:/* should never happen */ 111 default:/* should never happen */
95 return; 112 return;
diff --git a/drivers/pcmcia/au1000_generic.c b/drivers/pcmcia/au1000_generic.c
index d90a634cebf5..ba48cef3a9dc 100644
--- a/drivers/pcmcia/au1000_generic.c
+++ b/drivers/pcmcia/au1000_generic.c
@@ -490,7 +490,7 @@ int au1x00_drv_pcmcia_remove(struct device *dev)
490 flush_scheduled_work(); 490 flush_scheduled_work();
491 skt->ops->hw_shutdown(skt); 491 skt->ops->hw_shutdown(skt);
492 au1x00_pcmcia_config_skt(skt, &dead_socket); 492 au1x00_pcmcia_config_skt(skt, &dead_socket);
493 iounmap(skt->virt_io); 493 iounmap(skt->virt_io + (u32)mips_io_port_base);
494 skt->virt_io = NULL; 494 skt->virt_io = NULL;
495 } 495 }
496 496
@@ -528,10 +528,6 @@ static struct device_driver au1x00_pcmcia_driver = {
528 .resume = pcmcia_socket_dev_resume, 528 .resume = pcmcia_socket_dev_resume,
529}; 529};
530 530
531static struct platform_device au1x00_device = {
532 .name = "au1x00-pcmcia",
533 .id = 0,
534};
535 531
536/* au1x00_pcmcia_init() 532/* au1x00_pcmcia_init()
537 * 533 *
@@ -545,7 +541,6 @@ static int __init au1x00_pcmcia_init(void)
545 int error = 0; 541 int error = 0;
546 if ((error = driver_register(&au1x00_pcmcia_driver))) 542 if ((error = driver_register(&au1x00_pcmcia_driver)))
547 return error; 543 return error;
548 platform_device_register(&au1x00_device);
549 return error; 544 return error;
550} 545}
551 546
@@ -556,7 +551,6 @@ static int __init au1x00_pcmcia_init(void)
556static void __exit au1x00_pcmcia_exit(void) 551static void __exit au1x00_pcmcia_exit(void)
557{ 552{
558 driver_unregister(&au1x00_pcmcia_driver); 553 driver_unregister(&au1x00_pcmcia_driver);
559 platform_device_unregister(&au1x00_device);
560} 554}
561 555
562module_init(au1x00_pcmcia_init); 556module_init(au1x00_pcmcia_init);
diff --git a/drivers/pcmcia/au1000_generic.h b/drivers/pcmcia/au1000_generic.h
index d5122b1ea94b..b0e7908392a7 100644
--- a/drivers/pcmcia/au1000_generic.h
+++ b/drivers/pcmcia/au1000_generic.h
@@ -44,13 +44,13 @@
44/* pcmcia socket 1 needs external glue logic so the memory map 44/* pcmcia socket 1 needs external glue logic so the memory map
45 * differs from board to board. 45 * differs from board to board.
46 */ 46 */
47#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1550) 47#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_PB1200)
48#define AU1X_SOCK1_IO 0xF08000000 48#define AU1X_SOCK1_IO 0xF08000000
49#define AU1X_SOCK1_PHYS_ATTR 0xF48000000 49#define AU1X_SOCK1_PHYS_ATTR 0xF48000000
50#define AU1X_SOCK1_PHYS_MEM 0xF88000000 50#define AU1X_SOCK1_PHYS_MEM 0xF88000000
51#define AU1X_SOCK1_PSEUDO_PHYS_ATTR 0xF4800000 51#define AU1X_SOCK1_PSEUDO_PHYS_ATTR 0xF4800000
52#define AU1X_SOCK1_PSEUDO_PHYS_MEM 0xF8800000 52#define AU1X_SOCK1_PSEUDO_PHYS_MEM 0xF8800000
53#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) 53#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) || defined(CONFIG_MIPS_DB1200)
54#define AU1X_SOCK1_IO 0xF04000000 54#define AU1X_SOCK1_IO 0xF04000000
55#define AU1X_SOCK1_PHYS_ATTR 0xF44000000 55#define AU1X_SOCK1_PHYS_ATTR 0xF44000000
56#define AU1X_SOCK1_PHYS_MEM 0xF84000000 56#define AU1X_SOCK1_PHYS_MEM 0xF84000000
diff --git a/drivers/scsi/dec_esp.c b/drivers/scsi/dec_esp.c
index 315f95a0d6c0..4f39890b44ac 100644
--- a/drivers/scsi/dec_esp.c
+++ b/drivers/scsi/dec_esp.c
@@ -228,7 +228,7 @@ static int dec_esp_detect(Scsi_Host_Template * tpnt)
228 mem_start = get_tc_base_addr(slot); 228 mem_start = get_tc_base_addr(slot);
229 229
230 /* Store base addr into esp struct */ 230 /* Store base addr into esp struct */
231 esp->slot = PHYSADDR(mem_start); 231 esp->slot = CPHYSADDR(mem_start);
232 232
233 esp->dregs = 0; 233 esp->dregs = 0;
234 esp->eregs = (struct ESP_regs *) (mem_start + DEC_SCSI_SREG); 234 esp->eregs = (struct ESP_regs *) (mem_start + DEC_SCSI_SREG);
diff --git a/drivers/tc/tc.c b/drivers/tc/tc.c
index a89ef4df80c3..a0e5af638e0e 100644
--- a/drivers/tc/tc.c
+++ b/drivers/tc/tc.c
@@ -8,33 +8,31 @@
8 * for more details. 8 * for more details.
9 * 9 *
10 * Copyright (c) Harald Koerfgen, 1998 10 * Copyright (c) Harald Koerfgen, 1998
11 * Copyright (c) 2001, 2003 Maciej W. Rozycki 11 * Copyright (c) 2001, 2003, 2005 Maciej W. Rozycki
12 */ 12 */
13#include <linux/string.h>
14#include <linux/init.h> 13#include <linux/init.h>
15#include <linux/ioport.h>
16#include <linux/kernel.h> 14#include <linux/kernel.h>
17#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/types.h>
18 18
19#include <asm/addrspace.h> 19#include <asm/addrspace.h>
20#include <asm/bug.h>
20#include <asm/errno.h> 21#include <asm/errno.h>
22#include <asm/io.h>
23#include <asm/paccess.h>
24
21#include <asm/dec/machtype.h> 25#include <asm/dec/machtype.h>
22#include <asm/dec/prom.h> 26#include <asm/dec/prom.h>
23#include <asm/dec/tcinfo.h> 27#include <asm/dec/tcinfo.h>
24#include <asm/dec/tcmodule.h> 28#include <asm/dec/tcmodule.h>
25#include <asm/dec/interrupts.h> 29#include <asm/dec/interrupts.h>
26#include <asm/paccess.h>
27#include <asm/ptrace.h>
28
29#define TC_DEBUG
30 30
31MODULE_LICENSE("GPL"); 31MODULE_LICENSE("GPL");
32slot_info tc_bus[MAX_SLOT]; 32slot_info tc_bus[MAX_SLOT];
33static int num_tcslots; 33static int num_tcslots;
34static tcinfo *info; 34static tcinfo *info;
35 35
36unsigned long system_base;
37
38/* 36/*
39 * Interface to the world. Read comment in include/asm-mips/tc.h. 37 * Interface to the world. Read comment in include/asm-mips/tc.h.
40 */ 38 */
@@ -97,13 +95,16 @@ unsigned long get_tc_speed(void)
97static void __init tc_probe(unsigned long startaddr, unsigned long size, 95static void __init tc_probe(unsigned long startaddr, unsigned long size,
98 int slots) 96 int slots)
99{ 97{
98 unsigned long slotaddr;
100 int i, slot, err; 99 int i, slot, err;
101 long offset; 100 long offset;
102 unsigned char pattern[4]; 101 u8 pattern[4];
103 unsigned char *module; 102 volatile u8 *module;
104 103
105 for (slot = 0; slot < slots; slot++) { 104 for (slot = 0; slot < slots; slot++) {
106 module = (char *)(startaddr + slot * size); 105 slotaddr = startaddr + slot * size;
106 module = ioremap_nocache(slotaddr, size);
107 BUG_ON(!module);
107 108
108 offset = OLDCARD; 109 offset = OLDCARD;
109 110
@@ -112,8 +113,10 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
112 err |= get_dbe(pattern[1], module + OLDCARD + TC_PATTERN1); 113 err |= get_dbe(pattern[1], module + OLDCARD + TC_PATTERN1);
113 err |= get_dbe(pattern[2], module + OLDCARD + TC_PATTERN2); 114 err |= get_dbe(pattern[2], module + OLDCARD + TC_PATTERN2);
114 err |= get_dbe(pattern[3], module + OLDCARD + TC_PATTERN3); 115 err |= get_dbe(pattern[3], module + OLDCARD + TC_PATTERN3);
115 if (err) 116 if (err) {
117 iounmap(module);
116 continue; 118 continue;
119 }
117 120
118 if (pattern[0] != 0x55 || pattern[1] != 0x00 || 121 if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
119 pattern[2] != 0xaa || pattern[3] != 0xff) { 122 pattern[2] != 0xaa || pattern[3] != 0xff) {
@@ -124,16 +127,20 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
124 err |= get_dbe(pattern[1], module + TC_PATTERN1); 127 err |= get_dbe(pattern[1], module + TC_PATTERN1);
125 err |= get_dbe(pattern[2], module + TC_PATTERN2); 128 err |= get_dbe(pattern[2], module + TC_PATTERN2);
126 err |= get_dbe(pattern[3], module + TC_PATTERN3); 129 err |= get_dbe(pattern[3], module + TC_PATTERN3);
127 if (err) 130 if (err) {
131 iounmap(module);
128 continue; 132 continue;
133 }
129 } 134 }
130 135
131 if (pattern[0] != 0x55 || pattern[1] != 0x00 || 136 if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
132 pattern[2] != 0xaa || pattern[3] != 0xff) 137 pattern[2] != 0xaa || pattern[3] != 0xff) {
138 iounmap(module);
133 continue; 139 continue;
140 }
134 141
135 tc_bus[slot].base_addr = (unsigned long)module; 142 tc_bus[slot].base_addr = slotaddr;
136 for(i = 0; i < 8; i++) { 143 for (i = 0; i < 8; i++) {
137 tc_bus[slot].firmware[i] = 144 tc_bus[slot].firmware[i] =
138 module[TC_FIRM_VER + offset + 4 * i]; 145 module[TC_FIRM_VER + offset + 4 * i];
139 tc_bus[slot].vendor[i] = 146 tc_bus[slot].vendor[i] =
@@ -171,13 +178,15 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
171 tc_bus[slot].interrupt = -1; 178 tc_bus[slot].interrupt = -1;
172 break; 179 break;
173 } 180 }
181
182 iounmap(module);
174 } 183 }
175} 184}
176 185
177/* 186/*
178 * the main entry 187 * the main entry
179 */ 188 */
180void __init tc_init(void) 189static int __init tc_init(void)
181{ 190{
182 int tc_clock; 191 int tc_clock;
183 int i; 192 int i;
@@ -185,7 +194,7 @@ void __init tc_init(void)
185 unsigned long slot_size; 194 unsigned long slot_size;
186 195
187 if (!TURBOCHANNEL) 196 if (!TURBOCHANNEL)
188 return; 197 return 0;
189 198
190 for (i = 0; i < MAX_SLOT; i++) { 199 for (i = 0; i < MAX_SLOT; i++) {
191 tc_bus[i].base_addr = 0; 200 tc_bus[i].base_addr = 0;
@@ -196,8 +205,8 @@ void __init tc_init(void)
196 tc_bus[i].flags = FREE; 205 tc_bus[i].flags = FREE;
197 } 206 }
198 207
199 info = (tcinfo *) rex_gettcinfo(); 208 info = rex_gettcinfo();
200 slot0addr = (unsigned long)KSEG1ADDR(rex_slot_address(0)); 209 slot0addr = CPHYSADDR((long)rex_slot_address(0));
201 210
202 switch (mips_machtype) { 211 switch (mips_machtype) {
203 case MACH_DS5000_200: 212 case MACH_DS5000_200:
@@ -216,37 +225,24 @@ void __init tc_init(void)
216 225
217 tc_clock = 10000 / info->clk_period; 226 tc_clock = 10000 / info->clk_period;
218 227
219 if (TURBOCHANNEL && info->slot_size && slot0addr) { 228 if (info->slot_size && slot0addr) {
220 printk("TURBOchannel rev. %1d at %2d.%1d MHz ", info->revision, 229 pr_info("TURBOchannel rev. %d at %d.%d MHz (with%s parity)\n",
221 tc_clock / 10, tc_clock % 10); 230 info->revision, tc_clock / 10, tc_clock % 10,
222 printk("(with%s parity)\n", info->parity ? "" : "out"); 231 info->parity ? "" : "out");
223 232
224 slot_size = info->slot_size << 20; 233 slot_size = info->slot_size << 20;
225 234
226 tc_probe(slot0addr, slot_size, num_tcslots); 235 tc_probe(slot0addr, slot_size, num_tcslots);
227 236
228 /* 237 for (i = 0; i < num_tcslots; i++) {
229 * All TURBOchannel DECstations have the onboard devices 238 if (!tc_bus[i].base_addr)
230 * where the (num_tcslots + 0 or 1 on DS5k/xx) Option Module 239 continue;
231 * would be. 240 pr_info(" slot %d: %s %s %s\n", i, tc_bus[i].vendor,
232 */ 241 tc_bus[i].name, tc_bus[i].firmware);
233 if(mips_machtype == MACH_DS5000_XX) 242 }
234 i = 1;
235 else
236 i = 0;
237
238 system_base = slot0addr + slot_size * (num_tcslots + i);
239
240#ifdef TC_DEBUG
241 for (i = 0; i < num_tcslots; i++)
242 if (tc_bus[i].base_addr) {
243 printk(" slot %d: ", i);
244 printk("%s %s %s\n", tc_bus[i].vendor,
245 tc_bus[i].name, tc_bus[i].firmware);
246 }
247#endif
248 ioport_resource.end = KSEG2 - 1;
249 } 243 }
244
245 return 0;
250} 246}
251 247
252subsys_initcall(tc_init); 248subsys_initcall(tc_init);
@@ -257,4 +253,3 @@ EXPORT_SYMBOL(release_tc_card);
257EXPORT_SYMBOL(get_tc_base_addr); 253EXPORT_SYMBOL(get_tc_base_addr);
258EXPORT_SYMBOL(get_tc_irq_nr); 254EXPORT_SYMBOL(get_tc_irq_nr);
259EXPORT_SYMBOL(get_tc_speed); 255EXPORT_SYMBOL(get_tc_speed);
260EXPORT_SYMBOL(system_base);
diff --git a/drivers/tc/zs.c b/drivers/tc/zs.c
index 6bed8713897e..c52af73a251b 100644
--- a/drivers/tc/zs.c
+++ b/drivers/tc/zs.c
@@ -65,14 +65,14 @@
65#include <asm/system.h> 65#include <asm/system.h>
66#include <asm/uaccess.h> 66#include <asm/uaccess.h>
67#include <asm/bootinfo.h> 67#include <asm/bootinfo.h>
68#include <asm/dec/serial.h>
69 68
70#ifdef CONFIG_MACH_DECSTATION
71#include <asm/dec/interrupts.h> 69#include <asm/dec/interrupts.h>
70#include <asm/dec/ioasic_addrs.h>
72#include <asm/dec/machtype.h> 71#include <asm/dec/machtype.h>
72#include <asm/dec/serial.h>
73#include <asm/dec/system.h>
73#include <asm/dec/tc.h> 74#include <asm/dec/tc.h>
74#include <asm/dec/ioasic_addrs.h> 75
75#endif
76#ifdef CONFIG_KGDB 76#ifdef CONFIG_KGDB
77#include <asm/kgdb.h> 77#include <asm/kgdb.h>
78#endif 78#endif
@@ -192,18 +192,6 @@ static void probe_sccs(void);
192static void change_speed(struct dec_serial *info); 192static void change_speed(struct dec_serial *info);
193static void rs_wait_until_sent(struct tty_struct *tty, int timeout); 193static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
194 194
195/*
196 * tmp_buf is used as a temporary buffer by serial_write. We need to
197 * lock it in case the copy_from_user blocks while swapping in a page,
198 * and some other program tries to do a serial write at the same time.
199 * Since the lock will only come under contention when the system is
200 * swapping and available memory is low, it makes sense to share one
201 * buffer across all the serial ports, since it significantly saves
202 * memory if large numbers of serial ports are open.
203 */
204static unsigned char tmp_buf[4096]; /* This is cheating */
205static DECLARE_MUTEX(tmp_buf_sem);
206
207static inline int serial_paranoia_check(struct dec_serial *info, 195static inline int serial_paranoia_check(struct dec_serial *info,
208 char *name, const char *routine) 196 char *name, const char *routine)
209{ 197{
@@ -1628,30 +1616,22 @@ static void __init probe_sccs(void)
1628 return; 1616 return;
1629 } 1617 }
1630 1618
1631 /*
1632 * When serial console is activated, tc_init has not been called yet
1633 * and system_base is undefined. Unfortunately we have to hardcode
1634 * system_base for this case :-(. HK
1635 */
1636 switch(mips_machtype) { 1619 switch(mips_machtype) {
1637#ifdef CONFIG_MACH_DECSTATION 1620#ifdef CONFIG_MACH_DECSTATION
1638 case MACH_DS5000_2X0: 1621 case MACH_DS5000_2X0:
1639 case MACH_DS5900: 1622 case MACH_DS5900:
1640 system_base = KSEG1ADDR(0x1f800000);
1641 n_chips = 2; 1623 n_chips = 2;
1642 zs_parms = &ds_parms; 1624 zs_parms = &ds_parms;
1643 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; 1625 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
1644 zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1]; 1626 zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
1645 break; 1627 break;
1646 case MACH_DS5000_1XX: 1628 case MACH_DS5000_1XX:
1647 system_base = KSEG1ADDR(0x1c000000);
1648 n_chips = 2; 1629 n_chips = 2;
1649 zs_parms = &ds_parms; 1630 zs_parms = &ds_parms;
1650 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; 1631 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
1651 zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1]; 1632 zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
1652 break; 1633 break;
1653 case MACH_DS5000_XX: 1634 case MACH_DS5000_XX:
1654 system_base = KSEG1ADDR(0x1c000000);
1655 n_chips = 1; 1635 n_chips = 1;
1656 zs_parms = &ds_parms; 1636 zs_parms = &ds_parms;
1657 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; 1637 zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
@@ -1673,10 +1653,10 @@ static void __init probe_sccs(void)
1673 * The sccs reside on the high byte of the 16 bit IOBUS 1653 * The sccs reside on the high byte of the 16 bit IOBUS
1674 */ 1654 */
1675 zs_channels[n_channels].control = 1655 zs_channels[n_channels].control =
1676 (volatile unsigned char *)system_base + 1656 (volatile void *)CKSEG1ADDR(dec_kn_slot_base +
1677 (0 == chip ? zs_parms->scc0 : zs_parms->scc1) + 1657 (0 == chip ? zs_parms->scc0 : zs_parms->scc1) +
1678 (0 == channel ? zs_parms->channel_a_offset : 1658 (0 == channel ? zs_parms->channel_a_offset :
1679 zs_parms->channel_b_offset); 1659 zs_parms->channel_b_offset));
1680 zs_channels[n_channels].data = 1660 zs_channels[n_channels].data =
1681 zs_channels[n_channels].control + 4; 1661 zs_channels[n_channels].control + 4;
1682 1662
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1cd942abb580..7e297947a2b2 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1376,7 +1376,7 @@ config FB_HIT
1376 1376
1377config FB_PMAG_AA 1377config FB_PMAG_AA
1378 bool "PMAG-AA TURBOchannel framebuffer support" 1378 bool "PMAG-AA TURBOchannel framebuffer support"
1379 depends on (FB = y) && MACH_DECSTATION && TC 1379 depends on (FB = y) && TC
1380 select FB_CFB_FILLRECT 1380 select FB_CFB_FILLRECT
1381 select FB_CFB_COPYAREA 1381 select FB_CFB_COPYAREA
1382 select FB_CFB_IMAGEBLIT 1382 select FB_CFB_IMAGEBLIT
@@ -1387,7 +1387,7 @@ config FB_PMAG_AA
1387 1387
1388config FB_PMAG_BA 1388config FB_PMAG_BA
1389 bool "PMAG-BA TURBOchannel framebuffer support" 1389 bool "PMAG-BA TURBOchannel framebuffer support"
1390 depends on (FB = y) && MACH_DECSTATION && TC 1390 depends on (FB = y) && TC
1391 select FB_CFB_FILLRECT 1391 select FB_CFB_FILLRECT
1392 select FB_CFB_COPYAREA 1392 select FB_CFB_COPYAREA
1393 select FB_CFB_IMAGEBLIT 1393 select FB_CFB_IMAGEBLIT
@@ -1398,7 +1398,7 @@ config FB_PMAG_BA
1398 1398
1399config FB_PMAGB_B 1399config FB_PMAGB_B
1400 bool "PMAGB-B TURBOchannel framebuffer support" 1400 bool "PMAGB-B TURBOchannel framebuffer support"
1401 depends on (FB = y) && MACH_DECSTATION && TC 1401 depends on (FB = y) && TC
1402 select FB_CFB_FILLRECT 1402 select FB_CFB_FILLRECT
1403 select FB_CFB_COPYAREA 1403 select FB_CFB_COPYAREA
1404 select FB_CFB_IMAGEBLIT 1404 select FB_CFB_IMAGEBLIT
@@ -1410,7 +1410,7 @@ config FB_PMAGB_B
1410 1410
1411config FB_MAXINE 1411config FB_MAXINE
1412 bool "Maxine (Personal DECstation) onboard framebuffer support" 1412 bool "Maxine (Personal DECstation) onboard framebuffer support"
1413 depends on (FB = y) && MACH_DECSTATION && TC 1413 depends on (FB = y) && MACH_DECSTATION
1414 select FB_CFB_FILLRECT 1414 select FB_CFB_FILLRECT
1415 select FB_CFB_COPYAREA 1415 select FB_CFB_COPYAREA
1416 select FB_CFB_IMAGEBLIT 1416 select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 1fff29f48ca8..97c5d03ac8d9 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -86,7 +86,7 @@ obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o
86obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o 86obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o
87obj-$(CONFIG_FB_PXA) += pxafb.o 87obj-$(CONFIG_FB_PXA) += pxafb.o
88obj-$(CONFIG_FB_W100) += w100fb.o 88obj-$(CONFIG_FB_W100) += w100fb.o
89obj-$(CONFIG_FB_AU1100) += au1100fb.o fbgen.o 89obj-$(CONFIG_FB_AU1100) += au1100fb.o
90obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o 90obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o
91obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o 91obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o
92obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o 92obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o
diff --git a/drivers/video/au1100fb.c b/drivers/video/au1100fb.c
index b6fe30c3ad62..a5129806172f 100644
--- a/drivers/video/au1100fb.c
+++ b/drivers/video/au1100fb.c
@@ -2,6 +2,11 @@
2 * BRIEF MODULE DESCRIPTION 2 * BRIEF MODULE DESCRIPTION
3 * Au1100 LCD Driver. 3 * Au1100 LCD Driver.
4 * 4 *
5 * Rewritten for 2.6 by Embedded Alley Solutions
6 * <source@embeddedalley.com>, based on submissions by
7 * Karl Lessard <klessard@sunrisetelecom.com>
8 * <c.pellegrin@exadron.com>
9 *
5 * Copyright 2002 MontaVista Software 10 * Copyright 2002 MontaVista Software
6 * Author: MontaVista Software, Inc. 11 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com 12 * ppopov@mvista.com or source@mvista.com
@@ -33,298 +38,253 @@
33 * with this program; if not, write to the Free Software Foundation, Inc., 38 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA. 39 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */ 40 */
36 41#include <linux/config.h>
37#include <linux/module.h> 42#include <linux/module.h>
38#include <linux/kernel.h> 43#include <linux/kernel.h>
39#include <linux/errno.h> 44#include <linux/errno.h>
40#include <linux/string.h> 45#include <linux/string.h>
41#include <linux/mm.h> 46#include <linux/mm.h>
42#include <linux/tty.h>
43#include <linux/slab.h>
44#include <linux/delay.h>
45#include <linux/fb.h> 47#include <linux/fb.h>
46#include <linux/init.h> 48#include <linux/init.h>
47#include <linux/pci.h> 49#include <linux/interrupt.h>
50#include <linux/ctype.h>
51#include <linux/dma-mapping.h>
48 52
49#include <asm/au1000.h> 53#include <asm/mach-au1x00/au1000.h>
50#include <asm/pb1100.h>
51#include "au1100fb.h"
52 54
53#include <video/fbcon.h> 55#define DEBUG 0
54#include <video/fbcon-mfb.h> 56
55#include <video/fbcon-cfb2.h> 57#include "au1100fb.h"
56#include <video/fbcon-cfb4.h>
57#include <video/fbcon-cfb8.h>
58#include <video/fbcon-cfb16.h>
59 58
60/* 59/*
61 * Sanity check. If this is a new Au1100 based board, search for 60 * Sanity check. If this is a new Au1100 based board, search for
62 * the PB1100 ifdefs to make sure you modify the code accordingly. 61 * the PB1100 ifdefs to make sure you modify the code accordingly.
63 */ 62 */
64#if defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_HYDROGEN3) 63#if defined(CONFIG_MIPS_PB1100)
64 #include <asm/mach-pb1x00/pb1100.h>
65#elif defined(CONFIG_MIPS_DB1100)
66 #include <asm/mach-db1x00/db1x00.h>
65#else 67#else
66error Unknown Au1100 board 68 #error "Unknown Au1100 board, Au1100 FB driver not supported"
67#endif 69#endif
68 70
69#define CMAPSIZE 16 71#define DRIVER_NAME "au1100fb"
70 72#define DRIVER_DESC "LCD controller driver for AU1100 processors"
71static int my_lcd_index; /* default is zero */
72struct known_lcd_panels *p_lcd;
73AU1100_LCD *p_lcd_reg = (AU1100_LCD *)AU1100_LCD_ADDR;
74
75struct au1100fb_info {
76 struct fb_info_gen gen;
77 unsigned long fb_virt_start;
78 unsigned long fb_size;
79 unsigned long fb_phys;
80 int mmaped;
81 int nohwcursor;
82 73
83 struct { unsigned red, green, blue, pad; } palette[256]; 74#define to_au1100fb_device(_info) \
75 (_info ? container_of(_info, struct au1100fb_device, info) : NULL);
84 76
85#if defined(FBCON_HAS_CFB16) 77/* Bitfields format supported by the controller. Note that the order of formats
86 u16 fbcon_cmap16[16]; 78 * SHOULD be the same as in the LCD_CONTROL_SBPPF field, so we can retrieve the
87#endif 79 * right pixel format by doing rgb_bitfields[LCD_CONTROL_SBPPF_XXX >> LCD_CONTROL_SBPPF]
80 */
81struct fb_bitfield rgb_bitfields[][4] =
82{
83 /* Red, Green, Blue, Transp */
84 { { 10, 6, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
85 { { 11, 5, 0 }, { 5, 6, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
86 { { 11, 5, 0 }, { 6, 5, 0 }, { 0, 6, 0 }, { 0, 0, 0 } },
87 { { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 15, 1, 0 } },
88 { { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 1, 0 } },
89
90 /* The last is used to describe 12bpp format */
91 { { 8, 4, 0 }, { 4, 4, 0 }, { 0, 4, 0 }, { 0, 0, 0 } },
88}; 92};
89 93
90 94static struct fb_fix_screeninfo au1100fb_fix __initdata = {
91struct au1100fb_par { 95 .id = "AU1100 FB",
92 struct fb_var_screeninfo var; 96 .xpanstep = 1,
93 97 .ypanstep = 1,
94 int line_length; // in bytes 98 .type = FB_TYPE_PACKED_PIXELS,
95 int cmap_len; // color-map length 99 .accel = FB_ACCEL_NONE,
96}; 100};
97 101
98 102static struct fb_var_screeninfo au1100fb_var __initdata = {
99static struct au1100fb_info fb_info; 103 .activate = FB_ACTIVATE_NOW,
100static struct au1100fb_par current_par; 104 .height = -1,
101static struct display disp; 105 .width = -1,
102 106 .vmode = FB_VMODE_NONINTERLACED,
103int au1100fb_init(void);
104void au1100fb_setup(char *options, int *ints);
105static int au1100fb_mmap(struct fb_info *fb, struct file *file,
106 struct vm_area_struct *vma);
107static int au1100_blank(int blank_mode, struct fb_info_gen *info);
108static int au1100fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
109 u_long arg, int con, struct fb_info *info);
110
111void au1100_nocursor(struct display *p, int mode, int xx, int yy){};
112
113static struct fb_ops au1100fb_ops = {
114 .owner = THIS_MODULE,
115 .fb_get_fix = fbgen_get_fix,
116 .fb_get_var = fbgen_get_var,
117 .fb_set_var = fbgen_set_var,
118 .fb_get_cmap = fbgen_get_cmap,
119 .fb_set_cmap = fbgen_set_cmap,
120 .fb_pan_display = fbgen_pan_display,
121 .fb_ioctl = au1100fb_ioctl,
122 .fb_mmap = au1100fb_mmap,
123}; 107};
124 108
125static void au1100_detect(void) 109static struct au1100fb_drv_info drv_info;
126{
127 /*
128 * This function should detect the current video mode settings
129 * and store it as the default video mode
130 */
131 110
132 /* 111/*
133 * Yeh, well, we're not going to change any settings so we're 112 * Set hardware with var settings. This will enable the controller with a specific
134 * always stuck with the default ... 113 * mode, normally validated with the fb_check_var method
135 */ 114 */
136 115int au1100fb_setmode(struct au1100fb_device *fbdev)
137}
138
139static int au1100_encode_fix(struct fb_fix_screeninfo *fix,
140 const void *_par, struct fb_info_gen *_info)
141{ 116{
142 struct au1100fb_info *info = (struct au1100fb_info *) _info; 117 struct fb_info *info = &fbdev->info;
143 struct au1100fb_par *par = (struct au1100fb_par *) _par; 118 u32 words;
144 struct fb_var_screeninfo *var = &par->var; 119 int index;
145
146 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
147
148 fix->smem_start = info->fb_phys;
149 fix->smem_len = info->fb_size;
150 fix->type = FB_TYPE_PACKED_PIXELS;
151 fix->type_aux = 0;
152 fix->visual = (var->bits_per_pixel == 8) ?
153 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
154 fix->ywrapstep = 0;
155 fix->xpanstep = 1;
156 fix->ypanstep = 1;
157 fix->line_length = current_par.line_length;
158 return 0;
159}
160 120
161static void set_color_bitfields(struct fb_var_screeninfo *var) 121 if (!fbdev)
162{ 122 return -EINVAL;
163 switch (var->bits_per_pixel) { 123
164 case 8: 124 /* Update var-dependent FB info */
165 var->red.offset = 0; 125 if (panel_is_active(fbdev->panel) || panel_is_color(fbdev->panel)) {
166 var->red.length = 8; 126 if (info->var.bits_per_pixel <= 8) {
167 var->green.offset = 0; 127 /* palettized */
168 var->green.length = 8; 128 info->var.red.offset = 0;
169 var->blue.offset = 0; 129 info->var.red.length = info->var.bits_per_pixel;
170 var->blue.length = 8; 130 info->var.red.msb_right = 0;
171 var->transp.offset = 0; 131
172 var->transp.length = 0; 132 info->var.green.offset = 0;
173 break; 133 info->var.green.length = info->var.bits_per_pixel;
174 case 16: /* RGB 565 */ 134 info->var.green.msb_right = 0;
175 var->red.offset = 11; 135
176 var->red.length = 5; 136 info->var.blue.offset = 0;
177 var->green.offset = 5; 137 info->var.blue.length = info->var.bits_per_pixel;
178 var->green.length = 6; 138 info->var.blue.msb_right = 0;
179 var->blue.offset = 0; 139
180 var->blue.length = 5; 140 info->var.transp.offset = 0;
181 var->transp.offset = 0; 141 info->var.transp.length = 0;
182 var->transp.length = 0; 142 info->var.transp.msb_right = 0;
183 break; 143
144 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
145 info->fix.line_length = info->var.xres_virtual /
146 (8/info->var.bits_per_pixel);
147 } else {
148 /* non-palettized */
149 index = (fbdev->panel->control_base & LCD_CONTROL_SBPPF_MASK) >> LCD_CONTROL_SBPPF_BIT;
150 info->var.red = rgb_bitfields[index][0];
151 info->var.green = rgb_bitfields[index][1];
152 info->var.blue = rgb_bitfields[index][2];
153 info->var.transp = rgb_bitfields[index][3];
154
155 info->fix.visual = FB_VISUAL_TRUECOLOR;
156 info->fix.line_length = info->var.xres_virtual << 1; /* depth=16 */
157 }
158 } else {
159 /* mono */
160 info->fix.visual = FB_VISUAL_MONO10;
161 info->fix.line_length = info->var.xres_virtual / 8;
184 } 162 }
185 163
186 var->red.msb_right = 0; 164 info->screen_size = info->fix.line_length * info->var.yres_virtual;
187 var->green.msb_right = 0;
188 var->blue.msb_right = 0;
189 var->transp.msb_right = 0;
190}
191 165
192static int au1100_decode_var(const struct fb_var_screeninfo *var, 166 /* Determine BPP mode and format */
193 void *_par, struct fb_info_gen *_info) 167 fbdev->regs->lcd_control = fbdev->panel->control_base |
194{ 168 ((info->var.rotate/90) << LCD_CONTROL_SM_BIT);
195 169
196 struct au1100fb_par *par = (struct au1100fb_par *)_par; 170 fbdev->regs->lcd_intenable = 0;
171 fbdev->regs->lcd_intstatus = 0;
197 172
198 /* 173 fbdev->regs->lcd_horztiming = fbdev->panel->horztiming;
199 * Don't allow setting any of these yet: xres and yres don't
200 * make sense for LCD panels.
201 */
202 if (var->xres != p_lcd->xres ||
203 var->yres != p_lcd->yres ||
204 var->xres != p_lcd->xres ||
205 var->yres != p_lcd->yres) {
206 return -EINVAL;
207 }
208 if(var->bits_per_pixel != p_lcd->bpp) {
209 return -EINVAL;
210 }
211 174
212 memset(par, 0, sizeof(struct au1100fb_par)); 175 fbdev->regs->lcd_verttiming = fbdev->panel->verttiming;
213 par->var = *var; 176
214 177 fbdev->regs->lcd_clkcontrol = fbdev->panel->clkcontrol_base;
215 /* FIXME */
216 switch (var->bits_per_pixel) {
217 case 8:
218 par->var.bits_per_pixel = 8;
219 break;
220 case 16:
221 par->var.bits_per_pixel = 16;
222 break;
223 default:
224 printk("color depth %d bpp not supported\n",
225 var->bits_per_pixel);
226 return -EINVAL;
227 178
179 fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(fbdev->fb_phys);
180
181 if (panel_is_dual(fbdev->panel)) {
182 /* Second panel display seconf half of screen if possible,
183 * otherwise display the same as the first panel */
184 if (info->var.yres_virtual >= (info->var.yres << 1)) {
185 fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys +
186 (info->fix.line_length *
187 (info->var.yres_virtual >> 1)));
188 } else {
189 fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys);
190 }
228 } 191 }
229 set_color_bitfields(&par->var);
230 par->cmap_len = (par->var.bits_per_pixel == 8) ? 256 : 16;
231 return 0;
232}
233 192
234static int au1100_encode_var(struct fb_var_screeninfo *var, 193 words = info->fix.line_length / sizeof(u32);
235 const void *par, struct fb_info_gen *_info) 194 if (!info->var.rotate || (info->var.rotate == 180)) {
236{ 195 words *= info->var.yres_virtual;
196 if (info->var.rotate /* 180 */) {
197 words -= (words % 8); /* should be divisable by 8 */
198 }
199 }
200 fbdev->regs->lcd_words = LCD_WRD_WRDS_N(words);
237 201
238 *var = ((struct au1100fb_par *)par)->var; 202 fbdev->regs->lcd_pwmdiv = 0;
239 return 0; 203 fbdev->regs->lcd_pwmhi = 0;
240}
241 204
242static void 205 /* Resume controller */
243au1100_get_par(void *_par, struct fb_info_gen *_info) 206 fbdev->regs->lcd_control |= LCD_CONTROL_GO;
244{
245 *(struct au1100fb_par *)_par = current_par;
246}
247 207
248static void au1100_set_par(const void *par, struct fb_info_gen *info) 208 return 0;
249{
250 /* nothing to do: we don't change any settings */
251} 209}
252 210
253static int au1100_getcolreg(unsigned regno, unsigned *red, unsigned *green, 211/* fb_setcolreg
254 unsigned *blue, unsigned *transp, 212 * Set color in LCD palette.
255 struct fb_info *info) 213 */
214int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *fbi)
256{ 215{
216 struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
217 u32 *palette = fbdev->regs->lcd_pallettebase;
218 u32 value;
257 219
258 struct au1100fb_info* i = (struct au1100fb_info*)info; 220 if (regno > (AU1100_LCD_NBR_PALETTE_ENTRIES - 1))
259 221 return -EINVAL;
260 if (regno > 255)
261 return 1;
262 222
263 *red = i->palette[regno].red; 223 if (fbi->var.grayscale) {
264 *green = i->palette[regno].green; 224 /* Convert color to grayscale */
265 *blue = i->palette[regno].blue; 225 red = green = blue =
266 *transp = 0; 226 (19595 * red + 38470 * green + 7471 * blue) >> 16;
227 }
267 228
268 return 0; 229 if (fbi->fix.visual == FB_VISUAL_TRUECOLOR) {
269} 230 /* Place color in the pseudopalette */
231 if (regno > 16)
232 return -EINVAL;
270 233
271static int au1100_setcolreg(unsigned regno, unsigned red, unsigned green, 234 palette = (u32*)fbi->pseudo_palette;
272 unsigned blue, unsigned transp, 235
273 struct fb_info *info) 236 red >>= (16 - fbi->var.red.length);
274{ 237 green >>= (16 - fbi->var.green.length);
275 struct au1100fb_info* i = (struct au1100fb_info *)info; 238 blue >>= (16 - fbi->var.blue.length);
276 u32 rgbcol; 239
277 240 value = (red << fbi->var.red.offset) |
278 if (regno > 255) 241 (green << fbi->var.green.offset)|
279 return 1; 242 (blue << fbi->var.blue.offset);
280 243 value &= 0xFFFF;
281 i->palette[regno].red = red; 244
282 i->palette[regno].green = green; 245 } else if (panel_is_active(fbdev->panel)) {
283 i->palette[regno].blue = blue; 246 /* COLOR TFT PALLETTIZED (use RGB 565) */
284 247 value = (red & 0xF800)|((green >> 5) & 0x07E0)|((blue >> 11) & 0x001F);
285 switch(p_lcd->bpp) { 248 value &= 0xFFFF;
286#ifdef FBCON_HAS_CFB8 249
287 case 8: 250 } else if (panel_is_color(fbdev->panel)) {
288 red >>= 10; 251 /* COLOR STN MODE */
289 green >>= 10; 252 value = (((panel_swap_rgb(fbdev->panel) ? blue : red) >> 12) & 0x000F) |
290 blue >>= 10; 253 ((green >> 8) & 0x00F0) |
291 p_lcd_reg->lcd_pallettebase[regno] = (blue&0x1f) | 254 (((panel_swap_rgb(fbdev->panel) ? red : blue) >> 4) & 0x0F00);
292 ((green&0x3f)<<5) | ((red&0x1f)<<11); 255 value &= 0xFFF;
293 break; 256 } else {
294#endif 257 /* MONOCHROME MODE */
295#ifdef FBCON_HAS_CFB16 258 value = (green >> 12) & 0x000F;
296 case 16: 259 value &= 0xF;
297 i->fbcon_cmap16[regno] =
298 ((red & 0xf800) >> 0) |
299 ((green & 0xfc00) >> 5) |
300 ((blue & 0xf800) >> 11);
301 break;
302#endif
303 default:
304 break;
305 } 260 }
306 261
262 palette[regno] = value;
263
307 return 0; 264 return 0;
308} 265}
309 266
310 267/* fb_blank
311static int au1100_blank(int blank_mode, struct fb_info_gen *_info) 268 * Blank the screen. Depending on the mode, the screen will be
269 * activated with the backlight color, or desactivated
270 */
271int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi)
312{ 272{
273 struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
274
275 print_dbg("fb_blank %d %p", blank_mode, fbi);
313 276
314 switch (blank_mode) { 277 switch (blank_mode) {
278
315 case VESA_NO_BLANKING: 279 case VESA_NO_BLANKING:
316 /* turn on panel */ 280 /* Turn on panel */
317 //printk("turn on panel\n"); 281 fbdev->regs->lcd_control |= LCD_CONTROL_GO;
318#ifdef CONFIG_MIPS_PB1100 282#ifdef CONFIG_MIPS_PB1100
319 p_lcd_reg->lcd_control |= LCD_CONTROL_GO; 283 if (drv_info.panel_idx == 1) {
320 au_writew(au_readw(PB1100_G_CONTROL) | p_lcd->mode_backlight, 284 au_writew(au_readw(PB1100_G_CONTROL)
285 | (PB1100_G_CONTROL_BL | PB1100_G_CONTROL_VDD),
321 PB1100_G_CONTROL); 286 PB1100_G_CONTROL);
322#endif 287 }
323#ifdef CONFIG_MIPS_HYDROGEN3
324 /* Turn controller & power supply on, GPIO213 */
325 au_writel(0x20002000, 0xB1700008);
326 au_writel(0x00040000, 0xB1900108);
327 au_writel(0x01000100, 0xB1700008);
328#endif 288#endif
329 au_sync(); 289 au_sync();
330 break; 290 break;
@@ -332,12 +292,14 @@ static int au1100_blank(int blank_mode, struct fb_info_gen *_info)
332 case VESA_VSYNC_SUSPEND: 292 case VESA_VSYNC_SUSPEND:
333 case VESA_HSYNC_SUSPEND: 293 case VESA_HSYNC_SUSPEND:
334 case VESA_POWERDOWN: 294 case VESA_POWERDOWN:
335 /* turn off panel */ 295 /* Turn off panel */
336 //printk("turn off panel\n"); 296 fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
337#ifdef CONFIG_MIPS_PB1100 297#ifdef CONFIG_MIPS_PB1100
338 au_writew(au_readw(PB1100_G_CONTROL) & ~p_lcd->mode_backlight, 298 if (drv_info.panel_idx == 1) {
299 au_writew(au_readw(PB1100_G_CONTROL)
300 & ~(PB1100_G_CONTROL_BL | PB1100_G_CONTROL_VDD),
339 PB1100_G_CONTROL); 301 PB1100_G_CONTROL);
340 p_lcd_reg->lcd_control &= ~LCD_CONTROL_GO; 302 }
341#endif 303#endif
342 au_sync(); 304 au_sync();
343 break; 305 break;
@@ -348,49 +310,87 @@ static int au1100_blank(int blank_mode, struct fb_info_gen *_info)
348 return 0; 310 return 0;
349} 311}
350 312
351static void au1100_set_disp(const void *unused, struct display *disp, 313/* fb_pan_display
352 struct fb_info_gen *info) 314 * Pan display in x and/or y as specified
315 */
316int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
353{ 317{
354 disp->screen_base = (char *)fb_info.fb_virt_start; 318 struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
355 319 int dy;
356 switch (disp->var.bits_per_pixel) { 320
357#ifdef FBCON_HAS_CFB8 321 print_dbg("fb_pan_display %p %p", var, fbi);
358 case 8: 322
359 disp->dispsw = &fbcon_cfb8; 323 if (!var || !fbdev) {
360 if (fb_info.nohwcursor) 324 return -EINVAL;
361 fbcon_cfb8.cursor = au1100_nocursor; 325 }
362 break; 326
363#endif 327 if (var->xoffset - fbi->var.xoffset) {
364#ifdef FBCON_HAS_CFB16 328 /* No support for X panning for now! */
365 case 16: 329 return -EINVAL;
366 disp->dispsw = &fbcon_cfb16; 330 }
367 disp->dispsw_data = fb_info.fbcon_cmap16; 331
368 if (fb_info.nohwcursor) 332 print_dbg("fb_pan_display 2 %p %p", var, fbi);
369 fbcon_cfb16.cursor = au1100_nocursor; 333 dy = var->yoffset - fbi->var.yoffset;
370 break; 334 if (dy) {
371#endif 335
372 default: 336 u32 dmaaddr;
373 disp->dispsw = &fbcon_dummy; 337
374 disp->dispsw_data = NULL; 338 print_dbg("Panning screen of %d lines", dy);
375 break; 339
340 dmaaddr = fbdev->regs->lcd_dmaaddr0;
341 dmaaddr += (fbi->fix.line_length * dy);
342
343 /* TODO: Wait for current frame to finished */
344 fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
345
346 if (panel_is_dual(fbdev->panel)) {
347 dmaaddr = fbdev->regs->lcd_dmaaddr1;
348 dmaaddr += (fbi->fix.line_length * dy);
349 fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
350 }
351 }
352 print_dbg("fb_pan_display 3 %p %p", var, fbi);
353
354 return 0;
355}
356
357/* fb_rotate
358 * Rotate the display of this angle. This doesn't seems to be used by the core,
359 * but as our hardware supports it, so why not implementing it...
360 */
361void au1100fb_fb_rotate(struct fb_info *fbi, int angle)
362{
363 struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
364
365 print_dbg("fb_rotate %p %d", fbi, angle);
366
367 if (fbdev && (angle > 0) && !(angle % 90)) {
368
369 fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
370
371 fbdev->regs->lcd_control &= ~(LCD_CONTROL_SM_MASK);
372 fbdev->regs->lcd_control |= ((angle/90) << LCD_CONTROL_SM_BIT);
373
374 fbdev->regs->lcd_control |= LCD_CONTROL_GO;
376 } 375 }
377} 376}
378 377
379static int 378/* fb_mmap
380au1100fb_mmap(struct fb_info *_fb, 379 * Map video memory in user space. We don't use the generic fb_mmap method mainly
381 struct file *file, 380 * to allow the use of the TLB streaming flag (CCA=6)
382 struct vm_area_struct *vma) 381 */
382int au1100fb_fb_mmap(struct fb_info *fbi, struct file *file, struct vm_area_struct *vma)
383{ 383{
384 struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
384 unsigned int len; 385 unsigned int len;
385 unsigned long start=0, off; 386 unsigned long start=0, off;
386 struct au1100fb_info *fb = (struct au1100fb_info *)_fb;
387 387
388 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) { 388 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) {
389 return -EINVAL; 389 return -EINVAL;
390 } 390 }
391 391
392 start = fb_info.fb_phys & PAGE_MASK; 392 start = fbdev->fb_phys & PAGE_MASK;
393 len = PAGE_ALIGN((start & ~PAGE_MASK) + fb_info.fb_size); 393 len = PAGE_ALIGN((start & ~PAGE_MASK) + fbdev->fb_len);
394 394
395 off = vma->vm_pgoff << PAGE_SHIFT; 395 off = vma->vm_pgoff << PAGE_SHIFT;
396 396
@@ -401,276 +401,309 @@ au1100fb_mmap(struct fb_info *_fb,
401 off += start; 401 off += start;
402 vma->vm_pgoff = off >> PAGE_SHIFT; 402 vma->vm_pgoff = off >> PAGE_SHIFT;
403 403
404 pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK; 404 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
405 //pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;
406 pgprot_val(vma->vm_page_prot) |= (6 << 9); //CCA=6 405 pgprot_val(vma->vm_page_prot) |= (6 << 9); //CCA=6
407 406
408 /* This is an IO map - tell maydump to skip this VMA */
409 vma->vm_flags |= VM_IO; 407 vma->vm_flags |= VM_IO;
410 408
411 if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT, 409 if (io_remap_page_range(vma, vma->vm_start, off,
412 vma->vm_end - vma->vm_start, 410 vma->vm_end - vma->vm_start,
413 vma->vm_page_prot)) { 411 vma->vm_page_prot)) {
414 return -EAGAIN; 412 return -EAGAIN;
415 } 413 }
416 414
417 fb->mmaped = 1;
418 return 0; 415 return 0;
419} 416}
420 417
421int au1100_pan_display(const struct fb_var_screeninfo *var, 418static struct fb_ops au1100fb_ops =
422 struct fb_info_gen *info)
423{ 419{
424 return 0; 420 .owner = THIS_MODULE,
425} 421 .fb_setcolreg = au1100fb_fb_setcolreg,
422 .fb_blank = au1100fb_fb_blank,
423 .fb_pan_display = au1100fb_fb_pan_display,
424 .fb_fillrect = cfb_fillrect,
425 .fb_copyarea = cfb_copyarea,
426 .fb_imageblit = cfb_imageblit,
427 .fb_rotate = au1100fb_fb_rotate,
428 .fb_mmap = au1100fb_fb_mmap,
429};
426 430
427static int au1100fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
428 u_long arg, int con, struct fb_info *info)
429{
430 /* nothing to do yet */
431 return -EINVAL;
432}
433 431
434static struct fbgen_hwswitch au1100_switch = { 432/*-------------------------------------------------------------------------*/
435 au1100_detect,
436 au1100_encode_fix,
437 au1100_decode_var,
438 au1100_encode_var,
439 au1100_get_par,
440 au1100_set_par,
441 au1100_getcolreg,
442 au1100_setcolreg,
443 au1100_pan_display,
444 au1100_blank,
445 au1100_set_disp
446};
447 433
434/* AU1100 LCD controller device driver */
448 435
449int au1100_setmode(void) 436int au1100fb_drv_probe(struct device *dev)
450{ 437{
451 int words; 438 struct au1100fb_device *fbdev = NULL;
452 439 struct resource *regs_res;
453 /* FIXME Need to accomodate for swivel mode and 12bpp, <8bpp*/ 440 unsigned long page;
454 switch (p_lcd->mode_control & LCD_CONTROL_SM) 441 u32 sys_clksrc;
455 { 442
456 case LCD_CONTROL_SM_0: 443 if (!dev)
457 case LCD_CONTROL_SM_180:
458 words = (p_lcd->xres * p_lcd->yres * p_lcd->bpp) / 32;
459 break;
460 case LCD_CONTROL_SM_90:
461 case LCD_CONTROL_SM_270:
462 /* is this correct? */
463 words = (p_lcd->xres * p_lcd->bpp) / 8;
464 break;
465 default:
466 printk("mode_control reg not initialized\n");
467 return -EINVAL; 444 return -EINVAL;
445
446 /* Allocate new device private */
447 if (!(fbdev = kmalloc(sizeof(struct au1100fb_device), GFP_KERNEL))) {
448 print_err("fail to allocate device private record");
449 return -ENOMEM;
468 } 450 }
451 memset((void*)fbdev, 0, sizeof(struct au1100fb_device));
469 452
470 /* 453 fbdev->panel = &known_lcd_panels[drv_info.panel_idx];
471 * Setup LCD controller
472 */
473 454
474 p_lcd_reg->lcd_control = p_lcd->mode_control; 455 dev_set_drvdata(dev, (void*)fbdev);
475 p_lcd_reg->lcd_intstatus = 0;
476 p_lcd_reg->lcd_intenable = 0;
477 p_lcd_reg->lcd_horztiming = p_lcd->mode_horztiming;
478 p_lcd_reg->lcd_verttiming = p_lcd->mode_verttiming;
479 p_lcd_reg->lcd_clkcontrol = p_lcd->mode_clkcontrol;
480 p_lcd_reg->lcd_words = words - 1;
481 p_lcd_reg->lcd_dmaaddr0 = fb_info.fb_phys;
482 456
483 /* turn on panel */ 457 /* Allocate region for our registers and map them */
484#ifdef CONFIG_MIPS_PB1100 458 if (!(regs_res = platform_get_resource(to_platform_device(dev),
485 au_writew(au_readw(PB1100_G_CONTROL) | p_lcd->mode_backlight, 459 IORESOURCE_MEM, 0))) {
486 PB1100_G_CONTROL); 460 print_err("fail to retrieve registers resource");
487#endif 461 return -EFAULT;
488#ifdef CONFIG_MIPS_HYDROGEN3 462 }
489 /* Turn controller & power supply on, GPIO213 */
490 au_writel(0x20002000, 0xB1700008);
491 au_writel(0x00040000, 0xB1900108);
492 au_writel(0x01000100, 0xB1700008);
493#endif
494 463
495 p_lcd_reg->lcd_control |= LCD_CONTROL_GO; 464 au1100fb_fix.mmio_start = regs_res->start;
465 au1100fb_fix.mmio_len = regs_res->end - regs_res->start + 1;
496 466
497 return 0; 467 if (!request_mem_region(au1100fb_fix.mmio_start, au1100fb_fix.mmio_len,
498} 468 DRIVER_NAME)) {
469 print_err("fail to lock memory region at 0x%08x",
470 au1100fb_fix.mmio_start);
471 return -EBUSY;
472 }
499 473
474 fbdev->regs = (struct au1100fb_regs*)KSEG1ADDR(au1100fb_fix.mmio_start);
500 475
501int __init au1100fb_init(void) 476 print_dbg("Register memory map at %p", fbdev->regs);
502{ 477 print_dbg("phys=0x%08x, size=%d", fbdev->regs_phys, fbdev->regs_len);
503 uint32 sys_clksrc;
504 unsigned long page;
505 478
506 /*
507 * Get the panel information/display mode and update the registry
508 */
509 p_lcd = &panels[my_lcd_index];
510
511 switch (p_lcd->mode_control & LCD_CONTROL_SM)
512 {
513 case LCD_CONTROL_SM_0:
514 case LCD_CONTROL_SM_180:
515 p_lcd->xres =
516 (p_lcd->mode_horztiming & LCD_HORZTIMING_PPL) + 1;
517 p_lcd->yres =
518 (p_lcd->mode_verttiming & LCD_VERTTIMING_LPP) + 1;
519 break;
520 case LCD_CONTROL_SM_90:
521 case LCD_CONTROL_SM_270:
522 p_lcd->yres =
523 (p_lcd->mode_horztiming & LCD_HORZTIMING_PPL) + 1;
524 p_lcd->xres =
525 (p_lcd->mode_verttiming & LCD_VERTTIMING_LPP) + 1;
526 break;
527 }
528 479
529 /*
530 * Panel dimensions x bpp must be divisible by 32
531 */
532 if (((p_lcd->yres * p_lcd->bpp) % 32) != 0)
533 printk("VERT %% 32\n");
534 if (((p_lcd->xres * p_lcd->bpp) % 32) != 0)
535 printk("HORZ %% 32\n");
536 480
537 /* 481 /* Allocate the framebuffer to the maximum screen size * nbr of video buffers */
538 * Allocate LCD framebuffer from system memory 482 fbdev->fb_len = fbdev->panel->xres * fbdev->panel->yres *
539 */ 483 (fbdev->panel->bpp >> 3) * AU1100FB_NBR_VIDEO_BUFFERS;
540 fb_info.fb_size = (p_lcd->xres * p_lcd->yres * p_lcd->bpp) / 8; 484
541 485 fbdev->fb_mem = dma_alloc_coherent(dev, PAGE_ALIGN(fbdev->fb_len),
542 current_par.var.xres = p_lcd->xres; 486 &fbdev->fb_phys, GFP_KERNEL);
543 current_par.var.xres_virtual = p_lcd->xres; 487 if (!fbdev->fb_mem) {
544 current_par.var.yres = p_lcd->yres; 488 print_err("fail to allocate frambuffer (size: %dK))",
545 current_par.var.yres_virtual = p_lcd->yres; 489 fbdev->fb_len / 1024);
546 current_par.var.bits_per_pixel = p_lcd->bpp;
547
548 /* FIX!!! only works for 8/16 bpp */
549 current_par.line_length = p_lcd->xres * p_lcd->bpp / 8; /* in bytes */
550 fb_info.fb_virt_start = (unsigned long )
551 __get_free_pages(GFP_ATOMIC | GFP_DMA,
552 get_order(fb_info.fb_size + 0x1000));
553 if (!fb_info.fb_virt_start) {
554 printk("Unable to allocate fb memory\n");
555 return -ENOMEM; 490 return -ENOMEM;
556 } 491 }
557 fb_info.fb_phys = virt_to_bus((void *)fb_info.fb_virt_start); 492
493 au1100fb_fix.smem_start = fbdev->fb_phys;
494 au1100fb_fix.smem_len = fbdev->fb_len;
558 495
559 /* 496 /*
560 * Set page reserved so that mmap will work. This is necessary 497 * Set page reserved so that mmap will work. This is necessary
561 * since we'll be remapping normal memory. 498 * since we'll be remapping normal memory.
562 */ 499 */
563 for (page = fb_info.fb_virt_start; 500 for (page = (unsigned long)fbdev->fb_mem;
564 page < PAGE_ALIGN(fb_info.fb_virt_start + fb_info.fb_size); 501 page < PAGE_ALIGN((unsigned long)fbdev->fb_mem + fbdev->fb_len);
565 page += PAGE_SIZE) { 502 page += PAGE_SIZE) {
503#if CONFIG_DMA_NONCOHERENT
504 SetPageReserved(virt_to_page(CAC_ADDR(page)));
505#else
566 SetPageReserved(virt_to_page(page)); 506 SetPageReserved(virt_to_page(page));
507#endif
567 } 508 }
568 509
569 memset((void *)fb_info.fb_virt_start, 0, fb_info.fb_size); 510 print_dbg("Framebuffer memory map at %p", fbdev->fb_mem);
570 511 print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024);
571 /* set freqctrl now to allow more time to stabilize */ 512
572 /* zero-out out LCD bits */ 513 /* Setup LCD clock to AUX (48 MHz) */
573 sys_clksrc = au_readl(SYS_CLKSRC) & ~0x000003e0; 514 sys_clksrc = au_readl(SYS_CLKSRC) & ~(SYS_CS_ML_MASK | SYS_CS_DL | SYS_CS_CL);
574 sys_clksrc |= p_lcd->mode_toyclksrc; 515 au_writel((sys_clksrc | (1 << SYS_CS_ML_BIT)), SYS_CLKSRC);
575 au_writel(sys_clksrc, SYS_CLKSRC); 516
576 517 /* load the panel info into the var struct */
577 /* FIXME add check to make sure auxpll is what is expected! */ 518 au1100fb_var.bits_per_pixel = fbdev->panel->bpp;
578 au1100_setmode(); 519 au1100fb_var.xres = fbdev->panel->xres;
579 520 au1100fb_var.xres_virtual = au1100fb_var.xres;
580 fb_info.gen.parsize = sizeof(struct au1100fb_par); 521 au1100fb_var.yres = fbdev->panel->yres;
581 fb_info.gen.fbhw = &au1100_switch; 522 au1100fb_var.yres_virtual = au1100fb_var.yres;
582 523
583 strcpy(fb_info.gen.info.modename, "Au1100 LCD"); 524 fbdev->info.screen_base = fbdev->fb_mem;
584 fb_info.gen.info.changevar = NULL; 525 fbdev->info.fbops = &au1100fb_ops;
585 fb_info.gen.info.node = -1; 526 fbdev->info.fix = au1100fb_fix;
586 527
587 fb_info.gen.info.fbops = &au1100fb_ops; 528 if (!(fbdev->info.pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL))) {
588 fb_info.gen.info.disp = &disp; 529 return -ENOMEM;
589 fb_info.gen.info.switch_con = &fbgen_switch; 530 }
590 fb_info.gen.info.updatevar = &fbgen_update_var; 531 memset(fbdev->info.pseudo_palette, 0, sizeof(u32) * 16);
591 fb_info.gen.info.blank = &fbgen_blank; 532
592 fb_info.gen.info.flags = FBINFO_FLAG_DEFAULT; 533 if (fb_alloc_cmap(&fbdev->info.cmap, AU1100_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
593 534 print_err("Fail to allocate colormap (%d entries)",
594 /* This should give a reasonable default video mode */ 535 AU1100_LCD_NBR_PALETTE_ENTRIES);
595 fbgen_get_var(&disp.var, -1, &fb_info.gen.info); 536 kfree(fbdev->info.pseudo_palette);
596 fbgen_do_set_var(&disp.var, 1, &fb_info.gen); 537 return -EFAULT;
597 fbgen_set_disp(-1, &fb_info.gen); 538 }
598 fbgen_install_cmap(0, &fb_info.gen); 539
599 if (register_framebuffer(&fb_info.gen.info) < 0) 540 fbdev->info.var = au1100fb_var;
600 return -EINVAL; 541
601 printk(KERN_INFO "fb%d: %s frame buffer device\n", 542 /* Set h/w registers */
602 GET_FB_IDX(fb_info.gen.info.node), 543 au1100fb_setmode(fbdev);
603 fb_info.gen.info.modename); 544
545 /* Register new framebuffer */
546 if (register_framebuffer(&fbdev->info) < 0) {
547 print_err("cannot register new framebuffer");
548 goto failed;
549 }
550
551 return 0;
552
553failed:
554 if (fbdev->regs) {
555 release_mem_region(fbdev->regs_phys, fbdev->regs_len);
556 }
557 if (fbdev->fb_mem) {
558 dma_free_noncoherent(dev, fbdev->fb_len, fbdev->fb_mem, fbdev->fb_phys);
559 }
560 if (fbdev->info.cmap.len != 0) {
561 fb_dealloc_cmap(&fbdev->info.cmap);
562 }
563 kfree(fbdev);
564 dev_set_drvdata(dev, NULL);
604 565
605 return 0; 566 return 0;
606} 567}
607 568
569int au1100fb_drv_remove(struct device *dev)
570{
571 struct au1100fb_device *fbdev = NULL;
572
573 if (!dev)
574 return -ENODEV;
575
576 fbdev = (struct au1100fb_device*) dev_get_drvdata(dev);
577
578#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
579 au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info);
580#endif
581 fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
608 582
609void au1100fb_cleanup(struct fb_info *info) 583 /* Clean up all probe data */
584 unregister_framebuffer(&fbdev->info);
585
586 release_mem_region(fbdev->regs_phys, fbdev->regs_len);
587
588 dma_free_coherent(dev, PAGE_ALIGN(fbdev->fb_len), fbdev->fb_mem, fbdev->fb_phys);
589
590 fb_dealloc_cmap(&fbdev->info.cmap);
591 kfree(fbdev->info.pseudo_palette);
592 kfree((void*)fbdev);
593
594 return 0;
595}
596
597int au1100fb_drv_suspend(struct device *dev, u32 state, u32 level)
598{
599 /* TODO */
600 return 0;
601}
602
603int au1100fb_drv_resume(struct device *dev, u32 level)
610{ 604{
611 unregister_framebuffer(info); 605 /* TODO */
606 return 0;
612} 607}
613 608
609static struct device_driver au1100fb_driver = {
610 .name = "au1100-lcd",
611 .bus = &platform_bus_type,
614 612
615void au1100fb_setup(char *options, int *ints) 613 .probe = au1100fb_drv_probe,
614 .remove = au1100fb_drv_remove,
615 .suspend = au1100fb_drv_suspend,
616 .resume = au1100fb_drv_resume,
617};
618
619/*-------------------------------------------------------------------------*/
620
621/* Kernel driver */
622
623int au1100fb_setup(char *options)
616{ 624{
617 char* this_opt; 625 char* this_opt;
618 int i; 626 int num_panels = ARRAY_SIZE(known_lcd_panels);
619 int num_panels = sizeof(panels)/sizeof(struct known_lcd_panels); 627 char* mode = NULL;
628 int panel_idx = 0;
620 629
630 if (num_panels <= 0) {
631 print_err("No LCD panels supported by driver!");
632 return -EFAULT;
633 }
621 634
622 if (!options || !*options) 635 if (options) {
623 return; 636 while ((this_opt = strsep(&options,",")) != NULL) {
624 637 /* Panel option */
625 for(this_opt=strtok(options, ","); this_opt;
626 this_opt=strtok(NULL, ",")) {
627 if (!strncmp(this_opt, "panel:", 6)) { 638 if (!strncmp(this_opt, "panel:", 6)) {
628#if defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) 639 int i;
629 /* Read Pb1100 Switch S10 ? */ 640 this_opt += 6;
630 if (!strncmp(this_opt+6, "s10", 3)) 641 for (i = 0; i < num_panels; i++) {
631 { 642 if (!strncmp(this_opt,
632 int panel; 643 known_lcd_panels[i].name,
633 panel = *(volatile int *)0xAE000008; /* BCSR SWITCHES */
634 panel >>= 8;
635 panel &= 0x0F;
636 if (panel >= num_panels) panel = 0;
637 my_lcd_index = panel;
638 }
639 else
640#endif
641 /* Get the panel name, everything else if fixed */
642 for (i=0; i<num_panels; i++) {
643 if (!strncmp(this_opt+6, panels[i].panel_name,
644 strlen(this_opt))) { 644 strlen(this_opt))) {
645 my_lcd_index = i; 645 panel_idx = i;
646 break; 646 break;
647 } 647 }
648 } 648 }
649 if (i >= num_panels) {
650 print_warn("Panel %s not supported!", this_opt);
651 }
652 }
653 /* Mode option (only option that start with digit) */
654 else if (isdigit(this_opt[0])) {
655 mode = kmalloc(strlen(this_opt) + 1, GFP_KERNEL);
656 strncpy(mode, this_opt, strlen(this_opt) + 1);
657 }
658 /* Unsupported option */
659 else {
660 print_warn("Unsupported option \"%s\"", this_opt);
649 } 661 }
650 else if (!strncmp(this_opt, "nohwcursor", 10)) {
651 printk("nohwcursor\n");
652 fb_info.nohwcursor = 1;
653 } 662 }
654 } 663 }
655 664
656 printk("au1100fb: Panel %d %s\n", my_lcd_index, 665 drv_info.panel_idx = panel_idx;
657 panels[my_lcd_index].panel_name); 666 drv_info.opt_mode = mode;
658}
659 667
668 print_info("Panel=%s Mode=%s",
669 known_lcd_panels[drv_info.panel_idx].name,
670 drv_info.opt_mode ? drv_info.opt_mode : "default");
660 671
672 return 0;
673}
661 674
662#ifdef MODULE 675int __init au1100fb_init(void)
663MODULE_LICENSE("GPL");
664int init_module(void)
665{ 676{
666 return au1100fb_init(); 677 char* options;
678 int ret;
679
680 print_info("" DRIVER_DESC "");
681
682 memset(&drv_info, 0, sizeof(drv_info));
683
684 if (fb_get_options(DRIVER_NAME, &options))
685 return -ENODEV;
686
687 /* Setup driver with options */
688 ret = au1100fb_setup(options);
689 if (ret < 0) {
690 print_err("Fail to setup driver");
691 return ret;
692 }
693
694 return driver_register(&au1100fb_driver);
667} 695}
668 696
669void cleanup_module(void) 697void __exit au1100fb_cleanup(void)
670{ 698{
671 au1100fb_cleanup(void); 699 driver_unregister(&au1100fb_driver);
700
701 if (drv_info.opt_mode)
702 kfree(drv_info.opt_mode);
672} 703}
673 704
674MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>"); 705module_init(au1100fb_init);
675MODULE_DESCRIPTION("Au1100 LCD framebuffer device driver"); 706module_exit(au1100fb_cleanup);
676#endif /* MODULE */ 707
708MODULE_DESCRIPTION(DRIVER_DESC);
709MODULE_LICENSE("GPL");
diff --git a/drivers/video/au1100fb.h b/drivers/video/au1100fb.h
index 657c560ab73c..2855534dc235 100644
--- a/drivers/video/au1100fb.h
+++ b/drivers/video/au1100fb.h
@@ -30,352 +30,352 @@
30#ifndef _AU1100LCD_H 30#ifndef _AU1100LCD_H
31#define _AU1100LCD_H 31#define _AU1100LCD_H
32 32
33#include <asm/mach-au1x00/au1000.h>
34
35#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
36#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
37#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
38
39#if DEBUG
40#define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
41#else
42#define print_dbg(f, arg...) do {} while (0)
43#endif
44
45#if defined(__BIG_ENDIAN)
46#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
47#else
48#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
49#endif
50#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
51
33/********************************************************************/ 52/********************************************************************/
34#define uint32 unsigned long 53
35typedef volatile struct 54/* LCD controller restrictions */
36{ 55#define AU1100_LCD_MAX_XRES 800
37 uint32 lcd_control; 56#define AU1100_LCD_MAX_YRES 600
38 uint32 lcd_intstatus; 57#define AU1100_LCD_MAX_BPP 16
39 uint32 lcd_intenable; 58#define AU1100_LCD_MAX_CLK 48000000
40 uint32 lcd_horztiming; 59#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
41 uint32 lcd_verttiming; 60
42 uint32 lcd_clkcontrol; 61/* Default number of visible screen buffer to allocate */
43 uint32 lcd_dmaaddr0; 62#define AU1100FB_NBR_VIDEO_BUFFERS 4
44 uint32 lcd_dmaaddr1;
45 uint32 lcd_words;
46 uint32 lcd_pwmdiv;
47 uint32 lcd_pwmhi;
48 uint32 reserved[(0x0400-0x002C)/4];
49 uint32 lcd_pallettebase[256];
50
51} AU1100_LCD;
52 63
53/********************************************************************/ 64/********************************************************************/
54 65
55#define AU1100_LCD_ADDR 0xB5000000 66struct au1100fb_panel
67{
68 const char name[25]; /* Full name <vendor>_<model> */
56 69
57/* 70 u32 control_base; /* Mode-independent control values */
58 * Register bit definitions 71 u32 clkcontrol_base; /* Panel pixclock preferences */
59 */
60 72
61/* lcd_control */ 73 u32 horztiming;
62#define LCD_CONTROL_SBPPF (7<<18) 74 u32 verttiming;
63#define LCD_CONTROL_SBPPF_655 (0<<18)
64#define LCD_CONTROL_SBPPF_565 (1<<18)
65#define LCD_CONTROL_SBPPF_556 (2<<18)
66#define LCD_CONTROL_SBPPF_1555 (3<<18)
67#define LCD_CONTROL_SBPPF_5551 (4<<18)
68#define LCD_CONTROL_WP (1<<17)
69#define LCD_CONTROL_WD (1<<16)
70#define LCD_CONTROL_C (1<<15)
71#define LCD_CONTROL_SM (3<<13)
72#define LCD_CONTROL_SM_0 (0<<13)
73#define LCD_CONTROL_SM_90 (1<<13)
74#define LCD_CONTROL_SM_180 (2<<13)
75#define LCD_CONTROL_SM_270 (3<<13)
76#define LCD_CONTROL_DB (1<<12)
77#define LCD_CONTROL_CCO (1<<11)
78#define LCD_CONTROL_DP (1<<10)
79#define LCD_CONTROL_PO (3<<8)
80#define LCD_CONTROL_PO_00 (0<<8)
81#define LCD_CONTROL_PO_01 (1<<8)
82#define LCD_CONTROL_PO_10 (2<<8)
83#define LCD_CONTROL_PO_11 (3<<8)
84#define LCD_CONTROL_MPI (1<<7)
85#define LCD_CONTROL_PT (1<<6)
86#define LCD_CONTROL_PC (1<<5)
87#define LCD_CONTROL_BPP (7<<1)
88#define LCD_CONTROL_BPP_1 (0<<1)
89#define LCD_CONTROL_BPP_2 (1<<1)
90#define LCD_CONTROL_BPP_4 (2<<1)
91#define LCD_CONTROL_BPP_8 (3<<1)
92#define LCD_CONTROL_BPP_12 (4<<1)
93#define LCD_CONTROL_BPP_16 (5<<1)
94#define LCD_CONTROL_GO (1<<0)
95
96/* lcd_intstatus, lcd_intenable */
97#define LCD_INT_SD (1<<7)
98#define LCD_INT_OF (1<<6)
99#define LCD_INT_UF (1<<5)
100#define LCD_INT_SA (1<<3)
101#define LCD_INT_SS (1<<2)
102#define LCD_INT_S1 (1<<1)
103#define LCD_INT_S0 (1<<0)
104
105/* lcd_horztiming */
106#define LCD_HORZTIMING_HN2 (255<<24)
107#define LCD_HORZTIMING_HN2_N(N) (((N)-1)<<24)
108#define LCD_HORZTIMING_HN1 (255<<16)
109#define LCD_HORZTIMING_HN1_N(N) (((N)-1)<<16)
110#define LCD_HORZTIMING_HPW (63<<10)
111#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<10)
112#define LCD_HORZTIMING_PPL (1023<<0)
113#define LCD_HORZTIMING_PPL_N(N) (((N)-1)<<0)
114
115/* lcd_verttiming */
116#define LCD_VERTTIMING_VN2 (255<<24)
117#define LCD_VERTTIMING_VN2_N(N) (((N)-1)<<24)
118#define LCD_VERTTIMING_VN1 (255<<16)
119#define LCD_VERTTIMING_VN1_N(N) (((N)-1)<<16)
120#define LCD_VERTTIMING_VPW (63<<10)
121#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<10)
122#define LCD_VERTTIMING_LPP (1023<<0)
123#define LCD_VERTTIMING_LPP_N(N) (((N)-1)<<0)
124
125/* lcd_clkcontrol */
126#define LCD_CLKCONTROL_IB (1<<18)
127#define LCD_CLKCONTROL_IC (1<<17)
128#define LCD_CLKCONTROL_IH (1<<16)
129#define LCD_CLKCONTROL_IV (1<<15)
130#define LCD_CLKCONTROL_BF (31<<10)
131#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10)
132#define LCD_CLKCONTROL_PCD (1023<<0)
133#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0)
134
135/* lcd_pwmdiv */
136#define LCD_PWMDIV_EN (1<<12)
137#define LCD_PWMDIV_PWMDIV (2047<<0)
138#define LCD_PWMDIV_PWMDIV_N(N) (((N)-1)<<0)
139
140/* lcd_pwmhi */
141#define LCD_PWMHI_PWMHI1 (2047<<12)
142#define LCD_PWMHI_PWMHI1_N(N) ((N)<<12)
143#define LCD_PWMHI_PWMHI0 (2047<<0)
144#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0)
145
146/* lcd_pallettebase - MONOCHROME */
147#define LCD_PALLETTE_MONO_MI (15<<0)
148#define LCD_PALLETTE_MONO_MI_N(N) ((N)<<0)
149
150/* lcd_pallettebase - COLOR */
151#define LCD_PALLETTE_COLOR_BI (15<<8)
152#define LCD_PALLETTE_COLOR_BI_N(N) ((N)<<8)
153#define LCD_PALLETTE_COLOR_GI (15<<4)
154#define LCD_PALLETTE_COLOR_GI_N(N) ((N)<<4)
155#define LCD_PALLETTE_COLOR_RI (15<<0)
156#define LCD_PALLETTE_COLOR_RI_N(N) ((N)<<0)
157
158/* lcd_palletebase - COLOR TFT PALLETIZED */
159#define LCD_PALLETTE_TFT_DC (65535<<0)
160#define LCD_PALLETTE_TFT_DC_N(N) ((N)<<0)
161 75
162/********************************************************************/ 76 u32 xres; /* Maximum horizontal resolution */
77 u32 yres; /* Maximum vertical resolution */
78 u32 bpp; /* Maximum depth supported */
79};
163 80
164struct known_lcd_panels 81struct au1100fb_regs
165{ 82{
166 uint32 xres; 83 u32 lcd_control;
167 uint32 yres; 84 u32 lcd_intstatus;
168 uint32 bpp; 85 u32 lcd_intenable;
169 unsigned char panel_name[256]; 86 u32 lcd_horztiming;
170 uint32 mode_control; 87 u32 lcd_verttiming;
171 uint32 mode_horztiming; 88 u32 lcd_clkcontrol;
172 uint32 mode_verttiming; 89 u32 lcd_dmaaddr0;
173 uint32 mode_clkcontrol; 90 u32 lcd_dmaaddr1;
174 uint32 mode_pwmdiv; 91 u32 lcd_words;
175 uint32 mode_pwmhi; 92 u32 lcd_pwmdiv;
176 uint32 mode_toyclksrc; 93 u32 lcd_pwmhi;
177 uint32 mode_backlight; 94 u32 reserved[(0x0400-0x002C)/4];
95 u32 lcd_pallettebase[256];
96};
97
98struct au1100fb_device {
99
100 struct fb_info info; /* FB driver info record */
178 101
102 struct au1100fb_panel *panel; /* Panel connected to this device */
103
104 struct au1100fb_regs* regs; /* Registers memory map */
105 size_t regs_len;
106 unsigned int regs_phys;
107
108 unsigned char* fb_mem; /* FrameBuffer memory map */
109 size_t fb_len;
110 dma_addr_t fb_phys;
179}; 111};
180 112
181#if defined(__BIG_ENDIAN) 113/********************************************************************/
182#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_11
183#else
184#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_00
185#endif
186 114
187/* 115#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
188 * The fb driver assumes that AUX PLL is at 48MHz. That can 116 #define LCD_CONTROL_SBB_BIT 21
189 * cover up to 800x600 resolution; if you need higher resolution, 117 #define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
190 * you should modify the driver as needed, not just this structure. 118 #define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
119 #define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
120 #define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
121 #define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
122 #define LCD_CONTROL_SBPPF_BIT 18
123 #define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
124 #define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
125 #define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
126 #define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
127 #define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
128 #define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
129 #define LCD_CONTROL_WP (1<<17)
130 #define LCD_CONTROL_WD (1<<16)
131 #define LCD_CONTROL_C (1<<15)
132 #define LCD_CONTROL_SM_BIT 13
133 #define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
134 #define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
135 #define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
136 #define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
137 #define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
138 #define LCD_CONTROL_DB (1<<12)
139 #define LCD_CONTROL_CCO (1<<11)
140 #define LCD_CONTROL_DP (1<<10)
141 #define LCD_CONTROL_PO_BIT 8
142 #define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
143 #define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
144 #define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
145 #define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
146 #define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
147 #define LCD_CONTROL_MPI (1<<7)
148 #define LCD_CONTROL_PT (1<<6)
149 #define LCD_CONTROL_PC (1<<5)
150 #define LCD_CONTROL_BPP_BIT 1
151 #define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
152 #define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
153 #define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
154 #define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
155 #define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
156 #define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
157 #define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
158 #define LCD_CONTROL_GO (1<<0)
159
160#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
161#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
162 #define LCD_INT_SD (1<<7)
163 #define LCD_INT_OF (1<<6)
164 #define LCD_INT_UF (1<<5)
165 #define LCD_INT_SA (1<<3)
166 #define LCD_INT_SS (1<<2)
167 #define LCD_INT_S1 (1<<1)
168 #define LCD_INT_S0 (1<<0)
169
170#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
171 #define LCD_HORZTIMING_HN2_BIT 24
172 #define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
173 #define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
174 #define LCD_HORZTIMING_HN1_BIT 16
175 #define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
176 #define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
177 #define LCD_HORZTIMING_HPW_BIT 10
178 #define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
179 #define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
180 #define LCD_HORZTIMING_PPL_BIT 0
181 #define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
182 #define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
183
184#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
185 #define LCD_VERTTIMING_VN2_BIT 24
186 #define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
187 #define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
188 #define LCD_VERTTIMING_VN1_BIT 16
189 #define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
190 #define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
191 #define LCD_VERTTIMING_VPW_BIT 10
192 #define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
193 #define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
194 #define LCD_VERTTIMING_LPP_BIT 0
195 #define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
196 #define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
197
198#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
199 #define LCD_CLKCONTROL_IB (1<<18)
200 #define LCD_CLKCONTROL_IC (1<<17)
201 #define LCD_CLKCONTROL_IH (1<<16)
202 #define LCD_CLKCONTROL_IV (1<<15)
203 #define LCD_CLKCONTROL_BF_BIT 10
204 #define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
205 #define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
206 #define LCD_CLKCONTROL_PCD_BIT 0
207 #define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
208 #define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
209
210#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
211#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
212 #define LCD_DMA_SA_BIT 5
213 #define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
214 #define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
215
216#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
217 #define LCD_WRD_WRDS_BIT 0
218 #define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
219 #define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
220
221#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
222 #define LCD_PWMDIV_EN (1<<12)
223 #define LCD_PWMDIV_PWMDIV_BIT 0
224 #define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
225 #define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
226
227#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
228 #define LCD_PWMHI_PWMHI1_BIT 12
229 #define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
230 #define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
231 #define LCD_PWMHI_PWMHI0_BIT 0
232 #define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
233 #define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
234
235#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
236 #define LCD_PALLETTE_MONO_MI_BIT 0
237 #define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
238 #define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
239
240 #define LCD_PALLETTE_COLOR_RI_BIT 8
241 #define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
242 #define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
243 #define LCD_PALLETTE_COLOR_GI_BIT 4
244 #define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
245 #define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
246 #define LCD_PALLETTE_COLOR_BI_BIT 0
247 #define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
248 #define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
249
250 #define LCD_PALLETTE_TFT_DC_BIT 0
251 #define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
252 #define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
253
254/********************************************************************/
255
256/* List of panels known to work with the AU1100 LCD controller.
257 * To add a new panel, enter the same specifications as the
258 * Generic_TFT one, and MAKE SURE that it doesn't conflicts
259 * with the controller restrictions. Restrictions are:
260 *
261 * STN color panels: max_bpp <= 12
262 * STN mono panels: max_bpp <= 4
263 * TFT panels: max_bpp <= 16
264 * max_xres <= 800
265 * max_yres <= 600
191 */ 266 */
192struct known_lcd_panels panels[] = 267static struct au1100fb_panel known_lcd_panels[] =
193{ 268{
194 { /* 0: Pb1100 LCDA: Sharp 320x240 TFT panel */ 269 /* 800x600x16bpp CRT */
195 320, /* xres */ 270 [0] = {
196 240, /* yres */ 271 .name = "CRT_800x600_16",
197 16, /* bpp */ 272 .xres = 800,
198 273 .yres = 600,
199 "Sharp_320x240_16", 274 .bpp = 16,
200 /* mode_control */ 275 .control_base = 0x0004886A |
276 LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
277 LCD_CONTROL_BPP_16,
278 .clkcontrol_base = 0x00020000,
279 .horztiming = 0x005aff1f,
280 .verttiming = 0x16000e57,
281 },
282 /* just the standard LCD */
283 [1] = {
284 .name = "WWPC LCD",
285 .xres = 240,
286 .yres = 320,
287 .bpp = 16,
288 .control_base = 0x0006806A,
289 .horztiming = 0x0A1010EF,
290 .verttiming = 0x0301013F,
291 .clkcontrol_base = 0x00018001,
292 },
293 /* Sharp 320x240 TFT panel */
294 [2] = {
295 .name = "Sharp_LQ038Q5DR01",
296 .xres = 320,
297 .yres = 240,
298 .bpp = 16,
299 .control_base =
201 ( LCD_CONTROL_SBPPF_565 300 ( LCD_CONTROL_SBPPF_565
202 /*LCD_CONTROL_WP*/
203 /*LCD_CONTROL_WD*/
204 | LCD_CONTROL_C 301 | LCD_CONTROL_C
205 | LCD_CONTROL_SM_0 302 | LCD_CONTROL_SM_0
206 /*LCD_CONTROL_DB*/ 303 | LCD_CONTROL_DEFAULT_PO
207 /*LCD_CONTROL_CCO*/
208 /*LCD_CONTROL_DP*/
209 | LCD_DEFAULT_PIX_FORMAT
210 /*LCD_CONTROL_MPI*/
211 | LCD_CONTROL_PT 304 | LCD_CONTROL_PT
212 | LCD_CONTROL_PC 305 | LCD_CONTROL_PC
213 | LCD_CONTROL_BPP_16 ), 306 | LCD_CONTROL_BPP_16 ),
214 307 .horztiming =
215 /* mode_horztiming */
216 ( LCD_HORZTIMING_HN2_N(8) 308 ( LCD_HORZTIMING_HN2_N(8)
217 | LCD_HORZTIMING_HN1_N(60) 309 | LCD_HORZTIMING_HN1_N(60)
218 | LCD_HORZTIMING_HPW_N(12) 310 | LCD_HORZTIMING_HPW_N(12)
219 | LCD_HORZTIMING_PPL_N(320) ), 311 | LCD_HORZTIMING_PPL_N(320) ),
220 312 .verttiming =
221 /* mode_verttiming */
222 ( LCD_VERTTIMING_VN2_N(5) 313 ( LCD_VERTTIMING_VN2_N(5)
223 | LCD_VERTTIMING_VN1_N(17) 314 | LCD_VERTTIMING_VN1_N(17)
224 | LCD_VERTTIMING_VPW_N(1) 315 | LCD_VERTTIMING_VPW_N(1)
225 | LCD_VERTTIMING_LPP_N(240) ), 316 | LCD_VERTTIMING_LPP_N(240) ),
226 317 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
227 /* mode_clkcontrol */
228 ( 0
229 /*LCD_CLKCONTROL_IB*/
230 /*LCD_CLKCONTROL_IC*/
231 /*LCD_CLKCONTROL_IH*/
232 /*LCD_CLKCONTROL_IV*/
233 | LCD_CLKCONTROL_PCD_N(1) ),
234
235 /* mode_pwmdiv */
236 0,
237
238 /* mode_pwmhi */
239 0,
240
241 /* mode_toyclksrc */
242 ((1<<7) | (1<<6) | (1<<5)),
243
244 /* mode_backlight */
245 6
246 }, 318 },
247 319
248 { /* 1: Pb1100 LCDC 640x480 TFT panel */ 320 /* Hitachi SP14Q005 and possibly others */
249 640, /* xres */ 321 [3] = {
250 480, /* yres */ 322 .name = "Hitachi_SP14Qxxx",
251 16, /* bpp */ 323 .xres = 320,
252 324 .yres = 240,
253 "Generic_640x480_16", 325 .bpp = 4,
254 326 .control_base =
255 /* mode_control */ 327 ( LCD_CONTROL_C
256 0x004806a | LCD_DEFAULT_PIX_FORMAT, 328 | LCD_CONTROL_BPP_4 ),
257 329 .horztiming =
258 /* mode_horztiming */ 330 ( LCD_HORZTIMING_HN2_N(1)
259 0x3434d67f, 331 | LCD_HORZTIMING_HN1_N(1)
260 332 | LCD_HORZTIMING_HPW_N(1)
261 /* mode_verttiming */ 333 | LCD_HORZTIMING_PPL_N(320) ),
262 0x0e0e39df, 334 .verttiming =
263 335 ( LCD_VERTTIMING_VN2_N(1)
264 /* mode_clkcontrol */ 336 | LCD_VERTTIMING_VN1_N(1)
265 ( 0 337 | LCD_VERTTIMING_VPW_N(1)
266 /*LCD_CLKCONTROL_IB*/ 338 | LCD_VERTTIMING_LPP_N(240) ),
267 /*LCD_CLKCONTROL_IC*/ 339 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
268 /*LCD_CLKCONTROL_IH*/
269 /*LCD_CLKCONTROL_IV*/
270 | LCD_CLKCONTROL_PCD_N(1) ),
271
272 /* mode_pwmdiv */
273 0,
274
275 /* mode_pwmhi */
276 0,
277
278 /* mode_toyclksrc */
279 ((1<<7) | (1<<6) | (0<<5)),
280
281 /* mode_backlight */
282 7
283 }, 340 },
284 341
285 { /* 2: Pb1100 LCDB 640x480 PrimeView TFT panel */ 342 /* Generic 640x480 TFT panel */
286 640, /* xres */ 343 [4] = {
287 480, /* yres */ 344 .name = "TFT_640x480_16",
288 16, /* bpp */ 345 .xres = 640,
289 346 .yres = 480,
290 "PrimeView_640x480_16", 347 .bpp = 16,
291 348 .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
292 /* mode_control */ 349 .horztiming = 0x3434d67f,
293 0x0004886a | LCD_DEFAULT_PIX_FORMAT, 350 .verttiming = 0x0e0e39df,
294 351 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
295 /* mode_horztiming */
296 0x0e4bfe7f,
297
298 /* mode_verttiming */
299 0x210805df,
300
301 /* mode_clkcontrol */
302 0x00038001,
303
304 /* mode_pwmdiv */
305 0,
306
307 /* mode_pwmhi */
308 0,
309
310 /* mode_toyclksrc */
311 ((1<<7) | (1<<6) | (0<<5)),
312
313 /* mode_backlight */
314 7
315 }, 352 },
316 353
317 { /* 3: Pb1100 800x600x16bpp NEON CRT */ 354 /* Pb1100 LCDB 640x480 PrimeView TFT panel */
318 800, /* xres */ 355 [5] = {
319 600, /* yres */ 356 .name = "PrimeView_640x480_16",
320 16, /* bpp */ 357 .xres = 640,
321 358 .yres = 480,
322 "NEON_800x600_16", 359 .bpp = 16,
323 360 .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
324 /* mode_control */ 361 .horztiming = 0x0e4bfe7f,
325 0x0004886A | LCD_DEFAULT_PIX_FORMAT, 362 .verttiming = 0x210805df,
326 363 .clkcontrol_base = 0x00038001,
327 /* mode_horztiming */
328 0x005AFF1F,
329
330 /* mode_verttiming */
331 0x16000E57,
332
333 /* mode_clkcontrol */
334 0x00020000,
335
336 /* mode_pwmdiv */
337 0,
338
339 /* mode_pwmhi */
340 0,
341
342 /* mode_toyclksrc */
343 ((1<<7) | (1<<6) | (0<<5)),
344
345 /* mode_backlight */
346 7
347 }, 364 },
365};
348 366
349 { /* 4: Pb1100 640x480x16bpp NEON CRT */ 367struct au1100fb_drv_info {
350 640, /* xres */ 368 int panel_idx;
351 480, /* yres */ 369 char *opt_mode;
352 16, /* bpp */ 370};
353
354 "NEON_640x480_16",
355
356 /* mode_control */
357 0x0004886A | LCD_DEFAULT_PIX_FORMAT,
358
359 /* mode_horztiming */
360 0x0052E27F,
361
362 /* mode_verttiming */
363 0x18000DDF,
364
365 /* mode_clkcontrol */
366 0x00020000,
367 371
368 /* mode_pwmdiv */ 372/********************************************************************/
369 0,
370 373
371 /* mode_pwmhi */ 374/* Inline helpers */
372 0,
373 375
374 /* mode_toyclksrc */ 376#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
375 ((1<<7) | (1<<6) | (0<<5)), 377#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
378#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
379#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
376 380
377 /* mode_backlight */
378 7
379 },
380};
381#endif /* _AU1100LCD_H */ 381#endif /* _AU1100LCD_H */
diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c
index e793ffd39db5..762c7a593141 100644
--- a/drivers/video/console/newport_con.c
+++ b/drivers/video/console/newport_con.c
@@ -32,7 +32,6 @@
32#include <linux/font.h> 32#include <linux/font.h>
33 33
34 34
35extern struct font_desc font_vga_8x16;
36extern unsigned long sgi_gfxaddr; 35extern unsigned long sgi_gfxaddr;
37 36
38#define FONT_DATA ((unsigned char *)font_vga_8x16.data) 37#define FONT_DATA ((unsigned char *)font_vga_8x16.data)
diff --git a/drivers/video/gbefb.c b/drivers/video/gbefb.c
index d3c1922cb13a..485604cd4462 100644
--- a/drivers/video/gbefb.c
+++ b/drivers/video/gbefb.c
@@ -1126,7 +1126,7 @@ static int __init gbefb_probe(struct device *dev)
1126 gbefb_setup(options); 1126 gbefb_setup(options);
1127#endif 1127#endif
1128 1128
1129 if (!request_mem_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) { 1129 if (!request_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) {
1130 printk(KERN_ERR "gbefb: couldn't reserve mmio region\n"); 1130 printk(KERN_ERR "gbefb: couldn't reserve mmio region\n");
1131 ret = -EBUSY; 1131 ret = -EBUSY;
1132 goto out_release_framebuffer; 1132 goto out_release_framebuffer;
@@ -1152,12 +1152,24 @@ static int __init gbefb_probe(struct device *dev)
1152 if (gbe_mem_phys) { 1152 if (gbe_mem_phys) {
1153 /* memory was allocated at boot time */ 1153 /* memory was allocated at boot time */
1154 gbe_mem = ioremap_nocache(gbe_mem_phys, gbe_mem_size); 1154 gbe_mem = ioremap_nocache(gbe_mem_phys, gbe_mem_size);
1155 if (!gbe_mem) {
1156 printk(KERN_ERR "gbefb: couldn't map framebuffer\n");
1157 ret = -ENOMEM;
1158 goto out_tiles_free;
1159 }
1160
1155 gbe_dma_addr = 0; 1161 gbe_dma_addr = 0;
1156 } else { 1162 } else {
1157 /* try to allocate memory with the classical allocator 1163 /* try to allocate memory with the classical allocator
1158 * this has high chance to fail on low memory machines */ 1164 * this has high chance to fail on low memory machines */
1159 gbe_mem = dma_alloc_coherent(NULL, gbe_mem_size, &gbe_dma_addr, 1165 gbe_mem = dma_alloc_coherent(NULL, gbe_mem_size, &gbe_dma_addr,
1160 GFP_KERNEL); 1166 GFP_KERNEL);
1167 if (!gbe_mem) {
1168 printk(KERN_ERR "gbefb: couldn't allocate framebuffer memory\n");
1169 ret = -ENOMEM;
1170 goto out_tiles_free;
1171 }
1172
1161 gbe_mem_phys = (unsigned long) gbe_dma_addr; 1173 gbe_mem_phys = (unsigned long) gbe_dma_addr;
1162 } 1174 }
1163 1175
@@ -1165,12 +1177,6 @@ static int __init gbefb_probe(struct device *dev)
1165 mtrr_add(gbe_mem_phys, gbe_mem_size, MTRR_TYPE_WRCOMB, 1); 1177 mtrr_add(gbe_mem_phys, gbe_mem_size, MTRR_TYPE_WRCOMB, 1);
1166#endif 1178#endif
1167 1179
1168 if (!gbe_mem) {
1169 printk(KERN_ERR "gbefb: couldn't map framebuffer\n");
1170 ret = -ENXIO;
1171 goto out_tiles_free;
1172 }
1173
1174 /* map framebuffer memory into tiles table */ 1180 /* map framebuffer memory into tiles table */
1175 for (i = 0; i < (gbe_mem_size >> TILE_SHIFT); i++) 1181 for (i = 0; i < (gbe_mem_size >> TILE_SHIFT); i++)
1176 gbe_tiles.cpu[i] = (gbe_mem_phys >> TILE_SHIFT) + i; 1182 gbe_tiles.cpu[i] = (gbe_mem_phys >> TILE_SHIFT) + i;
diff --git a/include/asm-mips/abi.h b/include/asm-mips/abi.h
new file mode 100644
index 000000000000..2e7e651c3e3f
--- /dev/null
+++ b/include/asm-mips/abi.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 by Ralf Baechle
7 * Copyright (C) 2005 MIPS Technologies, Inc.
8 */
9#ifndef _ASM_ABI_H
10#define _ASM_ABI_H
11
12#include <asm/signal.h>
13#include <asm/siginfo.h>
14
15struct mips_abi {
16 int (* const do_signal)(sigset_t *oldset, struct pt_regs *regs);
17 int (* const setup_frame)(struct k_sigaction * ka,
18 struct pt_regs *regs, int signr,
19 sigset_t *set);
20 int (* const setup_rt_frame)(struct k_sigaction * ka,
21 struct pt_regs *regs, int signr,
22 sigset_t *set, siginfo_t *info);
23};
24
25#endif /* _ASM_ABI_H */
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 7dc2619f5006..42520cc84b0f 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -20,10 +20,12 @@
20#define _ATYPE_ 20#define _ATYPE_
21#define _ATYPE32_ 21#define _ATYPE32_
22#define _ATYPE64_ 22#define _ATYPE64_
23#define _LLCONST_(x) x
23#else 24#else
24#define _ATYPE_ __PTRDIFF_TYPE__ 25#define _ATYPE_ __PTRDIFF_TYPE__
25#define _ATYPE32_ int 26#define _ATYPE32_ int
26#define _ATYPE64_ long long 27#define _ATYPE64_ long long
28#define _LLCONST_(x) x ## LL
27#endif 29#endif
28 30
29/* 31/*
@@ -45,8 +47,9 @@
45/* 47/*
46 * Returns the physical address of a CKSEGx / XKPHYS address 48 * Returns the physical address of a CKSEGx / XKPHYS address
47 */ 49 */
48#define CPHYSADDR(a) ((_ACAST32_ (a)) & 0x1fffffff) 50#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
49#define XPHYSADDR(a) ((_ACAST64_ (a)) & 0x000000ffffffffff) 51#define XPHYSADDR(a) ((_ACAST64_(a)) & \
52 _LLCONST_(0x000000ffffffffff))
50 53
51#ifdef CONFIG_64BIT 54#ifdef CONFIG_64BIT
52 55
@@ -55,14 +58,14 @@
55 * The compatibility segments use the full 64-bit sign extended value. Note 58 * The compatibility segments use the full 64-bit sign extended value. Note
56 * the R8000 doesn't have them so don't reference these in generic MIPS code. 59 * the R8000 doesn't have them so don't reference these in generic MIPS code.
57 */ 60 */
58#define XKUSEG 0x0000000000000000 61#define XKUSEG _LLCONST_(0x0000000000000000)
59#define XKSSEG 0x4000000000000000 62#define XKSSEG _LLCONST_(0x4000000000000000)
60#define XKPHYS 0x8000000000000000 63#define XKPHYS _LLCONST_(0x8000000000000000)
61#define XKSEG 0xc000000000000000 64#define XKSEG _LLCONST_(0xc000000000000000)
62#define CKSEG0 0xffffffff80000000 65#define CKSEG0 _LLCONST_(0xffffffff80000000)
63#define CKSEG1 0xffffffffa0000000 66#define CKSEG1 _LLCONST_(0xffffffffa0000000)
64#define CKSSEG 0xffffffffc0000000 67#define CKSSEG _LLCONST_(0xffffffffc0000000)
65#define CKSEG3 0xffffffffe0000000 68#define CKSEG3 _LLCONST_(0xffffffffe0000000)
66 69
67#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) 70#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
68#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) 71#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
@@ -120,7 +123,8 @@
120#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) 123#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
121#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) 124#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
122#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) 125#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
123#define PHYS_TO_XKPHYS(cm,a) (0x8000000000000000 | ((cm)<<59) | (a)) 126#define PHYS_TO_XKPHYS(cm,a) (_LLCONST_(0x8000000000000000) | \
127 ((cm)<<59) | (a))
124 128
125#if defined (CONFIG_CPU_R4300) \ 129#if defined (CONFIG_CPU_R4300) \
126 || defined (CONFIG_CPU_R4X00) \ 130 || defined (CONFIG_CPU_R4X00) \
@@ -128,46 +132,56 @@
128 || defined (CONFIG_CPU_NEVADA) \ 132 || defined (CONFIG_CPU_NEVADA) \
129 || defined (CONFIG_CPU_TX49XX) \ 133 || defined (CONFIG_CPU_TX49XX) \
130 || defined (CONFIG_CPU_MIPS64) 134 || defined (CONFIG_CPU_MIPS64)
131#define KUSIZE 0x0000010000000000 /* 2^^40 */ 135#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
132#define KUSIZE_64 0x0000010000000000 /* 2^^40 */ 136#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
133#define K0SIZE 0x0000001000000000 /* 2^^36 */ 137#define K0SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */
134#define K1SIZE 0x0000001000000000 /* 2^^36 */ 138#define K1SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */
135#define K2SIZE 0x000000ff80000000 139#define K2SIZE _LLCONST_(0x000000ff80000000)
136#define KSEGSIZE 0x000000ff80000000 /* max syssegsz */ 140#define KSEGSIZE _LLCONST_(0x000000ff80000000) /* max syssegsz */
137#define TO_PHYS_MASK 0x0000000fffffffff /* 2^^36 - 1 */ 141#define TO_PHYS_MASK _LLCONST_(0x0000000fffffffff) /* 2^^36 - 1 */
138#endif 142#endif
139 143
140#if defined (CONFIG_CPU_R8000) 144#if defined (CONFIG_CPU_R8000)
141/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */ 145/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
142#define KUSIZE 0x0000010000000000 /* 2^^40 */ 146#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
143#define KUSIZE_64 0x0000010000000000 /* 2^^40 */ 147#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
144#define K0SIZE 0x0000010000000000 /* 2^^40 */ 148#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
145#define K1SIZE 0x0000010000000000 /* 2^^40 */ 149#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
146#define K2SIZE 0x0001000000000000 150#define K2SIZE _LLCONST_(0x0001000000000000)
147#define KSEGSIZE 0x0000010000000000 /* max syssegsz */ 151#define KSEGSIZE _LLCONST_(0x0000010000000000) /* max syssegsz */
148#define TO_PHYS_MASK 0x000000ffffffffff /* 2^^40 - 1 */ 152#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
149#endif 153#endif
150 154
151#if defined (CONFIG_CPU_R10000) 155#if defined (CONFIG_CPU_R10000)
152#define KUSIZE 0x0000010000000000 /* 2^^40 */ 156#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
153#define KUSIZE_64 0x0000010000000000 /* 2^^40 */ 157#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
154#define K0SIZE 0x0000010000000000 /* 2^^40 */ 158#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
155#define K1SIZE 0x0000010000000000 /* 2^^40 */ 159#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
156#define K2SIZE 0x00000fff80000000 160#define K2SIZE _LLCONST_(0x00000fff80000000)
157#define KSEGSIZE 0x00000fff80000000 /* max syssegsz */ 161#define KSEGSIZE _LLCONST_(0x00000fff80000000) /* max syssegsz */
158#define TO_PHYS_MASK 0x000000ffffffffff /* 2^^40 - 1 */ 162#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
163#endif
164
165#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
166#define KUSIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
167#define KUSIZE_64 _LLCONST_(0x0000100000000000) /* 2^^44 */
168#define K0SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
169#define K1SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
170#define K2SIZE _LLCONST_(0x0000ffff80000000)
171#define KSEGSIZE _LLCONST_(0x0000ffff80000000) /* max syssegsz */
172#define TO_PHYS_MASK _LLCONST_(0x00000fffffffffff) /* 2^^44 - 1 */
159#endif 173#endif
160 174
161/* 175/*
162 * Further names for SGI source compatibility. These are stolen from 176 * Further names for SGI source compatibility. These are stolen from
163 * IRIX's <sys/mips_addrspace.h>. 177 * IRIX's <sys/mips_addrspace.h>.
164 */ 178 */
165#define KUBASE 0 179#define KUBASE _LLCONST_(0)
166#define KUSIZE_32 0x0000000080000000 /* KUSIZE 180#define KUSIZE_32 _LLCONST_(0x0000000080000000) /* KUSIZE
167 for a 32 bit proc */ 181 for a 32 bit proc */
168#define K0BASE_EXL_WR 0xa800000000000000 /* exclusive on write */ 182#define K0BASE_EXL_WR _LLCONST_(0xa800000000000000) /* exclusive on write */
169#define K0BASE_NONCOH 0x9800000000000000 /* noncoherent */ 183#define K0BASE_NONCOH _LLCONST_(0x9800000000000000) /* noncoherent */
170#define K0BASE_EXL 0xa000000000000000 /* exclusive */ 184#define K0BASE_EXL _LLCONST_(0xa000000000000000) /* exclusive */
171 185
172#ifndef CONFIG_CPU_R8000 186#ifndef CONFIG_CPU_R8000
173 187
@@ -176,7 +190,7 @@
176 * in order to catch bugs in the source code. 190 * in order to catch bugs in the source code.
177 */ 191 */
178 192
179#define COMPAT_K1BASE32 0xffffffffa0000000 193#define COMPAT_K1BASE32 _LLCONST_(0xffffffffa0000000)
180#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ 194#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
181 195
182#endif 196#endif
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
index f53237772985..4b090f3142e0 100644
--- a/include/asm-mips/asm.h
+++ b/include/asm-mips/asm.h
@@ -107,6 +107,7 @@ symbol = value
107/* 107/*
108 * Print formatted string 108 * Print formatted string
109 */ 109 */
110#ifdef CONFIG_PRINTK
110#define PRINT(string) \ 111#define PRINT(string) \
111 .set push; \ 112 .set push; \
112 .set reorder; \ 113 .set reorder; \
@@ -114,6 +115,9 @@ symbol = value
114 jal printk; \ 115 jal printk; \
115 .set pop; \ 116 .set pop; \
116 TEXT(string) 117 TEXT(string)
118#else
119#define PRINT(string)
120#endif
117 121
118#define TEXT(msg) \ 122#define TEXT(msg) \
119 .pushsection .data; \ 123 .pushsection .data; \
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index c0bd8d014e14..6202eb8a14b7 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -62,20 +62,24 @@ static __inline__ void atomic_add(int i, atomic_t * v)
62 unsigned long temp; 62 unsigned long temp;
63 63
64 __asm__ __volatile__( 64 __asm__ __volatile__(
65 " .set mips3 \n"
65 "1: ll %0, %1 # atomic_add \n" 66 "1: ll %0, %1 # atomic_add \n"
66 " addu %0, %2 \n" 67 " addu %0, %2 \n"
67 " sc %0, %1 \n" 68 " sc %0, %1 \n"
68 " beqzl %0, 1b \n" 69 " beqzl %0, 1b \n"
70 " .set mips0 \n"
69 : "=&r" (temp), "=m" (v->counter) 71 : "=&r" (temp), "=m" (v->counter)
70 : "Ir" (i), "m" (v->counter)); 72 : "Ir" (i), "m" (v->counter));
71 } else if (cpu_has_llsc) { 73 } else if (cpu_has_llsc) {
72 unsigned long temp; 74 unsigned long temp;
73 75
74 __asm__ __volatile__( 76 __asm__ __volatile__(
77 " .set mips3 \n"
75 "1: ll %0, %1 # atomic_add \n" 78 "1: ll %0, %1 # atomic_add \n"
76 " addu %0, %2 \n" 79 " addu %0, %2 \n"
77 " sc %0, %1 \n" 80 " sc %0, %1 \n"
78 " beqz %0, 1b \n" 81 " beqz %0, 1b \n"
82 " .set mips0 \n"
79 : "=&r" (temp), "=m" (v->counter) 83 : "=&r" (temp), "=m" (v->counter)
80 : "Ir" (i), "m" (v->counter)); 84 : "Ir" (i), "m" (v->counter));
81 } else { 85 } else {
@@ -100,20 +104,24 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
100 unsigned long temp; 104 unsigned long temp;
101 105
102 __asm__ __volatile__( 106 __asm__ __volatile__(
107 " .set mips3 \n"
103 "1: ll %0, %1 # atomic_sub \n" 108 "1: ll %0, %1 # atomic_sub \n"
104 " subu %0, %2 \n" 109 " subu %0, %2 \n"
105 " sc %0, %1 \n" 110 " sc %0, %1 \n"
106 " beqzl %0, 1b \n" 111 " beqzl %0, 1b \n"
112 " .set mips0 \n"
107 : "=&r" (temp), "=m" (v->counter) 113 : "=&r" (temp), "=m" (v->counter)
108 : "Ir" (i), "m" (v->counter)); 114 : "Ir" (i), "m" (v->counter));
109 } else if (cpu_has_llsc) { 115 } else if (cpu_has_llsc) {
110 unsigned long temp; 116 unsigned long temp;
111 117
112 __asm__ __volatile__( 118 __asm__ __volatile__(
119 " .set mips3 \n"
113 "1: ll %0, %1 # atomic_sub \n" 120 "1: ll %0, %1 # atomic_sub \n"
114 " subu %0, %2 \n" 121 " subu %0, %2 \n"
115 " sc %0, %1 \n" 122 " sc %0, %1 \n"
116 " beqz %0, 1b \n" 123 " beqz %0, 1b \n"
124 " .set mips0 \n"
117 : "=&r" (temp), "=m" (v->counter) 125 : "=&r" (temp), "=m" (v->counter)
118 : "Ir" (i), "m" (v->counter)); 126 : "Ir" (i), "m" (v->counter));
119 } else { 127 } else {
@@ -136,12 +144,14 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
136 unsigned long temp; 144 unsigned long temp;
137 145
138 __asm__ __volatile__( 146 __asm__ __volatile__(
147 " .set mips3 \n"
139 "1: ll %1, %2 # atomic_add_return \n" 148 "1: ll %1, %2 # atomic_add_return \n"
140 " addu %0, %1, %3 \n" 149 " addu %0, %1, %3 \n"
141 " sc %0, %2 \n" 150 " sc %0, %2 \n"
142 " beqzl %0, 1b \n" 151 " beqzl %0, 1b \n"
143 " addu %0, %1, %3 \n" 152 " addu %0, %1, %3 \n"
144 " sync \n" 153 " sync \n"
154 " .set mips0 \n"
145 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 155 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
146 : "Ir" (i), "m" (v->counter) 156 : "Ir" (i), "m" (v->counter)
147 : "memory"); 157 : "memory");
@@ -149,12 +159,14 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
149 unsigned long temp; 159 unsigned long temp;
150 160
151 __asm__ __volatile__( 161 __asm__ __volatile__(
162 " .set mips3 \n"
152 "1: ll %1, %2 # atomic_add_return \n" 163 "1: ll %1, %2 # atomic_add_return \n"
153 " addu %0, %1, %3 \n" 164 " addu %0, %1, %3 \n"
154 " sc %0, %2 \n" 165 " sc %0, %2 \n"
155 " beqz %0, 1b \n" 166 " beqz %0, 1b \n"
156 " addu %0, %1, %3 \n" 167 " addu %0, %1, %3 \n"
157 " sync \n" 168 " sync \n"
169 " .set mips0 \n"
158 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 170 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
159 : "Ir" (i), "m" (v->counter) 171 : "Ir" (i), "m" (v->counter)
160 : "memory"); 172 : "memory");
@@ -179,12 +191,14 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
179 unsigned long temp; 191 unsigned long temp;
180 192
181 __asm__ __volatile__( 193 __asm__ __volatile__(
194 " .set mips3 \n"
182 "1: ll %1, %2 # atomic_sub_return \n" 195 "1: ll %1, %2 # atomic_sub_return \n"
183 " subu %0, %1, %3 \n" 196 " subu %0, %1, %3 \n"
184 " sc %0, %2 \n" 197 " sc %0, %2 \n"
185 " beqzl %0, 1b \n" 198 " beqzl %0, 1b \n"
186 " subu %0, %1, %3 \n" 199 " subu %0, %1, %3 \n"
187 " sync \n" 200 " sync \n"
201 " .set mips0 \n"
188 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 202 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
189 : "Ir" (i), "m" (v->counter) 203 : "Ir" (i), "m" (v->counter)
190 : "memory"); 204 : "memory");
@@ -192,12 +206,14 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
192 unsigned long temp; 206 unsigned long temp;
193 207
194 __asm__ __volatile__( 208 __asm__ __volatile__(
209 " .set mips3 \n"
195 "1: ll %1, %2 # atomic_sub_return \n" 210 "1: ll %1, %2 # atomic_sub_return \n"
196 " subu %0, %1, %3 \n" 211 " subu %0, %1, %3 \n"
197 " sc %0, %2 \n" 212 " sc %0, %2 \n"
198 " beqz %0, 1b \n" 213 " beqz %0, 1b \n"
199 " subu %0, %1, %3 \n" 214 " subu %0, %1, %3 \n"
200 " sync \n" 215 " sync \n"
216 " .set mips0 \n"
201 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 217 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
202 : "Ir" (i), "m" (v->counter) 218 : "Ir" (i), "m" (v->counter)
203 : "memory"); 219 : "memory");
@@ -229,6 +245,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
229 unsigned long temp; 245 unsigned long temp;
230 246
231 __asm__ __volatile__( 247 __asm__ __volatile__(
248 " .set mips3 \n"
232 "1: ll %1, %2 # atomic_sub_if_positive\n" 249 "1: ll %1, %2 # atomic_sub_if_positive\n"
233 " subu %0, %1, %3 \n" 250 " subu %0, %1, %3 \n"
234 " bltz %0, 1f \n" 251 " bltz %0, 1f \n"
@@ -236,6 +253,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
236 " beqzl %0, 1b \n" 253 " beqzl %0, 1b \n"
237 " sync \n" 254 " sync \n"
238 "1: \n" 255 "1: \n"
256 " .set mips0 \n"
239 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 257 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
240 : "Ir" (i), "m" (v->counter) 258 : "Ir" (i), "m" (v->counter)
241 : "memory"); 259 : "memory");
@@ -243,6 +261,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
243 unsigned long temp; 261 unsigned long temp;
244 262
245 __asm__ __volatile__( 263 __asm__ __volatile__(
264 " .set mips3 \n"
246 "1: ll %1, %2 # atomic_sub_if_positive\n" 265 "1: ll %1, %2 # atomic_sub_if_positive\n"
247 " subu %0, %1, %3 \n" 266 " subu %0, %1, %3 \n"
248 " bltz %0, 1f \n" 267 " bltz %0, 1f \n"
@@ -250,6 +269,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
250 " beqz %0, 1b \n" 269 " beqz %0, 1b \n"
251 " sync \n" 270 " sync \n"
252 "1: \n" 271 "1: \n"
272 " .set mips0 \n"
253 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 273 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
254 : "Ir" (i), "m" (v->counter) 274 : "Ir" (i), "m" (v->counter)
255 : "memory"); 275 : "memory");
@@ -367,20 +387,24 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
367 unsigned long temp; 387 unsigned long temp;
368 388
369 __asm__ __volatile__( 389 __asm__ __volatile__(
390 " .set mips3 \n"
370 "1: lld %0, %1 # atomic64_add \n" 391 "1: lld %0, %1 # atomic64_add \n"
371 " addu %0, %2 \n" 392 " addu %0, %2 \n"
372 " scd %0, %1 \n" 393 " scd %0, %1 \n"
373 " beqzl %0, 1b \n" 394 " beqzl %0, 1b \n"
395 " .set mips0 \n"
374 : "=&r" (temp), "=m" (v->counter) 396 : "=&r" (temp), "=m" (v->counter)
375 : "Ir" (i), "m" (v->counter)); 397 : "Ir" (i), "m" (v->counter));
376 } else if (cpu_has_llsc) { 398 } else if (cpu_has_llsc) {
377 unsigned long temp; 399 unsigned long temp;
378 400
379 __asm__ __volatile__( 401 __asm__ __volatile__(
402 " .set mips3 \n"
380 "1: lld %0, %1 # atomic64_add \n" 403 "1: lld %0, %1 # atomic64_add \n"
381 " addu %0, %2 \n" 404 " addu %0, %2 \n"
382 " scd %0, %1 \n" 405 " scd %0, %1 \n"
383 " beqz %0, 1b \n" 406 " beqz %0, 1b \n"
407 " .set mips0 \n"
384 : "=&r" (temp), "=m" (v->counter) 408 : "=&r" (temp), "=m" (v->counter)
385 : "Ir" (i), "m" (v->counter)); 409 : "Ir" (i), "m" (v->counter));
386 } else { 410 } else {
@@ -405,20 +429,24 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
405 unsigned long temp; 429 unsigned long temp;
406 430
407 __asm__ __volatile__( 431 __asm__ __volatile__(
432 " .set mips3 \n"
408 "1: lld %0, %1 # atomic64_sub \n" 433 "1: lld %0, %1 # atomic64_sub \n"
409 " subu %0, %2 \n" 434 " subu %0, %2 \n"
410 " scd %0, %1 \n" 435 " scd %0, %1 \n"
411 " beqzl %0, 1b \n" 436 " beqzl %0, 1b \n"
437 " .set mips0 \n"
412 : "=&r" (temp), "=m" (v->counter) 438 : "=&r" (temp), "=m" (v->counter)
413 : "Ir" (i), "m" (v->counter)); 439 : "Ir" (i), "m" (v->counter));
414 } else if (cpu_has_llsc) { 440 } else if (cpu_has_llsc) {
415 unsigned long temp; 441 unsigned long temp;
416 442
417 __asm__ __volatile__( 443 __asm__ __volatile__(
444 " .set mips3 \n"
418 "1: lld %0, %1 # atomic64_sub \n" 445 "1: lld %0, %1 # atomic64_sub \n"
419 " subu %0, %2 \n" 446 " subu %0, %2 \n"
420 " scd %0, %1 \n" 447 " scd %0, %1 \n"
421 " beqz %0, 1b \n" 448 " beqz %0, 1b \n"
449 " .set mips0 \n"
422 : "=&r" (temp), "=m" (v->counter) 450 : "=&r" (temp), "=m" (v->counter)
423 : "Ir" (i), "m" (v->counter)); 451 : "Ir" (i), "m" (v->counter));
424 } else { 452 } else {
@@ -441,12 +469,14 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
441 unsigned long temp; 469 unsigned long temp;
442 470
443 __asm__ __volatile__( 471 __asm__ __volatile__(
472 " .set mips3 \n"
444 "1: lld %1, %2 # atomic64_add_return \n" 473 "1: lld %1, %2 # atomic64_add_return \n"
445 " addu %0, %1, %3 \n" 474 " addu %0, %1, %3 \n"
446 " scd %0, %2 \n" 475 " scd %0, %2 \n"
447 " beqzl %0, 1b \n" 476 " beqzl %0, 1b \n"
448 " addu %0, %1, %3 \n" 477 " addu %0, %1, %3 \n"
449 " sync \n" 478 " sync \n"
479 " .set mips0 \n"
450 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 480 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
451 : "Ir" (i), "m" (v->counter) 481 : "Ir" (i), "m" (v->counter)
452 : "memory"); 482 : "memory");
@@ -454,12 +484,14 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
454 unsigned long temp; 484 unsigned long temp;
455 485
456 __asm__ __volatile__( 486 __asm__ __volatile__(
487 " .set mips3 \n"
457 "1: lld %1, %2 # atomic64_add_return \n" 488 "1: lld %1, %2 # atomic64_add_return \n"
458 " addu %0, %1, %3 \n" 489 " addu %0, %1, %3 \n"
459 " scd %0, %2 \n" 490 " scd %0, %2 \n"
460 " beqz %0, 1b \n" 491 " beqz %0, 1b \n"
461 " addu %0, %1, %3 \n" 492 " addu %0, %1, %3 \n"
462 " sync \n" 493 " sync \n"
494 " .set mips0 \n"
463 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 495 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
464 : "Ir" (i), "m" (v->counter) 496 : "Ir" (i), "m" (v->counter)
465 : "memory"); 497 : "memory");
@@ -484,12 +516,14 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
484 unsigned long temp; 516 unsigned long temp;
485 517
486 __asm__ __volatile__( 518 __asm__ __volatile__(
519 " .set mips3 \n"
487 "1: lld %1, %2 # atomic64_sub_return \n" 520 "1: lld %1, %2 # atomic64_sub_return \n"
488 " subu %0, %1, %3 \n" 521 " subu %0, %1, %3 \n"
489 " scd %0, %2 \n" 522 " scd %0, %2 \n"
490 " beqzl %0, 1b \n" 523 " beqzl %0, 1b \n"
491 " subu %0, %1, %3 \n" 524 " subu %0, %1, %3 \n"
492 " sync \n" 525 " sync \n"
526 " .set mips0 \n"
493 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 527 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
494 : "Ir" (i), "m" (v->counter) 528 : "Ir" (i), "m" (v->counter)
495 : "memory"); 529 : "memory");
@@ -497,12 +531,14 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
497 unsigned long temp; 531 unsigned long temp;
498 532
499 __asm__ __volatile__( 533 __asm__ __volatile__(
534 " .set mips3 \n"
500 "1: lld %1, %2 # atomic64_sub_return \n" 535 "1: lld %1, %2 # atomic64_sub_return \n"
501 " subu %0, %1, %3 \n" 536 " subu %0, %1, %3 \n"
502 " scd %0, %2 \n" 537 " scd %0, %2 \n"
503 " beqz %0, 1b \n" 538 " beqz %0, 1b \n"
504 " subu %0, %1, %3 \n" 539 " subu %0, %1, %3 \n"
505 " sync \n" 540 " sync \n"
541 " .set mips0 \n"
506 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 542 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
507 : "Ir" (i), "m" (v->counter) 543 : "Ir" (i), "m" (v->counter)
508 : "memory"); 544 : "memory");
@@ -534,6 +570,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
534 unsigned long temp; 570 unsigned long temp;
535 571
536 __asm__ __volatile__( 572 __asm__ __volatile__(
573 " .set mips3 \n"
537 "1: lld %1, %2 # atomic64_sub_if_positive\n" 574 "1: lld %1, %2 # atomic64_sub_if_positive\n"
538 " dsubu %0, %1, %3 \n" 575 " dsubu %0, %1, %3 \n"
539 " bltz %0, 1f \n" 576 " bltz %0, 1f \n"
@@ -541,6 +578,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
541 " beqzl %0, 1b \n" 578 " beqzl %0, 1b \n"
542 " sync \n" 579 " sync \n"
543 "1: \n" 580 "1: \n"
581 " .set mips0 \n"
544 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 582 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
545 : "Ir" (i), "m" (v->counter) 583 : "Ir" (i), "m" (v->counter)
546 : "memory"); 584 : "memory");
@@ -548,6 +586,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
548 unsigned long temp; 586 unsigned long temp;
549 587
550 __asm__ __volatile__( 588 __asm__ __volatile__(
589 " .set mips3 \n"
551 "1: lld %1, %2 # atomic64_sub_if_positive\n" 590 "1: lld %1, %2 # atomic64_sub_if_positive\n"
552 " dsubu %0, %1, %3 \n" 591 " dsubu %0, %1, %3 \n"
553 " bltz %0, 1f \n" 592 " bltz %0, 1f \n"
@@ -555,6 +594,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
555 " beqz %0, 1b \n" 594 " beqz %0, 1b \n"
556 " sync \n" 595 " sync \n"
557 "1: \n" 596 "1: \n"
597 " .set mips0 \n"
558 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 598 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
559 : "Ir" (i), "m" (v->counter) 599 : "Ir" (i), "m" (v->counter)
560 : "memory"); 600 : "memory");
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index eb8d79dba11c..5496f9064a6a 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -12,20 +12,21 @@
12#include <linux/config.h> 12#include <linux/config.h>
13#include <linux/compiler.h> 13#include <linux/compiler.h>
14#include <linux/types.h> 14#include <linux/types.h>
15#include <asm/bug.h>
15#include <asm/byteorder.h> /* sigh ... */ 16#include <asm/byteorder.h> /* sigh ... */
16#include <asm/cpu-features.h> 17#include <asm/cpu-features.h>
17 18
18#if (_MIPS_SZLONG == 32) 19#if (_MIPS_SZLONG == 32)
19#define SZLONG_LOG 5 20#define SZLONG_LOG 5
20#define SZLONG_MASK 31UL 21#define SZLONG_MASK 31UL
21#define __LL "ll " 22#define __LL "ll "
22#define __SC "sc " 23#define __SC "sc "
23#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) 24#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
24#elif (_MIPS_SZLONG == 64) 25#elif (_MIPS_SZLONG == 64)
25#define SZLONG_LOG 6 26#define SZLONG_LOG 6
26#define SZLONG_MASK 63UL 27#define SZLONG_MASK 63UL
27#define __LL "lld " 28#define __LL "lld "
28#define __SC "scd " 29#define __SC "scd "
29#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) 30#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
30#endif 31#endif
31 32
@@ -72,18 +73,22 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
72 73
73 if (cpu_has_llsc && R10000_LLSC_WAR) { 74 if (cpu_has_llsc && R10000_LLSC_WAR) {
74 __asm__ __volatile__( 75 __asm__ __volatile__(
76 " .set mips3 \n"
75 "1: " __LL "%0, %1 # set_bit \n" 77 "1: " __LL "%0, %1 # set_bit \n"
76 " or %0, %2 \n" 78 " or %0, %2 \n"
77 " "__SC "%0, %1 \n" 79 " " __SC "%0, %1 \n"
78 " beqzl %0, 1b \n" 80 " beqzl %0, 1b \n"
81 " .set mips0 \n"
79 : "=&r" (temp), "=m" (*m) 82 : "=&r" (temp), "=m" (*m)
80 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); 83 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
81 } else if (cpu_has_llsc) { 84 } else if (cpu_has_llsc) {
82 __asm__ __volatile__( 85 __asm__ __volatile__(
86 " .set mips3 \n"
83 "1: " __LL "%0, %1 # set_bit \n" 87 "1: " __LL "%0, %1 # set_bit \n"
84 " or %0, %2 \n" 88 " or %0, %2 \n"
85 " "__SC "%0, %1 \n" 89 " " __SC "%0, %1 \n"
86 " beqz %0, 1b \n" 90 " beqz %0, 1b \n"
91 " .set mips0 \n"
87 : "=&r" (temp), "=m" (*m) 92 : "=&r" (temp), "=m" (*m)
88 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); 93 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
89 } else { 94 } else {
@@ -132,18 +137,22 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
132 137
133 if (cpu_has_llsc && R10000_LLSC_WAR) { 138 if (cpu_has_llsc && R10000_LLSC_WAR) {
134 __asm__ __volatile__( 139 __asm__ __volatile__(
140 " .set mips3 \n"
135 "1: " __LL "%0, %1 # clear_bit \n" 141 "1: " __LL "%0, %1 # clear_bit \n"
136 " and %0, %2 \n" 142 " and %0, %2 \n"
137 " " __SC "%0, %1 \n" 143 " " __SC "%0, %1 \n"
138 " beqzl %0, 1b \n" 144 " beqzl %0, 1b \n"
145 " .set mips0 \n"
139 : "=&r" (temp), "=m" (*m) 146 : "=&r" (temp), "=m" (*m)
140 : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); 147 : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
141 } else if (cpu_has_llsc) { 148 } else if (cpu_has_llsc) {
142 __asm__ __volatile__( 149 __asm__ __volatile__(
150 " .set mips3 \n"
143 "1: " __LL "%0, %1 # clear_bit \n" 151 "1: " __LL "%0, %1 # clear_bit \n"
144 " and %0, %2 \n" 152 " and %0, %2 \n"
145 " " __SC "%0, %1 \n" 153 " " __SC "%0, %1 \n"
146 " beqz %0, 1b \n" 154 " beqz %0, 1b \n"
155 " .set mips0 \n"
147 : "=&r" (temp), "=m" (*m) 156 : "=&r" (temp), "=m" (*m)
148 : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); 157 : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
149 } else { 158 } else {
@@ -191,10 +200,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
191 unsigned long temp; 200 unsigned long temp;
192 201
193 __asm__ __volatile__( 202 __asm__ __volatile__(
203 " .set mips3 \n"
194 "1: " __LL "%0, %1 # change_bit \n" 204 "1: " __LL "%0, %1 # change_bit \n"
195 " xor %0, %2 \n" 205 " xor %0, %2 \n"
196 " "__SC "%0, %1 \n" 206 " " __SC "%0, %1 \n"
197 " beqzl %0, 1b \n" 207 " beqzl %0, 1b \n"
208 " .set mips0 \n"
198 : "=&r" (temp), "=m" (*m) 209 : "=&r" (temp), "=m" (*m)
199 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); 210 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
200 } else if (cpu_has_llsc) { 211 } else if (cpu_has_llsc) {
@@ -202,10 +213,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
202 unsigned long temp; 213 unsigned long temp;
203 214
204 __asm__ __volatile__( 215 __asm__ __volatile__(
216 " .set mips3 \n"
205 "1: " __LL "%0, %1 # change_bit \n" 217 "1: " __LL "%0, %1 # change_bit \n"
206 " xor %0, %2 \n" 218 " xor %0, %2 \n"
207 " "__SC "%0, %1 \n" 219 " " __SC "%0, %1 \n"
208 " beqz %0, 1b \n" 220 " beqz %0, 1b \n"
221 " .set mips0 \n"
209 : "=&r" (temp), "=m" (*m) 222 : "=&r" (temp), "=m" (*m)
210 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); 223 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
211 } else { 224 } else {
@@ -253,14 +266,16 @@ static inline int test_and_set_bit(unsigned long nr,
253 unsigned long temp, res; 266 unsigned long temp, res;
254 267
255 __asm__ __volatile__( 268 __asm__ __volatile__(
269 " .set mips3 \n"
256 "1: " __LL "%0, %1 # test_and_set_bit \n" 270 "1: " __LL "%0, %1 # test_and_set_bit \n"
257 " or %2, %0, %3 \n" 271 " or %2, %0, %3 \n"
258 " " __SC "%2, %1 \n" 272 " " __SC "%2, %1 \n"
259 " beqzl %2, 1b \n" 273 " beqzl %2, 1b \n"
260 " and %2, %0, %3 \n" 274 " and %2, %0, %3 \n"
261#ifdef CONFIG_SMP 275#ifdef CONFIG_SMP
262 "sync \n" 276 " sync \n"
263#endif 277#endif
278 " .set mips0 \n"
264 : "=&r" (temp), "=m" (*m), "=&r" (res) 279 : "=&r" (temp), "=m" (*m), "=&r" (res)
265 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 280 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
266 : "memory"); 281 : "memory");
@@ -271,16 +286,18 @@ static inline int test_and_set_bit(unsigned long nr,
271 unsigned long temp, res; 286 unsigned long temp, res;
272 287
273 __asm__ __volatile__( 288 __asm__ __volatile__(
274 " .set noreorder # test_and_set_bit \n" 289 " .set push \n"
275 "1: " __LL "%0, %1 \n" 290 " .set noreorder \n"
291 " .set mips3 \n"
292 "1: " __LL "%0, %1 # test_and_set_bit \n"
276 " or %2, %0, %3 \n" 293 " or %2, %0, %3 \n"
277 " " __SC "%2, %1 \n" 294 " " __SC "%2, %1 \n"
278 " beqz %2, 1b \n" 295 " beqz %2, 1b \n"
279 " and %2, %0, %3 \n" 296 " and %2, %0, %3 \n"
280#ifdef CONFIG_SMP 297#ifdef CONFIG_SMP
281 "sync \n" 298 " sync \n"
282#endif 299#endif
283 ".set\treorder" 300 " .set pop \n"
284 : "=&r" (temp), "=m" (*m), "=&r" (res) 301 : "=&r" (temp), "=m" (*m), "=&r" (res)
285 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 302 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
286 : "memory"); 303 : "memory");
@@ -343,15 +360,17 @@ static inline int test_and_clear_bit(unsigned long nr,
343 unsigned long temp, res; 360 unsigned long temp, res;
344 361
345 __asm__ __volatile__( 362 __asm__ __volatile__(
363 " .set mips3 \n"
346 "1: " __LL "%0, %1 # test_and_clear_bit \n" 364 "1: " __LL "%0, %1 # test_and_clear_bit \n"
347 " or %2, %0, %3 \n" 365 " or %2, %0, %3 \n"
348 " xor %2, %3 \n" 366 " xor %2, %3 \n"
349 __SC "%2, %1 \n" 367 " " __SC "%2, %1 \n"
350 " beqzl %2, 1b \n" 368 " beqzl %2, 1b \n"
351 " and %2, %0, %3 \n" 369 " and %2, %0, %3 \n"
352#ifdef CONFIG_SMP 370#ifdef CONFIG_SMP
353 " sync \n" 371 " sync \n"
354#endif 372#endif
373 " .set mips0 \n"
355 : "=&r" (temp), "=m" (*m), "=&r" (res) 374 : "=&r" (temp), "=m" (*m), "=&r" (res)
356 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 375 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
357 : "memory"); 376 : "memory");
@@ -362,17 +381,19 @@ static inline int test_and_clear_bit(unsigned long nr,
362 unsigned long temp, res; 381 unsigned long temp, res;
363 382
364 __asm__ __volatile__( 383 __asm__ __volatile__(
365 " .set noreorder # test_and_clear_bit \n" 384 " .set push \n"
366 "1: " __LL "%0, %1 \n" 385 " .set noreorder \n"
386 " .set mips3 \n"
387 "1: " __LL "%0, %1 # test_and_clear_bit \n"
367 " or %2, %0, %3 \n" 388 " or %2, %0, %3 \n"
368 " xor %2, %3 \n" 389 " xor %2, %3 \n"
369 __SC "%2, %1 \n" 390 " " __SC "%2, %1 \n"
370 " beqz %2, 1b \n" 391 " beqz %2, 1b \n"
371 " and %2, %0, %3 \n" 392 " and %2, %0, %3 \n"
372#ifdef CONFIG_SMP 393#ifdef CONFIG_SMP
373 " sync \n" 394 " sync \n"
374#endif 395#endif
375 " .set reorder \n" 396 " .set pop \n"
376 : "=&r" (temp), "=m" (*m), "=&r" (res) 397 : "=&r" (temp), "=m" (*m), "=&r" (res)
377 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 398 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
378 : "memory"); 399 : "memory");
@@ -435,14 +456,16 @@ static inline int test_and_change_bit(unsigned long nr,
435 unsigned long temp, res; 456 unsigned long temp, res;
436 457
437 __asm__ __volatile__( 458 __asm__ __volatile__(
438 "1: " __LL " %0, %1 # test_and_change_bit \n" 459 " .set mips3 \n"
460 "1: " __LL "%0, %1 # test_and_change_bit \n"
439 " xor %2, %0, %3 \n" 461 " xor %2, %0, %3 \n"
440 " "__SC "%2, %1 \n" 462 " " __SC "%2, %1 \n"
441 " beqzl %2, 1b \n" 463 " beqzl %2, 1b \n"
442 " and %2, %0, %3 \n" 464 " and %2, %0, %3 \n"
443#ifdef CONFIG_SMP 465#ifdef CONFIG_SMP
444 " sync \n" 466 " sync \n"
445#endif 467#endif
468 " .set mips0 \n"
446 : "=&r" (temp), "=m" (*m), "=&r" (res) 469 : "=&r" (temp), "=m" (*m), "=&r" (res)
447 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 470 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
448 : "memory"); 471 : "memory");
@@ -453,16 +476,18 @@ static inline int test_and_change_bit(unsigned long nr,
453 unsigned long temp, res; 476 unsigned long temp, res;
454 477
455 __asm__ __volatile__( 478 __asm__ __volatile__(
456 " .set noreorder # test_and_change_bit \n" 479 " .set push \n"
457 "1: " __LL " %0, %1 \n" 480 " .set noreorder \n"
481 " .set mips3 \n"
482 "1: " __LL "%0, %1 # test_and_change_bit \n"
458 " xor %2, %0, %3 \n" 483 " xor %2, %0, %3 \n"
459 " "__SC "\t%2, %1 \n" 484 " " __SC "\t%2, %1 \n"
460 " beqz %2, 1b \n" 485 " beqz %2, 1b \n"
461 " and %2, %0, %3 \n" 486 " and %2, %0, %3 \n"
462#ifdef CONFIG_SMP 487#ifdef CONFIG_SMP
463 " sync \n" 488 " sync \n"
464#endif 489#endif
465 " .set reorder \n" 490 " .set pop \n"
466 : "=&r" (temp), "=m" (*m), "=&r" (res) 491 : "=&r" (temp), "=m" (*m), "=&r" (res)
467 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 492 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
468 : "memory"); 493 : "memory");
@@ -523,22 +548,60 @@ static inline int test_bit(unsigned long nr, const volatile unsigned long *addr)
523} 548}
524 549
525/* 550/*
526 * ffz - find first zero in word. 551 * Return the bit position (0..63) of the most significant 1 bit in a word
552 * Returns -1 if no 1 bit exists
553 */
554static inline int __ilog2(unsigned long x)
555{
556 int lz;
557
558 if (sizeof(x) == 4) {
559 __asm__ (
560 " .set push \n"
561 " .set mips32 \n"
562 " clz %0, %1 \n"
563 " .set pop \n"
564 : "=r" (lz)
565 : "r" (x));
566
567 return 31 - lz;
568 }
569
570 BUG_ON(sizeof(x) != 8);
571
572 __asm__ (
573 " .set push \n"
574 " .set mips64 \n"
575 " dclz %0, %1 \n"
576 " .set pop \n"
577 : "=r" (lz)
578 : "r" (x));
579
580 return 63 - lz;
581}
582
583/*
584 * __ffs - find first bit in word.
527 * @word: The word to search 585 * @word: The word to search
528 * 586 *
529 * Undefined if no zero exists, so code should check against ~0UL first. 587 * Returns 0..SZLONG-1
588 * Undefined if no bit exists, so code should check against 0 first.
530 */ 589 */
531static inline unsigned long ffz(unsigned long word) 590static inline unsigned long __ffs(unsigned long word)
532{ 591{
592#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
593 return __ilog2(word & -word);
594#else
533 int b = 0, s; 595 int b = 0, s;
534 596
535 word = ~word;
536#ifdef CONFIG_32BIT 597#ifdef CONFIG_32BIT
537 s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s; 598 s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s;
538 s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s; 599 s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s;
539 s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s; 600 s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s;
540 s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s; 601 s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s;
541 s = 1; if (word << 31 != 0) s = 0; b += s; 602 s = 1; if (word << 31 != 0) s = 0; b += s;
603
604 return b;
542#endif 605#endif
543#ifdef CONFIG_64BIT 606#ifdef CONFIG_64BIT
544 s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s; 607 s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s;
@@ -547,27 +610,92 @@ static inline unsigned long ffz(unsigned long word)
547 s = 4; if (word << 60 != 0) s = 0; b += s; word >>= s; 610 s = 4; if (word << 60 != 0) s = 0; b += s; word >>= s;
548 s = 2; if (word << 62 != 0) s = 0; b += s; word >>= s; 611 s = 2; if (word << 62 != 0) s = 0; b += s; word >>= s;
549 s = 1; if (word << 63 != 0) s = 0; b += s; 612 s = 1; if (word << 63 != 0) s = 0; b += s;
550#endif
551 613
552 return b; 614 return b;
615#endif
616#endif
553} 617}
554 618
555/* 619/*
556 * __ffs - find first bit in word. 620 * ffs - find first bit set.
557 * @word: The word to search 621 * @word: The word to search
558 * 622 *
559 * Undefined if no bit exists, so code should check against 0 first. 623 * Returns 1..SZLONG
624 * Returns 0 if no bit exists
560 */ 625 */
561static inline unsigned long __ffs(unsigned long word) 626
627static inline unsigned long ffs(unsigned long word)
562{ 628{
563 return ffz(~word); 629 if (!word)
630 return 0;
631
632 return __ffs(word) + 1;
564} 633}
565 634
566/* 635/*
567 * fls: find last bit set. 636 * ffz - find first zero in word.
637 * @word: The word to search
638 *
639 * Undefined if no zero exists, so code should check against ~0UL first.
640 */
641static inline unsigned long ffz(unsigned long word)
642{
643 return __ffs (~word);
644}
645
646/*
647 * flz - find last zero in word.
648 * @word: The word to search
649 *
650 * Returns 0..SZLONG-1
651 * Undefined if no zero exists, so code should check against ~0UL first.
652 */
653static inline unsigned long flz(unsigned long word)
654{
655#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
656 return __ilog2(~word);
657#else
658#ifdef CONFIG_32BIT
659 int r = 31, s;
660 word = ~word;
661 s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s;
662 s = 8; if ((word & 0xff000000)) s = 0; r -= s; word <<= s;
663 s = 4; if ((word & 0xf0000000)) s = 0; r -= s; word <<= s;
664 s = 2; if ((word & 0xc0000000)) s = 0; r -= s; word <<= s;
665 s = 1; if ((word & 0x80000000)) s = 0; r -= s;
666
667 return r;
668#endif
669#ifdef CONFIG_64BIT
670 int r = 63, s;
671 word = ~word;
672 s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s;
673 s = 16; if ((word & 0xffff000000000000UL)) s = 0; r -= s; word <<= s;
674 s = 8; if ((word & 0xff00000000000000UL)) s = 0; r -= s; word <<= s;
675 s = 4; if ((word & 0xf000000000000000UL)) s = 0; r -= s; word <<= s;
676 s = 2; if ((word & 0xc000000000000000UL)) s = 0; r -= s; word <<= s;
677 s = 1; if ((word & 0x8000000000000000UL)) s = 0; r -= s;
678
679 return r;
680#endif
681#endif
682}
683
684/*
685 * fls - find last bit set.
686 * @word: The word to search
687 *
688 * Returns 1..SZLONG
689 * Returns 0 if no bit exists
568 */ 690 */
691static inline unsigned long fls(unsigned long word)
692{
693 if (word == 0)
694 return 0;
695
696 return flz(~word) + 1;
697}
569 698
570#define fls(x) generic_fls(x)
571 699
572/* 700/*
573 * find_next_zero_bit - find the first zero bit in a memory region 701 * find_next_zero_bit - find the first zero bit in a memory region
@@ -704,17 +832,6 @@ static inline int sched_find_first_bit(const unsigned long *b)
704} 832}
705 833
706/* 834/*
707 * ffs - find first bit set
708 * @x: the word to search
709 *
710 * This is defined the same way as
711 * the libc and compiler builtin ffs routines, therefore
712 * differs in spirit from the above ffz (man ffs).
713 */
714
715#define ffs(x) generic_ffs(x)
716
717/*
718 * hweightN - returns the hamming weight of a N-bit word 835 * hweightN - returns the hamming weight of a N-bit word
719 * @x: the word to weigh 836 * @x: the word to weigh
720 * 837 *
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index b1e57d783604..14fc88f27226 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -77,6 +77,7 @@
77#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ 77#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */
78#define MACH_SGI_IP28 2 /* Indigo2 Impact */ 78#define MACH_SGI_IP28 2 /* Indigo2 Impact */
79#define MACH_SGI_IP32 3 /* O2 */ 79#define MACH_SGI_IP32 3 /* O2 */
80#define MACH_SGI_IP30 4 /* Octane, Octane2 */
80 81
81/* 82/*
82 * Valid machtype for group COBALT 83 * Valid machtype for group COBALT
@@ -136,6 +137,7 @@
136#define MACH_GROUP_PHILIPS 14 137#define MACH_GROUP_PHILIPS 14
137#define MACH_PHILIPS_NINO 0 /* Nino */ 138#define MACH_PHILIPS_NINO 0 /* Nino */
138#define MACH_PHILIPS_VELO 1 /* Velo */ 139#define MACH_PHILIPS_VELO 1 /* Velo */
140#define MACH_PHILIPS_JBS 2 /* JBS */
139 141
140/* 142/*
141 * Valid machtype for group Globespan 143 * Valid machtype for group Globespan
@@ -159,6 +161,7 @@
159#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */ 161#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */
160#define MACH_TOSHIBA_RBTX4927 4 162#define MACH_TOSHIBA_RBTX4927 4
161#define MACH_TOSHIBA_RBTX4937 5 163#define MACH_TOSHIBA_RBTX4937 5
164#define MACH_TOSHIBA_RBTX4938 6
162 165
163#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \ 166#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \
164 "RBTX4927", "RBTX4937" } 167 "RBTX4927", "RBTX4937" }
@@ -177,6 +180,8 @@
177#define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */ 180#define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */
178#define MACH_PB1550 8 /* Au1550-based eval board */ 181#define MACH_PB1550 8 /* Au1550-based eval board */
179#define MACH_DB1550 9 /* Au1550-based eval board */ 182#define MACH_DB1550 9 /* Au1550-based eval board */
183#define MACH_PB1200 10 /* Au1200-based eval board */
184#define MACH_DB1200 11 /* Au1200-based eval board */
180 185
181/* 186/*
182 * Valid machtype for group NEC_VR41XX 187 * Valid machtype for group NEC_VR41XX
diff --git a/include/asm-mips/break.h b/include/asm-mips/break.h
index 2e6de788f207..25b980c91e7e 100644
--- a/include/asm-mips/break.h
+++ b/include/asm-mips/break.h
@@ -28,6 +28,7 @@
28#define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ 28#define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */
29#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ 29#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */
30#define BRK_BUG 512 /* Used by BUG() */ 30#define BRK_BUG 512 /* Used by BUG() */
31#define BRK_KDB 513 /* Used in KDB_ENTER() */
31#define BRK_MULOVF 1023 /* Multiply overflow */ 32#define BRK_MULOVF 1023 /* Multiply overflow */
32 33
33#endif /* __ASM_BREAK_H */ 34#endif /* __ASM_BREAK_H */
diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h
index 3f594b440abc..87d49a5bdc63 100644
--- a/include/asm-mips/bug.h
+++ b/include/asm-mips/bug.h
@@ -1,16 +1,21 @@
1#ifndef __ASM_BUG_H 1#ifndef __ASM_BUG_H
2#define __ASM_BUG_H 2#define __ASM_BUG_H
3 3
4#include <asm/break.h> 4#include <linux/config.h>
5 5
6#ifdef CONFIG_BUG 6#ifdef CONFIG_BUG
7#define HAVE_ARCH_BUG 7
8#include <asm/break.h>
9
8#define BUG() \ 10#define BUG() \
9do { \ 11do { \
10 __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \ 12 __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \
11} while (0) 13} while (0)
14
15#define HAVE_ARCH_BUG
16
12#endif 17#endif
13 18
14#include <asm-generic/bug.h> 19#include <asm-generic/bug.h>
15 20
16#endif 21#endif /* __ASM_BUG_H */
diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h
index b14b961c2100..cb2ea7c15c7a 100644
--- a/include/asm-mips/bugs.h
+++ b/include/asm-mips/bugs.h
@@ -8,12 +8,18 @@
8#define _ASM_BUGS_H 8#define _ASM_BUGS_H
9 9
10#include <linux/config.h> 10#include <linux/config.h>
11#include <linux/delay.h>
12#include <asm/cpu.h>
13#include <asm/cpu-info.h>
11 14
12extern void check_bugs32(void); 15extern void check_bugs32(void);
13extern void check_bugs64(void); 16extern void check_bugs64(void);
14 17
15static inline void check_bugs(void) 18static inline void check_bugs(void)
16{ 19{
20 unsigned int cpu = smp_processor_id();
21
22 cpu_data[cpu].udelay_val = loops_per_jiffy;
17 check_bugs32(); 23 check_bugs32();
18#ifdef CONFIG_64BIT 24#ifdef CONFIG_64BIT
19 check_bugs64(); 25 check_bugs64();
diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h
index 4517bdf20953..1a5d1a669db3 100644
--- a/include/asm-mips/cache.h
+++ b/include/asm-mips/cache.h
@@ -10,6 +10,7 @@
10#define _ASM_CACHE_H 10#define _ASM_CACHE_H
11 11
12#include <linux/config.h> 12#include <linux/config.h>
13#include <kmalloc.h>
13 14
14#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT 15#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
15#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 16#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
@@ -18,6 +19,4 @@
18#define SMP_CACHE_SHIFT L1_CACHE_SHIFT 19#define SMP_CACHE_SHIFT L1_CACHE_SHIFT
19#define SMP_CACHE_BYTES L1_CACHE_BYTES 20#define SMP_CACHE_BYTES L1_CACHE_BYTES
20 21
21#define ARCH_KMALLOC_MINALIGN 8
22
23#endif /* _ASM_CACHE_H */ 22#endif /* _ASM_CACHE_H */
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
index 635f1bfb403e..a18ba2edc0b6 100644
--- a/include/asm-mips/cacheflush.h
+++ b/include/asm-mips/cacheflush.h
@@ -49,17 +49,29 @@ static inline void flush_dcache_page(struct page *page)
49 49
50extern void (*flush_icache_page)(struct vm_area_struct *vma, 50extern void (*flush_icache_page)(struct vm_area_struct *vma,
51 struct page *page); 51 struct page *page);
52extern void (*flush_icache_range)(unsigned long start, unsigned long end); 52extern void (*flush_icache_range)(unsigned long __user start,
53 unsigned long __user end);
53#define flush_cache_vmap(start, end) flush_cache_all() 54#define flush_cache_vmap(start, end) flush_cache_all()
54#define flush_cache_vunmap(start, end) flush_cache_all() 55#define flush_cache_vunmap(start, end) flush_cache_all()
55 56
56#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 57static inline void copy_to_user_page(struct vm_area_struct *vma,
57do { \ 58 struct page *page, unsigned long vaddr, void *dst, const void *src,
58 memcpy(dst, (void *) src, len); \ 59 unsigned long len)
59 flush_icache_page(vma, page); \ 60{
60} while (0) 61 if (cpu_has_dc_aliases)
61#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 62 flush_cache_page(vma, vaddr, page_to_pfn(page));
62 memcpy(dst, src, len) 63 memcpy(dst, src, len);
64 flush_icache_page(vma, page);
65}
66
67static inline void copy_from_user_page(struct vm_area_struct *vma,
68 struct page *page, unsigned long vaddr, void *dst, const void *src,
69 unsigned long len)
70{
71 if (cpu_has_dc_aliases)
72 flush_cache_page(vma, vaddr, page_to_pfn(page));
73 memcpy(dst, src, len);
74}
63 75
64extern void (*flush_cache_sigtramp)(unsigned long addr); 76extern void (*flush_cache_sigtramp)(unsigned long addr);
65extern void (*flush_icache_all)(void); 77extern void (*flush_icache_all)(void);
@@ -78,4 +90,7 @@ extern void (*flush_data_cache_page)(unsigned long addr);
78#define ClearPageDcacheDirty(page) \ 90#define ClearPageDcacheDirty(page) \
79 clear_bit(PG_dcache_dirty, &(page)->flags) 91 clear_bit(PG_dcache_dirty, &(page)->flags)
80 92
93/* Run kernel code uncached, useful for cache probing functions. */
94unsigned long __init run_uncached(void *func);
95
81#endif /* _ASM_CACHEFLUSH_H */ 96#endif /* _ASM_CACHEFLUSH_H */
diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h
index c1ea5a8714f3..b09f8971e95d 100644
--- a/include/asm-mips/checksum.h
+++ b/include/asm-mips/checksum.h
@@ -34,8 +34,9 @@ unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum);
34 * this is a new version of the above that records errors it finds in *errp, 34 * this is a new version of the above that records errors it finds in *errp,
35 * but continues and zeros the rest of the buffer. 35 * but continues and zeros the rest of the buffer.
36 */ 36 */
37unsigned int csum_partial_copy_from_user(const unsigned char *src, unsigned char *dst, int len, 37unsigned int csum_partial_copy_from_user(const unsigned char __user *src,
38 unsigned int sum, int *errp); 38 unsigned char *dst, int len,
39 unsigned int sum, int *errp);
39 40
40/* 41/*
41 * Copy and checksum to user 42 * Copy and checksum to user
@@ -70,14 +71,15 @@ unsigned int csum_partial_copy_nocheck(const unsigned char *src, unsigned char *
70static inline unsigned short int csum_fold(unsigned int sum) 71static inline unsigned short int csum_fold(unsigned int sum)
71{ 72{
72 __asm__( 73 __asm__(
73 ".set\tnoat\t\t\t# csum_fold\n\t" 74 " .set push # csum_fold\n"
74 "sll\t$1,%0,16\n\t" 75 " .set noat \n"
75 "addu\t%0,$1\n\t" 76 " sll $1, %0, 16 \n"
76 "sltu\t$1,%0,$1\n\t" 77 " addu %0, $1 \n"
77 "srl\t%0,%0,16\n\t" 78 " sltu $1, %0, $1 \n"
78 "addu\t%0,$1\n\t" 79 " srl %0, %0, 16 \n"
79 "xori\t%0,0xffff\n\t" 80 " addu %0, $1 \n"
80 ".set\tat" 81 " xori %0, 0xffff \n"
82 " .set pop"
81 : "=r" (sum) 83 : "=r" (sum)
82 : "0" (sum)); 84 : "0" (sum));
83 85
@@ -127,29 +129,30 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr,
127 unsigned int sum) 129 unsigned int sum)
128{ 130{
129 __asm__( 131 __asm__(
130 ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t" 132 " .set push # csum_tcpudp_nofold\n"
133 " .set noat \n"
131#ifdef CONFIG_32BIT 134#ifdef CONFIG_32BIT
132 "addu\t%0, %2\n\t" 135 " addu %0, %2 \n"
133 "sltu\t$1, %0, %2\n\t" 136 " sltu $1, %0, %2 \n"
134 "addu\t%0, $1\n\t" 137 " addu %0, $1 \n"
135 138
136 "addu\t%0, %3\n\t" 139 " addu %0, %3 \n"
137 "sltu\t$1, %0, %3\n\t" 140 " sltu $1, %0, %3 \n"
138 "addu\t%0, $1\n\t" 141 " addu %0, $1 \n"
139 142
140 "addu\t%0, %4\n\t" 143 " addu %0, %4 \n"
141 "sltu\t$1, %0, %4\n\t" 144 " sltu $1, %0, %4 \n"
142 "addu\t%0, $1\n\t" 145 " addu %0, $1 \n"
143#endif 146#endif
144#ifdef CONFIG_64BIT 147#ifdef CONFIG_64BIT
145 "daddu\t%0, %2\n\t" 148 " daddu %0, %2 \n"
146 "daddu\t%0, %3\n\t" 149 " daddu %0, %3 \n"
147 "daddu\t%0, %4\n\t" 150 " daddu %0, %4 \n"
148 "dsll32\t$1, %0, 0\n\t" 151 " dsll32 $1, %0, 0 \n"
149 "daddu\t%0, $1\n\t" 152 " daddu %0, $1 \n"
150 "dsrl32\t%0, %0, 0\n\t" 153 " dsra32 %0, %0, 0 \n"
151#endif 154#endif
152 ".set\tat" 155 " .set pop"
153 : "=r" (sum) 156 : "=r" (sum)
154 : "0" (daddr), "r"(saddr), 157 : "0" (daddr), "r"(saddr),
155#ifdef __MIPSEL__ 158#ifdef __MIPSEL__
@@ -192,57 +195,57 @@ static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
192 unsigned int sum) 195 unsigned int sum)
193{ 196{
194 __asm__( 197 __asm__(
195 ".set\tpush\t\t\t# csum_ipv6_magic\n\t" 198 " .set push # csum_ipv6_magic\n"
196 ".set\tnoreorder\n\t" 199 " .set noreorder \n"
197 ".set\tnoat\n\t" 200 " .set noat \n"
198 "addu\t%0, %5\t\t\t# proto (long in network byte order)\n\t" 201 " addu %0, %5 # proto (long in network byte order)\n"
199 "sltu\t$1, %0, %5\n\t" 202 " sltu $1, %0, %5 \n"
200 "addu\t%0, $1\n\t" 203 " addu %0, $1 \n"
201 204
202 "addu\t%0, %6\t\t\t# csum\n\t" 205 " addu %0, %6 # csum\n"
203 "sltu\t$1, %0, %6\n\t" 206 " sltu $1, %0, %6 \n"
204 "lw\t%1, 0(%2)\t\t\t# four words source address\n\t" 207 " lw %1, 0(%2) # four words source address\n"
205 "addu\t%0, $1\n\t" 208 " addu %0, $1 \n"
206 "addu\t%0, %1\n\t" 209 " addu %0, %1 \n"
207 "sltu\t$1, %0, %1\n\t" 210 " sltu $1, %0, %1 \n"
208 211
209 "lw\t%1, 4(%2)\n\t" 212 " lw %1, 4(%2) \n"
210 "addu\t%0, $1\n\t" 213 " addu %0, $1 \n"
211 "addu\t%0, %1\n\t" 214 " addu %0, %1 \n"
212 "sltu\t$1, %0, %1\n\t" 215 " sltu $1, %0, %1 \n"
213 216
214 "lw\t%1, 8(%2)\n\t" 217 " lw %1, 8(%2) \n"
215 "addu\t%0, $1\n\t" 218 " addu %0, $1 \n"
216 "addu\t%0, %1\n\t" 219 " addu %0, %1 \n"
217 "sltu\t$1, %0, %1\n\t" 220 " sltu $1, %0, %1 \n"
218 221
219 "lw\t%1, 12(%2)\n\t" 222 " lw %1, 12(%2) \n"
220 "addu\t%0, $1\n\t" 223 " addu %0, $1 \n"
221 "addu\t%0, %1\n\t" 224 " addu %0, %1 \n"
222 "sltu\t$1, %0, %1\n\t" 225 " sltu $1, %0, %1 \n"
223 226
224 "lw\t%1, 0(%3)\n\t" 227 " lw %1, 0(%3) \n"
225 "addu\t%0, $1\n\t" 228 " addu %0, $1 \n"
226 "addu\t%0, %1\n\t" 229 " addu %0, %1 \n"
227 "sltu\t$1, %0, %1\n\t" 230 " sltu $1, %0, %1 \n"
228 231
229 "lw\t%1, 4(%3)\n\t" 232 " lw %1, 4(%3) \n"
230 "addu\t%0, $1\n\t" 233 " addu %0, $1 \n"
231 "addu\t%0, %1\n\t" 234 " addu %0, %1 \n"
232 "sltu\t$1, %0, %1\n\t" 235 " sltu $1, %0, %1 \n"
233 236
234 "lw\t%1, 8(%3)\n\t" 237 " lw %1, 8(%3) \n"
235 "addu\t%0, $1\n\t" 238 " addu %0, $1 \n"
236 "addu\t%0, %1\n\t" 239 " addu %0, %1 \n"
237 "sltu\t$1, %0, %1\n\t" 240 " sltu $1, %0, %1 \n"
238 241
239 "lw\t%1, 12(%3)\n\t" 242 " lw %1, 12(%3) \n"
240 "addu\t%0, $1\n\t" 243 " addu %0, $1 \n"
241 "addu\t%0, %1\n\t" 244 " addu %0, %1 \n"
242 "sltu\t$1, %0, %1\n\t" 245 " sltu $1, %0, %1 \n"
243 246
244 "addu\t%0, $1\t\t\t# Add final carry\n\t" 247 " addu %0, $1 # Add final carry\n"
245 ".set\tpop" 248 " .set pop"
246 : "=r" (sum), "=r" (proto) 249 : "=r" (sum), "=r" (proto)
247 : "r" (saddr), "r" (daddr), 250 : "r" (saddr), "r" (daddr),
248 "0" (htonl(len)), "1" (htonl(proto)), "r" (sum)); 251 "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
diff --git a/include/asm-mips/cobalt/cobalt.h b/include/asm-mips/cobalt/cobalt.h
index ca1fbc0579fe..78e1df2095fb 100644
--- a/include/asm-mips/cobalt/cobalt.h
+++ b/include/asm-mips/cobalt/cobalt.h
@@ -19,18 +19,23 @@
19 * 9 - PCI 19 * 9 - PCI
20 * 14 - IDE0 20 * 14 - IDE0
21 * 15 - IDE1 21 * 15 - IDE1
22 * 22 */
23#define COBALT_QUBE_SLOT_IRQ 9
24
25/*
23 * CPU IRQs are 16 ... 23 26 * CPU IRQs are 16 ... 23
24 */ 27 */
25#define COBALT_TIMER_IRQ 18 28#define COBALT_CPU_IRQ 16
26#define COBALT_SCC_IRQ 19 /* pre-production has 85C30 */ 29
27#define COBALT_RAQ_SCSI_IRQ 19 30#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
28#define COBALT_ETH0_IRQ 19 31#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */
29#define COBALT_ETH1_IRQ 20 32#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
30#define COBALT_SERIAL_IRQ 21 33#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
31#define COBALT_SCSI_IRQ 21 34#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
32#define COBALT_VIA_IRQ 22 /* Chained to VIA ISA bridge */ 35#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4)
33#define COBALT_QUBE_SLOT_IRQ 23 36#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5)
37#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5)
38#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */
34 39
35/* 40/*
36 * PCI configuration space manifest constants. These are wired into 41 * PCI configuration space manifest constants. These are wired into
@@ -69,16 +74,21 @@
69 * Most of this really should go into a separate GT64111 header file. 74 * Most of this really should go into a separate GT64111 header file.
70 */ 75 */
71#define GT64111_IO_BASE 0x10000000UL 76#define GT64111_IO_BASE 0x10000000UL
77#define GT64111_IO_END 0x11ffffffUL
78#define GT64111_MEM_BASE 0x12000000UL
79#define GT64111_MEM_END 0x13ffffffUL
72#define GT64111_BASE 0x14000000UL 80#define GT64111_BASE 0x14000000UL
73#define GALILEO_REG(ofs) (KSEG0 + GT64111_BASE + (unsigned long)(ofs)) 81#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
74 82
75#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port)) 83#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port))
76#define GALILEO_OUTL(val, port) \ 84#define GALILEO_OUTL(val, port) \
77do { \ 85do { \
78 *(volatile unsigned int *) GALILEO_REG(port) = (port); \ 86 *(volatile unsigned int *) GALILEO_REG(port) = (val); \
79} while (0) 87} while (0)
80 88
81#define GALILEO_T0EXP 0x0100 89#define GALILEO_INTR_T0EXP (1 << 8)
90#define GALILEO_INTR_RETRY_CTR (1 << 20)
91
82#define GALILEO_ENTC0 0x01 92#define GALILEO_ENTC0 0x01
83#define GALILEO_SELTC0 0x02 93#define GALILEO_SELTC0 0x02
84 94
@@ -86,5 +96,21 @@ do { \
86 GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \ 96 GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \
87 (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS) 97 (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
88 98
99#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
100# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */
101# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */
102# define COBALT_LED_WEB (1 << 2) /* RaQ */
103# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */
104# define COBALT_LED_RESET 0x0f
105
106#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
107# define COBALT_KEY_CLEAR (1 << 1)
108# define COBALT_KEY_LEFT (1 << 2)
109# define COBALT_KEY_UP (1 << 3)
110# define COBALT_KEY_DOWN (1 << 4)
111# define COBALT_KEY_RIGHT (1 << 5)
112# define COBALT_KEY_ENTER (1 << 6)
113# define COBALT_KEY_SELECT (1 << 7)
114# define COBALT_KEY_MASK 0xfe
89 115
90#endif /* __ASM_COBALT_H */ 116#endif /* __ASM_COBALT_H */
diff --git a/include/asm-mips/cobalt/mach-gt64120.h b/include/asm-mips/cobalt/mach-gt64120.h
new file mode 100644
index 000000000000..587fc4378f44
--- /dev/null
+++ b/include/asm-mips/cobalt/mach-gt64120.h
@@ -0,0 +1 @@
/* there's something here ... in the dark */
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h
index 2c084cd4bc0a..35d2604fe69c 100644
--- a/include/asm-mips/compat.h
+++ b/include/asm-mips/compat.h
@@ -15,10 +15,10 @@ typedef s32 compat_clock_t;
15typedef s32 compat_suseconds_t; 15typedef s32 compat_suseconds_t;
16 16
17typedef s32 compat_pid_t; 17typedef s32 compat_pid_t;
18typedef u32 __compat_uid_t; 18typedef s32 __compat_uid_t;
19typedef u32 __compat_gid_t; 19typedef s32 __compat_gid_t;
20typedef u32 __compat_uid32_t; 20typedef __compat_uid_t __compat_uid32_t;
21typedef u32 __compat_gid32_t; 21typedef __compat_gid_t __compat_gid32_t;
22typedef u32 compat_mode_t; 22typedef u32 compat_mode_t;
23typedef u32 compat_ino_t; 23typedef u32 compat_ino_t;
24typedef u32 compat_dev_t; 24typedef u32 compat_dev_t;
@@ -54,8 +54,8 @@ struct compat_stat {
54 compat_ino_t st_ino; 54 compat_ino_t st_ino;
55 compat_mode_t st_mode; 55 compat_mode_t st_mode;
56 compat_nlink_t st_nlink; 56 compat_nlink_t st_nlink;
57 __compat_uid32_t st_uid; 57 __compat_uid_t st_uid;
58 __compat_gid32_t st_gid; 58 __compat_gid_t st_gid;
59 compat_dev_t st_rdev; 59 compat_dev_t st_rdev;
60 s32 st_pad2[2]; 60 s32 st_pad2[2];
61 compat_off_t st_size; 61 compat_off_t st_size;
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 9a2de642eee6..03627cfb3e45 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -4,6 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle 6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
7 */ 8 */
8#ifndef __ASM_CPU_FEATURES_H 9#ifndef __ASM_CPU_FEATURES_H
9#define __ASM_CPU_FEATURES_H 10#define __ASM_CPU_FEATURES_H
@@ -24,8 +25,19 @@
24#ifndef cpu_has_4kex 25#ifndef cpu_has_4kex
25#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 26#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
26#endif 27#endif
27#ifndef cpu_has_4ktlb 28#ifndef cpu_has_3k_cache
28#define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB) 29#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
30#endif
31#define cpu_has_6k_cache 0
32#define cpu_has_8k_cache 0
33#ifndef cpu_has_4k_cache
34#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
35#endif
36#ifndef cpu_has_tx39_cache
37#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
38#endif
39#ifndef cpu_has_sb1_cache
40#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
29#endif 41#endif
30#ifndef cpu_has_fpu 42#ifndef cpu_has_fpu
31#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU) 43#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
@@ -39,9 +51,6 @@
39#ifndef cpu_has_watch 51#ifndef cpu_has_watch
40#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) 52#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
41#endif 53#endif
42#ifndef cpu_has_mips16
43#define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16)
44#endif
45#ifndef cpu_has_divec 54#ifndef cpu_has_divec
46#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) 55#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
47#endif 56#endif
@@ -66,6 +75,18 @@
66#ifndef cpu_has_llsc 75#ifndef cpu_has_llsc
67#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) 76#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
68#endif 77#endif
78#ifndef cpu_has_mips16
79#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
80#endif
81#ifndef cpu_has_mdmx
82#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
83#endif
84#ifndef cpu_has_mips3d
85#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
86#endif
87#ifndef cpu_has_smartmips
88#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
89#endif
69#ifndef cpu_has_vtag_icache 90#ifndef cpu_has_vtag_icache
70#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 91#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
71#endif 92#endif
@@ -95,15 +116,16 @@
95#endif 116#endif
96#endif 117#endif
97 118
98/* 119#ifndef cpu_has_dsp
99 * Certain CPUs may throw bizarre exceptions if not the whole cacheline 120#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
100 * contains valid instructions. For these we ensure proper alignment of 121#endif
101 * signal trampolines and pad them to the size of a full cache lines with 122
102 * nops. This is also used in structure definitions so can't be a test macro 123#ifdef CONFIG_MIPS_MT
103 * like the others. 124#ifndef cpu_has_mipsmt
104 */ 125# define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
105#ifndef PLAT_TRAMPOLINE_STUFF_LINE 126#endif
106#define PLAT_TRAMPOLINE_STUFF_LINE 0UL 127#else
128# define cpu_has_mipsmt 0
107#endif 129#endif
108 130
109#ifdef CONFIG_32BIT 131#ifdef CONFIG_32BIT
@@ -142,6 +164,22 @@
142# endif 164# endif
143#endif 165#endif
144 166
167#ifdef CONFIG_CPU_MIPSR2
168# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
169# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
170# else
171# define cpu_has_vint 0
172# endif
173# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
174# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
175# else
176# define cpu_has_veic 0
177# endif
178#else
179# define cpu_has_vint 0
180# define cpu_has_veic 0
181#endif
182
145#ifndef cpu_has_subset_pcaches 183#ifndef cpu_has_subset_pcaches
146#define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) 184#define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
147#endif 185#endif
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 20a35b15a31d..d5cf519f8fcc 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -7,6 +7,7 @@
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle 7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine 8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 * Copyright (C) 2004 Maciej W. Rozycki
10 */ 11 */
11#ifndef __ASM_CPU_INFO_H 12#ifndef __ASM_CPU_INFO_H
12#define __ASM_CPU_INFO_H 13#define __ASM_CPU_INFO_H
@@ -61,6 +62,7 @@ struct cpuinfo_mips {
61 * Capability and feature descriptor structure for MIPS CPU 62 * Capability and feature descriptor structure for MIPS CPU
62 */ 63 */
63 unsigned long options; 64 unsigned long options;
65 unsigned long ases;
64 unsigned int processor_id; 66 unsigned int processor_id;
65 unsigned int fpu_id; 67 unsigned int fpu_id;
66 unsigned int cputype; 68 unsigned int cputype;
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index dec060b49556..48eac296060f 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -3,6 +3,7 @@
3 * various MIPS cpu types. 3 * various MIPS cpu types.
4 * 4 *
5 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 5 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
6 * Copyright (C) 2004 Maciej W. Rozycki
6 */ 7 */
7#ifndef _ASM_CPU_H 8#ifndef _ASM_CPU_H
8#define _ASM_CPU_H 9#define _ASM_CPU_H
@@ -22,12 +23,17 @@
22 spec. 23 spec.
23*/ 24*/
24 25
25#define PRID_COMP_LEGACY 0x000000 26#define PRID_COMP_LEGACY 0x000000
26#define PRID_COMP_MIPS 0x010000 27#define PRID_COMP_MIPS 0x010000
27#define PRID_COMP_BROADCOM 0x020000 28#define PRID_COMP_BROADCOM 0x020000
28#define PRID_COMP_ALCHEMY 0x030000 29#define PRID_COMP_ALCHEMY 0x030000
29#define PRID_COMP_SIBYTE 0x040000 30#define PRID_COMP_SIBYTE 0x040000
30#define PRID_COMP_SANDCRAFT 0x050000 31#define PRID_COMP_SANDCRAFT 0x050000
32#define PRID_COMP_PHILIPS 0x060000
33#define PRID_COMP_TOSHIBA 0x070000
34#define PRID_COMP_LSI 0x080000
35#define PRID_COMP_LEXRA 0x0b0000
36
31 37
32/* 38/*
33 * Assigned values for the product ID register. In order to detect a 39 * Assigned values for the product ID register. In order to detect a
@@ -46,6 +52,7 @@
46#define PRID_IMP_VR41XX 0x0c00 52#define PRID_IMP_VR41XX 0x0c00
47#define PRID_IMP_R12000 0x0e00 53#define PRID_IMP_R12000 0x0e00
48#define PRID_IMP_R8000 0x1000 54#define PRID_IMP_R8000 0x1000
55#define PRID_IMP_PR4450 0x1200
49#define PRID_IMP_R4600 0x2000 56#define PRID_IMP_R4600 0x2000
50#define PRID_IMP_R4700 0x2100 57#define PRID_IMP_R4700 0x2100
51#define PRID_IMP_TX39 0x2200 58#define PRID_IMP_TX39 0x2200
@@ -60,6 +67,13 @@
60#define PRID_IMP_RM9000 0x3400 67#define PRID_IMP_RM9000 0x3400
61#define PRID_IMP_R5432 0x5400 68#define PRID_IMP_R5432 0x5400
62#define PRID_IMP_R5500 0x5500 69#define PRID_IMP_R5500 0x5500
70
71#define PRID_IMP_UNKNOWN 0xff00
72
73/*
74 * These are the PRID's for when 23:16 == PRID_COMP_MIPS
75 */
76
63#define PRID_IMP_4KC 0x8000 77#define PRID_IMP_4KC 0x8000
64#define PRID_IMP_5KC 0x8100 78#define PRID_IMP_5KC 0x8100
65#define PRID_IMP_20KC 0x8200 79#define PRID_IMP_20KC 0x8200
@@ -71,14 +85,15 @@
71#define PRID_IMP_4KEMPR2 0x9100 85#define PRID_IMP_4KEMPR2 0x9100
72#define PRID_IMP_4KSD 0x9200 86#define PRID_IMP_4KSD 0x9200
73#define PRID_IMP_24K 0x9300 87#define PRID_IMP_24K 0x9300
74 88#define PRID_IMP_34K 0x9500
75#define PRID_IMP_UNKNOWN 0xff00 89#define PRID_IMP_24KE 0x9600
76 90
77/* 91/*
78 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 92 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
79 */ 93 */
80 94
81#define PRID_IMP_SB1 0x0100 95#define PRID_IMP_SB1 0x0100
96#define PRID_IMP_SB1A 0x1100
82 97
83/* 98/*
84 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT 99 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
@@ -177,7 +192,11 @@
177#define CPU_VR4133 56 192#define CPU_VR4133 56
178#define CPU_AU1550 57 193#define CPU_AU1550 57
179#define CPU_24K 58 194#define CPU_24K 58
180#define CPU_LAST 58 195#define CPU_AU1200 59
196#define CPU_34K 60
197#define CPU_PR4450 61
198#define CPU_SB1A 62
199#define CPU_LAST 62
181 200
182/* 201/*
183 * ISA Level encodings 202 * ISA Level encodings
@@ -200,23 +219,37 @@
200 * CPU Option encodings 219 * CPU Option encodings
201 */ 220 */
202#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ 221#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
203/* Leave a spare bit for variant MMU types... */ 222#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
204#define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */ 223#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
205#define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */ 224#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
206#define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */ 225#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
207#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */ 226#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */
208#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */ 227#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */
209#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */ 228#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */
210#define MIPS_CPU_MIPS16 0x00000100 /* code compression */ 229#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */
211#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ 230#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */
212#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ 231#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */
213#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ 232#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */
214#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ 233#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */
215#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ 234#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */
216#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ 235#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */
217#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ 236#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */
218#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ 237#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */
219#define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */ 238#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */
220#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ 239#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */
240#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */
241#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */
242#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
243
244/*
245 * CPU ASE encodings
246 */
247#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
248#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
249#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
250#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
251#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
252#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
253
221 254
222#endif /* _ASM_CPU_H */ 255#endif /* _ASM_CPU_H */
diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h
index 724908b0bf13..19495a490e72 100644
--- a/include/asm-mips/dec/ecc.h
+++ b/include/asm-mips/dec/ecc.h
@@ -49,7 +49,8 @@ struct pt_regs;
49 49
50extern void dec_ecc_be_init(void); 50extern void dec_ecc_be_init(void);
51extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup); 51extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
52extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs); 52extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id,
53 struct pt_regs *regs);
53#endif 54#endif
54 55
55#endif /* __ASM_MIPS_DEC_ECC_H */ 56#endif /* __ASM_MIPS_DEC_ECC_H */
diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h
index 5e18a7510592..4cbc1f8a1129 100644
--- a/include/asm-mips/dec/ioasic_addrs.h
+++ b/include/asm-mips/dec/ioasic_addrs.h
@@ -45,7 +45,8 @@
45 45
46 46
47/* 47/*
48 * Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)). 48 * Offsets for I/O ASIC registers
49 * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
49 */ 50 */
50 /* all systems */ 51 /* all systems */
51#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */ 52#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */
diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h
index 946943502f83..eb522aa1e226 100644
--- a/include/asm-mips/dec/kn01.h
+++ b/include/asm-mips/dec/kn01.h
@@ -8,14 +8,12 @@
8 * 8 *
9 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions 9 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
10 * are by courtesy of Chris Fraser. 10 * are by courtesy of Chris Fraser.
11 * Copyright (C) 2002, 2003 Maciej W. Rozycki 11 * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
12 */ 12 */
13#ifndef __ASM_MIPS_DEC_KN01_H 13#ifndef __ASM_MIPS_DEC_KN01_H
14#define __ASM_MIPS_DEC_KN01_H 14#define __ASM_MIPS_DEC_KN01_H
15 15
16#include <asm/addrspace.h> 16#define KN01_SLOT_BASE 0x10000000
17
18#define KN01_SLOT_BASE KSEG1ADDR(0x10000000)
19#define KN01_SLOT_SIZE 0x01000000 17#define KN01_SLOT_SIZE 0x01000000
20 18
21/* 19/*
@@ -41,17 +39,9 @@
41 39
42 40
43/* 41/*
44 * Some port addresses...
45 */
46#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */
47#define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */
48#define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */
49
50
51/*
52 * Frame buffer memory address. 42 * Frame buffer memory address.
53 */ 43 */
54#define KN01_VFB_MEM KSEG1ADDR(0x0fc00000) 44#define KN01_VFB_MEM 0x0fc00000
55 45
56/* 46/*
57 * CPU interrupt bits. 47 * CPU interrupt bits.
@@ -80,4 +70,22 @@
80#define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */ 70#define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */
81#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ 71#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
82 72
73
74#ifndef __ASSEMBLY__
75
76#include <linux/interrupt.h>
77#include <linux/spinlock.h>
78#include <linux/types.h>
79
80struct pt_regs;
81
82extern u16 cached_kn01_csr;
83extern spinlock_t kn01_lock;
84
85extern void dec_kn01_be_init(void);
86extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
87extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
88 struct pt_regs *regs);
89#endif
90
83#endif /* __ASM_MIPS_DEC_KN01_H */ 91#endif /* __ASM_MIPS_DEC_KN01_H */
diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h
index f797f7045920..8319ad77b250 100644
--- a/include/asm-mips/dec/kn02.h
+++ b/include/asm-mips/dec/kn02.h
@@ -8,21 +8,12 @@
8 * 8 *
9 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions 9 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
10 * are by courtesy of Chris Fraser. 10 * are by courtesy of Chris Fraser.
11 * Copyright (C) 2002, 2003 Maciej W. Rozycki 11 * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
12 */ 12 */
13#ifndef __ASM_MIPS_DEC_KN02_H 13#ifndef __ASM_MIPS_DEC_KN02_H
14#define __ASM_MIPS_DEC_KN02_H 14#define __ASM_MIPS_DEC_KN02_H
15 15
16#ifndef __ASSEMBLY__ 16#define KN02_SLOT_BASE 0x1fc00000
17#include <linux/spinlock.h>
18#include <linux/types.h>
19#endif
20
21#include <asm/addrspace.h>
22#include <asm/dec/ecc.h>
23
24
25#define KN02_SLOT_BASE KSEG1ADDR(0x1fc00000)
26#define KN02_SLOT_SIZE 0x00080000 17#define KN02_SLOT_SIZE 0x00080000
27 18
28/* 19/*
@@ -39,22 +30,14 @@
39 30
40 31
41/* 32/*
42 * Some port addresses...
43 */
44#define KN02_DZ11_BASE (KN02_SLOT_BASE + KN02_DZ11) /* DZ11 */
45#define KN02_RTC_BASE (KN02_SLOT_BASE + KN02_RTC) /* RTC */
46#define KN02_CSR_BASE (KN02_SLOT_BASE + KN02_CSR) /* CSR */
47
48
49/*
50 * System Control & Status Register bits. 33 * System Control & Status Register bits.
51 */ 34 */
52#define KN02_CSR_RES_28 (0xf<<28) /* unused */ 35#define KN02_CSR_RES_28 (0xf<<28) /* unused */
53#define KN02_CSR_PSU (1<<27) /* power supply unit warning */ 36#define KN02_CSR_PSU (1<<27) /* power supply unit warning */
54#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */ 37#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */
55#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */ 38#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */
56#define KN03_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */ 39#define KN02_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */
57#define KN03_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */ 40#define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
58#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */ 41#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
59#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */ 42#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
60#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */ 43#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */
@@ -63,8 +46,8 @@
63#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */ 46#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */
64#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */ 47#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */
65#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */ 48#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */
66#define KN03_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */ 49#define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
67#define KN03_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ 50#define KN02_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
68 51
69 52
70/* 53/*
@@ -98,6 +81,10 @@
98 81
99 82
100#ifndef __ASSEMBLY__ 83#ifndef __ASSEMBLY__
84
85#include <linux/spinlock.h>
86#include <linux/types.h>
87
101extern u32 cached_kn02_csr; 88extern u32 cached_kn02_csr;
102extern spinlock_t kn02_lock; 89extern spinlock_t kn02_lock;
103extern void init_kn02_irqs(int base); 90extern void init_kn02_irqs(int base);
diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h
index 648c4dcbba1d..a25f3d7da7f7 100644
--- a/include/asm-mips/dec/kn02xa.h
+++ b/include/asm-mips/dec/kn02xa.h
@@ -9,7 +9,7 @@
9 * 9 *
10 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions 10 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
11 * are by courtesy of Chris Fraser. 11 * are by courtesy of Chris Fraser.
12 * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki 12 * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
13 * 13 *
14 * These are addresses which have to be known early in the boot process. 14 * These are addresses which have to be known early in the boot process.
15 * For other addresses refer to tc.h, ioasic_addrs.h and friends. 15 * For other addresses refer to tc.h, ioasic_addrs.h and friends.
@@ -17,31 +17,23 @@
17#ifndef __ASM_MIPS_DEC_KN02XA_H 17#ifndef __ASM_MIPS_DEC_KN02XA_H
18#define __ASM_MIPS_DEC_KN02XA_H 18#define __ASM_MIPS_DEC_KN02XA_H
19 19
20#include <asm/addrspace.h>
21#include <asm/dec/ioasic_addrs.h> 20#include <asm/dec/ioasic_addrs.h>
22 21
23#define KN02XA_SLOT_BASE KSEG1ADDR(0x1c000000) 22#define KN02XA_SLOT_BASE 0x1c000000
24
25/*
26 * Some port addresses...
27 */
28#define KN02XA_IOASIC_BASE (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
29#define KN02XA_RTC_BASE (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */
30
31 23
32/* 24/*
33 * Memory control ASIC registers. 25 * Memory control ASIC registers.
34 */ 26 */
35#define KN02XA_MER KSEG1ADDR(0x0c400000) /* memory error register */ 27#define KN02XA_MER 0x0c400000 /* memory error register */
36#define KN02XA_MSR KSEG1ADDR(0x0c800000) /* memory size register */ 28#define KN02XA_MSR 0x0c800000 /* memory size register */
37 29
38/* 30/*
39 * CPU control ASIC registers. 31 * CPU control ASIC registers.
40 */ 32 */
41#define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000) /* write timeout config */ 33#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
42#define KN02XA_EAR KSEG1ADDR(0x0e000004) /* error address register */ 34#define KN02XA_EAR 0x0e000004 /* error address register */
43#define KN02XA_BOOT0 KSEG1ADDR(0x0e000008) /* boot 0 register */ 35#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
44#define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */ 36#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
45 37
46/* 38/*
47 * Memory Error Register bits, common definitions. 39 * Memory Error Register bits, common definitions.
@@ -52,8 +44,13 @@
52#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */ 44#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */
53#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */ 45#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */
54#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */ 46#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */
55#define KN02XA_MER_RES_12 (0x3<<12) /* unused */ 47#define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */
56#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask */ 48#define KN02XA_MER_RES_12 (1<<12) /* unused */
49#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */
50#define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */
51#define KN02XA_MER_BYTERR_2 (0x4<<8) /* byte lane #2 */
52#define KN02XA_MER_BYTERR_1 (0x2<<8) /* byte lane #1 */
53#define KN02XA_MER_BYTERR_0 (0x1<<8) /* byte lane #0 */
57#define KN02XA_MER_RES_0 (0xff<<0) /* unused */ 54#define KN02XA_MER_RES_0 (0xff<<0) /* unused */
58 55
59/* 56/*
@@ -72,4 +69,17 @@
72#define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */ 69#define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */
73#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */ 70#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */
74 71
72
73#ifndef __ASSEMBLY__
74
75#include <linux/interrupt.h>
76
77struct pt_regs;
78
79extern void dec_kn02xa_be_init(void);
80extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
81extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
82 struct pt_regs *regs);
83#endif
84
75#endif /* __ASM_MIPS_DEC_KN02XA_H */ 85#endif /* __ASM_MIPS_DEC_KN02XA_H */
diff --git a/include/asm-mips/dec/kn03.h b/include/asm-mips/dec/kn03.h
index 676abd17c6a4..edede923ffb8 100644
--- a/include/asm-mips/dec/kn03.h
+++ b/include/asm-mips/dec/kn03.h
@@ -10,24 +10,15 @@
10 * 10 *
11 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions 11 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
12 * are by courtesy of Chris Fraser. 12 * are by courtesy of Chris Fraser.
13 * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki 13 * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
14 */ 14 */
15#ifndef __ASM_MIPS_DEC_KN03_H 15#ifndef __ASM_MIPS_DEC_KN03_H
16#define __ASM_MIPS_DEC_KN03_H 16#define __ASM_MIPS_DEC_KN03_H
17 17
18#include <asm/addrspace.h>
19#include <asm/dec/ecc.h> 18#include <asm/dec/ecc.h>
20#include <asm/dec/ioasic_addrs.h> 19#include <asm/dec/ioasic_addrs.h>
21 20
22#define KN03_SLOT_BASE KSEG1ADDR(0x1f800000) 21#define KN03_SLOT_BASE 0x1f800000
23
24/*
25 * Some port addresses...
26 */
27#define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
28#define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */
29#define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */
30
31 22
32/* 23/*
33 * CPU interrupt bits. 24 * CPU interrupt bits.
diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h
index b120362b8f13..15fe8f881e60 100644
--- a/include/asm-mips/dec/kn05.h
+++ b/include/asm-mips/dec/kn05.h
@@ -1,10 +1,12 @@
1/* 1/*
2 * include/asm-mips/dec/kn05.h 2 * include/asm-mips/dec/kn05.h
3 * 3 *
4 * DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260 4 * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
5 * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
6 * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
5 * definitions. 7 * definitions.
6 * 8 *
7 * Copyright (C) 2002, 2003 Maciej W. Rozycki 9 * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
8 * 10 *
9 * This program is free software; you can redistribute it and/or 11 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License 12 * modify it under the terms of the GNU General Public License
@@ -13,8 +15,8 @@
13 * 15 *
14 * WARNING! All this information is pure guesswork based on the 16 * WARNING! All this information is pure guesswork based on the
15 * ROM. It is provided here in hope it will give someone some 17 * ROM. It is provided here in hope it will give someone some
16 * food for thought. No documentation for the KN05 module has 18 * food for thought. No documentation for the KN05 nor the KN04
17 * been located so far. 19 * module has been located so far.
18 */ 20 */
19#ifndef __ASM_MIPS_DEC_KN05_H 21#ifndef __ASM_MIPS_DEC_KN05_H
20#define __ASM_MIPS_DEC_KN05_H 22#define __ASM_MIPS_DEC_KN05_H
@@ -24,48 +26,50 @@
24/* 26/*
25 * The oncard MB (Memory Buffer) ASIC provides an additional address 27 * The oncard MB (Memory Buffer) ASIC provides an additional address
26 * decoder. Certain address ranges within the "high" 16 slots are 28 * decoder. Certain address ranges within the "high" 16 slots are
27 * passed to the I/O ASIC's decoder like with the KN03. Others are 29 * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
28 * handled locally. "Low" slots are always passed. 30 * Others are handled locally. "Low" slots are always passed.
29 */ 31 */
30#define KN05_MB_ROM (16*IOASIC_SLOT_SIZE) /* KN05 card ROM */ 32#define KN4K_SLOT_BASE 0x1fc00000
31#define KN05_IOCTL (17*IOASIC_SLOT_SIZE) /* I/O ASIC */ 33
32#define KN05_ESAR (18*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ 34#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
33#define KN05_LANCE (19*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ 35#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
34#define KN05_MB_INT (20*IOASIC_SLOT_SIZE) /* MB interrupt register */ 36#define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
35#define KN05_MB_EA (21*IOASIC_SLOT_SIZE) /* MB error address? */ 37#define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
36#define KN05_MB_EC (22*IOASIC_SLOT_SIZE) /* MB error ??? */ 38#define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */
37#define KN05_MB_CSR (23*IOASIC_SLOT_SIZE) /* MB control & status */ 39#define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */
38#define KN05_RES_24 (24*IOASIC_SLOT_SIZE) /* unused? */ 40#define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */
39#define KN05_RES_25 (25*IOASIC_SLOT_SIZE) /* unused? */ 41#define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */
40#define KN05_RES_26 (26*IOASIC_SLOT_SIZE) /* unused? */ 42#define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */
41#define KN05_RES_27 (27*IOASIC_SLOT_SIZE) /* unused? */ 43#define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */
42#define KN05_SCSI (28*IOASIC_SLOT_SIZE) /* ASC SCSI */ 44#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */
43#define KN05_RES_29 (29*IOASIC_SLOT_SIZE) /* unused? */ 45#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */
44#define KN05_RES_30 (30*IOASIC_SLOT_SIZE) /* unused? */ 46#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
45#define KN05_RES_31 (31*IOASIC_SLOT_SIZE) /* unused? */ 47#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */
48#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */
49#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
46 50
47/* 51/*
48 * Bits for the MB interrupt register. 52 * Bits for the MB interrupt register.
49 * The register appears read-only. 53 * The register appears read-only.
50 */ 54 */
51#define KN05_MB_INT_TC (1<<0) /* TURBOchannel? */ 55#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */
52#define KN05_MB_INT_RTC (1<<1) /* RTC? */ 56#define KN4K_MB_INT_RTC (1<<1) /* RTC? */
53#define KN05_MB_INT_MT (1<<3) /* ??? */ 57#define KN4K_MB_INT_MT (1<<3) /* ??? */
54 58
55/* 59/*
56 * Bits for the MB control & status register. 60 * Bits for the MB control & status register.
57 * Set to 0x00bf8001 on my system by the ROM. 61 * Set to 0x00bf8001 on my system by the ROM.
58 */ 62 */
59#define KN05_MB_CSR_PF (1<<0) /* PreFetching enable? */ 63#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
60#define KN05_MB_CSR_F (1<<1) /* ??? */ 64#define KN4K_MB_CSR_F (1<<1) /* ??? */
61#define KN05_MB_CSR_ECC (0xff<<2) /* ??? */ 65#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */
62#define KN05_MB_CSR_OD (1<<10) /* ??? */ 66#define KN4K_MB_CSR_OD (1<<10) /* ??? */
63#define KN05_MB_CSR_CP (1<<11) /* ??? */ 67#define KN4K_MB_CSR_CP (1<<11) /* ??? */
64#define KN05_MB_CSR_UNC (1<<12) /* ??? */ 68#define KN4K_MB_CSR_UNC (1<<12) /* ??? */
65#define KN05_MB_CSR_IM (1<<13) /* ??? */ 69#define KN4K_MB_CSR_IM (1<<13) /* ??? */
66#define KN05_MB_CSR_NC (1<<14) /* ??? */ 70#define KN4K_MB_CSR_NC (1<<14) /* ??? */
67#define KN05_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ 71#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
68#define KN05_MB_CSR_MSK (0x1f<<16) /* ??? */ 72#define KN4K_MB_CSR_MSK (0x1f<<16) /* ??? */
69#define KN05_MB_CSR_FW (1<<21) /* ??? */ 73#define KN4K_MB_CSR_FW (1<<21) /* ??? */
70 74
71#endif /* __ASM_MIPS_DEC_KN05_H */ 75#endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h
index a05d6d3395fe..1384dd0964b9 100644
--- a/include/asm-mips/dec/prom.h
+++ b/include/asm-mips/dec/prom.h
@@ -24,7 +24,7 @@
24 * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's. 24 * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
25 * Many of these will work for MIPSen as well! 25 * Many of these will work for MIPSen as well!
26 */ 26 */
27#define VEC_RESET (u64 *)KSEG1ADDR(0x1fc00000) 27#define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000)
28 /* Prom base address */ 28 /* Prom base address */
29 29
30#define PMAX_PROM_ENTRY(x) (VEC_RESET + (x)) /* Prom jump table */ 30#define PMAX_PROM_ENTRY(x) (VEC_RESET + (x)) /* Prom jump table */
@@ -111,19 +111,21 @@ extern int (*__pmax_close)(int);
111 * On MIPS64 we have to call PROM functions via a helper 111 * On MIPS64 we have to call PROM functions via a helper
112 * dispatcher to accomodate ABI incompatibilities. 112 * dispatcher to accomodate ABI incompatibilities.
113 */ 113 */
114#define __DEC_PROM_O32 __attribute__((alias("call_o32"))) 114#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
115 115 __asm__(#fun " = call_o32")
116int _rex_bootinit(int (*)(void)) __DEC_PROM_O32; 116
117int _rex_bootread(int (*)(void)) __DEC_PROM_O32; 117int __DEC_PROM_O32(_rex_bootinit, (int (*)(void)));
118int _rex_getbitmap(int (*)(memmap *), memmap *) __DEC_PROM_O32; 118int __DEC_PROM_O32(_rex_bootread, (int (*)(void)));
119unsigned long *_rex_slot_address(unsigned long *(*)(int), int) __DEC_PROM_O32; 119int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *));
120void *_rex_gettcinfo(void *(*)(void)) __DEC_PROM_O32; 120unsigned long *__DEC_PROM_O32(_rex_slot_address,
121int _rex_getsysid(int (*)(void)) __DEC_PROM_O32; 121 (unsigned long *(*)(int), int));
122void _rex_clear_cache(void (*)(void)) __DEC_PROM_O32; 122void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void)));
123 123int __DEC_PROM_O32(_rex_getsysid, (int (*)(void)));
124int _prom_getchar(int (*)(void)) __DEC_PROM_O32; 124void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void)));
125char *_prom_getenv(char *(*)(char *), char *) __DEC_PROM_O32; 125
126int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32; 126int __DEC_PROM_O32(_prom_getchar, (int (*)(void)));
127char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *));
128int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...));
127 129
128 130
129#define rex_bootinit() _rex_bootinit(__rex_bootinit) 131#define rex_bootinit() _rex_bootinit(__rex_bootinit)
diff --git a/include/asm-mips/dec/system.h b/include/asm-mips/dec/system.h
new file mode 100644
index 000000000000..78af51fbc797
--- /dev/null
+++ b/include/asm-mips/dec/system.h
@@ -0,0 +1,18 @@
1/*
2 * include/asm-mips/dec/system.h
3 *
4 * Generic DECstation/DECsystem bits.
5 *
6 * Copyright (C) 2005 Maciej W. Rozycki
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13#ifndef __ASM_DEC_SYSTEM_H
14#define __ASM_DEC_SYSTEM_H
15
16extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
17
18#endif /* __ASM_DEC_SYSTEM_H */
diff --git a/include/asm-mips/dec/tc.h b/include/asm-mips/dec/tc.h
index d7bba43f863a..9cb51f24d42c 100644
--- a/include/asm-mips/dec/tc.h
+++ b/include/asm-mips/dec/tc.h
@@ -7,10 +7,8 @@
7 * 7 *
8 * Copyright (c) 1998 Harald Koerfgen 8 * Copyright (c) 1998 Harald Koerfgen
9 */ 9 */
10#ifndef ASM_TC_H 10#ifndef __ASM_DEC_TC_H
11#define ASM_TC_H 11#define __ASM_DEC_TC_H
12
13extern unsigned long system_base;
14 12
15/* 13/*
16 * Search for a TURBOchannel Option Module 14 * Search for a TURBOchannel Option Module
@@ -36,8 +34,8 @@ extern unsigned long get_tc_base_addr(int);
36 */ 34 */
37extern unsigned long get_tc_irq_nr(int); 35extern unsigned long get_tc_irq_nr(int);
38/* 36/*
39 * Return TURBOchannel clock frequency in hz 37 * Return TURBOchannel clock frequency in Hz
40 */ 38 */
41extern unsigned long get_tc_speed(void); 39extern unsigned long get_tc_speed(void);
42 40
43#endif 41#endif /* __ASM_DEC_TC_H */
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index a606dbee0412..85435a8d4e52 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -12,11 +12,9 @@
12 12
13#include <linux/config.h> 13#include <linux/config.h>
14#include <linux/param.h> 14#include <linux/param.h>
15 15#include <linux/smp.h>
16#include <asm/compiler.h> 16#include <asm/compiler.h>
17 17
18extern unsigned long loops_per_jiffy;
19
20static inline void __delay(unsigned long loops) 18static inline void __delay(unsigned long loops)
21{ 19{
22 if (sizeof(long) == 4) 20 if (sizeof(long) == 4)
@@ -82,11 +80,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
82 __delay(usecs); 80 __delay(usecs);
83} 81}
84 82
85#ifdef CONFIG_SMP
86#define __udelay_val cpu_data[smp_processor_id()].udelay_val 83#define __udelay_val cpu_data[smp_processor_id()].udelay_val
87#else
88#define __udelay_val loops_per_jiffy
89#endif
90 84
91#define udelay(usecs) __udelay((usecs),__udelay_val) 85#define udelay(usecs) __udelay((usecs),__udelay_val)
92 86
diff --git a/include/asm-mips/dsp.h b/include/asm-mips/dsp.h
new file mode 100644
index 000000000000..50f556bb4978
--- /dev/null
+++ b/include/asm-mips/dsp.h
@@ -0,0 +1,83 @@
1/*
2 * Copyright (C) 2005 Mips Technologies
3 * Author: Chris Dearman, chris@mips.com derived from fpu.h
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#ifndef _ASM_DSP_H
11#define _ASM_DSP_H
12
13#include <asm/cpu.h>
14#include <asm/cpu-features.h>
15#include <asm/hazards.h>
16#include <asm/mipsregs.h>
17
18#define DSP_DEFAULT 0x00000000
19#define DSP_MASK 0x1f
20
21#define __enable_dsp_hazard() \
22do { \
23 asm("_ehb"); \
24} while (0)
25
26static inline void __init_dsp(void)
27{
28 mthi1(0);
29 mtlo1(0);
30 mthi2(0);
31 mtlo2(0);
32 mthi3(0);
33 mtlo3(0);
34 wrdsp(DSP_DEFAULT, DSP_MASK);
35}
36
37static inline void init_dsp(void)
38{
39 if (cpu_has_dsp)
40 __init_dsp();
41}
42
43#define __save_dsp(tsk) \
44do { \
45 tsk->thread.dsp.dspr[0] = mfhi1(); \
46 tsk->thread.dsp.dspr[1] = mflo1(); \
47 tsk->thread.dsp.dspr[2] = mfhi2(); \
48 tsk->thread.dsp.dspr[3] = mflo2(); \
49 tsk->thread.dsp.dspr[4] = mfhi3(); \
50 tsk->thread.dsp.dspr[5] = mflo3(); \
51} while (0)
52
53#define save_dsp(tsk) \
54do { \
55 if (cpu_has_dsp) \
56 __save_dsp(tsk); \
57} while (0)
58
59#define __restore_dsp(tsk) \
60do { \
61 mthi1(tsk->thread.dsp.dspr[0]); \
62 mtlo1(tsk->thread.dsp.dspr[1]); \
63 mthi2(tsk->thread.dsp.dspr[2]); \
64 mtlo2(tsk->thread.dsp.dspr[3]); \
65 mthi3(tsk->thread.dsp.dspr[4]); \
66 mtlo3(tsk->thread.dsp.dspr[5]); \
67} while (0)
68
69#define restore_dsp(tsk) \
70do { \
71 if (cpu_has_dsp) \
72 __restore_dsp(tsk); \
73} while (0)
74
75#define __get_dsp_regs(tsk) \
76({ \
77 if (tsk == current) \
78 __save_dsp(current); \
79 \
80 tsk->thread.dsp.dspr; \
81})
82
83#endif /* _ASM_DSP_H */
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h
index e48811440015..7420f12742bb 100644
--- a/include/asm-mips/elf.h
+++ b/include/asm-mips/elf.h
@@ -2,6 +2,8 @@
2 * This file is subject to the terms and conditions of the GNU General Public 2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 *
6 * Much of this is taken from binutils and GNU libc ...
5 */ 7 */
6#ifndef _ASM_ELF_H 8#ifndef _ASM_ELF_H
7#define _ASM_ELF_H 9#define _ASM_ELF_H
@@ -17,6 +19,8 @@
17#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ 19#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
18#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ 20#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */
19#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ 21#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */
22#define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32 R2 code. */
23#define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64 R2 code. */
20 24
21/* The ABI of a file. */ 25/* The ABI of a file. */
22#define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ 26#define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */
@@ -105,7 +109,11 @@
105#define R_MIPS_LOVENDOR 100 109#define R_MIPS_LOVENDOR 100
106#define R_MIPS_HIVENDOR 127 110#define R_MIPS_HIVENDOR 127
107 111
108#define SHN_MIPS_ACCOMON 0xff00 112#define SHN_MIPS_ACCOMON 0xff00 /* Allocated common symbols */
113#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */
114#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */
115#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */
116#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */
109 117
110#define SHT_MIPS_LIST 0x70000000 118#define SHT_MIPS_LIST 0x70000000
111#define SHT_MIPS_CONFLICT 0x70000002 119#define SHT_MIPS_CONFLICT 0x70000002
@@ -193,50 +201,92 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
193 201
194#ifdef __KERNEL__ 202#ifdef __KERNEL__
195 203
204struct mips_abi;
205
206extern struct mips_abi mips_abi;
207extern struct mips_abi mips_abi_32;
208extern struct mips_abi mips_abi_n32;
209
196#ifdef CONFIG_32BIT 210#ifdef CONFIG_32BIT
197 211
198#define SET_PERSONALITY(ex, ibcs2) \ 212#define SET_PERSONALITY(ex, ibcs2) \
199do { \ 213do { \
200 if (ibcs2) \ 214 if (ibcs2) \
201 set_personality(PER_SVR4); \ 215 set_personality(PER_SVR4); \
202 set_personality(PER_LINUX); \ 216 set_personality(PER_LINUX); \
217 \
218 current->thread.abi = &mips_abi; \
203} while (0) 219} while (0)
204 220
205#endif /* CONFIG_32BIT */ 221#endif /* CONFIG_32BIT */
206 222
207#ifdef CONFIG_64BIT 223#ifdef CONFIG_64BIT
208 224
209#define SET_PERSONALITY(ex, ibcs2) \ 225#ifdef CONFIG_MIPS32_N32
210do { current->thread.mflags &= ~MF_ABI_MASK; \ 226#define __SET_PERSONALITY32_N32() \
211 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) { \ 227 do { \
212 if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \ 228 current->thread.mflags |= MF_N32; \
213 ((ex).e_flags & EF_MIPS_ABI) == 0) \ 229 current->thread.abi = &mips_abi_n32; \
214 current->thread.mflags |= MF_N32; \ 230 } while (0)
215 else \ 231#else
216 current->thread.mflags |= MF_O32; \ 232#define __SET_PERSONALITY32_N32() \
217 } else \ 233 do { } while (0)
218 current->thread.mflags |= MF_N64; \ 234#endif
219 if (ibcs2) \ 235
220 set_personality(PER_SVR4); \ 236#ifdef CONFIG_MIPS32_O32
221 else if (current->personality != PER_LINUX32) \ 237#define __SET_PERSONALITY32_O32() \
222 set_personality(PER_LINUX); \ 238 do { \
239 current->thread.mflags |= MF_O32; \
240 current->thread.abi = &mips_abi_32; \
241 } while (0)
242#else
243#define __SET_PERSONALITY32_O32() \
244 do { } while (0)
245#endif
246
247#ifdef CONFIG_MIPS32_COMPAT
248#define __SET_PERSONALITY32(ex) \
249do { \
250 if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \
251 ((ex).e_flags & EF_MIPS_ABI) == 0) \
252 __SET_PERSONALITY32_N32(); \
253 else \
254 __SET_PERSONALITY32_O32(); \
255} while (0)
256#else
257#define __SET_PERSONALITY32(ex) do { } while (0)
258#endif
259
260#define SET_PERSONALITY(ex, ibcs2) \
261do { \
262 current->thread.mflags &= ~MF_ABI_MASK; \
263 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
264 __SET_PERSONALITY32(ex); \
265 else { \
266 current->thread.mflags |= MF_N64; \
267 current->thread.abi = &mips_abi; \
268 } \
269 \
270 if (ibcs2) \
271 set_personality(PER_SVR4); \
272 else if (current->personality != PER_LINUX32) \
273 set_personality(PER_LINUX); \
223} while (0) 274} while (0)
224 275
225#endif /* CONFIG_64BIT */ 276#endif /* CONFIG_64BIT */
226 277
227extern void dump_regs(elf_greg_t *, struct pt_regs *regs); 278extern void dump_regs(elf_greg_t *, struct pt_regs *regs);
279extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
228extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); 280extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
229 281
230#define ELF_CORE_COPY_REGS(elf_regs, regs) \ 282#define ELF_CORE_COPY_REGS(elf_regs, regs) \
231 dump_regs((elf_greg_t *)&(elf_regs), regs); 283 dump_regs((elf_greg_t *)&(elf_regs), regs);
284#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
232#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ 285#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
233 dump_task_fpu(tsk, elf_fpregs) 286 dump_task_fpu(tsk, elf_fpregs)
234 287
235#endif /* __KERNEL__ */ 288#endif /* __KERNEL__ */
236 289
237/* This one accepts IRIX binaries. */
238#define irix_elf_check_arch(hdr) ((hdr)->e_flags & RHF_SGI_ONLY)
239
240#define USE_ELF_CORE_DUMP 290#define USE_ELF_CORE_DUMP
241#define ELF_EXEC_PAGESIZE PAGE_SIZE 291#define ELF_EXEC_PAGESIZE PAGE_SIZE
242 292
diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h
index 3c0d840e4577..9d3e6e7cdb92 100644
--- a/include/asm-mips/errno.h
+++ b/include/asm-mips/errno.h
@@ -119,6 +119,10 @@
119#define EOWNERDEAD 165 /* Owner died */ 119#define EOWNERDEAD 165 /* Owner died */
120#define ENOTRECOVERABLE 166 /* State not recoverable */ 120#define ENOTRECOVERABLE 166 /* State not recoverable */
121 121
122/* for robust mutexes */
123#define EOWNERDEAD 165 /* Owner died */
124#define ENOTRECOVERABLE 166 /* State not recoverable */
125
122#define EDQUOT 1133 /* Quota exceeded */ 126#define EDQUOT 1133 /* Quota exceeded */
123 127
124#ifdef __KERNEL__ 128#ifdef __KERNEL__
diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h
index 06c5d13faf66..43d047a9a6af 100644
--- a/include/asm-mips/fcntl.h
+++ b/include/asm-mips/fcntl.h
@@ -3,11 +3,13 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1995, 96, 97, 98, 99, 2003 Ralf Baechle 6 * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle
7 */ 7 */
8#ifndef _ASM_FCNTL_H 8#ifndef _ASM_FCNTL_H
9#define _ASM_FCNTL_H 9#define _ASM_FCNTL_H
10 10
11#include <linux/config.h>
12
11#define O_APPEND 0x0008 13#define O_APPEND 0x0008
12#define O_SYNC 0x0010 14#define O_SYNC 0x0010
13#define O_NONBLOCK 0x0080 15#define O_NONBLOCK 0x0080
@@ -40,13 +42,13 @@
40 * contain all the same fields as struct flock. 42 * contain all the same fields as struct flock.
41 */ 43 */
42 44
43#ifndef __mips64 45#ifdef CONFIG_32BIT
44 46
45struct flock { 47struct flock {
46 short l_type; 48 short l_type;
47 short l_whence; 49 short l_whence;
48 __kernel_off_t l_start; 50 off_t l_start;
49 __kernel_off_t l_len; 51 off_t l_len;
50 long l_sysid; 52 long l_sysid;
51 __kernel_pid_t l_pid; 53 __kernel_pid_t l_pid;
52 long pad[4]; 54 long pad[4];
@@ -54,13 +56,8 @@ struct flock {
54 56
55#define HAVE_ARCH_STRUCT_FLOCK 57#define HAVE_ARCH_STRUCT_FLOCK
56 58
57#endif 59#endif /* CONFIG_32BIT */
58 60
59#include <asm-generic/fcntl.h> 61#include <asm-generic/fcntl.h>
60 62
61typedef struct flock flock_t;
62#ifndef __mips64
63typedef struct flock64 flock64_t;
64#endif
65
66#endif /* _ASM_FCNTL_H */ 63#endif /* _ASM_FCNTL_H */
diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
index 26b6a90a690b..73a3028dd9f9 100644
--- a/include/asm-mips/fixmap.h
+++ b/include/asm-mips/fixmap.h
@@ -107,4 +107,11 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr)
107 return __virt_to_fix(vaddr); 107 return __virt_to_fix(vaddr);
108} 108}
109 109
110/*
111 * Called from pgtable_init()
112 */
113extern void fixrange_init(unsigned long start, unsigned long end,
114 pgd_t *pgd_base);
115
116
110#endif 117#endif
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
index ea24e733b1bc..9c828b1f8218 100644
--- a/include/asm-mips/fpu.h
+++ b/include/asm-mips/fpu.h
@@ -80,9 +80,14 @@ do { \
80 80
81#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) 81#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
82 82
83static inline int __is_fpu_owner(void)
84{
85 return test_thread_flag(TIF_USEDFPU);
86}
87
83static inline int is_fpu_owner(void) 88static inline int is_fpu_owner(void)
84{ 89{
85 return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); 90 return cpu_has_fpu && __is_fpu_owner();
86} 91}
87 92
88static inline void own_fpu(void) 93static inline void own_fpu(void)
@@ -127,7 +132,7 @@ static inline void restore_fp(struct task_struct *tsk)
127static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) 132static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
128{ 133{
129 if (cpu_has_fpu) { 134 if (cpu_has_fpu) {
130 if ((tsk == current) && is_fpu_owner()) 135 if ((tsk == current) && __is_fpu_owner())
131 _save_fp(current); 136 _save_fp(current);
132 return tsk->thread.fpu.hard.fpr; 137 return tsk->thread.fpu.hard.fpr;
133 } 138 }
diff --git a/include/asm-mips/fpu_emulator.h b/include/asm-mips/fpu_emulator.h
index 46972ae2b95d..16cb4d11dd0b 100644
--- a/include/asm-mips/fpu_emulator.h
+++ b/include/asm-mips/fpu_emulator.h
@@ -23,16 +23,15 @@
23#ifndef _ASM_FPU_EMULATOR_H 23#ifndef _ASM_FPU_EMULATOR_H
24#define _ASM_FPU_EMULATOR_H 24#define _ASM_FPU_EMULATOR_H
25 25
26struct mips_fpu_emulator_private { 26struct mips_fpu_emulator_stats {
27 unsigned int eir; 27 unsigned int emulated;
28 struct { 28 unsigned int loads;
29 unsigned int emulated; 29 unsigned int stores;
30 unsigned int loads; 30 unsigned int cp1ops;
31 unsigned int stores; 31 unsigned int cp1xops;
32 unsigned int cp1ops; 32 unsigned int errors;
33 unsigned int cp1xops;
34 unsigned int errors;
35 } stats;
36}; 33};
37 34
35extern struct mips_fpu_emulator_stats fpuemustats;
36
38#endif /* _ASM_FPU_EMULATOR_H */ 37#endif /* _ASM_FPU_EMULATOR_H */
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index 9feff4ce1424..2454c44a8f54 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -3,10 +3,45 @@
3 3
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5 5
6#include <linux/config.h>
6#include <linux/futex.h> 7#include <linux/futex.h>
7#include <asm/errno.h> 8#include <asm/errno.h>
8#include <asm/uaccess.h> 9#include <asm/uaccess.h>
9 10
11#ifdef CONFIG_SMP
12#define __FUTEX_SMP_SYNC " sync \n"
13#else
14#define __FUTEX_SMP_SYNC
15#endif
16
17#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
18{ \
19 __asm__ __volatile__( \
20 " .set push \n" \
21 " .set noat \n" \
22 " .set mips3 \n" \
23 "1: ll %1, (%3) # __futex_atomic_op1 \n" \
24 " .set mips0 \n" \
25 " " insn " \n" \
26 " .set mips3 \n" \
27 "2: sc $1, (%3) \n" \
28 " beqzl $1, 1b \n" \
29 __FUTEX_SMP_SYNC \
30 "3: \n" \
31 " .set pop \n" \
32 " .set mips0 \n" \
33 " .section .fixup,\"ax\" \n" \
34 "4: li %0, %5 \n" \
35 " j 2b \n" \
36 " .previous \n" \
37 " .section __ex_table,\"a\" \n" \
38 " "__UA_ADDR "\t1b, 4b \n" \
39 " "__UA_ADDR "\t2b, 4b \n" \
40 " .previous \n" \
41 : "=r" (ret), "=r" (oldval) \
42 : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \
43}
44
10static inline int 45static inline int
11futex_atomic_op_inuser (int encoded_op, int __user *uaddr) 46futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
12{ 47{
@@ -25,10 +60,25 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
25 60
26 switch (op) { 61 switch (op) {
27 case FUTEX_OP_SET: 62 case FUTEX_OP_SET:
63 __futex_atomic_op("move $1, %z4", ret, oldval, uaddr, oparg);
64 break;
65
28 case FUTEX_OP_ADD: 66 case FUTEX_OP_ADD:
67 __futex_atomic_op("addu $1, %1, %z4",
68 ret, oldval, uaddr, oparg);
69 break;
29 case FUTEX_OP_OR: 70 case FUTEX_OP_OR:
71 __futex_atomic_op("or $1, %1, %z4",
72 ret, oldval, uaddr, oparg);
73 break;
30 case FUTEX_OP_ANDN: 74 case FUTEX_OP_ANDN:
75 __futex_atomic_op("and $1, %1, %z4",
76 ret, oldval, uaddr, ~oparg);
77 break;
31 case FUTEX_OP_XOR: 78 case FUTEX_OP_XOR:
79 __futex_atomic_op("xor $1, %1, %z4",
80 ret, oldval, uaddr, oparg);
81 break;
32 default: 82 default:
33 ret = -ENOSYS; 83 ret = -ENOSYS;
34 } 84 }
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index f524eaccd5f1..7517189e469f 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -74,7 +74,8 @@
74#define irq_disable_hazard 74#define irq_disable_hazard
75 _ehb 75 _ehb
76 76
77#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) 77#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
78 defined(CONFIG_CPU_SB1)
78 79
79/* 80/*
80 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 81 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -107,6 +108,7 @@ __asm__(
107 " .endm \n\t"); 108 " .endm \n\t");
108 109
109#ifdef CONFIG_CPU_RM9000 110#ifdef CONFIG_CPU_RM9000
111
110/* 112/*
111 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent 113 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
112 * use of the JTLB for instructions should not occur for 4 cpu cycles and use 114 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
@@ -124,6 +126,9 @@ __asm__(
124 ".set\tmips32\n\t" \ 126 ".set\tmips32\n\t" \
125 "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ 127 "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
126 ".set\tmips0") 128 ".set\tmips0")
129
130#define back_to_back_c0_hazard() do { } while (0)
131
127#else 132#else
128 133
129/* 134/*
@@ -144,15 +149,13 @@ __asm__(
144#endif 149#endif
145 150
146/* 151/*
147 * mtc0->mfc0 hazard 152 * Interrupt enable/disable hazards
148 * The 24K has a 2 cycle mtc0/mfc0 execution hazard. 153 * Some processors have hazards when modifying
149 * It is a MIPS32R2 processor so ehb will clear the hazard. 154 * the status register to change the interrupt state
150 */ 155 */
151 156
152#ifdef CONFIG_CPU_MIPSR2 157#ifdef CONFIG_CPU_MIPSR2
153/* 158
154 * Use a macro for ehb unless explicit support for MIPSR2 is enabled
155 */
156__asm__( 159__asm__(
157 " .macro\tirq_enable_hazard \n\t" 160 " .macro\tirq_enable_hazard \n\t"
158 " _ehb \n\t" 161 " _ehb \n\t"
@@ -160,17 +163,26 @@ __asm__(
160 " \n\t" 163 " \n\t"
161 " .macro\tirq_disable_hazard \n\t" 164 " .macro\tirq_disable_hazard \n\t"
162 " _ehb \n\t" 165 " _ehb \n\t"
166 " .endm \n\t"
167 " \n\t"
168 " .macro\tback_to_back_c0_hazard \n\t"
169 " _ehb \n\t"
163 " .endm"); 170 " .endm");
164 171
165#define irq_enable_hazard() \ 172#define irq_enable_hazard() \
166 __asm__ __volatile__( \ 173 __asm__ __volatile__( \
167 "_ehb\t\t\t\t# irq_enable_hazard") 174 "irq_enable_hazard")
168 175
169#define irq_disable_hazard() \ 176#define irq_disable_hazard() \
170 __asm__ __volatile__( \ 177 __asm__ __volatile__( \
171 "_ehb\t\t\t\t# irq_disable_hazard") 178 "irq_disable_hazard")
179
180#define back_to_back_c0_hazard() \
181 __asm__ __volatile__( \
182 "back_to_back_c0_hazard")
172 183
173#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) 184#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
185 defined(CONFIG_CPU_SB1)
174 186
175/* 187/*
176 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 188 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -186,6 +198,8 @@ __asm__(
186#define irq_enable_hazard() do { } while (0) 198#define irq_enable_hazard() do { } while (0)
187#define irq_disable_hazard() do { } while (0) 199#define irq_disable_hazard() do { } while (0)
188 200
201#define back_to_back_c0_hazard() do { } while (0)
202
189#else 203#else
190 204
191/* 205/*
@@ -208,10 +222,32 @@ __asm__(
208#define irq_enable_hazard() do { } while (0) 222#define irq_enable_hazard() do { } while (0)
209#define irq_disable_hazard() \ 223#define irq_disable_hazard() \
210 __asm__ __volatile__( \ 224 __asm__ __volatile__( \
211 "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard") 225 "irq_disable_hazard")
226
227#define back_to_back_c0_hazard() \
228 __asm__ __volatile__( \
229 " .set noreorder \n" \
230 " nop; nop; nop \n" \
231 " .set reorder \n")
212 232
213#endif 233#endif
214 234
235#ifdef CONFIG_CPU_MIPSR2
236#define instruction_hazard() \
237do { \
238__label__ __next; \
239 __asm__ __volatile__( \
240 " jr.hb %0 \n" \
241 : \
242 : "r" (&&__next)); \
243__next: \
244 ; \
245} while (0)
246
247#else
248#define instruction_hazard() do { } while (0)
249#endif
250
215#endif /* __ASSEMBLY__ */ 251#endif /* __ASSEMBLY__ */
216 252
217#endif /* _ASM_HAZARDS_H */ 253#endif /* _ASM_HAZARDS_H */
diff --git a/include/asm-mips/highmem.h b/include/asm-mips/highmem.h
index f49930d947d4..8cf598402492 100644
--- a/include/asm-mips/highmem.h
+++ b/include/asm-mips/highmem.h
@@ -75,6 +75,7 @@ static inline void *kmap_atomic(struct page *page, enum km_type type)
75} 75}
76 76
77static inline void kunmap_atomic(void *kvaddr, enum km_type type) { } 77static inline void kunmap_atomic(void *kvaddr, enum km_type type) { }
78#define kmap_atomic_pfn(pfn, idx) page_address(pfn_to_page(pfn))
78 79
79#define kmap_atomic_to_page(ptr) virt_to_page(ptr) 80#define kmap_atomic_to_page(ptr) virt_to_page(ptr)
80 81
@@ -86,6 +87,7 @@ extern void *__kmap(struct page *page);
86extern void __kunmap(struct page *page); 87extern void __kunmap(struct page *page);
87extern void *__kmap_atomic(struct page *page, enum km_type type); 88extern void *__kmap_atomic(struct page *page, enum km_type type);
88extern void __kunmap_atomic(void *kvaddr, enum km_type type); 89extern void __kunmap_atomic(void *kvaddr, enum km_type type);
90extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
89extern struct page *__kmap_atomic_to_page(void *ptr); 91extern struct page *__kmap_atomic_to_page(void *ptr);
90 92
91#define kmap __kmap 93#define kmap __kmap
diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h
index 6ad517241768..e0745f4ff624 100644
--- a/include/asm-mips/inst.h
+++ b/include/asm-mips/inst.h
@@ -28,7 +28,7 @@ enum major_op {
28 sdl_op, sdr_op, swr_op, cache_op, 28 sdl_op, sdr_op, swr_op, cache_op,
29 ll_op, lwc1_op, lwc2_op, pref_op, 29 ll_op, lwc1_op, lwc2_op, pref_op,
30 lld_op, ldc1_op, ldc2_op, ld_op, 30 lld_op, ldc1_op, ldc2_op, ld_op,
31 sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */ 31 sc_op, swc1_op, swc2_op, rdhwr_op,
32 scd_op, sdc1_op, sdc2_op, sd_op 32 scd_op, sdc1_op, sdc2_op, sd_op
33}; 33};
34 34
@@ -62,10 +62,10 @@ enum rt_op {
62 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, 62 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
63 tgei_op, tgeiu_op, tlti_op, tltiu_op, 63 tgei_op, tgeiu_op, tlti_op, tltiu_op,
64 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, 64 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
65 bltzal_op, bgezal_op, bltzall_op, bgezall_op 65 bltzal_op, bgezal_op, bltzall_op, bgezall_op,
66 /* 66 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
67 * The others (0x14 - 0x1f) are unused. 67 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
68 */ 68 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
69}; 69};
70 70
71/* 71/*
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h
index e8357f5379fa..a5735761f5e5 100644
--- a/include/asm-mips/interrupt.h
+++ b/include/asm-mips/interrupt.h
@@ -11,20 +11,25 @@
11#ifndef _ASM_INTERRUPT_H 11#ifndef _ASM_INTERRUPT_H
12#define _ASM_INTERRUPT_H 12#define _ASM_INTERRUPT_H
13 13
14#include <linux/config.h>
14#include <asm/hazards.h> 15#include <asm/hazards.h>
15 16
16__asm__ ( 17__asm__ (
17 ".macro\tlocal_irq_enable\n\t" 18 " .macro local_irq_enable \n"
18 ".set\tpush\n\t" 19 " .set push \n"
19 ".set\treorder\n\t" 20 " .set reorder \n"
20 ".set\tnoat\n\t" 21 " .set noat \n"
21 "mfc0\t$1,$12\n\t" 22#ifdef CONFIG_CPU_MIPSR2
22 "ori\t$1,0x1f\n\t" 23 " ei \n"
23 "xori\t$1,0x1e\n\t" 24#else
24 "mtc0\t$1,$12\n\t" 25 " mfc0 $1,$12 \n"
25 "irq_enable_hazard\n\t" 26 " ori $1,0x1f \n"
26 ".set\tpop\n\t" 27 " xori $1,0x1e \n"
27 ".endm"); 28 " mtc0 $1,$12 \n"
29#endif
30 " irq_enable_hazard \n"
31 " .set pop \n"
32 " .endm");
28 33
29static inline void local_irq_enable(void) 34static inline void local_irq_enable(void)
30{ 35{
@@ -43,17 +48,21 @@ static inline void local_irq_enable(void)
43 * no nops at all. 48 * no nops at all.
44 */ 49 */
45__asm__ ( 50__asm__ (
46 ".macro\tlocal_irq_disable\n\t" 51 " .macro local_irq_disable\n"
47 ".set\tpush\n\t" 52 " .set push \n"
48 ".set\tnoat\n\t" 53 " .set noat \n"
49 "mfc0\t$1,$12\n\t" 54#ifdef CONFIG_CPU_MIPSR2
50 "ori\t$1,1\n\t" 55 " di \n"
51 "xori\t$1,1\n\t" 56#else
52 ".set\tnoreorder\n\t" 57 " mfc0 $1,$12 \n"
53 "mtc0\t$1,$12\n\t" 58 " ori $1,1 \n"
54 "irq_disable_hazard\n\t" 59 " xori $1,1 \n"
55 ".set\tpop\n\t" 60 " .set noreorder \n"
56 ".endm"); 61 " mtc0 $1,$12 \n"
62#endif
63 " irq_disable_hazard \n"
64 " .set pop \n"
65 " .endm \n");
57 66
58static inline void local_irq_disable(void) 67static inline void local_irq_disable(void)
59{ 68{
@@ -65,12 +74,12 @@ static inline void local_irq_disable(void)
65} 74}
66 75
67__asm__ ( 76__asm__ (
68 ".macro\tlocal_save_flags flags\n\t" 77 " .macro local_save_flags flags \n"
69 ".set\tpush\n\t" 78 " .set push \n"
70 ".set\treorder\n\t" 79 " .set reorder \n"
71 "mfc0\t\\flags, $12\n\t" 80 " mfc0 \\flags, $12 \n"
72 ".set\tpop\n\t" 81 " .set pop \n"
73 ".endm"); 82 " .endm \n");
74 83
75#define local_save_flags(x) \ 84#define local_save_flags(x) \
76__asm__ __volatile__( \ 85__asm__ __volatile__( \
@@ -78,18 +87,22 @@ __asm__ __volatile__( \
78 : "=r" (x)) 87 : "=r" (x))
79 88
80__asm__ ( 89__asm__ (
81 ".macro\tlocal_irq_save result\n\t" 90 " .macro local_irq_save result \n"
82 ".set\tpush\n\t" 91 " .set push \n"
83 ".set\treorder\n\t" 92 " .set reorder \n"
84 ".set\tnoat\n\t" 93 " .set noat \n"
85 "mfc0\t\\result, $12\n\t" 94#ifdef CONFIG_CPU_MIPSR2
86 "ori\t$1, \\result, 1\n\t" 95 " di \\result \n"
87 "xori\t$1, 1\n\t" 96#else
88 ".set\tnoreorder\n\t" 97 " mfc0 \\result, $12 \n"
89 "mtc0\t$1, $12\n\t" 98 " ori $1, \\result, 1 \n"
90 "irq_disable_hazard\n\t" 99 " xori $1, 1 \n"
91 ".set\tpop\n\t" 100 " .set noreorder \n"
92 ".endm"); 101 " mtc0 $1, $12 \n"
102#endif
103 " irq_disable_hazard \n"
104 " .set pop \n"
105 " .endm \n");
93 106
94#define local_irq_save(x) \ 107#define local_irq_save(x) \
95__asm__ __volatile__( \ 108__asm__ __volatile__( \
@@ -99,19 +112,37 @@ __asm__ __volatile__( \
99 : "memory") 112 : "memory")
100 113
101__asm__ ( 114__asm__ (
102 ".macro\tlocal_irq_restore flags\n\t" 115 " .macro local_irq_restore flags \n"
103 ".set\tnoreorder\n\t" 116 " .set noreorder \n"
104 ".set\tnoat\n\t" 117 " .set noat \n"
105 "mfc0\t$1, $12\n\t" 118#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
106 "andi\t\\flags, 1\n\t" 119 /*
107 "ori\t$1, 1\n\t" 120 * Slow, but doesn't suffer from a relativly unlikely race
108 "xori\t$1, 1\n\t" 121 * condition we're having since days 1.
109 "or\t\\flags, $1\n\t" 122 */
110 "mtc0\t\\flags, $12\n\t" 123 " beqz \\flags, 1f \n"
111 "irq_disable_hazard\n\t" 124 " di \n"
112 ".set\tat\n\t" 125 " ei \n"
113 ".set\treorder\n\t" 126 "1: \n"
114 ".endm"); 127#elif defined(CONFIG_CPU_MIPSR2)
128 /*
129 * Fast, dangerous. Life is fun, life is good.
130 */
131 " mfc0 $1, $12 \n"
132 " ins $1, \\flags, 0, 1 \n"
133 " mtc0 $1, $12 \n"
134#else
135 " mfc0 $1, $12 \n"
136 " andi \\flags, 1 \n"
137 " ori $1, 1 \n"
138 " xori $1, 1 \n"
139 " or \\flags, $1 \n"
140 " mtc0 \\flags, $12 \n"
141#endif
142 " irq_disable_hazard \n"
143 " .set at \n"
144 " .set reorder \n"
145 " .endm \n");
115 146
116#define local_irq_restore(flags) \ 147#define local_irq_restore(flags) \
117do { \ 148do { \
diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h
index 4cd36fe98173..92d90f75a636 100644
--- a/include/asm-mips/inventory.h
+++ b/include/asm-mips/inventory.h
@@ -4,6 +4,8 @@
4#ifndef __ASM_INVENTORY_H 4#ifndef __ASM_INVENTORY_H
5#define __ASM_INVENTORY_H 5#define __ASM_INVENTORY_H
6 6
7#include <linux/compiler.h>
8
7typedef struct inventory_s { 9typedef struct inventory_s {
8 struct inventory_s *inv_next; 10 struct inventory_s *inv_next;
9 int inv_class; 11 int inv_class;
@@ -14,7 +16,9 @@ typedef struct inventory_s {
14} inventory_t; 16} inventory_t;
15 17
16extern int inventory_items; 18extern int inventory_items;
17void add_to_inventory (int class, int type, int controller, int unit, int state); 19
18int dump_inventory_to_user (void *userbuf, int size); 20extern void add_to_inventory (int class, int type, int controller, int unit, int state);
21extern int dump_inventory_to_user (void __user *userbuf, int size);
22extern int __init init_inventory(void);
19 23
20#endif /* __ASM_INVENTORY_H */ 24#endif /* __ASM_INVENTORY_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 039845f2e6b0..3061870b7f6c 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -25,7 +25,9 @@
25#include <asm/page.h> 25#include <asm/page.h>
26#include <asm/pgtable-bits.h> 26#include <asm/pgtable-bits.h>
27#include <asm/processor.h> 27#include <asm/processor.h>
28#include <asm/string.h>
28 29
30#include <ioremap.h>
29#include <mangle-port.h> 31#include <mangle-port.h>
30 32
31/* 33/*
@@ -34,7 +36,7 @@
34#undef CONF_SLOWDOWN_IO 36#undef CONF_SLOWDOWN_IO
35 37
36/* 38/*
37 * Raw operations are never swapped in software. Otoh values that raw 39 * Raw operations are never swapped in software. OTOH values that raw
38 * operations are working on may or may not have been swapped by the bus 40 * operations are working on may or may not have been swapped by the bus
39 * hardware. An example use would be for flash memory that's used for 41 * hardware. An example use would be for flash memory that's used for
40 * execute in place. 42 * execute in place.
@@ -43,45 +45,53 @@
43# define __raw_ioswabw(x) (x) 45# define __raw_ioswabw(x) (x)
44# define __raw_ioswabl(x) (x) 46# define __raw_ioswabl(x) (x)
45# define __raw_ioswabq(x) (x) 47# define __raw_ioswabq(x) (x)
48# define ____raw_ioswabq(x) (x)
46 49
47/* 50/*
48 * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware; 51 * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
49 * less sane hardware forces software to fiddle with this... 52 * less sane hardware forces software to fiddle with this...
53 *
54 * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
55 * you can't have the numerical value of data and byte addresses within
56 * multibyte quantities both preserved at the same time. Hence two
57 * variations of functions: non-prefixed ones that preserve the value
58 * and prefixed ones that preserve byte addresses. The latters are
59 * typically used for moving raw data between a peripheral and memory (cf.
60 * string I/O functions), hence the "mem_" prefix.
50 */ 61 */
51#if defined(CONFIG_SWAP_IO_SPACE) 62#if defined(CONFIG_SWAP_IO_SPACE)
52 63
53# define ioswabb(x) (x) 64# define ioswabb(x) (x)
65# define mem_ioswabb(x) (x)
54# ifdef CONFIG_SGI_IP22 66# ifdef CONFIG_SGI_IP22
55/* 67/*
56 * IP22 seems braindead enough to swap 16bits values in hardware, but 68 * IP22 seems braindead enough to swap 16bits values in hardware, but
57 * not 32bits. Go figure... Can't tell without documentation. 69 * not 32bits. Go figure... Can't tell without documentation.
58 */ 70 */
59# define ioswabw(x) (x) 71# define ioswabw(x) (x)
72# define mem_ioswabw(x) le16_to_cpu(x)
60# else 73# else
61# define ioswabw(x) le16_to_cpu(x) 74# define ioswabw(x) le16_to_cpu(x)
75# define mem_ioswabw(x) (x)
62# endif 76# endif
63# define ioswabl(x) le32_to_cpu(x) 77# define ioswabl(x) le32_to_cpu(x)
78# define mem_ioswabl(x) (x)
64# define ioswabq(x) le64_to_cpu(x) 79# define ioswabq(x) le64_to_cpu(x)
80# define mem_ioswabq(x) (x)
65 81
66#else 82#else
67 83
68# define ioswabb(x) (x) 84# define ioswabb(x) (x)
85# define mem_ioswabb(x) (x)
69# define ioswabw(x) (x) 86# define ioswabw(x) (x)
87# define mem_ioswabw(x) cpu_to_le16(x)
70# define ioswabl(x) (x) 88# define ioswabl(x) (x)
89# define mem_ioswabl(x) cpu_to_le32(x)
71# define ioswabq(x) (x) 90# define ioswabq(x) (x)
91# define mem_ioswabq(x) cpu_to_le32(x)
72 92
73#endif 93#endif
74 94
75/*
76 * Native bus accesses never swapped.
77 */
78#define bus_ioswabb(x) (x)
79#define bus_ioswabw(x) (x)
80#define bus_ioswabl(x) (x)
81#define bus_ioswabq(x) (x)
82
83#define __bus_ioswabq bus_ioswabq
84
85#define IO_SPACE_LIMIT 0xffff 95#define IO_SPACE_LIMIT 0xffff
86 96
87/* 97/*
@@ -194,12 +204,14 @@ extern unsigned long isa_slot_offset;
194 */ 204 */
195#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 205#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
196 206
197extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags); 207extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
198extern void __iounmap(volatile void __iomem *addr); 208extern void __iounmap(volatile void __iomem *addr);
199 209
200static inline void * __ioremap_mode(phys_t offset, unsigned long size, 210static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
201 unsigned long flags) 211 unsigned long flags)
202{ 212{
213#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
214
203 if (cpu_has_64bit_addresses) { 215 if (cpu_has_64bit_addresses) {
204 u64 base = UNCAC_BASE; 216 u64 base = UNCAC_BASE;
205 217
@@ -209,10 +221,30 @@ static inline void * __ioremap_mode(phys_t offset, unsigned long size,
209 */ 221 */
210 if (flags == _CACHE_UNCACHED) 222 if (flags == _CACHE_UNCACHED)
211 base = (u64) IO_BASE; 223 base = (u64) IO_BASE;
212 return (void *) (unsigned long) (base + offset); 224 return (void __iomem *) (unsigned long) (base + offset);
225 } else if (__builtin_constant_p(offset) &&
226 __builtin_constant_p(size) && __builtin_constant_p(flags)) {
227 phys_t phys_addr, last_addr;
228
229 phys_addr = fixup_bigphys_addr(offset, size);
230
231 /* Don't allow wraparound or zero size. */
232 last_addr = phys_addr + size - 1;
233 if (!size || last_addr < phys_addr)
234 return NULL;
235
236 /*
237 * Map uncached objects in the low 512MB of address
238 * space using KSEG1.
239 */
240 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
241 flags == _CACHE_UNCACHED)
242 return (void __iomem *)CKSEG1ADDR(phys_addr);
213 } 243 }
214 244
215 return __ioremap(offset, size, flags); 245 return __ioremap(offset, size, flags);
246
247#undef __IS_LOW512
216} 248}
217 249
218/* 250/*
@@ -264,12 +296,16 @@ static inline void * __ioremap_mode(phys_t offset, unsigned long size,
264 296
265static inline void iounmap(volatile void __iomem *addr) 297static inline void iounmap(volatile void __iomem *addr)
266{ 298{
267 if (cpu_has_64bit_addresses) 299#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
300
301 if (cpu_has_64bit_addresses ||
302 (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
268 return; 303 return;
269 304
270 __iounmap(addr); 305 __iounmap(addr);
271}
272 306
307#undef __IS_KSEG1
308}
273 309
274#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ 310#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
275 \ 311 \
@@ -319,7 +355,8 @@ static inline type pfx##read##bwlq(volatile void __iomem *mem) \
319 else if (cpu_has_64bits) { \ 355 else if (cpu_has_64bits) { \
320 unsigned long __flags; \ 356 unsigned long __flags; \
321 \ 357 \
322 local_irq_save(__flags); \ 358 if (irq) \
359 local_irq_save(__flags); \
323 __asm__ __volatile__( \ 360 __asm__ __volatile__( \
324 ".set mips3" "\t\t# __readq" "\n\t" \ 361 ".set mips3" "\t\t# __readq" "\n\t" \
325 "ld %L0, %1" "\n\t" \ 362 "ld %L0, %1" "\n\t" \
@@ -328,7 +365,8 @@ static inline type pfx##read##bwlq(volatile void __iomem *mem) \
328 ".set mips0" "\n" \ 365 ".set mips0" "\n" \
329 : "=r" (__val) \ 366 : "=r" (__val) \
330 : "m" (*__mem)); \ 367 : "m" (*__mem)); \
331 local_irq_restore(__flags); \ 368 if (irq) \
369 local_irq_restore(__flags); \
332 } else { \ 370 } else { \
333 __val = 0; \ 371 __val = 0; \
334 BUG(); \ 372 BUG(); \
@@ -349,11 +387,11 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
349 \ 387 \
350 __val = pfx##ioswab##bwlq(val); \ 388 __val = pfx##ioswab##bwlq(val); \
351 \ 389 \
352 if (sizeof(type) != sizeof(u64)) { \ 390 /* Really, we want this to be atomic */ \
353 *__addr = __val; \ 391 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
354 slow; \ 392 \
355 } else \ 393 *__addr = __val; \
356 BUILD_BUG(); \ 394 slow; \
357} \ 395} \
358 \ 396 \
359static inline type pfx##in##bwlq##p(unsigned long port) \ 397static inline type pfx##in##bwlq##p(unsigned long port) \
@@ -364,13 +402,10 @@ static inline type pfx##in##bwlq##p(unsigned long port) \
364 port = __swizzle_addr_##bwlq(port); \ 402 port = __swizzle_addr_##bwlq(port); \
365 __addr = (void *)(mips_io_port_base + port); \ 403 __addr = (void *)(mips_io_port_base + port); \
366 \ 404 \
367 if (sizeof(type) != sizeof(u64)) { \ 405 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
368 __val = *__addr; \ 406 \
369 slow; \ 407 __val = *__addr; \
370 } else { \ 408 slow; \
371 __val = 0; \
372 BUILD_BUG(); \
373 } \
374 \ 409 \
375 return pfx##ioswab##bwlq(__val); \ 410 return pfx##ioswab##bwlq(__val); \
376} 411}
@@ -379,27 +414,35 @@ static inline type pfx##in##bwlq##p(unsigned long port) \
379 \ 414 \
380__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) 415__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
381 416
382#define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 417#define BUILDIO_MEM(bwlq, type) \
383 \
384__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
385__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
386
387#define BUILDIO(bwlq, type) \
388 \ 418 \
389__BUILD_MEMORY_PFX(, bwlq, type) \
390__BUILD_MEMORY_PFX(__raw_, bwlq, type) \ 419__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
391__BUILD_MEMORY_PFX(bus_, bwlq, type) \ 420__BUILD_MEMORY_PFX(, bwlq, type) \
392__BUILD_IOPORT_PFX(, bwlq, type) \ 421__BUILD_MEMORY_PFX(mem_, bwlq, type) \
393__BUILD_IOPORT_PFX(__raw_, bwlq, type) 422
423BUILDIO_MEM(b, u8)
424BUILDIO_MEM(w, u16)
425BUILDIO_MEM(l, u32)
426BUILDIO_MEM(q, u64)
427
428#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
429 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
430 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
431
432#define BUILDIO_IOPORT(bwlq, type) \
433 __BUILD_IOPORT_PFX(, bwlq, type) \
434 __BUILD_IOPORT_PFX(mem_, bwlq, type)
435
436BUILDIO_IOPORT(b, u8)
437BUILDIO_IOPORT(w, u16)
438BUILDIO_IOPORT(l, u32)
439#ifdef CONFIG_64BIT
440BUILDIO_IOPORT(q, u64)
441#endif
394 442
395#define __BUILDIO(bwlq, type) \ 443#define __BUILDIO(bwlq, type) \
396 \ 444 \
397__BUILD_MEMORY_SINGLE(__bus_, bwlq, type, 0) 445__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
398
399BUILDIO(b, u8)
400BUILDIO(w, u16)
401BUILDIO(l, u32)
402BUILDIO(q, u64)
403 446
404__BUILDIO(q, u64) 447__BUILDIO(q, u64)
405 448
@@ -422,7 +465,7 @@ static inline void writes##bwlq(volatile void __iomem *mem, void *addr, \
422 volatile type *__addr = addr; \ 465 volatile type *__addr = addr; \
423 \ 466 \
424 while (count--) { \ 467 while (count--) { \
425 __raw_write##bwlq(*__addr, mem); \ 468 mem_write##bwlq(*__addr, mem); \
426 __addr++; \ 469 __addr++; \
427 } \ 470 } \
428} \ 471} \
@@ -433,20 +476,20 @@ static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
433 volatile type *__addr = addr; \ 476 volatile type *__addr = addr; \
434 \ 477 \
435 while (count--) { \ 478 while (count--) { \
436 *__addr = __raw_read##bwlq(mem); \ 479 *__addr = mem_read##bwlq(mem); \
437 __addr++; \ 480 __addr++; \
438 } \ 481 } \
439} 482}
440 483
441#define __BUILD_IOPORT_STRING(bwlq, type) \ 484#define __BUILD_IOPORT_STRING(bwlq, type) \
442 \ 485 \
443static inline void outs##bwlq(unsigned long port, void *addr, \ 486static inline void outs##bwlq(unsigned long port, const void *addr, \
444 unsigned int count) \ 487 unsigned int count) \
445{ \ 488{ \
446 volatile type *__addr = addr; \ 489 const volatile type *__addr = addr; \
447 \ 490 \
448 while (count--) { \ 491 while (count--) { \
449 __raw_out##bwlq(*__addr, port); \ 492 mem_out##bwlq(*__addr, port); \
450 __addr++; \ 493 __addr++; \
451 } \ 494 } \
452} \ 495} \
@@ -457,7 +500,7 @@ static inline void ins##bwlq(unsigned long port, void *addr, \
457 volatile type *__addr = addr; \ 500 volatile type *__addr = addr; \
458 \ 501 \
459 while (count--) { \ 502 while (count--) { \
460 *__addr = __raw_in##bwlq(port); \ 503 *__addr = mem_in##bwlq(port); \
461 __addr++; \ 504 __addr++; \
462 } \ 505 } \
463} 506}
@@ -470,15 +513,26 @@ __BUILD_IOPORT_STRING(bwlq, type)
470BUILDSTRING(b, u8) 513BUILDSTRING(b, u8)
471BUILDSTRING(w, u16) 514BUILDSTRING(w, u16)
472BUILDSTRING(l, u32) 515BUILDSTRING(l, u32)
516#ifdef CONFIG_64BIT
473BUILDSTRING(q, u64) 517BUILDSTRING(q, u64)
518#endif
474 519
475 520
476/* Depends on MIPS II instruction set */ 521/* Depends on MIPS II instruction set */
477#define mmiowb() asm volatile ("sync" ::: "memory") 522#define mmiowb() asm volatile ("sync" ::: "memory")
478 523
479#define memset_io(a,b,c) memset((void *)(a),(b),(c)) 524static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
480#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) 525{
481#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) 526 memset((void __force *) addr, val, count);
527}
528static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
529{
530 memcpy(dst, (void __force *) src, count);
531}
532static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
533{
534 memcpy((void __force *) dst, src, count);
535}
482 536
483/* 537/*
484 * Memory Mapped I/O 538 * Memory Mapped I/O
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 3f2470e9e678..8a342ccb34a8 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -24,11 +24,9 @@ static inline int irq_canonicalize(int irq)
24 24
25struct pt_regs; 25struct pt_regs;
26 26
27#ifdef CONFIG_PREEMPT
28
29extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs); 27extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs);
30 28
31#else 29#ifdef CONFIG_PREEMPT
32 30
33/* 31/*
34 * do_IRQ handles all normal device IRQ's (the special 32 * do_IRQ handles all normal device IRQ's (the special
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index 86df317b4078..baf412967afa 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -202,20 +202,6 @@ static inline int jmr3927_have_isac(void)
202#endif /* !__ASSEMBLY__ */ 202#endif /* !__ASSEMBLY__ */
203 203
204/* 204/*
205 * UART defines for serial.h
206 */
207
208/* use Pre-scaler T0 (1/2) */
209#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16)
210
211#define UART0_ADDR 0xfffef300
212#define UART1_ADDR 0xfffef400
213#define UART0_INT JMR3927_IRQ_IRC_SIO0
214#define UART1_INT JMR3927_IRQ_IRC_SIO1
215#define UART0_FLAGS ASYNC_BOOT_AUTOCONF
216#define UART1_FLAGS 0
217
218/*
219 * IRQ mappings 205 * IRQ mappings
220 */ 206 */
221 207
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 148bae2fa7d3..8327ec341c18 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -60,59 +60,36 @@ void static inline au_sync_delay(int ms)
60 mdelay(ms); 60 mdelay(ms);
61} 61}
62 62
63void static inline au_writeb(u8 val, int reg) 63void static inline au_writeb(u8 val, unsigned long reg)
64{ 64{
65 *(volatile u8 *)(reg) = val; 65 *(volatile u8 *)(reg) = val;
66} 66}
67 67
68void static inline au_writew(u16 val, int reg) 68void static inline au_writew(u16 val, unsigned long reg)
69{ 69{
70 *(volatile u16 *)(reg) = val; 70 *(volatile u16 *)(reg) = val;
71} 71}
72 72
73void static inline au_writel(u32 val, int reg) 73void static inline au_writel(u32 val, unsigned long reg)
74{ 74{
75 *(volatile u32 *)(reg) = val; 75 *(volatile u32 *)(reg) = val;
76} 76}
77 77
78static inline u8 au_readb(unsigned long port) 78static inline u8 au_readb(unsigned long reg)
79{ 79{
80 return (*(volatile u8 *)port); 80 return (*(volatile u8 *)reg);
81} 81}
82 82
83static inline u16 au_readw(unsigned long port) 83static inline u16 au_readw(unsigned long reg)
84{ 84{
85 return (*(volatile u16 *)port); 85 return (*(volatile u16 *)reg);
86} 86}
87 87
88static inline u32 au_readl(unsigned long port) 88static inline u32 au_readl(unsigned long reg)
89{ 89{
90 return (*(volatile u32 *)port); 90 return (*(volatile u32 *)reg);
91} 91}
92 92
93/* These next three functions should be a generic part of the MIPS
94 * kernel (with the 'au_' removed from the name) and selected for
95 * processors that support the instructions.
96 * Taken from PPC tree. -- Dan
97 */
98/* Return the bit position of the most significant 1 bit in a word */
99static __inline__ int __ilog2(unsigned int x)
100{
101 int lz;
102
103 asm volatile (
104 ".set\tnoreorder\n\t"
105 ".set\tnoat\n\t"
106 ".set\tmips32\n\t"
107 "clz\t%0,%1\n\t"
108 ".set\tmips0\n\t"
109 ".set\tat\n\t"
110 ".set\treorder"
111 : "=r" (lz)
112 : "r" (x));
113
114 return 31 - lz;
115}
116 93
117static __inline__ int au_ffz(unsigned int x) 94static __inline__ int au_ffz(unsigned int x)
118{ 95{
@@ -162,28 +139,293 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
162#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) 139#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
163#endif 140#endif
164 141
165/* SDRAM Controller */ 142/*
143 * SDRAM Register Offsets
144 */
166#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) 145#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
167#define MEM_SDMODE0 0xB4000000 146#define MEM_SDMODE0 (0x0000)
168#define MEM_SDMODE1 0xB4000004 147#define MEM_SDMODE1 (0x0004)
169#define MEM_SDMODE2 0xB4000008 148#define MEM_SDMODE2 (0x0008)
149#define MEM_SDADDR0 (0x000C)
150#define MEM_SDADDR1 (0x0010)
151#define MEM_SDADDR2 (0x0014)
152#define MEM_SDREFCFG (0x0018)
153#define MEM_SDPRECMD (0x001C)
154#define MEM_SDAUTOREF (0x0020)
155#define MEM_SDWRMD0 (0x0024)
156#define MEM_SDWRMD1 (0x0028)
157#define MEM_SDWRMD2 (0x002C)
158#define MEM_SDSLEEP (0x0030)
159#define MEM_SDSMCKE (0x0034)
170 160
171#define MEM_SDADDR0 0xB400000C 161/*
172#define MEM_SDADDR1 0xB4000010 162 * MEM_SDMODE register content definitions
173#define MEM_SDADDR2 0xB4000014 163 */
164#define MEM_SDMODE_F (1<<22)
165#define MEM_SDMODE_SR (1<<21)
166#define MEM_SDMODE_BS (1<<20)
167#define MEM_SDMODE_RS (3<<18)
168#define MEM_SDMODE_CS (7<<15)
169#define MEM_SDMODE_TRAS (15<<11)
170#define MEM_SDMODE_TMRD (3<<9)
171#define MEM_SDMODE_TWR (3<<7)
172#define MEM_SDMODE_TRP (3<<5)
173#define MEM_SDMODE_TRCD (3<<3)
174#define MEM_SDMODE_TCL (7<<0)
175
176#define MEM_SDMODE_BS_2Bank (0<<20)
177#define MEM_SDMODE_BS_4Bank (1<<20)
178#define MEM_SDMODE_RS_11Row (0<<18)
179#define MEM_SDMODE_RS_12Row (1<<18)
180#define MEM_SDMODE_RS_13Row (2<<18)
181#define MEM_SDMODE_RS_N(N) ((N)<<18)
182#define MEM_SDMODE_CS_7Col (0<<15)
183#define MEM_SDMODE_CS_8Col (1<<15)
184#define MEM_SDMODE_CS_9Col (2<<15)
185#define MEM_SDMODE_CS_10Col (3<<15)
186#define MEM_SDMODE_CS_11Col (4<<15)
187#define MEM_SDMODE_CS_N(N) ((N)<<15)
188#define MEM_SDMODE_TRAS_N(N) ((N)<<11)
189#define MEM_SDMODE_TMRD_N(N) ((N)<<9)
190#define MEM_SDMODE_TWR_N(N) ((N)<<7)
191#define MEM_SDMODE_TRP_N(N) ((N)<<5)
192#define MEM_SDMODE_TRCD_N(N) ((N)<<3)
193#define MEM_SDMODE_TCL_N(N) ((N)<<0)
174 194
175#define MEM_SDREFCFG 0xB4000018 195/*
176#define MEM_SDPRECMD 0xB400001C 196 * MEM_SDADDR register contents definitions
177#define MEM_SDAUTOREF 0xB4000020 197 */
198#define MEM_SDADDR_E (1<<20)
199#define MEM_SDADDR_CSBA (0x03FF<<10)
200#define MEM_SDADDR_CSMASK (0x03FF<<0)
201#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12)
202#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
203
204/*
205 * MEM_SDREFCFG register content definitions
206 */
207#define MEM_SDREFCFG_TRC (15<<28)
208#define MEM_SDREFCFG_TRPM (3<<26)
209#define MEM_SDREFCFG_E (1<<25)
210#define MEM_SDREFCFG_RE (0x1ffffff<<0)
211#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC)
212#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
213#define MEM_SDREFCFG_REF_N(N) (N)
214#endif
178 215
179#define MEM_SDWRMD0 0xB4000024 216/***********************************************************************/
180#define MEM_SDWRMD1 0xB4000028
181#define MEM_SDWRMD2 0xB400002C
182 217
183#define MEM_SDSLEEP 0xB4000030 218/*
184#define MEM_SDSMCKE 0xB4000034 219 * Au1550 SDRAM Register Offsets
220 */
221
222/***********************************************************************/
223
224#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
225#define MEM_SDMODE0 (0x0800)
226#define MEM_SDMODE1 (0x0808)
227#define MEM_SDMODE2 (0x0810)
228#define MEM_SDADDR0 (0x0820)
229#define MEM_SDADDR1 (0x0828)
230#define MEM_SDADDR2 (0x0830)
231#define MEM_SDCONFIGA (0x0840)
232#define MEM_SDCONFIGB (0x0848)
233#define MEM_SDSTAT (0x0850)
234#define MEM_SDERRADDR (0x0858)
235#define MEM_SDSTRIDE0 (0x0860)
236#define MEM_SDSTRIDE1 (0x0868)
237#define MEM_SDSTRIDE2 (0x0870)
238#define MEM_SDWRMD0 (0x0880)
239#define MEM_SDWRMD1 (0x0888)
240#define MEM_SDWRMD2 (0x0890)
241#define MEM_SDPRECMD (0x08C0)
242#define MEM_SDAUTOREF (0x08C8)
243#define MEM_SDSREF (0x08D0)
244#define MEM_SDSLEEP MEM_SDSREF
245
246#endif
247
248/*
249 * Physical base addresses for integrated peripherals
250 */
251
252#ifdef CONFIG_SOC_AU1000
253#define MEM_PHYS_ADDR 0x14000000
254#define STATIC_MEM_PHYS_ADDR 0x14001000
255#define DMA0_PHYS_ADDR 0x14002000
256#define DMA1_PHYS_ADDR 0x14002100
257#define DMA2_PHYS_ADDR 0x14002200
258#define DMA3_PHYS_ADDR 0x14002300
259#define DMA4_PHYS_ADDR 0x14002400
260#define DMA5_PHYS_ADDR 0x14002500
261#define DMA6_PHYS_ADDR 0x14002600
262#define DMA7_PHYS_ADDR 0x14002700
263#define IC0_PHYS_ADDR 0x10400000
264#define IC1_PHYS_ADDR 0x11800000
265#define AC97_PHYS_ADDR 0x10000000
266#define USBH_PHYS_ADDR 0x10100000
267#define USBD_PHYS_ADDR 0x10200000
268#define IRDA_PHYS_ADDR 0x10300000
269#define MAC0_PHYS_ADDR 0x10500000
270#define MAC1_PHYS_ADDR 0x10510000
271#define MACEN_PHYS_ADDR 0x10520000
272#define MACDMA0_PHYS_ADDR 0x14004000
273#define MACDMA1_PHYS_ADDR 0x14004200
274#define I2S_PHYS_ADDR 0x11000000
275#define UART0_PHYS_ADDR 0x11100000
276#define UART1_PHYS_ADDR 0x11200000
277#define UART2_PHYS_ADDR 0x11300000
278#define UART3_PHYS_ADDR 0x11400000
279#define SSI0_PHYS_ADDR 0x11600000
280#define SSI1_PHYS_ADDR 0x11680000
281#define SYS_PHYS_ADDR 0x11900000
282#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
283#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
284#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
185#endif 285#endif
186 286
287/********************************************************************/
288
289#ifdef CONFIG_SOC_AU1500
290#define MEM_PHYS_ADDR 0x14000000
291#define STATIC_MEM_PHYS_ADDR 0x14001000
292#define DMA0_PHYS_ADDR 0x14002000
293#define DMA1_PHYS_ADDR 0x14002100
294#define DMA2_PHYS_ADDR 0x14002200
295#define DMA3_PHYS_ADDR 0x14002300
296#define DMA4_PHYS_ADDR 0x14002400
297#define DMA5_PHYS_ADDR 0x14002500
298#define DMA6_PHYS_ADDR 0x14002600
299#define DMA7_PHYS_ADDR 0x14002700
300#define IC0_PHYS_ADDR 0x10400000
301#define IC1_PHYS_ADDR 0x11800000
302#define AC97_PHYS_ADDR 0x10000000
303#define USBH_PHYS_ADDR 0x10100000
304#define USBD_PHYS_ADDR 0x10200000
305#define PCI_PHYS_ADDR 0x14005000
306#define MAC0_PHYS_ADDR 0x11500000
307#define MAC1_PHYS_ADDR 0x11510000
308#define MACEN_PHYS_ADDR 0x11520000
309#define MACDMA0_PHYS_ADDR 0x14004000
310#define MACDMA1_PHYS_ADDR 0x14004200
311#define I2S_PHYS_ADDR 0x11000000
312#define UART0_PHYS_ADDR 0x11100000
313#define UART3_PHYS_ADDR 0x11400000
314#define GPIO2_PHYS_ADDR 0x11700000
315#define SYS_PHYS_ADDR 0x11900000
316#define PCI_MEM_PHYS_ADDR 0x400000000ULL
317#define PCI_IO_PHYS_ADDR 0x500000000ULL
318#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
319#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
320#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
321#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
322#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
323#endif
324
325/********************************************************************/
326
327#ifdef CONFIG_SOC_AU1100
328#define MEM_PHYS_ADDR 0x14000000
329#define STATIC_MEM_PHYS_ADDR 0x14001000
330#define DMA0_PHYS_ADDR 0x14002000
331#define DMA1_PHYS_ADDR 0x14002100
332#define DMA2_PHYS_ADDR 0x14002200
333#define DMA3_PHYS_ADDR 0x14002300
334#define DMA4_PHYS_ADDR 0x14002400
335#define DMA5_PHYS_ADDR 0x14002500
336#define DMA6_PHYS_ADDR 0x14002600
337#define DMA7_PHYS_ADDR 0x14002700
338#define IC0_PHYS_ADDR 0x10400000
339#define SD0_PHYS_ADDR 0x10600000
340#define SD1_PHYS_ADDR 0x10680000
341#define IC1_PHYS_ADDR 0x11800000
342#define AC97_PHYS_ADDR 0x10000000
343#define USBH_PHYS_ADDR 0x10100000
344#define USBD_PHYS_ADDR 0x10200000
345#define IRDA_PHYS_ADDR 0x10300000
346#define MAC0_PHYS_ADDR 0x10500000
347#define MACEN_PHYS_ADDR 0x10520000
348#define MACDMA0_PHYS_ADDR 0x14004000
349#define MACDMA1_PHYS_ADDR 0x14004200
350#define I2S_PHYS_ADDR 0x11000000
351#define UART0_PHYS_ADDR 0x11100000
352#define UART1_PHYS_ADDR 0x11200000
353#define UART3_PHYS_ADDR 0x11400000
354#define SSI0_PHYS_ADDR 0x11600000
355#define SSI1_PHYS_ADDR 0x11680000
356#define GPIO2_PHYS_ADDR 0x11700000
357#define SYS_PHYS_ADDR 0x11900000
358#define LCD_PHYS_ADDR 0x15000000
359#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
360#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
361#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
362#endif
363
364/***********************************************************************/
365
366#ifdef CONFIG_SOC_AU1550
367#define MEM_PHYS_ADDR 0x14000000
368#define STATIC_MEM_PHYS_ADDR 0x14001000
369#define IC0_PHYS_ADDR 0x10400000
370#define IC1_PHYS_ADDR 0x11800000
371#define USBH_PHYS_ADDR 0x14020000
372#define USBD_PHYS_ADDR 0x10200000
373#define PCI_PHYS_ADDR 0x14005000
374#define MAC0_PHYS_ADDR 0x10500000
375#define MAC1_PHYS_ADDR 0x10510000
376#define MACEN_PHYS_ADDR 0x10520000
377#define MACDMA0_PHYS_ADDR 0x14004000
378#define MACDMA1_PHYS_ADDR 0x14004200
379#define UART0_PHYS_ADDR 0x11100000
380#define UART1_PHYS_ADDR 0x11200000
381#define UART3_PHYS_ADDR 0x11400000
382#define GPIO2_PHYS_ADDR 0x11700000
383#define SYS_PHYS_ADDR 0x11900000
384#define DDMA_PHYS_ADDR 0x14002000
385#define PE_PHYS_ADDR 0x14008000
386#define PSC0_PHYS_ADDR 0x11A00000
387#define PSC1_PHYS_ADDR 0x11B00000
388#define PSC2_PHYS_ADDR 0x10A00000
389#define PSC3_PHYS_ADDR 0x10B00000
390#define PCI_MEM_PHYS_ADDR 0x400000000ULL
391#define PCI_IO_PHYS_ADDR 0x500000000ULL
392#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
393#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
394#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
395#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
396#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
397#endif
398
399/***********************************************************************/
400
401#ifdef CONFIG_SOC_AU1200
402#define MEM_PHYS_ADDR 0x14000000
403#define STATIC_MEM_PHYS_ADDR 0x14001000
404#define AES_PHYS_ADDR 0x10300000
405#define CIM_PHYS_ADDR 0x14004000
406#define IC0_PHYS_ADDR 0x10400000
407#define IC1_PHYS_ADDR 0x11800000
408#define USBM_PHYS_ADDR 0x14020000
409#define USBH_PHYS_ADDR 0x14020100
410#define UART0_PHYS_ADDR 0x11100000
411#define UART1_PHYS_ADDR 0x11200000
412#define GPIO2_PHYS_ADDR 0x11700000
413#define SYS_PHYS_ADDR 0x11900000
414#define DDMA_PHYS_ADDR 0x14002000
415#define PSC0_PHYS_ADDR 0x11A00000
416#define PSC1_PHYS_ADDR 0x11B00000
417#define SD0_PHYS_ADDR 0x10600000
418#define SD1_PHYS_ADDR 0x10680000
419#define LCD_PHYS_ADDR 0x15000000
420#define SWCNT_PHYS_ADDR 0x1110010C
421#define MAEFE_PHYS_ADDR 0x14012000
422#define MAEBE_PHYS_ADDR 0x14010000
423#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
424#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
425#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
426#endif
427
428
187/* Static Bus Controller */ 429/* Static Bus Controller */
188#define MEM_STCFG0 0xB4001000 430#define MEM_STCFG0 0xB4001000
189#define MEM_STTIME0 0xB4001004 431#define MEM_STTIME0 0xB4001004
@@ -369,7 +611,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
369#define AU1000_MAC0_ENABLE 0xB0520000 611#define AU1000_MAC0_ENABLE 0xB0520000
370#define AU1000_MAC1_ENABLE 0xB0520004 612#define AU1000_MAC1_ENABLE 0xB0520004
371#define NUM_ETH_INTERFACES 2 613#define NUM_ETH_INTERFACES 2
372#endif // CONFIG_SOC_AU1000 614#endif /* CONFIG_SOC_AU1000 */
373 615
374/* Au1500 */ 616/* Au1500 */
375#ifdef CONFIG_SOC_AU1500 617#ifdef CONFIG_SOC_AU1500
@@ -429,6 +671,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
429#define AU1500_GPIO_207 62 671#define AU1500_GPIO_207 62
430#define AU1500_GPIO_208_215 63 672#define AU1500_GPIO_208_215 63
431 673
674/* shortcuts */
675#define INTA AU1000_PCI_INTA
676#define INTB AU1000_PCI_INTB
677#define INTC AU1000_PCI_INTC
678#define INTD AU1000_PCI_INTD
679
432#define UART0_ADDR 0xB1100000 680#define UART0_ADDR 0xB1100000
433#define UART3_ADDR 0xB1400000 681#define UART3_ADDR 0xB1400000
434 682
@@ -440,7 +688,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
440#define AU1500_MAC0_ENABLE 0xB1520000 688#define AU1500_MAC0_ENABLE 0xB1520000
441#define AU1500_MAC1_ENABLE 0xB1520004 689#define AU1500_MAC1_ENABLE 0xB1520004
442#define NUM_ETH_INTERFACES 2 690#define NUM_ETH_INTERFACES 2
443#endif // CONFIG_SOC_AU1500 691#endif /* CONFIG_SOC_AU1500 */
444 692
445/* Au1100 */ 693/* Au1100 */
446#ifdef CONFIG_SOC_AU1100 694#ifdef CONFIG_SOC_AU1100
@@ -485,6 +733,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
485#define AU1000_GPIO_13 45 733#define AU1000_GPIO_13 45
486#define AU1000_GPIO_14 46 734#define AU1000_GPIO_14 46
487#define AU1000_GPIO_15 47 735#define AU1000_GPIO_15 47
736#define AU1000_GPIO_16 48
737#define AU1000_GPIO_17 49
738#define AU1000_GPIO_18 50
739#define AU1000_GPIO_19 51
740#define AU1000_GPIO_20 52
741#define AU1000_GPIO_21 53
742#define AU1000_GPIO_22 54
743#define AU1000_GPIO_23 55
744#define AU1000_GPIO_24 56
745#define AU1000_GPIO_25 57
746#define AU1000_GPIO_26 58
747#define AU1000_GPIO_27 59
748#define AU1000_GPIO_28 60
749#define AU1000_GPIO_29 61
750#define AU1000_GPIO_30 62
751#define AU1000_GPIO_31 63
488 752
489#define UART0_ADDR 0xB1100000 753#define UART0_ADDR 0xB1100000
490#define UART1_ADDR 0xB1200000 754#define UART1_ADDR 0xB1200000
@@ -496,7 +760,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
496#define AU1100_ETH0_BASE 0xB0500000 760#define AU1100_ETH0_BASE 0xB0500000
497#define AU1100_MAC0_ENABLE 0xB0520000 761#define AU1100_MAC0_ENABLE 0xB0520000
498#define NUM_ETH_INTERFACES 1 762#define NUM_ETH_INTERFACES 1
499#endif // CONFIG_SOC_AU1100 763#endif /* CONFIG_SOC_AU1100 */
500 764
501#ifdef CONFIG_SOC_AU1550 765#ifdef CONFIG_SOC_AU1550
502#define AU1550_UART0_INT 0 766#define AU1550_UART0_INT 0
@@ -513,14 +777,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
513#define AU1550_PSC1_INT 11 777#define AU1550_PSC1_INT 11
514#define AU1550_PSC2_INT 12 778#define AU1550_PSC2_INT 12
515#define AU1550_PSC3_INT 13 779#define AU1550_PSC3_INT 13
516#define AU1550_TOY_INT 14 780#define AU1000_TOY_INT 14
517#define AU1550_TOY_MATCH0_INT 15 781#define AU1000_TOY_MATCH0_INT 15
518#define AU1550_TOY_MATCH1_INT 16 782#define AU1000_TOY_MATCH1_INT 16
519#define AU1550_TOY_MATCH2_INT 17 783#define AU1000_TOY_MATCH2_INT 17
520#define AU1550_RTC_INT 18 784#define AU1000_RTC_INT 18
521#define AU1550_RTC_MATCH0_INT 19 785#define AU1000_RTC_MATCH0_INT 19
522#define AU1550_RTC_MATCH1_INT 20 786#define AU1000_RTC_MATCH1_INT 20
523#define AU1550_RTC_MATCH2_INT 21 787#define AU1000_RTC_MATCH2_INT 21
524#define AU1550_NAND_INT 23 788#define AU1550_NAND_INT 23
525#define AU1550_USB_DEV_REQ_INT 24 789#define AU1550_USB_DEV_REQ_INT 24
526#define AU1550_USB_DEV_SUS_INT 25 790#define AU1550_USB_DEV_SUS_INT 25
@@ -563,6 +827,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
563#define AU1500_GPIO_207 62 827#define AU1500_GPIO_207 62
564#define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218 828#define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218
565 829
830/* shortcuts */
831#define INTA AU1550_PCI_INTA
832#define INTB AU1550_PCI_INTB
833#define INTC AU1550_PCI_INTC
834#define INTD AU1550_PCI_INTD
835
566#define UART0_ADDR 0xB1100000 836#define UART0_ADDR 0xB1100000
567#define UART1_ADDR 0xB1200000 837#define UART1_ADDR 0xB1200000
568#define UART3_ADDR 0xB1400000 838#define UART3_ADDR 0xB1400000
@@ -575,7 +845,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
575#define AU1550_MAC0_ENABLE 0xB0520000 845#define AU1550_MAC0_ENABLE 0xB0520000
576#define AU1550_MAC1_ENABLE 0xB0520004 846#define AU1550_MAC1_ENABLE 0xB0520004
577#define NUM_ETH_INTERFACES 2 847#define NUM_ETH_INTERFACES 2
578#endif // CONFIG_SOC_AU1550 848#endif /* CONFIG_SOC_AU1550 */
579 849
580#ifdef CONFIG_SOC_AU1200 850#ifdef CONFIG_SOC_AU1200
581#define AU1200_UART0_INT 0 851#define AU1200_UART0_INT 0
@@ -592,14 +862,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
592#define AU1200_PSC1_INT 11 862#define AU1200_PSC1_INT 11
593#define AU1200_AES_INT 12 863#define AU1200_AES_INT 12
594#define AU1200_CAMERA_INT 13 864#define AU1200_CAMERA_INT 13
595#define AU1200_TOY_INT 14 865#define AU1000_TOY_INT 14
596#define AU1200_TOY_MATCH0_INT 15 866#define AU1000_TOY_MATCH0_INT 15
597#define AU1200_TOY_MATCH1_INT 16 867#define AU1000_TOY_MATCH1_INT 16
598#define AU1200_TOY_MATCH2_INT 17 868#define AU1000_TOY_MATCH2_INT 17
599#define AU1200_RTC_INT 18 869#define AU1000_RTC_INT 18
600#define AU1200_RTC_MATCH0_INT 19 870#define AU1000_RTC_MATCH0_INT 19
601#define AU1200_RTC_MATCH1_INT 20 871#define AU1000_RTC_MATCH1_INT 20
602#define AU1200_RTC_MATCH2_INT 21 872#define AU1000_RTC_MATCH2_INT 21
603#define AU1200_NAND_INT 23 873#define AU1200_NAND_INT 23
604#define AU1200_GPIO_204 24 874#define AU1200_GPIO_204 24
605#define AU1200_GPIO_205 25 875#define AU1200_GPIO_205 25
@@ -607,6 +877,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
607#define AU1200_GPIO_207 27 877#define AU1200_GPIO_207 27
608#define AU1200_GPIO_208_215 28 // Logical OR of 208:215 878#define AU1200_GPIO_208_215 28 // Logical OR of 208:215
609#define AU1200_USB_INT 29 879#define AU1200_USB_INT 29
880#define AU1000_USB_HOST_INT AU1200_USB_INT
610#define AU1200_LCD_INT 30 881#define AU1200_LCD_INT 30
611#define AU1200_MAE_BOTH_INT 31 882#define AU1200_MAE_BOTH_INT 31
612#define AU1000_GPIO_0 32 883#define AU1000_GPIO_0 32
@@ -645,20 +916,36 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
645#define UART0_ADDR 0xB1100000 916#define UART0_ADDR 0xB1100000
646#define UART1_ADDR 0xB1200000 917#define UART1_ADDR 0xB1200000
647 918
648#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap 919#define USB_UOC_BASE 0x14020020
649#define USB_HOST_CONFIG 0xB4027ffc 920#define USB_UOC_LEN 0x20
650 921#define USB_OHCI_BASE 0x14020100
651// these are here for prototyping on au1550 (do not exist on au1200) 922#define USB_OHCI_LEN 0x100
652#define AU1200_ETH0_BASE 0xB0500000 923#define USB_EHCI_BASE 0x14020200
653#define AU1200_ETH1_BASE 0xB0510000 924#define USB_EHCI_LEN 0x100
654#define AU1200_MAC0_ENABLE 0xB0520000 925#define USB_UDC_BASE 0x14022000
655#define AU1200_MAC1_ENABLE 0xB0520004 926#define USB_UDC_LEN 0x2000
656#define NUM_ETH_INTERFACES 2 927#define USB_MSR_BASE 0xB4020000
657#endif // CONFIG_SOC_AU1200 928#define USB_MSR_MCFG 4
929#define USBMSRMCFG_OMEMEN 0
930#define USBMSRMCFG_OBMEN 1
931#define USBMSRMCFG_EMEMEN 2
932#define USBMSRMCFG_EBMEN 3
933#define USBMSRMCFG_DMEMEN 4
934#define USBMSRMCFG_DBMEN 5
935#define USBMSRMCFG_GMEMEN 6
936#define USBMSRMCFG_OHCCLKEN 16
937#define USBMSRMCFG_EHCCLKEN 17
938#define USBMSRMCFG_UDCCLKEN 18
939#define USBMSRMCFG_PHYPLLEN 19
940#define USBMSRMCFG_RDCOMB 30
941#define USBMSRMCFG_PFEN 31
942
943#endif /* CONFIG_SOC_AU1200 */
658 944
659#define AU1000_LAST_INTC0_INT 31 945#define AU1000_LAST_INTC0_INT 31
946#define AU1000_LAST_INTC1_INT 63
660#define AU1000_MAX_INTR 63 947#define AU1000_MAX_INTR 63
661 948#define INTX 0xFF /* not valid */
662 949
663/* Programmable Counters 0 and 1 */ 950/* Programmable Counters 0 and 1 */
664#define SYS_BASE 0xB1900000 951#define SYS_BASE 0xB1900000
@@ -730,6 +1017,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
730 #define I2S_CONTROL_D (1<<1) 1017 #define I2S_CONTROL_D (1<<1)
731 #define I2S_CONTROL_CE (1<<0) 1018 #define I2S_CONTROL_CE (1<<0)
732 1019
1020#ifndef CONFIG_SOC_AU1200
1021
733/* USB Host Controller */ 1022/* USB Host Controller */
734#define USB_OHCI_LEN 0x00100000 1023#define USB_OHCI_LEN 0x00100000
735 1024
@@ -775,6 +1064,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
775 #define USBDEV_ENABLE (1<<1) 1064 #define USBDEV_ENABLE (1<<1)
776 #define USBDEV_CE (1<<0) 1065 #define USBDEV_CE (1<<0)
777 1066
1067#endif /* !CONFIG_SOC_AU1200 */
1068
778/* Ethernet Controllers */ 1069/* Ethernet Controllers */
779 1070
780/* 4 byte offsets from AU1000_ETH_BASE */ 1071/* 4 byte offsets from AU1000_ETH_BASE */
@@ -1173,6 +1464,37 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1173 #define SYS_PF_PSC1_S1 (1 << 1) 1464 #define SYS_PF_PSC1_S1 (1 << 1)
1174 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1465 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1175 1466
1467/* Au1200 Only */
1468#ifdef CONFIG_SOC_AU1200
1469#define SYS_PINFUNC_DMA (1<<31)
1470#define SYS_PINFUNC_S0A (1<<30)
1471#define SYS_PINFUNC_S1A (1<<29)
1472#define SYS_PINFUNC_LP0 (1<<28)
1473#define SYS_PINFUNC_LP1 (1<<27)
1474#define SYS_PINFUNC_LD16 (1<<26)
1475#define SYS_PINFUNC_LD8 (1<<25)
1476#define SYS_PINFUNC_LD1 (1<<24)
1477#define SYS_PINFUNC_LD0 (1<<23)
1478#define SYS_PINFUNC_P1A (3<<21)
1479#define SYS_PINFUNC_P1B (1<<20)
1480#define SYS_PINFUNC_FS3 (1<<19)
1481#define SYS_PINFUNC_P0A (3<<17)
1482#define SYS_PINFUNC_CS (1<<16)
1483#define SYS_PINFUNC_CIM (1<<15)
1484#define SYS_PINFUNC_P1C (1<<14)
1485#define SYS_PINFUNC_U1T (1<<12)
1486#define SYS_PINFUNC_U1R (1<<11)
1487#define SYS_PINFUNC_EX1 (1<<10)
1488#define SYS_PINFUNC_EX0 (1<<9)
1489#define SYS_PINFUNC_U0R (1<<8)
1490#define SYS_PINFUNC_MC (1<<7)
1491#define SYS_PINFUNC_S0B (1<<6)
1492#define SYS_PINFUNC_S0C (1<<5)
1493#define SYS_PINFUNC_P0B (1<<4)
1494#define SYS_PINFUNC_U0T (1<<3)
1495#define SYS_PINFUNC_S1B (1<<2)
1496#endif
1497
1176#define SYS_TRIOUTRD 0xB1900100 1498#define SYS_TRIOUTRD 0xB1900100
1177#define SYS_TRIOUTCLR 0xB1900100 1499#define SYS_TRIOUTCLR 0xB1900100
1178#define SYS_OUTPUTRD 0xB1900108 1500#define SYS_OUTPUTRD 0xB1900108
@@ -1239,6 +1561,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1239 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) 1561 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
1240 #define SYS_CS_DI2 (1<<16) 1562 #define SYS_CS_DI2 (1<<16)
1241 #define SYS_CS_CI2 (1<<15) 1563 #define SYS_CS_CI2 (1<<15)
1564#ifdef CONFIG_SOC_AU1100
1565 #define SYS_CS_ML_BIT 7
1566 #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
1567 #define SYS_CS_DL (1<<6)
1568 #define SYS_CS_CL (1<<5)
1569#else
1242 #define SYS_CS_MUH_BIT 12 1570 #define SYS_CS_MUH_BIT 12
1243 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) 1571 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
1244 #define SYS_CS_DUH (1<<11) 1572 #define SYS_CS_DUH (1<<11)
@@ -1247,6 +1575,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1247 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) 1575 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
1248 #define SYS_CS_DUD (1<<6) 1576 #define SYS_CS_DUD (1<<6)
1249 #define SYS_CS_CUD (1<<5) 1577 #define SYS_CS_CUD (1<<5)
1578#endif
1250 #define SYS_CS_MIR_BIT 2 1579 #define SYS_CS_MIR_BIT 2
1251 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) 1580 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
1252 #define SYS_CS_DIR (1<<1) 1581 #define SYS_CS_DIR (1<<1)
@@ -1300,7 +1629,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1300#define SD1_XMIT_FIFO 0xB0680000 1629#define SD1_XMIT_FIFO 0xB0680000
1301#define SD1_RECV_FIFO 0xB0680004 1630#define SD1_RECV_FIFO 0xB0680004
1302 1631
1303
1304#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1632#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1305/* Au1500 PCI Controller */ 1633/* Au1500 PCI Controller */
1306#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr 1634#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
@@ -1363,36 +1691,77 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1363 _ctl_; }) 1691 _ctl_; })
1364 1692
1365 1693
1366#else /* Au1000 and Au1100 */ 1694#else /* Au1000 and Au1100 and Au1200 */
1367 1695
1368/* don't allow any legacy ports probing */ 1696/* don't allow any legacy ports probing */
1369#define IOPORT_RESOURCE_START 0x10000000; 1697#define IOPORT_RESOURCE_START 0x10000000
1370#define IOPORT_RESOURCE_END 0xffffffff 1698#define IOPORT_RESOURCE_END 0xffffffff
1371#define IOMEM_RESOURCE_START 0x10000000 1699#define IOMEM_RESOURCE_START 0x10000000
1372#define IOMEM_RESOURCE_END 0xffffffff 1700#define IOMEM_RESOURCE_END 0xffffffff
1373 1701
1374#ifdef CONFIG_MIPS_PB1000
1375#define PCI_IO_START 0x10000000
1376#define PCI_IO_END 0x1000ffff
1377#define PCI_MEM_START 0x18000000
1378#define PCI_MEM_END 0x18ffffff
1379#define PCI_FIRST_DEVFN 0
1380#define PCI_LAST_DEVFN 1
1381#else
1382/* no PCI bus controller */
1383#define PCI_IO_START 0 1702#define PCI_IO_START 0
1384#define PCI_IO_END 0 1703#define PCI_IO_END 0
1385#define PCI_MEM_START 0 1704#define PCI_MEM_START 0
1386#define PCI_MEM_END 0 1705#define PCI_MEM_END 0
1387#define PCI_FIRST_DEVFN 0 1706#define PCI_FIRST_DEVFN 0
1388#define PCI_LAST_DEVFN 0 1707#define PCI_LAST_DEVFN 0
1389#endif
1390 1708
1391#endif 1709#endif
1392 1710
1711#ifndef _LANGUAGE_ASSEMBLY
1712typedef volatile struct
1713{
1714 /* 0x0000 */ u32 toytrim;
1715 /* 0x0004 */ u32 toywrite;
1716 /* 0x0008 */ u32 toymatch0;
1717 /* 0x000C */ u32 toymatch1;
1718 /* 0x0010 */ u32 toymatch2;
1719 /* 0x0014 */ u32 cntrctrl;
1720 /* 0x0018 */ u32 scratch0;
1721 /* 0x001C */ u32 scratch1;
1722 /* 0x0020 */ u32 freqctrl0;
1723 /* 0x0024 */ u32 freqctrl1;
1724 /* 0x0028 */ u32 clksrc;
1725 /* 0x002C */ u32 pinfunc;
1726 /* 0x0030 */ u32 reserved0;
1727 /* 0x0034 */ u32 wakemsk;
1728 /* 0x0038 */ u32 endian;
1729 /* 0x003C */ u32 powerctrl;
1730 /* 0x0040 */ u32 toyread;
1731 /* 0x0044 */ u32 rtctrim;
1732 /* 0x0048 */ u32 rtcwrite;
1733 /* 0x004C */ u32 rtcmatch0;
1734 /* 0x0050 */ u32 rtcmatch1;
1735 /* 0x0054 */ u32 rtcmatch2;
1736 /* 0x0058 */ u32 rtcread;
1737 /* 0x005C */ u32 wakesrc;
1738 /* 0x0060 */ u32 cpupll;
1739 /* 0x0064 */ u32 auxpll;
1740 /* 0x0068 */ u32 reserved1;
1741 /* 0x006C */ u32 reserved2;
1742 /* 0x0070 */ u32 reserved3;
1743 /* 0x0074 */ u32 reserved4;
1744 /* 0x0078 */ u32 slppwr;
1745 /* 0x007C */ u32 sleep;
1746 /* 0x0080 */ u32 reserved5[32];
1747 /* 0x0100 */ u32 trioutrd;
1748#define trioutclr trioutrd
1749 /* 0x0104 */ u32 reserved6;
1750 /* 0x0108 */ u32 outputrd;
1751#define outputset outputrd
1752 /* 0x010C */ u32 outputclr;
1753 /* 0x0110 */ u32 pinstaterd;
1754#define pininputen pinstaterd
1755
1756} AU1X00_SYS;
1757
1758static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE;
1759
1760#endif
1393/* Processor information base on prid. 1761/* Processor information base on prid.
1394 * Copied from PowerPC. 1762 * Copied from PowerPC.
1395 */ 1763 */
1764#ifndef _LANGUAGE_ASSEMBLY
1396struct cpu_spec { 1765struct cpu_spec {
1397 /* CPU is matched via (PRID & prid_mask) == prid_value */ 1766 /* CPU is matched via (PRID & prid_mask) == prid_value */
1398 unsigned int prid_mask; 1767 unsigned int prid_mask;
@@ -1406,3 +1775,6 @@ struct cpu_spec {
1406extern struct cpu_spec cpu_specs[]; 1775extern struct cpu_spec cpu_specs[];
1407extern struct cpu_spec *cur_cpu_spec[]; 1776extern struct cpu_spec *cur_cpu_spec[];
1408#endif 1777#endif
1778
1779#endif
1780
diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/include/asm-mips/mach-au1x00/au1xxx.h
new file mode 100644
index 000000000000..b7b46dd9b929
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1xxx.h
@@ -0,0 +1,44 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _AU1XXX_H_
24#define _AU1XXX_H_
25
26#include <linux/config.h>
27
28#include <asm/mach-au1x00/au1000.h>
29
30#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
31#include <asm/mach-db1x00/db1x00.h>
32
33#elif defined(CONFIG_MIPS_PB1550)
34#include <asm/mach-pb1x00/pb1550.h>
35
36#elif defined(CONFIG_MIPS_PB1200)
37#include <asm/mach-pb1x00/pb1200.h>
38
39#elif defined(CONFIG_MIPS_DB1200)
40#include <asm/mach-db1x00/db1200.h>
41
42#endif
43
44#endif /* _AU1XXX_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
index d5eb88cd7d51..b327bcd3fee1 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -45,7 +45,7 @@
45#define DDMA_GLOBAL_BASE 0xb4003000 45#define DDMA_GLOBAL_BASE 0xb4003000
46#define DDMA_CHANNEL_BASE 0xb4002000 46#define DDMA_CHANNEL_BASE 0xb4002000
47 47
48typedef struct dbdma_global { 48typedef volatile struct dbdma_global {
49 u32 ddma_config; 49 u32 ddma_config;
50 u32 ddma_intstat; 50 u32 ddma_intstat;
51 u32 ddma_throttle; 51 u32 ddma_throttle;
@@ -62,7 +62,7 @@ typedef struct dbdma_global {
62 62
63/* The structure of a DMA Channel. 63/* The structure of a DMA Channel.
64*/ 64*/
65typedef struct au1xxx_dma_channel { 65typedef volatile struct au1xxx_dma_channel {
66 u32 ddma_cfg; /* See below */ 66 u32 ddma_cfg; /* See below */
67 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */ 67 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
68 u32 ddma_statptr; /* word aligned pointer to status word */ 68 u32 ddma_statptr; /* word aligned pointer to status word */
@@ -98,7 +98,7 @@ typedef struct au1xxx_dma_channel {
98/* "Standard" DDMA Descriptor. 98/* "Standard" DDMA Descriptor.
99 * Must be 32-byte aligned. 99 * Must be 32-byte aligned.
100 */ 100 */
101typedef struct au1xxx_ddma_desc { 101typedef volatile struct au1xxx_ddma_desc {
102 u32 dscr_cmd0; /* See below */ 102 u32 dscr_cmd0; /* See below */
103 u32 dscr_cmd1; /* See below */ 103 u32 dscr_cmd1; /* See below */
104 u32 dscr_source0; /* source phys address */ 104 u32 dscr_source0; /* source phys address */
@@ -107,6 +107,12 @@ typedef struct au1xxx_ddma_desc {
107 u32 dscr_dest1; /* See below */ 107 u32 dscr_dest1; /* See below */
108 u32 dscr_stat; /* completion status */ 108 u32 dscr_stat; /* completion status */
109 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ 109 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
110 /* First 32bytes are HW specific!!!
111 Lets have some SW data following.. make sure its 32bytes
112 */
113 u32 sw_status;
114 u32 sw_context;
115 u32 sw_reserved[6];
110} au1x_ddma_desc_t; 116} au1x_ddma_desc_t;
111 117
112#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */ 118#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */
@@ -125,8 +131,11 @@ typedef struct au1xxx_ddma_desc {
125#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ 131#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
126#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ 132#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
127 133
134#define SW_STATUS_INUSE (1<<0)
135
128/* Command 0 device IDs. 136/* Command 0 device IDs.
129*/ 137*/
138#ifdef CONFIG_SOC_AU1550
130#define DSCR_CMD0_UART0_TX 0 139#define DSCR_CMD0_UART0_TX 0
131#define DSCR_CMD0_UART0_RX 1 140#define DSCR_CMD0_UART0_RX 1
132#define DSCR_CMD0_UART3_TX 2 141#define DSCR_CMD0_UART3_TX 2
@@ -155,9 +164,45 @@ typedef struct au1xxx_ddma_desc {
155#define DSCR_CMD0_MAC0_TX 25 164#define DSCR_CMD0_MAC0_TX 25
156#define DSCR_CMD0_MAC1_RX 26 165#define DSCR_CMD0_MAC1_RX 26
157#define DSCR_CMD0_MAC1_TX 27 166#define DSCR_CMD0_MAC1_TX 27
167#endif /* CONFIG_SOC_AU1550 */
168
169#ifdef CONFIG_SOC_AU1200
170#define DSCR_CMD0_UART0_TX 0
171#define DSCR_CMD0_UART0_RX 1
172#define DSCR_CMD0_UART1_TX 2
173#define DSCR_CMD0_UART1_RX 3
174#define DSCR_CMD0_DMA_REQ0 4
175#define DSCR_CMD0_DMA_REQ1 5
176#define DSCR_CMD0_MAE_BE 6
177#define DSCR_CMD0_MAE_FE 7
178#define DSCR_CMD0_SDMS_TX0 8
179#define DSCR_CMD0_SDMS_RX0 9
180#define DSCR_CMD0_SDMS_TX1 10
181#define DSCR_CMD0_SDMS_RX1 11
182#define DSCR_CMD0_AES_TX 13
183#define DSCR_CMD0_AES_RX 12
184#define DSCR_CMD0_PSC0_TX 14
185#define DSCR_CMD0_PSC0_RX 15
186#define DSCR_CMD0_PSC1_TX 16
187#define DSCR_CMD0_PSC1_RX 17
188#define DSCR_CMD0_CIM_RXA 18
189#define DSCR_CMD0_CIM_RXB 19
190#define DSCR_CMD0_CIM_RXC 20
191#define DSCR_CMD0_MAE_BOTH 21
192#define DSCR_CMD0_LCD 22
193#define DSCR_CMD0_NAND_FLASH 23
194#define DSCR_CMD0_PSC0_SYNC 24
195#define DSCR_CMD0_PSC1_SYNC 25
196#define DSCR_CMD0_CIM_SYNC 26
197#endif /* CONFIG_SOC_AU1200 */
198
158#define DSCR_CMD0_THROTTLE 30 199#define DSCR_CMD0_THROTTLE 30
159#define DSCR_CMD0_ALWAYS 31 200#define DSCR_CMD0_ALWAYS 31
160#define DSCR_NDEV_IDS 32 201#define DSCR_NDEV_IDS 32
202/* THis macro is used to find/create custom device types */
203#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
204#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
205
161 206
162#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) 207#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
163#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) 208#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
@@ -246,6 +291,43 @@ typedef struct au1xxx_ddma_desc {
246*/ 291*/
247#define NUM_DBDMA_CHANS 16 292#define NUM_DBDMA_CHANS 16
248 293
294/*
295 * Ddma API definitions
296 * FIXME: may not fit to this header file
297 */
298typedef struct dbdma_device_table {
299 u32 dev_id;
300 u32 dev_flags;
301 u32 dev_tsize;
302 u32 dev_devwidth;
303 u32 dev_physaddr; /* If FIFO */
304 u32 dev_intlevel;
305 u32 dev_intpolarity;
306} dbdev_tab_t;
307
308
309typedef struct dbdma_chan_config {
310 spinlock_t lock;
311
312 u32 chan_flags;
313 u32 chan_index;
314 dbdev_tab_t *chan_src;
315 dbdev_tab_t *chan_dest;
316 au1x_dma_chan_t *chan_ptr;
317 au1x_ddma_desc_t *chan_desc_base;
318 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
319 void *chan_callparam;
320 void (*chan_callback)(int, void *, struct pt_regs *);
321} chan_tab_t;
322
323#define DEV_FLAGS_INUSE (1 << 0)
324#define DEV_FLAGS_ANYUSE (1 << 1)
325#define DEV_FLAGS_OUT (1 << 2)
326#define DEV_FLAGS_IN (1 << 3)
327#define DEV_FLAGS_BURSTABLE (1 << 4)
328#define DEV_FLAGS_SYNC (1 << 5)
329/* end Ddma API definitions */
330
249/* External functions for drivers to use. 331/* External functions for drivers to use.
250*/ 332*/
251/* Use this to allocate a dbdma channel. The device ids are one of the 333/* Use this to allocate a dbdma channel. The device ids are one of the
@@ -258,18 +340,6 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
258 340
259#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS 341#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
260 342
261/* ACK! These should be in a board specific description file.
262*/
263#ifdef CONFIG_MIPS_PB1550
264#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
265#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
266#endif
267#ifdef CONFIG_MIPS_DB1550
268#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
269#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
270#endif
271
272
273/* Set the device width of a in/out fifo. 343/* Set the device width of a in/out fifo.
274*/ 344*/
275u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); 345u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
@@ -280,8 +350,8 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
280 350
281/* Put buffers on source/destination descriptors. 351/* Put buffers on source/destination descriptors.
282*/ 352*/
283u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes); 353u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
284u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes); 354u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
285 355
286/* Get a buffer from the destination descriptor. 356/* Get a buffer from the destination descriptor.
287*/ 357*/
@@ -295,5 +365,29 @@ u32 au1xxx_get_dma_residue(u32 chanid);
295void au1xxx_dbdma_chan_free(u32 chanid); 365void au1xxx_dbdma_chan_free(u32 chanid);
296void au1xxx_dbdma_dump(u32 chanid); 366void au1xxx_dbdma_dump(u32 chanid);
297 367
368u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
369
370u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
371void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
372
373/*
374 Some compatibilty macros --
375 Needed to make changes to API without breaking existing drivers
376*/
377#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
378#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
379#define put_source_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags)
380
381
382#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
383#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
384#define put_dest_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags)
385
386/*
387 * Flags for the put_source/put_dest functions.
388 */
389#define DDMA_FLAGS_IE (1<<0)
390#define DDMA_FLAGS_NOIE (1<<1)
391
298#endif /* _LANGUAGE_ASSEMBLY */ 392#endif /* _LANGUAGE_ASSEMBLY */
299#endif /* _AU1000_DBDMA_H_ */ 393#endif /* _AU1000_DBDMA_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_gpio.h b/include/asm-mips/mach-au1x00/au1xxx_gpio.h
new file mode 100644
index 000000000000..27911e054ffc
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1xxx_gpio.h
@@ -0,0 +1,20 @@
1#ifndef __AU1XXX_GPIO_H
2#define __AU1XXX_GPIO_H
3
4void au1xxx_gpio1_set_inputs(void);
5void au1xxx_gpio_tristate(int signal);
6void au1xxx_gpio_write(int signal, int value);
7int au1xxx_gpio_read(int signal);
8
9typedef volatile struct
10{
11 u32 dir;
12 u32 reserved;
13 u32 output;
14 u32 pinstate;
15 u32 inten;
16 u32 enable;
17
18} AU1X00_GPIO2;
19
20#endif //__AU1XXX_GPIO_H
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
new file mode 100644
index 000000000000..33d275c3b84c
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h
@@ -0,0 +1,301 @@
1/*
2 * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005
3 *
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
6 *
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
8 *
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
12 * version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
31 */
32#include <linux/config.h>
33
34#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
35 #define DMA_WAIT_TIMEOUT 100
36 #define NUM_DESCRIPTORS PRD_ENTRIES
37#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
38 #define NUM_DESCRIPTORS 2
39#endif
40
41#ifndef AU1XXX_ATA_RQSIZE
42 #define AU1XXX_ATA_RQSIZE 128
43#endif
44
45/* Disable Burstable-Support for DBDMA */
46#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
47 #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
48#endif
49
50#ifdef CONFIG_PM
51/*
52* This will enable the device to be powered up when write() or read()
53* is called. If this is not defined, the driver will return -EBUSY.
54*/
55#define WAKE_ON_ACCESS 1
56
57typedef struct
58{
59 spinlock_t lock; /* Used to block on state transitions */
60 au1xxx_power_dev_t *dev; /* Power Managers device structure */
61 unsigned stopped; /* USed to signaling device is stopped */
62} pm_state;
63#endif
64
65
66typedef struct
67{
68 u32 tx_dev_id, rx_dev_id, target_dev_id;
69 u32 tx_chan, rx_chan;
70 void *tx_desc_head, *rx_desc_head;
71 ide_hwif_t *hwif;
72#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
73 ide_drive_t *drive;
74 u8 white_list, black_list;
75 struct dbdma_cmd *dma_table_cpu;
76 dma_addr_t dma_table_dma;
77 struct scatterlist *sg_table;
78 int sg_nents;
79 int sg_dma_direction;
80#endif
81 struct device *dev;
82 int irq;
83 u32 regbase;
84#ifdef CONFIG_PM
85 pm_state pm;
86#endif
87} _auide_hwif;
88
89#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
90struct drive_list_entry {
91 const char * id_model;
92 const char * id_firmware;
93};
94
95/* HD white list */
96static const struct drive_list_entry dma_white_list [] = {
97/*
98 * Hitachi
99 */
100 { "HITACHI_DK14FA-20" , "ALL" },
101 { "HTS726060M9AT00" , "ALL" },
102/*
103 * Maxtor
104 */
105 { "Maxtor 6E040L0" , "ALL" },
106 { "Maxtor 6Y080P0" , "ALL" },
107 { "Maxtor 6Y160P0" , "ALL" },
108/*
109 * Seagate
110 */
111 { "ST3120026A" , "ALL" },
112 { "ST320014A" , "ALL" },
113 { "ST94011A" , "ALL" },
114 { "ST340016A" , "ALL" },
115/*
116 * Western Digital
117 */
118 { "WDC WD400UE-00HCT0" , "ALL" },
119 { "WDC WD400JB-00JJC0" , "ALL" },
120 { NULL , NULL }
121};
122
123/* HD black list */
124static const struct drive_list_entry dma_black_list [] = {
125/*
126 * Western Digital
127 */
128 { "WDC WD100EB-00CGH0" , "ALL" },
129 { "WDC WD200BB-00AUA1" , "ALL" },
130 { "WDC AC24300L" , "ALL" },
131 { NULL , NULL }
132};
133#endif
134
135/* function prototyping */
136u8 auide_inb(unsigned long port);
137u16 auide_inw(unsigned long port);
138u32 auide_inl(unsigned long port);
139void auide_insw(unsigned long port, void *addr, u32 count);
140void auide_insl(unsigned long port, void *addr, u32 count);
141void auide_outb(u8 addr, unsigned long port);
142void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port);
143void auide_outw(u16 addr, unsigned long port);
144void auide_outl(u32 addr, unsigned long port);
145void auide_outsw(unsigned long port, void *addr, u32 count);
146void auide_outsl(unsigned long port, void *addr, u32 count);
147static void auide_tune_drive(ide_drive_t *drive, byte pio);
148static int auide_tune_chipset (ide_drive_t *drive, u8 speed);
149static int auide_ddma_init( _auide_hwif *auide );
150static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif);
151int __init auide_probe(void);
152
153#ifdef CONFIG_PM
154 int au1200ide_pm_callback( au1xxx_power_dev_t *dev,
155 au1xxx_request_t request, void *data);
156 static int au1xxxide_pm_standby( au1xxx_power_dev_t *dev );
157 static int au1xxxide_pm_sleep( au1xxx_power_dev_t *dev );
158 static int au1xxxide_pm_resume( au1xxx_power_dev_t *dev );
159 static int au1xxxide_pm_getstatus( au1xxx_power_dev_t *dev );
160 static int au1xxxide_pm_access( au1xxx_power_dev_t *dev );
161 static int au1xxxide_pm_idle( au1xxx_power_dev_t *dev );
162 static int au1xxxide_pm_cleanup( au1xxx_power_dev_t *dev );
163#endif
164
165
166/*
167 * Multi-Word DMA + DbDMA functions
168 */
169#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
170
171 static int in_drive_list(struct hd_driveid *id,
172 const struct drive_list_entry *drive_table);
173 static int auide_build_sglist(ide_drive_t *drive, struct request *rq);
174 static int auide_build_dmatable(ide_drive_t *drive);
175 static int auide_dma_end(ide_drive_t *drive);
176 static void auide_dma_start(ide_drive_t *drive );
177 ide_startstop_t auide_dma_intr (ide_drive_t *drive);
178 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command);
179 static int auide_dma_setup(ide_drive_t *drive);
180 static int auide_dma_check(ide_drive_t *drive);
181 static int auide_dma_test_irq(ide_drive_t *drive);
182 static int auide_dma_host_off(ide_drive_t *drive);
183 static int auide_dma_host_on(ide_drive_t *drive);
184 static int auide_dma_lostirq(ide_drive_t *drive);
185 static int auide_dma_on(ide_drive_t *drive);
186 static void auide_ddma_tx_callback(int irq, void *param,
187 struct pt_regs *regs);
188 static void auide_ddma_rx_callback(int irq, void *param,
189 struct pt_regs *regs);
190 static int auide_dma_off_quietly(ide_drive_t *drive);
191 static int auide_dma_timeout(ide_drive_t *drive);
192
193#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
194
195/*******************************************************************************
196* PIO Mode timing calculation : *
197* *
198* Static Bus Spec ATA Spec *
199* Tcsoe = t1 *
200* Toecs = t9 *
201* Twcs = t9 *
202* Tcsh = t2i | t2 *
203* Tcsoff = t2i | t2 *
204* Twp = t2 *
205* Tcsw = t1 *
206* Tpm = 0 *
207* Ta = t1+t2 *
208*******************************************************************************/
209
210#define TCSOE_MASK (0x07<<29)
211#define TOECS_MASK (0x07<<26)
212#define TWCS_MASK (0x07<<28)
213#define TCSH_MASK (0x0F<<24)
214#define TCSOFF_MASK (0x07<<20)
215#define TWP_MASK (0x3F<<14)
216#define TCSW_MASK (0x0F<<10)
217#define TPM_MASK (0x0F<<6)
218#define TA_MASK (0x3F<<0)
219#define TS_MASK (1<<8)
220
221/* Timing parameters PIO mode 0 */
222#define SBC_IDE_PIO0_TCSOE (0x04<<29)
223#define SBC_IDE_PIO0_TOECS (0x01<<26)
224#define SBC_IDE_PIO0_TWCS (0x02<<28)
225#define SBC_IDE_PIO0_TCSH (0x08<<24)
226#define SBC_IDE_PIO0_TCSOFF (0x07<<20)
227#define SBC_IDE_PIO0_TWP (0x10<<14)
228#define SBC_IDE_PIO0_TCSW (0x04<<10)
229#define SBC_IDE_PIO0_TPM (0x0<<6)
230#define SBC_IDE_PIO0_TA (0x15<<0)
231/* Timing parameters PIO mode 1 */
232#define SBC_IDE_PIO1_TCSOE (0x03<<29)
233#define SBC_IDE_PIO1_TOECS (0x01<<26)
234#define SBC_IDE_PIO1_TWCS (0x01<<28)
235#define SBC_IDE_PIO1_TCSH (0x06<<24)
236#define SBC_IDE_PIO1_TCSOFF (0x06<<20)
237#define SBC_IDE_PIO1_TWP (0x08<<14)
238#define SBC_IDE_PIO1_TCSW (0x03<<10)
239#define SBC_IDE_PIO1_TPM (0x00<<6)
240#define SBC_IDE_PIO1_TA (0x0B<<0)
241/* Timing parameters PIO mode 2 */
242#define SBC_IDE_PIO2_TCSOE (0x05<<29)
243#define SBC_IDE_PIO2_TOECS (0x01<<26)
244#define SBC_IDE_PIO2_TWCS (0x01<<28)
245#define SBC_IDE_PIO2_TCSH (0x07<<24)
246#define SBC_IDE_PIO2_TCSOFF (0x07<<20)
247#define SBC_IDE_PIO2_TWP (0x1F<<14)
248#define SBC_IDE_PIO2_TCSW (0x05<<10)
249#define SBC_IDE_PIO2_TPM (0x00<<6)
250#define SBC_IDE_PIO2_TA (0x22<<0)
251/* Timing parameters PIO mode 3 */
252#define SBC_IDE_PIO3_TCSOE (0x05<<29)
253#define SBC_IDE_PIO3_TOECS (0x01<<26)
254#define SBC_IDE_PIO3_TWCS (0x01<<28)
255#define SBC_IDE_PIO3_TCSH (0x0D<<24)
256#define SBC_IDE_PIO3_TCSOFF (0x0D<<20)
257#define SBC_IDE_PIO3_TWP (0x15<<14)
258#define SBC_IDE_PIO3_TCSW (0x05<<10)
259#define SBC_IDE_PIO3_TPM (0x00<<6)
260#define SBC_IDE_PIO3_TA (0x1A<<0)
261/* Timing parameters PIO mode 4 */
262#define SBC_IDE_PIO4_TCSOE (0x04<<29)
263#define SBC_IDE_PIO4_TOECS (0x01<<26)
264#define SBC_IDE_PIO4_TWCS (0x01<<28)
265#define SBC_IDE_PIO4_TCSH (0x04<<24)
266#define SBC_IDE_PIO4_TCSOFF (0x04<<20)
267#define SBC_IDE_PIO4_TWP (0x0D<<14)
268#define SBC_IDE_PIO4_TCSW (0x03<<10)
269#define SBC_IDE_PIO4_TPM (0x00<<6)
270#define SBC_IDE_PIO4_TA (0x12<<0)
271/* Timing parameters MDMA mode 0 */
272#define SBC_IDE_MDMA0_TCSOE (0x03<<29)
273#define SBC_IDE_MDMA0_TOECS (0x01<<26)
274#define SBC_IDE_MDMA0_TWCS (0x01<<28)
275#define SBC_IDE_MDMA0_TCSH (0x07<<24)
276#define SBC_IDE_MDMA0_TCSOFF (0x07<<20)
277#define SBC_IDE_MDMA0_TWP (0x0C<<14)
278#define SBC_IDE_MDMA0_TCSW (0x03<<10)
279#define SBC_IDE_MDMA0_TPM (0x00<<6)
280#define SBC_IDE_MDMA0_TA (0x0F<<0)
281/* Timing parameters MDMA mode 1 */
282#define SBC_IDE_MDMA1_TCSOE (0x05<<29)
283#define SBC_IDE_MDMA1_TOECS (0x01<<26)
284#define SBC_IDE_MDMA1_TWCS (0x01<<28)
285#define SBC_IDE_MDMA1_TCSH (0x05<<24)
286#define SBC_IDE_MDMA1_TCSOFF (0x05<<20)
287#define SBC_IDE_MDMA1_TWP (0x0F<<14)
288#define SBC_IDE_MDMA1_TCSW (0x05<<10)
289#define SBC_IDE_MDMA1_TPM (0x00<<6)
290#define SBC_IDE_MDMA1_TA (0x15<<0)
291/* Timing parameters MDMA mode 2 */
292#define SBC_IDE_MDMA2_TCSOE (0x04<<29)
293#define SBC_IDE_MDMA2_TOECS (0x01<<26)
294#define SBC_IDE_MDMA2_TWCS (0x01<<28)
295#define SBC_IDE_MDMA2_TCSH (0x04<<24)
296#define SBC_IDE_MDMA2_TCSOFF (0x04<<20)
297#define SBC_IDE_MDMA2_TWP (0x0D<<14)
298#define SBC_IDE_MDMA2_TCSW (0x04<<10)
299#define SBC_IDE_MDMA2_TPM (0x00<<6)
300#define SBC_IDE_MDMA2_TA (0x12<<0)
301
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
index 283519dfdec4..8e5fb3c7da4d 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h
@@ -33,6 +33,8 @@
33#ifndef _AU1000_PSC_H_ 33#ifndef _AU1000_PSC_H_
34#define _AU1000_PSC_H_ 34#define _AU1000_PSC_H_
35 35
36#include <linux/config.h>
37
36/* The PSC base addresses. */ 38/* The PSC base addresses. */
37#ifdef CONFIG_SOC_AU1550 39#ifdef CONFIG_SOC_AU1550
38#define PSC0_BASE_ADDR 0xb1a00000 40#define PSC0_BASE_ADDR 0xb1a00000
diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h
new file mode 100644
index 000000000000..d3ec6274575a
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/ioremap.h
@@ -0,0 +1,32 @@
1/*
2 * include/asm-mips/mach-au1x00/ioremap.h
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifndef __ASM_MACH_AU1X00_IOREMAP_H
10#define __ASM_MACH_AU1X00_IOREMAP_H
11
12#include <linux/config.h>
13#include <linux/types.h>
14
15#ifdef CONFIG_64BIT_PHYS_ADDR
16extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
17#else
18static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
19{
20 return phys_addr;
21}
22#endif
23
24/*
25 * Allow physical addresses to be fixed up to help 36-bit peripherals.
26 */
27static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
28{
29 return __fixup_bigphys_addr(phys_addr, size);
30}
31
32#endif /* __ASM_MACH_AU1X00_IOREMAP_H */
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
new file mode 100644
index 000000000000..5d894376fc1a
--- /dev/null
+++ b/include/asm-mips/mach-db1x00/db1200.h
@@ -0,0 +1,224 @@
1/*
2 * AMD Alchemy DB1200 Referrence Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_DB1200_H
25#define __ASM_DB1200_H
26
27#include <linux/types.h>
28
29// This is defined in au1000.h with bogus value
30#undef AU1X00_EXTERNAL_INT
31
32#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
34#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
35#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
36
37/* SPI and SMB are muxed on the Pb1200 board.
38 Refer to board documentation.
39 */
40#define SPI_PSC_BASE PSC0_BASE_ADDR
41#define SMBUS_PSC_BASE PSC0_BASE_ADDR
42/* AC97 and I2S are muxed on the Pb1200 board.
43 Refer to board documentation.
44 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR
47
48#define BCSR_KSEG1_ADDR 0xB9800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_U0RXD 0x1000
106#define BCSR_STATUS_U1RXD 0x2000
107
108#define BCSR_SWITCHES_OCTAL 0x00FF
109#define BCSR_SWITCHES_DIP_1 0x0080
110#define BCSR_SWITCHES_DIP_2 0x0040
111#define BCSR_SWITCHES_DIP_3 0x0020
112#define BCSR_SWITCHES_DIP_4 0x0010
113#define BCSR_SWITCHES_DIP_5 0x0008
114#define BCSR_SWITCHES_DIP_6 0x0004
115#define BCSR_SWITCHES_DIP_7 0x0002
116#define BCSR_SWITCHES_DIP_8 0x0001
117#define BCSR_SWITCHES_ROTARY 0x0F00
118
119#define BCSR_RESETS_ETH 0x0001
120#define BCSR_RESETS_CAMERA 0x0002
121#define BCSR_RESETS_DC 0x0004
122#define BCSR_RESETS_IDE 0x0008
123#define BCSR_RESETS_TV 0x0010
124/* not resets but in the same register */
125#define BCSR_RESETS_PWMR1mUX 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129
130#define BCSR_PCMCIA_PC0VPP 0x0003
131#define BCSR_PCMCIA_PC0VCC 0x000C
132#define BCSR_PCMCIA_PC0DRVEN 0x0010
133#define BCSR_PCMCIA_PC0RST 0x0080
134#define BCSR_PCMCIA_PC1VPP 0x0300
135#define BCSR_PCMCIA_PC1VCC 0x0C00
136#define BCSR_PCMCIA_PC1DRVEN 0x1000
137#define BCSR_PCMCIA_PC1RST 0x8000
138
139#define BCSR_BOARD_LCDVEE 0x0001
140#define BCSR_BOARD_LCDVDD 0x0002
141#define BCSR_BOARD_LCDBL 0x0004
142#define BCSR_BOARD_CAMSNAP 0x0010
143#define BCSR_BOARD_CAMPWR 0x0020
144#define BCSR_BOARD_SD0PWR 0x0040
145
146#define BCSR_LEDS_DECIMALS 0x0003
147#define BCSR_LEDS_LED0 0x0100
148#define BCSR_LEDS_LED1 0x0200
149#define BCSR_LEDS_LED2 0x0400
150#define BCSR_LEDS_LED3 0x0800
151
152#define BCSR_SYSTEM_POWEROFF 0x4000
153#define BCSR_SYSTEM_RESET 0x8000
154
155/* Bit positions for the different interrupt sources */
156#define BCSR_INT_IDE 0x0001
157#define BCSR_INT_ETH 0x0002
158#define BCSR_INT_PC0 0x0004
159#define BCSR_INT_PC0STSCHG 0x0008
160#define BCSR_INT_PC1 0x0010
161#define BCSR_INT_PC1STSCHG 0x0020
162#define BCSR_INT_DC 0x0040
163#define BCSR_INT_FLASHBUSY 0x0080
164#define BCSR_INT_PC0INSERT 0x0100
165#define BCSR_INT_PC0EJECT 0x0200
166#define BCSR_INT_PC1INSERT 0x0400
167#define BCSR_INT_PC1EJECT 0x0800
168#define BCSR_INT_SD0INSERT 0x1000
169#define BCSR_INT_SD0EJECT 0x2000
170
171#define AU1XXX_SMC91111_PHYS_ADDR (0x19000300)
172#define AU1XXX_SMC91111_IRQ DB1200_ETH_INT
173
174#define AU1XXX_ATA_PHYS_ADDR (0x18800000)
175#define AU1XXX_ATA_PHYS_LEN (0x100)
176#define AU1XXX_ATA_REG_OFFSET (5)
177#define AU1XXX_ATA_INT DB1200_IDE_INT
178#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1;
179#define AU1XXX_ATA_RQSIZE 128
180
181#define NAND_PHYS_ADDR 0x20000000
182
183/*
184 * External Interrupts for Pb1200 as of 8/6/2004.
185 * Bit positions in the CPLD registers can be calculated by taking
186 * the interrupt define and subtracting the DB1200_INT_BEGIN value.
187 * *example: IDE bis pos is = 64 - 64
188 ETH bit pos is = 65 - 64
189 */
190#define DB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1)
191#define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
192#define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
193#define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
194#define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
195#define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
196#define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
197#define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
198#define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
199#define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
200#define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
201#define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
202#define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
203#define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
204#define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
205
206#define DB1200_INT_END (DB1200_INT_BEGIN + 15)
207
208/* For drivers/pcmcia/au1000_db1x00.c */
209
210/* PCMCIA Db1x00 specific defines */
211
212#define PCMCIA_MAX_SOCK 1
213#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
214
215/* VPP/VCC */
216#define SET_VCC_VPP(VCC, VPP, SLOT)\
217 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
218
219#define BOARD_PC0_INT DB1200_PC0_INT
220#define BOARD_PC1_INT DB1200_PC1_INT
221#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
222
223#endif /* __ASM_DB1200_H */
224
diff --git a/include/asm-mips/mach-dec/mc146818rtc.h b/include/asm-mips/mach-dec/mc146818rtc.h
index a326f451253b..6d37a5675803 100644
--- a/include/asm-mips/mach-dec/mc146818rtc.h
+++ b/include/asm-mips/mach-dec/mc146818rtc.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 1998, 2001 by Ralf Baechle 4 * Copyright (C) 1998, 2001 by Ralf Baechle
5 * Copyright (C) 1998 by Harald Koerfgen 5 * Copyright (C) 1998 by Harald Koerfgen
6 * Copyright (C) 2002 Maciej W. Rozycki 6 * Copyright (C) 2002, 2005 Maciej W. Rozycki
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License 9 * modify it under the terms of the GNU General Public License
@@ -14,23 +14,18 @@
14#define __ASM_MIPS_DEC_RTC_DEC_H 14#define __ASM_MIPS_DEC_RTC_DEC_H
15 15
16#include <linux/types.h> 16#include <linux/types.h>
17
18#include <asm/addrspace.h> 17#include <asm/addrspace.h>
18#include <asm/dec/system.h>
19 19
20extern volatile u8 *dec_rtc_base; 20extern volatile u8 *dec_rtc_base;
21extern unsigned long dec_kn_slot_size;
22 21
23#define RTC_PORT(x) CPHYSADDR(dec_rtc_base) 22#define RTC_PORT(x) CPHYSADDR((long)dec_rtc_base)
24#define RTC_IO_EXTENT dec_kn_slot_size 23#define RTC_IO_EXTENT dec_kn_slot_size
25#define RTC_IOMAPPED 0 24#define RTC_IOMAPPED 0
26#undef RTC_IRQ 25#undef RTC_IRQ
27 26
28#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */ 27#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */
29 28
30#include <linux/mc146818rtc.h>
31#include <linux/module.h>
32#include <linux/types.h>
33
34static inline unsigned char CMOS_READ(unsigned long addr) 29static inline unsigned char CMOS_READ(unsigned long addr)
35{ 30{
36 return dec_rtc_base[addr * 4]; 31 return dec_rtc_base[addr * 4];
diff --git a/include/asm-mips/mach-generic/cpu-feature-overrides.h b/include/asm-mips/mach-generic/cpu-feature-overrides.h
index 0aecfd08e39a..7c185bb06f13 100644
--- a/include/asm-mips/mach-generic/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-generic/cpu-feature-overrides.h
@@ -8,6 +8,6 @@
8#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H 8#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H 9#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
10 10
11/* Intensionally empty file ... */ 11/* Intentionally empty file ... */
12 12
13#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */ 13#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
index cb2edd018ad6..961006948c7c 100644
--- a/include/asm-mips/mach-generic/ide.h
+++ b/include/asm-mips/mach-generic/ide.h
@@ -18,6 +18,7 @@
18#include <linux/config.h> 18#include <linux/config.h>
19#include <linux/pci.h> 19#include <linux/pci.h>
20#include <linux/stddef.h> 20#include <linux/stddef.h>
21#include <asm/processor.h>
21 22
22#ifndef MAX_HWIFS 23#ifndef MAX_HWIFS
23# ifdef CONFIG_BLK_DEV_IDEPCI 24# ifdef CONFIG_BLK_DEV_IDEPCI
@@ -104,15 +105,71 @@ static __inline__ unsigned long ide_default_io_base(int index)
104 105
105/* MIPS port and memory-mapped I/O string operations. */ 106/* MIPS port and memory-mapped I/O string operations. */
106 107
107#define __ide_insw insw 108static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
108#define __ide_insl insl 109{
109#define __ide_outsw outsw 110 if (cpu_has_dc_aliases) {
110#define __ide_outsl outsl 111 unsigned long end = addr + size;
112 for (; addr < end; addr += PAGE_SIZE)
113 flush_dcache_page(virt_to_page(addr));
114 }
115}
116
117static inline void __ide_insw(unsigned long port, void *addr,
118 unsigned int count)
119{
120 insw(port, addr, count);
121 __ide_flush_dcache_range((unsigned long)addr, count * 2);
122}
123
124static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
125{
126 insl(port, addr, count);
127 __ide_flush_dcache_range((unsigned long)addr, count * 4);
128}
129
130static inline void __ide_outsw(unsigned long port, const void *addr,
131 unsigned long count)
132{
133 outsw(port, addr, count);
134 __ide_flush_dcache_range((unsigned long)addr, count * 2);
135}
136
137static inline void __ide_outsl(unsigned long port, const void *addr,
138 unsigned long count)
139{
140 outsl(port, addr, count);
141 __ide_flush_dcache_range((unsigned long)addr, count * 4);
142}
143
144static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
145{
146 readsw(port, addr, count);
147 __ide_flush_dcache_range((unsigned long)addr, count * 2);
148}
149
150static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
151{
152 readsl(port, addr, count);
153 __ide_flush_dcache_range((unsigned long)addr, count * 4);
154}
155
156static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
157{
158 writesw(port, addr, count);
159 __ide_flush_dcache_range((unsigned long)addr, count * 2);
160}
161
162static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
163{
164 writesl(port, addr, count);
165 __ide_flush_dcache_range((unsigned long)addr, count * 4);
166}
111 167
112#define __ide_mm_insw readsw 168/* ide_insw calls insw, not __ide_insw. Why? */
113#define __ide_mm_insl readsl 169#undef insw
114#define __ide_mm_outsw writesw 170#undef insl
115#define __ide_mm_outsl writesl 171#define insw(port, addr, count) __ide_insw(port, addr, count)
172#define insl(port, addr, count) __ide_insl(port, addr, count)
116 173
117#endif /* __KERNEL__ */ 174#endif /* __KERNEL__ */
118 175
diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h
new file mode 100644
index 000000000000..9b64ff6e485d
--- /dev/null
+++ b/include/asm-mips/mach-generic/ioremap.h
@@ -0,0 +1,23 @@
1/*
2 * include/asm-mips/mach-generic/ioremap.h
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifndef __ASM_MACH_GENERIC_IOREMAP_H
10#define __ASM_MACH_GENERIC_IOREMAP_H
11
12#include <linux/types.h>
13
14/*
15 * Allow physical addresses to be fixed up to help peripherals located
16 * outside the low 32-bit range -- generic pass-through version.
17 */
18static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
19{
20 return phys_addr;
21}
22
23#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/include/asm-mips/mach-generic/kernel-entry-init.h b/include/asm-mips/mach-generic/kernel-entry-init.h
new file mode 100644
index 000000000000..7e66505fa574
--- /dev/null
+++ b/include/asm-mips/mach-generic/kernel-entry-init.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 Embedded Alley Solutions, Inc
7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8 */
9#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
10#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
11
12/* Intentionally empty macro, used in head.S. Override in
13 * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
14 */
15.macro kernel_entry_setup
16.endm
17
18/*
19 * Do SMP slave processor setup necessary before we can savely execute C code.
20 */
21 .macro smp_slave_setup
22 .endm
23
24
25#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */
diff --git a/include/asm-mips/mach-generic/kmalloc.h b/include/asm-mips/mach-generic/kmalloc.h
new file mode 100644
index 000000000000..373d66dee9d7
--- /dev/null
+++ b/include/asm-mips/mach-generic/kmalloc.h
@@ -0,0 +1,13 @@
1#ifndef __ASM_MACH_GENERIC_KMALLOC_H
2#define __ASM_MACH_GENERIC_KMALLOC_H
3
4#include <linux/config.h>
5
6#ifndef CONFIG_DMA_COHERENT
7/*
8 * Total overkill for most systems but need as a safe default.
9 */
10#define ARCH_KMALLOC_MINALIGN 128
11#endif
12
13#endif /* __ASM_MACH_GENERIC_KMALLOC_H */
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h
index 5a2c1efb4eb7..b849d8dd7e78 100644
--- a/include/asm-mips/mach-generic/spaces.h
+++ b/include/asm-mips/mach-generic/spaces.h
@@ -55,13 +55,13 @@
55#endif 55#endif
56 56
57#ifdef CONFIG_DMA_NONCOHERENT 57#ifdef CONFIG_DMA_NONCOHERENT
58#define CAC_BASE 0x9800000000000000 58#define CAC_BASE 0x9800000000000000UL
59#else 59#else
60#define CAC_BASE 0xa800000000000000 60#define CAC_BASE 0xa800000000000000UL
61#endif 61#endif
62#define IO_BASE 0x9000000000000000 62#define IO_BASE 0x9000000000000000UL
63#define UNCAC_BASE 0x9000000000000000 63#define UNCAC_BASE 0x9000000000000000UL
64#define MAP_BASE 0xc000000000000000 64#define MAP_BASE 0xc000000000000000UL
65 65
66#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) 66#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
67#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) 67#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
index 3c8896d9b133..ab9714668177 100644
--- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
@@ -11,6 +11,12 @@
11/* 11/*
12 * IP22 with a variety of processors so we can't use defaults for everything. 12 * IP22 with a variety of processors so we can't use defaults for everything.
13 */ 13 */
14#define cpu_has_tlb 1
15#define cpu_has_4kex 1
16#define cpu_has_4kcache 1
17#define cpu_has_fpu 1
18#define cpu_has_32fpr 1
19#define cpu_has_counter 1
14#define cpu_has_mips16 0 20#define cpu_has_mips16 0
15#define cpu_has_divec 0 21#define cpu_has_divec 0
16#define cpu_has_cache_cdex_p 1 22#define cpu_has_cache_cdex_p 1
@@ -23,6 +29,8 @@
23#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) 29#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
24#define cpu_has_ic_fills_f_dc 0 30#define cpu_has_ic_fills_f_dc 0
25 31
32#define cpu_has_dsp 0
33
26#define cpu_has_nofpuex 0 34#define cpu_has_nofpuex 0
27#define cpu_has_64bits 1 35#define cpu_has_64bits 1
28 36
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h
index e96166f27c49..8385f716798d 100644
--- a/include/asm-mips/mach-ip22/spaces.h
+++ b/include/asm-mips/mach-ip22/spaces.h
@@ -44,7 +44,7 @@
44#define CAC_BASE 0xffffffff80000000 44#define CAC_BASE 0xffffffff80000000
45#define IO_BASE 0xffffffffa0000000 45#define IO_BASE 0xffffffffa0000000
46#define UNCAC_BASE 0xffffffffa0000000 46#define UNCAC_BASE 0xffffffffa0000000
47#define MAP_BASE 0xffffffffc0000000 47#define MAP_BASE 0xc000000000000000
48 48
49#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) 49#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
50#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) 50#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
index fe96d7358517..4c8a90051fd0 100644
--- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
25#define cpu_has_vtag_icache 0 25#define cpu_has_vtag_icache 0
26#define cpu_has_dc_aliases 0 26#define cpu_has_dc_aliases 0
27#define cpu_has_ic_fills_f_dc 0 27#define cpu_has_ic_fills_f_dc 0
28#define cpu_has_dsp 0
28#define cpu_icache_snoops_remote_store 1 29#define cpu_icache_snoops_remote_store 1
29 30
30#define cpu_has_nofpuex 0 31#define cpu_has_nofpuex 0
diff --git a/include/asm-mips/mach-ip27/kernel-entry-init.h b/include/asm-mips/mach-ip27/kernel-entry-init.h
new file mode 100644
index 000000000000..c1a10314b317
--- /dev/null
+++ b/include/asm-mips/mach-ip27/kernel-entry-init.h
@@ -0,0 +1,52 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Silicon Graphics, Inc.
7 * Copyright (C) 2005 Ralf Baechle <ralf@linux-mips.org>
8 */
9#ifndef __ASM_MACH_IP27_KERNEL_ENTRY_H
10#define __ASM_MACH_IP27_KERNEL_ENTRY_H
11
12#include <asm/sn/addrs.h>
13#include <asm/sn/sn0/hubni.h>
14#include <asm/sn/klkernvars.h>
15
16/*
17 * Returns the local nasid into res.
18 */
19 .macro GET_NASID_ASM res
20 dli \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
21 ld \res, (\res)
22 and \res, NSRI_NODEID_MASK
23 dsrl \res, NSRI_NODEID_SHFT
24 .endm
25
26/*
27 * Intentionally empty macro, used in head.S. Override in
28 * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
29 */
30 .macro kernel_entry_setup
31 GET_NASID_ASM t1
32 move t2, t1 # text and data are here
33 MAPPED_KERNEL_SETUP_TLB
34 .endm
35
36/*
37 * Do SMP slave processor setup necessary before we can savely execute C code.
38 */
39 .macro smp_slave_setup
40 GET_NASID_ASM t1
41 dli t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
42 KLDIR_OFF_POINTER + CAC_BASE
43 dsll t1, NASID_SHFT
44 or t0, t0, t1
45 ld t0, 0(t0) # t0 points to kern_vars struct
46 lh t1, KV_RO_NASID_OFFSET(t0)
47 lh t2, KV_RW_NASID_OFFSET(t0)
48 MAPPED_KERNEL_SETUP_TLB
49 ARC64_TWIDDLE_PC
50 .endm
51
52#endif /* __ASM_MACH_IP27_KERNEL_ENTRY_H */
diff --git a/include/asm-mips/mach-ip27/kmalloc.h b/include/asm-mips/mach-ip27/kmalloc.h
new file mode 100644
index 000000000000..426bd049b2d7
--- /dev/null
+++ b/include/asm-mips/mach-ip27/kmalloc.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_MACH_IP27_KMALLOC_H
2#define __ASM_MACH_IP27_KMALLOC_H
3
4/*
5 * All happy, no need to define ARCH_KMALLOC_MINALIGN
6 */
7
8#endif /* __ASM_MACH_IP27_KMALLOC_H */
diff --git a/include/asm-mips/mach-ip27/mmzone.h b/include/asm-mips/mach-ip27/mmzone.h
index d3f566362e9d..986a3b9b59a7 100644
--- a/include/asm-mips/mach-ip27/mmzone.h
+++ b/include/asm-mips/mach-ip27/mmzone.h
@@ -10,7 +10,6 @@
10#define LEVELS_PER_SLICE 128 10#define LEVELS_PER_SLICE 128
11 11
12struct slice_data { 12struct slice_data {
13 unsigned long irq_alloc_mask[2];
14 unsigned long irq_enable_mask[2]; 13 unsigned long irq_enable_mask[2];
15 int level_to_irq[LEVELS_PER_SLICE]; 14 int level_to_irq[LEVELS_PER_SLICE];
16}; 15};
@@ -20,6 +19,7 @@ struct hub_data {
20 DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW); 19 DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
21 cpumask_t h_cpus; 20 cpumask_t h_cpus;
22 unsigned long slice_map; 21 unsigned long slice_map;
22 unsigned long irq_alloc_mask[2];
23 struct slice_data slice[2]; 23 struct slice_data slice[2];
24}; 24};
25 25
diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h
index e3b3fe32eeb1..45e61785ef42 100644
--- a/include/asm-mips/mach-ip27/spaces.h
+++ b/include/asm-mips/mach-ip27/spaces.h
@@ -20,6 +20,7 @@
20#define IO_BASE 0x9200000000000000 20#define IO_BASE 0x9200000000000000
21#define MSPEC_BASE 0x9400000000000000 21#define MSPEC_BASE 0x9400000000000000
22#define UNCAC_BASE 0x9600000000000000 22#define UNCAC_BASE 0x9600000000000000
23#define MAP_BASE 0xc000000000000000
23 24
24#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) 25#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
25#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) 26#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h
index a70a81257c3d..82141c711c33 100644
--- a/include/asm-mips/mach-ip27/topology.h
+++ b/include/asm-mips/mach-ip27/topology.h
@@ -9,6 +9,9 @@
9#define parent_node(node) (node) 9#define parent_node(node) (node)
10#define node_to_cpumask(node) (hub_data(node)->h_cpus) 10#define node_to_cpumask(node) (hub_data(node)->h_cpus)
11#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node))) 11#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
12struct pci_bus;
13extern int pcibus_to_node(struct pci_bus *);
14
12#define pcibus_to_cpumask(bus) (cpu_online_map) 15#define pcibus_to_cpumask(bus) (cpu_online_map)
13 16
14extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; 17extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
index 04713973c6c3..ab37fc1842ba 100644
--- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
@@ -37,5 +37,6 @@
37#define cpu_has_ejtag 0 37#define cpu_has_ejtag 0
38#define cpu_has_vtag_icache 0 38#define cpu_has_vtag_icache 0
39#define cpu_has_ic_fills_f_dc 0 39#define cpu_has_ic_fills_f_dc 0
40#define cpu_has_dsp 0
40 41
41#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */ 42#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h
new file mode 100644
index 000000000000..9d2d4d9ac036
--- /dev/null
+++ b/include/asm-mips/mach-ip32/kmalloc.h
@@ -0,0 +1,12 @@
1#ifndef __ASM_MACH_IP32_KMALLOC_H
2#define __ASM_MACH_IP32_KMALLOC_H
3
4#include <linux/config.h>
5
6#if defined(CONFIG_CPU_R5000) || defined (CONFIG_CPU_RM7000)
7#define ARCH_KMALLOC_MINALIGN 32
8#else
9#define ARCH_KMALLOC_MINALIGN 128
10#endif
11
12#endif /* __ASM_MACH_IP32_KMALLOC_H */
diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h
index c7839f85c68d..44abe5c02389 100644
--- a/include/asm-mips/mach-ip32/spaces.h
+++ b/include/asm-mips/mach-ip32/spaces.h
@@ -19,10 +19,10 @@
19#define HIGHMEM_START (1UL << 59UL) 19#define HIGHMEM_START (1UL << 59UL)
20#endif 20#endif
21 21
22#define CAC_BASE 0x9800000000000000 22#define CAC_BASE 0x9800000000000000UL
23#define IO_BASE 0x9000000000000000 23#define IO_BASE 0x9000000000000000UL
24#define UNCAC_BASE 0x9000000000000000 24#define UNCAC_BASE 0x9000000000000000UL
25#define MAP_BASE 0xc000000000000000 25#define MAP_BASE 0xc000000000000000UL
26 26
27#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) 27#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
28#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) 28#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h
index ca57e7db98bb..a0fde405d4c4 100644
--- a/include/asm-mips/mach-ja/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
25#define cpu_has_vtag_icache 0 25#define cpu_has_vtag_icache 0
26#define cpu_has_dc_aliases 0 26#define cpu_has_dc_aliases 0
27#define cpu_has_ic_fills_f_dc 0 27#define cpu_has_ic_fills_f_dc 0
28#define cpu_has_dsp 0
28#define cpu_icache_snoops_remote_store 0 29#define cpu_icache_snoops_remote_store 0
29 30
30#define cpu_has_nofpuex 0 31#define cpu_has_nofpuex 0
@@ -36,10 +37,4 @@
36#define cpu_icache_line_size() 32 37#define cpu_icache_line_size() 32
37#define cpu_scache_line_size() 32 38#define cpu_scache_line_size() 32
38 39
39/*
40 * On the RM9000 we need to ensure that I-cache lines being fetches only
41 * contain valid instructions are funny things will happen.
42 */
43#define PLAT_TRAMPOLINE_STUFF_LINE 32UL
44
45#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ 40#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h
index 6f51be571bf0..9f92aed17754 100644
--- a/include/asm-mips/mach-mips/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h
@@ -17,7 +17,7 @@
17#ifdef CONFIG_CPU_MIPS32 17#ifdef CONFIG_CPU_MIPS32
18#define cpu_has_tlb 1 18#define cpu_has_tlb 1
19#define cpu_has_4kex 1 19#define cpu_has_4kex 1
20#define cpu_has_4ktlb 1 20#define cpu_has_4kcache 1
21/* #define cpu_has_fpu ? */ 21/* #define cpu_has_fpu ? */
22/* #define cpu_has_32fpr ? */ 22/* #define cpu_has_32fpr ? */
23#define cpu_has_counter 1 23#define cpu_has_counter 1
@@ -37,12 +37,13 @@
37/* #define cpu_has_64bits ? */ 37/* #define cpu_has_64bits ? */
38/* #define cpu_has_64bit_zero_reg ? */ 38/* #define cpu_has_64bit_zero_reg ? */
39/* #define cpu_has_subset_pcaches ? */ 39/* #define cpu_has_subset_pcaches ? */
40#define cpu_icache_snoops_remote_store 1
40#endif 41#endif
41 42
42#ifdef CONFIG_CPU_MIPS64 43#ifdef CONFIG_CPU_MIPS64
43#define cpu_has_tlb 1 44#define cpu_has_tlb 1
44#define cpu_has_4kex 1 45#define cpu_has_4kex 1
45#define cpu_has_4ktlb 1 46#define cpu_has_4kcache 1
46/* #define cpu_has_fpu ? */ 47/* #define cpu_has_fpu ? */
47/* #define cpu_has_32fpr ? */ 48/* #define cpu_has_32fpr ? */
48#define cpu_has_counter 1 49#define cpu_has_counter 1
@@ -62,6 +63,7 @@
62/* #define cpu_has_64bits ? */ 63/* #define cpu_has_64bits ? */
63/* #define cpu_has_64bit_zero_reg ? */ 64/* #define cpu_has_64bit_zero_reg ? */
64/* #define cpu_has_subset_pcaches ? */ 65/* #define cpu_has_subset_pcaches ? */
66#define cpu_icache_snoops_remote_store 1
65#endif 67#endif
66 68
67#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ 69#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-mips/irq.h b/include/asm-mips/mach-mips/irq.h
new file mode 100644
index 000000000000..f8579696ca54
--- /dev/null
+++ b/include/asm-mips/mach-mips/irq.h
@@ -0,0 +1,14 @@
1#ifndef __ASM_MACH_MIPS_IRQ_H
2#define __ASM_MACH_MIPS_IRQ_H
3
4#include <linux/config.h>
5
6#define NR_IRQS 256
7
8#ifdef CONFIG_SMP
9
10#define ARCH_HAS_IRQ_PER_CPU
11
12#endif
13
14#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
index 7473512384bc..825c5f674dfc 100644
--- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
@@ -28,6 +28,7 @@
28#define cpu_has_vtag_icache 0 28#define cpu_has_vtag_icache 0
29#define cpu_has_dc_aliases 0 29#define cpu_has_dc_aliases 0
30#define cpu_has_ic_fills_f_dc 0 30#define cpu_has_ic_fills_f_dc 0
31#define cpu_has_dsp 0
31#define cpu_icache_snoops_remote_store 0 32#define cpu_icache_snoops_remote_store 0
32 33
33#define cpu_has_nofpuex 0 34#define cpu_has_nofpuex 0
@@ -39,10 +40,4 @@
39#define cpu_icache_line_size() 32 40#define cpu_icache_line_size() 32
40#define cpu_scache_line_size() 32 41#define cpu_scache_line_size() 32
41 42
42/*
43 * On the RM9000 we need to ensure that I-cache lines being fetches only
44 * contain valid instructions are funny things will happen.
45 */
46#define PLAT_TRAMPOLINE_STUFF_LINE 32UL
47
48#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ 43#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
new file mode 100644
index 000000000000..9a3088b19bf3
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -0,0 +1,252 @@
1/*
2 * AMD Alchemy PB1200 Referrence Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_PB1200_H
25#define __ASM_PB1200_H
26
27#include <linux/types.h>
28
29// This is defined in au1000.h with bogus value
30#undef AU1X00_EXTERNAL_INT
31
32#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
34#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
35#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
36
37/* SPI and SMB are muxed on the Pb1200 board.
38 Refer to board documentation.
39 */
40#define SPI_PSC_BASE PSC0_BASE_ADDR
41#define SMBUS_PSC_BASE PSC0_BASE_ADDR
42/* AC97 and I2S are muxed on the Pb1200 board.
43 Refer to board documentation.
44 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR
47
48#define BCSR_KSEG1_ADDR 0xAD800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_SD1WP 0x0800
106#define BCSR_STATUS_U0RXD 0x1000
107#define BCSR_STATUS_U1RXD 0x2000
108
109#define BCSR_SWITCHES_OCTAL 0x00FF
110#define BCSR_SWITCHES_DIP_1 0x0080
111#define BCSR_SWITCHES_DIP_2 0x0040
112#define BCSR_SWITCHES_DIP_3 0x0020
113#define BCSR_SWITCHES_DIP_4 0x0010
114#define BCSR_SWITCHES_DIP_5 0x0008
115#define BCSR_SWITCHES_DIP_6 0x0004
116#define BCSR_SWITCHES_DIP_7 0x0002
117#define BCSR_SWITCHES_DIP_8 0x0001
118#define BCSR_SWITCHES_ROTARY 0x0F00
119
120#define BCSR_RESETS_ETH 0x0001
121#define BCSR_RESETS_CAMERA 0x0002
122#define BCSR_RESETS_DC 0x0004
123#define BCSR_RESETS_IDE 0x0008
124/* not resets but in the same register */
125#define BCSR_RESETS_WSCFSM 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129#define BCSR_RESETS_SD1MUX 0x8000
130
131#define BCSR_PCMCIA_PC0VPP 0x0003
132#define BCSR_PCMCIA_PC0VCC 0x000C
133#define BCSR_PCMCIA_PC0DRVEN 0x0010
134#define BCSR_PCMCIA_PC0RST 0x0080
135#define BCSR_PCMCIA_PC1VPP 0x0300
136#define BCSR_PCMCIA_PC1VCC 0x0C00
137#define BCSR_PCMCIA_PC1DRVEN 0x1000
138#define BCSR_PCMCIA_PC1RST 0x8000
139
140#define BCSR_BOARD_LCDVEE 0x0001
141#define BCSR_BOARD_LCDVDD 0x0002
142#define BCSR_BOARD_LCDBL 0x0004
143#define BCSR_BOARD_CAMSNAP 0x0010
144#define BCSR_BOARD_CAMPWR 0x0020
145#define BCSR_BOARD_SD0PWR 0x0040
146#define BCSR_BOARD_SD1PWR 0x0080
147
148#define BCSR_LEDS_DECIMALS 0x00FF
149#define BCSR_LEDS_LED0 0x0100
150#define BCSR_LEDS_LED1 0x0200
151#define BCSR_LEDS_LED2 0x0400
152#define BCSR_LEDS_LED3 0x0800
153
154#define BCSR_SYSTEM_VDDI 0x001F
155#define BCSR_SYSTEM_POWEROFF 0x4000
156#define BCSR_SYSTEM_RESET 0x8000
157
158/* Bit positions for the different interrupt sources */
159#define BCSR_INT_IDE 0x0001
160#define BCSR_INT_ETH 0x0002
161#define BCSR_INT_PC0 0x0004
162#define BCSR_INT_PC0STSCHG 0x0008
163#define BCSR_INT_PC1 0x0010
164#define BCSR_INT_PC1STSCHG 0x0020
165#define BCSR_INT_DC 0x0040
166#define BCSR_INT_FLASHBUSY 0x0080
167#define BCSR_INT_PC0INSERT 0x0100
168#define BCSR_INT_PC0EJECT 0x0200
169#define BCSR_INT_PC1INSERT 0x0400
170#define BCSR_INT_PC1EJECT 0x0800
171#define BCSR_INT_SD0INSERT 0x1000
172#define BCSR_INT_SD0EJECT 0x2000
173#define BCSR_INT_SD1INSERT 0x4000
174#define BCSR_INT_SD1EJECT 0x8000
175
176/* PCMCIA Db1x00 specific defines */
177#define PCMCIA_MAX_SOCK 1
178#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
179
180/* VPP/VCC */
181#define SET_VCC_VPP(VCC, VPP, SLOT)\
182 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
183
184#define AU1XXX_SMC91111_PHYS_ADDR (0x0D000300)
185#define AU1XXX_SMC91111_IRQ PB1200_ETH_INT
186
187#define AU1XXX_ATA_PHYS_ADDR (0x0C800000)
188#define AU1XXX_ATA_PHYS_LEN (0x100)
189#define AU1XXX_ATA_REG_OFFSET (5)
190#define AU1XXX_ATA_INT PB1200_IDE_INT
191#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1;
192#define AU1XXX_ATA_RQSIZE 128
193
194#define NAND_PHYS_ADDR 0x1C000000
195
196/* Timing values as described in databook, * ns value stripped of
197 * lower 2 bits.
198 * These defines are here rather than an SOC1200 generic file because
199 * the parts chosen on another board may be different and may require
200 * different timings.
201 */
202#define NAND_T_H (18 >> 2)
203#define NAND_T_PUL (30 >> 2)
204#define NAND_T_SU (30 >> 2)
205#define NAND_T_WH (30 >> 2)
206
207/* Bitfield shift amounts */
208#define NAND_T_H_SHIFT 0
209#define NAND_T_PUL_SHIFT 4
210#define NAND_T_SU_SHIFT 8
211#define NAND_T_WH_SHIFT 12
212
213#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
214 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
215 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
216 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
217
218
219/*
220 * External Interrupts for Pb1200 as of 8/6/2004.
221 * Bit positions in the CPLD registers can be calculated by taking
222 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
223 * *example: IDE bis pos is = 64 - 64
224 ETH bit pos is = 65 - 64
225 */
226#define PB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1)
227#define PB1200_IDE_INT (PB1200_INT_BEGIN + 0)
228#define PB1200_ETH_INT (PB1200_INT_BEGIN + 1)
229#define PB1200_PC0_INT (PB1200_INT_BEGIN + 2)
230#define PB1200_PC0_STSCHG_INT (PB1200_INT_BEGIN + 3)
231#define PB1200_PC1_INT (PB1200_INT_BEGIN + 4)
232#define PB1200_PC1_STSCHG_INT (PB1200_INT_BEGIN + 5)
233#define PB1200_DC_INT (PB1200_INT_BEGIN + 6)
234#define PB1200_FLASHBUSY_INT (PB1200_INT_BEGIN + 7)
235#define PB1200_PC0_INSERT_INT (PB1200_INT_BEGIN + 8)
236#define PB1200_PC0_EJECT_INT (PB1200_INT_BEGIN + 9)
237#define PB1200_PC1_INSERT_INT (PB1200_INT_BEGIN + 10)
238#define PB1200_PC1_EJECT_INT (PB1200_INT_BEGIN + 11)
239#define PB1200_SD0_INSERT_INT (PB1200_INT_BEGIN + 12)
240#define PB1200_SD0_EJECT_INT (PB1200_INT_BEGIN + 13)
241#define PB1200_SD1_INSERT_INT (PB1200_INT_BEGIN + 14)
242#define PB1200_SD1_EJECT_INT (PB1200_INT_BEGIN + 15)
243
244#define PB1200_INT_END (PB1200_INT_BEGIN + 15)
245
246/* For drivers/pcmcia/au1000_db1x00.c */
247#define BOARD_PC0_INT PB1200_PC0_INT
248#define BOARD_PC1_INT PB1200_PC1_INT
249#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
250
251#endif /* __ASM_PB1200_H */
252
diff --git a/include/asm-mips/mach-pnx8550/cm.h b/include/asm-mips/mach-pnx8550/cm.h
new file mode 100644
index 000000000000..bb0a56c7d011
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/cm.h
@@ -0,0 +1,43 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Clock module specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_CM_H
23#define __PNX8550_CM_H
24
25#define PNX8550_CM_BASE 0xBBE47000
26
27#define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
28#define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
29#define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
30#define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
31
32// Table not complete.....
33
34#define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000
35#define PNX8550_CM_PLL_LOCK_MASK 0x40000000
36#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
37#define PNX8550_CM_PLL_N_MASK 0x01ff0000
38#define PNX8550_CM_PLL_M_MASK 0x00003f00
39#define PNX8550_CM_PLL_P_MASK 0x0000000c
40#define PNX8550_CM_PLL_PD_MASK 0x00000002
41
42
43#endif
diff --git a/include/asm-mips/mach-pnx8550/glb.h b/include/asm-mips/mach-pnx8550/glb.h
new file mode 100644
index 000000000000..07aa85e609bc
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/glb.h
@@ -0,0 +1,86 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PNX8550 global definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_GLB_H
23#define __PNX8550_GLB_H
24
25#define PNX8550_GLB1_BASE 0xBBE63000
26#define PNX8550_GLB2_BASE 0xBBE4d000
27#define PNX8550_RESET_BASE 0xBBE60000
28
29/* PCI Inta Output Enable Registers */
30#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
31
32/* Bit 1:Enable DAC Powerdown
33 0:DACs are enabled and are working normally
34 1:DACs are powerdown
35*/
36#define PNX8550_GLB_DAC_PD 0x2
37/* Bit 0:Enable of PCI inta output
38 0 = Disable PCI inta output
39 1 = Enable PCI inta output
40*/
41#define PNX8550_GLB_ENABLE_INTA_O 0x1
42
43/* PCI Direct Mappings */
44#define PNX8550_PCIMEM 0x12000000
45#define PNX8550_PCIMEM_SIZE 0x08000000
46#define PNX8550_PCIIO 0x1c000000
47#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */
48
49#define PNX8550_PORT_BASE KSEG1
50
51// GPIO def
52#define PNX8550_GPIO_BASE 0x1Be00000
53
54#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500)
55#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004)
56#define PNX8550_GPIO_MC_31_BIT 30
57#define PNX8550_GPIO_MC_30_BIT 28
58#define PNX8550_GPIO_MC_29_BIT 26
59#define PNX8550_GPIO_MC_28_BIT 24
60#define PNX8550_GPIO_MC_27_BIT 22
61#define PNX8550_GPIO_MC_26_BIT 20
62#define PNX8550_GPIO_MC_25_BIT 18
63#define PNX8550_GPIO_MC_24_BIT 16
64#define PNX8550_GPIO_MC_23_BIT 14
65#define PNX8550_GPIO_MC_22_BIT 12
66#define PNX8550_GPIO_MC_21_BIT 10
67#define PNX8550_GPIO_MC_20_BIT 8
68#define PNX8550_GPIO_MC_19_BIT 6
69#define PNX8550_GPIO_MC_18_BIT 4
70#define PNX8550_GPIO_MC_17_BIT 2
71#define PNX8550_GPIO_MC_16_BIT 0
72
73#define PNX8550_GPIO_MODE_PRIMOP 0x1
74#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
75#define PNX8550_GPIO_MODE_OPENDR 0x3
76
77// RESET module
78#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
79#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
80#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
81
82#define PNX8550_RST_REL_MIPS_RST_N 0x8
83#define PNX8550_RST_DO_SW_RST 0x4
84#define PNX8550_RST_REL_SYS_RST_OUT 0x2
85#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
86#endif
diff --git a/include/asm-mips/mach-pnx8550/int.h b/include/asm-mips/mach-pnx8550/int.h
new file mode 100644
index 000000000000..0e0668b524f4
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/int.h
@@ -0,0 +1,140 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Interrupt specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_INT_H
23#define __PNX8550_INT_H
24
25#define PNX8550_GIC_BASE 0xBBE3E000
26
27#define PNX8550_GIC_PRIMASK_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
28#define PNX8550_GIC_PRIMASK_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
29#define PNX8550_GIC_VECTOR_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
30#define PNX8550_GIC_VECTOR_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
31#define PNX8550_GIC_PEND_1_31 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
32#define PNX8550_GIC_PEND_32_63 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
33#define PNX8550_GIC_PEND_64_70 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
34#define PNX8550_GIC_FEATURES *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
35#define PNX8550_GIC_REQ(x) *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
36#define PNX8550_GIC_MOD_ID *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
37
38// cp0 is two software + six hw exceptions
39#define PNX8550_INT_CP0_TOTINT 8
40#define PNX8550_INT_CP0_MIN 0
41#define PNX8550_INT_CP0_MAX (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
42
43#define MIPS_CPU_GIC_IRQ 2
44#define MIPS_CPU_TIMER_IRQ 7
45
46// GIC are 71 exceptions connected to cp0's first hardware exception
47#define PNX8550_INT_GIC_TOTINT 71
48#define PNX8550_INT_GIC_MIN (PNX8550_INT_CP0_MAX+1)
49#define PNX8550_INT_GIC_MAX (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
50
51#define PNX8550_INT_UNDEF (PNX8550_INT_GIC_MIN+0)
52#define PNX8550_INT_IPC_TARGET0_MIPS (PNX8550_INT_GIC_MIN+1)
53#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
54#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
55#define PNX8550_INT_RESERVED_4 (PNX8550_INT_GIC_MIN+4)
56#define PNX8550_INT_USB (PNX8550_INT_GIC_MIN+5)
57#define PNX8550_INT_GPIO_EQ1 (PNX8550_INT_GIC_MIN+6)
58#define PNX8550_INT_GPIO_EQ2 (PNX8550_INT_GIC_MIN+7)
59#define PNX8550_INT_GPIO_EQ3 (PNX8550_INT_GIC_MIN+8)
60#define PNX8550_INT_GPIO_EQ4 (PNX8550_INT_GIC_MIN+9)
61
62#define PNX8550_INT_GPIO_EQ5 (PNX8550_INT_GIC_MIN+10)
63#define PNX8550_INT_GPIO_EQ6 (PNX8550_INT_GIC_MIN+11)
64#define PNX8550_INT_RESERVED_12 (PNX8550_INT_GIC_MIN+12)
65#define PNX8550_INT_QVCP1 (PNX8550_INT_GIC_MIN+13)
66#define PNX8550_INT_QVCP2 (PNX8550_INT_GIC_MIN+14)
67#define PNX8550_INT_I2C1 (PNX8550_INT_GIC_MIN+15)
68#define PNX8550_INT_I2C2 (PNX8550_INT_GIC_MIN+16)
69#define PNX8550_INT_ISO_UART1 (PNX8550_INT_GIC_MIN+17)
70#define PNX8550_INT_ISO_UART2 (PNX8550_INT_GIC_MIN+18)
71#define PNX8550_INT_UART1 (PNX8550_INT_GIC_MIN+19)
72
73#define PNX8550_INT_UART2 (PNX8550_INT_GIC_MIN+20)
74#define PNX8550_INT_QNTR (PNX8550_INT_GIC_MIN+21)
75#define PNX8550_INT_RESERVED22 (PNX8550_INT_GIC_MIN+22)
76#define PNX8550_INT_T_DSC (PNX8550_INT_GIC_MIN+23)
77#define PNX8550_INT_M_DSC (PNX8550_INT_GIC_MIN+24)
78#define PNX8550_INT_RESERVED25 (PNX8550_INT_GIC_MIN+25)
79#define PNX8550_INT_2D_DRAW_ENG (PNX8550_INT_GIC_MIN+26)
80#define PNX8550_INT_MEM_BASED_SCALAR1 (PNX8550_INT_GIC_MIN+27)
81#define PNX8550_INT_VIDEO_MPEG (PNX8550_INT_GIC_MIN+28)
82#define PNX8550_INT_VIDEO_INPUT_P1 (PNX8550_INT_GIC_MIN+29)
83
84#define PNX8550_INT_VIDEO_INPUT_P2 (PNX8550_INT_GIC_MIN+30)
85#define PNX8550_INT_SPDI1 (PNX8550_INT_GIC_MIN+31)
86#define PNX8550_INT_SPDO (PNX8550_INT_GIC_MIN+32)
87#define PNX8550_INT_AUDIO_INPUT1 (PNX8550_INT_GIC_MIN+33)
88#define PNX8550_INT_AUDIO_OUTPUT1 (PNX8550_INT_GIC_MIN+34)
89#define PNX8550_INT_AUDIO_INPUT2 (PNX8550_INT_GIC_MIN+35)
90#define PNX8550_INT_AUDIO_OUTPUT2 (PNX8550_INT_GIC_MIN+36)
91#define PNX8550_INT_MEMBASED_SCALAR2 (PNX8550_INT_GIC_MIN+37)
92#define PNX8550_INT_VPK (PNX8550_INT_GIC_MIN+38)
93#define PNX8550_INT_MPEG1_MIPS (PNX8550_INT_GIC_MIN+39)
94
95#define PNX8550_INT_MPEG1_TM (PNX8550_INT_GIC_MIN+40)
96#define PNX8550_INT_MPEG2_MIPS (PNX8550_INT_GIC_MIN+41)
97#define PNX8550_INT_MPEG2_TM (PNX8550_INT_GIC_MIN+42)
98#define PNX8550_INT_TS_DMA (PNX8550_INT_GIC_MIN+43)
99#define PNX8550_INT_EDMA (PNX8550_INT_GIC_MIN+44)
100#define PNX8550_INT_TM_DEBUG1 (PNX8550_INT_GIC_MIN+45)
101#define PNX8550_INT_TM_DEBUG2 (PNX8550_INT_GIC_MIN+46)
102#define PNX8550_INT_PCI_INTA (PNX8550_INT_GIC_MIN+47)
103#define PNX8550_INT_CLOCK_MODULE (PNX8550_INT_GIC_MIN+48)
104#define PNX8550_INT_PCI_XIO_INTA_PCI (PNX8550_INT_GIC_MIN+49)
105
106#define PNX8550_INT_PCI_XIO_INTB_DMA (PNX8550_INT_GIC_MIN+50)
107#define PNX8550_INT_PCI_XIO_INTC_GPPM (PNX8550_INT_GIC_MIN+51)
108#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
109#define PNX8550_INT_DVD_CSS (PNX8550_INT_GIC_MIN+53)
110#define PNX8550_INT_VLD (PNX8550_INT_GIC_MIN+54)
111#define PNX8550_INT_GPIO_TSU_7_0 (PNX8550_INT_GIC_MIN+55)
112#define PNX8550_INT_GPIO_TSU_15_8 (PNX8550_INT_GIC_MIN+56)
113#define PNX8550_INT_GPIO_CTU_IR (PNX8550_INT_GIC_MIN+57)
114#define PNX8550_INT_GPIO0 (PNX8550_INT_GIC_MIN+58)
115#define PNX8550_INT_GPIO1 (PNX8550_INT_GIC_MIN+59)
116
117#define PNX8550_INT_GPIO2 (PNX8550_INT_GIC_MIN+60)
118#define PNX8550_INT_GPIO3 (PNX8550_INT_GIC_MIN+61)
119#define PNX8550_INT_GPIO4 (PNX8550_INT_GIC_MIN+62)
120#define PNX8550_INT_GPIO5 (PNX8550_INT_GIC_MIN+63)
121#define PNX8550_INT_GPIO6 (PNX8550_INT_GIC_MIN+64)
122#define PNX8550_INT_GPIO7 (PNX8550_INT_GIC_MIN+65)
123#define PNX8550_INT_PMAN_SECURITY (PNX8550_INT_GIC_MIN+66)
124#define PNX8550_INT_I2C3 (PNX8550_INT_GIC_MIN+67)
125#define PNX8550_INT_RESERVED_68 (PNX8550_INT_GIC_MIN+68)
126#define PNX8550_INT_SPDI2 (PNX8550_INT_GIC_MIN+69)
127
128#define PNX8550_INT_I2C4 (PNX8550_INT_GIC_MIN+70)
129
130// Timer are 3 exceptions connected to cp0's 7th hardware exception
131#define PNX8550_INT_TIMER_TOTINT 3
132#define PNX8550_INT_TIMER_MIN (PNX8550_INT_GIC_MAX+1)
133#define PNX8550_INT_TIMER_MAX (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
134
135#define PNX8550_INT_TIMER1 (PNX8550_INT_TIMER_MIN+0)
136#define PNX8550_INT_TIMER2 (PNX8550_INT_TIMER_MIN+1)
137#define PNX8550_INT_TIMER3 (PNX8550_INT_TIMER_MIN+2)
138#define PNX8550_INT_WATCHDOG PNX8550_INT_TIMER3
139
140#endif
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
new file mode 100644
index 000000000000..57102fa9da51
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
@@ -0,0 +1,262 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 Embedded Alley Solutions, Inc
7 */
8#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
9#define __ASM_MACH_KERNEL_ENTRY_INIT_H
10
11#include <asm/cacheops.h>
12#include <asm/addrspace.h>
13
14#define CO_CONFIGPR_VALID 0x3F1F41FF /* valid bits to write to ConfigPR */
15#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
16#define CACHE_OPC 0xBC000000 /* MIPS cache instruction opcode */
17#define ICACHE_LINE_SIZE 32 /* Instruction cache line size bytes */
18#define DCACHE_LINE_SIZE 32 /* Data cache line size in bytes */
19
20#define ICACHE_SET_COUNT 256 /* Instruction cache set count */
21#define DCACHE_SET_COUNT 128 /* Data cache set count */
22
23#define ICACHE_SET_SIZE (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
24#define DCACHE_SET_SIZE (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
25
26 .macro kernel_entry_setup
27 .set push
28 .set noreorder
29 /*
30 * PNX8550 entry point, when running a non compressed
31 * kernel. When loading a zImage, the head.S code in
32 * arch/mips/zboot/pnx8550 will init the caches and,
33 * decompress the kernel, and branch to kernel_entry.
34 */
35cache_begin: li t0, (1<<28)
36 mtc0 t0, CP0_STATUS /* cp0 usable */
37 HAZARD_CP0
38
39 mtc0 zero, CP0_CAUSE
40 HAZARD_CP0
41
42
43 /* Set static virtual to phys address translation and TLB disabled */
44 mfc0 t0, CP0_CONFIG, 7
45 HAZARD_CP0
46
47 and t0,~((1<<19) | (1<<20)) /* TLB/MAP cleared */
48 mtc0 t0, CP0_CONFIG, 7
49 HAZARD_CP0
50
51 /* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
52
53 init_icache
54 nop
55 init_dcache
56 nop
57
58 cachePr4450ICReset
59 nop
60
61 cachePr4450DCReset
62 nop
63
64 /* read ConfigPR into t0 */
65 mfc0 t0, CP0_CONFIG, 7
66 HAZARD_CP0
67
68 /* enable the TLB */
69 or t0, (1<<19)
70
71 /* disable the ICACHE: at least 10x slower */
72 /* or t0, (1<<26) */
73
74 /* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set */
75 /* or t0, (1<<27) */
76
77 and t0, CO_CONFIGPR_VALID
78
79 /* enable TLB. */
80 mtc0 t0, CP0_CONFIG, 7
81 HAZARD_CP0
82cache_end:
83 /* Setup CMEM_0 to MMIO address space, 2MB */
84 lui t0, 0x1BE0
85 addi t0, t0, 0x3
86 mtc0 $8, $22, 4
87 nop
88
89 /* Setup CMEM_1, 128MB */
90 lui t0, 0x1000
91 addi t0, t0, 0xf
92 mtc0 $8, $22, 5
93 nop
94
95
96 /* Setup CMEM_2, 32MB */
97 lui t0, 0x1C00
98 addi t0, t0, 0xb
99 mtc0 $8, $22, 6
100 nop
101
102 /* Setup CMEM_3, 0MB */
103 lui t0, 0x0
104 addi t0, t0, 0x0
105 mtc0 $8, $22, 7
106 nop
107
108 /* Enable cache */
109 mfc0 t0, CP0_CONFIG
110 HAZARD_CP0
111 and t0, t0, 0xFFFFFFF8
112 or t0, t0, 3
113 mtc0 t0, CP0_CONFIG
114 HAZARD_CP0
115 .set pop
116 .endm
117
118 .macro init_icache
119 .set push
120 .set noreorder
121
122 /* Get Cache Configuration */
123 mfc0 t3, CP0_CONFIG, 1
124 HAZARD_CP0
125
126 /* get cache Line size */
127
128 srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */
129 andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */
130 beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
131 nop
132 addiu t0, t1, 1
133 ori t1, zero, 1
134 sllv t1, t1, t0
135
136 /* get max cache Index */
137 srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */
138 andi t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
139 addiu t0, t2, 6
140 ori t2, zero, 1
141 sllv t2, t2, t0
142
143 /* get max cache way */
144 srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */
145 andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
146 addiu t3, t3, 1
147
148 /* total no of cache lines */
149 multu t2, t3 /* max index * max way */
150 mflo t2
151 addiu t2, t2, -1
152
153 move t0, zero
154pr4450_next_instruction_cache_set:
155 cache Index_Invalidate_I, 0(t0)
156 addu t0, t0, t1 /* add bytes in a line */
157 bne t2, zero, pr4450_next_instruction_cache_set
158 addiu t2, t2, -1 /* reduce no of lines to invalidate by one */
159pr4450_instr_cache_invalidated:
160 .set pop
161 .endm
162
163 .macro init_dcache
164 .set push
165 .set noreorder
166 move t1, zero
167
168 /* Store Tag Information */
169 mtc0 zero, CP0_TAGLO, 0
170 HAZARD_CP0
171
172 mtc0 zero, CP0_TAGHI, 0
173 HAZARD_CP0
174
175 /* Cache size is 16384 = 512 lines x 32 bytes per line */
176 or t2, zero, (128*4)-1 /* 512 lines */
177 /* Invalidate all lines */
1782:
179 cache Index_Store_Tag_D, 0(t1)
180 addiu t2, t2, -1
181 bne t2, zero, 2b
182 addiu t1, t1, 32 /* 32 bytes in a line */
183 .set pop
184 .endm
185
186 .macro cachePr4450ICReset
187 .set push
188 .set noreorder
189
190 /* Save CP0 status reg on entry; */
191 /* disable interrupts during cache reset */
192 mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
193 HAZARD_CP0
194
195 mtc0 zero, CP0_STATUS /* disable CPU interrupts */
196 HAZARD_CP0
197
198 or t1, zero, zero /* T1 = starting cache index (0) */
199 ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
200
201 icache_invd_loop:
202 /* 9 == register t1 */
203 .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
204 (0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */
205 .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
206 (1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */
207
208 addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
209 bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
210 addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
211
212 /* Initialize the latches in the instruction cache tag */
213 /* that drive the way selection tri-state bus drivers, by doing a */
214 /* dummy load while the instruction cache is still disabled. */
215 /* TODO: Is this needed ? */
216 la t1, KSEG0 /* T1 = cached memory base address */
217 lw zero, 0x0000(t1) /* (dummy read of first memory word) */
218
219 mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
220 HAZARD_CP0
221 .set pop
222 .endm
223
224 .macro cachePr4450DCReset
225 .set push
226 .set noreorder
227 mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
228 HAZARD_CP0
229 mtc0 zero, CP0_STATUS /* disable CPU interrupts */
230 HAZARD_CP0
231
232 /* Writeback/invalidate entire data cache sets/ways/lines */
233 or t1, zero, zero /* T1 = starting cache index (0) */
234 ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
235
236 dcache_wbinvd_loop:
237 /* 9 == register t1 */
238 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
239 (0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */
240 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
241 (1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */
242 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
243 (2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */
244 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
245 (3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */
246
247 addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
248 bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
249 addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
250
251 /* Initialize the latches in the data cache tag that drive the way
252 selection tri-state bus drivers, by doing a dummy load while the
253 data cache is still in the disabled mode. TODO: Is this needed ? */
254 la t1, KSEG0 /* T1 = cached memory base address */
255 lw zero, 0x0000(t1) /* (dummy read of first memory word) */
256
257 mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
258 HAZARD_CP0
259 .set pop
260 .endm
261
262#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
diff --git a/include/asm-mips/mach-pnx8550/nand.h b/include/asm-mips/mach-pnx8550/nand.h
new file mode 100644
index 000000000000..aefbc514ab09
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/nand.h
@@ -0,0 +1,121 @@
1#ifndef __PNX8550_NAND_H
2#define __PNX8550_NAND_H
3
4#define PNX8550_NAND_BASE_ADDR 0x10000000
5#define PNX8550_PCIXIO_BASE 0xBBE40000
6
7#define PNX8550_DMA_EXT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
8#define PNX8550_DMA_INT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
9#define PNX8550_DMA_TRANS_SIZE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
10#define PNX8550_DMA_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
11#define PNX8550_XIO_SEL0 *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
12#define PNX8550_GPXIO_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
13#define PNX8550_GPXIO_WR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
14#define PNX8550_GPXIO_RD *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
15#define PNX8550_GPXIO_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
16#define PNX8550_XIO_FLASH_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
17#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
18#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
19#define PNX8550_GPXIO_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
20#define PNX8550_DMA_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
21#define PNX8550_DMA_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
22#define PNX8550_DMA_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
23
24#define PNX8550_XIO_SEL0_EN_16BIT 0x00800000
25#define PNX8550_XIO_SEL0_USE_ACK 0x00400000
26#define PNX8550_XIO_SEL0_REN_HIGH 0x00100000
27#define PNX8550_XIO_SEL0_REN_LOW 0x00040000
28#define PNX8550_XIO_SEL0_WEN_HIGH 0x00010000
29#define PNX8550_XIO_SEL0_WEN_LOW 0x00004000
30#define PNX8550_XIO_SEL0_WAIT 0x00000200
31#define PNX8550_XIO_SEL0_OFFSET 0x00000020
32#define PNX8550_XIO_SEL0_TYPE_68360 0x00000000
33#define PNX8550_XIO_SEL0_TYPE_NOR 0x00000008
34#define PNX8550_XIO_SEL0_TYPE_NAND 0x00000010
35#define PNX8550_XIO_SEL0_TYPE_IDE 0x00000018
36#define PNX8550_XIO_SEL0_SIZE_8MB 0x00000000
37#define PNX8550_XIO_SEL0_SIZE_16MB 0x00000002
38#define PNX8550_XIO_SEL0_SIZE_32MB 0x00000004
39#define PNX8550_XIO_SEL0_SIZE_64MB 0x00000006
40#define PNX8550_XIO_SEL0_ENAB 0x00000001
41
42#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT) | \
43 (PNX8550_XIO_SEL0_REN_HIGH*0)| \
44 (PNX8550_XIO_SEL0_REN_LOW*2) | \
45 (PNX8550_XIO_SEL0_WEN_HIGH*0)| \
46 (PNX8550_XIO_SEL0_WEN_LOW*2) | \
47 (PNX8550_XIO_SEL0_WAIT*4) | \
48 (PNX8550_XIO_SEL0_OFFSET*0) | \
49 (PNX8550_XIO_SEL0_TYPE_NAND) | \
50 (PNX8550_XIO_SEL0_SIZE_32MB) | \
51 (PNX8550_XIO_SEL0_ENAB))
52
53#define PNX8550_GPXIO_PENDING 0x00000200
54#define PNX8550_GPXIO_DONE 0x00000100
55#define PNX8550_GPXIO_CLR_DONE 0x00000080
56#define PNX8550_GPXIO_INIT 0x00000040
57#define PNX8550_GPXIO_READ_CMD 0x00000010
58#define PNX8550_GPXIO_BEN 0x0000000F
59
60#define PNX8550_XIO_FLASH_64MB 0x00200000
61#define PNX8550_XIO_FLASH_INC_DATA 0x00100000
62#define PNX8550_XIO_FLASH_CMD_PH 0x000C0000
63#define PNX8550_XIO_FLASH_CMD_PH2 0x00080000
64#define PNX8550_XIO_FLASH_CMD_PH1 0x00040000
65#define PNX8550_XIO_FLASH_CMD_PH0 0x00000000
66#define PNX8550_XIO_FLASH_ADR_PH 0x00030000
67#define PNX8550_XIO_FLASH_ADR_PH3 0x00030000
68#define PNX8550_XIO_FLASH_ADR_PH2 0x00020000
69#define PNX8550_XIO_FLASH_ADR_PH1 0x00010000
70#define PNX8550_XIO_FLASH_ADR_PH0 0x00000000
71#define PNX8550_XIO_FLASH_CMD_B(x) ((x<<8) & 0x0000FF00)
72#define PNX8550_XIO_FLASH_CMD_A(x) (x & 0x000000FF)
73
74#define PNX8550_XIO_INT_ACK 0x00004000
75#define PNX8550_XIO_INT_COMPL 0x00002000
76#define PNX8550_XIO_INT_NONSUP 0x00000200
77#define PNX8550_XIO_INT_ABORT 0x00000004
78
79#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
80#define PNX8550_DMA_CTRL_SND2XIO 0x00000200
81#define PNX8550_DMA_CTRL_FIX_ADDR 0x00000100
82#define PNX8550_DMA_CTRL_BURST_8 0x00000000
83#define PNX8550_DMA_CTRL_BURST_16 0x00000020
84#define PNX8550_DMA_CTRL_BURST_32 0x00000040
85#define PNX8550_DMA_CTRL_BURST_64 0x00000060
86#define PNX8550_DMA_CTRL_BURST_128 0x00000080
87#define PNX8550_DMA_CTRL_BURST_256 0x000000A0
88#define PNX8550_DMA_CTRL_BURST_512 0x000000C0
89#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
90#define PNX8550_DMA_CTRL_INIT_DMA 0x00000010
91#define PNX8550_DMA_CTRL_CMD_TYPE 0x0000000F
92
93/* see PCI system arch, page 100 for the full list: */
94#define PNX8550_DMA_CTRL_PCI_CMD_READ 0x00000006
95#define PNX8550_DMA_CTRL_PCI_CMD_WRITE 0x00000007
96
97#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14)
98#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12)
99#define PNX8550_DMA_INT_STAT_DMA_ERR (1<<9)
100#define PNX8550_DMA_INT_STAT_PERR5 (1<<5)
101#define PNX8550_DMA_INT_STAT_PERR4 (1<<4)
102#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2)
103#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1)
104
105#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14)
106#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12)
107#define PNX8550_DMA_INT_EN_DMA_ERR (1<<9)
108#define PNX8550_DMA_INT_EN_PERR5 (1<<5)
109#define PNX8550_DMA_INT_EN_PERR4 (1<<4)
110#define PNX8550_DMA_INT_EN_M_ABORT (1<<2)
111#define PNX8550_DMA_INT_EN_T_ABORT (1<<1)
112
113#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14)
114#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12)
115#define PNX8550_DMA_INT_CLR_DMA_ERR (1<<9)
116#define PNX8550_DMA_INT_CLR_PERR5 (1<<5)
117#define PNX8550_DMA_INT_CLR_PERR4 (1<<4)
118#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2)
119#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1)
120
121#endif
diff --git a/include/asm-mips/mach-pnx8550/pci.h b/include/asm-mips/mach-pnx8550/pci.h
new file mode 100644
index 000000000000..b921508d701b
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/pci.h
@@ -0,0 +1,185 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PCI specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_PCI_H
23#define __PNX8550_PCI_H
24
25#include <linux/types.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28#include <linux/init.h>
29
30#define PCI_ACCESS_READ 0
31#define PCI_ACCESS_WRITE 1
32
33#define PCI_CMD_IOR 0x20
34#define PCI_CMD_IOW 0x30
35#define PCI_CMD_CONFIG_READ 0xa0
36#define PCI_CMD_CONFIG_WRITE 0xb0
37
38#define PCI_IO_TIMEOUT 1000
39#define PCI_IO_RETRY 5
40/* Timeout for IO and CFG accesses.
41 This is in 1/1024 th of a jiffie(=10ms)
42 i.e. approx 10us */
43#define PCI_IO_JIFFIES_TIMEOUT 40
44#define PCI_IO_JIFFIES_SHIFT 10
45
46#define PCI_BYTE_ENABLE_MASK 0x0000000f
47#define PCI_CFG_BUS_SHIFT 16
48#define PCI_CFG_FUNC_SHIFT 8
49#define PCI_CFG_REG_SHIFT 2
50
51#define PCI_BASE 0x1be00000
52#define PCI_SETUP 0x00040010
53#define PCI_DIS_REQGNT (1<<30)
54#define PCI_DIS_REQGNTA (1<<29)
55#define PCI_DIS_REQGNTB (1<<28)
56#define PCI_D2_SUPPORT (1<<27)
57#define PCI_D1_SUPPORT (1<<26)
58#define PCI_EN_TA (1<<24)
59#define PCI_EN_PCI2MMI (1<<23)
60#define PCI_EN_XIO (1<<22)
61#define PCI_BASE18_PREF (1<<21)
62#define SIZE_16M 0x3
63#define SIZE_32M 0x4
64#define SIZE_64M 0x5
65#define SIZE_128M 0x6
66#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
67#define PCI_SETUP_BASE18_EN (1<<17)
68#define PCI_SETUP_BASE14_PREF (1<<16)
69#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
70#define PCI_SETUP_BASE14_EN (1<<11)
71#define PCI_SETUP_BASE10_PREF (1<<10)
72#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
73#define PCI_SETUP_CFGMANAGE_EN (1<<1)
74#define PCI_SETUP_PCIARB_EN (1<<0)
75
76#define PCI_CTRL 0x040014
77#define PCI_SWPB_DCS_PCI (1<<16)
78#define PCI_SWPB_PCI_PCI (1<<15)
79#define PCI_SWPB_PCI_DCS (1<<14)
80#define PCI_REG_WR_POST (1<<13)
81#define PCI_XIO_WR_POST (1<<12)
82#define PCI_PCI2_WR_POST (1<<13)
83#define PCI_PCI1_WR_POST (1<<12)
84#define PCI_SERR_SEEN (1<<11)
85#define PCI_B10_SPEC_RD (1<<6)
86#define PCI_B14_SPEC_RD (1<<5)
87#define PCI_B18_SPEC_RD (1<<4)
88#define PCI_B10_NOSUBWORD (1<<3)
89#define PCI_B14_NOSUBWORD (1<<2)
90#define PCI_B18_NOSUBWORD (1<<1)
91#define PCI_RETRY_TMREN (1<<0)
92
93#define PCI_BASE1_LO 0x040018
94#define PCI_BASE1_HI 0x04001C
95#define PCI_BASE2_LO 0x040020
96#define PCI_BASE2_HI 0x040024
97#define PCI_RDLIFETIM 0x040028
98#define PCI_GPPM_ADDR 0x04002C
99#define PCI_GPPM_WDAT 0x040030
100#define PCI_GPPM_RDAT 0x040034
101#define PCI_GPPM_CTRL 0x040038
102#define GPPM_DONE (1<<10)
103#define INIT_PCI_CYCLE (1<<9)
104#define GPPM_CMD(X) (((X)&0xf)<<4)
105#define GPPM_BYTEEN(X) ((X)&0xf)
106#define PCI_UNLOCKREG 0x04003C
107#define UNLOCK_SSID(X) (((X)&0xff)<<8)
108#define UNLOCK_SETUP(X) (((X)&0xff)<<0)
109#define UNLOCK_MAGIC 0xCA
110#define PCI_DEV_VEND_ID 0x040040
111#define DEVICE_ID(X) (((X)>>16)&0xffff)
112#define VENDOR_ID(X) (((X)&0xffff))
113#define PCI_CFG_CMDSTAT 0x040044
114#define PCI_CFG_STATUS(X) (((X)>>16)&0xffff)
115#define PCI_CFG_COMMAND(X) ((X)&0xffff)
116#define PCI_CLASS_REV 0x040048
117#define PCI_CLASSCODE(X) (((X)>>8)&0xffffff)
118#define PCI_REVID(X) ((X)&0xff)
119#define PCI_LAT_TMR 0x04004c
120#define PCI_BASE10 0x040050
121#define PCI_BASE14 0x040054
122#define PCI_BASE18 0x040058
123#define PCI_SUBSYS_ID 0x04006c
124#define PCI_CAP_PTR 0x040074
125#define PCI_CFG_MISC 0x04007c
126#define PCI_PMC 0x040080
127#define PCI_PWR_STATE 0x040084
128#define PCI_IO 0x040088
129#define PCI_SLVTUNING 0x04008C
130#define PCI_DMATUNING 0x040090
131#define PCI_DMAEADDR 0x040800
132#define PCI_DMAIADDR 0x040804
133#define PCI_DMALEN 0x040808
134#define PCI_DMACTRL 0x04080C
135#define PCI_XIOCTRL 0x040810
136#define PCI_SEL0PROF 0x040814
137#define PCI_SEL1PROF 0x040818
138#define PCI_SEL2PROF 0x04081C
139#define PCI_GPXIOADDR 0x040820
140#define PCI_NANDCTRLS 0x400830
141#define PCI_SEL3PROF 0x040834
142#define PCI_SEL4PROF 0x040838
143#define PCI_GPXIO_STAT 0x040FB0
144#define PCI_GPXIO_IMASK 0x040FB4
145#define PCI_GPXIO_ICLR 0x040FB8
146#define PCI_GPXIO_ISET 0x040FBC
147#define PCI_GPPM_STATUS 0x040FC0
148#define GPPM_DONE (1<<10)
149#define GPPM_ERR (1<<9)
150#define GPPM_MPAR_ERR (1<<8)
151#define GPPM_PAR_ERR (1<<7)
152#define GPPM_R_MABORT (1<<2)
153#define GPPM_R_TABORT (1<<1)
154#define PCI_GPPM_IMASK 0x040FC4
155#define PCI_GPPM_ICLR 0x040FC8
156#define PCI_GPPM_ISET 0x040FCC
157#define PCI_DMA_STATUS 0x040FD0
158#define PCI_DMA_IMASK 0x040FD4
159#define PCI_DMA_ICLR 0x040FD8
160#define PCI_DMA_ISET 0x040FDC
161#define PCI_ISTATUS 0x040FE0
162#define PCI_IMASK 0x040FE4
163#define PCI_ICLR 0x040FE8
164#define PCI_ISET 0x040FEC
165#define PCI_MOD_ID 0x040FFC
166
167/*
168 * PCI configuration cycle AD bus definition
169 */
170/* Type 0 */
171#define PCI_CFG_TYPE0_REG_SHF 0
172#define PCI_CFG_TYPE0_FUNC_SHF 8
173
174/* Type 1 */
175#define PCI_CFG_TYPE1_REG_SHF 0
176#define PCI_CFG_TYPE1_FUNC_SHF 8
177#define PCI_CFG_TYPE1_DEV_SHF 11
178#define PCI_CFG_TYPE1_BUS_SHF 16
179
180/*
181 * Ethernet device DP83816 definition
182 */
183#define DP83816_IRQ_ETHER 66
184
185#endif
diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h
new file mode 100644
index 000000000000..e32b9a23d70e
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/uart.h
@@ -0,0 +1,16 @@
1#ifndef __IP3106_UART_H
2#define __IP3106_UART_H
3
4#include <int.h>
5
6/* early macros for kgdb use. fixme: clean this up */
7
8#define UART_BASE 0xbbe4a000 /* PNX8550 */
9
10#define PNX8550_UART_PORT0 (UART_BASE)
11#define PNX8550_UART_PORT1 (UART_BASE + 0x1000)
12
13#define PNX8550_UART_INT(x) (PNX8550_INT_GIC_MIN+19+x)
14#define IRQ_TO_UART(x) (x-PNX8550_INT_GIC_MIN-19)
15
16#endif
diff --git a/include/asm-mips/mach-pnx8550/usb.h b/include/asm-mips/mach-pnx8550/usb.h
new file mode 100644
index 000000000000..483b7fc65d41
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/usb.h
@@ -0,0 +1,32 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * USB specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_USB_H
23#define __PNX8550_USB_H
24
25/*
26 * USB Host controller
27 */
28
29#define PNX8550_USB_OHCI_OP_BASE 0x1be48000
30#define PNX8550_USB_OHCI_OP_LEN 0x1000
31
32#endif
diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
index f48736032b2a..79f9b064c864 100644
--- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
@@ -14,7 +14,7 @@
14 14
15#define cpu_has_tlb 1 15#define cpu_has_tlb 1
16#define cpu_has_4kex 1 16#define cpu_has_4kex 1
17#define cpu_has_4ktlb 1 17#define cpu_has_4kcache 1
18#define cpu_has_fpu 1 18#define cpu_has_fpu 1
19#define cpu_has_32fpr 1 19#define cpu_has_32fpr 1
20#define cpu_has_counter 1 20#define cpu_has_counter 1
@@ -31,6 +31,7 @@
31#define cpu_has_vtag_icache 0 31#define cpu_has_vtag_icache 0
32#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) 32#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
33#define cpu_has_ic_fills_f_dc 0 33#define cpu_has_ic_fills_f_dc 0
34#define cpu_has_dsp 0
34#define cpu_has_nofpuex 0 35#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1 36#define cpu_has_64bits 1
36 37
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
index a3a2cc6014b2..193a666cd131 100644
--- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
25#define cpu_has_vtag_icache 1 25#define cpu_has_vtag_icache 1
26#define cpu_has_dc_aliases 0 26#define cpu_has_dc_aliases 0
27#define cpu_has_ic_fills_f_dc 0 27#define cpu_has_ic_fills_f_dc 0
28#define cpu_has_dsp 0
28#define cpu_icache_snoops_remote_store 0 29#define cpu_icache_snoops_remote_store 0
29 30
30#define cpu_has_nofpuex 0 31#define cpu_has_nofpuex 0
diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-sim/cpu-feature-overrides.h
new file mode 100644
index 000000000000..cadbe8eda79c
--- /dev/null
+++ b/include/asm-mips/mach-sim/cpu-feature-overrides.h
@@ -0,0 +1,66 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Chris Dearman
7 */
8#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
10
11#include <linux/config.h>
12
13/*
14 * CPU feature overrides for MIPS boards
15 */
16#ifdef CONFIG_CPU_MIPS32
17#define cpu_has_tlb 1
18#define cpu_has_4kex 1
19#define cpu_has_4kcache 1
20#define cpu_has_fpu 0
21/* #define cpu_has_32fpr ? */
22#define cpu_has_counter 1
23/* #define cpu_has_watch ? */
24#define cpu_has_divec 1
25#define cpu_has_vce 0
26/* #define cpu_has_cache_cdex_p ? */
27/* #define cpu_has_cache_cdex_s ? */
28/* #define cpu_has_prefetch ? */
29#define cpu_has_mcheck 1
30/* #define cpu_has_ejtag ? */
31#define cpu_has_llsc 1
32/* #define cpu_has_vtag_icache ? */
33/* #define cpu_has_dc_aliases ? */
34/* #define cpu_has_ic_fills_f_dc ? */
35#define cpu_has_nofpuex 0
36/* #define cpu_has_64bits ? */
37/* #define cpu_has_64bit_zero_reg ? */
38/* #define cpu_has_subset_pcaches ? */
39#endif
40
41#ifdef CONFIG_CPU_MIPS64
42#define cpu_has_tlb 1
43#define cpu_has_4kex 1
44#define cpu_has_4kcache 1
45/* #define cpu_has_fpu ? */
46/* #define cpu_has_32fpr ? */
47#define cpu_has_counter 1
48/* #define cpu_has_watch ? */
49#define cpu_has_divec 1
50#define cpu_has_vce 0
51/* #define cpu_has_cache_cdex_p ? */
52/* #define cpu_has_cache_cdex_s ? */
53/* #define cpu_has_prefetch ? */
54#define cpu_has_mcheck 1
55/* #define cpu_has_ejtag ? */
56#define cpu_has_llsc 1
57/* #define cpu_has_vtag_icache ? */
58/* #define cpu_has_dc_aliases ? */
59/* #define cpu_has_ic_fills_f_dc ? */
60#define cpu_has_nofpuex 0
61/* #define cpu_has_64bits ? */
62/* #define cpu_has_64bit_zero_reg ? */
63/* #define cpu_has_subset_pcaches ? */
64#endif
65
66#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
index 58603e3daca6..463d051f4683 100644
--- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
@@ -25,6 +25,7 @@
25#define cpu_has_vtag_icache 0 25#define cpu_has_vtag_icache 0
26#define cpu_has_dc_aliases 0 26#define cpu_has_dc_aliases 0
27#define cpu_has_ic_fills_f_dc 0 27#define cpu_has_ic_fills_f_dc 0
28#define cpu_has_dsp 0
28#define cpu_icache_snoops_remote_store 0 29#define cpu_icache_snoops_remote_store 0
29 30
30#define cpu_has_nofpuex 0 31#define cpu_has_nofpuex 0
@@ -36,10 +37,4 @@
36#define cpu_icache_line_size() 32 37#define cpu_icache_line_size() 32
37#define cpu_scache_line_size() 32 38#define cpu_scache_line_size() 32
38 39
39/*
40 * On the RM9000 we need to ensure that I-cache lines being fetches only
41 * contain valid instructions are funny things will happen.
42 */
43#define PLAT_TRAMPOLINE_STUFF_LINE 32UL
44
45#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */ 40#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index 65d1d16eab16..25b6ffc26623 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -66,6 +66,7 @@
66#define MIPS_REVISION_CORID_CORE_EMUL 6 66#define MIPS_REVISION_CORID_CORE_EMUL 6
67#define MIPS_REVISION_CORID_CORE_FPGA2 7 67#define MIPS_REVISION_CORID_CORE_FPGA2 7
68#define MIPS_REVISION_CORID_CORE_FPGAR2 8 68#define MIPS_REVISION_CORID_CORE_FPGAR2 8
69#define MIPS_REVISION_CORID_CORE_FPGA3 9
69 70
70/**** Artificial corid defines ****/ 71/**** Artificial corid defines ****/
71/* 72/*
@@ -79,4 +80,10 @@
79 80
80extern unsigned int mips_revision_corid; 81extern unsigned int mips_revision_corid;
81 82
83#ifdef CONFIG_PCI
84extern void mips_pcibios_init(void);
85#else
86#define mips_pcibios_init() do { } while (0)
87#endif
88
82#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 89#endif /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
index 376181882e81..da6cc2fbbc78 100644
--- a/include/asm-mips/mips-boards/maltaint.h
+++ b/include/asm-mips/mips-boards/maltaint.h
@@ -25,9 +25,63 @@
25#ifndef _MIPS_MALTAINT_H 25#ifndef _MIPS_MALTAINT_H
26#define _MIPS_MALTAINT_H 26#define _MIPS_MALTAINT_H
27 27
28/* Number of IRQ supported on hw interrupt 0. */ 28/*
29#define MALTAINT_END 16 29 * Interrupts 0..15 are used for Malta ISA compatible interrupts
30 */
31#define MALTA_INT_BASE 0
32
33/*
34 * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
35 */
36#define MIPSCPU_INT_BASE 16
37
38/* CPU interrupt offsets */
39#define MIPSCPU_INT_SW0 0
40#define MIPSCPU_INT_SW1 1
41#define MIPSCPU_INT_MB0 2
42#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
43#define MIPSCPU_INT_MB1 3
44#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
45#define MIPSCPU_INT_MB2 4
46#define MIPSCPU_INT_MB3 5
47#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
48#define MIPSCPU_INT_MB4 6
49#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4
50#define MIPSCPU_INT_CPUCTR 7
51
52/*
53 * Interrupts 64..127 are used for Soc-it Classic interrupts
54 */
55#define MSC01C_INT_BASE 64
56
57/* SOC-it Classic interrupt offsets */
58#define MSC01C_INT_TMR 0
59#define MSC01C_INT_PCI 1
60
61/*
62 * Interrupts 64..127 are used for Soc-it EIC interrupts
63 */
64#define MSC01E_INT_BASE 64
65
66/* SOC-it EIC interrupt offsets */
67#define MSC01E_INT_SW0 1
68#define MSC01E_INT_SW1 2
69#define MSC01E_INT_MB0 3
70#define MSC01E_INT_I8259A MSC01E_INT_MB0
71#define MSC01E_INT_MB1 4
72#define MSC01E_INT_SMI MSC01E_INT_MB1
73#define MSC01E_INT_MB2 5
74#define MSC01E_INT_MB3 6
75#define MSC01E_INT_COREHI MSC01E_INT_MB3
76#define MSC01E_INT_MB4 7
77#define MSC01E_INT_CORELO MSC01E_INT_MB4
78#define MSC01E_INT_TMR 8
79#define MSC01E_INT_PCI 9
80#define MSC01E_INT_PERFCTR 10
81#define MSC01E_INT_CPUCTR 11
30 82
83#ifndef __ASSEMBLY__
31extern void maltaint_init(void); 84extern void maltaint_init(void);
85#endif
32 86
33#endif /* !(_MIPS_MALTAINT_H) */ 87#endif /* !(_MIPS_MALTAINT_H) */
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
index 6b2a87a38f4b..8eaefb837b9d 100644
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ b/include/asm-mips/mips-boards/msc01_pci.h
@@ -1,8 +1,9 @@
1/* 1/*
2 * PCI Register definitions for the MIPS System Controller. 2 * PCI Register definitions for the MIPS System Controller.
3 * 3 *
4 * Carsten Langgaard, carstenl@mips.com 4 * Copyright (C) 2002, 2005 MIPS Technologies, Inc. All rights reserved.
5 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. 5 * Authors: Carsten Langgaard <carstenl@mips.com>
6 * Maciej W. Rozycki <macro@mips.com>
6 * 7 *
7 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -29,22 +30,22 @@
29#define MSC01_PCI_CFGADDR_OFS 0x0610 30#define MSC01_PCI_CFGADDR_OFS 0x0610
30#define MSC01_PCI_CFGDATA_OFS 0x0618 31#define MSC01_PCI_CFGDATA_OFS 0x0618
31#define MSC01_PCI_IACK_OFS 0x0620 32#define MSC01_PCI_IACK_OFS 0x0620
32#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */ 33#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */
33#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */ 34#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */
34#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */ 35#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */
35#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */ 36#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */
36#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */ 37#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */
37#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */ 38#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */
38#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */ 39#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */
39#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */ 40#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */
40#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */ 41#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */
41#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */ 42#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */
42#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */ 43#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */
43#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */ 44#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */
44#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */ 45#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */
45#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */ 46#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */
46#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */ 47#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */
47#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */ 48#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */
48#define MSC01_PCI_BAR0_OFS 0x2220 49#define MSC01_PCI_BAR0_OFS 0x2220
49#define MSC01_PCI_CFG_OFS 0x2380 50#define MSC01_PCI_CFG_OFS 0x2380
50#define MSC01_PCI_SWAP_OFS 0x2388 51#define MSC01_PCI_SWAP_OFS 0x2388
@@ -86,73 +87,73 @@
86#define MSC01_PCI_P2SCMAPL_MAP_SHF 24 87#define MSC01_PCI_P2SCMAPL_MAP_SHF 24
87#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000 88#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000
88 89
89#define MSC01_PCI_INTCFG_RST_SHF 10 90#define MSC01_PCI_INTCFG_RST_SHF 10
90#define MSC01_PCI_INTCFG_RST_MSK 0x00000400 91#define MSC01_PCI_INTCFG_RST_MSK 0x00000400
91#define MSC01_PCI_INTCFG_RST_BIT 0x00000400 92#define MSC01_PCI_INTCFG_RST_BIT 0x00000400
92#define MSC01_PCI_INTCFG_MWE_SHF 9 93#define MSC01_PCI_INTCFG_MWE_SHF 9
93#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200 94#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200
94#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200 95#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200
95#define MSC01_PCI_INTCFG_DTO_SHF 8 96#define MSC01_PCI_INTCFG_DTO_SHF 8
96#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100 97#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100
97#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100 98#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100
98#define MSC01_PCI_INTCFG_MA_SHF 7 99#define MSC01_PCI_INTCFG_MA_SHF 7
99#define MSC01_PCI_INTCFG_MA_MSK 0x00000080 100#define MSC01_PCI_INTCFG_MA_MSK 0x00000080
100#define MSC01_PCI_INTCFG_MA_BIT 0x00000080 101#define MSC01_PCI_INTCFG_MA_BIT 0x00000080
101#define MSC01_PCI_INTCFG_TA_SHF 6 102#define MSC01_PCI_INTCFG_TA_SHF 6
102#define MSC01_PCI_INTCFG_TA_MSK 0x00000040 103#define MSC01_PCI_INTCFG_TA_MSK 0x00000040
103#define MSC01_PCI_INTCFG_TA_BIT 0x00000040 104#define MSC01_PCI_INTCFG_TA_BIT 0x00000040
104#define MSC01_PCI_INTCFG_RTY_SHF 5 105#define MSC01_PCI_INTCFG_RTY_SHF 5
105#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020 106#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020
106#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020 107#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020
107#define MSC01_PCI_INTCFG_MWP_SHF 4 108#define MSC01_PCI_INTCFG_MWP_SHF 4
108#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010 109#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010
109#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010 110#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010
110#define MSC01_PCI_INTCFG_MRP_SHF 3 111#define MSC01_PCI_INTCFG_MRP_SHF 3
111#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008 112#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008
112#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008 113#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008
113#define MSC01_PCI_INTCFG_SWP_SHF 2 114#define MSC01_PCI_INTCFG_SWP_SHF 2
114#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004 115#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004
115#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004 116#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004
116#define MSC01_PCI_INTCFG_SRP_SHF 1 117#define MSC01_PCI_INTCFG_SRP_SHF 1
117#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002 118#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002
118#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002 119#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002
119#define MSC01_PCI_INTCFG_SE_SHF 0 120#define MSC01_PCI_INTCFG_SE_SHF 0
120#define MSC01_PCI_INTCFG_SE_MSK 0x00000001 121#define MSC01_PCI_INTCFG_SE_MSK 0x00000001
121#define MSC01_PCI_INTCFG_SE_BIT 0x00000001 122#define MSC01_PCI_INTCFG_SE_BIT 0x00000001
122 123
123#define MSC01_PCI_INTSTAT_RST_SHF 10 124#define MSC01_PCI_INTSTAT_RST_SHF 10
124#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400 125#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400
125#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400 126#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400
126#define MSC01_PCI_INTSTAT_MWE_SHF 9 127#define MSC01_PCI_INTSTAT_MWE_SHF 9
127#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200 128#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200
128#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200 129#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200
129#define MSC01_PCI_INTSTAT_DTO_SHF 8 130#define MSC01_PCI_INTSTAT_DTO_SHF 8
130#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100 131#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100
131#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100 132#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100
132#define MSC01_PCI_INTSTAT_MA_SHF 7 133#define MSC01_PCI_INTSTAT_MA_SHF 7
133#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080 134#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080
134#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080 135#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080
135#define MSC01_PCI_INTSTAT_TA_SHF 6 136#define MSC01_PCI_INTSTAT_TA_SHF 6
136#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040 137#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040
137#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040 138#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040
138#define MSC01_PCI_INTSTAT_RTY_SHF 5 139#define MSC01_PCI_INTSTAT_RTY_SHF 5
139#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020 140#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020
140#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020 141#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020
141#define MSC01_PCI_INTSTAT_MWP_SHF 4 142#define MSC01_PCI_INTSTAT_MWP_SHF 4
142#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010 143#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010
143#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010 144#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010
144#define MSC01_PCI_INTSTAT_MRP_SHF 3 145#define MSC01_PCI_INTSTAT_MRP_SHF 3
145#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008 146#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008
146#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008 147#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008
147#define MSC01_PCI_INTSTAT_SWP_SHF 2 148#define MSC01_PCI_INTSTAT_SWP_SHF 2
148#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004 149#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004
149#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004 150#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004
150#define MSC01_PCI_INTSTAT_SRP_SHF 1 151#define MSC01_PCI_INTSTAT_SRP_SHF 1
151#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002 152#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002
152#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002 153#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002
153#define MSC01_PCI_INTSTAT_SE_SHF 0 154#define MSC01_PCI_INTSTAT_SE_SHF 0
154#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001 155#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001
155#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001 156#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001
156 157
157#define MSC01_PCI_CFGADDR_BNUM_SHF 16 158#define MSC01_PCI_CFGADDR_BNUM_SHF 16
158#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000 159#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000
@@ -167,29 +168,29 @@
167#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff 168#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff
168 169
169/* The defines below are ONLY valid for a MEM bar! */ 170/* The defines below are ONLY valid for a MEM bar! */
170#define MSC01_PCI_BAR0_SIZE_SHF 4 171#define MSC01_PCI_BAR0_SIZE_SHF 4
171#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0 172#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0
172#define MSC01_PCI_BAR0_P_SHF 3 173#define MSC01_PCI_BAR0_P_SHF 3
173#define MSC01_PCI_BAR0_P_MSK 0x00000008 174#define MSC01_PCI_BAR0_P_MSK 0x00000008
174#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK 175#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK
175#define MSC01_PCI_BAR0_D_SHF 1 176#define MSC01_PCI_BAR0_D_SHF 1
176#define MSC01_PCI_BAR0_D_MSK 0x00000006 177#define MSC01_PCI_BAR0_D_MSK 0x00000006
177#define MSC01_PCI_BAR0_T_SHF 0 178#define MSC01_PCI_BAR0_T_SHF 0
178#define MSC01_PCI_BAR0_T_MSK 0x00000001 179#define MSC01_PCI_BAR0_T_MSK 0x00000001
179#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK 180#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK
180 181
181 182
182#define MSC01_PCI_CFG_RA_SHF 17 183#define MSC01_PCI_CFG_RA_SHF 17
183#define MSC01_PCI_CFG_RA_MSK 0x00020000 184#define MSC01_PCI_CFG_RA_MSK 0x00020000
184#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK 185#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK
185#define MSC01_PCI_CFG_G_SHF 16 186#define MSC01_PCI_CFG_G_SHF 16
186#define MSC01_PCI_CFG_G_MSK 0x00010000 187#define MSC01_PCI_CFG_G_MSK 0x00010000
187#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK 188#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK
188#define MSC01_PCI_CFG_EN_SHF 15 189#define MSC01_PCI_CFG_EN_SHF 15
189#define MSC01_PCI_CFG_EN_MSK 0x00008000 190#define MSC01_PCI_CFG_EN_MSK 0x00008000
190#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK 191#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK
191#define MSC01_PCI_CFG_MAXRTRY_SHF 0 192#define MSC01_PCI_CFG_MAXRTRY_SHF 0
192#define MSC01_PCI_CFG_MAXRTRY_MSK 0x000000ff 193#define MSC01_PCI_CFG_MAXRTRY_MSK 0x00000fff
193 194
194#define MSC01_PCI_SWAP_IO_SHF 18 195#define MSC01_PCI_SWAP_IO_SHF 18
195#define MSC01_PCI_SWAP_IO_MSK 0x000c0000 196#define MSC01_PCI_SWAP_IO_MSK 0x000c0000
@@ -206,7 +207,7 @@
206 * FIXME - are these macros specific to Malta and co or to the MSC? If the 207 * FIXME - are these macros specific to Malta and co or to the MSC? If the
207 * latter, they should be moved elsewhere. 208 * latter, they should be moved elsewhere.
208 */ 209 */
209#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 210#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
210 211
211extern unsigned long _pcictrl_msc; 212extern unsigned long _pcictrl_msc;
212 213
@@ -219,19 +220,19 @@ extern unsigned long _pcictrl_msc;
219 * Registers absolute addresses 220 * Registers absolute addresses
220 */ 221 */
221 222
222#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) 223#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
223#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) 224#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
224#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS) 225#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
225#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS) 226#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
226#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS) 227#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
227#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS) 228#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
228#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS) 229#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
229#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS) 230#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
230#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS) 231#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
231#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS) 232#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
232#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS) 233#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
233#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS) 234#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
234#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS) 235#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
235#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS) 236#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
236#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS) 237#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
237#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS) 238#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
@@ -248,7 +249,7 @@ extern unsigned long _pcictrl_msc;
248#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 249#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
249#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 250#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
250#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 251#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
251#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 252#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
252#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS) 253#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
253#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS) 254#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
254#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS) 255#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
diff --git a/include/asm-mips/mips-boards/sim.h b/include/asm-mips/mips-boards/sim.h
new file mode 100644
index 000000000000..acb7c2331d98
--- /dev/null
+++ b/include/asm-mips/mips-boards/sim.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18
19#ifndef _ASM_MIPS_BOARDS_SIM_H
20#define _ASM_MIPS_BOARDS_SIM_H
21
22#define STATS_ON 1
23#define STATS_OFF 2
24#define STATS_CLEAR 3
25#define STATS_DUMP 4
26#define TRACE_ON 5
27#define TRACE_OFF 6
28
29
30#define simcfg(code) \
31({ \
32 __asm__ __volatile__( \
33 "sltiu $0,$0, %0" \
34 ::"i"(code) \
35 ); \
36})
37
38
39
40#endif
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h
new file mode 100644
index 000000000000..4952e0b3bf11
--- /dev/null
+++ b/include/asm-mips/mips-boards/simint.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 */
17#ifndef _MIPS_SIMINT_H
18#define _MIPS_SIMINT_H
19
20
21#define SIM_INT_BASE 0
22#define MIPSCPU_INT_MB0 2
23#define MIPSCPU_INT_BASE 16
24#define MIPS_CPU_TIMER_IRQ 7
25
26
27#define MIPSCPU_INT_CPUCTR 7
28
29#define MSC01E_INT_BASE 64
30
31#define MIPSCPU_INT_CPUCTR 7
32#define MSC01E_INT_CPUCTR 11
33
34#endif
diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h
new file mode 100644
index 000000000000..a669c0702c66
--- /dev/null
+++ b/include/asm-mips/mipsmtregs.h
@@ -0,0 +1,391 @@
1/*
2 * MT regs definitions, follows on from mipsregs.h
3 * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved.
4 * Elizabeth Clarke et. al.
5 *
6 */
7#ifndef _ASM_MIPSMTREGS_H
8#define _ASM_MIPSMTREGS_H
9
10#include <asm/mipsregs.h>
11#include <asm/war.h>
12
13#ifndef __ASSEMBLY__
14
15/*
16 * C macros
17 */
18
19#define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1)
20#define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val)
21
22#define read_c0_mvpconf0() __read_32bit_c0_register($0, 2)
23#define read_c0_mvpconf1() __read_32bit_c0_register($0, 3)
24
25#define read_c0_vpecontrol() __read_32bit_c0_register($1, 1)
26#define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val)
27
28#define read_c0_vpeconf0() __read_32bit_c0_register($1, 2)
29#define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val)
30
31#define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
32#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
33
34#define read_c0_tcbind() __read_32bit_c0_register($2, 2)
35
36#define read_c0_tccontext() __read_32bit_c0_register($2, 5)
37#define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val)
38
39#else /* Assembly */
40/*
41 * Macros for use in assembly language code
42 */
43
44#define CP0_MVPCONTROL $0,1
45#define CP0_MVPCONF0 $0,2
46#define CP0_MVPCONF1 $0,3
47#define CP0_VPECONTROL $1,1
48#define CP0_VPECONF0 $1,2
49#define CP0_VPECONF1 $1,3
50#define CP0_YQMASK $1,4
51#define CP0_VPESCHEDULE $1,5
52#define CP0_VPESCHEFBK $1,6
53#define CP0_TCSTATUS $2,1
54#define CP0_TCBIND $2,2
55#define CP0_TCRESTART $2,3
56#define CP0_TCHALT $2,4
57#define CP0_TCCONTEXT $2,5
58#define CP0_TCSCHEDULE $2,6
59#define CP0_TCSCHEFBK $2,7
60#define CP0_SRSCONF0 $6,1
61#define CP0_SRSCONF1 $6,2
62#define CP0_SRSCONF2 $6,3
63#define CP0_SRSCONF3 $6,4
64#define CP0_SRSCONF4 $6,5
65
66#endif
67
68/* MVPControl fields */
69#define MVPCONTROL_EVP (_ULCAST_(1))
70
71#define MVPCONTROL_VPC_SHIFT 1
72#define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
73
74#define MVPCONTROL_STLB_SHIFT 2
75#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
76
77
78/* MVPConf0 fields */
79#define MVPCONF0_PTC_SHIFT 0
80#define MVPCONF0_PTC ( _ULCAST_(0xff))
81#define MVPCONF0_PVPE_SHIFT 10
82#define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
83#define MVPCONF0_TCA_SHIFT 15
84#define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
85#define MVPCONF0_PTLBE_SHIFT 16
86#define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
87#define MVPCONF0_TLBS_SHIFT 29
88#define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
89#define MVPCONF0_M_SHIFT 31
90#define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
91
92
93/* config3 fields */
94#define CONFIG3_MT_SHIFT 2
95#define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT)
96
97
98/* VPEControl fields (per VPE) */
99#define VPECONTROL_TARGTC (_ULCAST_(0xff))
100
101#define VPECONTROL_TE_SHIFT 15
102#define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
103#define VPECONTROL_EXCPT_SHIFT 16
104#define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
105
106/* Thread Exception Codes for EXCPT field */
107#define THREX_TU 0
108#define THREX_TO 1
109#define THREX_IYQ 2
110#define THREX_GSX 3
111#define THREX_YSCH 4
112#define THREX_GSSCH 5
113
114#define VPECONTROL_GSI_SHIFT 20
115#define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
116#define VPECONTROL_YSI_SHIFT 21
117#define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
118
119/* VPEConf0 fields (per VPE) */
120#define VPECONF0_VPA_SHIFT 0
121#define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
122#define VPECONF0_MVP_SHIFT 1
123#define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
124#define VPECONF0_XTC_SHIFT 21
125#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
126
127/* TCStatus fields (per TC) */
128#define TCSTATUS_TASID (_ULCAST_(0xff))
129#define TCSTATUS_IXMT_SHIFT 10
130#define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
131#define TCSTATUS_TKSU_SHIFT 11
132#define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
133#define TCSTATUS_A_SHIFT 13
134#define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT)
135#define TCSTATUS_DA_SHIFT 15
136#define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
137#define TCSTATUS_DT_SHIFT 20
138#define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
139#define TCSTATUS_TDS_SHIFT 21
140#define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
141#define TCSTATUS_TSST_SHIFT 22
142#define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
143#define TCSTATUS_RNST_SHIFT 23
144#define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
145/* Codes for RNST */
146#define TC_RUNNING 0
147#define TC_WAITING 1
148#define TC_YIELDING 2
149#define TC_GATED 3
150
151#define TCSTATUS_TMX_SHIFT 27
152#define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
153/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
154
155/* TCBind */
156#define TCBIND_CURVPE_SHIFT 0
157#define TCBIND_CURVPE (_ULCAST_(0xf))
158
159#define TCBIND_CURTC_SHIFT 21
160
161#define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
162
163/* TCHalt */
164#define TCHALT_H (_ULCAST_(1))
165
166#ifndef __ASSEMBLY__
167
168extern void mips_mt_regdump(void);
169
170static inline unsigned int dvpe(void)
171{
172 int res = 0;
173
174 __asm__ __volatile__(
175 " .set push \n"
176 " .set noreorder \n"
177 " .set noat \n"
178 " .set mips32r2 \n"
179 " .word 0x41610001 # dvpe $1 \n"
180 " move %0, $1 \n"
181 " ehb \n"
182 " .set pop \n"
183 : "=r" (res));
184
185 instruction_hazard();
186
187 return res;
188}
189
190static inline void __raw_evpe(void)
191{
192 __asm__ __volatile__(
193 " .set push \n"
194 " .set noreorder \n"
195 " .set noat \n"
196 " .set mips32r2 \n"
197 " .word 0x41600021 # evpe \n"
198 " ehb \n"
199 " .set pop \n");
200}
201
202/* Enable multiMT if previous suggested it should be.
203 EMT_ENABLE to force */
204
205#define EVPE_ENABLE MVPCONTROL_EVP
206
207static inline void evpe(int previous)
208{
209 if ((previous & MVPCONTROL_EVP))
210 __raw_evpe();
211}
212
213static inline unsigned int dmt(void)
214{
215 int res;
216
217 __asm__ __volatile__(
218 " .set push \n"
219 " .set mips32r2 \n"
220 " .set noat \n"
221 " .word 0x41610BC1 # dmt $1 \n"
222 " ehb \n"
223 " move %0, $1 \n"
224 " .set pop \n"
225 : "=r" (res));
226
227 instruction_hazard();
228
229 return res;
230}
231
232static inline void __raw_emt(void)
233{
234 __asm__ __volatile__(
235 " .set noreorder \n"
236 " .set mips32r2 \n"
237 " emt \n"
238 " ehb \n"
239 " .set mips0 \n"
240 " .set reorder");
241}
242
243/* enable multiVPE if previous suggested it should be.
244 EVPE_ENABLE to force */
245
246#define EMT_ENABLE VPECONTROL_TE
247
248static inline void emt(int previous)
249{
250 if ((previous & EMT_ENABLE))
251 __raw_emt();
252}
253
254static inline void ehb(void)
255{
256 __asm__ __volatile__(
257 " .set mips32r2 \n"
258 " ehb \n"
259 " .set mips0 \n");
260}
261
262#define mftc0(rt,sel) \
263({ \
264 unsigned long __res; \
265 \
266 __asm__ __volatile__( \
267 " .set push \n" \
268 " .set mips32r2 \n" \
269 " .set noat \n" \
270 " # mftc0 $1, $" #rt ", " #sel " \n" \
271 " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
272 " move %0, $1 \n" \
273 " .set pop \n" \
274 : "=r" (__res)); \
275 \
276 __res; \
277})
278
279#define mftgpr(rt) \
280({ \
281 unsigned long __res; \
282 \
283 __asm__ __volatile__( \
284 " .set push \n" \
285 " .set mips32r2 \n" \
286 " mftgpr %0," #rt " \n" \
287 " .set pop \n" \
288 : "=r" (__res)); \
289 \
290 __res; \
291})
292
293#define mftr(rt,u,sel) \
294({ \
295 unsigned long __res; \
296 \
297 __asm__ __volatile__( \
298 ".set noat\n\t" \
299 "mftr\t%0, " #rt ", " #u ", " #sel "\n\t" \
300 ".set at\n\t" \
301 : "=r" (__res)); \
302 \
303 __res; \
304})
305
306#define mttgpr(rd,v) \
307do { \
308 __asm__ __volatile__( \
309 " .set push \n" \
310 " .set mips32r2 \n" \
311 " .set noat \n" \
312 " move $1, %0 \n" \
313 " # mttgpr $1, " #rd " \n" \
314 " .word 0x41810020 | (" #rd " << 11) \n" \
315 " .set pop \n" \
316 : : "r" (v)); \
317} while (0)
318
319#define mttc0(rd,sel,v) \
320({ \
321 __asm__ __volatile__( \
322 " .set push \n" \
323 " .set mips32r2 \n" \
324 " .set noat \n" \
325 " move $1, %0 \n" \
326 " # mttc0 %0," #rd ", " #sel " \n" \
327 " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \
328 " .set pop \n" \
329 : \
330 : "r" (v)); \
331})
332
333
334#define mttr(rd,u,sel,v) \
335({ \
336 __asm__ __volatile__( \
337 "mttr %0," #rd ", " #u ", " #sel \
338 : : "r" (v)); \
339})
340
341
342#define settc(tc) \
343do { \
344 write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
345 ehb(); \
346} while (0)
347
348
349/* you *must* set the target tc (settc) before trying to use these */
350#define read_vpe_c0_vpecontrol() mftc0(1, 1)
351#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
352#define read_vpe_c0_vpeconf0() mftc0(1, 2)
353#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
354#define read_vpe_c0_status() mftc0(12, 0)
355#define write_vpe_c0_status(val) mttc0(12, 0, val)
356#define read_vpe_c0_cause() mftc0(13, 0)
357#define write_vpe_c0_cause(val) mttc0(13, 0, val)
358#define read_vpe_c0_config() mftc0(16, 0)
359#define write_vpe_c0_config(val) mttc0(16, 0, val)
360#define read_vpe_c0_config1() mftc0(16, 1)
361#define write_vpe_c0_config1(val) mttc0(16, 1, val)
362#define read_vpe_c0_config7() mftc0(16, 7)
363#define write_vpe_c0_config7(val) mttc0(16, 7, val)
364#define read_vpe_c0_ebase() mftc0(15,1)
365#define write_vpe_c0_ebase(val) mttc0(15, 1, val)
366#define write_vpe_c0_compare(val) mttc0(11, 0, val)
367
368
369/* TC */
370#define read_tc_c0_tcstatus() mftc0(2, 1)
371#define write_tc_c0_tcstatus(val) mttc0(2,1,val)
372#define read_tc_c0_tcbind() mftc0(2, 2)
373#define write_tc_c0_tcbind(val) mttc0(2,2,val)
374#define read_tc_c0_tcrestart() mftc0(2, 3)
375#define write_tc_c0_tcrestart(val) mttc0(2,3,val)
376#define read_tc_c0_tchalt() mftc0(2, 4)
377#define write_tc_c0_tchalt(val) mttc0(2,4,val)
378#define read_tc_c0_tccontext() mftc0(2, 5)
379#define write_tc_c0_tccontext(val) mttc0(2,5,val)
380
381/* GPR */
382#define read_tc_gpr_sp() mftgpr(29)
383#define write_tc_gpr_sp(val) mttgpr(29, val)
384#define read_tc_gpr_gp() mftgpr(28)
385#define write_tc_gpr_gp(val) mttgpr(28, val)
386
387__BUILD_SET_C0(mvpcontrol)
388
389#endif /* Not __ASSEMBLY__ */
390
391#endif
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 2197aa4ce456..80370e0a5589 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -8,7 +8,7 @@
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2003 Maciej W. Rozycki 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */ 12 */
13#ifndef _ASM_MIPSREGS_H 13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H 14#define _ASM_MIPSREGS_H
@@ -96,6 +96,16 @@
96#define CP0_S1_INTCONTROL $20 96#define CP0_S1_INTCONTROL $20
97 97
98/* 98/*
99 * Coprocessor 0 Set 2 register names
100 */
101#define CP0_S2_SRSCTL $12 /* MIPSR2 */
102
103/*
104 * Coprocessor 0 Set 3 register names
105 */
106#define CP0_S3_SRSMAP $12 /* MIPSR2 */
107
108/*
99 * TX39 Series 109 * TX39 Series
100 */ 110 */
101#define CP0_TX39_CACHE $7 111#define CP0_TX39_CACHE $7
@@ -281,6 +291,11 @@
281#define ST0_DL (_ULCAST_(1) << 24) 291#define ST0_DL (_ULCAST_(1) << 24)
282 292
283/* 293/*
294 * Enable the MIPS DSP ASE
295 */
296#define ST0_MX 0x01000000
297
298/*
284 * Bitfields in the TX39 family CP0 Configuration Register 3 299 * Bitfields in the TX39 family CP0 Configuration Register 3
285 */ 300 */
286#define TX39_CONF_ICS_SHIFT 19 301#define TX39_CONF_ICS_SHIFT 19
@@ -433,6 +448,14 @@
433#define R5K_CONF_SE (_ULCAST_(1) << 12) 448#define R5K_CONF_SE (_ULCAST_(1) << 12)
434#define R5K_CONF_SS (_ULCAST_(3) << 20) 449#define R5K_CONF_SS (_ULCAST_(3) << 20)
435 450
451/* Bits specific to the RM7000. */
452#define RM7K_CONF_SE (_ULCAST_(1) << 3)
453#define RM7K_CONF_TE (_ULCAST_(1) << 12)
454#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
455#define RM7K_CONF_TC (_ULCAST_(1) << 17)
456#define RM7K_CONF_SI (_ULCAST_(3) << 20)
457#define RM7K_CONF_SC (_ULCAST_(1) << 31)
458
436/* Bits specific to the R10000. */ 459/* Bits specific to the R10000. */
437#define R10K_CONF_DN (_ULCAST_(3) << 3) 460#define R10K_CONF_DN (_ULCAST_(3) << 3)
438#define R10K_CONF_CT (_ULCAST_(1) << 5) 461#define R10K_CONF_CT (_ULCAST_(1) << 5)
@@ -475,6 +498,53 @@
475#define MIPS_CONF_M (_ULCAST_(1) << 31) 498#define MIPS_CONF_M (_ULCAST_(1) << 31)
476 499
477/* 500/*
501 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
502 */
503#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
504#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
505#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
506#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
507#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
508#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
509#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
510#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
511#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
512#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
513#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
514#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
515#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
516#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
517
518#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
519#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
520#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
521#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
522#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
523#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
524#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
525#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
526
527#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
528#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
529#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
530#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
531#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
532#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
533#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
534#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
535
536/*
537 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
538 */
539#define MIPS_FPIR_S (_ULCAST_(1) << 16)
540#define MIPS_FPIR_D (_ULCAST_(1) << 17)
541#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
542#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
543#define MIPS_FPIR_W (_ULCAST_(1) << 20)
544#define MIPS_FPIR_L (_ULCAST_(1) << 21)
545#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
546
547/*
478 * R10000 performance counter definitions. 548 * R10000 performance counter definitions.
479 * 549 *
480 * FIXME: The R10000 performance counter opens a nice way to implement CPU 550 * FIXME: The R10000 performance counter opens a nice way to implement CPU
@@ -621,13 +691,13 @@ do { \
621 if (sel == 0) \ 691 if (sel == 0) \
622 __asm__ __volatile__( \ 692 __asm__ __volatile__( \
623 "mtc0\t%z0, " #register "\n\t" \ 693 "mtc0\t%z0, " #register "\n\t" \
624 : : "Jr" ((unsigned int)value)); \ 694 : : "Jr" ((unsigned int)(value))); \
625 else \ 695 else \
626 __asm__ __volatile__( \ 696 __asm__ __volatile__( \
627 ".set\tmips32\n\t" \ 697 ".set\tmips32\n\t" \
628 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 698 "mtc0\t%z0, " #register ", " #sel "\n\t" \
629 ".set\tmips0" \ 699 ".set\tmips0" \
630 : : "Jr" ((unsigned int)value)); \ 700 : : "Jr" ((unsigned int)(value))); \
631} while (0) 701} while (0)
632 702
633#define __write_64bit_c0_register(register, sel, value) \ 703#define __write_64bit_c0_register(register, sel, value) \
@@ -676,7 +746,7 @@ do { \
676do { \ 746do { \
677 __asm__ __volatile__( \ 747 __asm__ __volatile__( \
678 "ctc0\t%z0, " #register "\n\t" \ 748 "ctc0\t%z0, " #register "\n\t" \
679 : : "Jr" ((unsigned int)value)); \ 749 : : "Jr" ((unsigned int)(value))); \
680} while (0) 750} while (0)
681 751
682/* 752/*
@@ -769,12 +839,24 @@ do { \
769#define read_c0_count() __read_32bit_c0_register($9, 0) 839#define read_c0_count() __read_32bit_c0_register($9, 0)
770#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 840#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
771 841
842#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
843#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
844
845#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
846#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
847
772#define read_c0_entryhi() __read_ulong_c0_register($10, 0) 848#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
773#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 849#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
774 850
775#define read_c0_compare() __read_32bit_c0_register($11, 0) 851#define read_c0_compare() __read_32bit_c0_register($11, 0)
776#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 852#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
777 853
854#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
855#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
856
857#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
858#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
859
778#define read_c0_status() __read_32bit_c0_register($12, 0) 860#define read_c0_status() __read_32bit_c0_register($12, 0)
779#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 861#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
780 862
@@ -790,10 +872,18 @@ do { \
790#define read_c0_config1() __read_32bit_c0_register($16, 1) 872#define read_c0_config1() __read_32bit_c0_register($16, 1)
791#define read_c0_config2() __read_32bit_c0_register($16, 2) 873#define read_c0_config2() __read_32bit_c0_register($16, 2)
792#define read_c0_config3() __read_32bit_c0_register($16, 3) 874#define read_c0_config3() __read_32bit_c0_register($16, 3)
875#define read_c0_config4() __read_32bit_c0_register($16, 4)
876#define read_c0_config5() __read_32bit_c0_register($16, 5)
877#define read_c0_config6() __read_32bit_c0_register($16, 6)
878#define read_c0_config7() __read_32bit_c0_register($16, 7)
793#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 879#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
794#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 880#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
795#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 881#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
796#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 882#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
883#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
884#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
885#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
886#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
797 887
798/* 888/*
799 * The WatchLo register. There may be upto 8 of them. 889 * The WatchLo register. There may be upto 8 of them.
@@ -917,6 +1007,22 @@ do { \
917#define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1007#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
918#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1008#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
919 1009
1010/* MIPSR2 */
1011#define read_c0_hwrena() __read_32bit_c0_register($7,0)
1012#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1013
1014#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1015#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1016
1017#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1018#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1019
1020#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1021#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1022
1023#define read_c0_ebase() __read_32bit_c0_register($15,1)
1024#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1025
920/* 1026/*
921 * Macros to access the floating point coprocessor control registers 1027 * Macros to access the floating point coprocessor control registers
922 */ 1028 */
@@ -930,6 +1036,284 @@ do { \
930 : "=r" (__res)); \ 1036 : "=r" (__res)); \
931 __res;}) 1037 __res;})
932 1038
1039#define rddsp(mask) \
1040({ \
1041 unsigned int __res; \
1042 \
1043 __asm__ __volatile__( \
1044 " .set push \n" \
1045 " .set noat \n" \
1046 " # rddsp $1, %x1 \n" \
1047 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1048 " move %0, $1 \n" \
1049 " .set pop \n" \
1050 : "=r" (__res) \
1051 : "i" (mask)); \
1052 __res; \
1053})
1054
1055#define wrdsp(val, mask) \
1056do { \
1057 __asm__ __volatile__( \
1058 " .set push \n" \
1059 " .set noat \n" \
1060 " move $1, %0 \n" \
1061 " # wrdsp $1, %x1 \n" \
1062 " .word 0x7c2004f8 | (%x1 << 15) \n" \
1063 " .set pop \n" \
1064 : \
1065 : "r" (val), "i" (mask)); \
1066} while (0)
1067
1068#if 0 /* Need DSP ASE capable assembler ... */
1069#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1070#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1071#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1072#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1073
1074#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1075#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1076#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1077#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1078
1079#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1080#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1081#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1082#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1083
1084#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1085#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1086#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1087#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1088
1089#else
1090
1091#define mfhi0() \
1092({ \
1093 unsigned long __treg; \
1094 \
1095 __asm__ __volatile__( \
1096 " .set push \n" \
1097 " .set noat \n" \
1098 " # mfhi %0, $ac0 \n" \
1099 " .word 0x00000810 \n" \
1100 " move %0, $1 \n" \
1101 " .set pop \n" \
1102 : "=r" (__treg)); \
1103 __treg; \
1104})
1105
1106#define mfhi1() \
1107({ \
1108 unsigned long __treg; \
1109 \
1110 __asm__ __volatile__( \
1111 " .set push \n" \
1112 " .set noat \n" \
1113 " # mfhi %0, $ac1 \n" \
1114 " .word 0x00200810 \n" \
1115 " move %0, $1 \n" \
1116 " .set pop \n" \
1117 : "=r" (__treg)); \
1118 __treg; \
1119})
1120
1121#define mfhi2() \
1122({ \
1123 unsigned long __treg; \
1124 \
1125 __asm__ __volatile__( \
1126 " .set push \n" \
1127 " .set noat \n" \
1128 " # mfhi %0, $ac2 \n" \
1129 " .word 0x00400810 \n" \
1130 " move %0, $1 \n" \
1131 " .set pop \n" \
1132 : "=r" (__treg)); \
1133 __treg; \
1134})
1135
1136#define mfhi3() \
1137({ \
1138 unsigned long __treg; \
1139 \
1140 __asm__ __volatile__( \
1141 " .set push \n" \
1142 " .set noat \n" \
1143 " # mfhi %0, $ac3 \n" \
1144 " .word 0x00600810 \n" \
1145 " move %0, $1 \n" \
1146 " .set pop \n" \
1147 : "=r" (__treg)); \
1148 __treg; \
1149})
1150
1151#define mflo0() \
1152({ \
1153 unsigned long __treg; \
1154 \
1155 __asm__ __volatile__( \
1156 " .set push \n" \
1157 " .set noat \n" \
1158 " # mflo %0, $ac0 \n" \
1159 " .word 0x00000812 \n" \
1160 " move %0, $1 \n" \
1161 " .set pop \n" \
1162 : "=r" (__treg)); \
1163 __treg; \
1164})
1165
1166#define mflo1() \
1167({ \
1168 unsigned long __treg; \
1169 \
1170 __asm__ __volatile__( \
1171 " .set push \n" \
1172 " .set noat \n" \
1173 " # mflo %0, $ac1 \n" \
1174 " .word 0x00200812 \n" \
1175 " move %0, $1 \n" \
1176 " .set pop \n" \
1177 : "=r" (__treg)); \
1178 __treg; \
1179})
1180
1181#define mflo2() \
1182({ \
1183 unsigned long __treg; \
1184 \
1185 __asm__ __volatile__( \
1186 " .set push \n" \
1187 " .set noat \n" \
1188 " # mflo %0, $ac2 \n" \
1189 " .word 0x00400812 \n" \
1190 " move %0, $1 \n" \
1191 " .set pop \n" \
1192 : "=r" (__treg)); \
1193 __treg; \
1194})
1195
1196#define mflo3() \
1197({ \
1198 unsigned long __treg; \
1199 \
1200 __asm__ __volatile__( \
1201 " .set push \n" \
1202 " .set noat \n" \
1203 " # mflo %0, $ac3 \n" \
1204 " .word 0x00600812 \n" \
1205 " move %0, $1 \n" \
1206 " .set pop \n" \
1207 : "=r" (__treg)); \
1208 __treg; \
1209})
1210
1211#define mthi0(x) \
1212do { \
1213 __asm__ __volatile__( \
1214 " .set push \n" \
1215 " .set noat \n" \
1216 " move $1, %0 \n" \
1217 " # mthi $1, $ac0 \n" \
1218 " .word 0x00200011 \n" \
1219 " .set pop \n" \
1220 : \
1221 : "r" (x)); \
1222} while (0)
1223
1224#define mthi1(x) \
1225do { \
1226 __asm__ __volatile__( \
1227 " .set push \n" \
1228 " .set noat \n" \
1229 " move $1, %0 \n" \
1230 " # mthi $1, $ac1 \n" \
1231 " .word 0x00200811 \n" \
1232 " .set pop \n" \
1233 : \
1234 : "r" (x)); \
1235} while (0)
1236
1237#define mthi2(x) \
1238do { \
1239 __asm__ __volatile__( \
1240 " .set push \n" \
1241 " .set noat \n" \
1242 " move $1, %0 \n" \
1243 " # mthi $1, $ac2 \n" \
1244 " .word 0x00201011 \n" \
1245 " .set pop \n" \
1246 : \
1247 : "r" (x)); \
1248} while (0)
1249
1250#define mthi3(x) \
1251do { \
1252 __asm__ __volatile__( \
1253 " .set push \n" \
1254 " .set noat \n" \
1255 " move $1, %0 \n" \
1256 " # mthi $1, $ac3 \n" \
1257 " .word 0x00201811 \n" \
1258 " .set pop \n" \
1259 : \
1260 : "r" (x)); \
1261} while (0)
1262
1263#define mtlo0(x) \
1264do { \
1265 __asm__ __volatile__( \
1266 " .set push \n" \
1267 " .set noat \n" \
1268 " move $1, %0 \n" \
1269 " # mtlo $1, $ac0 \n" \
1270 " .word 0x00200013 \n" \
1271 " .set pop \n" \
1272 : \
1273 : "r" (x)); \
1274} while (0)
1275
1276#define mtlo1(x) \
1277do { \
1278 __asm__ __volatile__( \
1279 " .set push \n" \
1280 " .set noat \n" \
1281 " move $1, %0 \n" \
1282 " # mtlo $1, $ac1 \n" \
1283 " .word 0x00200813 \n" \
1284 " .set pop \n" \
1285 : \
1286 : "r" (x)); \
1287} while (0)
1288
1289#define mtlo2(x) \
1290do { \
1291 __asm__ __volatile__( \
1292 " .set push \n" \
1293 " .set noat \n" \
1294 " move $1, %0 \n" \
1295 " # mtlo $1, $ac2 \n" \
1296 " .word 0x00201013 \n" \
1297 " .set pop \n" \
1298 : \
1299 : "r" (x)); \
1300} while (0)
1301
1302#define mtlo3(x) \
1303do { \
1304 __asm__ __volatile__( \
1305 " .set push \n" \
1306 " .set noat \n" \
1307 " move $1, %0 \n" \
1308 " # mtlo $1, $ac3 \n" \
1309 " .word 0x00201813 \n" \
1310 " .set pop \n" \
1311 : \
1312 : "r" (x)); \
1313} while (0)
1314
1315#endif
1316
933/* 1317/*
934 * TLB operations. 1318 * TLB operations.
935 * 1319 *
@@ -1012,6 +1396,8 @@ __BUILD_SET_C0(status)
1012__BUILD_SET_C0(cause) 1396__BUILD_SET_C0(cause)
1013__BUILD_SET_C0(config) 1397__BUILD_SET_C0(config)
1014__BUILD_SET_C0(intcontrol) 1398__BUILD_SET_C0(intcontrol)
1399__BUILD_SET_C0(intctl)
1400__BUILD_SET_C0(srsmap)
1015 1401
1016#endif /* !__ASSEMBLY__ */ 1402#endif /* !__ASSEMBLY__ */
1017 1403
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
index 45cd72d172e8..19cdf7642e66 100644
--- a/include/asm-mips/mmu_context.h
+++ b/include/asm-mips/mmu_context.h
@@ -30,7 +30,7 @@ extern unsigned long pgd_current[];
30 30
31#ifdef CONFIG_32BIT 31#ifdef CONFIG_32BIT
32#define TLBMISS_HANDLER_SETUP() \ 32#define TLBMISS_HANDLER_SETUP() \
33 write_c0_context((unsigned long) smp_processor_id() << 23); \ 33 write_c0_context((unsigned long) smp_processor_id() << 25); \
34 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 34 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
35#endif 35#endif
36#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) 36#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
@@ -40,7 +40,7 @@ extern unsigned long pgd_current[];
40#endif 40#endif
41#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) 41#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
42#define TLBMISS_HANDLER_SETUP() \ 42#define TLBMISS_HANDLER_SETUP() \
43 write_c0_context((unsigned long) smp_processor_id() << 23); \ 43 write_c0_context((unsigned long) smp_processor_id() << 26); \
44 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 44 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
45#endif 45#endif
46 46
diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h
index d721143dbd47..011caebac369 100644
--- a/include/asm-mips/mmzone.h
+++ b/include/asm-mips/mmzone.h
@@ -5,6 +5,7 @@
5#ifndef _ASM_MMZONE_H_ 5#ifndef _ASM_MMZONE_H_
6#define _ASM_MMZONE_H_ 6#define _ASM_MMZONE_H_
7 7
8#include <linux/config.h>
8#include <asm/page.h> 9#include <asm/page.h>
9#include <mmzone.h> 10#include <mmzone.h>
10 11
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index 0be58b2aeb9f..2be399311eec 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -14,15 +14,23 @@ struct mod_arch_specific {
14 14
15typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ 15typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */
16 16
17typedef struct 17typedef struct {
18{ 18 Elf64_Addr r_offset; /* Address of relocation. */
19 Elf64_Addr r_offset; /* Address of relocation. */ 19 Elf64_Word r_sym; /* Symbol index. */
20 Elf64_Word r_sym; /* Symbol index. */ 20 Elf64_Byte r_ssym; /* Special symbol. */
21 Elf64_Byte r_ssym; /* Special symbol. */ 21 Elf64_Byte r_type3; /* Third relocation. */
22 Elf64_Byte r_type3; /* Third relocation. */ 22 Elf64_Byte r_type2; /* Second relocation. */
23 Elf64_Byte r_type2; /* Second relocation. */ 23 Elf64_Byte r_type; /* First relocation. */
24 Elf64_Byte r_type; /* First relocation. */ 24} Elf64_Mips_Rel;
25 Elf64_Sxword r_addend; /* Addend. */ 25
26typedef struct {
27 Elf64_Addr r_offset; /* Address of relocation. */
28 Elf64_Word r_sym; /* Symbol index. */
29 Elf64_Byte r_ssym; /* Special symbol. */
30 Elf64_Byte r_type3; /* Third relocation. */
31 Elf64_Byte r_type2; /* Second relocation. */
32 Elf64_Byte r_type; /* First relocation. */
33 Elf64_Sxword r_addend; /* Addend. */
26} Elf64_Mips_Rela; 34} Elf64_Mips_Rela;
27 35
28#ifdef CONFIG_32BIT 36#ifdef CONFIG_32BIT
@@ -30,6 +38,13 @@ typedef struct
30#define Elf_Shdr Elf32_Shdr 38#define Elf_Shdr Elf32_Shdr
31#define Elf_Sym Elf32_Sym 39#define Elf_Sym Elf32_Sym
32#define Elf_Ehdr Elf32_Ehdr 40#define Elf_Ehdr Elf32_Ehdr
41#define Elf_Addr Elf32_Addr
42
43#define Elf_Mips_Rel Elf32_Rel
44#define Elf_Mips_Rela Elf32_Rela
45
46#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM(rel.r_info)
47#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE(rel.r_info)
33 48
34#endif 49#endif
35 50
@@ -38,6 +53,13 @@ typedef struct
38#define Elf_Shdr Elf64_Shdr 53#define Elf_Shdr Elf64_Shdr
39#define Elf_Sym Elf64_Sym 54#define Elf_Sym Elf64_Sym
40#define Elf_Ehdr Elf64_Ehdr 55#define Elf_Ehdr Elf64_Ehdr
56#define Elf_Addr Elf64_Addr
57
58#define Elf_Mips_Rel Elf64_Mips_Rel
59#define Elf_Mips_Rela Elf64_Mips_Rela
60
61#define ELF_MIPS_R_SYM(rel) (rel.r_sym)
62#define ELF_MIPS_R_TYPE(rel) (rel.r_type)
41 63
42#endif 64#endif
43 65
@@ -53,4 +75,54 @@ search_module_dbetables(unsigned long addr)
53} 75}
54#endif 76#endif
55 77
78#ifdef CONFIG_CPU_MIPS32_R1
79#define MODULE_PROC_FAMILY "MIPS32_R1"
80#elif defined CONFIG_CPU_MIPS32_R2
81#define MODULE_PROC_FAMILY "MIPS32_R2"
82#elif defined CONFIG_CPU_MIPS64_R1
83#define MODULE_PROC_FAMILY "MIPS64_R1"
84#elif defined CONFIG_CPU_MIPS64_R2
85#define MODULE_PROC_FAMILY "MIPS64_R2"
86#elif defined CONFIG_CPU_R3000
87#define MODULE_PROC_FAMILY "R3000"
88#elif defined CONFIG_CPU_TX39XX
89#define MODULE_PROC_FAMILY "TX39XX"
90#elif defined CONFIG_CPU_VR41XX
91#define MODULE_PROC_FAMILY "VR41XX"
92#elif defined CONFIG_CPU_R4300
93#define MODULE_PROC_FAMILY "R4300"
94#elif defined CONFIG_CPU_R4X00
95#define MODULE_PROC_FAMILY "R4X00"
96#elif defined CONFIG_CPU_TX49XX
97#define MODULE_PROC_FAMILY "TX49XX"
98#elif defined CONFIG_CPU_R5000
99#define MODULE_PROC_FAMILY "R5000"
100#elif defined CONFIG_CPU_R5432
101#define MODULE_PROC_FAMILY "R5432"
102#elif defined CONFIG_CPU_R6000
103#define MODULE_PROC_FAMILY "R6000"
104#elif defined CONFIG_CPU_NEVADA
105#define MODULE_PROC_FAMILY "NEVADA"
106#elif defined CONFIG_CPU_R8000
107#define MODULE_PROC_FAMILY "R8000"
108#elif defined CONFIG_CPU_R10000
109#define MODULE_PROC_FAMILY "R10000"
110#elif defined CONFIG_CPU_RM7000
111#define MODULE_PROC_FAMILY "RM7000"
112#elif defined CONFIG_CPU_RM9000
113#define MODULE_PROC_FAMILY "RM9000"
114#elif defined CONFIG_CPU_SB1
115#define MODULE_PROC_FAMILY "SB1"
116#else
117#error MODULE_PROC_FAMILY undefined for your processor configuration
118#endif
119
120#ifdef CONFIG_32BIT
121#define MODULE_KERNEL_TYPE "32BIT "
122#elif defined CONFIG_64BIT
123#define MODULE_KERNEL_TYPE "64BIT "
124#endif
125
126#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_KERNEL_TYPE
127
56#endif /* _ASM_MODULE_H */ 128#endif /* _ASM_MODULE_H */
diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h
index 309bc3099f68..46f2d23d2697 100644
--- a/include/asm-mips/paccess.h
+++ b/include/asm-mips/paccess.h
@@ -52,7 +52,7 @@ struct __large_pstruct { unsigned long buf[100]; };
52}) 52})
53 53
54#define __get_dbe_asm(insn) \ 54#define __get_dbe_asm(insn) \
55({ \ 55{ \
56 __asm__ __volatile__( \ 56 __asm__ __volatile__( \
57 "1:\t" insn "\t%1,%2\n\t" \ 57 "1:\t" insn "\t%1,%2\n\t" \
58 "move\t%0,$0\n" \ 58 "move\t%0,$0\n" \
@@ -67,7 +67,7 @@ struct __large_pstruct { unsigned long buf[100]; };
67 ".previous" \ 67 ".previous" \
68 :"=r" (__gu_err), "=r" (__gu_val) \ 68 :"=r" (__gu_err), "=r" (__gu_val) \
69 :"o" (__mp(__gu_addr)), "i" (-EFAULT)); \ 69 :"o" (__mp(__gu_addr)), "i" (-EFAULT)); \
70}) 70}
71 71
72extern void __get_dbe_unknown(void); 72extern void __get_dbe_unknown(void);
73 73
@@ -90,7 +90,7 @@ extern void __get_dbe_unknown(void);
90}) 90})
91 91
92#define __put_dbe_asm(insn) \ 92#define __put_dbe_asm(insn) \
93({ \ 93{ \
94 __asm__ __volatile__( \ 94 __asm__ __volatile__( \
95 "1:\t" insn "\t%1,%2\n\t" \ 95 "1:\t" insn "\t%1,%2\n\t" \
96 "move\t%0,$0\n" \ 96 "move\t%0,$0\n" \
@@ -104,7 +104,7 @@ extern void __get_dbe_unknown(void);
104 ".previous" \ 104 ".previous" \
105 : "=r" (__pu_err) \ 105 : "=r" (__pu_err) \
106 : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT)); \ 106 : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT)); \
107}) 107}
108 108
109extern void __put_dbe_unknown(void); 109extern void __put_dbe_unknown(void);
110 110
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 652b6d67a571..ee25a779bf49 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -87,22 +87,48 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
87typedef struct { unsigned long pte; } pte_t; 87typedef struct { unsigned long pte; } pte_t;
88#define pte_val(x) ((x).pte) 88#define pte_val(x) ((x).pte)
89#endif 89#endif
90#define __pte(x) ((pte_t) { (x) } )
90 91
91typedef struct { unsigned long pmd; } pmd_t; 92/*
92typedef struct { unsigned long pgd; } pgd_t; 93 * For 3-level pagetables we defines these ourselves, for 2-level the
93typedef struct { unsigned long pgprot; } pgprot_t; 94 * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
95 */
96#ifdef CONFIG_64BIT
94 97
98typedef struct { unsigned long pmd; } pmd_t;
95#define pmd_val(x) ((x).pmd) 99#define pmd_val(x) ((x).pmd)
96#define pgd_val(x) ((x).pgd) 100#define __pmd(x) ((pmd_t) { (x) } )
97#define pgprot_val(x) ((x).pgprot)
98 101
99#define ptep_buddy(x) ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t))) 102#endif
100 103
101#define __pte(x) ((pte_t) { (x) } ) 104/*
102#define __pmd(x) ((pmd_t) { (x) } ) 105 * Right now we don't support 4-level pagetables, so all pud-related
106 * definitions come from <asm-generic/pgtable-nopud.h>.
107 */
108
109/*
110 * Finall the top of the hierarchy, the pgd
111 */
112typedef struct { unsigned long pgd; } pgd_t;
113#define pgd_val(x) ((x).pgd)
103#define __pgd(x) ((pgd_t) { (x) } ) 114#define __pgd(x) ((pgd_t) { (x) } )
115
116/*
117 * Manipulate page protection bits
118 */
119typedef struct { unsigned long pgprot; } pgprot_t;
120#define pgprot_val(x) ((x).pgprot)
104#define __pgprot(x) ((pgprot_t) { (x) } ) 121#define __pgprot(x) ((pgprot_t) { (x) } )
105 122
123/*
124 * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
125 * pair of pages we only have a single global bit per pair of pages. When
126 * writing to the TLB make sure we always have the bit set for both pages
127 * or none. This macro is used to access the `buddy' of the pte we're just
128 * working on.
129 */
130#define ptep_buddy(x) ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
131
106#endif /* !__ASSEMBLY__ */ 132#endif /* !__ASSEMBLY__ */
107 133
108/* to align the pointer to the (next) page boundary */ 134/* to align the pointer to the (next) page boundary */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index c9a00ca1c012..6c9ad8171a77 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -40,6 +40,11 @@ struct pci_controller {
40 unsigned int need_domain_info; 40 unsigned int need_domain_info;
41 41
42 int iommu; 42 int iommu;
43
44 /* Optional access methods for reading/writing the bus number
45 of the PCI controller */
46 int (*get_busno)(void);
47 void (*set_busno)(int busno);
43}; 48};
44 49
45/* 50/*
@@ -142,8 +147,22 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
142 147
143extern void pcibios_resource_to_bus(struct pci_dev *dev, 148extern void pcibios_resource_to_bus(struct pci_dev *dev,
144 struct pci_bus_region *region, struct resource *res); 149 struct pci_bus_region *region, struct resource *res);
145extern void pcibios_bus_to_resource(struct pci_dev *dev, 150
146 struct resource *res, struct pci_bus_region *region); 151extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
152 struct pci_bus_region *region);
153
154static inline struct resource *
155pcibios_select_root(struct pci_dev *pdev, struct resource *res)
156{
157 struct resource *root = NULL;
158
159 if (res->flags & IORESOURCE_IO)
160 root = &ioport_resource;
161 if (res->flags & IORESOURCE_MEM)
162 root = &iomem_resource;
163
164 return root;
165}
147 166
148#ifdef CONFIG_PCI_DOMAINS 167#ifdef CONFIG_PCI_DOMAINS
149 168
@@ -169,17 +188,4 @@ static inline void pcibios_add_platform_entries(struct pci_dev *dev)
169/* Do platform specific device initialization at pci_enable_device() time */ 188/* Do platform specific device initialization at pci_enable_device() time */
170extern int pcibios_plat_dev_init(struct pci_dev *dev); 189extern int pcibios_plat_dev_init(struct pci_dev *dev);
171 190
172static inline struct resource *
173pcibios_select_root(struct pci_dev *pdev, struct resource *res)
174{
175 struct resource *root = NULL;
176
177 if (res->flags & IORESOURCE_IO)
178 root = &ioport_resource;
179 if (res->flags & IORESOURCE_MEM)
180 root = &iomem_resource;
181
182 return root;
183}
184
185#endif /* _ASM_PCI_H */ 191#endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h
index ce57288d43bd..fe1df572318b 100644
--- a/include/asm-mips/pgalloc.h
+++ b/include/asm-mips/pgalloc.h
@@ -26,10 +26,22 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
26} 26}
27 27
28/* 28/*
29 * Initialize a new pmd table with invalid pointers.
30 */
31extern void pmd_init(unsigned long page, unsigned long pagetable);
32
33#ifdef CONFIG_64BIT
34
35static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
36{
37 set_pud(pud, __pud((unsigned long)pmd));
38}
39#endif
40
41/*
29 * Initialize a new pgd / pmd table with invalid pointers. 42 * Initialize a new pgd / pmd table with invalid pointers.
30 */ 43 */
31extern void pgd_init(unsigned long page); 44extern void pgd_init(unsigned long page);
32extern void pmd_init(unsigned long page, unsigned long pagetable);
33 45
34static inline pgd_t *pgd_alloc(struct mm_struct *mm) 46static inline pgd_t *pgd_alloc(struct mm_struct *mm)
35{ 47{
@@ -86,21 +98,18 @@ static inline void pte_free(struct page *pte)
86#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) 98#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
87 99
88#ifdef CONFIG_32BIT 100#ifdef CONFIG_32BIT
89#define pgd_populate(mm, pmd, pte) BUG()
90 101
91/* 102/*
92 * allocating and freeing a pmd is trivial: the 1-entry pmd is 103 * allocating and freeing a pmd is trivial: the 1-entry pmd is
93 * inside the pgd, so has no extra memory associated with it. 104 * inside the pgd, so has no extra memory associated with it.
94 */ 105 */
95#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); })
96#define pmd_free(x) do { } while (0) 106#define pmd_free(x) do { } while (0)
97#define __pmd_free_tlb(tlb,x) do { } while (0) 107#define __pmd_free_tlb(tlb,x) do { } while (0)
108
98#endif 109#endif
99 110
100#ifdef CONFIG_64BIT 111#ifdef CONFIG_64BIT
101 112
102#define pgd_populate(mm, pgd, pmd) set_pgd(pgd, __pgd(pmd))
103
104static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) 113static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
105{ 114{
106 pmd_t *pmd; 115 pmd_t *pmd;
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 7fec93b76da9..0cff64ce0fb8 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -17,6 +17,8 @@
17#include <asm/cachectl.h> 17#include <asm/cachectl.h>
18#include <asm/fixmap.h> 18#include <asm/fixmap.h>
19 19
20#include <asm-generic/pgtable-nopmd.h>
21
20/* 22/*
21 * - add_wired_entry() add a fixed TLB entry, and move wired register 23 * - add_wired_entry() add a fixed TLB entry, and move wired register
22 */ 24 */
@@ -41,42 +43,38 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
41 * works even with the cache aliasing problem the R4k and above have. 43 * works even with the cache aliasing problem the R4k and above have.
42 */ 44 */
43 45
44/* PMD_SHIFT determines the size of the area a second-level page table can map */ 46/* PGDIR_SHIFT determines what a third-level page table entry can map */
45#ifdef CONFIG_64BIT_PHYS_ADDR 47#ifdef CONFIG_64BIT_PHYS_ADDR
46#define PMD_SHIFT 21 48#define PGDIR_SHIFT 21
47#else 49#else
48#define PMD_SHIFT 22 50#define PGDIR_SHIFT 22
49#endif 51#endif
50#define PMD_SIZE (1UL << PMD_SHIFT)
51#define PMD_MASK (~(PMD_SIZE-1))
52
53/* PGDIR_SHIFT determines what a third-level page table entry can map */
54#define PGDIR_SHIFT PMD_SHIFT
55#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 52#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
56#define PGDIR_MASK (~(PGDIR_SIZE-1)) 53#define PGDIR_MASK (~(PGDIR_SIZE-1))
57 54
58/* 55/*
59 * Entries per page directory level: we use two-level, so 56 * Entries per page directory level: we use two-level, so
60 * we don't really have any PMD directory physically. 57 * we don't really have any PUD/PMD directory physically.
61 */ 58 */
62#ifdef CONFIG_64BIT_PHYS_ADDR 59#ifdef CONFIG_64BIT_PHYS_ADDR
63#define PGD_ORDER 1 60#define PGD_ORDER 1
64#define PMD_ORDER 0 61#define PUD_ORDER aieeee_attempt_to_allocate_pud
62#define PMD_ORDER 1
65#define PTE_ORDER 0 63#define PTE_ORDER 0
66#else 64#else
67#define PGD_ORDER 0 65#define PGD_ORDER 0
68#define PMD_ORDER 0 66#define PUD_ORDER aieeee_attempt_to_allocate_pud
67#define PMD_ORDER 1
69#define PTE_ORDER 0 68#define PTE_ORDER 0
70#endif 69#endif
71 70
72#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) 71#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
73#define PTRS_PER_PMD 1
74#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) 72#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
75 73
76#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) 74#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
77#define FIRST_USER_ADDRESS 0 75#define FIRST_USER_ADDRESS 0
78 76
79#define VMALLOC_START KSEG2 77#define VMALLOC_START MAP_BASE
80 78
81#ifdef CONFIG_HIGHMEM 79#ifdef CONFIG_HIGHMEM
82# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE) 80# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
@@ -91,8 +89,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
91#define pte_ERROR(e) \ 89#define pte_ERROR(e) \
92 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 90 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
93#endif 91#endif
94#define pmd_ERROR(e) \
95 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
96#define pgd_ERROR(e) \ 92#define pgd_ERROR(e) \
97 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 93 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
98 94
@@ -120,17 +116,7 @@ static inline void pmd_clear(pmd_t *pmdp)
120 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); 116 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
121} 117}
122 118
123/* 119#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
124 * The "pgd_xxx()" functions here are trivial for a folded two-level
125 * setup: the pgd is never bad, and a pmd always exists (as it's folded
126 * into the pgd entry)
127 */
128static inline int pgd_none(pgd_t pgd) { return 0; }
129static inline int pgd_bad(pgd_t pgd) { return 0; }
130static inline int pgd_present(pgd_t pgd) { return 1; }
131static inline void pgd_clear(pgd_t *pgdp) { }
132
133#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
134#define pte_page(x) pfn_to_page(pte_pfn(x)) 120#define pte_page(x) pfn_to_page(pte_pfn(x))
135#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) 121#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
136static inline pte_t 122static inline pte_t
@@ -151,27 +137,22 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
151#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) 137#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
152#else 138#else
153#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) 139#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
154#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 140#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
155#endif 141#endif
156#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ 142#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
157 143
158#define __pgd_offset(address) pgd_index(address) 144#define __pgd_offset(address) pgd_index(address)
145#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
159#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 146#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
160 147
161/* to find an entry in a kernel page-table-directory */ 148/* to find an entry in a kernel page-table-directory */
162#define pgd_offset_k(address) pgd_offset(&init_mm, address) 149#define pgd_offset_k(address) pgd_offset(&init_mm, address)
163 150
164#define pgd_index(address) ((address) >> PGDIR_SHIFT) 151#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
165 152
166/* to find an entry in a page-table-directory */ 153/* to find an entry in a page-table-directory */
167#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) 154#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr))
168 155
169/* Find an entry in the second-level page table.. */
170static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
171{
172 return (pmd_t *) dir;
173}
174
175/* Find an entry in the third-level page table.. */ 156/* Find an entry in the third-level page table.. */
176#define __pte_offset(address) \ 157#define __pte_offset(address) \
177 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 158 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
@@ -221,7 +202,7 @@ static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
221 */ 202 */
222#define PTE_FILE_MAX_BITS 27 203#define PTE_FILE_MAX_BITS 27
223 204
224#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 205#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
225 /* fixme */ 206 /* fixme */
226#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f)) 207#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
227#define pgoff_to_pte(off) \ 208#define pgoff_to_pte(off) \
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index 1011e0635f56..3e0a522c0f0e 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -16,13 +16,15 @@
16#include <asm/page.h> 16#include <asm/page.h>
17#include <asm/cachectl.h> 17#include <asm/cachectl.h>
18 18
19#include <asm-generic/pgtable-nopud.h>
20
19/* 21/*
20 * Each address space has 2 4K pages as its page directory, giving 1024 22 * Each address space has 2 4K pages as its page directory, giving 1024
21 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a 23 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
22 * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to 24 * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
23 * page tables. Each page table is a single 4K page, giving 512 (== 25 * tables. Each page table is also a single 4K page, giving 512 (==
24 * PTRS_PER_PTE) 8 byte ptes. Each pgde is initialized to point to 26 * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
25 * invalid_pmd_table, each pmde is initialized to point to 27 * invalid_pmd_table, each pmd entry is initialized to point to
26 * invalid_pte_table, each pte is initialized to 0. When memory is low, 28 * invalid_pte_table, each pte is initialized to 0. When memory is low,
27 * and a pmd table or a page table allocation fails, empty_bad_pmd_table 29 * and a pmd table or a page table allocation fails, empty_bad_pmd_table
28 * and empty_bad_page_table is returned back to higher layer code, so 30 * and empty_bad_page_table is returned back to higher layer code, so
@@ -36,17 +38,17 @@
36 */ 38 */
37 39
38/* PMD_SHIFT determines the size of the area a second-level page table can map */ 40/* PMD_SHIFT determines the size of the area a second-level page table can map */
39#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3)) 41#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
40#define PMD_SIZE (1UL << PMD_SHIFT) 42#define PMD_SIZE (1UL << PMD_SHIFT)
41#define PMD_MASK (~(PMD_SIZE-1)) 43#define PMD_MASK (~(PMD_SIZE-1))
42 44
43/* PGDIR_SHIFT determines what a third-level page table entry can map */ 45/* PGDIR_SHIFT determines what a third-level page table entry can map */
44#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + 1 - 3)) 46#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
45#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 47#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
46#define PGDIR_MASK (~(PGDIR_SIZE-1)) 48#define PGDIR_MASK (~(PGDIR_SIZE-1))
47 49
48/* 50/*
49 * For 4kB page size we use a 3 level page tree and a 8kB pmd and pgds which 51 * For 4kB page size we use a 3 level page tree and an 8kB pud, which
50 * permits us mapping 40 bits of virtual address space. 52 * permits us mapping 40 bits of virtual address space.
51 * 53 *
52 * We used to implement 41 bits by having an order 1 pmd level but that seemed 54 * We used to implement 41 bits by having an order 1 pmd level but that seemed
@@ -57,7 +59,7 @@
57 * two levels would be easy to implement. 59 * two levels would be easy to implement.
58 * 60 *
59 * For 16kB page size we use a 2 level page tree which permits a total of 61 * For 16kB page size we use a 2 level page tree which permits a total of
60 * 36 bits of virtual address space. We could add a third leve. but it seems 62 * 36 bits of virtual address space. We could add a third level but it seems
61 * like at the moment there's no need for this. 63 * like at the moment there's no need for this.
62 * 64 *
63 * For 64kB page size we use a 2 level page table tree for a total of 42 bits 65 * For 64kB page size we use a 2 level page table tree for a total of 42 bits
@@ -65,21 +67,25 @@
65 */ 67 */
66#ifdef CONFIG_PAGE_SIZE_4KB 68#ifdef CONFIG_PAGE_SIZE_4KB
67#define PGD_ORDER 1 69#define PGD_ORDER 1
70#define PUD_ORDER aieeee_attempt_to_allocate_pud
68#define PMD_ORDER 0 71#define PMD_ORDER 0
69#define PTE_ORDER 0 72#define PTE_ORDER 0
70#endif 73#endif
71#ifdef CONFIG_PAGE_SIZE_8KB 74#ifdef CONFIG_PAGE_SIZE_8KB
72#define PGD_ORDER 0 75#define PGD_ORDER 0
76#define PUD_ORDER aieeee_attempt_to_allocate_pud
73#define PMD_ORDER 0 77#define PMD_ORDER 0
74#define PTE_ORDER 0 78#define PTE_ORDER 0
75#endif 79#endif
76#ifdef CONFIG_PAGE_SIZE_16KB 80#ifdef CONFIG_PAGE_SIZE_16KB
77#define PGD_ORDER 0 81#define PGD_ORDER 0
82#define PUD_ORDER aieeee_attempt_to_allocate_pud
78#define PMD_ORDER 0 83#define PMD_ORDER 0
79#define PTE_ORDER 0 84#define PTE_ORDER 0
80#endif 85#endif
81#ifdef CONFIG_PAGE_SIZE_64KB 86#ifdef CONFIG_PAGE_SIZE_64KB
82#define PGD_ORDER 0 87#define PGD_ORDER 0
88#define PUD_ORDER aieeee_attempt_to_allocate_pud
83#define PMD_ORDER 0 89#define PMD_ORDER 0
84#define PTE_ORDER 0 90#define PTE_ORDER 0
85#endif 91#endif
@@ -91,7 +97,7 @@
91#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 97#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
92#define FIRST_USER_ADDRESS 0 98#define FIRST_USER_ADDRESS 0
93 99
94#define VMALLOC_START XKSEG 100#define VMALLOC_START MAP_BASE
95#define VMALLOC_END \ 101#define VMALLOC_END \
96 (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE) 102 (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
97 103
@@ -102,13 +108,13 @@
102#define pgd_ERROR(e) \ 108#define pgd_ERROR(e) \
103 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 109 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
104 110
105extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)]; 111extern pte_t invalid_pte_table[PTRS_PER_PTE];
106extern pte_t empty_bad_page_table[PAGE_SIZE/sizeof(pte_t)]; 112extern pte_t empty_bad_page_table[PTRS_PER_PTE];
107extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)]; 113extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
108extern pmd_t empty_bad_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)]; 114extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
109 115
110/* 116/*
111 * Empty pmd entries point to the invalid_pte_table. 117 * Empty pgd/pmd entries point to the invalid_pte_table.
112 */ 118 */
113static inline int pmd_none(pmd_t pmd) 119static inline int pmd_none(pmd_t pmd)
114{ 120{
@@ -128,26 +134,30 @@ static inline void pmd_clear(pmd_t *pmdp)
128} 134}
129 135
130/* 136/*
131 * Empty pgd entries point to the invalid_pmd_table. 137 * Empty pud entries point to the invalid_pmd_table.
132 */ 138 */
133static inline int pgd_none(pgd_t pgd) 139static inline int pud_none(pud_t pud)
134{ 140{
135 return pgd_val(pgd) == (unsigned long) invalid_pmd_table; 141 return pud_val(pud) == (unsigned long) invalid_pmd_table;
136} 142}
137 143
138#define pgd_bad(pgd) (pgd_val(pgd) &~ PAGE_MASK) 144static inline int pud_bad(pud_t pud)
145{
146 return pud_val(pud) & ~PAGE_MASK;
147}
139 148
140static inline int pgd_present(pgd_t pgd) 149static inline int pud_present(pud_t pud)
141{ 150{
142 return pgd_val(pgd) != (unsigned long) invalid_pmd_table; 151 return pud_val(pud) != (unsigned long) invalid_pmd_table;
143} 152}
144 153
145static inline void pgd_clear(pgd_t *pgdp) 154static inline void pud_clear(pud_t *pudp)
146{ 155{
147 pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table); 156 pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
148} 157}
149 158
150#define pte_page(x) pfn_to_page((unsigned long)((pte_val(x) >> PAGE_SHIFT))) 159#define pte_page(x) pfn_to_page(pte_pfn(x))
160
151#ifdef CONFIG_CPU_VR41XX 161#ifdef CONFIG_CPU_VR41XX
152#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) 162#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
153#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) 163#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
@@ -157,26 +167,28 @@ static inline void pgd_clear(pgd_t *pgdp)
157#endif 167#endif
158 168
159#define __pgd_offset(address) pgd_index(address) 169#define __pgd_offset(address) pgd_index(address)
170#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
171#define __pmd_offset(address) pmd_index(address)
160#define page_pte(page) page_pte_prot(page, __pgprot(0)) 172#define page_pte(page) page_pte_prot(page, __pgprot(0))
161 173
162/* to find an entry in a kernel page-table-directory */ 174/* to find an entry in a kernel page-table-directory */
163#define pgd_offset_k(address) pgd_offset(&init_mm, 0) 175#define pgd_offset_k(address) pgd_offset(&init_mm, 0)
164 176
165#define pgd_index(address) ((address) >> PGDIR_SHIFT) 177#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
178#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
166 179
167/* to find an entry in a page-table-directory */ 180/* to find an entry in a page-table-directory */
168#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) 181#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr))
169 182
170static inline unsigned long pgd_page(pgd_t pgd) 183static inline unsigned long pud_page(pud_t pud)
171{ 184{
172 return pgd_val(pgd); 185 return pud_val(pud);
173} 186}
174 187
175/* Find an entry in the second-level page table.. */ 188/* Find an entry in the second-level page table.. */
176static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address) 189static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
177{ 190{
178 return (pmd_t *) pgd_page(*dir) + 191 return (pmd_t *) pud_page(*pud) + pmd_index(address);
179 ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
180} 192}
181 193
182/* Find an entry in the third-level page table.. */ 194/* Find an entry in the third-level page table.. */
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 3aad751ccd5f..01e76e932e3f 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -33,7 +33,7 @@
33 * unpredictable things. The code (when it is written) to deal with 33 * unpredictable things. The code (when it is written) to deal with
34 * this problem will be in the update_mmu_cache() code for the r4k. 34 * this problem will be in the update_mmu_cache() code for the r4k.
35 */ 35 */
36#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) 36#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
37 37
38#define _PAGE_PRESENT (1<<6) /* implemented in software */ 38#define _PAGE_PRESENT (1<<6) /* implemented in software */
39#define _PAGE_READ (1<<7) /* implemented in software */ 39#define _PAGE_READ (1<<7) /* implemented in software */
@@ -123,7 +123,7 @@
123 123
124#endif 124#endif
125#endif 125#endif
126#endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */ 126#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
127 127
128#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) 128#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
129#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 129#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
@@ -140,7 +140,7 @@
140#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW 140#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
141#endif 141#endif
142 142
143#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) 143#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
144#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3) 144#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
145#else 145#else
146#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) 146#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index eaf5d9b3a0e1..1e8ae2723be4 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -8,8 +8,6 @@
8#ifndef _ASM_PGTABLE_H 8#ifndef _ASM_PGTABLE_H
9#define _ASM_PGTABLE_H 9#define _ASM_PGTABLE_H
10 10
11#include <asm-generic/4level-fixup.h>
12
13#include <linux/config.h> 11#include <linux/config.h>
14#ifdef CONFIG_32BIT 12#ifdef CONFIG_32BIT
15#include <asm/pgtable-32.h> 13#include <asm/pgtable-32.h>
@@ -18,6 +16,7 @@
18#include <asm/pgtable-64.h> 16#include <asm/pgtable-64.h>
19#endif 17#endif
20 18
19#include <asm/io.h>
21#include <asm/pgtable-bits.h> 20#include <asm/pgtable-bits.h>
22 21
23#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) 22#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
@@ -84,7 +83,7 @@ extern void paging_init(void);
84#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) 83#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
85#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) 84#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
86 85
87#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 86#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
88static inline void set_pte(pte_t *ptep, pte_t pte) 87static inline void set_pte(pte_t *ptep, pte_t pte)
89{ 88{
90 ptep->pte_high = pte.pte_high; 89 ptep->pte_high = pte.pte_high;
@@ -148,11 +147,18 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
148#endif 147#endif
149 148
150/* 149/*
151 * (pmds are folded into pgds so this doesn't get actually called, 150 * (pmds are folded into puds so this doesn't get actually called,
152 * but the define is needed for a generic inline function.) 151 * but the define is needed for a generic inline function.)
153 */ 152 */
154#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0) 153#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
155#define set_pgd(pgdptr, pgdval) do { *(pgdptr) = (pgdval); } while(0) 154
155#ifdef CONFIG_64BIT
156/*
157 * (puds are folded into pgds so this doesn't get actually called,
158 * but the define is needed for a generic inline function.)
159 */
160#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
161#endif
156 162
157#define PGD_T_LOG2 ffz(~sizeof(pgd_t)) 163#define PGD_T_LOG2 ffz(~sizeof(pgd_t))
158#define PMD_T_LOG2 ffz(~sizeof(pmd_t)) 164#define PMD_T_LOG2 ffz(~sizeof(pmd_t))
@@ -165,7 +171,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
165 * Undefined behaviour if not.. 171 * Undefined behaviour if not..
166 */ 172 */
167static inline int pte_user(pte_t pte) { BUG(); return 0; } 173static inline int pte_user(pte_t pte) { BUG(); return 0; }
168#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 174#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
169static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; } 175static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; }
170static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; } 176static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; }
171static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; } 177static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; }
@@ -324,7 +330,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
324 */ 330 */
325#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 331#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
326 332
327#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 333#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
328static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 334static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
329{ 335{
330 pte.pte_low &= _PAGE_CHG_MASK; 336 pte.pte_low &= _PAGE_CHG_MASK;
@@ -357,7 +363,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
357#endif 363#endif
358 364
359#ifdef CONFIG_64BIT_PHYS_ADDR 365#ifdef CONFIG_64BIT_PHYS_ADDR
360extern phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size);
361extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); 366extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
362 367
363static inline int io_remap_pfn_range(struct vm_area_struct *vma, 368static inline int io_remap_pfn_range(struct vm_area_struct *vma,
@@ -367,7 +372,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
367 pgprot_t prot) 372 pgprot_t prot)
368{ 373{
369 phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); 374 phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
370 return remap_pfn_range(vma, vaddr, pfn, size, prot); 375 return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
371} 376}
372#else 377#else
373#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ 378#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index d6466aa09fb7..f1980c6c3bcc 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -96,12 +96,26 @@ union mips_fpu_union {
96 {{0,},} \ 96 {{0,},} \
97} 97}
98 98
99#define NUM_DSP_REGS 6
100
101typedef __u32 dspreg_t;
102
103struct mips_dsp_state {
104 dspreg_t dspr[NUM_DSP_REGS];
105 unsigned int dspcontrol;
106 unsigned short used_dsp;
107};
108
109#define INIT_DSP {{0,},}
110
99typedef struct { 111typedef struct {
100 unsigned long seg; 112 unsigned long seg;
101} mm_segment_t; 113} mm_segment_t;
102 114
103#define ARCH_MIN_TASKALIGN 8 115#define ARCH_MIN_TASKALIGN 8
104 116
117struct mips_abi;
118
105/* 119/*
106 * If you change thread_struct remember to change the #defines below too! 120 * If you change thread_struct remember to change the #defines below too!
107 */ 121 */
@@ -117,6 +131,9 @@ struct thread_struct {
117 /* Saved fpu/fpu emulator stuff. */ 131 /* Saved fpu/fpu emulator stuff. */
118 union mips_fpu_union fpu; 132 union mips_fpu_union fpu;
119 133
134 /* Saved state of the DSP ASE, if available. */
135 struct mips_dsp_state dsp;
136
120 /* Other stuff associated with the thread. */ 137 /* Other stuff associated with the thread. */
121 unsigned long cp0_badvaddr; /* Last user fault */ 138 unsigned long cp0_badvaddr; /* Last user fault */
122 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 139 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
@@ -129,6 +146,7 @@ struct thread_struct {
129 unsigned long mflags; 146 unsigned long mflags;
130 unsigned long irix_trampoline; /* Wheee... */ 147 unsigned long irix_trampoline; /* Wheee... */
131 unsigned long irix_oldctx; 148 unsigned long irix_oldctx;
149 struct mips_abi *abi;
132}; 150};
133 151
134#define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR) 152#define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR)
@@ -151,6 +169,10 @@ struct thread_struct {
151 */ \ 169 */ \
152 INIT_FPU, \ 170 INIT_FPU, \
153 /* \ 171 /* \
172 * saved dsp/dsp emulator stuff \
173 */ \
174 INIT_DSP, \
175 /* \
154 * Other stuff associated with the process \ 176 * Other stuff associated with the process \
155 */ \ 177 */ \
156 0, 0, 0, 0, \ 178 0, 0, 0, 0, \
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 2b5c624c3d4f..95c5839ac465 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -22,6 +22,8 @@
22#define MMLO 68 22#define MMLO 68
23#define FPC_CSR 69 23#define FPC_CSR 69
24#define FPC_EIR 70 24#define FPC_EIR 70
25#define DSP_BASE 71 /* 3 more hi / lo register pairs */
26#define DSP_CONTROL 77
25 27
26/* 28/*
27 * This struct defines the way the registers are stored on the stack during a 29 * This struct defines the way the registers are stored on the stack during a
@@ -38,18 +40,18 @@ struct pt_regs {
38 40
39 /* Saved special registers. */ 41 /* Saved special registers. */
40 unsigned long cp0_status; 42 unsigned long cp0_status;
41 unsigned long lo;
42 unsigned long hi; 43 unsigned long hi;
44 unsigned long lo;
43 unsigned long cp0_badvaddr; 45 unsigned long cp0_badvaddr;
44 unsigned long cp0_cause; 46 unsigned long cp0_cause;
45 unsigned long cp0_epc; 47 unsigned long cp0_epc;
46}; 48};
47 49
48/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ 50/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
49/* #define PTRACE_GETREGS 12 */ 51#define PTRACE_GETREGS 12
50/* #define PTRACE_SETREGS 13 */ 52#define PTRACE_SETREGS 13
51/* #define PTRACE_GETFPREGS 14 */ 53#define PTRACE_GETFPREGS 14
52/* #define PTRACE_SETFPREGS 15 */ 54#define PTRACE_SETFPREGS 15
53/* #define PTRACE_GETFPXREGS 18 */ 55/* #define PTRACE_GETFPXREGS 18 */
54/* #define PTRACE_SETFPXREGS 19 */ 56/* #define PTRACE_SETFPXREGS 19 */
55 57
@@ -58,6 +60,13 @@ struct pt_regs {
58#define PTRACE_GET_THREAD_AREA 25 60#define PTRACE_GET_THREAD_AREA 25
59#define PTRACE_SET_THREAD_AREA 26 61#define PTRACE_SET_THREAD_AREA 26
60 62
63/* Calls to trace a 64bit program from a 32bit program. */
64#define PTRACE_PEEKTEXT_3264 0xc0
65#define PTRACE_PEEKDATA_3264 0xc1
66#define PTRACE_POKETEXT_3264 0xc2
67#define PTRACE_POKEDATA_3264 0xc3
68#define PTRACE_GET_THREAD_AREA_3264 0xc4
69
61#ifdef __KERNEL__ 70#ifdef __KERNEL__
62 71
63#include <linux/linkage.h> 72#include <linux/linkage.h>
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 5bea49feec66..a5ea9d828aee 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -21,7 +21,7 @@
21 * 21 *
22 * - The MIPS32 and MIPS64 specs permit an implementation to directly derive 22 * - The MIPS32 and MIPS64 specs permit an implementation to directly derive
23 * the index bits from the virtual address. This breaks with tradition 23 * the index bits from the virtual address. This breaks with tradition
24 * set by the R4000. To keep unpleassant surprises from happening we pick 24 * set by the R4000. To keep unpleasant surprises from happening we pick
25 * an address in KSEG0 / CKSEG0. 25 * an address in KSEG0 / CKSEG0.
26 * - We need a properly sign extended address for 64-bit code. To get away 26 * - We need a properly sign extended address for 64-bit code. To get away
27 * without ifdefs we let the compiler do it by a type cast. 27 * without ifdefs we let the compiler do it by a type cast.
@@ -30,11 +30,11 @@
30 30
31#define cache_op(op,addr) \ 31#define cache_op(op,addr) \
32 __asm__ __volatile__( \ 32 __asm__ __volatile__( \
33 " .set push \n" \
33 " .set noreorder \n" \ 34 " .set noreorder \n" \
34 " .set mips3\n\t \n" \ 35 " .set mips3\n\t \n" \
35 " cache %0, %1 \n" \ 36 " cache %0, %1 \n" \
36 " .set mips0 \n" \ 37 " .set pop \n" \
37 " .set reorder" \
38 : \ 38 : \
39 : "i" (op), "m" (*(unsigned char *)(addr))) 39 : "i" (op), "m" (*(unsigned char *)(addr)))
40 40
@@ -84,14 +84,14 @@ static inline void flush_scache_line(unsigned long addr)
84static inline void protected_flush_icache_line(unsigned long addr) 84static inline void protected_flush_icache_line(unsigned long addr)
85{ 85{
86 __asm__ __volatile__( 86 __asm__ __volatile__(
87 ".set noreorder\n\t" 87 " .set push \n"
88 ".set mips3\n" 88 " .set noreorder \n"
89 "1:\tcache %0,(%1)\n" 89 " .set mips3 \n"
90 "2:\t.set mips0\n\t" 90 "1: cache %0, (%1) \n"
91 ".set reorder\n\t" 91 "2: .set pop \n"
92 ".section\t__ex_table,\"a\"\n\t" 92 " .section __ex_table,\"a\" \n"
93 STR(PTR)"\t1b,2b\n\t" 93 " "STR(PTR)" 1b, 2b \n"
94 ".previous" 94 " .previous"
95 : 95 :
96 : "i" (Hit_Invalidate_I), "r" (addr)); 96 : "i" (Hit_Invalidate_I), "r" (addr));
97} 97}
@@ -100,19 +100,19 @@ static inline void protected_flush_icache_line(unsigned long addr)
100 * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D 100 * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
101 * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style 101 * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
102 * caches. We're talking about one cacheline unnecessarily getting invalidated 102 * caches. We're talking about one cacheline unnecessarily getting invalidated
103 * here so the penaltiy isn't overly hard. 103 * here so the penalty isn't overly hard.
104 */ 104 */
105static inline void protected_writeback_dcache_line(unsigned long addr) 105static inline void protected_writeback_dcache_line(unsigned long addr)
106{ 106{
107 __asm__ __volatile__( 107 __asm__ __volatile__(
108 ".set noreorder\n\t" 108 " .set push \n"
109 ".set mips3\n" 109 " .set noreorder \n"
110 "1:\tcache %0,(%1)\n" 110 " .set mips3 \n"
111 "2:\t.set mips0\n\t" 111 "1: cache %0, (%1) \n"
112 ".set reorder\n\t" 112 "2: .set pop \n"
113 ".section\t__ex_table,\"a\"\n\t" 113 " .section __ex_table,\"a\" \n"
114 STR(PTR)"\t1b,2b\n\t" 114 " "STR(PTR)" 1b, 2b \n"
115 ".previous" 115 " .previous"
116 : 116 :
117 : "i" (Hit_Writeback_Inv_D), "r" (addr)); 117 : "i" (Hit_Writeback_Inv_D), "r" (addr));
118} 118}
@@ -120,14 +120,14 @@ static inline void protected_writeback_dcache_line(unsigned long addr)
120static inline void protected_writeback_scache_line(unsigned long addr) 120static inline void protected_writeback_scache_line(unsigned long addr)
121{ 121{
122 __asm__ __volatile__( 122 __asm__ __volatile__(
123 ".set noreorder\n\t" 123 " .set push \n"
124 ".set mips3\n" 124 " .set noreorder \n"
125 "1:\tcache %0,(%1)\n" 125 " .set mips3 \n"
126 "2:\t.set mips0\n\t" 126 "1: cache %0, (%1) \n"
127 ".set reorder\n\t" 127 "2: .set pop \n"
128 ".section\t__ex_table,\"a\"\n\t" 128 " .section __ex_table,\"a\" \n"
129 STR(PTR)"\t1b,2b\n\t" 129 " "STR(PTR)" 1b, 2b \n"
130 ".previous" 130 " .previous"
131 : 131 :
132 : "i" (Hit_Writeback_Inv_SD), "r" (addr)); 132 : "i" (Hit_Writeback_Inv_SD), "r" (addr));
133} 133}
@@ -142,6 +142,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
142 142
143#define cache16_unroll32(base,op) \ 143#define cache16_unroll32(base,op) \
144 __asm__ __volatile__( \ 144 __asm__ __volatile__( \
145 " .set push \n" \
145 " .set noreorder \n" \ 146 " .set noreorder \n" \
146 " .set mips3 \n" \ 147 " .set mips3 \n" \
147 " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ 148 " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
@@ -160,8 +161,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
160 " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ 161 " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
161 " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ 162 " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
162 " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ 163 " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
163 " .set mips0 \n" \ 164 " .set pop \n" \
164 " .set reorder \n" \
165 : \ 165 : \
166 : "r" (base), \ 166 : "r" (base), \
167 "i" (op)); 167 "i" (op));
@@ -285,6 +285,7 @@ static inline void blast_scache16_page_indexed(unsigned long page)
285 285
286#define cache32_unroll32(base,op) \ 286#define cache32_unroll32(base,op) \
287 __asm__ __volatile__( \ 287 __asm__ __volatile__( \
288 " .set push \n" \
288 " .set noreorder \n" \ 289 " .set noreorder \n" \
289 " .set mips3 \n" \ 290 " .set mips3 \n" \
290 " cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \ 291 " cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \
@@ -303,8 +304,7 @@ static inline void blast_scache16_page_indexed(unsigned long page)
303 " cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \ 304 " cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \
304 " cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \ 305 " cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \
305 " cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \ 306 " cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \
306 " .set mips0 \n" \ 307 " .set pop \n" \
307 " .set reorder \n" \
308 : \ 308 : \
309 : "r" (base), \ 309 : "r" (base), \
310 "i" (op)); 310 "i" (op));
@@ -428,6 +428,7 @@ static inline void blast_scache32_page_indexed(unsigned long page)
428 428
429#define cache64_unroll32(base,op) \ 429#define cache64_unroll32(base,op) \
430 __asm__ __volatile__( \ 430 __asm__ __volatile__( \
431 " .set push \n" \
431 " .set noreorder \n" \ 432 " .set noreorder \n" \
432 " .set mips3 \n" \ 433 " .set mips3 \n" \
433 " cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \ 434 " cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \
@@ -446,8 +447,7 @@ static inline void blast_scache32_page_indexed(unsigned long page)
446 " cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \ 447 " cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \
447 " cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \ 448 " cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \
448 " cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \ 449 " cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \
449 " .set mips0 \n" \ 450 " .set pop \n" \
450 " .set reorder \n" \
451 : \ 451 : \
452 : "r" (base), \ 452 : "r" (base), \
453 "i" (op)); 453 "i" (op));
@@ -532,6 +532,7 @@ static inline void blast_scache64_page_indexed(unsigned long page)
532 532
533#define cache128_unroll32(base,op) \ 533#define cache128_unroll32(base,op) \
534 __asm__ __volatile__( \ 534 __asm__ __volatile__( \
535 " .set push \n" \
535 " .set noreorder \n" \ 536 " .set noreorder \n" \
536 " .set mips3 \n" \ 537 " .set mips3 \n" \
537 " cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \ 538 " cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \
@@ -550,8 +551,7 @@ static inline void blast_scache64_page_indexed(unsigned long page)
550 " cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \ 551 " cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \
551 " cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \ 552 " cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \
552 " cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \ 553 " cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \
553 " .set mips0 \n" \ 554 " .set pop \n" \
554 " .set reorder \n" \
555 : \ 555 : \
556 : "r" (base), \ 556 : "r" (base), \
557 "i" (op)); 557 "i" (op));
diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h
index 3c4b637fd925..a60e0dc7c9b9 100644
--- a/include/asm-mips/rtc.h
+++ b/include/asm-mips/rtc.h
@@ -14,7 +14,9 @@
14 14
15#ifdef __KERNEL__ 15#ifdef __KERNEL__
16 16
17#include <linux/spinlock.h>
17#include <linux/rtc.h> 18#include <linux/rtc.h>
19#include <asm/time.h>
18 20
19#define RTC_PIE 0x40 /* periodic interrupt enable */ 21#define RTC_PIE 0x40 /* periodic interrupt enable */
20#define RTC_AIE 0x20 /* alarm interrupt enable */ 22#define RTC_AIE 0x20 /* alarm interrupt enable */
@@ -27,11 +29,52 @@
27#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ 29#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
28#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ 30#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
29 31
30unsigned int get_rtc_time(struct rtc_time *time); 32static DEFINE_SPINLOCK(mips_rtc_lock);
31int set_rtc_time(struct rtc_time *time);
32unsigned int get_rtc_ss(void);
33int get_rtc_pll(struct rtc_pll_info *pll);
34int set_rtc_pll(struct rtc_pll_info *pll);
35 33
34static inline unsigned int get_rtc_time(struct rtc_time *time)
35{
36 unsigned long nowtime;
37
38 spin_lock(&mips_rtc_lock);
39 nowtime = rtc_get_time();
40 to_tm(nowtime, time);
41 time->tm_year -= 1900;
42 spin_unlock(&mips_rtc_lock);
43
44 return RTC_24H;
45}
46
47static inline int set_rtc_time(struct rtc_time *time)
48{
49 unsigned long nowtime;
50 int ret;
51
52 spin_lock(&mips_rtc_lock);
53 nowtime = mktime(time->tm_year+1900, time->tm_mon+1,
54 time->tm_mday, time->tm_hour, time->tm_min,
55 time->tm_sec);
56 ret = rtc_set_time(nowtime);
57 spin_unlock(&mips_rtc_lock);
58
59 return ret;
60}
61
62static inline unsigned int get_rtc_ss(void)
63{
64 struct rtc_time h;
65
66 get_rtc_time(&h);
67 return h.tm_sec;
68}
69
70static inline int get_rtc_pll(struct rtc_pll_info *pll)
71{
72 return -EINVAL;
73}
74
75static inline int set_rtc_pll(struct rtc_pll_info *pll)
76{
77 return -EINVAL;
78}
36#endif 79#endif
37#endif 80#endif
diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h
new file mode 100644
index 000000000000..83cdf6ab0d1f
--- /dev/null
+++ b/include/asm-mips/rtlx.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 */
5
6#ifndef _RTLX_H
7#define _RTLX_H_
8
9#define LX_NODE_BASE 10
10
11#define MIPSCPU_INT_BASE 16
12#define MIPS_CPU_RTLX_IRQ 0
13
14#define RTLX_VERSION 1
15#define RTLX_xID 0x12345600
16#define RTLX_ID (RTLX_xID | RTLX_VERSION)
17#define RTLX_CHANNELS 8
18
19enum rtlx_state {
20 RTLX_STATE_UNUSED = 0,
21 RTLX_STATE_INITIALISED,
22 RTLX_STATE_REMOTE_READY,
23 RTLX_STATE_OPENED
24};
25
26#define RTLX_BUFFER_SIZE 1024
27/* each channel supports read and write.
28 linux (vpe0) reads lx_buffer and writes rt_buffer
29 SP (vpe1) reads rt_buffer and writes lx_buffer
30*/
31typedef struct rtlx_channel {
32 enum rtlx_state rt_state;
33 enum rtlx_state lx_state;
34
35 int buffer_size;
36
37 /* read and write indexes per buffer */
38 int rt_write, rt_read;
39 char *rt_buffer;
40
41 int lx_write, lx_read;
42 char *lx_buffer;
43
44 void *queues;
45
46} rtlx_channel_t;
47
48typedef struct rtlx_info {
49 unsigned long id;
50 enum rtlx_state state;
51
52 struct rtlx_channel channel[RTLX_CHANNELS];
53
54} rtlx_info_t;
55
56#endif
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 4eed8e2acdc3..e796d75f027e 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -52,16 +52,6 @@
52#define JAZZ_SERIAL_PORT_DEFNS 52#define JAZZ_SERIAL_PORT_DEFNS
53#endif 53#endif
54 54
55#ifdef CONFIG_MIPS_COBALT
56#include <asm/cobalt/cobalt.h>
57#define COBALT_BASE_BAUD (18432000 / 16)
58#define COBALT_SERIAL_PORT_DEFNS \
59 /* UART CLK PORT IRQ FLAGS */ \
60 { 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS }, /* ttyS0 */
61#else
62#define COBALT_SERIAL_PORT_DEFNS
63#endif
64
65/* 55/*
66 * Both Galileo boards have the same UART mappings. 56 * Both Galileo boards have the same UART mappings.
67 */ 57 */
@@ -113,17 +103,6 @@
113#define IVR_SERIAL_PORT_DEFNS 103#define IVR_SERIAL_PORT_DEFNS
114#endif 104#endif
115 105
116#ifdef CONFIG_TOSHIBA_JMR3927
117#include <asm/jmr3927/jmr3927.h>
118#define TXX927_SERIAL_PORT_DEFNS \
119 { .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT, \
120 .flags = UART0_FLAGS, .type = 1 }, \
121 { .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT, \
122 .flags = UART1_FLAGS, .type = 1 },
123#else
124#define TXX927_SERIAL_PORT_DEFNS
125#endif
126
127#ifdef CONFIG_SERIAL_AU1X00 106#ifdef CONFIG_SERIAL_AU1X00
128#include <asm/mach-au1x00/au1000.h> 107#include <asm/mach-au1x00/au1000.h>
129#ifdef CONFIG_SOC_AU1000 108#ifdef CONFIG_SOC_AU1000
@@ -227,9 +206,9 @@
227#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L 206#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
228 207
229#define _JAGUAR_ATX_SERIAL_INIT(int, base) \ 208#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
230 { baud_base: JAGUAR_ATX_BASE_BAUD, irq: int, \ 209 { .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int, \
231 flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 210 .flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
232 iomem_base: (u8 *) base, iomem_reg_shift: 2, \ 211 .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
233 io_type: SERIAL_IO_MEM } 212 io_type: SERIAL_IO_MEM }
234#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \ 213#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
235 _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE) 214 _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
@@ -243,9 +222,9 @@
243#define OCELOT_3_SERIAL_BASE (signed)0xfd000020 222#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
244 223
245#define _OCELOT_3_SERIAL_INIT(int, base) \ 224#define _OCELOT_3_SERIAL_INIT(int, base) \
246 { baud_base: OCELOT_3_BASE_BAUD, irq: int, \ 225 { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \
247 flags: STD_COM_FLAGS, \ 226 .flags = STD_COM_FLAGS, \
248 iomem_base: (u8 *) base, iomem_reg_shift: 2, \ 227 .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
249 io_type: SERIAL_IO_MEM } 228 io_type: SERIAL_IO_MEM }
250 229
251#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ 230#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
@@ -342,7 +321,6 @@
342#endif /* CONFIG_SGI_IP32 */ 321#endif /* CONFIG_SGI_IP32 */
343 322
344#define SERIAL_PORT_DFNS \ 323#define SERIAL_PORT_DFNS \
345 COBALT_SERIAL_PORT_DEFNS \
346 DDB5477_SERIAL_PORT_DEFNS \ 324 DDB5477_SERIAL_PORT_DEFNS \
347 EV96100_SERIAL_PORT_DEFNS \ 325 EV96100_SERIAL_PORT_DEFNS \
348 IP32_SERIAL_PORT_DEFNS \ 326 IP32_SERIAL_PORT_DEFNS \
@@ -354,7 +332,6 @@
354 MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ 332 MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
355 MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ 333 MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
356 MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ 334 MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
357 TXX927_SERIAL_PORT_DEFNS \
358 AU1000_SERIAL_PORT_DEFNS 335 AU1000_SERIAL_PORT_DEFNS
359 336
360#endif /* _ASM_SERIAL_H */ 337#endif /* _ASM_SERIAL_H */
diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h
new file mode 100644
index 000000000000..42d4cf00efd3
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_int.h
@@ -0,0 +1,310 @@
1/* *********************************************************************
2 * BCM1280/BCM1480 Board Support Package
3 *
4 * Interrupt Mapper definitions File: bcm1480_int.h
5 *
6 * This module contains constants for manipulating the
7 * BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and
8 * definitions for the interrupt sources.
9 *
10 * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
11 *
12 *********************************************************************
13 *
14 * Copyright 2000,2001,2002,2003
15 * Broadcom Corporation. All rights reserved.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 ********************************************************************* */
32
33
34#ifndef _BCM1480_INT_H
35#define _BCM1480_INT_H
36
37#include "sb1250_defs.h"
38
39/* *********************************************************************
40 * Interrupt Mapper Constants
41 ********************************************************************* */
42
43/*
44 * The interrupt mapper deals with 128-bit logical registers that are
45 * implemented as pairs of 64-bit registers, with the "low" 64 bits in
46 * a register that has an address 0x1000 higher(!) than the
47 * corresponding "high" register.
48 *
49 * For appropriate registers, bit 0 of the "high" register is a
50 * cascade bit that summarizes (as a bit-OR) the 64 bits of the "low"
51 * register.
52 */
53
54/*
55 * This entire file uses _BCM1480_ in all the symbols because it is
56 * entirely BCM1480 specific.
57 */
58
59/*
60 * Interrupt sources (Table 22)
61 */
62
63#define K_BCM1480_INT_SOURCES 128
64
65#define _BCM1480_INT_HIGH(k) (k)
66#define _BCM1480_INT_LOW(k) ((k)+64)
67
68#define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1)
69#define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4)
70#define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5)
71#define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6)
72#define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7)
73#define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8)
74#define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9)
75#define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10)
76#define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11)
77#define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12)
78#define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13)
79#define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14)
80#define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15)
81#define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20)
82#define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21)
83#define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22)
84#define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23)
85#define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28)
86#define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29)
87#define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30)
88#define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31)
89#define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36)
90#define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37)
91#define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38)
92#define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39)
93#define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40)
94#define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41)
95#define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42)
96#define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43)
97#define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52)
98#define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53)
99#define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54)
100#define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55)
101#define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56)
102#define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57)
103#define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58)
104#define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59)
105#define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60)
106#define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61)
107#define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62)
108#define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63)
109
110#define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1)
111#define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2)
112#define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3)
113#define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4)
114#define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5)
115#define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6)
116#define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7)
117#define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8)
118#define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9)
119#define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10)
120#define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11)
121#define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16)
122#define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17)
123#define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18)
124#define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19)
125#define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20)
126#define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21)
127#define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22)
128#define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23)
129#define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24)
130#define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25)
131#define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32)
132#define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33)
133#define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34)
134#define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35)
135#define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36)
136#define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40)
137#define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41)
138#define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42)
139#define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44)
140#define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45)
141#define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46)
142#define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47)
143#define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52)
144#define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53)
145#define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54)
146#define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55)
147#define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56)
148#define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57)
149#define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58)
150#define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59)
151#define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60)
152#define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61)
153#define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62)
154#define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63)
155
156/*
157 * Mask values for each interrupt
158 */
159
160#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F))
161#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6)
162
163#define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
164
165#define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
166#define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
167#define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
168#define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
169#define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
170#define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
171#define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
172#define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
173#define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
174#define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
175#define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
176#define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
177#define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
178#define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
179#define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
180#define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
181#define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
182#define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
183#define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
184#define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
185#define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
186#define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
187#define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
188#define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
189#define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
190#define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
191#define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
192#define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
193#define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
194#define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
195#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
196#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
197#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
198#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
199#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
200#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
201#define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
202#define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
203#define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
204#define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
205#define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
206#define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
207#define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
208#define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
209#define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
210#define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
211#define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
212#define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
213#define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
214#define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
215#define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
216#define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
217#define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
218#define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
219#define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
220#define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
221#define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
222#define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
223#define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
224#define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
225#define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
226#define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
227#define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
228#define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
229#define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
230#define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
231#define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
232#define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
233#define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
234#define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
235#define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
236#define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
237#define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
238#define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
239#define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
240#define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
241#define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
242#define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
243#define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
244#define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
245#define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
246#define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
247#define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
248#define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
249#define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
250#define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
251
252/*
253 * Interrupt mappings (Table 18)
254 */
255
256#define K_BCM1480_INT_MAP_I0 0 /* interrupt pins on processor */
257#define K_BCM1480_INT_MAP_I1 1
258#define K_BCM1480_INT_MAP_I2 2
259#define K_BCM1480_INT_MAP_I3 3
260#define K_BCM1480_INT_MAP_I4 4
261#define K_BCM1480_INT_MAP_I5 5
262#define K_BCM1480_INT_MAP_NMI 6 /* nonmaskable */
263#define K_BCM1480_INT_MAP_DINT 7 /* debug interrupt */
264
265/*
266 * Interrupt LDT Set Register (Table 19)
267 */
268
269#define S_BCM1480_INT_HT_INTMSG 0
270#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG)
271#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG)
272#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG)
273
274#define K_BCM1480_INT_HT_INTMSG_FIXED 0
275#define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1
276#define K_BCM1480_INT_HT_INTMSG_SMI 2
277#define K_BCM1480_INT_HT_INTMSG_NMI 3
278#define K_BCM1480_INT_HT_INTMSG_INIT 4
279#define K_BCM1480_INT_HT_INTMSG_STARTUP 5
280#define K_BCM1480_INT_HT_INTMSG_EXTINT 6
281#define K_BCM1480_INT_HT_INTMSG_RESERVED 7
282
283#define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3)
284#define V_BCM1480_INT_HT_EDGETRIGGER 0
285#define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE
286
287#define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4)
288#define V_BCM1480_INT_HT_PHYSICALDEST 0
289#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE
290
291#define S_BCM1480_INT_HT_INTDEST 5
292#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST)
293#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST)
294#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST)
295
296#define S_BCM1480_INT_HT_VECTOR 13
297#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR)
298#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR)
299#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR)
300
301/*
302 * Vector prefix (Table 4-7)
303 */
304
305#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH 0x00
306#define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40
307#define M_BCM1480_HTVECT_RAISE_INTLDT_LO 0x80
308#define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0
309
310#endif /* _BCM1480_INT_H */
diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h
new file mode 100644
index 000000000000..886b099565e6
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_l2c.h
@@ -0,0 +1,176 @@
1/* *********************************************************************
2 * BCM1280/BCM1480 Board Support Package
3 *
4 * L2 Cache constants and macros File: bcm1480_l2c.h
5 *
6 * This module contains constants useful for manipulating the
7 * level 2 cache.
8 *
9 * BCM1400 specification level: 1280-UM100-D2 (11/14/03)
10 *
11 *********************************************************************
12 *
13 * Copyright 2000,2001,2002,2003
14 * Broadcom Corporation. All rights reserved.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 ********************************************************************* */
31
32
33#ifndef _BCM1480_L2C_H
34#define _BCM1480_L2C_H
35
36#include "sb1250_defs.h"
37
38/*
39 * Format of level 2 cache management address (Table 55)
40 */
41
42#define S_BCM1480_L2C_MGMT_INDEX 5
43#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_MGMT_INDEX)
44#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_INDEX)
45#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_INDEX,M_BCM1480_L2C_MGMT_INDEX)
46
47#define S_BCM1480_L2C_MGMT_WAY 17
48#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_MGMT_WAY)
49#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_WAY)
50#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_WAY,M_BCM1480_L2C_MGMT_WAY)
51
52#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20)
53#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21)
54
55#define S_BCM1480_L2C_MGMT_ECC_DIAG 22
56#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_BCM1480_L2C_MGMT_ECC_DIAG)
57#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG)
58#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG,M_BCM1480_L2C_MGMT_ECC_DIAG)
59
60#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000
61
62#define BCM1480_L2C_ENTRIES_PER_WAY 4096
63#define BCM1480_L2C_NUM_WAYS 8
64
65
66/*
67 * Level 2 Cache Tag register (Table 59)
68 */
69
70#define S_BCM1480_L2C_TAG_MBZ 0
71#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5,S_BCM1480_L2C_TAG_MBZ)
72
73#define S_BCM1480_L2C_TAG_INDEX 5
74#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_TAG_INDEX)
75#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_INDEX)
76#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_INDEX,M_BCM1480_L2C_TAG_INDEX)
77
78/* Note that index bit 16 is also tag bit 40 */
79#define S_BCM1480_L2C_TAG_TAG 17
80#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23,S_BCM1480_L2C_TAG_TAG)
81#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_TAG)
82#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_TAG,M_BCM1480_L2C_TAG_TAG)
83
84#define S_BCM1480_L2C_TAG_ECC 40
85#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6,S_BCM1480_L2C_TAG_ECC)
86#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_ECC)
87#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_ECC,M_BCM1480_L2C_TAG_ECC)
88
89#define S_BCM1480_L2C_TAG_WAY 46
90#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_TAG_WAY)
91#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_WAY)
92#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_WAY,M_BCM1480_L2C_TAG_WAY)
93
94#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49)
95#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50)
96
97#define S_BCM1480_L2C_DATA_ECC 51
98#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10,S_BCM1480_L2C_DATA_ECC)
99#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_DATA_ECC)
100#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_DATA_ECC,M_BCM1480_L2C_DATA_ECC)
101
102
103/*
104 * L2 Misc0 Value Register (Table 60)
105 */
106
107#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0
108#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_REMOTE)
109#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_REMOTE,M_BCM1480_L2C_MISC0_WAY_REMOTE)
110
111#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8
112#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_LOCAL)
113#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_LOCAL,M_BCM1480_L2C_MISC0_WAY_LOCAL)
114
115#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16
116#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_ENABLE)
117#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_ENABLE,M_BCM1480_L2C_MISC0_WAY_ENABLE)
118
119#define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24
120#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_DISABLE)
121#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_DISABLE,M_BCM1480_L2C_MISC0_CACHE_DISABLE)
122
123#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26
124#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_QUAD)
125#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_QUAD,M_BCM1480_L2C_MISC0_CACHE_QUAD)
126
127#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30
128#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
129
130#define S_BCM1480_L2C_MISC0_ECC_CLEANUP 31
131#define M_BCM1480_L2C_MISC0_ECC_CLEANUP _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP)
132
133
134/*
135 * L2 Misc1 Value Register (Table 60)
136 */
137
138#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0
139#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_0)
140#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_0,M_BCM1480_L2C_MISC1_WAY_AGENT_0)
141
142#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8
143#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_1)
144#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_1,M_BCM1480_L2C_MISC1_WAY_AGENT_1)
145
146#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16
147#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_2)
148#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_2,M_BCM1480_L2C_MISC1_WAY_AGENT_2)
149
150#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24
151#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_3)
152#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_3,M_BCM1480_L2C_MISC1_WAY_AGENT_3)
153
154#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32
155#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_4)
156#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_4,M_BCM1480_L2C_MISC1_WAY_AGENT_4)
157
158
159/*
160 * L2 Misc2 Value Register (Table 60)
161 */
162
163#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0
164#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_8)
165#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_8,M_BCM1480_L2C_MISC2_WAY_AGENT_8)
166
167#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8
168#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_9)
169#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_9,M_BCM1480_L2C_MISC2_WAY_AGENT_9)
170
171#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16
172#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_A)
173#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_A,M_BCM1480_L2C_MISC2_WAY_AGENT_A)
174
175
176#endif /* _BCM1480_L2C_H */
diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h
new file mode 100644
index 000000000000..6bdc941afc91
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_mc.h
@@ -0,0 +1,962 @@
1/* *********************************************************************
2 * BCM1280/BCM1480 Board Support Package
3 *
4 * Memory Controller constants File: bcm1480_mc.h
5 *
6 * This module contains constants and macros useful for
7 * programming the memory controller.
8 *
9 * BCM1400 specification level: 1280-UM100-D1 (11/14/03 Review Copy)
10 *
11 *********************************************************************
12 *
13 * Copyright 2000,2001,2002,2003
14 * Broadcom Corporation. All rights reserved.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 ********************************************************************* */
31
32
33#ifndef _BCM1480_MC_H
34#define _BCM1480_MC_H
35
36#include "sb1250_defs.h"
37
38/*
39 * Memory Channel Configuration Register (Table 81)
40 */
41
42#define S_BCM1480_MC_INTLV0 0
43#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0)
44#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0)
45#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0)
46#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0)
47
48#define S_BCM1480_MC_INTLV1 8
49#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1)
50#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1)
51#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1)
52#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0)
53
54#define S_BCM1480_MC_INTLV2 16
55#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2)
56#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2)
57#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2)
58#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0)
59
60#define S_BCM1480_MC_CS_MODE 32
61#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE)
62#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE)
63#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE)
64#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0)
65
66#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \
67 V_BCM1480_MC_INTLV1_DEFAULT | \
68 V_BCM1480_MC_INTLV2_DEFAULT | \
69 V_BCM1480_MC_CS_MODE_DEFAULT)
70
71#define K_BCM1480_MC_CS01_MODE 0x03
72#define K_BCM1480_MC_CS02_MODE 0x05
73#define K_BCM1480_MC_CS0123_MODE 0x0F
74#define K_BCM1480_MC_CS0246_MODE 0x55
75#define K_BCM1480_MC_CS0145_MODE 0x33
76#define K_BCM1480_MC_CS0167_MODE 0xC3
77#define K_BCM1480_MC_CSFULL_MODE 0xFF
78
79/*
80 * Chip Select Start Address Register (Table 82)
81 */
82
83#define S_BCM1480_MC_CS0_START 0
84#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START)
85#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START)
86#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START)
87
88#define S_BCM1480_MC_CS1_START 16
89#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START)
90#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START)
91#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START)
92
93#define S_BCM1480_MC_CS2_START 32
94#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START)
95#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START)
96#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START)
97
98#define S_BCM1480_MC_CS3_START 48
99#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START)
100#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START)
101#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START)
102
103/*
104 * Chip Select End Address Register (Table 83)
105 */
106
107#define S_BCM1480_MC_CS0_END 0
108#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END)
109#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END)
110#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END)
111
112#define S_BCM1480_MC_CS1_END 16
113#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END)
114#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END)
115#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END)
116
117#define S_BCM1480_MC_CS2_END 32
118#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END)
119#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END)
120#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END)
121
122#define S_BCM1480_MC_CS3_END 48
123#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END)
124#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END)
125#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END)
126
127/*
128 * Row Address Bit Select Register 0 (Table 84)
129 */
130
131#define S_BCM1480_MC_ROW00 0
132#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6,S_BCM1480_MC_ROW00)
133#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00)
134#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00)
135
136#define S_BCM1480_MC_ROW01 8
137#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6,S_BCM1480_MC_ROW01)
138#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01)
139#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01)
140
141#define S_BCM1480_MC_ROW02 16
142#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6,S_BCM1480_MC_ROW02)
143#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02)
144#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02)
145
146#define S_BCM1480_MC_ROW03 24
147#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6,S_BCM1480_MC_ROW03)
148#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03)
149#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03)
150
151#define S_BCM1480_MC_ROW04 32
152#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6,S_BCM1480_MC_ROW04)
153#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04)
154#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04)
155
156#define S_BCM1480_MC_ROW05 40
157#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6,S_BCM1480_MC_ROW05)
158#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05)
159#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05)
160
161#define S_BCM1480_MC_ROW06 48
162#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6,S_BCM1480_MC_ROW06)
163#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06)
164#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06)
165
166#define S_BCM1480_MC_ROW07 56
167#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6,S_BCM1480_MC_ROW07)
168#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07)
169#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07)
170
171/*
172 * Row Address Bit Select Register 1 (Table 85)
173 */
174
175#define S_BCM1480_MC_ROW08 0
176#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6,S_BCM1480_MC_ROW08)
177#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08)
178#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08)
179
180#define S_BCM1480_MC_ROW09 8
181#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6,S_BCM1480_MC_ROW09)
182#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09)
183#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09)
184
185#define S_BCM1480_MC_ROW10 16
186#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6,S_BCM1480_MC_ROW10)
187#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10)
188#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10)
189
190#define S_BCM1480_MC_ROW11 24
191#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6,S_BCM1480_MC_ROW11)
192#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11)
193#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11)
194
195#define S_BCM1480_MC_ROW12 32
196#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6,S_BCM1480_MC_ROW12)
197#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12)
198#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12)
199
200#define S_BCM1480_MC_ROW13 40
201#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6,S_BCM1480_MC_ROW13)
202#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13)
203#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13)
204
205#define S_BCM1480_MC_ROW14 48
206#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6,S_BCM1480_MC_ROW14)
207#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14)
208#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14)
209
210#define K_BCM1480_MC_ROWX_BIT_SPACING 8
211
212/*
213 * Column Address Bit Select Register 0 (Table 86)
214 */
215
216#define S_BCM1480_MC_COL00 0
217#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6,S_BCM1480_MC_COL00)
218#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL00)
219#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00)
220
221#define S_BCM1480_MC_COL01 8
222#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6,S_BCM1480_MC_COL01)
223#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL01)
224#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01)
225
226#define S_BCM1480_MC_COL02 16
227#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6,S_BCM1480_MC_COL02)
228#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL02)
229#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02)
230
231#define S_BCM1480_MC_COL03 24
232#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6,S_BCM1480_MC_COL03)
233#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL03)
234#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03)
235
236#define S_BCM1480_MC_COL04 32
237#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6,S_BCM1480_MC_COL04)
238#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL04)
239#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04)
240
241#define S_BCM1480_MC_COL05 40
242#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05)
243#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05)
244#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05)
245
246#define S_BCM1480_MC_COL06 48
247#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06)
248#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06)
249#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06)
250
251#define S_BCM1480_MC_COL07 56
252#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07)
253#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07)
254#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07)
255
256/*
257 * Column Address Bit Select Register 1 (Table 87)
258 */
259
260#define S_BCM1480_MC_COL08 0
261#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08)
262#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08)
263#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08)
264
265#define S_BCM1480_MC_COL09 8
266#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09)
267#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09)
268#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09)
269
270#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */
271
272#define S_BCM1480_MC_COL11 24
273#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11)
274#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11)
275#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11)
276
277#define S_BCM1480_MC_COL12 32
278#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12)
279#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12)
280#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12)
281
282#define S_BCM1480_MC_COL13 40
283#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13)
284#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13)
285#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13)
286
287#define S_BCM1480_MC_COL14 48
288#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14)
289#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14)
290#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14)
291
292#define K_BCM1480_MC_COLX_BIT_SPACING 8
293
294/*
295 * CS0 and CS1 Bank Address Bit Select Register (Table 88)
296 */
297
298#define S_BCM1480_MC_CS01_BANK0 0
299#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0)
300#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0)
301#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0)
302
303#define S_BCM1480_MC_CS01_BANK1 8
304#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1)
305#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1)
306#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1)
307
308#define S_BCM1480_MC_CS01_BANK2 16
309#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2)
310#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2)
311#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2)
312
313/*
314 * CS2 and CS3 Bank Address Bit Select Register (Table 89)
315 */
316
317#define S_BCM1480_MC_CS23_BANK0 0
318#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0)
319#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0)
320#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0)
321
322#define S_BCM1480_MC_CS23_BANK1 8
323#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1)
324#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1)
325#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1)
326
327#define S_BCM1480_MC_CS23_BANK2 16
328#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2)
329#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2)
330#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2)
331
332#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8
333
334/*
335 * DRAM Command Register (Table 90)
336 */
337
338#define S_BCM1480_MC_COMMAND 0
339#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND)
340#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND)
341#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND)
342
343#define K_BCM1480_MC_COMMAND_EMRS 0
344#define K_BCM1480_MC_COMMAND_MRS 1
345#define K_BCM1480_MC_COMMAND_PRE 2
346#define K_BCM1480_MC_COMMAND_AR 3
347#define K_BCM1480_MC_COMMAND_SETRFSH 4
348#define K_BCM1480_MC_COMMAND_CLRRFSH 5
349#define K_BCM1480_MC_COMMAND_SETPWRDN 6
350#define K_BCM1480_MC_COMMAND_CLRPWRDN 7
351
352#if SIBYTE_HDR_FEATURE(1480, PASS2)
353#define K_BCM1480_MC_COMMAND_EMRS2 8
354#define K_BCM1480_MC_COMMAND_EMRS3 9
355#define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10
356#define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11
357#endif
358
359#define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS)
360#define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS)
361#define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE)
362#define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR)
363#define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH)
364#define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH)
365#define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN)
366#define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN)
367
368#if SIBYTE_HDR_FEATURE(1480, PASS2)
369#define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2)
370#define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3)
371#define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK)
372#define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK)
373#endif
374
375#define S_BCM1480_MC_CS0 4
376#define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4)
377#define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5)
378#define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6)
379#define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7)
380#define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8)
381#define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9)
382#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10)
383#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11)
384
385#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16)
386
387/*
388 * DRAM Mode Register (Table 91)
389 */
390
391#define S_BCM1480_MC_EMODE 0
392#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE)
393#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE)
394#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE)
395#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0)
396
397#define S_BCM1480_MC_MODE 16
398#define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE)
399#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE)
400#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE)
401#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0)
402
403#define S_BCM1480_MC_DRAM_TYPE 32
404#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE)
405#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE)
406#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE)
407
408#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0
409#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1
410
411#if SIBYTE_HDR_FEATURE(1480, PASS2)
412#define K_BCM1480_MC_DRAM_TYPE_DDR2 2
413#endif
414
415#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
416#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
417
418#if SIBYTE_HDR_FEATURE(1480, PASS2)
419#define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2)
420#endif
421
422#define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36)
423#define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37)
424#define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38)
425#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39)
426
427#define S_BCM1480_MC_PG_POLICY 40
428#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY)
429#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY)
430#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY)
431
432#define K_BCM1480_MC_PG_POLICY_CLOSED 0
433#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1
434
435#define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED)
436#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
437
438#if SIBYTE_HDR_FEATURE(1480, PASS2)
439#define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42)
440#define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43)
441#endif
442
443#define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \
444 V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
445
446/*
447 * Memory Clock Configuration Register (Table 92)
448 */
449
450#define S_BCM1480_MC_CLK_RATIO 0
451#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO)
452#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO)
453#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO)
454
455#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10)
456
457#define S_BCM1480_MC_REF_RATE 8
458#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE)
459#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE)
460#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE)
461
462#define K_BCM1480_MC_REF_RATE_100MHz 0x31
463#define K_BCM1480_MC_REF_RATE_200MHz 0x62
464#define K_BCM1480_MC_REF_RATE_400MHz 0xC4
465
466#define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz)
467#define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz)
468#define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz)
469#define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz
470
471#if SIBYTE_HDR_FEATURE(1480, PASS2)
472#define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16)
473#endif
474
475/*
476 * ODT Register (Table 99)
477 */
478
479#if SIBYTE_HDR_FEATURE(1480, PASS2)
480#define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0)
481#define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1)
482#define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2)
483#define M_BCM1480_MC_RD_ODT0_CS6 _SB_MAKEMASK1(3)
484#define M_BCM1480_MC_WR_ODT0_CS0 _SB_MAKEMASK1(4)
485#define M_BCM1480_MC_WR_ODT0_CS2 _SB_MAKEMASK1(5)
486#define M_BCM1480_MC_WR_ODT0_CS4 _SB_MAKEMASK1(6)
487#define M_BCM1480_MC_WR_ODT0_CS6 _SB_MAKEMASK1(7)
488#define M_BCM1480_MC_RD_ODT2_CS0 _SB_MAKEMASK1(8)
489#define M_BCM1480_MC_RD_ODT2_CS2 _SB_MAKEMASK1(9)
490#define M_BCM1480_MC_RD_ODT2_CS4 _SB_MAKEMASK1(10)
491#define M_BCM1480_MC_RD_ODT2_CS6 _SB_MAKEMASK1(11)
492#define M_BCM1480_MC_WR_ODT2_CS0 _SB_MAKEMASK1(12)
493#define M_BCM1480_MC_WR_ODT2_CS2 _SB_MAKEMASK1(13)
494#define M_BCM1480_MC_WR_ODT2_CS4 _SB_MAKEMASK1(14)
495#define M_BCM1480_MC_WR_ODT2_CS6 _SB_MAKEMASK1(15)
496#define M_BCM1480_MC_RD_ODT4_CS0 _SB_MAKEMASK1(16)
497#define M_BCM1480_MC_RD_ODT4_CS2 _SB_MAKEMASK1(17)
498#define M_BCM1480_MC_RD_ODT4_CS4 _SB_MAKEMASK1(18)
499#define M_BCM1480_MC_RD_ODT4_CS6 _SB_MAKEMASK1(19)
500#define M_BCM1480_MC_WR_ODT4_CS0 _SB_MAKEMASK1(20)
501#define M_BCM1480_MC_WR_ODT4_CS2 _SB_MAKEMASK1(21)
502#define M_BCM1480_MC_WR_ODT4_CS4 _SB_MAKEMASK1(22)
503#define M_BCM1480_MC_WR_ODT4_CS6 _SB_MAKEMASK1(23)
504#define M_BCM1480_MC_RD_ODT6_CS0 _SB_MAKEMASK1(24)
505#define M_BCM1480_MC_RD_ODT6_CS2 _SB_MAKEMASK1(25)
506#define M_BCM1480_MC_RD_ODT6_CS4 _SB_MAKEMASK1(26)
507#define M_BCM1480_MC_RD_ODT6_CS6 _SB_MAKEMASK1(27)
508#define M_BCM1480_MC_WR_ODT6_CS0 _SB_MAKEMASK1(28)
509#define M_BCM1480_MC_WR_ODT6_CS2 _SB_MAKEMASK1(29)
510#define M_BCM1480_MC_WR_ODT6_CS4 _SB_MAKEMASK1(30)
511#define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31)
512
513#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32)
514#endif
515
516/*
517 * Memory DLL Configuration Register (Table 93)
518 */
519
520#define S_BCM1480_MC_ADDR_COARSE_ADJ 0
521#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ)
522#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ)
523#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ)
524#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0)
525
526#if SIBYTE_HDR_FEATURE(1480, PASS2)
527#define S_BCM1480_MC_ADDR_FREQ_RANGE 8
528#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE)
529#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE)
530#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE)
531#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4)
532#endif
533
534#define S_BCM1480_MC_ADDR_FINE_ADJ 8
535#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ)
536#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ)
537#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ)
538#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8)
539
540#define S_BCM1480_MC_DQI_COARSE_ADJ 16
541#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ)
542#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ)
543#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ)
544#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0)
545
546#if SIBYTE_HDR_FEATURE(1480, PASS2)
547#define S_BCM1480_MC_DQI_FREQ_RANGE 24
548#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE)
549#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE)
550#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE)
551#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4)
552#endif
553
554#define S_BCM1480_MC_DQI_FINE_ADJ 24
555#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ)
556#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ)
557#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ)
558#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8)
559
560#define S_BCM1480_MC_DQO_COARSE_ADJ 32
561#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ)
562#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ)
563#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ)
564#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0)
565
566#if SIBYTE_HDR_FEATURE(1480, PASS2)
567#define S_BCM1480_MC_DQO_FREQ_RANGE 40
568#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE)
569#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE)
570#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE)
571#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4)
572#endif
573
574#define S_BCM1480_MC_DQO_FINE_ADJ 40
575#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ)
576#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ)
577#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ)
578#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8)
579
580#if SIBYTE_HDR_FEATURE(1480, PASS2)
581#define S_BCM1480_MC_DLL_PDSEL 44
582#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL)
583#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL)
584#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL)
585#define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0)
586
587#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46)
588#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47)
589#endif
590
591#define S_BCM1480_MC_DLL_DEFAULT 48
592#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT)
593#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT)
594#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT)
595#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10)
596
597#if SIBYTE_HDR_FEATURE(1480, PASS2)
598#define S_BCM1480_MC_DLL_REGCTRL 54
599#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL)
600#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL)
601#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL)
602#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0)
603#endif
604
605#if SIBYTE_HDR_FEATURE(1480, PASS2)
606#define S_BCM1480_MC_DLL_FREQ_RANGE 56
607#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE)
608#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE)
609#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE)
610#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4)
611#endif
612
613#define S_BCM1480_MC_DLL_STEP_SIZE 56
614#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE)
615#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE)
616#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE)
617#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8)
618
619#if SIBYTE_HDR_FEATURE(1480, PASS2)
620#define S_BCM1480_MC_DLL_BGCTRL 60
621#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL)
622#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL)
623#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL)
624#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0)
625#endif
626
627#define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63)
628
629/*
630 * Memory Drive Configuration Register (Table 94)
631 */
632
633#define S_BCM1480_MC_RTT_BYP_PULLDOWN 0
634#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN)
635#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN)
636#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN)
637
638#define S_BCM1480_MC_RTT_BYP_PULLUP 6
639#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP)
640#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP)
641#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP)
642
643#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8)
644#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9)
645
646#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10
647#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
648#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
649#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
650
651#define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15
652#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP)
653#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP)
654#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP)
655
656#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20
657#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
658#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
659#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
660
661#define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25
662#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP)
663#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP)
664#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP)
665
666#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30)
667#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31)
668
669#define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34)
670#define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35)
671#define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36)
672
673#define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37)
674#define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38)
675#define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39)
676#define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40)
677#define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41)
678
679/*
680 * ECC Test Data Register (Table 95)
681 */
682
683#define S_BCM1480_MC_DATA_INVERT 0
684#define M_DATA_ECC_INVERT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT)
685
686/*
687 * ECC Test ECC Register (Table 96)
688 */
689
690#define S_BCM1480_MC_ECC_INVERT 0
691#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT)
692
693/*
694 * SDRAM Timing Register (Table 97)
695 */
696
697#define S_BCM1480_MC_tRCD 0
698#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4,S_BCM1480_MC_tRCD)
699#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD)
700#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD)
701#define K_BCM1480_MC_tRCD_DEFAULT 3
702#define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT)
703
704#define S_BCM1480_MC_tCL 4
705#define M_BCM1480_MC_tCL _SB_MAKEMASK(4,S_BCM1480_MC_tCL)
706#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCL)
707#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL)
708#define K_BCM1480_MC_tCL_DEFAULT 2
709#define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT)
710
711#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8)
712
713#define S_BCM1480_MC_tWR 9
714#define M_BCM1480_MC_tWR _SB_MAKEMASK(3,S_BCM1480_MC_tWR)
715#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tWR)
716#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR)
717#define K_BCM1480_MC_tWR_DEFAULT 2
718#define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT)
719
720#define S_BCM1480_MC_tCwD 12
721#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4,S_BCM1480_MC_tCwD)
722#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD)
723#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD)
724#define K_BCM1480_MC_tCwD_DEFAULT 1
725#define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT)
726
727#define S_BCM1480_MC_tRP 16
728#define M_BCM1480_MC_tRP _SB_MAKEMASK(4,S_BCM1480_MC_tRP)
729#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRP)
730#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP)
731#define K_BCM1480_MC_tRP_DEFAULT 4
732#define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT)
733
734#define S_BCM1480_MC_tRRD 20
735#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4,S_BCM1480_MC_tRRD)
736#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD)
737#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD)
738#define K_BCM1480_MC_tRRD_DEFAULT 2
739#define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT)
740
741#define S_BCM1480_MC_tRCw 24
742#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5,S_BCM1480_MC_tRCw)
743#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw)
744#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw)
745#define K_BCM1480_MC_tRCw_DEFAULT 10
746#define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT)
747
748#define S_BCM1480_MC_tRCr 32
749#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5,S_BCM1480_MC_tRCr)
750#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr)
751#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr)
752#define K_BCM1480_MC_tRCr_DEFAULT 9
753#define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT)
754
755#if SIBYTE_HDR_FEATURE(1480, PASS2)
756#define S_BCM1480_MC_tFAW 40
757#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6,S_BCM1480_MC_tFAW)
758#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW)
759#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW)
760#define K_BCM1480_MC_tFAW_DEFAULT 0
761#define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT)
762#endif
763
764#define S_BCM1480_MC_tRFC 48
765#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7,S_BCM1480_MC_tRFC)
766#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC)
767#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC)
768#define K_BCM1480_MC_tRFC_DEFAULT 12
769#define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT)
770
771#define S_BCM1480_MC_tFIFO 56
772#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO)
773#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO)
774#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO)
775#define K_BCM1480_MC_tFIFO_DEFAULT 0
776#define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT)
777
778#define S_BCM1480_MC_tW2R 58
779#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2,S_BCM1480_MC_tW2R)
780#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R)
781#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R)
782#define K_BCM1480_MC_tW2R_DEFAULT 1
783#define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT)
784
785#define S_BCM1480_MC_tR2W 60
786#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2,S_BCM1480_MC_tR2W)
787#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W)
788#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W)
789#define K_BCM1480_MC_tR2W_DEFAULT 0
790#define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT)
791
792#define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62)
793
794#define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \
795 V_BCM1480_MC_tFIFO_DEFAULT | \
796 V_BCM1480_MC_tR2W_DEFAULT | \
797 V_BCM1480_MC_tW2R_DEFAULT | \
798 V_BCM1480_MC_tRFC_DEFAULT | \
799 V_BCM1480_MC_tRCr_DEFAULT | \
800 V_BCM1480_MC_tRCw_DEFAULT | \
801 V_BCM1480_MC_tRRD_DEFAULT | \
802 V_BCM1480_MC_tRP_DEFAULT | \
803 V_BCM1480_MC_tCwD_DEFAULT | \
804 V_BCM1480_MC_tWR_DEFAULT | \
805 M_BCM1480_MC_tCrDh | \
806 V_BCM1480_MC_tCL_DEFAULT | \
807 V_BCM1480_MC_tRCD_DEFAULT)
808
809/*
810 * SDRAM Timing Register 2
811 */
812
813#if SIBYTE_HDR_FEATURE(1480, PASS2)
814
815#define S_BCM1480_MC_tAL 0
816#define M_BCM1480_MC_tAL _SB_MAKEMASK(4,S_BCM1480_MC_tAL)
817#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tAL)
818#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL)
819#define K_BCM1480_MC_tAL_DEFAULT 0
820#define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT)
821
822#define S_BCM1480_MC_tRTP 4
823#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3,S_BCM1480_MC_tRTP)
824#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP)
825#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP)
826#define K_BCM1480_MC_tRTP_DEFAULT 2
827#define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT)
828
829#define S_BCM1480_MC_tW2W 8
830#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2,S_BCM1480_MC_tW2W)
831#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W)
832#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W)
833#define K_BCM1480_MC_tW2W_DEFAULT 0
834#define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT)
835
836#define S_BCM1480_MC_tRAP 12
837#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4,S_BCM1480_MC_tRAP)
838#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP)
839#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP)
840#define K_BCM1480_MC_tRAP_DEFAULT 0
841#define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT)
842
843#endif
844
845
846
847/*
848 * Global Registers: single instances per BCM1480
849 */
850
851/*
852 * Global Configuration Register (Table 99)
853 */
854
855#define S_BCM1480_MC_BLK_SET_MARK 8
856#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK)
857#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK)
858#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK)
859
860#define S_BCM1480_MC_BLK_CLR_MARK 12
861#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK)
862#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK)
863#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK)
864
865#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16)
866
867#define S_BCM1480_MC_MAX_AGE 20
868#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE)
869#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE)
870#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE)
871
872#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29)
873#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30)
874#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32)
875
876#define S_BCM1480_MC_SLEW 33
877#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2,S_BCM1480_MC_SLEW)
878#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW)
879#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW)
880
881#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35)
882
883/*
884 * Global Channel Interleave Register (Table 100)
885 */
886
887#define S_BCM1480_MC_INTLV0 0
888#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0)
889#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0)
890#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0)
891
892#define S_BCM1480_MC_INTLV1 8
893#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1)
894#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1)
895#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1)
896
897#define S_BCM1480_MC_INTLV_MODE 16
898#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE)
899#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE)
900#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE)
901
902#define K_BCM1480_MC_INTLV_MODE_NONE 0x0
903#define K_BCM1480_MC_INTLV_MODE_01 0x1
904#define K_BCM1480_MC_INTLV_MODE_23 0x2
905#define K_BCM1480_MC_INTLV_MODE_01_23 0x3
906#define K_BCM1480_MC_INTLV_MODE_0123 0x4
907
908#define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE)
909#define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01)
910#define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23)
911#define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23)
912#define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123)
913
914/*
915 * ECC Status Register
916 */
917
918#define S_BCM1480_MC_ECC_ERR_ADDR 0
919#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR)
920#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR)
921#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR)
922
923#if SIBYTE_HDR_FEATURE(1480, PASS2)
924#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60)
925#endif
926
927#define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61)
928#define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62)
929#define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63)
930
931/*
932 * Global ECC Address Register (Table 102)
933 */
934
935#define S_BCM1480_MC_ECC_CORR_ADDR 0
936#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR)
937#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR)
938#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR)
939
940/*
941 * Global ECC Correction Register (Table 103)
942 */
943
944#define S_BCM1480_MC_ECC_CORRECT 0
945#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT)
946#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT)
947#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT)
948
949/*
950 * Global ECC Performance Counters Control Register (Table 104)
951 */
952
953#define S_BCM1480_MC_CHANNEL_SELECT 0
954#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT)
955#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT)
956#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT)
957#define K_BCM1480_MC_CHANNEL_SELECT_0 0x1
958#define K_BCM1480_MC_CHANNEL_SELECT_1 0x2
959#define K_BCM1480_MC_CHANNEL_SELECT_2 0x4
960#define K_BCM1480_MC_CHANNEL_SELECT_3 0x8
961
962#endif /* _BCM1480_MC_H */
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h
new file mode 100644
index 000000000000..c2dd2fe3047c
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_regs.h
@@ -0,0 +1,869 @@
1/* *********************************************************************
2 * BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
3 *
4 * Register Definitions File: bcm1480_regs.h
5 *
6 * This module contains the addresses of the on-chip peripherals
7 * on the BCM1280 and BCM1480.
8 *
9 * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
10 *
11 *********************************************************************
12 *
13 * Copyright 2000,2001,2002,2003
14 * Broadcom Corporation. All rights reserved.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 ********************************************************************* */
31
32#ifndef _BCM1480_REGS_H
33#define _BCM1480_REGS_H
34
35#include "sb1250_defs.h"
36
37/* *********************************************************************
38 * Pull in the BCM1250's registers since a great deal of the 1480's
39 * functions are the same as the BCM1250.
40 ********************************************************************* */
41
42#include "sb1250_regs.h"
43
44
45/* *********************************************************************
46 * Some general notes:
47 *
48 * Register addresses are grouped by function and follow the order
49 * of the User Manual.
50 *
51 * For the most part, when there is more than one peripheral
52 * of the same type on the SOC, the constants below will be
53 * offsets from the base of each peripheral. For example,
54 * the MAC registers are described as offsets from the first
55 * MAC register, and there will be a MAC_REGISTER() macro
56 * to calculate the base address of a given MAC.
57 *
58 * The information in this file is based on the BCM1X55/BCM1X80
59 * User Manual, Document 1X55_1X80-UM100-R, 22/12/03.
60 *
61 * This file is basically a "what's new" header file. Since the
62 * BCM1250 and the new BCM1480 (and derivatives) share many common
63 * features, this file contains only what's new or changed from
64 * the 1250. (above, you can see that we include the 1250 symbols
65 * to get the base functionality).
66 *
67 * In software, be sure to use the correct symbols, particularly
68 * for blocks that are different between the two chip families.
69 * All BCM1480-specific symbols have _BCM1480_ in their names,
70 * and all BCM1250-specific and "base" functions that are common in
71 * both chips have no special names (this is for compatibility with
72 * older include files). Therefore, if you're working with the
73 * SCD, which is very different on each chip, A_SCD_xxx implies
74 * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
75 * version.
76 ********************************************************************* */
77
78
79/* *********************************************************************
80 * Memory Controller Registers (Section 6)
81 ********************************************************************* */
82
83#define A_BCM1480_MC_BASE_0 0x0010050000
84#define A_BCM1480_MC_BASE_1 0x0010051000
85#define A_BCM1480_MC_BASE_2 0x0010052000
86#define A_BCM1480_MC_BASE_3 0x0010053000
87#define BCM1480_MC_REGISTER_SPACING 0x1000
88
89#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
90#define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg))
91
92#define R_BCM1480_MC_CONFIG 0x0000000100
93#define R_BCM1480_MC_CS_START 0x0000000120
94#define R_BCM1480_MC_CS_END 0x0000000140
95#define S_BCM1480_MC_CS_STARTEND 24
96
97#define R_BCM1480_MC_CS01_ROW0 0x0000000180
98#define R_BCM1480_MC_CS01_ROW1 0x00000001A0
99#define R_BCM1480_MC_CS23_ROW0 0x0000000200
100#define R_BCM1480_MC_CS23_ROW1 0x0000000220
101#define R_BCM1480_MC_CS01_COL0 0x0000000280
102#define R_BCM1480_MC_CS01_COL1 0x00000002A0
103#define R_BCM1480_MC_CS23_COL0 0x0000000300
104#define R_BCM1480_MC_CS23_COL1 0x0000000320
105
106#define R_BCM1480_MC_CSX_BASE 0x0000000180
107#define R_BCM1480_MC_CSX_ROW0 0x0000000000 /* relative to CSX_BASE */
108#define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */
109#define R_BCM1480_MC_CSX_COL0 0x0000000100 /* relative to CSX_BASE */
110#define R_BCM1480_MC_CSX_COL1 0x0000000120 /* relative to CSX_BASE */
111#define BCM1480_MC_CSX_SPACING 0x0000000080 /* CS23 relative to CS01 */
112
113#define R_BCM1480_MC_CS01_BA 0x0000000380
114#define R_BCM1480_MC_CS23_BA 0x00000003A0
115#define R_BCM1480_MC_DRAMCMD 0x0000000400
116#define R_BCM1480_MC_DRAMMODE 0x0000000420
117#define R_BCM1480_MC_CLOCK_CFG 0x0000000440
118#define R_BCM1480_MC_MCLK_CFG R_BCM1480_MC_CLOCK_CFG
119#define R_BCM1480_MC_TEST_DATA 0x0000000480
120#define R_BCM1480_MC_TEST_ECC 0x00000004A0
121#define R_BCM1480_MC_TIMING1 0x00000004C0
122#define R_BCM1480_MC_TIMING2 0x00000004E0
123#define R_BCM1480_MC_DLL_CFG 0x0000000500
124#define R_BCM1480_MC_DRIVE_CFG 0x0000000520
125
126#if SIBYTE_HDR_FEATURE(1480, PASS2)
127#define R_BCM1480_MC_ODT 0x0000000460
128#define R_BCM1480_MC_ECC_STATUS 0x0000000540
129#endif
130
131/* Global registers (single instance) */
132#define A_BCM1480_MC_GLB_CONFIG 0x0010054100
133#define A_BCM1480_MC_GLB_INTLV 0x0010054120
134#define A_BCM1480_MC_GLB_ECC_STATUS 0x0010054140
135#define A_BCM1480_MC_GLB_ECC_ADDR 0x0010054160
136#define A_BCM1480_MC_GLB_ECC_CORRECT 0x0010054180
137#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL 0x00100541A0
138
139/* *********************************************************************
140 * L2 Cache Control Registers (Section 5)
141 ********************************************************************* */
142
143#define A_BCM1480_L2_BASE 0x0010040000
144
145#define A_BCM1480_L2_READ_TAG 0x0010040018
146#define A_BCM1480_L2_ECC_TAG 0x0010040038
147#define A_BCM1480_L2_MISC0_VALUE 0x0010040058
148#define A_BCM1480_L2_MISC1_VALUE 0x0010040078
149#define A_BCM1480_L2_MISC2_VALUE 0x0010040098
150#define A_BCM1480_L2_MISC_CONFIG 0x0010040040 /* x040 */
151#define A_BCM1480_L2_CACHE_DISABLE 0x0010040060 /* x060 */
152#define A_BCM1480_L2_MAKECACHEDISABLE(x) (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12))
153#define A_BCM1480_L2_WAY_ENABLE_3_0 0x0010040080 /* x080 */
154#define A_BCM1480_L2_WAY_ENABLE_7_4 0x00100400A0 /* x0A0 */
155#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12))
156#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12))
157#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12))
158#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12))
159#define A_BCM1480_L2_WAY_LOCAL_3_0 0x0010040100 /* x100 */
160#define A_BCM1480_L2_WAY_LOCAL_7_4 0x0010040120 /* x120 */
161#define A_BCM1480_L2_WAY_REMOTE_3_0 0x0010040140 /* x140 */
162#define A_BCM1480_L2_WAY_REMOTE_7_4 0x0010040160 /* x160 */
163#define A_BCM1480_L2_WAY_AGENT_3_0 0x00100400C0 /* xxC0 */
164#define A_BCM1480_L2_WAY_AGENT_7_4 0x00100400E0 /* xxE0 */
165#define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8))
166#define A_BCM1480_L2_BANK_BASE 0x00D0300000
167#define A_BCM1480_L2_BANK_ADDRESS(b) (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17))
168#define A_BCM1480_L2_MGMT_TAG_BASE 0x00D0000000
169
170
171/* *********************************************************************
172 * PCI-X Interface Registers (Section 7)
173 ********************************************************************* */
174
175#define A_BCM1480_PCI_BASE 0x0010061400
176
177#define A_BCM1480_PCI_RESET 0x0010061400
178#define A_BCM1480_PCI_DLL 0x0010061500
179
180#define A_BCM1480_PCI_TYPE00_HEADER 0x002E000000
181
182/* *********************************************************************
183 * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6)
184 ********************************************************************* */
185
186/* No register changes with Rev.C BCM1250, but one additional MAC */
187
188#define A_BCM1480_MAC_BASE_2 0x0010066000
189
190#ifndef A_MAC_BASE_2
191#define A_MAC_BASE_2 A_BCM1480_MAC_BASE_2
192#endif
193
194#define A_BCM1480_MAC_BASE_3 0x0010067000
195#define A_MAC_BASE_3 A_BCM1480_MAC_BASE_3
196
197#define R_BCM1480_MAC_DMA_OODPKTLOST 0x00000038
198
199#ifndef R_MAC_DMA_OODPKTLOST
200#define R_MAC_DMA_OODPKTLOST R_BCM1480_MAC_DMA_OODPKTLOST
201#endif
202
203
204/* *********************************************************************
205 * DUART Registers (Section 14)
206 ********************************************************************* */
207
208/* No significant differences from BCM1250, two DUARTs */
209
210/* Conventions, per user manual:
211 * DUART generic, channels A,B,C,D
212 * DUART0 implementing channels A,B
213 * DUART1 inplementing channels C,D
214 */
215
216#define BCM1480_DUART_NUM_PORTS 4
217
218#define A_BCM1480_DUART0 0x0010060000
219#define A_BCM1480_DUART1 0x0010060400
220#define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1)
221
222#define BCM1480_DUART_CHANREG_SPACING 0x100
223#define A_BCM1480_DUART_CHANREG(chan,reg) (A_BCM1480_DUART(chan) \
224 + BCM1480_DUART_CHANREG_SPACING*((chan)&1) \
225 + (reg))
226#define R_BCM1480_DUART_CHANREG(chan,reg) (BCM1480_DUART_CHANREG_SPACING*((chan)&1) + (reg))
227
228#define R_BCM1480_DUART_IMRREG(chan) (R_DUART_IMR_A + ((chan)&1)*DUART_IMRISR_SPACING)
229#define R_BCM1480_DUART_ISRREG(chan) (R_DUART_ISR_A + ((chan)&1)*DUART_IMRISR_SPACING)
230
231#define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan))
232#define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan))
233
234/*
235 * These constants are the absolute addresses.
236 */
237
238#define A_BCM1480_DUART_MODE_REG_1_C 0x0010060400
239#define A_BCM1480_DUART_MODE_REG_2_C 0x0010060410
240#define A_BCM1480_DUART_STATUS_C 0x0010060420
241#define A_BCM1480_DUART_CLK_SEL_C 0x0010060430
242#define A_BCM1480_DUART_FULL_CTL_C 0x0010060440
243#define A_BCM1480_DUART_CMD_C 0x0010060450
244#define A_BCM1480_DUART_RX_HOLD_C 0x0010060460
245#define A_BCM1480_DUART_TX_HOLD_C 0x0010060470
246#define A_BCM1480_DUART_OPCR_C 0x0010060480
247#define A_BCM1480_DUART_AUX_CTRL_C 0x0010060490
248
249#define A_BCM1480_DUART_MODE_REG_1_D 0x0010060500
250#define A_BCM1480_DUART_MODE_REG_2_D 0x0010060510
251#define A_BCM1480_DUART_STATUS_D 0x0010060520
252#define A_BCM1480_DUART_CLK_SEL_D 0x0010060530
253#define A_BCM1480_DUART_FULL_CTL_D 0x0010060540
254#define A_BCM1480_DUART_CMD_D 0x0010060550
255#define A_BCM1480_DUART_RX_HOLD_D 0x0010060560
256#define A_BCM1480_DUART_TX_HOLD_D 0x0010060570
257#define A_BCM1480_DUART_OPCR_D 0x0010060580
258#define A_BCM1480_DUART_AUX_CTRL_D 0x0010060590
259
260#define A_BCM1480_DUART_INPORT_CHNG_CD 0x0010060600
261#define A_BCM1480_DUART_AUX_CTRL_CD 0x0010060610
262#define A_BCM1480_DUART_ISR_C 0x0010060620
263#define A_BCM1480_DUART_IMR_C 0x0010060630
264#define A_BCM1480_DUART_ISR_D 0x0010060640
265#define A_BCM1480_DUART_IMR_D 0x0010060650
266#define A_BCM1480_DUART_OUT_PORT_CD 0x0010060660
267#define A_BCM1480_DUART_OPCR_CD 0x0010060670
268#define A_BCM1480_DUART_IN_PORT_CD 0x0010060680
269#define A_BCM1480_DUART_ISR_CD 0x0010060690
270#define A_BCM1480_DUART_IMR_CD 0x00100606A0
271#define A_BCM1480_DUART_SET_OPR_CD 0x00100606B0
272#define A_BCM1480_DUART_CLEAR_OPR_CD 0x00100606C0
273#define A_BCM1480_DUART_INPORT_CHNG_C 0x00100606D0
274#define A_BCM1480_DUART_INPORT_CHNG_D 0x00100606E0
275
276
277/* *********************************************************************
278 * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16)
279 ********************************************************************* */
280
281#define A_BCM1480_IO_PCMCIA_CFG_B 0x0010061A58
282#define A_BCM1480_IO_PCMCIA_STATUS_B 0x0010061A68
283
284/* *********************************************************************
285 * GPIO Registers (Section 17)
286 ********************************************************************* */
287
288/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */
289
290#define A_BCM1480_GPIO_INT_ADD_TYPE 0x0010061A78
291#define R_BCM1480_GPIO_INT_ADD_TYPE (-8)
292
293#define A_GPIO_INT_ADD_TYPE A_BCM1480_GPIO_INT_ADD_TYPE
294#define R_GPIO_INT_ADD_TYPE R_BCM1480_GPIO_INT_ADD_TYPE
295
296/* *********************************************************************
297 * SMBus Registers (Section 18)
298 ********************************************************************* */
299
300/* No changes from BCM1250 */
301
302/* *********************************************************************
303 * Timer Registers (Sections 4.6)
304 ********************************************************************* */
305
306/* BCM1480 has two additional watchdogs */
307
308/* Watchdog timers */
309
310#define A_BCM1480_SCD_WDOG_2 0x0010022050
311#define A_BCM1480_SCD_WDOG_3 0x0010022150
312
313#define BCM1480_SCD_NUM_WDOGS 4
314
315#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
316#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
317
318#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050
319#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058
320#define A_BCM1480_SCD_WDOG_CFG_2 0x0010022060
321
322#define A_BCM1480_SCD_WDOG_INIT_3 0x0010022150
323#define A_BCM1480_SCD_WDOG_CNT_3 0x0010022158
324#define A_BCM1480_SCD_WDOG_CFG_3 0x0010022160
325
326/* BCM1480 has two additional compare registers */
327
328#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT A_SCD_ZBBUS_CYCLE_COUNT
329#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE 0x0010020C00
330#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0 A_SCD_ZBBUS_CYCLE_CP0
331#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1 A_SCD_ZBBUS_CYCLE_CP1
332#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2 0x0010020C10
333#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3 0x0010020C18
334
335/* *********************************************************************
336 * System Control Registers (Section 4.2)
337 ********************************************************************* */
338
339/* Scratch register in different place */
340
341#define A_BCM1480_SCD_SCRATCH 0x100200A0
342
343/* *********************************************************************
344 * System Address Trap Registers (Section 4.9)
345 ********************************************************************* */
346
347/* No changes from BCM1250 */
348
349/* *********************************************************************
350 * System Interrupt Mapper Registers (Sections 4.3-4.5)
351 ********************************************************************* */
352
353#define A_BCM1480_IMR_CPU0_BASE 0x0010020000
354#define A_BCM1480_IMR_CPU1_BASE 0x0010022000
355#define A_BCM1480_IMR_CPU2_BASE 0x0010024000
356#define A_BCM1480_IMR_CPU3_BASE 0x0010026000
357#define BCM1480_IMR_REGISTER_SPACING 0x2000
358#define BCM1480_IMR_REGISTER_SPACING_SHIFT 13
359
360#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
361#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
362
363/* Most IMR registers are 128 bits, implemented as non-contiguous
364 64-bit registers high (_H) and low (_L) */
365#define BCM1480_IMR_HL_SPACING 0x1000
366
367#define R_BCM1480_IMR_INTERRUPT_DIAG_H 0x0010
368#define R_BCM1480_IMR_LDT_INTERRUPT_H 0x0018
369#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H 0x0020
370#define R_BCM1480_IMR_INTERRUPT_MASK_H 0x0028
371#define R_BCM1480_IMR_INTERRUPT_TRACE_H 0x0038
372#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040
373#define R_BCM1480_IMR_LDT_INTERRUPT_SET 0x0048
374#define R_BCM1480_IMR_MAILBOX_0_CPU 0x00C0
375#define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8
376#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0
377#define R_BCM1480_IMR_MAILBOX_1_CPU 0x00E0
378#define R_BCM1480_IMR_MAILBOX_1_SET_CPU 0x00E8
379#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU 0x00F0
380#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H 0x0100
381#define BCM1480_IMR_INTERRUPT_STATUS_COUNT 8
382#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H 0x0200
383#define BCM1480_IMR_INTERRUPT_MAP_COUNT 64
384
385#define R_BCM1480_IMR_INTERRUPT_DIAG_L 0x1010
386#define R_BCM1480_IMR_LDT_INTERRUPT_L 0x1018
387#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L 0x1020
388#define R_BCM1480_IMR_INTERRUPT_MASK_L 0x1028
389#define R_BCM1480_IMR_INTERRUPT_TRACE_L 0x1038
390#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040
391#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L 0x1100
392#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L 0x1200
393
394#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE 0x0010028000
395#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE 0x0010028100
396#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE 0x0010028200
397#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE 0x0010028300
398#define BCM1480_IMR_ALIAS_MAILBOX_SPACING 0100
399
400#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
401 (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
402#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
403
404#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */
405#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */
406
407/* *********************************************************************
408 * System Performance Counter Registers (Section 4.7)
409 ********************************************************************* */
410
411/* BCM1480 has four more performance counter registers, and two control
412 registers. */
413
414#define A_BCM1480_SCD_PERF_CNT_BASE 0x00100204C0
415
416#define A_BCM1480_SCD_PERF_CNT_CFG0 0x00100204C0
417#define A_BCM1480_SCD_PERF_CNT_CFG_0 A_BCM1480_SCD_PERF_CNT_CFG0
418#define A_BCM1480_SCD_PERF_CNT_CFG1 0x00100204C8
419#define A_BCM1480_SCD_PERF_CNT_CFG_1 A_BCM1480_SCD_PERF_CNT_CFG1
420
421#define A_BCM1480_SCD_PERF_CNT_0 A_SCD_PERF_CNT_0
422#define A_BCM1480_SCD_PERF_CNT_1 A_SCD_PERF_CNT_1
423#define A_BCM1480_SCD_PERF_CNT_2 A_SCD_PERF_CNT_2
424#define A_BCM1480_SCD_PERF_CNT_3 A_SCD_PERF_CNT_3
425
426#define A_BCM1480_SCD_PERF_CNT_4 0x00100204F0
427#define A_BCM1480_SCD_PERF_CNT_5 0x00100204F8
428#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500
429#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508
430
431/* *********************************************************************
432 * System Bus Watcher Registers (Section 4.8)
433 ********************************************************************* */
434
435
436/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
437
438#define A_BCM1480_BUS_ERR_STATUS_DEBUG 0x00100208D8
439
440/* *********************************************************************
441 * System Debug Controller Registers (Section 19)
442 ********************************************************************* */
443
444/* Same as 1250 */
445
446/* *********************************************************************
447 * System Trace Unit Registers (Sections 4.10)
448 ********************************************************************* */
449
450/* Same as 1250 */
451
452/* *********************************************************************
453 * Data Mover DMA Registers (Section 10.7)
454 ********************************************************************* */
455
456/* Same as 1250 */
457
458
459/* *********************************************************************
460 * HyperTransport Interface Registers (Section 8)
461 ********************************************************************* */
462
463#define BCM1480_HT_NUM_PORTS 3
464#define BCM1480_HT_PORT_SPACING 0x800
465#define A_BCM1480_HT_PORT_HEADER(x) (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING))
466
467#define A_BCM1480_HT_PORT0_HEADER 0x00FE000000
468#define A_BCM1480_HT_PORT1_HEADER 0x00FE000800
469#define A_BCM1480_HT_PORT2_HEADER 0x00FE001000
470#define A_BCM1480_HT_TYPE00_HEADER 0x00FE002000
471
472
473/* *********************************************************************
474 * Node Controller Registers (Section 9)
475 ********************************************************************* */
476
477#define A_BCM1480_NC_BASE 0x00DFBD0000
478
479#define A_BCM1480_NC_RLD_FIELD 0x00DFBD0000
480#define A_BCM1480_NC_RLD_TRIGGER 0x00DFBD0020
481#define A_BCM1480_NC_RLD_BAD_ERROR 0x00DFBD0040
482#define A_BCM1480_NC_RLD_COR_ERROR 0x00DFBD0060
483#define A_BCM1480_NC_RLD_ECC_STATUS 0x00DFBD0080
484#define A_BCM1480_NC_RLD_WAY_ENABLE 0x00DFBD00A0
485#define A_BCM1480_NC_RLD_RANDOM_LFSR 0x00DFBD00C0
486
487#define A_BCM1480_NC_INTERRUPT_STATUS 0x00DFBD00E0
488#define A_BCM1480_NC_INTERRUPT_ENABLE 0x00DFBD0100
489#define A_BCM1480_NC_TIMEOUT_COUNTER 0x00DFBD0120
490#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL 0x00DFBD0140
491
492#define A_BCM1480_NC_CREDIT_STATUS_REG0 0x00DFBD0200
493#define A_BCM1480_NC_CREDIT_STATUS_REG1 0x00DFBD0220
494#define A_BCM1480_NC_CREDIT_STATUS_REG2 0x00DFBD0240
495#define A_BCM1480_NC_CREDIT_STATUS_REG3 0x00DFBD0260
496#define A_BCM1480_NC_CREDIT_STATUS_REG4 0x00DFBD0280
497#define A_BCM1480_NC_CREDIT_STATUS_REG5 0x00DFBD02A0
498#define A_BCM1480_NC_CREDIT_STATUS_REG6 0x00DFBD02C0
499#define A_BCM1480_NC_CREDIT_STATUS_REG7 0x00DFBD02E0
500#define A_BCM1480_NC_CREDIT_STATUS_REG8 0x00DFBD0300
501#define A_BCM1480_NC_CREDIT_STATUS_REG9 0x00DFBD0320
502#define A_BCM1480_NC_CREDIT_STATUS_REG10 0x00DFBE0000
503#define A_BCM1480_NC_CREDIT_STATUS_REG11 0x00DFBE0020
504#define A_BCM1480_NC_CREDIT_STATUS_REG12 0x00DFBE0040
505
506#define A_BCM1480_NC_SR_TIMEOUT_COUNTER 0x00DFBE0060
507#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080
508
509
510/* *********************************************************************
511 * H&R Block Configuration Registers (Section 12.4)
512 ********************************************************************* */
513
514#define A_BCM1480_HR_BASE_0 0x00DF820000
515#define A_BCM1480_HR_BASE_1 0x00DF8A0000
516#define A_BCM1480_HR_BASE_2 0x00DF920000
517#define BCM1480_HR_REGISTER_SPACING 0x80000
518
519#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
520#define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg))
521
522#define R_BCM1480_HR_CFG 0x0000000000
523
524#define R_BCM1480_HR_MAPPING 0x0000010010
525
526#define BCM1480_HR_RULE_SPACING 0x0000000010
527#define BCM1480_HR_NUM_RULES 16
528#define BCM1480_HR_OP_OFFSET 0x0000000100
529#define BCM1480_HR_TYPE_OFFSET 0x0000000108
530#define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
531#define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
532
533#define BCM1480_HR_LEAF_SPACING 0x0000000010
534#define BCM1480_HR_NUM_LEAVES 10
535#define BCM1480_HR_LEAF_OFFSET 0x0000000300
536#define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING))
537
538#define R_BCM1480_HR_EX_LEAF0 0x00000003A0
539
540#define BCM1480_HR_PATH_SPACING 0x0000000010
541#define BCM1480_HR_NUM_PATHS 16
542#define BCM1480_HR_PATH_OFFSET 0x0000000600
543#define R_BCM1480_HR_PATH(idx) (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING))
544
545#define R_BCM1480_HR_PATH_DEFAULT 0x0000000700
546
547#define BCM1480_HR_ROUTE_SPACING 8
548#define BCM1480_HR_NUM_ROUTES 512
549#define BCM1480_HR_ROUTE_OFFSET 0x0000001000
550#define R_BCM1480_HR_RT_WORD(idx) (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING))
551
552
553/* checked to here - ehs */
554/* *********************************************************************
555 * Packet Manager DMA Registers (Section 12.5)
556 ********************************************************************* */
557
558#define A_BCM1480_PM_BASE 0x0010056000
559
560#define A_BCM1480_PMI_LCL_0 0x0010058000
561#define A_BCM1480_PMO_LCL_0 0x001005C000
562#define A_BCM1480_PMI_OFFSET_0 (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE)
563#define A_BCM1480_PMO_OFFSET_0 (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE)
564
565#define BCM1480_PM_LCL_REGISTER_SPACING 0x100
566#define BCM1480_PM_NUM_CHANNELS 32
567
568#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
569#define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
570#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
571#define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg))
572
573#define BCM1480_PM_INT_PACKING 8
574#define BCM1480_PM_INT_FUNCTION_SPACING 0x40
575#define BCM1480_PM_INT_NUM_FUNCTIONS 3
576
577/*
578 * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n)
579 */
580
581#define R_BCM1480_PM_BASE_SIZE 0x0000000000
582#define R_BCM1480_PM_CNT 0x0000000008
583#define R_BCM1480_PM_PFCNT 0x0000000010
584#define R_BCM1480_PM_LAST 0x0000000018
585#define R_BCM1480_PM_PFINDX 0x0000000020
586#define R_BCM1480_PM_INT_WMK 0x0000000028
587#define R_BCM1480_PM_CONFIG0 0x0000000030
588#define R_BCM1480_PM_LOCALDEBUG 0x0000000078
589#define R_BCM1480_PM_CACHEABILITY 0x0000000080 /* PMI only */
590#define R_BCM1480_PM_INT_CNFG 0x0000000088
591#define R_BCM1480_PM_DESC_MERGE_TIMER 0x0000000090
592#define R_BCM1480_PM_LOCALDEBUG_PIB 0x00000000F8 /* PMI only */
593#define R_BCM1480_PM_LOCALDEBUG_POB 0x00000000F8 /* PMO only */
594
595/*
596 * Global Registers (Not Channelized)
597 */
598
599#define A_BCM1480_PMI_GLB_0 0x0010056000
600#define A_BCM1480_PMO_GLB_0 0x0010057000
601
602/*
603 * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0
604 */
605
606#define R_BCM1480_PM_PMO_MAPPING 0x00000008C8 /* PMO only */
607
608#define A_BCM1480_PM_PMO_MAPPING (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING)
609
610/*
611 * Interrupt mapping registers
612 */
613
614
615#define A_BCM1480_PMI_INT_0 0x0010056800
616#define A_BCM1480_PMI_INT(q) (A_BCM1480_PMI_INT_0 + ((q>>8)<<8))
617#define A_BCM1480_PMI_INT_OFFSET_0 (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE)
618#define A_BCM1480_PMO_INT_0 0x0010057800
619#define A_BCM1480_PMO_INT(q) (A_BCM1480_PMO_INT_0 + ((q>>8)<<8))
620#define A_BCM1480_PMO_INT_OFFSET_0 (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE)
621
622/*
623 * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0
624 */
625
626#define R_BCM1480_PM_INT_ST 0x0000000000
627#define R_BCM1480_PM_INT_MSK 0x0000000040
628#define R_BCM1480_PM_INT_CLR 0x0000000080
629#define R_BCM1480_PM_MRGD_INT 0x00000000C0
630
631/*
632 * Debug registers (global)
633 */
634
635#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI 0x0010056000
636#define A_BCM1480_PM_GLOBALDEBUG_PID 0x00100567F8
637#define A_BCM1480_PM_GLOBALDEBUG_PIB 0x0010056FF8
638#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO 0x0010057000
639#define A_BCM1480_PM_GLOBALDEBUG_POD 0x00100577F8
640#define A_BCM1480_PM_GLOBALDEBUG_POB 0x0010057FF8
641
642/* *********************************************************************
643 * Switch performance counters
644 ********************************************************************* */
645
646#define A_BCM1480_SWPERF_CFG 0xdfb91800
647#define A_BCM1480_SWPERF_CNT0 0xdfb91880
648#define A_BCM1480_SWPERF_CNT1 0xdfb91888
649#define A_BCM1480_SWPERF_CNT2 0xdfb91890
650#define A_BCM1480_SWPERF_CNT3 0xdfb91898
651
652
653/* *********************************************************************
654 * Switch Trace Unit
655 ********************************************************************* */
656
657#define A_BCM1480_SWTRC_MATCH_CONTROL_0 0xDFB91000
658#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 0xDFB91100
659#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0 0xDFB91108
660#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 0xDFB91200
661#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0 0xDFB91208
662#define A_BCM1480_SWTRC_EVENT_0 0xDFB91300
663#define A_BCM1480_SWTRC_SEQUENCE_0 0xDFB91400
664
665#define A_BCM1480_SWTRC_CFG 0xDFB91500
666#define A_BCM1480_SWTRC_READ 0xDFB91508
667
668#define A_BCM1480_SWDEBUG_SCHEDSTOP 0xDFB92000
669
670#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8))
671#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8))
672#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8))
673
674#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16))
675#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16))
676#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16))
677#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16))
678
679
680
681/* *********************************************************************
682 * High-Speed Port Registers (Section 13)
683 ********************************************************************* */
684
685#define A_BCM1480_HSP_BASE_0 0x00DF810000
686#define A_BCM1480_HSP_BASE_1 0x00DF890000
687#define A_BCM1480_HSP_BASE_2 0x00DF910000
688#define BCM1480_HSP_REGISTER_SPACING 0x80000
689
690#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
691#define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg))
692
693#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000
694#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008
695#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010
696#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018
697#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN 0x0000000020
698#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028
699
700#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0 0x0000000200
701#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1 0x0000000208
702
703#define R_BCM1480_HSP_RX_PLL_CNFG 0x0000000800
704#define R_BCM1480_HSP_RX_CALIBRATION 0x0000000808
705#define R_BCM1480_HSP_RX_TEST 0x0000000810
706#define R_BCM1480_HSP_RX_DIAG_DETAILS 0x0000000818
707#define R_BCM1480_HSP_RX_DIAG_CRC_0 0x0000000820
708#define R_BCM1480_HSP_RX_DIAG_CRC_1 0x0000000828
709#define R_BCM1480_HSP_RX_DIAG_HTCMD 0x0000000830
710#define R_BCM1480_HSP_RX_DIAG_PKTCTL 0x0000000838
711
712#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER 0x0000000870
713
714#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0 0x0000020020
715#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1 0x0000020028
716#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2 0x0000020030
717#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3 0x0000020038
718#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4 0x0000020040
719#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5 0x0000020048
720#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6 0x0000020050
721#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7 0x0000020058
722#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx))
723
724/* XXX Following registers were shuffled. Renamed/renumbered per errata. */
725#define R_BCM1480_HSP_RX_HT_RAMALLOC_0 0x0000020078
726#define R_BCM1480_HSP_RX_HT_RAMALLOC_1 0x0000020080
727#define R_BCM1480_HSP_RX_HT_RAMALLOC_2 0x0000020088
728#define R_BCM1480_HSP_RX_HT_RAMALLOC_3 0x0000020090
729#define R_BCM1480_HSP_RX_HT_RAMALLOC_4 0x0000020098
730#define R_BCM1480_HSP_RX_HT_RAMALLOC_5 0x00000200A0
731
732#define R_BCM1480_HSP_RX_SPI_WATERMARK_0 0x00000200B0
733#define R_BCM1480_HSP_RX_SPI_WATERMARK_1 0x00000200B8
734#define R_BCM1480_HSP_RX_SPI_WATERMARK_2 0x00000200C0
735#define R_BCM1480_HSP_RX_SPI_WATERMARK_3 0x00000200C8
736#define R_BCM1480_HSP_RX_SPI_WATERMARK_4 0x00000200D0
737#define R_BCM1480_HSP_RX_SPI_WATERMARK_5 0x00000200D8
738#define R_BCM1480_HSP_RX_SPI_WATERMARK_6 0x00000200E0
739#define R_BCM1480_HSP_RX_SPI_WATERMARK_7 0x00000200E8
740#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx) (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx))
741
742#define R_BCM1480_HSP_RX_VIS_CMDQ_0 0x00000200F0
743#define R_BCM1480_HSP_RX_VIS_CMDQ_1 0x00000200F8
744#define R_BCM1480_HSP_RX_VIS_CMDQ_2 0x0000020100
745#define R_BCM1480_HSP_RX_RAM_READCTL 0x0000020108
746#define R_BCM1480_HSP_RX_RAM_READWINDOW 0x0000020110
747#define R_BCM1480_HSP_RX_RF_READCTL 0x0000020118
748#define R_BCM1480_HSP_RX_RF_READWINDOW 0x0000020120
749
750#define R_BCM1480_HSP_TX_SPI4_CFG_0 0x0000040000
751#define R_BCM1480_HSP_TX_SPI4_CFG_1 0x0000040008
752#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT 0x0000040010
753
754#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0 0x0000040020
755#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1 0x0000040028
756#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2 0x0000040030
757#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3 0x0000040038
758#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4 0x0000040040
759#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5 0x0000040048
760#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6 0x0000040050
761#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7 0x0000040058
762#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx))
763#define R_BCM1480_HSP_TX_NPC_RAMALLOC 0x0000040078
764#define R_BCM1480_HSP_TX_RSP_RAMALLOC 0x0000040080
765#define R_BCM1480_HSP_TX_PC_RAMALLOC 0x0000040088
766#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0 0x0000040090
767#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1 0x0000040098
768#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2 0x00000400A0
769
770#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 0x00000400B0
771#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1 0x00000400B8
772#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2 0x00000400C0
773#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3 0x00000400C8
774#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx))
775#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT 0x00000400D0
776#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT 0x00000400D8
777
778#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 0x00000400E0
779#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1 0x00000400E8
780#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2 0x00000400F0
781#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3 0x00000400F8
782#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx))
783#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT 0x0000040100
784#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT 0x0000040108
785
786#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0 0x0000040200
787#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1 0x0000040208
788
789#define R_BCM1480_HSP_TX_PLL_CNFG 0x0000040800
790#define R_BCM1480_HSP_TX_CALIBRATION 0x0000040808
791#define R_BCM1480_HSP_TX_TEST 0x0000040810
792
793#define R_BCM1480_HSP_TX_VIS_CMDQ_0 0x0000040840
794#define R_BCM1480_HSP_TX_VIS_CMDQ_1 0x0000040848
795#define R_BCM1480_HSP_TX_VIS_CMDQ_2 0x0000040850
796#define R_BCM1480_HSP_TX_RAM_READCTL 0x0000040860
797#define R_BCM1480_HSP_TX_RAM_READWINDOW 0x0000040868
798#define R_BCM1480_HSP_TX_RF_READCTL 0x0000040870
799#define R_BCM1480_HSP_TX_RF_READWINDOW 0x0000040878
800
801#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880
802#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN 0x0000040888
803
804#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400
805#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x))
806
807
808
809/* *********************************************************************
810 * Physical Address Map (Table 10 and Figure 7)
811 ********************************************************************* */
812
813#define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000)
814#define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024))
815#define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000)
816#define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000)
817#define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000)
818#define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000)
819#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000)
820#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000)
821#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000)
822#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000)
823#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000)
824#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000)
825#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000)
826#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000)
827#define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000)
828#define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000)
829#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000)
830#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000)
831#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000)
832#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000)
833#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000)
834#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000)
835#define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000)
836#define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000)
837#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000)
838#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000)
839#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000)
840#define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000)
841#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000)
842#define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000)
843#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000)
844#define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000)
845#define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024))
846#define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000)
847#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000)
848#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000)
849#define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000)
850#define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000)
851
852
853/* *********************************************************************
854 * L2 Cache as RAM (Table 54)
855 ********************************************************************* */
856
857#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000)
858#define BCM1480_PHYS_L2CACHE_NUM_WAYS 8
859#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000)
860#define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000)
861#define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000)
862#define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000)
863#define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000)
864#define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000)
865#define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000)
866#define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000)
867#define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000)
868
869#endif /* _BCM1480_REGS_H */
diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h
new file mode 100644
index 000000000000..648bed96780f
--- /dev/null
+++ b/include/asm-mips/sibyte/bcm1480_scd.h
@@ -0,0 +1,436 @@
1/* *********************************************************************
2 * BCM1280/BCM1400 Board Support Package
3 *
4 * SCD Constants and Macros File: bcm1480_scd.h
5 *
6 * This module contains constants and macros useful for
7 * manipulating the System Control and Debug module.
8 *
9 * BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03)
10 *
11 *********************************************************************
12 *
13 * Copyright 2000,2001,2002,2003
14 * Broadcom Corporation. All rights reserved.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 ********************************************************************* */
31
32#ifndef _BCM1480_SCD_H
33#define _BCM1480_SCD_H
34
35#include "sb1250_defs.h"
36
37/* *********************************************************************
38 * Pull in the BCM1250's SCD since lots of stuff is the same.
39 ********************************************************************* */
40
41#include "sb1250_scd.h"
42
43/* *********************************************************************
44 * Some general notes:
45 *
46 * This file is basically a "what's new" header file. Since the
47 * BCM1250 and the new BCM1480 (and derivatives) share many common
48 * features, this file contains only what's new or changed from
49 * the 1250. (above, you can see that we include the 1250 symbols
50 * to get the base functionality).
51 *
52 * In software, be sure to use the correct symbols, particularly
53 * for blocks that are different between the two chip families.
54 * All BCM1480-specific symbols have _BCM1480_ in their names,
55 * and all BCM1250-specific and "base" functions that are common in
56 * both chips have no special names (this is for compatibility with
57 * older include files). Therefore, if you're working with the
58 * SCD, which is very different on each chip, A_SCD_xxx implies
59 * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
60 * version.
61 ********************************************************************* */
62
63/* *********************************************************************
64 * System control/debug registers
65 ********************************************************************* */
66
67/*
68 * System Identification and Revision Register (Table 12)
69 * Register: SCD_SYSTEM_REVISION
70 * This register is field compatible with the 1250.
71 */
72
73/*
74 * New part definitions
75 */
76
77#define K_SYS_PART_BCM1480 0x1406
78#define K_SYS_PART_BCM1280 0x1206
79#define K_SYS_PART_BCM1455 0x1407
80#define K_SYS_PART_BCM1255 0x1257
81
82/*
83 * Manufacturing Information Register (Table 14)
84 * Register: SCD_SYSTEM_MANUF
85 */
86
87/*
88 * System Configuration Register (Table 15)
89 * Register: SCD_SYSTEM_CFG
90 * Entire register is different from 1250, all new constants below
91 */
92
93#define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0)
94#define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1)
95#define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2)
96#define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3)
97#define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4)
98#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5)
99
100#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6)
101#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV)
102#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV)
103#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV)
104
105#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11)
106#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV)
107#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV)
108#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV)
109
110#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
111#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17)
112
113#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18)
114#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE)
115#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE)
116#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE)
117#define K_BCM1480_SYS_BOOT_MODE_ROM32 0
118#define K_BCM1480_SYS_BOOT_MODE_ROM8 1
119#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
120#define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3
121#define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19)
122
123#define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20)
124#define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21)
125#define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
126#define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23)
127#define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24)
128#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25)
129
130#define S_BCM1480_SYS_CONFIG 26
131#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG)
132#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG)
133#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG)
134
135#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32,15)
136
137#define S_BCM1480_SYS_NODEID 47
138#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID)
139#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID)
140#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID)
141
142#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51)
143#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52)
144#define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53)
145#define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54)
146#define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55)
147#define S_BCM1480_SYS_DISABLECPU0 56
148#define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
149#define S_BCM1480_SYS_DISABLECPU1 57
150#define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
151#define S_BCM1480_SYS_DISABLECPU2 58
152#define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
153#define S_BCM1480_SYS_DISABLECPU3 59
154#define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
155
156#define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60)
157#define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61)
158#define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62)
159#define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63)
160
161/*
162 * Scratch Register (Table 16)
163 * Register: SCD_SYSTEM_SCRATCH
164 * Same as BCM1250
165 */
166
167
168/*
169 * Mailbox Registers (Table 17)
170 * Registers: SCD_MBOX_{0,1}_CPU_x
171 * Same as BCM1250
172 */
173
174
175/*
176 * See bcm1480_int.h for interrupt mapper registers.
177 */
178
179
180/*
181 * Watchdog Timer Initial Count Registers (Table 23)
182 * Registers: SCD_WDOG_INIT_CNT_x
183 *
184 * The watchdogs are almost the same as the 1250, except
185 * the configuration register has more bits to control the
186 * other CPUs.
187 */
188
189
190/*
191 * Watchdog Timer Configuration Registers (Table 25)
192 * Registers: SCD_WDOG_CFG_x
193 */
194
195#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0)
196
197#define S_BCM1480_SCD_WDOG_RESET_TYPE 2
198#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE)
199#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE)
200#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE)
201
202#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */
203#define K_BCM1480_SCD_WDOG_RESET_SOFT 1
204#define K_BCM1480_SCD_WDOG_RESET_CPU0 3
205#define K_BCM1480_SCD_WDOG_RESET_CPU1 5
206#define K_BCM1480_SCD_WDOG_RESET_CPU2 9
207#define K_BCM1480_SCD_WDOG_RESET_CPU3 17
208#define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31
209
210
211#define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8)
212
213/*
214 * General Timer Initial Count Registers (Table 26)
215 * Registers: SCD_TIMER_INIT_x
216 *
217 * The timer registers are the same as the BCM1250
218 */
219
220
221/*
222 * ZBbus Count Register (Table 29)
223 * Register: ZBBUS_CYCLE_COUNT
224 *
225 * Same as BCM1250
226 */
227
228/*
229 * ZBbus Compare Registers (Table 30)
230 * Registers: ZBBUS_CYCLE_CPx
231 *
232 * Same as BCM1250
233 */
234
235
236/*
237 * System Performance Counter Configuration Register (Table 31)
238 * Register: PERF_CNT_CFG_0
239 *
240 * Since the clear/enable bits are moved compared to the
241 * 1250 and there are more fields, this register will be BCM1480 specific.
242 */
243
244#define S_BCM1480_SPC_CFG_SRC0 0
245#define M_BCM1480_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC0)
246#define V_BCM1480_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC0)
247#define G_BCM1480_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC0,M_BCM1480_SPC_CFG_SRC0)
248
249#define S_BCM1480_SPC_CFG_SRC1 8
250#define M_BCM1480_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC1)
251#define V_BCM1480_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC1)
252#define G_BCM1480_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC1,M_BCM1480_SPC_CFG_SRC1)
253
254#define S_BCM1480_SPC_CFG_SRC2 16
255#define M_BCM1480_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC2)
256#define V_BCM1480_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC2)
257#define G_BCM1480_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC2,M_BCM1480_SPC_CFG_SRC2)
258
259#define S_BCM1480_SPC_CFG_SRC3 24
260#define M_BCM1480_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC3)
261#define V_BCM1480_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC3)
262#define G_BCM1480_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC3,M_BCM1480_SPC_CFG_SRC3)
263
264#define S_BCM1480_SPC_CFG_SRC4 32
265#define M_BCM1480_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC4)
266#define V_BCM1480_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC4)
267#define G_BCM1480_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC4,M_BCM1480_SPC_CFG_SRC4)
268
269#define S_BCM1480_SPC_CFG_SRC5 40
270#define M_BCM1480_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC5)
271#define V_BCM1480_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC5)
272#define G_BCM1480_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC5,M_BCM1480_SPC_CFG_SRC5)
273
274#define S_BCM1480_SPC_CFG_SRC6 48
275#define M_BCM1480_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC6)
276#define V_BCM1480_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC6)
277#define G_BCM1480_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC6,M_BCM1480_SPC_CFG_SRC6)
278
279#define S_BCM1480_SPC_CFG_SRC7 56
280#define M_BCM1480_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC7)
281#define V_BCM1480_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC7)
282#define G_BCM1480_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC7,M_BCM1480_SPC_CFG_SRC7)
283
284/*
285 * System Performance Counter Control Register (Table 32)
286 * Register: PERF_CNT_CFG_1
287 * BCM1480 specific
288 */
289
290#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0)
291#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1)
292
293/*
294 * System Performance Counters (Table 33)
295 * Registers: PERF_CNT_x
296 */
297
298#define S_BCM1480_SPC_CNT_COUNT 0
299#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT)
300#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT)
301#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT)
302
303#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40)
304
305
306/*
307 * Bus Watcher Error Status Register (Tables 36, 37)
308 * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG
309 * Same as BCM1250.
310 */
311
312/*
313 * Bus Watcher Error Data Registers (Table 38)
314 * Registers: BUS_ERR_DATA_x
315 * Same as BCM1250.
316 */
317
318/*
319 * Bus Watcher L2 ECC Counter Register (Table 39)
320 * Register: BUS_L2_ERRORS
321 * Same as BCM1250.
322 */
323
324
325/*
326 * Bus Watcher Memory and I/O Error Counter Register (Table 40)
327 * Register: BUS_MEM_IO_ERRORS
328 * Same as BCM1250.
329 */
330
331
332/*
333 * Address Trap Registers
334 *
335 * Register layout same as BCM1250, almost. The bus agents
336 * are different, and the address trap configuration bits are
337 * slightly different.
338 */
339
340#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4,0)
341#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40,0)
342
343#define S_BCM1480_ATRAP_CFG_CNT 0
344#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT)
345#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT)
346#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT)
347
348#define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
349#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
350#define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5)
351#define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
352#define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
353
354#define S_BCM1480_ATRAP_CFG_AGENTID 8
355#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID)
356#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID)
357#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID)
358
359
360#define K_BCM1480_BUS_AGENT_CPU0 0
361#define K_BCM1480_BUS_AGENT_CPU1 1
362#define K_BCM1480_BUS_AGENT_NC 2
363#define K_BCM1480_BUS_AGENT_IOB 3
364#define K_BCM1480_BUS_AGENT_SCD 4
365#define K_BCM1480_BUS_AGENT_L2C 6
366#define K_BCM1480_BUS_AGENT_MC 7
367#define K_BCM1480_BUS_AGENT_CPU2 8
368#define K_BCM1480_BUS_AGENT_CPU3 9
369#define K_BCM1480_BUS_AGENT_PM 10
370
371#define S_BCM1480_ATRAP_CFG_CATTR 12
372#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR)
373#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR)
374#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR)
375
376#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0
377#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1
378#define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2
379#define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3
380
381#define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14)
382
383
384/*
385 * Trace Event Registers (Table 47)
386 * Same as BCM1250.
387 */
388
389/*
390 * Trace Sequence Control Registers (Table 48)
391 * Registers: TRACE_SEQUENCE_x
392 *
393 * Same as BCM1250 except for two new fields.
394 */
395
396
397#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25)
398
399#define S_BCM1480_SCD_TRSEQ_SWFUNC 26
400#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC)
401#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC)
402#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC)
403
404/*
405 * Trace Control Register (Table 49)
406 * Register: TRACE_CFG
407 *
408 * Bits 0..8 are the same as the BCM1250, rest are different.
409 * Entire register is redefined below.
410 */
411
412#define M_BCM1480_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
413#define M_BCM1480_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
414#define M_BCM1480_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
415#define M_BCM1480_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
416#define M_BCM1480_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
417#define M_BCM1480_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
418#define M_BCM1480_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
419#define M_BCM1480_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
420#define M_BCM1480_SCD_TRACE_CFG_FORCE_CNT _SB_MAKEMASK1(8)
421
422#define S_BCM1480_SCD_TRACE_CFG_MODE 16
423#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE)
424#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE)
425#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE)
426
427#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0
428#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
429#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2
430
431#define S_BCM1480_SCD_TRACE_CFG_CUR_ADDR 24
432#define M_BCM1480_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
433#define V_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
434#define G_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR,M_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
435
436#endif /* _BCM1480_SCD_H */
diff --git a/include/asm-mips/sibyte/bigsur.h b/include/asm-mips/sibyte/bigsur.h
new file mode 100644
index 000000000000..ebefe797fc1d
--- /dev/null
+++ b/include/asm-mips/sibyte/bigsur.h
@@ -0,0 +1,49 @@
1/*
2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#ifndef __ASM_SIBYTE_BIGSUR_H
19#define __ASM_SIBYTE_BIGSUR_H
20
21#include <asm/sibyte/sb1250.h>
22#include <asm/sibyte/bcm1480_int.h>
23
24#ifdef CONFIG_SIBYTE_BIGSUR
25#define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)"
26#define SIBYTE_HAVE_PCMCIA 1
27#define SIBYTE_HAVE_IDE 1
28#endif
29
30/* Generic bus chip selects */
31#define LEDS_CS 3
32#define LEDS_PHYS 0x100a0000
33
34#ifdef SIBYTE_HAVE_IDE
35#define IDE_CS 4
36#define IDE_PHYS 0x100b0000
37#define K_GPIO_GB_IDE 4
38#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE)
39#endif
40
41#ifdef SIBYTE_HAVE_PCMCIA
42#define PCMCIA_CS 6
43#define PCMCIA_PHYS 0x11000000
44#define K_GPIO_PC_READY 9
45#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY)
46#endif
47
48#endif /* __ASM_SIBYTE_BIGSUR_H */
49
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
index d7b11b6c7c32..900edcbeec37 100644
--- a/include/asm-mips/sibyte/board.h
+++ b/include/asm-mips/sibyte/board.h
@@ -21,8 +21,6 @@
21 21
22#include <linux/config.h> 22#include <linux/config.h>
23 23
24#ifdef CONFIG_SIBYTE_BOARD
25
26#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \ 24#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \
27 defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \ 25 defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \
28 defined(CONFIG_SIBYTE_LITTLESUR) 26 defined(CONFIG_SIBYTE_LITTLESUR)
@@ -37,6 +35,10 @@
37#include <asm/sibyte/carmel.h> 35#include <asm/sibyte/carmel.h>
38#endif 36#endif
39 37
38#ifdef CONFIG_SIBYTE_BIGSUR
39#include <asm/sibyte/bigsur.h>
40#endif
41
40#ifdef __ASSEMBLY__ 42#ifdef __ASSEMBLY__
41 43
42#ifdef LEDS_PHYS 44#ifdef LEDS_PHYS
@@ -54,16 +56,6 @@
54#define setleds(t0,t1,c0,c1,c2,c3) 56#define setleds(t0,t1,c0,c1,c2,c3)
55#endif /* LEDS_PHYS */ 57#endif /* LEDS_PHYS */
56 58
57#else
58
59#ifdef LEDS_PHYS
60extern void setleds(char *str);
61#else
62#define setleds(s) do { } while (0)
63#endif /* LEDS_PHYS */
64
65#endif /* __ASSEMBLY__ */ 59#endif /* __ASSEMBLY__ */
66 60
67#endif /* CONFIG_SIBYTE_BOARD */
68
69#endif /* _SIBYTE_BOARD_H */ 61#endif /* _SIBYTE_BOARD_H */
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h
index d62da4e2dd36..a474c29cd701 100644
--- a/include/asm-mips/sibyte/sb1250.h
+++ b/include/asm-mips/sibyte/sb1250.h
@@ -27,6 +27,9 @@
27 27
28#define SB1250_NR_IRQS 64 28#define SB1250_NR_IRQS 64
29 29
30#define BCM1480_NR_IRQS 128
31#define BCM1480_NR_IRQS_HALF 64
32
30#define SB1250_DUART_MINOR_BASE 64 33#define SB1250_DUART_MINOR_BASE 64
31 34
32#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
@@ -35,6 +38,7 @@
35 38
36/* For revision/pass information */ 39/* For revision/pass information */
37#include <asm/sibyte/sb1250_scd.h> 40#include <asm/sibyte/sb1250_scd.h>
41#include <asm/sibyte/bcm1480_scd.h>
38extern unsigned int sb1_pass; 42extern unsigned int sb1_pass;
39extern unsigned int soc_pass; 43extern unsigned int soc_pass;
40extern unsigned int soc_type; 44extern unsigned int soc_type;
@@ -46,6 +50,13 @@ extern unsigned long sb1250_gettimeoffset(void);
46extern void sb1250_mask_irq(int cpu, int irq); 50extern void sb1250_mask_irq(int cpu, int irq);
47extern void sb1250_unmask_irq(int cpu, int irq); 51extern void sb1250_unmask_irq(int cpu, int irq);
48extern void sb1250_smp_finish(void); 52extern void sb1250_smp_finish(void);
53
54extern void bcm1480_time_init(void);
55extern unsigned long bcm1480_gettimeoffset(void);
56extern void bcm1480_mask_irq(int cpu, int irq);
57extern void bcm1480_unmask_irq(int cpu, int irq);
58extern void bcm1480_smp_finish(void);
59
49extern void prom_printf(char *fmt, ...); 60extern void prom_printf(char *fmt, ...);
50 61
51#define AT_spin \ 62#define AT_spin \
@@ -58,6 +69,6 @@ extern void prom_printf(char *fmt, ...);
58 69
59#endif 70#endif
60 71
61#define IOADDR(a) (IO_BASE + (a)) 72#define IOADDR(a) ((volatile void __iomem *)(IO_BASE + (a)))
62 73
63#endif 74#endif
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
index 40ef97c76c8b..335dbaf1d831 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -8,8 +8,6 @@
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg
12 *
13 ********************************************************************* 11 *********************************************************************
14 * 12 *
15 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003
@@ -97,13 +95,17 @@
97 * ordering, so be careful when adding support for new minor revs. 95 * ordering, so be careful when adding support for new minor revs.
98 ********************************************************************* */ 96 ********************************************************************* */
99 97
100#define SIBYTE_HDR_FMASK_1250_ALL 0x00000ff 98#define SIBYTE_HDR_FMASK_1250_ALL 0x000000ff
101#define SIBYTE_HDR_FMASK_1250_PASS1 0x0000001 99#define SIBYTE_HDR_FMASK_1250_PASS1 0x00000001
102#define SIBYTE_HDR_FMASK_1250_PASS2 0x0000002 100#define SIBYTE_HDR_FMASK_1250_PASS2 0x00000002
103#define SIBYTE_HDR_FMASK_1250_PASS3 0x0000004 101#define SIBYTE_HDR_FMASK_1250_PASS3 0x00000004
102
103#define SIBYTE_HDR_FMASK_112x_ALL 0x00000f00
104#define SIBYTE_HDR_FMASK_112x_PASS1 0x00000100
104 105
105#define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00 106#define SIBYTE_HDR_FMASK_1480_ALL 0x0000f000
106#define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100 107#define SIBYTE_HDR_FMASK_1480_PASS1 0x00001000
108#define SIBYTE_HDR_FMASK_1480_PASS2 0x00002000
107 109
108/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ 110/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */
109#define SIBYTE_HDR_FMASK(chip, pass) \ 111#define SIBYTE_HDR_FMASK(chip, pass) \
@@ -111,8 +113,17 @@
111#define SIBYTE_HDR_FMASK_ALLREVS(chip) \ 113#define SIBYTE_HDR_FMASK_ALLREVS(chip) \
112 (SIBYTE_HDR_FMASK_ ## chip ## _ALL) 114 (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
113 115
116/* Default constant value for all chips, all revisions */
114#define SIBYTE_HDR_FMASK_ALL \ 117#define SIBYTE_HDR_FMASK_ALL \
118 (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL \
119 | SIBYTE_HDR_FMASK_1480_ALL)
120
121/* This one is used for the "original" BCM1250/BCM112x chips. We use this
122 to weed out constants and macros that do not exist on later chips like
123 the BCM1480 */
124#define SIBYTE_HDR_FMASK_1250_112x_ALL \
115 (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL) 125 (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
126#define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL
116 127
117#ifndef SIBYTE_HDR_FEATURES 128#ifndef SIBYTE_HDR_FEATURES
118#define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL 129#define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL
@@ -133,6 +144,12 @@
133#define SIBYTE_HDR_FEATURE_CHIP(chip) \ 144#define SIBYTE_HDR_FEATURE_CHIP(chip) \
134 (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES)) 145 (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
135 146
147/* True for all versions of the BCM1250 and BCM1125, but not true for
148 anything else */
149#define SIBYTE_HDR_FEATURE_1250_112x \
150 (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
151/* (!! (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */
152
136/* True if header features enabled for that rev or later, inclusive. */ 153/* True if header features enabled for that rev or later, inclusive. */
137#define SIBYTE_HDR_FEATURE(chip, pass) \ 154#define SIBYTE_HDR_FEATURE(chip, pass) \
138 (!! ((SIBYTE_HDR_FMASK(chip, pass) \ 155 (!! ((SIBYTE_HDR_FMASK(chip, pass) \
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
index 3cdb48f50ed0..e6145f524fbd 100644
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -7,9 +7,8 @@
7 * programming the SB1250's DMA controllers, both the data mover 7 * programming the SB1250's DMA controllers, both the data mover
8 * and the Ethernet DMA. 8 * and the Ethernet DMA.
9 * 9 *
10 * SB1250 specification level: User's manual 1/02/02 10 * SB1250 specification level: User's manual 10/21/02
11 * 11 * BCM1280 specification level: User's manual 11/24/03
12 * Author: Mitch Lichtenberg
13 * 12 *
14 ********************************************************************* 13 *********************************************************************
15 * 14 *
@@ -58,17 +57,17 @@
58#define M_DMA_RESERVED1 _SB_MAKEMASK1(2) 57#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
59 58
60#define S_DMA_DESC_TYPE _SB_MAKE64(1) 59#define S_DMA_DESC_TYPE _SB_MAKE64(1)
61#define M_DMA_DESC_TYPE _SB_MAKE64(2,S_DMA_DESC_TYPE) 60#define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE)
62#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) 61#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE)
63#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) 62#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE)
64 63
65#define K_DMA_DESC_TYPE_RING_AL 0 64#define K_DMA_DESC_TYPE_RING_AL 0
66#define K_DMA_DESC_TYPE_CHAIN_AL 1 65#define K_DMA_DESC_TYPE_CHAIN_AL 1
67 66
68#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 67#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
69#define K_DMA_DESC_TYPE_RING_UAL_WI 2 68#define K_DMA_DESC_TYPE_RING_UAL_WI 2
70#define K_DMA_DESC_TYPE_RING_UAL_RMW 3 69#define K_DMA_DESC_TYPE_RING_UAL_RMW 3
71#endif /* 1250 PASS3 || 112x PASS1 */ 70#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
72 71
73#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) 72#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
74#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) 73#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
@@ -111,11 +110,11 @@
111#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) 110#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
112#define M_DMA_L2CA _SB_MAKEMASK1(5) 111#define M_DMA_L2CA _SB_MAKEMASK1(5)
113 112
114#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 113#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
115#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6) 114#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6)
116#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6) 115#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6)
117#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) 116#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)
118#endif /* 1250 PASS3 || 112x PASS1 */ 117#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
119 118
120#define M_DMA_MBZ1 _SB_MAKEMASK(6,15) 119#define M_DMA_MBZ1 _SB_MAKEMASK(6,15)
121 120
@@ -165,14 +164,14 @@
165#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) 164#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
166#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) 165#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
167 166
168#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 167#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
169#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) 168#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)
170#endif /* 1250 PASS3 || 112x PASS1 */ 169#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
171 170
172/* 171/*
173 * Receive Packet Drop Registers 172 * Receive Packet Drop Registers
174 */ 173 */
175#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 174#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
176#define S_DMA_OODLOST_RX _SB_MAKE64(0) 175#define S_DMA_OODLOST_RX _SB_MAKE64(0)
177#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) 176#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
178#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) 177#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
@@ -180,7 +179,7 @@
180#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) 179#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
181#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) 180#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
182#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) 181#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
183#endif /* 1250 PASS3 || 112x PASS1 */ 182#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
184 183
185/* ********************************************************************* 184/* *********************************************************************
186 * DMA Descriptors 185 * DMA Descriptors
@@ -201,21 +200,21 @@
201 200
202#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) 201#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
203 202
204#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 203#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
205#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) 204#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
206#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) 205#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
207#endif /* 1250 PASS3 || 112x PASS1 */ 206#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
208 207
209#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) 208#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
210#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) 209#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
211#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) 210#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
212#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) 211#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
213 212
214#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 213#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
215#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) 214#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
216#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) 215#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
217#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) 216#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
218#endif /* 1250 PASS3 || 112x PASS1 */ 217#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
219 218
220#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) 219#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
221#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) 220#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
@@ -235,12 +234,12 @@
235#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) 234#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
236#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) 235#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
237 236
238#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 237#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
239#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) 238#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
240#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) 239#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
241#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) 240#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
242#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) 241#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
243#endif /* 1250 PASS3 || 112x PASS1 */ 242#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
244 243
245#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) 244#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
246 245
@@ -255,12 +254,12 @@
255 254
256#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) 255#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
257 256
258#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 257#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
259#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) 258#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
260#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) 259#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
261#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) 260#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
262#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) 261#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
263#endif /* 1250 PASS3 || 112x PASS1 */ 262#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
264 263
265#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) 264#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
266#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) 265#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
@@ -282,15 +281,16 @@
282#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) 281#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
283#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) 282#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
284 283
285#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 284#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
286/* Note: BADTCPCS is actually in DSCR_B options field */ 285/* Note: This bit is in the DSCR_B options field */
287#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) 286#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)
288#endif /* 1250 PASS2 || 112x PASS1 */ 287#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
289 288
290#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 289#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
290/* Note: These bits are in the DSCR_B options field */
291#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1) 291#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1)
292#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) 292#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2)
293#endif /* 1250 PASS3 || 112x PASS1 */ 293#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
294 294
295#define S_DMA_ETHRX_RXCH 53 295#define S_DMA_ETHRX_RXCH 53
296#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) 296#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
@@ -438,7 +438,7 @@
438 M_DM_CUR_DSCR_DSCR_COUNT) 438 M_DM_CUR_DSCR_DSCR_COUNT)
439 439
440 440
441#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 441#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
442/* 442/*
443 * Data Mover Channel Partial Result Registers 443 * Data Mover Channel Partial Result Registers
444 * Register: DM_PARTIAL_0 444 * Register: DM_PARTIAL_0
@@ -459,10 +459,10 @@
459 M_DM_PARTIAL_TCPCS_PARTIAL) 459 M_DM_PARTIAL_TCPCS_PARTIAL)
460 460
461#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) 461#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48)
462#endif /* 1250 PASS3 || 112x PASS1 */ 462#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
463 463
464 464
465#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 465#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
466/* 466/*
467 * Data Mover CRC Definition Registers 467 * Data Mover CRC Definition Registers
468 * Register: CRC_DEF_0 468 * Register: CRC_DEF_0
@@ -479,10 +479,10 @@
479#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) 479#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
480#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ 480#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
481 M_CRC_DEF_CRC_POLY) 481 M_CRC_DEF_CRC_POLY)
482#endif /* 1250 PASS3 || 112x PASS1 */ 482#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
483 483
484 484
485#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 485#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
486/* 486/*
487 * Data Mover CRC/Checksum Definition Registers 487 * Data Mover CRC/Checksum Definition Registers
488 * Register: CTCP_DEF_0 488 * Register: CTCP_DEF_0
@@ -511,7 +511,7 @@
511#define K_CTCP_DEF_CRC_WIDTH_1 2 511#define K_CTCP_DEF_CRC_WIDTH_1 2
512 512
513#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) 513#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50)
514#endif /* 1250 PASS3 || 112x PASS1 */ 514#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
515 515
516 516
517/* 517/*
@@ -560,12 +560,12 @@
560#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) 560#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
561#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) 561#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
562 562
563#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 563#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
564#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) 564#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52)
565#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) 565#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53)
566#endif /* 1250 PASS2 || 112x PASS1 */ 566#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
567 567
568#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 568#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
569#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) 569#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54)
570#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) 570#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55)
571#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) 571#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56)
@@ -574,7 +574,7 @@
574#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) 574#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59)
575#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) 575#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60)
576#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) 576#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61)
577#endif /* 1250 PASS3 || 112x PASS1 */ 577#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
578 578
579#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) 579#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61)
580 580
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h
index f1f509f295c4..1b5cbc5c6454 100644
--- a/include/asm-mips/sibyte/sb1250_genbus.h
+++ b/include/asm-mips/sibyte/sb1250_genbus.h
@@ -6,9 +6,8 @@
6 * This module contains constants and macros useful for 6 * This module contains constants and macros useful for
7 * manipulating the SB1250's Generic Bus interface 7 * manipulating the SB1250's Generic Bus interface
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 10/21/02
10 * 10 * BCM1280 specification level: User's Manual 11/14/03
11 * Author: Mitch Lichtenberg
12 * 11 *
13 ********************************************************************* 12 *********************************************************************
14 * 13 *
@@ -51,19 +50,21 @@
51#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) 50#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL)
52#define K_IO_WIDTH_SEL_1 0 51#define K_IO_WIDTH_SEL_1 0
53#define K_IO_WIDTH_SEL_2 1 52#define K_IO_WIDTH_SEL_2 1
54#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 53#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
54 || SIBYTE_HDR_FEATURE_CHIP(1480)
55#define K_IO_WIDTH_SEL_1L 2 55#define K_IO_WIDTH_SEL_1L 2
56#endif /* 1250 PASS2 || 112x PASS1 */ 56#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
57#define K_IO_WIDTH_SEL_4 3 57#define K_IO_WIDTH_SEL_4 3
58#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) 58#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL)
59#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) 59#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL)
60 60
61#define S_IO_PARITY_ENA 4 61#define S_IO_PARITY_ENA 4
62#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) 62#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA)
63#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 63#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
64 || SIBYTE_HDR_FEATURE_CHIP(1480)
64#define S_IO_BURST_EN 5 65#define S_IO_BURST_EN 5
65#define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) 66#define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN)
66#endif /* 1250 PASS2 || 112x PASS1 */ 67#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
67#define S_IO_PARITY_ODD 6 68#define S_IO_PARITY_ODD 6
68#define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) 69#define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD)
69#define S_IO_NONMUX 7 70#define S_IO_NONMUX 7
@@ -96,8 +97,11 @@
96 97
97#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ 98#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */
98 99
100#define M_IO_BLK_CACHE _SB_MAKEMASK1(15)
101
102
99/* 103/*
100 * Generic Bus Region 0 Timing Registers (Table 11-7) 104 * Generic Bus Timing 0 Registers (Table 11-7)
101 */ 105 */
102 106
103#define S_IO_ALE_WIDTH 0 107#define S_IO_ALE_WIDTH 0
@@ -105,21 +109,23 @@
105#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) 109#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH)
106#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) 110#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH)
107 111
108#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 112#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
113 || SIBYTE_HDR_FEATURE_CHIP(1480)
109#define M_IO_EARLY_CS _SB_MAKEMASK1(3) 114#define M_IO_EARLY_CS _SB_MAKEMASK1(3)
110#endif /* 1250 PASS2 || 112x PASS1 */ 115#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
111 116
112#define S_IO_ALE_TO_CS 4 117#define S_IO_ALE_TO_CS 4
113#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) 118#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS)
114#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) 119#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS)
115#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) 120#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS)
116 121
117#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 122#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
123 || SIBYTE_HDR_FEATURE_CHIP(1480)
118#define S_IO_BURST_WIDTH _SB_MAKE64(6) 124#define S_IO_BURST_WIDTH _SB_MAKE64(6)
119#define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) 125#define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH)
120#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) 126#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH)
121#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) 127#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH)
122#endif /* 1250 PASS2 || 112x PASS1 */ 128#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
123 129
124#define S_IO_CS_WIDTH 8 130#define S_IO_CS_WIDTH 8
125#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) 131#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH)
@@ -141,9 +147,10 @@
141#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) 147#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE)
142#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) 148#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE)
143 149
144#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 150#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
151 || SIBYTE_HDR_FEATURE_CHIP(1480)
145#define M_IO_RDY_SYNC _SB_MAKEMASK1(3) 152#define M_IO_RDY_SYNC _SB_MAKEMASK1(3)
146#endif /* 1250 PASS2 || 112x PASS1 */ 153#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
147 154
148#define S_IO_WRITE_WIDTH 4 155#define S_IO_WRITE_WIDTH 4
149#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) 156#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH)
@@ -183,9 +190,127 @@
183#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) 190#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10)
184#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) 191#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11)
185#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) 192#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12)
186#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 193#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
187#define M_IO_COH_ERR _SB_MAKEMASK1(14) 194#define M_IO_COH_ERR _SB_MAKEMASK1(14)
188#endif /* 1250 PASS2 || 112x PASS1 */ 195#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
196
197
198/*
199 * Generic Bus Output Drive Control Register 0 (Table 14-18)
200 */
201
202#define S_IO_SLEW0 0
203#define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0)
204#define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0)
205#define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0)
206
207#define S_IO_DRV_A 2
208#define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A)
209#define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A)
210#define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A)
211
212#define S_IO_DRV_B 6
213#define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B)
214#define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B)
215#define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B)
216
217#define S_IO_DRV_C 10
218#define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C)
219#define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C)
220#define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C)
221
222#define S_IO_DRV_D 14
223#define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D)
224#define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D)
225#define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D)
226
227/*
228 * Generic Bus Output Drive Control Register 1 (Table 14-19)
229 */
230
231#define S_IO_DRV_E 2
232#define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E)
233#define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E)
234#define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E)
235
236#define S_IO_DRV_F 6
237#define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F)
238#define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F)
239#define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F)
240
241#define S_IO_SLEW1 8
242#define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1)
243#define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1)
244#define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1)
245
246#define S_IO_DRV_G 10
247#define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G)
248#define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G)
249#define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G)
250
251#define S_IO_SLEW2 12
252#define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2)
253#define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2)
254#define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2)
255
256#define S_IO_DRV_H 14
257#define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H)
258#define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H)
259#define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H)
260
261/*
262 * Generic Bus Output Drive Control Register 2 (Table 14-20)
263 */
264
265#define S_IO_DRV_J 2
266#define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J)
267#define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J)
268#define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J)
269
270#define S_IO_DRV_K 6
271#define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K)
272#define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K)
273#define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K)
274
275#define S_IO_DRV_L 10
276#define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L)
277#define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L)
278#define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L)
279
280#define S_IO_DRV_M 14
281#define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M)
282#define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M)
283#define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M)
284
285/*
286 * Generic Bus Output Drive Control Register 3 (Table 14-21)
287 */
288
289#define S_IO_SLEW3 0
290#define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3)
291#define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3)
292#define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3)
293
294#define S_IO_DRV_N 2
295#define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N)
296#define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N)
297#define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N)
298
299#define S_IO_DRV_P 6
300#define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P)
301#define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P)
302#define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P)
303
304#define S_IO_DRV_Q 10
305#define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q)
306#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q)
307#define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q)
308
309#define S_IO_DRV_R 14
310#define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R)
311#define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R)
312#define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R)
313
189 314
190/* 315/*
191 * PCMCIA configuration register (Table 12-6) 316 * PCMCIA configuration register (Table 12-6)
@@ -202,6 +327,22 @@
202#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) 327#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8)
203#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) 328#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9)
204 329
330#if SIBYTE_HDR_FEATURE_CHIP(1480)
331#define S_PCMCIA_MODE 16
332#define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE)
333#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE)
334#define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE)
335
336#define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */
337#define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */
338#define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */
339#define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */
340#define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */
341#define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */
342#define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */
343#endif
344
345
205/* 346/*
206 * PCMCIA status register (Table 12-7) 347 * PCMCIA status register (Table 12-7)
207 */ 348 */
@@ -272,5 +413,62 @@
272#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) 413#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14)
273#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) 414#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14)
274 415
416#if SIBYTE_HDR_FEATURE_CHIP(1480)
417
418/*
419 * GPIO Interrupt Additional Type Register
420 */
421
422#define K_GPIO_INTR_BOTHEDGE 0
423#define K_GPIO_INTR_RISEEDGE 1
424#define K_GPIO_INTR_UNPRED1 2
425#define K_GPIO_INTR_UNPRED2 3
426
427#define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2)
428#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n))
429#define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n))
430#define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n))
431
432#define S_GPIO_INTR_ATYPE0 0
433#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0)
434#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0)
435#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0)
436
437#define S_GPIO_INTR_ATYPE2 2
438#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2)
439#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2)
440#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2)
441
442#define S_GPIO_INTR_ATYPE4 4
443#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4)
444#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4)
445#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4)
446
447#define S_GPIO_INTR_ATYPE6 6
448#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6)
449#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6)
450#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6)
451
452#define S_GPIO_INTR_ATYPE8 8
453#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8)
454#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8)
455#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8)
456
457#define S_GPIO_INTR_ATYPE10 10
458#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10)
459#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10)
460#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10)
461
462#define S_GPIO_INTR_ATYPE12 12
463#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12)
464#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12)
465#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12)
466
467#define S_GPIO_INTR_ATYPE14 14
468#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14)
469#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14)
470#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14)
471#endif
472
275 473
276#endif 474#endif
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
index e173e2ea4c98..05c7b39f1b02 100644
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -8,8 +8,6 @@
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg
12 *
13 ********************************************************************* 11 *********************************************************************
14 * 12 *
15 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003
@@ -47,6 +45,10 @@
47 * First, the interrupt numbers. 45 * First, the interrupt numbers.
48 */ 46 */
49 47
48#if SIBYTE_HDR_FEATURE_1250_112x
49
50#define K_INT_SOURCES 64
51
50#define K_INT_WATCHDOG_TIMER_0 0 52#define K_INT_WATCHDOG_TIMER_0 0
51#define K_INT_WATCHDOG_TIMER_1 1 53#define K_INT_WATCHDOG_TIMER_1 1
52#define K_INT_TIMER_0 2 54#define K_INT_TIMER_0 2
@@ -244,4 +246,6 @@
244#define M_LDTVECT_RAISEMBOX 0x40 246#define M_LDTVECT_RAISEMBOX 0x40
245 247
246 248
249#endif /* 1250/112x */
250
247#endif 251#endif
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h
index 8afe8e01581b..842f205094af 100644
--- a/include/asm-mips/sibyte/sb1250_l2c.h
+++ b/include/asm-mips/sibyte/sb1250_l2c.h
@@ -8,8 +8,6 @@
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg
12 *
13 ********************************************************************* 11 *********************************************************************
14 * 12 *
15 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003
@@ -89,8 +87,13 @@
89#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY) 87#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY)
90#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY) 88#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY)
91 89
92#define S_L2C_MGMT_TAG 21 90#define S_L2C_MGMT_ECC_DIAG 21
93#define M_L2C_MGMT_TAG _SB_MAKEMASK(6,S_L2C_MGMT_TAG) 91#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_L2C_MGMT_ECC_DIAG)
92#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_ECC_DIAG)
93#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_L2C_MGMT_ECC_DIAG,M_L2C_MGMT_ECC_DIAG)
94
95#define S_L2C_MGMT_TAG 23
96#define M_L2C_MGMT_TAG _SB_MAKEMASK(4,S_L2C_MGMT_TAG)
94#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG) 97#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG)
95#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG) 98#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG)
96 99
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h
index f2617ded0a8f..7092535d1108 100644
--- a/include/asm-mips/sibyte/sb1250_ldt.h
+++ b/include/asm-mips/sibyte/sb1250_ldt.h
@@ -8,8 +8,6 @@
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg
12 *
13 ********************************************************************* 11 *********************************************************************
14 * 12 *
15 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
index 18e74e43f4a2..adfc688fa559 100644
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -8,8 +8,6 @@
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg
12 *
13 ********************************************************************* 11 *********************************************************************
14 * 12 *
15 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003
@@ -81,7 +79,10 @@
81#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) 79#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9)
82 80
83#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) 81#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17)
84#define M_MAC_RESERVED2 _SB_MAKEMASK1(18) 82
83#if SIBYTE_HDR_FEATURE_CHIP(1480)
84#define M_MAC_TIMESTAMP _SB_MAKEMASK1(18)
85#endif
85#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) 86#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19)
86#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) 87#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20)
87#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) 88#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21)
@@ -132,9 +133,9 @@
132#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) 133#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44)
133#endif /* 1250 PASS2 || 112x PASS1 */ 134#endif /* 1250 PASS2 || 112x PASS1 */
134 135
135#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 136#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
136#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) 137#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45)
137#endif /* 1250 PASS3 || 112x PASS1 */ 138#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
138 139
139#define S_MAC_BYPASS_IFG _SB_MAKE64(46) 140#define S_MAC_BYPASS_IFG _SB_MAKE64(46)
140#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) 141#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG)
@@ -176,10 +177,22 @@
176 177
177#define M_MAC_PORT_RESET _SB_MAKEMASK1(8) 178#define M_MAC_PORT_RESET _SB_MAKEMASK1(8)
178 179
180#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
179#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) 181#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10)
180#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) 182#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11)
181#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) 183#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12)
182#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) 184#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13)
185#endif
186
187/*
188 * MAC reset information register (1280/1255)
189 */
190#if SIBYTE_HDR_FEATURE_CHIP(1480)
191#define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8)
192#define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16)
193#define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24)
194#define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32)
195#endif
183 196
184/* 197/*
185 * MAC DMA Control Register 198 * MAC DMA Control Register
@@ -267,12 +280,12 @@
267#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) 280#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX)
268#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) 281#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX)
269 282
270#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 283#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
271#define S_MAC_PRE_LEN _SB_MAKE64(0) 284#define S_MAC_PRE_LEN _SB_MAKE64(0)
272#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) 285#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN)
273#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) 286#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN)
274#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) 287#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN)
275#endif /* 1250 PASS3 || 112x PASS1 */ 288#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
276 289
277#define S_MAC_IFG_TX _SB_MAKE64(6) 290#define S_MAC_IFG_TX _SB_MAKE64(6)
278#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) 291#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX)
@@ -458,9 +471,9 @@
458#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) 471#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR)
459#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) 472#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR)
460 473
461#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 474#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
462#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) 475#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52)
463#endif /* 1250 PASS3 || 112x PASS1 */ 476#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
464 477
465/* 478/*
466 * MAC Fifo Pointer Registers (Table 9-19) [Debug register] 479 * MAC Fifo Pointer Registers (Table 9-19) [Debug register]
@@ -594,7 +607,7 @@
594#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) 607#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET)
595#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) 608#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET)
596 609
597#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 610#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
598#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) 611#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16)
599#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) 612#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET)
600#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) 613#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET)
@@ -612,7 +625,7 @@
612#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) 625#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL)
613#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) 626#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL)
614#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) 627#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL)
615#endif /* 1250 PASS3 || 112x PASS1 */ 628#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
616 629
617/* 630/*
618 * MAC Receive Channel Select Registers (Table 9-25) 631 * MAC Receive Channel Select Registers (Table 9-25)
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
index 1dd41c927996..26e421498c97 100644
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -8,8 +8,6 @@
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg
12 *
13 ********************************************************************* 11 *********************************************************************
14 * 12 *
15 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003
@@ -324,6 +322,10 @@
324#define K_MC_tRFC_DEFAULT 12 322#define K_MC_tRFC_DEFAULT 12
325#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) 323#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT)
326 324
325#if SIBYTE_HDR_FEATURE(1250, PASS3)
326#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */
327#endif
328
327#define S_MC_tCwCr 40 329#define S_MC_tCwCr 40
328#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) 330#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr)
329#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) 331#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr)
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
index 9db80cd13a79..bab3a4580a36 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -8,8 +8,6 @@
8 * 8 *
9 * SB1250 specification level: 01/02/2002 9 * SB1250 specification level: 01/02/2002
10 * 10 *
11 * Author: Mitch Lichtenberg
12 *
13 ********************************************************************* 11 *********************************************************************
14 * 12 *
15 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003
@@ -61,6 +59,8 @@
61 * XXX: can't remove MC base 0 if 112x, since it's used by other macros, 59 * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
62 * since there is one reg there (but it could get its addr/offset constant). 60 * since there is one reg there (but it could get its addr/offset constant).
63 */ 61 */
62
63#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */
64#define A_MC_BASE_0 0x0010051000 64#define A_MC_BASE_0 0x0010051000
65#define A_MC_BASE_1 0x0010052000 65#define A_MC_BASE_1 0x0010052000
66#define MC_REGISTER_SPACING 0x1000 66#define MC_REGISTER_SPACING 0x1000
@@ -101,10 +101,14 @@
101#define R_MC_TEST_ECC 0x0000000420 101#define R_MC_TEST_ECC 0x0000000420
102#define R_MC_MCLK_CFG 0x0000000500 102#define R_MC_MCLK_CFG 0x0000000500
103 103
104#endif /* 1250 & 112x */
105
104/* ********************************************************************* 106/* *********************************************************************
105 * L2 Cache Control Registers 107 * L2 Cache Control Registers
106 ********************************************************************* */ 108 ********************************************************************* */
107 109
110#if SIBYTE_HDR_FEATURE_1250_112x /* This L2C only on 1250/112x */
111
108#define A_L2_READ_TAG 0x0010040018 112#define A_L2_READ_TAG 0x0010040018
109#define A_L2_ECC_TAG 0x0010040038 113#define A_L2_ECC_TAG 0x0010040038
110#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 114#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
@@ -125,13 +129,16 @@
125#define A_L2_READ_ADDRESS A_L2_READ_TAG 129#define A_L2_READ_ADDRESS A_L2_READ_TAG
126#define A_L2_EEC_ADDRESS A_L2_ECC_TAG 130#define A_L2_EEC_ADDRESS A_L2_ECC_TAG
127 131
132#endif
128 133
129/* ********************************************************************* 134/* *********************************************************************
130 * PCI Interface Registers 135 * PCI Interface Registers
131 ********************************************************************* */ 136 ********************************************************************* */
132 137
138#if SIBYTE_HDR_FEATURE_1250_112x /* This PCI/HT only on 1250/112x */
133#define A_PCI_TYPE00_HEADER 0x00DE000000 139#define A_PCI_TYPE00_HEADER 0x00DE000000
134#define A_PCI_TYPE01_HEADER 0x00DE000800 140#define A_PCI_TYPE01_HEADER 0x00DE000800
141#endif
135 142
136 143
137/* ********************************************************************* 144/* *********************************************************************
@@ -264,15 +271,15 @@
264 ********************************************************************* */ 271 ********************************************************************* */
265 272
266 273
274#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */
267#define R_DUART_NUM_PORTS 2 275#define R_DUART_NUM_PORTS 2
268 276
269#define A_DUART 0x0010060000 277#define A_DUART 0x0010060000
270 278
271#define A_DUART_REG(r)
272
273#define DUART_CHANREG_SPACING 0x100 279#define DUART_CHANREG_SPACING 0x100
274#define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) 280#define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg))
275#define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) 281#define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg))
282#endif /* 1250 & 112x */
276 283
277#define R_DUART_MODE_REG_1 0x100 284#define R_DUART_MODE_REG_1 0x100
278#define R_DUART_MODE_REG_2 0x110 285#define R_DUART_MODE_REG_2 0x110
@@ -307,11 +314,13 @@
307 314
308#define DUART_IMRISR_SPACING 0x20 315#define DUART_IMRISR_SPACING 0x20
309 316
317#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */
310#define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) 318#define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING)
311#define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) 319#define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING)
312 320
313#define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) 321#define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan))
314#define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) 322#define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan))
323#endif /* 1250 & 112x */
315 324
316 325
317 326
@@ -368,6 +377,8 @@
368 ********************************************************************* */ 377 ********************************************************************* */
369 378
370 379
380#if SIBYTE_HDR_FEATURE_1250_112x /* sync serial only on 1250/112x */
381
371#define A_SER_BASE_0 0x0010060400 382#define A_SER_BASE_0 0x0010060400
372#define A_SER_BASE_1 0x0010060800 383#define A_SER_BASE_1 0x0010060800
373#define SER_SPACING 0x400 384#define SER_SPACING 0x400
@@ -457,6 +468,8 @@
457#define R_SER_RMON_RX_ERRORS 0x000001F0 468#define R_SER_RMON_RX_ERRORS 0x000001F0
458#define R_SER_RMON_RX_BADADDR 0x000001F8 469#define R_SER_RMON_RX_BADADDR 0x000001F8
459 470
471#endif /* 1250/112x */
472
460/* ********************************************************************* 473/* *********************************************************************
461 * Generic Bus Registers 474 * Generic Bus Registers
462 ********************************************************************* */ 475 ********************************************************************* */
@@ -634,12 +647,13 @@
634 647
635#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 648#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
636#define A_SCD_SCRATCH 0x0010020C10 649#define A_SCD_SCRATCH 0x0010020C10
650#endif /* 1250 PASS2 || 112x PASS1 */
637 651
652#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
638#define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 653#define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000
639#define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 654#define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00
640#define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 655#define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08
641#endif /* 1250 PASS2 || 112x PASS1 */ 656#endif
642
643 657
644/* ********************************************************************* 658/* *********************************************************************
645 * System Control Registers 659 * System Control Registers
@@ -667,15 +681,16 @@
667#define A_ADDR_TRAP_CFG_1 0x0010020448 681#define A_ADDR_TRAP_CFG_1 0x0010020448
668#define A_ADDR_TRAP_CFG_2 0x0010020450 682#define A_ADDR_TRAP_CFG_2 0x0010020450
669#define A_ADDR_TRAP_CFG_3 0x0010020458 683#define A_ADDR_TRAP_CFG_3 0x0010020458
670#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 684#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
671#define A_ADDR_TRAP_REG_DEBUG 0x0010020460 685#define A_ADDR_TRAP_REG_DEBUG 0x0010020460
672#endif /* 1250 PASS2 || 112x PASS1 */ 686#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
673 687
674 688
675/* ********************************************************************* 689/* *********************************************************************
676 * System Interrupt Mapper Registers 690 * System Interrupt Mapper Registers
677 ********************************************************************* */ 691 ********************************************************************* */
678 692
693#if SIBYTE_HDR_FEATURE_1250_112x
679#define A_IMR_CPU0_BASE 0x0010020000 694#define A_IMR_CPU0_BASE 0x0010020000
680#define A_IMR_CPU1_BASE 0x0010022000 695#define A_IMR_CPU1_BASE 0x0010022000
681#define IMR_REGISTER_SPACING 0x2000 696#define IMR_REGISTER_SPACING 0x2000
@@ -700,6 +715,7 @@
700#define R_IMR_INTERRUPT_STATUS_COUNT 7 715#define R_IMR_INTERRUPT_STATUS_COUNT 7
701#define R_IMR_INTERRUPT_MAP_BASE 0x0200 716#define R_IMR_INTERRUPT_MAP_BASE 0x0200
702#define R_IMR_INTERRUPT_MAP_COUNT 64 717#define R_IMR_INTERRUPT_MAP_COUNT 64
718#endif /* 1250/112x */
703 719
704/* ********************************************************************* 720/* *********************************************************************
705 * System Performance Counter Registers 721 * System Performance Counter Registers
@@ -718,6 +734,7 @@
718#define A_SCD_BUS_ERR_STATUS 0x0010020880 734#define A_SCD_BUS_ERR_STATUS 0x0010020880
719#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 735#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
720#define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 736#define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0
737#define A_BUS_ERR_STATUS_DEBUG 0x00100208D0
721#endif /* 1250 PASS2 || 112x PASS1 */ 738#endif /* 1250 PASS2 || 112x PASS1 */
722#define A_BUS_ERR_DATA_0 0x00100208A0 739#define A_BUS_ERR_DATA_0 0x00100208A0
723#define A_BUS_ERR_DATA_1 0x00100208A8 740#define A_BUS_ERR_DATA_1 0x00100208A8
@@ -798,6 +815,7 @@
798 * Physical Address Map 815 * Physical Address Map
799 ********************************************************************* */ 816 ********************************************************************* */
800 817
818#if SIBYTE_HDR_FEATURE_1250_112x
801#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) 819#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000)
802#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) 820#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024))
803#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) 821#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000)
@@ -831,6 +849,7 @@
831#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) 849#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000)
832#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) 850#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000)
833#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) 851#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000)
852#endif
834 853
835 854
836#endif 855#endif
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index dbbd682fb47e..a667bc14a7cd 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -8,8 +8,6 @@
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg
12 *
13 ********************************************************************* 11 *********************************************************************
14 * 12 *
15 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003
@@ -51,26 +49,70 @@
51#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) 49#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION)
52#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) 50#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)
53 51
54#if SIBYTE_HDR_FEATURE_CHIP(1250) 52#define K_SYS_REVISION_BCM1250_PASS1 0x01
55#define K_SYS_REVISION_BCM1250_PASS1 1 53
56#define K_SYS_REVISION_BCM1250_PASS2 3 54#define K_SYS_REVISION_BCM1250_PASS2 0x03
57#define K_SYS_REVISION_BCM1250_A10 11 55#define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */
58#define K_SYS_REVISION_BCM1250_PASS2_2 16 56#define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */
59#define K_SYS_REVISION_BCM1250_B2 17 57#define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */
60#define K_SYS_REVISION_BCM1250_PASS3 32 58#define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */
61#define K_SYS_REVISION_BCM1250_C1 33 59#define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */
60#define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */
61#define K_SYS_REVISION_BCM1250_A9 0x08
62#define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8
62 63
64#define K_SYS_REVISION_BCM1250_PASS2_2 0x10
65#define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1
66#define K_SYS_REVISION_BCM1250_B1 0x10
67#define K_SYS_REVISION_BCM1250_B2 0x11
68
69#define K_SYS_REVISION_BCM1250_C0 0x20
70#define K_SYS_REVISION_BCM1250_C1 0x21
71#define K_SYS_REVISION_BCM1250_C2 0x22
72#define K_SYS_REVISION_BCM1250_C3 0x23
73
74#if SIBYTE_HDR_FEATURE_CHIP(1250)
63/* XXX: discourage people from using these constants. */ 75/* XXX: discourage people from using these constants. */
64#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 76#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1
65#define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 77#define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2
66#define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 78#define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2
67#define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 79#define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3
80#define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0
68#endif /* 1250 */ 81#endif /* 1250 */
69 82
70#if SIBYTE_HDR_FEATURE_CHIP(112x) 83#define K_SYS_REVISION_BCM112x_A1 0x20
71#define K_SYS_REVISION_BCM112x_A1 32 84#define K_SYS_REVISION_BCM112x_A2 0x21
72#define K_SYS_REVISION_BCM112x_A2 33 85#define K_SYS_REVISION_BCM112x_A3 0x22
73#endif /* 112x */ 86#define K_SYS_REVISION_BCM112x_A4 0x23
87
88#define K_SYS_REVISION_BCM1480_S0 0x01
89#define K_SYS_REVISION_BCM1480_A1 0x02
90#define K_SYS_REVISION_BCM1480_A2 0x03
91#define K_SYS_REVISION_BCM1480_A3 0x04
92#define K_SYS_REVISION_BCM1480_B0 0x11
93
94/*Cache size - 23:20 of revision register*/
95#define S_SYS_L2C_SIZE _SB_MAKE64(20)
96#define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE)
97#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE)
98#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE)
99
100#define K_SYS_L2C_SIZE_1MB 0
101#define K_SYS_L2C_SIZE_512KB 5
102#define K_SYS_L2C_SIZE_256KB 2
103#define K_SYS_L2C_SIZE_128KB 1
104
105#define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB
106#define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB
107#define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB
108
109
110/* Number of CPU cores, bits 27:24 of revision register*/
111#define S_SYS_NUM_CPUS _SB_MAKE64(24)
112#define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS)
113#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS)
114#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS)
115
74 116
75/* XXX: discourage people from using these constants. */ 117/* XXX: discourage people from using these constants. */
76#define S_SYS_PART _SB_MAKE64(16) 118#define S_SYS_PART _SB_MAKE64(16)
@@ -83,6 +125,8 @@
83#define K_SYS_PART_BCM1120 0x1121 125#define K_SYS_PART_BCM1120 0x1121
84#define K_SYS_PART_BCM1125 0x1123 126#define K_SYS_PART_BCM1125 0x1123
85#define K_SYS_PART_BCM1125H 0x1124 127#define K_SYS_PART_BCM1125H 0x1124
128#define K_SYS_PART_BCM1122 0x1113
129
86 130
87/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ 131/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */
88#define S_SYS_SOC_TYPE _SB_MAKE64(16) 132#define S_SYS_SOC_TYPE _SB_MAKE64(16)
@@ -96,6 +140,8 @@
96#define K_SYS_SOC_TYPE_BCM1125 0x3 140#define K_SYS_SOC_TYPE_BCM1125 0x3
97#define K_SYS_SOC_TYPE_BCM1125H 0x4 141#define K_SYS_SOC_TYPE_BCM1125H 0x4
98#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ 142#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */
143#define K_SYS_SOC_TYPE_BCM1x80 0x6
144#define K_SYS_SOC_TYPE_BCM1x55 0x7
99 145
100/* 146/*
101 * Calculate correct SOC type given a copy of system revision register. 147 * Calculate correct SOC type given a copy of system revision register.
@@ -127,10 +173,12 @@
127#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) 173#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID)
128#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) 174#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)
129 175
130/* System Manufacturing Register 176/*
131* Register: SCD_SYSTEM_MANUF 177 * System Manufacturing Register
132*/ 178 * Register: SCD_SYSTEM_MANUF
179 */
133 180
181#if SIBYTE_HDR_FEATURE_1250_112x
134/* Wafer ID: bits 31:0 */ 182/* Wafer ID: bits 31:0 */
135#define S_SYS_WAFERID1_200 _SB_MAKE64(0) 183#define S_SYS_WAFERID1_200 _SB_MAKE64(0)
136#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) 184#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200)
@@ -139,8 +187,8 @@
139 187
140#define S_SYS_BIN _SB_MAKE64(32) 188#define S_SYS_BIN _SB_MAKE64(32)
141#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) 189#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN)
142#define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) 190#define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN)
143#define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) 191#define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
144 192
145/* Wafer ID: bits 39:36 */ 193/* Wafer ID: bits 39:36 */
146#define S_SYS_WAFERID2_200 _SB_MAKE64(36) 194#define S_SYS_WAFERID2_200 _SB_MAKE64(36)
@@ -163,12 +211,14 @@
163#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) 211#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS)
164#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) 212#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS)
165#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) 213#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
214#endif
166 215
167/* 216/*
168 * System Config Register (Table 4-2) 217 * System Config Register (Table 4-2)
169 * Register: SCD_SYSTEM_CFG 218 * Register: SCD_SYSTEM_CFG
170 */ 219 */
171 220
221#if SIBYTE_HDR_FEATURE_1250_112x
172#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) 222#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
173#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) 223#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
174#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) 224#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
@@ -253,6 +303,8 @@
253#define M_SYS_SW_FLAG _SB_MAKEMASK1(63) 303#define M_SYS_SW_FLAG _SB_MAKEMASK1(63)
254#endif /* 1250 PASS2 || 112x PASS1 */ 304#endif /* 1250 PASS2 || 112x PASS1 */
255 305
306#endif
307
256 308
257/* 309/*
258 * Mailbox Registers (Table 4-3) 310 * Mailbox Registers (Table 4-3)
@@ -326,6 +378,7 @@
326 * System Performance Counters 378 * System Performance Counters
327 */ 379 */
328 380
381#if SIBYTE_HDR_FEATURE_1250_112x
329#define S_SPC_CFG_SRC0 0 382#define S_SPC_CFG_SRC0 0
330#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 383#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
331#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 384#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
@@ -348,6 +401,7 @@
348 401
349#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 402#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
350#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 403#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
404#endif
351 405
352 406
353/* 407/*
@@ -412,6 +466,7 @@
412 * Address Trap Registers 466 * Address Trap Registers
413 */ 467 */
414 468
469#if SIBYTE_HDR_FEATURE_1250_112x
415#define M_ATRAP_INDEX _SB_MAKEMASK(4,0) 470#define M_ATRAP_INDEX _SB_MAKEMASK(4,0)
416#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 471#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0)
417 472
@@ -436,7 +491,6 @@
436#define K_BUS_AGENT_IOB0 2 491#define K_BUS_AGENT_IOB0 2
437#define K_BUS_AGENT_IOB1 3 492#define K_BUS_AGENT_IOB1 3
438#define K_BUS_AGENT_SCD 4 493#define K_BUS_AGENT_SCD 4
439#define K_BUS_AGENT_RESERVED 5
440#define K_BUS_AGENT_L2C 6 494#define K_BUS_AGENT_L2C 6
441#define K_BUS_AGENT_MC 7 495#define K_BUS_AGENT_MC 7
442 496
@@ -454,10 +508,14 @@
454#define K_ATRAP_CFG_CATTR_NOTNONCOH 6 508#define K_ATRAP_CFG_CATTR_NOTNONCOH 6
455#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 509#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7
456 510
511#endif /* 1250/112x */
512
457/* 513/*
458 * Trace Buffer Config register 514 * Trace Buffer Config register
459 */ 515 */
460 516
517#if SIBYTE_HDR_FEATURE_1250_112x
518
461#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 519#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
462#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 520#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
463#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 521#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
@@ -475,6 +533,8 @@
475#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 533#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
476#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 534#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
477 535
536#endif /* 1250/112x */
537
478/* 538/*
479 * Trace Event registers 539 * Trace Event registers
480 */ 540 */
@@ -578,5 +638,7 @@
578#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) 638#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
579#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) 639#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
580#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) 640#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)
641#define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23)
642#define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24)
581 643
582#endif 644#endif
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h
index 335c53e92936..279a912213cd 100644
--- a/include/asm-mips/sibyte/sb1250_smbus.h
+++ b/include/asm-mips/sibyte/sb1250_smbus.h
@@ -6,9 +6,8 @@
6 * This module contains constants and macros useful for 6 * This module contains constants and macros useful for
7 * manipulating the SB1250's SMbus devices. 7 * manipulating the SB1250's SMbus devices.
8 * 8 *
9 * SB1250 specification level: 01/02/2002 9 * SB1250 specification level: 10/21/02
10 * 10 * BCM1280 specification level: 11/24/03
11 * Author: Mitch Lichtenberg
12 * 11 *
13 ********************************************************************* 12 *********************************************************************
14 * 13 *
@@ -47,6 +46,7 @@
47 46
48#define K_SMB_FREQ_400KHZ 0x1F 47#define K_SMB_FREQ_400KHZ 0x1F
49#define K_SMB_FREQ_100KHZ 0x7D 48#define K_SMB_FREQ_100KHZ 0x7D
49#define K_SMB_FREQ_10KHZ 1250
50 50
51#define S_SMB_CMD 0 51#define S_SMB_CMD 0
52#define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD) 52#define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD)
@@ -58,7 +58,11 @@
58 58
59#define M_SMB_ERR_INTR _SB_MAKEMASK1(0) 59#define M_SMB_ERR_INTR _SB_MAKEMASK1(0)
60#define M_SMB_FINISH_INTR _SB_MAKEMASK1(1) 60#define M_SMB_FINISH_INTR _SB_MAKEMASK1(1)
61#define M_SMB_DATA_OUT _SB_MAKEMASK1(4) 61
62#define S_SMB_DATA_OUT 4
63#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT)
64#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x,S_SMB_DATA_OUT)
65
62#define M_SMB_DATA_DIR _SB_MAKEMASK1(5) 66#define M_SMB_DATA_DIR _SB_MAKEMASK1(5)
63#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR 67#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR
64#define M_SMB_CLK_OUT _SB_MAKEMASK1(6) 68#define M_SMB_CLK_OUT _SB_MAKEMASK1(6)
@@ -71,8 +75,23 @@
71#define M_SMB_BUSY _SB_MAKEMASK1(0) 75#define M_SMB_BUSY _SB_MAKEMASK1(0)
72#define M_SMB_ERROR _SB_MAKEMASK1(1) 76#define M_SMB_ERROR _SB_MAKEMASK1(1)
73#define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2) 77#define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2)
74#define M_SMB_REF _SB_MAKEMASK1(6) 78
75#define M_SMB_DATA_IN _SB_MAKEMASK1(7) 79#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
80#define S_SMB_SCL_IN 5
81#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN)
82#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x,S_SMB_SCL_IN)
83#define G_SMB_SCL_IN(x) _SB_GETVALUE(x,S_SMB_SCL_IN,M_SMB_SCL_IN)
84#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
85
86#define S_SMB_REF 6
87#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF)
88#define V_SMB_REF(x) _SB_MAKEVALUE(x,S_SMB_REF)
89#define G_SMB_REF(x) _SB_GETVALUE(x,S_SMB_REF,M_SMB_REF)
90
91#define S_SMB_DATA_IN 7
92#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN)
93#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x,S_SMB_DATA_IN)
94#define G_SMB_DATA_IN(x) _SB_GETVALUE(x,S_SMB_DATA_IN,M_SMB_DATA_IN)
76 95
77/* 96/*
78 * SMBus Start/Command registers (Table 14-9) 97 * SMBus Start/Command registers (Table 14-9)
@@ -132,16 +151,14 @@
132#define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC) 151#define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC)
133 152
134 153
135#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 154#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
136 155
137#define S_SMB_CMDH 8 156#define S_SMB_CMDH 8
138#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMBH_CMD) 157#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMB_CMDH)
139#define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMBH_CMD) 158#define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMB_CMDH)
140 159
141#define M_SMB_EXTEND _SB_MAKEMASK1(14) 160#define M_SMB_EXTEND _SB_MAKEMASK1(14)
142 161
143#define M_SMB_DIR _SB_MAKEMASK1(13)
144
145#define S_SMB_DFMT 8 162#define S_SMB_DFMT 8
146#define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT) 163#define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT)
147#define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT) 164#define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT)
@@ -165,6 +182,23 @@
165#define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE) 182#define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
166#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) 183#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED)
167 184
168#endif /* 1250 PASS2 || 112x PASS1 */ 185#define S_SMB_AFMT 11
186#define M_SMB_AFMT _SB_MAKEMASK(2,S_SMB_AFMT)
187#define V_SMB_AFMT(x) _SB_MAKEVALUE(x,S_SMB_AFMT)
188#define G_SMB_AFMT(x) _SB_GETVALUE(x,S_SMB_AFMT,M_SMB_AFMT)
189
190#define K_SMB_AFMT_NONE 0
191#define K_SMB_AFMT_ADDR 1
192#define K_SMB_AFMT_ADDR_CMD1BYTE 2
193#define K_SMB_AFMT_ADDR_CMD2BYTE 3
194
195#define V_SMB_AFMT_NONE V_SMB_AFMT(K_SMB_AFMT_NONE)
196#define V_SMB_AFMT_ADDR V_SMB_AFMT(K_SMB_AFMT_ADDR)
197#define V_SMB_AFMT_ADDR_CMD1BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE)
198#define V_SMB_AFMT_ADDR_CMD2BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE)
199
200#define M_SMB_DIR _SB_MAKEMASK1(13)
201
202#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
169 203
170#endif 204#endif
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h
index fa2760d38b8b..dd154ac505d8 100644
--- a/include/asm-mips/sibyte/sb1250_syncser.h
+++ b/include/asm-mips/sibyte/sb1250_syncser.h
@@ -8,8 +8,6 @@
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg
12 *
13 ********************************************************************* 11 *********************************************************************
14 * 12 *
15 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h
index 923ea4f44e0f..e87045e62bf0 100644
--- a/include/asm-mips/sibyte/sb1250_uart.h
+++ b/include/asm-mips/sibyte/sb1250_uart.h
@@ -8,8 +8,6 @@
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg
12 *
13 ********************************************************************* 11 *********************************************************************
14 * 12 *
15 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003
@@ -240,7 +238,12 @@
240 */ 238 */
241 239
242#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) 240#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0)
243#define M_DUART_ISR_RX_A _SB_MAKEMASK1(1) 241
242#define S_DUART_ISR_RX_A 1
243#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A)
244#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x,S_DUART_ISR_RX_A)
245#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A)
246
244#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) 247#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2)
245#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) 248#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3)
246#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) 249#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4)
@@ -331,7 +334,7 @@
331#define M_DUART_OUT_PIN_CLR(chan) \ 334#define M_DUART_OUT_PIN_CLR(chan) \
332 (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) 335 (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
333 336
334#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 337#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
335/* 338/*
336 * Full Interrupt Control Register 339 * Full Interrupt Control Register
337 */ 340 */
@@ -345,7 +348,7 @@
345#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) 348#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME)
346#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) 349#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME)
347#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) 350#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME)
348#endif /* 1250 PASS2 || 112x PASS1 */ 351#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
349 352
350 353
351/* ********************************************************************** */ 354/* ********************************************************************** */
diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h
index 97fa0494c30c..06e1d528e03a 100644
--- a/include/asm-mips/sibyte/swarm.h
+++ b/include/asm-mips/sibyte/swarm.h
@@ -34,7 +34,7 @@
34#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200" 34#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
35#endif 35#endif
36#ifdef CONFIG_SIBYTE_LITTLESUR 36#ifdef CONFIG_SIBYTE_LITTLESUR
37#define SIBYTE_BOARD_NAME "BCM1250C2 (LittleSur)" 37#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
38#define SIBYTE_HAVE_PCMCIA 0 38#define SIBYTE_HAVE_PCMCIA 0
39#define SIBYTE_HAVE_IDE 1 39#define SIBYTE_HAVE_IDE 1
40#define SIBYTE_DEFAULT_CONSOLE "cfe0" 40#define SIBYTE_DEFAULT_CONSOLE "cfe0"
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h
index f7fbebaa0744..8edabb0be23f 100644
--- a/include/asm-mips/sigcontext.h
+++ b/include/asm-mips/sigcontext.h
@@ -27,14 +27,15 @@ struct sigcontext {
27 unsigned int sc_fpc_csr; 27 unsigned int sc_fpc_csr;
28 unsigned int sc_fpc_eir; /* Unused */ 28 unsigned int sc_fpc_eir; /* Unused */
29 unsigned int sc_used_math; 29 unsigned int sc_used_math;
30 unsigned int sc_ssflags; /* Unused */ 30 unsigned int sc_dsp; /* dsp status, was sc_ssflags */
31 unsigned long long sc_mdhi; 31 unsigned long long sc_mdhi;
32 unsigned long long sc_mdlo; 32 unsigned long long sc_mdlo;
33 33 unsigned long sc_hi1; /* Was sc_cause */
34 unsigned int sc_cause; /* Unused */ 34 unsigned long sc_lo1; /* Was sc_badvaddr */
35 unsigned int sc_badvaddr; /* Unused */ 35 unsigned long sc_hi2; /* Was sc_sigset[4] */
36 36 unsigned long sc_lo2;
37 unsigned long sc_sigset[4]; /* kernel's sigset_t */ 37 unsigned long sc_hi3;
38 unsigned long sc_lo3;
38}; 39};
39 40
40#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 41#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
@@ -48,19 +49,19 @@ struct sigcontext {
48 * Warning: this structure illdefined with sc_badvaddr being just an unsigned 49 * Warning: this structure illdefined with sc_badvaddr being just an unsigned
49 * int so it was changed to unsigned long in 2.6.0-test1. This may break 50 * int so it was changed to unsigned long in 2.6.0-test1. This may break
50 * binary compatibility - no prisoners. 51 * binary compatibility - no prisoners.
52 * DSP ASE in 2.6.12-rc4. Turn sc_mdhi and sc_mdlo into an array of four
53 * entries, add sc_dsp and sc_reserved for padding. No prisoners.
51 */ 54 */
52struct sigcontext { 55struct sigcontext {
53 unsigned long sc_regs[32]; 56 unsigned long sc_regs[32];
54 unsigned long sc_fpregs[32]; 57 unsigned long sc_fpregs[32];
55 unsigned long sc_mdhi; 58 unsigned long sc_hi[4];
56 unsigned long sc_mdlo; 59 unsigned long sc_lo[4];
57 unsigned long sc_pc; 60 unsigned long sc_pc;
58 unsigned long sc_badvaddr;
59 unsigned int sc_status;
60 unsigned int sc_fpc_csr; 61 unsigned int sc_fpc_csr;
61 unsigned int sc_fpc_eir;
62 unsigned int sc_used_math; 62 unsigned int sc_used_math;
63 unsigned int sc_cause; 63 unsigned int sc_dsp;
64 unsigned int sc_reserved;
64}; 65};
65 66
66#ifdef __KERNEL__ 67#ifdef __KERNEL__
@@ -68,23 +69,24 @@ struct sigcontext {
68#include <linux/posix_types.h> 69#include <linux/posix_types.h>
69 70
70struct sigcontext32 { 71struct sigcontext32 {
71 __u32 sc_regmask; /* Unused */ 72 __u32 sc_regmask; /* Unused */
72 __u32 sc_status; 73 __u32 sc_status;
73 __u64 sc_pc; 74 __u64 sc_pc;
74 __u64 sc_regs[32]; 75 __u64 sc_regs[32];
75 __u64 sc_fpregs[32]; 76 __u64 sc_fpregs[32];
76 __u32 sc_ownedfp; /* Unused */ 77 __u32 sc_ownedfp; /* Unused */
77 __u32 sc_fpc_csr; 78 __u32 sc_fpc_csr;
78 __u32 sc_fpc_eir; /* Unused */ 79 __u32 sc_fpc_eir; /* Unused */
79 __u32 sc_used_math; 80 __u32 sc_used_math;
80 __u32 sc_ssflags; /* Unused */ 81 __u32 sc_dsp; /* dsp status, was sc_ssflags */
81 __u64 sc_mdhi; 82 __u64 sc_mdhi;
82 __u64 sc_mdlo; 83 __u64 sc_mdlo;
83 84 __u32 sc_hi1; /* Was sc_cause */
84 __u32 sc_cause; /* Unused */ 85 __u32 sc_lo1; /* Was sc_badvaddr */
85 __u32 sc_badvaddr; /* Unused */ 86 __u32 sc_hi2; /* Was sc_sigset[4] */
86 87 __u32 sc_lo2;
87 __u32 sc_sigset[4]; /* kernel's sigset_t */ 88 __u32 sc_hi3;
89 __u32 sc_lo3;
88}; 90};
89#endif /* __KERNEL__ */ 91#endif /* __KERNEL__ */
90 92
diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h
index 698becab5a9e..2ba313d94a78 100644
--- a/include/asm-mips/siginfo.h
+++ b/include/asm-mips/siginfo.h
@@ -11,6 +11,7 @@
11 11
12#include <linux/config.h> 12#include <linux/config.h>
13 13
14#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))
14#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ... */ 15#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ... */
15 16
16#define HAVE_ARCH_SIGINFO_T 17#define HAVE_ARCH_SIGINFO_T
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
index f2c470f1d369..8ca539e80d87 100644
--- a/include/asm-mips/signal.h
+++ b/include/asm-mips/signal.h
@@ -98,12 +98,39 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */
98#define MINSIGSTKSZ 2048 98#define MINSIGSTKSZ 2048
99#define SIGSTKSZ 8192 99#define SIGSTKSZ 8192
100 100
101#ifdef __KERNEL__
102
103/*
104 * These values of sa_flags are used only by the kernel as part of the
105 * irq handling routines.
106 *
107 * SA_INTERRUPT is also used by the irq handling routines.
108 * SA_SHIRQ flag is for shared interrupt support on PCI and EISA.
109 */
110#define SA_SAMPLE_RANDOM SA_RESTART
111
112#ifdef CONFIG_TRAD_SIGNALS
113#define sig_uses_siginfo(ka) ((ka)->sa.sa_flags & SA_SIGINFO)
114#else
115#define sig_uses_siginfo(ka) (1)
116#endif
117
118#endif /* __KERNEL__ */
119
101#define SIG_BLOCK 1 /* for blocking signals */ 120#define SIG_BLOCK 1 /* for blocking signals */
102#define SIG_UNBLOCK 2 /* for unblocking signals */ 121#define SIG_UNBLOCK 2 /* for unblocking signals */
103#define SIG_SETMASK 3 /* for setting the signal mask */ 122#define SIG_SETMASK 3 /* for setting the signal mask */
104#define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility: 123#define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility:
105 set only the low 32 bit of the sigset. */ 124 set only the low 32 bit of the sigset. */
106#include <asm-generic/signal.h> 125
126/* Type of a signal handler. */
127typedef void __signalfn_t(int);
128typedef __signalfn_t __user *__sighandler_t;
129
130/* Fake signal functions */
131#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
132#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
133#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
107 134
108struct sigaction { 135struct sigaction {
109 unsigned int sa_flags; 136 unsigned int sa_flags;
diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h
index 0e00dd474afc..fb78773a5efe 100644
--- a/include/asm-mips/sn/sn0/arch.h
+++ b/include/asm-mips/sn/sn0/arch.h
@@ -74,13 +74,8 @@
74#define MAX_MEM_SLOTS 32 /* max slots per node */ 74#define MAX_MEM_SLOTS 32 /* max slots per node */
75#endif /* defined(N_MODE) */ 75#endif /* defined(N_MODE) */
76 76
77#if SABLE_RTL
78#define SLOT_SHIFT (28)
79#define SLOT_MIN_MEM_SIZE (16*1024*1024)
80#else
81#define SLOT_SHIFT (27) 77#define SLOT_SHIFT (27)
82#define SLOT_MIN_MEM_SIZE (32*1024*1024) 78#define SLOT_MIN_MEM_SIZE (32*1024*1024)
83#endif
84 79
85#define CPUS_PER_NODE 2 /* CPUs on a single hub */ 80#define CPUS_PER_NODE 2 /* CPUs on a single hub */
86#define CPUS_PER_NODE_SHFT 1 /* Bits to shift in the node number */ 81#define CPUS_PER_NODE_SHFT 1 /* Bits to shift in the node number */
diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h
index 753b6620e6fa..0bb31e5aaca6 100644
--- a/include/asm-mips/socket.h
+++ b/include/asm-mips/socket.h
@@ -37,8 +37,6 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */
37#define SO_ERROR 0x1007 /* get error status and clear */ 37#define SO_ERROR 0x1007 /* get error status and clear */
38#define SO_SNDBUF 0x1001 /* Send buffer size. */ 38#define SO_SNDBUF 0x1001 /* Send buffer size. */
39#define SO_RCVBUF 0x1002 /* Receive buffer. */ 39#define SO_RCVBUF 0x1002 /* Receive buffer. */
40#define SO_SNDBUFFORCE 0x100a
41#define SO_RCVBUFFORCE 0x100b
42#define SO_SNDLOWAT 0x1003 /* send low-water mark */ 40#define SO_SNDLOWAT 0x1003 /* send low-water mark */
43#define SO_RCVLOWAT 0x1004 /* receive low-water mark */ 41#define SO_RCVLOWAT 0x1004 /* receive low-water mark */
44#define SO_SNDTIMEO 0x1005 /* send timeout */ 42#define SO_SNDTIMEO 0x1005 /* send timeout */
@@ -69,6 +67,8 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */
69#define SCM_TIMESTAMP SO_TIMESTAMP 67#define SCM_TIMESTAMP SO_TIMESTAMP
70 68
71#define SO_PEERSEC 30 69#define SO_PEERSEC 30
70#define SO_SNDBUFFORCE 31
71#define SO_RCVBUFFORCE 33
72 72
73#ifdef __KERNEL__ 73#ifdef __KERNEL__
74 74
@@ -92,6 +92,7 @@ enum sock_type {
92 SOCK_RAW = 3, 92 SOCK_RAW = 3,
93 SOCK_RDM = 4, 93 SOCK_RDM = 4,
94 SOCK_SEQPACKET = 5, 94 SOCK_SEQPACKET = 5,
95 SOCK_DCCP = 6,
95 SOCK_PACKET = 10, 96 SOCK_PACKET = 10,
96}; 97};
97 98
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
index 4d0135b11156..669b8e349ff2 100644
--- a/include/asm-mips/spinlock.h
+++ b/include/asm-mips/spinlock.h
@@ -9,17 +9,16 @@
9#ifndef _ASM_SPINLOCK_H 9#ifndef _ASM_SPINLOCK_H
10#define _ASM_SPINLOCK_H 10#define _ASM_SPINLOCK_H
11 11
12#include <linux/config.h>
13#include <asm/war.h> 12#include <asm/war.h>
14 13
15/* 14/*
16 * Your basic SMP spinlocks, allowing only a single CPU anywhere 15 * Your basic SMP spinlocks, allowing only a single CPU anywhere
17 */ 16 */
18 17
19#define __raw_spin_is_locked(x) ((x)->lock != 0) 18#define __raw_spin_is_locked(x) ((x)->lock != 0)
20#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) 19#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
21#define __raw_spin_unlock_wait(x) \ 20#define __raw_spin_unlock_wait(x) \
22 do { cpu_relax(); } while ((x)->lock) 21 do { cpu_relax(); } while ((x)->lock)
23 22
24/* 23/*
25 * Simple spin lock operations. There are two variants, one clears IRQ's 24 * Simple spin lock operations. There are two variants, one clears IRQ's
@@ -119,6 +118,18 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
119 * read-locks. 118 * read-locks.
120 */ 119 */
121 120
121/*
122 * read_can_lock - would read_trylock() succeed?
123 * @lock: the rwlock in question.
124 */
125#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
126
127/*
128 * write_can_lock - would write_trylock() succeed?
129 * @lock: the rwlock in question.
130 */
131#define __raw_write_can_lock(rw) (!(rw)->lock)
132
122static inline void __raw_read_lock(raw_rwlock_t *rw) 133static inline void __raw_read_lock(raw_rwlock_t *rw)
123{ 134{
124 unsigned int tmp; 135 unsigned int tmp;
@@ -197,8 +208,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
197 " lui %1, 0x8000 \n" 208 " lui %1, 0x8000 \n"
198 " sc %1, %0 \n" 209 " sc %1, %0 \n"
199 " beqzl %1, 1b \n" 210 " beqzl %1, 1b \n"
200 " nop \n" 211 " sync \n"
201 " sync \n"
202 " .set reorder \n" 212 " .set reorder \n"
203 : "=m" (rw->lock), "=&r" (tmp) 213 : "=m" (rw->lock), "=&r" (tmp)
204 : "m" (rw->lock) 214 : "m" (rw->lock)
@@ -211,8 +221,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
211 " lui %1, 0x8000 \n" 221 " lui %1, 0x8000 \n"
212 " sc %1, %0 \n" 222 " sc %1, %0 \n"
213 " beqz %1, 1b \n" 223 " beqz %1, 1b \n"
214 " nop \n" 224 " sync \n"
215 " sync \n"
216 " .set reorder \n" 225 " .set reorder \n"
217 : "=m" (rw->lock), "=&r" (tmp) 226 : "=m" (rw->lock), "=&r" (tmp)
218 : "m" (rw->lock) 227 : "m" (rw->lock)
@@ -246,8 +255,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
246 " lui %1, 0x8000 \n" 255 " lui %1, 0x8000 \n"
247 " sc %1, %0 \n" 256 " sc %1, %0 \n"
248 " beqzl %1, 1b \n" 257 " beqzl %1, 1b \n"
249 " nop \n" 258 " sync \n"
250 " sync \n"
251 " li %2, 1 \n" 259 " li %2, 1 \n"
252 " .set reorder \n" 260 " .set reorder \n"
253 "2: \n" 261 "2: \n"
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 7b5e64600bc8..a8919dcc93c8 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -60,7 +60,6 @@
60 mfc0 k0, CP0_CONTEXT 60 mfc0 k0, CP0_CONTEXT
61 lui k1, %hi(kernelsp) 61 lui k1, %hi(kernelsp)
62 srl k0, k0, 23 62 srl k0, k0, 23
63 sll k0, k0, 2
64 addu k1, k0 63 addu k1, k0
65 LONG_L k1, %lo(kernelsp)(k1) 64 LONG_L k1, %lo(kernelsp)(k1)
66#endif 65#endif
@@ -76,9 +75,14 @@
76#endif 75#endif
77#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) 76#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
78 MFC0 k1, CP0_CONTEXT 77 MFC0 k1, CP0_CONTEXT
78 lui k0, %highest(kernelsp)
79 dsrl k1, 23 79 dsrl k1, 23
80 dsll k1, k1, 3 80 daddiu k0, %higher(kernelsp)
81 LONG_L k1, kernelsp(k1) 81 dsll k0, k0, 16
82 daddiu k0, %hi(kernelsp)
83 dsll k0, k0, 16
84 daddu k1, k1, k0
85 LONG_L k1, %lo(kernelsp)(k1)
82#endif 86#endif
83 .endm 87 .endm
84 88
@@ -86,25 +90,28 @@
86#ifdef CONFIG_32BIT 90#ifdef CONFIG_32BIT
87 mfc0 \temp, CP0_CONTEXT 91 mfc0 \temp, CP0_CONTEXT
88 srl \temp, 23 92 srl \temp, 23
89 sll \temp, 2
90 LONG_S \stackp, kernelsp(\temp)
91#endif 93#endif
92#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) 94#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
93 lw \temp, TI_CPU(gp) 95 lw \temp, TI_CPU(gp)
94 dsll \temp, 3 96 dsll \temp, 3
95 lui \temp2, %hi(kernelsp)
96 daddu \temp, \temp2
97 LONG_S \stackp, %lo(kernelsp)(\temp)
98#endif 97#endif
99#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) 98#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
100 lw \temp, TI_CPU(gp) 99 MFC0 \temp, CP0_CONTEXT
101 dsll \temp, 3 100 dsrl \temp, 23
102 LONG_S \stackp, kernelsp(\temp)
103#endif 101#endif
102 LONG_S \stackp, kernelsp(\temp)
104 .endm 103 .endm
105#else 104#else
106 .macro get_saved_sp /* Uniprocessor variation */ 105 .macro get_saved_sp /* Uniprocessor variation */
106#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
107 lui k1, %highest(kernelsp)
108 daddiu k1, %higher(kernelsp)
109 dsll k1, k1, 16
110 daddiu k1, %hi(kernelsp)
111 dsll k1, k1, 16
112#else
107 lui k1, %hi(kernelsp) 113 lui k1, %hi(kernelsp)
114#endif
108 LONG_L k1, %lo(kernelsp)(k1) 115 LONG_L k1, %lo(kernelsp)(k1)
109 .endm 116 .endm
110 117
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 6663efd49b27..330c4e497af3 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -17,6 +17,7 @@
17 17
18#include <asm/addrspace.h> 18#include <asm/addrspace.h>
19#include <asm/cpu-features.h> 19#include <asm/cpu-features.h>
20#include <asm/dsp.h>
20#include <asm/ptrace.h> 21#include <asm/ptrace.h>
21#include <asm/war.h> 22#include <asm/war.h>
22#include <asm/interrupt.h> 23#include <asm/interrupt.h>
@@ -70,7 +71,7 @@
70 * does not enforce ordering, since there is no data dependency between 71 * does not enforce ordering, since there is no data dependency between
71 * the read of "a" and the read of "b". Therefore, on some CPUs, such 72 * the read of "a" and the read of "b". Therefore, on some CPUs, such
72 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() 73 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
73 * in cases like thiswhere there are no data dependencies. 74 * in cases like this where there are no data dependencies.
74 */ 75 */
75 76
76#define read_barrier_depends() do { } while(0) 77#define read_barrier_depends() do { } while(0)
@@ -154,15 +155,15 @@ extern asmlinkage void *resume(void *last, void *next, void *next_ti);
154 155
155struct task_struct; 156struct task_struct;
156 157
157#define switch_to(prev,next,last) \ 158#define switch_to(prev,next,last) \
158do { \ 159do { \
159 (last) = resume(prev, next, next->thread_info); \ 160 if (cpu_has_dsp) \
161 __save_dsp(prev); \
162 (last) = resume(prev, next, next->thread_info); \
163 if (cpu_has_dsp) \
164 __restore_dsp(current); \
160} while(0) 165} while(0)
161 166
162#define ROT_IN_PIECES \
163 " .set noreorder \n" \
164 " .set reorder \n"
165
166static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) 167static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
167{ 168{
168 __u32 retval; 169 __u32 retval;
@@ -171,14 +172,17 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
171 unsigned long dummy; 172 unsigned long dummy;
172 173
173 __asm__ __volatile__( 174 __asm__ __volatile__(
175 " .set mips3 \n"
174 "1: ll %0, %3 # xchg_u32 \n" 176 "1: ll %0, %3 # xchg_u32 \n"
177 " .set mips0 \n"
175 " move %2, %z4 \n" 178 " move %2, %z4 \n"
179 " .set mips3 \n"
176 " sc %2, %1 \n" 180 " sc %2, %1 \n"
177 " beqzl %2, 1b \n" 181 " beqzl %2, 1b \n"
178 ROT_IN_PIECES
179#ifdef CONFIG_SMP 182#ifdef CONFIG_SMP
180 " sync \n" 183 " sync \n"
181#endif 184#endif
185 " .set mips0 \n"
182 : "=&r" (retval), "=m" (*m), "=&r" (dummy) 186 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
183 : "R" (*m), "Jr" (val) 187 : "R" (*m), "Jr" (val)
184 : "memory"); 188 : "memory");
@@ -186,13 +190,17 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
186 unsigned long dummy; 190 unsigned long dummy;
187 191
188 __asm__ __volatile__( 192 __asm__ __volatile__(
193 " .set mips3 \n"
189 "1: ll %0, %3 # xchg_u32 \n" 194 "1: ll %0, %3 # xchg_u32 \n"
195 " .set mips0 \n"
190 " move %2, %z4 \n" 196 " move %2, %z4 \n"
197 " .set mips3 \n"
191 " sc %2, %1 \n" 198 " sc %2, %1 \n"
192 " beqz %2, 1b \n" 199 " beqz %2, 1b \n"
193#ifdef CONFIG_SMP 200#ifdef CONFIG_SMP
194 " sync \n" 201 " sync \n"
195#endif 202#endif
203 " .set mips0 \n"
196 : "=&r" (retval), "=m" (*m), "=&r" (dummy) 204 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
197 : "R" (*m), "Jr" (val) 205 : "R" (*m), "Jr" (val)
198 : "memory"); 206 : "memory");
@@ -217,14 +225,15 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
217 unsigned long dummy; 225 unsigned long dummy;
218 226
219 __asm__ __volatile__( 227 __asm__ __volatile__(
228 " .set mips3 \n"
220 "1: lld %0, %3 # xchg_u64 \n" 229 "1: lld %0, %3 # xchg_u64 \n"
221 " move %2, %z4 \n" 230 " move %2, %z4 \n"
222 " scd %2, %1 \n" 231 " scd %2, %1 \n"
223 " beqzl %2, 1b \n" 232 " beqzl %2, 1b \n"
224 ROT_IN_PIECES
225#ifdef CONFIG_SMP 233#ifdef CONFIG_SMP
226 " sync \n" 234 " sync \n"
227#endif 235#endif
236 " .set mips0 \n"
228 : "=&r" (retval), "=m" (*m), "=&r" (dummy) 237 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
229 : "R" (*m), "Jr" (val) 238 : "R" (*m), "Jr" (val)
230 : "memory"); 239 : "memory");
@@ -232,6 +241,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
232 unsigned long dummy; 241 unsigned long dummy;
233 242
234 __asm__ __volatile__( 243 __asm__ __volatile__(
244 " .set mips3 \n"
235 "1: lld %0, %3 # xchg_u64 \n" 245 "1: lld %0, %3 # xchg_u64 \n"
236 " move %2, %z4 \n" 246 " move %2, %z4 \n"
237 " scd %2, %1 \n" 247 " scd %2, %1 \n"
@@ -239,6 +249,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
239#ifdef CONFIG_SMP 249#ifdef CONFIG_SMP
240 " sync \n" 250 " sync \n"
241#endif 251#endif
252 " .set mips0 \n"
242 : "=&r" (retval), "=m" (*m), "=&r" (dummy) 253 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
243 : "R" (*m), "Jr" (val) 254 : "R" (*m), "Jr" (val)
244 : "memory"); 255 : "memory");
@@ -286,34 +297,41 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
286 297
287 if (cpu_has_llsc && R10000_LLSC_WAR) { 298 if (cpu_has_llsc && R10000_LLSC_WAR) {
288 __asm__ __volatile__( 299 __asm__ __volatile__(
300 " .set push \n"
289 " .set noat \n" 301 " .set noat \n"
302 " .set mips3 \n"
290 "1: ll %0, %2 # __cmpxchg_u32 \n" 303 "1: ll %0, %2 # __cmpxchg_u32 \n"
291 " bne %0, %z3, 2f \n" 304 " bne %0, %z3, 2f \n"
305 " .set mips0 \n"
292 " move $1, %z4 \n" 306 " move $1, %z4 \n"
307 " .set mips3 \n"
293 " sc $1, %1 \n" 308 " sc $1, %1 \n"
294 " beqzl $1, 1b \n" 309 " beqzl $1, 1b \n"
295 ROT_IN_PIECES
296#ifdef CONFIG_SMP 310#ifdef CONFIG_SMP
297 " sync \n" 311 " sync \n"
298#endif 312#endif
299 "2: \n" 313 "2: \n"
300 " .set at \n" 314 " .set pop \n"
301 : "=&r" (retval), "=m" (*m) 315 : "=&r" (retval), "=m" (*m)
302 : "R" (*m), "Jr" (old), "Jr" (new) 316 : "R" (*m), "Jr" (old), "Jr" (new)
303 : "memory"); 317 : "memory");
304 } else if (cpu_has_llsc) { 318 } else if (cpu_has_llsc) {
305 __asm__ __volatile__( 319 __asm__ __volatile__(
320 " .set push \n"
306 " .set noat \n" 321 " .set noat \n"
322 " .set mips3 \n"
307 "1: ll %0, %2 # __cmpxchg_u32 \n" 323 "1: ll %0, %2 # __cmpxchg_u32 \n"
308 " bne %0, %z3, 2f \n" 324 " bne %0, %z3, 2f \n"
325 " .set mips0 \n"
309 " move $1, %z4 \n" 326 " move $1, %z4 \n"
327 " .set mips3 \n"
310 " sc $1, %1 \n" 328 " sc $1, %1 \n"
311 " beqz $1, 1b \n" 329 " beqz $1, 1b \n"
312#ifdef CONFIG_SMP 330#ifdef CONFIG_SMP
313 " sync \n" 331 " sync \n"
314#endif 332#endif
315 "2: \n" 333 "2: \n"
316 " .set at \n" 334 " .set pop \n"
317 : "=&r" (retval), "=m" (*m) 335 : "=&r" (retval), "=m" (*m)
318 : "R" (*m), "Jr" (old), "Jr" (new) 336 : "R" (*m), "Jr" (old), "Jr" (new)
319 : "memory"); 337 : "memory");
@@ -338,24 +356,27 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
338 356
339 if (cpu_has_llsc) { 357 if (cpu_has_llsc) {
340 __asm__ __volatile__( 358 __asm__ __volatile__(
359 " .set push \n"
341 " .set noat \n" 360 " .set noat \n"
361 " .set mips3 \n"
342 "1: lld %0, %2 # __cmpxchg_u64 \n" 362 "1: lld %0, %2 # __cmpxchg_u64 \n"
343 " bne %0, %z3, 2f \n" 363 " bne %0, %z3, 2f \n"
344 " move $1, %z4 \n" 364 " move $1, %z4 \n"
345 " scd $1, %1 \n" 365 " scd $1, %1 \n"
346 " beqzl $1, 1b \n" 366 " beqzl $1, 1b \n"
347 ROT_IN_PIECES
348#ifdef CONFIG_SMP 367#ifdef CONFIG_SMP
349 " sync \n" 368 " sync \n"
350#endif 369#endif
351 "2: \n" 370 "2: \n"
352 " .set at \n" 371 " .set pop \n"
353 : "=&r" (retval), "=m" (*m) 372 : "=&r" (retval), "=m" (*m)
354 : "R" (*m), "Jr" (old), "Jr" (new) 373 : "R" (*m), "Jr" (old), "Jr" (new)
355 : "memory"); 374 : "memory");
356 } else if (cpu_has_llsc) { 375 } else if (cpu_has_llsc) {
357 __asm__ __volatile__( 376 __asm__ __volatile__(
377 " .set push \n"
358 " .set noat \n" 378 " .set noat \n"
379 " .set mips3 \n"
359 "1: lld %0, %2 # __cmpxchg_u64 \n" 380 "1: lld %0, %2 # __cmpxchg_u64 \n"
360 " bne %0, %z3, 2f \n" 381 " bne %0, %z3, 2f \n"
361 " move $1, %z4 \n" 382 " move $1, %z4 \n"
@@ -365,7 +386,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
365 " sync \n" 386 " sync \n"
366#endif 387#endif
367 "2: \n" 388 "2: \n"
368 " .set at \n" 389 " .set pop \n"
369 : "=&r" (retval), "=m" (*m) 390 : "=&r" (retval), "=m" (*m)
370 : "R" (*m), "Jr" (old), "Jr" (new) 391 : "R" (*m), "Jr" (old), "Jr" (new)
371 : "memory"); 392 : "memory");
@@ -406,18 +427,20 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
406 427
407#define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr)))) 428#define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
408 429
430extern void set_handler (unsigned long offset, void *addr, unsigned long len);
431extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
432extern void *set_vi_handler (int n, void *addr);
433extern void *set_vi_srs_handler (int n, void *addr, int regset);
409extern void *set_except_vector(int n, void *addr); 434extern void *set_except_vector(int n, void *addr);
410extern void per_cpu_trap_init(void); 435extern void per_cpu_trap_init(void);
411 436
412extern NORET_TYPE void __die(const char *, struct pt_regs *, const char *file, 437extern NORET_TYPE void die(const char *, struct pt_regs *);
413 const char *func, unsigned long line);
414extern void __die_if_kernel(const char *, struct pt_regs *, const char *file,
415 const char *func, unsigned long line);
416 438
417#define die(msg, regs) \ 439static inline void die_if_kernel(const char *str, struct pt_regs *regs)
418 __die(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__) 440{
419#define die_if_kernel(msg, regs) \ 441 if (unlikely(!user_mode(regs)))
420 __die_if_kernel(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__) 442 die(str, regs);
443}
421 444
422extern int stop_a_enabled; 445extern int stop_a_enabled;
423 446
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h
index a70cb0854c8a..e6c24472e03f 100644
--- a/include/asm-mips/thread_info.h
+++ b/include/asm-mips/thread_info.h
@@ -26,6 +26,7 @@ struct thread_info {
26 struct task_struct *task; /* main task structure */ 26 struct task_struct *task; /* main task structure */
27 struct exec_domain *exec_domain; /* execution domain */ 27 struct exec_domain *exec_domain; /* execution domain */
28 unsigned long flags; /* low level flags */ 28 unsigned long flags; /* low level flags */
29 unsigned long tp_value; /* thread pointer */
29 __u32 cpu; /* current CPU */ 30 __u32 cpu; /* current CPU */
30 int preempt_count; /* 0 => preemptable, <0 => BUG */ 31 int preempt_count; /* 0 => preemptable, <0 => BUG */
31 32
@@ -114,6 +115,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
114#define TIF_SIGPENDING 2 /* signal pending */ 115#define TIF_SIGPENDING 2 /* signal pending */
115#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ 116#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
116#define TIF_SYSCALL_AUDIT 4 /* syscall auditing active */ 117#define TIF_SYSCALL_AUDIT 4 /* syscall auditing active */
118#define TIF_SECCOMP 5 /* secure computing */
117#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ 119#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
118#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ 120#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */
119#define TIF_MEMDIE 18 121#define TIF_MEMDIE 18
@@ -124,13 +126,14 @@ register struct thread_info *__current_thread_info __asm__("$28");
124#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) 126#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
125#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 127#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
126#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) 128#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
129#define _TIF_SECCOMP (1<<TIF_SECCOMP)
127#define _TIF_USEDFPU (1<<TIF_USEDFPU) 130#define _TIF_USEDFPU (1<<TIF_USEDFPU)
128#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 131#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
129 132
130#define _TIF_WORK_MASK 0x0000ffef /* work to do on 133/* work to do on interrupt/exception return */
131 interrupt/exception return */ 134#define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP)
132#define _TIF_ALLWORK_MASK 0x8000ffff /* work to do on any return to 135/* work to do on any return to u-space */
133 u-space */ 136#define _TIF_ALLWORK_MASK (0x8000ffff & ~_TIF_SECCOMP)
134 137
135#endif /* __KERNEL__ */ 138#endif /* __KERNEL__ */
136 139
diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h
index 179012263007..d02e019b0127 100644
--- a/include/asm-mips/traps.h
+++ b/include/asm-mips/traps.h
@@ -21,4 +21,7 @@
21extern void (*board_be_init)(void); 21extern void (*board_be_init)(void);
22extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 22extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
23 23
24extern void (*board_nmi_handler_setup)(void);
25extern void (*board_ejtag_handler_setup)(void);
26
24#endif /* _ASM_TRAPS_H */ 27#endif /* _ASM_TRAPS_H */
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
new file mode 100644
index 000000000000..0fbedafdcea8
--- /dev/null
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -0,0 +1,207 @@
1/*
2 * linux/include/asm-mips/tx4938/rbtx4938.h
3 * Definitions for TX4937/TX4938
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#ifndef __ASM_TX_BOARDS_RBTX4938_H
13#define __ASM_TX_BOARDS_RBTX4938_H
14
15#include <asm/addrspace.h>
16#include <asm/tx4938/tx4938.h>
17
18/* CS */
19#define RBTX4938_CE0 0x1c000000 /* 64M */
20#define RBTX4938_CE2 0x17f00000 /* 1M */
21
22/* Address map */
23#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000)
24#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002)
25#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004)
26#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006)
27#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008)
28#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000)
29#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002)
30#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004)
31#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000)
32#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002)
33#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004)
34#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006)
35#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008)
36#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a)
37#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c)
38#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000)
39#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000)
40#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002)
41#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008)
42#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a)
43#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000)
44#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002)
45#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004)
46#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000)
47
48/* Ethernet port address (Jumperless Mode (W12:Open)) */
49#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
50
51/* bits for ISTAT/IMASK/IMSTAT */
52#define RBTX4938_INTB_PCID 0
53#define RBTX4938_INTB_PCIC 1
54#define RBTX4938_INTB_PCIB 2
55#define RBTX4938_INTB_PCIA 3
56#define RBTX4938_INTB_RTC 4
57#define RBTX4938_INTB_ATA 5
58#define RBTX4938_INTB_MODEM 6
59#define RBTX4938_INTB_SWINT 7
60#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID)
61#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC)
62#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB)
63#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA)
64#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC)
65#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA)
66#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
67#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
68
69#define rbtx4938_fpga_rev_ptr \
70 ((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR)
71#define rbtx4938_led_ptr \
72 ((volatile unsigned char *)RBTX4938_LED_ADDR)
73#define rbtx4938_dipsw_ptr \
74 ((volatile unsigned char *)RBTX4938_DIPSW_ADDR)
75#define rbtx4938_bdipsw_ptr \
76 ((volatile unsigned char *)RBTX4938_BDIPSW_ADDR)
77#define rbtx4938_imask_ptr \
78 ((volatile unsigned char *)RBTX4938_IMASK_ADDR)
79#define rbtx4938_imask2_ptr \
80 ((volatile unsigned char *)RBTX4938_IMASK2_ADDR)
81#define rbtx4938_intpol_ptr \
82 ((volatile unsigned char *)RBTX4938_INTPOL_ADDR)
83#define rbtx4938_istat_ptr \
84 ((volatile unsigned char *)RBTX4938_ISTAT_ADDR)
85#define rbtx4938_istat2_ptr \
86 ((volatile unsigned char *)RBTX4938_ISTAT2_ADDR)
87#define rbtx4938_imstat_ptr \
88 ((volatile unsigned char *)RBTX4938_IMSTAT_ADDR)
89#define rbtx4938_imstat2_ptr \
90 ((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR)
91#define rbtx4938_softint_ptr \
92 ((volatile unsigned char *)RBTX4938_SOFTINT_ADDR)
93#define rbtx4938_piosel_ptr \
94 ((volatile unsigned char *)RBTX4938_PIOSEL_ADDR)
95#define rbtx4938_spics_ptr \
96 ((volatile unsigned char *)RBTX4938_SPICS_ADDR)
97#define rbtx4938_sfpwr_ptr \
98 ((volatile unsigned char *)RBTX4938_SFPWR_ADDR)
99#define rbtx4938_sfvol_ptr \
100 ((volatile unsigned char *)RBTX4938_SFVOL_ADDR)
101#define rbtx4938_softreset_ptr \
102 ((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR)
103#define rbtx4938_softresetlock_ptr \
104 ((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR)
105#define rbtx4938_pcireset_ptr \
106 ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
107
108/* SPI */
109#define RBTX4938_SEEPROM1_CHIPID 0
110#define RBTX4938_SEEPROM2_CHIPID 1
111#define RBTX4938_SEEPROM3_CHIPID 2
112#define RBTX4938_SRTC_CHIPID 3
113
114/*
115 * IRQ mappings
116 */
117
118#define RBTX4938_SOFT_INT0 0 /* not used */
119#define RBTX4938_SOFT_INT1 1 /* not used */
120#define RBTX4938_IRC_INT 2
121#define RBTX4938_TIMER_INT 7
122
123/* These are the virtual IRQ numbers, we divide all IRQ's into
124 * 'spaces', the 'space' determines where and how to enable/disable
125 * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
126 * IRQ hardware is supported.
127 */
128#define RBTX4938_NR_IRQ_LOCAL 8
129#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */
130#define RBTX4938_NR_IRQ_IOC 8
131
132#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */
133#define MI8259_IRQ_ISA_RAW_END 15
134#define TX4938_IRQ_CP0_RAW_BEG 0 /* tx4938 cpu built-in cp0 */
135#define TX4938_IRQ_CP0_RAW_END 7
136#define TX4938_IRQ_PIC_RAW_BEG 0 /* tx4938 cpu build-in pic */
137#define TX4938_IRQ_PIC_RAW_END 31
138
139#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */
140#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */
141
142#define TX4938_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG) /* 16 */
143#define TX4938_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END) /* 23 */
144
145#define TX4938_IRQ_PIC_BEG ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG) /* 24 */
146#define TX4938_IRQ_PIC_END ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END) /* 55 */
147#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2)
148#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2)
149#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0)
150#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1)
151#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7)
152
153#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0
154#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7
155
156#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
157#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
158#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG
159#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
160#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
161#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
162
163#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
164#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
165#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
166#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
167#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
168#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
169#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
170#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
171#define RBTX4938_IRQ_IRC_DMA(ch,n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n))
172#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
173#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
174#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
175#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
176#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
177#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
178#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
179#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
180#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
181#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
182#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
183#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
184#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
185#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
186#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
187#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
188#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
189#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
190#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
191
192
193/* IOC (PCI, etc) */
194#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC)
195/* Onboard 10M Ether */
196#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1)
197
198#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
199#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
200
201/* IRCR : Int. Control */
202#define TX4938_IRCR_LOW 0x00000000
203#define TX4938_IRCR_HIGH 0x00000001
204#define TX4938_IRCR_DOWN 0x00000002
205#define TX4938_IRCR_UP 0x00000003
206
207#endif /* __ASM_TX_BOARDS_RBTX4938_H */
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h
new file mode 100644
index 000000000000..0dbbab820a5a
--- /dev/null
+++ b/include/asm-mips/tx4938/spi.h
@@ -0,0 +1,74 @@
1/*
2 * linux/include/asm-mips/tx4938/spi.h
3 * Definitions for TX4937/TX4938 SPI
4 *
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14#ifndef __ASM_TX_BOARDS_TX4938_SPI_H
15#define __ASM_TX_BOARDS_TX4938_SPI_H
16
17/* SPI */
18struct spi_dev_desc {
19 unsigned int baud;
20 unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */
21 unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */
22 unsigned int polarity:1; /* 0:High-Active */
23 unsigned int phase:1; /* 0:Sample-Then-Shift */
24};
25
26extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init;
27extern void txx9_spi_irqinit(int irc_irq) __init;
28extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
29 unsigned char **inbufs, unsigned int *incounts,
30 unsigned char **outbufs, unsigned int *outcounts,
31 int cansleep);
32extern int spi_eeprom_write_enable(int chipid, int enable);
33extern int spi_eeprom_read_status(int chipid);
34extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
35extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len);
36extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init;
37
38#define TXX9_IMCLK (txx9_gbus_clock / 2)
39
40/*
41* SPI
42*/
43
44/* SPMCR : SPI Master Control */
45#define TXx9_SPMCR_OPMODE 0xc0
46#define TXx9_SPMCR_CONFIG 0x40
47#define TXx9_SPMCR_ACTIVE 0x80
48#define TXx9_SPMCR_SPSTP 0x02
49#define TXx9_SPMCR_BCLR 0x01
50
51/* SPCR0 : SPI Status */
52#define TXx9_SPCR0_TXIFL_MASK 0xc000
53#define TXx9_SPCR0_RXIFL_MASK 0x3000
54#define TXx9_SPCR0_SIDIE 0x0800
55#define TXx9_SPCR0_SOEIE 0x0400
56#define TXx9_SPCR0_RBSIE 0x0200
57#define TXx9_SPCR0_TBSIE 0x0100
58#define TXx9_SPCR0_IFSPSE 0x0010
59#define TXx9_SPCR0_SBOS 0x0004
60#define TXx9_SPCR0_SPHA 0x0002
61#define TXx9_SPCR0_SPOL 0x0001
62
63/* SPSR : SPI Status */
64#define TXx9_SPSR_TBSI 0x8000
65#define TXx9_SPSR_RBSI 0x4000
66#define TXx9_SPSR_TBS_MASK 0x3800
67#define TXx9_SPSR_RBS_MASK 0x0700
68#define TXx9_SPSR_SPOE 0x0080
69#define TXx9_SPSR_IFSD 0x0008
70#define TXx9_SPSR_SIDLE 0x0004
71#define TXx9_SPSR_STRDY 0x0002
72#define TXx9_SPSR_SRRDY 0x0001
73
74#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
new file mode 100644
index 000000000000..e25b1a0975cb
--- /dev/null
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -0,0 +1,706 @@
1/*
2 * linux/include/asm-mips/tx4938/tx4938.h
3 * Definitions for TX4937/TX4938
4 * Copyright (C) 2000-2001 Toshiba Corporation
5 *
6 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
7 * terms of the GNU General Public License version 2. This program is
8 * licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 */
13#ifndef __ASM_TX_BOARDS_TX4938_H
14#define __ASM_TX_BOARDS_TX4938_H
15
16#include <asm/tx4938/tx4938_mips.h>
17
18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
19#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b)
20
21#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG
22
23#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)
24#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)
25
26#define TX4938_PCIIO_0 0x10000000
27#define TX4938_PCIIO_1 0x01010000
28#define TX4938_PCIMEM_0 0x08000000
29#define TX4938_PCIMEM_1 0x11000000
30
31#define TX4938_PCIIO_SIZE_0 0x01000000
32#define TX4938_PCIIO_SIZE_1 0x00010000
33#define TX4938_PCIMEM_SIZE_0 0x08000000
34#define TX4938_PCIMEM_SIZE_1 0x00010000
35
36#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
37#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
38
39/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
40#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000)
41#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000)
42#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000)
43#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000)
44#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000)
45#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
46#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000)
47#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000)
48#define TX4938_NR_TMR 3
49#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
50#define TX4938_NR_SIO 2
51#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
52#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500)
53#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600)
54#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
55#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
56
57#ifndef _LANGUAGE_ASSEMBLY
58#include <asm/byteorder.h>
59
60#define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) ))
61
62#define TX4938_RD08( reg ) (*(vu08*)(reg))
63#define TX4938_WR08( reg, val ) ((*(vu08*)(reg))=(val))
64
65#define TX4938_RD16( reg ) (*(vu16*)(reg))
66#define TX4938_WR16( reg, val ) ((*(vu16*)(reg))=(val))
67
68#define TX4938_RD32( reg ) (*(vu32*)(reg))
69#define TX4938_WR32( reg, val ) ((*(vu32*)(reg))=(val))
70
71#define TX4938_RD64( reg ) (*(vu64*)(reg))
72#define TX4938_WR64( reg, val ) ((*(vu64*)(reg))=(val))
73
74#define TX4938_RD( reg ) TX4938_RD32( reg )
75#define TX4938_WR( reg, val ) TX4938_WR32( reg, val )
76
77#endif /* !__ASSEMBLY__ */
78
79#ifdef __ASSEMBLY__
80#define _CONST64(c) c
81#else
82#define _CONST64(c) c##ull
83
84#include <asm/byteorder.h>
85
86#ifdef __BIG_ENDIAN
87#define endian_def_l2(e1,e2) \
88 volatile unsigned long e1,e2
89#define endian_def_s2(e1,e2) \
90 volatile unsigned short e1,e2
91#define endian_def_sb2(e1,e2,e3) \
92 volatile unsigned short e1;volatile unsigned char e2,e3
93#define endian_def_b2s(e1,e2,e3) \
94 volatile unsigned char e1,e2;volatile unsigned short e3
95#define endian_def_b4(e1,e2,e3,e4) \
96 volatile unsigned char e1,e2,e3,e4
97#else
98#define endian_def_l2(e1,e2) \
99 volatile unsigned long e2,e1
100#define endian_def_s2(e1,e2) \
101 volatile unsigned short e2,e1
102#define endian_def_sb2(e1,e2,e3) \
103 volatile unsigned char e3,e2;volatile unsigned short e1
104#define endian_def_b2s(e1,e2,e3) \
105 volatile unsigned short e3;volatile unsigned char e2,e1
106#define endian_def_b4(e1,e2,e3,e4) \
107 volatile unsigned char e4,e3,e2,e1
108#endif
109
110
111struct tx4938_sdramc_reg {
112 volatile unsigned long long cr[4];
113 volatile unsigned long long unused0[4];
114 volatile unsigned long long tr;
115 volatile unsigned long long unused1[2];
116 volatile unsigned long long cmd;
117 volatile unsigned long long sfcmd;
118};
119
120struct tx4938_ebusc_reg {
121 volatile unsigned long long cr[8];
122};
123
124struct tx4938_dma_reg {
125 struct tx4938_dma_ch_reg {
126 volatile unsigned long long cha;
127 volatile unsigned long long sar;
128 volatile unsigned long long dar;
129 endian_def_l2(unused0, cntr);
130 endian_def_l2(unused1, sair);
131 endian_def_l2(unused2, dair);
132 endian_def_l2(unused3, ccr);
133 endian_def_l2(unused4, csr);
134 } ch[4];
135 volatile unsigned long long dbr[8];
136 volatile unsigned long long tdhr;
137 volatile unsigned long long midr;
138 endian_def_l2(unused0, mcr);
139};
140
141struct tx4938_pcic_reg {
142 volatile unsigned long pciid;
143 volatile unsigned long pcistatus;
144 volatile unsigned long pciccrev;
145 volatile unsigned long pcicfg1;
146 volatile unsigned long p2gm0plbase; /* +10 */
147 volatile unsigned long p2gm0pubase;
148 volatile unsigned long p2gm1plbase;
149 volatile unsigned long p2gm1pubase;
150 volatile unsigned long p2gm2pbase; /* +20 */
151 volatile unsigned long p2giopbase;
152 volatile unsigned long unused0;
153 volatile unsigned long pcisid;
154 volatile unsigned long unused1; /* +30 */
155 volatile unsigned long pcicapptr;
156 volatile unsigned long unused2;
157 volatile unsigned long pcicfg2;
158 volatile unsigned long g2ptocnt; /* +40 */
159 volatile unsigned long unused3[15];
160 volatile unsigned long g2pstatus; /* +80 */
161 volatile unsigned long g2pmask;
162 volatile unsigned long pcisstatus;
163 volatile unsigned long pcimask;
164 volatile unsigned long p2gcfg; /* +90 */
165 volatile unsigned long p2gstatus;
166 volatile unsigned long p2gmask;
167 volatile unsigned long p2gccmd;
168 volatile unsigned long unused4[24]; /* +a0 */
169 volatile unsigned long pbareqport; /* +100 */
170 volatile unsigned long pbacfg;
171 volatile unsigned long pbastatus;
172 volatile unsigned long pbamask;
173 volatile unsigned long pbabm; /* +110 */
174 volatile unsigned long pbacreq;
175 volatile unsigned long pbacgnt;
176 volatile unsigned long pbacstate;
177 volatile unsigned long long g2pmgbase[3]; /* +120 */
178 volatile unsigned long long g2piogbase;
179 volatile unsigned long g2pmmask[3]; /* +140 */
180 volatile unsigned long g2piomask;
181 volatile unsigned long long g2pmpbase[3]; /* +150 */
182 volatile unsigned long long g2piopbase;
183 volatile unsigned long pciccfg; /* +170 */
184 volatile unsigned long pcicstatus;
185 volatile unsigned long pcicmask;
186 volatile unsigned long unused5;
187 volatile unsigned long long p2gmgbase[3]; /* +180 */
188 volatile unsigned long long p2giogbase;
189 volatile unsigned long g2pcfgadrs; /* +1a0 */
190 volatile unsigned long g2pcfgdata;
191 volatile unsigned long unused6[8];
192 volatile unsigned long g2pintack;
193 volatile unsigned long g2pspc;
194 volatile unsigned long unused7[12]; /* +1d0 */
195 volatile unsigned long long pdmca; /* +200 */
196 volatile unsigned long long pdmga;
197 volatile unsigned long long pdmpa;
198 volatile unsigned long long pdmctr;
199 volatile unsigned long long pdmcfg; /* +220 */
200 volatile unsigned long long pdmsts;
201};
202
203struct tx4938_aclc_reg {
204 volatile unsigned long acctlen;
205 volatile unsigned long acctldis;
206 volatile unsigned long acregacc;
207 volatile unsigned long unused0;
208 volatile unsigned long acintsts;
209 volatile unsigned long acintmsts;
210 volatile unsigned long acinten;
211 volatile unsigned long acintdis;
212 volatile unsigned long acsemaph;
213 volatile unsigned long unused1[7];
214 volatile unsigned long acgpidat;
215 volatile unsigned long acgpodat;
216 volatile unsigned long acslten;
217 volatile unsigned long acsltdis;
218 volatile unsigned long acfifosts;
219 volatile unsigned long unused2[11];
220 volatile unsigned long acdmasts;
221 volatile unsigned long acdmasel;
222 volatile unsigned long unused3[6];
223 volatile unsigned long acaudodat;
224 volatile unsigned long acsurrdat;
225 volatile unsigned long accentdat;
226 volatile unsigned long aclfedat;
227 volatile unsigned long acaudiat;
228 volatile unsigned long unused4;
229 volatile unsigned long acmodoat;
230 volatile unsigned long acmodidat;
231 volatile unsigned long unused5[15];
232 volatile unsigned long acrevid;
233};
234
235
236struct tx4938_tmr_reg {
237 volatile unsigned long tcr;
238 volatile unsigned long tisr;
239 volatile unsigned long cpra;
240 volatile unsigned long cprb;
241 volatile unsigned long itmr;
242 volatile unsigned long unused0[3];
243 volatile unsigned long ccdr;
244 volatile unsigned long unused1[3];
245 volatile unsigned long pgmr;
246 volatile unsigned long unused2[3];
247 volatile unsigned long wtmr;
248 volatile unsigned long unused3[43];
249 volatile unsigned long trr;
250};
251
252struct tx4938_sio_reg {
253 volatile unsigned long lcr;
254 volatile unsigned long dicr;
255 volatile unsigned long disr;
256 volatile unsigned long cisr;
257 volatile unsigned long fcr;
258 volatile unsigned long flcr;
259 volatile unsigned long bgr;
260 volatile unsigned long tfifo;
261 volatile unsigned long rfifo;
262};
263
264struct tx4938_pio_reg {
265 volatile unsigned long dout;
266 volatile unsigned long din;
267 volatile unsigned long dir;
268 volatile unsigned long od;
269 volatile unsigned long flag[2];
270 volatile unsigned long pol;
271 volatile unsigned long intc;
272 volatile unsigned long maskcpu;
273 volatile unsigned long maskext;
274};
275struct tx4938_irc_reg {
276 volatile unsigned long cer;
277 volatile unsigned long cr[2];
278 volatile unsigned long unused0;
279 volatile unsigned long ilr[8];
280 volatile unsigned long unused1[4];
281 volatile unsigned long imr;
282 volatile unsigned long unused2[7];
283 volatile unsigned long scr;
284 volatile unsigned long unused3[7];
285 volatile unsigned long ssr;
286 volatile unsigned long unused4[7];
287 volatile unsigned long csr;
288};
289
290struct tx4938_ndfmc_reg {
291 endian_def_l2(unused0, dtr);
292 endian_def_l2(unused1, mcr);
293 endian_def_l2(unused2, sr);
294 endian_def_l2(unused3, isr);
295 endian_def_l2(unused4, imr);
296 endian_def_l2(unused5, spr);
297 endian_def_l2(unused6, rstr);
298};
299
300struct tx4938_spi_reg {
301 volatile unsigned long mcr;
302 volatile unsigned long cr0;
303 volatile unsigned long cr1;
304 volatile unsigned long fs;
305 volatile unsigned long unused1;
306 volatile unsigned long sr;
307 volatile unsigned long dr;
308 volatile unsigned long unused2;
309};
310
311struct tx4938_sramc_reg {
312 volatile unsigned long long cr;
313};
314
315struct tx4938_ccfg_reg {
316 volatile unsigned long long ccfg;
317 volatile unsigned long long crir;
318 volatile unsigned long long pcfg;
319 volatile unsigned long long tear;
320 volatile unsigned long long clkctr;
321 volatile unsigned long long unused0;
322 volatile unsigned long long garbc;
323 volatile unsigned long long unused1;
324 volatile unsigned long long unused2;
325 volatile unsigned long long ramp;
326 volatile unsigned long long unused3;
327 volatile unsigned long long jmpadr;
328};
329
330#undef endian_def_l2
331#undef endian_def_s2
332#undef endian_def_sb2
333#undef endian_def_b2s
334#undef endian_def_b4
335
336#endif /* __ASSEMBLY__ */
337
338/*
339 * NDFMC
340 */
341
342/* NDFMCR : NDFMC Mode Control */
343#define TX4938_NDFMCR_WE 0x80
344#define TX4938_NDFMCR_ECC_ALL 0x60
345#define TX4938_NDFMCR_ECC_RESET 0x60
346#define TX4938_NDFMCR_ECC_READ 0x40
347#define TX4938_NDFMCR_ECC_ON 0x20
348#define TX4938_NDFMCR_ECC_OFF 0x00
349#define TX4938_NDFMCR_CE 0x10
350#define TX4938_NDFMCR_BSPRT 0x04
351#define TX4938_NDFMCR_ALE 0x02
352#define TX4938_NDFMCR_CLE 0x01
353
354/* NDFMCR : NDFMC Status */
355#define TX4938_NDFSR_BUSY 0x80
356
357/* NDFMCR : NDFMC Reset */
358#define TX4938_NDFRSTR_RST 0x01
359
360/*
361 * IRC
362 */
363
364#define TX4938_IR_ECCERR 0
365#define TX4938_IR_WTOERR 1
366#define TX4938_NUM_IR_INT 6
367#define TX4938_IR_INT(n) (2 + (n))
368#define TX4938_NUM_IR_SIO 2
369#define TX4938_IR_SIO(n) (8 + (n))
370#define TX4938_NUM_IR_DMA 4
371#define TX4938_IR_DMA(ch,n) ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */
372#define TX4938_IR_PIO 14
373#define TX4938_IR_PDMAC 15
374#define TX4938_IR_PCIC 16
375#define TX4938_NUM_IR_TMR 3
376#define TX4938_IR_TMR(n) (17 + (n))
377#define TX4938_IR_NDFMC 21
378#define TX4938_IR_PCIERR 22
379#define TX4938_IR_PCIPME 23
380#define TX4938_IR_ACLC 24
381#define TX4938_IR_ACLCPME 25
382#define TX4938_IR_PCIC1 26
383#define TX4938_IR_SPI 31
384#define TX4938_NUM_IR 32
385/* multiplex */
386#define TX4938_IR_ETH0 TX4938_IR_INT(4)
387#define TX4938_IR_ETH1 TX4938_IR_INT(3)
388
389/*
390 * CCFG
391 */
392/* CCFG : Chip Configuration */
393#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000)
394#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000)
395#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000)
396#define TX4938_CCFG_TINTDIS 0x01000000
397#define TX4938_CCFG_PCI66 0x00800000
398#define TX4938_CCFG_PCIMODE 0x00400000
399#define TX4938_CCFG_PCI1_66 0x00200000
400#define TX4938_CCFG_DIVMODE_MASK 0x001e0000
401#define TX4938_CCFG_DIVMODE_2 (0x4 << 17)
402#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
403#define TX4938_CCFG_DIVMODE_3 (0x5 << 17)
404#define TX4938_CCFG_DIVMODE_4 (0x6 << 17)
405#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
406#define TX4938_CCFG_DIVMODE_8 (0x0 << 17)
407#define TX4938_CCFG_DIVMODE_10 (0xb << 17)
408#define TX4938_CCFG_DIVMODE_12 (0x1 << 17)
409#define TX4938_CCFG_DIVMODE_16 (0x2 << 17)
410#define TX4938_CCFG_DIVMODE_18 (0x9 << 17)
411#define TX4938_CCFG_BEOW 0x00010000
412#define TX4938_CCFG_WR 0x00008000
413#define TX4938_CCFG_TOE 0x00004000
414#define TX4938_CCFG_PCIXARB 0x00002000
415#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
416#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
417#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10)
418#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10)
419#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10)
420#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10)
421#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10)
422#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10)
423#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10)
424#define TX4938_CCFG_PCI1DMD 0x00000100
425#define TX4938_CCFG_SYSSP_MASK 0x000000c0
426#define TX4938_CCFG_ENDIAN 0x00000004
427#define TX4938_CCFG_HALT 0x00000002
428#define TX4938_CCFG_ACEHOLD 0x00000001
429
430/* PCFG : Pin Configuration */
431#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000)
432#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000)
433#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000)
434#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000)
435#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000)
436#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000)
437#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
438#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
439#define TX4938_PCFG_SYSCLKEN 0x08000000
440#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
441#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
442#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000
443#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
444#define TX4938_PCFG_SEL2 0x00000200
445#define TX4938_PCFG_SEL1 0x00000100
446#define TX4938_PCFG_DMASEL_ALL 0x0000000f
447#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000
448#define TX4938_PCFG_DMASEL0_SIO1 0x00000001
449#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000
450#define TX4938_PCFG_DMASEL1_SIO1 0x00000002
451#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000
452#define TX4938_PCFG_DMASEL2_SIO0 0x00000004
453#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000
454#define TX4938_PCFG_DMASEL3_SIO0 0x00000008
455
456/* CLKCTR : Clock Control */
457#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000)
458#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000)
459#define TX4938_CLKCTR_ETH1CKD 0x80000000
460#define TX4938_CLKCTR_ETH0CKD 0x40000000
461#define TX4938_CLKCTR_SPICKD 0x20000000
462#define TX4938_CLKCTR_SRAMCKD 0x10000000
463#define TX4938_CLKCTR_PCIC1CKD 0x08000000
464#define TX4938_CLKCTR_DMA1CKD 0x04000000
465#define TX4938_CLKCTR_ACLCKD 0x02000000
466#define TX4938_CLKCTR_PIOCKD 0x01000000
467#define TX4938_CLKCTR_DMACKD 0x00800000
468#define TX4938_CLKCTR_PCICKD 0x00400000
469#define TX4938_CLKCTR_TM0CKD 0x00100000
470#define TX4938_CLKCTR_TM1CKD 0x00080000
471#define TX4938_CLKCTR_TM2CKD 0x00040000
472#define TX4938_CLKCTR_SIO0CKD 0x00020000
473#define TX4938_CLKCTR_SIO1CKD 0x00010000
474#define TX4938_CLKCTR_ETH1RST 0x00008000
475#define TX4938_CLKCTR_ETH0RST 0x00004000
476#define TX4938_CLKCTR_SPIRST 0x00002000
477#define TX4938_CLKCTR_SRAMRST 0x00001000
478#define TX4938_CLKCTR_PCIC1RST 0x00000800
479#define TX4938_CLKCTR_DMA1RST 0x00000400
480#define TX4938_CLKCTR_ACLRST 0x00000200
481#define TX4938_CLKCTR_PIORST 0x00000100
482#define TX4938_CLKCTR_DMARST 0x00000080
483#define TX4938_CLKCTR_PCIRST 0x00000040
484#define TX4938_CLKCTR_TM0RST 0x00000010
485#define TX4938_CLKCTR_TM1RST 0x00000008
486#define TX4938_CLKCTR_TM2RST 0x00000004
487#define TX4938_CLKCTR_SIO0RST 0x00000002
488#define TX4938_CLKCTR_SIO1RST 0x00000001
489
490/* bits for G2PSTATUS/G2PMASK */
491#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003
492#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002
493#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001
494
495/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
496#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900
497
498/* bits for PBACFG */
499#define TX4938_PCIC_PBACFG_FIXPA 0x00000008
500#define TX4938_PCIC_PBACFG_RPBA 0x00000004
501#define TX4938_PCIC_PBACFG_PBAEN 0x00000002
502#define TX4938_PCIC_PBACFG_BMCEN 0x00000001
503
504/* bits for G2PMnGBASE */
505#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
506#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
507
508/* bits for G2PIOGBASE */
509#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
510#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
511
512/* bits for PCICSTATUS/PCICMASK */
513#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8
514#define TX4938_PCIC_PCICSTATUS_PME 0x00000400
515#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200
516#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100
517#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080
518#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020
519#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010
520#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008
521#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002
522#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001
523
524/* bits for PCICCFG */
525#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
526#define TX4938_PCIC_PCICCFG_HRST 0x00000800
527#define TX4938_PCIC_PCICCFG_SRST 0x00000400
528#define TX4938_PCIC_PCICCFG_IRBER 0x00000200
529#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
530#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100
531#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080
532#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040
533#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020
534#define TX4938_PCIC_PCICCFG_TCAR 0x00000010
535#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008
536
537/* bits for P2GMnGBASE */
538#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
539#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
540#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
541
542/* bits for P2GIOGBASE */
543#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
544#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
545#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
546
547#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
548#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
549
550/* bits for PDMCFG */
551#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000
552#define TX4938_PCIC_PDMCFG_EXFER 0x00100000
553#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800
554#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
555#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11)
556#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11)
557#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11)
558#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11)
559#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11)
560#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11)
561#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
562#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400
563#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200
564#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100
565#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080
566#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040
567#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020
568#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
569#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
570#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
571#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
572#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002
573#define TX4938_PCIC_PDMCFG_CHRST 0x00000001
574
575/* bits for PDMSTS */
576#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
577#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
578#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
579#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000
580#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800
581#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400
582#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200
583#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100
584#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080
585#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040
586#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020
587#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008
588#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004
589#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002
590#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001
591#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0
592#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f
593
594/*
595 * DMA
596 */
597/* bits for MCR */
598#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch))
599#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch))
600#define TX4938_DMA_MCR_RSFIF 0x00000080
601#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
602#define TX4938_DMA_MCR_RPRT 0x00000002
603#define TX4938_DMA_MCR_MSTEN 0x00000001
604
605/* bits for CCRn */
606#define TX4938_DMA_CCR_IMMCHN 0x20000000
607#define TX4938_DMA_CCR_USEXFSZ 0x10000000
608#define TX4938_DMA_CCR_LE 0x08000000
609#define TX4938_DMA_CCR_DBINH 0x04000000
610#define TX4938_DMA_CCR_SBINH 0x02000000
611#define TX4938_DMA_CCR_CHRST 0x01000000
612#define TX4938_DMA_CCR_RVBYTE 0x00800000
613#define TX4938_DMA_CCR_ACKPOL 0x00400000
614#define TX4938_DMA_CCR_REQPL 0x00200000
615#define TX4938_DMA_CCR_EGREQ 0x00100000
616#define TX4938_DMA_CCR_CHDN 0x00080000
617#define TX4938_DMA_CCR_DNCTL 0x00060000
618#define TX4938_DMA_CCR_EXTRQ 0x00010000
619#define TX4938_DMA_CCR_INTRQD 0x0000e000
620#define TX4938_DMA_CCR_INTENE 0x00001000
621#define TX4938_DMA_CCR_INTENC 0x00000800
622#define TX4938_DMA_CCR_INTENT 0x00000400
623#define TX4938_DMA_CCR_CHNEN 0x00000200
624#define TX4938_DMA_CCR_XFACT 0x00000100
625#define TX4938_DMA_CCR_SMPCHN 0x00000020
626#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
627#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2)
628#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3)
629#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4)
630#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5)
631#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
632#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
633#define TX4938_DMA_CCR_MEMIO 0x00000002
634#define TX4938_DMA_CCR_SNGAD 0x00000001
635
636/* bits for CSRn */
637#define TX4938_DMA_CSR_CHNEN 0x00000400
638#define TX4938_DMA_CSR_STLXFER 0x00000200
639#define TX4938_DMA_CSR_CHNACT 0x00000100
640#define TX4938_DMA_CSR_ABCHC 0x00000080
641#define TX4938_DMA_CSR_NCHNC 0x00000040
642#define TX4938_DMA_CSR_NTRNFC 0x00000020
643#define TX4938_DMA_CSR_EXTDN 0x00000010
644#define TX4938_DMA_CSR_CFERR 0x00000008
645#define TX4938_DMA_CSR_CHERR 0x00000004
646#define TX4938_DMA_CSR_DESERR 0x00000002
647#define TX4938_DMA_CSR_SORERR 0x00000001
648
649/* TX4938 Interrupt Controller (32-bit registers) */
650#define TX4938_IRC_BASE 0xf510
651#define TX4938_IRC_IRFLAG0 0xf510
652#define TX4938_IRC_IRFLAG1 0xf514
653#define TX4938_IRC_IRPOL 0xf518
654#define TX4938_IRC_IRRCNT 0xf51c
655#define TX4938_IRC_IRMASKINT 0xf520
656#define TX4938_IRC_IRMASKEXT 0xf524
657#define TX4938_IRC_IRDEN 0xf600
658#define TX4938_IRC_IRDM0 0xf604
659#define TX4938_IRC_IRDM1 0xf608
660#define TX4938_IRC_IRLVL0 0xf610
661#define TX4938_IRC_IRLVL1 0xf614
662#define TX4938_IRC_IRLVL2 0xf618
663#define TX4938_IRC_IRLVL3 0xf61c
664#define TX4938_IRC_IRLVL4 0xf620
665#define TX4938_IRC_IRLVL5 0xf624
666#define TX4938_IRC_IRLVL6 0xf628
667#define TX4938_IRC_IRLVL7 0xf62c
668#define TX4938_IRC_IRMSK 0xf640
669#define TX4938_IRC_IREDC 0xf660
670#define TX4938_IRC_IRPND 0xf680
671#define TX4938_IRC_IRCS 0xf6a0
672#define TX4938_IRC_LIMIT 0xf6ff
673
674
675#ifndef __ASSEMBLY__
676
677#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
678#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
679#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
680#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
681#define tx4938_ircptr ((struct tx4938_irc_reg *)TX4938_IRC_REG)
682#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
683#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
684#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
685#define tx4938_tmrptr(ch) ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch))
686#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
687#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG)
688#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
689#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG)
690#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
691
692
693#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff)
694#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16)
695
696#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
697#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
698
699#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
700#define TX4938_EBUSC_SIZE(ch) \
701 (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
702
703
704#endif /* !__ASSEMBLY__ */
705
706#endif
diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h
new file mode 100644
index 000000000000..cf89b205f103
--- /dev/null
+++ b/include/asm-mips/tx4938/tx4938_mips.h
@@ -0,0 +1,54 @@
1/*
2 * linux/include/asm-mips/tx4938/tx4938_bitmask.h
3 * Generic bitmask definitions
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12
13#ifndef TX4938_TX4938_MIPS_H
14#define TX4938_TX4938_MIPS_H
15#ifndef __ASSEMBLY__
16
17#define reg_rd08(r) ((u8 )(*((vu8 *)(r))))
18#define reg_rd16(r) ((u16)(*((vu16*)(r))))
19#define reg_rd32(r) ((u32)(*((vu32*)(r))))
20#define reg_rd64(r) ((u64)(*((vu64*)(r))))
21
22#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v)))
23#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v)))
24#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v)))
25#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v)))
26
27typedef volatile __signed char vs8;
28typedef volatile unsigned char vu8;
29
30typedef volatile __signed short vs16;
31typedef volatile unsigned short vu16;
32
33typedef volatile __signed int vs32;
34typedef volatile unsigned int vu32;
35
36typedef s8 s08;
37typedef vs8 vs08;
38
39typedef u8 u08;
40typedef vu8 vu08;
41
42#if (_MIPS_SZLONG == 64)
43
44typedef volatile __signed__ long vs64;
45typedef volatile unsigned long vu64;
46
47#else
48
49typedef volatile __signed__ long long vs64;
50typedef volatile unsigned long long vu64;
51
52#endif
53#endif
54#endif
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index 5c2c98329012..41bb96bb2120 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -196,63 +196,55 @@
196 __get_user_nocheck((x),(ptr),sizeof(*(ptr))) 196 __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
197 197
198struct __large_struct { unsigned long buf[100]; }; 198struct __large_struct { unsigned long buf[100]; };
199#define __m(x) (*(struct __large_struct *)(x)) 199#define __m(x) (*(struct __large_struct __user *)(x))
200 200
201/* 201/*
202 * Yuck. We need two variants, one for 64bit operation and one 202 * Yuck. We need two variants, one for 64bit operation and one
203 * for 32 bit mode and old iron. 203 * for 32 bit mode and old iron.
204 */ 204 */
205#ifdef __mips64 205#ifdef __mips64
206#define __GET_USER_DW(__gu_err) __get_user_asm("ld", __gu_err) 206#define __GET_USER_DW(ptr) __get_user_asm("ld", ptr)
207#else 207#else
208#define __GET_USER_DW(__gu_err) __get_user_asm_ll32(__gu_err) 208#define __GET_USER_DW(ptr) __get_user_asm_ll32(ptr)
209#endif 209#endif
210 210
211#define __get_user_nocheck(x,ptr,size) \ 211#define __get_user_nocheck(x,ptr,size) \
212({ \ 212({ \
213 __typeof(*(ptr)) __gu_val = 0; \ 213 __typeof(*(ptr)) __gu_val = (__typeof(*(ptr))) 0; \
214 long __gu_addr; \
215 long __gu_err = 0; \ 214 long __gu_err = 0; \
216 \ 215 \
217 might_sleep(); \
218 __gu_addr = (long) (ptr); \
219 switch (size) { \ 216 switch (size) { \
220 case 1: __get_user_asm("lb", __gu_err); break; \ 217 case 1: __get_user_asm("lb", ptr); break; \
221 case 2: __get_user_asm("lh", __gu_err); break; \ 218 case 2: __get_user_asm("lh", ptr); break; \
222 case 4: __get_user_asm("lw", __gu_err); break; \ 219 case 4: __get_user_asm("lw", ptr); break; \
223 case 8: __GET_USER_DW(__gu_err); break; \ 220 case 8: __GET_USER_DW(ptr); break; \
224 default: __get_user_unknown(); break; \ 221 default: __get_user_unknown(); break; \
225 } \ 222 } \
226 x = (__typeof__(*(ptr))) __gu_val; \ 223 (x) = (__typeof__(*(ptr))) __gu_val; \
227 __gu_err; \ 224 __gu_err; \
228}) 225})
229 226
230#define __get_user_check(x,ptr,size) \ 227#define __get_user_check(x,ptr,size) \
231({ \ 228({ \
229 const __typeof__(*(ptr)) __user * __gu_addr = (ptr); \
232 __typeof__(*(ptr)) __gu_val = 0; \ 230 __typeof__(*(ptr)) __gu_val = 0; \
233 long __gu_addr; \ 231 long __gu_err = -EFAULT; \
234 long __gu_err; \
235 \
236 might_sleep(); \
237 __gu_addr = (long) (ptr); \
238 __gu_err = access_ok(VERIFY_READ, (void *) __gu_addr, size) \
239 ? 0 : -EFAULT; \
240 \ 232 \
241 if (likely(!__gu_err)) { \ 233 if (likely(access_ok(VERIFY_READ, __gu_addr, size))) { \
242 switch (size) { \ 234 switch (size) { \
243 case 1: __get_user_asm("lb", __gu_err); break; \ 235 case 1: __get_user_asm("lb", __gu_addr); break; \
244 case 2: __get_user_asm("lh", __gu_err); break; \ 236 case 2: __get_user_asm("lh", __gu_addr); break; \
245 case 4: __get_user_asm("lw", __gu_err); break; \ 237 case 4: __get_user_asm("lw", __gu_addr); break; \
246 case 8: __GET_USER_DW(__gu_err); break; \ 238 case 8: __GET_USER_DW(__gu_addr); break; \
247 default: __get_user_unknown(); break; \ 239 default: __get_user_unknown(); break; \
248 } \ 240 } \
249 } \ 241 } \
250 x = (__typeof__(*(ptr))) __gu_val; \ 242 (x) = (__typeof__(*(ptr))) __gu_val; \
251 __gu_err; \ 243 __gu_err; \
252}) 244})
253 245
254#define __get_user_asm(insn,__gu_err) \ 246#define __get_user_asm(insn, addr) \
255({ \ 247{ \
256 __asm__ __volatile__( \ 248 __asm__ __volatile__( \
257 "1: " insn " %1, %3 \n" \ 249 "1: " insn " %1, %3 \n" \
258 "2: \n" \ 250 "2: \n" \
@@ -264,20 +256,20 @@ struct __large_struct { unsigned long buf[100]; };
264 " "__UA_ADDR "\t1b, 3b \n" \ 256 " "__UA_ADDR "\t1b, 3b \n" \
265 " .previous \n" \ 257 " .previous \n" \
266 : "=r" (__gu_err), "=r" (__gu_val) \ 258 : "=r" (__gu_err), "=r" (__gu_val) \
267 : "0" (__gu_err), "o" (__m(__gu_addr)), "i" (-EFAULT)); \ 259 : "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \
268}) 260}
269 261
270/* 262/*
271 * Get a long long 64 using 32 bit registers. 263 * Get a long long 64 using 32 bit registers.
272 */ 264 */
273#define __get_user_asm_ll32(__gu_err) \ 265#define __get_user_asm_ll32(addr) \
274({ \ 266{ \
275 __asm__ __volatile__( \ 267 __asm__ __volatile__( \
276 "1: lw %1, %3 \n" \ 268 "1: lw %1, (%3) \n" \
277 "2: lw %D1, %4 \n" \ 269 "2: lw %D1, 4(%3) \n" \
278 " move %0, $0 \n" \ 270 " move %0, $0 \n" \
279 "3: .section .fixup,\"ax\" \n" \ 271 "3: .section .fixup,\"ax\" \n" \
280 "4: li %0, %5 \n" \ 272 "4: li %0, %4 \n" \
281 " move %1, $0 \n" \ 273 " move %1, $0 \n" \
282 " move %D1, $0 \n" \ 274 " move %D1, $0 \n" \
283 " j 3b \n" \ 275 " j 3b \n" \
@@ -287,9 +279,8 @@ struct __large_struct { unsigned long buf[100]; };
287 " " __UA_ADDR " 2b, 4b \n" \ 279 " " __UA_ADDR " 2b, 4b \n" \
288 " .previous \n" \ 280 " .previous \n" \
289 : "=r" (__gu_err), "=&r" (__gu_val) \ 281 : "=r" (__gu_err), "=&r" (__gu_val) \
290 : "0" (__gu_err), "o" (__m(__gu_addr)), \ 282 : "0" (0), "r" (addr), "i" (-EFAULT)); \
291 "o" (__m(__gu_addr + 4)), "i" (-EFAULT)); \ 283}
292})
293 284
294extern void __get_user_unknown(void); 285extern void __get_user_unknown(void);
295 286
@@ -298,25 +289,22 @@ extern void __get_user_unknown(void);
298 * for 32 bit mode and old iron. 289 * for 32 bit mode and old iron.
299 */ 290 */
300#ifdef __mips64 291#ifdef __mips64
301#define __PUT_USER_DW(__pu_val) __put_user_asm("sd", __pu_val) 292#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
302#else 293#else
303#define __PUT_USER_DW(__pu_val) __put_user_asm_ll32(__pu_val) 294#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr)
304#endif 295#endif
305 296
306#define __put_user_nocheck(x,ptr,size) \ 297#define __put_user_nocheck(x,ptr,size) \
307({ \ 298({ \
308 __typeof__(*(ptr)) __pu_val; \ 299 __typeof__(*(ptr)) __pu_val; \
309 long __pu_addr; \
310 long __pu_err = 0; \ 300 long __pu_err = 0; \
311 \ 301 \
312 might_sleep(); \
313 __pu_val = (x); \ 302 __pu_val = (x); \
314 __pu_addr = (long) (ptr); \
315 switch (size) { \ 303 switch (size) { \
316 case 1: __put_user_asm("sb", __pu_val); break; \ 304 case 1: __put_user_asm("sb", ptr); break; \
317 case 2: __put_user_asm("sh", __pu_val); break; \ 305 case 2: __put_user_asm("sh", ptr); break; \
318 case 4: __put_user_asm("sw", __pu_val); break; \ 306 case 4: __put_user_asm("sw", ptr); break; \
319 case 8: __PUT_USER_DW(__pu_val); break; \ 307 case 8: __PUT_USER_DW(ptr); break; \
320 default: __put_user_unknown(); break; \ 308 default: __put_user_unknown(); break; \
321 } \ 309 } \
322 __pu_err; \ 310 __pu_err; \
@@ -324,30 +312,24 @@ extern void __get_user_unknown(void);
324 312
325#define __put_user_check(x,ptr,size) \ 313#define __put_user_check(x,ptr,size) \
326({ \ 314({ \
327 __typeof__(*(ptr)) __pu_val; \ 315 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
328 long __pu_addr; \ 316 __typeof__(*(ptr)) __pu_val = (x); \
329 long __pu_err; \ 317 long __pu_err = -EFAULT; \
330 \ 318 \
331 might_sleep(); \ 319 if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \
332 __pu_val = (x); \
333 __pu_addr = (long) (ptr); \
334 __pu_err = access_ok(VERIFY_WRITE, (void *) __pu_addr, size) \
335 ? 0 : -EFAULT; \
336 \
337 if (likely(!__pu_err)) { \
338 switch (size) { \ 320 switch (size) { \
339 case 1: __put_user_asm("sb", __pu_val); break; \ 321 case 1: __put_user_asm("sb", __pu_addr); break; \
340 case 2: __put_user_asm("sh", __pu_val); break; \ 322 case 2: __put_user_asm("sh", __pu_addr); break; \
341 case 4: __put_user_asm("sw", __pu_val); break; \ 323 case 4: __put_user_asm("sw", __pu_addr); break; \
342 case 8: __PUT_USER_DW(__pu_val); break; \ 324 case 8: __PUT_USER_DW(__pu_addr); break; \
343 default: __put_user_unknown(); break; \ 325 default: __put_user_unknown(); break; \
344 } \ 326 } \
345 } \ 327 } \
346 __pu_err; \ 328 __pu_err; \
347}) 329})
348 330
349#define __put_user_asm(insn, __pu_val) \ 331#define __put_user_asm(insn, ptr) \
350({ \ 332{ \
351 __asm__ __volatile__( \ 333 __asm__ __volatile__( \
352 "1: " insn " %z2, %3 # __put_user_asm\n" \ 334 "1: " insn " %z2, %3 # __put_user_asm\n" \
353 "2: \n" \ 335 "2: \n" \
@@ -359,18 +341,18 @@ extern void __get_user_unknown(void);
359 " " __UA_ADDR " 1b, 3b \n" \ 341 " " __UA_ADDR " 1b, 3b \n" \
360 " .previous \n" \ 342 " .previous \n" \
361 : "=r" (__pu_err) \ 343 : "=r" (__pu_err) \
362 : "0" (__pu_err), "Jr" (__pu_val), "o" (__m(__pu_addr)), \ 344 : "0" (0), "Jr" (__pu_val), "o" (__m(ptr)), \
363 "i" (-EFAULT)); \ 345 "i" (-EFAULT)); \
364}) 346}
365 347
366#define __put_user_asm_ll32(__pu_val) \ 348#define __put_user_asm_ll32(ptr) \
367({ \ 349{ \
368 __asm__ __volatile__( \ 350 __asm__ __volatile__( \
369 "1: sw %2, %3 # __put_user_asm_ll32 \n" \ 351 "1: sw %2, (%3) # __put_user_asm_ll32 \n" \
370 "2: sw %D2, %4 \n" \ 352 "2: sw %D2, 4(%3) \n" \
371 "3: \n" \ 353 "3: \n" \
372 " .section .fixup,\"ax\" \n" \ 354 " .section .fixup,\"ax\" \n" \
373 "4: li %0, %5 \n" \ 355 "4: li %0, %4 \n" \
374 " j 3b \n" \ 356 " j 3b \n" \
375 " .previous \n" \ 357 " .previous \n" \
376 " .section __ex_table,\"a\" \n" \ 358 " .section __ex_table,\"a\" \n" \
@@ -378,9 +360,9 @@ extern void __get_user_unknown(void);
378 " " __UA_ADDR " 2b, 4b \n" \ 360 " " __UA_ADDR " 2b, 4b \n" \
379 " .previous" \ 361 " .previous" \
380 : "=r" (__pu_err) \ 362 : "=r" (__pu_err) \
381 : "0" (__pu_err), "r" (__pu_val), "o" (__m(__pu_addr)), \ 363 : "0" (0), "r" (__pu_val), "r" (ptr), \
382 "o" (__m(__pu_addr + 4)), "i" (-EFAULT)); \ 364 "i" (-EFAULT)); \
383}) 365}
384 366
385extern void __put_user_unknown(void); 367extern void __put_user_unknown(void);
386 368
@@ -403,7 +385,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
403 385
404#define __invoke_copy_to_user(to,from,n) \ 386#define __invoke_copy_to_user(to,from,n) \
405({ \ 387({ \
406 register void *__cu_to_r __asm__ ("$4"); \ 388 register void __user *__cu_to_r __asm__ ("$4"); \
407 register const void *__cu_from_r __asm__ ("$5"); \ 389 register const void *__cu_from_r __asm__ ("$5"); \
408 register long __cu_len_r __asm__ ("$6"); \ 390 register long __cu_len_r __asm__ ("$6"); \
409 \ 391 \
@@ -435,7 +417,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
435 */ 417 */
436#define __copy_to_user(to,from,n) \ 418#define __copy_to_user(to,from,n) \
437({ \ 419({ \
438 void *__cu_to; \ 420 void __user *__cu_to; \
439 const void *__cu_from; \ 421 const void *__cu_from; \
440 long __cu_len; \ 422 long __cu_len; \
441 \ 423 \
@@ -465,7 +447,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
465 */ 447 */
466#define copy_to_user(to,from,n) \ 448#define copy_to_user(to,from,n) \
467({ \ 449({ \
468 void *__cu_to; \ 450 void __user *__cu_to; \
469 const void *__cu_from; \ 451 const void *__cu_from; \
470 long __cu_len; \ 452 long __cu_len; \
471 \ 453 \
@@ -482,7 +464,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
482#define __invoke_copy_from_user(to,from,n) \ 464#define __invoke_copy_from_user(to,from,n) \
483({ \ 465({ \
484 register void *__cu_to_r __asm__ ("$4"); \ 466 register void *__cu_to_r __asm__ ("$4"); \
485 register const void *__cu_from_r __asm__ ("$5"); \ 467 register const void __user *__cu_from_r __asm__ ("$5"); \
486 register long __cu_len_r __asm__ ("$6"); \ 468 register long __cu_len_r __asm__ ("$6"); \
487 \ 469 \
488 __cu_to_r = (to); \ 470 __cu_to_r = (to); \
@@ -521,7 +503,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
521#define __copy_from_user(to,from,n) \ 503#define __copy_from_user(to,from,n) \
522({ \ 504({ \
523 void *__cu_to; \ 505 void *__cu_to; \
524 const void *__cu_from; \ 506 const void __user *__cu_from; \
525 long __cu_len; \ 507 long __cu_len; \
526 \ 508 \
527 might_sleep(); \ 509 might_sleep(); \
@@ -552,7 +534,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
552#define copy_from_user(to,from,n) \ 534#define copy_from_user(to,from,n) \
553({ \ 535({ \
554 void *__cu_to; \ 536 void *__cu_to; \
555 const void *__cu_from; \ 537 const void __user *__cu_from; \
556 long __cu_len; \ 538 long __cu_len; \
557 \ 539 \
558 might_sleep(); \ 540 might_sleep(); \
@@ -569,8 +551,8 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
569 551
570#define copy_in_user(to,from,n) \ 552#define copy_in_user(to,from,n) \
571({ \ 553({ \
572 void *__cu_to; \ 554 void __user *__cu_to; \
573 const void *__cu_from; \ 555 const void __user *__cu_from; \
574 long __cu_len; \ 556 long __cu_len; \
575 \ 557 \
576 might_sleep(); \ 558 might_sleep(); \
@@ -596,7 +578,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
596 * On success, this will be zero. 578 * On success, this will be zero.
597 */ 579 */
598static inline __kernel_size_t 580static inline __kernel_size_t
599__clear_user(void *addr, __kernel_size_t size) 581__clear_user(void __user *addr, __kernel_size_t size)
600{ 582{
601 __kernel_size_t res; 583 __kernel_size_t res;
602 584
@@ -616,7 +598,7 @@ __clear_user(void *addr, __kernel_size_t size)
616 598
617#define clear_user(addr,n) \ 599#define clear_user(addr,n) \
618({ \ 600({ \
619 void * __cl_addr = (addr); \ 601 void __user * __cl_addr = (addr); \
620 unsigned long __cl_size = (n); \ 602 unsigned long __cl_size = (n); \
621 if (__cl_size && access_ok(VERIFY_WRITE, \ 603 if (__cl_size && access_ok(VERIFY_WRITE, \
622 ((unsigned long)(__cl_addr)), __cl_size)) \ 604 ((unsigned long)(__cl_addr)), __cl_size)) \
@@ -645,7 +627,7 @@ __clear_user(void *addr, __kernel_size_t size)
645 * and returns @count. 627 * and returns @count.
646 */ 628 */
647static inline long 629static inline long
648__strncpy_from_user(char *__to, const char *__from, long __len) 630__strncpy_from_user(char *__to, const char __user *__from, long __len)
649{ 631{
650 long res; 632 long res;
651 633
@@ -682,7 +664,7 @@ __strncpy_from_user(char *__to, const char *__from, long __len)
682 * and returns @count. 664 * and returns @count.
683 */ 665 */
684static inline long 666static inline long
685strncpy_from_user(char *__to, const char *__from, long __len) 667strncpy_from_user(char *__to, const char __user *__from, long __len)
686{ 668{
687 long res; 669 long res;
688 670
@@ -701,7 +683,7 @@ strncpy_from_user(char *__to, const char *__from, long __len)
701} 683}
702 684
703/* Returns: 0 if bad, string length+1 (memory size) of string if ok */ 685/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
704static inline long __strlen_user(const char *s) 686static inline long __strlen_user(const char __user *s)
705{ 687{
706 long res; 688 long res;
707 689
@@ -731,7 +713,7 @@ static inline long __strlen_user(const char *s)
731 * If there is a limit on the length of a valid string, you may wish to 713 * If there is a limit on the length of a valid string, you may wish to
732 * consider using strnlen_user() instead. 714 * consider using strnlen_user() instead.
733 */ 715 */
734static inline long strlen_user(const char *s) 716static inline long strlen_user(const char __user *s)
735{ 717{
736 long res; 718 long res;
737 719
@@ -748,7 +730,7 @@ static inline long strlen_user(const char *s)
748} 730}
749 731
750/* Returns: 0 if bad, string length+1 (memory size) of string if ok */ 732/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
751static inline long __strnlen_user(const char *s, long n) 733static inline long __strnlen_user(const char __user *s, long n)
752{ 734{
753 long res; 735 long res;
754 736
@@ -779,7 +761,7 @@ static inline long __strnlen_user(const char *s, long n)
779 * If there is a limit on the length of a valid string, you may wish to 761 * If there is a limit on the length of a valid string, you may wish to
780 * consider using strnlen_user() instead. 762 * consider using strnlen_user() instead.
781 */ 763 */
782static inline long strnlen_user(const char *s, long n) 764static inline long strnlen_user(const char __user *s, long n)
783{ 765{
784 long res; 766 long res;
785 767
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index ad4d48056307..c9eaf4c104de 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -303,16 +303,21 @@
303#define __NR_add_key (__NR_Linux + 280) 303#define __NR_add_key (__NR_Linux + 280)
304#define __NR_request_key (__NR_Linux + 281) 304#define __NR_request_key (__NR_Linux + 281)
305#define __NR_keyctl (__NR_Linux + 282) 305#define __NR_keyctl (__NR_Linux + 282)
306#define __NR_set_thread_area (__NR_Linux + 283)
307#define __NR_inotify_init (__NR_Linux + 284)
308#define __NR_inotify_add_watch (__NR_Linux + 285)
309#define __NR_inotify_rm_watch (__NR_Linux + 286)
310
306 311
307/* 312/*
308 * Offset of the last Linux o32 flavoured syscall 313 * Offset of the last Linux o32 flavoured syscall
309 */ 314 */
310#define __NR_Linux_syscalls 282 315#define __NR_Linux_syscalls 286
311 316
312#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 317#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
313 318
314#define __NR_O32_Linux 4000 319#define __NR_O32_Linux 4000
315#define __NR_O32_Linux_syscalls 282 320#define __NR_O32_Linux_syscalls 283
316 321
317#if _MIPS_SIM == _MIPS_SIM_ABI64 322#if _MIPS_SIM == _MIPS_SIM_ABI64
318 323
@@ -562,16 +567,20 @@
562#define __NR_add_key (__NR_Linux + 239) 567#define __NR_add_key (__NR_Linux + 239)
563#define __NR_request_key (__NR_Linux + 240) 568#define __NR_request_key (__NR_Linux + 240)
564#define __NR_keyctl (__NR_Linux + 241) 569#define __NR_keyctl (__NR_Linux + 241)
570#define __NR_set_thread_area (__NR_Linux + 242)
571#define __NR_inotify_init (__NR_Linux + 243)
572#define __NR_inotify_add_watch (__NR_Linux + 244)
573#define __NR_inotify_rm_watch (__NR_Linux + 245)
565 574
566/* 575/*
567 * Offset of the last Linux 64-bit flavoured syscall 576 * Offset of the last Linux 64-bit flavoured syscall
568 */ 577 */
569#define __NR_Linux_syscalls 241 578#define __NR_Linux_syscalls 245
570 579
571#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 580#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
572 581
573#define __NR_64_Linux 5000 582#define __NR_64_Linux 5000
574#define __NR_64_Linux_syscalls 241 583#define __NR_64_Linux_syscalls 242
575 584
576#if _MIPS_SIM == _MIPS_SIM_NABI32 585#if _MIPS_SIM == _MIPS_SIM_NABI32
577 586
@@ -825,16 +834,20 @@
825#define __NR_add_key (__NR_Linux + 243) 834#define __NR_add_key (__NR_Linux + 243)
826#define __NR_request_key (__NR_Linux + 244) 835#define __NR_request_key (__NR_Linux + 244)
827#define __NR_keyctl (__NR_Linux + 245) 836#define __NR_keyctl (__NR_Linux + 245)
837#define __NR_set_thread_area (__NR_Linux + 246)
838#define __NR_inotify_init (__NR_Linux + 247)
839#define __NR_inotify_add_watch (__NR_Linux + 248)
840#define __NR_inotify_rm_watch (__NR_Linux + 249)
828 841
829/* 842/*
830 * Offset of the last N32 flavoured syscall 843 * Offset of the last N32 flavoured syscall
831 */ 844 */
832#define __NR_Linux_syscalls 245 845#define __NR_Linux_syscalls 249
833 846
834#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 847#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
835 848
836#define __NR_N32_Linux 6000 849#define __NR_N32_Linux 6000
837#define __NR_N32_Linux_syscalls 245 850#define __NR_N32_Linux_syscalls 246
838 851
839#ifndef __ASSEMBLY__ 852#ifndef __ASSEMBLY__
840 853
diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h
index 6b35cf054c79..ca5cec97e167 100644
--- a/include/asm-mips/vga.h
+++ b/include/asm-mips/vga.h
@@ -6,6 +6,8 @@
6#ifndef _ASM_VGA_H 6#ifndef _ASM_VGA_H
7#define _ASM_VGA_H 7#define _ASM_VGA_H
8 8
9#include <asm/byteorder.h>
10
9/* 11/*
10 * On the PC, we can just recalculate addresses and then 12 * On the PC, we can just recalculate addresses and then
11 * access the videoram directly without any black magic. 13 * access the videoram directly without any black magic.
@@ -16,4 +18,27 @@
16#define vga_readb(x) (*(x)) 18#define vga_readb(x) (*(x))
17#define vga_writeb(x,y) (*(y) = (x)) 19#define vga_writeb(x,y) (*(y) = (x))
18 20
21#define VT_BUF_HAVE_RW
22/*
23 * These are only needed for supporting VGA or MDA text mode, which use little
24 * endian byte ordering.
25 * In other cases, we can optimize by using native byte ordering and
26 * <linux/vt_buffer.h> has already done the right job for us.
27 */
28
29static inline void scr_writew(u16 val, volatile u16 *addr)
30{
31 *addr = cpu_to_le16(val);
32}
33
34static inline u16 scr_readw(volatile const u16 *addr)
35{
36 return le16_to_cpu(*addr);
37}
38
39#define scr_memcpyw(d, s, c) memcpy(d, s, c)
40#define scr_memmovew(d, s, c) memmove(d, s, c)
41#define VT_BUF_HAVE_MEMCPYW
42#define VT_BUF_HAVE_MEMMOVEW
43
19#endif /* _ASM_VGA_H */ 44#endif /* _ASM_VGA_H */
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index 04ee53b34c2e..ad374bd3f130 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -177,6 +177,17 @@
177#endif 177#endif
178 178
179/* 179/*
180 * The RM9000 has a bug (though PMC-Sierra opposes it being called that)
181 * where invalid instructions in the same I-cache line worth of instructions
182 * being fetched may case spurious exceptions.
183 */
184#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
185 defined(CONFIG_PMC_YOSEMITE)
186#define ICACHE_REFILLS_WORKAROUND_WAR 1
187#endif
188
189
190/*
180 * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that 191 * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
181 * may cause ll / sc and lld / scd sequences to execute non-atomically. 192 * may cause ll / sc and lld / scd sequences to execute non-atomically.
182 */ 193 */
@@ -187,6 +198,9 @@
187/* 198/*
188 * Workarounds default to off 199 * Workarounds default to off
189 */ 200 */
201#ifndef ICACHE_REFILLS_WORKAROUND_WAR
202#define ICACHE_REFILLS_WORKAROUND_WAR 0
203#endif
190#ifndef R4600_V1_INDEX_ICACHEOP_WAR 204#ifndef R4600_V1_INDEX_ICACHEOP_WAR
191#define R4600_V1_INDEX_ICACHEOP_WAR 0 205#define R4600_V1_INDEX_ICACHEOP_WAR 0
192#endif 206#endif
diff --git a/include/linux/ide.h b/include/linux/ide.h
index a6dbb51ecd7b..3461abc1e854 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -218,7 +218,7 @@ typedef enum { ide_unknown, ide_generic, ide_pci,
218 ide_rz1000, ide_trm290, 218 ide_rz1000, ide_trm290,
219 ide_cmd646, ide_cy82c693, ide_4drives, 219 ide_cmd646, ide_cy82c693, ide_4drives,
220 ide_pmac, ide_etrax100, ide_acorn, 220 ide_pmac, ide_etrax100, ide_acorn,
221 ide_forced 221 ide_au1xxx, ide_forced
222} hwif_chipset_t; 222} hwif_chipset_t;
223 223
224/* 224/*
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 27db8da43aa4..2b0401b93f2b 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -39,7 +39,8 @@
39#define PORT_RSA 13 39#define PORT_RSA 13
40#define PORT_NS16550A 14 40#define PORT_NS16550A 14
41#define PORT_XSCALE 15 41#define PORT_XSCALE 15
42#define PORT_MAX_8250 15 /* max port ID */ 42#define PORT_IP3106 16
43#define PORT_MAX_8250 16 /* max port ID */
43 44
44/* 45/*
45 * ARM specific type numbers. These are not currently guaranteed 46 * ARM specific type numbers. These are not currently guaranteed
diff --git a/include/linux/serial_ip3106.h b/include/linux/serial_ip3106.h
new file mode 100644
index 000000000000..f500ac602c5c
--- /dev/null
+++ b/include/linux/serial_ip3106.h
@@ -0,0 +1,81 @@
1/*
2 * Embedded Alley Solutions, source@embeddedalley.com.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef _LINUX_SERIAL_IP3106_H
20#define _LINUX_SERIAL_IP3106_H
21
22#include <linux/serial_core.h>
23#include <linux/device.h>
24
25#define IP3106_NR_PORTS 2
26
27struct ip3106_port {
28 struct uart_port port;
29 struct timer_list timer;
30 unsigned int old_status;
31};
32
33/* register offsets */
34#define IP3106_LCR 0
35#define IP3106_MCR 0x004
36#define IP3106_BAUD 0x008
37#define IP3106_CFG 0x00c
38#define IP3106_FIFO 0x028
39#define IP3106_ISTAT 0xfe0
40#define IP3106_IEN 0xfe4
41#define IP3106_ICLR 0xfe8
42#define IP3106_ISET 0xfec
43#define IP3106_PD 0xff4
44#define IP3106_MID 0xffc
45
46#define IP3106_UART_LCR_TXBREAK (1<<30)
47#define IP3106_UART_LCR_PAREVN 0x10000000
48#define IP3106_UART_LCR_PAREN 0x08000000
49#define IP3106_UART_LCR_2STOPB 0x04000000
50#define IP3106_UART_LCR_8BIT 0x01000000
51#define IP3106_UART_LCR_TX_RST 0x00040000
52#define IP3106_UART_LCR_RX_RST 0x00020000
53#define IP3106_UART_LCR_RX_NEXT 0x00010000
54
55#define IP3106_UART_MCR_SCR 0xFF000000
56#define IP3106_UART_MCR_DCD 0x00800000
57#define IP3106_UART_MCR_CTS 0x00100000
58#define IP3106_UART_MCR_LOOP 0x00000010
59#define IP3106_UART_MCR_RTS 0x00000002
60#define IP3106_UART_MCR_DTR 0x00000001
61
62#define IP3106_UART_INT_TX 0x00000080
63#define IP3106_UART_INT_EMPTY 0x00000040
64#define IP3106_UART_INT_RCVTO 0x00000020
65#define IP3106_UART_INT_RX 0x00000010
66#define IP3106_UART_INT_RXOVRN 0x00000008
67#define IP3106_UART_INT_FRERR 0x00000004
68#define IP3106_UART_INT_BREAK 0x00000002
69#define IP3106_UART_INT_PARITY 0x00000001
70#define IP3106_UART_INT_ALLRX 0x0000003F
71#define IP3106_UART_INT_ALLTX 0x000000C0
72
73#define IP3106_UART_FIFO_TXFIFO 0x001F0000
74#define IP3106_UART_FIFO_TXFIFO_STA (0x1f<<16)
75#define IP3106_UART_FIFO_RXBRK 0x00008000
76#define IP3106_UART_FIFO_RXFE 0x00004000
77#define IP3106_UART_FIFO_RXPAR 0x00002000
78#define IP3106_UART_FIFO_RXFIFO 0x00001F00
79#define IP3106_UART_FIFO_RBRTHR 0x000000FF
80
81#endif
diff --git a/sound/oss/au1550_ac97.c b/sound/oss/au1550_ac97.c
index a78e48d412d2..6b46a8a4b1cc 100644
--- a/sound/oss/au1550_ac97.c
+++ b/sound/oss/au1550_ac97.c
@@ -35,7 +35,6 @@
35 35
36#undef DEBUG 36#undef DEBUG
37 37
38#include <linux/version.h>
39#include <linux/module.h> 38#include <linux/module.h>
40#include <linux/string.h> 39#include <linux/string.h>
41#include <linux/ioport.h> 40#include <linux/ioport.h>
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-06 05:34:45 -0400