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-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c433
-rw-r--r--arch/arm/plat-omap/include/plat/l3_3xxx.h20
-rw-r--r--arch/arm/plat-omap/include/plat/l4_3xxx.h10
3 files changed, 463 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 879f55f272e2..e9d001228568 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -18,6 +18,7 @@
18#include <plat/cpu.h> 18#include <plat/cpu.h>
19#include <plat/dma.h> 19#include <plat/dma.h>
20#include <plat/serial.h> 20#include <plat/serial.h>
21#include <plat/l3_3xxx.h>
21#include <plat/l4_3xxx.h> 22#include <plat/l4_3xxx.h>
22#include <plat/i2c.h> 23#include <plat/i2c.h>
23#include <plat/gpio.h> 24#include <plat/gpio.h>
@@ -46,6 +47,12 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod;
46static struct omap_hwmod omap3xxx_l4_core_hwmod; 47static struct omap_hwmod omap3xxx_l4_core_hwmod;
47static struct omap_hwmod omap3xxx_l4_per_hwmod; 48static struct omap_hwmod omap3xxx_l4_per_hwmod;
48static struct omap_hwmod omap3xxx_wd_timer2_hwmod; 49static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
50static struct omap_hwmod omap3430es1_dss_core_hwmod;
51static struct omap_hwmod omap3xxx_dss_core_hwmod;
52static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
53static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
54static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
55static struct omap_hwmod omap3xxx_dss_venc_hwmod;
49static struct omap_hwmod omap3xxx_i2c1_hwmod; 56static struct omap_hwmod omap3xxx_i2c1_hwmod;
50static struct omap_hwmod omap3xxx_i2c2_hwmod; 57static struct omap_hwmod omap3xxx_i2c2_hwmod;
51static struct omap_hwmod omap3xxx_i2c3_hwmod; 58static struct omap_hwmod omap3xxx_i2c3_hwmod;
@@ -91,6 +98,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
91 &omap3xxx_mpu__l3_main, 98 &omap3xxx_mpu__l3_main,
92}; 99};
93 100
101/* DSS -> l3 */
102static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
103 .master = &omap3xxx_dss_core_hwmod,
104 .slave = &omap3xxx_l3_main_hwmod,
105 .fw = {
106 .omap2 = {
107 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
108 .flags = OMAP_FIREWALL_L3,
109 }
110 },
111 .user = OCP_USER_MPU | OCP_USER_SDMA,
112};
113
94/* Master interfaces on the L3 interconnect */ 114/* Master interfaces on the L3 interconnect */
95static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { 115static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
96 &omap3xxx_l3_main__l4_core, 116 &omap3xxx_l3_main__l4_core,
@@ -742,6 +762,410 @@ static struct omap_hwmod_class i2c_class = {
742 .sysc = &i2c_sysc, 762 .sysc = &i2c_sysc,
743}; 763};
744 764
765/*
766 * 'dss' class
767 * display sub-system
768 */
769
770static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
771 .rev_offs = 0x0000,
772 .sysc_offs = 0x0010,
773 .syss_offs = 0x0014,
774 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
775 .sysc_fields = &omap_hwmod_sysc_type1,
776};
777
778static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
779 .name = "dss",
780 .sysc = &omap3xxx_dss_sysc,
781};
782
783/* dss */
784static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
785 { .irq = 25 },
786};
787
788static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
789 { .name = "dispc", .dma_req = 5 },
790 { .name = "dsi1", .dma_req = 74 },
791};
792
793/* dss */
794/* dss master ports */
795static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
796 &omap3xxx_dss__l3,
797};
798
799static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
800 {
801 .pa_start = 0x48050000,
802 .pa_end = 0x480503FF,
803 .flags = ADDR_TYPE_RT
804 },
805};
806
807/* l4_core -> dss */
808static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
809 .master = &omap3xxx_l4_core_hwmod,
810 .slave = &omap3430es1_dss_core_hwmod,
811 .clk = "dss_ick",
812 .addr = omap3xxx_dss_addrs,
813 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
814 .fw = {
815 .omap2 = {
816 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
817 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
818 .flags = OMAP_FIREWALL_L4,
819 }
820 },
821 .user = OCP_USER_MPU | OCP_USER_SDMA,
822};
823
824static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
825 .master = &omap3xxx_l4_core_hwmod,
826 .slave = &omap3xxx_dss_core_hwmod,
827 .clk = "dss_ick",
828 .addr = omap3xxx_dss_addrs,
829 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
830 .fw = {
831 .omap2 = {
832 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
833 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
834 .flags = OMAP_FIREWALL_L4,
835 }
836 },
837 .user = OCP_USER_MPU | OCP_USER_SDMA,
838};
839
840/* dss slave ports */
841static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
842 &omap3430es1_l4_core__dss,
843};
844
845static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
846 &omap3xxx_l4_core__dss,
847};
848
849static struct omap_hwmod_opt_clk dss_opt_clks[] = {
850 { .role = "tv_clk", .clk = "dss_tv_fck" },
851 { .role = "dssclk", .clk = "dss_96m_fck" },
852 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
853};
854
855static struct omap_hwmod omap3430es1_dss_core_hwmod = {
856 .name = "dss_core",
857 .class = &omap3xxx_dss_hwmod_class,
858 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
859 .mpu_irqs = omap3xxx_dss_irqs,
860 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
861 .sdma_reqs = omap3xxx_dss_sdma_chs,
862 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
863
864 .prcm = {
865 .omap2 = {
866 .prcm_reg_id = 1,
867 .module_bit = OMAP3430_EN_DSS1_SHIFT,
868 .module_offs = OMAP3430_DSS_MOD,
869 .idlest_reg_id = 1,
870 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
871 },
872 },
873 .opt_clks = dss_opt_clks,
874 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
875 .slaves = omap3430es1_dss_slaves,
876 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
877 .masters = omap3xxx_dss_masters,
878 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
879 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
880 .flags = HWMOD_NO_IDLEST,
881};
882
883static struct omap_hwmod omap3xxx_dss_core_hwmod = {
884 .name = "dss_core",
885 .class = &omap3xxx_dss_hwmod_class,
886 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
887 .mpu_irqs = omap3xxx_dss_irqs,
888 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
889 .sdma_reqs = omap3xxx_dss_sdma_chs,
890 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
891
892 .prcm = {
893 .omap2 = {
894 .prcm_reg_id = 1,
895 .module_bit = OMAP3430_EN_DSS1_SHIFT,
896 .module_offs = OMAP3430_DSS_MOD,
897 .idlest_reg_id = 1,
898 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
899 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
900 },
901 },
902 .opt_clks = dss_opt_clks,
903 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
904 .slaves = omap3xxx_dss_slaves,
905 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
906 .masters = omap3xxx_dss_masters,
907 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
908 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
909 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
910};
911
912/*
913 * 'dispc' class
914 * display controller
915 */
916
917static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
918 .rev_offs = 0x0000,
919 .sysc_offs = 0x0010,
920 .syss_offs = 0x0014,
921 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
922 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
923 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
924 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
925 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
926 .sysc_fields = &omap_hwmod_sysc_type1,
927};
928
929static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
930 .name = "dispc",
931 .sysc = &omap3xxx_dispc_sysc,
932};
933
934static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
935 {
936 .pa_start = 0x48050400,
937 .pa_end = 0x480507FF,
938 .flags = ADDR_TYPE_RT
939 },
940};
941
942/* l4_core -> dss_dispc */
943static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
944 .master = &omap3xxx_l4_core_hwmod,
945 .slave = &omap3xxx_dss_dispc_hwmod,
946 .clk = "dss_ick",
947 .addr = omap3xxx_dss_dispc_addrs,
948 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
949 .fw = {
950 .omap2 = {
951 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
952 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
953 .flags = OMAP_FIREWALL_L4,
954 }
955 },
956 .user = OCP_USER_MPU | OCP_USER_SDMA,
957};
958
959/* dss_dispc slave ports */
960static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
961 &omap3xxx_l4_core__dss_dispc,
962};
963
964static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
965 .name = "dss_dispc",
966 .class = &omap3xxx_dispc_hwmod_class,
967 .main_clk = "dss1_alwon_fck",
968 .prcm = {
969 .omap2 = {
970 .prcm_reg_id = 1,
971 .module_bit = OMAP3430_EN_DSS1_SHIFT,
972 .module_offs = OMAP3430_DSS_MOD,
973 },
974 },
975 .slaves = omap3xxx_dss_dispc_slaves,
976 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
977 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
978 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
979 CHIP_GE_OMAP3630ES1_1),
980 .flags = HWMOD_NO_IDLEST,
981};
982
983/*
984 * 'dsi' class
985 * display serial interface controller
986 */
987
988static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
989 .name = "dsi",
990};
991
992/* dss_dsi1 */
993static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
994 {
995 .pa_start = 0x4804FC00,
996 .pa_end = 0x4804FFFF,
997 .flags = ADDR_TYPE_RT
998 },
999};
1000
1001/* l4_core -> dss_dsi1 */
1002static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1003 .master = &omap3xxx_l4_core_hwmod,
1004 .slave = &omap3xxx_dss_dsi1_hwmod,
1005 .addr = omap3xxx_dss_dsi1_addrs,
1006 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1007 .fw = {
1008 .omap2 = {
1009 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1010 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1011 .flags = OMAP_FIREWALL_L4,
1012 }
1013 },
1014 .user = OCP_USER_MPU | OCP_USER_SDMA,
1015};
1016
1017/* dss_dsi1 slave ports */
1018static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1019 &omap3xxx_l4_core__dss_dsi1,
1020};
1021
1022static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1023 .name = "dss_dsi1",
1024 .class = &omap3xxx_dsi_hwmod_class,
1025 .main_clk = "dss1_alwon_fck",
1026 .prcm = {
1027 .omap2 = {
1028 .prcm_reg_id = 1,
1029 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1030 .module_offs = OMAP3430_DSS_MOD,
1031 },
1032 },
1033 .slaves = omap3xxx_dss_dsi1_slaves,
1034 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1035 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1036 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1037 CHIP_GE_OMAP3630ES1_1),
1038 .flags = HWMOD_NO_IDLEST,
1039};
1040
1041/*
1042 * 'rfbi' class
1043 * remote frame buffer interface
1044 */
1045
1046static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1047 .rev_offs = 0x0000,
1048 .sysc_offs = 0x0010,
1049 .syss_offs = 0x0014,
1050 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1051 SYSC_HAS_AUTOIDLE),
1052 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1053 .sysc_fields = &omap_hwmod_sysc_type1,
1054};
1055
1056static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1057 .name = "rfbi",
1058 .sysc = &omap3xxx_rfbi_sysc,
1059};
1060
1061static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1062 {
1063 .pa_start = 0x48050800,
1064 .pa_end = 0x48050BFF,
1065 .flags = ADDR_TYPE_RT
1066 },
1067};
1068
1069/* l4_core -> dss_rfbi */
1070static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1071 .master = &omap3xxx_l4_core_hwmod,
1072 .slave = &omap3xxx_dss_rfbi_hwmod,
1073 .clk = "dss_ick",
1074 .addr = omap3xxx_dss_rfbi_addrs,
1075 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1076 .fw = {
1077 .omap2 = {
1078 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1079 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1080 .flags = OMAP_FIREWALL_L4,
1081 }
1082 },
1083 .user = OCP_USER_MPU | OCP_USER_SDMA,
1084};
1085
1086/* dss_rfbi slave ports */
1087static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1088 &omap3xxx_l4_core__dss_rfbi,
1089};
1090
1091static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1092 .name = "dss_rfbi",
1093 .class = &omap3xxx_rfbi_hwmod_class,
1094 .main_clk = "dss1_alwon_fck",
1095 .prcm = {
1096 .omap2 = {
1097 .prcm_reg_id = 1,
1098 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1099 .module_offs = OMAP3430_DSS_MOD,
1100 },
1101 },
1102 .slaves = omap3xxx_dss_rfbi_slaves,
1103 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1104 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1105 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1106 CHIP_GE_OMAP3630ES1_1),
1107 .flags = HWMOD_NO_IDLEST,
1108};
1109
1110/*
1111 * 'venc' class
1112 * video encoder
1113 */
1114
1115static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1116 .name = "venc",
1117};
1118
1119/* dss_venc */
1120static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1121 {
1122 .pa_start = 0x48050C00,
1123 .pa_end = 0x48050FFF,
1124 .flags = ADDR_TYPE_RT
1125 },
1126};
1127
1128/* l4_core -> dss_venc */
1129static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1130 .master = &omap3xxx_l4_core_hwmod,
1131 .slave = &omap3xxx_dss_venc_hwmod,
1132 .clk = "dss_tv_fck",
1133 .addr = omap3xxx_dss_venc_addrs,
1134 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1135 .fw = {
1136 .omap2 = {
1137 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1138 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1139 .flags = OMAP_FIREWALL_L4,
1140 }
1141 },
1142 .user = OCP_USER_MPU | OCP_USER_SDMA,
1143};
1144
1145/* dss_venc slave ports */
1146static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1147 &omap3xxx_l4_core__dss_venc,
1148};
1149
1150static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1151 .name = "dss_venc",
1152 .class = &omap3xxx_venc_hwmod_class,
1153 .main_clk = "dss1_alwon_fck",
1154 .prcm = {
1155 .omap2 = {
1156 .prcm_reg_id = 1,
1157 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1158 .module_offs = OMAP3430_DSS_MOD,
1159 },
1160 },
1161 .slaves = omap3xxx_dss_venc_slaves,
1162 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1163 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1164 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1165 CHIP_GE_OMAP3630ES1_1),
1166 .flags = HWMOD_NO_IDLEST,
1167};
1168
745/* I2C1 */ 1169/* I2C1 */
746 1170
747static struct omap_i2c_dev_attr i2c1_dev_attr = { 1171static struct omap_i2c_dev_attr i2c1_dev_attr = {
@@ -1800,6 +2224,15 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
1800 &omap3xxx_uart2_hwmod, 2224 &omap3xxx_uart2_hwmod,
1801 &omap3xxx_uart3_hwmod, 2225 &omap3xxx_uart3_hwmod,
1802 &omap3xxx_uart4_hwmod, 2226 &omap3xxx_uart4_hwmod,
2227 /* dss class */
2228 &omap3430es1_dss_core_hwmod,
2229 &omap3xxx_dss_core_hwmod,
2230 &omap3xxx_dss_dispc_hwmod,
2231 &omap3xxx_dss_dsi1_hwmod,
2232 &omap3xxx_dss_rfbi_hwmod,
2233 &omap3xxx_dss_venc_hwmod,
2234
2235 /* i2c class */
1803 &omap3xxx_i2c1_hwmod, 2236 &omap3xxx_i2c1_hwmod,
1804 &omap3xxx_i2c2_hwmod, 2237 &omap3xxx_i2c2_hwmod,
1805 &omap3xxx_i2c3_hwmod, 2238 &omap3xxx_i2c3_hwmod,
diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/plat-omap/include/plat/l3_3xxx.h
new file mode 100644
index 000000000000..cde1938c5f82
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l3_3xxx.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Sumit Semwal
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
14#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
15
16/* L3 Initiator IDs */
17/* Display Sub system (DSS) */
18#define OMAP3_L3_CORE_FW_INIT_ID_DSS 29
19
20#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h
index 5e1949375422..881a858b1ffc 100644
--- a/arch/arm/plat-omap/include/plat/l4_3xxx.h
+++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h
@@ -21,4 +21,14 @@
21#define OMAP3_L4_CORE_FW_I2C3_REGION 73 21#define OMAP3_L4_CORE_FW_I2C3_REGION 73
22#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74 22#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74
23 23
24/* Display Sub system (DSS) */
25#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP 2
26
27#define OMAP3_L4_CORE_FW_DSS_DSI_REGION 104
28#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION 3
29#define OMAP3_L4_CORE_FW_DSS_CORE_REGION 4
30#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION 4
31#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION 5
32#define OMAP3_L4_CORE_FW_DSS_VENC_REGION 6
33#define OMAP3_L4_CORE_FW_DSS_TA_REGION 7
24#endif 34#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-01 13:26:33 -0400