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-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c612
1 files changed, 604 insertions, 8 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 37b30246a063..aafe60dc711a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Hardware modules present on the OMAP44xx chips 2 * Hardware modules present on the OMAP44xx chips
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley 7 * Paul Walmsley
@@ -43,6 +43,7 @@
43static struct omap_hwmod omap44xx_dma_system_hwmod; 43static struct omap_hwmod omap44xx_dma_system_hwmod;
44static struct omap_hwmod omap44xx_dmm_hwmod; 44static struct omap_hwmod omap44xx_dmm_hwmod;
45static struct omap_hwmod omap44xx_dsp_hwmod; 45static struct omap_hwmod omap44xx_dsp_hwmod;
46static struct omap_hwmod omap44xx_dss_hwmod;
46static struct omap_hwmod omap44xx_emif_fw_hwmod; 47static struct omap_hwmod omap44xx_emif_fw_hwmod;
47static struct omap_hwmod omap44xx_iva_hwmod; 48static struct omap_hwmod omap44xx_iva_hwmod;
48static struct omap_hwmod omap44xx_l3_instr_hwmod; 49static struct omap_hwmod omap44xx_l3_instr_hwmod;
@@ -213,6 +214,14 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
213 .user = OCP_USER_MPU | OCP_USER_SDMA, 214 .user = OCP_USER_MPU | OCP_USER_SDMA,
214}; 215};
215 216
217/* dss -> l3_main_1 */
218static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
219 .master = &omap44xx_dss_hwmod,
220 .slave = &omap44xx_l3_main_1_hwmod,
221 .clk = "l3_div_ck",
222 .user = OCP_USER_MPU | OCP_USER_SDMA,
223};
224
216/* l3_main_2 -> l3_main_1 */ 225/* l3_main_2 -> l3_main_1 */
217static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { 226static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
218 .master = &omap44xx_l3_main_2_hwmod, 227 .master = &omap44xx_l3_main_2_hwmod,
@@ -240,6 +249,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
240/* l3_main_1 slave ports */ 249/* l3_main_1 slave ports */
241static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { 250static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
242 &omap44xx_dsp__l3_main_1, 251 &omap44xx_dsp__l3_main_1,
252 &omap44xx_dss__l3_main_1,
243 &omap44xx_l3_main_2__l3_main_1, 253 &omap44xx_l3_main_2__l3_main_1,
244 &omap44xx_l4_cfg__l3_main_1, 254 &omap44xx_l4_cfg__l3_main_1,
245 &omap44xx_mpu__l3_main_1, 255 &omap44xx_mpu__l3_main_1,
@@ -507,13 +517,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
507 * ctrl_module_wkup 517 * ctrl_module_wkup
508 * debugss 518 * debugss
509 * dmic 519 * dmic
510 * dss
511 * dss_dispc
512 * dss_dsi1
513 * dss_dsi2
514 * dss_hdmi
515 * dss_rfbi
516 * dss_venc
517 * efuse_ctrl_cust 520 * efuse_ctrl_cust
518 * efuse_ctrl_std 521 * efuse_ctrl_std
519 * elm 522 * elm
@@ -731,6 +734,590 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
731}; 734};
732 735
733/* 736/*
737 * 'dss' class
738 * display sub-system
739 */
740
741static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
742 .rev_offs = 0x0000,
743 .syss_offs = 0x0014,
744 .sysc_flags = SYSS_HAS_RESET_STATUS,
745};
746
747static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
748 .name = "dss",
749 .sysc = &omap44xx_dss_sysc,
750};
751
752/* dss */
753/* dss master ports */
754static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
755 &omap44xx_dss__l3_main_1,
756};
757
758static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
759 {
760 .pa_start = 0x58000000,
761 .pa_end = 0x5800007f,
762 .flags = ADDR_TYPE_RT
763 },
764};
765
766/* l3_main_2 -> dss */
767static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
768 .master = &omap44xx_l3_main_2_hwmod,
769 .slave = &omap44xx_dss_hwmod,
770 .clk = "l3_div_ck",
771 .addr = omap44xx_dss_dma_addrs,
772 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
773 .user = OCP_USER_SDMA,
774};
775
776static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
777 {
778 .pa_start = 0x48040000,
779 .pa_end = 0x4804007f,
780 .flags = ADDR_TYPE_RT
781 },
782};
783
784/* l4_per -> dss */
785static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
786 .master = &omap44xx_l4_per_hwmod,
787 .slave = &omap44xx_dss_hwmod,
788 .clk = "l4_div_ck",
789 .addr = omap44xx_dss_addrs,
790 .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
791 .user = OCP_USER_MPU,
792};
793
794/* dss slave ports */
795static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
796 &omap44xx_l3_main_2__dss,
797 &omap44xx_l4_per__dss,
798};
799
800static struct omap_hwmod_opt_clk dss_opt_clks[] = {
801 { .role = "sys_clk", .clk = "dss_sys_clk" },
802 { .role = "tv_clk", .clk = "dss_tv_clk" },
803 { .role = "dss_clk", .clk = "dss_dss_clk" },
804 { .role = "video_clk", .clk = "dss_48mhz_clk" },
805};
806
807static struct omap_hwmod omap44xx_dss_hwmod = {
808 .name = "dss_core",
809 .class = &omap44xx_dss_hwmod_class,
810 .main_clk = "dss_fck",
811 .prcm = {
812 .omap4 = {
813 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
814 },
815 },
816 .opt_clks = dss_opt_clks,
817 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
818 .slaves = omap44xx_dss_slaves,
819 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
820 .masters = omap44xx_dss_masters,
821 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
822 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
823};
824
825/*
826 * 'dispc' class
827 * display controller
828 */
829
830static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
831 .rev_offs = 0x0000,
832 .sysc_offs = 0x0010,
833 .syss_offs = 0x0014,
834 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
835 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
836 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
837 SYSS_HAS_RESET_STATUS),
838 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
839 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
840 .sysc_fields = &omap_hwmod_sysc_type1,
841};
842
843static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
844 .name = "dispc",
845 .sysc = &omap44xx_dispc_sysc,
846};
847
848/* dss_dispc */
849static struct omap_hwmod omap44xx_dss_dispc_hwmod;
850static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
851 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
852};
853
854static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
855 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
856};
857
858static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
859 {
860 .pa_start = 0x58001000,
861 .pa_end = 0x58001fff,
862 .flags = ADDR_TYPE_RT
863 },
864};
865
866/* l3_main_2 -> dss_dispc */
867static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
868 .master = &omap44xx_l3_main_2_hwmod,
869 .slave = &omap44xx_dss_dispc_hwmod,
870 .clk = "l3_div_ck",
871 .addr = omap44xx_dss_dispc_dma_addrs,
872 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
873 .user = OCP_USER_SDMA,
874};
875
876static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
877 {
878 .pa_start = 0x48041000,
879 .pa_end = 0x48041fff,
880 .flags = ADDR_TYPE_RT
881 },
882};
883
884/* l4_per -> dss_dispc */
885static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
886 .master = &omap44xx_l4_per_hwmod,
887 .slave = &omap44xx_dss_dispc_hwmod,
888 .clk = "l4_div_ck",
889 .addr = omap44xx_dss_dispc_addrs,
890 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
891 .user = OCP_USER_MPU,
892};
893
894/* dss_dispc slave ports */
895static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
896 &omap44xx_l3_main_2__dss_dispc,
897 &omap44xx_l4_per__dss_dispc,
898};
899
900static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
901 .name = "dss_dispc",
902 .class = &omap44xx_dispc_hwmod_class,
903 .mpu_irqs = omap44xx_dss_dispc_irqs,
904 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
905 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
906 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
907 .main_clk = "dss_fck",
908 .prcm = {
909 .omap4 = {
910 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
911 },
912 },
913 .slaves = omap44xx_dss_dispc_slaves,
914 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
915 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
916};
917
918/*
919 * 'dsi' class
920 * display serial interface controller
921 */
922
923static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
924 .rev_offs = 0x0000,
925 .sysc_offs = 0x0010,
926 .syss_offs = 0x0014,
927 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
928 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
929 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
930 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
931 .sysc_fields = &omap_hwmod_sysc_type1,
932};
933
934static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
935 .name = "dsi",
936 .sysc = &omap44xx_dsi_sysc,
937};
938
939/* dss_dsi1 */
940static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
941static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
942 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
943};
944
945static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
946 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
947};
948
949static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
950 {
951 .pa_start = 0x58004000,
952 .pa_end = 0x580041ff,
953 .flags = ADDR_TYPE_RT
954 },
955};
956
957/* l3_main_2 -> dss_dsi1 */
958static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
959 .master = &omap44xx_l3_main_2_hwmod,
960 .slave = &omap44xx_dss_dsi1_hwmod,
961 .clk = "l3_div_ck",
962 .addr = omap44xx_dss_dsi1_dma_addrs,
963 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
964 .user = OCP_USER_SDMA,
965};
966
967static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
968 {
969 .pa_start = 0x48044000,
970 .pa_end = 0x480441ff,
971 .flags = ADDR_TYPE_RT
972 },
973};
974
975/* l4_per -> dss_dsi1 */
976static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
977 .master = &omap44xx_l4_per_hwmod,
978 .slave = &omap44xx_dss_dsi1_hwmod,
979 .clk = "l4_div_ck",
980 .addr = omap44xx_dss_dsi1_addrs,
981 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
982 .user = OCP_USER_MPU,
983};
984
985/* dss_dsi1 slave ports */
986static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
987 &omap44xx_l3_main_2__dss_dsi1,
988 &omap44xx_l4_per__dss_dsi1,
989};
990
991static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
992 .name = "dss_dsi1",
993 .class = &omap44xx_dsi_hwmod_class,
994 .mpu_irqs = omap44xx_dss_dsi1_irqs,
995 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
996 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
997 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
998 .main_clk = "dss_fck",
999 .prcm = {
1000 .omap4 = {
1001 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1002 },
1003 },
1004 .slaves = omap44xx_dss_dsi1_slaves,
1005 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1006 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1007};
1008
1009/* dss_dsi2 */
1010static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1011static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1012 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1013};
1014
1015static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1016 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1017};
1018
1019static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1020 {
1021 .pa_start = 0x58005000,
1022 .pa_end = 0x580051ff,
1023 .flags = ADDR_TYPE_RT
1024 },
1025};
1026
1027/* l3_main_2 -> dss_dsi2 */
1028static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1029 .master = &omap44xx_l3_main_2_hwmod,
1030 .slave = &omap44xx_dss_dsi2_hwmod,
1031 .clk = "l3_div_ck",
1032 .addr = omap44xx_dss_dsi2_dma_addrs,
1033 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1034 .user = OCP_USER_SDMA,
1035};
1036
1037static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1038 {
1039 .pa_start = 0x48045000,
1040 .pa_end = 0x480451ff,
1041 .flags = ADDR_TYPE_RT
1042 },
1043};
1044
1045/* l4_per -> dss_dsi2 */
1046static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1047 .master = &omap44xx_l4_per_hwmod,
1048 .slave = &omap44xx_dss_dsi2_hwmod,
1049 .clk = "l4_div_ck",
1050 .addr = omap44xx_dss_dsi2_addrs,
1051 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1052 .user = OCP_USER_MPU,
1053};
1054
1055/* dss_dsi2 slave ports */
1056static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1057 &omap44xx_l3_main_2__dss_dsi2,
1058 &omap44xx_l4_per__dss_dsi2,
1059};
1060
1061static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1062 .name = "dss_dsi2",
1063 .class = &omap44xx_dsi_hwmod_class,
1064 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1065 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1066 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1067 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1068 .main_clk = "dss_fck",
1069 .prcm = {
1070 .omap4 = {
1071 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1072 },
1073 },
1074 .slaves = omap44xx_dss_dsi2_slaves,
1075 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1076 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1077};
1078
1079/*
1080 * 'hdmi' class
1081 * hdmi controller
1082 */
1083
1084static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1085 .rev_offs = 0x0000,
1086 .sysc_offs = 0x0010,
1087 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1088 SYSC_HAS_SOFTRESET),
1089 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1090 SIDLE_SMART_WKUP),
1091 .sysc_fields = &omap_hwmod_sysc_type2,
1092};
1093
1094static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1095 .name = "hdmi",
1096 .sysc = &omap44xx_hdmi_sysc,
1097};
1098
1099/* dss_hdmi */
1100static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1101static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1102 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1103};
1104
1105static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1106 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1107};
1108
1109static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1110 {
1111 .pa_start = 0x58006000,
1112 .pa_end = 0x58006fff,
1113 .flags = ADDR_TYPE_RT
1114 },
1115};
1116
1117/* l3_main_2 -> dss_hdmi */
1118static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1119 .master = &omap44xx_l3_main_2_hwmod,
1120 .slave = &omap44xx_dss_hdmi_hwmod,
1121 .clk = "l3_div_ck",
1122 .addr = omap44xx_dss_hdmi_dma_addrs,
1123 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1124 .user = OCP_USER_SDMA,
1125};
1126
1127static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1128 {
1129 .pa_start = 0x48046000,
1130 .pa_end = 0x48046fff,
1131 .flags = ADDR_TYPE_RT
1132 },
1133};
1134
1135/* l4_per -> dss_hdmi */
1136static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1137 .master = &omap44xx_l4_per_hwmod,
1138 .slave = &omap44xx_dss_hdmi_hwmod,
1139 .clk = "l4_div_ck",
1140 .addr = omap44xx_dss_hdmi_addrs,
1141 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1142 .user = OCP_USER_MPU,
1143};
1144
1145/* dss_hdmi slave ports */
1146static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1147 &omap44xx_l3_main_2__dss_hdmi,
1148 &omap44xx_l4_per__dss_hdmi,
1149};
1150
1151static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1152 .name = "dss_hdmi",
1153 .class = &omap44xx_hdmi_hwmod_class,
1154 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1155 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1156 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1157 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1158 .main_clk = "dss_fck",
1159 .prcm = {
1160 .omap4 = {
1161 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1162 },
1163 },
1164 .slaves = omap44xx_dss_hdmi_slaves,
1165 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1166 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1167};
1168
1169/*
1170 * 'rfbi' class
1171 * remote frame buffer interface
1172 */
1173
1174static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1175 .rev_offs = 0x0000,
1176 .sysc_offs = 0x0010,
1177 .syss_offs = 0x0014,
1178 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1179 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1180 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1181 .sysc_fields = &omap_hwmod_sysc_type1,
1182};
1183
1184static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1185 .name = "rfbi",
1186 .sysc = &omap44xx_rfbi_sysc,
1187};
1188
1189/* dss_rfbi */
1190static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1191static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1192 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1193};
1194
1195static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1196 {
1197 .pa_start = 0x58002000,
1198 .pa_end = 0x580020ff,
1199 .flags = ADDR_TYPE_RT
1200 },
1201};
1202
1203/* l3_main_2 -> dss_rfbi */
1204static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1205 .master = &omap44xx_l3_main_2_hwmod,
1206 .slave = &omap44xx_dss_rfbi_hwmod,
1207 .clk = "l3_div_ck",
1208 .addr = omap44xx_dss_rfbi_dma_addrs,
1209 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1210 .user = OCP_USER_SDMA,
1211};
1212
1213static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1214 {
1215 .pa_start = 0x48042000,
1216 .pa_end = 0x480420ff,
1217 .flags = ADDR_TYPE_RT
1218 },
1219};
1220
1221/* l4_per -> dss_rfbi */
1222static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1223 .master = &omap44xx_l4_per_hwmod,
1224 .slave = &omap44xx_dss_rfbi_hwmod,
1225 .clk = "l4_div_ck",
1226 .addr = omap44xx_dss_rfbi_addrs,
1227 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1228 .user = OCP_USER_MPU,
1229};
1230
1231/* dss_rfbi slave ports */
1232static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1233 &omap44xx_l3_main_2__dss_rfbi,
1234 &omap44xx_l4_per__dss_rfbi,
1235};
1236
1237static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1238 .name = "dss_rfbi",
1239 .class = &omap44xx_rfbi_hwmod_class,
1240 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1241 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1242 .main_clk = "dss_fck",
1243 .prcm = {
1244 .omap4 = {
1245 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1246 },
1247 },
1248 .slaves = omap44xx_dss_rfbi_slaves,
1249 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1250 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1251};
1252
1253/*
1254 * 'venc' class
1255 * video encoder
1256 */
1257
1258static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1259 .name = "venc",
1260};
1261
1262/* dss_venc */
1263static struct omap_hwmod omap44xx_dss_venc_hwmod;
1264static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1265 {
1266 .pa_start = 0x58003000,
1267 .pa_end = 0x580030ff,
1268 .flags = ADDR_TYPE_RT
1269 },
1270};
1271
1272/* l3_main_2 -> dss_venc */
1273static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1274 .master = &omap44xx_l3_main_2_hwmod,
1275 .slave = &omap44xx_dss_venc_hwmod,
1276 .clk = "l3_div_ck",
1277 .addr = omap44xx_dss_venc_dma_addrs,
1278 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1279 .user = OCP_USER_SDMA,
1280};
1281
1282static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1283 {
1284 .pa_start = 0x48043000,
1285 .pa_end = 0x480430ff,
1286 .flags = ADDR_TYPE_RT
1287 },
1288};
1289
1290/* l4_per -> dss_venc */
1291static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1292 .master = &omap44xx_l4_per_hwmod,
1293 .slave = &omap44xx_dss_venc_hwmod,
1294 .clk = "l4_div_ck",
1295 .addr = omap44xx_dss_venc_addrs,
1296 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1297 .user = OCP_USER_MPU,
1298};
1299
1300/* dss_venc slave ports */
1301static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1302 &omap44xx_l3_main_2__dss_venc,
1303 &omap44xx_l4_per__dss_venc,
1304};
1305
1306static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1307 .name = "dss_venc",
1308 .class = &omap44xx_venc_hwmod_class,
1309 .main_clk = "dss_fck",
1310 .prcm = {
1311 .omap4 = {
1312 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1313 },
1314 },
1315 .slaves = omap44xx_dss_venc_slaves,
1316 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1317 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1318};
1319
1320/*
734 * 'gpio' class 1321 * 'gpio' class
735 * general purpose io module 1322 * general purpose io module
736 */ 1323 */
@@ -2924,6 +3511,15 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2924 &omap44xx_dsp_hwmod, 3511 &omap44xx_dsp_hwmod,
2925 &omap44xx_dsp_c0_hwmod, 3512 &omap44xx_dsp_c0_hwmod,
2926 3513
3514 /* dss class */
3515 &omap44xx_dss_hwmod,
3516 &omap44xx_dss_dispc_hwmod,
3517 &omap44xx_dss_dsi1_hwmod,
3518 &omap44xx_dss_dsi2_hwmod,
3519 &omap44xx_dss_hdmi_hwmod,
3520 &omap44xx_dss_rfbi_hwmod,
3521 &omap44xx_dss_venc_hwmod,
3522
2927 /* gpio class */ 3523 /* gpio class */
2928 &omap44xx_gpio1_hwmod, 3524 &omap44xx_gpio1_hwmod,
2929 &omap44xx_gpio2_hwmod, 3525 &omap44xx_gpio2_hwmod,
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-16 00:33:34 -0400