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-rw-r--r--drivers/ata/Kconfig9
-rw-r--r--drivers/ata/Makefile1
-rw-r--r--drivers/ata/ahci.c4
-rw-r--r--drivers/ata/libata-core.c4
-rw-r--r--drivers/ata/pata_amd.c3
-rw-r--r--drivers/ata/pata_atp867x.c548
-rw-r--r--drivers/ata/sata_promise.c155
-rw-r--r--include/linux/pci_ids.h2
8 files changed, 704 insertions, 22 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index ab2fa4eeb364..f2df6e2a224c 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -255,6 +255,15 @@ config PATA_ARTOP
255 255
256 If unsure, say N. 256 If unsure, say N.
257 257
258config PATA_ATP867X
259 tristate "ARTOP/Acard ATP867X PATA support"
260 depends on PCI
261 help
262 This option enables support for ARTOP/Acard ATP867X PATA
263 controllers.
264
265 If unsure, say N.
266
258config PATA_AT32 267config PATA_AT32
259 tristate "Atmel AVR32 PATA support (Experimental)" 268 tristate "Atmel AVR32 PATA support (Experimental)"
260 depends on AVR32 && PLATFORM_AT32AP && EXPERIMENTAL 269 depends on AVR32 && PLATFORM_AT32AP && EXPERIMENTAL
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 463eb52236aa..01e126f343b3 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_SATA_FSL) += sata_fsl.o
22obj-$(CONFIG_PATA_ALI) += pata_ali.o 22obj-$(CONFIG_PATA_ALI) += pata_ali.o
23obj-$(CONFIG_PATA_AMD) += pata_amd.o 23obj-$(CONFIG_PATA_AMD) += pata_amd.o
24obj-$(CONFIG_PATA_ARTOP) += pata_artop.o 24obj-$(CONFIG_PATA_ARTOP) += pata_artop.o
25obj-$(CONFIG_PATA_ATP867X) += pata_atp867x.o
25obj-$(CONFIG_PATA_AT32) += pata_at32.o 26obj-$(CONFIG_PATA_AT32) += pata_at32.o
26obj-$(CONFIG_PATA_ATIIXP) += pata_atiixp.o 27obj-$(CONFIG_PATA_ATIIXP) += pata_atiixp.o
27obj-$(CONFIG_PATA_CMD640_PCI) += pata_cmd640.o 28obj-$(CONFIG_PATA_CMD640_PCI) += pata_cmd640.o
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index d4cd9c203314..acd1162712b1 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -2930,8 +2930,8 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2930 if (ahci_sb600_32bit_only(pdev)) 2930 if (ahci_sb600_32bit_only(pdev))
2931 hpriv->flags |= AHCI_HFLAG_32BIT_ONLY; 2931 hpriv->flags |= AHCI_HFLAG_32BIT_ONLY;
2932 2932
2933 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) 2933 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2934 pci_enable_msi(pdev); 2934 pci_intx(pdev, 1);
2935 2935
2936 /* save initial config */ 2936 /* save initial config */
2937 ahci_save_initial_config(pdev, hpriv); 2937 ahci_save_initial_config(pdev, hpriv);
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index df31deac5c82..0ddaf43d68c6 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -5024,8 +5024,6 @@ void ata_qc_complete(struct ata_queued_cmd *qc)
5024 struct ata_device *dev = qc->dev; 5024 struct ata_device *dev = qc->dev;
5025 struct ata_eh_info *ehi = &dev->link->eh_info; 5025 struct ata_eh_info *ehi = &dev->link->eh_info;
5026 5026
5027 WARN_ON_ONCE(ap->pflags & ATA_PFLAG_FROZEN);
5028
5029 if (unlikely(qc->err_mask)) 5027 if (unlikely(qc->err_mask))
5030 qc->flags |= ATA_QCFLAG_FAILED; 5028 qc->flags |= ATA_QCFLAG_FAILED;
5031 5029
@@ -5038,6 +5036,8 @@ void ata_qc_complete(struct ata_queued_cmd *qc)
5038 } 5036 }
5039 } 5037 }
5040 5038
5039 WARN_ON_ONCE(ap->pflags & ATA_PFLAG_FROZEN);
5040
5041 /* read result TF if requested */ 5041 /* read result TF if requested */
5042 if (qc->flags & ATA_QCFLAG_RESULT_TF) 5042 if (qc->flags & ATA_QCFLAG_RESULT_TF)
5043 fill_result_tf(qc); 5043 fill_result_tf(qc);
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
index 33a74f11171c..567f3f72774e 100644
--- a/drivers/ata/pata_amd.c
+++ b/drivers/ata/pata_amd.c
@@ -307,6 +307,9 @@ static unsigned long nv_mode_filter(struct ata_device *dev,
307 limit |= ATA_MASK_PIO; 307 limit |= ATA_MASK_PIO;
308 if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA))) 308 if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
309 limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA; 309 limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;
310 /* PIO4, MWDMA2, UDMA2 should always be supported regardless of
311 cable detection result */
312 limit |= ata_pack_xfermask(ATA_PIO4, ATA_MWDMA2, ATA_UDMA2);
310 313
311 ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, " 314 ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
312 "BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n", 315 "BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
diff --git a/drivers/ata/pata_atp867x.c b/drivers/ata/pata_atp867x.c
new file mode 100644
index 000000000000..7990de925d2e
--- /dev/null
+++ b/drivers/ata/pata_atp867x.c
@@ -0,0 +1,548 @@
1/*
2 * pata_atp867x.c - ARTOP 867X 64bit 4-channel UDMA133 ATA controller driver
3 *
4 * (C) 2009 Google Inc. John(Jung-Ik) Lee <jilee@google.com>
5 *
6 * Per Atp867 data sheet rev 1.2, Acard.
7 * Based in part on early ide code from
8 * 2003-2004 by Eric Uhrhane, Google, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 *
25 * TODO:
26 * 1. RAID features [comparison, XOR, striping, mirroring, etc.]
27 */
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/init.h>
33#include <linux/blkdev.h>
34#include <linux/delay.h>
35#include <linux/device.h>
36#include <scsi/scsi_host.h>
37#include <linux/libata.h>
38
39#define DRV_NAME "pata_atp867x"
40#define DRV_VERSION "0.7.5"
41
42/*
43 * IO Registers
44 * Note that all runtime hot priv ports are cached in ap private_data
45 */
46
47enum {
48 ATP867X_IO_CHANNEL_OFFSET = 0x10,
49
50 /*
51 * IO Register Bitfields
52 */
53
54 ATP867X_IO_PIOSPD_ACTIVE_SHIFT = 4,
55 ATP867X_IO_PIOSPD_RECOVER_SHIFT = 0,
56
57 ATP867X_IO_DMAMODE_MSTR_SHIFT = 0,
58 ATP867X_IO_DMAMODE_MSTR_MASK = 0x07,
59 ATP867X_IO_DMAMODE_SLAVE_SHIFT = 4,
60 ATP867X_IO_DMAMODE_SLAVE_MASK = 0x70,
61
62 ATP867X_IO_DMAMODE_UDMA_6 = 0x07,
63 ATP867X_IO_DMAMODE_UDMA_5 = 0x06,
64 ATP867X_IO_DMAMODE_UDMA_4 = 0x05,
65 ATP867X_IO_DMAMODE_UDMA_3 = 0x04,
66 ATP867X_IO_DMAMODE_UDMA_2 = 0x03,
67 ATP867X_IO_DMAMODE_UDMA_1 = 0x02,
68 ATP867X_IO_DMAMODE_UDMA_0 = 0x01,
69 ATP867X_IO_DMAMODE_DISABLE = 0x00,
70
71 ATP867X_IO_SYS_INFO_66MHZ = 0x04,
72 ATP867X_IO_SYS_INFO_SLOW_UDMA5 = 0x02,
73 ATP867X_IO_SYS_MASK_RESERVED = (~0xf1),
74
75 ATP867X_IO_PORTSPD_VAL = 0x1143,
76 ATP867X_PREREAD_VAL = 0x0200,
77
78 ATP867X_NUM_PORTS = 4,
79 ATP867X_BAR_IOBASE = 0,
80 ATP867X_BAR_ROMBASE = 6,
81};
82
83#define ATP867X_IOBASE(ap) ((ap)->host->iomap[0])
84#define ATP867X_SYS_INFO(ap) (0x3F + ATP867X_IOBASE(ap))
85
86#define ATP867X_IO_PORTBASE(ap, port) (0x00 + ATP867X_IOBASE(ap) + \
87 (port) * ATP867X_IO_CHANNEL_OFFSET)
88#define ATP867X_IO_DMABASE(ap, port) (0x40 + \
89 ATP867X_IO_PORTBASE((ap), (port)))
90
91#define ATP867X_IO_STATUS(ap, port) (0x07 + \
92 ATP867X_IO_PORTBASE((ap), (port)))
93#define ATP867X_IO_ALTSTATUS(ap, port) (0x0E + \
94 ATP867X_IO_PORTBASE((ap), (port)))
95
96/*
97 * hot priv ports
98 */
99#define ATP867X_IO_MSTRPIOSPD(ap, port) (0x08 + \
100 ATP867X_IO_DMABASE((ap), (port)))
101#define ATP867X_IO_SLAVPIOSPD(ap, port) (0x09 + \
102 ATP867X_IO_DMABASE((ap), (port)))
103#define ATP867X_IO_8BPIOSPD(ap, port) (0x0A + \
104 ATP867X_IO_DMABASE((ap), (port)))
105#define ATP867X_IO_DMAMODE(ap, port) (0x0B + \
106 ATP867X_IO_DMABASE((ap), (port)))
107
108#define ATP867X_IO_PORTSPD(ap, port) (0x4A + \
109 ATP867X_IO_PORTBASE((ap), (port)))
110#define ATP867X_IO_PREREAD(ap, port) (0x4C + \
111 ATP867X_IO_PORTBASE((ap), (port)))
112
113struct atp867x_priv {
114 void __iomem *dma_mode;
115 void __iomem *mstr_piospd;
116 void __iomem *slave_piospd;
117 void __iomem *eightb_piospd;
118 int pci66mhz;
119};
120
121static inline u8 atp867x_speed_to_mode(u8 speed)
122{
123 return speed - XFER_UDMA_0 + 1;
124}
125
126static void atp867x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
127{
128 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
129 struct atp867x_priv *dp = ap->private_data;
130 u8 speed = adev->dma_mode;
131 u8 b;
132 u8 mode;
133
134 mode = atp867x_speed_to_mode(speed);
135
136 /*
137 * Doc 6.6.9: decrease the udma mode value by 1 for safer UDMA speed
138 * on 66MHz bus
139 * rev-A: UDMA_1~4 (5, 6 no change)
140 * rev-B: all UDMA modes
141 * UDMA_0 stays not to disable UDMA
142 */
143 if (dp->pci66mhz && mode > ATP867X_IO_DMAMODE_UDMA_0 &&
144 (pdev->device == PCI_DEVICE_ID_ARTOP_ATP867B ||
145 mode < ATP867X_IO_DMAMODE_UDMA_5))
146 mode--;
147
148 b = ioread8(dp->dma_mode);
149 if (adev->devno & 1) {
150 b = (b & ~ATP867X_IO_DMAMODE_SLAVE_MASK) |
151 (mode << ATP867X_IO_DMAMODE_SLAVE_SHIFT);
152 } else {
153 b = (b & ~ATP867X_IO_DMAMODE_MSTR_MASK) |
154 (mode << ATP867X_IO_DMAMODE_MSTR_SHIFT);
155 }
156 iowrite8(b, dp->dma_mode);
157}
158
159static int atp867x_get_active_clocks_shifted(unsigned int clk)
160{
161 unsigned char clocks = clk;
162
163 switch (clocks) {
164 case 0:
165 clocks = 1;
166 break;
167 case 1 ... 7:
168 break;
169 case 8 ... 12:
170 clocks = 7;
171 break;
172 default:
173 printk(KERN_WARNING "ATP867X: active %dclk is invalid. "
174 "Using default 8clk.\n", clk);
175 clocks = 0; /* 8 clk */
176 break;
177 }
178 return clocks << ATP867X_IO_PIOSPD_ACTIVE_SHIFT;
179}
180
181static int atp867x_get_recover_clocks_shifted(unsigned int clk)
182{
183 unsigned char clocks = clk;
184
185 switch (clocks) {
186 case 0:
187 clocks = 1;
188 break;
189 case 1 ... 11:
190 break;
191 case 12:
192 clocks = 0;
193 break;
194 case 13: case 14:
195 --clocks;
196 break;
197 case 15:
198 break;
199 default:
200 printk(KERN_WARNING "ATP867X: recover %dclk is invalid. "
201 "Using default 15clk.\n", clk);
202 clocks = 0; /* 12 clk */
203 break;
204 }
205 return clocks << ATP867X_IO_PIOSPD_RECOVER_SHIFT;
206}
207
208static void atp867x_set_piomode(struct ata_port *ap, struct ata_device *adev)
209{
210 struct ata_device *peer = ata_dev_pair(adev);
211 struct atp867x_priv *dp = ap->private_data;
212 u8 speed = adev->pio_mode;
213 struct ata_timing t, p;
214 int T, UT;
215 u8 b;
216
217 T = 1000000000 / 33333;
218 UT = T / 4;
219
220 ata_timing_compute(adev, speed, &t, T, UT);
221 if (peer && peer->pio_mode) {
222 ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
223 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
224 }
225
226 b = ioread8(dp->dma_mode);
227 if (adev->devno & 1)
228 b = (b & ~ATP867X_IO_DMAMODE_SLAVE_MASK);
229 else
230 b = (b & ~ATP867X_IO_DMAMODE_MSTR_MASK);
231 iowrite8(b, dp->dma_mode);
232
233 b = atp867x_get_active_clocks_shifted(t.active) |
234 atp867x_get_recover_clocks_shifted(t.recover);
235 if (dp->pci66mhz)
236 b += 0x10;
237
238 if (adev->devno & 1)
239 iowrite8(b, dp->slave_piospd);
240 else
241 iowrite8(b, dp->mstr_piospd);
242
243 /*
244 * use the same value for comand timing as for PIO timimg
245 */
246 iowrite8(b, dp->eightb_piospd);
247}
248
249static int atp867x_cable_detect(struct ata_port *ap)
250{
251 return ATA_CBL_PATA40_SHORT;
252}
253
254static struct scsi_host_template atp867x_sht = {
255 ATA_BMDMA_SHT(DRV_NAME),
256};
257
258static struct ata_port_operations atp867x_ops = {
259 .inherits = &ata_bmdma_port_ops,
260 .cable_detect = atp867x_cable_detect,
261 .set_piomode = atp867x_set_piomode,
262 .set_dmamode = atp867x_set_dmamode,
263};
264
265
266#ifdef ATP867X_DEBUG
267static void atp867x_check_res(struct pci_dev *pdev)
268{
269 int i;
270 unsigned long start, len;
271
272 /* Check the PCI resources for this channel are enabled */
273 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
274 start = pci_resource_start(pdev, i);
275 len = pci_resource_len(pdev, i);
276 printk(KERN_DEBUG "ATP867X: resource start:len=%lx:%lx\n",
277 start, len);
278 }
279}
280
281static void atp867x_check_ports(struct ata_port *ap, int port)
282{
283 struct ata_ioports *ioaddr = &ap->ioaddr;
284 struct atp867x_priv *dp = ap->private_data;
285
286 printk(KERN_DEBUG "ATP867X: port[%d] addresses\n"
287 " cmd_addr =0x%llx, 0x%llx\n"
288 " ctl_addr =0x%llx, 0x%llx\n"
289 " bmdma_addr =0x%llx, 0x%llx\n"
290 " data_addr =0x%llx\n"
291 " error_addr =0x%llx\n"
292 " feature_addr =0x%llx\n"
293 " nsect_addr =0x%llx\n"
294 " lbal_addr =0x%llx\n"
295 " lbam_addr =0x%llx\n"
296 " lbah_addr =0x%llx\n"
297 " device_addr =0x%llx\n"
298 " status_addr =0x%llx\n"
299 " command_addr =0x%llx\n"
300 " dp->dma_mode =0x%llx\n"
301 " dp->mstr_piospd =0x%llx\n"
302 " dp->slave_piospd =0x%llx\n"
303 " dp->eightb_piospd =0x%llx\n"
304 " dp->pci66mhz =0x%lx\n",
305 port,
306 (unsigned long long)ioaddr->cmd_addr,
307 (unsigned long long)ATP867X_IO_PORTBASE(ap, port),
308 (unsigned long long)ioaddr->ctl_addr,
309 (unsigned long long)ATP867X_IO_ALTSTATUS(ap, port),
310 (unsigned long long)ioaddr->bmdma_addr,
311 (unsigned long long)ATP867X_IO_DMABASE(ap, port),
312 (unsigned long long)ioaddr->data_addr,
313 (unsigned long long)ioaddr->error_addr,
314 (unsigned long long)ioaddr->feature_addr,
315 (unsigned long long)ioaddr->nsect_addr,
316 (unsigned long long)ioaddr->lbal_addr,
317 (unsigned long long)ioaddr->lbam_addr,
318 (unsigned long long)ioaddr->lbah_addr,
319 (unsigned long long)ioaddr->device_addr,
320 (unsigned long long)ioaddr->status_addr,
321 (unsigned long long)ioaddr->command_addr,
322 (unsigned long long)dp->dma_mode,
323 (unsigned long long)dp->mstr_piospd,
324 (unsigned long long)dp->slave_piospd,
325 (unsigned long long)dp->eightb_piospd,
326 (unsigned long)dp->pci66mhz);
327}
328#endif
329
330static int atp867x_set_priv(struct ata_port *ap)
331{
332 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
333 struct atp867x_priv *dp;
334 int port = ap->port_no;
335
336 dp = ap->private_data =
337 devm_kzalloc(&pdev->dev, sizeof(*dp), GFP_KERNEL);
338 if (dp == NULL)
339 return -ENOMEM;
340
341 dp->dma_mode = ATP867X_IO_DMAMODE(ap, port);
342 dp->mstr_piospd = ATP867X_IO_MSTRPIOSPD(ap, port);
343 dp->slave_piospd = ATP867X_IO_SLAVPIOSPD(ap, port);
344 dp->eightb_piospd = ATP867X_IO_8BPIOSPD(ap, port);
345
346 dp->pci66mhz =
347 ioread8(ATP867X_SYS_INFO(ap)) & ATP867X_IO_SYS_INFO_66MHZ;
348
349 return 0;
350}
351
352static void atp867x_fixup(struct ata_host *host)
353{
354 struct pci_dev *pdev = to_pci_dev(host->dev);
355 struct ata_port *ap = host->ports[0];
356 int i;
357 u8 v;
358
359 /*
360 * Broken BIOS might not set latency high enough
361 */
362 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &v);
363 if (v < 0x80) {
364 v = 0x80;
365 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, v);
366 printk(KERN_DEBUG "ATP867X: set latency timer of device %s"
367 " to %d\n", pci_name(pdev), v);
368 }
369
370 /*
371 * init 8bit io ports speed(0aaarrrr) to 43h and
372 * init udma modes of master/slave to 0/0(11h)
373 */
374 for (i = 0; i < ATP867X_NUM_PORTS; i++)
375 iowrite16(ATP867X_IO_PORTSPD_VAL, ATP867X_IO_PORTSPD(ap, i));
376
377 /*
378 * init PreREAD counts
379 */
380 for (i = 0; i < ATP867X_NUM_PORTS; i++)
381 iowrite16(ATP867X_PREREAD_VAL, ATP867X_IO_PREREAD(ap, i));
382
383 v = ioread8(ATP867X_IOBASE(ap) + 0x28);
384 v &= 0xcf; /* Enable INTA#: bit4=0 means enable */
385 v |= 0xc0; /* Enable PCI burst, MRM & not immediate interrupts */
386 iowrite8(v, ATP867X_IOBASE(ap) + 0x28);
387
388 /*
389 * Turn off the over clocked udma5 mode, only for Rev-B
390 */
391 v = ioread8(ATP867X_SYS_INFO(ap));
392 v &= ATP867X_IO_SYS_MASK_RESERVED;
393 if (pdev->device == PCI_DEVICE_ID_ARTOP_ATP867B)
394 v |= ATP867X_IO_SYS_INFO_SLOW_UDMA5;
395 iowrite8(v, ATP867X_SYS_INFO(ap));
396}
397
398static int atp867x_ata_pci_sff_init_host(struct ata_host *host)
399{
400 struct device *gdev = host->dev;
401 struct pci_dev *pdev = to_pci_dev(gdev);
402 unsigned int mask = 0;
403 int i, rc;
404
405 /*
406 * do not map rombase
407 */
408 rc = pcim_iomap_regions(pdev, 1 << ATP867X_BAR_IOBASE, DRV_NAME);
409 if (rc == -EBUSY)
410 pcim_pin_device(pdev);
411 if (rc)
412 return rc;
413 host->iomap = pcim_iomap_table(pdev);
414
415#ifdef ATP867X_DEBUG
416 atp867x_check_res(pdev);
417
418 for (i = 0; i < PCI_ROM_RESOURCE; i++)
419 printk(KERN_DEBUG "ATP867X: iomap[%d]=0x%llx\n", i,
420 (unsigned long long)(host->iomap[i]));
421#endif
422
423 /*
424 * request, iomap BARs and init port addresses accordingly
425 */
426 for (i = 0; i < host->n_ports; i++) {
427 struct ata_port *ap = host->ports[i];
428 struct ata_ioports *ioaddr = &ap->ioaddr;
429
430 ioaddr->cmd_addr = ATP867X_IO_PORTBASE(ap, i);
431 ioaddr->ctl_addr = ioaddr->altstatus_addr
432 = ATP867X_IO_ALTSTATUS(ap, i);
433 ioaddr->bmdma_addr = ATP867X_IO_DMABASE(ap, i);
434
435 ata_sff_std_ports(ioaddr);
436 rc = atp867x_set_priv(ap);
437 if (rc)
438 return rc;
439
440#ifdef ATP867X_DEBUG
441 atp867x_check_ports(ap, i);
442#endif
443 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
444 (unsigned long)ioaddr->cmd_addr,
445 (unsigned long)ioaddr->ctl_addr);
446 ata_port_desc(ap, "bmdma 0x%lx",
447 (unsigned long)ioaddr->bmdma_addr);
448
449 mask |= 1 << i;
450 }
451
452 if (!mask) {
453 dev_printk(KERN_ERR, gdev, "no available native port\n");
454 return -ENODEV;
455 }
456
457 atp867x_fixup(host);
458
459 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
460 if (rc)
461 return rc;
462
463 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
464 return rc;
465}
466
467static int atp867x_init_one(struct pci_dev *pdev,
468 const struct pci_device_id *id)
469{
470 static int printed_version;
471 static const struct ata_port_info info_867x = {
472 .flags = ATA_FLAG_SLAVE_POSS,
473 .pio_mask = ATA_PIO4,
474 .mwdma_mask = ATA_MWDMA2,
475 .udma_mask = ATA_UDMA6,
476 .port_ops = &atp867x_ops,
477 };
478
479 struct ata_host *host;
480 const struct ata_port_info *ppi[] = { &info_867x, NULL };
481 int rc;
482
483 if (!printed_version++)
484 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
485
486 rc = pcim_enable_device(pdev);
487 if (rc)
488 return rc;
489
490 printk(KERN_INFO "ATP867X: ATP867 ATA UDMA133 controller (rev %02X)",
491 pdev->device);
492
493 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ATP867X_NUM_PORTS);
494 if (!host) {
495 dev_printk(KERN_ERR, &pdev->dev,
496 "failed to allocate ATA host\n");
497 rc = -ENOMEM;
498 goto err_out;
499 }
500
501 rc = atp867x_ata_pci_sff_init_host(host);
502 if (rc) {
503 dev_printk(KERN_ERR, &pdev->dev, "failed to init host\n");
504 goto err_out;
505 }
506
507 pci_set_master(pdev);
508
509 rc = ata_host_activate(host, pdev->irq, ata_sff_interrupt,
510 IRQF_SHARED, &atp867x_sht);
511 if (rc)
512 dev_printk(KERN_ERR, &pdev->dev, "failed to activate host\n");
513
514err_out:
515 return rc;
516}
517
518static struct pci_device_id atp867x_pci_tbl[] = {
519 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP867A), 0 },
520 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP867B), 0 },
521 { },
522};
523
524static struct pci_driver atp867x_driver = {
525 .name = DRV_NAME,
526 .id_table = atp867x_pci_tbl,
527 .probe = atp867x_init_one,
528 .remove = ata_pci_remove_one,
529};
530
531static int __init atp867x_init(void)
532{
533 return pci_register_driver(&atp867x_driver);
534}
535
536static void __exit atp867x_exit(void)
537{
538 pci_unregister_driver(&atp867x_driver);
539}
540
541MODULE_AUTHOR("John(Jung-Ik) Lee, Google Inc.");
542MODULE_DESCRIPTION("low level driver for Artop/Acard 867x ATA controller");
543MODULE_LICENSE("GPL");
544MODULE_DEVICE_TABLE(pci, atp867x_pci_tbl);
545MODULE_VERSION(DRV_VERSION);
546
547module_init(atp867x_init);
548module_exit(atp867x_exit);
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index b1fd7d62071a..07d8d00b4d34 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -56,6 +56,7 @@ enum {
56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */ 56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_FLASH_CTL = 0x44, /* Flash control register */ 58 PDC_FLASH_CTL = 0x44, /* Flash control register */
59 PDC_PCI_CTL = 0x48, /* PCI control/status reg */
59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
60 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ 61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
61 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ 62 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
@@ -75,7 +76,17 @@ enum {
75 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 76 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
76 77
77 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */ 78 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
79 PDC_SATA_ERROR = 0x04,
78 PDC_PHYMODE4 = 0x14, 80 PDC_PHYMODE4 = 0x14,
81 PDC_LINK_LAYER_ERRORS = 0x6C,
82 PDC_FPDMA_CTLSTAT = 0xD8,
83 PDC_INTERNAL_DEBUG_1 = 0xF8, /* also used for PATA */
84 PDC_INTERNAL_DEBUG_2 = 0xFC, /* also used for PATA */
85
86 /* PDC_FPDMA_CTLSTAT bit definitions */
87 PDC_FPDMA_CTLSTAT_RESET = 1 << 3,
88 PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
89 PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11,
79 90
80 /* PDC_GLOBAL_CTL bit definitions */ 91 /* PDC_GLOBAL_CTL bit definitions */
81 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ 92 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
@@ -195,9 +206,12 @@ static struct ata_port_operations pdc_sata_ops = {
195 .hardreset = pdc_sata_hardreset, 206 .hardreset = pdc_sata_hardreset,
196}; 207};
197 208
198/* First-generation chips need a more restrictive ->check_atapi_dma op */ 209/* First-generation chips need a more restrictive ->check_atapi_dma op,
210 and ->freeze/thaw that ignore the hotplug controls. */
199static struct ata_port_operations pdc_old_sata_ops = { 211static struct ata_port_operations pdc_old_sata_ops = {
200 .inherits = &pdc_sata_ops, 212 .inherits = &pdc_sata_ops,
213 .freeze = pdc_freeze,
214 .thaw = pdc_thaw,
201 .check_atapi_dma = pdc_old_sata_check_atapi_dma, 215 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
202}; 216};
203 217
@@ -356,12 +370,76 @@ static int pdc_sata_port_start(struct ata_port *ap)
356 return 0; 370 return 0;
357} 371}
358 372
373static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
374{
375 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
376 u32 tmp;
377
378 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
379 tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
380 tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
381
382 /* It's not allowed to write to the entire FPDMA_CTLSTAT register
383 when NCQ is running. So do a byte-sized write to bits 10 and 11. */
384 writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
385 readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */
386}
387
388static void pdc_fpdma_reset(struct ata_port *ap)
389{
390 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
391 u8 tmp;
392
393 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
394 tmp &= 0x7F;
395 tmp |= PDC_FPDMA_CTLSTAT_RESET;
396 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
397 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
398 udelay(100);
399 tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
400 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
401 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
402
403 pdc_fpdma_clear_interrupt_flag(ap);
404}
405
406static void pdc_not_at_command_packet_phase(struct ata_port *ap)
407{
408 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
409 unsigned int i;
410 u32 tmp;
411
412 /* check not at ASIC packet command phase */
413 for (i = 0; i < 100; ++i) {
414 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
415 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
416 if ((tmp & 0xF) != 1)
417 break;
418 udelay(100);
419 }
420}
421
422static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
423{
424 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
425
426 writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
427 writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
428}
429
359static void pdc_reset_port(struct ata_port *ap) 430static void pdc_reset_port(struct ata_port *ap)
360{ 431{
361 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; 432 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
362 unsigned int i; 433 unsigned int i;
363 u32 tmp; 434 u32 tmp;
364 435
436 if (ap->flags & PDC_FLAG_GEN_II)
437 pdc_not_at_command_packet_phase(ap);
438
439 tmp = readl(ata_ctlstat_mmio);
440 tmp |= PDC_RESET;
441 writel(tmp, ata_ctlstat_mmio);
442
365 for (i = 11; i > 0; i--) { 443 for (i = 11; i > 0; i--) {
366 tmp = readl(ata_ctlstat_mmio); 444 tmp = readl(ata_ctlstat_mmio);
367 if (tmp & PDC_RESET) 445 if (tmp & PDC_RESET)
@@ -376,6 +454,11 @@ static void pdc_reset_port(struct ata_port *ap)
376 tmp &= ~PDC_RESET; 454 tmp &= ~PDC_RESET;
377 writel(tmp, ata_ctlstat_mmio); 455 writel(tmp, ata_ctlstat_mmio);
378 readl(ata_ctlstat_mmio); /* flush */ 456 readl(ata_ctlstat_mmio); /* flush */
457
458 if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
459 pdc_fpdma_reset(ap);
460 pdc_clear_internal_debug_record_error_register(ap);
461 }
379} 462}
380 463
381static int pdc_pata_cable_detect(struct ata_port *ap) 464static int pdc_pata_cable_detect(struct ata_port *ap)
@@ -626,11 +709,6 @@ static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
626 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags)); 709 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
627} 710}
628 711
629static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap)
630{
631 return (ap->flags & PDC_FLAG_GEN_II) ? PDC2_SATA_PLUG_CSR : PDC_SATA_PLUG_CSR;
632}
633
634static void pdc_freeze(struct ata_port *ap) 712static void pdc_freeze(struct ata_port *ap)
635{ 713{
636 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 714 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
@@ -647,7 +725,7 @@ static void pdc_sata_freeze(struct ata_port *ap)
647{ 725{
648 struct ata_host *host = ap->host; 726 struct ata_host *host = ap->host;
649 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 727 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
650 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap); 728 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
651 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); 729 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
652 u32 hotplug_status; 730 u32 hotplug_status;
653 731
@@ -685,7 +763,7 @@ static void pdc_sata_thaw(struct ata_port *ap)
685{ 763{
686 struct ata_host *host = ap->host; 764 struct ata_host *host = ap->host;
687 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 765 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
688 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap); 766 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
689 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); 767 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
690 u32 hotplug_status; 768 u32 hotplug_status;
691 769
@@ -708,11 +786,50 @@ static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
708 return ata_sff_softreset(link, class, deadline); 786 return ata_sff_softreset(link, class, deadline);
709} 787}
710 788
789static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
790{
791 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
792 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
793
794 /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */
795 return (ata_mmio - host_mmio - 0x200) / 0x80;
796}
797
798static void pdc_hard_reset_port(struct ata_port *ap)
799{
800 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
801 void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
802 unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
803 u8 tmp;
804
805 spin_lock(&ap->host->lock);
806
807 tmp = readb(pcictl_b1_mmio);
808 tmp &= ~(0x10 << ata_no);
809 writeb(tmp, pcictl_b1_mmio);
810 readb(pcictl_b1_mmio); /* flush */
811 udelay(100);
812 tmp |= (0x10 << ata_no);
813 writeb(tmp, pcictl_b1_mmio);
814 readb(pcictl_b1_mmio); /* flush */
815
816 spin_unlock(&ap->host->lock);
817}
818
711static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class, 819static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
712 unsigned long deadline) 820 unsigned long deadline)
713{ 821{
822 if (link->ap->flags & PDC_FLAG_GEN_II)
823 pdc_not_at_command_packet_phase(link->ap);
824 /* hotplug IRQs should have been masked by pdc_sata_freeze() */
825 pdc_hard_reset_port(link->ap);
714 pdc_reset_port(link->ap); 826 pdc_reset_port(link->ap);
715 return sata_sff_hardreset(link, class, deadline); 827
828 /* sata_promise can't reliably acquire the first D2H Reg FIS
829 * after hardreset. Do non-waiting hardreset and request
830 * follow-up SRST.
831 */
832 return sata_std_hardreset(link, class, deadline);
716} 833}
717 834
718static void pdc_error_handler(struct ata_port *ap) 835static void pdc_error_handler(struct ata_port *ap)
@@ -832,14 +949,14 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
832 spin_lock(&host->lock); 949 spin_lock(&host->lock);
833 950
834 /* read and clear hotplug flags for all ports */ 951 /* read and clear hotplug flags for all ports */
835 if (host->ports[0]->flags & PDC_FLAG_GEN_II) 952 if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
836 hotplug_offset = PDC2_SATA_PLUG_CSR; 953 hotplug_offset = PDC2_SATA_PLUG_CSR;
837 else 954 hotplug_status = readl(host_mmio + hotplug_offset);
838 hotplug_offset = PDC_SATA_PLUG_CSR; 955 if (hotplug_status & 0xff)
839 hotplug_status = readl(host_mmio + hotplug_offset); 956 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
840 if (hotplug_status & 0xff) 957 hotplug_status &= 0xff; /* clear uninteresting bits */
841 writel(hotplug_status | 0xff, host_mmio + hotplug_offset); 958 } else
842 hotplug_status &= 0xff; /* clear uninteresting bits */ 959 hotplug_status = 0;
843 960
844 /* reading should also clear interrupts */ 961 /* reading should also clear interrupts */
845 mask = readl(host_mmio + PDC_INT_SEQMASK); 962 mask = readl(host_mmio + PDC_INT_SEQMASK);
@@ -1034,9 +1151,11 @@ static void pdc_host_init(struct ata_host *host)
1034 tmp = readl(host_mmio + hotplug_offset); 1151 tmp = readl(host_mmio + hotplug_offset);
1035 writel(tmp | 0xff, host_mmio + hotplug_offset); 1152 writel(tmp | 0xff, host_mmio + hotplug_offset);
1036 1153
1037 /* unmask plug/unplug ints */
1038 tmp = readl(host_mmio + hotplug_offset); 1154 tmp = readl(host_mmio + hotplug_offset);
1039 writel(tmp & ~0xff0000, host_mmio + hotplug_offset); 1155 if (is_gen2) /* unmask plug/unplug ints */
1156 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1157 else /* mask plug/unplug ints */
1158 writel(tmp | 0xff0000, host_mmio + hotplug_offset);
1040 1159
1041 /* don't initialise TBG or SLEW on 2nd generation chips */ 1160 /* don't initialise TBG or SLEW on 2nd generation chips */
1042 if (is_gen2) 1161 if (is_gen2)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 8975add8668f..3b6b788fe2b5 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1529,6 +1529,8 @@
1529#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007 1529#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007
1530#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008 1530#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008
1531#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009 1531#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009
1532#define PCI_DEVICE_ID_ARTOP_ATP867A 0x000A
1533#define PCI_DEVICE_ID_ARTOP_ATP867B 0x000B
1532#define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002 1534#define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002
1533#define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010 1535#define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010
1534#define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020 1536#define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 15:20:11 -0500