aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/configs/omap2plus_defconfig1
-rw-r--r--arch/arm/mach-omap2/Kconfig2
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c21
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c80
-rw-r--r--arch/arm/mach-omap2/board-3630sdp.c3
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c92
-rw-r--r--arch/arm/mach-omap2/board-flash.c32
-rw-r--r--arch/arm/mach-omap2/board-flash.h4
-rw-r--r--arch/arm/mach-omap2/board-ldp.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c197
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c70
-rw-r--r--arch/arm/mach-omap2/board-zoom.c5
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c2
-rw-r--r--arch/arm/mach-omap2/devices.c41
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c7
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c113
-rw-r--r--arch/arm/mach-omap2/gpmc.c56
-rw-r--r--arch/arm/mach-omap2/hsmmc.c5
-rw-r--r--arch/arm/mach-omap2/id.c31
-rw-r--r--arch/arm/mach-omap2/io.c2
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h16
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h18
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h2
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h9
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h11
-rw-r--r--arch/arm/plat-omap/include/plat/onenand.h10
-rw-r--r--arch/arm/plat-omap/sram.c16
-rw-r--r--drivers/mmc/host/omap_hsmmc.c24
-rw-r--r--drivers/mtd/nand/Kconfig17
-rw-r--r--drivers/mtd/nand/omap2.c367
-rw-r--r--drivers/mtd/onenand/omap2.c36
-rw-r--r--include/linux/mtd/onenand_regs.h1
32 files changed, 997 insertions, 296 deletions
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index ae890caa17a7..019fb7c67dc3 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -58,6 +58,7 @@ CONFIG_ARM_ERRATA_411920=y
58CONFIG_NO_HZ=y 58CONFIG_NO_HZ=y
59CONFIG_HIGH_RES_TIMERS=y 59CONFIG_HIGH_RES_TIMERS=y
60CONFIG_SMP=y 60CONFIG_SMP=y
61CONFIG_NR_CPUS=2
61# CONFIG_LOCAL_TIMERS is not set 62# CONFIG_LOCAL_TIMERS is not set
62CONFIG_AEABI=y 63CONFIG_AEABI=y
63CONFIG_LEDS=y 64CONFIG_LEDS=y
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 9b4e78fe3d1c..b9d8a7b2a862 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -310,6 +310,7 @@ config MACH_OMAP_4430SDP
310 depends on ARCH_OMAP4 310 depends on ARCH_OMAP4
311 select OMAP_PACKAGE_CBL 311 select OMAP_PACKAGE_CBL
312 select OMAP_PACKAGE_CBS 312 select OMAP_PACKAGE_CBS
313 select REGULATOR_FIXED_VOLTAGE
313 314
314config MACH_OMAP4_PANDA 315config MACH_OMAP4_PANDA
315 bool "OMAP4 Panda Board" 316 bool "OMAP4 Panda Board"
@@ -317,6 +318,7 @@ config MACH_OMAP4_PANDA
317 depends on ARCH_OMAP4 318 depends on ARCH_OMAP4
318 select OMAP_PACKAGE_CBL 319 select OMAP_PACKAGE_CBL
319 select OMAP_PACKAGE_CBS 320 select OMAP_PACKAGE_CBS
321 select REGULATOR_FIXED_VOLTAGE
320 322
321config OMAP3_EMU 323config OMAP3_EMU
322 bool "OMAP3 debugging peripherals" 324 bool "OMAP3 debugging peripherals"
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index ec74c0f2051c..cc42d474c443 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -22,6 +22,7 @@
22#include <linux/mmc/host.h> 22#include <linux/mmc/host.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/i2c/twl.h> 24#include <linux/i2c/twl.h>
25#include <linux/regulator/machine.h>
25#include <linux/err.h> 26#include <linux/err.h>
26#include <linux/clk.h> 27#include <linux/clk.h>
27#include <linux/io.h> 28#include <linux/io.h>
@@ -147,6 +148,25 @@ static void __init omap_2430sdp_init_early(void)
147 omap2_init_common_devices(NULL, NULL); 148 omap2_init_common_devices(NULL, NULL);
148} 149}
149 150
151static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
152 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"),
153};
154
155/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
156static struct regulator_init_data sdp2430_vmmc1 = {
157 .constraints = {
158 .min_uV = 1850000,
159 .max_uV = 3150000,
160 .valid_modes_mask = REGULATOR_MODE_NORMAL
161 | REGULATOR_MODE_STANDBY,
162 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
163 | REGULATOR_CHANGE_MODE
164 | REGULATOR_CHANGE_STATUS,
165 },
166 .num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies),
167 .consumer_supplies = &sdp2430_vmmc1_supplies[0],
168};
169
150static struct twl4030_gpio_platform_data sdp2430_gpio_data = { 170static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
151 .gpio_base = OMAP_MAX_GPIO_LINES, 171 .gpio_base = OMAP_MAX_GPIO_LINES,
152 .irq_base = TWL4030_GPIO_IRQ_BASE, 172 .irq_base = TWL4030_GPIO_IRQ_BASE,
@@ -159,6 +179,7 @@ static struct twl4030_platform_data sdp2430_twldata = {
159 179
160 /* platform_data for children goes here */ 180 /* platform_data for children goes here */
161 .gpio = &sdp2430_gpio_data, 181 .gpio = &sdp2430_gpio_data,
182 .vmmc1 = &sdp2430_vmmc1,
162}; 183};
163 184
164static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = { 185static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = {
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 31085883199e..76a260f7c00e 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -315,11 +315,6 @@ static struct platform_device sdp3430_dss_device = {
315 }, 315 },
316}; 316};
317 317
318static struct regulator_consumer_supply sdp3430_vdda_dac_supply = {
319 .supply = "vdda_dac",
320 .dev = &sdp3430_dss_device.dev,
321};
322
323static struct platform_device *sdp3430_devices[] __initdata = { 318static struct platform_device *sdp3430_devices[] __initdata = {
324 &sdp3430_dss_device, 319 &sdp3430_dss_device,
325}; 320};
@@ -369,18 +364,6 @@ static struct omap2_hsmmc_info mmc[] = {
369 {} /* Terminator */ 364 {} /* Terminator */
370}; 365};
371 366
372static struct regulator_consumer_supply sdp3430_vmmc1_supply = {
373 .supply = "vmmc",
374};
375
376static struct regulator_consumer_supply sdp3430_vsim_supply = {
377 .supply = "vmmc_aux",
378};
379
380static struct regulator_consumer_supply sdp3430_vmmc2_supply = {
381 .supply = "vmmc",
382};
383
384static int sdp3430_twl_gpio_setup(struct device *dev, 367static int sdp3430_twl_gpio_setup(struct device *dev,
385 unsigned gpio, unsigned ngpio) 368 unsigned gpio, unsigned ngpio)
386{ 369{
@@ -391,13 +374,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
391 mmc[1].gpio_cd = gpio + 1; 374 mmc[1].gpio_cd = gpio + 1;
392 omap2_hsmmc_init(mmc); 375 omap2_hsmmc_init(mmc);
393 376
394 /* link regulators to MMC adapters ... we "know" the
395 * regulators will be set up only *after* we return.
396 */
397 sdp3430_vmmc1_supply.dev = mmc[0].dev;
398 sdp3430_vsim_supply.dev = mmc[0].dev;
399 sdp3430_vmmc2_supply.dev = mmc[1].dev;
400
401 /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */ 377 /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
402 gpio_request(gpio + 7, "sub_lcd_en_bkl"); 378 gpio_request(gpio + 7, "sub_lcd_en_bkl");
403 gpio_direction_output(gpio + 7, 0); 379 gpio_direction_output(gpio + 7, 0);
@@ -426,6 +402,34 @@ static struct twl4030_madc_platform_data sdp3430_madc_data = {
426 .irq_line = 1, 402 .irq_line = 1,
427}; 403};
428 404
405/* regulator consumer mappings */
406
407/* ads7846 on SPI */
408static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
409 REGULATOR_SUPPLY("vcc", "spi1.0"),
410};
411
412static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
413 REGULATOR_SUPPLY("vdda_dac", "omapdss"),
414};
415
416/* VPLL2 for digital video outputs */
417static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
418 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
419};
420
421static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
422 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"),
423};
424
425static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
426 REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.0"),
427};
428
429static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
430 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
431};
432
429/* 433/*
430 * Apply all the fixed voltages since most versions of U-Boot 434 * Apply all the fixed voltages since most versions of U-Boot
431 * don't bother with that initialization. 435 * don't bother with that initialization.
@@ -468,6 +472,8 @@ static struct regulator_init_data sdp3430_vaux3 = {
468 .valid_ops_mask = REGULATOR_CHANGE_MODE 472 .valid_ops_mask = REGULATOR_CHANGE_MODE
469 | REGULATOR_CHANGE_STATUS, 473 | REGULATOR_CHANGE_STATUS,
470 }, 474 },
475 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
476 .consumer_supplies = sdp3430_vaux3_supplies,
471}; 477};
472 478
473/* VAUX4 for OMAP VDD_CSI2 (camera) */ 479/* VAUX4 for OMAP VDD_CSI2 (camera) */
@@ -494,8 +500,8 @@ static struct regulator_init_data sdp3430_vmmc1 = {
494 | REGULATOR_CHANGE_MODE 500 | REGULATOR_CHANGE_MODE
495 | REGULATOR_CHANGE_STATUS, 501 | REGULATOR_CHANGE_STATUS,
496 }, 502 },
497 .num_consumer_supplies = 1, 503 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
498 .consumer_supplies = &sdp3430_vmmc1_supply, 504 .consumer_supplies = sdp3430_vmmc1_supplies,
499}; 505};
500 506
501/* VMMC2 for MMC2 card */ 507/* VMMC2 for MMC2 card */
@@ -509,8 +515,8 @@ static struct regulator_init_data sdp3430_vmmc2 = {
509 .valid_ops_mask = REGULATOR_CHANGE_MODE 515 .valid_ops_mask = REGULATOR_CHANGE_MODE
510 | REGULATOR_CHANGE_STATUS, 516 | REGULATOR_CHANGE_STATUS,
511 }, 517 },
512 .num_consumer_supplies = 1, 518 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
513 .consumer_supplies = &sdp3430_vmmc2_supply, 519 .consumer_supplies = sdp3430_vmmc2_supplies,
514}; 520};
515 521
516/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ 522/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
@@ -524,8 +530,8 @@ static struct regulator_init_data sdp3430_vsim = {
524 | REGULATOR_CHANGE_MODE 530 | REGULATOR_CHANGE_MODE
525 | REGULATOR_CHANGE_STATUS, 531 | REGULATOR_CHANGE_STATUS,
526 }, 532 },
527 .num_consumer_supplies = 1, 533 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
528 .consumer_supplies = &sdp3430_vsim_supply, 534 .consumer_supplies = sdp3430_vsim_supplies,
529}; 535};
530 536
531/* VDAC for DSS driving S-Video */ 537/* VDAC for DSS driving S-Video */
@@ -539,16 +545,8 @@ static struct regulator_init_data sdp3430_vdac = {
539 .valid_ops_mask = REGULATOR_CHANGE_MODE 545 .valid_ops_mask = REGULATOR_CHANGE_MODE
540 | REGULATOR_CHANGE_STATUS, 546 | REGULATOR_CHANGE_STATUS,
541 }, 547 },
542 .num_consumer_supplies = 1, 548 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
543 .consumer_supplies = &sdp3430_vdda_dac_supply, 549 .consumer_supplies = sdp3430_vdda_dac_supplies,
544};
545
546/* VPLL2 for digital video outputs */
547static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
548 {
549 .supply = "vdds_dsi",
550 .dev = &sdp3430_dss_device.dev,
551 }
552}; 550};
553 551
554static struct regulator_init_data sdp3430_vpll2 = { 552static struct regulator_init_data sdp3430_vpll2 = {
@@ -812,7 +810,7 @@ static void __init omap_3430sdp_init(void)
812 omap_serial_init(); 810 omap_serial_init();
813 usb_musb_init(&musb_board_data); 811 usb_musb_init(&musb_board_data);
814 board_smc91x_init(); 812 board_smc91x_init();
815 board_flash_init(sdp_flash_partitions, chip_sel_3430); 813 board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
816 sdp3430_display_init(); 814 sdp3430_display_init();
817 enable_board_wakeup_source(); 815 enable_board_wakeup_source();
818 usb_ehci_init(&ehci_pdata); 816 usb_ehci_init(&ehci_pdata);
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 16538757291a..8d1c4358ecf9 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -11,6 +11,7 @@
11#include <linux/platform_device.h> 11#include <linux/platform_device.h>
12#include <linux/input.h> 12#include <linux/input.h>
13#include <linux/gpio.h> 13#include <linux/gpio.h>
14#include <linux/mtd/nand.h>
14 15
15#include <asm/mach-types.h> 16#include <asm/mach-types.h>
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
@@ -208,7 +209,7 @@ static void __init omap_sdp_init(void)
208 zoom_peripherals_init(); 209 zoom_peripherals_init();
209 zoom_display_init(); 210 zoom_display_init();
210 board_smc91x_init(); 211 board_smc91x_init();
211 board_flash_init(sdp_flash_partitions, chip_sel_sdp); 212 board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
212 enable_board_wakeup_source(); 213 enable_board_wakeup_source();
213 usb_ehci_init(&ehci_pdata); 214 usb_ehci_init(&ehci_pdata);
214} 215}
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index bf8268438d00..1a943be822c3 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -35,6 +35,7 @@
35#include <plat/common.h> 35#include <plat/common.h>
36#include <plat/usb.h> 36#include <plat/usb.h>
37#include <plat/mmc.h> 37#include <plat/mmc.h>
38#include <plat/omap4-keypad.h>
38 39
39#include "mux.h" 40#include "mux.h"
40#include "hsmmc.h" 41#include "hsmmc.h"
@@ -47,6 +48,90 @@
47#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 48#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
48#define OMAP4_SFH7741_ENABLE_GPIO 188 49#define OMAP4_SFH7741_ENABLE_GPIO 188
49 50
51static const int sdp4430_keymap[] = {
52 KEY(0, 0, KEY_E),
53 KEY(0, 1, KEY_R),
54 KEY(0, 2, KEY_T),
55 KEY(0, 3, KEY_HOME),
56 KEY(0, 4, KEY_F5),
57 KEY(0, 5, KEY_UNKNOWN),
58 KEY(0, 6, KEY_I),
59 KEY(0, 7, KEY_LEFTSHIFT),
60
61 KEY(1, 0, KEY_D),
62 KEY(1, 1, KEY_F),
63 KEY(1, 2, KEY_G),
64 KEY(1, 3, KEY_SEND),
65 KEY(1, 4, KEY_F6),
66 KEY(1, 5, KEY_UNKNOWN),
67 KEY(1, 6, KEY_K),
68 KEY(1, 7, KEY_ENTER),
69
70 KEY(2, 0, KEY_X),
71 KEY(2, 1, KEY_C),
72 KEY(2, 2, KEY_V),
73 KEY(2, 3, KEY_END),
74 KEY(2, 4, KEY_F7),
75 KEY(2, 5, KEY_UNKNOWN),
76 KEY(2, 6, KEY_DOT),
77 KEY(2, 7, KEY_CAPSLOCK),
78
79 KEY(3, 0, KEY_Z),
80 KEY(3, 1, KEY_KPPLUS),
81 KEY(3, 2, KEY_B),
82 KEY(3, 3, KEY_F1),
83 KEY(3, 4, KEY_F8),
84 KEY(3, 5, KEY_UNKNOWN),
85 KEY(3, 6, KEY_O),
86 KEY(3, 7, KEY_SPACE),
87
88 KEY(4, 0, KEY_W),
89 KEY(4, 1, KEY_Y),
90 KEY(4, 2, KEY_U),
91 KEY(4, 3, KEY_F2),
92 KEY(4, 4, KEY_VOLUMEUP),
93 KEY(4, 5, KEY_UNKNOWN),
94 KEY(4, 6, KEY_L),
95 KEY(4, 7, KEY_LEFT),
96
97 KEY(5, 0, KEY_S),
98 KEY(5, 1, KEY_H),
99 KEY(5, 2, KEY_J),
100 KEY(5, 3, KEY_F3),
101 KEY(5, 4, KEY_F9),
102 KEY(5, 5, KEY_VOLUMEDOWN),
103 KEY(5, 6, KEY_M),
104 KEY(5, 7, KEY_RIGHT),
105
106 KEY(6, 0, KEY_Q),
107 KEY(6, 1, KEY_A),
108 KEY(6, 2, KEY_N),
109 KEY(6, 3, KEY_BACK),
110 KEY(6, 4, KEY_BACKSPACE),
111 KEY(6, 5, KEY_UNKNOWN),
112 KEY(6, 6, KEY_P),
113 KEY(6, 7, KEY_UP),
114
115 KEY(7, 0, KEY_PROG1),
116 KEY(7, 1, KEY_PROG2),
117 KEY(7, 2, KEY_PROG3),
118 KEY(7, 3, KEY_PROG4),
119 KEY(7, 4, KEY_F4),
120 KEY(7, 5, KEY_UNKNOWN),
121 KEY(7, 6, KEY_OK),
122 KEY(7, 7, KEY_DOWN),
123};
124
125static struct matrix_keymap_data sdp4430_keymap_data = {
126 .keymap = sdp4430_keymap,
127 .keymap_size = ARRAY_SIZE(sdp4430_keymap),
128};
129
130static struct omap4_keypad_platform_data sdp4430_keypad_data = {
131 .keymap_data = &sdp4430_keymap_data,
132 .rows = 8,
133 .cols = 8,
134};
50static struct gpio_led sdp4430_gpio_leds[] = { 135static struct gpio_led sdp4430_gpio_leds[] = {
51 { 136 {
52 .name = "omap4:green:debug0", 137 .name = "omap4:green:debug0",
@@ -422,7 +507,6 @@ static struct regulator_init_data sdp4430_vana = {
422 .constraints = { 507 .constraints = {
423 .min_uV = 2100000, 508 .min_uV = 2100000,
424 .max_uV = 2100000, 509 .max_uV = 2100000,
425 .apply_uV = true,
426 .valid_modes_mask = REGULATOR_MODE_NORMAL 510 .valid_modes_mask = REGULATOR_MODE_NORMAL
427 | REGULATOR_MODE_STANDBY, 511 | REGULATOR_MODE_STANDBY,
428 .valid_ops_mask = REGULATOR_CHANGE_MODE 512 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -434,7 +518,6 @@ static struct regulator_init_data sdp4430_vcxio = {
434 .constraints = { 518 .constraints = {
435 .min_uV = 1800000, 519 .min_uV = 1800000,
436 .max_uV = 1800000, 520 .max_uV = 1800000,
437 .apply_uV = true,
438 .valid_modes_mask = REGULATOR_MODE_NORMAL 521 .valid_modes_mask = REGULATOR_MODE_NORMAL
439 | REGULATOR_MODE_STANDBY, 522 | REGULATOR_MODE_STANDBY,
440 .valid_ops_mask = REGULATOR_CHANGE_MODE 523 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -446,7 +529,6 @@ static struct regulator_init_data sdp4430_vdac = {
446 .constraints = { 529 .constraints = {
447 .min_uV = 1800000, 530 .min_uV = 1800000,
448 .max_uV = 1800000, 531 .max_uV = 1800000,
449 .apply_uV = true,
450 .valid_modes_mask = REGULATOR_MODE_NORMAL 532 .valid_modes_mask = REGULATOR_MODE_NORMAL
451 | REGULATOR_MODE_STANDBY, 533 | REGULATOR_MODE_STANDBY,
452 .valid_ops_mask = REGULATOR_CHANGE_MODE 534 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -574,6 +656,10 @@ static void __init omap_4430sdp_init(void)
574 spi_register_board_info(sdp4430_spi_board_info, 656 spi_register_board_info(sdp4430_spi_board_info,
575 ARRAY_SIZE(sdp4430_spi_board_info)); 657 ARRAY_SIZE(sdp4430_spi_board_info));
576 } 658 }
659
660 status = omap4_keyboard_init(&sdp4430_keypad_data);
661 if (status)
662 pr_err("Keypad initialization failed: %d\n", status);
577} 663}
578 664
579static void __init omap_4430sdp_map_io(void) 665static void __init omap_4430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index fd38c05bb47f..c32c06828f08 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * board-sdp-flash.c 2 * board-flash.c
3 * Modified from mach-omap2/board-3430sdp-flash.c 3 * Modified from mach-omap2/board-3430sdp-flash.c
4 * 4 *
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009 Nokia Corporation
@@ -16,6 +16,7 @@
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h> 17#include <linux/mtd/physmap.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <plat/irqs.h>
19 20
20#include <plat/gpmc.h> 21#include <plat/gpmc.h>
21#include <plat/nand.h> 22#include <plat/nand.h>
@@ -73,11 +74,11 @@ __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
73 + FLASH_SIZE_SDPV1 - 1; 74 + FLASH_SIZE_SDPV1 - 1;
74 } 75 }
75 if (err < 0) { 76 if (err < 0) {
76 printk(KERN_ERR "NOR: Can't request GPMC CS\n"); 77 pr_err("NOR: Can't request GPMC CS\n");
77 return; 78 return;
78 } 79 }
79 if (platform_device_register(&board_nor_device) < 0) 80 if (platform_device_register(&board_nor_device) < 0)
80 printk(KERN_ERR "Unable to register NOR device\n"); 81 pr_err("Unable to register NOR device\n");
81} 82}
82 83
83#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ 84#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
@@ -139,12 +140,16 @@ static struct omap_nand_platform_data board_nand_data = {
139}; 140};
140 141
141void 142void
142__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) 143__init board_nand_init(struct mtd_partition *nand_parts,
144 u8 nr_parts, u8 cs, int nand_type)
143{ 145{
144 board_nand_data.cs = cs; 146 board_nand_data.cs = cs;
145 board_nand_data.parts = nand_parts; 147 board_nand_data.parts = nand_parts;
146 board_nand_data.nr_parts = nr_parts; 148 board_nand_data.nr_parts = nr_parts;
149 board_nand_data.devsize = nand_type;
147 150
151 board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
152 board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
148 gpmc_nand_init(&board_nand_data); 153 gpmc_nand_init(&board_nand_data);
149} 154}
150#else 155#else
@@ -189,12 +194,12 @@ unmap:
189} 194}
190 195
191/** 196/**
192 * sdp3430_flash_init - Identify devices connected to GPMC and register. 197 * board_flash_init - Identify devices connected to GPMC and register.
193 * 198 *
194 * @return - void. 199 * @return - void.
195 */ 200 */
196void board_flash_init(struct flash_partitions partition_info[], 201void board_flash_init(struct flash_partitions partition_info[],
197 char chip_sel_board[][GPMC_CS_NUM]) 202 char chip_sel_board[][GPMC_CS_NUM], int nand_type)
198{ 203{
199 u8 cs = 0; 204 u8 cs = 0;
200 u8 norcs = GPMC_CS_NUM + 1; 205 u8 norcs = GPMC_CS_NUM + 1;
@@ -208,7 +213,7 @@ void board_flash_init(struct flash_partitions partition_info[],
208 */ 213 */
209 idx = get_gpmc0_type(); 214 idx = get_gpmc0_type();
210 if (idx >= MAX_SUPPORTED_GPMC_CONFIG) { 215 if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
211 printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); 216 pr_err("%s: Invalid chip select: %d\n", __func__, cs);
212 return; 217 return;
213 } 218 }
214 config_sel = (unsigned char *)(chip_sel_board[idx]); 219 config_sel = (unsigned char *)(chip_sel_board[idx]);
@@ -232,23 +237,20 @@ void board_flash_init(struct flash_partitions partition_info[],
232 } 237 }
233 238
234 if (norcs > GPMC_CS_NUM) 239 if (norcs > GPMC_CS_NUM)
235 printk(KERN_INFO "NOR: Unable to find configuration " 240 pr_err("NOR: Unable to find configuration in GPMC\n");
236 "in GPMC\n");
237 else 241 else
238 board_nor_init(partition_info[0].parts, 242 board_nor_init(partition_info[0].parts,
239 partition_info[0].nr_parts, norcs); 243 partition_info[0].nr_parts, norcs);
240 244
241 if (onenandcs > GPMC_CS_NUM) 245 if (onenandcs > GPMC_CS_NUM)
242 printk(KERN_INFO "OneNAND: Unable to find configuration " 246 pr_err("OneNAND: Unable to find configuration in GPMC\n");
243 "in GPMC\n");
244 else 247 else
245 board_onenand_init(partition_info[1].parts, 248 board_onenand_init(partition_info[1].parts,
246 partition_info[1].nr_parts, onenandcs); 249 partition_info[1].nr_parts, onenandcs);
247 250
248 if (nandcs > GPMC_CS_NUM) 251 if (nandcs > GPMC_CS_NUM)
249 printk(KERN_INFO "NAND: Unable to find configuration " 252 pr_err("NAND: Unable to find configuration in GPMC\n");
250 "in GPMC\n");
251 else 253 else
252 board_nand_init(partition_info[2].parts, 254 board_nand_init(partition_info[2].parts,
253 partition_info[2].nr_parts, nandcs); 255 partition_info[2].nr_parts, nandcs, nand_type);
254} 256}
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index 69befe00dd2f..c240a3f8d163 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -25,6 +25,6 @@ struct flash_partitions {
25}; 25};
26 26
27extern void board_flash_init(struct flash_partitions [], 27extern void board_flash_init(struct flash_partitions [],
28 char chip_sel[][GPMC_CS_NUM]); 28 char chip_sel[][GPMC_CS_NUM], int nand_type);
29extern void board_nand_init(struct mtd_partition *nand_parts, 29extern void board_nand_init(struct mtd_partition *nand_parts,
30 u8 nr_parts, u8 cs); 30 u8 nr_parts, u8 cs, int nand_type);
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d8eb2cb7cbc7..a3fae5697a72 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -433,7 +433,7 @@ static void __init omap_ldp_init(void)
433 omap_serial_init(); 433 omap_serial_init();
434 usb_musb_init(&musb_board_data); 434 usb_musb_init(&musb_board_data);
435 board_nand_init(ldp_nand_partitions, 435 board_nand_init(ldp_nand_partitions,
436 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS); 436 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
437 437
438 omap2_hsmmc_init(mmc); 438 omap2_hsmmc_init(mmc);
439 /* link regulators to MMC adapters */ 439 /* link regulators to MMC adapters */
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c2a0fca4aa53..d4a115712290 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -30,6 +30,8 @@
30#include <linux/usb/otg.h> 30#include <linux/usb/otg.h>
31#include <linux/smsc911x.h> 31#include <linux/smsc911x.h>
32 32
33#include <linux/wl12xx.h>
34#include <linux/regulator/fixed.h>
33#include <linux/regulator/machine.h> 35#include <linux/regulator/machine.h>
34#include <linux/mmc/host.h> 36#include <linux/mmc/host.h>
35 37
@@ -58,6 +60,13 @@
58#define OMAP3EVM_ETHR_ID_REV 0x50 60#define OMAP3EVM_ETHR_ID_REV 0x50
59#define OMAP3EVM_ETHR_GPIO_IRQ 176 61#define OMAP3EVM_ETHR_GPIO_IRQ 176
60#define OMAP3EVM_SMSC911X_CS 5 62#define OMAP3EVM_SMSC911X_CS 5
63/*
64 * Eth Reset signal
65 * 64 = Generation 1 (<=RevD)
66 * 7 = Generation 2 (>=RevE)
67 */
68#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
69#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
61 70
62static u8 omap3_evm_version; 71static u8 omap3_evm_version;
63 72
@@ -124,10 +133,15 @@ static struct platform_device omap3evm_smsc911x_device = {
124 133
125static inline void __init omap3evm_init_smsc911x(void) 134static inline void __init omap3evm_init_smsc911x(void)
126{ 135{
127 int eth_cs; 136 int eth_cs, eth_rst;
128 struct clk *l3ck; 137 struct clk *l3ck;
129 unsigned int rate; 138 unsigned int rate;
130 139
140 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
141 eth_rst = OMAP3EVM_GEN1_ETHR_GPIO_RST;
142 else
143 eth_rst = OMAP3EVM_GEN2_ETHR_GPIO_RST;
144
131 eth_cs = OMAP3EVM_SMSC911X_CS; 145 eth_cs = OMAP3EVM_SMSC911X_CS;
132 146
133 l3ck = clk_get(NULL, "l3_ck"); 147 l3ck = clk_get(NULL, "l3_ck");
@@ -136,6 +150,27 @@ static inline void __init omap3evm_init_smsc911x(void)
136 else 150 else
137 rate = clk_get_rate(l3ck); 151 rate = clk_get_rate(l3ck);
138 152
153 /* Configure ethernet controller reset gpio */
154 if (cpu_is_omap3430()) {
155 if (gpio_request(eth_rst, "SMSC911x gpio") < 0) {
156 pr_err(KERN_ERR "Failed to request %d for smsc911x\n",
157 eth_rst);
158 return;
159 }
160
161 if (gpio_direction_output(eth_rst, 1) < 0) {
162 pr_err(KERN_ERR "Failed to set direction of %d for" \
163 " smsc911x\n", eth_rst);
164 return;
165 }
166 /* reset pulse to ethernet controller*/
167 usleep_range(150, 220);
168 gpio_set_value(eth_rst, 0);
169 usleep_range(150, 220);
170 gpio_set_value(eth_rst, 1);
171 usleep_range(1, 2);
172 }
173
139 if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) { 174 if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) {
140 printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n", 175 printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
141 OMAP3EVM_ETHR_GPIO_IRQ); 176 OMAP3EVM_ETHR_GPIO_IRQ);
@@ -235,9 +270,9 @@ static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
235 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0); 270 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
236 271
237 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) 272 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
238 gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); 273 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
239 else 274 else
240 gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); 275 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
241 276
242 lcd_enabled = 1; 277 lcd_enabled = 1;
243 return 0; 278 return 0;
@@ -248,9 +283,9 @@ static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
248 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1); 283 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
249 284
250 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) 285 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
251 gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); 286 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
252 else 287 else
253 gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); 288 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
254 289
255 lcd_enabled = 0; 290 lcd_enabled = 0;
256} 291}
@@ -289,7 +324,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
289 return -EINVAL; 324 return -EINVAL;
290 } 325 }
291 326
292 gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); 327 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
293 328
294 dvi_enabled = 1; 329 dvi_enabled = 1;
295 return 0; 330 return 0;
@@ -297,7 +332,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
297 332
298static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev) 333static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
299{ 334{
300 gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); 335 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
301 336
302 dvi_enabled = 0; 337 dvi_enabled = 0;
303} 338}
@@ -381,6 +416,16 @@ static struct omap2_hsmmc_info mmc[] = {
381 .gpio_cd = -EINVAL, 416 .gpio_cd = -EINVAL,
382 .gpio_wp = 63, 417 .gpio_wp = 63,
383 }, 418 },
419#ifdef CONFIG_WL12XX_PLATFORM_DATA
420 {
421 .name = "wl1271",
422 .mmc = 2,
423 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
424 .gpio_wp = -EINVAL,
425 .gpio_cd = -EINVAL,
426 .nonremovable = true,
427 },
428#endif
384 {} /* Terminator */ 429 {} /* Terminator */
385}; 430};
386 431
@@ -411,6 +456,8 @@ static struct platform_device leds_gpio = {
411static int omap3evm_twl_gpio_setup(struct device *dev, 456static int omap3evm_twl_gpio_setup(struct device *dev,
412 unsigned gpio, unsigned ngpio) 457 unsigned gpio, unsigned ngpio)
413{ 458{
459 int r;
460
414 /* gpio + 0 is "mmc0_cd" (input/IRQ) */ 461 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
415 omap_mux_init_gpio(63, OMAP_PIN_INPUT); 462 omap_mux_init_gpio(63, OMAP_PIN_INPUT);
416 mmc[0].gpio_cd = gpio + 0; 463 mmc[0].gpio_cd = gpio + 0;
@@ -426,8 +473,12 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
426 */ 473 */
427 474
428 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */ 475 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
429 gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); 476 r = gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
430 gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); 477 if (!r)
478 r = gpio_direction_output(gpio + TWL4030_GPIO_MAX,
479 (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) ? 1 : 0);
480 if (r)
481 printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
431 482
432 /* gpio + 7 == DVI Enable */ 483 /* gpio + 7 == DVI Enable */
433 gpio_request(gpio + 7, "EN_DVI"); 484 gpio_request(gpio + 7, "EN_DVI");
@@ -538,6 +589,69 @@ static struct regulator_init_data omap3_evm_vpll2 = {
538 .consumer_supplies = &omap3_evm_vpll2_supply, 589 .consumer_supplies = &omap3_evm_vpll2_supply,
539}; 590};
540 591
592/* ads7846 on SPI */
593static struct regulator_consumer_supply omap3evm_vio_supply =
594 REGULATOR_SUPPLY("vcc", "spi1.0");
595
596/* VIO for ads7846 */
597static struct regulator_init_data omap3evm_vio = {
598 .constraints = {
599 .min_uV = 1800000,
600 .max_uV = 1800000,
601 .apply_uV = true,
602 .valid_modes_mask = REGULATOR_MODE_NORMAL
603 | REGULATOR_MODE_STANDBY,
604 .valid_ops_mask = REGULATOR_CHANGE_MODE
605 | REGULATOR_CHANGE_STATUS,
606 },
607 .num_consumer_supplies = 1,
608 .consumer_supplies = &omap3evm_vio_supply,
609};
610
611#ifdef CONFIG_WL12XX_PLATFORM_DATA
612
613#define OMAP3EVM_WLAN_PMENA_GPIO (150)
614#define OMAP3EVM_WLAN_IRQ_GPIO (149)
615
616static struct regulator_consumer_supply omap3evm_vmmc2_supply = {
617 .supply = "vmmc",
618 .dev_name = "mmci-omap-hs.1",
619};
620
621/* VMMC2 for driving the WL12xx module */
622static struct regulator_init_data omap3evm_vmmc2 = {
623 .constraints = {
624 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
625 },
626 .num_consumer_supplies = 1,
627 .consumer_supplies = &omap3evm_vmmc2_supply,
628};
629
630static struct fixed_voltage_config omap3evm_vwlan = {
631 .supply_name = "vwl1271",
632 .microvolts = 1800000, /* 1.80V */
633 .gpio = OMAP3EVM_WLAN_PMENA_GPIO,
634 .startup_delay = 70000, /* 70ms */
635 .enable_high = 1,
636 .enabled_at_boot = 0,
637 .init_data = &omap3evm_vmmc2,
638};
639
640static struct platform_device omap3evm_vwlan_device = {
641 .name = "reg-fixed-voltage",
642 .id = 1,
643 .dev = {
644 .platform_data = &omap3evm_vwlan,
645 },
646};
647
648struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
649 .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
650 /* ref clock is 38.4 MHz */
651 .board_ref_clock = 2,
652};
653#endif
654
541static struct twl4030_platform_data omap3evm_twldata = { 655static struct twl4030_platform_data omap3evm_twldata = {
542 .irq_base = TWL4030_IRQ_BASE, 656 .irq_base = TWL4030_IRQ_BASE,
543 .irq_end = TWL4030_IRQ_END, 657 .irq_end = TWL4030_IRQ_END,
@@ -550,6 +664,7 @@ static struct twl4030_platform_data omap3evm_twldata = {
550 .codec = &omap3evm_codec_data, 664 .codec = &omap3evm_codec_data,
551 .vdac = &omap3_evm_vdac, 665 .vdac = &omap3_evm_vdac,
552 .vpll2 = &omap3_evm_vpll2, 666 .vpll2 = &omap3_evm_vpll2,
667 .vio = &omap3evm_vio,
553}; 668};
554 669
555static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = { 670static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = {
@@ -651,14 +766,61 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
651}; 766};
652 767
653#ifdef CONFIG_OMAP_MUX 768#ifdef CONFIG_OMAP_MUX
654static struct omap_board_mux board_mux[] __initdata = { 769static struct omap_board_mux omap35x_board_mux[] __initdata = {
770 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
771 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
772 OMAP_PIN_OFF_WAKEUPENABLE),
773 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
774 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
775 OMAP_PIN_OFF_WAKEUPENABLE),
776 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
777 OMAP_PIN_OFF_NONE),
778 OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
779 OMAP_PIN_OFF_NONE),
780#ifdef CONFIG_WL12XX_PLATFORM_DATA
781 /* WLAN IRQ - GPIO 149 */
782 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
783
784 /* WLAN POWER ENABLE - GPIO 150 */
785 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
786
787 /* MMC2 SDIO pin muxes for WL12xx */
788 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
789 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
790 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
791 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
792 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
793 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
794#endif
795 { .reg_offset = OMAP_MUX_TERMINATOR },
796};
797
798static struct omap_board_mux omap36x_board_mux[] __initdata = {
655 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | 799 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
656 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | 800 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
657 OMAP_PIN_OFF_WAKEUPENABLE), 801 OMAP_PIN_OFF_WAKEUPENABLE),
658 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | 802 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
659 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), 803 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
804 OMAP_PIN_OFF_WAKEUPENABLE),
805 /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
806 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
807 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
808 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
809 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
810 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
811 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
812 OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
813 OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
814 OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
815 OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
816 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
817 OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
818
660 { .reg_offset = OMAP_MUX_TERMINATOR }, 819 { .reg_offset = OMAP_MUX_TERMINATOR },
661}; 820};
821#else
822#define omap35x_board_mux NULL
823#define omap36x_board_mux NULL
662#endif 824#endif
663 825
664static struct omap_musb_board_data musb_board_data = { 826static struct omap_musb_board_data musb_board_data = {
@@ -670,7 +832,11 @@ static struct omap_musb_board_data musb_board_data = {
670static void __init omap3_evm_init(void) 832static void __init omap3_evm_init(void)
671{ 833{
672 omap3_evm_get_revision(); 834 omap3_evm_get_revision();
673 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 835
836 if (cpu_is_omap3630())
837 omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
838 else
839 omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
674 840
675 omap3_evm_i2c_init(); 841 omap3_evm_i2c_init();
676 842
@@ -714,6 +880,13 @@ static void __init omap3_evm_init(void)
714 ads7846_dev_init(); 880 ads7846_dev_init();
715 omap3evm_init_smsc911x(); 881 omap3evm_init_smsc911x();
716 omap3_evm_display_init(); 882 omap3_evm_display_init();
883
884#ifdef CONFIG_WL12XX_PLATFORM_DATA
885 /* WL12xx WLAN Init */
886 if (wl12xx_set_platform_data(&omap3evm_wlan_data))
887 pr_err("error setting wl12xx data\n");
888 platform_device_register(&omap3evm_vwlan_device);
889#endif
717} 890}
718 891
719MACHINE_START(OMAP3EVM, "OMAP3 EVM") 892MACHINE_START(OMAP3EVM, "OMAP3 EVM")
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index fca5b9e80c18..3dd241b95159 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -26,6 +26,8 @@
26#include <linux/usb/otg.h> 26#include <linux/usb/otg.h>
27#include <linux/i2c/twl.h> 27#include <linux/i2c/twl.h>
28#include <linux/regulator/machine.h> 28#include <linux/regulator/machine.h>
29#include <linux/regulator/fixed.h>
30#include <linux/wl12xx.h>
29 31
30#include <mach/hardware.h> 32#include <mach/hardware.h>
31#include <mach/omap4-common.h> 33#include <mach/omap4-common.h>
@@ -45,6 +47,8 @@
45 47
46#define GPIO_HUB_POWER 1 48#define GPIO_HUB_POWER 1
47#define GPIO_HUB_NRESET 62 49#define GPIO_HUB_NRESET 62
50#define GPIO_WIFI_PMENA 43
51#define GPIO_WIFI_IRQ 53
48 52
49static struct gpio_led gpio_leds[] = { 53static struct gpio_led gpio_leds[] = {
50 { 54 {
@@ -161,6 +165,15 @@ static struct omap2_hsmmc_info mmc[] = {
161 .gpio_wp = -EINVAL, 165 .gpio_wp = -EINVAL,
162 .gpio_cd = -EINVAL, 166 .gpio_cd = -EINVAL,
163 }, 167 },
168 {
169 .name = "wl1271",
170 .mmc = 5,
171 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
172 .gpio_wp = -EINVAL,
173 .gpio_cd = -EINVAL,
174 .ocr_mask = MMC_VDD_165_195,
175 .nonremovable = true,
176 },
164 {} /* Terminator */ 177 {} /* Terminator */
165}; 178};
166 179
@@ -171,6 +184,43 @@ static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
171 }, 184 },
172}; 185};
173 186
187static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
188 .supply = "vmmc",
189 .dev_name = "mmci-omap-hs.4",
190};
191
192static struct regulator_init_data panda_vmmc5 = {
193 .constraints = {
194 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
195 },
196 .num_consumer_supplies = 1,
197 .consumer_supplies = &omap4_panda_vmmc5_supply,
198};
199
200static struct fixed_voltage_config panda_vwlan = {
201 .supply_name = "vwl1271",
202 .microvolts = 1800000, /* 1.8V */
203 .gpio = GPIO_WIFI_PMENA,
204 .startup_delay = 70000, /* 70msec */
205 .enable_high = 1,
206 .enabled_at_boot = 0,
207 .init_data = &panda_vmmc5,
208};
209
210static struct platform_device omap_vwlan_device = {
211 .name = "reg-fixed-voltage",
212 .id = 1,
213 .dev = {
214 .platform_data = &panda_vwlan,
215 },
216};
217
218struct wl12xx_platform_data omap_panda_wlan_data __initdata = {
219 .irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
220 /* PANDA ref clock is 38.4 MHz */
221 .board_ref_clock = 2,
222};
223
174static int omap4_twl6030_hsmmc_late_init(struct device *dev) 224static int omap4_twl6030_hsmmc_late_init(struct device *dev)
175{ 225{
176 int ret = 0; 226 int ret = 0;
@@ -304,7 +354,6 @@ static struct regulator_init_data omap4_panda_vana = {
304 .constraints = { 354 .constraints = {
305 .min_uV = 2100000, 355 .min_uV = 2100000,
306 .max_uV = 2100000, 356 .max_uV = 2100000,
307 .apply_uV = true,
308 .valid_modes_mask = REGULATOR_MODE_NORMAL 357 .valid_modes_mask = REGULATOR_MODE_NORMAL
309 | REGULATOR_MODE_STANDBY, 358 | REGULATOR_MODE_STANDBY,
310 .valid_ops_mask = REGULATOR_CHANGE_MODE 359 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -316,7 +365,6 @@ static struct regulator_init_data omap4_panda_vcxio = {
316 .constraints = { 365 .constraints = {
317 .min_uV = 1800000, 366 .min_uV = 1800000,
318 .max_uV = 1800000, 367 .max_uV = 1800000,
319 .apply_uV = true,
320 .valid_modes_mask = REGULATOR_MODE_NORMAL 368 .valid_modes_mask = REGULATOR_MODE_NORMAL
321 | REGULATOR_MODE_STANDBY, 369 | REGULATOR_MODE_STANDBY,
322 .valid_ops_mask = REGULATOR_CHANGE_MODE 370 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -328,7 +376,6 @@ static struct regulator_init_data omap4_panda_vdac = {
328 .constraints = { 376 .constraints = {
329 .min_uV = 1800000, 377 .min_uV = 1800000,
330 .max_uV = 1800000, 378 .max_uV = 1800000,
331 .apply_uV = true,
332 .valid_modes_mask = REGULATOR_MODE_NORMAL 379 .valid_modes_mask = REGULATOR_MODE_NORMAL
333 | REGULATOR_MODE_STANDBY, 380 | REGULATOR_MODE_STANDBY,
334 .valid_ops_mask = REGULATOR_CHANGE_MODE 381 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -390,6 +437,19 @@ static int __init omap4_panda_i2c_init(void)
390 437
391#ifdef CONFIG_OMAP_MUX 438#ifdef CONFIG_OMAP_MUX
392static struct omap_board_mux board_mux[] __initdata = { 439static struct omap_board_mux board_mux[] __initdata = {
440 /* WLAN IRQ - GPIO 53 */
441 OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
442 /* WLAN POWER ENABLE - GPIO 43 */
443 OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
444 /* WLAN SDIO: MMC5 CMD */
445 OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
446 /* WLAN SDIO: MMC5 CLK */
447 OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
448 /* WLAN SDIO: MMC5 DAT[0-3] */
449 OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
450 OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
451 OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
452 OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
393 { .reg_offset = OMAP_MUX_TERMINATOR }, 453 { .reg_offset = OMAP_MUX_TERMINATOR },
394}; 454};
395#else 455#else
@@ -404,8 +464,12 @@ static void __init omap4_panda_init(void)
404 package = OMAP_PACKAGE_CBL; 464 package = OMAP_PACKAGE_CBL;
405 omap4_mux_init(board_mux, package); 465 omap4_mux_init(board_mux, package);
406 466
467 if (wl12xx_set_platform_data(&omap_panda_wlan_data))
468 pr_err("error setting wl12xx data\n");
469
407 omap4_panda_i2c_init(); 470 omap4_panda_i2c_init();
408 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); 471 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
472 platform_device_register(&omap_vwlan_device);
409 omap_serial_init(); 473 omap_serial_init();
410 omap4_twl6030_hsmmc_init(mmc); 474 omap4_twl6030_hsmmc_init(mmc);
411 omap4_ehci_init(); 475 omap4_ehci_init();
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 85d4170f30ab..7e3f1595d77b 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -16,6 +16,7 @@
16#include <linux/input.h> 16#include <linux/input.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/i2c/twl.h> 18#include <linux/i2c/twl.h>
19#include <linux/mtd/nand.h>
19 20
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
@@ -124,8 +125,8 @@ static void __init omap_zoom_init(void)
124 usb_ehci_init(&ehci_pdata); 125 usb_ehci_init(&ehci_pdata);
125 } 126 }
126 127
127 board_nand_init(zoom_nand_partitions, 128 board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
128 ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); 129 ZOOM_NAND_CS, NAND_BUSWIDTH_16);
129 zoom_debugboard_init(); 130 zoom_debugboard_init();
130 zoom_peripherals_init(); 131 zoom_peripherals_init();
131 zoom_display_init(); 132 zoom_display_init();
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index a781cd6795a4..e25364de028a 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,7 +97,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
97 u32 *field_val) 97 u32 *field_val)
98{ 98{
99 const struct clksel *clks; 99 const struct clksel *clks;
100 const struct clksel_rate *clkr, *max_clkr; 100 const struct clksel_rate *clkr, *max_clkr = NULL;
101 u8 max_div = 0; 101 u8 max_div = 0;
102 102
103 clks = _get_clksel_by_parent(clk, src_clk); 103 clks = _get_clksel_by_parent(clk, src_clk);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 71f099b85e7c..9ee876fd367a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -31,6 +31,7 @@
31#include <plat/dma.h> 31#include <plat/dma.h>
32#include <plat/omap_hwmod.h> 32#include <plat/omap_hwmod.h>
33#include <plat/omap_device.h> 33#include <plat/omap_device.h>
34#include <plat/omap4-keypad.h>
34 35
35#include "mux.h" 36#include "mux.h"
36#include "control.h" 37#include "control.h"
@@ -142,6 +143,46 @@ static inline void omap_init_camera(void)
142} 143}
143#endif 144#endif
144 145
146struct omap_device_pm_latency omap_keyboard_latency[] = {
147 {
148 .deactivate_func = omap_device_idle_hwmods,
149 .activate_func = omap_device_enable_hwmods,
150 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
151 },
152};
153
154int __init omap4_keyboard_init(struct omap4_keypad_platform_data
155 *sdp4430_keypad_data)
156{
157 struct omap_device *od;
158 struct omap_hwmod *oh;
159 struct omap4_keypad_platform_data *keypad_data;
160 unsigned int id = -1;
161 char *oh_name = "kbd";
162 char *name = "omap4-keypad";
163
164 oh = omap_hwmod_lookup(oh_name);
165 if (!oh) {
166 pr_err("Could not look up %s\n", oh_name);
167 return -ENODEV;
168 }
169
170 keypad_data = sdp4430_keypad_data;
171
172 od = omap_device_build(name, id, oh, keypad_data,
173 sizeof(struct omap4_keypad_platform_data),
174 omap_keyboard_latency,
175 ARRAY_SIZE(omap_keyboard_latency), 0);
176
177 if (IS_ERR(od)) {
178 WARN(1, "Cant build omap_device for %s:%s.\n",
179 name, oh->name);
180 return PTR_ERR(od);
181 }
182
183 return 0;
184}
185
145#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) 186#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
146 187
147#define MBOX_REG_SIZE 0x120 188#define MBOX_REG_SIZE 0x120
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 2bb29c160702..c1791d08ae56 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -12,6 +12,7 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/mtd/nand.h>
15 16
16#include <asm/mach/flash.h> 17#include <asm/mach/flash.h>
17 18
@@ -69,8 +70,10 @@ static int omap2_nand_gpmc_retime(void)
69 t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); 70 t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
70 71
71 /* Configure GPMC */ 72 /* Configure GPMC */
72 gpmc_cs_configure(gpmc_nand_data->cs, 73 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
73 GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize); 74 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
75 else
76 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
74 gpmc_cs_configure(gpmc_nand_data->cs, 77 gpmc_cs_configure(gpmc_nand_data->cs,
75 GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); 78 GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
76 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); 79 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 3a7d25fb00ef..d776ded9830d 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -94,7 +94,7 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
94} 94}
95 95
96static void set_onenand_cfg(void __iomem *onenand_base, int latency, 96static void set_onenand_cfg(void __iomem *onenand_base, int latency,
97 int sync_read, int sync_write, int hf) 97 int sync_read, int sync_write, int hf, int vhf)
98{ 98{
99 u32 reg; 99 u32 reg;
100 100
@@ -114,12 +114,57 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
114 reg |= ONENAND_SYS_CFG1_HF; 114 reg |= ONENAND_SYS_CFG1_HF;
115 else 115 else
116 reg &= ~ONENAND_SYS_CFG1_HF; 116 reg &= ~ONENAND_SYS_CFG1_HF;
117 if (vhf)
118 reg |= ONENAND_SYS_CFG1_VHF;
119 else
120 reg &= ~ONENAND_SYS_CFG1_VHF;
117 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); 121 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
118} 122}
119 123
124static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
125 void __iomem *onenand_base, bool *clk_dep)
126{
127 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
128 int freq = 0;
129
130 if (cfg->get_freq) {
131 struct onenand_freq_info fi;
132
133 fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
134 fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
135 fi.ver_id = ver;
136 freq = cfg->get_freq(&fi, clk_dep);
137 if (freq)
138 return freq;
139 }
140
141 switch ((ver >> 4) & 0xf) {
142 case 0:
143 freq = 40;
144 break;
145 case 1:
146 freq = 54;
147 break;
148 case 2:
149 freq = 66;
150 break;
151 case 3:
152 freq = 83;
153 break;
154 case 4:
155 freq = 104;
156 break;
157 default:
158 freq = 54;
159 break;
160 }
161
162 return freq;
163}
164
120static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, 165static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
121 void __iomem *onenand_base, 166 void __iomem *onenand_base,
122 int freq) 167 int *freq_ptr)
123{ 168{
124 struct gpmc_timings t; 169 struct gpmc_timings t;
125 const int t_cer = 15; 170 const int t_cer = 15;
@@ -130,10 +175,11 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
130 const int t_wph = 30; 175 const int t_wph = 30;
131 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; 176 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
132 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; 177 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
133 int first_time = 0, hf = 0, sync_read = 0, sync_write = 0; 178 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
134 int err, ticks_cez; 179 int err, ticks_cez;
135 int cs = cfg->cs; 180 int cs = cfg->cs, freq = *freq_ptr;
136 u32 reg; 181 u32 reg;
182 bool clk_dep = false;
137 183
138 if (cfg->flags & ONENAND_SYNC_READ) { 184 if (cfg->flags & ONENAND_SYNC_READ) {
139 sync_read = 1; 185 sync_read = 1;
@@ -148,27 +194,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
148 err = omap2_onenand_set_async_mode(cs, onenand_base); 194 err = omap2_onenand_set_async_mode(cs, onenand_base);
149 if (err) 195 if (err)
150 return err; 196 return err;
151 reg = readw(onenand_base + ONENAND_REG_VERSION_ID); 197 freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
152 switch ((reg >> 4) & 0xf) {
153 case 0:
154 freq = 40;
155 break;
156 case 1:
157 freq = 54;
158 break;
159 case 2:
160 freq = 66;
161 break;
162 case 3:
163 freq = 83;
164 break;
165 case 4:
166 freq = 104;
167 break;
168 default:
169 freq = 54;
170 break;
171 }
172 first_time = 1; 198 first_time = 1;
173 } 199 }
174 200
@@ -180,7 +206,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
180 t_avdh = 2; 206 t_avdh = 2;
181 t_ach = 3; 207 t_ach = 3;
182 t_aavdh = 6; 208 t_aavdh = 6;
183 t_rdyo = 9; 209 t_rdyo = 6;
184 break; 210 break;
185 case 83: 211 case 83:
186 min_gpmc_clk_period = 12000; /* 83 MHz */ 212 min_gpmc_clk_period = 12000; /* 83 MHz */
@@ -217,16 +243,36 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
217 gpmc_clk_ns = gpmc_ticks_to_ns(div); 243 gpmc_clk_ns = gpmc_ticks_to_ns(div);
218 if (gpmc_clk_ns < 15) /* >66Mhz */ 244 if (gpmc_clk_ns < 15) /* >66Mhz */
219 hf = 1; 245 hf = 1;
220 if (hf) 246 if (gpmc_clk_ns < 12) /* >83Mhz */
247 vhf = 1;
248 if (vhf)
249 latency = 8;
250 else if (hf)
221 latency = 6; 251 latency = 6;
222 else if (gpmc_clk_ns >= 25) /* 40 MHz*/ 252 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
223 latency = 3; 253 latency = 3;
224 else 254 else
225 latency = 4; 255 latency = 4;
226 256
257 if (clk_dep) {
258 if (gpmc_clk_ns < 12) { /* >83Mhz */
259 t_ces = 3;
260 t_avds = 4;
261 } else if (gpmc_clk_ns < 15) { /* >66Mhz */
262 t_ces = 5;
263 t_avds = 4;
264 } else if (gpmc_clk_ns < 25) { /* >40Mhz */
265 t_ces = 6;
266 t_avds = 5;
267 } else {
268 t_ces = 7;
269 t_avds = 7;
270 }
271 }
272
227 if (first_time) 273 if (first_time)
228 set_onenand_cfg(onenand_base, latency, 274 set_onenand_cfg(onenand_base, latency,
229 sync_read, sync_write, hf); 275 sync_read, sync_write, hf, vhf);
230 276
231 if (div == 1) { 277 if (div == 1) {
232 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); 278 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -264,6 +310,9 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
264 /* Read */ 310 /* Read */
265 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh)); 311 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
266 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach)); 312 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
313 /* Force at least 1 clk between AVD High to OE Low */
314 if (t.oe_on <= t.adv_rd_off)
315 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
267 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div); 316 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
268 t.oe_off = t.access + gpmc_round_ns_to_ticks(1); 317 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
269 t.cs_rd_off = t.oe_off; 318 t.cs_rd_off = t.oe_off;
@@ -317,18 +366,20 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
317 if (err) 366 if (err)
318 return err; 367 return err;
319 368
320 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf); 369 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
370
371 *freq_ptr = freq;
321 372
322 return 0; 373 return 0;
323} 374}
324 375
325static int gpmc_onenand_setup(void __iomem *onenand_base, int freq) 376static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
326{ 377{
327 struct device *dev = &gpmc_onenand_device.dev; 378 struct device *dev = &gpmc_onenand_device.dev;
328 379
329 /* Set sync timings in GPMC */ 380 /* Set sync timings in GPMC */
330 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, 381 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
331 freq) < 0) { 382 freq_ptr) < 0) {
332 dev_err(dev, "Unable to set synchronous mode\n"); 383 dev_err(dev, "Unable to set synchronous mode\n");
333 return -EINVAL; 384 return -EINVAL;
334 } 385 }
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 1b7b3e7d02f7..674174365f78 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -14,6 +14,7 @@
14 */ 14 */
15#undef DEBUG 15#undef DEBUG
16 16
17#include <linux/irq.h>
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/init.h> 19#include <linux/init.h>
19#include <linux/err.h> 20#include <linux/err.h>
@@ -22,6 +23,7 @@
22#include <linux/spinlock.h> 23#include <linux/spinlock.h>
23#include <linux/io.h> 24#include <linux/io.h>
24#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/interrupt.h>
25 27
26#include <asm/mach-types.h> 28#include <asm/mach-types.h>
27#include <plat/gpmc.h> 29#include <plat/gpmc.h>
@@ -58,7 +60,6 @@
58#define GPMC_CHUNK_SHIFT 24 /* 16 MB */ 60#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
59#define GPMC_SECTION_SHIFT 28 /* 128 MB */ 61#define GPMC_SECTION_SHIFT 28 /* 128 MB */
60 62
61#define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
62#define CS_NUM_SHIFT 24 63#define CS_NUM_SHIFT 24
63#define ENABLE_PREFETCH (0x1 << 7) 64#define ENABLE_PREFETCH (0x1 << 7)
64#define DMA_MPU_MODE 2 65#define DMA_MPU_MODE 2
@@ -100,6 +101,8 @@ static void __iomem *gpmc_base;
100 101
101static struct clk *gpmc_l3_clk; 102static struct clk *gpmc_l3_clk;
102 103
104static irqreturn_t gpmc_handle_irq(int irq, void *dev);
105
103static void gpmc_write_reg(int idx, u32 val) 106static void gpmc_write_reg(int idx, u32 val)
104{ 107{
105 __raw_writel(val, gpmc_base + idx); 108 __raw_writel(val, gpmc_base + idx);
@@ -497,6 +500,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
497 u32 regval = 0; 500 u32 regval = 0;
498 501
499 switch (cmd) { 502 switch (cmd) {
503 case GPMC_ENABLE_IRQ:
504 gpmc_write_reg(GPMC_IRQENABLE, wval);
505 break;
506
500 case GPMC_SET_IRQ_STATUS: 507 case GPMC_SET_IRQ_STATUS:
501 gpmc_write_reg(GPMC_IRQSTATUS, wval); 508 gpmc_write_reg(GPMC_IRQSTATUS, wval);
502 break; 509 break;
@@ -598,15 +605,19 @@ EXPORT_SYMBOL(gpmc_nand_write);
598/** 605/**
599 * gpmc_prefetch_enable - configures and starts prefetch transfer 606 * gpmc_prefetch_enable - configures and starts prefetch transfer
600 * @cs: cs (chip select) number 607 * @cs: cs (chip select) number
608 * @fifo_th: fifo threshold to be used for read/ write
601 * @dma_mode: dma mode enable (1) or disable (0) 609 * @dma_mode: dma mode enable (1) or disable (0)
602 * @u32_count: number of bytes to be transferred 610 * @u32_count: number of bytes to be transferred
603 * @is_write: prefetch read(0) or write post(1) mode 611 * @is_write: prefetch read(0) or write post(1) mode
604 */ 612 */
605int gpmc_prefetch_enable(int cs, int dma_mode, 613int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
606 unsigned int u32_count, int is_write) 614 unsigned int u32_count, int is_write)
607{ 615{
608 616
609 if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { 617 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
618 pr_err("gpmc: fifo threshold is not supported\n");
619 return -1;
620 } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
610 /* Set the amount of bytes to be prefetched */ 621 /* Set the amount of bytes to be prefetched */
611 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); 622 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
612 623
@@ -614,7 +625,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode,
614 * enable the engine. Set which cs is has requested for. 625 * enable the engine. Set which cs is has requested for.
615 */ 626 */
616 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | 627 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
617 PREFETCH_FIFOTHRESHOLD | 628 PREFETCH_FIFOTHRESHOLD(fifo_th) |
618 ENABLE_PREFETCH | 629 ENABLE_PREFETCH |
619 (dma_mode << DMA_MPU_MODE) | 630 (dma_mode << DMA_MPU_MODE) |
620 (0x1 & is_write))); 631 (0x1 & is_write)));
@@ -678,9 +689,10 @@ static void __init gpmc_mem_init(void)
678 } 689 }
679} 690}
680 691
681void __init gpmc_init(void) 692static int __init gpmc_init(void)
682{ 693{
683 u32 l; 694 u32 l, irq;
695 int cs, ret = -EINVAL;
684 char *ck = NULL; 696 char *ck = NULL;
685 697
686 if (cpu_is_omap24xx()) { 698 if (cpu_is_omap24xx()) {
@@ -698,7 +710,7 @@ void __init gpmc_init(void)
698 } 710 }
699 711
700 if (WARN_ON(!ck)) 712 if (WARN_ON(!ck))
701 return; 713 return ret;
702 714
703 gpmc_l3_clk = clk_get(NULL, ck); 715 gpmc_l3_clk = clk_get(NULL, ck);
704 if (IS_ERR(gpmc_l3_clk)) { 716 if (IS_ERR(gpmc_l3_clk)) {
@@ -723,6 +735,36 @@ void __init gpmc_init(void)
723 l |= (0x02 << 3) | (1 << 0); 735 l |= (0x02 << 3) | (1 << 0);
724 gpmc_write_reg(GPMC_SYSCONFIG, l); 736 gpmc_write_reg(GPMC_SYSCONFIG, l);
725 gpmc_mem_init(); 737 gpmc_mem_init();
738
739 /* initalize the irq_chained */
740 irq = OMAP_GPMC_IRQ_BASE;
741 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
742 set_irq_handler(irq, handle_simple_irq);
743 set_irq_flags(irq, IRQF_VALID);
744 irq++;
745 }
746
747 ret = request_irq(INT_34XX_GPMC_IRQ,
748 gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
749 if (ret)
750 pr_err("gpmc: irq-%d could not claim: err %d\n",
751 INT_34XX_GPMC_IRQ, ret);
752 return ret;
753}
754postcore_initcall(gpmc_init);
755
756static irqreturn_t gpmc_handle_irq(int irq, void *dev)
757{
758 u8 cs;
759
760 if (irq != INT_34XX_GPMC_IRQ)
761 return IRQ_HANDLED;
762 /* check cs to invoke the irq */
763 cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
764 if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
765 generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
766
767 return IRQ_HANDLED;
726} 768}
727 769
728#ifdef CONFIG_ARCH_OMAP3 770#ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 34272e4863fd..5496bc7d40ad 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -350,6 +350,11 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
350 mmc->slots[0].after_set_reg = NULL; 350 mmc->slots[0].after_set_reg = NULL;
351 } 351 }
352 break; 352 break;
353 case 4:
354 case 5:
355 mmc->slots[0].before_set_reg = NULL;
356 mmc->slots[0].after_set_reg = NULL;
357 break;
353 default: 358 default:
354 pr_err("MMC%d configuration not supported!\n", c->mmc); 359 pr_err("MMC%d configuration not supported!\n", c->mmc);
355 kfree(mmc); 360 kfree(mmc);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 5c25f1b55235..3168b17bc264 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -6,7 +6,7 @@
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com> 7 * Written by Tony Lindgren <tony@atomide.com>
8 * 8 *
9 * Copyright (C) 2009 Texas Instruments 9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
@@ -328,7 +328,7 @@ static void __init omap4_check_revision(void)
328 */ 328 */
329 idcode = read_tap_reg(OMAP_TAP_IDCODE); 329 idcode = read_tap_reg(OMAP_TAP_IDCODE);
330 hawkeye = (idcode >> 12) & 0xffff; 330 hawkeye = (idcode >> 12) & 0xffff;
331 rev = (idcode >> 28) & 0xff; 331 rev = (idcode >> 28) & 0xf;
332 332
333 /* 333 /*
334 * Few initial ES2.0 samples IDCODE is same as ES1.0 334 * Few initial ES2.0 samples IDCODE is same as ES1.0
@@ -347,22 +347,31 @@ static void __init omap4_check_revision(void)
347 omap_chip.oc |= CHIP_IS_OMAP4430ES1; 347 omap_chip.oc |= CHIP_IS_OMAP4430ES1;
348 break; 348 break;
349 case 1: 349 case 1:
350 default:
350 omap_revision = OMAP4430_REV_ES2_0; 351 omap_revision = OMAP4430_REV_ES2_0;
351 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 352 omap_chip.oc |= CHIP_IS_OMAP4430ES2;
353 }
354 break;
355 case 0xb95c:
356 switch (rev) {
357 case 3:
358 omap_revision = OMAP4430_REV_ES2_1;
359 omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
352 break; 360 break;
361 case 4:
353 default: 362 default:
354 omap_revision = OMAP4430_REV_ES2_0; 363 omap_revision = OMAP4430_REV_ES2_2;
355 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 364 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
356 } 365 }
357 break; 366 break;
358 default: 367 default:
359 /* Unknown default to latest silicon rev as default*/ 368 /* Unknown default to latest silicon rev as default */
360 omap_revision = OMAP4430_REV_ES2_0; 369 omap_revision = OMAP4430_REV_ES2_2;
361 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 370 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
362 } 371 }
363 372
364 pr_info("OMAP%04x ES%d.0\n", 373 pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
365 omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); 374 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
366} 375}
367 376
368#define OMAP3_SHOW_FEATURE(feat) \ 377#define OMAP3_SHOW_FEATURE(feat) \
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index b8b49e4ae928..657f3c84687c 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -30,7 +30,6 @@
30 30
31#include <plat/sram.h> 31#include <plat/sram.h>
32#include <plat/sdrc.h> 32#include <plat/sdrc.h>
33#include <plat/gpmc.h>
34#include <plat/serial.h> 33#include <plat/serial.h>
35 34
36#include "clock2xxx.h" 35#include "clock2xxx.h"
@@ -422,7 +421,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
422 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 421 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
423 _omap2_init_reprogram_sdrc(); 422 _omap2_init_reprogram_sdrc();
424 } 423 }
425 gpmc_init();
426 424
427 omap_irq_base_init(); 425 omap_irq_base_init();
428} 426}
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index be99438d385e..8198bb6cdb5e 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -5,7 +5,7 @@
5 * 5 *
6 * Copyright (C) 2004, 2008 Nokia Corporation 6 * Copyright (C) 2004, 2008 Nokia Corporation
7 * 7 *
8 * Copyright (C) 2009 Texas Instruments. 8 * Copyright (C) 2009-11 Texas Instruments.
9 * 9 *
10 * Written by Tony Lindgren <tony.lindgren@nokia.com> 10 * Written by Tony Lindgren <tony.lindgren@nokia.com>
11 * 11 *
@@ -405,8 +405,10 @@ IS_OMAP_TYPE(3517, 0x3517)
405#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) 405#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
406 406
407#define OMAP443X_CLASS 0x44300044 407#define OMAP443X_CLASS 0x44300044
408#define OMAP4430_REV_ES1_0 OMAP443X_CLASS 408#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
409#define OMAP4430_REV_ES2_0 0x44301044 409#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
410#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
411#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
410 412
411/* 413/*
412 * omap_chip bits 414 * omap_chip bits
@@ -434,12 +436,16 @@ IS_OMAP_TYPE(3517, 0x3517)
434#define CHIP_IS_OMAP3630ES1_1 (1 << 9) 436#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
435#define CHIP_IS_OMAP3630ES1_2 (1 << 10) 437#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
436#define CHIP_IS_OMAP4430ES2 (1 << 11) 438#define CHIP_IS_OMAP4430ES2 (1 << 11)
439#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
440#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
437#define CHIP_IS_TI816X (1 << 14) 441#define CHIP_IS_TI816X (1 << 14)
438 442
439#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 443#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
440 444
441#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ 445#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
442 CHIP_IS_OMAP4430ES2) 446 CHIP_IS_OMAP4430ES2 | \
447 CHIP_IS_OMAP4430ES2_1 | \
448 CHIP_IS_OMAP4430ES2_2)
443 449
444/* 450/*
445 * "GE" here represents "greater than or equal to" in terms of ES 451 * "GE" here represents "greater than or equal to" in terms of ES
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 85ded598853e..12b316165037 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -41,6 +41,8 @@
41#define GPMC_NAND_ADDRESS 0x0000000b 41#define GPMC_NAND_ADDRESS 0x0000000b
42#define GPMC_NAND_DATA 0x0000000c 42#define GPMC_NAND_DATA 0x0000000c
43 43
44#define GPMC_ENABLE_IRQ 0x0000000d
45
44/* ECC commands */ 46/* ECC commands */
45#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ 47#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
46#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ 48#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
@@ -78,6 +80,19 @@
78#define WR_RD_PIN_MONITORING 0x00600000 80#define WR_RD_PIN_MONITORING 0x00600000
79#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) 81#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
80#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) 82#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
83#define GPMC_IRQ_FIFOEVENTENABLE 0x01
84#define GPMC_IRQ_COUNT_EVENT 0x02
85
86#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
87#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
88
89enum omap_ecc {
90 /* 1-bit ecc: stored at end of spare area */
91 OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
92 OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
93 /* 1-bit ecc: stored at begining of spare area as romcode */
94 OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
95};
81 96
82/* 97/*
83 * Note that all values in this struct are in nanoseconds except sync_clk 98 * Note that all values in this struct are in nanoseconds except sync_clk
@@ -130,12 +145,11 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
130extern void gpmc_cs_free(int cs); 145extern void gpmc_cs_free(int cs);
131extern int gpmc_cs_set_reserved(int cs, int reserved); 146extern int gpmc_cs_set_reserved(int cs, int reserved);
132extern int gpmc_cs_reserved(int cs); 147extern int gpmc_cs_reserved(int cs);
133extern int gpmc_prefetch_enable(int cs, int dma_mode, 148extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
134 unsigned int u32_count, int is_write); 149 unsigned int u32_count, int is_write);
135extern int gpmc_prefetch_reset(int cs); 150extern int gpmc_prefetch_reset(int cs);
136extern void omap3_gpmc_save_context(void); 151extern void omap3_gpmc_save_context(void);
137extern void omap3_gpmc_restore_context(void); 152extern void omap3_gpmc_restore_context(void);
138extern void gpmc_init(void);
139extern int gpmc_read_status(int cmd); 153extern int gpmc_read_status(int cmd);
140extern int gpmc_cs_configure(int cs, int cmd, int wval); 154extern int gpmc_cs_configure(int cs, int cmd, int wval);
141extern int gpmc_nand_read(int cs, int cmd); 155extern int gpmc_nand_read(int cs, int cmd);
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 69230d685538..19cbb5e9ece2 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -154,6 +154,8 @@ extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
154extern void flush_iotlb_all(struct iommu *obj); 154extern void flush_iotlb_all(struct iommu *obj);
155 155
156extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); 156extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
157extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd,
158 u32 **ppte);
157extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); 159extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
158 160
159extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); 161extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 2910de921c52..1b911681e911 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -318,6 +318,7 @@
318#define INT_34XX_PRCM_MPU_IRQ 11 318#define INT_34XX_PRCM_MPU_IRQ 11
319#define INT_34XX_MCBSP1_IRQ 16 319#define INT_34XX_MCBSP1_IRQ 16
320#define INT_34XX_MCBSP2_IRQ 17 320#define INT_34XX_MCBSP2_IRQ 17
321#define INT_34XX_GPMC_IRQ 20
321#define INT_34XX_MCBSP3_IRQ 22 322#define INT_34XX_MCBSP3_IRQ 22
322#define INT_34XX_MCBSP4_IRQ 23 323#define INT_34XX_MCBSP4_IRQ 23
323#define INT_34XX_CAM_IRQ 24 324#define INT_34XX_CAM_IRQ 24
@@ -411,7 +412,13 @@
411#define TWL_IRQ_END TWL6030_IRQ_END 412#define TWL_IRQ_END TWL6030_IRQ_END
412#endif 413#endif
413 414
414#define NR_IRQS TWL_IRQ_END 415/* GPMC related */
416#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END)
417#define OMAP_GPMC_NR_IRQS 7
418#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
419
420
421#define NR_IRQS OMAP_GPMC_IRQ_END
415 422
416#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 423#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
417 424
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 6562cd082bb1..d86d1ecf0068 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -8,8 +8,16 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <plat/gpmc.h>
11#include <linux/mtd/partitions.h> 12#include <linux/mtd/partitions.h>
12 13
14enum nand_io {
15 NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
16 NAND_OMAP_POLLED, /* polled mode, without prefetch */
17 NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
18 NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
19};
20
13struct omap_nand_platform_data { 21struct omap_nand_platform_data {
14 unsigned int options; 22 unsigned int options;
15 int cs; 23 int cs;
@@ -20,8 +28,11 @@ struct omap_nand_platform_data {
20 int (*nand_setup)(void); 28 int (*nand_setup)(void);
21 int (*dev_ready)(struct omap_nand_platform_data *); 29 int (*dev_ready)(struct omap_nand_platform_data *);
22 int dma_channel; 30 int dma_channel;
31 int gpmc_irq;
32 enum nand_io xfer_type;
23 unsigned long phys_base; 33 unsigned long phys_base;
24 int devsize; 34 int devsize;
35 enum omap_ecc ecc_opt;
25}; 36};
26 37
27/* minimum size for IO mapping */ 38/* minimum size for IO mapping */
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index affe87e9ece7..cbe897ca7f9e 100644
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
@@ -15,12 +15,20 @@
15#define ONENAND_SYNC_READ (1 << 0) 15#define ONENAND_SYNC_READ (1 << 0)
16#define ONENAND_SYNC_READWRITE (1 << 1) 16#define ONENAND_SYNC_READWRITE (1 << 1)
17 17
18struct onenand_freq_info {
19 u16 maf_id;
20 u16 dev_id;
21 u16 ver_id;
22};
23
18struct omap_onenand_platform_data { 24struct omap_onenand_platform_data {
19 int cs; 25 int cs;
20 int gpio_irq; 26 int gpio_irq;
21 struct mtd_partition *parts; 27 struct mtd_partition *parts;
22 int nr_parts; 28 int nr_parts;
23 int (*onenand_setup)(void __iomem *, int freq); 29 int (*onenand_setup)(void __iomem *, int *freq_ptr);
30 int (*get_freq)(const struct onenand_freq_info *freq_info,
31 bool *clk_dep);
24 int dma_channel; 32 int dma_channel;
25 u8 flags; 33 u8 flags;
26 u8 regulator_can_sleep; 34 u8 regulator_can_sleep;
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index aedcb3be4e66..9d80064e979b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -405,20 +405,6 @@ static inline int omap34xx_sram_init(void)
405} 405}
406#endif 406#endif
407 407
408#ifdef CONFIG_ARCH_OMAP4
409static int __init omap44xx_sram_init(void)
410{
411 printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
412
413 return -ENODEV;
414}
415#else
416static inline int omap44xx_sram_init(void)
417{
418 return 0;
419}
420#endif
421
422int __init omap_sram_init(void) 408int __init omap_sram_init(void)
423{ 409{
424 omap_detect_sram(); 410 omap_detect_sram();
@@ -432,8 +418,6 @@ int __init omap_sram_init(void)
432 omap243x_sram_init(); 418 omap243x_sram_init();
433 else if (cpu_is_omap34xx()) 419 else if (cpu_is_omap34xx())
434 omap34xx_sram_init(); 420 omap34xx_sram_init();
435 else if (cpu_is_omap44xx())
436 omap44xx_sram_init();
437 421
438 return 0; 422 return 0;
439} 423}
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 078fdf11af03..8c42573f42ea 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -260,7 +260,7 @@ static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
260 return ret; 260 return ret;
261} 261}
262 262
263static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, 263static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
264 int vdd) 264 int vdd)
265{ 265{
266 struct omap_hsmmc_host *host = 266 struct omap_hsmmc_host *host =
@@ -316,6 +316,12 @@ static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
316 return ret; 316 return ret;
317} 317}
318 318
319static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
320 int vdd)
321{
322 return 0;
323}
324
319static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, 325static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
320 int vdd, int cardsleep) 326 int vdd, int cardsleep)
321{ 327{
@@ -326,7 +332,7 @@ static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
326 return regulator_set_mode(host->vcc, mode); 332 return regulator_set_mode(host->vcc, mode);
327} 333}
328 334
329static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, 335static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
330 int vdd, int cardsleep) 336 int vdd, int cardsleep)
331{ 337{
332 struct omap_hsmmc_host *host = 338 struct omap_hsmmc_host *host =
@@ -365,6 +371,12 @@ static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
365 return regulator_enable(host->vcc_aux); 371 return regulator_enable(host->vcc_aux);
366} 372}
367 373
374static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
375 int vdd, int cardsleep)
376{
377 return 0;
378}
379
368static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 380static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
369{ 381{
370 struct regulator *reg; 382 struct regulator *reg;
@@ -379,10 +391,14 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
379 break; 391 break;
380 case OMAP_MMC2_DEVID: 392 case OMAP_MMC2_DEVID:
381 case OMAP_MMC3_DEVID: 393 case OMAP_MMC3_DEVID:
394 case OMAP_MMC5_DEVID:
382 /* Off-chip level shifting, or none */ 395 /* Off-chip level shifting, or none */
383 mmc_slot(host).set_power = omap_hsmmc_23_set_power; 396 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
384 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep; 397 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
385 break; 398 break;
399 case OMAP_MMC4_DEVID:
400 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
401 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
386 default: 402 default:
387 pr_err("MMC%d configuration not supported!\n", host->id); 403 pr_err("MMC%d configuration not supported!\n", host->id);
388 return -EINVAL; 404 return -EINVAL;
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index c89592239bc7..178e2006063d 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -106,23 +106,6 @@ config MTD_NAND_OMAP2
106 help 106 help
107 Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms. 107 Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms.
108 108
109config MTD_NAND_OMAP_PREFETCH
110 bool "GPMC prefetch support for NAND Flash device"
111 depends on MTD_NAND_OMAP2
112 default y
113 help
114 The NAND device can be accessed for Read/Write using GPMC PREFETCH engine
115 to improve the performance.
116
117config MTD_NAND_OMAP_PREFETCH_DMA
118 depends on MTD_NAND_OMAP_PREFETCH
119 bool "DMA mode"
120 default n
121 help
122 The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode
123 or in DMA interrupt mode.
124 Say y for DMA mode or MPU mode will be used
125
126config MTD_NAND_IDS 109config MTD_NAND_IDS
127 tristate 110 tristate
128 111
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 15682ec8530e..4e33972ad17a 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -11,6 +11,7 @@
11#include <linux/platform_device.h> 11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h> 12#include <linux/dma-mapping.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/interrupt.h>
14#include <linux/jiffies.h> 15#include <linux/jiffies.h>
15#include <linux/sched.h> 16#include <linux/sched.h>
16#include <linux/mtd/mtd.h> 17#include <linux/mtd/mtd.h>
@@ -24,6 +25,7 @@
24#include <plat/nand.h> 25#include <plat/nand.h>
25 26
26#define DRIVER_NAME "omap2-nand" 27#define DRIVER_NAME "omap2-nand"
28#define OMAP_NAND_TIMEOUT_MS 5000
27 29
28#define NAND_Ecc_P1e (1 << 0) 30#define NAND_Ecc_P1e (1 << 0)
29#define NAND_Ecc_P2e (1 << 1) 31#define NAND_Ecc_P2e (1 << 1)
@@ -96,26 +98,19 @@
96static const char *part_probes[] = { "cmdlinepart", NULL }; 98static const char *part_probes[] = { "cmdlinepart", NULL };
97#endif 99#endif
98 100
99#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH 101/* oob info generated runtime depending on ecc algorithm and layout selected */
100static int use_prefetch = 1; 102static struct nand_ecclayout omap_oobinfo;
101 103/* Define some generic bad / good block scan pattern which are used
102/* "modprobe ... use_prefetch=0" etc */ 104 * while scanning a device for factory marked good / bad blocks
103module_param(use_prefetch, bool, 0); 105 */
104MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH"); 106static uint8_t scan_ff_pattern[] = { 0xff };
105 107static struct nand_bbt_descr bb_descrip_flashbased = {
106#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA 108 .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
107static int use_dma = 1; 109 .offs = 0,
110 .len = 1,
111 .pattern = scan_ff_pattern,
112};
108 113
109/* "modprobe ... use_dma=0" etc */
110module_param(use_dma, bool, 0);
111MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
112#else
113static const int use_dma;
114#endif
115#else
116const int use_prefetch;
117static const int use_dma;
118#endif
119 114
120struct omap_nand_info { 115struct omap_nand_info {
121 struct nand_hw_control controller; 116 struct nand_hw_control controller;
@@ -129,6 +124,13 @@ struct omap_nand_info {
129 unsigned long phys_base; 124 unsigned long phys_base;
130 struct completion comp; 125 struct completion comp;
131 int dma_ch; 126 int dma_ch;
127 int gpmc_irq;
128 enum {
129 OMAP_NAND_IO_READ = 0, /* read */
130 OMAP_NAND_IO_WRITE, /* write */
131 } iomode;
132 u_char *buf;
133 int buf_len;
132}; 134};
133 135
134/** 136/**
@@ -256,7 +258,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
256 } 258 }
257 259
258 /* configure and start prefetch transfer */ 260 /* configure and start prefetch transfer */
259 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); 261 ret = gpmc_prefetch_enable(info->gpmc_cs,
262 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
260 if (ret) { 263 if (ret) {
261 /* PFPW engine is busy, use cpu copy method */ 264 /* PFPW engine is busy, use cpu copy method */
262 if (info->nand.options & NAND_BUSWIDTH_16) 265 if (info->nand.options & NAND_BUSWIDTH_16)
@@ -288,9 +291,10 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
288{ 291{
289 struct omap_nand_info *info = container_of(mtd, 292 struct omap_nand_info *info = container_of(mtd,
290 struct omap_nand_info, mtd); 293 struct omap_nand_info, mtd);
291 uint32_t pref_count = 0, w_count = 0; 294 uint32_t w_count = 0;
292 int i = 0, ret = 0; 295 int i = 0, ret = 0;
293 u16 *p; 296 u16 *p;
297 unsigned long tim, limit;
294 298
295 /* take care of subpage writes */ 299 /* take care of subpage writes */
296 if (len % 2 != 0) { 300 if (len % 2 != 0) {
@@ -300,7 +304,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
300 } 304 }
301 305
302 /* configure and start prefetch transfer */ 306 /* configure and start prefetch transfer */
303 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); 307 ret = gpmc_prefetch_enable(info->gpmc_cs,
308 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
304 if (ret) { 309 if (ret) {
305 /* PFPW engine is busy, use cpu copy method */ 310 /* PFPW engine is busy, use cpu copy method */
306 if (info->nand.options & NAND_BUSWIDTH_16) 311 if (info->nand.options & NAND_BUSWIDTH_16)
@@ -316,15 +321,17 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
316 iowrite16(*p++, info->nand.IO_ADDR_W); 321 iowrite16(*p++, info->nand.IO_ADDR_W);
317 } 322 }
318 /* wait for data to flushed-out before reset the prefetch */ 323 /* wait for data to flushed-out before reset the prefetch */
319 do { 324 tim = 0;
320 pref_count = gpmc_read_status(GPMC_PREFETCH_COUNT); 325 limit = (loops_per_jiffy *
321 } while (pref_count); 326 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
327 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
328 cpu_relax();
329
322 /* disable and stop the PFPW engine */ 330 /* disable and stop the PFPW engine */
323 gpmc_prefetch_reset(info->gpmc_cs); 331 gpmc_prefetch_reset(info->gpmc_cs);
324 } 332 }
325} 333}
326 334
327#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
328/* 335/*
329 * omap_nand_dma_cb: callback on the completion of dma transfer 336 * omap_nand_dma_cb: callback on the completion of dma transfer
330 * @lch: logical channel 337 * @lch: logical channel
@@ -348,14 +355,15 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
348{ 355{
349 struct omap_nand_info *info = container_of(mtd, 356 struct omap_nand_info *info = container_of(mtd,
350 struct omap_nand_info, mtd); 357 struct omap_nand_info, mtd);
351 uint32_t prefetch_status = 0;
352 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : 358 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
353 DMA_FROM_DEVICE; 359 DMA_FROM_DEVICE;
354 dma_addr_t dma_addr; 360 dma_addr_t dma_addr;
355 int ret; 361 int ret;
362 unsigned long tim, limit;
356 363
357 /* The fifo depth is 64 bytes. We have a sync at each frame and frame 364 /* The fifo depth is 64 bytes max.
358 * length is 64 bytes. 365 * But configure the FIFO-threahold to 32 to get a sync at each frame
366 * and frame length is 32 bytes.
359 */ 367 */
360 int buf_len = len >> 6; 368 int buf_len = len >> 6;
361 369
@@ -396,9 +404,10 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
396 OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC); 404 OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
397 } 405 }
398 /* configure and start prefetch transfer */ 406 /* configure and start prefetch transfer */
399 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write); 407 ret = gpmc_prefetch_enable(info->gpmc_cs,
408 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
400 if (ret) 409 if (ret)
401 /* PFPW engine is busy, use cpu copy methode */ 410 /* PFPW engine is busy, use cpu copy method */
402 goto out_copy; 411 goto out_copy;
403 412
404 init_completion(&info->comp); 413 init_completion(&info->comp);
@@ -407,10 +416,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
407 416
408 /* setup and start DMA using dma_addr */ 417 /* setup and start DMA using dma_addr */
409 wait_for_completion(&info->comp); 418 wait_for_completion(&info->comp);
419 tim = 0;
420 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
421 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
422 cpu_relax();
410 423
411 do {
412 prefetch_status = gpmc_read_status(GPMC_PREFETCH_COUNT);
413 } while (prefetch_status);
414 /* disable and stop the PFPW engine */ 424 /* disable and stop the PFPW engine */
415 gpmc_prefetch_reset(info->gpmc_cs); 425 gpmc_prefetch_reset(info->gpmc_cs);
416 426
@@ -426,14 +436,6 @@ out_copy:
426 : omap_write_buf8(mtd, (u_char *) addr, len); 436 : omap_write_buf8(mtd, (u_char *) addr, len);
427 return 0; 437 return 0;
428} 438}
429#else
430static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) {}
431static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
432 unsigned int len, int is_write)
433{
434 return 0;
435}
436#endif
437 439
438/** 440/**
439 * omap_read_buf_dma_pref - read data from NAND controller into buffer 441 * omap_read_buf_dma_pref - read data from NAND controller into buffer
@@ -466,6 +468,157 @@ static void omap_write_buf_dma_pref(struct mtd_info *mtd,
466 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); 468 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
467} 469}
468 470
471/*
472 * omap_nand_irq - GMPC irq handler
473 * @this_irq: gpmc irq number
474 * @dev: omap_nand_info structure pointer is passed here
475 */
476static irqreturn_t omap_nand_irq(int this_irq, void *dev)
477{
478 struct omap_nand_info *info = (struct omap_nand_info *) dev;
479 u32 bytes;
480 u32 irq_stat;
481
482 irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
483 bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
484 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
485 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
486 if (irq_stat & 0x2)
487 goto done;
488
489 if (info->buf_len && (info->buf_len < bytes))
490 bytes = info->buf_len;
491 else if (!info->buf_len)
492 bytes = 0;
493 iowrite32_rep(info->nand.IO_ADDR_W,
494 (u32 *)info->buf, bytes >> 2);
495 info->buf = info->buf + bytes;
496 info->buf_len -= bytes;
497
498 } else {
499 ioread32_rep(info->nand.IO_ADDR_R,
500 (u32 *)info->buf, bytes >> 2);
501 info->buf = info->buf + bytes;
502
503 if (irq_stat & 0x2)
504 goto done;
505 }
506 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
507
508 return IRQ_HANDLED;
509
510done:
511 complete(&info->comp);
512 /* disable irq */
513 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
514
515 /* clear status */
516 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
517
518 return IRQ_HANDLED;
519}
520
521/*
522 * omap_read_buf_irq_pref - read data from NAND controller into buffer
523 * @mtd: MTD device structure
524 * @buf: buffer to store date
525 * @len: number of bytes to read
526 */
527static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
528{
529 struct omap_nand_info *info = container_of(mtd,
530 struct omap_nand_info, mtd);
531 int ret = 0;
532
533 if (len <= mtd->oobsize) {
534 omap_read_buf_pref(mtd, buf, len);
535 return;
536 }
537
538 info->iomode = OMAP_NAND_IO_READ;
539 info->buf = buf;
540 init_completion(&info->comp);
541
542 /* configure and start prefetch transfer */
543 ret = gpmc_prefetch_enable(info->gpmc_cs,
544 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
545 if (ret)
546 /* PFPW engine is busy, use cpu copy method */
547 goto out_copy;
548
549 info->buf_len = len;
550 /* enable irq */
551 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
552 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
553
554 /* waiting for read to complete */
555 wait_for_completion(&info->comp);
556
557 /* disable and stop the PFPW engine */
558 gpmc_prefetch_reset(info->gpmc_cs);
559 return;
560
561out_copy:
562 if (info->nand.options & NAND_BUSWIDTH_16)
563 omap_read_buf16(mtd, buf, len);
564 else
565 omap_read_buf8(mtd, buf, len);
566}
567
568/*
569 * omap_write_buf_irq_pref - write buffer to NAND controller
570 * @mtd: MTD device structure
571 * @buf: data buffer
572 * @len: number of bytes to write
573 */
574static void omap_write_buf_irq_pref(struct mtd_info *mtd,
575 const u_char *buf, int len)
576{
577 struct omap_nand_info *info = container_of(mtd,
578 struct omap_nand_info, mtd);
579 int ret = 0;
580 unsigned long tim, limit;
581
582 if (len <= mtd->oobsize) {
583 omap_write_buf_pref(mtd, buf, len);
584 return;
585 }
586
587 info->iomode = OMAP_NAND_IO_WRITE;
588 info->buf = (u_char *) buf;
589 init_completion(&info->comp);
590
591 /* configure and start prefetch transfer : size=24 */
592 ret = gpmc_prefetch_enable(info->gpmc_cs,
593 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
594 if (ret)
595 /* PFPW engine is busy, use cpu copy method */
596 goto out_copy;
597
598 info->buf_len = len;
599 /* enable irq */
600 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
601 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
602
603 /* waiting for write to complete */
604 wait_for_completion(&info->comp);
605 /* wait for data to flushed-out before reset the prefetch */
606 tim = 0;
607 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
608 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
609 cpu_relax();
610
611 /* disable and stop the PFPW engine */
612 gpmc_prefetch_reset(info->gpmc_cs);
613 return;
614
615out_copy:
616 if (info->nand.options & NAND_BUSWIDTH_16)
617 omap_write_buf16(mtd, buf, len);
618 else
619 omap_write_buf8(mtd, buf, len);
620}
621
469/** 622/**
470 * omap_verify_buf - Verify chip data against buffer 623 * omap_verify_buf - Verify chip data against buffer
471 * @mtd: MTD device structure 624 * @mtd: MTD device structure
@@ -487,8 +640,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
487 return 0; 640 return 0;
488} 641}
489 642
490#ifdef CONFIG_MTD_NAND_OMAP_HWECC
491
492/** 643/**
493 * gen_true_ecc - This function will generate true ECC value 644 * gen_true_ecc - This function will generate true ECC value
494 * @ecc_buf: buffer to store ecc code 645 * @ecc_buf: buffer to store ecc code
@@ -708,8 +859,6 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
708 gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); 859 gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
709} 860}
710 861
711#endif
712
713/** 862/**
714 * omap_wait - wait until the command is done 863 * omap_wait - wait until the command is done
715 * @mtd: MTD device structure 864 * @mtd: MTD device structure
@@ -779,6 +928,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
779 struct omap_nand_info *info; 928 struct omap_nand_info *info;
780 struct omap_nand_platform_data *pdata; 929 struct omap_nand_platform_data *pdata;
781 int err; 930 int err;
931 int i, offset;
782 932
783 pdata = pdev->dev.platform_data; 933 pdata = pdev->dev.platform_data;
784 if (pdata == NULL) { 934 if (pdata == NULL) {
@@ -804,7 +954,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
804 info->mtd.name = dev_name(&pdev->dev); 954 info->mtd.name = dev_name(&pdev->dev);
805 info->mtd.owner = THIS_MODULE; 955 info->mtd.owner = THIS_MODULE;
806 956
807 info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0; 957 info->nand.options = pdata->devsize;
808 info->nand.options |= NAND_SKIP_BBTSCAN; 958 info->nand.options |= NAND_SKIP_BBTSCAN;
809 959
810 /* NAND write protect off */ 960 /* NAND write protect off */
@@ -842,28 +992,13 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
842 info->nand.chip_delay = 50; 992 info->nand.chip_delay = 50;
843 } 993 }
844 994
845 if (use_prefetch) { 995 switch (pdata->xfer_type) {
846 996 case NAND_OMAP_PREFETCH_POLLED:
847 info->nand.read_buf = omap_read_buf_pref; 997 info->nand.read_buf = omap_read_buf_pref;
848 info->nand.write_buf = omap_write_buf_pref; 998 info->nand.write_buf = omap_write_buf_pref;
849 if (use_dma) { 999 break;
850 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND", 1000
851 omap_nand_dma_cb, &info->comp, &info->dma_ch); 1001 case NAND_OMAP_POLLED:
852 if (err < 0) {
853 info->dma_ch = -1;
854 printk(KERN_WARNING "DMA request failed."
855 " Non-dma data transfer mode\n");
856 } else {
857 omap_set_dma_dest_burst_mode(info->dma_ch,
858 OMAP_DMA_DATA_BURST_16);
859 omap_set_dma_src_burst_mode(info->dma_ch,
860 OMAP_DMA_DATA_BURST_16);
861
862 info->nand.read_buf = omap_read_buf_dma_pref;
863 info->nand.write_buf = omap_write_buf_dma_pref;
864 }
865 }
866 } else {
867 if (info->nand.options & NAND_BUSWIDTH_16) { 1002 if (info->nand.options & NAND_BUSWIDTH_16) {
868 info->nand.read_buf = omap_read_buf16; 1003 info->nand.read_buf = omap_read_buf16;
869 info->nand.write_buf = omap_write_buf16; 1004 info->nand.write_buf = omap_write_buf16;
@@ -871,20 +1006,61 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
871 info->nand.read_buf = omap_read_buf8; 1006 info->nand.read_buf = omap_read_buf8;
872 info->nand.write_buf = omap_write_buf8; 1007 info->nand.write_buf = omap_write_buf8;
873 } 1008 }
1009 break;
1010
1011 case NAND_OMAP_PREFETCH_DMA:
1012 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
1013 omap_nand_dma_cb, &info->comp, &info->dma_ch);
1014 if (err < 0) {
1015 info->dma_ch = -1;
1016 dev_err(&pdev->dev, "DMA request failed!\n");
1017 goto out_release_mem_region;
1018 } else {
1019 omap_set_dma_dest_burst_mode(info->dma_ch,
1020 OMAP_DMA_DATA_BURST_16);
1021 omap_set_dma_src_burst_mode(info->dma_ch,
1022 OMAP_DMA_DATA_BURST_16);
1023
1024 info->nand.read_buf = omap_read_buf_dma_pref;
1025 info->nand.write_buf = omap_write_buf_dma_pref;
1026 }
1027 break;
1028
1029 case NAND_OMAP_PREFETCH_IRQ:
1030 err = request_irq(pdata->gpmc_irq,
1031 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
1032 if (err) {
1033 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1034 pdata->gpmc_irq, err);
1035 goto out_release_mem_region;
1036 } else {
1037 info->gpmc_irq = pdata->gpmc_irq;
1038 info->nand.read_buf = omap_read_buf_irq_pref;
1039 info->nand.write_buf = omap_write_buf_irq_pref;
1040 }
1041 break;
1042
1043 default:
1044 dev_err(&pdev->dev,
1045 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1046 err = -EINVAL;
1047 goto out_release_mem_region;
874 } 1048 }
875 info->nand.verify_buf = omap_verify_buf;
876 1049
877#ifdef CONFIG_MTD_NAND_OMAP_HWECC 1050 info->nand.verify_buf = omap_verify_buf;
878 info->nand.ecc.bytes = 3;
879 info->nand.ecc.size = 512;
880 info->nand.ecc.calculate = omap_calculate_ecc;
881 info->nand.ecc.hwctl = omap_enable_hwecc;
882 info->nand.ecc.correct = omap_correct_data;
883 info->nand.ecc.mode = NAND_ECC_HW;
884 1051
885#else 1052 /* selsect the ecc type */
886 info->nand.ecc.mode = NAND_ECC_SOFT; 1053 if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
887#endif 1054 info->nand.ecc.mode = NAND_ECC_SOFT;
1055 else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
1056 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1057 info->nand.ecc.bytes = 3;
1058 info->nand.ecc.size = 512;
1059 info->nand.ecc.calculate = omap_calculate_ecc;
1060 info->nand.ecc.hwctl = omap_enable_hwecc;
1061 info->nand.ecc.correct = omap_correct_data;
1062 info->nand.ecc.mode = NAND_ECC_HW;
1063 }
888 1064
889 /* DIP switches on some boards change between 8 and 16 bit 1065 /* DIP switches on some boards change between 8 and 16 bit
890 * bus widths for flash. Try the other width if the first try fails. 1066 * bus widths for flash. Try the other width if the first try fails.
@@ -897,6 +1073,26 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
897 } 1073 }
898 } 1074 }
899 1075
1076 /* rom code layout */
1077 if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1078
1079 if (info->nand.options & NAND_BUSWIDTH_16)
1080 offset = 2;
1081 else {
1082 offset = 1;
1083 info->nand.badblock_pattern = &bb_descrip_flashbased;
1084 }
1085 omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
1086 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1087 omap_oobinfo.eccpos[i] = i+offset;
1088
1089 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
1090 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1091 (offset + omap_oobinfo.eccbytes);
1092
1093 info->nand.ecc.layout = &omap_oobinfo;
1094 }
1095
900#ifdef CONFIG_MTD_PARTITIONS 1096#ifdef CONFIG_MTD_PARTITIONS
901 err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0); 1097 err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
902 if (err > 0) 1098 if (err > 0)
@@ -926,9 +1122,12 @@ static int omap_nand_remove(struct platform_device *pdev)
926 mtd); 1122 mtd);
927 1123
928 platform_set_drvdata(pdev, NULL); 1124 platform_set_drvdata(pdev, NULL);
929 if (use_dma) 1125 if (info->dma_ch != -1)
930 omap_free_dma(info->dma_ch); 1126 omap_free_dma(info->dma_ch);
931 1127
1128 if (info->gpmc_irq)
1129 free_irq(info->gpmc_irq, info);
1130
932 /* Release NAND device, its internal structures and partitions */ 1131 /* Release NAND device, its internal structures and partitions */
933 nand_release(&info->mtd); 1132 nand_release(&info->mtd);
934 iounmap(info->nand.IO_ADDR_R); 1133 iounmap(info->nand.IO_ADDR_R);
@@ -947,16 +1146,8 @@ static struct platform_driver omap_nand_driver = {
947 1146
948static int __init omap_nand_init(void) 1147static int __init omap_nand_init(void)
949{ 1148{
950 printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME); 1149 pr_info("%s driver initializing\n", DRIVER_NAME);
951 1150
952 /* This check is required if driver is being
953 * loaded run time as a module
954 */
955 if ((1 == use_dma) && (0 == use_prefetch)) {
956 printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 "
957 "without use_prefetch'. Prefetch will not be"
958 " used in either mode (mpu or dma)\n");
959 }
960 return platform_driver_register(&omap_nand_driver); 1151 return platform_driver_register(&omap_nand_driver);
961} 1152}
962 1153
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index ac31f461cc1c..ec26399e3cf2 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -63,7 +63,7 @@ struct omap2_onenand {
63 struct completion dma_done; 63 struct completion dma_done;
64 int dma_channel; 64 int dma_channel;
65 int freq; 65 int freq;
66 int (*setup)(void __iomem *base, int freq); 66 int (*setup)(void __iomem *base, int *freq_ptr);
67 struct regulator *regulator; 67 struct regulator *regulator;
68}; 68};
69 69
@@ -148,11 +148,9 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
148 wait_err("controller error", state, ctrl, intr); 148 wait_err("controller error", state, ctrl, intr);
149 return -EIO; 149 return -EIO;
150 } 150 }
151 if ((intr & intr_flags) != intr_flags) { 151 if ((intr & intr_flags) == intr_flags)
152 wait_err("timeout", state, ctrl, intr); 152 return 0;
153 return -EIO; 153 /* Continue in wait for interrupt branch */
154 }
155 return 0;
156 } 154 }
157 155
158 if (state != FL_READING) { 156 if (state != FL_READING) {
@@ -581,7 +579,7 @@ static int __adjust_timing(struct device *dev, void *data)
581 579
582 /* DMA is not in use so this is all that is needed */ 580 /* DMA is not in use so this is all that is needed */
583 /* Revisit for OMAP3! */ 581 /* Revisit for OMAP3! */
584 ret = c->setup(c->onenand.base, c->freq); 582 ret = c->setup(c->onenand.base, &c->freq);
585 583
586 return ret; 584 return ret;
587} 585}
@@ -673,7 +671,7 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
673 } 671 }
674 672
675 if (pdata->onenand_setup != NULL) { 673 if (pdata->onenand_setup != NULL) {
676 r = pdata->onenand_setup(c->onenand.base, c->freq); 674 r = pdata->onenand_setup(c->onenand.base, &c->freq);
677 if (r < 0) { 675 if (r < 0) {
678 dev_err(&pdev->dev, "Onenand platform setup failed: " 676 dev_err(&pdev->dev, "Onenand platform setup failed: "
679 "%d\n", r); 677 "%d\n", r);
@@ -718,8 +716,8 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
718 } 716 }
719 717
720 dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual " 718 dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
721 "base %p\n", c->gpmc_cs, c->phys_base, 719 "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
722 c->onenand.base); 720 c->onenand.base, c->freq);
723 721
724 c->pdev = pdev; 722 c->pdev = pdev;
725 c->mtd.name = dev_name(&pdev->dev); 723 c->mtd.name = dev_name(&pdev->dev);
@@ -754,24 +752,6 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
754 if ((r = onenand_scan(&c->mtd, 1)) < 0) 752 if ((r = onenand_scan(&c->mtd, 1)) < 0)
755 goto err_release_regulator; 753 goto err_release_regulator;
756 754
757 switch ((c->onenand.version_id >> 4) & 0xf) {
758 case 0:
759 c->freq = 40;
760 break;
761 case 1:
762 c->freq = 54;
763 break;
764 case 2:
765 c->freq = 66;
766 break;
767 case 3:
768 c->freq = 83;
769 break;
770 case 4:
771 c->freq = 104;
772 break;
773 }
774
775#ifdef CONFIG_MTD_PARTITIONS 755#ifdef CONFIG_MTD_PARTITIONS
776 r = parse_mtd_partitions(&c->mtd, part_probes, &c->parts, 0); 756 r = parse_mtd_partitions(&c->mtd, part_probes, &c->parts, 0);
777 if (r > 0) 757 if (r > 0)
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
index cd6f3b431195..d60130f88eed 100644
--- a/include/linux/mtd/onenand_regs.h
+++ b/include/linux/mtd/onenand_regs.h
@@ -168,6 +168,7 @@
168#define ONENAND_SYS_CFG1_INT (1 << 6) 168#define ONENAND_SYS_CFG1_INT (1 << 6)
169#define ONENAND_SYS_CFG1_IOBE (1 << 5) 169#define ONENAND_SYS_CFG1_IOBE (1 << 5)
170#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) 170#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
171#define ONENAND_SYS_CFG1_VHF (1 << 3)
171#define ONENAND_SYS_CFG1_HF (1 << 2) 172#define ONENAND_SYS_CFG1_HF (1 << 2)
172#define ONENAND_SYS_CFG1_SYNC_WRITE (1 << 1) 173#define ONENAND_SYS_CFG1_SYNC_WRITE (1 << 1)
173 174
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-28 04:56:26 -0400