94 files changed, 9360 insertions, 3525 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cf8d0945530c..67a2fa2caa49 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -4,16 +4,21 @@ config MIPS
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_IDE
         select HAVE_OPROFILE
+        select HAVE_PERF_EVENTS
+        select PERF_USE_VMALLOC
         select HAVE_ARCH_KGDB
         select HAVE_FUNCTION_TRACER
         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FTRACE_MCOUNT_RECORD
+        select HAVE_C_RECORDMCOUNT
         select HAVE_FUNCTION_GRAPH_TRACER
         select HAVE_KPROBES
         select HAVE_KRETPROBES
         select RTC_LIB if !MACH_LOONGSON
         select GENERIC_ATOMIC64 if !64BIT
+        select HAVE_DMA_ATTRS
+        select HAVE_DMA_API_DEBUG
 
 menu "Machine selection"
 
@@ -691,6 +696,9 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
         select SWAP_IO_SPACE
         select HW_HAS_PCI
         select ARCH_SUPPORTS_MSI
+        select ZONE_DMA32
+        select USB_ARCH_HAS_OHCI
+        select USB_ARCH_HAS_EHCI
         help
           This option supports all of the Octeon reference boards from Cavium
           Networks. It builds a kernel that dynamically determines the Octeon
@@ -1334,6 +1342,57 @@ config CPU_CAVIUM_OCTEON
           can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
           Full details can be found at http://www.caviumnetworks.com.
 
+config CPU_BMIPS3300
+        bool "BMIPS3300"
+        depends on SYS_HAS_CPU_BMIPS3300
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select WEAK_ORDERING
+        help
+          Broadcom BMIPS3300 processors.
+
+config CPU_BMIPS4350
+        bool "BMIPS4350"
+        depends on SYS_HAS_CPU_BMIPS4350
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_HOTPLUG_CPU
+        select WEAK_ORDERING
+        help
+          Broadcom BMIPS4350 ("VIPER") processors.
+
+config CPU_BMIPS4380
+        bool "BMIPS4380"
+        depends on SYS_HAS_CPU_BMIPS4380
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_HOTPLUG_CPU
+        select WEAK_ORDERING
+        help
+          Broadcom BMIPS4380 processors.
+
+config CPU_BMIPS5000
+        bool "BMIPS5000"
+        depends on SYS_HAS_CPU_BMIPS5000
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select CPU_SUPPORTS_HIGHMEM
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_HOTPLUG_CPU
+        select WEAK_ORDERING
+        help
+          Broadcom BMIPS5000 processors.
+
 endchoice
 
 if CPU_LOONGSON2F
@@ -1452,6 +1511,18 @@ config SYS_HAS_CPU_SB1
 config SYS_HAS_CPU_CAVIUM_OCTEON
         bool
 
+config SYS_HAS_CPU_BMIPS3300
+        bool
+
+config SYS_HAS_CPU_BMIPS4350
+        bool
+
+config SYS_HAS_CPU_BMIPS4380
+        bool
+
+config SYS_HAS_CPU_BMIPS5000
+        bool
+
 #
 # CPU may reorder R->R, R->W, W->R, W->W
 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@@ -1928,6 +1999,14 @@ config NODES_SHIFT
         default "6"
         depends on NEED_MULTIPLE_NODES
 
+config HW_PERF_EVENTS
+        bool "Enable hardware performance counter support for perf events"
+        depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32
+        default y
+        help
+          Enable hardware performance counter support for perf events. If
+          disabled, perf events will use software events only.
+
 source "mm/Kconfig"
 
 config SMP
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 43dc27997730..f437cd1fafb8 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -67,6 +67,15 @@ config CMDLINE_OVERRIDE
 
           Normally, you will choose 'N' here.
 
+config DEBUG_STACKOVERFLOW
+        bool "Check for stack overflows"
+        depends on DEBUG_KERNEL
+        help
+          This option will cause messages to be printed if free stack space
+          drops below a certain limit(2GB on MIPS). The debugging option
+          provides another way to check stack overflow happened on kernel mode
+          stack usually caused by nested interruption.
+
 config DEBUG_STACK_USAGE
         bool "Enable stack utilization instrumentation"
         depends on DEBUG_KERNEL
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index f4a4b663ebb3..7c1102e41fe2 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -48,9 +48,6 @@ ifneq ($(SUBARCH),$(ARCH))
   endif
 endif
 
-ifndef CONFIG_FUNCTION_TRACER
-cflags-y := -ffunction-sections
-endif
 ifdef CONFIG_FUNCTION_GRAPH_TRACER
   ifndef KBUILD_MCOUNT_RA_ADDRESS
     ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
@@ -159,6 +156,7 @@ cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap
 ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
 cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
 endif
+cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
 
 cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)  += $(call cc-option,-mfix-r4000,)
 cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)  += $(call cc-option,-mfix-r4400,)
diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c
index c32fbb57441a..425dfa5d6e12 100644
--- a/arch/mips/ar7/gpio.c
+++ b/arch/mips/ar7/gpio.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
- * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -37,6 +37,16 @@ static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
         return readl(gpio_in) & (1 << gpio);
 }
 
+static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
+        void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
+
+        return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
+}
+
 static void ar7_gpio_set_value(struct gpio_chip *chip,
                                 unsigned gpio, int value)
 {
@@ -51,6 +61,21 @@ static void ar7_gpio_set_value(struct gpio_chip *chip,
         writel(tmp, gpio_out);
 }
 
+static void titan_gpio_set_value(struct gpio_chip *chip,
+                                unsigned gpio, int value)
+{
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
+        void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
+        unsigned tmp;
+
+        tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
+        if (value)
+                tmp |= 1 << (gpio & 0x1f);
+        writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
+}
+
 static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 {
         struct ar7_gpio_chip *gpch =
@@ -62,6 +87,21 @@ static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
         return 0;
 }
 
+static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
+        void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
+
+        if (gpio >= TITAN_GPIO_MAX)
+                return -EINVAL;
+
+        writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
+                        gpio >> 5 ? gpio_dir1 : gpio_dir0);
+        return 0;
+}
+
 static int ar7_gpio_direction_output(struct gpio_chip *chip,
                                         unsigned gpio, int value)
 {
@@ -75,6 +115,24 @@ static int ar7_gpio_direction_output(struct gpio_chip *chip,
         return 0;
 }
 
+static int titan_gpio_direction_output(struct gpio_chip *chip,
+                                        unsigned gpio, int value)
+{
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
+        void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
+
+        if (gpio >= TITAN_GPIO_MAX)
+                return -EINVAL;
+
+        titan_gpio_set_value(chip, gpio, value);
+        writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
+                (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
+
+        return 0;
+}
+
 static struct ar7_gpio_chip ar7_gpio_chip = {
         .chip = {
                 .label                  = "ar7-gpio",
@@ -87,7 +145,19 @@ static struct ar7_gpio_chip ar7_gpio_chip = {
         }
 };
 
-int ar7_gpio_enable(unsigned gpio)
+static struct ar7_gpio_chip titan_gpio_chip = {
+        .chip = {
+                .label                  = "titan-gpio",
+                .direction_input        = titan_gpio_direction_input,
+                .direction_output       = titan_gpio_direction_output,
+                .set                    = titan_gpio_set_value,
+                .get                    = titan_gpio_get_value,
+                .base                   = 0,
+                .ngpio                  = TITAN_GPIO_MAX,
+        }
+};
+
+static inline int ar7_gpio_enable_ar7(unsigned gpio)
 {
         void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
 
@@ -95,9 +165,26 @@ int ar7_gpio_enable(unsigned gpio)
 
         return 0;
 }
+
+static inline int ar7_gpio_enable_titan(unsigned gpio)
+{
+        void __iomem *gpio_en0 = titan_gpio_chip.regs  + TITAN_GPIO_ENBL_0;
+        void __iomem *gpio_en1 = titan_gpio_chip.regs  + TITAN_GPIO_ENBL_1;
+
+        writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
+                gpio >> 5 ? gpio_en1 : gpio_en0);
+
+        return 0;
+}
+
+int ar7_gpio_enable(unsigned gpio)
+{
+        return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
+                                ar7_gpio_enable_ar7(gpio);
+}
 EXPORT_SYMBOL(ar7_gpio_enable);
 
-int ar7_gpio_disable(unsigned gpio)
+static inline int ar7_gpio_disable_ar7(unsigned gpio)
 {
         void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
 
@@ -105,27 +192,159 @@ int ar7_gpio_disable(unsigned gpio)
 
         return 0;
 }
+
+static inline int ar7_gpio_disable_titan(unsigned gpio)
+{
+        void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
+        void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
+
+        writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
+                        gpio >> 5 ? gpio_en1 : gpio_en0);
+
+        return 0;
+}
+
+int ar7_gpio_disable(unsigned gpio)
+{
+        return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
+                                ar7_gpio_disable_ar7(gpio);
+}
 EXPORT_SYMBOL(ar7_gpio_disable);
 
-static int __init ar7_gpio_init(void)
+struct titan_gpio_cfg {
+        u32 reg;
+        u32 shift;
+        u32 func;
+};
+
+static struct titan_gpio_cfg titan_gpio_table[] = {
+        /* reg, start bit, mux value */
+        {4, 24, 1},
+        {4, 26, 1},
+        {4, 28, 1},
+        {4, 30, 1},
+        {5, 6, 1},
+        {5, 8, 1},
+        {5, 10, 1},
+        {5, 12, 1},
+        {7, 14, 3},
+        {7, 16, 3},
+        {7, 18, 3},
+        {7, 20, 3},
+        {7, 22, 3},
+        {7, 26, 3},
+        {7, 28, 3},
+        {7, 30, 3},
+        {8, 0, 3},
+        {8, 2, 3},
+        {8, 4, 3},
+        {8, 10, 3},
+        {8, 14, 3},
+        {8, 16, 3},
+        {8, 18, 3},
+        {8, 20, 3},
+        {9, 8, 3},
+        {9, 10, 3},
+        {9, 12, 3},
+        {9, 14, 3},
+        {9, 18, 3},
+        {9, 20, 3},
+        {9, 24, 3},
+        {9, 26, 3},
+        {9, 28, 3},
+        {9, 30, 3},
+        {10, 0, 3},
+        {10, 2, 3},
+        {10, 8, 3},
+        {10, 10, 3},
+        {10, 12, 3},
+        {10, 14, 3},
+        {13, 12, 3},
+        {13, 14, 3},
+        {13, 16, 3},
+        {13, 18, 3},
+        {13, 24, 3},
+        {13, 26, 3},
+        {13, 28, 3},
+        {13, 30, 3},
+        {14, 2, 3},
+        {14, 6, 3},
+        {14, 8, 3},
+        {14, 12, 3}
+};
+
+static int titan_gpio_pinsel(unsigned gpio)
+{
+        struct titan_gpio_cfg gpio_cfg;
+        u32 mux_status, pin_sel_reg, tmp;
+        void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
+
+        if (gpio >= ARRAY_SIZE(titan_gpio_table))
+                return -EINVAL;
+
+        gpio_cfg = titan_gpio_table[gpio];
+        pin_sel_reg = gpio_cfg.reg - 1;
+
+        mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
+
+        /* Check the mux status */
+        if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
+                return 0;
+
+        /* Set the pin sel value */
+        tmp = readl(pin_sel + pin_sel_reg);
+        tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
+        writel(tmp, pin_sel + pin_sel_reg);
+
+        return 0;
+}
+
+/* Perform minimal Titan GPIO configuration */
+static void titan_gpio_init(void)
+{
+        unsigned i;
+
+        for (i = 44; i < 48; i++) {
+                titan_gpio_pinsel(i);
+                ar7_gpio_enable_titan(i);
+                titan_gpio_direction_input(&titan_gpio_chip.chip, i);
+        }
+}
+
+int __init ar7_gpio_init(void)
 {
         int ret;
+        struct ar7_gpio_chip *gpch;
+        unsigned size;
+
+        if (!ar7_is_titan()) {
+                gpch = &ar7_gpio_chip;
+                size = 0x10;
+        } else {
+                gpch = &titan_gpio_chip;
+                size = 0x1f;
+        }
 
-        ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO,
+        gpch->regs = ioremap_nocache(AR7_REGS_GPIO,
                                         AR7_REGS_GPIO + 0x10);
 
-        if (!ar7_gpio_chip.regs) {
-                printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n");
+        if (!gpch->regs) {
+                printk(KERN_ERR "%s: failed to ioremap regs\n",
+                                        gpch->chip.label);
                 return -ENOMEM;
         }
 
-        ret = gpiochip_add(&ar7_gpio_chip.chip);
+        ret = gpiochip_add(&gpch->chip);
         if (ret) {
-                printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n");
+                printk(KERN_ERR "%s: failed to add gpiochip\n",
+                                        gpch->chip.label);
                 return ret;
         }
-        printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n",
-                                ar7_gpio_chip.chip.ngpio);
+        printk(KERN_INFO "%s: registered %d GPIOs\n",
+                                gpch->chip.label, gpch->chip.ngpio);
+
+        if (ar7_is_titan())
+                titan_gpio_init();
+
         return ret;
 }
-arch_initcall(ar7_gpio_init);
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 0da5b2b8dd88..7d2fab392327 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -357,6 +357,11 @@ static struct gpio_led default_leds[] = {
         },
 };
 
+static struct gpio_led titan_leds[] = {
+        { .name = "status", .gpio = 8, .active_low = 1, },
+        { .name = "wifi", .gpio = 13, .active_low = 1, },
+};
+
 static struct gpio_led dsl502t_leds[] = {
         {
                 .name                   = "status",
@@ -495,6 +500,9 @@ static void __init detect_leds(void)
         } else if (strstr(prid, "DG834")) {
                 ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
                 ar7_led_data.leds = dg834g_leds;
+        } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
+                ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
+                ar7_led_data.leds = titan_leds;
         }
 }
 
@@ -560,6 +568,51 @@ static int __init ar7_register_uarts(void)
         return 0;
 }
 
+static void __init titan_fixup_devices(void)
+{
+        /* Set vlynq0 data */
+        vlynq_low_data.reset_bit = 15;
+        vlynq_low_data.gpio_bit = 14;
+
+        /* Set vlynq1 data */
+        vlynq_high_data.reset_bit = 16;
+        vlynq_high_data.gpio_bit = 7;
+
+        /* Set vlynq0 resources */
+        vlynq_low_res[0].start = TITAN_REGS_VLYNQ0;
+        vlynq_low_res[0].end = TITAN_REGS_VLYNQ0 + 0xff;
+        vlynq_low_res[1].start = 33;
+        vlynq_low_res[1].end = 33;
+        vlynq_low_res[2].start = 0x0c000000;
+        vlynq_low_res[2].end = 0x0fffffff;
+        vlynq_low_res[3].start = 80;
+        vlynq_low_res[3].end = 111;
+
+        /* Set vlynq1 resources */
+        vlynq_high_res[0].start = TITAN_REGS_VLYNQ1;
+        vlynq_high_res[0].end = TITAN_REGS_VLYNQ1 + 0xff;
+        vlynq_high_res[1].start = 34;
+        vlynq_high_res[1].end = 34;
+        vlynq_high_res[2].start = 0x40000000;
+        vlynq_high_res[2].end = 0x43ffffff;
+        vlynq_high_res[3].start = 112;
+        vlynq_high_res[3].end = 143;
+
+        /* Set cpmac0 data */
+        cpmac_low_data.phy_mask = 0x40000000;
+
+        /* Set cpmac1 data */
+        cpmac_high_data.phy_mask = 0x80000000;
+
+        /* Set cpmac0 resources */
+        cpmac_low_res[0].start = TITAN_REGS_MAC0;
+        cpmac_low_res[0].end = TITAN_REGS_MAC0 + 0x7ff;
+
+        /* Set cpmac1 resources */
+        cpmac_high_res[0].start = TITAN_REGS_MAC1;
+        cpmac_high_res[0].end = TITAN_REGS_MAC1 + 0x7ff;
+}
+
 static int __init ar7_register_devices(void)
 {
         void __iomem *bootcr;
@@ -574,6 +627,9 @@ static int __init ar7_register_devices(void)
         if (res)
                 pr_warning("unable to register physmap-flash: %d\n", res);
 
+        if (ar7_is_titan())
+                titan_fixup_devices();
+
         ar7_device_disable(vlynq_low_data.reset_bit);
         res = platform_device_register(&vlynq_low);
         if (res)
diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c
index 52385790e5c1..23818d299127 100644
--- a/arch/mips/ar7/prom.c
+++ b/arch/mips/ar7/prom.c
@@ -246,6 +246,8 @@ void __init prom_init(void)
         ar7_init_cmdline(fw_arg0, (char **)fw_arg1);
         ar7_init_env((struct env_var *)fw_arg2);
         console_config();
+
+        ar7_gpio_init();
 }
 
 #define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4)))
diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c
index 3a801d2cb6e5..f20b53e597c4 100644
--- a/arch/mips/ar7/setup.c
+++ b/arch/mips/ar7/setup.c
@@ -23,6 +23,7 @@
 #include <asm/reboot.h>
 #include <asm/mach-ar7/ar7.h>
 #include <asm/mach-ar7/prom.h>
+#include <asm/mach-ar7/gpio.h>
 
 static void ar7_machine_restart(char *command)
 {
@@ -49,6 +50,8 @@ static void ar7_machine_power_off(void)
 const char *get_system_type(void)
 {
         u16 chip_id = ar7_chip_id();
+        u16 titan_variant_id = titan_chip_id();
+
         switch (chip_id) {
         case AR7_CHIP_7100:
                 return "TI AR7 (TNETD7100)";
@@ -56,6 +59,17 @@ const char *get_system_type(void)
                 return "TI AR7 (TNETD7200)";
         case AR7_CHIP_7300:
                 return "TI AR7 (TNETD7300)";
+        case AR7_CHIP_TITAN:
+                switch (titan_variant_id) {
+                case TITAN_CHIP_1050:
+                        return "TI AR7 (TNETV1050)";
+                case TITAN_CHIP_1055:
+                        return "TI AR7 (TNETV1055)";
+                case TITAN_CHIP_1056:
+                        return "TI AR7 (TNETV1056)";
+                case TITAN_CHIP_1060:
+                        return "TI AR7 (TNETV1060)";
+                }
         default:
                 return "TI AR7 (unknown)";
         }
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index cbb7caf86d77..7c7e4d4486ce 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -10,7 +10,9 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/cpu.h>
+#include <asm/cpu.h>
 #include <asm/cpu-info.h>
+#include <asm/mipsregs.h>
 #include <bcm63xx_cpu.h>
 #include <bcm63xx_regs.h>
 #include <bcm63xx_io.h>
@@ -296,26 +298,24 @@ void __init bcm63xx_cpu_init(void)
         expected_cpu_id = 0;
 
         switch (c->cputype) {
-        /*
-         * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
-         */
-        case CPU_BCM3302:
-                __cpu_name[cpu] = "Broadcom BCM6338";
-                expected_cpu_id = BCM6338_CPU_ID;
-                bcm63xx_regs_base = bcm96338_regs_base;
-                bcm63xx_irqs = bcm96338_irqs;
+        case CPU_BMIPS3300:
+                if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
+                        expected_cpu_id = BCM6348_CPU_ID;
+                        bcm63xx_regs_base = bcm96348_regs_base;
+                        bcm63xx_irqs = bcm96348_irqs;
+                } else {
+                        __cpu_name[cpu] = "Broadcom BCM6338";
+                        expected_cpu_id = BCM6338_CPU_ID;
+                        bcm63xx_regs_base = bcm96338_regs_base;
+                        bcm63xx_irqs = bcm96338_irqs;
+                }
                 break;
-        case CPU_BCM6345:
+        case CPU_BMIPS32:
                 expected_cpu_id = BCM6345_CPU_ID;
                 bcm63xx_regs_base = bcm96345_regs_base;
                 bcm63xx_irqs = bcm96345_irqs;
                 break;
-        case CPU_BCM6348:
-                expected_cpu_id = BCM6348_CPU_ID;
-                bcm63xx_regs_base = bcm96348_regs_base;
-                bcm63xx_irqs = bcm96348_irqs;
-                break;
-        case CPU_BCM6358:
+        case CPU_BMIPS4350:
                 expected_cpu_id = BCM6358_CPU_ID;
                 bcm63xx_regs_base = bcm96358_regs_base;
                 bcm63xx_irqs = bcm96358_irqs;
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 47323ca452dc..caae22858163 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -3,6 +3,17 @@ config CAVIUM_OCTEON_SPECIFIC_OPTIONS
         depends on CPU_CAVIUM_OCTEON
         default "y"
 
+config CAVIUM_CN63XXP1
+        bool "Enable CN63XXP1 errata worarounds"
+        depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
+        default "n"
+        help
+          The CN63XXP1 chip requires build time workarounds to
+          function reliably, select this option to enable them.  These
+          workarounds will cause a slight decrease in performance on
+          non-CN63XXP1 hardware, so it is recommended to select "n"
+          unless it is known the workarounds are needed.
+
 config CAVIUM_OCTEON_2ND_KERNEL
         bool "Build the kernel to be used as a 2nd kernel on the same chip"
         depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
@@ -87,3 +98,15 @@ config ARCH_SPARSEMEM_ENABLE
 config CAVIUM_OCTEON_HELPER
         def_bool y
         depends on OCTEON_ETHERNET || PCI
+
+config IOMMU_HELPER
+        bool
+
+config NEED_SG_DMA_LENGTH
+        bool
+
+config SWIOTLB
+        def_bool y
+        depends on CPU_CAVIUM_OCTEON
+        select IOMMU_HELPER
+        select NEED_SG_DMA_LENGTH
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index b6847c8e0ddd..26bf71130bf8 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -4,14 +4,18 @@
  * for more details.
  *
  * Copyright (C) 2007 by Ralf Baechle
+ * Copyright (C) 2009, 2010 Cavium Networks, Inc.
  */
 #include <linux/clocksource.h>
 #include <linux/init.h>
+#include <linux/smp.h>
 
+#include <asm/cpu-info.h>
 #include <asm/time.h>
 
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/cvmx-ipd-defs.h>
+#include <asm/octeon/cvmx-mio-defs.h>
 
 /*
  * Set the current core's cvmcount counter to the value of the
@@ -19,11 +23,23 @@
  * on-line.  This allows for a read from a local cpu register to
  * access a synchronized counter.
  *
+ * On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv.
  */
 void octeon_init_cvmcount(void)
 {
         unsigned long flags;
         unsigned loops = 2;
+        u64 f = 0;
+        u64 rdiv = 0;
+        u64 sdiv = 0;
+        if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
+                union cvmx_mio_rst_boot rst_boot;
+                rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+                rdiv = rst_boot.s.c_mul;        /* CPU clock */
+                sdiv = rst_boot.s.pnr_mul;      /* I/O clock */
+                f = (0x8000000000000000ull / sdiv) * 2;
+        }
+
 
         /* Clobber loops so GCC will not unroll the following while loop. */
         asm("" : "+r" (loops));
@@ -33,8 +49,20 @@ void octeon_init_cvmcount(void)
          * Loop several times so we are executing from the cache,
          * which should give more deterministic timing.
          */
-        while (loops--)
-                write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT));
+        while (loops--) {
+                u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT);
+                if (rdiv != 0) {
+                        ipd_clk_count *= rdiv;
+                        if (f != 0) {
+                                asm("dmultu\t%[cnt],%[f]\n\t"
+                                    "mfhi\t%[cnt]"
+                                    : [cnt] "+r" (ipd_clk_count),
+                                      [f] "=r" (f)
+                                    : : "hi", "lo");
+                        }
+                }
+                write_c0_cvmcount(ipd_clk_count);
+        }
         local_irq_restore(flags);
 }
 
@@ -77,7 +105,7 @@ unsigned long long notrace sched_clock(void)
 void __init plat_time_init(void)
 {
         clocksource_mips.rating = 300;
-        clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
+        clocksource_set_clock(&clocksource_mips, octeon_get_clock_rate());
         clocksource_register(&clocksource_mips);
 }
 
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index d22b5a2d64f4..1abb66caaa1d 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -8,335 +8,342 @@
  * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
  * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
  * IP32 changes by Ilya.
- * Cavium Networks: Create new dma setup for Cavium Networks Octeon based on
- * the kernels original.
+ * Copyright (C) 2010 Cavium Networks, Inc.
  */
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/string.h>
 #include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
 #include <linux/scatterlist.h>
+#include <linux/bootmem.h>
+#include <linux/swiotlb.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
 
-#include <linux/cache.h>
-#include <linux/io.h>
+#include <asm/bootinfo.h>
 
 #include <asm/octeon/octeon.h>
+
+#ifdef CONFIG_PCI
+#include <asm/octeon/pci-octeon.h>
 #include <asm/octeon/cvmx-npi-defs.h>
 #include <asm/octeon/cvmx-pci-defs.h>
 
-#include <dma-coherence.h>
+static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
+{
+        if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
+                return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
+        else
+                return paddr;
+}
 
-#ifdef CONFIG_PCI
-#include <asm/octeon/pci-octeon.h>
-#endif
+static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
+{
+        if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
+                return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
+        else
+                return daddr;
+}
+
+static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+                paddr -= 0x400000000ull;
+        return octeon_hole_phys_to_dma(paddr);
+}
 
-#define BAR2_PCI_ADDRESS 0x8000000000ul
+static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        daddr = octeon_hole_dma_to_phys(daddr);
 
-struct bar1_index_state {
-        int16_t ref_count;      /* Number of PCI mappings using this index */
-        uint16_t address_bits;  /* Upper bits of physical address. This is
-                                   shifted 22 bits */
-};
+        if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+                daddr += 0x400000000ull;
 
-#ifdef CONFIG_PCI
-static DEFINE_RAW_SPINLOCK(bar1_lock);
-static struct bar1_index_state bar1_state[32];
-#endif
+        return daddr;
+}
 
-dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
+static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
-#ifndef CONFIG_PCI
-        /* Without PCI/PCIe this function can be called for Octeon internal
-           devices such as USB. These devices all support 64bit addressing */
+        if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+                paddr -= 0x400000000ull;
+
+        /* Anything in the BAR1 hole or above goes via BAR2 */
+        if (paddr >= 0xf0000000ull)
+                paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
+
+        return paddr;
+}
+
+static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
+                daddr -= OCTEON_BAR2_PCI_ADDRESS;
+
+        if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+                daddr += 0x400000000ull;
+        return daddr;
+}
+
+static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
+                                           phys_addr_t paddr)
+{
+        if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+                paddr -= 0x400000000ull;
+
+        /* Anything not in the BAR1 range goes via BAR2 */
+        if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
+                paddr = paddr - octeon_bar1_pci_phys;
+        else
+                paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
+
+        return paddr;
+}
+
+static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
+                                            dma_addr_t daddr)
+{
+        if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
+                daddr -= OCTEON_BAR2_PCI_ADDRESS;
+        else
+                daddr += octeon_bar1_pci_phys;
+
+        if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+                daddr += 0x400000000ull;
+        return daddr;
+}
+
+#endif /* CONFIG_PCI */
+
+static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page,
+        unsigned long offset, size_t size, enum dma_data_direction direction,
+        struct dma_attrs *attrs)
+{
+        dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size,
+                                            direction, attrs);
         mb();
-        return virt_to_phys(ptr);
-#else
-        unsigned long flags;
-        uint64_t dma_mask;
-        int64_t start_index;
-        dma_addr_t result = -1;
-        uint64_t physical = virt_to_phys(ptr);
-        int64_t index;
 
+        return daddr;
+}
+
+static int octeon_dma_map_sg(struct device *dev, struct scatterlist *sg,
+        int nents, enum dma_data_direction direction, struct dma_attrs *attrs)
+{
+        int r = swiotlb_map_sg_attrs(dev, sg, nents, direction, attrs);
         mb();
-        /*
-         * Use the DMA masks to determine the allowed memory
-         * region. For us it doesn't limit the actual memory, just the
-         * address visible over PCI.  Devices with limits need to use
-         * lower indexed Bar1 entries.
-         */
-        if (dev) {
-                dma_mask = dev->coherent_dma_mask;
-                if (dev->dma_mask)
-                        dma_mask = *dev->dma_mask;
-        } else {
-                dma_mask = 0xfffffffful;
-        }
+        return r;
+}
 
-        /*
-         * Platform devices, such as the internal USB, skip all
-         * translation and use Octeon physical addresses directly.
-         */
-        if (!dev || dev->bus == &platform_bus_type)
-                return physical;
+static void octeon_dma_sync_single_for_device(struct device *dev,
+        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
+{
+        swiotlb_sync_single_for_device(dev, dma_handle, size, direction);
+        mb();
+}
 
-        switch (octeon_dma_bar_type) {
-        case OCTEON_DMA_BAR_TYPE_PCIE:
-                if (unlikely(physical < (16ul << 10)))
-                        panic("dma_map_single: Not allowed to map first 16KB."
-                              " It interferes with BAR0 special area\n");
-                else if ((physical + size >= (256ul << 20)) &&
-                         (physical < (512ul << 20)))
-                        panic("dma_map_single: Not allowed to map bootbus\n");
-                else if ((physical + size >= 0x400000000ull) &&
-                         physical < 0x410000000ull)
-                        panic("dma_map_single: "
-                              "Attempt to map illegal memory address 0x%llx\n",
-                              physical);
-                else if (physical >= 0x420000000ull)
-                        panic("dma_map_single: "
-                              "Attempt to map illegal memory address 0x%llx\n",
-                              physical);
-                else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE &&
-                         physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) {
-                        result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
-
-                        if (((result+size-1) & dma_mask) != result+size-1)
-                                panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n",
-                                      physical, physical+size-1, dma_mask);
-                        goto done;
-                }
-
-                /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
-                if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
-                        result = physical - 0x400000000ull;
-                else
-                        result = physical;
-                if (((result+size-1) & dma_mask) != result+size-1)
-                        panic("dma_map_single: Attempt to map address "
-                              "0x%llx-0x%llx, which can't be accessed "
-                              "according to the dma mask 0x%llx\n",
-                              physical, physical+size-1, dma_mask);
-                goto done;
+static void octeon_dma_sync_sg_for_device(struct device *dev,
+        struct scatterlist *sg, int nelems, enum dma_data_direction direction)
+{
+        swiotlb_sync_sg_for_device(dev, sg, nelems, direction);
+        mb();
+}
 
-        case OCTEON_DMA_BAR_TYPE_BIG:
-#ifdef CONFIG_64BIT
-                /* If the device supports 64bit addressing, then use BAR2 */
-                if (dma_mask > BAR2_PCI_ADDRESS) {
-                        result = physical + BAR2_PCI_ADDRESS;
-                        goto done;
-                }
-#endif
-                if (unlikely(physical < (4ul << 10))) {
-                        panic("dma_map_single: Not allowed to map first 4KB. "
-                              "It interferes with BAR0 special area\n");
-                } else if (physical < (256ul << 20)) {
-                        if (unlikely(physical + size > (256ul << 20)))
-                                panic("dma_map_single: Requested memory spans "
-                                      "Bar0 0:256MB and bootbus\n");
-                        result = physical;
-                        goto done;
-                } else if (unlikely(physical < (512ul << 20))) {
-                        panic("dma_map_single: Not allowed to map bootbus\n");
-                } else if (physical < (2ul << 30)) {
-                        if (unlikely(physical + size > (2ul << 30)))
-                                panic("dma_map_single: Requested memory spans "
-                                      "Bar0 512MB:2GB and BAR1\n");
-                        result = physical;
-                        goto done;
-                } else if (physical < (2ul << 30) + (128 << 20)) {
-                        /* Fall through */
-                } else if (physical <
-                           (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) {
-                        if (unlikely
-                            (physical + size >
-                             (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)))
-                                panic("dma_map_single: Requested memory "
-                                      "extends past Bar1 (4GB-%luMB)\n",
-                                      OCTEON_PCI_BAR1_HOLE_SIZE);
-                        result = physical;
-                        goto done;
-                } else if ((physical >= 0x410000000ull) &&
-                           (physical < 0x420000000ull)) {
-                        if (unlikely(physical + size > 0x420000000ull))
-                                panic("dma_map_single: Requested memory spans "
-                                      "non existant memory\n");
-                        /* BAR0 fixed mapping 256MB:512MB ->
-                         * 16GB+256MB:16GB+512MB */
-                        result = physical - 0x400000000ull;
-                        goto done;
-                } else {
-                        /* Continued below switch statement */
-                }
-                break;
+static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
+        dma_addr_t *dma_handle, gfp_t gfp)
+{
+        void *ret;
 
-        case OCTEON_DMA_BAR_TYPE_SMALL:
-#ifdef CONFIG_64BIT
-                /* If the device supports 64bit addressing, then use BAR2 */
-                if (dma_mask > BAR2_PCI_ADDRESS) {
-                        result = physical + BAR2_PCI_ADDRESS;
-                        goto done;
-                }
+        if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
+                return ret;
+
+        /* ignore region specifiers */
+        gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
+
+#ifdef CONFIG_ZONE_DMA
+        if (dev == NULL)
+                gfp |= __GFP_DMA;
+        else if (dev->coherent_dma_mask <= DMA_BIT_MASK(24))
+                gfp |= __GFP_DMA;
+        else
 #endif
-                /* Continued below switch statement */
-                break;
+#ifdef CONFIG_ZONE_DMA32
+             if (dev->coherent_dma_mask <= DMA_BIT_MASK(32))
+                gfp |= __GFP_DMA32;
+        else
+#endif
+                ;
 
-        default:
-                panic("dma_map_single: Invalid octeon_dma_bar_type\n");
-        }
+        /* Don't invoke OOM killer */
+        gfp |= __GFP_NORETRY;
 
-        /* Don't allow mapping to span multiple Bar entries. The hardware guys
-           won't guarantee that DMA across boards work */
-        if (unlikely((physical >> 22) != ((physical + size - 1) >> 22)))
-                panic("dma_map_single: "
-                      "Requested memory spans more than one Bar1 entry\n");
+        ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
 
-        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
-                start_index = 31;
-        else if (unlikely(dma_mask < (1ul << 27)))
-                start_index = (dma_mask >> 22);
-        else
-                start_index = 31;
-
-        /* Only one processor can access the Bar register at once */
-        raw_spin_lock_irqsave(&bar1_lock, flags);
-
-        /* Look through Bar1 for existing mapping that will work */
-        for (index = start_index; index >= 0; index--) {
-                if ((bar1_state[index].address_bits == physical >> 22) &&
-                    (bar1_state[index].ref_count)) {
-                        /* An existing mapping will work, use it */
-                        bar1_state[index].ref_count++;
-                        if (unlikely(bar1_state[index].ref_count < 0))
-                                panic("dma_map_single: "
-                                      "Bar1[%d] reference count overflowed\n",
-                                      (int) index);
-                        result = (index << 22) | (physical & ((1 << 22) - 1));
-                        /* Large BAR1 is offset at 2GB */
-                        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
-                                result += 2ul << 30;
-                        goto done_unlock;
-                }
-        }
+        mb();
 
-        /* No existing mappings, look for a free entry */
-        for (index = start_index; index >= 0; index--) {
-                if (unlikely(bar1_state[index].ref_count == 0)) {
-                        union cvmx_pci_bar1_indexx bar1_index;
-                        /* We have a free entry, use it */
-                        bar1_state[index].ref_count = 1;
-                        bar1_state[index].address_bits = physical >> 22;
-                        bar1_index.u32 = 0;
-                        /* Address bits[35:22] sent to L2C */
-                        bar1_index.s.addr_idx = physical >> 22;
-                        /* Don't put PCI accesses in L2. */
-                        bar1_index.s.ca = 1;
-                        /* Endian Swap Mode */
-                        bar1_index.s.end_swp = 1;
-                        /* Set '1' when the selected address range is valid. */
-                        bar1_index.s.addr_v = 1;
-                        octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
-                                           bar1_index.u32);
-                        /* An existing mapping will work, use it */
-                        result = (index << 22) | (physical & ((1 << 22) - 1));
-                        /* Large BAR1 is offset at 2GB */
-                        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
-                                result += 2ul << 30;
-                        goto done_unlock;
-                }
-        }
+        return ret;
+}
 
-        pr_err("dma_map_single: "
-               "Can't find empty BAR1 index for physical mapping 0x%llx\n",
-               (unsigned long long) physical);
+static void octeon_dma_free_coherent(struct device *dev, size_t size,
+        void *vaddr, dma_addr_t dma_handle)
+{
+        int order = get_order(size);
 
-done_unlock:
-        raw_spin_unlock_irqrestore(&bar1_lock, flags);
-done:
-        pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result);
-        return result;
-#endif
+        if (dma_release_from_coherent(dev, order, vaddr))
+                return;
+
+        swiotlb_free_coherent(dev, size, vaddr, dma_handle);
 }
 
-void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
-#ifndef CONFIG_PCI
-        /*
-         * Without PCI/PCIe this function can be called for Octeon internal
-         * devices such as USB. These devices all support 64bit addressing.
-         */
-        return;
-#else
-        unsigned long flags;
-        uint64_t index;
+        return paddr;
+}
 
+static phys_addr_t octeon_unity_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        return daddr;
+}
+
+struct octeon_dma_map_ops {
+        struct dma_map_ops dma_map_ops;
+        dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
+        phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
+};
+
+dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
+                                                      struct octeon_dma_map_ops,
+                                                      dma_map_ops);
+
+        return ops->phys_to_dma(dev, paddr);
+}
+EXPORT_SYMBOL(phys_to_dma);
+
+phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
+                                                      struct octeon_dma_map_ops,
+                                                      dma_map_ops);
+
+        return ops->dma_to_phys(dev, daddr);
+}
+EXPORT_SYMBOL(dma_to_phys);
+
+static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
+        .dma_map_ops = {
+                .alloc_coherent = octeon_dma_alloc_coherent,
+                .free_coherent = octeon_dma_free_coherent,
+                .map_page = octeon_dma_map_page,
+                .unmap_page = swiotlb_unmap_page,
+                .map_sg = octeon_dma_map_sg,
+                .unmap_sg = swiotlb_unmap_sg_attrs,
+                .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
+                .sync_single_for_device = octeon_dma_sync_single_for_device,
+                .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+                .sync_sg_for_device = octeon_dma_sync_sg_for_device,
+                .mapping_error = swiotlb_dma_mapping_error,
+                .dma_supported = swiotlb_dma_supported
+        },
+        .phys_to_dma = octeon_unity_phys_to_dma,
+        .dma_to_phys = octeon_unity_dma_to_phys
+};
+
+char *octeon_swiotlb;
+
+void __init plat_swiotlb_setup(void)
+{
+        int i;
+        phys_t max_addr;
+        phys_t addr_size;
+        size_t swiotlbsize;
+        unsigned long swiotlb_nslabs;
+
+        max_addr = 0;
+        addr_size = 0;
+
+        for (i = 0 ; i < boot_mem_map.nr_map; i++) {
+                struct boot_mem_map_entry *e = &boot_mem_map.map[i];
+                if (e->type != BOOT_MEM_RAM)
+                        continue;
+
+                /* These addresses map low for PCI. */
+                if (e->addr > 0x410000000ull)
+                        continue;
+
+                addr_size += e->size;
+
+                if (max_addr < e->addr + e->size)
+                        max_addr = e->addr + e->size;
+
+        }
+
+        swiotlbsize = PAGE_SIZE;
+
+#ifdef CONFIG_PCI
         /*
-         * Platform devices, such as the internal USB, skip all
-         * translation and use Octeon physical addresses directly.
+         * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
+         * size to a maximum of 64MB
          */
-        if (dev->bus == &platform_bus_type)
-                return;
+        if (OCTEON_IS_MODEL(OCTEON_CN31XX)
+            || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
+                swiotlbsize = addr_size / 4;
+                if (swiotlbsize > 64 * (1<<20))
+                        swiotlbsize = 64 * (1<<20);
+        } else if (max_addr > 0xf0000000ul) {
+                /*
+                 * Otherwise only allocate a big iotlb if there is
+                 * memory past the BAR1 hole.
+                 */
+                swiotlbsize = 64 * (1<<20);
+        }
+#endif
+        swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
+        swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
+        swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
+
+        octeon_swiotlb = alloc_bootmem_low_pages(swiotlbsize);
 
+        swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1);
+
+        mips_dma_map_ops = &octeon_linear_dma_map_ops.dma_map_ops;
+}
+
+#ifdef CONFIG_PCI
+static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = {
+        .dma_map_ops = {
+                .alloc_coherent = octeon_dma_alloc_coherent,
+                .free_coherent = octeon_dma_free_coherent,
+                .map_page = octeon_dma_map_page,
+                .unmap_page = swiotlb_unmap_page,
+                .map_sg = octeon_dma_map_sg,
+                .unmap_sg = swiotlb_unmap_sg_attrs,
+                .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
+                .sync_single_for_device = octeon_dma_sync_single_for_device,
+                .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+                .sync_sg_for_device = octeon_dma_sync_sg_for_device,
+                .mapping_error = swiotlb_dma_mapping_error,
+                .dma_supported = swiotlb_dma_supported
+        },
+};
+
+struct dma_map_ops *octeon_pci_dma_map_ops;
+
+void __init octeon_pci_dma_init(void)
+{
         switch (octeon_dma_bar_type) {
         case OCTEON_DMA_BAR_TYPE_PCIE:
-                /* Nothing to do, all mappings are static */
-                goto done;
-
+                _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
+                _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
+                break;
         case OCTEON_DMA_BAR_TYPE_BIG:
-#ifdef CONFIG_64BIT
-                /* Nothing to do for addresses using BAR2 */
-                if (dma_addr >= BAR2_PCI_ADDRESS)
-                        goto done;
-#endif
-                if (unlikely(dma_addr < (4ul << 10)))
-                        panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
-                              dma_addr);
-                else if (dma_addr < (2ul << 30))
-                        /* Nothing to do for addresses using BAR0 */
-                        goto done;
-                else if (dma_addr < (2ul << 30) + (128ul << 20))
-                        /* Need to unmap, fall through */
-                        index = (dma_addr - (2ul << 30)) >> 22;
-                else if (dma_addr <
-                         (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))
-                        goto done;      /* Nothing to do for the rest of BAR1 */
-                else
-                        panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
-                              dma_addr);
-                /* Continued below switch statement */
+                _octeon_pci_dma_map_ops.phys_to_dma = octeon_big_phys_to_dma;
+                _octeon_pci_dma_map_ops.dma_to_phys = octeon_big_dma_to_phys;
                 break;
-
         case OCTEON_DMA_BAR_TYPE_SMALL:
-#ifdef CONFIG_64BIT
-                /* Nothing to do for addresses using BAR2 */
-                if (dma_addr >= BAR2_PCI_ADDRESS)
-                        goto done;
-#endif
-                index = dma_addr >> 22;
-                /* Continued below switch statement */
+                _octeon_pci_dma_map_ops.phys_to_dma = octeon_small_phys_to_dma;
+                _octeon_pci_dma_map_ops.dma_to_phys = octeon_small_dma_to_phys;
                 break;
-
         default:
-                panic("dma_unmap_single: Invalid octeon_dma_bar_type\n");
+                BUG();
         }
-
-        if (unlikely(index > 31))
-                panic("dma_unmap_single: "
-                      "Attempt to unmap an invalid address (0x%llx)\n",
-                      dma_addr);
-
-        raw_spin_lock_irqsave(&bar1_lock, flags);
-        bar1_state[index].ref_count--;
-        if (bar1_state[index].ref_count == 0)
-                octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
-        else if (unlikely(bar1_state[index].ref_count < 0))
-                panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
-                      (int) index);
-        raw_spin_unlock_irqrestore(&bar1_lock, flags);
-done:
-        pr_debug("dma_unmap_single 0x%llx\n", dma_addr);
-        return;
-#endif
+        octeon_pci_dma_map_ops = &_octeon_pci_dma_map_ops.dma_map_ops;
 }
+#endif /* CONFIG_PCI */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index 6abe56f1e097..d38246e33ddb 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -26,8 +26,8 @@
  ***********************license end**************************************/
 
 /*
- * Implementation of the Level 2 Cache (L2C) control, measurement, and
- * debugging facilities.
+ * Implementation of the Level 2 Cache (L2C) control,
+ * measurement, and debugging facilities.
  */
 
 #include <asm/octeon/cvmx.h>
@@ -42,13 +42,7 @@
  * if multiple applications or operating systems are running, then it
  * is up to the user program to coordinate between them.
  */
-static cvmx_spinlock_t cvmx_l2c_spinlock;
-
-static inline int l2_size_half(void)
-{
-        uint64_t val = cvmx_read_csr(CVMX_L2D_FUS3);
-        return !!(val & (1ull << 34));
-}
+cvmx_spinlock_t cvmx_l2c_spinlock;
 
 int cvmx_l2c_get_core_way_partition(uint32_t core)
 {
@@ -58,6 +52,9 @@ int cvmx_l2c_get_core_way_partition(uint32_t core)
         if (core >= cvmx_octeon_num_cores())
                 return -1;
 
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+                return cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff;
+
         /*
          * Use the lower two bits of the coreNumber to determine the
          * bit offset of the UMSK[] field in the L2C_SPAR register.
@@ -71,17 +68,13 @@ int cvmx_l2c_get_core_way_partition(uint32_t core)
 
         switch (core & 0xC) {
         case 0x0:
-                return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >>
-                        field;
+                return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field;
         case 0x4:
-                return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >>
-                        field;
+                return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field;
         case 0x8:
-                return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >>
-                        field;
+                return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field;
         case 0xC:
-                return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >>
-                        field;
+                return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field;
         }
         return 0;
 }
@@ -95,48 +88,50 @@ int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask)
 
         mask &= valid_mask;
 
-        /* A UMSK setting which blocks all L2C Ways is an error. */
-        if (mask == valid_mask)
+        /* A UMSK setting which blocks all L2C Ways is an error on some chips */
+        if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
                 return -1;
 
         /* Validate the core number */
         if (core >= cvmx_octeon_num_cores())
                 return -1;
 
-        /* Check to make sure current mask & new mask don't block all ways */
-        if (((mask | cvmx_l2c_get_core_way_partition(core)) & valid_mask) ==
-            valid_mask)
-                return -1;
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask);
+                return 0;
+        }
 
-        /* Use the lower two bits of core to determine the bit offset of the
+        /*
+         * Use the lower two bits of core to determine the bit offset of the
          * UMSK[] field in the L2C_SPAR register.
          */
         field = (core & 0x3) * 8;
 
-        /* Assign the new mask setting to the UMSK[] field in the appropriate
+        /*
+         * Assign the new mask setting to the UMSK[] field in the appropriate
          * L2C_SPAR register based on the core_num.
          *
          */
         switch (core & 0xC) {
         case 0x0:
                 cvmx_write_csr(CVMX_L2C_SPAR0,
-                               (cvmx_read_csr(CVMX_L2C_SPAR0) &
-                                ~(0xFF << field)) | mask << field);
+                               (cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) |
+                               mask << field);
                 break;
         case 0x4:
                 cvmx_write_csr(CVMX_L2C_SPAR1,
-                               (cvmx_read_csr(CVMX_L2C_SPAR1) &
-                                ~(0xFF << field)) | mask << field);
+                               (cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) |
+                               mask << field);
                 break;
         case 0x8:
                 cvmx_write_csr(CVMX_L2C_SPAR2,
-                               (cvmx_read_csr(CVMX_L2C_SPAR2) &
-                                ~(0xFF << field)) | mask << field);
+                               (cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) |
+                               mask << field);
                 break;
         case 0xC:
                 cvmx_write_csr(CVMX_L2C_SPAR3,
-                               (cvmx_read_csr(CVMX_L2C_SPAR3) &
-                                ~(0xFF << field)) | mask << field);
+                               (cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) |
+                               mask << field);
                 break;
         }
         return 0;
@@ -146,84 +141,137 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask)
 {
         uint32_t valid_mask;
 
-        valid_mask = 0xff;
-
-        if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) {
-                if (l2_size_half())
-                        valid_mask = 0xf;
-        } else if (l2_size_half())
-                valid_mask = 0x3;
-
+        valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
         mask &= valid_mask;
 
-        /* A UMSK setting which blocks all L2C Ways is an error. */
-        if (mask == valid_mask)
-                return -1;
-        /* Check to make sure current mask & new mask don't block all ways */
-        if (((mask | cvmx_l2c_get_hw_way_partition()) & valid_mask) ==
-            valid_mask)
+        /* A UMSK setting which blocks all L2C Ways is an error on some chips */
+        if (mask == valid_mask  && !OCTEON_IS_MODEL(OCTEON_CN63XX))
                 return -1;
 
-        cvmx_write_csr(CVMX_L2C_SPAR4,
-                       (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+                cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask);
+        else
+                cvmx_write_csr(CVMX_L2C_SPAR4,
+                               (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
         return 0;
 }
 
 int cvmx_l2c_get_hw_way_partition(void)
 {
-        return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+                return cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff;
+        else
+                return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
 }
 
 void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
                           uint32_t clear_on_read)
 {
-        union cvmx_l2c_pfctl pfctl;
+        if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+                union cvmx_l2c_pfctl pfctl;
 
-        pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
+                pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
 
-        switch (counter) {
-        case 0:
-                pfctl.s.cnt0sel = event;
-                pfctl.s.cnt0ena = 1;
-                if (!cvmx_octeon_is_pass1())
+                switch (counter) {
+                case 0:
+                        pfctl.s.cnt0sel = event;
+                        pfctl.s.cnt0ena = 1;
                         pfctl.s.cnt0rdclr = clear_on_read;
-                break;
-        case 1:
-                pfctl.s.cnt1sel = event;
-                pfctl.s.cnt1ena = 1;
-                if (!cvmx_octeon_is_pass1())
+                        break;
+                case 1:
+                        pfctl.s.cnt1sel = event;
+                        pfctl.s.cnt1ena = 1;
                         pfctl.s.cnt1rdclr = clear_on_read;
-                break;
-        case 2:
-                pfctl.s.cnt2sel = event;
-                pfctl.s.cnt2ena = 1;
-                if (!cvmx_octeon_is_pass1())
+                        break;
+                case 2:
+                        pfctl.s.cnt2sel = event;
+                        pfctl.s.cnt2ena = 1;
                         pfctl.s.cnt2rdclr = clear_on_read;
-                break;
-        case 3:
-        default:
-                pfctl.s.cnt3sel = event;
-                pfctl.s.cnt3ena = 1;
-                if (!cvmx_octeon_is_pass1())
+                        break;
+                case 3:
+                default:
+                        pfctl.s.cnt3sel = event;
+                        pfctl.s.cnt3ena = 1;
                         pfctl.s.cnt3rdclr = clear_on_read;
-                break;
-        }
+                        break;
+                }
 
-        cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
+                cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
+        } else {
+                union cvmx_l2c_tadx_prf l2c_tadx_prf;
+                int tad;
+
+                cvmx_dprintf("L2C performance counter events are different for this chip, mapping 'event' to cvmx_l2c_tad_event_t\n");
+                if (clear_on_read)
+                        cvmx_dprintf("L2C counters don't support clear on read for this chip\n");
+
+                l2c_tadx_prf.u64 = cvmx_read_csr(CVMX_L2C_TADX_PRF(0));
+
+                switch (counter) {
+                case 0:
+                        l2c_tadx_prf.s.cnt0sel = event;
+                        break;
+                case 1:
+                        l2c_tadx_prf.s.cnt1sel = event;
+                        break;
+                case 2:
+                        l2c_tadx_prf.s.cnt2sel = event;
+                        break;
+                default:
+                case 3:
+                        l2c_tadx_prf.s.cnt3sel = event;
+                        break;
+                }
+                for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                        cvmx_write_csr(CVMX_L2C_TADX_PRF(tad),
+                                       l2c_tadx_prf.u64);
+        }
 }
 
 uint64_t cvmx_l2c_read_perf(uint32_t counter)
 {
         switch (counter) {
         case 0:
-                return cvmx_read_csr(CVMX_L2C_PFC0);
+                if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                        return cvmx_read_csr(CVMX_L2C_PFC0);
+                else {
+                        uint64_t counter = 0;
+                        int tad;
+                        for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));
+                        return counter;
+                }
         case 1:
-                return cvmx_read_csr(CVMX_L2C_PFC1);
+                if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                        return cvmx_read_csr(CVMX_L2C_PFC1);
+                else {
+                        uint64_t counter = 0;
+                        int tad;
+                        for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));
+                        return counter;
+                }
         case 2:
-                return cvmx_read_csr(CVMX_L2C_PFC2);
+                if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                        return cvmx_read_csr(CVMX_L2C_PFC2);
+                else {
+                        uint64_t counter = 0;
+                        int tad;
+                        for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));
+                        return counter;
+                }
         case 3:
         default:
-                return cvmx_read_csr(CVMX_L2C_PFC3);
+                if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                        return cvmx_read_csr(CVMX_L2C_PFC3);
+                else {
+                        uint64_t counter = 0;
+                        int tad;
+                        for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));
+                        return counter;
+                }
         }
 }
 
@@ -240,7 +288,7 @@ static void fault_in(uint64_t addr, int len)
         volatile char dummy;
         /*
          * Adjust addr and length so we get all cache lines even for
-         * small ranges spanning two cache lines
+         * small ranges spanning two cache lines.
          */
         len += addr & CVMX_CACHE_LINE_MASK;
         addr &= ~CVMX_CACHE_LINE_MASK;
@@ -259,67 +307,100 @@ static void fault_in(uint64_t addr, int len)
 
 int cvmx_l2c_lock_line(uint64_t addr)
 {
-        int retval = 0;
-        union cvmx_l2c_dbg l2cdbg;
-        union cvmx_l2c_lckbase lckbase;
-        union cvmx_l2c_lckoff lckoff;
-        union cvmx_l2t_err l2t_err;
-        l2cdbg.u64 = 0;
-        lckbase.u64 = 0;
-        lckoff.u64 = 0;
-
-        cvmx_spinlock_lock(&cvmx_l2c_spinlock);
-
-        /* Clear l2t error bits if set */
-        l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
-        l2t_err.s.lckerr = 1;
-        l2t_err.s.lckerr2 = 1;
-        cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                int shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
+                uint64_t assoc = cvmx_l2c_get_num_assoc();
+                uint64_t tag = addr >> shift;
+                uint64_t index = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, cvmx_l2c_address_to_index(addr) << CVMX_L2C_IDX_ADDR_SHIFT);
+                uint64_t way;
+                union cvmx_l2c_tadx_tag l2c_tadx_tag;
+
+                CVMX_CACHE_LCKL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, addr), 0);
+
+                /* Make sure we were able to lock the line */
+                for (way = 0; way < assoc; way++) {
+                        CVMX_CACHE_LTGL2I(index | (way << shift), 0);
+                        /* make sure CVMX_L2C_TADX_TAG is updated */
+                        CVMX_SYNC;
+                        l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+                        if (l2c_tadx_tag.s.valid && l2c_tadx_tag.s.tag == tag)
+                                break;
+                }
 
-        addr &= ~CVMX_CACHE_LINE_MASK;
+                /* Check if a valid line is found */
+                if (way >= assoc) {
+                        /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: line not found for locking at 0x%llx address\n", (unsigned long long)addr); */
+                        return -1;
+                }
 
-        /* Set this core as debug core */
-        l2cdbg.s.ppnum = cvmx_get_core_num();
-        CVMX_SYNC;
-        cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
-        cvmx_read_csr(CVMX_L2C_DBG);
-
-        lckoff.s.lck_offset = 0;        /* Only lock 1 line at a time */
-        cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
-        cvmx_read_csr(CVMX_L2C_LCKOFF);
-
-        if (((union cvmx_l2c_cfg) (cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
-                int alias_shift =
-                    CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
-                uint64_t addr_tmp =
-                    addr ^ (addr & ((1 << alias_shift) - 1)) >>
-                    CVMX_L2_SET_BITS;
-                lckbase.s.lck_base = addr_tmp >> 7;
+                /* Check if lock bit is not set */
+                if (!l2c_tadx_tag.s.lock) {
+                        /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: Not able to lock at 0x%llx address\n", (unsigned long long)addr); */
+                        return -1;
+                }
+                return way;
         } else {
-                lckbase.s.lck_base = addr >> 7;
-        }
+                int retval = 0;
+                union cvmx_l2c_dbg l2cdbg;
+                union cvmx_l2c_lckbase lckbase;
+                union cvmx_l2c_lckoff lckoff;
+                union cvmx_l2t_err l2t_err;
 
-        lckbase.s.lck_ena = 1;
-        cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
-        cvmx_read_csr(CVMX_L2C_LCKBASE);        /* Make sure it gets there */
+                cvmx_spinlock_lock(&cvmx_l2c_spinlock);
 
-        fault_in(addr, CVMX_CACHE_LINE_SIZE);
+                l2cdbg.u64 = 0;
+                lckbase.u64 = 0;
+                lckoff.u64 = 0;
 
-        lckbase.s.lck_ena = 0;
-        cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
-        cvmx_read_csr(CVMX_L2C_LCKBASE);        /* Make sure it gets there */
+                /* Clear l2t error bits if set */
+                l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+                l2t_err.s.lckerr = 1;
+                l2t_err.s.lckerr2 = 1;
+                cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
 
-        /* Stop being debug core */
-        cvmx_write_csr(CVMX_L2C_DBG, 0);
-        cvmx_read_csr(CVMX_L2C_DBG);
+                addr &= ~CVMX_CACHE_LINE_MASK;
 
-        l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
-        if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
-                retval = 1;     /* We were unable to lock the line */
+                /* Set this core as debug core */
+                l2cdbg.s.ppnum = cvmx_get_core_num();
+                CVMX_SYNC;
+                cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+                cvmx_read_csr(CVMX_L2C_DBG);
+
+                lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
+                cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
+                cvmx_read_csr(CVMX_L2C_LCKOFF);
+
+                if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
+                        int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
+                        uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;
+                        lckbase.s.lck_base = addr_tmp >> 7;
+                } else {
+                        lckbase.s.lck_base = addr >> 7;
+                }
 
-        cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+                lckbase.s.lck_ena = 1;
+                cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+                /* Make sure it gets there */
+                cvmx_read_csr(CVMX_L2C_LCKBASE);
 
-        return retval;
+                fault_in(addr, CVMX_CACHE_LINE_SIZE);
+
+                lckbase.s.lck_ena = 0;
+                cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+                /* Make sure it gets there */
+                cvmx_read_csr(CVMX_L2C_LCKBASE);
+
+                /* Stop being debug core */
+                cvmx_write_csr(CVMX_L2C_DBG, 0);
+                cvmx_read_csr(CVMX_L2C_DBG);
+
+                l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+                if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
+                        retval = 1;  /* We were unable to lock the line */
+
+                cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+                return retval;
+        }
 }
 
 int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
@@ -336,7 +417,6 @@ int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
                 start += CVMX_CACHE_LINE_SIZE;
                 len -= CVMX_CACHE_LINE_SIZE;
         }
-
         return retval;
 }
 
@@ -344,80 +424,73 @@ void cvmx_l2c_flush(void)
 {
         uint64_t assoc, set;
         uint64_t n_assoc, n_set;
-        union cvmx_l2c_dbg l2cdbg;
-
-        cvmx_spinlock_lock(&cvmx_l2c_spinlock);
 
-        l2cdbg.u64 = 0;
-        if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
-                l2cdbg.s.ppnum = cvmx_get_core_num();
-        l2cdbg.s.finv = 1;
-        n_set = CVMX_L2_SETS;
-        n_assoc = l2_size_half() ? (CVMX_L2_ASSOC / 2) : CVMX_L2_ASSOC;
-        for (set = 0; set < n_set; set++) {
-                for (assoc = 0; assoc < n_assoc; assoc++) {
-                        l2cdbg.s.set = assoc;
-                        /* Enter debug mode, and make sure all other
-                         ** writes complete before we enter debug
-                         ** mode */
-                        CVMX_SYNCW;
-                        cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
-                        cvmx_read_csr(CVMX_L2C_DBG);
-
-                        CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
-                                               (CVMX_MIPS_SPACE_XKPHYS,
-                                                set * CVMX_CACHE_LINE_SIZE), 0);
-                        CVMX_SYNCW;     /* Push STF out to L2 */
-                        /* Exit debug mode */
-                        CVMX_SYNC;
-                        cvmx_write_csr(CVMX_L2C_DBG, 0);
-                        cvmx_read_csr(CVMX_L2C_DBG);
+        n_set = cvmx_l2c_get_num_sets();
+        n_assoc = cvmx_l2c_get_num_assoc();
+
+        if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                uint64_t address;
+                /* These may look like constants, but they aren't... */
+                int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
+                int set_shift = CVMX_L2C_IDX_ADDR_SHIFT;
+                for (set = 0; set < n_set; set++) {
+                        for (assoc = 0; assoc < n_assoc; assoc++) {
+                                address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                                       (assoc << assoc_shift) | (set << set_shift));
+                                CVMX_CACHE_WBIL2I(address, 0);
+                        }
                 }
+        } else {
+                for (set = 0; set < n_set; set++)
+                        for (assoc = 0; assoc < n_assoc; assoc++)
+                                cvmx_l2c_flush_line(assoc, set);
         }
-
-        cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
 }
 
+
 int cvmx_l2c_unlock_line(uint64_t address)
 {
-        int assoc;
-        union cvmx_l2c_tag tag;
-        union cvmx_l2c_dbg l2cdbg;
-        uint32_t tag_addr;
 
-        uint32_t index = cvmx_l2c_address_to_index(address);
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                int assoc;
+                union cvmx_l2c_tag tag;
+                uint32_t tag_addr;
+                uint32_t index = cvmx_l2c_address_to_index(address);
+
+                tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+
+                /*
+                 * For 63XX, we can flush a line by using the physical
+                 * address directly, so finding the cache line used by
+                 * the address is only required to provide the proper
+                 * return value for the function.
+                 */
+                for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
+                        tag = cvmx_l2c_get_tag(assoc, index);
+
+                        if (tag.s.V && (tag.s.addr == tag_addr)) {
+                                CVMX_CACHE_WBIL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, address), 0);
+                                return tag.s.L;
+                        }
+                }
+        } else {
+                int assoc;
+                union cvmx_l2c_tag tag;
+                uint32_t tag_addr;
 
-        cvmx_spinlock_lock(&cvmx_l2c_spinlock);
-        /* Compute portion of address that is stored in tag */
-        tag_addr =
-            ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) &
-             ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
-        for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
-                tag = cvmx_get_l2c_tag(assoc, index);
+                uint32_t index = cvmx_l2c_address_to_index(address);
 
-                if (tag.s.V && (tag.s.addr == tag_addr)) {
-                        l2cdbg.u64 = 0;
-                        l2cdbg.s.ppnum = cvmx_get_core_num();
-                        l2cdbg.s.set = assoc;
-                        l2cdbg.s.finv = 1;
+                /* Compute portion of address that is stored in tag */
+                tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+                for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
+                        tag = cvmx_l2c_get_tag(assoc, index);
 
-                        CVMX_SYNC;
-                        /* Enter debug mode */
-                        cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
-                        cvmx_read_csr(CVMX_L2C_DBG);
-
-                        CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
-                                               (CVMX_MIPS_SPACE_XKPHYS,
-                                                address), 0);
-                        CVMX_SYNC;
-                        /* Exit debug mode */
-                        cvmx_write_csr(CVMX_L2C_DBG, 0);
-                        cvmx_read_csr(CVMX_L2C_DBG);
-                        cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
-                        return tag.s.L;
+                        if (tag.s.V && (tag.s.addr == tag_addr)) {
+                                cvmx_l2c_flush_line(assoc, index);
+                                return tag.s.L;
+                        }
                 }
         }
-        cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
         return 0;
 }
 
@@ -445,48 +518,49 @@ union __cvmx_l2c_tag {
         uint64_t u64;
         struct cvmx_l2c_tag_cn50xx {
                 uint64_t reserved:40;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:20;       /* Phys mem addr (33..14) */
         } cn50xx;
         struct cvmx_l2c_tag_cn30xx {
                 uint64_t reserved:41;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:19;       /* Phys mem addr (33..15) */
         } cn30xx;
         struct cvmx_l2c_tag_cn31xx {
                 uint64_t reserved:42;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:18;       /* Phys mem addr (33..16) */
         } cn31xx;
         struct cvmx_l2c_tag_cn38xx {
                 uint64_t reserved:43;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:17;       /* Phys mem addr (33..17) */
         } cn38xx;
         struct cvmx_l2c_tag_cn58xx {
                 uint64_t reserved:44;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:16;       /* Phys mem addr (33..18) */
         } cn58xx;
         struct cvmx_l2c_tag_cn58xx cn56xx;      /* 2048 sets */
         struct cvmx_l2c_tag_cn31xx cn52xx;      /* 512 sets */
 };
 
+
 /**
  * @INTERNAL
  * Function to read a L2C tag.  This code make the current core
@@ -503,7 +577,7 @@ union __cvmx_l2c_tag {
 static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
 {
 
-        uint64_t debug_tag_addr = (((1ULL << 63) | (index << 7)) + 96);
+        uint64_t debug_tag_addr = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, (index << 7) + 96);
         uint64_t core = cvmx_get_core_num();
         union __cvmx_l2c_tag tag_val;
         uint64_t dbg_addr = CVMX_L2C_DBG;
@@ -512,12 +586,15 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
         union cvmx_l2c_dbg debug_val;
         debug_val.u64 = 0;
         /*
-         * For low core count parts, the core number is always small enough
-         * to stay in the correct field and not set any reserved bits.
+         * For low core count parts, the core number is always small
+         * enough to stay in the correct field and not set any
+         * reserved bits.
          */
         debug_val.s.ppnum = core;
         debug_val.s.l2t = 1;
         debug_val.s.set = assoc;
+
+        local_irq_save(flags);
         /*
          * Make sure core is quiet (no prefetches, etc.) before
          * entering debug mode.
@@ -526,112 +603,139 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
         /* Flush L1 to make sure debug load misses L1 */
         CVMX_DCACHE_INVALIDATE;
 
-        local_irq_save(flags);
-
         /*
          * The following must be done in assembly as when in debug
          * mode all data loads from L2 return special debug data, not
-         * normal memory contents.  Also, interrupts must be
-         * disabled, since if an interrupt occurs while in debug mode
-         * the ISR will get debug data from all its memory reads
-         * instead of the contents of memory
+         * normal memory contents.  Also, interrupts must be disabled,
+         * since if an interrupt occurs while in debug mode the ISR
+         * will get debug data from all its memory * reads instead of
+         * the contents of memory.
          */
 
-        asm volatile (".set push              \n"
-                "        .set mips64              \n"
-                "        .set noreorder           \n"
-                /* Enter debug mode, wait for store */
-                "        sd    %[dbg_val], 0(%[dbg_addr])  \n"
-                "        ld    $0, 0(%[dbg_addr]) \n"
-                /* Read L2C tag data */
-                "        ld    %[tag_val], 0(%[tag_addr]) \n"
-                /* Exit debug mode, wait for store */
-                "        sd    $0, 0(%[dbg_addr])  \n"
-                "        ld    $0, 0(%[dbg_addr]) \n"
-                /* Invalidate dcache to discard debug data */
-                "        cache 9, 0($0) \n"
-                "        .set pop" :
-                [tag_val] "=r"(tag_val.u64) : [dbg_addr] "r"(dbg_addr),
-                [dbg_val] "r"(debug_val.u64),
-                [tag_addr] "r"(debug_tag_addr) : "memory");
+        asm volatile (
+                ".set push\n\t"
+                ".set mips64\n\t"
+                ".set noreorder\n\t"
+                "sd    %[dbg_val], 0(%[dbg_addr])\n\t"   /* Enter debug mode, wait for store */
+                "ld    $0, 0(%[dbg_addr])\n\t"
+                "ld    %[tag_val], 0(%[tag_addr])\n\t"   /* Read L2C tag data */
+                "sd    $0, 0(%[dbg_addr])\n\t"          /* Exit debug mode, wait for store */
+                "ld    $0, 0(%[dbg_addr])\n\t"
+                "cache 9, 0($0)\n\t"             /* Invalidate dcache to discard debug data */
+                ".set pop"
+                : [tag_val] "=r" (tag_val)
+                : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr)
+                : "memory");
 
         local_irq_restore(flags);
-        return tag_val;
 
+        return tag_val;
 }
 
+
 union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
 {
-        union __cvmx_l2c_tag tmp_tag;
         union cvmx_l2c_tag tag;
         tag.u64 = 0;
 
         if ((int)association >= cvmx_l2c_get_num_assoc()) {
-                cvmx_dprintf
-                    ("ERROR: cvmx_get_l2c_tag association out of range\n");
+                cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n");
                 return tag;
         }
         if ((int)index >= cvmx_l2c_get_num_sets()) {
-                cvmx_dprintf("ERROR: cvmx_get_l2c_tag "
-                             "index out of range (arg: %d, max: %d\n",
-                     index, cvmx_l2c_get_num_sets());
+                cvmx_dprintf("ERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)\n",
+                             (int)index, cvmx_l2c_get_num_sets());
                 return tag;
         }
-        /* __read_l2_tag is intended for internal use only */
-        tmp_tag = __read_l2_tag(association, index);
-
-        /*
-         * Convert all tag structure types to generic version, as it
-         * can represent all models.
-         */
-        if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
-                tag.s.V = tmp_tag.cn58xx.V;
-                tag.s.D = tmp_tag.cn58xx.D;
-                tag.s.L = tmp_tag.cn58xx.L;
-                tag.s.U = tmp_tag.cn58xx.U;
-                tag.s.addr = tmp_tag.cn58xx.addr;
-        } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
-                tag.s.V = tmp_tag.cn38xx.V;
-                tag.s.D = tmp_tag.cn38xx.D;
-                tag.s.L = tmp_tag.cn38xx.L;
-                tag.s.U = tmp_tag.cn38xx.U;
-                tag.s.addr = tmp_tag.cn38xx.addr;
-        } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
-                   || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
-                tag.s.V = tmp_tag.cn31xx.V;
-                tag.s.D = tmp_tag.cn31xx.D;
-                tag.s.L = tmp_tag.cn31xx.L;
-                tag.s.U = tmp_tag.cn31xx.U;
-                tag.s.addr = tmp_tag.cn31xx.addr;
-        } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
-                tag.s.V = tmp_tag.cn30xx.V;
-                tag.s.D = tmp_tag.cn30xx.D;
-                tag.s.L = tmp_tag.cn30xx.L;
-                tag.s.U = tmp_tag.cn30xx.U;
-                tag.s.addr = tmp_tag.cn30xx.addr;
-        } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
-                tag.s.V = tmp_tag.cn50xx.V;
-                tag.s.D = tmp_tag.cn50xx.D;
-                tag.s.L = tmp_tag.cn50xx.L;
-                tag.s.U = tmp_tag.cn50xx.U;
-                tag.s.addr = tmp_tag.cn50xx.addr;
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                union cvmx_l2c_tadx_tag l2c_tadx_tag;
+                uint64_t address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                                (association << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+                                                (index << CVMX_L2C_IDX_ADDR_SHIFT));
+                /*
+                 * Use L2 cache Index load tag cache instruction, as
+                 * hardware loads the virtual tag for the L2 cache
+                 * block with the contents of L2C_TAD0_TAG
+                 * register.
+                 */
+                CVMX_CACHE_LTGL2I(address, 0);
+                CVMX_SYNC;   /* make sure CVMX_L2C_TADX_TAG is updated */
+                l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+
+                tag.s.V     = l2c_tadx_tag.s.valid;
+                tag.s.D     = l2c_tadx_tag.s.dirty;
+                tag.s.L     = l2c_tadx_tag.s.lock;
+                tag.s.U     = l2c_tadx_tag.s.use;
+                tag.s.addr  = l2c_tadx_tag.s.tag;
         } else {
-                cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
+                union __cvmx_l2c_tag tmp_tag;
+                /* __read_l2_tag is intended for internal use only */
+                tmp_tag = __read_l2_tag(association, index);
+
+                /*
+                 * Convert all tag structure types to generic version,
+                 * as it can represent all models.
+                 */
+                if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
+                        tag.s.V    = tmp_tag.cn58xx.V;
+                        tag.s.D    = tmp_tag.cn58xx.D;
+                        tag.s.L    = tmp_tag.cn58xx.L;
+                        tag.s.U    = tmp_tag.cn58xx.U;
+                        tag.s.addr = tmp_tag.cn58xx.addr;
+                } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
+                        tag.s.V    = tmp_tag.cn38xx.V;
+                        tag.s.D    = tmp_tag.cn38xx.D;
+                        tag.s.L    = tmp_tag.cn38xx.L;
+                        tag.s.U    = tmp_tag.cn38xx.U;
+                        tag.s.addr = tmp_tag.cn38xx.addr;
+                } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                        tag.s.V    = tmp_tag.cn31xx.V;
+                        tag.s.D    = tmp_tag.cn31xx.D;
+                        tag.s.L    = tmp_tag.cn31xx.L;
+                        tag.s.U    = tmp_tag.cn31xx.U;
+                        tag.s.addr = tmp_tag.cn31xx.addr;
+                } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
+                        tag.s.V    = tmp_tag.cn30xx.V;
+                        tag.s.D    = tmp_tag.cn30xx.D;
+                        tag.s.L    = tmp_tag.cn30xx.L;
+                        tag.s.U    = tmp_tag.cn30xx.U;
+                        tag.s.addr = tmp_tag.cn30xx.addr;
+                } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                        tag.s.V    = tmp_tag.cn50xx.V;
+                        tag.s.D    = tmp_tag.cn50xx.D;
+                        tag.s.L    = tmp_tag.cn50xx.L;
+                        tag.s.U    = tmp_tag.cn50xx.U;
+                        tag.s.addr = tmp_tag.cn50xx.addr;
+                } else {
+                        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
+                }
         }
-
         return tag;
 }
 
 uint32_t cvmx_l2c_address_to_index(uint64_t addr)
 {
         uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT;
-        union cvmx_l2c_cfg l2c_cfg;
-        l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+        int indxalias = 0;
 
-        if (l2c_cfg.s.idxalias) {
-                idx ^=
-                    ((addr & CVMX_L2C_ALIAS_MASK) >>
-                     CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+        if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                union cvmx_l2c_ctl l2c_ctl;
+                l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
+                indxalias = !l2c_ctl.s.disidxalias;
+        } else {
+                union cvmx_l2c_cfg l2c_cfg;
+                l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+                indxalias = l2c_cfg.s.idxalias;
+        }
+
+        if (indxalias) {
+                if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                        uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7;
+                        idx ^= idx / cvmx_l2c_get_num_sets();
+                        idx ^= a_14_12;
+                } else {
+                        idx ^= ((addr & CVMX_L2C_ALIAS_MASK) >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+                }
         }
         idx &= CVMX_L2C_IDX_MASK;
         return idx;
@@ -652,10 +756,9 @@ int cvmx_l2c_get_set_bits(void)
         int l2_set_bits;
         if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
                 l2_set_bits = 11;       /* 2048 sets */
-        else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+        else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
                 l2_set_bits = 10;       /* 1024 sets */
-        else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
-                 || OCTEON_IS_MODEL(OCTEON_CN52XX))
+        else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
                 l2_set_bits = 9;        /* 512 sets */
         else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
                 l2_set_bits = 8;        /* 256 sets */
@@ -666,7 +769,6 @@ int cvmx_l2c_get_set_bits(void)
                 l2_set_bits = 11;       /* 2048 sets */
         }
         return l2_set_bits;
-
 }
 
 /* Return the number of sets in the L2 Cache */
@@ -682,8 +784,11 @@ int cvmx_l2c_get_num_assoc(void)
         if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
             OCTEON_IS_MODEL(OCTEON_CN52XX) ||
             OCTEON_IS_MODEL(OCTEON_CN58XX) ||
-            OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN38XX))
+            OCTEON_IS_MODEL(OCTEON_CN50XX) ||
+            OCTEON_IS_MODEL(OCTEON_CN38XX))
                 l2_assoc = 8;
+        else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+                l2_assoc = 16;
         else if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
                  OCTEON_IS_MODEL(OCTEON_CN30XX))
                 l2_assoc = 4;
@@ -693,11 +798,42 @@ int cvmx_l2c_get_num_assoc(void)
         }
 
         /* Check to see if part of the cache is disabled */
-        if (cvmx_fuse_read(265))
-                l2_assoc = l2_assoc >> 2;
-        else if (cvmx_fuse_read(264))
-                l2_assoc = l2_assoc >> 1;
-
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                union cvmx_mio_fus_dat3 mio_fus_dat3;
+
+                mio_fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
+                /*
+                 * cvmx_mio_fus_dat3.s.l2c_crip fuses map as follows
+                 * <2> will be not used for 63xx
+                 * <1> disables 1/2 ways
+                 * <0> disables 1/4 ways
+                 * They are cumulative, so for 63xx:
+                 * <1> <0>
+                 * 0 0 16-way 2MB cache
+                 * 0 1 12-way 1.5MB cache
+                 * 1 0 8-way 1MB cache
+                 * 1 1 4-way 512KB cache
+                 */
+
+                if (mio_fus_dat3.s.l2c_crip == 3)
+                        l2_assoc = 4;
+                else if (mio_fus_dat3.s.l2c_crip == 2)
+                        l2_assoc = 8;
+                else if (mio_fus_dat3.s.l2c_crip == 1)
+                        l2_assoc = 12;
+        } else {
+                union cvmx_l2d_fus3 val;
+                val.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
+                /*
+                 * Using shifts here, as bit position names are
+                 * different for each model but they all mean the
+                 * same.
+                 */
+                if ((val.u64 >> 35) & 0x1)
+                        l2_assoc = l2_assoc >> 2;
+                else if ((val.u64 >> 34) & 0x1)
+                        l2_assoc = l2_assoc >> 1;
+        }
         return l2_assoc;
 }
 
@@ -711,24 +847,54 @@ int cvmx_l2c_get_num_assoc(void)
  */
 void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
 {
-        union cvmx_l2c_dbg l2cdbg;
+        /* Check the range of the index. */
+        if (index > (uint32_t)cvmx_l2c_get_num_sets()) {
+                cvmx_dprintf("ERROR: cvmx_l2c_flush_line index out of range.\n");
+                return;
+        }
 
-        l2cdbg.u64 = 0;
-        l2cdbg.s.ppnum = cvmx_get_core_num();
-        l2cdbg.s.finv = 1;
+        /* Check the range of association. */
+        if (assoc > (uint32_t)cvmx_l2c_get_num_assoc()) {
+                cvmx_dprintf("ERROR: cvmx_l2c_flush_line association out of range.\n");
+                return;
+        }
 
-        l2cdbg.s.set = assoc;
-        /*
-         * Enter debug mode, and make sure all other writes complete
-         * before we enter debug mode.
-         */
-        asm volatile ("sync" : : : "memory");
-        cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
-        cvmx_read_csr(CVMX_L2C_DBG);
-
-        CVMX_PREPARE_FOR_STORE(((1ULL << 63) + (index) * 128), 0);
-        /* Exit debug mode */
-        asm volatile ("sync" : : : "memory");
-        cvmx_write_csr(CVMX_L2C_DBG, 0);
-        cvmx_read_csr(CVMX_L2C_DBG);
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                uint64_t address;
+                /* Create the address based on index and association.
+                 * Bits<20:17> select the way of the cache block involved in
+                 *             the operation
+                 * Bits<16:7> of the effect address select the index
+                 */
+                address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                (assoc << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+                                (index << CVMX_L2C_IDX_ADDR_SHIFT));
+                CVMX_CACHE_WBIL2I(address, 0);
+        } else {
+                union cvmx_l2c_dbg l2cdbg;
+
+                l2cdbg.u64 = 0;
+                if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
+                        l2cdbg.s.ppnum = cvmx_get_core_num();
+                l2cdbg.s.finv = 1;
+
+                l2cdbg.s.set = assoc;
+                cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+                /*
+                 * Enter debug mode, and make sure all other writes
+                 * complete before we enter debug mode
+                 */
+                CVMX_SYNC;
+                cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+                cvmx_read_csr(CVMX_L2C_DBG);
+
+                CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                                    index * CVMX_CACHE_LINE_SIZE),
+                                       0);
+                /* Exit debug mode */
+                CVMX_SYNC;
+                cvmx_write_csr(CVMX_L2C_DBG, 0);
+                cvmx_read_csr(CVMX_L2C_DBG);
+                cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+        }
 }
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 62ac30eef5e8..cecaf62aef32 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -3,13 +3,15 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004-2009 Cavium Networks
+ * Copyright (C) 2004-2010 Cavium Networks
  * Copyright (C) 2008 Wind River Systems
  */
 
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/i2c.h>
+#include <linux/usb.h>
+#include <linux/dma-mapping.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
@@ -198,7 +200,7 @@ static int __init octeon_i2c_device_init(void)
                 num_ports = 1;
 
         for (port = 0; port < num_ports; port++) {
-                octeon_i2c_data[port].sys_freq = octeon_get_clock_rate();
+                octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate();
                 /*FIXME: should be examined. At the moment is set for 100Khz */
                 octeon_i2c_data[port].i2c_freq = 100000;
 
@@ -301,6 +303,10 @@ static int __init octeon_mgmt_device_init(void)
                         ret = -ENOMEM;
                         goto out;
                 }
+                /* No DMA restrictions */
+                pd->dev.coherent_dma_mask = DMA_BIT_MASK(64);
+                pd->dev.dma_mask = &pd->dev.coherent_dma_mask;
+
                 switch (port) {
                 case 0:
                         mgmt_port_resource.start = OCTEON_IRQ_MII0;
@@ -332,6 +338,108 @@ out:
 }
 device_initcall(octeon_mgmt_device_init);
 
+#ifdef CONFIG_USB
+
+static int __init octeon_ehci_device_init(void)
+{
+        struct platform_device *pd;
+        int ret = 0;
+
+        struct resource usb_resources[] = {
+                {
+                        .flags  = IORESOURCE_MEM,
+                }, {
+                        .flags  = IORESOURCE_IRQ,
+                }
+        };
+
+        /* Only Octeon2 has ehci/ohci */
+        if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+                return 0;
+
+        if (octeon_is_simulation() || usb_disabled())
+                return 0; /* No USB in the simulator. */
+
+        pd = platform_device_alloc("octeon-ehci", 0);
+        if (!pd) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        usb_resources[0].start = 0x00016F0000000000ULL;
+        usb_resources[0].end = usb_resources[0].start + 0x100;
+
+        usb_resources[1].start = OCTEON_IRQ_USB0;
+        usb_resources[1].end = OCTEON_IRQ_USB0;
+
+        ret = platform_device_add_resources(pd, usb_resources,
+                                            ARRAY_SIZE(usb_resources));
+        if (ret)
+                goto fail;
+
+        ret = platform_device_add(pd);
+        if (ret)
+                goto fail;
+
+        return ret;
+fail:
+        platform_device_put(pd);
+out:
+        return ret;
+}
+device_initcall(octeon_ehci_device_init);
+
+static int __init octeon_ohci_device_init(void)
+{
+        struct platform_device *pd;
+        int ret = 0;
+
+        struct resource usb_resources[] = {
+                {
+                        .flags  = IORESOURCE_MEM,
+                }, {
+                        .flags  = IORESOURCE_IRQ,
+                }
+        };
+
+        /* Only Octeon2 has ehci/ohci */
+        if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+                return 0;
+
+        if (octeon_is_simulation() || usb_disabled())
+                return 0; /* No USB in the simulator. */
+
+        pd = platform_device_alloc("octeon-ohci", 0);
+        if (!pd) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        usb_resources[0].start = 0x00016F0000000400ULL;
+        usb_resources[0].end = usb_resources[0].start + 0x100;
+
+        usb_resources[1].start = OCTEON_IRQ_USB0;
+        usb_resources[1].end = OCTEON_IRQ_USB0;
+
+        ret = platform_device_add_resources(pd, usb_resources,
+                                            ARRAY_SIZE(usb_resources));
+        if (ret)
+                goto fail;
+
+        ret = platform_device_add(pd);
+        if (ret)
+                goto fail;
+
+        return ret;
+fail:
+        platform_device_put(pd);
+out:
+        return ret;
+}
+device_initcall(octeon_ohci_device_init);
+
+#endif /* CONFIG_USB */
+
 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
 MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
index 12dbf533b77d..057f0ae88c99 100644
--- a/arch/mips/cavium-octeon/serial.c
+++ b/arch/mips/cavium-octeon/serial.c
@@ -66,7 +66,7 @@ static void __init octeon_uart_set_common(struct plat_serial8250_port *p)
                 /* Make simulator output fast*/
                 p->uartclk = 115200 * 16;
         else
-                p->uartclk = mips_hpt_frequency;
+                p->uartclk = octeon_get_io_clock_rate();
         p->serial_in = octeon_serial_in;
         p->serial_out = octeon_serial_out;
 }
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 69197cb6c7ea..b0c3686c96dd 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -33,6 +33,7 @@
 
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/pci-octeon.h>
+#include <asm/octeon/cvmx-mio-defs.h>
 
 #ifdef CONFIG_CAVIUM_DECODE_RSL
 extern void cvmx_interrupt_rsl_decode(void);
@@ -96,12 +97,21 @@ int octeon_is_pci_host(void)
  */
 uint64_t octeon_get_clock_rate(void)
 {
-        if (octeon_is_simulation())
-                octeon_bootinfo->eclock_hz = 6000000;
-        return octeon_bootinfo->eclock_hz;
+        struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
+
+        return sysinfo->cpu_clock_hz;
 }
 EXPORT_SYMBOL(octeon_get_clock_rate);
 
+static u64 octeon_io_clock_rate;
+
+u64 octeon_get_io_clock_rate(void)
+{
+        return octeon_io_clock_rate;
+}
+EXPORT_SYMBOL(octeon_get_io_clock_rate);
+
+
 /**
  * Write to the LCD display connected to the bootbus. This display
  * exists on most Cavium evaluation boards. If it doesn't exist, then
@@ -346,8 +356,18 @@ void octeon_user_io_init(void)
         cvmmemctl.s.wbfltime = 0;
         /* R/W If set, do not put Istream in the L2 cache. */
         cvmmemctl.s.istrnol2 = 0;
-        /* R/W The write buffer threshold. */
-        cvmmemctl.s.wbthresh = 10;
+
+        /*
+         * R/W The write buffer threshold. As per erratum Core-14752
+         * for CN63XX, a sc/scd might fail if the write buffer is
+         * full.  Lowering WBTHRESH greatly lowers the chances of the
+         * write buffer ever being full and triggering the erratum.
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+                cvmmemctl.s.wbthresh = 4;
+        else
+                cvmmemctl.s.wbthresh = 10;
+
         /* R/W If set, CVMSEG is available for loads/stores in
          * kernel/debug mode. */
 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
@@ -365,14 +385,13 @@ void octeon_user_io_init(void)
          * is max legal value. */
         cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
 
+        write_c0_cvmmemctl(cvmmemctl.u64);
 
         if (smp_processor_id() == 0)
                 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
                           CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
                           CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
 
-        write_c0_cvmmemctl(cvmmemctl.u64);
-
         /* Move the performance counter interrupts to IRQ 6 */
         cvmctl = read_c0_cvmctl();
         cvmctl &= ~(7 << 7);
@@ -416,6 +435,41 @@ void __init prom_init(void)
                 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
         cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
 
+        sysinfo = cvmx_sysinfo_get();
+        memset(sysinfo, 0, sizeof(*sysinfo));
+        sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
+        sysinfo->phy_mem_desc_ptr =
+                cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
+        sysinfo->core_mask = octeon_bootinfo->core_mask;
+        sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
+        sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
+        sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
+        sysinfo->board_type = octeon_bootinfo->board_type;
+        sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
+        sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
+        memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
+               sizeof(sysinfo->mac_addr_base));
+        sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
+        memcpy(sysinfo->board_serial_number,
+               octeon_bootinfo->board_serial_number,
+               sizeof(sysinfo->board_serial_number));
+        sysinfo->compact_flash_common_base_addr =
+                octeon_bootinfo->compact_flash_common_base_addr;
+        sysinfo->compact_flash_attribute_base_addr =
+                octeon_bootinfo->compact_flash_attribute_base_addr;
+        sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
+        sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
+        sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
+
+        if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                /* I/O clock runs at a different rate than the CPU. */
+                union cvmx_mio_rst_boot rst_boot;
+                rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+                octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
+        } else {
+                octeon_io_clock_rate = sysinfo->cpu_clock_hz;
+        }
+
         /*
          * Only enable the LED controller if we're running on a CN38XX, CN58XX,
          * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
@@ -479,33 +533,6 @@ void __init prom_init(void)
         }
 #endif
 
-        sysinfo = cvmx_sysinfo_get();
-        memset(sysinfo, 0, sizeof(*sysinfo));
-        sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
-        sysinfo->phy_mem_desc_ptr =
-                cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
-        sysinfo->core_mask = octeon_bootinfo->core_mask;
-        sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
-        sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
-        sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
-        sysinfo->board_type = octeon_bootinfo->board_type;
-        sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
-        sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
-        memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
-               sizeof(sysinfo->mac_addr_base));
-        sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
-        memcpy(sysinfo->board_serial_number,
-               octeon_bootinfo->board_serial_number,
-               sizeof(sysinfo->board_serial_number));
-        sysinfo->compact_flash_common_base_addr =
-                octeon_bootinfo->compact_flash_common_base_addr;
-        sysinfo->compact_flash_attribute_base_addr =
-                octeon_bootinfo->compact_flash_attribute_base_addr;
-        sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
-        sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
-        sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
-
-
         octeon_check_cpu_bist();
 
         octeon_uart = octeon_get_boot_uart();
@@ -740,6 +767,31 @@ EXPORT_SYMBOL(prom_putchar);
 
 void prom_free_prom_memory(void)
 {
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
+                /* Check for presence of Core-14449 fix.  */
+                u32 insn;
+                u32 *foo;
+
+                foo = &insn;
+
+                asm volatile("# before" : : : "memory");
+                prefetch(foo);
+                asm volatile(
+                        ".set push\n\t"
+                        ".set noreorder\n\t"
+                        "bal 1f\n\t"
+                        "nop\n"
+                        "1:\tlw %0,-12($31)\n\t"
+                        ".set pop\n\t"
+                        : "=r" (insn) : : "$31", "memory");
+
+                if ((insn >> 26) != 0x33)
+                        panic("No PREF instruction at Core-14449 probe point.\n");
+
+                if (((insn >> 16) & 0x1f) != 28)
+                        panic("Core-14449 WAR not in place (%04x).\n"
+                              "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn);
+        }
 #ifdef CONFIG_CAVIUM_DECODE_RSL
         cvmx_interrupt_rsl_enable();
 
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 47d87da379f9..4a02fe891ab6 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -64,18 +64,16 @@ static __inline__ void atomic_add(int i, atomic_t * v)
         } else if (kernel_uses_llsc) {
                 int temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %1          # atomic_add            \n"
-                "       addu    %0, %2                                  \n"
-                "       sc      %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       ll      %0, %1          # atomic_add    \n"
+                        "       addu    %0, %2                          \n"
+                        "       sc      %0, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
+                } while (unlikely(!temp));
         } else {
                 unsigned long flags;
 
@@ -109,18 +107,16 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
         } else if (kernel_uses_llsc) {
                 int temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %1          # atomic_sub            \n"
-                "       subu    %0, %2                                  \n"
-                "       sc      %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       ll      %0, %1          # atomic_sub    \n"
+                        "       subu    %0, %2                          \n"
+                        "       sc      %0, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
+                } while (unlikely(!temp));
         } else {
                 unsigned long flags;
 
@@ -156,20 +152,19 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
         } else if (kernel_uses_llsc) {
                 int temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %1, %2          # atomic_add_return     \n"
-                "       addu    %0, %1, %3                              \n"
-                "       sc      %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       addu    %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       ll      %1, %2  # atomic_add_return     \n"
+                        "       addu    %0, %1, %3                      \n"
+                        "       sc      %0, %2                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter)
+                        : "memory");
+                } while (unlikely(!result));
+
+                result = temp + i;
         } else {
                 unsigned long flags;
 
@@ -205,23 +200,24 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
+
+                result = temp - i;
         } else if (kernel_uses_llsc) {
                 int temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %1, %2          # atomic_sub_return     \n"
-                "       subu    %0, %1, %3                              \n"
-                "       sc      %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       subu    %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       ll      %1, %2  # atomic_sub_return     \n"
+                        "       subu    %0, %1, %3                      \n"
+                        "       sc      %0, %2                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter)
+                        : "memory");
+                } while (unlikely(!result));
+
+                result = temp - i;
         } else {
                 unsigned long flags;
 
@@ -279,12 +275,9 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                 "       bltz    %0, 1f                                  \n"
                 "       sc      %0, %2                                  \n"
                 "       .set    noreorder                               \n"
-                "       beqz    %0, 2f                                  \n"
+                "       beqz    %0, 1b                                  \n"
                 "        subu   %0, %1, %3                              \n"
                 "       .set    reorder                                 \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
                 "1:                                                     \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
@@ -443,18 +436,16 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
         } else if (kernel_uses_llsc) {
                 long temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %1          # atomic64_add          \n"
-                "       daddu   %0, %2                                  \n"
-                "       scd     %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       lld     %0, %1          # atomic64_add  \n"
+                        "       daddu   %0, %2                          \n"
+                        "       scd     %0, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
+                } while (unlikely(!temp));
         } else {
                 unsigned long flags;
 
@@ -488,18 +479,16 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
         } else if (kernel_uses_llsc) {
                 long temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %1          # atomic64_sub          \n"
-                "       dsubu   %0, %2                                  \n"
-                "       scd     %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       lld     %0, %1          # atomic64_sub  \n"
+                        "       dsubu   %0, %2                          \n"
+                        "       scd     %0, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
+                } while (unlikely(!temp));
         } else {
                 unsigned long flags;
 
@@ -535,20 +524,19 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
         } else if (kernel_uses_llsc) {
                 long temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %1, %2          # atomic64_add_return   \n"
-                "       daddu   %0, %1, %3                              \n"
-                "       scd     %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       daddu   %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       lld     %1, %2  # atomic64_add_return   \n"
+                        "       daddu   %0, %1, %3                      \n"
+                        "       scd     %0, %2                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter)
+                        : "memory");
+                } while (unlikely(!result));
+
+                result = temp + i;
         } else {
                 unsigned long flags;
 
@@ -587,20 +575,19 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
         } else if (kernel_uses_llsc) {
                 long temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %1, %2          # atomic64_sub_return   \n"
-                "       dsubu   %0, %1, %3                              \n"
-                "       scd     %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       dsubu   %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       lld     %1, %2  # atomic64_sub_return   \n"
+                        "       dsubu   %0, %1, %3                      \n"
+                        "       scd     %0, %2                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter)
+                        : "memory");
+                } while (unlikely(!result));
+
+                result = temp - i;
         } else {
                 unsigned long flags;
 
@@ -658,12 +645,9 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                 "       bltz    %0, 1f                                  \n"
                 "       scd     %0, %2                                  \n"
                 "       .set    noreorder                               \n"
-                "       beqz    %0, 2f                                  \n"
+                "       beqz    %0, 1b                                  \n"
                 "        dsubu  %0, %1, %3                              \n"
                 "       .set    reorder                                 \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
                 "1:                                                     \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index b0ce7ca2851f..50b4ef288c53 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -73,30 +73,26 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
                 : "ir" (1UL << bit), "m" (*m));
 #ifdef CONFIG_CPU_MIPSR2
         } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
-                __asm__ __volatile__(
-                "1:     " __LL "%0, %1                  # set_bit       \n"
-                "       " __INS "%0, %4, %2, 1                          \n"
-                "       " __SC "%0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (bit), "m" (*m), "r" (~0));
+                do {
+                        __asm__ __volatile__(
+                        "       " __LL "%0, %1          # set_bit       \n"
+                        "       " __INS "%0, %3, %2, 1                  \n"
+                        "       " __SC "%0, %1                          \n"
+                        : "=&r" (temp), "+m" (*m)
+                        : "ir" (bit), "r" (~0));
+                } while (unlikely(!temp));
 #endif /* CONFIG_CPU_MIPSR2 */
         } else if (kernel_uses_llsc) {
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1                  # set_bit       \n"
-                "       or      %0, %2                                  \n"
-                "       " __SC  "%0, %1                                 \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << bit), "m" (*m));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL "%0, %1          # set_bit       \n"
+                        "       or      %0, %2                          \n"
+                        "       " __SC  "%0, %1                         \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m)
+                        : "ir" (1UL << bit));
+                } while (unlikely(!temp));
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -134,34 +130,30 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
                 "       " __SC "%0, %1                                  \n"
                 "       beqzl   %0, 1b                                  \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (~(1UL << bit)), "m" (*m));
+                : "=&r" (temp), "+m" (*m)
+                : "ir" (~(1UL << bit)));
 #ifdef CONFIG_CPU_MIPSR2
         } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
-                __asm__ __volatile__(
-                "1:     " __LL "%0, %1                  # clear_bit     \n"
-                "       " __INS "%0, $0, %2, 1                          \n"
-                "       " __SC "%0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (bit), "m" (*m));
+                do {
+                        __asm__ __volatile__(
+                        "       " __LL "%0, %1          # clear_bit     \n"
+                        "       " __INS "%0, $0, %2, 1                  \n"
+                        "       " __SC "%0, %1                          \n"
+                        : "=&r" (temp), "+m" (*m)
+                        : "ir" (bit));
+                } while (unlikely(!temp));
 #endif /* CONFIG_CPU_MIPSR2 */
         } else if (kernel_uses_llsc) {
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1                  # clear_bit     \n"
-                "       and     %0, %2                                  \n"
-                "       " __SC "%0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (~(1UL << bit)), "m" (*m));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL "%0, %1          # clear_bit     \n"
+                        "       and     %0, %2                          \n"
+                        "       " __SC "%0, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m)
+                        : "ir" (~(1UL << bit)));
+                } while (unlikely(!temp));
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -213,24 +205,22 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                 "       " __SC  "%0, %1                         \n"
                 "       beqzl   %0, 1b                          \n"
                 "       .set    mips0                           \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << bit), "m" (*m));
+                : "=&r" (temp), "+m" (*m)
+                : "ir" (1UL << bit));
         } else if (kernel_uses_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                           \n"
-                "1:     " __LL "%0, %1          # change_bit    \n"
-                "       xor     %0, %2                          \n"
-                "       " __SC  "%0, %1                         \n"
-                "       beqz    %0, 2f                          \n"
-                "       .subsection 2                           \n"
-                "2:     b       1b                              \n"
-                "       .previous                               \n"
-                "       .set    mips0                           \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << bit), "m" (*m));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL "%0, %1          # change_bit    \n"
+                        "       xor     %0, %2                          \n"
+                        "       " __SC  "%0, %1                         \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m)
+                        : "ir" (1UL << bit));
+                } while (unlikely(!temp));
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -272,30 +262,26 @@ static inline int test_and_set_bit(unsigned long nr,
                 "       beqzl   %2, 1b                                  \n"
                 "       and     %2, %0, %3                              \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
+                : "=&r" (temp), "+m" (*m), "=&r" (res)
+                : "r" (1UL << bit)
                 : "memory");
         } else if (kernel_uses_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
-                "       or      %2, %0, %3                              \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL "%0, %1  # test_and_set_bit      \n"
+                        "       or      %2, %0, %3                      \n"
+                        "       " __SC  "%2, %1                         \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m), "=&r" (res)
+                        : "r" (1UL << bit)
+                        : "memory");
+                } while (unlikely(!res));
+
+                res = temp & (1UL << bit);
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -340,30 +326,26 @@ static inline int test_and_set_bit_lock(unsigned long nr,
                 "       beqzl   %2, 1b                                  \n"
                 "       and     %2, %0, %3                              \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
+                : "=&r" (temp), "+m" (*m), "=&r" (res)
+                : "r" (1UL << bit)
                 : "memory");
         } else if (kernel_uses_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
-                "       or      %2, %0, %3                              \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL "%0, %1  # test_and_set_bit      \n"
+                        "       or      %2, %0, %3                      \n"
+                        "       " __SC  "%2, %1                         \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m), "=&r" (res)
+                        : "r" (1UL << bit)
+                        : "memory");
+                } while (unlikely(!res));
+
+                res = temp & (1UL << bit);
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -410,49 +392,43 @@ static inline int test_and_clear_bit(unsigned long nr,
                 "       beqzl   %2, 1b                                  \n"
                 "       and     %2, %0, %3                              \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
+                : "=&r" (temp), "+m" (*m), "=&r" (res)
+                : "r" (1UL << bit)
                 : "memory");
 #ifdef CONFIG_CPU_MIPSR2
         } else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
-                "       " __EXT "%2, %0, %3, 1                          \n"
-                "       " __INS "%0, $0, %3, 1                          \n"
-                "       " __SC  "%0, %1                                 \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "ir" (bit), "m" (*m)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       " __LL  "%0, %1 # test_and_clear_bit    \n"
+                        "       " __EXT "%2, %0, %3, 1                  \n"
+                        "       " __INS "%0, $0, %3, 1                  \n"
+                        "       " __SC  "%0, %1                         \n"
+                        : "=&r" (temp), "+m" (*m), "=&r" (res)
+                        : "ir" (bit)
+                        : "memory");
+                } while (unlikely(!temp));
 #endif
         } else if (kernel_uses_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
-                "       or      %2, %0, %3                              \n"
-                "       xor     %2, %3                                  \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL  "%0, %1 # test_and_clear_bit    \n"
+                        "       or      %2, %0, %3                      \n"
+                        "       xor     %2, %3                          \n"
+                        "       " __SC  "%2, %1                         \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m), "=&r" (res)
+                        : "r" (1UL << bit)
+                        : "memory");
+                } while (unlikely(!res));
+
+                res = temp & (1UL << bit);
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -499,30 +475,26 @@ static inline int test_and_change_bit(unsigned long nr,
                 "       beqzl   %2, 1b                                  \n"
                 "       and     %2, %0, %3                              \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
+                : "=&r" (temp), "+m" (*m), "=&r" (res)
+                : "r" (1UL << bit)
                 : "memory");
         } else if (kernel_uses_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL  "%0, %1         # test_and_change_bit   \n"
-                "       xor     %2, %0, %3                              \n"
-                "       " __SC  "\t%2, %1                               \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL  "%0, %1 # test_and_change_bit   \n"
+                        "       xor     %2, %0, %3                      \n"
+                        "       " __SC  "\t%2, %1                       \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m), "=&r" (res)
+                        : "r" (1UL << bit)
+                        : "memory");
+                } while (unlikely(!res));
+
+                res = temp & (1UL << bit);
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 15a8ef0707c6..35cd1bab69c3 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -125,4 +125,16 @@ extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
  */
 extern void plat_mem_setup(void);
 
+#ifdef CONFIG_SWIOTLB
+/*
+ * Optional platform hook to call swiotlb_setup().
+ */
+extern void plat_swiotlb_setup(void);
+
+#else
+
+static inline void plat_swiotlb_setup(void) {}
+
+#endif /* CONFIG_SWIOTLB */
+
 #endif /* _ASM_BOOTINFO_H */
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 2d28017e95d0..d8d1c2805ac7 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -44,12 +44,9 @@
                 "       move    $1, %z4                         \n"     \
                 "       .set    mips3                           \n"     \
                 "       " st "  $1, %1                          \n"     \
-                "       beqz    $1, 3f                          \n"     \
-                "2:                                             \n"     \
-                "       .subsection 2                           \n"     \
-                "3:     b       1b                              \n"     \
-                "       .previous                               \n"     \
+                "       beqz    $1, 1b                          \n"     \
                 "       .set    pop                             \n"     \
+                "2:                                             \n"     \
                 : "=&r" (__ret), "=R" (*m)                              \
                 : "R" (*m), "Jr" (old), "Jr" (new)                      \
                 : "memory");                                            \
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index b201a8f5b127..06d59dcbe243 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -111,14 +111,16 @@
  * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
  */
 
-#define PRID_IMP_BCM4710        0x4000
-#define PRID_IMP_BCM3302        0x9000
-#define PRID_IMP_BCM6338        0x9000
-#define PRID_IMP_BCM6345        0x8000
-#define PRID_IMP_BCM6348        0x9100
-#define PRID_IMP_BCM4350        0xA000
-#define PRID_REV_BCM6358        0x0010
-#define PRID_REV_BCM6368        0x0030
+#define PRID_IMP_BMIPS4KC       0x4000
+#define PRID_IMP_BMIPS32        0x8000
+#define PRID_IMP_BMIPS3300      0x9000
+#define PRID_IMP_BMIPS3300_ALT  0x9100
+#define PRID_IMP_BMIPS3300_BUG  0x0000
+#define PRID_IMP_BMIPS43XX      0xa000
+#define PRID_IMP_BMIPS5000      0x5a00
+
+#define PRID_REV_BMIPS4380_LO   0x0040
+#define PRID_REV_BMIPS4380_HI   0x006f
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
@@ -131,6 +133,7 @@
 #define PRID_IMP_CAVIUM_CN56XX 0x0400
 #define PRID_IMP_CAVIUM_CN50XX 0x0600
 #define PRID_IMP_CAVIUM_CN52XX 0x0700
+#define PRID_IMP_CAVIUM_CN63XX 0x9000
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
@@ -223,15 +226,14 @@ enum cpu_type_enum {
          * MIPS32 class processors
          */
         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
-        CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
-        CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
-        CPU_JZRISC,
+        CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
+        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC,
 
         /*
          * MIPS64 class processors
          */
         CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
-        CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+        CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
 
         CPU_LAST
 };
diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h
index 06746c5e8099..c94fafba9e62 100644
--- a/arch/mips/include/asm/device.h
+++ b/arch/mips/include/asm/device.h
@@ -3,4 +3,17 @@
  *
  * This file is released under the GPLv2
  */
-#include <asm-generic/device.h>
+#ifndef _ASM_MIPS_DEVICE_H
+#define _ASM_MIPS_DEVICE_H
+
+struct dma_map_ops;
+
+struct dev_archdata {
+        /* DMA operations on that device */
+        struct dma_map_ops *dma_ops;
+};
+
+struct pdev_archdata {
+};
+
+#endif /* _ASM_MIPS_DEVICE_H*/
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 18fbf7af8e93..655f849bd08d 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -5,51 +5,41 @@
 #include <asm/cache.h>
 #include <asm-generic/dma-coherent.h>
 
-void *dma_alloc_noncoherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t flag);
+#include <dma-coherence.h>
 
-void dma_free_noncoherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle);
+extern struct dma_map_ops *mips_dma_map_ops;
 
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t flag);
+static inline struct dma_map_ops *get_dma_ops(struct device *dev)
+{
+        if (dev && dev->archdata.dma_ops)
+                return dev->archdata.dma_ops;
+        else
+                return mips_dma_map_ops;
+}
 
-void dma_free_coherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle);
+static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+{
+        if (!dev->dma_mask)
+                return 0;
 
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
-        enum dma_data_direction direction);
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
-        size_t size, enum dma_data_direction direction);
-extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-        enum dma_data_direction direction);
-extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
-        unsigned long offset, size_t size, enum dma_data_direction direction);
-
-static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
-        size_t size, enum dma_data_direction direction)
+        return addr + size <= *dev->dma_mask;
+}
+
+static inline void dma_mark_clean(void *addr, size_t size) {}
+
+#include <asm-generic/dma-mapping-common.h>
+
+static inline int dma_supported(struct device *dev, u64 mask)
 {
-        dma_unmap_single(dev, dma_address, size, direction);
+        struct dma_map_ops *ops = get_dma_ops(dev);
+        return ops->dma_supported(dev, mask);
 }
 
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-        int nhwentries, enum dma_data_direction direction);
-extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
-        size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_for_device(struct device *dev,
-        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_range_for_cpu(struct device *dev,
-        dma_addr_t dma_handle, unsigned long offset, size_t size,
-        enum dma_data_direction direction);
-extern void dma_sync_single_range_for_device(struct device *dev,
-        dma_addr_t dma_handle, unsigned long offset, size_t size,
-        enum dma_data_direction direction);
-extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
-        int nelems, enum dma_data_direction direction);
-extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
-        int nelems, enum dma_data_direction direction);
-extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
-extern int dma_supported(struct device *dev, u64 mask);
+static inline int dma_mapping_error(struct device *dev, u64 mask)
+{
+        struct dma_map_ops *ops = get_dma_ops(dev);
+        return ops->mapping_error(dev, mask);
+}
 
 static inline int
 dma_set_mask(struct device *dev, u64 mask)
@@ -65,4 +55,34 @@ dma_set_mask(struct device *dev, u64 mask)
 extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                enum dma_data_direction direction);
 
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+                                       dma_addr_t *dma_handle, gfp_t gfp)
+{
+        void *ret;
+        struct dma_map_ops *ops = get_dma_ops(dev);
+
+        ret = ops->alloc_coherent(dev, size, dma_handle, gfp);
+
+        debug_dma_alloc_coherent(dev, size, *dma_handle, ret);
+
+        return ret;
+}
+
+static inline void dma_free_coherent(struct device *dev, size_t size,
+                                     void *vaddr, dma_addr_t dma_handle)
+{
+        struct dma_map_ops *ops = get_dma_ops(dev);
+
+        ops->free_coherent(dev, size, vaddr, dma_handle);
+
+        debug_dma_free_coherent(dev, size, vaddr, dma_handle);
+}
+
+
+void *dma_alloc_noncoherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, gfp_t flag);
+
+void dma_free_noncoherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle);
+
 #endif /* _ASM_DMA_MAPPING_H */
diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h
index 1353c81065d1..2d47da62d5a7 100644
--- a/arch/mips/include/asm/dma.h
+++ b/arch/mips/include/asm/dma.h
@@ -91,7 +91,10 @@
 #define MAX_DMA_ADDRESS         (PAGE_OFFSET + 0x01000000)
 #endif
 #define MAX_DMA_PFN             PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
+
+#ifndef MAX_DMA32_PFN
 #define MAX_DMA32_PFN           (1UL << (32 - PAGE_SHIFT))
+#endif
 
 /* 8237 DMA controllers */
 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index bdcdef02d147..fffc8307a80a 100644
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -117,7 +117,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
 
 #define local_cmpxchg(l, o, n) \
         ((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
-#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
+#define local_xchg(l, n) (atomic_long_xchg((&(l)->a), (n)))
 
 /**
  * local_add_unless - add unless the number is a given value
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index 483ffea9ecb1..7919d76186bf 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -39,6 +39,7 @@
 #define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
 #define AR7_REGS_USB    (AR7_REGS_BASE + 0x1200)
 #define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
+#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
 #define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1a00)
 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
@@ -50,6 +51,14 @@
 #define UR8_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
 #define UR8_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
 
+/* Titan registers */
+#define TITAN_REGS_ESWITCH_BASE (0x08640000)
+#define TITAN_REGS_MAC0         (TITAN_REGS_ESWITCH_BASE)
+#define TITAN_REGS_MAC1         (TITAN_REGS_ESWITCH_BASE + 0x0800)
+#define TITAN_REGS_MDIO         (TITAN_REGS_ESWITCH_BASE + 0x02000)
+#define TITAN_REGS_VLYNQ0       (AR7_REGS_BASE + 0x1c00)
+#define TITAN_REGS_VLYNQ1       (AR7_REGS_BASE + 0x1300)
+
 #define AR7_RESET_PERIPHERAL    0x0
 #define AR7_RESET_SOFTWARE      0x4
 #define AR7_RESET_STATUS        0x8
@@ -59,15 +68,30 @@
 #define AR7_RESET_BIT_MDIO      22
 #define AR7_RESET_BIT_EPHY      26
 
+#define TITAN_RESET_BIT_EPHY1   28
+
 /* GPIO control registers */
 #define AR7_GPIO_INPUT  0x0
 #define AR7_GPIO_OUTPUT 0x4
 #define AR7_GPIO_DIR    0x8
 #define AR7_GPIO_ENABLE 0xc
+#define TITAN_GPIO_INPUT_0      0x0
+#define TITAN_GPIO_INPUT_1      0x4
+#define TITAN_GPIO_OUTPUT_0     0x8
+#define TITAN_GPIO_OUTPUT_1     0xc
+#define TITAN_GPIO_DIR_0        0x10
+#define TITAN_GPIO_DIR_1        0x14
+#define TITAN_GPIO_ENBL_0       0x18
+#define TITAN_GPIO_ENBL_1       0x1c
 
 #define AR7_CHIP_7100   0x18
 #define AR7_CHIP_7200   0x2b
 #define AR7_CHIP_7300   0x05
+#define AR7_CHIP_TITAN  0x07
+#define TITAN_CHIP_1050 0x0f
+#define TITAN_CHIP_1055 0x0e
+#define TITAN_CHIP_1056 0x0d
+#define TITAN_CHIP_1060 0x07
 
 /* Interrupts */
 #define AR7_IRQ_UART0   15
@@ -95,14 +119,29 @@ struct plat_dsl_data {
 
 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
 
+static inline int ar7_is_titan(void)
+{
+        return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
+                AR7_CHIP_TITAN;
+}
+
 static inline u16 ar7_chip_id(void)
 {
-        return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
+        return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
+                KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
+}
+
+static inline u16 titan_chip_id(void)
+{
+        unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
+                                                TITAN_GPIO_INPUT_1));
+        return ((val >> 12) & 0x0f);
 }
 
 static inline u8 ar7_chip_rev(void)
 {
-        return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
+        return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
+                0x14))) >> 16) & 0xff;
 }
 
 struct clk {
@@ -161,4 +200,8 @@ static inline void ar7_device_off(u32 bit)
         msleep(20);
 }
 
+int __init ar7_gpio_init(void);
+
+int __init ar7_gpio_init(void);
+
 #endif /* __AR7_H__ */
diff --git a/arch/mips/include/asm/mach-ar7/gpio.h b/arch/mips/include/asm/mach-ar7/gpio.h
index abc317c0372e..c177cd1eed25 100644
--- a/arch/mips/include/asm/mach-ar7/gpio.h
+++ b/arch/mips/include/asm/mach-ar7/gpio.h
@@ -22,7 +22,8 @@
 #include <asm/mach-ar7/ar7.h>
 
 #define AR7_GPIO_MAX 32
-#define NR_BUILTIN_GPIO AR7_GPIO_MAX
+#define TITAN_GPIO_MAX  51
+#define NR_BUILTIN_GPIO TITAN_GPIO_MAX
 
 #define gpio_to_irq(gpio)       -1
 
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index b952fc7215e2..0d5a42b5f47a 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -59,7 +59,7 @@
 #define cpu_has_veic            0
 #define cpu_hwrena_impl_bits    0xc0000000
 
-#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
+#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
 
 #define ARCH_HAS_IRQ_PER_CPU    1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
@@ -81,4 +81,10 @@ static inline int octeon_has_saa(void)
         return id >= 0x000d0300;
 }
 
+/*
+ * The last 256MB are reserved for device to device mappings and the
+ * BAR1 hole.
+ */
+#define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT)
+
 #endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index 17d579471ec4..be8fb4240cec 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -15,41 +15,40 @@
 
 struct device;
 
-dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t);
-void octeon_unmap_dma_mem(struct device *, dma_addr_t);
+extern void octeon_pci_dma_init(void);
 
 static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
         size_t size)
 {
-        return octeon_map_dma_mem(dev, addr, size);
+        BUG();
 }
 
 static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
         struct page *page)
 {
-        return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
+        BUG();
 }
 
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
-        return dma_addr;
+        BUG();
 }
 
 static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
         size_t size, enum dma_data_direction direction)
 {
-        octeon_unmap_dma_mem(dev, dma_addr);
+        BUG();
 }
 
 static inline int plat_dma_supported(struct device *dev, u64 mask)
 {
-        return 1;
+        BUG();
 }
 
 static inline void plat_extra_sync_for_device(struct device *dev)
 {
-        mb();
+        BUG();
 }
 
 static inline int plat_device_is_coherent(struct device *dev)
@@ -60,7 +59,14 @@ static inline int plat_device_is_coherent(struct device *dev)
 static inline int plat_dma_mapping_error(struct device *dev,
                                          dma_addr_t dma_addr)
 {
-        return dma_addr == -1;
+        BUG();
 }
 
+dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
+phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
+
+struct dma_map_ops;
+extern struct dma_map_ops *octeon_pci_dma_map_ops;
+extern char *octeon_swiotlb;
+
 #endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index d3d04018a858..016d0989b141 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -26,14 +26,15 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
         return pa;
 }
 
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+        struct page *page)
 {
         dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page));
 
         return pa;
 }
 
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
         return dma_addr & ~(0xffUL << 56);
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 37855955b313..c8fb5aacf50a 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -37,7 +37,8 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
         return pa;
 }
 
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+        struct page *page)
 {
         dma_addr_t pa;
 
@@ -50,7 +51,7 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
 }
 
 /* This is almost certainly wrong but it's what dma-ip32.c used to use  */
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
         unsigned long addr = dma_addr & RAM_OFFSET_MASK;
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index f93aee59454a..302101b54acb 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -12,23 +12,24 @@
 
 struct device;
 
-static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
 {
         return vdma_alloc(virt_to_phys(addr), size);
 }
 
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+        struct page *page)
 {
         return vdma_alloc(page_to_phys(page), PAGE_SIZE);
 }
 
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
         return vdma_log2phys(dma_addr);
 }
 
-static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
         size_t size, enum dma_data_direction direction)
 {
         vdma_free(dma_addr);
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 335474c155f6..4d9870975382 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1040,6 +1040,12 @@ do {									\
 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
 
+#define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
+#define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
+
+#define read_c0_staglo()        __read_32bit_c0_register($28, 4)
+#define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
+
 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
 
@@ -1082,6 +1088,51 @@ do {									\
 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
 
+/* BMIPS3300 */
+#define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
+
+/* BMIPS4380 */
+#define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
+#define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
+
+/* BMIPS5000 */
+#define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
+#define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
+
 /*
  * Macros to access the floating point coprocessor control registers
  */
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
index ec94b9ab7be1..30d68f2365e0 100644
--- a/arch/mips/include/asm/octeon/cvmx-agl-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,148 +28,80 @@
 #ifndef __CVMX_AGL_DEFS_H__
 #define __CVMX_AGL_DEFS_H__
 
-#define CVMX_AGL_GMX_BAD_REG \
-         CVMX_ADD_IO_SEG(0x00011800E0000518ull)
-#define CVMX_AGL_GMX_BIST \
-         CVMX_ADD_IO_SEG(0x00011800E0000400ull)
-#define CVMX_AGL_GMX_DRV_CTL \
-         CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
-#define CVMX_AGL_GMX_INF_MODE \
-         CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
-#define CVMX_AGL_GMX_PRTX_CFG(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_DECISION(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_IFG(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_JABBER(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_PRT_INFO \
-         CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
-#define CVMX_AGL_GMX_RX_TX_STATUS \
-         CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
-#define CVMX_AGL_GMX_SMACX(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_STAT_BP \
-         CVMX_ADD_IO_SEG(0x00011800E0000520ull)
-#define CVMX_AGL_GMX_TXX_APPEND(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT0(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT1(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT2(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT3(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT4(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT5(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT6(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT7(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT8(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT9(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_THRESH(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TX_BP \
-         CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
-#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
-         CVMX_ADD_IO_SEG(0x00011800E0000498ull)
-#define CVMX_AGL_GMX_TX_IFG \
-         CVMX_ADD_IO_SEG(0x00011800E0000488ull)
-#define CVMX_AGL_GMX_TX_INT_EN \
-         CVMX_ADD_IO_SEG(0x00011800E0000508ull)
-#define CVMX_AGL_GMX_TX_INT_REG \
-         CVMX_ADD_IO_SEG(0x00011800E0000500ull)
-#define CVMX_AGL_GMX_TX_JAM \
-         CVMX_ADD_IO_SEG(0x00011800E0000490ull)
-#define CVMX_AGL_GMX_TX_LFSR \
-         CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
-#define CVMX_AGL_GMX_TX_OVR_BP \
-         CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
-#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
-         CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
-#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
-         CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
+#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
+#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
+#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
+#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
+#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
+#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
+#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
+#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
+#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
+#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
+#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
+#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
+#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
+#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
+#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
+#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
 
 union cvmx_agl_gmx_bad_reg {
         uint64_t u64;
@@ -183,14 +115,29 @@ union cvmx_agl_gmx_bad_reg {
                 uint64_t ovrflw:1;
                 uint64_t reserved_27_31:5;
                 uint64_t statovr:1;
+                uint64_t reserved_24_25:2;
+                uint64_t loststat:2;
+                uint64_t reserved_4_21:18;
+                uint64_t out_ovr:2;
+                uint64_t reserved_0_1:2;
+        } s;
+        struct cvmx_agl_gmx_bad_reg_cn52xx {
+                uint64_t reserved_38_63:26;
+                uint64_t txpsh1:1;
+                uint64_t txpop1:1;
+                uint64_t ovrflw1:1;
+                uint64_t txpsh:1;
+                uint64_t txpop:1;
+                uint64_t ovrflw:1;
+                uint64_t reserved_27_31:5;
+                uint64_t statovr:1;
                 uint64_t reserved_23_25:3;
                 uint64_t loststat:1;
                 uint64_t reserved_4_21:18;
                 uint64_t out_ovr:2;
                 uint64_t reserved_0_1:2;
-        } s;
-        struct cvmx_agl_gmx_bad_reg_s cn52xx;
-        struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
+        } cn52xx;
+        struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_bad_reg_cn56xx {
                 uint64_t reserved_35_63:29;
                 uint64_t txpsh:1;
@@ -205,18 +152,25 @@ union cvmx_agl_gmx_bad_reg {
                 uint64_t reserved_0_1:2;
         } cn56xx;
         struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_bad_reg_s cn63xx;
+        struct cvmx_agl_gmx_bad_reg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_bist {
         uint64_t u64;
         struct cvmx_agl_gmx_bist_s {
+                uint64_t reserved_25_63:39;
+                uint64_t status:25;
+        } s;
+        struct cvmx_agl_gmx_bist_cn52xx {
                 uint64_t reserved_10_63:54;
                 uint64_t status:10;
-        } s;
-        struct cvmx_agl_gmx_bist_s cn52xx;
-        struct cvmx_agl_gmx_bist_s cn52xxp1;
-        struct cvmx_agl_gmx_bist_s cn56xx;
-        struct cvmx_agl_gmx_bist_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_agl_gmx_bist_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_bist_cn52xx cn56xx;
+        struct cvmx_agl_gmx_bist_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_bist_s cn63xx;
+        struct cvmx_agl_gmx_bist_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_drv_ctl {
@@ -264,7 +218,13 @@ union cvmx_agl_gmx_inf_mode {
 union cvmx_agl_gmx_prtx_cfg {
         uint64_t u64;
         struct cvmx_agl_gmx_prtx_cfg_s {
-                uint64_t reserved_6_63:58;
+                uint64_t reserved_14_63:50;
+                uint64_t tx_idle:1;
+                uint64_t rx_idle:1;
+                uint64_t reserved_9_11:3;
+                uint64_t speed_msb:1;
+                uint64_t reserved_7_7:1;
+                uint64_t burst:1;
                 uint64_t tx_en:1;
                 uint64_t rx_en:1;
                 uint64_t slottime:1;
@@ -272,10 +232,20 @@ union cvmx_agl_gmx_prtx_cfg {
                 uint64_t speed:1;
                 uint64_t en:1;
         } s;
-        struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
-        struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
-        struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
-        struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
+        struct cvmx_agl_gmx_prtx_cfg_cn52xx {
+                uint64_t reserved_6_63:58;
+                uint64_t tx_en:1;
+                uint64_t rx_en:1;
+                uint64_t slottime:1;
+                uint64_t duplex:1;
+                uint64_t speed:1;
+                uint64_t en:1;
+        } cn52xx;
+        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;
+        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_prtx_cfg_s cn63xx;
+        struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam0 {
@@ -287,6 +257,8 @@ union cvmx_agl_gmx_rxx_adr_cam0 {
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam1 {
@@ -298,6 +270,8 @@ union cvmx_agl_gmx_rxx_adr_cam1 {
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam2 {
@@ -309,6 +283,8 @@ union cvmx_agl_gmx_rxx_adr_cam2 {
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam3 {
@@ -320,6 +296,8 @@ union cvmx_agl_gmx_rxx_adr_cam3 {
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam4 {
@@ -331,6 +309,8 @@ union cvmx_agl_gmx_rxx_adr_cam4 {
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam5 {
@@ -342,6 +322,8 @@ union cvmx_agl_gmx_rxx_adr_cam5 {
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam_en {
@@ -354,6 +336,8 @@ union cvmx_agl_gmx_rxx_adr_cam_en {
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_ctl {
@@ -368,6 +352,8 @@ union cvmx_agl_gmx_rxx_adr_ctl {
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_decision {
@@ -380,11 +366,26 @@ union cvmx_agl_gmx_rxx_decision {
         struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_decision_s cn56xx;
         struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_decision_s cn63xx;
+        struct cvmx_agl_gmx_rxx_decision_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_chk {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_frm_chk_s {
+                uint64_t reserved_10_63:54;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
                 uint64_t reserved_9_63:55;
                 uint64_t skperr:1;
                 uint64_t rcverr:1;
@@ -395,17 +396,21 @@ union cvmx_agl_gmx_rxx_frm_chk {
                 uint64_t maxerr:1;
                 uint64_t reserved_1_1:1;
                 uint64_t minerr:1;
-        } s;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_ctl {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_frm_ctl_s {
-                uint64_t reserved_10_63:54;
+                uint64_t reserved_13_63:51;
+                uint64_t ptp_mode:1;
+                uint64_t reserved_11_11:1;
+                uint64_t null_dis:1;
                 uint64_t pre_align:1;
                 uint64_t pad_len:1;
                 uint64_t vlan_len:1;
@@ -417,10 +422,24 @@ union cvmx_agl_gmx_rxx_frm_ctl {
                 uint64_t pre_strp:1;
                 uint64_t pre_chk:1;
         } s;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
+                uint64_t reserved_10_63:54;
+                uint64_t pre_align:1;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+        } cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_max {
@@ -433,6 +452,8 @@ union cvmx_agl_gmx_rxx_frm_max {
         struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
         struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn63xx;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_min {
@@ -445,6 +466,8 @@ union cvmx_agl_gmx_rxx_frm_min {
         struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
         struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn63xx;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_ifg {
@@ -457,6 +480,8 @@ union cvmx_agl_gmx_rxx_ifg {
         struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
         struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_ifg_s cn63xx;
+        struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_int_en {
@@ -464,6 +489,29 @@ union cvmx_agl_gmx_rxx_int_en {
         struct cvmx_agl_gmx_rxx_int_en_s {
                 uint64_t reserved_20_63:44;
                 uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_int_en_cn52xx {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
                 uint64_t reserved_16_18:3;
                 uint64_t ifgerr:1;
                 uint64_t coldet:1;
@@ -481,11 +529,12 @@ union cvmx_agl_gmx_rxx_int_en {
                 uint64_t maxerr:1;
                 uint64_t reserved_1_1:1;
                 uint64_t minerr:1;
-        } s;
-        struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
-        struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
-        struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
-        struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
+        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_rxx_int_en_s cn63xx;
+        struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_int_reg {
@@ -493,6 +542,29 @@ union cvmx_agl_gmx_rxx_int_reg {
         struct cvmx_agl_gmx_rxx_int_reg_s {
                 uint64_t reserved_20_63:44;
                 uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
                 uint64_t reserved_16_18:3;
                 uint64_t ifgerr:1;
                 uint64_t coldet:1;
@@ -510,11 +582,12 @@ union cvmx_agl_gmx_rxx_int_reg {
                 uint64_t maxerr:1;
                 uint64_t reserved_1_1:1;
                 uint64_t minerr:1;
-        } s;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
+        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn63xx;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_jabber {
@@ -527,6 +600,8 @@ union cvmx_agl_gmx_rxx_jabber {
         struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
         struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_jabber_s cn63xx;
+        struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_pause_drop_time {
@@ -539,6 +614,20 @@ union cvmx_agl_gmx_rxx_pause_drop_time {
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
+};
+
+union cvmx_agl_gmx_rxx_rx_inbnd {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_rx_inbnd_s {
+                uint64_t reserved_4_63:60;
+                uint64_t duplex:1;
+                uint64_t speed:2;
+                uint64_t status:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;
+        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_ctl {
@@ -551,6 +640,8 @@ union cvmx_agl_gmx_rxx_stats_ctl {
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs {
@@ -563,6 +654,8 @@ union cvmx_agl_gmx_rxx_stats_octs {
         struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_ctl {
@@ -575,6 +668,8 @@ union cvmx_agl_gmx_rxx_stats_octs_ctl {
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_dmac {
@@ -587,6 +682,8 @@ union cvmx_agl_gmx_rxx_stats_octs_dmac {
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_drp {
@@ -599,6 +696,8 @@ union cvmx_agl_gmx_rxx_stats_octs_drp {
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts {
@@ -611,6 +710,8 @@ union cvmx_agl_gmx_rxx_stats_pkts {
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_bad {
@@ -623,6 +724,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_bad {
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_ctl {
@@ -635,6 +738,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_ctl {
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_dmac {
@@ -647,6 +752,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_dmac {
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_drp {
@@ -659,6 +766,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_drp {
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_udd_skp {
@@ -673,6 +782,8 @@ union cvmx_agl_gmx_rxx_udd_skp {
         struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
         struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_dropx {
@@ -685,6 +796,8 @@ union cvmx_agl_gmx_rx_bp_dropx {
         struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
         struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
         struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_offx {
@@ -697,6 +810,8 @@ union cvmx_agl_gmx_rx_bp_offx {
         struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
         struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
         struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn63xx;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_onx {
@@ -709,6 +824,8 @@ union cvmx_agl_gmx_rx_bp_onx {
         struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
         struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
         struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn63xx;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rx_prt_info {
@@ -728,6 +845,8 @@ union cvmx_agl_gmx_rx_prt_info {
                 uint64_t commit:1;
         } cn56xx;
         struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_rx_prt_info_s cn63xx;
+        struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rx_tx_status {
@@ -747,6 +866,8 @@ union cvmx_agl_gmx_rx_tx_status {
                 uint64_t rx:1;
         } cn56xx;
         struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_rx_tx_status_s cn63xx;
+        struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_smacx {
@@ -759,6 +880,8 @@ union cvmx_agl_gmx_smacx {
         struct cvmx_agl_gmx_smacx_s cn52xxp1;
         struct cvmx_agl_gmx_smacx_s cn56xx;
         struct cvmx_agl_gmx_smacx_s cn56xxp1;
+        struct cvmx_agl_gmx_smacx_s cn63xx;
+        struct cvmx_agl_gmx_smacx_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_stat_bp {
@@ -772,6 +895,8 @@ union cvmx_agl_gmx_stat_bp {
         struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
         struct cvmx_agl_gmx_stat_bp_s cn56xx;
         struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
+        struct cvmx_agl_gmx_stat_bp_s cn63xx;
+        struct cvmx_agl_gmx_stat_bp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_append {
@@ -787,6 +912,18 @@ union cvmx_agl_gmx_txx_append {
         struct cvmx_agl_gmx_txx_append_s cn52xxp1;
         struct cvmx_agl_gmx_txx_append_s cn56xx;
         struct cvmx_agl_gmx_txx_append_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_append_s cn63xx;
+        struct cvmx_agl_gmx_txx_append_s cn63xxp1;
+};
+
+union cvmx_agl_gmx_txx_clk {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_clk_s {
+                uint64_t reserved_6_63:58;
+                uint64_t clk_cnt:6;
+        } s;
+        struct cvmx_agl_gmx_txx_clk_s cn63xx;
+        struct cvmx_agl_gmx_txx_clk_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_ctl {
@@ -800,6 +937,8 @@ union cvmx_agl_gmx_txx_ctl {
         struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_txx_ctl_s cn56xx;
         struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_ctl_s cn63xx;
+        struct cvmx_agl_gmx_txx_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_min_pkt {
@@ -812,6 +951,8 @@ union cvmx_agl_gmx_txx_min_pkt {
         struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
         struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
         struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn63xx;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_pkt_interval {
@@ -824,6 +965,8 @@ union cvmx_agl_gmx_txx_pause_pkt_interval {
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_pkt_time {
@@ -836,6 +979,8 @@ union cvmx_agl_gmx_txx_pause_pkt_time {
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_togo {
@@ -848,6 +993,8 @@ union cvmx_agl_gmx_txx_pause_togo {
         struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn63xx;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_zero {
@@ -860,6 +1007,8 @@ union cvmx_agl_gmx_txx_pause_zero {
         struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn63xx;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_soft_pause {
@@ -872,6 +1021,8 @@ union cvmx_agl_gmx_txx_soft_pause {
         struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
         struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
         struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn63xx;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat0 {
@@ -884,6 +1035,8 @@ union cvmx_agl_gmx_txx_stat0 {
         struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat0_s cn56xx;
         struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat0_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat0_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat1 {
@@ -896,6 +1049,8 @@ union cvmx_agl_gmx_txx_stat1 {
         struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat1_s cn56xx;
         struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat1_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat1_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat2 {
@@ -908,6 +1063,8 @@ union cvmx_agl_gmx_txx_stat2 {
         struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat2_s cn56xx;
         struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat2_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat2_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat3 {
@@ -920,6 +1077,8 @@ union cvmx_agl_gmx_txx_stat3 {
         struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat3_s cn56xx;
         struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat3_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat3_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat4 {
@@ -932,6 +1091,8 @@ union cvmx_agl_gmx_txx_stat4 {
         struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat4_s cn56xx;
         struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat4_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat4_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat5 {
@@ -944,6 +1105,8 @@ union cvmx_agl_gmx_txx_stat5 {
         struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat5_s cn56xx;
         struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat5_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat5_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat6 {
@@ -956,6 +1119,8 @@ union cvmx_agl_gmx_txx_stat6 {
         struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat6_s cn56xx;
         struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat6_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat6_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat7 {
@@ -968,6 +1133,8 @@ union cvmx_agl_gmx_txx_stat7 {
         struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat7_s cn56xx;
         struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat7_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat7_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat8 {
@@ -980,6 +1147,8 @@ union cvmx_agl_gmx_txx_stat8 {
         struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat8_s cn56xx;
         struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat8_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat8_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat9 {
@@ -992,6 +1161,8 @@ union cvmx_agl_gmx_txx_stat9 {
         struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat9_s cn56xx;
         struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat9_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat9_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stats_ctl {
@@ -1004,6 +1175,8 @@ union cvmx_agl_gmx_txx_stats_ctl {
         struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
         struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_thresh {
@@ -1016,6 +1189,8 @@ union cvmx_agl_gmx_txx_thresh {
         struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
         struct cvmx_agl_gmx_txx_thresh_s cn56xx;
         struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_thresh_s cn63xx;
+        struct cvmx_agl_gmx_txx_thresh_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_bp {
@@ -1031,6 +1206,8 @@ union cvmx_agl_gmx_tx_bp {
                 uint64_t bp:1;
         } cn56xx;
         struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_tx_bp_s cn63xx;
+        struct cvmx_agl_gmx_tx_bp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_col_attempt {
@@ -1043,6 +1220,8 @@ union cvmx_agl_gmx_tx_col_attempt {
         struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
         struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
         struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn63xx;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_ifg {
@@ -1056,12 +1235,16 @@ union cvmx_agl_gmx_tx_ifg {
         struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
         struct cvmx_agl_gmx_tx_ifg_s cn56xx;
         struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_ifg_s cn63xx;
+        struct cvmx_agl_gmx_tx_ifg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_int_en {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_int_en_s {
-                uint64_t reserved_18_63:46;
+                uint64_t reserved_22_63:42;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_18_19:2;
                 uint64_t late_col:2;
                 uint64_t reserved_14_15:2;
                 uint64_t xsdef:2;
@@ -1072,8 +1255,19 @@ union cvmx_agl_gmx_tx_int_en {
                 uint64_t reserved_1_1:1;
                 uint64_t pko_nxa:1;
         } s;
-        struct cvmx_agl_gmx_tx_int_en_s cn52xx;
-        struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_int_en_cn52xx {
+                uint64_t reserved_18_63:46;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn52xx;
+        struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_tx_int_en_cn56xx {
                 uint64_t reserved_17_63:47;
                 uint64_t late_col:1;
@@ -1087,12 +1281,16 @@ union cvmx_agl_gmx_tx_int_en {
                 uint64_t pko_nxa:1;
         } cn56xx;
         struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_tx_int_en_s cn63xx;
+        struct cvmx_agl_gmx_tx_int_en_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_int_reg {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_int_reg_s {
-                uint64_t reserved_18_63:46;
+                uint64_t reserved_22_63:42;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_18_19:2;
                 uint64_t late_col:2;
                 uint64_t reserved_14_15:2;
                 uint64_t xsdef:2;
@@ -1103,8 +1301,19 @@ union cvmx_agl_gmx_tx_int_reg {
                 uint64_t reserved_1_1:1;
                 uint64_t pko_nxa:1;
         } s;
-        struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
-        struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_int_reg_cn52xx {
+                uint64_t reserved_18_63:46;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn52xx;
+        struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_tx_int_reg_cn56xx {
                 uint64_t reserved_17_63:47;
                 uint64_t late_col:1;
@@ -1118,6 +1327,8 @@ union cvmx_agl_gmx_tx_int_reg {
                 uint64_t pko_nxa:1;
         } cn56xx;
         struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_tx_int_reg_s cn63xx;
+        struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_jam {
@@ -1130,6 +1341,8 @@ union cvmx_agl_gmx_tx_jam {
         struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
         struct cvmx_agl_gmx_tx_jam_s cn56xx;
         struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_jam_s cn63xx;
+        struct cvmx_agl_gmx_tx_jam_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_lfsr {
@@ -1142,6 +1355,8 @@ union cvmx_agl_gmx_tx_lfsr {
         struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
         struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
         struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_lfsr_s cn63xx;
+        struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_ovr_bp {
@@ -1165,6 +1380,8 @@ union cvmx_agl_gmx_tx_ovr_bp {
                 uint64_t ign_full:1;
         } cn56xx;
         struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx;
+        struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_pause_pkt_dmac {
@@ -1177,6 +1394,8 @@ union cvmx_agl_gmx_tx_pause_pkt_dmac {
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_pause_pkt_type {
@@ -1189,6 +1408,39 @@ union cvmx_agl_gmx_tx_pause_pkt_type {
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
+};
+
+union cvmx_agl_prtx_ctl {
+        uint64_t u64;
+        struct cvmx_agl_prtx_ctl_s {
+                uint64_t drv_byp:1;
+                uint64_t reserved_62_62:1;
+                uint64_t cmp_pctl:6;
+                uint64_t reserved_54_55:2;
+                uint64_t cmp_nctl:6;
+                uint64_t reserved_46_47:2;
+                uint64_t drv_pctl:6;
+                uint64_t reserved_38_39:2;
+                uint64_t drv_nctl:6;
+                uint64_t reserved_29_31:3;
+                uint64_t clk_set:5;
+                uint64_t clkrx_byp:1;
+                uint64_t reserved_21_22:2;
+                uint64_t clkrx_set:5;
+                uint64_t clktx_byp:1;
+                uint64_t reserved_13_14:2;
+                uint64_t clktx_set:5;
+                uint64_t reserved_5_7:3;
+                uint64_t dllrst:1;
+                uint64_t comp:1;
+                uint64_t enable:1;
+                uint64_t clkrst:1;
+                uint64_t mode:1;
+        } s;
+        struct cvmx_agl_prtx_ctl_s cn63xx;
+        struct cvmx_agl_prtx_ctl_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
index b21d3fc1ef91..5de5de95311b 100644
--- a/arch/mips/include/asm/octeon/cvmx-asm.h
+++ b/arch/mips/include/asm/octeon/cvmx-asm.h
@@ -114,6 +114,17 @@
 #define CVMX_DCACHE_INVALIDATE \
         { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
 
+#define CVMX_CACHE(op, address, offset)                                 \
+        asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \
+                : : [rbase] "d" (address) )
+/* fetch and lock the state. */
+#define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset)
+/* unlock the state. */
+#define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset)
+/* invalidate the cache block and clear the USED bits for the block */
+#define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset)
+/* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */
+#define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset)
 
 #define CVMX_POP(result, input) \
         asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
index f8f05b7764b7..27cead370411 100644
--- a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,87 +28,61 @@
 #ifndef __CVMX_CIU_DEFS_H__
 #define __CVMX_CIU_DEFS_H__
 
-#define CVMX_CIU_BIST \
-         CVMX_ADD_IO_SEG(0x0001070000000730ull)
-#define CVMX_CIU_DINT \
-         CVMX_ADD_IO_SEG(0x0001070000000720ull)
-#define CVMX_CIU_FUSE \
-         CVMX_ADD_IO_SEG(0x0001070000000728ull)
-#define CVMX_CIU_GSTOP \
-         CVMX_ADD_IO_SEG(0x0001070000000710ull)
-#define CVMX_CIU_INTX_EN0(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN0_W1C(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN0_W1S(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1_W1C(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1_W1S(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN4_0(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_0_W1C(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_0_W1S(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1_W1C(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1_W1S(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_SUM0(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8))
-#define CVMX_CIU_INTX_SUM4(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8))
-#define CVMX_CIU_INT_SUM1 \
-         CVMX_ADD_IO_SEG(0x0001070000000108ull)
-#define CVMX_CIU_MBOX_CLRX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8))
-#define CVMX_CIU_MBOX_SETX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8))
-#define CVMX_CIU_NMI \
-         CVMX_ADD_IO_SEG(0x0001070000000718ull)
-#define CVMX_CIU_PCI_INTA \
-         CVMX_ADD_IO_SEG(0x0001070000000750ull)
-#define CVMX_CIU_PP_DBG \
-         CVMX_ADD_IO_SEG(0x0001070000000708ull)
-#define CVMX_CIU_PP_POKEX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8))
-#define CVMX_CIU_PP_RST \
-         CVMX_ADD_IO_SEG(0x0001070000000700ull)
-#define CVMX_CIU_QLM_DCOK \
-         CVMX_ADD_IO_SEG(0x0001070000000760ull)
-#define CVMX_CIU_QLM_JTGC \
-         CVMX_ADD_IO_SEG(0x0001070000000768ull)
-#define CVMX_CIU_QLM_JTGD \
-         CVMX_ADD_IO_SEG(0x0001070000000770ull)
-#define CVMX_CIU_SOFT_BIST \
-         CVMX_ADD_IO_SEG(0x0001070000000738ull)
-#define CVMX_CIU_SOFT_PRST \
-         CVMX_ADD_IO_SEG(0x0001070000000748ull)
-#define CVMX_CIU_SOFT_PRST1 \
-         CVMX_ADD_IO_SEG(0x0001070000000758ull)
-#define CVMX_CIU_SOFT_RST \
-         CVMX_ADD_IO_SEG(0x0001070000000740ull)
-#define CVMX_CIU_TIMX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8))
-#define CVMX_CIU_WDOGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8))
+#define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
+#define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
+#define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
+#define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
+#define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
+#define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
+#define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8)
+#define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
+#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
+#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
+#define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
+#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
+#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
+#define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull))
+#define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull))
+#define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
+#define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull))
+#define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull))
+#define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull))
+#define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull))
+#define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull))
+#define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
+#define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
+#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8)
+#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8)
 
 union cvmx_ciu_bist {
         uint64_t u64;
         struct cvmx_ciu_bist_s {
+                uint64_t reserved_5_63:59;
+                uint64_t bist:5;
+        } s;
+        struct cvmx_ciu_bist_cn30xx {
                 uint64_t reserved_4_63:60;
                 uint64_t bist:4;
-        } s;
-        struct cvmx_ciu_bist_s cn30xx;
-        struct cvmx_ciu_bist_s cn31xx;
-        struct cvmx_ciu_bist_s cn38xx;
-        struct cvmx_ciu_bist_s cn38xxp2;
+        } cn30xx;
+        struct cvmx_ciu_bist_cn30xx cn31xx;
+        struct cvmx_ciu_bist_cn30xx cn38xx;
+        struct cvmx_ciu_bist_cn30xx cn38xxp2;
         struct cvmx_ciu_bist_cn50xx {
                 uint64_t reserved_2_63:62;
                 uint64_t bist:2;
@@ -118,10 +92,57 @@ union cvmx_ciu_bist {
                 uint64_t bist:3;
         } cn52xx;
         struct cvmx_ciu_bist_cn52xx cn52xxp1;
-        struct cvmx_ciu_bist_s cn56xx;
-        struct cvmx_ciu_bist_s cn56xxp1;
-        struct cvmx_ciu_bist_s cn58xx;
-        struct cvmx_ciu_bist_s cn58xxp1;
+        struct cvmx_ciu_bist_cn30xx cn56xx;
+        struct cvmx_ciu_bist_cn30xx cn56xxp1;
+        struct cvmx_ciu_bist_cn30xx cn58xx;
+        struct cvmx_ciu_bist_cn30xx cn58xxp1;
+        struct cvmx_ciu_bist_s cn63xx;
+        struct cvmx_ciu_bist_s cn63xxp1;
+};
+
+union cvmx_ciu_block_int {
+        uint64_t u64;
+        struct cvmx_ciu_block_int_s {
+                uint64_t reserved_43_63:21;
+                uint64_t ptp:1;
+                uint64_t dpi:1;
+                uint64_t dfm:1;
+                uint64_t reserved_34_39:6;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t reserved_31_31:1;
+                uint64_t iob:1;
+                uint64_t reserved_29_29:1;
+                uint64_t agl:1;
+                uint64_t reserved_27_27:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t reserved_23_24:2;
+                uint64_t asxpcs0:1;
+                uint64_t reserved_21_21:1;
+                uint64_t pip:1;
+                uint64_t reserved_18_19:2;
+                uint64_t lmc0:1;
+                uint64_t l2c:1;
+                uint64_t reserved_15_15:1;
+                uint64_t rad:1;
+                uint64_t usb:1;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t reserved_8_8:1;
+                uint64_t zip:1;
+                uint64_t dfa:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t sli:1;
+                uint64_t reserved_2_2:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+        } s;
+        struct cvmx_ciu_block_int_s cn63xx;
+        struct cvmx_ciu_block_int_s cn63xxp1;
 };
 
 union cvmx_ciu_dint {
@@ -153,6 +174,11 @@ union cvmx_ciu_dint {
         struct cvmx_ciu_dint_cn56xx cn56xxp1;
         struct cvmx_ciu_dint_s cn58xx;
         struct cvmx_ciu_dint_s cn58xxp1;
+        struct cvmx_ciu_dint_cn63xx {
+                uint64_t reserved_6_63:58;
+                uint64_t dint:6;
+        } cn63xx;
+        struct cvmx_ciu_dint_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_fuse {
@@ -184,6 +210,11 @@ union cvmx_ciu_fuse {
         struct cvmx_ciu_fuse_cn56xx cn56xxp1;
         struct cvmx_ciu_fuse_s cn58xx;
         struct cvmx_ciu_fuse_s cn58xxp1;
+        struct cvmx_ciu_fuse_cn63xx {
+                uint64_t reserved_6_63:58;
+                uint64_t fuse:6;
+        } cn63xx;
+        struct cvmx_ciu_fuse_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_gstop {
@@ -203,6 +234,8 @@ union cvmx_ciu_gstop {
         struct cvmx_ciu_gstop_s cn56xxp1;
         struct cvmx_ciu_gstop_s cn58xx;
         struct cvmx_ciu_gstop_s cn58xxp1;
+        struct cvmx_ciu_gstop_s cn63xx;
+        struct cvmx_ciu_gstop_s cn63xxp1;
 };
 
 union cvmx_ciu_intx_en0 {
@@ -343,6 +376,8 @@ union cvmx_ciu_intx_en0 {
         struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_en0_cn38xx cn58xx;
         struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
+        struct cvmx_ciu_intx_en0_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en0_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en0_w1c {
@@ -412,6 +447,8 @@ union cvmx_ciu_intx_en0_w1c {
                 uint64_t gpio:16;
                 uint64_t workq:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en0_w1s {
@@ -481,12 +518,42 @@ union cvmx_ciu_intx_en0_w1s {
                 uint64_t gpio:16;
                 uint64_t workq:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en1 {
         uint64_t u64;
         struct cvmx_ciu_intx_en1_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -531,12 +598,76 @@ union cvmx_ciu_intx_en1 {
         struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_en1_cn38xx cn58xx;
         struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
+        struct cvmx_ciu_intx_en1_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en1_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en1_w1c {
         uint64_t u64;
         struct cvmx_ciu_intx_en1_w1c_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -560,12 +691,76 @@ union cvmx_ciu_intx_en1_w1c {
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en1_w1c_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en1_w1s {
         uint64_t u64;
         struct cvmx_ciu_intx_en1_w1s_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -589,6 +784,42 @@ union cvmx_ciu_intx_en1_w1s {
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en1_w1s_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_0 {
@@ -705,6 +936,8 @@ union cvmx_ciu_intx_en4_0 {
                 uint64_t workq:16;
         } cn58xx;
         struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
+        struct cvmx_ciu_intx_en4_0_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_0_w1c {
@@ -774,6 +1007,8 @@ union cvmx_ciu_intx_en4_0_w1c {
                 uint64_t gpio:16;
                 uint64_t workq:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_0_w1s {
@@ -843,12 +1078,42 @@ union cvmx_ciu_intx_en4_0_w1s {
                 uint64_t gpio:16;
                 uint64_t workq:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_1 {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_1_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -886,12 +1151,76 @@ union cvmx_ciu_intx_en4_1 {
                 uint64_t wdog:16;
         } cn58xx;
         struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
+        struct cvmx_ciu_intx_en4_1_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_1_w1c {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_1_w1c_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -915,12 +1244,76 @@ union cvmx_ciu_intx_en4_1_w1c {
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_1_w1s {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_1_w1s_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -944,6 +1337,42 @@ union cvmx_ciu_intx_en4_1_w1s {
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_sum0 {
@@ -1084,6 +1513,8 @@ union cvmx_ciu_intx_sum0 {
         struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
         struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
+        struct cvmx_ciu_intx_sum0_cn52xx cn63xx;
+        struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_sum4 {
@@ -1200,12 +1631,85 @@ union cvmx_ciu_intx_sum4 {
                 uint64_t workq:16;
         } cn58xx;
         struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
+        struct cvmx_ciu_intx_sum4_cn52xx cn63xx;
+        struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1;
+};
+
+union cvmx_ciu_int33_sum0 {
+        uint64_t u64;
+        struct cvmx_ciu_int33_sum0_s {
+                uint64_t bootdma:1;
+                uint64_t mii:1;
+                uint64_t ipdppthr:1;
+                uint64_t powiq:1;
+                uint64_t twsi2:1;
+                uint64_t reserved_57_58:2;
+                uint64_t usb:1;
+                uint64_t timer:4;
+                uint64_t reserved_51_51:1;
+                uint64_t ipd_drp:1;
+                uint64_t reserved_49_49:1;
+                uint64_t gmx_drp:1;
+                uint64_t trace:1;
+                uint64_t rml:1;
+                uint64_t twsi:1;
+                uint64_t wdog_sum:1;
+                uint64_t pci_msi:4;
+                uint64_t pci_int:4;
+                uint64_t uart:2;
+                uint64_t mbox:2;
+                uint64_t gpio:16;
+                uint64_t workq:16;
+        } s;
+        struct cvmx_ciu_int33_sum0_s cn63xx;
+        struct cvmx_ciu_int33_sum0_s cn63xxp1;
+};
+
+union cvmx_ciu_int_dbg_sel {
+        uint64_t u64;
+        struct cvmx_ciu_int_dbg_sel_s {
+                uint64_t reserved_19_63:45;
+                uint64_t sel:3;
+                uint64_t reserved_10_15:6;
+                uint64_t irq:2;
+                uint64_t reserved_3_7:5;
+                uint64_t pp:3;
+        } s;
+        struct cvmx_ciu_int_dbg_sel_s cn63xx;
 };
 
 union cvmx_ciu_int_sum1 {
         uint64_t u64;
         struct cvmx_ciu_int_sum1_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -1250,6 +1754,42 @@ union cvmx_ciu_int_sum1 {
         struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
         struct cvmx_ciu_int_sum1_cn38xx cn58xx;
         struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
+        struct cvmx_ciu_int_sum1_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_int_sum1_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_mbox_clrx {
@@ -1269,6 +1809,8 @@ union cvmx_ciu_mbox_clrx {
         struct cvmx_ciu_mbox_clrx_s cn56xxp1;
         struct cvmx_ciu_mbox_clrx_s cn58xx;
         struct cvmx_ciu_mbox_clrx_s cn58xxp1;
+        struct cvmx_ciu_mbox_clrx_s cn63xx;
+        struct cvmx_ciu_mbox_clrx_s cn63xxp1;
 };
 
 union cvmx_ciu_mbox_setx {
@@ -1288,6 +1830,8 @@ union cvmx_ciu_mbox_setx {
         struct cvmx_ciu_mbox_setx_s cn56xxp1;
         struct cvmx_ciu_mbox_setx_s cn58xx;
         struct cvmx_ciu_mbox_setx_s cn58xxp1;
+        struct cvmx_ciu_mbox_setx_s cn63xx;
+        struct cvmx_ciu_mbox_setx_s cn63xxp1;
 };
 
 union cvmx_ciu_nmi {
@@ -1319,6 +1863,11 @@ union cvmx_ciu_nmi {
         struct cvmx_ciu_nmi_cn56xx cn56xxp1;
         struct cvmx_ciu_nmi_s cn58xx;
         struct cvmx_ciu_nmi_s cn58xxp1;
+        struct cvmx_ciu_nmi_cn63xx {
+                uint64_t reserved_6_63:58;
+                uint64_t nmi:6;
+        } cn63xx;
+        struct cvmx_ciu_nmi_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_pci_inta {
@@ -1338,6 +1887,8 @@ union cvmx_ciu_pci_inta {
         struct cvmx_ciu_pci_inta_s cn56xxp1;
         struct cvmx_ciu_pci_inta_s cn58xx;
         struct cvmx_ciu_pci_inta_s cn58xxp1;
+        struct cvmx_ciu_pci_inta_s cn63xx;
+        struct cvmx_ciu_pci_inta_s cn63xxp1;
 };
 
 union cvmx_ciu_pp_dbg {
@@ -1369,12 +1920,17 @@ union cvmx_ciu_pp_dbg {
         struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
         struct cvmx_ciu_pp_dbg_s cn58xx;
         struct cvmx_ciu_pp_dbg_s cn58xxp1;
+        struct cvmx_ciu_pp_dbg_cn63xx {
+                uint64_t reserved_6_63:58;
+                uint64_t ppdbg:6;
+        } cn63xx;
+        struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_pp_pokex {
         uint64_t u64;
         struct cvmx_ciu_pp_pokex_s {
-                uint64_t reserved_0_63:64;
+                uint64_t poke:64;
         } s;
         struct cvmx_ciu_pp_pokex_s cn30xx;
         struct cvmx_ciu_pp_pokex_s cn31xx;
@@ -1387,6 +1943,8 @@ union cvmx_ciu_pp_pokex {
         struct cvmx_ciu_pp_pokex_s cn56xxp1;
         struct cvmx_ciu_pp_pokex_s cn58xx;
         struct cvmx_ciu_pp_pokex_s cn58xxp1;
+        struct cvmx_ciu_pp_pokex_s cn63xx;
+        struct cvmx_ciu_pp_pokex_s cn63xxp1;
 };
 
 union cvmx_ciu_pp_rst {
@@ -1422,6 +1980,97 @@ union cvmx_ciu_pp_rst {
         struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
         struct cvmx_ciu_pp_rst_s cn58xx;
         struct cvmx_ciu_pp_rst_s cn58xxp1;
+        struct cvmx_ciu_pp_rst_cn63xx {
+                uint64_t reserved_6_63:58;
+                uint64_t rst:5;
+                uint64_t rst0:1;
+        } cn63xx;
+        struct cvmx_ciu_pp_rst_cn63xx cn63xxp1;
+};
+
+union cvmx_ciu_qlm0 {
+        uint64_t u64;
+        struct cvmx_ciu_qlm0_s {
+                uint64_t g2bypass:1;
+                uint64_t reserved_53_62:10;
+                uint64_t g2deemph:5;
+                uint64_t reserved_45_47:3;
+                uint64_t g2margin:5;
+                uint64_t reserved_32_39:8;
+                uint64_t txbypass:1;
+                uint64_t reserved_21_30:10;
+                uint64_t txdeemph:5;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } s;
+        struct cvmx_ciu_qlm0_s cn63xx;
+        struct cvmx_ciu_qlm0_cn63xxp1 {
+                uint64_t reserved_32_63:32;
+                uint64_t txbypass:1;
+                uint64_t reserved_20_30:11;
+                uint64_t txdeemph:4;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } cn63xxp1;
+};
+
+union cvmx_ciu_qlm1 {
+        uint64_t u64;
+        struct cvmx_ciu_qlm1_s {
+                uint64_t g2bypass:1;
+                uint64_t reserved_53_62:10;
+                uint64_t g2deemph:5;
+                uint64_t reserved_45_47:3;
+                uint64_t g2margin:5;
+                uint64_t reserved_32_39:8;
+                uint64_t txbypass:1;
+                uint64_t reserved_21_30:10;
+                uint64_t txdeemph:5;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } s;
+        struct cvmx_ciu_qlm1_s cn63xx;
+        struct cvmx_ciu_qlm1_cn63xxp1 {
+                uint64_t reserved_32_63:32;
+                uint64_t txbypass:1;
+                uint64_t reserved_20_30:11;
+                uint64_t txdeemph:4;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } cn63xxp1;
+};
+
+union cvmx_ciu_qlm2 {
+        uint64_t u64;
+        struct cvmx_ciu_qlm2_s {
+                uint64_t reserved_32_63:32;
+                uint64_t txbypass:1;
+                uint64_t reserved_21_30:10;
+                uint64_t txdeemph:5;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } s;
+        struct cvmx_ciu_qlm2_s cn63xx;
+        struct cvmx_ciu_qlm2_cn63xxp1 {
+                uint64_t reserved_32_63:32;
+                uint64_t txbypass:1;
+                uint64_t reserved_20_30:11;
+                uint64_t txdeemph:4;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } cn63xxp1;
 };
 
 union cvmx_ciu_qlm_dcok {
@@ -1459,6 +2108,15 @@ union cvmx_ciu_qlm_jtgc {
         struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
         struct cvmx_ciu_qlm_jtgc_s cn56xx;
         struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
+        struct cvmx_ciu_qlm_jtgc_cn63xx {
+                uint64_t reserved_11_63:53;
+                uint64_t clk_div:3;
+                uint64_t reserved_6_7:2;
+                uint64_t mux_sel:2;
+                uint64_t reserved_3_3:1;
+                uint64_t bypass:3;
+        } cn63xx;
+        struct cvmx_ciu_qlm_jtgc_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_qlm_jtgd {
@@ -1493,6 +2151,17 @@ union cvmx_ciu_qlm_jtgd {
                 uint64_t shft_cnt:5;
                 uint64_t shft_reg:32;
         } cn56xxp1;
+        struct cvmx_ciu_qlm_jtgd_cn63xx {
+                uint64_t capture:1;
+                uint64_t shift:1;
+                uint64_t update:1;
+                uint64_t reserved_43_60:18;
+                uint64_t select:3;
+                uint64_t reserved_37_39:3;
+                uint64_t shft_cnt:5;
+                uint64_t shft_reg:32;
+        } cn63xx;
+        struct cvmx_ciu_qlm_jtgd_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_soft_bist {
@@ -1512,6 +2181,8 @@ union cvmx_ciu_soft_bist {
         struct cvmx_ciu_soft_bist_s cn56xxp1;
         struct cvmx_ciu_soft_bist_s cn58xx;
         struct cvmx_ciu_soft_bist_s cn58xxp1;
+        struct cvmx_ciu_soft_bist_s cn63xx;
+        struct cvmx_ciu_soft_bist_s cn63xxp1;
 };
 
 union cvmx_ciu_soft_prst {
@@ -1536,6 +2207,8 @@ union cvmx_ciu_soft_prst {
         struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
         struct cvmx_ciu_soft_prst_s cn58xx;
         struct cvmx_ciu_soft_prst_s cn58xxp1;
+        struct cvmx_ciu_soft_prst_cn52xx cn63xx;
+        struct cvmx_ciu_soft_prst_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_soft_prst1 {
@@ -1548,6 +2221,8 @@ union cvmx_ciu_soft_prst1 {
         struct cvmx_ciu_soft_prst1_s cn52xxp1;
         struct cvmx_ciu_soft_prst1_s cn56xx;
         struct cvmx_ciu_soft_prst1_s cn56xxp1;
+        struct cvmx_ciu_soft_prst1_s cn63xx;
+        struct cvmx_ciu_soft_prst1_s cn63xxp1;
 };
 
 union cvmx_ciu_soft_rst {
@@ -1567,6 +2242,8 @@ union cvmx_ciu_soft_rst {
         struct cvmx_ciu_soft_rst_s cn56xxp1;
         struct cvmx_ciu_soft_rst_s cn58xx;
         struct cvmx_ciu_soft_rst_s cn58xxp1;
+        struct cvmx_ciu_soft_rst_s cn63xx;
+        struct cvmx_ciu_soft_rst_s cn63xxp1;
 };
 
 union cvmx_ciu_timx {
@@ -1587,6 +2264,8 @@ union cvmx_ciu_timx {
         struct cvmx_ciu_timx_s cn56xxp1;
         struct cvmx_ciu_timx_s cn58xx;
         struct cvmx_ciu_timx_s cn58xxp1;
+        struct cvmx_ciu_timx_s cn63xx;
+        struct cvmx_ciu_timx_s cn63xxp1;
 };
 
 union cvmx_ciu_wdogx {
@@ -1611,6 +2290,8 @@ union cvmx_ciu_wdogx {
         struct cvmx_ciu_wdogx_s cn56xxp1;
         struct cvmx_ciu_wdogx_s cn58xx;
         struct cvmx_ciu_wdogx_s cn58xxp1;
+        struct cvmx_ciu_wdogx_s cn63xx;
+        struct cvmx_ciu_wdogx_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
index 5fdd6ba48a05..395564e8d1f0 100644
--- a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,29 +28,22 @@
 #ifndef __CVMX_GPIO_DEFS_H__
 #define __CVMX_GPIO_DEFS_H__
 
-#define CVMX_GPIO_BIT_CFGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8))
-#define CVMX_GPIO_BOOT_ENA \
-         CVMX_ADD_IO_SEG(0x00010700000008A8ull)
-#define CVMX_GPIO_CLK_GENX(offset) \
-         CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8))
-#define CVMX_GPIO_DBG_ENA \
-         CVMX_ADD_IO_SEG(0x00010700000008A0ull)
-#define CVMX_GPIO_INT_CLR \
-         CVMX_ADD_IO_SEG(0x0001070000000898ull)
-#define CVMX_GPIO_RX_DAT \
-         CVMX_ADD_IO_SEG(0x0001070000000880ull)
-#define CVMX_GPIO_TX_CLR \
-         CVMX_ADD_IO_SEG(0x0001070000000890ull)
-#define CVMX_GPIO_TX_SET \
-         CVMX_ADD_IO_SEG(0x0001070000000888ull)
-#define CVMX_GPIO_XBIT_CFGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16)
+#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
+#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
+#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
+#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
+#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
+#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
+#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
+#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
+#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
+#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
 
 union cvmx_gpio_bit_cfgx {
         uint64_t u64;
         struct cvmx_gpio_bit_cfgx_s {
-                uint64_t reserved_15_63:49;
+                uint64_t reserved_17_63:47;
+                uint64_t synce_sel:2;
                 uint64_t clk_gen:1;
                 uint64_t clk_sel:2;
                 uint64_t fil_sel:4;
@@ -73,12 +66,24 @@ union cvmx_gpio_bit_cfgx {
         struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
         struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
         struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
-        struct cvmx_gpio_bit_cfgx_s cn52xx;
-        struct cvmx_gpio_bit_cfgx_s cn52xxp1;
-        struct cvmx_gpio_bit_cfgx_s cn56xx;
-        struct cvmx_gpio_bit_cfgx_s cn56xxp1;
+        struct cvmx_gpio_bit_cfgx_cn52xx {
+                uint64_t reserved_15_63:49;
+                uint64_t clk_gen:1;
+                uint64_t clk_sel:2;
+                uint64_t fil_sel:4;
+                uint64_t fil_cnt:4;
+                uint64_t int_type:1;
+                uint64_t int_en:1;
+                uint64_t rx_xor:1;
+                uint64_t tx_oe:1;
+        } cn52xx;
+        struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
+        struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
+        struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
         struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
         struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
+        struct cvmx_gpio_bit_cfgx_s cn63xx;
+        struct cvmx_gpio_bit_cfgx_s cn63xxp1;
 };
 
 union cvmx_gpio_boot_ena {
@@ -103,6 +108,19 @@ union cvmx_gpio_clk_genx {
         struct cvmx_gpio_clk_genx_s cn52xxp1;
         struct cvmx_gpio_clk_genx_s cn56xx;
         struct cvmx_gpio_clk_genx_s cn56xxp1;
+        struct cvmx_gpio_clk_genx_s cn63xx;
+        struct cvmx_gpio_clk_genx_s cn63xxp1;
+};
+
+union cvmx_gpio_clk_qlmx {
+        uint64_t u64;
+        struct cvmx_gpio_clk_qlmx_s {
+                uint64_t reserved_3_63:61;
+                uint64_t div:1;
+                uint64_t lane_sel:2;
+        } s;
+        struct cvmx_gpio_clk_qlmx_s cn63xx;
+        struct cvmx_gpio_clk_qlmx_s cn63xxp1;
 };
 
 union cvmx_gpio_dbg_ena {
@@ -133,6 +151,8 @@ union cvmx_gpio_int_clr {
         struct cvmx_gpio_int_clr_s cn56xxp1;
         struct cvmx_gpio_int_clr_s cn58xx;
         struct cvmx_gpio_int_clr_s cn58xxp1;
+        struct cvmx_gpio_int_clr_s cn63xx;
+        struct cvmx_gpio_int_clr_s cn63xxp1;
 };
 
 union cvmx_gpio_rx_dat {
@@ -155,6 +175,8 @@ union cvmx_gpio_rx_dat {
         struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
         struct cvmx_gpio_rx_dat_cn38xx cn58xx;
         struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
+        struct cvmx_gpio_rx_dat_cn38xx cn63xx;
+        struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
 };
 
 union cvmx_gpio_tx_clr {
@@ -177,6 +199,8 @@ union cvmx_gpio_tx_clr {
         struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
         struct cvmx_gpio_tx_clr_cn38xx cn58xx;
         struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
+        struct cvmx_gpio_tx_clr_cn38xx cn63xx;
+        struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
 };
 
 union cvmx_gpio_tx_set {
@@ -199,6 +223,8 @@ union cvmx_gpio_tx_set {
         struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
         struct cvmx_gpio_tx_set_cn38xx cn58xx;
         struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
+        struct cvmx_gpio_tx_set_cn38xx cn63xx;
+        struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
 };
 
 union cvmx_gpio_xbit_cfgx {
diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
index 0ee36baec500..d7d856c2483d 100644
--- a/arch/mips/include/asm/octeon/cvmx-iob-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,55 +28,39 @@
 #ifndef __CVMX_IOB_DEFS_H__
 #define __CVMX_IOB_DEFS_H__
 
-#define CVMX_IOB_BIST_STATUS \
-         CVMX_ADD_IO_SEG(0x00011800F00007F8ull)
-#define CVMX_IOB_CTL_STATUS \
-         CVMX_ADD_IO_SEG(0x00011800F0000050ull)
-#define CVMX_IOB_DWB_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000028ull)
-#define CVMX_IOB_FAU_TIMEOUT \
-         CVMX_ADD_IO_SEG(0x00011800F0000000ull)
-#define CVMX_IOB_I2C_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000010ull)
-#define CVMX_IOB_INB_CONTROL_MATCH \
-         CVMX_ADD_IO_SEG(0x00011800F0000078ull)
-#define CVMX_IOB_INB_CONTROL_MATCH_ENB \
-         CVMX_ADD_IO_SEG(0x00011800F0000088ull)
-#define CVMX_IOB_INB_DATA_MATCH \
-         CVMX_ADD_IO_SEG(0x00011800F0000070ull)
-#define CVMX_IOB_INB_DATA_MATCH_ENB \
-         CVMX_ADD_IO_SEG(0x00011800F0000080ull)
-#define CVMX_IOB_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00011800F0000060ull)
-#define CVMX_IOB_INT_SUM \
-         CVMX_ADD_IO_SEG(0x00011800F0000058ull)
-#define CVMX_IOB_N2C_L2C_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000020ull)
-#define CVMX_IOB_N2C_RSP_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000008ull)
-#define CVMX_IOB_OUTB_COM_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000040ull)
-#define CVMX_IOB_OUTB_CONTROL_MATCH \
-         CVMX_ADD_IO_SEG(0x00011800F0000098ull)
-#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB \
-         CVMX_ADD_IO_SEG(0x00011800F00000A8ull)
-#define CVMX_IOB_OUTB_DATA_MATCH \
-         CVMX_ADD_IO_SEG(0x00011800F0000090ull)
-#define CVMX_IOB_OUTB_DATA_MATCH_ENB \
-         CVMX_ADD_IO_SEG(0x00011800F00000A0ull)
-#define CVMX_IOB_OUTB_FPA_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000048ull)
-#define CVMX_IOB_OUTB_REQ_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000038ull)
-#define CVMX_IOB_P2C_REQ_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000018ull)
-#define CVMX_IOB_PKT_ERR \
-         CVMX_ADD_IO_SEG(0x00011800F0000068ull)
+#define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
+#define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
+#define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
+#define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
+#define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
+#define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
+#define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
+#define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
+#define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
+#define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
+#define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
+#define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
+#define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
+#define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
+#define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
+#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
+#define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
+#define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
+#define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
+#define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
+#define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
+#define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
+#define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
 
 union cvmx_iob_bist_status {
         uint64_t u64;
         struct cvmx_iob_bist_status_s {
-                uint64_t reserved_18_63:46;
+                uint64_t reserved_23_63:41;
+                uint64_t xmdfif:1;
+                uint64_t xmcfif:1;
+                uint64_t iorfif:1;
+                uint64_t rsdfif:1;
+                uint64_t iocfif:1;
                 uint64_t icnrcb:1;
                 uint64_t icr0:1;
                 uint64_t icr1:1;
@@ -96,40 +80,81 @@ union cvmx_iob_bist_status {
                 uint64_t ibd:1;
                 uint64_t icd:1;
         } s;
-        struct cvmx_iob_bist_status_s cn30xx;
-        struct cvmx_iob_bist_status_s cn31xx;
-        struct cvmx_iob_bist_status_s cn38xx;
-        struct cvmx_iob_bist_status_s cn38xxp2;
-        struct cvmx_iob_bist_status_s cn50xx;
-        struct cvmx_iob_bist_status_s cn52xx;
-        struct cvmx_iob_bist_status_s cn52xxp1;
-        struct cvmx_iob_bist_status_s cn56xx;
-        struct cvmx_iob_bist_status_s cn56xxp1;
-        struct cvmx_iob_bist_status_s cn58xx;
-        struct cvmx_iob_bist_status_s cn58xxp1;
+        struct cvmx_iob_bist_status_cn30xx {
+                uint64_t reserved_18_63:46;
+                uint64_t icnrcb:1;
+                uint64_t icr0:1;
+                uint64_t icr1:1;
+                uint64_t icnr1:1;
+                uint64_t icnr0:1;
+                uint64_t ibdr0:1;
+                uint64_t ibdr1:1;
+                uint64_t ibr0:1;
+                uint64_t ibr1:1;
+                uint64_t icnrt:1;
+                uint64_t ibrq0:1;
+                uint64_t ibrq1:1;
+                uint64_t icrn0:1;
+                uint64_t icrn1:1;
+                uint64_t icrp0:1;
+                uint64_t icrp1:1;
+                uint64_t ibd:1;
+                uint64_t icd:1;
+        } cn30xx;
+        struct cvmx_iob_bist_status_cn30xx cn31xx;
+        struct cvmx_iob_bist_status_cn30xx cn38xx;
+        struct cvmx_iob_bist_status_cn30xx cn38xxp2;
+        struct cvmx_iob_bist_status_cn30xx cn50xx;
+        struct cvmx_iob_bist_status_cn30xx cn52xx;
+        struct cvmx_iob_bist_status_cn30xx cn52xxp1;
+        struct cvmx_iob_bist_status_cn30xx cn56xx;
+        struct cvmx_iob_bist_status_cn30xx cn56xxp1;
+        struct cvmx_iob_bist_status_cn30xx cn58xx;
+        struct cvmx_iob_bist_status_cn30xx cn58xxp1;
+        struct cvmx_iob_bist_status_s cn63xx;
+        struct cvmx_iob_bist_status_s cn63xxp1;
 };
 
 union cvmx_iob_ctl_status {
         uint64_t u64;
         struct cvmx_iob_ctl_status_s {
-                uint64_t reserved_5_63:59;
+                uint64_t reserved_10_63:54;
+                uint64_t xmc_per:4;
+                uint64_t rr_mode:1;
                 uint64_t outb_mat:1;
                 uint64_t inb_mat:1;
                 uint64_t pko_enb:1;
                 uint64_t dwb_enb:1;
                 uint64_t fau_end:1;
         } s;
-        struct cvmx_iob_ctl_status_s cn30xx;
-        struct cvmx_iob_ctl_status_s cn31xx;
-        struct cvmx_iob_ctl_status_s cn38xx;
-        struct cvmx_iob_ctl_status_s cn38xxp2;
-        struct cvmx_iob_ctl_status_s cn50xx;
-        struct cvmx_iob_ctl_status_s cn52xx;
-        struct cvmx_iob_ctl_status_s cn52xxp1;
-        struct cvmx_iob_ctl_status_s cn56xx;
-        struct cvmx_iob_ctl_status_s cn56xxp1;
-        struct cvmx_iob_ctl_status_s cn58xx;
-        struct cvmx_iob_ctl_status_s cn58xxp1;
+        struct cvmx_iob_ctl_status_cn30xx {
+                uint64_t reserved_5_63:59;
+                uint64_t outb_mat:1;
+                uint64_t inb_mat:1;
+                uint64_t pko_enb:1;
+                uint64_t dwb_enb:1;
+                uint64_t fau_end:1;
+        } cn30xx;
+        struct cvmx_iob_ctl_status_cn30xx cn31xx;
+        struct cvmx_iob_ctl_status_cn30xx cn38xx;
+        struct cvmx_iob_ctl_status_cn30xx cn38xxp2;
+        struct cvmx_iob_ctl_status_cn30xx cn50xx;
+        struct cvmx_iob_ctl_status_cn52xx {
+                uint64_t reserved_6_63:58;
+                uint64_t rr_mode:1;
+                uint64_t outb_mat:1;
+                uint64_t inb_mat:1;
+                uint64_t pko_enb:1;
+                uint64_t dwb_enb:1;
+                uint64_t fau_end:1;
+        } cn52xx;
+        struct cvmx_iob_ctl_status_cn30xx cn52xxp1;
+        struct cvmx_iob_ctl_status_cn30xx cn56xx;
+        struct cvmx_iob_ctl_status_cn30xx cn56xxp1;
+        struct cvmx_iob_ctl_status_cn30xx cn58xx;
+        struct cvmx_iob_ctl_status_cn30xx cn58xxp1;
+        struct cvmx_iob_ctl_status_s cn63xx;
+        struct cvmx_iob_ctl_status_s cn63xxp1;
 };
 
 union cvmx_iob_dwb_pri_cnt {
@@ -147,6 +172,8 @@ union cvmx_iob_dwb_pri_cnt {
         struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
         struct cvmx_iob_dwb_pri_cnt_s cn58xx;
         struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_dwb_pri_cnt_s cn63xx;
+        struct cvmx_iob_dwb_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_fau_timeout {
@@ -167,6 +194,8 @@ union cvmx_iob_fau_timeout {
         struct cvmx_iob_fau_timeout_s cn56xxp1;
         struct cvmx_iob_fau_timeout_s cn58xx;
         struct cvmx_iob_fau_timeout_s cn58xxp1;
+        struct cvmx_iob_fau_timeout_s cn63xx;
+        struct cvmx_iob_fau_timeout_s cn63xxp1;
 };
 
 union cvmx_iob_i2c_pri_cnt {
@@ -184,6 +213,8 @@ union cvmx_iob_i2c_pri_cnt {
         struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
         struct cvmx_iob_i2c_pri_cnt_s cn58xx;
         struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_i2c_pri_cnt_s cn63xx;
+        struct cvmx_iob_i2c_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_inb_control_match {
@@ -206,6 +237,8 @@ union cvmx_iob_inb_control_match {
         struct cvmx_iob_inb_control_match_s cn56xxp1;
         struct cvmx_iob_inb_control_match_s cn58xx;
         struct cvmx_iob_inb_control_match_s cn58xxp1;
+        struct cvmx_iob_inb_control_match_s cn63xx;
+        struct cvmx_iob_inb_control_match_s cn63xxp1;
 };
 
 union cvmx_iob_inb_control_match_enb {
@@ -228,6 +261,8 @@ union cvmx_iob_inb_control_match_enb {
         struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
         struct cvmx_iob_inb_control_match_enb_s cn58xx;
         struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
+        struct cvmx_iob_inb_control_match_enb_s cn63xx;
+        struct cvmx_iob_inb_control_match_enb_s cn63xxp1;
 };
 
 union cvmx_iob_inb_data_match {
@@ -246,6 +281,8 @@ union cvmx_iob_inb_data_match {
         struct cvmx_iob_inb_data_match_s cn56xxp1;
         struct cvmx_iob_inb_data_match_s cn58xx;
         struct cvmx_iob_inb_data_match_s cn58xxp1;
+        struct cvmx_iob_inb_data_match_s cn63xx;
+        struct cvmx_iob_inb_data_match_s cn63xxp1;
 };
 
 union cvmx_iob_inb_data_match_enb {
@@ -264,6 +301,8 @@ union cvmx_iob_inb_data_match_enb {
         struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
         struct cvmx_iob_inb_data_match_enb_s cn58xx;
         struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
+        struct cvmx_iob_inb_data_match_enb_s cn63xx;
+        struct cvmx_iob_inb_data_match_enb_s cn63xxp1;
 };
 
 union cvmx_iob_int_enb {
@@ -294,6 +333,8 @@ union cvmx_iob_int_enb {
         struct cvmx_iob_int_enb_s cn56xxp1;
         struct cvmx_iob_int_enb_s cn58xx;
         struct cvmx_iob_int_enb_s cn58xxp1;
+        struct cvmx_iob_int_enb_s cn63xx;
+        struct cvmx_iob_int_enb_s cn63xxp1;
 };
 
 union cvmx_iob_int_sum {
@@ -324,6 +365,8 @@ union cvmx_iob_int_sum {
         struct cvmx_iob_int_sum_s cn56xxp1;
         struct cvmx_iob_int_sum_s cn58xx;
         struct cvmx_iob_int_sum_s cn58xxp1;
+        struct cvmx_iob_int_sum_s cn63xx;
+        struct cvmx_iob_int_sum_s cn63xxp1;
 };
 
 union cvmx_iob_n2c_l2c_pri_cnt {
@@ -341,6 +384,8 @@ union cvmx_iob_n2c_l2c_pri_cnt {
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx;
+        struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_n2c_rsp_pri_cnt {
@@ -358,6 +403,8 @@ union cvmx_iob_n2c_rsp_pri_cnt {
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx;
+        struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_outb_com_pri_cnt {
@@ -375,6 +422,8 @@ union cvmx_iob_outb_com_pri_cnt {
         struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
         struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
         struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_outb_com_pri_cnt_s cn63xx;
+        struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_outb_control_match {
@@ -397,6 +446,8 @@ union cvmx_iob_outb_control_match {
         struct cvmx_iob_outb_control_match_s cn56xxp1;
         struct cvmx_iob_outb_control_match_s cn58xx;
         struct cvmx_iob_outb_control_match_s cn58xxp1;
+        struct cvmx_iob_outb_control_match_s cn63xx;
+        struct cvmx_iob_outb_control_match_s cn63xxp1;
 };
 
 union cvmx_iob_outb_control_match_enb {
@@ -419,6 +470,8 @@ union cvmx_iob_outb_control_match_enb {
         struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
         struct cvmx_iob_outb_control_match_enb_s cn58xx;
         struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
+        struct cvmx_iob_outb_control_match_enb_s cn63xx;
+        struct cvmx_iob_outb_control_match_enb_s cn63xxp1;
 };
 
 union cvmx_iob_outb_data_match {
@@ -437,6 +490,8 @@ union cvmx_iob_outb_data_match {
         struct cvmx_iob_outb_data_match_s cn56xxp1;
         struct cvmx_iob_outb_data_match_s cn58xx;
         struct cvmx_iob_outb_data_match_s cn58xxp1;
+        struct cvmx_iob_outb_data_match_s cn63xx;
+        struct cvmx_iob_outb_data_match_s cn63xxp1;
 };
 
 union cvmx_iob_outb_data_match_enb {
@@ -455,6 +510,8 @@ union cvmx_iob_outb_data_match_enb {
         struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
         struct cvmx_iob_outb_data_match_enb_s cn58xx;
         struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
+        struct cvmx_iob_outb_data_match_enb_s cn63xx;
+        struct cvmx_iob_outb_data_match_enb_s cn63xxp1;
 };
 
 union cvmx_iob_outb_fpa_pri_cnt {
@@ -472,6 +529,8 @@ union cvmx_iob_outb_fpa_pri_cnt {
         struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
         struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
         struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx;
+        struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_outb_req_pri_cnt {
@@ -489,6 +548,8 @@ union cvmx_iob_outb_req_pri_cnt {
         struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
         struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
         struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_outb_req_pri_cnt_s cn63xx;
+        struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_p2c_req_pri_cnt {
@@ -506,25 +567,46 @@ union cvmx_iob_p2c_req_pri_cnt {
         struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
         struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
         struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_p2c_req_pri_cnt_s cn63xx;
+        struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_pkt_err {
         uint64_t u64;
         struct cvmx_iob_pkt_err_s {
+                uint64_t reserved_12_63:52;
+                uint64_t vport:6;
+                uint64_t port:6;
+        } s;
+        struct cvmx_iob_pkt_err_cn30xx {
                 uint64_t reserved_6_63:58;
                 uint64_t port:6;
+        } cn30xx;
+        struct cvmx_iob_pkt_err_cn30xx cn31xx;
+        struct cvmx_iob_pkt_err_cn30xx cn38xx;
+        struct cvmx_iob_pkt_err_cn30xx cn38xxp2;
+        struct cvmx_iob_pkt_err_cn30xx cn50xx;
+        struct cvmx_iob_pkt_err_cn30xx cn52xx;
+        struct cvmx_iob_pkt_err_cn30xx cn52xxp1;
+        struct cvmx_iob_pkt_err_cn30xx cn56xx;
+        struct cvmx_iob_pkt_err_cn30xx cn56xxp1;
+        struct cvmx_iob_pkt_err_cn30xx cn58xx;
+        struct cvmx_iob_pkt_err_cn30xx cn58xxp1;
+        struct cvmx_iob_pkt_err_s cn63xx;
+        struct cvmx_iob_pkt_err_s cn63xxp1;
+};
+
+union cvmx_iob_to_cmb_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_cmb_credits_s {
+                uint64_t reserved_9_63:55;
+                uint64_t pko_rd:3;
+                uint64_t ncb_rd:3;
+                uint64_t ncb_wr:3;
         } s;
-        struct cvmx_iob_pkt_err_s cn30xx;
-        struct cvmx_iob_pkt_err_s cn31xx;
-        struct cvmx_iob_pkt_err_s cn38xx;
-        struct cvmx_iob_pkt_err_s cn38xxp2;
-        struct cvmx_iob_pkt_err_s cn50xx;
-        struct cvmx_iob_pkt_err_s cn52xx;
-        struct cvmx_iob_pkt_err_s cn52xxp1;
-        struct cvmx_iob_pkt_err_s cn56xx;
-        struct cvmx_iob_pkt_err_s cn56xxp1;
-        struct cvmx_iob_pkt_err_s cn58xx;
-        struct cvmx_iob_pkt_err_s cn58xxp1;
+        struct cvmx_iob_to_cmb_credits_s cn52xx;
+        struct cvmx_iob_to_cmb_credits_s cn63xx;
+        struct cvmx_iob_to_cmb_credits_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
index f8b8fc657d2c..e0a5bfe88d04 100644
--- a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,104 +28,57 @@
 #ifndef __CVMX_IPD_DEFS_H__
 #define __CVMX_IPD_DEFS_H__
 
-#define CVMX_IPD_1ST_MBUFF_SKIP \
-         CVMX_ADD_IO_SEG(0x00014F0000000000ull)
-#define CVMX_IPD_1st_NEXT_PTR_BACK \
-         CVMX_ADD_IO_SEG(0x00014F0000000150ull)
-#define CVMX_IPD_2nd_NEXT_PTR_BACK \
-         CVMX_ADD_IO_SEG(0x00014F0000000158ull)
-#define CVMX_IPD_BIST_STATUS \
-         CVMX_ADD_IO_SEG(0x00014F00000007F8ull)
-#define CVMX_IPD_BP_PRT_RED_END \
-         CVMX_ADD_IO_SEG(0x00014F0000000328ull)
-#define CVMX_IPD_CLK_COUNT \
-         CVMX_ADD_IO_SEG(0x00014F0000000338ull)
-#define CVMX_IPD_CTL_STATUS \
-         CVMX_ADD_IO_SEG(0x00014F0000000018ull)
-#define CVMX_IPD_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00014F0000000160ull)
-#define CVMX_IPD_INT_SUM \
-         CVMX_ADD_IO_SEG(0x00014F0000000168ull)
-#define CVMX_IPD_NOT_1ST_MBUFF_SKIP \
-         CVMX_ADD_IO_SEG(0x00014F0000000008ull)
-#define CVMX_IPD_PACKET_MBUFF_SIZE \
-         CVMX_ADD_IO_SEG(0x00014F0000000010ull)
-#define CVMX_IPD_PKT_PTR_VALID \
-         CVMX_ADD_IO_SEG(0x00014F0000000358ull)
-#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000028ull + (((offset) & 63) * 8))
-#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000368ull + (((offset) & 63) * 8) - 8 * 36)
-#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000388ull + (((offset) & 63) * 8) - 8 * 36)
-#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) \
-         CVMX_ADD_IO_SEG(0x00014F00000001B8ull + (((offset) & 63) * 8))
-#define CVMX_IPD_PORT_QOS_INTX(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000808ull + (((offset) & 7) * 8))
-#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000848ull + (((offset) & 7) * 8))
-#define CVMX_IPD_PORT_QOS_X_CNT(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000888ull + (((offset) & 511) * 8))
-#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL \
-         CVMX_ADD_IO_SEG(0x00014F0000000348ull)
-#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL \
-         CVMX_ADD_IO_SEG(0x00014F0000000350ull)
-#define CVMX_IPD_PTR_COUNT \
-         CVMX_ADD_IO_SEG(0x00014F0000000320ull)
-#define CVMX_IPD_PWP_PTR_FIFO_CTL \
-         CVMX_ADD_IO_SEG(0x00014F0000000340ull)
-#define CVMX_IPD_QOS0_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F0000000178ull)
-#define CVMX_IPD_QOS1_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F0000000180ull)
-#define CVMX_IPD_QOS2_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F0000000188ull)
-#define CVMX_IPD_QOS3_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F0000000190ull)
-#define CVMX_IPD_QOS4_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F0000000198ull)
-#define CVMX_IPD_QOS5_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F00000001A0ull)
-#define CVMX_IPD_QOS6_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F00000001A8ull)
-#define CVMX_IPD_QOS7_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F00000001B0ull)
-#define CVMX_IPD_QOSX_RED_MARKS(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000178ull + (((offset) & 7) * 8))
-#define CVMX_IPD_QUE0_FREE_PAGE_CNT \
-         CVMX_ADD_IO_SEG(0x00014F0000000330ull)
-#define CVMX_IPD_RED_PORT_ENABLE \
-         CVMX_ADD_IO_SEG(0x00014F00000002D8ull)
-#define CVMX_IPD_RED_PORT_ENABLE2 \
-         CVMX_ADD_IO_SEG(0x00014F00000003A8ull)
-#define CVMX_IPD_RED_QUE0_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F00000002E0ull)
-#define CVMX_IPD_RED_QUE1_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F00000002E8ull)
-#define CVMX_IPD_RED_QUE2_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F00000002F0ull)
-#define CVMX_IPD_RED_QUE3_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F00000002F8ull)
-#define CVMX_IPD_RED_QUE4_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F0000000300ull)
-#define CVMX_IPD_RED_QUE5_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F0000000308ull)
-#define CVMX_IPD_RED_QUE6_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F0000000310ull)
-#define CVMX_IPD_RED_QUE7_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F0000000318ull)
-#define CVMX_IPD_RED_QUEX_PARAM(offset) \
-         CVMX_ADD_IO_SEG(0x00014F00000002E0ull + (((offset) & 7) * 8))
-#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT \
-         CVMX_ADD_IO_SEG(0x00014F0000000148ull)
-#define CVMX_IPD_SUB_PORT_FCS \
-         CVMX_ADD_IO_SEG(0x00014F0000000170ull)
-#define CVMX_IPD_SUB_PORT_QOS_CNT \
-         CVMX_ADD_IO_SEG(0x00014F0000000800ull)
-#define CVMX_IPD_WQE_FPA_QUEUE \
-         CVMX_ADD_IO_SEG(0x00014F0000000020ull)
-#define CVMX_IPD_WQE_PTR_VALID \
-         CVMX_ADD_IO_SEG(0x00014F0000000360ull)
+#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
+#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
+#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
+#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
+#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
+#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
+#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
+#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
+#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
+#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
+#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
+#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
+#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
+#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
+#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
+#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
+#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
+#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
+#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
+#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
+#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull))
+#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
+#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
+#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
+#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
+#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
+#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
+#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
+#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
+#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
+#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
+#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull))
+#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
+#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
+#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
+#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
+#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
+#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
+#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
+#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
+#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
+#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
+#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
+#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull))
+#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull))
 
 union cvmx_ipd_1st_mbuff_skip {
         uint64_t u64;
@@ -144,6 +97,8 @@ union cvmx_ipd_1st_mbuff_skip {
         struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;
         struct cvmx_ipd_1st_mbuff_skip_s cn58xx;
         struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;
+        struct cvmx_ipd_1st_mbuff_skip_s cn63xx;
+        struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1;
 };
 
 union cvmx_ipd_1st_next_ptr_back {
@@ -163,6 +118,8 @@ union cvmx_ipd_1st_next_ptr_back {
         struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;
         struct cvmx_ipd_1st_next_ptr_back_s cn58xx;
         struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;
+        struct cvmx_ipd_1st_next_ptr_back_s cn63xx;
+        struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1;
 };
 
 union cvmx_ipd_2nd_next_ptr_back {
@@ -182,6 +139,8 @@ union cvmx_ipd_2nd_next_ptr_back {
         struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;
         struct cvmx_ipd_2nd_next_ptr_back_s cn58xx;
         struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;
+        struct cvmx_ipd_2nd_next_ptr_back_s cn63xx;
+        struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1;
 };
 
 union cvmx_ipd_bist_status {
@@ -236,13 +195,15 @@ union cvmx_ipd_bist_status {
         struct cvmx_ipd_bist_status_s cn56xxp1;
         struct cvmx_ipd_bist_status_cn30xx cn58xx;
         struct cvmx_ipd_bist_status_cn30xx cn58xxp1;
+        struct cvmx_ipd_bist_status_s cn63xx;
+        struct cvmx_ipd_bist_status_s cn63xxp1;
 };
 
 union cvmx_ipd_bp_prt_red_end {
         uint64_t u64;
         struct cvmx_ipd_bp_prt_red_end_s {
-                uint64_t reserved_40_63:24;
-                uint64_t prt_enb:40;
+                uint64_t reserved_44_63:20;
+                uint64_t prt_enb:44;
         } s;
         struct cvmx_ipd_bp_prt_red_end_cn30xx {
                 uint64_t reserved_36_63:28;
@@ -252,12 +213,17 @@ union cvmx_ipd_bp_prt_red_end {
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
-        struct cvmx_ipd_bp_prt_red_end_s cn52xx;
-        struct cvmx_ipd_bp_prt_red_end_s cn52xxp1;
-        struct cvmx_ipd_bp_prt_red_end_s cn56xx;
-        struct cvmx_ipd_bp_prt_red_end_s cn56xxp1;
+        struct cvmx_ipd_bp_prt_red_end_cn52xx {
+                uint64_t reserved_40_63:24;
+                uint64_t prt_enb:40;
+        } cn52xx;
+        struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1;
+        struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx;
+        struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
+        struct cvmx_ipd_bp_prt_red_end_s cn63xx;
+        struct cvmx_ipd_bp_prt_red_end_s cn63xxp1;
 };
 
 union cvmx_ipd_clk_count {
@@ -276,12 +242,17 @@ union cvmx_ipd_clk_count {
         struct cvmx_ipd_clk_count_s cn56xxp1;
         struct cvmx_ipd_clk_count_s cn58xx;
         struct cvmx_ipd_clk_count_s cn58xxp1;
+        struct cvmx_ipd_clk_count_s cn63xx;
+        struct cvmx_ipd_clk_count_s cn63xxp1;
 };
 
 union cvmx_ipd_ctl_status {
         uint64_t u64;
         struct cvmx_ipd_ctl_status_s {
-                uint64_t reserved_15_63:49;
+                uint64_t reserved_18_63:46;
+                uint64_t use_sop:1;
+                uint64_t rst_done:1;
+                uint64_t clken:1;
                 uint64_t no_wptr:1;
                 uint64_t pq_apkt:1;
                 uint64_t pq_nabuf:1;
@@ -322,11 +293,27 @@ union cvmx_ipd_ctl_status {
                 uint64_t opc_mode:2;
                 uint64_t ipd_en:1;
         } cn38xxp2;
-        struct cvmx_ipd_ctl_status_s cn50xx;
-        struct cvmx_ipd_ctl_status_s cn52xx;
-        struct cvmx_ipd_ctl_status_s cn52xxp1;
-        struct cvmx_ipd_ctl_status_s cn56xx;
-        struct cvmx_ipd_ctl_status_s cn56xxp1;
+        struct cvmx_ipd_ctl_status_cn50xx {
+                uint64_t reserved_15_63:49;
+                uint64_t no_wptr:1;
+                uint64_t pq_apkt:1;
+                uint64_t pq_nabuf:1;
+                uint64_t ipd_full:1;
+                uint64_t pkt_off:1;
+                uint64_t len_m8:1;
+                uint64_t reset:1;
+                uint64_t addpkt:1;
+                uint64_t naddbuf:1;
+                uint64_t pkt_lend:1;
+                uint64_t wqe_lend:1;
+                uint64_t pbp_en:1;
+                uint64_t opc_mode:2;
+                uint64_t ipd_en:1;
+        } cn50xx;
+        struct cvmx_ipd_ctl_status_cn50xx cn52xx;
+        struct cvmx_ipd_ctl_status_cn50xx cn52xxp1;
+        struct cvmx_ipd_ctl_status_cn50xx cn56xx;
+        struct cvmx_ipd_ctl_status_cn50xx cn56xxp1;
         struct cvmx_ipd_ctl_status_cn58xx {
                 uint64_t reserved_12_63:52;
                 uint64_t ipd_full:1;
@@ -342,6 +329,25 @@ union cvmx_ipd_ctl_status {
                 uint64_t ipd_en:1;
         } cn58xx;
         struct cvmx_ipd_ctl_status_cn58xx cn58xxp1;
+        struct cvmx_ipd_ctl_status_s cn63xx;
+        struct cvmx_ipd_ctl_status_cn63xxp1 {
+                uint64_t reserved_16_63:48;
+                uint64_t clken:1;
+                uint64_t no_wptr:1;
+                uint64_t pq_apkt:1;
+                uint64_t pq_nabuf:1;
+                uint64_t ipd_full:1;
+                uint64_t pkt_off:1;
+                uint64_t len_m8:1;
+                uint64_t reset:1;
+                uint64_t addpkt:1;
+                uint64_t naddbuf:1;
+                uint64_t pkt_lend:1;
+                uint64_t wqe_lend:1;
+                uint64_t pbp_en:1;
+                uint64_t opc_mode:2;
+                uint64_t ipd_en:1;
+        } cn63xxp1;
 };
 
 union cvmx_ipd_int_enb {
@@ -391,6 +397,8 @@ union cvmx_ipd_int_enb {
         struct cvmx_ipd_int_enb_s cn56xxp1;
         struct cvmx_ipd_int_enb_cn38xx cn58xx;
         struct cvmx_ipd_int_enb_cn38xx cn58xxp1;
+        struct cvmx_ipd_int_enb_s cn63xx;
+        struct cvmx_ipd_int_enb_s cn63xxp1;
 };
 
 union cvmx_ipd_int_sum {
@@ -440,6 +448,8 @@ union cvmx_ipd_int_sum {
         struct cvmx_ipd_int_sum_s cn56xxp1;
         struct cvmx_ipd_int_sum_cn38xx cn58xx;
         struct cvmx_ipd_int_sum_cn38xx cn58xxp1;
+        struct cvmx_ipd_int_sum_s cn63xx;
+        struct cvmx_ipd_int_sum_s cn63xxp1;
 };
 
 union cvmx_ipd_not_1st_mbuff_skip {
@@ -459,6 +469,8 @@ union cvmx_ipd_not_1st_mbuff_skip {
         struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
         struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
         struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
+        struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx;
+        struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1;
 };
 
 union cvmx_ipd_packet_mbuff_size {
@@ -478,6 +490,8 @@ union cvmx_ipd_packet_mbuff_size {
         struct cvmx_ipd_packet_mbuff_size_s cn56xxp1;
         struct cvmx_ipd_packet_mbuff_size_s cn58xx;
         struct cvmx_ipd_packet_mbuff_size_s cn58xxp1;
+        struct cvmx_ipd_packet_mbuff_size_s cn63xx;
+        struct cvmx_ipd_packet_mbuff_size_s cn63xxp1;
 };
 
 union cvmx_ipd_pkt_ptr_valid {
@@ -496,6 +510,8 @@ union cvmx_ipd_pkt_ptr_valid {
         struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;
         struct cvmx_ipd_pkt_ptr_valid_s cn58xx;
         struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;
+        struct cvmx_ipd_pkt_ptr_valid_s cn63xx;
+        struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1;
 };
 
 union cvmx_ipd_portx_bp_page_cnt {
@@ -516,6 +532,8 @@ union cvmx_ipd_portx_bp_page_cnt {
         struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;
         struct cvmx_ipd_portx_bp_page_cnt_s cn58xx;
         struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;
+        struct cvmx_ipd_portx_bp_page_cnt_s cn63xx;
+        struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1;
 };
 
 union cvmx_ipd_portx_bp_page_cnt2 {
@@ -529,6 +547,19 @@ union cvmx_ipd_portx_bp_page_cnt2 {
         struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
         struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
         struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
+        struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx;
+        struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1;
+};
+
+union cvmx_ipd_portx_bp_page_cnt3 {
+        uint64_t u64;
+        struct cvmx_ipd_portx_bp_page_cnt3_s {
+                uint64_t reserved_18_63:46;
+                uint64_t bp_enb:1;
+                uint64_t page_cnt:17;
+        } s;
+        struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx;
+        struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1;
 };
 
 union cvmx_ipd_port_bp_counters2_pairx {
@@ -541,6 +572,18 @@ union cvmx_ipd_port_bp_counters2_pairx {
         struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
         struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
         struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
+        struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx;
+        struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1;
+};
+
+union cvmx_ipd_port_bp_counters3_pairx {
+        uint64_t u64;
+        struct cvmx_ipd_port_bp_counters3_pairx_s {
+                uint64_t reserved_25_63:39;
+                uint64_t cnt_val:25;
+        } s;
+        struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx;
+        struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1;
 };
 
 union cvmx_ipd_port_bp_counters_pairx {
@@ -560,6 +603,8 @@ union cvmx_ipd_port_bp_counters_pairx {
         struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
         struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
         struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
+        struct cvmx_ipd_port_bp_counters_pairx_s cn63xx;
+        struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1;
 };
 
 union cvmx_ipd_port_qos_x_cnt {
@@ -572,6 +617,8 @@ union cvmx_ipd_port_qos_x_cnt {
         struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;
         struct cvmx_ipd_port_qos_x_cnt_s cn56xx;
         struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;
+        struct cvmx_ipd_port_qos_x_cnt_s cn63xx;
+        struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1;
 };
 
 union cvmx_ipd_port_qos_intx {
@@ -583,6 +630,8 @@ union cvmx_ipd_port_qos_intx {
         struct cvmx_ipd_port_qos_intx_s cn52xxp1;
         struct cvmx_ipd_port_qos_intx_s cn56xx;
         struct cvmx_ipd_port_qos_intx_s cn56xxp1;
+        struct cvmx_ipd_port_qos_intx_s cn63xx;
+        struct cvmx_ipd_port_qos_intx_s cn63xxp1;
 };
 
 union cvmx_ipd_port_qos_int_enbx {
@@ -594,6 +643,8 @@ union cvmx_ipd_port_qos_int_enbx {
         struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;
         struct cvmx_ipd_port_qos_int_enbx_s cn56xx;
         struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;
+        struct cvmx_ipd_port_qos_int_enbx_s cn63xx;
+        struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1;
 };
 
 union cvmx_ipd_prc_hold_ptr_fifo_ctl {
@@ -616,6 +667,8 @@ union cvmx_ipd_prc_hold_ptr_fifo_ctl {
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
+        struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx;
+        struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1;
 };
 
 union cvmx_ipd_prc_port_ptr_fifo_ctl {
@@ -637,6 +690,8 @@ union cvmx_ipd_prc_port_ptr_fifo_ctl {
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
+        struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx;
+        struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1;
 };
 
 union cvmx_ipd_ptr_count {
@@ -660,6 +715,8 @@ union cvmx_ipd_ptr_count {
         struct cvmx_ipd_ptr_count_s cn56xxp1;
         struct cvmx_ipd_ptr_count_s cn58xx;
         struct cvmx_ipd_ptr_count_s cn58xxp1;
+        struct cvmx_ipd_ptr_count_s cn63xx;
+        struct cvmx_ipd_ptr_count_s cn63xxp1;
 };
 
 union cvmx_ipd_pwp_ptr_fifo_ctl {
@@ -683,6 +740,8 @@ union cvmx_ipd_pwp_ptr_fifo_ctl {
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;
+        struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx;
+        struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1;
 };
 
 union cvmx_ipd_qosx_red_marks {
@@ -702,6 +761,8 @@ union cvmx_ipd_qosx_red_marks {
         struct cvmx_ipd_qosx_red_marks_s cn56xxp1;
         struct cvmx_ipd_qosx_red_marks_s cn58xx;
         struct cvmx_ipd_qosx_red_marks_s cn58xxp1;
+        struct cvmx_ipd_qosx_red_marks_s cn63xx;
+        struct cvmx_ipd_qosx_red_marks_s cn63xxp1;
 };
 
 union cvmx_ipd_que0_free_page_cnt {
@@ -721,6 +782,8 @@ union cvmx_ipd_que0_free_page_cnt {
         struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
         struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
         struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
+        struct cvmx_ipd_que0_free_page_cnt_s cn63xx;
+        struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1;
 };
 
 union cvmx_ipd_red_port_enable {
@@ -741,18 +804,25 @@ union cvmx_ipd_red_port_enable {
         struct cvmx_ipd_red_port_enable_s cn56xxp1;
         struct cvmx_ipd_red_port_enable_s cn58xx;
         struct cvmx_ipd_red_port_enable_s cn58xxp1;
+        struct cvmx_ipd_red_port_enable_s cn63xx;
+        struct cvmx_ipd_red_port_enable_s cn63xxp1;
 };
 
 union cvmx_ipd_red_port_enable2 {
         uint64_t u64;
         struct cvmx_ipd_red_port_enable2_s {
+                uint64_t reserved_8_63:56;
+                uint64_t prt_enb:8;
+        } s;
+        struct cvmx_ipd_red_port_enable2_cn52xx {
                 uint64_t reserved_4_63:60;
                 uint64_t prt_enb:4;
-        } s;
-        struct cvmx_ipd_red_port_enable2_s cn52xx;
-        struct cvmx_ipd_red_port_enable2_s cn52xxp1;
-        struct cvmx_ipd_red_port_enable2_s cn56xx;
-        struct cvmx_ipd_red_port_enable2_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1;
+        struct cvmx_ipd_red_port_enable2_cn52xx cn56xx;
+        struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1;
+        struct cvmx_ipd_red_port_enable2_s cn63xx;
+        struct cvmx_ipd_red_port_enable2_s cn63xxp1;
 };
 
 union cvmx_ipd_red_quex_param {
@@ -775,6 +845,8 @@ union cvmx_ipd_red_quex_param {
         struct cvmx_ipd_red_quex_param_s cn56xxp1;
         struct cvmx_ipd_red_quex_param_s cn58xx;
         struct cvmx_ipd_red_quex_param_s cn58xxp1;
+        struct cvmx_ipd_red_quex_param_s cn63xx;
+        struct cvmx_ipd_red_quex_param_s cn63xxp1;
 };
 
 union cvmx_ipd_sub_port_bp_page_cnt {
@@ -795,6 +867,8 @@ union cvmx_ipd_sub_port_bp_page_cnt {
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
+        struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx;
+        struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1;
 };
 
 union cvmx_ipd_sub_port_fcs {
@@ -822,6 +896,8 @@ union cvmx_ipd_sub_port_fcs {
         struct cvmx_ipd_sub_port_fcs_s cn56xxp1;
         struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;
         struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;
+        struct cvmx_ipd_sub_port_fcs_s cn63xx;
+        struct cvmx_ipd_sub_port_fcs_s cn63xxp1;
 };
 
 union cvmx_ipd_sub_port_qos_cnt {
@@ -835,6 +911,8 @@ union cvmx_ipd_sub_port_qos_cnt {
         struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;
         struct cvmx_ipd_sub_port_qos_cnt_s cn56xx;
         struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;
+        struct cvmx_ipd_sub_port_qos_cnt_s cn63xx;
+        struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1;
 };
 
 union cvmx_ipd_wqe_fpa_queue {
@@ -854,6 +932,8 @@ union cvmx_ipd_wqe_fpa_queue {
         struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;
         struct cvmx_ipd_wqe_fpa_queue_s cn58xx;
         struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;
+        struct cvmx_ipd_wqe_fpa_queue_s cn63xx;
+        struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1;
 };
 
 union cvmx_ipd_wqe_ptr_valid {
@@ -872,6 +952,8 @@ union cvmx_ipd_wqe_ptr_valid {
         struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;
         struct cvmx_ipd_wqe_ptr_valid_s cn58xx;
         struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;
+        struct cvmx_ipd_wqe_ptr_valid_s cn63xx;
+        struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
index 337583842b51..7a50a0beb472 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,70 +28,113 @@
 #ifndef __CVMX_L2C_DEFS_H__
 #define __CVMX_L2C_DEFS_H__
 
-#define CVMX_L2C_BST0 \
-         CVMX_ADD_IO_SEG(0x00011800800007F8ull)
-#define CVMX_L2C_BST1 \
-         CVMX_ADD_IO_SEG(0x00011800800007F0ull)
-#define CVMX_L2C_BST2 \
-         CVMX_ADD_IO_SEG(0x00011800800007E8ull)
-#define CVMX_L2C_CFG \
-         CVMX_ADD_IO_SEG(0x0001180080000000ull)
-#define CVMX_L2C_DBG \
-         CVMX_ADD_IO_SEG(0x0001180080000030ull)
-#define CVMX_L2C_DUT \
-         CVMX_ADD_IO_SEG(0x0001180080000050ull)
-#define CVMX_L2C_GRPWRR0 \
-         CVMX_ADD_IO_SEG(0x00011800800000C8ull)
-#define CVMX_L2C_GRPWRR1 \
-         CVMX_ADD_IO_SEG(0x00011800800000D0ull)
-#define CVMX_L2C_INT_EN \
-         CVMX_ADD_IO_SEG(0x0001180080000100ull)
-#define CVMX_L2C_INT_STAT \
-         CVMX_ADD_IO_SEG(0x00011800800000F8ull)
-#define CVMX_L2C_LCKBASE \
-         CVMX_ADD_IO_SEG(0x0001180080000058ull)
-#define CVMX_L2C_LCKOFF \
-         CVMX_ADD_IO_SEG(0x0001180080000060ull)
-#define CVMX_L2C_LFB0 \
-         CVMX_ADD_IO_SEG(0x0001180080000038ull)
-#define CVMX_L2C_LFB1 \
-         CVMX_ADD_IO_SEG(0x0001180080000040ull)
-#define CVMX_L2C_LFB2 \
-         CVMX_ADD_IO_SEG(0x0001180080000048ull)
-#define CVMX_L2C_LFB3 \
-         CVMX_ADD_IO_SEG(0x00011800800000B8ull)
-#define CVMX_L2C_OOB \
-         CVMX_ADD_IO_SEG(0x00011800800000D8ull)
-#define CVMX_L2C_OOB1 \
-         CVMX_ADD_IO_SEG(0x00011800800000E0ull)
-#define CVMX_L2C_OOB2 \
-         CVMX_ADD_IO_SEG(0x00011800800000E8ull)
-#define CVMX_L2C_OOB3 \
-         CVMX_ADD_IO_SEG(0x00011800800000F0ull)
-#define CVMX_L2C_PFC0 \
-         CVMX_ADD_IO_SEG(0x0001180080000098ull)
-#define CVMX_L2C_PFC1 \
-         CVMX_ADD_IO_SEG(0x00011800800000A0ull)
-#define CVMX_L2C_PFC2 \
-         CVMX_ADD_IO_SEG(0x00011800800000A8ull)
-#define CVMX_L2C_PFC3 \
-         CVMX_ADD_IO_SEG(0x00011800800000B0ull)
-#define CVMX_L2C_PFCTL \
-         CVMX_ADD_IO_SEG(0x0001180080000090ull)
-#define CVMX_L2C_PFCX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180080000098ull + (((offset) & 3) * 8))
-#define CVMX_L2C_PPGRP \
-         CVMX_ADD_IO_SEG(0x00011800800000C0ull)
-#define CVMX_L2C_SPAR0 \
-         CVMX_ADD_IO_SEG(0x0001180080000068ull)
-#define CVMX_L2C_SPAR1 \
-         CVMX_ADD_IO_SEG(0x0001180080000070ull)
-#define CVMX_L2C_SPAR2 \
-         CVMX_ADD_IO_SEG(0x0001180080000078ull)
-#define CVMX_L2C_SPAR3 \
-         CVMX_ADD_IO_SEG(0x0001180080000080ull)
-#define CVMX_L2C_SPAR4 \
-         CVMX_ADD_IO_SEG(0x0001180080000088ull)
+#define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull))
+#define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull))
+#define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull))
+#define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull))
+#define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull))
+#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull))
+#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull))
+#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull))
+#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
+#define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8)
+#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
+#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
+#define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull))
+#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8)
+#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull))
+#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull))
+#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull))
+#define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull))
+#define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull))
+#define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull))
+#define CVMX_L2C_INT_EN (CVMX_ADD_IO_SEG(0x0001180080000100ull))
+#define CVMX_L2C_INT_ENA (CVMX_ADD_IO_SEG(0x0001180080800020ull))
+#define CVMX_L2C_INT_REG (CVMX_ADD_IO_SEG(0x0001180080800018ull))
+#define CVMX_L2C_INT_STAT (CVMX_ADD_IO_SEG(0x00011800800000F8ull))
+#define CVMX_L2C_IOCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800420ull))
+#define CVMX_L2C_IORX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800428ull))
+#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull))
+#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull))
+#define CVMX_L2C_LFB0 (CVMX_ADD_IO_SEG(0x0001180080000038ull))
+#define CVMX_L2C_LFB1 (CVMX_ADD_IO_SEG(0x0001180080000040ull))
+#define CVMX_L2C_LFB2 (CVMX_ADD_IO_SEG(0x0001180080000048ull))
+#define CVMX_L2C_LFB3 (CVMX_ADD_IO_SEG(0x00011800800000B8ull))
+#define CVMX_L2C_OOB (CVMX_ADD_IO_SEG(0x00011800800000D8ull))
+#define CVMX_L2C_OOB1 (CVMX_ADD_IO_SEG(0x00011800800000E0ull))
+#define CVMX_L2C_OOB2 (CVMX_ADD_IO_SEG(0x00011800800000E8ull))
+#define CVMX_L2C_OOB3 (CVMX_ADD_IO_SEG(0x00011800800000F0ull))
+#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
+#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
+#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
+#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
+#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
+#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8)
+#define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull))
+#define CVMX_L2C_QOS_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080880200ull))
+#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull))
+#define CVMX_L2C_RSCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800410ull))
+#define CVMX_L2C_RSDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800418ull))
+#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull))
+#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull))
+#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull))
+#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull))
+#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull))
+#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull))
+#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull))
+#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull))
+#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull))
+#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull))
+#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull))
+#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull))
+#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull))
+#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull))
+#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull))
+#define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull))
+#define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull))
+#define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull))
+#define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull))
+#define CVMX_L2C_VIRTID_IOBX(block_id) (CVMX_ADD_IO_SEG(0x00011800808C0200ull))
+#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull))
+#define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8)
+#define CVMX_L2C_WPAR_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080840200ull))
+#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_XMCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800400ull))
+#define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull))
+#define CVMX_L2C_XMDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800408ull))
+
+union cvmx_l2c_big_ctl {
+        uint64_t u64;
+        struct cvmx_l2c_big_ctl_s {
+                uint64_t reserved_8_63:56;
+                uint64_t maxdram:4;
+                uint64_t reserved_1_3:3;
+                uint64_t disable:1;
+        } s;
+        struct cvmx_l2c_big_ctl_s cn63xx;
+};
+
+union cvmx_l2c_bst {
+        uint64_t u64;
+        struct cvmx_l2c_bst_s {
+                uint64_t reserved_38_63:26;
+                uint64_t dutfl:6;
+                uint64_t reserved_17_31:15;
+                uint64_t ioccmdfl:1;
+                uint64_t reserved_13_15:3;
+                uint64_t iocdatfl:1;
+                uint64_t reserved_9_11:3;
+                uint64_t dutresfl:1;
+                uint64_t reserved_5_7:3;
+                uint64_t vrtfl:1;
+                uint64_t reserved_1_3:3;
+                uint64_t tdffl:1;
+        } s;
+        struct cvmx_l2c_bst_s cn63xx;
+        struct cvmx_l2c_bst_s cn63xxp1;
+};
 
 union cvmx_l2c_bst0 {
         uint64_t u64;
@@ -253,6 +296,48 @@ union cvmx_l2c_bst2 {
         struct cvmx_l2c_bst2_cn56xx cn58xxp1;
 };
 
+union cvmx_l2c_bst_memx {
+        uint64_t u64;
+        struct cvmx_l2c_bst_memx_s {
+                uint64_t start_bist:1;
+                uint64_t clear_bist:1;
+                uint64_t reserved_5_61:57;
+                uint64_t rdffl:1;
+                uint64_t vbffl:4;
+        } s;
+        struct cvmx_l2c_bst_memx_s cn63xx;
+        struct cvmx_l2c_bst_memx_s cn63xxp1;
+};
+
+union cvmx_l2c_bst_tdtx {
+        uint64_t u64;
+        struct cvmx_l2c_bst_tdtx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t fbfrspfl:8;
+                uint64_t sbffl:8;
+                uint64_t fbffl:8;
+                uint64_t l2dfl:8;
+        } s;
+        struct cvmx_l2c_bst_tdtx_s cn63xx;
+        struct cvmx_l2c_bst_tdtx_cn63xxp1 {
+                uint64_t reserved_24_63:40;
+                uint64_t sbffl:8;
+                uint64_t fbffl:8;
+                uint64_t l2dfl:8;
+        } cn63xxp1;
+};
+
+union cvmx_l2c_bst_ttgx {
+        uint64_t u64;
+        struct cvmx_l2c_bst_ttgx_s {
+                uint64_t reserved_17_63:47;
+                uint64_t lrufl:1;
+                uint64_t tagfl:16;
+        } s;
+        struct cvmx_l2c_bst_ttgx_s cn63xx;
+        struct cvmx_l2c_bst_ttgx_s cn63xxp1;
+};
+
 union cvmx_l2c_cfg {
         uint64_t u64;
         struct cvmx_l2c_cfg_s {
@@ -333,6 +418,49 @@ union cvmx_l2c_cfg {
         } cn58xxp1;
 };
 
+union cvmx_l2c_cop0_mapx {
+        uint64_t u64;
+        struct cvmx_l2c_cop0_mapx_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_l2c_cop0_mapx_s cn63xx;
+        struct cvmx_l2c_cop0_mapx_s cn63xxp1;
+};
+
+union cvmx_l2c_ctl {
+        uint64_t u64;
+        struct cvmx_l2c_ctl_s {
+                uint64_t reserved_28_63:36;
+                uint64_t disstgl2i:1;
+                uint64_t l2dfsbe:1;
+                uint64_t l2dfdbe:1;
+                uint64_t discclk:1;
+                uint64_t maxvab:4;
+                uint64_t maxlfb:4;
+                uint64_t rsp_arb_mode:1;
+                uint64_t xmc_arb_mode:1;
+                uint64_t ef_ena:1;
+                uint64_t ef_cnt:7;
+                uint64_t vab_thresh:4;
+                uint64_t disecc:1;
+                uint64_t disidxalias:1;
+        } s;
+        struct cvmx_l2c_ctl_s cn63xx;
+        struct cvmx_l2c_ctl_cn63xxp1 {
+                uint64_t reserved_25_63:39;
+                uint64_t discclk:1;
+                uint64_t maxvab:4;
+                uint64_t maxlfb:4;
+                uint64_t rsp_arb_mode:1;
+                uint64_t xmc_arb_mode:1;
+                uint64_t ef_ena:1;
+                uint64_t ef_cnt:7;
+                uint64_t vab_thresh:4;
+                uint64_t disecc:1;
+                uint64_t disidxalias:1;
+        } cn63xxp1;
+};
+
 union cvmx_l2c_dbg {
         uint64_t u64;
         struct cvmx_l2c_dbg_s {
@@ -349,7 +477,9 @@ union cvmx_l2c_dbg {
                 uint64_t reserved_13_63:51;
                 uint64_t lfb_enum:2;
                 uint64_t lfb_dmp:1;
-                uint64_t reserved_5_9:5;
+                uint64_t reserved_7_9:3;
+                uint64_t ppnum:1;
+                uint64_t reserved_5_5:1;
                 uint64_t set:2;
                 uint64_t finv:1;
                 uint64_t l2d:1;
@@ -420,6 +550,79 @@ union cvmx_l2c_dut {
         struct cvmx_l2c_dut_s cn58xxp1;
 };
 
+union cvmx_l2c_dut_mapx {
+        uint64_t u64;
+        struct cvmx_l2c_dut_mapx_s {
+                uint64_t reserved_38_63:26;
+                uint64_t tag:28;
+                uint64_t reserved_1_9:9;
+                uint64_t valid:1;
+        } s;
+        struct cvmx_l2c_dut_mapx_s cn63xx;
+        struct cvmx_l2c_dut_mapx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_tdtx {
+        uint64_t u64;
+        struct cvmx_l2c_err_tdtx_s {
+                uint64_t dbe:1;
+                uint64_t sbe:1;
+                uint64_t vdbe:1;
+                uint64_t vsbe:1;
+                uint64_t syn:10;
+                uint64_t reserved_21_49:29;
+                uint64_t wayidx:17;
+                uint64_t reserved_2_3:2;
+                uint64_t type:2;
+        } s;
+        struct cvmx_l2c_err_tdtx_s cn63xx;
+        struct cvmx_l2c_err_tdtx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_ttgx {
+        uint64_t u64;
+        struct cvmx_l2c_err_ttgx_s {
+                uint64_t dbe:1;
+                uint64_t sbe:1;
+                uint64_t noway:1;
+                uint64_t reserved_56_60:5;
+                uint64_t syn:6;
+                uint64_t reserved_21_49:29;
+                uint64_t wayidx:14;
+                uint64_t reserved_2_6:5;
+                uint64_t type:2;
+        } s;
+        struct cvmx_l2c_err_ttgx_s cn63xx;
+        struct cvmx_l2c_err_ttgx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_vbfx {
+        uint64_t u64;
+        struct cvmx_l2c_err_vbfx_s {
+                uint64_t reserved_62_63:2;
+                uint64_t vdbe:1;
+                uint64_t vsbe:1;
+                uint64_t vsyn:10;
+                uint64_t reserved_2_49:48;
+                uint64_t type:2;
+        } s;
+        struct cvmx_l2c_err_vbfx_s cn63xx;
+        struct cvmx_l2c_err_vbfx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_xmc {
+        uint64_t u64;
+        struct cvmx_l2c_err_xmc_s {
+                uint64_t cmd:6;
+                uint64_t reserved_52_57:6;
+                uint64_t sid:4;
+                uint64_t reserved_38_47:10;
+                uint64_t addr:38;
+        } s;
+        struct cvmx_l2c_err_xmc_s cn63xx;
+        struct cvmx_l2c_err_xmc_s cn63xxp1;
+};
+
 union cvmx_l2c_grpwrr0 {
         uint64_t u64;
         struct cvmx_l2c_grpwrr0_s {
@@ -464,6 +667,60 @@ union cvmx_l2c_int_en {
         struct cvmx_l2c_int_en_s cn56xxp1;
 };
 
+union cvmx_l2c_int_ena {
+        uint64_t u64;
+        struct cvmx_l2c_int_ena_s {
+                uint64_t reserved_8_63:56;
+                uint64_t bigrd:1;
+                uint64_t bigwr:1;
+                uint64_t vrtpe:1;
+                uint64_t vrtadrng:1;
+                uint64_t vrtidrng:1;
+                uint64_t vrtwr:1;
+                uint64_t holewr:1;
+                uint64_t holerd:1;
+        } s;
+        struct cvmx_l2c_int_ena_s cn63xx;
+        struct cvmx_l2c_int_ena_cn63xxp1 {
+                uint64_t reserved_6_63:58;
+                uint64_t vrtpe:1;
+                uint64_t vrtadrng:1;
+                uint64_t vrtidrng:1;
+                uint64_t vrtwr:1;
+                uint64_t holewr:1;
+                uint64_t holerd:1;
+        } cn63xxp1;
+};
+
+union cvmx_l2c_int_reg {
+        uint64_t u64;
+        struct cvmx_l2c_int_reg_s {
+                uint64_t reserved_17_63:47;
+                uint64_t tad0:1;
+                uint64_t reserved_8_15:8;
+                uint64_t bigrd:1;
+                uint64_t bigwr:1;
+                uint64_t vrtpe:1;
+                uint64_t vrtadrng:1;
+                uint64_t vrtidrng:1;
+                uint64_t vrtwr:1;
+                uint64_t holewr:1;
+                uint64_t holerd:1;
+        } s;
+        struct cvmx_l2c_int_reg_s cn63xx;
+        struct cvmx_l2c_int_reg_cn63xxp1 {
+                uint64_t reserved_17_63:47;
+                uint64_t tad0:1;
+                uint64_t reserved_6_15:10;
+                uint64_t vrtpe:1;
+                uint64_t vrtadrng:1;
+                uint64_t vrtidrng:1;
+                uint64_t vrtwr:1;
+                uint64_t holewr:1;
+                uint64_t holerd:1;
+        } cn63xxp1;
+};
+
 union cvmx_l2c_int_stat {
         uint64_t u64;
         struct cvmx_l2c_int_stat_s {
@@ -484,6 +741,24 @@ union cvmx_l2c_int_stat {
         struct cvmx_l2c_int_stat_s cn56xxp1;
 };
 
+union cvmx_l2c_iocx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_iocx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_iocx_pfc_s cn63xx;
+        struct cvmx_l2c_iocx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_iorx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_iorx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_iorx_pfc_s cn63xx;
+        struct cvmx_l2c_iorx_pfc_s cn63xxp1;
+};
+
 union cvmx_l2c_lckbase {
         uint64_t u64;
         struct cvmx_l2c_lckbase_s {
@@ -855,6 +1130,59 @@ union cvmx_l2c_ppgrp {
         struct cvmx_l2c_ppgrp_s cn56xxp1;
 };
 
+union cvmx_l2c_qos_iobx {
+        uint64_t u64;
+        struct cvmx_l2c_qos_iobx_s {
+                uint64_t reserved_6_63:58;
+                uint64_t dwblvl:2;
+                uint64_t reserved_2_3:2;
+                uint64_t lvl:2;
+        } s;
+        struct cvmx_l2c_qos_iobx_s cn63xx;
+        struct cvmx_l2c_qos_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_qos_ppx {
+        uint64_t u64;
+        struct cvmx_l2c_qos_ppx_s {
+                uint64_t reserved_2_63:62;
+                uint64_t lvl:2;
+        } s;
+        struct cvmx_l2c_qos_ppx_s cn63xx;
+        struct cvmx_l2c_qos_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_qos_wgt {
+        uint64_t u64;
+        struct cvmx_l2c_qos_wgt_s {
+                uint64_t reserved_32_63:32;
+                uint64_t wgt3:8;
+                uint64_t wgt2:8;
+                uint64_t wgt1:8;
+                uint64_t wgt0:8;
+        } s;
+        struct cvmx_l2c_qos_wgt_s cn63xx;
+        struct cvmx_l2c_qos_wgt_s cn63xxp1;
+};
+
+union cvmx_l2c_rscx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_rscx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_rscx_pfc_s cn63xx;
+        struct cvmx_l2c_rscx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_rsdx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_rsdx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_rsdx_pfc_s cn63xx;
+        struct cvmx_l2c_rsdx_pfc_s cn63xxp1;
+};
+
 union cvmx_l2c_spar0 {
         uint64_t u64;
         struct cvmx_l2c_spar0_s {
@@ -960,4 +1288,282 @@ union cvmx_l2c_spar4 {
         struct cvmx_l2c_spar4_s cn58xxp1;
 };
 
+union cvmx_l2c_tadx_ecc0 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_ecc0_s {
+                uint64_t reserved_58_63:6;
+                uint64_t ow3ecc:10;
+                uint64_t reserved_42_47:6;
+                uint64_t ow2ecc:10;
+                uint64_t reserved_26_31:6;
+                uint64_t ow1ecc:10;
+                uint64_t reserved_10_15:6;
+                uint64_t ow0ecc:10;
+        } s;
+        struct cvmx_l2c_tadx_ecc0_s cn63xx;
+        struct cvmx_l2c_tadx_ecc0_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_ecc1 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_ecc1_s {
+                uint64_t reserved_58_63:6;
+                uint64_t ow7ecc:10;
+                uint64_t reserved_42_47:6;
+                uint64_t ow6ecc:10;
+                uint64_t reserved_26_31:6;
+                uint64_t ow5ecc:10;
+                uint64_t reserved_10_15:6;
+                uint64_t ow4ecc:10;
+        } s;
+        struct cvmx_l2c_tadx_ecc1_s cn63xx;
+        struct cvmx_l2c_tadx_ecc1_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_ien {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_ien_s {
+                uint64_t reserved_9_63:55;
+                uint64_t wrdislmc:1;
+                uint64_t rddislmc:1;
+                uint64_t noway:1;
+                uint64_t vbfdbe:1;
+                uint64_t vbfsbe:1;
+                uint64_t tagdbe:1;
+                uint64_t tagsbe:1;
+                uint64_t l2ddbe:1;
+                uint64_t l2dsbe:1;
+        } s;
+        struct cvmx_l2c_tadx_ien_s cn63xx;
+        struct cvmx_l2c_tadx_ien_cn63xxp1 {
+                uint64_t reserved_7_63:57;
+                uint64_t noway:1;
+                uint64_t vbfdbe:1;
+                uint64_t vbfsbe:1;
+                uint64_t tagdbe:1;
+                uint64_t tagsbe:1;
+                uint64_t l2ddbe:1;
+                uint64_t l2dsbe:1;
+        } cn63xxp1;
+};
+
+union cvmx_l2c_tadx_int {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_int_s {
+                uint64_t reserved_9_63:55;
+                uint64_t wrdislmc:1;
+                uint64_t rddislmc:1;
+                uint64_t noway:1;
+                uint64_t vbfdbe:1;
+                uint64_t vbfsbe:1;
+                uint64_t tagdbe:1;
+                uint64_t tagsbe:1;
+                uint64_t l2ddbe:1;
+                uint64_t l2dsbe:1;
+        } s;
+        struct cvmx_l2c_tadx_int_s cn63xx;
+};
+
+union cvmx_l2c_tadx_pfc0 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_pfc0_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_tadx_pfc0_s cn63xx;
+        struct cvmx_l2c_tadx_pfc0_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc1 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_pfc1_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_tadx_pfc1_s cn63xx;
+        struct cvmx_l2c_tadx_pfc1_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc2 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_pfc2_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_tadx_pfc2_s cn63xx;
+        struct cvmx_l2c_tadx_pfc2_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc3 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_pfc3_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_tadx_pfc3_s cn63xx;
+        struct cvmx_l2c_tadx_pfc3_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_prf {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_prf_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt3sel:8;
+                uint64_t cnt2sel:8;
+                uint64_t cnt1sel:8;
+                uint64_t cnt0sel:8;
+        } s;
+        struct cvmx_l2c_tadx_prf_s cn63xx;
+        struct cvmx_l2c_tadx_prf_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_tag {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_tag_s {
+                uint64_t reserved_46_63:18;
+                uint64_t ecc:6;
+                uint64_t reserved_36_39:4;
+                uint64_t tag:19;
+                uint64_t reserved_4_16:13;
+                uint64_t use:1;
+                uint64_t valid:1;
+                uint64_t dirty:1;
+                uint64_t lock:1;
+        } s;
+        struct cvmx_l2c_tadx_tag_s cn63xx;
+        struct cvmx_l2c_tadx_tag_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_id {
+        uint64_t u64;
+        struct cvmx_l2c_ver_id_s {
+                uint64_t mask:64;
+        } s;
+        struct cvmx_l2c_ver_id_s cn63xx;
+        struct cvmx_l2c_ver_id_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_iob {
+        uint64_t u64;
+        struct cvmx_l2c_ver_iob_s {
+                uint64_t reserved_1_63:63;
+                uint64_t mask:1;
+        } s;
+        struct cvmx_l2c_ver_iob_s cn63xx;
+        struct cvmx_l2c_ver_iob_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_msc {
+        uint64_t u64;
+        struct cvmx_l2c_ver_msc_s {
+                uint64_t reserved_2_63:62;
+                uint64_t invl2:1;
+                uint64_t dwb:1;
+        } s;
+        struct cvmx_l2c_ver_msc_s cn63xx;
+};
+
+union cvmx_l2c_ver_pp {
+        uint64_t u64;
+        struct cvmx_l2c_ver_pp_s {
+                uint64_t reserved_6_63:58;
+                uint64_t mask:6;
+        } s;
+        struct cvmx_l2c_ver_pp_s cn63xx;
+        struct cvmx_l2c_ver_pp_s cn63xxp1;
+};
+
+union cvmx_l2c_virtid_iobx {
+        uint64_t u64;
+        struct cvmx_l2c_virtid_iobx_s {
+                uint64_t reserved_14_63:50;
+                uint64_t dwbid:6;
+                uint64_t reserved_6_7:2;
+                uint64_t id:6;
+        } s;
+        struct cvmx_l2c_virtid_iobx_s cn63xx;
+        struct cvmx_l2c_virtid_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_virtid_ppx {
+        uint64_t u64;
+        struct cvmx_l2c_virtid_ppx_s {
+                uint64_t reserved_6_63:58;
+                uint64_t id:6;
+        } s;
+        struct cvmx_l2c_virtid_ppx_s cn63xx;
+        struct cvmx_l2c_virtid_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_vrt_ctl {
+        uint64_t u64;
+        struct cvmx_l2c_vrt_ctl_s {
+                uint64_t reserved_9_63:55;
+                uint64_t ooberr:1;
+                uint64_t reserved_7_7:1;
+                uint64_t memsz:3;
+                uint64_t numid:3;
+                uint64_t enable:1;
+        } s;
+        struct cvmx_l2c_vrt_ctl_s cn63xx;
+        struct cvmx_l2c_vrt_ctl_s cn63xxp1;
+};
+
+union cvmx_l2c_vrt_memx {
+        uint64_t u64;
+        struct cvmx_l2c_vrt_memx_s {
+                uint64_t reserved_36_63:28;
+                uint64_t parity:4;
+                uint64_t data:32;
+        } s;
+        struct cvmx_l2c_vrt_memx_s cn63xx;
+        struct cvmx_l2c_vrt_memx_s cn63xxp1;
+};
+
+union cvmx_l2c_wpar_iobx {
+        uint64_t u64;
+        struct cvmx_l2c_wpar_iobx_s {
+                uint64_t reserved_16_63:48;
+                uint64_t mask:16;
+        } s;
+        struct cvmx_l2c_wpar_iobx_s cn63xx;
+        struct cvmx_l2c_wpar_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_wpar_ppx {
+        uint64_t u64;
+        struct cvmx_l2c_wpar_ppx_s {
+                uint64_t reserved_16_63:48;
+                uint64_t mask:16;
+        } s;
+        struct cvmx_l2c_wpar_ppx_s cn63xx;
+        struct cvmx_l2c_wpar_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_xmcx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_xmcx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_xmcx_pfc_s cn63xx;
+        struct cvmx_l2c_xmcx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_xmc_cmd {
+        uint64_t u64;
+        struct cvmx_l2c_xmc_cmd_s {
+                uint64_t inuse:1;
+                uint64_t cmd:6;
+                uint64_t reserved_38_56:19;
+                uint64_t addr:38;
+        } s;
+        struct cvmx_l2c_xmc_cmd_s cn63xx;
+        struct cvmx_l2c_xmc_cmd_s cn63xxp1;
+};
+
+union cvmx_l2c_xmdx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_xmdx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_xmdx_pfc_s cn63xx;
+        struct cvmx_l2c_xmdx_pfc_s cn63xxp1;
+};
+
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
index 2a8c0902ea50..0b32c5b118e2 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -26,7 +26,6 @@
  ***********************license end**************************************/
 
 /*
- *
  * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
  * facilities.
  */
@@ -34,93 +33,126 @@
 #ifndef __CVMX_L2C_H__
 #define __CVMX_L2C_H__
 
-/* Deprecated macro, use function */
-#define CVMX_L2_ASSOC     cvmx_l2c_get_num_assoc()
-
-/* Deprecated macro, use function */
-#define CVMX_L2_SET_BITS  cvmx_l2c_get_set_bits()
+#define CVMX_L2_ASSOC     cvmx_l2c_get_num_assoc()   /* Deprecated macro, use function */
+#define CVMX_L2_SET_BITS  cvmx_l2c_get_set_bits()    /* Deprecated macro, use function */
+#define CVMX_L2_SETS      cvmx_l2c_get_num_sets()    /* Deprecated macro, use function */
 
-/* Deprecated macro, use function */
-#define CVMX_L2_SETS      cvmx_l2c_get_num_sets()
 
 #define CVMX_L2C_IDX_ADDR_SHIFT 7  /* based on 128 byte cache line size */
 #define CVMX_L2C_IDX_MASK       (cvmx_l2c_get_num_sets() - 1)
 
 /* Defines for index aliasing computations */
-#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT \
-        (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
+#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
+#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+#define CVMX_L2C_MEMBANK_SELECT_SIZE  4096
 
-#define CVMX_L2C_ALIAS_MASK \
-        (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+/* Defines for Virtualizations, valid only from Octeon II onwards. */
+#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0)
+#define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0)
 
 union cvmx_l2c_tag {
         uint64_t u64;
         struct {
                 uint64_t reserved:28;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:32;       /* Phys mem (not all bits valid) */
         } s;
 };
 
+/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
+#define CVMX_L2C_TADS  1
+
   /* L2C Performance Counter events. */
 enum cvmx_l2c_event {
-        CVMX_L2C_EVENT_CYCLES = 0,
-        CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
-        CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
-        CVMX_L2C_EVENT_DATA_MISS = 3,
-        CVMX_L2C_EVENT_DATA_HIT = 4,
-        CVMX_L2C_EVENT_MISS = 5,
-        CVMX_L2C_EVENT_HIT = 6,
-        CVMX_L2C_EVENT_VICTIM_HIT = 7,
-        CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
-        CVMX_L2C_EVENT_TAG_PROBE = 9,
-        CVMX_L2C_EVENT_TAG_UPDATE = 10,
-        CVMX_L2C_EVENT_TAG_COMPLETE = 11,
-        CVMX_L2C_EVENT_TAG_DIRTY = 12,
-        CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
-        CVMX_L2C_EVENT_DATA_STORE_READ = 14,
+        CVMX_L2C_EVENT_CYCLES           =  0,
+        CVMX_L2C_EVENT_INSTRUCTION_MISS =  1,
+        CVMX_L2C_EVENT_INSTRUCTION_HIT  =  2,
+        CVMX_L2C_EVENT_DATA_MISS        =  3,
+        CVMX_L2C_EVENT_DATA_HIT         =  4,
+        CVMX_L2C_EVENT_MISS             =  5,
+        CVMX_L2C_EVENT_HIT              =  6,
+        CVMX_L2C_EVENT_VICTIM_HIT       =  7,
+        CVMX_L2C_EVENT_INDEX_CONFLICT   =  8,
+        CVMX_L2C_EVENT_TAG_PROBE        =  9,
+        CVMX_L2C_EVENT_TAG_UPDATE       = 10,
+        CVMX_L2C_EVENT_TAG_COMPLETE     = 11,
+        CVMX_L2C_EVENT_TAG_DIRTY        = 12,
+        CVMX_L2C_EVENT_DATA_STORE_NOP   = 13,
+        CVMX_L2C_EVENT_DATA_STORE_READ  = 14,
         CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
-        CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
-        CVMX_L2C_EVENT_WRITE_REQUEST = 17,
-        CVMX_L2C_EVENT_READ_REQUEST = 18,
+        CVMX_L2C_EVENT_FILL_DATA_VALID  = 16,
+        CVMX_L2C_EVENT_WRITE_REQUEST    = 17,
+        CVMX_L2C_EVENT_READ_REQUEST     = 18,
         CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
-        CVMX_L2C_EVENT_XMC_NOP = 20,
-        CVMX_L2C_EVENT_XMC_LDT = 21,
-        CVMX_L2C_EVENT_XMC_LDI = 22,
-        CVMX_L2C_EVENT_XMC_LDD = 23,
-        CVMX_L2C_EVENT_XMC_STF = 24,
-        CVMX_L2C_EVENT_XMC_STT = 25,
-        CVMX_L2C_EVENT_XMC_STP = 26,
-        CVMX_L2C_EVENT_XMC_STC = 27,
-        CVMX_L2C_EVENT_XMC_DWB = 28,
-        CVMX_L2C_EVENT_XMC_PL2 = 29,
-        CVMX_L2C_EVENT_XMC_PSL1 = 30,
-        CVMX_L2C_EVENT_XMC_IOBLD = 31,
-        CVMX_L2C_EVENT_XMC_IOBST = 32,
-        CVMX_L2C_EVENT_XMC_IOBDMA = 33,
-        CVMX_L2C_EVENT_XMC_IOBRSP = 34,
-        CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
-        CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
-        CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
-        CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
-        CVMX_L2C_EVENT_RSC_NOP = 39,
-        CVMX_L2C_EVENT_RSC_STDN = 40,
-        CVMX_L2C_EVENT_RSC_FILL = 41,
-        CVMX_L2C_EVENT_RSC_REFL = 42,
-        CVMX_L2C_EVENT_RSC_STIN = 43,
-        CVMX_L2C_EVENT_RSC_SCIN = 44,
-        CVMX_L2C_EVENT_RSC_SCFL = 45,
-        CVMX_L2C_EVENT_RSC_SCDN = 46,
-        CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
-        CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
-        CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
-        CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
-        CVMX_L2C_EVENT_LRF_REQ = 51,
-        CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
-        CVMX_L2C_EVENT_DT_WR_INVAL = 53
+        CVMX_L2C_EVENT_XMC_NOP          = 20,
+        CVMX_L2C_EVENT_XMC_LDT          = 21,
+        CVMX_L2C_EVENT_XMC_LDI          = 22,
+        CVMX_L2C_EVENT_XMC_LDD          = 23,
+        CVMX_L2C_EVENT_XMC_STF          = 24,
+        CVMX_L2C_EVENT_XMC_STT          = 25,
+        CVMX_L2C_EVENT_XMC_STP          = 26,
+        CVMX_L2C_EVENT_XMC_STC          = 27,
+        CVMX_L2C_EVENT_XMC_DWB          = 28,
+        CVMX_L2C_EVENT_XMC_PL2          = 29,
+        CVMX_L2C_EVENT_XMC_PSL1         = 30,
+        CVMX_L2C_EVENT_XMC_IOBLD        = 31,
+        CVMX_L2C_EVENT_XMC_IOBST        = 32,
+        CVMX_L2C_EVENT_XMC_IOBDMA       = 33,
+        CVMX_L2C_EVENT_XMC_IOBRSP       = 34,
+        CVMX_L2C_EVENT_XMC_BUS_VALID    = 35,
+        CVMX_L2C_EVENT_XMC_MEM_DATA     = 36,
+        CVMX_L2C_EVENT_XMC_REFL_DATA    = 37,
+        CVMX_L2C_EVENT_XMC_IOBRSP_DATA  = 38,
+        CVMX_L2C_EVENT_RSC_NOP          = 39,
+        CVMX_L2C_EVENT_RSC_STDN         = 40,
+        CVMX_L2C_EVENT_RSC_FILL         = 41,
+        CVMX_L2C_EVENT_RSC_REFL         = 42,
+        CVMX_L2C_EVENT_RSC_STIN         = 43,
+        CVMX_L2C_EVENT_RSC_SCIN         = 44,
+        CVMX_L2C_EVENT_RSC_SCFL         = 45,
+        CVMX_L2C_EVENT_RSC_SCDN         = 46,
+        CVMX_L2C_EVENT_RSC_DATA_VALID   = 47,
+        CVMX_L2C_EVENT_RSC_VALID_FILL   = 48,
+        CVMX_L2C_EVENT_RSC_VALID_STRSP  = 49,
+        CVMX_L2C_EVENT_RSC_VALID_REFL   = 50,
+        CVMX_L2C_EVENT_LRF_REQ          = 51,
+        CVMX_L2C_EVENT_DT_RD_ALLOC      = 52,
+        CVMX_L2C_EVENT_DT_WR_INVAL      = 53,
+        CVMX_L2C_EVENT_MAX
+};
+
+/* L2C Performance Counter events for Octeon2. */
+enum cvmx_l2c_tad_event {
+        CVMX_L2C_TAD_EVENT_NONE          = 0,
+        CVMX_L2C_TAD_EVENT_TAG_HIT       = 1,
+        CVMX_L2C_TAD_EVENT_TAG_MISS      = 2,
+        CVMX_L2C_TAD_EVENT_TAG_NOALLOC   = 3,
+        CVMX_L2C_TAD_EVENT_TAG_VICTIM    = 4,
+        CVMX_L2C_TAD_EVENT_SC_FAIL       = 5,
+        CVMX_L2C_TAD_EVENT_SC_PASS       = 6,
+        CVMX_L2C_TAD_EVENT_LFB_VALID     = 7,
+        CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB  = 8,
+        CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB  = 9,
+        CVMX_L2C_TAD_EVENT_QUAD0_INDEX   = 128,
+        CVMX_L2C_TAD_EVENT_QUAD0_READ    = 129,
+        CVMX_L2C_TAD_EVENT_QUAD0_BANK    = 130,
+        CVMX_L2C_TAD_EVENT_QUAD0_WDAT    = 131,
+        CVMX_L2C_TAD_EVENT_QUAD1_INDEX   = 144,
+        CVMX_L2C_TAD_EVENT_QUAD1_READ    = 145,
+        CVMX_L2C_TAD_EVENT_QUAD1_BANK    = 146,
+        CVMX_L2C_TAD_EVENT_QUAD1_WDAT    = 147,
+        CVMX_L2C_TAD_EVENT_QUAD2_INDEX   = 160,
+        CVMX_L2C_TAD_EVENT_QUAD2_READ    = 161,
+        CVMX_L2C_TAD_EVENT_QUAD2_BANK    = 162,
+        CVMX_L2C_TAD_EVENT_QUAD2_WDAT    = 163,
+        CVMX_L2C_TAD_EVENT_QUAD3_INDEX   = 176,
+        CVMX_L2C_TAD_EVENT_QUAD3_READ    = 177,
+        CVMX_L2C_TAD_EVENT_QUAD3_BANK    = 178,
+        CVMX_L2C_TAD_EVENT_QUAD3_WDAT    = 179,
+        CVMX_L2C_TAD_EVENT_MAX
 };
 
 /**
@@ -132,10 +164,10 @@ enum cvmx_l2c_event {
  * @clear_on_read:  When asserted, any read of the performance counter
  *                       clears the counter.
  *
- * The routine does not clear the counter.
+ * @note The routine does not clear the counter.
  */
-void cvmx_l2c_config_perf(uint32_t counter,
-                          enum cvmx_l2c_event event, uint32_t clear_on_read);
+void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t clear_on_read);
+
 /**
  * Read the given L2 Cache performance counter. The counter must be configured
  * before reading, but this routine does not enforce this requirement.
@@ -160,18 +192,18 @@ int cvmx_l2c_get_core_way_partition(uint32_t core);
 /**
  * Partitions the L2 cache for a core
  *
- * @core:  The core that the partitioning applies to.
+ * @core: The core that the partitioning applies to.
+ * @mask: The partitioning of the ways expressed as a binary
+ *             mask. A 0 bit allows the core to evict cache lines from
+ *             a way, while a 1 bit blocks the core from evicting any
+ *             lines from that way. There must be at least one allowed
+ *             way (0 bit) in the mask.
  *
- * @mask: The partitioning of the ways expressed as a binary mask. A 0
- *        bit allows the core to evict cache lines from a way, while a
- *        1 bit blocks the core from evicting any lines from that
- *        way. There must be at least one allowed way (0 bit) in the
- *        mask.
- *
- * If any ways are blocked for all cores and the HW blocks, then those
- * ways will never have any cache lines evicted from them.  All cores
- * and the hardware blocks are free to read from all ways regardless
- * of the partitioning.
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ *       those ways will never have any cache lines evicted from them.
+ *       All cores and the hardware blocks are free to read from all
+ *       ways regardless of the partitioning.
  */
 int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
 
@@ -187,19 +219,21 @@ int cvmx_l2c_get_hw_way_partition(void);
 /**
  * Partitions the L2 cache for the hardware blocks.
  *
- * @mask: The partitioning of the ways expressed as a binary mask. A 0
- *        bit allows the core to evict cache lines from a way, while a
- *        1 bit blocks the core from evicting any lines from that
- *        way. There must be at least one allowed way (0 bit) in the
- *        mask.
+ * @mask: The partitioning of the ways expressed as a binary
+ *             mask. A 0 bit allows the core to evict cache lines from
+ *             a way, while a 1 bit blocks the core from evicting any
+ *             lines from that way. There must be at least one allowed
+ *             way (0 bit) in the mask.
  *
- * If any ways are blocked for all cores and the HW blocks, then those
- * ways will never have any cache lines evicted from them.  All cores
- * and the hardware blocks are free to read from all ways regardless
- * of the partitioning.
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ *       those ways will never have any cache lines evicted from them.
+ *       All cores and the hardware blocks are free to read from all
+ *       ways regardless of the partitioning.
  */
 int cvmx_l2c_set_hw_way_partition(uint32_t mask);
 
+
 /**
  * Locks a line in the L2 cache at the specified physical address
  *
@@ -263,13 +297,14 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
  */
 union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
 
-/* Wrapper around deprecated old function name */
-static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
-                                              uint32_t index)
+/* Wrapper providing a deprecated old function name */
+static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated));
+static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index)
 {
         return cvmx_l2c_get_tag(association, index);
 }
 
+
 /**
  * Returns the cache index for a given physical address
  *
diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
index d7102d455e1b..60543e0e77fc 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,30 +28,18 @@
 #ifndef __CVMX_L2D_DEFS_H__
 #define __CVMX_L2D_DEFS_H__
 
-#define CVMX_L2D_BST0 \
-         CVMX_ADD_IO_SEG(0x0001180080000780ull)
-#define CVMX_L2D_BST1 \
-         CVMX_ADD_IO_SEG(0x0001180080000788ull)
-#define CVMX_L2D_BST2 \
-         CVMX_ADD_IO_SEG(0x0001180080000790ull)
-#define CVMX_L2D_BST3 \
-         CVMX_ADD_IO_SEG(0x0001180080000798ull)
-#define CVMX_L2D_ERR \
-         CVMX_ADD_IO_SEG(0x0001180080000010ull)
-#define CVMX_L2D_FADR \
-         CVMX_ADD_IO_SEG(0x0001180080000018ull)
-#define CVMX_L2D_FSYN0 \
-         CVMX_ADD_IO_SEG(0x0001180080000020ull)
-#define CVMX_L2D_FSYN1 \
-         CVMX_ADD_IO_SEG(0x0001180080000028ull)
-#define CVMX_L2D_FUS0 \
-         CVMX_ADD_IO_SEG(0x00011800800007A0ull)
-#define CVMX_L2D_FUS1 \
-         CVMX_ADD_IO_SEG(0x00011800800007A8ull)
-#define CVMX_L2D_FUS2 \
-         CVMX_ADD_IO_SEG(0x00011800800007B0ull)
-#define CVMX_L2D_FUS3 \
-         CVMX_ADD_IO_SEG(0x00011800800007B8ull)
+#define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
+#define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
+#define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
+#define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
+#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
+#define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
+#define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
+#define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
+#define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
+#define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
+#define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
+#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
 
 union cvmx_l2d_bst0 {
         uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
index 2639a3f5ffc2..873968f55eeb 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,8 +28,7 @@
 #ifndef __CVMX_L2T_DEFS_H__
 #define __CVMX_L2T_DEFS_H__
 
-#define CVMX_L2T_ERR \
-         CVMX_ADD_IO_SEG(0x0001180080000008ull)
+#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
 
 union cvmx_l2t_err {
         uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h
index 16f174a4dadf..e25173bb8bb7 100644
--- a/arch/mips/include/asm/octeon/cvmx-led-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,32 +28,19 @@
 #ifndef __CVMX_LED_DEFS_H__
 #define __CVMX_LED_DEFS_H__
 
-#define CVMX_LED_BLINK \
-         CVMX_ADD_IO_SEG(0x0001180000001A48ull)
-#define CVMX_LED_CLK_PHASE \
-         CVMX_ADD_IO_SEG(0x0001180000001A08ull)
-#define CVMX_LED_CYLON \
-         CVMX_ADD_IO_SEG(0x0001180000001AF8ull)
-#define CVMX_LED_DBG \
-         CVMX_ADD_IO_SEG(0x0001180000001A18ull)
-#define CVMX_LED_EN \
-         CVMX_ADD_IO_SEG(0x0001180000001A00ull)
-#define CVMX_LED_POLARITY \
-         CVMX_ADD_IO_SEG(0x0001180000001A50ull)
-#define CVMX_LED_PRT \
-         CVMX_ADD_IO_SEG(0x0001180000001A10ull)
-#define CVMX_LED_PRT_FMT \
-         CVMX_ADD_IO_SEG(0x0001180000001A30ull)
-#define CVMX_LED_PRT_STATUSX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8))
-#define CVMX_LED_UDD_CNTX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8))
-#define CVMX_LED_UDD_DATX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8))
-#define CVMX_LED_UDD_DAT_CLRX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16))
-#define CVMX_LED_UDD_DAT_SETX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16))
+#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
+#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
+#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
+#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
+#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
+#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
+#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
+#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
+#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
+#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
+#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
+#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
+#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
 
 union cvmx_led_blink {
         uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
index 6555f0530988..52b14a333ad4 100644
--- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,191 +28,117 @@
 #ifndef __CVMX_MIO_DEFS_H__
 #define __CVMX_MIO_DEFS_H__
 
-#define CVMX_MIO_BOOT_BIST_STAT \
-         CVMX_ADD_IO_SEG(0x00011800000000F8ull)
-#define CVMX_MIO_BOOT_COMP \
-         CVMX_ADD_IO_SEG(0x00011800000000B8ull)
-#define CVMX_MIO_BOOT_DMA_CFGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000100ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_INTX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000138ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000150ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_TIMX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000120ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_ERR \
-         CVMX_ADD_IO_SEG(0x00011800000000A0ull)
-#define CVMX_MIO_BOOT_INT \
-         CVMX_ADD_IO_SEG(0x00011800000000A8ull)
-#define CVMX_MIO_BOOT_LOC_ADR \
-         CVMX_ADD_IO_SEG(0x0001180000000090ull)
-#define CVMX_MIO_BOOT_LOC_CFGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000080ull + (((offset) & 1) * 8))
-#define CVMX_MIO_BOOT_LOC_DAT \
-         CVMX_ADD_IO_SEG(0x0001180000000098ull)
-#define CVMX_MIO_BOOT_PIN_DEFS \
-         CVMX_ADD_IO_SEG(0x00011800000000C0ull)
-#define CVMX_MIO_BOOT_REG_CFGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000000ull + (((offset) & 7) * 8))
-#define CVMX_MIO_BOOT_REG_TIMX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000040ull + (((offset) & 7) * 8))
-#define CVMX_MIO_BOOT_THR \
-         CVMX_ADD_IO_SEG(0x00011800000000B0ull)
-#define CVMX_MIO_FUS_BNK_DATX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001520ull + (((offset) & 3) * 8))
-#define CVMX_MIO_FUS_DAT0 \
-         CVMX_ADD_IO_SEG(0x0001180000001400ull)
-#define CVMX_MIO_FUS_DAT1 \
-         CVMX_ADD_IO_SEG(0x0001180000001408ull)
-#define CVMX_MIO_FUS_DAT2 \
-         CVMX_ADD_IO_SEG(0x0001180000001410ull)
-#define CVMX_MIO_FUS_DAT3 \
-         CVMX_ADD_IO_SEG(0x0001180000001418ull)
-#define CVMX_MIO_FUS_EMA \
-         CVMX_ADD_IO_SEG(0x0001180000001550ull)
-#define CVMX_MIO_FUS_PDF \
-         CVMX_ADD_IO_SEG(0x0001180000001420ull)
-#define CVMX_MIO_FUS_PLL \
-         CVMX_ADD_IO_SEG(0x0001180000001580ull)
-#define CVMX_MIO_FUS_PROG \
-         CVMX_ADD_IO_SEG(0x0001180000001510ull)
-#define CVMX_MIO_FUS_PROG_TIMES \
-         CVMX_ADD_IO_SEG(0x0001180000001518ull)
-#define CVMX_MIO_FUS_RCMD \
-         CVMX_ADD_IO_SEG(0x0001180000001500ull)
-#define CVMX_MIO_FUS_SPR_REPAIR_RES \
-         CVMX_ADD_IO_SEG(0x0001180000001548ull)
-#define CVMX_MIO_FUS_SPR_REPAIR_SUM \
-         CVMX_ADD_IO_SEG(0x0001180000001540ull)
-#define CVMX_MIO_FUS_UNLOCK \
-         CVMX_ADD_IO_SEG(0x0001180000001578ull)
-#define CVMX_MIO_FUS_WADR \
-         CVMX_ADD_IO_SEG(0x0001180000001508ull)
-#define CVMX_MIO_NDF_DMA_CFG \
-         CVMX_ADD_IO_SEG(0x0001180000000168ull)
-#define CVMX_MIO_NDF_DMA_INT \
-         CVMX_ADD_IO_SEG(0x0001180000000170ull)
-#define CVMX_MIO_NDF_DMA_INT_EN \
-         CVMX_ADD_IO_SEG(0x0001180000000178ull)
-#define CVMX_MIO_PLL_CTL \
-         CVMX_ADD_IO_SEG(0x0001180000001448ull)
-#define CVMX_MIO_PLL_SETTING \
-         CVMX_ADD_IO_SEG(0x0001180000001440ull)
-#define CVMX_MIO_TWSX_INT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001010ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_SW_TWSI(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001000ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001018ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_TWSI_SW(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001008ull + (((offset) & 1) * 512))
-#define CVMX_MIO_UART2_DLH \
-         CVMX_ADD_IO_SEG(0x0001180000000488ull)
-#define CVMX_MIO_UART2_DLL \
-         CVMX_ADD_IO_SEG(0x0001180000000480ull)
-#define CVMX_MIO_UART2_FAR \
-         CVMX_ADD_IO_SEG(0x0001180000000520ull)
-#define CVMX_MIO_UART2_FCR \
-         CVMX_ADD_IO_SEG(0x0001180000000450ull)
-#define CVMX_MIO_UART2_HTX \
-         CVMX_ADD_IO_SEG(0x0001180000000708ull)
-#define CVMX_MIO_UART2_IER \
-         CVMX_ADD_IO_SEG(0x0001180000000408ull)
-#define CVMX_MIO_UART2_IIR \
-         CVMX_ADD_IO_SEG(0x0001180000000410ull)
-#define CVMX_MIO_UART2_LCR \
-         CVMX_ADD_IO_SEG(0x0001180000000418ull)
-#define CVMX_MIO_UART2_LSR \
-         CVMX_ADD_IO_SEG(0x0001180000000428ull)
-#define CVMX_MIO_UART2_MCR \
-         CVMX_ADD_IO_SEG(0x0001180000000420ull)
-#define CVMX_MIO_UART2_MSR \
-         CVMX_ADD_IO_SEG(0x0001180000000430ull)
-#define CVMX_MIO_UART2_RBR \
-         CVMX_ADD_IO_SEG(0x0001180000000400ull)
-#define CVMX_MIO_UART2_RFL \
-         CVMX_ADD_IO_SEG(0x0001180000000608ull)
-#define CVMX_MIO_UART2_RFW \
-         CVMX_ADD_IO_SEG(0x0001180000000530ull)
-#define CVMX_MIO_UART2_SBCR \
-         CVMX_ADD_IO_SEG(0x0001180000000620ull)
-#define CVMX_MIO_UART2_SCR \
-         CVMX_ADD_IO_SEG(0x0001180000000438ull)
-#define CVMX_MIO_UART2_SFE \
-         CVMX_ADD_IO_SEG(0x0001180000000630ull)
-#define CVMX_MIO_UART2_SRR \
-         CVMX_ADD_IO_SEG(0x0001180000000610ull)
-#define CVMX_MIO_UART2_SRT \
-         CVMX_ADD_IO_SEG(0x0001180000000638ull)
-#define CVMX_MIO_UART2_SRTS \
-         CVMX_ADD_IO_SEG(0x0001180000000618ull)
-#define CVMX_MIO_UART2_STT \
-         CVMX_ADD_IO_SEG(0x0001180000000700ull)
-#define CVMX_MIO_UART2_TFL \
-         CVMX_ADD_IO_SEG(0x0001180000000600ull)
-#define CVMX_MIO_UART2_TFR \
-         CVMX_ADD_IO_SEG(0x0001180000000528ull)
-#define CVMX_MIO_UART2_THR \
-         CVMX_ADD_IO_SEG(0x0001180000000440ull)
-#define CVMX_MIO_UART2_USR \
-         CVMX_ADD_IO_SEG(0x0001180000000538ull)
-#define CVMX_MIO_UARTX_DLH(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000888ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_DLL(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000880ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_FAR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000920ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_FCR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000850ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_HTX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000B08ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_IER(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000808ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_IIR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000810ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_LCR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000818ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_LSR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000828ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_MCR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000820ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_MSR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000830ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RBR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000800ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RFL(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A08ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RFW(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000930ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SBCR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A20ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SCR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000838ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SFE(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A30ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A10ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A38ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRTS(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A18ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_STT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000B00ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_TFL(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A00ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_TFR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000928ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_THR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000840ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_USR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000938ull + (((offset) & 1) * 1024))
+#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
+#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
+#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
+#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
+#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
+#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
+#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
+#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
+#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
+#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
+#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
+#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
+#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
+#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
+#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
+#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
+#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
+#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
+#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
+#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
+#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
+#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
+#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
+#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
+#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
+#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
+#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
+#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
+#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
+#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
+#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
+#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
+#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
+#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
+#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
+#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
+#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
+#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
+#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
+#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
+#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
+#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
+#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
+#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
+#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
+#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
+#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
+#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
+#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
+#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
+#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
+#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
+#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
+#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
+#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
+#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
+#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
+#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
+#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
+#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
+#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
+#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
+#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
+#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
+#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
+#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
+#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
+#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
+#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
+#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
+#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
+#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
+#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
 
 union cvmx_mio_boot_bist_stat {
         uint64_t u64;
         struct cvmx_mio_boot_bist_stat_s {
-                uint64_t reserved_2_63:62;
-                uint64_t loc:1;
-                uint64_t ncbi:1;
+                uint64_t reserved_0_63:64;
         } s;
         struct cvmx_mio_boot_bist_stat_cn30xx {
                 uint64_t reserved_4_63:60;
@@ -257,20 +183,33 @@ union cvmx_mio_boot_bist_stat {
         struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
         struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
         struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
+        struct cvmx_mio_boot_bist_stat_cn63xx {
+                uint64_t reserved_9_63:55;
+                uint64_t stat:9;
+        } cn63xx;
+        struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_boot_comp {
         uint64_t u64;
         struct cvmx_mio_boot_comp_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_mio_boot_comp_cn50xx {
                 uint64_t reserved_10_63:54;
                 uint64_t pctl:5;
                 uint64_t nctl:5;
-        } s;
-        struct cvmx_mio_boot_comp_s cn50xx;
-        struct cvmx_mio_boot_comp_s cn52xx;
-        struct cvmx_mio_boot_comp_s cn52xxp1;
-        struct cvmx_mio_boot_comp_s cn56xx;
-        struct cvmx_mio_boot_comp_s cn56xxp1;
+        } cn50xx;
+        struct cvmx_mio_boot_comp_cn50xx cn52xx;
+        struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
+        struct cvmx_mio_boot_comp_cn50xx cn56xx;
+        struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
+        struct cvmx_mio_boot_comp_cn63xx {
+                uint64_t reserved_12_63:52;
+                uint64_t pctl:6;
+                uint64_t nctl:6;
+        } cn63xx;
+        struct cvmx_mio_boot_comp_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_boot_dma_cfgx {
@@ -291,6 +230,8 @@ union cvmx_mio_boot_dma_cfgx {
         struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
         struct cvmx_mio_boot_dma_cfgx_s cn56xx;
         struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_cfgx_s cn63xx;
+        struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_dma_intx {
@@ -304,6 +245,8 @@ union cvmx_mio_boot_dma_intx {
         struct cvmx_mio_boot_dma_intx_s cn52xxp1;
         struct cvmx_mio_boot_dma_intx_s cn56xx;
         struct cvmx_mio_boot_dma_intx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_intx_s cn63xx;
+        struct cvmx_mio_boot_dma_intx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_dma_int_enx {
@@ -317,6 +260,8 @@ union cvmx_mio_boot_dma_int_enx {
         struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
         struct cvmx_mio_boot_dma_int_enx_s cn56xx;
         struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_int_enx_s cn63xx;
+        struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_dma_timx {
@@ -342,6 +287,8 @@ union cvmx_mio_boot_dma_timx {
         struct cvmx_mio_boot_dma_timx_s cn52xxp1;
         struct cvmx_mio_boot_dma_timx_s cn56xx;
         struct cvmx_mio_boot_dma_timx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_timx_s cn63xx;
+        struct cvmx_mio_boot_dma_timx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_err {
@@ -362,6 +309,8 @@ union cvmx_mio_boot_err {
         struct cvmx_mio_boot_err_s cn56xxp1;
         struct cvmx_mio_boot_err_s cn58xx;
         struct cvmx_mio_boot_err_s cn58xxp1;
+        struct cvmx_mio_boot_err_s cn63xx;
+        struct cvmx_mio_boot_err_s cn63xxp1;
 };
 
 union cvmx_mio_boot_int {
@@ -382,6 +331,8 @@ union cvmx_mio_boot_int {
         struct cvmx_mio_boot_int_s cn56xxp1;
         struct cvmx_mio_boot_int_s cn58xx;
         struct cvmx_mio_boot_int_s cn58xxp1;
+        struct cvmx_mio_boot_int_s cn63xx;
+        struct cvmx_mio_boot_int_s cn63xxp1;
 };
 
 union cvmx_mio_boot_loc_adr {
@@ -402,6 +353,8 @@ union cvmx_mio_boot_loc_adr {
         struct cvmx_mio_boot_loc_adr_s cn56xxp1;
         struct cvmx_mio_boot_loc_adr_s cn58xx;
         struct cvmx_mio_boot_loc_adr_s cn58xxp1;
+        struct cvmx_mio_boot_loc_adr_s cn63xx;
+        struct cvmx_mio_boot_loc_adr_s cn63xxp1;
 };
 
 union cvmx_mio_boot_loc_cfgx {
@@ -424,6 +377,8 @@ union cvmx_mio_boot_loc_cfgx {
         struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
         struct cvmx_mio_boot_loc_cfgx_s cn58xx;
         struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
+        struct cvmx_mio_boot_loc_cfgx_s cn63xx;
+        struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_loc_dat {
@@ -442,6 +397,8 @@ union cvmx_mio_boot_loc_dat {
         struct cvmx_mio_boot_loc_dat_s cn56xxp1;
         struct cvmx_mio_boot_loc_dat_s cn58xx;
         struct cvmx_mio_boot_loc_dat_s cn58xxp1;
+        struct cvmx_mio_boot_loc_dat_s cn63xx;
+        struct cvmx_mio_boot_loc_dat_s cn63xxp1;
 };
 
 union cvmx_mio_boot_pin_defs {
@@ -478,6 +435,8 @@ union cvmx_mio_boot_pin_defs {
                 uint64_t term:2;
                 uint64_t reserved_0_8:9;
         } cn56xx;
+        struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
+        struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
 };
 
 union cvmx_mio_boot_reg_cfgx {
@@ -539,6 +498,8 @@ union cvmx_mio_boot_reg_cfgx {
         struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
         struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
         struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
+        struct cvmx_mio_boot_reg_cfgx_s cn63xx;
+        struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_reg_timx {
@@ -583,6 +544,8 @@ union cvmx_mio_boot_reg_timx {
         struct cvmx_mio_boot_reg_timx_s cn56xxp1;
         struct cvmx_mio_boot_reg_timx_s cn58xx;
         struct cvmx_mio_boot_reg_timx_s cn58xxp1;
+        struct cvmx_mio_boot_reg_timx_s cn63xx;
+        struct cvmx_mio_boot_reg_timx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_thr {
@@ -611,6 +574,8 @@ union cvmx_mio_boot_thr {
         struct cvmx_mio_boot_thr_s cn56xxp1;
         struct cvmx_mio_boot_thr_cn30xx cn58xx;
         struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
+        struct cvmx_mio_boot_thr_s cn63xx;
+        struct cvmx_mio_boot_thr_s cn63xxp1;
 };
 
 union cvmx_mio_fus_bnk_datx {
@@ -625,6 +590,8 @@ union cvmx_mio_fus_bnk_datx {
         struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
         struct cvmx_mio_fus_bnk_datx_s cn58xx;
         struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
+        struct cvmx_mio_fus_bnk_datx_s cn63xx;
+        struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
 };
 
 union cvmx_mio_fus_dat0 {
@@ -644,6 +611,8 @@ union cvmx_mio_fus_dat0 {
         struct cvmx_mio_fus_dat0_s cn56xxp1;
         struct cvmx_mio_fus_dat0_s cn58xx;
         struct cvmx_mio_fus_dat0_s cn58xxp1;
+        struct cvmx_mio_fus_dat0_s cn63xx;
+        struct cvmx_mio_fus_dat0_s cn63xxp1;
 };
 
 union cvmx_mio_fus_dat1 {
@@ -663,12 +632,15 @@ union cvmx_mio_fus_dat1 {
         struct cvmx_mio_fus_dat1_s cn56xxp1;
         struct cvmx_mio_fus_dat1_s cn58xx;
         struct cvmx_mio_fus_dat1_s cn58xxp1;
+        struct cvmx_mio_fus_dat1_s cn63xx;
+        struct cvmx_mio_fus_dat1_s cn63xxp1;
 };
 
 union cvmx_mio_fus_dat2 {
         uint64_t u64;
         struct cvmx_mio_fus_dat2_s {
-                uint64_t reserved_34_63:30;
+                uint64_t reserved_35_63:29;
+                uint64_t dorm_crypto:1;
                 uint64_t fus318:1;
                 uint64_t raid_en:1;
                 uint64_t reserved_30_31:2;
@@ -775,14 +747,38 @@ union cvmx_mio_fus_dat2 {
                 uint64_t pp_dis:16;
         } cn58xx;
         struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
+        struct cvmx_mio_fus_dat2_cn63xx {
+                uint64_t reserved_35_63:29;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_6_15:10;
+                uint64_t pp_dis:6;
+        } cn63xx;
+        struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_fus_dat3 {
         uint64_t u64;
         struct cvmx_mio_fus_dat3_s {
-                uint64_t reserved_32_63:32;
+                uint64_t reserved_58_63:6;
+                uint64_t pll_ctl:10;
+                uint64_t dfa_info_dte:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t reserved_40_40:1;
+                uint64_t ema:2;
+                uint64_t efus_lck_rsv:1;
+                uint64_t efus_lck_man:1;
+                uint64_t pll_half_dis:1;
+                uint64_t l2c_crip:3;
                 uint64_t pll_div4:1;
-                uint64_t zip_crip:2;
+                uint64_t reserved_29_30:2;
                 uint64_t bar2_en:1;
                 uint64_t efus_lck:1;
                 uint64_t efus_ign:1;
@@ -801,7 +797,17 @@ union cvmx_mio_fus_dat3 {
                 uint64_t nodfa_dte:1;
                 uint64_t icache:24;
         } cn30xx;
-        struct cvmx_mio_fus_dat3_s cn31xx;
+        struct cvmx_mio_fus_dat3_cn31xx {
+                uint64_t reserved_32_63:32;
+                uint64_t pll_div4:1;
+                uint64_t zip_crip:2;
+                uint64_t bar2_en:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t icache:24;
+        } cn31xx;
         struct cvmx_mio_fus_dat3_cn38xx {
                 uint64_t reserved_31_63:33;
                 uint64_t zip_crip:2;
@@ -828,6 +834,27 @@ union cvmx_mio_fus_dat3 {
         struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
         struct cvmx_mio_fus_dat3_cn38xx cn58xx;
         struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
+        struct cvmx_mio_fus_dat3_cn63xx {
+                uint64_t reserved_58_63:6;
+                uint64_t pll_ctl:10;
+                uint64_t dfa_info_dte:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t reserved_40_40:1;
+                uint64_t ema:2;
+                uint64_t efus_lck_rsv:1;
+                uint64_t efus_lck_man:1;
+                uint64_t pll_half_dis:1;
+                uint64_t l2c_crip:3;
+                uint64_t reserved_31_31:1;
+                uint64_t zip_info:2;
+                uint64_t bar2_en:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t reserved_0_23:24;
+        } cn63xx;
+        struct cvmx_mio_fus_dat3_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_fus_ema {
@@ -848,6 +875,8 @@ union cvmx_mio_fus_ema {
                 uint64_t ema:2;
         } cn58xx;
         struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
+        struct cvmx_mio_fus_ema_s cn63xx;
+        struct cvmx_mio_fus_ema_s cn63xxp1;
 };
 
 union cvmx_mio_fus_pdf {
@@ -861,60 +890,96 @@ union cvmx_mio_fus_pdf {
         struct cvmx_mio_fus_pdf_s cn56xx;
         struct cvmx_mio_fus_pdf_s cn56xxp1;
         struct cvmx_mio_fus_pdf_s cn58xx;
+        struct cvmx_mio_fus_pdf_s cn63xx;
+        struct cvmx_mio_fus_pdf_s cn63xxp1;
 };
 
 union cvmx_mio_fus_pll {
         uint64_t u64;
         struct cvmx_mio_fus_pll_s {
-                uint64_t reserved_2_63:62;
+                uint64_t reserved_8_63:56;
+                uint64_t c_cout_rst:1;
+                uint64_t c_cout_sel:2;
+                uint64_t pnr_cout_rst:1;
+                uint64_t pnr_cout_sel:2;
                 uint64_t rfslip:1;
                 uint64_t fbslip:1;
         } s;
-        struct cvmx_mio_fus_pll_s cn50xx;
-        struct cvmx_mio_fus_pll_s cn52xx;
-        struct cvmx_mio_fus_pll_s cn52xxp1;
-        struct cvmx_mio_fus_pll_s cn56xx;
-        struct cvmx_mio_fus_pll_s cn56xxp1;
-        struct cvmx_mio_fus_pll_s cn58xx;
-        struct cvmx_mio_fus_pll_s cn58xxp1;
+        struct cvmx_mio_fus_pll_cn50xx {
+                uint64_t reserved_2_63:62;
+                uint64_t rfslip:1;
+                uint64_t fbslip:1;
+        } cn50xx;
+        struct cvmx_mio_fus_pll_cn50xx cn52xx;
+        struct cvmx_mio_fus_pll_cn50xx cn52xxp1;
+        struct cvmx_mio_fus_pll_cn50xx cn56xx;
+        struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
+        struct cvmx_mio_fus_pll_cn50xx cn58xx;
+        struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
+        struct cvmx_mio_fus_pll_s cn63xx;
+        struct cvmx_mio_fus_pll_s cn63xxp1;
 };
 
 union cvmx_mio_fus_prog {
         uint64_t u64;
         struct cvmx_mio_fus_prog_s {
-                uint64_t reserved_1_63:63;
+                uint64_t reserved_2_63:62;
+                uint64_t soft:1;
                 uint64_t prog:1;
         } s;
-        struct cvmx_mio_fus_prog_s cn30xx;
-        struct cvmx_mio_fus_prog_s cn31xx;
-        struct cvmx_mio_fus_prog_s cn38xx;
-        struct cvmx_mio_fus_prog_s cn38xxp2;
-        struct cvmx_mio_fus_prog_s cn50xx;
-        struct cvmx_mio_fus_prog_s cn52xx;
-        struct cvmx_mio_fus_prog_s cn52xxp1;
-        struct cvmx_mio_fus_prog_s cn56xx;
-        struct cvmx_mio_fus_prog_s cn56xxp1;
-        struct cvmx_mio_fus_prog_s cn58xx;
-        struct cvmx_mio_fus_prog_s cn58xxp1;
+        struct cvmx_mio_fus_prog_cn30xx {
+                uint64_t reserved_1_63:63;
+                uint64_t prog:1;
+        } cn30xx;
+        struct cvmx_mio_fus_prog_cn30xx cn31xx;
+        struct cvmx_mio_fus_prog_cn30xx cn38xx;
+        struct cvmx_mio_fus_prog_cn30xx cn38xxp2;
+        struct cvmx_mio_fus_prog_cn30xx cn50xx;
+        struct cvmx_mio_fus_prog_cn30xx cn52xx;
+        struct cvmx_mio_fus_prog_cn30xx cn52xxp1;
+        struct cvmx_mio_fus_prog_cn30xx cn56xx;
+        struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
+        struct cvmx_mio_fus_prog_cn30xx cn58xx;
+        struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
+        struct cvmx_mio_fus_prog_s cn63xx;
+        struct cvmx_mio_fus_prog_s cn63xxp1;
 };
 
 union cvmx_mio_fus_prog_times {
         uint64_t u64;
         struct cvmx_mio_fus_prog_times_s {
+                uint64_t reserved_35_63:29;
+                uint64_t vgate_pin:1;
+                uint64_t fsrc_pin:1;
+                uint64_t prog_pin:1;
+                uint64_t reserved_6_31:26;
+                uint64_t setup:6;
+        } s;
+        struct cvmx_mio_fus_prog_times_cn50xx {
                 uint64_t reserved_33_63:31;
                 uint64_t prog_pin:1;
                 uint64_t out:8;
                 uint64_t sclk_lo:4;
                 uint64_t sclk_hi:12;
                 uint64_t setup:8;
-        } s;
-        struct cvmx_mio_fus_prog_times_s cn50xx;
-        struct cvmx_mio_fus_prog_times_s cn52xx;
-        struct cvmx_mio_fus_prog_times_s cn52xxp1;
-        struct cvmx_mio_fus_prog_times_s cn56xx;
-        struct cvmx_mio_fus_prog_times_s cn56xxp1;
-        struct cvmx_mio_fus_prog_times_s cn58xx;
-        struct cvmx_mio_fus_prog_times_s cn58xxp1;
+        } cn50xx;
+        struct cvmx_mio_fus_prog_times_cn50xx cn52xx;
+        struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1;
+        struct cvmx_mio_fus_prog_times_cn50xx cn56xx;
+        struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
+        struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
+        struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
+        struct cvmx_mio_fus_prog_times_cn63xx {
+                uint64_t reserved_35_63:29;
+                uint64_t vgate_pin:1;
+                uint64_t fsrc_pin:1;
+                uint64_t prog_pin:1;
+                uint64_t out:7;
+                uint64_t sclk_lo:4;
+                uint64_t sclk_hi:15;
+                uint64_t setup:6;
+        } cn63xx;
+        struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_fus_rcmd {
@@ -948,6 +1013,57 @@ union cvmx_mio_fus_rcmd {
         struct cvmx_mio_fus_rcmd_s cn56xxp1;
         struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
         struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
+        struct cvmx_mio_fus_rcmd_s cn63xx;
+        struct cvmx_mio_fus_rcmd_s cn63xxp1;
+};
+
+union cvmx_mio_fus_read_times {
+        uint64_t u64;
+        struct cvmx_mio_fus_read_times_s {
+                uint64_t reserved_26_63:38;
+                uint64_t sch:4;
+                uint64_t fsh:4;
+                uint64_t prh:4;
+                uint64_t sdh:4;
+                uint64_t setup:10;
+        } s;
+        struct cvmx_mio_fus_read_times_s cn63xx;
+        struct cvmx_mio_fus_read_times_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res0 {
+        uint64_t u64;
+        struct cvmx_mio_fus_repair_res0_s {
+                uint64_t reserved_55_63:9;
+                uint64_t too_many:1;
+                uint64_t repair2:18;
+                uint64_t repair1:18;
+                uint64_t repair0:18;
+        } s;
+        struct cvmx_mio_fus_repair_res0_s cn63xx;
+        struct cvmx_mio_fus_repair_res0_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res1 {
+        uint64_t u64;
+        struct cvmx_mio_fus_repair_res1_s {
+                uint64_t reserved_54_63:10;
+                uint64_t repair5:18;
+                uint64_t repair4:18;
+                uint64_t repair3:18;
+        } s;
+        struct cvmx_mio_fus_repair_res1_s cn63xx;
+        struct cvmx_mio_fus_repair_res1_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res2 {
+        uint64_t u64;
+        struct cvmx_mio_fus_repair_res2_s {
+                uint64_t reserved_18_63:46;
+                uint64_t repair6:18;
+        } s;
+        struct cvmx_mio_fus_repair_res2_s cn63xx;
+        struct cvmx_mio_fus_repair_res2_s cn63xxp1;
 };
 
 union cvmx_mio_fus_spr_repair_res {
@@ -968,6 +1084,8 @@ union cvmx_mio_fus_spr_repair_res {
         struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
         struct cvmx_mio_fus_spr_repair_res_s cn58xx;
         struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
+        struct cvmx_mio_fus_spr_repair_res_s cn63xx;
+        struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
 };
 
 union cvmx_mio_fus_spr_repair_sum {
@@ -986,6 +1104,8 @@ union cvmx_mio_fus_spr_repair_sum {
         struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
         struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
+        struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
+        struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
 };
 
 union cvmx_mio_fus_unlock {
@@ -1021,6 +1141,22 @@ union cvmx_mio_fus_wadr {
         struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
         struct cvmx_mio_fus_wadr_cn50xx cn58xx;
         struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
+        struct cvmx_mio_fus_wadr_cn63xx {
+                uint64_t reserved_4_63:60;
+                uint64_t addr:4;
+        } cn63xx;
+        struct cvmx_mio_fus_wadr_cn63xx cn63xxp1;
+};
+
+union cvmx_mio_gpio_comp {
+        uint64_t u64;
+        struct cvmx_mio_gpio_comp_s {
+                uint64_t reserved_12_63:52;
+                uint64_t pctl:6;
+                uint64_t nctl:6;
+        } s;
+        struct cvmx_mio_gpio_comp_s cn63xx;
+        struct cvmx_mio_gpio_comp_s cn63xxp1;
 };
 
 union cvmx_mio_ndf_dma_cfg {
@@ -1038,6 +1174,8 @@ union cvmx_mio_ndf_dma_cfg {
                 uint64_t adr:36;
         } s;
         struct cvmx_mio_ndf_dma_cfg_s cn52xx;
+        struct cvmx_mio_ndf_dma_cfg_s cn63xx;
+        struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
 };
 
 union cvmx_mio_ndf_dma_int {
@@ -1047,6 +1185,8 @@ union cvmx_mio_ndf_dma_int {
                 uint64_t done:1;
         } s;
         struct cvmx_mio_ndf_dma_int_s cn52xx;
+        struct cvmx_mio_ndf_dma_int_s cn63xx;
+        struct cvmx_mio_ndf_dma_int_s cn63xxp1;
 };
 
 union cvmx_mio_ndf_dma_int_en {
@@ -1056,6 +1196,8 @@ union cvmx_mio_ndf_dma_int_en {
                 uint64_t done:1;
         } s;
         struct cvmx_mio_ndf_dma_int_en_s cn52xx;
+        struct cvmx_mio_ndf_dma_int_en_s cn63xx;
+        struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
 };
 
 union cvmx_mio_pll_ctl {
@@ -1078,6 +1220,173 @@ union cvmx_mio_pll_setting {
         struct cvmx_mio_pll_setting_s cn31xx;
 };
 
+union cvmx_mio_ptp_clock_cfg {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_cfg_s {
+                uint64_t reserved_24_63:40;
+                uint64_t evcnt_in:6;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_en:1;
+                uint64_t tstmp_in:6;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t ext_clk_en:1;
+                uint64_t ptp_en:1;
+        } s;
+        struct cvmx_mio_ptp_clock_cfg_s cn63xx;
+        struct cvmx_mio_ptp_clock_cfg_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_comp {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_comp_s {
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_clock_comp_s cn63xx;
+        struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_hi {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_hi_s {
+                uint64_t nanosec:64;
+        } s;
+        struct cvmx_mio_ptp_clock_hi_s cn63xx;
+        struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_lo {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_lo_s {
+                uint64_t reserved_32_63:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_clock_lo_s cn63xx;
+        struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_evt_cnt {
+        uint64_t u64;
+        struct cvmx_mio_ptp_evt_cnt_s {
+                uint64_t cntr:64;
+        } s;
+        struct cvmx_mio_ptp_evt_cnt_s cn63xx;
+        struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_timestamp {
+        uint64_t u64;
+        struct cvmx_mio_ptp_timestamp_s {
+                uint64_t nanosec:64;
+        } s;
+        struct cvmx_mio_ptp_timestamp_s cn63xx;
+        struct cvmx_mio_ptp_timestamp_s cn63xxp1;
+};
+
+union cvmx_mio_rst_boot {
+        uint64_t u64;
+        struct cvmx_mio_rst_boot_s {
+                uint64_t reserved_36_63:28;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } s;
+        struct cvmx_mio_rst_boot_s cn63xx;
+        struct cvmx_mio_rst_boot_s cn63xxp1;
+};
+
+union cvmx_mio_rst_cfg {
+        uint64_t u64;
+        struct cvmx_mio_rst_cfg_s {
+                uint64_t bist_delay:58;
+                uint64_t reserved_3_5:3;
+                uint64_t cntl_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+        } s;
+        struct cvmx_mio_rst_cfg_s cn63xx;
+        struct cvmx_mio_rst_cfg_cn63xxp1 {
+                uint64_t bist_delay:58;
+                uint64_t reserved_2_5:4;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+        } cn63xxp1;
+};
+
+union cvmx_mio_rst_ctlx {
+        uint64_t u64;
+        struct cvmx_mio_rst_ctlx_s {
+                uint64_t reserved_10_63:54;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+        } s;
+        struct cvmx_mio_rst_ctlx_s cn63xx;
+        struct cvmx_mio_rst_ctlx_cn63xxp1 {
+                uint64_t reserved_9_63:55;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+        } cn63xxp1;
+};
+
+union cvmx_mio_rst_delay {
+        uint64_t u64;
+        struct cvmx_mio_rst_delay_s {
+                uint64_t reserved_32_63:32;
+                uint64_t soft_rst_dly:16;
+                uint64_t warm_rst_dly:16;
+        } s;
+        struct cvmx_mio_rst_delay_s cn63xx;
+        struct cvmx_mio_rst_delay_s cn63xxp1;
+};
+
+union cvmx_mio_rst_int {
+        uint64_t u64;
+        struct cvmx_mio_rst_int_s {
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_2_7:6;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+        } s;
+        struct cvmx_mio_rst_int_s cn63xx;
+        struct cvmx_mio_rst_int_s cn63xxp1;
+};
+
+union cvmx_mio_rst_int_en {
+        uint64_t u64;
+        struct cvmx_mio_rst_int_en_s {
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_2_7:6;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+        } s;
+        struct cvmx_mio_rst_int_en_s cn63xx;
+        struct cvmx_mio_rst_int_en_s cn63xxp1;
+};
+
 union cvmx_mio_twsx_int {
         uint64_t u64;
         struct cvmx_mio_twsx_int_s {
@@ -1115,6 +1424,8 @@ union cvmx_mio_twsx_int {
         struct cvmx_mio_twsx_int_s cn56xxp1;
         struct cvmx_mio_twsx_int_s cn58xx;
         struct cvmx_mio_twsx_int_s cn58xxp1;
+        struct cvmx_mio_twsx_int_s cn63xx;
+        struct cvmx_mio_twsx_int_s cn63xxp1;
 };
 
 union cvmx_mio_twsx_sw_twsi {
@@ -1144,6 +1455,8 @@ union cvmx_mio_twsx_sw_twsi {
         struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
         struct cvmx_mio_twsx_sw_twsi_s cn58xx;
         struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
+        struct cvmx_mio_twsx_sw_twsi_s cn63xx;
+        struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
 };
 
 union cvmx_mio_twsx_sw_twsi_ext {
@@ -1164,6 +1477,8 @@ union cvmx_mio_twsx_sw_twsi_ext {
         struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
 };
 
 union cvmx_mio_twsx_twsi_sw {
@@ -1184,6 +1499,8 @@ union cvmx_mio_twsx_twsi_sw {
         struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
         struct cvmx_mio_twsx_twsi_sw_s cn58xx;
         struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
+        struct cvmx_mio_twsx_twsi_sw_s cn63xx;
+        struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_dlh {
@@ -1203,6 +1520,8 @@ union cvmx_mio_uartx_dlh {
         struct cvmx_mio_uartx_dlh_s cn56xxp1;
         struct cvmx_mio_uartx_dlh_s cn58xx;
         struct cvmx_mio_uartx_dlh_s cn58xxp1;
+        struct cvmx_mio_uartx_dlh_s cn63xx;
+        struct cvmx_mio_uartx_dlh_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_dll {
@@ -1222,6 +1541,8 @@ union cvmx_mio_uartx_dll {
         struct cvmx_mio_uartx_dll_s cn56xxp1;
         struct cvmx_mio_uartx_dll_s cn58xx;
         struct cvmx_mio_uartx_dll_s cn58xxp1;
+        struct cvmx_mio_uartx_dll_s cn63xx;
+        struct cvmx_mio_uartx_dll_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_far {
@@ -1241,6 +1562,8 @@ union cvmx_mio_uartx_far {
         struct cvmx_mio_uartx_far_s cn56xxp1;
         struct cvmx_mio_uartx_far_s cn58xx;
         struct cvmx_mio_uartx_far_s cn58xxp1;
+        struct cvmx_mio_uartx_far_s cn63xx;
+        struct cvmx_mio_uartx_far_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_fcr {
@@ -1265,6 +1588,8 @@ union cvmx_mio_uartx_fcr {
         struct cvmx_mio_uartx_fcr_s cn56xxp1;
         struct cvmx_mio_uartx_fcr_s cn58xx;
         struct cvmx_mio_uartx_fcr_s cn58xxp1;
+        struct cvmx_mio_uartx_fcr_s cn63xx;
+        struct cvmx_mio_uartx_fcr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_htx {
@@ -1284,6 +1609,8 @@ union cvmx_mio_uartx_htx {
         struct cvmx_mio_uartx_htx_s cn56xxp1;
         struct cvmx_mio_uartx_htx_s cn58xx;
         struct cvmx_mio_uartx_htx_s cn58xxp1;
+        struct cvmx_mio_uartx_htx_s cn63xx;
+        struct cvmx_mio_uartx_htx_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_ier {
@@ -1308,6 +1635,8 @@ union cvmx_mio_uartx_ier {
         struct cvmx_mio_uartx_ier_s cn56xxp1;
         struct cvmx_mio_uartx_ier_s cn58xx;
         struct cvmx_mio_uartx_ier_s cn58xxp1;
+        struct cvmx_mio_uartx_ier_s cn63xx;
+        struct cvmx_mio_uartx_ier_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_iir {
@@ -1329,6 +1658,8 @@ union cvmx_mio_uartx_iir {
         struct cvmx_mio_uartx_iir_s cn56xxp1;
         struct cvmx_mio_uartx_iir_s cn58xx;
         struct cvmx_mio_uartx_iir_s cn58xxp1;
+        struct cvmx_mio_uartx_iir_s cn63xx;
+        struct cvmx_mio_uartx_iir_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_lcr {
@@ -1354,6 +1685,8 @@ union cvmx_mio_uartx_lcr {
         struct cvmx_mio_uartx_lcr_s cn56xxp1;
         struct cvmx_mio_uartx_lcr_s cn58xx;
         struct cvmx_mio_uartx_lcr_s cn58xxp1;
+        struct cvmx_mio_uartx_lcr_s cn63xx;
+        struct cvmx_mio_uartx_lcr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_lsr {
@@ -1380,6 +1713,8 @@ union cvmx_mio_uartx_lsr {
         struct cvmx_mio_uartx_lsr_s cn56xxp1;
         struct cvmx_mio_uartx_lsr_s cn58xx;
         struct cvmx_mio_uartx_lsr_s cn58xxp1;
+        struct cvmx_mio_uartx_lsr_s cn63xx;
+        struct cvmx_mio_uartx_lsr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_mcr {
@@ -1404,6 +1739,8 @@ union cvmx_mio_uartx_mcr {
         struct cvmx_mio_uartx_mcr_s cn56xxp1;
         struct cvmx_mio_uartx_mcr_s cn58xx;
         struct cvmx_mio_uartx_mcr_s cn58xxp1;
+        struct cvmx_mio_uartx_mcr_s cn63xx;
+        struct cvmx_mio_uartx_mcr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_msr {
@@ -1430,6 +1767,8 @@ union cvmx_mio_uartx_msr {
         struct cvmx_mio_uartx_msr_s cn56xxp1;
         struct cvmx_mio_uartx_msr_s cn58xx;
         struct cvmx_mio_uartx_msr_s cn58xxp1;
+        struct cvmx_mio_uartx_msr_s cn63xx;
+        struct cvmx_mio_uartx_msr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_rbr {
@@ -1449,6 +1788,8 @@ union cvmx_mio_uartx_rbr {
         struct cvmx_mio_uartx_rbr_s cn56xxp1;
         struct cvmx_mio_uartx_rbr_s cn58xx;
         struct cvmx_mio_uartx_rbr_s cn58xxp1;
+        struct cvmx_mio_uartx_rbr_s cn63xx;
+        struct cvmx_mio_uartx_rbr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_rfl {
@@ -1468,6 +1809,8 @@ union cvmx_mio_uartx_rfl {
         struct cvmx_mio_uartx_rfl_s cn56xxp1;
         struct cvmx_mio_uartx_rfl_s cn58xx;
         struct cvmx_mio_uartx_rfl_s cn58xxp1;
+        struct cvmx_mio_uartx_rfl_s cn63xx;
+        struct cvmx_mio_uartx_rfl_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_rfw {
@@ -1489,6 +1832,8 @@ union cvmx_mio_uartx_rfw {
         struct cvmx_mio_uartx_rfw_s cn56xxp1;
         struct cvmx_mio_uartx_rfw_s cn58xx;
         struct cvmx_mio_uartx_rfw_s cn58xxp1;
+        struct cvmx_mio_uartx_rfw_s cn63xx;
+        struct cvmx_mio_uartx_rfw_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_sbcr {
@@ -1508,6 +1853,8 @@ union cvmx_mio_uartx_sbcr {
         struct cvmx_mio_uartx_sbcr_s cn56xxp1;
         struct cvmx_mio_uartx_sbcr_s cn58xx;
         struct cvmx_mio_uartx_sbcr_s cn58xxp1;
+        struct cvmx_mio_uartx_sbcr_s cn63xx;
+        struct cvmx_mio_uartx_sbcr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_scr {
@@ -1527,6 +1874,8 @@ union cvmx_mio_uartx_scr {
         struct cvmx_mio_uartx_scr_s cn56xxp1;
         struct cvmx_mio_uartx_scr_s cn58xx;
         struct cvmx_mio_uartx_scr_s cn58xxp1;
+        struct cvmx_mio_uartx_scr_s cn63xx;
+        struct cvmx_mio_uartx_scr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_sfe {
@@ -1546,6 +1895,8 @@ union cvmx_mio_uartx_sfe {
         struct cvmx_mio_uartx_sfe_s cn56xxp1;
         struct cvmx_mio_uartx_sfe_s cn58xx;
         struct cvmx_mio_uartx_sfe_s cn58xxp1;
+        struct cvmx_mio_uartx_sfe_s cn63xx;
+        struct cvmx_mio_uartx_sfe_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_srr {
@@ -1567,6 +1918,8 @@ union cvmx_mio_uartx_srr {
         struct cvmx_mio_uartx_srr_s cn56xxp1;
         struct cvmx_mio_uartx_srr_s cn58xx;
         struct cvmx_mio_uartx_srr_s cn58xxp1;
+        struct cvmx_mio_uartx_srr_s cn63xx;
+        struct cvmx_mio_uartx_srr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_srt {
@@ -1586,6 +1939,8 @@ union cvmx_mio_uartx_srt {
         struct cvmx_mio_uartx_srt_s cn56xxp1;
         struct cvmx_mio_uartx_srt_s cn58xx;
         struct cvmx_mio_uartx_srt_s cn58xxp1;
+        struct cvmx_mio_uartx_srt_s cn63xx;
+        struct cvmx_mio_uartx_srt_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_srts {
@@ -1605,6 +1960,8 @@ union cvmx_mio_uartx_srts {
         struct cvmx_mio_uartx_srts_s cn56xxp1;
         struct cvmx_mio_uartx_srts_s cn58xx;
         struct cvmx_mio_uartx_srts_s cn58xxp1;
+        struct cvmx_mio_uartx_srts_s cn63xx;
+        struct cvmx_mio_uartx_srts_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_stt {
@@ -1624,6 +1981,8 @@ union cvmx_mio_uartx_stt {
         struct cvmx_mio_uartx_stt_s cn56xxp1;
         struct cvmx_mio_uartx_stt_s cn58xx;
         struct cvmx_mio_uartx_stt_s cn58xxp1;
+        struct cvmx_mio_uartx_stt_s cn63xx;
+        struct cvmx_mio_uartx_stt_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_tfl {
@@ -1643,6 +2002,8 @@ union cvmx_mio_uartx_tfl {
         struct cvmx_mio_uartx_tfl_s cn56xxp1;
         struct cvmx_mio_uartx_tfl_s cn58xx;
         struct cvmx_mio_uartx_tfl_s cn58xxp1;
+        struct cvmx_mio_uartx_tfl_s cn63xx;
+        struct cvmx_mio_uartx_tfl_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_tfr {
@@ -1662,6 +2023,8 @@ union cvmx_mio_uartx_tfr {
         struct cvmx_mio_uartx_tfr_s cn56xxp1;
         struct cvmx_mio_uartx_tfr_s cn58xx;
         struct cvmx_mio_uartx_tfr_s cn58xxp1;
+        struct cvmx_mio_uartx_tfr_s cn63xx;
+        struct cvmx_mio_uartx_tfr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_thr {
@@ -1681,6 +2044,8 @@ union cvmx_mio_uartx_thr {
         struct cvmx_mio_uartx_thr_s cn56xxp1;
         struct cvmx_mio_uartx_thr_s cn58xx;
         struct cvmx_mio_uartx_thr_s cn58xxp1;
+        struct cvmx_mio_uartx_thr_s cn63xx;
+        struct cvmx_mio_uartx_thr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_usr {
@@ -1704,6 +2069,8 @@ union cvmx_mio_uartx_usr {
         struct cvmx_mio_uartx_usr_s cn56xxp1;
         struct cvmx_mio_uartx_usr_s cn58xx;
         struct cvmx_mio_uartx_usr_s cn58xxp1;
+        struct cvmx_mio_uartx_usr_s cn63xx;
+        struct cvmx_mio_uartx_usr_s cn63xxp1;
 };
 
 union cvmx_mio_uart2_dlh {
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
index dab6dca492f9..7057c447e69e 100644
--- a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,52 +28,52 @@
 #ifndef __CVMX_MIXX_DEFS_H__
 #define __CVMX_MIXX_DEFS_H__
 
-#define CVMX_MIXX_BIST(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_INTENA(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRCNT(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRHWM(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRING1(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRING2(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ISR(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORCNT(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORHWM(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORING1(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORING2(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_REMCNT(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
 
 union cvmx_mixx_bist {
         uint64_t u64;
         struct cvmx_mixx_bist_s {
-                uint64_t reserved_4_63:60;
+                uint64_t reserved_6_63:58;
+                uint64_t opfdat:1;
+                uint64_t mrgdat:1;
                 uint64_t mrqdat:1;
                 uint64_t ipfdat:1;
                 uint64_t irfdat:1;
                 uint64_t orfdat:1;
         } s;
-        struct cvmx_mixx_bist_s cn52xx;
-        struct cvmx_mixx_bist_s cn52xxp1;
-        struct cvmx_mixx_bist_s cn56xx;
-        struct cvmx_mixx_bist_s cn56xxp1;
+        struct cvmx_mixx_bist_cn52xx {
+                uint64_t reserved_4_63:60;
+                uint64_t mrqdat:1;
+                uint64_t ipfdat:1;
+                uint64_t irfdat:1;
+                uint64_t orfdat:1;
+        } cn52xx;
+        struct cvmx_mixx_bist_cn52xx cn52xxp1;
+        struct cvmx_mixx_bist_cn52xx cn56xx;
+        struct cvmx_mixx_bist_cn52xx cn56xxp1;
+        struct cvmx_mixx_bist_s cn63xx;
+        struct cvmx_mixx_bist_s cn63xxp1;
 };
 
 union cvmx_mixx_ctl {
         uint64_t u64;
         struct cvmx_mixx_ctl_s {
-                uint64_t reserved_8_63:56;
+                uint64_t reserved_12_63:52;
+                uint64_t ts_thresh:4;
                 uint64_t crc_strip:1;
                 uint64_t busy:1;
                 uint64_t en:1;
@@ -82,16 +82,28 @@ union cvmx_mixx_ctl {
                 uint64_t nbtarb:1;
                 uint64_t mrq_hwm:2;
         } s;
-        struct cvmx_mixx_ctl_s cn52xx;
-        struct cvmx_mixx_ctl_s cn52xxp1;
-        struct cvmx_mixx_ctl_s cn56xx;
-        struct cvmx_mixx_ctl_s cn56xxp1;
+        struct cvmx_mixx_ctl_cn52xx {
+                uint64_t reserved_8_63:56;
+                uint64_t crc_strip:1;
+                uint64_t busy:1;
+                uint64_t en:1;
+                uint64_t reset:1;
+                uint64_t lendian:1;
+                uint64_t nbtarb:1;
+                uint64_t mrq_hwm:2;
+        } cn52xx;
+        struct cvmx_mixx_ctl_cn52xx cn52xxp1;
+        struct cvmx_mixx_ctl_cn52xx cn56xx;
+        struct cvmx_mixx_ctl_cn52xx cn56xxp1;
+        struct cvmx_mixx_ctl_s cn63xx;
+        struct cvmx_mixx_ctl_s cn63xxp1;
 };
 
 union cvmx_mixx_intena {
         uint64_t u64;
         struct cvmx_mixx_intena_s {
-                uint64_t reserved_7_63:57;
+                uint64_t reserved_8_63:56;
+                uint64_t tsena:1;
                 uint64_t orunena:1;
                 uint64_t irunena:1;
                 uint64_t data_drpena:1;
@@ -100,10 +112,21 @@ union cvmx_mixx_intena {
                 uint64_t ivfena:1;
                 uint64_t ovfena:1;
         } s;
-        struct cvmx_mixx_intena_s cn52xx;
-        struct cvmx_mixx_intena_s cn52xxp1;
-        struct cvmx_mixx_intena_s cn56xx;
-        struct cvmx_mixx_intena_s cn56xxp1;
+        struct cvmx_mixx_intena_cn52xx {
+                uint64_t reserved_7_63:57;
+                uint64_t orunena:1;
+                uint64_t irunena:1;
+                uint64_t data_drpena:1;
+                uint64_t ithena:1;
+                uint64_t othena:1;
+                uint64_t ivfena:1;
+                uint64_t ovfena:1;
+        } cn52xx;
+        struct cvmx_mixx_intena_cn52xx cn52xxp1;
+        struct cvmx_mixx_intena_cn52xx cn56xx;
+        struct cvmx_mixx_intena_cn52xx cn56xxp1;
+        struct cvmx_mixx_intena_s cn63xx;
+        struct cvmx_mixx_intena_s cn63xxp1;
 };
 
 union cvmx_mixx_ircnt {
@@ -116,6 +139,8 @@ union cvmx_mixx_ircnt {
         struct cvmx_mixx_ircnt_s cn52xxp1;
         struct cvmx_mixx_ircnt_s cn56xx;
         struct cvmx_mixx_ircnt_s cn56xxp1;
+        struct cvmx_mixx_ircnt_s cn63xx;
+        struct cvmx_mixx_ircnt_s cn63xxp1;
 };
 
 union cvmx_mixx_irhwm {
@@ -129,6 +154,8 @@ union cvmx_mixx_irhwm {
         struct cvmx_mixx_irhwm_s cn52xxp1;
         struct cvmx_mixx_irhwm_s cn56xx;
         struct cvmx_mixx_irhwm_s cn56xxp1;
+        struct cvmx_mixx_irhwm_s cn63xx;
+        struct cvmx_mixx_irhwm_s cn63xxp1;
 };
 
 union cvmx_mixx_iring1 {
@@ -136,14 +163,21 @@ union cvmx_mixx_iring1 {
         struct cvmx_mixx_iring1_s {
                 uint64_t reserved_60_63:4;
                 uint64_t isize:20;
+                uint64_t ibase:37;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_mixx_iring1_cn52xx {
+                uint64_t reserved_60_63:4;
+                uint64_t isize:20;
                 uint64_t reserved_36_39:4;
                 uint64_t ibase:33;
                 uint64_t reserved_0_2:3;
-        } s;
-        struct cvmx_mixx_iring1_s cn52xx;
-        struct cvmx_mixx_iring1_s cn52xxp1;
-        struct cvmx_mixx_iring1_s cn56xx;
-        struct cvmx_mixx_iring1_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_mixx_iring1_cn52xx cn52xxp1;
+        struct cvmx_mixx_iring1_cn52xx cn56xx;
+        struct cvmx_mixx_iring1_cn52xx cn56xxp1;
+        struct cvmx_mixx_iring1_s cn63xx;
+        struct cvmx_mixx_iring1_s cn63xxp1;
 };
 
 union cvmx_mixx_iring2 {
@@ -158,12 +192,15 @@ union cvmx_mixx_iring2 {
         struct cvmx_mixx_iring2_s cn52xxp1;
         struct cvmx_mixx_iring2_s cn56xx;
         struct cvmx_mixx_iring2_s cn56xxp1;
+        struct cvmx_mixx_iring2_s cn63xx;
+        struct cvmx_mixx_iring2_s cn63xxp1;
 };
 
 union cvmx_mixx_isr {
         uint64_t u64;
         struct cvmx_mixx_isr_s {
-                uint64_t reserved_7_63:57;
+                uint64_t reserved_8_63:56;
+                uint64_t ts:1;
                 uint64_t orun:1;
                 uint64_t irun:1;
                 uint64_t data_drp:1;
@@ -172,10 +209,21 @@ union cvmx_mixx_isr {
                 uint64_t idblovf:1;
                 uint64_t odblovf:1;
         } s;
-        struct cvmx_mixx_isr_s cn52xx;
-        struct cvmx_mixx_isr_s cn52xxp1;
-        struct cvmx_mixx_isr_s cn56xx;
-        struct cvmx_mixx_isr_s cn56xxp1;
+        struct cvmx_mixx_isr_cn52xx {
+                uint64_t reserved_7_63:57;
+                uint64_t orun:1;
+                uint64_t irun:1;
+                uint64_t data_drp:1;
+                uint64_t irthresh:1;
+                uint64_t orthresh:1;
+                uint64_t idblovf:1;
+                uint64_t odblovf:1;
+        } cn52xx;
+        struct cvmx_mixx_isr_cn52xx cn52xxp1;
+        struct cvmx_mixx_isr_cn52xx cn56xx;
+        struct cvmx_mixx_isr_cn52xx cn56xxp1;
+        struct cvmx_mixx_isr_s cn63xx;
+        struct cvmx_mixx_isr_s cn63xxp1;
 };
 
 union cvmx_mixx_orcnt {
@@ -188,6 +236,8 @@ union cvmx_mixx_orcnt {
         struct cvmx_mixx_orcnt_s cn52xxp1;
         struct cvmx_mixx_orcnt_s cn56xx;
         struct cvmx_mixx_orcnt_s cn56xxp1;
+        struct cvmx_mixx_orcnt_s cn63xx;
+        struct cvmx_mixx_orcnt_s cn63xxp1;
 };
 
 union cvmx_mixx_orhwm {
@@ -200,6 +250,8 @@ union cvmx_mixx_orhwm {
         struct cvmx_mixx_orhwm_s cn52xxp1;
         struct cvmx_mixx_orhwm_s cn56xx;
         struct cvmx_mixx_orhwm_s cn56xxp1;
+        struct cvmx_mixx_orhwm_s cn63xx;
+        struct cvmx_mixx_orhwm_s cn63xxp1;
 };
 
 union cvmx_mixx_oring1 {
@@ -207,14 +259,21 @@ union cvmx_mixx_oring1 {
         struct cvmx_mixx_oring1_s {
                 uint64_t reserved_60_63:4;
                 uint64_t osize:20;
+                uint64_t obase:37;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_mixx_oring1_cn52xx {
+                uint64_t reserved_60_63:4;
+                uint64_t osize:20;
                 uint64_t reserved_36_39:4;
                 uint64_t obase:33;
                 uint64_t reserved_0_2:3;
-        } s;
-        struct cvmx_mixx_oring1_s cn52xx;
-        struct cvmx_mixx_oring1_s cn52xxp1;
-        struct cvmx_mixx_oring1_s cn56xx;
-        struct cvmx_mixx_oring1_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_mixx_oring1_cn52xx cn52xxp1;
+        struct cvmx_mixx_oring1_cn52xx cn56xx;
+        struct cvmx_mixx_oring1_cn52xx cn56xxp1;
+        struct cvmx_mixx_oring1_s cn63xx;
+        struct cvmx_mixx_oring1_s cn63xxp1;
 };
 
 union cvmx_mixx_oring2 {
@@ -229,6 +288,8 @@ union cvmx_mixx_oring2 {
         struct cvmx_mixx_oring2_s cn52xxp1;
         struct cvmx_mixx_oring2_s cn56xx;
         struct cvmx_mixx_oring2_s cn56xxp1;
+        struct cvmx_mixx_oring2_s cn63xx;
+        struct cvmx_mixx_oring2_s cn63xxp1;
 };
 
 union cvmx_mixx_remcnt {
@@ -243,6 +304,31 @@ union cvmx_mixx_remcnt {
         struct cvmx_mixx_remcnt_s cn52xxp1;
         struct cvmx_mixx_remcnt_s cn56xx;
         struct cvmx_mixx_remcnt_s cn56xxp1;
+        struct cvmx_mixx_remcnt_s cn63xx;
+        struct cvmx_mixx_remcnt_s cn63xxp1;
+};
+
+union cvmx_mixx_tsctl {
+        uint64_t u64;
+        struct cvmx_mixx_tsctl_s {
+                uint64_t reserved_21_63:43;
+                uint64_t tsavl:5;
+                uint64_t reserved_13_15:3;
+                uint64_t tstot:5;
+                uint64_t reserved_5_7:3;
+                uint64_t tscnt:5;
+        } s;
+        struct cvmx_mixx_tsctl_s cn63xx;
+        struct cvmx_mixx_tsctl_s cn63xxp1;
+};
+
+union cvmx_mixx_tstamp {
+        uint64_t u64;
+        struct cvmx_mixx_tstamp_s {
+                uint64_t tstamp:64;
+        } s;
+        struct cvmx_mixx_tstamp_s cn63xx;
+        struct cvmx_mixx_tstamp_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 4b347bb8ce80..9899a9d2ba72 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,206 +28,114 @@
 #ifndef __CVMX_NPEI_DEFS_H__
 #define __CVMX_NPEI_DEFS_H__
 
-#define CVMX_NPEI_BAR1_INDEXX(offset) \
-         (0x0000000000000000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_BIST_STATUS \
-         (0x0000000000000580ull)
-#define CVMX_NPEI_BIST_STATUS2 \
-         (0x0000000000000680ull)
-#define CVMX_NPEI_CTL_PORT0 \
-         (0x0000000000000250ull)
-#define CVMX_NPEI_CTL_PORT1 \
-         (0x0000000000000260ull)
-#define CVMX_NPEI_CTL_STATUS \
-         (0x0000000000000570ull)
-#define CVMX_NPEI_CTL_STATUS2 \
-         (0x0000000000003C00ull)
-#define CVMX_NPEI_DATA_OUT_CNT \
-         (0x00000000000005F0ull)
-#define CVMX_NPEI_DBG_DATA \
-         (0x0000000000000510ull)
-#define CVMX_NPEI_DBG_SELECT \
-         (0x0000000000000500ull)
-#define CVMX_NPEI_DMA0_INT_LEVEL \
-         (0x00000000000005C0ull)
-#define CVMX_NPEI_DMA1_INT_LEVEL \
-         (0x00000000000005D0ull)
-#define CVMX_NPEI_DMAX_COUNTS(offset) \
-         (0x0000000000000450ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_DBELL(offset) \
-         (0x00000000000003B0ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
-         (0x0000000000000400ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_NADDR(offset) \
-         (0x00000000000004A0ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMA_CNTS \
-         (0x00000000000005E0ull)
-#define CVMX_NPEI_DMA_CONTROL \
-         (0x00000000000003A0ull)
-#define CVMX_NPEI_INT_A_ENB \
-         (0x0000000000000560ull)
-#define CVMX_NPEI_INT_A_ENB2 \
-         (0x0000000000003CE0ull)
-#define CVMX_NPEI_INT_A_SUM \
-         (0x0000000000000550ull)
-#define CVMX_NPEI_INT_ENB \
-         (0x0000000000000540ull)
-#define CVMX_NPEI_INT_ENB2 \
-         (0x0000000000003CD0ull)
-#define CVMX_NPEI_INT_INFO \
-         (0x0000000000000590ull)
-#define CVMX_NPEI_INT_SUM \
-         (0x0000000000000530ull)
-#define CVMX_NPEI_INT_SUM2 \
-         (0x0000000000003CC0ull)
-#define CVMX_NPEI_LAST_WIN_RDATA0 \
-         (0x0000000000000600ull)
-#define CVMX_NPEI_LAST_WIN_RDATA1 \
-         (0x0000000000000610ull)
-#define CVMX_NPEI_MEM_ACCESS_CTL \
-         (0x00000000000004F0ull)
-#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
-         (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
-#define CVMX_NPEI_MSI_ENB0 \
-         (0x0000000000003C50ull)
-#define CVMX_NPEI_MSI_ENB1 \
-         (0x0000000000003C60ull)
-#define CVMX_NPEI_MSI_ENB2 \
-         (0x0000000000003C70ull)
-#define CVMX_NPEI_MSI_ENB3 \
-         (0x0000000000003C80ull)
-#define CVMX_NPEI_MSI_RCV0 \
-         (0x0000000000003C10ull)
-#define CVMX_NPEI_MSI_RCV1 \
-         (0x0000000000003C20ull)
-#define CVMX_NPEI_MSI_RCV2 \
-         (0x0000000000003C30ull)
-#define CVMX_NPEI_MSI_RCV3 \
-         (0x0000000000003C40ull)
-#define CVMX_NPEI_MSI_RD_MAP \
-         (0x0000000000003CA0ull)
-#define CVMX_NPEI_MSI_W1C_ENB0 \
-         (0x0000000000003CF0ull)
-#define CVMX_NPEI_MSI_W1C_ENB1 \
-         (0x0000000000003D00ull)
-#define CVMX_NPEI_MSI_W1C_ENB2 \
-         (0x0000000000003D10ull)
-#define CVMX_NPEI_MSI_W1C_ENB3 \
-         (0x0000000000003D20ull)
-#define CVMX_NPEI_MSI_W1S_ENB0 \
-         (0x0000000000003D30ull)
-#define CVMX_NPEI_MSI_W1S_ENB1 \
-         (0x0000000000003D40ull)
-#define CVMX_NPEI_MSI_W1S_ENB2 \
-         (0x0000000000003D50ull)
-#define CVMX_NPEI_MSI_W1S_ENB3 \
-         (0x0000000000003D60ull)
-#define CVMX_NPEI_MSI_WR_MAP \
-         (0x0000000000003C90ull)
-#define CVMX_NPEI_PCIE_CREDIT_CNT \
-         (0x0000000000003D70ull)
-#define CVMX_NPEI_PCIE_MSI_RCV \
-         (0x0000000000003CB0ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B1 \
-         (0x0000000000000650ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B2 \
-         (0x0000000000000660ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B3 \
-         (0x0000000000000670ull)
-#define CVMX_NPEI_PKTX_CNTS(offset) \
-         (0x0000000000002400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
-         (0x0000000000002800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
-         (0x0000000000002C00ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
-         (0x0000000000003000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
-         (0x0000000000003400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_IN_BP(offset) \
-         (0x0000000000003800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
-         (0x0000000000001400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
-         (0x0000000000001800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
-         (0x0000000000001C00ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKT_CNT_INT \
-         (0x0000000000001110ull)
-#define CVMX_NPEI_PKT_CNT_INT_ENB \
-         (0x0000000000001130ull)
-#define CVMX_NPEI_PKT_DATA_OUT_ES \
-         (0x00000000000010B0ull)
-#define CVMX_NPEI_PKT_DATA_OUT_NS \
-         (0x00000000000010A0ull)
-#define CVMX_NPEI_PKT_DATA_OUT_ROR \
-         (0x0000000000001090ull)
-#define CVMX_NPEI_PKT_DPADDR \
-         (0x0000000000001080ull)
-#define CVMX_NPEI_PKT_INPUT_CONTROL \
-         (0x0000000000001150ull)
-#define CVMX_NPEI_PKT_INSTR_ENB \
-         (0x0000000000001000ull)
-#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
-         (0x0000000000001190ull)
-#define CVMX_NPEI_PKT_INSTR_SIZE \
-         (0x0000000000001020ull)
-#define CVMX_NPEI_PKT_INT_LEVELS \
-         (0x0000000000001100ull)
-#define CVMX_NPEI_PKT_IN_BP \
-         (0x00000000000006B0ull)
-#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
-         (0x0000000000002000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
-         (0x00000000000006A0ull)
-#define CVMX_NPEI_PKT_IN_PCIE_PORT \
-         (0x00000000000011A0ull)
-#define CVMX_NPEI_PKT_IPTR \
-         (0x0000000000001070ull)
-#define CVMX_NPEI_PKT_OUTPUT_WMARK \
-         (0x0000000000001160ull)
-#define CVMX_NPEI_PKT_OUT_BMODE \
-         (0x00000000000010D0ull)
-#define CVMX_NPEI_PKT_OUT_ENB \
-         (0x0000000000001010ull)
-#define CVMX_NPEI_PKT_PCIE_PORT \
-         (0x00000000000010E0ull)
-#define CVMX_NPEI_PKT_PORT_IN_RST \
-         (0x0000000000000690ull)
-#define CVMX_NPEI_PKT_SLIST_ES \
-         (0x0000000000001050ull)
-#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
-         (0x0000000000001180ull)
-#define CVMX_NPEI_PKT_SLIST_NS \
-         (0x0000000000001040ull)
-#define CVMX_NPEI_PKT_SLIST_ROR \
-         (0x0000000000001030ull)
-#define CVMX_NPEI_PKT_TIME_INT \
-         (0x0000000000001120ull)
-#define CVMX_NPEI_PKT_TIME_INT_ENB \
-         (0x0000000000001140ull)
-#define CVMX_NPEI_RSL_INT_BLOCKS \
-         (0x0000000000000520ull)
-#define CVMX_NPEI_SCRATCH_1 \
-         (0x0000000000000270ull)
-#define CVMX_NPEI_STATE1 \
-         (0x0000000000000620ull)
-#define CVMX_NPEI_STATE2 \
-         (0x0000000000000630ull)
-#define CVMX_NPEI_STATE3 \
-         (0x0000000000000640ull)
-#define CVMX_NPEI_WINDOW_CTL \
-         (0x0000000000000380ull)
-#define CVMX_NPEI_WIN_RD_ADDR \
-         (0x0000000000000210ull)
-#define CVMX_NPEI_WIN_RD_DATA \
-         (0x0000000000000240ull)
-#define CVMX_NPEI_WIN_WR_ADDR \
-         (0x0000000000000200ull)
-#define CVMX_NPEI_WIN_WR_DATA \
-         (0x0000000000000220ull)
-#define CVMX_NPEI_WIN_WR_MASK \
-         (0x0000000000000230ull)
+#define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
+#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
+#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
+#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
+#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
+#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
+#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
+#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
+#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
+#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
+#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
+#define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
+#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
+#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
+#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
+#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
+#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
+#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
+#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
+#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
+#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
+#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
+#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
+#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
+#define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
+#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
+#define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
+#define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
+#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
+#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
+#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
+#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
+#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
+#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
+#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
+#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
+#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
+#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
+#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
+#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
+#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
+#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
+#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
+#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
+#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
+#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
+#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
+#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
+#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
+#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
+#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
+#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
+#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
+#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
+#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
+#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
+#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
+#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
+#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
+#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
+#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
+#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
+#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
+#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
+#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
+#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
+#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
+#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
+#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
+#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
+#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
+#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
+#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
+#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
+#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
+#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
+#define CVMX_NPEI_STATE1 (0x0000000000000620ull)
+#define CVMX_NPEI_STATE2 (0x0000000000000630ull)
+#define CVMX_NPEI_STATE3 (0x0000000000000640ull)
+#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
+#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
+#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
+#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
+#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
+#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
 
 union cvmx_npei_bar1_indexx {
         uint32_t u32;
@@ -248,9 +156,7 @@ union cvmx_npei_bist_status {
         uint64_t u64;
         struct cvmx_npei_bist_status_s {
                 uint64_t pkt_rdf:1;
-                uint64_t pkt_pmem:1;
-                uint64_t pkt_p1:1;
-                uint64_t reserved_60_60:1;
+                uint64_t reserved_60_62:3;
                 uint64_t pcr_gim:1;
                 uint64_t pkt_pif:1;
                 uint64_t pcsr_int:1;
@@ -301,9 +207,7 @@ union cvmx_npei_bist_status {
         } s;
         struct cvmx_npei_bist_status_cn52xx {
                 uint64_t pkt_rdf:1;
-                uint64_t pkt_pmem:1;
-                uint64_t pkt_p1:1;
-                uint64_t reserved_60_60:1;
+                uint64_t reserved_60_62:3;
                 uint64_t pcr_gim:1;
                 uint64_t pkt_pif:1;
                 uint64_t pcsr_int:1;
@@ -410,66 +314,7 @@ union cvmx_npei_bist_status {
                 uint64_t msi:1;
                 uint64_t ncb_cmd:1;
         } cn52xxp1;
-        struct cvmx_npei_bist_status_cn56xx {
-                uint64_t pkt_rdf:1;
-                uint64_t reserved_60_62:3;
-                uint64_t pcr_gim:1;
-                uint64_t pkt_pif:1;
-                uint64_t pcsr_int:1;
-                uint64_t pcsr_im:1;
-                uint64_t pcsr_cnt:1;
-                uint64_t pcsr_id:1;
-                uint64_t pcsr_sl:1;
-                uint64_t pkt_imem:1;
-                uint64_t pkt_pfm:1;
-                uint64_t pkt_pof:1;
-                uint64_t reserved_48_49:2;
-                uint64_t pkt_pop0:1;
-                uint64_t pkt_pop1:1;
-                uint64_t d0_mem:1;
-                uint64_t d1_mem:1;
-                uint64_t d2_mem:1;
-                uint64_t d3_mem:1;
-                uint64_t d4_mem:1;
-                uint64_t ds_mem:1;
-                uint64_t reserved_36_39:4;
-                uint64_t d0_pst:1;
-                uint64_t d1_pst:1;
-                uint64_t d2_pst:1;
-                uint64_t d3_pst:1;
-                uint64_t d4_pst:1;
-                uint64_t n2p0_c:1;
-                uint64_t n2p0_o:1;
-                uint64_t n2p1_c:1;
-                uint64_t n2p1_o:1;
-                uint64_t cpl_p0:1;
-                uint64_t cpl_p1:1;
-                uint64_t p2n1_po:1;
-                uint64_t p2n1_no:1;
-                uint64_t p2n1_co:1;
-                uint64_t p2n0_po:1;
-                uint64_t p2n0_no:1;
-                uint64_t p2n0_co:1;
-                uint64_t p2n0_c0:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_p1:1;
-                uint64_t csm0:1;
-                uint64_t csm1:1;
-                uint64_t dif0:1;
-                uint64_t dif1:1;
-                uint64_t dif2:1;
-                uint64_t dif3:1;
-                uint64_t dif4:1;
-                uint64_t msi:1;
-                uint64_t ncb_cmd:1;
-        } cn56xx;
+        struct cvmx_npei_bist_status_cn52xx cn56xx;
         struct cvmx_npei_bist_status_cn56xxp1 {
                 uint64_t reserved_58_63:6;
                 uint64_t pcsr_int:1;
@@ -536,7 +381,16 @@ union cvmx_npei_bist_status {
 union cvmx_npei_bist_status2 {
         uint64_t u64;
         struct cvmx_npei_bist_status2_s {
-                uint64_t reserved_5_63:59;
+                uint64_t reserved_14_63:50;
+                uint64_t prd_tag:1;
+                uint64_t prd_st0:1;
+                uint64_t prd_st1:1;
+                uint64_t prd_err:1;
+                uint64_t nrd_st:1;
+                uint64_t nwe_st:1;
+                uint64_t nwe_wr0:1;
+                uint64_t nwe_wr1:1;
+                uint64_t pkt_rd:1;
                 uint64_t psc_p0:1;
                 uint64_t psc_p1:1;
                 uint64_t pkt_gd:1;
@@ -630,8 +484,7 @@ union cvmx_npei_ctl_status {
         } cn52xxp1;
         struct cvmx_npei_ctl_status_s cn56xx;
         struct cvmx_npei_ctl_status_cn56xxp1 {
-                uint64_t reserved_16_63:48;
-                uint64_t ring_en:1;
+                uint64_t reserved_15_63:49;
                 uint64_t lnk_rst:1;
                 uint64_t arb:1;
                 uint64_t pkt_bp:4;
@@ -756,14 +609,14 @@ union cvmx_npei_dmax_ibuff_saddr {
                 uint64_t saddr:29;
                 uint64_t reserved_0_6:7;
         } s;
-        struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
+        struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
+        struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
                 uint64_t reserved_36_63:28;
                 uint64_t saddr:29;
                 uint64_t reserved_0_6:7;
-        } cn52xx;
-        struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
+        } cn52xxp1;
         struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
-        struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
+        struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
 };
 
 union cvmx_npei_dmax_naddr {
@@ -817,7 +670,8 @@ union cvmx_npei_dma_cnts {
 union cvmx_npei_dma_control {
         uint64_t u64;
         struct cvmx_npei_dma_control_s {
-                uint64_t reserved_39_63:25;
+                uint64_t reserved_40_63:24;
+                uint64_t p_32b_m:1;
                 uint64_t dma4_enb:1;
                 uint64_t dma3_enb:1;
                 uint64_t dma2_enb:1;
@@ -853,7 +707,161 @@ union cvmx_npei_dma_control {
                 uint64_t csize:14;
         } cn52xxp1;
         struct cvmx_npei_dma_control_s cn56xx;
-        struct cvmx_npei_dma_control_s cn56xxp1;
+        struct cvmx_npei_dma_control_cn56xxp1 {
+                uint64_t reserved_39_63:25;
+                uint64_t dma4_enb:1;
+                uint64_t dma3_enb:1;
+                uint64_t dma2_enb:1;
+                uint64_t dma1_enb:1;
+                uint64_t dma0_enb:1;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t csize:14;
+        } cn56xxp1;
+};
+
+union cvmx_npei_dma_pcie_req_num {
+        uint64_t u64;
+        struct cvmx_npei_dma_pcie_req_num_s {
+                uint64_t dma_arb:1;
+                uint64_t reserved_53_62:10;
+                uint64_t pkt_cnt:5;
+                uint64_t reserved_45_47:3;
+                uint64_t dma4_cnt:5;
+                uint64_t reserved_37_39:3;
+                uint64_t dma3_cnt:5;
+                uint64_t reserved_29_31:3;
+                uint64_t dma2_cnt:5;
+                uint64_t reserved_21_23:3;
+                uint64_t dma1_cnt:5;
+                uint64_t reserved_13_15:3;
+                uint64_t dma0_cnt:5;
+                uint64_t reserved_5_7:3;
+                uint64_t dma_cnt:5;
+        } s;
+        struct cvmx_npei_dma_pcie_req_num_s cn52xx;
+        struct cvmx_npei_dma_pcie_req_num_s cn56xx;
+};
+
+union cvmx_npei_dma_state1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state1_s {
+                uint64_t reserved_40_63:24;
+                uint64_t d4_dwe:8;
+                uint64_t d3_dwe:8;
+                uint64_t d2_dwe:8;
+                uint64_t d1_dwe:8;
+                uint64_t d0_dwe:8;
+        } s;
+        struct cvmx_npei_dma_state1_s cn52xx;
+};
+
+union cvmx_npei_dma_state1_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state1_p1_s {
+                uint64_t reserved_60_63:4;
+                uint64_t d0_difst:7;
+                uint64_t d1_difst:7;
+                uint64_t d2_difst:7;
+                uint64_t d3_difst:7;
+                uint64_t d4_difst:7;
+                uint64_t d0_reqst:5;
+                uint64_t d1_reqst:5;
+                uint64_t d2_reqst:5;
+                uint64_t d3_reqst:5;
+                uint64_t d4_reqst:5;
+        } s;
+        struct cvmx_npei_dma_state1_p1_cn52xxp1 {
+                uint64_t reserved_60_63:4;
+                uint64_t d0_difst:7;
+                uint64_t d1_difst:7;
+                uint64_t d2_difst:7;
+                uint64_t d3_difst:7;
+                uint64_t reserved_25_31:7;
+                uint64_t d0_reqst:5;
+                uint64_t d1_reqst:5;
+                uint64_t d2_reqst:5;
+                uint64_t d3_reqst:5;
+                uint64_t reserved_0_4:5;
+        } cn52xxp1;
+        struct cvmx_npei_dma_state1_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state2 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state2_s {
+                uint64_t reserved_28_63:36;
+                uint64_t ndwe:4;
+                uint64_t reserved_21_23:3;
+                uint64_t ndre:5;
+                uint64_t reserved_10_15:6;
+                uint64_t prd:10;
+        } s;
+        struct cvmx_npei_dma_state2_s cn52xx;
+};
+
+union cvmx_npei_dma_state2_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state2_p1_s {
+                uint64_t reserved_45_63:19;
+                uint64_t d0_dffst:9;
+                uint64_t d1_dffst:9;
+                uint64_t d2_dffst:9;
+                uint64_t d3_dffst:9;
+                uint64_t d4_dffst:9;
+        } s;
+        struct cvmx_npei_dma_state2_p1_cn52xxp1 {
+                uint64_t reserved_45_63:19;
+                uint64_t d0_dffst:9;
+                uint64_t d1_dffst:9;
+                uint64_t d2_dffst:9;
+                uint64_t d3_dffst:9;
+                uint64_t reserved_0_8:9;
+        } cn52xxp1;
+        struct cvmx_npei_dma_state2_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state3_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state3_p1_s {
+                uint64_t reserved_60_63:4;
+                uint64_t d0_drest:15;
+                uint64_t d1_drest:15;
+                uint64_t d2_drest:15;
+                uint64_t d3_drest:15;
+        } s;
+        struct cvmx_npei_dma_state3_p1_s cn52xxp1;
+        struct cvmx_npei_dma_state3_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state4_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state4_p1_s {
+                uint64_t reserved_52_63:12;
+                uint64_t d0_dwest:13;
+                uint64_t d1_dwest:13;
+                uint64_t d2_dwest:13;
+                uint64_t d3_dwest:13;
+        } s;
+        struct cvmx_npei_dma_state4_p1_s cn52xxp1;
+        struct cvmx_npei_dma_state4_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state5_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state5_p1_s {
+                uint64_t reserved_28_63:36;
+                uint64_t d4_drest:15;
+                uint64_t d4_dwest:13;
+        } s;
+        struct cvmx_npei_dma_state5_p1_s cn56xxp1;
 };
 
 union cvmx_npei_int_a_enb {
@@ -871,17 +879,7 @@ union cvmx_npei_int_a_enb {
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
         } s;
-        struct cvmx_npei_int_a_enb_cn52xx {
-                uint64_t reserved_8_63:56;
-                uint64_t p1_rdlk:1;
-                uint64_t p0_rdlk:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t dma1_cpl:1;
-                uint64_t dma0_cpl:1;
-        } cn52xx;
+        struct cvmx_npei_int_a_enb_s cn52xx;
         struct cvmx_npei_int_a_enb_cn52xxp1 {
                 uint64_t reserved_2_63:62;
                 uint64_t dma1_cpl:1;
@@ -905,16 +903,7 @@ union cvmx_npei_int_a_enb2 {
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
         } s;
-        struct cvmx_npei_int_a_enb2_cn52xx {
-                uint64_t reserved_8_63:56;
-                uint64_t p1_rdlk:1;
-                uint64_t p0_rdlk:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t reserved_0_1:2;
-        } cn52xx;
+        struct cvmx_npei_int_a_enb2_s cn52xx;
         struct cvmx_npei_int_a_enb2_cn52xxp1 {
                 uint64_t reserved_2_63:62;
                 uint64_t dma1_cpl:1;
@@ -938,17 +927,7 @@ union cvmx_npei_int_a_sum {
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
         } s;
-        struct cvmx_npei_int_a_sum_cn52xx {
-                uint64_t reserved_8_63:56;
-                uint64_t p1_rdlk:1;
-                uint64_t p0_rdlk:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t dma1_cpl:1;
-                uint64_t dma0_cpl:1;
-        } cn52xx;
+        struct cvmx_npei_int_a_sum_s cn52xx;
         struct cvmx_npei_int_a_sum_cn52xxp1 {
                 uint64_t reserved_2_63:62;
                 uint64_t dma1_cpl:1;
@@ -1550,10 +1529,7 @@ union cvmx_npei_int_sum {
                 uint64_t c0_se:1;
                 uint64_t reserved_20_20:1;
                 uint64_t c0_aeri:1;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
+                uint64_t reserved_15_18:4;
                 uint64_t dtime1:1;
                 uint64_t dtime0:1;
                 uint64_t dcnt1:1;
@@ -1959,7 +1935,6 @@ union cvmx_npei_pktx_cnts {
         } s;
         struct cvmx_npei_pktx_cnts_s cn52xx;
         struct cvmx_npei_pktx_cnts_s cn56xx;
-        struct cvmx_npei_pktx_cnts_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_in_bp {
@@ -1970,7 +1945,6 @@ union cvmx_npei_pktx_in_bp {
         } s;
         struct cvmx_npei_pktx_in_bp_s cn52xx;
         struct cvmx_npei_pktx_in_bp_s cn56xx;
-        struct cvmx_npei_pktx_in_bp_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_instr_baddr {
@@ -1981,7 +1955,6 @@ union cvmx_npei_pktx_instr_baddr {
         } s;
         struct cvmx_npei_pktx_instr_baddr_s cn52xx;
         struct cvmx_npei_pktx_instr_baddr_s cn56xx;
-        struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_instr_baoff_dbell {
@@ -1992,7 +1965,6 @@ union cvmx_npei_pktx_instr_baoff_dbell {
         } s;
         struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
         struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
-        struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_instr_fifo_rsize {
@@ -2006,7 +1978,6 @@ union cvmx_npei_pktx_instr_fifo_rsize {
         } s;
         struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
         struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
-        struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_instr_header {
@@ -2014,21 +1985,20 @@ union cvmx_npei_pktx_instr_header {
         struct cvmx_npei_pktx_instr_header_s {
                 uint64_t reserved_44_63:20;
                 uint64_t pbp:1;
-                uint64_t rsv_f:5;
+                uint64_t reserved_38_42:5;
                 uint64_t rparmode:2;
-                uint64_t rsv_e:1;
+                uint64_t reserved_35_35:1;
                 uint64_t rskp_len:7;
-                uint64_t rsv_d:6;
+                uint64_t reserved_22_27:6;
                 uint64_t use_ihdr:1;
-                uint64_t rsv_c:5;
+                uint64_t reserved_16_20:5;
                 uint64_t par_mode:2;
-                uint64_t rsv_b:1;
+                uint64_t reserved_13_13:1;
                 uint64_t skp_len:7;
-                uint64_t rsv_a:6;
+                uint64_t reserved_0_5:6;
         } s;
         struct cvmx_npei_pktx_instr_header_s cn52xx;
         struct cvmx_npei_pktx_instr_header_s cn56xx;
-        struct cvmx_npei_pktx_instr_header_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_slist_baddr {
@@ -2039,7 +2009,6 @@ union cvmx_npei_pktx_slist_baddr {
         } s;
         struct cvmx_npei_pktx_slist_baddr_s cn52xx;
         struct cvmx_npei_pktx_slist_baddr_s cn56xx;
-        struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_slist_baoff_dbell {
@@ -2050,7 +2019,6 @@ union cvmx_npei_pktx_slist_baoff_dbell {
         } s;
         struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
         struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
-        struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_slist_fifo_rsize {
@@ -2061,7 +2029,6 @@ union cvmx_npei_pktx_slist_fifo_rsize {
         } s;
         struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
         struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
-        struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_cnt_int {
@@ -2072,7 +2039,6 @@ union cvmx_npei_pkt_cnt_int {
         } s;
         struct cvmx_npei_pkt_cnt_int_s cn52xx;
         struct cvmx_npei_pkt_cnt_int_s cn56xx;
-        struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_cnt_int_enb {
@@ -2083,7 +2049,6 @@ union cvmx_npei_pkt_cnt_int_enb {
         } s;
         struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
         struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
-        struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_data_out_es {
@@ -2093,7 +2058,6 @@ union cvmx_npei_pkt_data_out_es {
         } s;
         struct cvmx_npei_pkt_data_out_es_s cn52xx;
         struct cvmx_npei_pkt_data_out_es_s cn56xx;
-        struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_data_out_ns {
@@ -2104,7 +2068,6 @@ union cvmx_npei_pkt_data_out_ns {
         } s;
         struct cvmx_npei_pkt_data_out_ns_s cn52xx;
         struct cvmx_npei_pkt_data_out_ns_s cn56xx;
-        struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_data_out_ror {
@@ -2115,7 +2078,6 @@ union cvmx_npei_pkt_data_out_ror {
         } s;
         struct cvmx_npei_pkt_data_out_ror_s cn52xx;
         struct cvmx_npei_pkt_data_out_ror_s cn56xx;
-        struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_dpaddr {
@@ -2126,7 +2088,6 @@ union cvmx_npei_pkt_dpaddr {
         } s;
         struct cvmx_npei_pkt_dpaddr_s cn52xx;
         struct cvmx_npei_pkt_dpaddr_s cn56xx;
-        struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_in_bp {
@@ -2135,6 +2096,7 @@ union cvmx_npei_pkt_in_bp {
                 uint64_t reserved_32_63:32;
                 uint64_t bp:32;
         } s;
+        struct cvmx_npei_pkt_in_bp_s cn52xx;
         struct cvmx_npei_pkt_in_bp_s cn56xx;
 };
 
@@ -2146,7 +2108,6 @@ union cvmx_npei_pkt_in_donex_cnts {
         } s;
         struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
         struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
-        struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_in_instr_counts {
@@ -2184,7 +2145,6 @@ union cvmx_npei_pkt_input_control {
         } s;
         struct cvmx_npei_pkt_input_control_s cn52xx;
         struct cvmx_npei_pkt_input_control_s cn56xx;
-        struct cvmx_npei_pkt_input_control_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_instr_enb {
@@ -2195,7 +2155,6 @@ union cvmx_npei_pkt_instr_enb {
         } s;
         struct cvmx_npei_pkt_instr_enb_s cn52xx;
         struct cvmx_npei_pkt_instr_enb_s cn56xx;
-        struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_instr_rd_size {
@@ -2215,7 +2174,6 @@ union cvmx_npei_pkt_instr_size {
         } s;
         struct cvmx_npei_pkt_instr_size_s cn52xx;
         struct cvmx_npei_pkt_instr_size_s cn56xx;
-        struct cvmx_npei_pkt_instr_size_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_int_levels {
@@ -2227,7 +2185,6 @@ union cvmx_npei_pkt_int_levels {
         } s;
         struct cvmx_npei_pkt_int_levels_s cn52xx;
         struct cvmx_npei_pkt_int_levels_s cn56xx;
-        struct cvmx_npei_pkt_int_levels_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_iptr {
@@ -2238,7 +2195,6 @@ union cvmx_npei_pkt_iptr {
         } s;
         struct cvmx_npei_pkt_iptr_s cn52xx;
         struct cvmx_npei_pkt_iptr_s cn56xx;
-        struct cvmx_npei_pkt_iptr_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_out_bmode {
@@ -2249,7 +2205,6 @@ union cvmx_npei_pkt_out_bmode {
         } s;
         struct cvmx_npei_pkt_out_bmode_s cn52xx;
         struct cvmx_npei_pkt_out_bmode_s cn56xx;
-        struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_out_enb {
@@ -2260,7 +2215,6 @@ union cvmx_npei_pkt_out_enb {
         } s;
         struct cvmx_npei_pkt_out_enb_s cn52xx;
         struct cvmx_npei_pkt_out_enb_s cn56xx;
-        struct cvmx_npei_pkt_out_enb_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_output_wmark {
@@ -2280,7 +2234,6 @@ union cvmx_npei_pkt_pcie_port {
         } s;
         struct cvmx_npei_pkt_pcie_port_s cn52xx;
         struct cvmx_npei_pkt_pcie_port_s cn56xx;
-        struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_port_in_rst {
@@ -2300,7 +2253,6 @@ union cvmx_npei_pkt_slist_es {
         } s;
         struct cvmx_npei_pkt_slist_es_s cn52xx;
         struct cvmx_npei_pkt_slist_es_s cn56xx;
-        struct cvmx_npei_pkt_slist_es_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_slist_id_size {
@@ -2312,7 +2264,6 @@ union cvmx_npei_pkt_slist_id_size {
         } s;
         struct cvmx_npei_pkt_slist_id_size_s cn52xx;
         struct cvmx_npei_pkt_slist_id_size_s cn56xx;
-        struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_slist_ns {
@@ -2323,7 +2274,6 @@ union cvmx_npei_pkt_slist_ns {
         } s;
         struct cvmx_npei_pkt_slist_ns_s cn52xx;
         struct cvmx_npei_pkt_slist_ns_s cn56xx;
-        struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_slist_ror {
@@ -2334,7 +2284,6 @@ union cvmx_npei_pkt_slist_ror {
         } s;
         struct cvmx_npei_pkt_slist_ror_s cn52xx;
         struct cvmx_npei_pkt_slist_ror_s cn56xx;
-        struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_time_int {
@@ -2345,7 +2294,6 @@ union cvmx_npei_pkt_time_int {
         } s;
         struct cvmx_npei_pkt_time_int_s cn52xx;
         struct cvmx_npei_pkt_time_int_s cn56xx;
-        struct cvmx_npei_pkt_time_int_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_time_int_enb {
@@ -2356,7 +2304,6 @@ union cvmx_npei_pkt_time_int_enb {
         } s;
         struct cvmx_npei_pkt_time_int_enb_s cn52xx;
         struct cvmx_npei_pkt_time_int_enb_s cn56xx;
-        struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
 };
 
 union cvmx_npei_rsl_int_blocks {
@@ -2371,7 +2318,8 @@ union cvmx_npei_rsl_int_blocks {
                 uint64_t asxpcs0:1;
                 uint64_t reserved_21_21:1;
                 uint64_t pip:1;
-                uint64_t reserved_18_19:2;
+                uint64_t spx1:1;
+                uint64_t spx0:1;
                 uint64_t lmc0:1;
                 uint64_t l2c:1;
                 uint64_t usb1:1;
@@ -2383,7 +2331,7 @@ union cvmx_npei_rsl_int_blocks {
                 uint64_t ipd:1;
                 uint64_t reserved_8_8:1;
                 uint64_t zip:1;
-                uint64_t reserved_6_6:1;
+                uint64_t dfa:1;
                 uint64_t fpa:1;
                 uint64_t key:1;
                 uint64_t npei:1;
@@ -2393,37 +2341,8 @@ union cvmx_npei_rsl_int_blocks {
         } s;
         struct cvmx_npei_rsl_int_blocks_s cn52xx;
         struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
-        struct cvmx_npei_rsl_int_blocks_cn56xx {
-                uint64_t reserved_31_63:33;
-                uint64_t iob:1;
-                uint64_t lmc1:1;
-                uint64_t agl:1;
-                uint64_t reserved_24_27:4;
-                uint64_t asxpcs1:1;
-                uint64_t asxpcs0:1;
-                uint64_t reserved_21_21:1;
-                uint64_t pip:1;
-                uint64_t reserved_18_19:2;
-                uint64_t lmc0:1;
-                uint64_t l2c:1;
-                uint64_t reserved_15_15:1;
-                uint64_t rad:1;
-                uint64_t usb:1;
-                uint64_t pow:1;
-                uint64_t tim:1;
-                uint64_t pko:1;
-                uint64_t ipd:1;
-                uint64_t reserved_8_8:1;
-                uint64_t zip:1;
-                uint64_t reserved_6_6:1;
-                uint64_t fpa:1;
-                uint64_t key:1;
-                uint64_t npei:1;
-                uint64_t gmx1:1;
-                uint64_t gmx0:1;
-                uint64_t mio:1;
-        } cn56xx;
-        struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
+        struct cvmx_npei_rsl_int_blocks_s cn56xx;
+        struct cvmx_npei_rsl_int_blocks_s cn56xxp1;
 };
 
 union cvmx_npei_scratch_1 {
diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
index 4e03cd8561e3..f089c780060f 100644
--- a/arch/mips/include/asm/octeon/cvmx-npi-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,246 +28,126 @@
 #ifndef __CVMX_NPI_DEFS_H__
 #define __CVMX_NPI_DEFS_H__
 
-#define CVMX_NPI_BASE_ADDR_INPUT0 \
-         CVMX_ADD_IO_SEG(0x00011F0000000070ull)
-#define CVMX_NPI_BASE_ADDR_INPUT1 \
-         CVMX_ADD_IO_SEG(0x00011F0000000080ull)
-#define CVMX_NPI_BASE_ADDR_INPUT2 \
-         CVMX_ADD_IO_SEG(0x00011F0000000090ull)
-#define CVMX_NPI_BASE_ADDR_INPUT3 \
-         CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
-#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
-#define CVMX_NPI_BASE_ADDR_OUTPUT0 \
-         CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT1 \
-         CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT2 \
-         CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT3 \
-         CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
-#define CVMX_NPI_BIST_STATUS \
-         CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
-         CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
-         CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
-         CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
-         CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_COMP_CTL \
-         CVMX_ADD_IO_SEG(0x00011F0000000218ull)
-#define CVMX_NPI_CTL_STATUS \
-         CVMX_ADD_IO_SEG(0x00011F0000000010ull)
-#define CVMX_NPI_DBG_SELECT \
-         CVMX_ADD_IO_SEG(0x00011F0000000008ull)
-#define CVMX_NPI_DMA_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F0000000128ull)
-#define CVMX_NPI_DMA_HIGHP_COUNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000148ull)
-#define CVMX_NPI_DMA_HIGHP_NADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000158ull)
-#define CVMX_NPI_DMA_LOWP_COUNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000140ull)
-#define CVMX_NPI_DMA_LOWP_NADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000150ull)
-#define CVMX_NPI_HIGHP_DBELL \
-         CVMX_ADD_IO_SEG(0x00011F0000000120ull)
-#define CVMX_NPI_HIGHP_IBUFF_SADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000110ull)
-#define CVMX_NPI_INPUT_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F0000000138ull)
-#define CVMX_NPI_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000000020ull)
-#define CVMX_NPI_INT_SUM \
-         CVMX_ADD_IO_SEG(0x00011F0000000018ull)
-#define CVMX_NPI_LOWP_DBELL \
-         CVMX_ADD_IO_SEG(0x00011F0000000118ull)
-#define CVMX_NPI_LOWP_IBUFF_SADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000108ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID3 \
-         CVMX_ADD_IO_SEG(0x00011F0000000028ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID4 \
-         CVMX_ADD_IO_SEG(0x00011F0000000030ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID5 \
-         CVMX_ADD_IO_SEG(0x00011F0000000038ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID6 \
-         CVMX_ADD_IO_SEG(0x00011F0000000040ull)
-#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
-#define CVMX_NPI_MSI_RCV \
-         (0x0000000000000190ull)
-#define CVMX_NPI_NPI_MSI_RCV \
-         CVMX_ADD_IO_SEG(0x00011F0000001190ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT0 \
-         CVMX_ADD_IO_SEG(0x00011F0000000050ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT1 \
-         CVMX_ADD_IO_SEG(0x00011F0000000058ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT2 \
-         CVMX_ADD_IO_SEG(0x00011F0000000060ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT3 \
-         CVMX_ADD_IO_SEG(0x00011F0000000068ull)
-#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
-#define CVMX_NPI_OUTPUT_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F0000000100ull)
-#define CVMX_NPI_P0_DBPAIR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000180ull)
-#define CVMX_NPI_P0_INSTR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
-#define CVMX_NPI_P0_INSTR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
-#define CVMX_NPI_P0_PAIR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000160ull)
-#define CVMX_NPI_P1_DBPAIR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000188ull)
-#define CVMX_NPI_P1_INSTR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
-#define CVMX_NPI_P1_INSTR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
-#define CVMX_NPI_P1_PAIR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000168ull)
-#define CVMX_NPI_P2_DBPAIR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000190ull)
-#define CVMX_NPI_P2_INSTR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
-#define CVMX_NPI_P2_INSTR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
-#define CVMX_NPI_P2_PAIR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000170ull)
-#define CVMX_NPI_P3_DBPAIR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000198ull)
-#define CVMX_NPI_P3_INSTR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
-#define CVMX_NPI_P3_INSTR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
-#define CVMX_NPI_P3_PAIR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000178ull)
-#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
-#define CVMX_NPI_PCI_BIST_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
-#define CVMX_NPI_PCI_BURST_SIZE \
-         CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
-#define CVMX_NPI_PCI_CFG00 \
-         CVMX_ADD_IO_SEG(0x00011F0000001800ull)
-#define CVMX_NPI_PCI_CFG01 \
-         CVMX_ADD_IO_SEG(0x00011F0000001804ull)
-#define CVMX_NPI_PCI_CFG02 \
-         CVMX_ADD_IO_SEG(0x00011F0000001808ull)
-#define CVMX_NPI_PCI_CFG03 \
-         CVMX_ADD_IO_SEG(0x00011F000000180Cull)
-#define CVMX_NPI_PCI_CFG04 \
-         CVMX_ADD_IO_SEG(0x00011F0000001810ull)
-#define CVMX_NPI_PCI_CFG05 \
-         CVMX_ADD_IO_SEG(0x00011F0000001814ull)
-#define CVMX_NPI_PCI_CFG06 \
-         CVMX_ADD_IO_SEG(0x00011F0000001818ull)
-#define CVMX_NPI_PCI_CFG07 \
-         CVMX_ADD_IO_SEG(0x00011F000000181Cull)
-#define CVMX_NPI_PCI_CFG08 \
-         CVMX_ADD_IO_SEG(0x00011F0000001820ull)
-#define CVMX_NPI_PCI_CFG09 \
-         CVMX_ADD_IO_SEG(0x00011F0000001824ull)
-#define CVMX_NPI_PCI_CFG10 \
-         CVMX_ADD_IO_SEG(0x00011F0000001828ull)
-#define CVMX_NPI_PCI_CFG11 \
-         CVMX_ADD_IO_SEG(0x00011F000000182Cull)
-#define CVMX_NPI_PCI_CFG12 \
-         CVMX_ADD_IO_SEG(0x00011F0000001830ull)
-#define CVMX_NPI_PCI_CFG13 \
-         CVMX_ADD_IO_SEG(0x00011F0000001834ull)
-#define CVMX_NPI_PCI_CFG15 \
-         CVMX_ADD_IO_SEG(0x00011F000000183Cull)
-#define CVMX_NPI_PCI_CFG16 \
-         CVMX_ADD_IO_SEG(0x00011F0000001840ull)
-#define CVMX_NPI_PCI_CFG17 \
-         CVMX_ADD_IO_SEG(0x00011F0000001844ull)
-#define CVMX_NPI_PCI_CFG18 \
-         CVMX_ADD_IO_SEG(0x00011F0000001848ull)
-#define CVMX_NPI_PCI_CFG19 \
-         CVMX_ADD_IO_SEG(0x00011F000000184Cull)
-#define CVMX_NPI_PCI_CFG20 \
-         CVMX_ADD_IO_SEG(0x00011F0000001850ull)
-#define CVMX_NPI_PCI_CFG21 \
-         CVMX_ADD_IO_SEG(0x00011F0000001854ull)
-#define CVMX_NPI_PCI_CFG22 \
-         CVMX_ADD_IO_SEG(0x00011F0000001858ull)
-#define CVMX_NPI_PCI_CFG56 \
-         CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
-#define CVMX_NPI_PCI_CFG57 \
-         CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
-#define CVMX_NPI_PCI_CFG58 \
-         CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
-#define CVMX_NPI_PCI_CFG59 \
-         CVMX_ADD_IO_SEG(0x00011F00000018ECull)
-#define CVMX_NPI_PCI_CFG60 \
-         CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
-#define CVMX_NPI_PCI_CFG61 \
-         CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
-#define CVMX_NPI_PCI_CFG62 \
-         CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
-#define CVMX_NPI_PCI_CFG63 \
-         CVMX_ADD_IO_SEG(0x00011F00000018FCull)
-#define CVMX_NPI_PCI_CNT_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
-#define CVMX_NPI_PCI_CTL_STATUS_2 \
-         CVMX_ADD_IO_SEG(0x00011F000000118Cull)
-#define CVMX_NPI_PCI_INT_ARB_CFG \
-         CVMX_ADD_IO_SEG(0x00011F0000000130ull)
-#define CVMX_NPI_PCI_INT_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
-#define CVMX_NPI_PCI_INT_SUM2 \
-         CVMX_ADD_IO_SEG(0x00011F0000001198ull)
-#define CVMX_NPI_PCI_READ_CMD \
-         CVMX_ADD_IO_SEG(0x00011F0000000048ull)
-#define CVMX_NPI_PCI_READ_CMD_6 \
-         CVMX_ADD_IO_SEG(0x00011F0000001180ull)
-#define CVMX_NPI_PCI_READ_CMD_C \
-         CVMX_ADD_IO_SEG(0x00011F0000001184ull)
-#define CVMX_NPI_PCI_READ_CMD_E \
-         CVMX_ADD_IO_SEG(0x00011F0000001188ull)
-#define CVMX_NPI_PCI_SCM_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
-#define CVMX_NPI_PCI_TSR_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
-#define CVMX_NPI_PORT32_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
-#define CVMX_NPI_PORT33_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000200ull)
-#define CVMX_NPI_PORT34_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000208ull)
-#define CVMX_NPI_PORT35_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000210ull)
-#define CVMX_NPI_PORT_BP_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
-#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_INSTR_ADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_INSTR_CNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_PAIR_CNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
-#define CVMX_NPI_RSL_INT_BLOCKS \
-         CVMX_ADD_IO_SEG(0x00011F0000000000ull)
-#define CVMX_NPI_SIZE_INPUT0 \
-         CVMX_ADD_IO_SEG(0x00011F0000000078ull)
-#define CVMX_NPI_SIZE_INPUT1 \
-         CVMX_ADD_IO_SEG(0x00011F0000000088ull)
-#define CVMX_NPI_SIZE_INPUT2 \
-         CVMX_ADD_IO_SEG(0x00011F0000000098ull)
-#define CVMX_NPI_SIZE_INPUT3 \
-         CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
-#define CVMX_NPI_SIZE_INPUTX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
-#define CVMX_NPI_WIN_READ_TO \
-         CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
+#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
+#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
+#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
+#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
+#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
+#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
+#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
+#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
+#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
+#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
+#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
+#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
+#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
+#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
+#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
+#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
+#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
+#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
+#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
+#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
+#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
+#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
+#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
+#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
+#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
+#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
+#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
+#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
+#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
+#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
+#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
+#define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
+#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
+#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
+#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
+#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
+#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
+#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
+#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
+#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
+#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
+#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
+#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
+#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
+#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
+#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
+#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
+#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
+#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
+#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
+#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
+#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
+#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
+#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
+#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
+#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
+#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
+#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
+#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
+#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
+#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
+#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
+#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
+#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
+#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
+#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
+#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
+#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
+#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
+#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
+#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
+#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
+#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
+#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
+#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
+#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
+#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
+#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
+#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
+#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
+#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
+#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
+#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
+#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
+#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
+#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
+#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
+#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
+#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
+#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
+#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
+#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
+#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
+#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
+#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
+#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
+#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
+#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
+#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
+#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
+#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
+#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
 
 union cvmx_npi_base_addr_inputx {
         uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
index 90f8d6535753..6ff6d9d357ba 100644
--- a/arch/mips/include/asm/octeon/cvmx-pci-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,184 +28,91 @@
 #ifndef __CVMX_PCI_DEFS_H__
 #define __CVMX_PCI_DEFS_H__
 
-#define CVMX_PCI_BAR1_INDEXX(offset) \
-         (0x0000000000000100ull + (((offset) & 31) * 4))
-#define CVMX_PCI_BIST_REG \
-         (0x00000000000001C0ull)
-#define CVMX_PCI_CFG00 \
-         (0x0000000000000000ull)
-#define CVMX_PCI_CFG01 \
-         (0x0000000000000004ull)
-#define CVMX_PCI_CFG02 \
-         (0x0000000000000008ull)
-#define CVMX_PCI_CFG03 \
-         (0x000000000000000Cull)
-#define CVMX_PCI_CFG04 \
-         (0x0000000000000010ull)
-#define CVMX_PCI_CFG05 \
-         (0x0000000000000014ull)
-#define CVMX_PCI_CFG06 \
-         (0x0000000000000018ull)
-#define CVMX_PCI_CFG07 \
-         (0x000000000000001Cull)
-#define CVMX_PCI_CFG08 \
-         (0x0000000000000020ull)
-#define CVMX_PCI_CFG09 \
-         (0x0000000000000024ull)
-#define CVMX_PCI_CFG10 \
-         (0x0000000000000028ull)
-#define CVMX_PCI_CFG11 \
-         (0x000000000000002Cull)
-#define CVMX_PCI_CFG12 \
-         (0x0000000000000030ull)
-#define CVMX_PCI_CFG13 \
-         (0x0000000000000034ull)
-#define CVMX_PCI_CFG15 \
-         (0x000000000000003Cull)
-#define CVMX_PCI_CFG16 \
-         (0x0000000000000040ull)
-#define CVMX_PCI_CFG17 \
-         (0x0000000000000044ull)
-#define CVMX_PCI_CFG18 \
-         (0x0000000000000048ull)
-#define CVMX_PCI_CFG19 \
-         (0x000000000000004Cull)
-#define CVMX_PCI_CFG20 \
-         (0x0000000000000050ull)
-#define CVMX_PCI_CFG21 \
-         (0x0000000000000054ull)
-#define CVMX_PCI_CFG22 \
-         (0x0000000000000058ull)
-#define CVMX_PCI_CFG56 \
-         (0x00000000000000E0ull)
-#define CVMX_PCI_CFG57 \
-         (0x00000000000000E4ull)
-#define CVMX_PCI_CFG58 \
-         (0x00000000000000E8ull)
-#define CVMX_PCI_CFG59 \
-         (0x00000000000000ECull)
-#define CVMX_PCI_CFG60 \
-         (0x00000000000000F0ull)
-#define CVMX_PCI_CFG61 \
-         (0x00000000000000F4ull)
-#define CVMX_PCI_CFG62 \
-         (0x00000000000000F8ull)
-#define CVMX_PCI_CFG63 \
-         (0x00000000000000FCull)
-#define CVMX_PCI_CNT_REG \
-         (0x00000000000001B8ull)
-#define CVMX_PCI_CTL_STATUS_2 \
-         (0x000000000000018Cull)
-#define CVMX_PCI_DBELL_0 \
-         (0x0000000000000080ull)
-#define CVMX_PCI_DBELL_1 \
-         (0x0000000000000088ull)
-#define CVMX_PCI_DBELL_2 \
-         (0x0000000000000090ull)
-#define CVMX_PCI_DBELL_3 \
-         (0x0000000000000098ull)
-#define CVMX_PCI_DBELL_X(offset) \
-         (0x0000000000000080ull + (((offset) & 3) * 8))
-#define CVMX_PCI_DMA_CNT0 \
-         (0x00000000000000A0ull)
-#define CVMX_PCI_DMA_CNT1 \
-         (0x00000000000000A8ull)
-#define CVMX_PCI_DMA_CNTX(offset) \
-         (0x00000000000000A0ull + (((offset) & 1) * 8))
-#define CVMX_PCI_DMA_INT_LEV0 \
-         (0x00000000000000A4ull)
-#define CVMX_PCI_DMA_INT_LEV1 \
-         (0x00000000000000ACull)
-#define CVMX_PCI_DMA_INT_LEVX(offset) \
-         (0x00000000000000A4ull + (((offset) & 1) * 8))
-#define CVMX_PCI_DMA_TIME0 \
-         (0x00000000000000B0ull)
-#define CVMX_PCI_DMA_TIME1 \
-         (0x00000000000000B4ull)
-#define CVMX_PCI_DMA_TIMEX(offset) \
-         (0x00000000000000B0ull + (((offset) & 1) * 4))
-#define CVMX_PCI_INSTR_COUNT0 \
-         (0x0000000000000084ull)
-#define CVMX_PCI_INSTR_COUNT1 \
-         (0x000000000000008Cull)
-#define CVMX_PCI_INSTR_COUNT2 \
-         (0x0000000000000094ull)
-#define CVMX_PCI_INSTR_COUNT3 \
-         (0x000000000000009Cull)
-#define CVMX_PCI_INSTR_COUNTX(offset) \
-         (0x0000000000000084ull + (((offset) & 3) * 8))
-#define CVMX_PCI_INT_ENB \
-         (0x0000000000000038ull)
-#define CVMX_PCI_INT_ENB2 \
-         (0x00000000000001A0ull)
-#define CVMX_PCI_INT_SUM \
-         (0x0000000000000030ull)
-#define CVMX_PCI_INT_SUM2 \
-         (0x0000000000000198ull)
-#define CVMX_PCI_MSI_RCV \
-         (0x00000000000000F0ull)
-#define CVMX_PCI_PKTS_SENT0 \
-         (0x0000000000000040ull)
-#define CVMX_PCI_PKTS_SENT1 \
-         (0x0000000000000050ull)
-#define CVMX_PCI_PKTS_SENT2 \
-         (0x0000000000000060ull)
-#define CVMX_PCI_PKTS_SENT3 \
-         (0x0000000000000070ull)
-#define CVMX_PCI_PKTS_SENTX(offset) \
-         (0x0000000000000040ull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKTS_SENT_INT_LEV0 \
-         (0x0000000000000048ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV1 \
-         (0x0000000000000058ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV2 \
-         (0x0000000000000068ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV3 \
-         (0x0000000000000078ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \
-         (0x0000000000000048ull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKTS_SENT_TIME0 \
-         (0x000000000000004Cull)
-#define CVMX_PCI_PKTS_SENT_TIME1 \
-         (0x000000000000005Cull)
-#define CVMX_PCI_PKTS_SENT_TIME2 \
-         (0x000000000000006Cull)
-#define CVMX_PCI_PKTS_SENT_TIME3 \
-         (0x000000000000007Cull)
-#define CVMX_PCI_PKTS_SENT_TIMEX(offset) \
-         (0x000000000000004Cull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKT_CREDITS0 \
-         (0x0000000000000044ull)
-#define CVMX_PCI_PKT_CREDITS1 \
-         (0x0000000000000054ull)
-#define CVMX_PCI_PKT_CREDITS2 \
-         (0x0000000000000064ull)
-#define CVMX_PCI_PKT_CREDITS3 \
-         (0x0000000000000074ull)
-#define CVMX_PCI_PKT_CREDITSX(offset) \
-         (0x0000000000000044ull + (((offset) & 3) * 16))
-#define CVMX_PCI_READ_CMD_6 \
-         (0x0000000000000180ull)
-#define CVMX_PCI_READ_CMD_C \
-         (0x0000000000000184ull)
-#define CVMX_PCI_READ_CMD_E \
-         (0x0000000000000188ull)
-#define CVMX_PCI_READ_TIMEOUT \
-         CVMX_ADD_IO_SEG(0x00011F00000000B0ull)
-#define CVMX_PCI_SCM_REG \
-         (0x00000000000001A8ull)
-#define CVMX_PCI_TSR_REG \
-         (0x00000000000001B0ull)
-#define CVMX_PCI_WIN_RD_ADDR \
-         (0x0000000000000008ull)
-#define CVMX_PCI_WIN_RD_DATA \
-         (0x0000000000000020ull)
-#define CVMX_PCI_WIN_WR_ADDR \
-         (0x0000000000000000ull)
-#define CVMX_PCI_WIN_WR_DATA \
-         (0x0000000000000010ull)
-#define CVMX_PCI_WIN_WR_MASK \
-         (0x0000000000000018ull)
+#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4)
+#define CVMX_PCI_BIST_REG (0x00000000000001C0ull)
+#define CVMX_PCI_CFG00 (0x0000000000000000ull)
+#define CVMX_PCI_CFG01 (0x0000000000000004ull)
+#define CVMX_PCI_CFG02 (0x0000000000000008ull)
+#define CVMX_PCI_CFG03 (0x000000000000000Cull)
+#define CVMX_PCI_CFG04 (0x0000000000000010ull)
+#define CVMX_PCI_CFG05 (0x0000000000000014ull)
+#define CVMX_PCI_CFG06 (0x0000000000000018ull)
+#define CVMX_PCI_CFG07 (0x000000000000001Cull)
+#define CVMX_PCI_CFG08 (0x0000000000000020ull)
+#define CVMX_PCI_CFG09 (0x0000000000000024ull)
+#define CVMX_PCI_CFG10 (0x0000000000000028ull)
+#define CVMX_PCI_CFG11 (0x000000000000002Cull)
+#define CVMX_PCI_CFG12 (0x0000000000000030ull)
+#define CVMX_PCI_CFG13 (0x0000000000000034ull)
+#define CVMX_PCI_CFG15 (0x000000000000003Cull)
+#define CVMX_PCI_CFG16 (0x0000000000000040ull)
+#define CVMX_PCI_CFG17 (0x0000000000000044ull)
+#define CVMX_PCI_CFG18 (0x0000000000000048ull)
+#define CVMX_PCI_CFG19 (0x000000000000004Cull)
+#define CVMX_PCI_CFG20 (0x0000000000000050ull)
+#define CVMX_PCI_CFG21 (0x0000000000000054ull)
+#define CVMX_PCI_CFG22 (0x0000000000000058ull)
+#define CVMX_PCI_CFG56 (0x00000000000000E0ull)
+#define CVMX_PCI_CFG57 (0x00000000000000E4ull)
+#define CVMX_PCI_CFG58 (0x00000000000000E8ull)
+#define CVMX_PCI_CFG59 (0x00000000000000ECull)
+#define CVMX_PCI_CFG60 (0x00000000000000F0ull)
+#define CVMX_PCI_CFG61 (0x00000000000000F4ull)
+#define CVMX_PCI_CFG62 (0x00000000000000F8ull)
+#define CVMX_PCI_CFG63 (0x00000000000000FCull)
+#define CVMX_PCI_CNT_REG (0x00000000000001B8ull)
+#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull)
+#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8)
+#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
+#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
+#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
+#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
+#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
+#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
+#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
+#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
+#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
+#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
+#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
+#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
+#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
+#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8)
+#define CVMX_PCI_INT_ENB (0x0000000000000038ull)
+#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull)
+#define CVMX_PCI_INT_SUM (0x0000000000000030ull)
+#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull)
+#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull)
+#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
+#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
+#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
+#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
+#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
+#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
+#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
+#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
+#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
+#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
+#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
+#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
+#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
+#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
+#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
+#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
+#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16)
+#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull)
+#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull)
+#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull)
+#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull))
+#define CVMX_PCI_SCM_REG (0x00000000000001A8ull)
+#define CVMX_PCI_TSR_REG (0x00000000000001B0ull)
+#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull)
+#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull)
+#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull)
+#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull)
+#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull)
 
 union cvmx_pci_bar1_indexx {
         uint32_t u32;
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index 75574c918942..f8cb88902efb 100644
--- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,158 +28,83 @@
 #ifndef __CVMX_PCIERCX_DEFS_H__
 #define __CVMX_PCIERCX_DEFS_H__
 
-#define CVMX_PCIERCX_CFG000(offset) \
-         (0x0000000000000000ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG001(offset) \
-         (0x0000000000000004ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG002(offset) \
-         (0x0000000000000008ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG003(offset) \
-         (0x000000000000000Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG004(offset) \
-         (0x0000000000000010ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG005(offset) \
-         (0x0000000000000014ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG006(offset) \
-         (0x0000000000000018ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG007(offset) \
-         (0x000000000000001Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG008(offset) \
-         (0x0000000000000020ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG009(offset) \
-         (0x0000000000000024ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG010(offset) \
-         (0x0000000000000028ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG011(offset) \
-         (0x000000000000002Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG012(offset) \
-         (0x0000000000000030ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG013(offset) \
-         (0x0000000000000034ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG014(offset) \
-         (0x0000000000000038ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG015(offset) \
-         (0x000000000000003Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG016(offset) \
-         (0x0000000000000040ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG017(offset) \
-         (0x0000000000000044ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG020(offset) \
-         (0x0000000000000050ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG021(offset) \
-         (0x0000000000000054ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG022(offset) \
-         (0x0000000000000058ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG023(offset) \
-         (0x000000000000005Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG028(offset) \
-         (0x0000000000000070ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG029(offset) \
-         (0x0000000000000074ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG030(offset) \
-         (0x0000000000000078ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG031(offset) \
-         (0x000000000000007Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG032(offset) \
-         (0x0000000000000080ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG033(offset) \
-         (0x0000000000000084ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG034(offset) \
-         (0x0000000000000088ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG035(offset) \
-         (0x000000000000008Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG036(offset) \
-         (0x0000000000000090ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG037(offset) \
-         (0x0000000000000094ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG038(offset) \
-         (0x0000000000000098ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG039(offset) \
-         (0x000000000000009Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG040(offset) \
-         (0x00000000000000A0ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG041(offset) \
-         (0x00000000000000A4ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG042(offset) \
-         (0x00000000000000A8ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG064(offset) \
-         (0x0000000000000100ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG065(offset) \
-         (0x0000000000000104ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG066(offset) \
-         (0x0000000000000108ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG067(offset) \
-         (0x000000000000010Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG068(offset) \
-         (0x0000000000000110ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG069(offset) \
-         (0x0000000000000114ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG070(offset) \
-         (0x0000000000000118ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG071(offset) \
-         (0x000000000000011Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG072(offset) \
-         (0x0000000000000120ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG073(offset) \
-         (0x0000000000000124ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG074(offset) \
-         (0x0000000000000128ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG075(offset) \
-         (0x000000000000012Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG076(offset) \
-         (0x0000000000000130ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG077(offset) \
-         (0x0000000000000134ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG448(offset) \
-         (0x0000000000000700ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG449(offset) \
-         (0x0000000000000704ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG450(offset) \
-         (0x0000000000000708ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG451(offset) \
-         (0x000000000000070Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG452(offset) \
-         (0x0000000000000710ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG453(offset) \
-         (0x0000000000000714ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG454(offset) \
-         (0x0000000000000718ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG455(offset) \
-         (0x000000000000071Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG456(offset) \
-         (0x0000000000000720ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG458(offset) \
-         (0x0000000000000728ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG459(offset) \
-         (0x000000000000072Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG460(offset) \
-         (0x0000000000000730ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG461(offset) \
-         (0x0000000000000734ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG462(offset) \
-         (0x0000000000000738ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG463(offset) \
-         (0x000000000000073Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG464(offset) \
-         (0x0000000000000740ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG465(offset) \
-         (0x0000000000000744ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG466(offset) \
-         (0x0000000000000748ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG467(offset) \
-         (0x000000000000074Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG468(offset) \
-         (0x0000000000000750ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG490(offset) \
-         (0x00000000000007A8ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG491(offset) \
-         (0x00000000000007ACull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG492(offset) \
-         (0x00000000000007B0ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG516(offset) \
-         (0x0000000000000810ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG517(offset) \
-         (0x0000000000000814ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull)
+#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull)
+#define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull)
+#define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull)
+#define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull)
+#define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull)
+#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull)
+#define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull)
+#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull)
+#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull)
+#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull)
+#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull)
+#define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull)
+#define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull)
+#define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull)
+#define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull)
+#define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull)
+#define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull)
+#define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull)
+#define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull)
+#define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull)
+#define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull)
+#define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull)
+#define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull)
+#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull)
+#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull)
+#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull)
+#define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull)
+#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull)
+#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull)
+#define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull)
+#define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull)
+#define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull)
+#define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull)
+#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull)
+#define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull)
+#define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull)
+#define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull)
+#define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull)
+#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull)
+#define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull)
+#define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull)
+#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull)
+#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull)
+#define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull)
+#define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull)
+#define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull)
+#define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull)
+#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull)
+#define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull)
+#define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull)
+#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull)
+#define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull)
+#define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull)
+#define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull)
+#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull)
+#define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull)
+#define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull)
+#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull)
+#define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull)
+#define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull)
+#define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull)
+#define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull)
+#define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull)
+#define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull)
+#define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull)
+#define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull)
+#define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull)
+#define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull)
+#define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull)
+#define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull)
+#define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull)
+#define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull)
+#define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull)
+#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull)
+#define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull)
+#define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull)
 
 union cvmx_pciercx_cfg000 {
         uint32_t u32;
@@ -191,6 +116,8 @@ union cvmx_pciercx_cfg000 {
         struct cvmx_pciercx_cfg000_s cn52xxp1;
         struct cvmx_pciercx_cfg000_s cn56xx;
         struct cvmx_pciercx_cfg000_s cn56xxp1;
+        struct cvmx_pciercx_cfg000_s cn63xx;
+        struct cvmx_pciercx_cfg000_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg001 {
@@ -225,6 +152,8 @@ union cvmx_pciercx_cfg001 {
         struct cvmx_pciercx_cfg001_s cn52xxp1;
         struct cvmx_pciercx_cfg001_s cn56xx;
         struct cvmx_pciercx_cfg001_s cn56xxp1;
+        struct cvmx_pciercx_cfg001_s cn63xx;
+        struct cvmx_pciercx_cfg001_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg002 {
@@ -239,6 +168,8 @@ union cvmx_pciercx_cfg002 {
         struct cvmx_pciercx_cfg002_s cn52xxp1;
         struct cvmx_pciercx_cfg002_s cn56xx;
         struct cvmx_pciercx_cfg002_s cn56xxp1;
+        struct cvmx_pciercx_cfg002_s cn63xx;
+        struct cvmx_pciercx_cfg002_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg003 {
@@ -254,6 +185,8 @@ union cvmx_pciercx_cfg003 {
         struct cvmx_pciercx_cfg003_s cn52xxp1;
         struct cvmx_pciercx_cfg003_s cn56xx;
         struct cvmx_pciercx_cfg003_s cn56xxp1;
+        struct cvmx_pciercx_cfg003_s cn63xx;
+        struct cvmx_pciercx_cfg003_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg004 {
@@ -265,6 +198,8 @@ union cvmx_pciercx_cfg004 {
         struct cvmx_pciercx_cfg004_s cn52xxp1;
         struct cvmx_pciercx_cfg004_s cn56xx;
         struct cvmx_pciercx_cfg004_s cn56xxp1;
+        struct cvmx_pciercx_cfg004_s cn63xx;
+        struct cvmx_pciercx_cfg004_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg005 {
@@ -276,6 +211,8 @@ union cvmx_pciercx_cfg005 {
         struct cvmx_pciercx_cfg005_s cn52xxp1;
         struct cvmx_pciercx_cfg005_s cn56xx;
         struct cvmx_pciercx_cfg005_s cn56xxp1;
+        struct cvmx_pciercx_cfg005_s cn63xx;
+        struct cvmx_pciercx_cfg005_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg006 {
@@ -290,6 +227,8 @@ union cvmx_pciercx_cfg006 {
         struct cvmx_pciercx_cfg006_s cn52xxp1;
         struct cvmx_pciercx_cfg006_s cn56xx;
         struct cvmx_pciercx_cfg006_s cn56xxp1;
+        struct cvmx_pciercx_cfg006_s cn63xx;
+        struct cvmx_pciercx_cfg006_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg007 {
@@ -317,6 +256,8 @@ union cvmx_pciercx_cfg007 {
         struct cvmx_pciercx_cfg007_s cn52xxp1;
         struct cvmx_pciercx_cfg007_s cn56xx;
         struct cvmx_pciercx_cfg007_s cn56xxp1;
+        struct cvmx_pciercx_cfg007_s cn63xx;
+        struct cvmx_pciercx_cfg007_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg008 {
@@ -331,6 +272,8 @@ union cvmx_pciercx_cfg008 {
         struct cvmx_pciercx_cfg008_s cn52xxp1;
         struct cvmx_pciercx_cfg008_s cn56xx;
         struct cvmx_pciercx_cfg008_s cn56xxp1;
+        struct cvmx_pciercx_cfg008_s cn63xx;
+        struct cvmx_pciercx_cfg008_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg009 {
@@ -347,6 +290,8 @@ union cvmx_pciercx_cfg009 {
         struct cvmx_pciercx_cfg009_s cn52xxp1;
         struct cvmx_pciercx_cfg009_s cn56xx;
         struct cvmx_pciercx_cfg009_s cn56xxp1;
+        struct cvmx_pciercx_cfg009_s cn63xx;
+        struct cvmx_pciercx_cfg009_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg010 {
@@ -358,6 +303,8 @@ union cvmx_pciercx_cfg010 {
         struct cvmx_pciercx_cfg010_s cn52xxp1;
         struct cvmx_pciercx_cfg010_s cn56xx;
         struct cvmx_pciercx_cfg010_s cn56xxp1;
+        struct cvmx_pciercx_cfg010_s cn63xx;
+        struct cvmx_pciercx_cfg010_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg011 {
@@ -369,6 +316,8 @@ union cvmx_pciercx_cfg011 {
         struct cvmx_pciercx_cfg011_s cn52xxp1;
         struct cvmx_pciercx_cfg011_s cn56xx;
         struct cvmx_pciercx_cfg011_s cn56xxp1;
+        struct cvmx_pciercx_cfg011_s cn63xx;
+        struct cvmx_pciercx_cfg011_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg012 {
@@ -381,6 +330,8 @@ union cvmx_pciercx_cfg012 {
         struct cvmx_pciercx_cfg012_s cn52xxp1;
         struct cvmx_pciercx_cfg012_s cn56xx;
         struct cvmx_pciercx_cfg012_s cn56xxp1;
+        struct cvmx_pciercx_cfg012_s cn63xx;
+        struct cvmx_pciercx_cfg012_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg013 {
@@ -393,6 +344,8 @@ union cvmx_pciercx_cfg013 {
         struct cvmx_pciercx_cfg013_s cn52xxp1;
         struct cvmx_pciercx_cfg013_s cn56xx;
         struct cvmx_pciercx_cfg013_s cn56xxp1;
+        struct cvmx_pciercx_cfg013_s cn63xx;
+        struct cvmx_pciercx_cfg013_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg014 {
@@ -404,6 +357,8 @@ union cvmx_pciercx_cfg014 {
         struct cvmx_pciercx_cfg014_s cn52xxp1;
         struct cvmx_pciercx_cfg014_s cn56xx;
         struct cvmx_pciercx_cfg014_s cn56xxp1;
+        struct cvmx_pciercx_cfg014_s cn63xx;
+        struct cvmx_pciercx_cfg014_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg015 {
@@ -429,6 +384,8 @@ union cvmx_pciercx_cfg015 {
         struct cvmx_pciercx_cfg015_s cn52xxp1;
         struct cvmx_pciercx_cfg015_s cn56xx;
         struct cvmx_pciercx_cfg015_s cn56xxp1;
+        struct cvmx_pciercx_cfg015_s cn63xx;
+        struct cvmx_pciercx_cfg015_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg016 {
@@ -449,6 +406,8 @@ union cvmx_pciercx_cfg016 {
         struct cvmx_pciercx_cfg016_s cn52xxp1;
         struct cvmx_pciercx_cfg016_s cn56xx;
         struct cvmx_pciercx_cfg016_s cn56xxp1;
+        struct cvmx_pciercx_cfg016_s cn63xx;
+        struct cvmx_pciercx_cfg016_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg017 {
@@ -471,6 +430,8 @@ union cvmx_pciercx_cfg017 {
         struct cvmx_pciercx_cfg017_s cn52xxp1;
         struct cvmx_pciercx_cfg017_s cn56xx;
         struct cvmx_pciercx_cfg017_s cn56xxp1;
+        struct cvmx_pciercx_cfg017_s cn63xx;
+        struct cvmx_pciercx_cfg017_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg020 {
@@ -488,6 +449,8 @@ union cvmx_pciercx_cfg020 {
         struct cvmx_pciercx_cfg020_s cn52xxp1;
         struct cvmx_pciercx_cfg020_s cn56xx;
         struct cvmx_pciercx_cfg020_s cn56xxp1;
+        struct cvmx_pciercx_cfg020_s cn63xx;
+        struct cvmx_pciercx_cfg020_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg021 {
@@ -500,6 +463,8 @@ union cvmx_pciercx_cfg021 {
         struct cvmx_pciercx_cfg021_s cn52xxp1;
         struct cvmx_pciercx_cfg021_s cn56xx;
         struct cvmx_pciercx_cfg021_s cn56xxp1;
+        struct cvmx_pciercx_cfg021_s cn63xx;
+        struct cvmx_pciercx_cfg021_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg022 {
@@ -511,6 +476,8 @@ union cvmx_pciercx_cfg022 {
         struct cvmx_pciercx_cfg022_s cn52xxp1;
         struct cvmx_pciercx_cfg022_s cn56xx;
         struct cvmx_pciercx_cfg022_s cn56xxp1;
+        struct cvmx_pciercx_cfg022_s cn63xx;
+        struct cvmx_pciercx_cfg022_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg023 {
@@ -523,6 +490,8 @@ union cvmx_pciercx_cfg023 {
         struct cvmx_pciercx_cfg023_s cn52xxp1;
         struct cvmx_pciercx_cfg023_s cn56xx;
         struct cvmx_pciercx_cfg023_s cn56xxp1;
+        struct cvmx_pciercx_cfg023_s cn63xx;
+        struct cvmx_pciercx_cfg023_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg028 {
@@ -540,6 +509,8 @@ union cvmx_pciercx_cfg028 {
         struct cvmx_pciercx_cfg028_s cn52xxp1;
         struct cvmx_pciercx_cfg028_s cn56xx;
         struct cvmx_pciercx_cfg028_s cn56xxp1;
+        struct cvmx_pciercx_cfg028_s cn63xx;
+        struct cvmx_pciercx_cfg028_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg029 {
@@ -561,6 +532,8 @@ union cvmx_pciercx_cfg029 {
         struct cvmx_pciercx_cfg029_s cn52xxp1;
         struct cvmx_pciercx_cfg029_s cn56xx;
         struct cvmx_pciercx_cfg029_s cn56xxp1;
+        struct cvmx_pciercx_cfg029_s cn63xx;
+        struct cvmx_pciercx_cfg029_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg030 {
@@ -590,6 +563,8 @@ union cvmx_pciercx_cfg030 {
         struct cvmx_pciercx_cfg030_s cn52xxp1;
         struct cvmx_pciercx_cfg030_s cn56xx;
         struct cvmx_pciercx_cfg030_s cn56xxp1;
+        struct cvmx_pciercx_cfg030_s cn63xx;
+        struct cvmx_pciercx_cfg030_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg031 {
@@ -611,6 +586,8 @@ union cvmx_pciercx_cfg031 {
         struct cvmx_pciercx_cfg031_s cn52xxp1;
         struct cvmx_pciercx_cfg031_s cn56xx;
         struct cvmx_pciercx_cfg031_s cn56xxp1;
+        struct cvmx_pciercx_cfg031_s cn63xx;
+        struct cvmx_pciercx_cfg031_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg032 {
@@ -641,6 +618,8 @@ union cvmx_pciercx_cfg032 {
         struct cvmx_pciercx_cfg032_s cn52xxp1;
         struct cvmx_pciercx_cfg032_s cn56xx;
         struct cvmx_pciercx_cfg032_s cn56xxp1;
+        struct cvmx_pciercx_cfg032_s cn63xx;
+        struct cvmx_pciercx_cfg032_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg033 {
@@ -663,6 +642,8 @@ union cvmx_pciercx_cfg033 {
         struct cvmx_pciercx_cfg033_s cn52xxp1;
         struct cvmx_pciercx_cfg033_s cn56xx;
         struct cvmx_pciercx_cfg033_s cn56xxp1;
+        struct cvmx_pciercx_cfg033_s cn63xx;
+        struct cvmx_pciercx_cfg033_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg034 {
@@ -695,6 +676,8 @@ union cvmx_pciercx_cfg034 {
         struct cvmx_pciercx_cfg034_s cn52xxp1;
         struct cvmx_pciercx_cfg034_s cn56xx;
         struct cvmx_pciercx_cfg034_s cn56xxp1;
+        struct cvmx_pciercx_cfg034_s cn63xx;
+        struct cvmx_pciercx_cfg034_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg035 {
@@ -713,6 +696,8 @@ union cvmx_pciercx_cfg035 {
         struct cvmx_pciercx_cfg035_s cn52xxp1;
         struct cvmx_pciercx_cfg035_s cn56xx;
         struct cvmx_pciercx_cfg035_s cn56xxp1;
+        struct cvmx_pciercx_cfg035_s cn63xx;
+        struct cvmx_pciercx_cfg035_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg036 {
@@ -727,6 +712,8 @@ union cvmx_pciercx_cfg036 {
         struct cvmx_pciercx_cfg036_s cn52xxp1;
         struct cvmx_pciercx_cfg036_s cn56xx;
         struct cvmx_pciercx_cfg036_s cn56xxp1;
+        struct cvmx_pciercx_cfg036_s cn63xx;
+        struct cvmx_pciercx_cfg036_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg037 {
@@ -740,6 +727,8 @@ union cvmx_pciercx_cfg037 {
         struct cvmx_pciercx_cfg037_s cn52xxp1;
         struct cvmx_pciercx_cfg037_s cn56xx;
         struct cvmx_pciercx_cfg037_s cn56xxp1;
+        struct cvmx_pciercx_cfg037_s cn63xx;
+        struct cvmx_pciercx_cfg037_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg038 {
@@ -753,28 +742,51 @@ union cvmx_pciercx_cfg038 {
         struct cvmx_pciercx_cfg038_s cn52xxp1;
         struct cvmx_pciercx_cfg038_s cn56xx;
         struct cvmx_pciercx_cfg038_s cn56xxp1;
+        struct cvmx_pciercx_cfg038_s cn63xx;
+        struct cvmx_pciercx_cfg038_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg039 {
         uint32_t u32;
         struct cvmx_pciercx_cfg039_s {
-                uint32_t reserved_0_31:32;
+                uint32_t reserved_9_31:23;
+                uint32_t cls:1;
+                uint32_t slsv:7;
+                uint32_t reserved_0_0:1;
         } s;
-        struct cvmx_pciercx_cfg039_s cn52xx;
-        struct cvmx_pciercx_cfg039_s cn52xxp1;
-        struct cvmx_pciercx_cfg039_s cn56xx;
-        struct cvmx_pciercx_cfg039_s cn56xxp1;
+        struct cvmx_pciercx_cfg039_cn52xx {
+                uint32_t reserved_0_31:32;
+        } cn52xx;
+        struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg039_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg039_s cn63xx;
+        struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
 };
 
 union cvmx_pciercx_cfg040 {
         uint32_t u32;
         struct cvmx_pciercx_cfg040_s {
+                uint32_t reserved_17_31:15;
+                uint32_t cdl:1;
+                uint32_t reserved_13_15:3;
+                uint32_t cde:1;
+                uint32_t csos:1;
+                uint32_t emc:1;
+                uint32_t tm:3;
+                uint32_t sde:1;
+                uint32_t hasd:1;
+                uint32_t ec:1;
+                uint32_t tls:4;
+        } s;
+        struct cvmx_pciercx_cfg040_cn52xx {
                 uint32_t reserved_0_31:32;
-        } s;
-        struct cvmx_pciercx_cfg040_s cn52xx;
-        struct cvmx_pciercx_cfg040_s cn52xxp1;
-        struct cvmx_pciercx_cfg040_s cn56xx;
-        struct cvmx_pciercx_cfg040_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg040_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg040_s cn63xx;
+        struct cvmx_pciercx_cfg040_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg041 {
@@ -786,6 +798,8 @@ union cvmx_pciercx_cfg041 {
         struct cvmx_pciercx_cfg041_s cn52xxp1;
         struct cvmx_pciercx_cfg041_s cn56xx;
         struct cvmx_pciercx_cfg041_s cn56xxp1;
+        struct cvmx_pciercx_cfg041_s cn63xx;
+        struct cvmx_pciercx_cfg041_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg042 {
@@ -797,6 +811,8 @@ union cvmx_pciercx_cfg042 {
         struct cvmx_pciercx_cfg042_s cn52xxp1;
         struct cvmx_pciercx_cfg042_s cn56xx;
         struct cvmx_pciercx_cfg042_s cn56xxp1;
+        struct cvmx_pciercx_cfg042_s cn63xx;
+        struct cvmx_pciercx_cfg042_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg064 {
@@ -810,6 +826,8 @@ union cvmx_pciercx_cfg064 {
         struct cvmx_pciercx_cfg064_s cn52xxp1;
         struct cvmx_pciercx_cfg064_s cn56xx;
         struct cvmx_pciercx_cfg064_s cn56xxp1;
+        struct cvmx_pciercx_cfg064_s cn63xx;
+        struct cvmx_pciercx_cfg064_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg065 {
@@ -834,6 +852,8 @@ union cvmx_pciercx_cfg065 {
         struct cvmx_pciercx_cfg065_s cn52xxp1;
         struct cvmx_pciercx_cfg065_s cn56xx;
         struct cvmx_pciercx_cfg065_s cn56xxp1;
+        struct cvmx_pciercx_cfg065_s cn63xx;
+        struct cvmx_pciercx_cfg065_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg066 {
@@ -858,6 +878,8 @@ union cvmx_pciercx_cfg066 {
         struct cvmx_pciercx_cfg066_s cn52xxp1;
         struct cvmx_pciercx_cfg066_s cn56xx;
         struct cvmx_pciercx_cfg066_s cn56xxp1;
+        struct cvmx_pciercx_cfg066_s cn63xx;
+        struct cvmx_pciercx_cfg066_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg067 {
@@ -882,6 +904,8 @@ union cvmx_pciercx_cfg067 {
         struct cvmx_pciercx_cfg067_s cn52xxp1;
         struct cvmx_pciercx_cfg067_s cn56xx;
         struct cvmx_pciercx_cfg067_s cn56xxp1;
+        struct cvmx_pciercx_cfg067_s cn63xx;
+        struct cvmx_pciercx_cfg067_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg068 {
@@ -901,6 +925,8 @@ union cvmx_pciercx_cfg068 {
         struct cvmx_pciercx_cfg068_s cn52xxp1;
         struct cvmx_pciercx_cfg068_s cn56xx;
         struct cvmx_pciercx_cfg068_s cn56xxp1;
+        struct cvmx_pciercx_cfg068_s cn63xx;
+        struct cvmx_pciercx_cfg068_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg069 {
@@ -920,6 +946,8 @@ union cvmx_pciercx_cfg069 {
         struct cvmx_pciercx_cfg069_s cn52xxp1;
         struct cvmx_pciercx_cfg069_s cn56xx;
         struct cvmx_pciercx_cfg069_s cn56xxp1;
+        struct cvmx_pciercx_cfg069_s cn63xx;
+        struct cvmx_pciercx_cfg069_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg070 {
@@ -936,6 +964,8 @@ union cvmx_pciercx_cfg070 {
         struct cvmx_pciercx_cfg070_s cn52xxp1;
         struct cvmx_pciercx_cfg070_s cn56xx;
         struct cvmx_pciercx_cfg070_s cn56xxp1;
+        struct cvmx_pciercx_cfg070_s cn63xx;
+        struct cvmx_pciercx_cfg070_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg071 {
@@ -947,6 +977,8 @@ union cvmx_pciercx_cfg071 {
         struct cvmx_pciercx_cfg071_s cn52xxp1;
         struct cvmx_pciercx_cfg071_s cn56xx;
         struct cvmx_pciercx_cfg071_s cn56xxp1;
+        struct cvmx_pciercx_cfg071_s cn63xx;
+        struct cvmx_pciercx_cfg071_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg072 {
@@ -958,6 +990,8 @@ union cvmx_pciercx_cfg072 {
         struct cvmx_pciercx_cfg072_s cn52xxp1;
         struct cvmx_pciercx_cfg072_s cn56xx;
         struct cvmx_pciercx_cfg072_s cn56xxp1;
+        struct cvmx_pciercx_cfg072_s cn63xx;
+        struct cvmx_pciercx_cfg072_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg073 {
@@ -969,6 +1003,8 @@ union cvmx_pciercx_cfg073 {
         struct cvmx_pciercx_cfg073_s cn52xxp1;
         struct cvmx_pciercx_cfg073_s cn56xx;
         struct cvmx_pciercx_cfg073_s cn56xxp1;
+        struct cvmx_pciercx_cfg073_s cn63xx;
+        struct cvmx_pciercx_cfg073_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg074 {
@@ -980,6 +1016,8 @@ union cvmx_pciercx_cfg074 {
         struct cvmx_pciercx_cfg074_s cn52xxp1;
         struct cvmx_pciercx_cfg074_s cn56xx;
         struct cvmx_pciercx_cfg074_s cn56xxp1;
+        struct cvmx_pciercx_cfg074_s cn63xx;
+        struct cvmx_pciercx_cfg074_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg075 {
@@ -994,6 +1032,8 @@ union cvmx_pciercx_cfg075 {
         struct cvmx_pciercx_cfg075_s cn52xxp1;
         struct cvmx_pciercx_cfg075_s cn56xx;
         struct cvmx_pciercx_cfg075_s cn56xxp1;
+        struct cvmx_pciercx_cfg075_s cn63xx;
+        struct cvmx_pciercx_cfg075_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg076 {
@@ -1013,6 +1053,8 @@ union cvmx_pciercx_cfg076 {
         struct cvmx_pciercx_cfg076_s cn52xxp1;
         struct cvmx_pciercx_cfg076_s cn56xx;
         struct cvmx_pciercx_cfg076_s cn56xxp1;
+        struct cvmx_pciercx_cfg076_s cn63xx;
+        struct cvmx_pciercx_cfg076_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg077 {
@@ -1025,6 +1067,8 @@ union cvmx_pciercx_cfg077 {
         struct cvmx_pciercx_cfg077_s cn52xxp1;
         struct cvmx_pciercx_cfg077_s cn56xx;
         struct cvmx_pciercx_cfg077_s cn56xxp1;
+        struct cvmx_pciercx_cfg077_s cn63xx;
+        struct cvmx_pciercx_cfg077_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg448 {
@@ -1037,6 +1081,8 @@ union cvmx_pciercx_cfg448 {
         struct cvmx_pciercx_cfg448_s cn52xxp1;
         struct cvmx_pciercx_cfg448_s cn56xx;
         struct cvmx_pciercx_cfg448_s cn56xxp1;
+        struct cvmx_pciercx_cfg448_s cn63xx;
+        struct cvmx_pciercx_cfg448_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg449 {
@@ -1048,6 +1094,8 @@ union cvmx_pciercx_cfg449 {
         struct cvmx_pciercx_cfg449_s cn52xxp1;
         struct cvmx_pciercx_cfg449_s cn56xx;
         struct cvmx_pciercx_cfg449_s cn56xxp1;
+        struct cvmx_pciercx_cfg449_s cn63xx;
+        struct cvmx_pciercx_cfg449_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg450 {
@@ -1064,6 +1112,8 @@ union cvmx_pciercx_cfg450 {
         struct cvmx_pciercx_cfg450_s cn52xxp1;
         struct cvmx_pciercx_cfg450_s cn56xx;
         struct cvmx_pciercx_cfg450_s cn56xxp1;
+        struct cvmx_pciercx_cfg450_s cn63xx;
+        struct cvmx_pciercx_cfg450_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg451 {
@@ -1080,6 +1130,8 @@ union cvmx_pciercx_cfg451 {
         struct cvmx_pciercx_cfg451_s cn52xxp1;
         struct cvmx_pciercx_cfg451_s cn56xx;
         struct cvmx_pciercx_cfg451_s cn56xxp1;
+        struct cvmx_pciercx_cfg451_s cn63xx;
+        struct cvmx_pciercx_cfg451_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg452 {
@@ -1103,6 +1155,8 @@ union cvmx_pciercx_cfg452 {
         struct cvmx_pciercx_cfg452_s cn52xxp1;
         struct cvmx_pciercx_cfg452_s cn56xx;
         struct cvmx_pciercx_cfg452_s cn56xxp1;
+        struct cvmx_pciercx_cfg452_s cn63xx;
+        struct cvmx_pciercx_cfg452_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg453 {
@@ -1118,6 +1172,8 @@ union cvmx_pciercx_cfg453 {
         struct cvmx_pciercx_cfg453_s cn52xxp1;
         struct cvmx_pciercx_cfg453_s cn56xx;
         struct cvmx_pciercx_cfg453_s cn56xxp1;
+        struct cvmx_pciercx_cfg453_s cn63xx;
+        struct cvmx_pciercx_cfg453_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg454 {
@@ -1136,6 +1192,8 @@ union cvmx_pciercx_cfg454 {
         struct cvmx_pciercx_cfg454_s cn52xxp1;
         struct cvmx_pciercx_cfg454_s cn56xx;
         struct cvmx_pciercx_cfg454_s cn56xxp1;
+        struct cvmx_pciercx_cfg454_s cn63xx;
+        struct cvmx_pciercx_cfg454_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg455 {
@@ -1165,6 +1223,8 @@ union cvmx_pciercx_cfg455 {
         struct cvmx_pciercx_cfg455_s cn52xxp1;
         struct cvmx_pciercx_cfg455_s cn56xx;
         struct cvmx_pciercx_cfg455_s cn56xxp1;
+        struct cvmx_pciercx_cfg455_s cn63xx;
+        struct cvmx_pciercx_cfg455_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg456 {
@@ -1178,6 +1238,8 @@ union cvmx_pciercx_cfg456 {
         struct cvmx_pciercx_cfg456_s cn52xxp1;
         struct cvmx_pciercx_cfg456_s cn56xx;
         struct cvmx_pciercx_cfg456_s cn56xxp1;
+        struct cvmx_pciercx_cfg456_s cn63xx;
+        struct cvmx_pciercx_cfg456_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg458 {
@@ -1189,6 +1251,8 @@ union cvmx_pciercx_cfg458 {
         struct cvmx_pciercx_cfg458_s cn52xxp1;
         struct cvmx_pciercx_cfg458_s cn56xx;
         struct cvmx_pciercx_cfg458_s cn56xxp1;
+        struct cvmx_pciercx_cfg458_s cn63xx;
+        struct cvmx_pciercx_cfg458_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg459 {
@@ -1200,6 +1264,8 @@ union cvmx_pciercx_cfg459 {
         struct cvmx_pciercx_cfg459_s cn52xxp1;
         struct cvmx_pciercx_cfg459_s cn56xx;
         struct cvmx_pciercx_cfg459_s cn56xxp1;
+        struct cvmx_pciercx_cfg459_s cn63xx;
+        struct cvmx_pciercx_cfg459_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg460 {
@@ -1213,6 +1279,8 @@ union cvmx_pciercx_cfg460 {
         struct cvmx_pciercx_cfg460_s cn52xxp1;
         struct cvmx_pciercx_cfg460_s cn56xx;
         struct cvmx_pciercx_cfg460_s cn56xxp1;
+        struct cvmx_pciercx_cfg460_s cn63xx;
+        struct cvmx_pciercx_cfg460_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg461 {
@@ -1226,6 +1294,8 @@ union cvmx_pciercx_cfg461 {
         struct cvmx_pciercx_cfg461_s cn52xxp1;
         struct cvmx_pciercx_cfg461_s cn56xx;
         struct cvmx_pciercx_cfg461_s cn56xxp1;
+        struct cvmx_pciercx_cfg461_s cn63xx;
+        struct cvmx_pciercx_cfg461_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg462 {
@@ -1239,6 +1309,8 @@ union cvmx_pciercx_cfg462 {
         struct cvmx_pciercx_cfg462_s cn52xxp1;
         struct cvmx_pciercx_cfg462_s cn56xx;
         struct cvmx_pciercx_cfg462_s cn56xxp1;
+        struct cvmx_pciercx_cfg462_s cn63xx;
+        struct cvmx_pciercx_cfg462_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg463 {
@@ -1253,6 +1325,8 @@ union cvmx_pciercx_cfg463 {
         struct cvmx_pciercx_cfg463_s cn52xxp1;
         struct cvmx_pciercx_cfg463_s cn56xx;
         struct cvmx_pciercx_cfg463_s cn56xxp1;
+        struct cvmx_pciercx_cfg463_s cn63xx;
+        struct cvmx_pciercx_cfg463_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg464 {
@@ -1267,6 +1341,8 @@ union cvmx_pciercx_cfg464 {
         struct cvmx_pciercx_cfg464_s cn52xxp1;
         struct cvmx_pciercx_cfg464_s cn56xx;
         struct cvmx_pciercx_cfg464_s cn56xxp1;
+        struct cvmx_pciercx_cfg464_s cn63xx;
+        struct cvmx_pciercx_cfg464_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg465 {
@@ -1281,6 +1357,8 @@ union cvmx_pciercx_cfg465 {
         struct cvmx_pciercx_cfg465_s cn52xxp1;
         struct cvmx_pciercx_cfg465_s cn56xx;
         struct cvmx_pciercx_cfg465_s cn56xxp1;
+        struct cvmx_pciercx_cfg465_s cn63xx;
+        struct cvmx_pciercx_cfg465_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg466 {
@@ -1298,6 +1376,8 @@ union cvmx_pciercx_cfg466 {
         struct cvmx_pciercx_cfg466_s cn52xxp1;
         struct cvmx_pciercx_cfg466_s cn56xx;
         struct cvmx_pciercx_cfg466_s cn56xxp1;
+        struct cvmx_pciercx_cfg466_s cn63xx;
+        struct cvmx_pciercx_cfg466_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg467 {
@@ -1313,6 +1393,8 @@ union cvmx_pciercx_cfg467 {
         struct cvmx_pciercx_cfg467_s cn52xxp1;
         struct cvmx_pciercx_cfg467_s cn56xx;
         struct cvmx_pciercx_cfg467_s cn56xxp1;
+        struct cvmx_pciercx_cfg467_s cn63xx;
+        struct cvmx_pciercx_cfg467_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg468 {
@@ -1328,6 +1410,8 @@ union cvmx_pciercx_cfg468 {
         struct cvmx_pciercx_cfg468_s cn52xxp1;
         struct cvmx_pciercx_cfg468_s cn56xx;
         struct cvmx_pciercx_cfg468_s cn56xxp1;
+        struct cvmx_pciercx_cfg468_s cn63xx;
+        struct cvmx_pciercx_cfg468_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg490 {
@@ -1342,6 +1426,8 @@ union cvmx_pciercx_cfg490 {
         struct cvmx_pciercx_cfg490_s cn52xxp1;
         struct cvmx_pciercx_cfg490_s cn56xx;
         struct cvmx_pciercx_cfg490_s cn56xxp1;
+        struct cvmx_pciercx_cfg490_s cn63xx;
+        struct cvmx_pciercx_cfg490_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg491 {
@@ -1356,6 +1442,8 @@ union cvmx_pciercx_cfg491 {
         struct cvmx_pciercx_cfg491_s cn52xxp1;
         struct cvmx_pciercx_cfg491_s cn56xx;
         struct cvmx_pciercx_cfg491_s cn56xxp1;
+        struct cvmx_pciercx_cfg491_s cn63xx;
+        struct cvmx_pciercx_cfg491_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg492 {
@@ -1370,6 +1458,23 @@ union cvmx_pciercx_cfg492 {
         struct cvmx_pciercx_cfg492_s cn52xxp1;
         struct cvmx_pciercx_cfg492_s cn56xx;
         struct cvmx_pciercx_cfg492_s cn56xxp1;
+        struct cvmx_pciercx_cfg492_s cn63xx;
+        struct cvmx_pciercx_cfg492_s cn63xxp1;
+};
+
+union cvmx_pciercx_cfg515 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg515_s {
+                uint32_t reserved_21_31:11;
+                uint32_t s_d_e:1;
+                uint32_t ctcrb:1;
+                uint32_t cpyts:1;
+                uint32_t dsc:1;
+                uint32_t le:9;
+                uint32_t n_fts:8;
+        } s;
+        struct cvmx_pciercx_cfg515_s cn63xx;
+        struct cvmx_pciercx_cfg515_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg516 {
@@ -1381,6 +1486,8 @@ union cvmx_pciercx_cfg516 {
         struct cvmx_pciercx_cfg516_s cn52xxp1;
         struct cvmx_pciercx_cfg516_s cn56xx;
         struct cvmx_pciercx_cfg516_s cn56xxp1;
+        struct cvmx_pciercx_cfg516_s cn63xx;
+        struct cvmx_pciercx_cfg516_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg517 {
@@ -1392,6 +1499,8 @@ union cvmx_pciercx_cfg517 {
         struct cvmx_pciercx_cfg517_s cn52xxp1;
         struct cvmx_pciercx_cfg517_s cn56xx;
         struct cvmx_pciercx_cfg517_s cn56xxp1;
+        struct cvmx_pciercx_cfg517_s cn63xx;
+        struct cvmx_pciercx_cfg517_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
index f40cfaf84454..aef84851a94c 100644
--- a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,38 +28,22 @@
 #ifndef __CVMX_PESCX_DEFS_H__
 #define __CVMX_PESCX_DEFS_H__
 
-#define CVMX_PESCX_BIST_STATUS(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_BIST_STATUS2(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CFG_RD(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CFG_WR(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CPL_LUT_VALID(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CTL_STATUS(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CTL_STATUS2(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DBG_INFO(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DBG_INFO_EN(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DIAG_STATUS(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR0_START(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR1_START(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR2_START(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2P_BARX_END(offset, block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2P_BARX_START(offset, block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_TLP_CREDITS(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
 
 union cvmx_pescx_bist_status {
         uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index 5ea5dc571b54..5ab8679d89af 100644
--- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -35,195 +35,191 @@
 #ifndef __CVMX_PEXP_DEFS_H__
 #define __CVMX_PEXP_DEFS_H__
 
-#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_BIST_STATUS \
-         CVMX_ADD_IO_SEG(0x00011F0000008580ull)
-#define CVMX_PEXP_NPEI_BIST_STATUS2 \
-         CVMX_ADD_IO_SEG(0x00011F0000008680ull)
-#define CVMX_PEXP_NPEI_CTL_PORT0 \
-         CVMX_ADD_IO_SEG(0x00011F0000008250ull)
-#define CVMX_PEXP_NPEI_CTL_PORT1 \
-         CVMX_ADD_IO_SEG(0x00011F0000008260ull)
-#define CVMX_PEXP_NPEI_CTL_STATUS \
-         CVMX_ADD_IO_SEG(0x00011F0000008570ull)
-#define CVMX_PEXP_NPEI_CTL_STATUS2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC00ull)
-#define CVMX_PEXP_NPEI_DATA_OUT_CNT \
-         CVMX_ADD_IO_SEG(0x00011F00000085F0ull)
-#define CVMX_PEXP_NPEI_DBG_DATA \
-         CVMX_ADD_IO_SEG(0x00011F0000008510ull)
-#define CVMX_PEXP_NPEI_DBG_SELECT \
-         CVMX_ADD_IO_SEG(0x00011F0000008500ull)
-#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \
-         CVMX_ADD_IO_SEG(0x00011F00000085C0ull)
-#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \
-         CVMX_ADD_IO_SEG(0x00011F00000085D0ull)
-#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMA_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000085E0ull)
-#define CVMX_PEXP_NPEI_DMA_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F00000083A0ull)
-#define CVMX_PEXP_NPEI_INT_A_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000008560ull)
-#define CVMX_PEXP_NPEI_INT_A_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)
-#define CVMX_PEXP_NPEI_INT_A_SUM \
-         CVMX_ADD_IO_SEG(0x00011F0000008550ull)
-#define CVMX_PEXP_NPEI_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000008540ull)
-#define CVMX_PEXP_NPEI_INT_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)
-#define CVMX_PEXP_NPEI_INT_INFO \
-         CVMX_ADD_IO_SEG(0x00011F0000008590ull)
-#define CVMX_PEXP_NPEI_INT_SUM \
-         CVMX_ADD_IO_SEG(0x00011F0000008530ull)
-#define CVMX_PEXP_NPEI_INT_SUM2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)
-#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \
-         CVMX_ADD_IO_SEG(0x00011F0000008600ull)
-#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \
-         CVMX_ADD_IO_SEG(0x00011F0000008610ull)
-#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \
-         CVMX_ADD_IO_SEG(0x00011F00000084F0ull)
-#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12)
-#define CVMX_PEXP_NPEI_MSI_ENB0 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC50ull)
-#define CVMX_PEXP_NPEI_MSI_ENB1 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC60ull)
-#define CVMX_PEXP_NPEI_MSI_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC70ull)
-#define CVMX_PEXP_NPEI_MSI_ENB3 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC80ull)
-#define CVMX_PEXP_NPEI_MSI_RCV0 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC10ull)
-#define CVMX_PEXP_NPEI_MSI_RCV1 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC20ull)
-#define CVMX_PEXP_NPEI_MSI_RCV2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC30ull)
-#define CVMX_PEXP_NPEI_MSI_RCV3 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC40ull)
-#define CVMX_PEXP_NPEI_MSI_RD_MAP \
-         CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \
-         CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD00ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD10ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD20ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD30ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD40ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD50ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD60ull)
-#define CVMX_PEXP_NPEI_MSI_WR_MAP \
-         CVMX_ADD_IO_SEG(0x00011F000000BC90ull)
-#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \
-         CVMX_ADD_IO_SEG(0x00011F000000BD70ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \
-         CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \
-         CVMX_ADD_IO_SEG(0x00011F0000008650ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \
-         CVMX_ADD_IO_SEG(0x00011F0000008660ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \
-         CVMX_ADD_IO_SEG(0x00011F0000008670ull)
-#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKT_CNT_INT \
-         CVMX_ADD_IO_SEG(0x00011F0000009110ull)
-#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000009130ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \
-         CVMX_ADD_IO_SEG(0x00011F00000090B0ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \
-         CVMX_ADD_IO_SEG(0x00011F00000090A0ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \
-         CVMX_ADD_IO_SEG(0x00011F0000009090ull)
-#define CVMX_PEXP_NPEI_PKT_DPADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000009080ull)
-#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F0000009150ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000009000ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \
-         CVMX_ADD_IO_SEG(0x00011F0000009190ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \
-         CVMX_ADD_IO_SEG(0x00011F0000009020ull)
-#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \
-         CVMX_ADD_IO_SEG(0x00011F0000009100ull)
-#define CVMX_PEXP_NPEI_PKT_IN_BP \
-         CVMX_ADD_IO_SEG(0x00011F00000086B0ull)
-#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000086A0ull)
-#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \
-         CVMX_ADD_IO_SEG(0x00011F00000091A0ull)
-#define CVMX_PEXP_NPEI_PKT_IPTR \
-         CVMX_ADD_IO_SEG(0x00011F0000009070ull)
-#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \
-         CVMX_ADD_IO_SEG(0x00011F0000009160ull)
-#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \
-         CVMX_ADD_IO_SEG(0x00011F00000090D0ull)
-#define CVMX_PEXP_NPEI_PKT_OUT_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000009010ull)
-#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \
-         CVMX_ADD_IO_SEG(0x00011F00000090E0ull)
-#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \
-         CVMX_ADD_IO_SEG(0x00011F0000008690ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ES \
-         CVMX_ADD_IO_SEG(0x00011F0000009050ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \
-         CVMX_ADD_IO_SEG(0x00011F0000009180ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_NS \
-         CVMX_ADD_IO_SEG(0x00011F0000009040ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \
-         CVMX_ADD_IO_SEG(0x00011F0000009030ull)
-#define CVMX_PEXP_NPEI_PKT_TIME_INT \
-         CVMX_ADD_IO_SEG(0x00011F0000009120ull)
-#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000009140ull)
-#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \
-         CVMX_ADD_IO_SEG(0x00011F0000008520ull)
-#define CVMX_PEXP_NPEI_SCRATCH_1 \
-         CVMX_ADD_IO_SEG(0x00011F0000008270ull)
-#define CVMX_PEXP_NPEI_STATE1 \
-         CVMX_ADD_IO_SEG(0x00011F0000008620ull)
-#define CVMX_PEXP_NPEI_STATE2 \
-         CVMX_ADD_IO_SEG(0x00011F0000008630ull)
-#define CVMX_PEXP_NPEI_STATE3 \
-         CVMX_ADD_IO_SEG(0x00011F0000008640ull)
-#define CVMX_PEXP_NPEI_WINDOW_CTL \
-         CVMX_ADD_IO_SEG(0x00011F0000008380ull)
+#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
+#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
+#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
+#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
+#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
+#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
+#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
+#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
+#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
+#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
+#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
+#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
+#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
+#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
+#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
+#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
+#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
+#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
+#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
+#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
+#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
+#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
+#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
+#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
+#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
+#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
+#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
+#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
+#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
+#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
+#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
+#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
+#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
+#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
+#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
+#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
+#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
+#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
+#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
+#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
+#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
+#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
+#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
+#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
+#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
+#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
+#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
+#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
+#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
+#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
+#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
+#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
+#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
+#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
+#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
+#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
+#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
+#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
+#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
+#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
+#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
+#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
+#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
+#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
+#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
+#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
+#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
+#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
+#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
+#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
+#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
+#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
+#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
+#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
+#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
+#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
+#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
+#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
+#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
+#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
+#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
+#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
+#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
+#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
+#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
+#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
+#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
+#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
+#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
+#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
+#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
+#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
+#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
+#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
+#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
index 2d82e24be51c..39fd75b03f77 100644
--- a/arch/mips/include/asm/octeon/cvmx-pow-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,52 +28,29 @@
 #ifndef __CVMX_POW_DEFS_H__
 #define __CVMX_POW_DEFS_H__
 
-#define CVMX_POW_BIST_STAT \
-         CVMX_ADD_IO_SEG(0x00016700000003F8ull)
-#define CVMX_POW_DS_PC \
-         CVMX_ADD_IO_SEG(0x0001670000000398ull)
-#define CVMX_POW_ECC_ERR \
-         CVMX_ADD_IO_SEG(0x0001670000000218ull)
-#define CVMX_POW_INT_CTL \
-         CVMX_ADD_IO_SEG(0x0001670000000220ull)
-#define CVMX_POW_IQ_CNTX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000340ull + (((offset) & 7) * 8))
-#define CVMX_POW_IQ_COM_CNT \
-         CVMX_ADD_IO_SEG(0x0001670000000388ull)
-#define CVMX_POW_IQ_INT \
-         CVMX_ADD_IO_SEG(0x0001670000000238ull)
-#define CVMX_POW_IQ_INT_EN \
-         CVMX_ADD_IO_SEG(0x0001670000000240ull)
-#define CVMX_POW_IQ_THRX(offset) \
-         CVMX_ADD_IO_SEG(0x00016700000003A0ull + (((offset) & 7) * 8))
-#define CVMX_POW_NOS_CNT \
-         CVMX_ADD_IO_SEG(0x0001670000000228ull)
-#define CVMX_POW_NW_TIM \
-         CVMX_ADD_IO_SEG(0x0001670000000210ull)
-#define CVMX_POW_PF_RST_MSK \
-         CVMX_ADD_IO_SEG(0x0001670000000230ull)
-#define CVMX_POW_PP_GRP_MSKX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000000ull + (((offset) & 15) * 8))
-#define CVMX_POW_QOS_RNDX(offset) \
-         CVMX_ADD_IO_SEG(0x00016700000001C0ull + (((offset) & 7) * 8))
-#define CVMX_POW_QOS_THRX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000180ull + (((offset) & 7) * 8))
-#define CVMX_POW_TS_PC \
-         CVMX_ADD_IO_SEG(0x0001670000000390ull)
-#define CVMX_POW_WA_COM_PC \
-         CVMX_ADD_IO_SEG(0x0001670000000380ull)
-#define CVMX_POW_WA_PCX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000300ull + (((offset) & 7) * 8))
-#define CVMX_POW_WQ_INT \
-         CVMX_ADD_IO_SEG(0x0001670000000200ull)
-#define CVMX_POW_WQ_INT_CNTX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000100ull + (((offset) & 15) * 8))
-#define CVMX_POW_WQ_INT_PC \
-         CVMX_ADD_IO_SEG(0x0001670000000208ull)
-#define CVMX_POW_WQ_INT_THRX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000080ull + (((offset) & 15) * 8))
-#define CVMX_POW_WS_PCX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000280ull + (((offset) & 15) * 8))
+#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
+#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
+#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
+#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
+#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
+#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
+#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
+#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
+#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
+#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
+#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
+#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
+#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
+#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
+#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
+#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
+#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
+#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
+#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
+#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
+#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
+#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
+#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
 
 union cvmx_pow_bist_stat {
         uint64_t u64;
@@ -160,6 +137,19 @@ union cvmx_pow_bist_stat {
         struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
         struct cvmx_pow_bist_stat_cn38xx cn58xx;
         struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
+        struct cvmx_pow_bist_stat_cn63xx {
+                uint64_t reserved_22_63:42;
+                uint64_t pp:6;
+                uint64_t reserved_12_15:4;
+                uint64_t cam:1;
+                uint64_t nbr:3;
+                uint64_t nbt:4;
+                uint64_t index:1;
+                uint64_t fidx:1;
+                uint64_t pend:1;
+                uint64_t adr:1;
+        } cn63xx;
+        struct cvmx_pow_bist_stat_cn63xx cn63xxp1;
 };
 
 union cvmx_pow_ds_pc {
@@ -179,6 +169,8 @@ union cvmx_pow_ds_pc {
         struct cvmx_pow_ds_pc_s cn56xxp1;
         struct cvmx_pow_ds_pc_s cn58xx;
         struct cvmx_pow_ds_pc_s cn58xxp1;
+        struct cvmx_pow_ds_pc_s cn63xx;
+        struct cvmx_pow_ds_pc_s cn63xxp1;
 };
 
 union cvmx_pow_ecc_err {
@@ -219,6 +211,8 @@ union cvmx_pow_ecc_err {
         struct cvmx_pow_ecc_err_s cn56xxp1;
         struct cvmx_pow_ecc_err_s cn58xx;
         struct cvmx_pow_ecc_err_s cn58xxp1;
+        struct cvmx_pow_ecc_err_s cn63xx;
+        struct cvmx_pow_ecc_err_s cn63xxp1;
 };
 
 union cvmx_pow_int_ctl {
@@ -239,6 +233,8 @@ union cvmx_pow_int_ctl {
         struct cvmx_pow_int_ctl_s cn56xxp1;
         struct cvmx_pow_int_ctl_s cn58xx;
         struct cvmx_pow_int_ctl_s cn58xxp1;
+        struct cvmx_pow_int_ctl_s cn63xx;
+        struct cvmx_pow_int_ctl_s cn63xxp1;
 };
 
 union cvmx_pow_iq_cntx {
@@ -258,6 +254,8 @@ union cvmx_pow_iq_cntx {
         struct cvmx_pow_iq_cntx_s cn56xxp1;
         struct cvmx_pow_iq_cntx_s cn58xx;
         struct cvmx_pow_iq_cntx_s cn58xxp1;
+        struct cvmx_pow_iq_cntx_s cn63xx;
+        struct cvmx_pow_iq_cntx_s cn63xxp1;
 };
 
 union cvmx_pow_iq_com_cnt {
@@ -277,6 +275,8 @@ union cvmx_pow_iq_com_cnt {
         struct cvmx_pow_iq_com_cnt_s cn56xxp1;
         struct cvmx_pow_iq_com_cnt_s cn58xx;
         struct cvmx_pow_iq_com_cnt_s cn58xxp1;
+        struct cvmx_pow_iq_com_cnt_s cn63xx;
+        struct cvmx_pow_iq_com_cnt_s cn63xxp1;
 };
 
 union cvmx_pow_iq_int {
@@ -289,6 +289,8 @@ union cvmx_pow_iq_int {
         struct cvmx_pow_iq_int_s cn52xxp1;
         struct cvmx_pow_iq_int_s cn56xx;
         struct cvmx_pow_iq_int_s cn56xxp1;
+        struct cvmx_pow_iq_int_s cn63xx;
+        struct cvmx_pow_iq_int_s cn63xxp1;
 };
 
 union cvmx_pow_iq_int_en {
@@ -301,6 +303,8 @@ union cvmx_pow_iq_int_en {
         struct cvmx_pow_iq_int_en_s cn52xxp1;
         struct cvmx_pow_iq_int_en_s cn56xx;
         struct cvmx_pow_iq_int_en_s cn56xxp1;
+        struct cvmx_pow_iq_int_en_s cn63xx;
+        struct cvmx_pow_iq_int_en_s cn63xxp1;
 };
 
 union cvmx_pow_iq_thrx {
@@ -313,6 +317,8 @@ union cvmx_pow_iq_thrx {
         struct cvmx_pow_iq_thrx_s cn52xxp1;
         struct cvmx_pow_iq_thrx_s cn56xx;
         struct cvmx_pow_iq_thrx_s cn56xxp1;
+        struct cvmx_pow_iq_thrx_s cn63xx;
+        struct cvmx_pow_iq_thrx_s cn63xxp1;
 };
 
 union cvmx_pow_nos_cnt {
@@ -341,6 +347,11 @@ union cvmx_pow_nos_cnt {
         struct cvmx_pow_nos_cnt_s cn56xxp1;
         struct cvmx_pow_nos_cnt_s cn58xx;
         struct cvmx_pow_nos_cnt_s cn58xxp1;
+        struct cvmx_pow_nos_cnt_cn63xx {
+                uint64_t reserved_11_63:53;
+                uint64_t nos_cnt:11;
+        } cn63xx;
+        struct cvmx_pow_nos_cnt_cn63xx cn63xxp1;
 };
 
 union cvmx_pow_nw_tim {
@@ -360,6 +371,8 @@ union cvmx_pow_nw_tim {
         struct cvmx_pow_nw_tim_s cn56xxp1;
         struct cvmx_pow_nw_tim_s cn58xx;
         struct cvmx_pow_nw_tim_s cn58xxp1;
+        struct cvmx_pow_nw_tim_s cn63xx;
+        struct cvmx_pow_nw_tim_s cn63xxp1;
 };
 
 union cvmx_pow_pf_rst_msk {
@@ -375,6 +388,8 @@ union cvmx_pow_pf_rst_msk {
         struct cvmx_pow_pf_rst_msk_s cn56xxp1;
         struct cvmx_pow_pf_rst_msk_s cn58xx;
         struct cvmx_pow_pf_rst_msk_s cn58xxp1;
+        struct cvmx_pow_pf_rst_msk_s cn63xx;
+        struct cvmx_pow_pf_rst_msk_s cn63xxp1;
 };
 
 union cvmx_pow_pp_grp_mskx {
@@ -405,6 +420,8 @@ union cvmx_pow_pp_grp_mskx {
         struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
         struct cvmx_pow_pp_grp_mskx_s cn58xx;
         struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
+        struct cvmx_pow_pp_grp_mskx_s cn63xx;
+        struct cvmx_pow_pp_grp_mskx_s cn63xxp1;
 };
 
 union cvmx_pow_qos_rndx {
@@ -427,6 +444,8 @@ union cvmx_pow_qos_rndx {
         struct cvmx_pow_qos_rndx_s cn56xxp1;
         struct cvmx_pow_qos_rndx_s cn58xx;
         struct cvmx_pow_qos_rndx_s cn58xxp1;
+        struct cvmx_pow_qos_rndx_s cn63xx;
+        struct cvmx_pow_qos_rndx_s cn63xxp1;
 };
 
 union cvmx_pow_qos_thrx {
@@ -485,6 +504,19 @@ union cvmx_pow_qos_thrx {
         struct cvmx_pow_qos_thrx_s cn56xxp1;
         struct cvmx_pow_qos_thrx_s cn58xx;
         struct cvmx_pow_qos_thrx_s cn58xxp1;
+        struct cvmx_pow_qos_thrx_cn63xx {
+                uint64_t reserved_59_63:5;
+                uint64_t des_cnt:11;
+                uint64_t reserved_47_47:1;
+                uint64_t buf_cnt:11;
+                uint64_t reserved_35_35:1;
+                uint64_t free_cnt:11;
+                uint64_t reserved_22_23:2;
+                uint64_t max_thr:10;
+                uint64_t reserved_10_11:2;
+                uint64_t min_thr:10;
+        } cn63xx;
+        struct cvmx_pow_qos_thrx_cn63xx cn63xxp1;
 };
 
 union cvmx_pow_ts_pc {
@@ -504,6 +536,8 @@ union cvmx_pow_ts_pc {
         struct cvmx_pow_ts_pc_s cn56xxp1;
         struct cvmx_pow_ts_pc_s cn58xx;
         struct cvmx_pow_ts_pc_s cn58xxp1;
+        struct cvmx_pow_ts_pc_s cn63xx;
+        struct cvmx_pow_ts_pc_s cn63xxp1;
 };
 
 union cvmx_pow_wa_com_pc {
@@ -523,6 +557,8 @@ union cvmx_pow_wa_com_pc {
         struct cvmx_pow_wa_com_pc_s cn56xxp1;
         struct cvmx_pow_wa_com_pc_s cn58xx;
         struct cvmx_pow_wa_com_pc_s cn58xxp1;
+        struct cvmx_pow_wa_com_pc_s cn63xx;
+        struct cvmx_pow_wa_com_pc_s cn63xxp1;
 };
 
 union cvmx_pow_wa_pcx {
@@ -542,6 +578,8 @@ union cvmx_pow_wa_pcx {
         struct cvmx_pow_wa_pcx_s cn56xxp1;
         struct cvmx_pow_wa_pcx_s cn58xx;
         struct cvmx_pow_wa_pcx_s cn58xxp1;
+        struct cvmx_pow_wa_pcx_s cn63xx;
+        struct cvmx_pow_wa_pcx_s cn63xxp1;
 };
 
 union cvmx_pow_wq_int {
@@ -562,6 +600,8 @@ union cvmx_pow_wq_int {
         struct cvmx_pow_wq_int_s cn56xxp1;
         struct cvmx_pow_wq_int_s cn58xx;
         struct cvmx_pow_wq_int_s cn58xxp1;
+        struct cvmx_pow_wq_int_s cn63xx;
+        struct cvmx_pow_wq_int_s cn63xxp1;
 };
 
 union cvmx_pow_wq_int_cntx {
@@ -604,6 +644,15 @@ union cvmx_pow_wq_int_cntx {
         struct cvmx_pow_wq_int_cntx_s cn56xxp1;
         struct cvmx_pow_wq_int_cntx_s cn58xx;
         struct cvmx_pow_wq_int_cntx_s cn58xxp1;
+        struct cvmx_pow_wq_int_cntx_cn63xx {
+                uint64_t reserved_28_63:36;
+                uint64_t tc_cnt:4;
+                uint64_t reserved_23_23:1;
+                uint64_t ds_cnt:11;
+                uint64_t reserved_11_11:1;
+                uint64_t iq_cnt:11;
+        } cn63xx;
+        struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1;
 };
 
 union cvmx_pow_wq_int_pc {
@@ -626,6 +675,8 @@ union cvmx_pow_wq_int_pc {
         struct cvmx_pow_wq_int_pc_s cn56xxp1;
         struct cvmx_pow_wq_int_pc_s cn58xx;
         struct cvmx_pow_wq_int_pc_s cn58xxp1;
+        struct cvmx_pow_wq_int_pc_s cn63xx;
+        struct cvmx_pow_wq_int_pc_s cn63xxp1;
 };
 
 union cvmx_pow_wq_int_thrx {
@@ -674,6 +725,16 @@ union cvmx_pow_wq_int_thrx {
         struct cvmx_pow_wq_int_thrx_s cn56xxp1;
         struct cvmx_pow_wq_int_thrx_s cn58xx;
         struct cvmx_pow_wq_int_thrx_s cn58xxp1;
+        struct cvmx_pow_wq_int_thrx_cn63xx {
+                uint64_t reserved_29_63:35;
+                uint64_t tc_en:1;
+                uint64_t tc_thr:4;
+                uint64_t reserved_22_23:2;
+                uint64_t ds_thr:10;
+                uint64_t reserved_10_11:2;
+                uint64_t iq_thr:10;
+        } cn63xx;
+        struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1;
 };
 
 union cvmx_pow_ws_pcx {
@@ -693,6 +754,8 @@ union cvmx_pow_ws_pcx {
         struct cvmx_pow_ws_pcx_s cn56xxp1;
         struct cvmx_pow_ws_pcx_s cn58xx;
         struct cvmx_pow_ws_pcx_s cn58xxp1;
+        struct cvmx_pow_ws_pcx_s cn63xx;
+        struct cvmx_pow_ws_pcx_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
index 4586958c97be..c45da1f35ea7 100644
--- a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -30,10 +30,11 @@
 
 #include <linux/types.h>
 
-#define CVMX_RNM_BIST_STATUS \
-         CVMX_ADD_IO_SEG(0x0001180040000008ull)
-#define CVMX_RNM_CTL_STATUS \
-         CVMX_ADD_IO_SEG(0x0001180040000000ull)
+#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
+#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
+#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
+#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
+#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
 
 union cvmx_rnm_bist_status {
         uint64_t u64;
@@ -53,12 +54,16 @@ union cvmx_rnm_bist_status {
         struct cvmx_rnm_bist_status_s cn56xxp1;
         struct cvmx_rnm_bist_status_s cn58xx;
         struct cvmx_rnm_bist_status_s cn58xxp1;
+        struct cvmx_rnm_bist_status_s cn63xx;
+        struct cvmx_rnm_bist_status_s cn63xxp1;
 };
 
 union cvmx_rnm_ctl_status {
         uint64_t u64;
         struct cvmx_rnm_ctl_status_s {
-                uint64_t reserved_9_63:55;
+                uint64_t reserved_11_63:53;
+                uint64_t eer_lck:1;
+                uint64_t eer_val:1;
                 uint64_t ent_sel:4;
                 uint64_t exp_ent:1;
                 uint64_t rng_rst:1;
@@ -76,13 +81,49 @@ union cvmx_rnm_ctl_status {
         struct cvmx_rnm_ctl_status_cn30xx cn31xx;
         struct cvmx_rnm_ctl_status_cn30xx cn38xx;
         struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
-        struct cvmx_rnm_ctl_status_s cn50xx;
-        struct cvmx_rnm_ctl_status_s cn52xx;
-        struct cvmx_rnm_ctl_status_s cn52xxp1;
-        struct cvmx_rnm_ctl_status_s cn56xx;
-        struct cvmx_rnm_ctl_status_s cn56xxp1;
-        struct cvmx_rnm_ctl_status_s cn58xx;
-        struct cvmx_rnm_ctl_status_s cn58xxp1;
+        struct cvmx_rnm_ctl_status_cn50xx {
+                uint64_t reserved_9_63:55;
+                uint64_t ent_sel:4;
+                uint64_t exp_ent:1;
+                uint64_t rng_rst:1;
+                uint64_t rnm_rst:1;
+                uint64_t rng_en:1;
+                uint64_t ent_en:1;
+        } cn50xx;
+        struct cvmx_rnm_ctl_status_cn50xx cn52xx;
+        struct cvmx_rnm_ctl_status_cn50xx cn52xxp1;
+        struct cvmx_rnm_ctl_status_cn50xx cn56xx;
+        struct cvmx_rnm_ctl_status_cn50xx cn56xxp1;
+        struct cvmx_rnm_ctl_status_cn50xx cn58xx;
+        struct cvmx_rnm_ctl_status_cn50xx cn58xxp1;
+        struct cvmx_rnm_ctl_status_s cn63xx;
+        struct cvmx_rnm_ctl_status_s cn63xxp1;
+};
+
+union cvmx_rnm_eer_dbg {
+        uint64_t u64;
+        struct cvmx_rnm_eer_dbg_s {
+                uint64_t dat:64;
+        } s;
+        struct cvmx_rnm_eer_dbg_s cn63xx;
+        struct cvmx_rnm_eer_dbg_s cn63xxp1;
+};
+
+union cvmx_rnm_eer_key {
+        uint64_t u64;
+        struct cvmx_rnm_eer_key_s {
+                uint64_t key:64;
+        } s;
+        struct cvmx_rnm_eer_key_s cn63xx;
+        struct cvmx_rnm_eer_key_s cn63xxp1;
+};
+
+union cvmx_rnm_serial_num {
+        uint64_t u64;
+        struct cvmx_rnm_serial_num_s {
+                uint64_t dat:64;
+        } s;
+        struct cvmx_rnm_serial_num_s cn63xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
index 9ae45fcbe3e3..4f3c0666e94a 100644
--- a/arch/mips/include/asm/octeon/cvmx-smix-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,16 +28,11 @@
 #ifndef __CVMX_SMIX_DEFS_H__
 #define __CVMX_SMIX_DEFS_H__
 
-#define CVMX_SMIX_CLK(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_CMD(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_EN(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_RD_DAT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_WR_DAT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256)
 
 union cvmx_smix_clk {
         uint64_t u64;
@@ -56,7 +51,8 @@ union cvmx_smix_clk {
         struct cvmx_smix_clk_cn30xx {
                 uint64_t reserved_21_63:43;
                 uint64_t sample_hi:5;
-                uint64_t reserved_14_15:2;
+                uint64_t sample_mode:1;
+                uint64_t reserved_14_14:1;
                 uint64_t clk_idle:1;
                 uint64_t preamble:1;
                 uint64_t sample:4;
@@ -65,23 +61,15 @@ union cvmx_smix_clk {
         struct cvmx_smix_clk_cn30xx cn31xx;
         struct cvmx_smix_clk_cn30xx cn38xx;
         struct cvmx_smix_clk_cn30xx cn38xxp2;
-        struct cvmx_smix_clk_cn50xx {
-                uint64_t reserved_25_63:39;
-                uint64_t mode:1;
-                uint64_t reserved_21_23:3;
-                uint64_t sample_hi:5;
-                uint64_t reserved_14_15:2;
-                uint64_t clk_idle:1;
-                uint64_t preamble:1;
-                uint64_t sample:4;
-                uint64_t phase:8;
-        } cn50xx;
+        struct cvmx_smix_clk_s cn50xx;
         struct cvmx_smix_clk_s cn52xx;
-        struct cvmx_smix_clk_cn50xx cn52xxp1;
+        struct cvmx_smix_clk_s cn52xxp1;
         struct cvmx_smix_clk_s cn56xx;
-        struct cvmx_smix_clk_cn50xx cn56xxp1;
+        struct cvmx_smix_clk_s cn56xxp1;
         struct cvmx_smix_clk_cn30xx cn58xx;
         struct cvmx_smix_clk_cn30xx cn58xxp1;
+        struct cvmx_smix_clk_s cn63xx;
+        struct cvmx_smix_clk_s cn63xxp1;
 };
 
 union cvmx_smix_cmd {
@@ -112,6 +100,8 @@ union cvmx_smix_cmd {
         struct cvmx_smix_cmd_s cn56xxp1;
         struct cvmx_smix_cmd_cn30xx cn58xx;
         struct cvmx_smix_cmd_cn30xx cn58xxp1;
+        struct cvmx_smix_cmd_s cn63xx;
+        struct cvmx_smix_cmd_s cn63xxp1;
 };
 
 union cvmx_smix_en {
@@ -131,6 +121,8 @@ union cvmx_smix_en {
         struct cvmx_smix_en_s cn56xxp1;
         struct cvmx_smix_en_s cn58xx;
         struct cvmx_smix_en_s cn58xxp1;
+        struct cvmx_smix_en_s cn63xx;
+        struct cvmx_smix_en_s cn63xxp1;
 };
 
 union cvmx_smix_rd_dat {
@@ -152,6 +144,8 @@ union cvmx_smix_rd_dat {
         struct cvmx_smix_rd_dat_s cn56xxp1;
         struct cvmx_smix_rd_dat_s cn58xx;
         struct cvmx_smix_rd_dat_s cn58xxp1;
+        struct cvmx_smix_rd_dat_s cn63xx;
+        struct cvmx_smix_rd_dat_s cn63xxp1;
 };
 
 union cvmx_smix_wr_dat {
@@ -173,6 +167,8 @@ union cvmx_smix_wr_dat {
         struct cvmx_smix_wr_dat_s cn56xxp1;
         struct cvmx_smix_wr_dat_s cn58xx;
         struct cvmx_smix_wr_dat_s cn58xxp1;
+        struct cvmx_smix_wr_dat_s cn63xx;
+        struct cvmx_smix_wr_dat_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
new file mode 100644
index 000000000000..594f1b68cd62
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
@@ -0,0 +1,261 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2010 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_UCTLX_TYPEDEFS_H__
+#define __CVMX_UCTLX_TYPEDEFS_H__
+
+#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
+#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
+#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
+#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
+#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
+#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
+#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
+#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
+#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
+#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
+#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
+#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
+#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
+
+union cvmx_uctlx_bist_status {
+        uint64_t u64;
+        struct cvmx_uctlx_bist_status_s {
+                uint64_t reserved_6_63:58;
+                uint64_t data_bis:1;
+                uint64_t desc_bis:1;
+                uint64_t erbm_bis:1;
+                uint64_t orbm_bis:1;
+                uint64_t wrbm_bis:1;
+                uint64_t ppaf_bis:1;
+        } s;
+        struct cvmx_uctlx_bist_status_s       cn63xx;
+        struct cvmx_uctlx_bist_status_s       cn63xxp1;
+};
+
+union cvmx_uctlx_clk_rst_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_clk_rst_ctl_s {
+                uint64_t reserved_25_63:39;
+                uint64_t clear_bist:1;
+                uint64_t start_bist:1;
+                uint64_t ehci_sm:1;
+                uint64_t ohci_clkcktrst:1;
+                uint64_t ohci_sm:1;
+                uint64_t ohci_susp_lgcy:1;
+                uint64_t app_start_clk:1;
+                uint64_t o_clkdiv_rst:1;
+                uint64_t h_clkdiv_byp:1;
+                uint64_t h_clkdiv_rst:1;
+                uint64_t h_clkdiv_en:1;
+                uint64_t o_clkdiv_en:1;
+                uint64_t h_div:4;
+                uint64_t p_refclk_sel:2;
+                uint64_t p_refclk_div:2;
+                uint64_t reserved_4_4:1;
+                uint64_t p_com_on:1;
+                uint64_t p_por:1;
+                uint64_t p_prst:1;
+                uint64_t hrst:1;
+        } s;
+        struct cvmx_uctlx_clk_rst_ctl_s       cn63xx;
+        struct cvmx_uctlx_clk_rst_ctl_s       cn63xxp1;
+};
+
+union cvmx_uctlx_ehci_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_ehci_ctl_s {
+                uint64_t reserved_20_63:44;
+                uint64_t desc_rbm:1;
+                uint64_t reg_nb:1;
+                uint64_t l2c_dc:1;
+                uint64_t l2c_bc:1;
+                uint64_t l2c_0pag:1;
+                uint64_t l2c_stt:1;
+                uint64_t l2c_buff_emod:2;
+                uint64_t l2c_desc_emod:2;
+                uint64_t inv_reg_a2:1;
+                uint64_t ehci_64b_addr_en:1;
+                uint64_t l2c_addr_msb:8;
+        } s;
+        struct cvmx_uctlx_ehci_ctl_s          cn63xx;
+        struct cvmx_uctlx_ehci_ctl_s          cn63xxp1;
+};
+
+union cvmx_uctlx_ehci_fla {
+        uint64_t u64;
+        struct cvmx_uctlx_ehci_fla_s {
+                uint64_t reserved_6_63:58;
+                uint64_t fla:6;
+        } s;
+        struct cvmx_uctlx_ehci_fla_s          cn63xx;
+        struct cvmx_uctlx_ehci_fla_s          cn63xxp1;
+};
+
+union cvmx_uctlx_erto_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_erto_ctl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t to_val:27;
+                uint64_t reserved_0_4:5;
+        } s;
+        struct cvmx_uctlx_erto_ctl_s          cn63xx;
+        struct cvmx_uctlx_erto_ctl_s          cn63xxp1;
+};
+
+union cvmx_uctlx_if_ena {
+        uint64_t u64;
+        struct cvmx_uctlx_if_ena_s {
+                uint64_t reserved_1_63:63;
+                uint64_t en:1;
+        } s;
+        struct cvmx_uctlx_if_ena_s            cn63xx;
+        struct cvmx_uctlx_if_ena_s            cn63xxp1;
+};
+
+union cvmx_uctlx_int_ena {
+        uint64_t u64;
+        struct cvmx_uctlx_int_ena_s {
+                uint64_t reserved_8_63:56;
+                uint64_t ec_ovf_e:1;
+                uint64_t oc_ovf_e:1;
+                uint64_t wb_pop_e:1;
+                uint64_t wb_psh_f:1;
+                uint64_t cf_psh_f:1;
+                uint64_t or_psh_f:1;
+                uint64_t er_psh_f:1;
+                uint64_t pp_psh_f:1;
+        } s;
+        struct cvmx_uctlx_int_ena_s           cn63xx;
+        struct cvmx_uctlx_int_ena_s           cn63xxp1;
+};
+
+union cvmx_uctlx_int_reg {
+        uint64_t u64;
+        struct cvmx_uctlx_int_reg_s {
+                uint64_t reserved_8_63:56;
+                uint64_t ec_ovf_e:1;
+                uint64_t oc_ovf_e:1;
+                uint64_t wb_pop_e:1;
+                uint64_t wb_psh_f:1;
+                uint64_t cf_psh_f:1;
+                uint64_t or_psh_f:1;
+                uint64_t er_psh_f:1;
+                uint64_t pp_psh_f:1;
+        } s;
+        struct cvmx_uctlx_int_reg_s           cn63xx;
+        struct cvmx_uctlx_int_reg_s           cn63xxp1;
+};
+
+union cvmx_uctlx_ohci_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_ohci_ctl_s {
+                uint64_t reserved_19_63:45;
+                uint64_t reg_nb:1;
+                uint64_t l2c_dc:1;
+                uint64_t l2c_bc:1;
+                uint64_t l2c_0pag:1;
+                uint64_t l2c_stt:1;
+                uint64_t l2c_buff_emod:2;
+                uint64_t l2c_desc_emod:2;
+                uint64_t inv_reg_a2:1;
+                uint64_t reserved_8_8:1;
+                uint64_t l2c_addr_msb:8;
+        } s;
+        struct cvmx_uctlx_ohci_ctl_s          cn63xx;
+        struct cvmx_uctlx_ohci_ctl_s          cn63xxp1;
+};
+
+union cvmx_uctlx_orto_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_orto_ctl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t to_val:24;
+                uint64_t reserved_0_7:8;
+        } s;
+        struct cvmx_uctlx_orto_ctl_s          cn63xx;
+        struct cvmx_uctlx_orto_ctl_s          cn63xxp1;
+};
+
+union cvmx_uctlx_ppaf_wm {
+        uint64_t u64;
+        struct cvmx_uctlx_ppaf_wm_s {
+                uint64_t reserved_5_63:59;
+                uint64_t wm:5;
+        } s;
+        struct cvmx_uctlx_ppaf_wm_s           cn63xx;
+        struct cvmx_uctlx_ppaf_wm_s           cn63xxp1;
+};
+
+union cvmx_uctlx_uphy_ctl_status {
+        uint64_t u64;
+        struct cvmx_uctlx_uphy_ctl_status_s {
+                uint64_t reserved_10_63:54;
+                uint64_t bist_done:1;
+                uint64_t bist_err:1;
+                uint64_t hsbist:1;
+                uint64_t fsbist:1;
+                uint64_t lsbist:1;
+                uint64_t siddq:1;
+                uint64_t vtest_en:1;
+                uint64_t uphy_bist:1;
+                uint64_t bist_en:1;
+                uint64_t ate_reset:1;
+        } s;
+        struct cvmx_uctlx_uphy_ctl_status_s   cn63xx;
+        struct cvmx_uctlx_uphy_ctl_status_s   cn63xxp1;
+};
+
+union cvmx_uctlx_uphy_portx_ctl_status {
+        uint64_t u64;
+        struct cvmx_uctlx_uphy_portx_ctl_status_s {
+                uint64_t reserved_43_63:21;
+                uint64_t tdata_out:4;
+                uint64_t txbiststuffenh:1;
+                uint64_t txbiststuffen:1;
+                uint64_t dmpulldown:1;
+                uint64_t dppulldown:1;
+                uint64_t vbusvldext:1;
+                uint64_t portreset:1;
+                uint64_t txhsvxtune:2;
+                uint64_t txvreftune:4;
+                uint64_t txrisetune:1;
+                uint64_t txpreemphasistune:1;
+                uint64_t txfslstune:4;
+                uint64_t sqrxtune:3;
+                uint64_t compdistune:3;
+                uint64_t loop_en:1;
+                uint64_t tclk:1;
+                uint64_t tdata_sel:1;
+                uint64_t taddr_in:4;
+                uint64_t tdata_in:8;
+        } s;
+        struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
+        struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index cf50336eca2e..700f88e31cad 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -35,14 +35,6 @@
 #ifndef __OCTEON_MODEL_H__
 #define __OCTEON_MODEL_H__
 
-/* NOTE: These must match what is checked in common-config.mk */
-/* Defines to represent the different versions of Octeon.  */
-
-/*
- * IMPORTANT: When the default pass is updated for an Octeon Model,
- * the corresponding change must also be made in the oct-sim script.
- */
-
 /*
  * The defines below should be used with the OCTEON_IS_MODEL() macro
  * to determine what model of chip the software is running on.  Models
@@ -71,6 +63,21 @@
 #define OM_IGNORE_MINOR_REVISION  0x08000000
 #define OM_FLAG_MASK              0xff000000
 
+#define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000 /* Match all cn5XXX Octeon models. */
+#define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000 /* Match all cn6XXX Octeon models. */
+
+/*
+ * CN6XXX models with new revision encoding
+ */
+#define OCTEON_CN63XX_PASS1_0   0x000d9000
+#define OCTEON_CN63XX_PASS1_1   0x000d9001
+#define OCTEON_CN63XX_PASS1_2   0x000d9002
+#define OCTEON_CN63XX_PASS2_0   0x000d9008
+
+#define OCTEON_CN63XX           (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN63XX_PASS1_X   (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN63XX_PASS2_X   (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+
 /*
  * CN5XXX models with new revision encoding
  */
@@ -189,6 +196,9 @@
                                  | OM_MATCH_PREVIOUS_MODELS \
                                  | OM_IGNORE_REVISION)
 
+#define OCTEON_CN5XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
+#define OCTEON_CN6XXX           (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
+
 /* The revision byte (low byte) has two different encodings.
  * CN3XXX:
  *
@@ -222,6 +232,7 @@
                                       | OCTEON_58XX_MODEL_MASK)
 #define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
                                           & 0x00fffff8)
+#define OCTEON_5XXX_MODEL_MASK       0x00ff0fc0
 
 #define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
 
@@ -273,6 +284,15 @@ static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
                     __OCTEON_MATCH_MASK__((chip_model), (arg_model),
                                           OCTEON_58XX_MODEL_REV_MASK))
                         return 1;
+
+                if (((arg_model & OM_MATCH_5XXX_FAMILY_MODELS) == OM_MATCH_5XXX_FAMILY_MODELS) &&
+                    ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0))
+                        return 1;
+
+                if (((arg_model & OM_MATCH_6XXX_FAMILY_MODELS) == OM_MATCH_6XXX_FAMILY_MODELS) &&
+                    ((chip_model) >= OCTEON_CN63XX_PASS1_0))
+                        return 1;
+
                 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
                     ((chip_model & OCTEON_58XX_MODEL_MASK) <
                             (arg_model & OCTEON_58XX_MODEL_MASK)))
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 917a6c413b1a..6b34afd0d4e7 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -35,6 +35,7 @@ extern int octeon_is_simulation(void);
 extern int octeon_is_pci_host(void);
 extern int octeon_usb_is_ref_clk(void);
 extern uint64_t octeon_get_clock_rate(void);
+extern u64 octeon_get_io_clock_rate(void);
 extern const char *octeon_board_type_string(void);
 extern const char *octeon_get_pci_interrupts(void);
 extern int octeon_get_southbridge_interrupt(void);
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index ece78043acf6..fba2ba200f58 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -36,6 +36,16 @@ extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
                                      u8 slot, u8 pin);
 
 /*
+ * For PCI (not PCIe) the BAR2 base address.
+ */
+#define OCTEON_BAR2_PCI_ADDRESS 0x8000000000ull
+
+/*
+ * For PCI (not PCIe) the base of the memory mapped by BAR1
+ */
+extern u64 octeon_bar1_pci_phys;
+
+/*
  * The following defines are used when octeon_dma_bar_type =
  * OCTEON_DMA_BAR_TYPE_BIG
  */
diff --git a/arch/mips/include/asm/perf_event.h b/arch/mips/include/asm/perf_event.h
new file mode 100644
index 000000000000..e00007cf8162
--- /dev/null
+++ b/arch/mips/include/asm/perf_event.h
@@ -0,0 +1,25 @@
+/*
+ * linux/arch/mips/include/asm/perf_event.h
+ *
+ * Copyright (C) 2010 MIPS Technologies, Inc.
+ * Author: Deng-Cheng Zhu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MIPS_PERF_EVENT_H__
+#define __MIPS_PERF_EVENT_H__
+
+/*
+ * MIPS performance counters do not raise NMI upon overflow, a regular
+ * interrupt will be signaled. Hence we can do the pending perf event
+ * work at the tail of the irq handler.
+ */
+static inline void
+set_perf_event_pending(void)
+{
+}
+
+#endif /* __MIPS_PERF_EVENT_H__ */
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index f00896087dda..55908fd56b1f 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -113,10 +113,10 @@
 #endif
 #define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
 
-#if PGDIR_SIZE >= TASK_SIZE
+#if PGDIR_SIZE >= TASK_SIZE64
 #define USER_PTRS_PER_PGD       (1)
 #else
-#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
+#define USER_PTRS_PER_PGD       (TASK_SIZE64 / PGDIR_SIZE)
 #endif
 #define FIRST_USER_ADDRESS      0UL
 
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 0d629bb93cbe..ead6928fa6b8 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -50,13 +50,10 @@ extern unsigned int vced_count, vcei_count;
  * so don't change it unless you know what you are doing.
  */
 #define TASK_SIZE       0x7fff8000UL
-#define STACK_TOP       ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
 
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE      ((TASK_SIZE / 3) & ~(PAGE_SIZE))
+#ifdef __KERNEL__
+#define STACK_TOP_MAX   TASK_SIZE
+#endif
 
 #define TASK_IS_32BIT_ADDR 1
 
@@ -71,28 +68,29 @@ extern unsigned int vced_count, vcei_count;
  * 8192EB ...
  */
 #define TASK_SIZE32     0x7fff8000UL
-#define TASK_SIZE       0x10000000000UL
-#define STACK_TOP       \
-        (((test_thread_flag(TIF_32BIT_ADDR) ?                           \
-           TASK_SIZE32 : TASK_SIZE) & PAGE_MASK) - SPECIAL_PAGES_SIZE)
+#define TASK_SIZE64     0x10000000000UL
+#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
+
+#ifdef __KERNEL__
+#define STACK_TOP_MAX   TASK_SIZE64
+#endif
+
 
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE                                              \
-        (test_thread_flag(TIF_32BIT_ADDR) ?                             \
-                PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
 #define TASK_SIZE_OF(tsk)                                               \
-        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
+        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
 
 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
 
 #endif
 
-#ifdef __KERNEL__
-#define STACK_TOP_MAX   TASK_SIZE
-#endif
+#define STACK_TOP       ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
+
 
 #define NUM_FPU_REGS    32
 
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index bb937ccfba1e..6018c80ce37a 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -115,21 +115,19 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
         } else if (kernel_uses_llsc) {
                 unsigned long dummy;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %3                  # xchg_u32      \n"
-                "       .set    mips0                                   \n"
-                "       move    %2, %z4                                 \n"
-                "       .set    mips3                                   \n"
-                "       sc      %2, %1                                  \n"
-                "       beqz    %2, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                : "R" (*m), "Jr" (val)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       ll      %0, %3          # xchg_u32      \n"
+                        "       .set    mips0                           \n"
+                        "       move    %2, %z4                         \n"
+                        "       .set    mips3                           \n"
+                        "       sc      %2, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                        : "R" (*m), "Jr" (val)
+                        : "memory");
+                } while (unlikely(!dummy));
         } else {
                 unsigned long flags;
 
@@ -167,19 +165,17 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
         } else if (kernel_uses_llsc) {
                 unsigned long dummy;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %3                  # xchg_u64      \n"
-                "       move    %2, %z4                                 \n"
-                "       scd     %2, %1                                  \n"
-                "       beqz    %2, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                : "R" (*m), "Jr" (val)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       lld     %0, %3          # xchg_u64      \n"
+                        "       move    %2, %z4                         \n"
+                        "       scd     %2, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                        : "R" (*m), "Jr" (val)
+                        : "memory");
+                } while (unlikely(!dummy));
         } else {
                 unsigned long flags;
 
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 70df9c0d3c5b..d309556cacf8 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -83,6 +83,8 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
 #define THREAD_MASK (THREAD_SIZE - 1UL)
 
+#define STACK_WARN      (THREAD_SIZE / 8)
+
 #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
 
 #ifdef CONFIG_DEBUG_STACK_USAGE
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index c2d53c18fd36..653a412c036c 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -35,7 +35,9 @@
 
 #ifdef CONFIG_64BIT
 
-#define __UA_LIMIT      (- TASK_SIZE)
+extern u64 __ua_limit;
+
+#define __UA_LIMIT      __ua_limit
 
 #define __UA_ADDR       ".dword"
 #define __UA_LA         "dla"
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 80884983270d..22b2e0e38617 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -104,4 +104,6 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)	+= 8250-platform.o
 
 obj-$(CONFIG_MIPS_CPUFREQ)      += cpufreq/
 
+obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o
+
 CPPFLAGS_vmlinux.lds            := $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b1b304ea2128..71620e19827a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -25,6 +25,8 @@
 #include <asm/system.h>
 #include <asm/watch.h>
 #include <asm/spram.h>
+#include <asm/uaccess.h>
+
 /*
  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  * the implementation of the "wait" feature differs between CPU families. This
@@ -181,12 +183,13 @@ void __init check_wait(void)
         case CPU_5KC:
         case CPU_25KF:
         case CPU_PR4450:
-        case CPU_BCM3302:
-        case CPU_BCM6338:
-        case CPU_BCM6348:
-        case CPU_BCM6358:
+        case CPU_BMIPS3300:
+        case CPU_BMIPS4350:
+        case CPU_BMIPS4380:
+        case CPU_BMIPS5000:
         case CPU_CAVIUM_OCTEON:
         case CPU_CAVIUM_OCTEON_PLUS:
+        case CPU_CAVIUM_OCTEON2:
         case CPU_JZRISC:
                 cpu_wait = r4k_wait;
                 break;
@@ -902,33 +905,37 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 {
         decode_configs(c);
         switch (c->processor_id & 0xff00) {
-        case PRID_IMP_BCM3302:
-         /* same as PRID_IMP_BCM6338 */
-                c->cputype = CPU_BCM3302;
-                __cpu_name[cpu] = "Broadcom BCM3302";
-                break;
-        case PRID_IMP_BCM4710:
-                c->cputype = CPU_BCM4710;
-                __cpu_name[cpu] = "Broadcom BCM4710";
-                break;
-        case PRID_IMP_BCM6345:
-                c->cputype = CPU_BCM6345;
-                __cpu_name[cpu] = "Broadcom BCM6345";
+        case PRID_IMP_BMIPS32:
+                c->cputype = CPU_BMIPS32;
+                __cpu_name[cpu] = "Broadcom BMIPS32";
+                break;
+        case PRID_IMP_BMIPS3300:
+        case PRID_IMP_BMIPS3300_ALT:
+        case PRID_IMP_BMIPS3300_BUG:
+                c->cputype = CPU_BMIPS3300;
+                __cpu_name[cpu] = "Broadcom BMIPS3300";
+                break;
+        case PRID_IMP_BMIPS43XX: {
+                int rev = c->processor_id & 0xff;
+
+                if (rev >= PRID_REV_BMIPS4380_LO &&
+                                rev <= PRID_REV_BMIPS4380_HI) {
+                        c->cputype = CPU_BMIPS4380;
+                        __cpu_name[cpu] = "Broadcom BMIPS4380";
+                } else {
+                        c->cputype = CPU_BMIPS4350;
+                        __cpu_name[cpu] = "Broadcom BMIPS4350";
+                }
                 break;
-        case PRID_IMP_BCM6348:
-                c->cputype = CPU_BCM6348;
-                __cpu_name[cpu] = "Broadcom BCM6348";
+        }
+        case PRID_IMP_BMIPS5000:
+                c->cputype = CPU_BMIPS5000;
+                __cpu_name[cpu] = "Broadcom BMIPS5000";
+                c->options |= MIPS_CPU_ULRI;
                 break;
-        case PRID_IMP_BCM4350:
-                switch (c->processor_id & 0xf0) {
-                case PRID_REV_BCM6358:
-                        c->cputype = CPU_BCM6358;
-                        __cpu_name[cpu] = "Broadcom BCM6358";
-                        break;
-                default:
-                        c->cputype = CPU_UNKNOWN;
-                        break;
-                }
+        case PRID_IMP_BMIPS4KC:
+                c->cputype = CPU_4KC;
+                __cpu_name[cpu] = "MIPS 4Kc";
                 break;
         }
 }
@@ -953,6 +960,12 @@ platform:
                 if (cpu == 0)
                         __elf_platform = "octeon";
                 break;
+        case PRID_IMP_CAVIUM_CN63XX:
+                c->cputype = CPU_CAVIUM_OCTEON2;
+                __cpu_name[cpu] = "Cavium Octeon II";
+                if (cpu == 0)
+                        __elf_platform = "octeon2";
+                break;
         default:
                 printk(KERN_INFO "Unknown Octeon chip!\n");
                 c->cputype = CPU_UNKNOWN;
@@ -976,6 +989,12 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
         }
 }
 
+#ifdef CONFIG_64BIT
+/* For use by uaccess.h */
+u64 __ua_limit;
+EXPORT_SYMBOL(__ua_limit);
+#endif
+
 const char *__cpu_name[NR_CPUS];
 const char *__elf_platform;
 
@@ -1053,6 +1072,11 @@ __cpuinit void cpu_probe(void)
                 c->srsets = 1;
 
         cpu_probe_vmbits(c);
+
+#ifdef CONFIG_64BIT
+        if (cpu == 0)
+                __ua_limit = ~((1ull << cpu_vmbits) - 1);
+#endif
 }
 
 __cpuinit void cpu_report(void)
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index c6345f579a8a..4f93db58a79e 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -151,6 +151,29 @@ void __init init_IRQ(void)
 #endif
 }
 
+#ifdef DEBUG_STACKOVERFLOW
+static inline void check_stack_overflow(void)
+{
+        unsigned long sp;
+
+        __asm__ __volatile__("move %0, $sp" : "=r" (sp));
+        sp &= THREAD_MASK;
+
+        /*
+         * Check for stack overflow: is there less than STACK_WARN free?
+         * STACK_WARN is defined as 1/8 of THREAD_SIZE by default.
+         */
+        if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
+                printk("do_IRQ: stack overflow: %ld\n",
+                       sp - sizeof(struct thread_info));
+                dump_stack();
+        }
+}
+#else
+static inline void check_stack_overflow(void) {}
+#endif
+
+
 /*
  * do_IRQ handles all normal device IRQ's (the special
  * SMP cross-CPU interrupts have their own specific
@@ -159,6 +182,7 @@ void __init init_IRQ(void)
 void __irq_entry do_IRQ(unsigned int irq)
 {
         irq_enter();
+        check_stack_overflow();
         __DO_IRQ_SMTC_HOOK(irq);
         generic_handle_irq(irq);
         irq_exit();
diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
new file mode 100644
index 000000000000..2b7f3f703b83
--- /dev/null
+++ b/arch/mips/kernel/perf_event.c
@@ -0,0 +1,601 @@
+/*
+ * Linux performance counter support for MIPS.
+ *
+ * Copyright (C) 2010 MIPS Technologies, Inc.
+ * Author: Deng-Cheng Zhu
+ *
+ * This code is based on the implementation for ARM, which is in turn
+ * based on the sparc64 perf event code and the x86 code. Performance
+ * counter access is based on the MIPS Oprofile code. And the callchain
+ * support references the code of MIPS stacktrace.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/kernel.h>
+#include <linux/perf_event.h>
+#include <linux/uaccess.h>
+
+#include <asm/irq.h>
+#include <asm/irq_regs.h>
+#include <asm/stacktrace.h>
+#include <asm/time.h> /* For perf_irq */
+
+/* These are for 32bit counters. For 64bit ones, define them accordingly. */
+#define MAX_PERIOD      ((1ULL << 32) - 1)
+#define VALID_COUNT     0x7fffffff
+#define TOTAL_BITS      32
+#define HIGHEST_BIT     31
+
+#define MIPS_MAX_HWEVENTS 4
+
+struct cpu_hw_events {
+        /* Array of events on this cpu. */
+        struct perf_event       *events[MIPS_MAX_HWEVENTS];
+
+        /*
+         * Set the bit (indexed by the counter number) when the counter
+         * is used for an event.
+         */
+        unsigned long           used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
+
+        /*
+         * The borrowed MSB for the performance counter. A MIPS performance
+         * counter uses its bit 31 (for 32bit counters) or bit 63 (for 64bit
+         * counters) as a factor of determining whether a counter overflow
+         * should be signaled. So here we use a separate MSB for each
+         * counter to make things easy.
+         */
+        unsigned long           msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
+
+        /*
+         * Software copy of the control register for each performance counter.
+         * MIPS CPUs vary in performance counters. They use this differently,
+         * and even may not use it.
+         */
+        unsigned int            saved_ctrl[MIPS_MAX_HWEVENTS];
+};
+DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
+        .saved_ctrl = {0},
+};
+
+/* The description of MIPS performance events. */
+struct mips_perf_event {
+        unsigned int event_id;
+        /*
+         * MIPS performance counters are indexed starting from 0.
+         * CNTR_EVEN indicates the indexes of the counters to be used are
+         * even numbers.
+         */
+        unsigned int cntr_mask;
+        #define CNTR_EVEN       0x55555555
+        #define CNTR_ODD        0xaaaaaaaa
+#ifdef CONFIG_MIPS_MT_SMP
+        enum {
+                T  = 0,
+                V  = 1,
+                P  = 2,
+        } range;
+#else
+        #define T
+        #define V
+        #define P
+#endif
+};
+
+static struct mips_perf_event raw_event;
+static DEFINE_MUTEX(raw_event_mutex);
+
+#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
+#define C(x) PERF_COUNT_HW_CACHE_##x
+
+struct mips_pmu {
+        const char      *name;
+        int             irq;
+        irqreturn_t     (*handle_irq)(int irq, void *dev);
+        int             (*handle_shared_irq)(void);
+        void            (*start)(void);
+        void            (*stop)(void);
+        int             (*alloc_counter)(struct cpu_hw_events *cpuc,
+                                        struct hw_perf_event *hwc);
+        u64             (*read_counter)(unsigned int idx);
+        void            (*write_counter)(unsigned int idx, u64 val);
+        void            (*enable_event)(struct hw_perf_event *evt, int idx);
+        void            (*disable_event)(int idx);
+        const struct mips_perf_event *(*map_raw_event)(u64 config);
+        const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
+        const struct mips_perf_event (*cache_event_map)
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX];
+        unsigned int    num_counters;
+};
+
+static const struct mips_pmu *mipspmu;
+
+static int
+mipspmu_event_set_period(struct perf_event *event,
+                        struct hw_perf_event *hwc,
+                        int idx)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        s64 left = local64_read(&hwc->period_left);
+        s64 period = hwc->sample_period;
+        int ret = 0;
+        u64 uleft;
+        unsigned long flags;
+
+        if (unlikely(left <= -period)) {
+                left = period;
+                local64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+
+        if (unlikely(left <= 0)) {
+                left += period;
+                local64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+
+        if (left > (s64)MAX_PERIOD)
+                left = MAX_PERIOD;
+
+        local64_set(&hwc->prev_count, (u64)-left);
+
+        local_irq_save(flags);
+        uleft = (u64)(-left) & MAX_PERIOD;
+        uleft > VALID_COUNT ?
+                set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs);
+        mipspmu->write_counter(idx, (u64)(-left) & VALID_COUNT);
+        local_irq_restore(flags);
+
+        perf_event_update_userpage(event);
+
+        return ret;
+}
+
+static int mipspmu_enable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx;
+        int err = 0;
+
+        /* To look for a free counter for this event. */
+        idx = mipspmu->alloc_counter(cpuc, hwc);
+        if (idx < 0) {
+                err = idx;
+                goto out;
+        }
+
+        /*
+         * If there is an event in the counter we are going to use then
+         * make sure it is disabled.
+         */
+        event->hw.idx = idx;
+        mipspmu->disable_event(idx);
+        cpuc->events[idx] = event;
+
+        /* Set the period for the event. */
+        mipspmu_event_set_period(event, hwc, idx);
+
+        /* Enable the event. */
+        mipspmu->enable_event(hwc, idx);
+
+        /* Propagate our changes to the userspace mapping. */
+        perf_event_update_userpage(event);
+
+out:
+        return err;
+}
+
+static void mipspmu_event_update(struct perf_event *event,
+                        struct hw_perf_event *hwc,
+                        int idx)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        unsigned long flags;
+        int shift = 64 - TOTAL_BITS;
+        s64 prev_raw_count, new_raw_count;
+        s64 delta;
+
+again:
+        prev_raw_count = local64_read(&hwc->prev_count);
+        local_irq_save(flags);
+        /* Make the counter value be a "real" one. */
+        new_raw_count = mipspmu->read_counter(idx);
+        if (new_raw_count & (test_bit(idx, cpuc->msbs) << HIGHEST_BIT)) {
+                new_raw_count &= VALID_COUNT;
+                clear_bit(idx, cpuc->msbs);
+        } else
+                new_raw_count |= (test_bit(idx, cpuc->msbs) << HIGHEST_BIT);
+        local_irq_restore(flags);
+
+        if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                                new_raw_count) != prev_raw_count)
+                goto again;
+
+        delta = (new_raw_count << shift) - (prev_raw_count << shift);
+        delta >>= shift;
+
+        local64_add(delta, &event->count);
+        local64_sub(delta, &hwc->period_left);
+
+        return;
+}
+
+static void mipspmu_disable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+
+        WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+        /* We are working on a local event. */
+        mipspmu->disable_event(idx);
+
+        barrier();
+
+        mipspmu_event_update(event, hwc, idx);
+        cpuc->events[idx] = NULL;
+        clear_bit(idx, cpuc->used_mask);
+
+        perf_event_update_userpage(event);
+}
+
+static void mipspmu_unthrottle(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        mipspmu->enable_event(hwc, hwc->idx);
+}
+
+static void mipspmu_read(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        /* Don't read disabled counters! */
+        if (hwc->idx < 0)
+                return;
+
+        mipspmu_event_update(event, hwc, hwc->idx);
+}
+
+static struct pmu pmu = {
+        .enable         = mipspmu_enable,
+        .disable        = mipspmu_disable,
+        .unthrottle     = mipspmu_unthrottle,
+        .read           = mipspmu_read,
+};
+
+static atomic_t active_events = ATOMIC_INIT(0);
+static DEFINE_MUTEX(pmu_reserve_mutex);
+static int (*save_perf_irq)(void);
+
+static int mipspmu_get_irq(void)
+{
+        int err;
+
+        if (mipspmu->irq >= 0) {
+                /* Request my own irq handler. */
+                err = request_irq(mipspmu->irq, mipspmu->handle_irq,
+                        IRQF_DISABLED | IRQF_NOBALANCING,
+                        "mips_perf_pmu", NULL);
+                if (err) {
+                        pr_warning("Unable to request IRQ%d for MIPS "
+                           "performance counters!\n", mipspmu->irq);
+                }
+        } else if (cp0_perfcount_irq < 0) {
+                /*
+                 * We are sharing the irq number with the timer interrupt.
+                 */
+                save_perf_irq = perf_irq;
+                perf_irq = mipspmu->handle_shared_irq;
+                err = 0;
+        } else {
+                pr_warning("The platform hasn't properly defined its "
+                        "interrupt controller.\n");
+                err = -ENOENT;
+        }
+
+        return err;
+}
+
+static void mipspmu_free_irq(void)
+{
+        if (mipspmu->irq >= 0)
+                free_irq(mipspmu->irq, NULL);
+        else if (cp0_perfcount_irq < 0)
+                perf_irq = save_perf_irq;
+}
+
+static inline unsigned int
+mipspmu_perf_event_encode(const struct mips_perf_event *pev)
+{
+/*
+ * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
+ * event_id.
+ */
+#ifdef CONFIG_MIPS_MT_SMP
+        return ((unsigned int)pev->range << 24) |
+                (pev->cntr_mask & 0xffff00) |
+                (pev->event_id & 0xff);
+#else
+        return (pev->cntr_mask & 0xffff00) |
+                (pev->event_id & 0xff);
+#endif
+}
+
+static const struct mips_perf_event *
+mipspmu_map_general_event(int idx)
+{
+        const struct mips_perf_event *pev;
+
+        pev = ((*mipspmu->general_event_map)[idx].event_id ==
+                UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
+                &(*mipspmu->general_event_map)[idx]);
+
+        return pev;
+}
+
+static const struct mips_perf_event *
+mipspmu_map_cache_event(u64 config)
+{
+        unsigned int cache_type, cache_op, cache_result;
+        const struct mips_perf_event *pev;
+
+        cache_type = (config >> 0) & 0xff;
+        if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
+                return ERR_PTR(-EINVAL);
+
+        cache_op = (config >> 8) & 0xff;
+        if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
+                return ERR_PTR(-EINVAL);
+
+        cache_result = (config >> 16) & 0xff;
+        if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+                return ERR_PTR(-EINVAL);
+
+        pev = &((*mipspmu->cache_event_map)
+                                        [cache_type]
+                                        [cache_op]
+                                        [cache_result]);
+
+        if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID)
+                return ERR_PTR(-EOPNOTSUPP);
+
+        return pev;
+
+}
+
+static int validate_event(struct cpu_hw_events *cpuc,
+               struct perf_event *event)
+{
+        struct hw_perf_event fake_hwc = event->hw;
+
+        if (event->pmu && event->pmu != &pmu)
+                return 0;
+
+        return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0;
+}
+
+static int validate_group(struct perf_event *event)
+{
+        struct perf_event *sibling, *leader = event->group_leader;
+        struct cpu_hw_events fake_cpuc;
+
+        memset(&fake_cpuc, 0, sizeof(fake_cpuc));
+
+        if (!validate_event(&fake_cpuc, leader))
+                return -ENOSPC;
+
+        list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+                if (!validate_event(&fake_cpuc, sibling))
+                        return -ENOSPC;
+        }
+
+        if (!validate_event(&fake_cpuc, event))
+                return -ENOSPC;
+
+        return 0;
+}
+
+/*
+ * mipsxx/rm9000/loongson2 have different performance counters, they have
+ * specific low-level init routines.
+ */
+static void reset_counters(void *arg);
+static int __hw_perf_event_init(struct perf_event *event);
+
+static void hw_perf_event_destroy(struct perf_event *event)
+{
+        if (atomic_dec_and_mutex_lock(&active_events,
+                                &pmu_reserve_mutex)) {
+                /*
+                 * We must not call the destroy function with interrupts
+                 * disabled.
+                 */
+                on_each_cpu(reset_counters,
+                        (void *)(long)mipspmu->num_counters, 1);
+                mipspmu_free_irq();
+                mutex_unlock(&pmu_reserve_mutex);
+        }
+}
+
+const struct pmu *hw_perf_event_init(struct perf_event *event)
+{
+        int err = 0;
+
+        if (!mipspmu || event->cpu >= nr_cpumask_bits ||
+                (event->cpu >= 0 && !cpu_online(event->cpu)))
+                return ERR_PTR(-ENODEV);
+
+        if (!atomic_inc_not_zero(&active_events)) {
+                if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
+                        atomic_dec(&active_events);
+                        return ERR_PTR(-ENOSPC);
+                }
+
+                mutex_lock(&pmu_reserve_mutex);
+                if (atomic_read(&active_events) == 0)
+                        err = mipspmu_get_irq();
+
+                if (!err)
+                        atomic_inc(&active_events);
+                mutex_unlock(&pmu_reserve_mutex);
+        }
+
+        if (err)
+                return ERR_PTR(err);
+
+        err = __hw_perf_event_init(event);
+        if (err)
+                hw_perf_event_destroy(event);
+
+        return err ? ERR_PTR(err) : &pmu;
+}
+
+void hw_perf_enable(void)
+{
+        if (mipspmu)
+                mipspmu->start();
+}
+
+void hw_perf_disable(void)
+{
+        if (mipspmu)
+                mipspmu->stop();
+}
+
+/* This is needed by specific irq handlers in perf_event_*.c */
+static void
+handle_associated_event(struct cpu_hw_events *cpuc,
+        int idx, struct perf_sample_data *data, struct pt_regs *regs)
+{
+        struct perf_event *event = cpuc->events[idx];
+        struct hw_perf_event *hwc = &event->hw;
+
+        mipspmu_event_update(event, hwc, idx);
+        data->period = event->hw.last_period;
+        if (!mipspmu_event_set_period(event, hwc, idx))
+                return;
+
+        if (perf_event_overflow(event, 0, data, regs))
+                mipspmu->disable_event(idx);
+}
+
+#include "perf_event_mipsxx.c"
+
+/* Callchain handling code. */
+static inline void
+callchain_store(struct perf_callchain_entry *entry,
+                u64 ip)
+{
+        if (entry->nr < PERF_MAX_STACK_DEPTH)
+                entry->ip[entry->nr++] = ip;
+}
+
+/*
+ * Leave userspace callchain empty for now. When we find a way to trace
+ * the user stack callchains, we add here.
+ */
+static void
+perf_callchain_user(struct pt_regs *regs,
+                    struct perf_callchain_entry *entry)
+{
+}
+
+static void save_raw_perf_callchain(struct perf_callchain_entry *entry,
+        unsigned long reg29)
+{
+        unsigned long *sp = (unsigned long *)reg29;
+        unsigned long addr;
+
+        while (!kstack_end(sp)) {
+                addr = *sp++;
+                if (__kernel_text_address(addr)) {
+                        callchain_store(entry, addr);
+                        if (entry->nr >= PERF_MAX_STACK_DEPTH)
+                                break;
+                }
+        }
+}
+
+static void
+perf_callchain_kernel(struct pt_regs *regs,
+                      struct perf_callchain_entry *entry)
+{
+        unsigned long sp = regs->regs[29];
+#ifdef CONFIG_KALLSYMS
+        unsigned long ra = regs->regs[31];
+        unsigned long pc = regs->cp0_epc;
+
+        callchain_store(entry, PERF_CONTEXT_KERNEL);
+        if (raw_show_trace || !__kernel_text_address(pc)) {
+                unsigned long stack_page =
+                        (unsigned long)task_stack_page(current);
+                if (stack_page && sp >= stack_page &&
+                    sp <= stack_page + THREAD_SIZE - 32)
+                        save_raw_perf_callchain(entry, sp);
+                return;
+        }
+        do {
+                callchain_store(entry, pc);
+                if (entry->nr >= PERF_MAX_STACK_DEPTH)
+                        break;
+                pc = unwind_stack(current, &sp, pc, &ra);
+        } while (pc);
+#else
+        callchain_store(entry, PERF_CONTEXT_KERNEL);
+        save_raw_perf_callchain(entry, sp);
+#endif
+}
+
+static void
+perf_do_callchain(struct pt_regs *regs,
+                  struct perf_callchain_entry *entry)
+{
+        int is_user;
+
+        if (!regs)
+                return;
+
+        is_user = user_mode(regs);
+
+        if (!current || !current->pid)
+                return;
+
+        if (is_user && current->state != TASK_RUNNING)
+                return;
+
+        if (!is_user) {
+                perf_callchain_kernel(regs, entry);
+                if (current->mm)
+                        regs = task_pt_regs(current);
+                else
+                        regs = NULL;
+        }
+        if (regs)
+                perf_callchain_user(regs, entry);
+}
+
+static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
+
+struct perf_callchain_entry *
+perf_callchain(struct pt_regs *regs)
+{
+        struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry);
+
+        entry->nr = 0;
+        perf_do_callchain(regs, entry);
+        return entry;
+}
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
new file mode 100644
index 000000000000..5c7c6fc07565
--- /dev/null
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -0,0 +1,1052 @@
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \
+    defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1)
+
+#define M_CONFIG1_PC    (1 << 4)
+
+#define M_PERFCTL_EXL                   (1UL      <<  0)
+#define M_PERFCTL_KERNEL                (1UL      <<  1)
+#define M_PERFCTL_SUPERVISOR            (1UL      <<  2)
+#define M_PERFCTL_USER                  (1UL      <<  3)
+#define M_PERFCTL_INTERRUPT_ENABLE      (1UL      <<  4)
+#define M_PERFCTL_EVENT(event)          (((event) & 0x3ff)  << 5)
+#define M_PERFCTL_VPEID(vpe)            ((vpe)    << 16)
+#define M_PERFCTL_MT_EN(filter)         ((filter) << 20)
+#define    M_TC_EN_ALL                  M_PERFCTL_MT_EN(0)
+#define    M_TC_EN_VPE                  M_PERFCTL_MT_EN(1)
+#define    M_TC_EN_TC                   M_PERFCTL_MT_EN(2)
+#define M_PERFCTL_TCID(tcid)            ((tcid)   << 22)
+#define M_PERFCTL_WIDE                  (1UL      << 30)
+#define M_PERFCTL_MORE                  (1UL      << 31)
+
+#define M_PERFCTL_COUNT_EVENT_WHENEVER  (M_PERFCTL_EXL |                \
+                                        M_PERFCTL_KERNEL |              \
+                                        M_PERFCTL_USER |                \
+                                        M_PERFCTL_SUPERVISOR |          \
+                                        M_PERFCTL_INTERRUPT_ENABLE)
+
+#ifdef CONFIG_MIPS_MT_SMP
+#define M_PERFCTL_CONFIG_MASK           0x3fff801f
+#else
+#define M_PERFCTL_CONFIG_MASK           0x1f
+#endif
+#define M_PERFCTL_EVENT_MASK            0xfe0
+
+#define M_COUNTER_OVERFLOW              (1UL      << 31)
+
+#ifdef CONFIG_MIPS_MT_SMP
+static int cpu_has_mipsmt_pertccounters;
+
+/*
+ * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
+ * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
+ */
+#if defined(CONFIG_HW_PERF_EVENTS)
+#define vpe_id()        (cpu_has_mipsmt_pertccounters ? \
+                        0 : smp_processor_id())
+#else
+#define vpe_id()        (cpu_has_mipsmt_pertccounters ? \
+                        0 : cpu_data[smp_processor_id()].vpe_id)
+#endif
+
+/* Copied from op_model_mipsxx.c */
+static inline unsigned int vpe_shift(void)
+{
+        if (num_possible_cpus() > 1)
+                return 1;
+
+        return 0;
+}
+#else /* !CONFIG_MIPS_MT_SMP */
+#define vpe_id()        0
+
+static inline unsigned int vpe_shift(void)
+{
+        return 0;
+}
+#endif /* CONFIG_MIPS_MT_SMP */
+
+static inline unsigned int
+counters_total_to_per_cpu(unsigned int counters)
+{
+        return counters >> vpe_shift();
+}
+
+static inline unsigned int
+counters_per_cpu_to_total(unsigned int counters)
+{
+        return counters << vpe_shift();
+}
+
+#define __define_perf_accessors(r, n, np)                               \
+                                                                        \
+static inline unsigned int r_c0_ ## r ## n(void)                        \
+{                                                                       \
+        unsigned int cpu = vpe_id();                                    \
+                                                                        \
+        switch (cpu) {                                                  \
+        case 0:                                                         \
+                return read_c0_ ## r ## n();                            \
+        case 1:                                                         \
+                return read_c0_ ## r ## np();                           \
+        default:                                                        \
+                BUG();                                                  \
+        }                                                               \
+        return 0;                                                       \
+}                                                                       \
+                                                                        \
+static inline void w_c0_ ## r ## n(unsigned int value)                  \
+{                                                                       \
+        unsigned int cpu = vpe_id();                                    \
+                                                                        \
+        switch (cpu) {                                                  \
+        case 0:                                                         \
+                write_c0_ ## r ## n(value);                             \
+                return;                                                 \
+        case 1:                                                         \
+                write_c0_ ## r ## np(value);                            \
+                return;                                                 \
+        default:                                                        \
+                BUG();                                                  \
+        }                                                               \
+        return;                                                         \
+}                                                                       \
+
+__define_perf_accessors(perfcntr, 0, 2)
+__define_perf_accessors(perfcntr, 1, 3)
+__define_perf_accessors(perfcntr, 2, 0)
+__define_perf_accessors(perfcntr, 3, 1)
+
+__define_perf_accessors(perfctrl, 0, 2)
+__define_perf_accessors(perfctrl, 1, 3)
+__define_perf_accessors(perfctrl, 2, 0)
+__define_perf_accessors(perfctrl, 3, 1)
+
+static inline int __n_counters(void)
+{
+        if (!(read_c0_config1() & M_CONFIG1_PC))
+                return 0;
+        if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
+                return 1;
+        if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
+                return 2;
+        if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
+                return 3;
+
+        return 4;
+}
+
+static inline int n_counters(void)
+{
+        int counters;
+
+        switch (current_cpu_type()) {
+        case CPU_R10000:
+                counters = 2;
+                break;
+
+        case CPU_R12000:
+        case CPU_R14000:
+                counters = 4;
+                break;
+
+        default:
+                counters = __n_counters();
+        }
+
+        return counters;
+}
+
+static void reset_counters(void *arg)
+{
+        int counters = (int)(long)arg;
+        switch (counters) {
+        case 4:
+                w_c0_perfctrl3(0);
+                w_c0_perfcntr3(0);
+        case 3:
+                w_c0_perfctrl2(0);
+                w_c0_perfcntr2(0);
+        case 2:
+                w_c0_perfctrl1(0);
+                w_c0_perfcntr1(0);
+        case 1:
+                w_c0_perfctrl0(0);
+                w_c0_perfcntr0(0);
+        }
+}
+
+static inline u64
+mipsxx_pmu_read_counter(unsigned int idx)
+{
+        switch (idx) {
+        case 0:
+                return r_c0_perfcntr0();
+        case 1:
+                return r_c0_perfcntr1();
+        case 2:
+                return r_c0_perfcntr2();
+        case 3:
+                return r_c0_perfcntr3();
+        default:
+                WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
+                return 0;
+        }
+}
+
+static inline void
+mipsxx_pmu_write_counter(unsigned int idx, u64 val)
+{
+        switch (idx) {
+        case 0:
+                w_c0_perfcntr0(val);
+                return;
+        case 1:
+                w_c0_perfcntr1(val);
+                return;
+        case 2:
+                w_c0_perfcntr2(val);
+                return;
+        case 3:
+                w_c0_perfcntr3(val);
+                return;
+        }
+}
+
+static inline unsigned int
+mipsxx_pmu_read_control(unsigned int idx)
+{
+        switch (idx) {
+        case 0:
+                return r_c0_perfctrl0();
+        case 1:
+                return r_c0_perfctrl1();
+        case 2:
+                return r_c0_perfctrl2();
+        case 3:
+                return r_c0_perfctrl3();
+        default:
+                WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
+                return 0;
+        }
+}
+
+static inline void
+mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
+{
+        switch (idx) {
+        case 0:
+                w_c0_perfctrl0(val);
+                return;
+        case 1:
+                w_c0_perfctrl1(val);
+                return;
+        case 2:
+                w_c0_perfctrl2(val);
+                return;
+        case 3:
+                w_c0_perfctrl3(val);
+                return;
+        }
+}
+
+#ifdef CONFIG_MIPS_MT_SMP
+static DEFINE_RWLOCK(pmuint_rwlock);
+#endif
+
+/* 24K/34K/1004K cores can share the same event map. */
+static const struct mips_perf_event mipsxxcore_event_map
+                                [PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
+        [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
+        [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
+        [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
+        [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
+        [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
+};
+
+/* 74K core has different branch event code. */
+static const struct mips_perf_event mipsxx74Kcore_event_map
+                                [PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
+        [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
+        [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
+        [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
+        [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
+        [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
+};
+
+/* 24K/34K/1004K cores can share the same cache event map. */
+static const struct mips_perf_event mipsxxcore_cache_map
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+        /*
+         * Like some other architectures (e.g. ARM), the performance
+         * counters don't differentiate between read and write
+         * accesses/misses, so this isn't strictly correct, but it's the
+         * best we can do. Writes and reads get combined.
+         */
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x0a, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x0a, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(L1I)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x09, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x09, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x09, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x09, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { 0x14, CNTR_EVEN, T },
+                /*
+                 * Note that MIPS has only "hit" events countable for
+                 * the prefetch operation.
+                 */
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(LL)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x15, CNTR_ODD, P },
+                [C(RESULT_MISS)]        = { 0x16, CNTR_EVEN, P },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x15, CNTR_ODD, P },
+                [C(RESULT_MISS)]        = { 0x16, CNTR_EVEN, P },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(DTLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(ITLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x05, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x05, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x05, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x05, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(BPU)] = {
+        /* Using the same code for *HW_BRANCH* */
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+};
+
+/* 74K core has completely different cache event map. */
+static const struct mips_perf_event mipsxx74Kcore_cache_map
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+        /*
+         * Like some other architectures (e.g. ARM), the performance
+         * counters don't differentiate between read and write
+         * accesses/misses, so this isn't strictly correct, but it's the
+         * best we can do. Writes and reads get combined.
+         */
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x17, CNTR_ODD, T },
+                [C(RESULT_MISS)]        = { 0x18, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x17, CNTR_ODD, T },
+                [C(RESULT_MISS)]        = { 0x18, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(L1I)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { 0x34, CNTR_EVEN, T },
+                /*
+                 * Note that MIPS has only "hit" events countable for
+                 * the prefetch operation.
+                 */
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(LL)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
+                [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
+                [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(DTLB)] = {
+        /* 74K core does not have specific DTLB events. */
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(ITLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x04, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x04, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(BPU)] = {
+        /* Using the same code for *HW_BRANCH* */
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x27, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x27, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x27, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x27, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+};
+
+#ifdef CONFIG_MIPS_MT_SMP
+static void
+check_and_calc_range(struct perf_event *event,
+                        const struct mips_perf_event *pev)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        if (event->cpu >= 0) {
+                if (pev->range > V) {
+                        /*
+                         * The user selected an event that is processor
+                         * wide, while expecting it to be VPE wide.
+                         */
+                        hwc->config_base |= M_TC_EN_ALL;
+                } else {
+                        /*
+                         * FIXME: cpu_data[event->cpu].vpe_id reports 0
+                         * for both CPUs.
+                         */
+                        hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
+                        hwc->config_base |= M_TC_EN_VPE;
+                }
+        } else
+                hwc->config_base |= M_TC_EN_ALL;
+}
+#else
+static void
+check_and_calc_range(struct perf_event *event,
+                        const struct mips_perf_event *pev)
+{
+}
+#endif
+
+static int __hw_perf_event_init(struct perf_event *event)
+{
+        struct perf_event_attr *attr = &event->attr;
+        struct hw_perf_event *hwc = &event->hw;
+        const struct mips_perf_event *pev;
+        int err;
+
+        /* Returning MIPS event descriptor for generic perf event. */
+        if (PERF_TYPE_HARDWARE == event->attr.type) {
+                if (event->attr.config >= PERF_COUNT_HW_MAX)
+                        return -EINVAL;
+                pev = mipspmu_map_general_event(event->attr.config);
+        } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
+                pev = mipspmu_map_cache_event(event->attr.config);
+        } else if (PERF_TYPE_RAW == event->attr.type) {
+                /* We are working on the global raw event. */
+                mutex_lock(&raw_event_mutex);
+                pev = mipspmu->map_raw_event(event->attr.config);
+        } else {
+                /* The event type is not (yet) supported. */
+                return -EOPNOTSUPP;
+        }
+
+        if (IS_ERR(pev)) {
+                if (PERF_TYPE_RAW == event->attr.type)
+                        mutex_unlock(&raw_event_mutex);
+                return PTR_ERR(pev);
+        }
+
+        /*
+         * We allow max flexibility on how each individual counter shared
+         * by the single CPU operates (the mode exclusion and the range).
+         */
+        hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
+
+        /* Calculate range bits and validate it. */
+        if (num_possible_cpus() > 1)
+                check_and_calc_range(event, pev);
+
+        hwc->event_base = mipspmu_perf_event_encode(pev);
+        if (PERF_TYPE_RAW == event->attr.type)
+                mutex_unlock(&raw_event_mutex);
+
+        if (!attr->exclude_user)
+                hwc->config_base |= M_PERFCTL_USER;
+        if (!attr->exclude_kernel) {
+                hwc->config_base |= M_PERFCTL_KERNEL;
+                /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
+                hwc->config_base |= M_PERFCTL_EXL;
+        }
+        if (!attr->exclude_hv)
+                hwc->config_base |= M_PERFCTL_SUPERVISOR;
+
+        hwc->config_base &= M_PERFCTL_CONFIG_MASK;
+        /*
+         * The event can belong to another cpu. We do not assign a local
+         * counter for it for now.
+         */
+        hwc->idx = -1;
+        hwc->config = 0;
+
+        if (!hwc->sample_period) {
+                hwc->sample_period  = MAX_PERIOD;
+                hwc->last_period    = hwc->sample_period;
+                local64_set(&hwc->period_left, hwc->sample_period);
+        }
+
+        err = 0;
+        if (event->group_leader != event) {
+                err = validate_group(event);
+                if (err)
+                        return -EINVAL;
+        }
+
+        event->destroy = hw_perf_event_destroy;
+
+        return err;
+}
+
+static void pause_local_counters(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        int counters = mipspmu->num_counters;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        switch (counters) {
+        case 4:
+                cpuc->saved_ctrl[3] = r_c0_perfctrl3();
+                w_c0_perfctrl3(cpuc->saved_ctrl[3] &
+                        ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+        case 3:
+                cpuc->saved_ctrl[2] = r_c0_perfctrl2();
+                w_c0_perfctrl2(cpuc->saved_ctrl[2] &
+                        ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+        case 2:
+                cpuc->saved_ctrl[1] = r_c0_perfctrl1();
+                w_c0_perfctrl1(cpuc->saved_ctrl[1] &
+                        ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+        case 1:
+                cpuc->saved_ctrl[0] = r_c0_perfctrl0();
+                w_c0_perfctrl0(cpuc->saved_ctrl[0] &
+                        ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+        }
+        local_irq_restore(flags);
+}
+
+static void resume_local_counters(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        int counters = mipspmu->num_counters;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        switch (counters) {
+        case 4:
+                w_c0_perfctrl3(cpuc->saved_ctrl[3]);
+        case 3:
+                w_c0_perfctrl2(cpuc->saved_ctrl[2]);
+        case 2:
+                w_c0_perfctrl1(cpuc->saved_ctrl[1]);
+        case 1:
+                w_c0_perfctrl0(cpuc->saved_ctrl[0]);
+        }
+        local_irq_restore(flags);
+}
+
+static int mipsxx_pmu_handle_shared_irq(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct perf_sample_data data;
+        unsigned int counters = mipspmu->num_counters;
+        unsigned int counter;
+        int handled = IRQ_NONE;
+        struct pt_regs *regs;
+
+        if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
+                return handled;
+
+        /*
+         * First we pause the local counters, so that when we are locked
+         * here, the counters are all paused. When it gets locked due to
+         * perf_disable(), the timer interrupt handler will be delayed.
+         *
+         * See also mipsxx_pmu_start().
+         */
+        pause_local_counters();
+#ifdef CONFIG_MIPS_MT_SMP
+        read_lock(&pmuint_rwlock);
+#endif
+
+        regs = get_irq_regs();
+
+        perf_sample_data_init(&data, 0);
+
+        switch (counters) {
+#define HANDLE_COUNTER(n)                                               \
+        case n + 1:                                                     \
+                if (test_bit(n, cpuc->used_mask)) {                     \
+                        counter = r_c0_perfcntr ## n();                 \
+                        if (counter & M_COUNTER_OVERFLOW) {             \
+                                w_c0_perfcntr ## n(counter &            \
+                                                VALID_COUNT);           \
+                                if (test_and_change_bit(n, cpuc->msbs)) \
+                                        handle_associated_event(cpuc,   \
+                                                n, &data, regs);        \
+                                handled = IRQ_HANDLED;                  \
+                        }                                               \
+                }
+        HANDLE_COUNTER(3)
+        HANDLE_COUNTER(2)
+        HANDLE_COUNTER(1)
+        HANDLE_COUNTER(0)
+        }
+
+        /*
+         * Do all the work for the pending perf events. We can do this
+         * in here because the performance counter interrupt is a regular
+         * interrupt, not NMI.
+         */
+        if (handled == IRQ_HANDLED)
+                perf_event_do_pending();
+
+#ifdef CONFIG_MIPS_MT_SMP
+        read_unlock(&pmuint_rwlock);
+#endif
+        resume_local_counters();
+        return handled;
+}
+
+static irqreturn_t
+mipsxx_pmu_handle_irq(int irq, void *dev)
+{
+        return mipsxx_pmu_handle_shared_irq();
+}
+
+static void mipsxx_pmu_start(void)
+{
+#ifdef CONFIG_MIPS_MT_SMP
+        write_unlock(&pmuint_rwlock);
+#endif
+        resume_local_counters();
+}
+
+/*
+ * MIPS performance counters can be per-TC. The control registers can
+ * not be directly accessed accross CPUs. Hence if we want to do global
+ * control, we need cross CPU calls. on_each_cpu() can help us, but we
+ * can not make sure this function is called with interrupts enabled. So
+ * here we pause local counters and then grab a rwlock and leave the
+ * counters on other CPUs alone. If any counter interrupt raises while
+ * we own the write lock, simply pause local counters on that CPU and
+ * spin in the handler. Also we know we won't be switched to another
+ * CPU after pausing local counters and before grabbing the lock.
+ */
+static void mipsxx_pmu_stop(void)
+{
+        pause_local_counters();
+#ifdef CONFIG_MIPS_MT_SMP
+        write_lock(&pmuint_rwlock);
+#endif
+}
+
+static int
+mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
+                        struct hw_perf_event *hwc)
+{
+        int i;
+
+        /*
+         * We only need to care the counter mask. The range has been
+         * checked definitely.
+         */
+        unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
+
+        for (i = mipspmu->num_counters - 1; i >= 0; i--) {
+                /*
+                 * Note that some MIPS perf events can be counted by both
+                 * even and odd counters, wheresas many other are only by
+                 * even _or_ odd counters. This introduces an issue that
+                 * when the former kind of event takes the counter the
+                 * latter kind of event wants to use, then the "counter
+                 * allocation" for the latter event will fail. In fact if
+                 * they can be dynamically swapped, they both feel happy.
+                 * But here we leave this issue alone for now.
+                 */
+                if (test_bit(i, &cntr_mask) &&
+                        !test_and_set_bit(i, cpuc->used_mask))
+                        return i;
+        }
+
+        return -EAGAIN;
+}
+
+static void
+mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        unsigned long flags;
+
+        WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+        local_irq_save(flags);
+        cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
+                (evt->config_base & M_PERFCTL_CONFIG_MASK) |
+                /* Make sure interrupt enabled. */
+                M_PERFCTL_INTERRUPT_ENABLE;
+        /*
+         * We do not actually let the counter run. Leave it until start().
+         */
+        local_irq_restore(flags);
+}
+
+static void
+mipsxx_pmu_disable_event(int idx)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        unsigned long flags;
+
+        WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+        local_irq_save(flags);
+        cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
+                ~M_PERFCTL_COUNT_EVENT_WHENEVER;
+        mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
+        local_irq_restore(flags);
+}
+
+/* 24K */
+#define IS_UNSUPPORTED_24K_EVENT(r, b)                                  \
+        ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 ||          \
+         (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 ||           \
+         (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 ||           \
+         (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) ||         \
+         ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_24K_EVENT(b)                                   \
+        ((b) == 0 || (b) == 1 || (b) == 11)
+
+/* 34K */
+#define IS_UNSUPPORTED_34K_EVENT(r, b)                                  \
+        ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 ||           \
+         (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) ||         \
+         ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_34K_EVENT(b)                                   \
+        ((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+#define IS_RANGE_P_34K_EVENT(r, b)                                      \
+        ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
+         (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 ||           \
+         (r) == 176 || ((b) >= 50 && (b) <= 55) ||                      \
+         ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
+#endif
+
+/* 74K */
+#define IS_UNSUPPORTED_74K_EVENT(r, b)                                  \
+        ((r) == 5 || ((r) >= 135 && (r) <= 137) ||                      \
+         ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 ||          \
+         (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) ||          \
+         (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 ||           \
+         (b) == 61 || (r) == 62 || (r) == 191 ||                        \
+         ((b) >= 64 && (b) <= 127))
+#define IS_BOTH_COUNTERS_74K_EVENT(b)                                   \
+        ((b) == 0 || (b) == 1)
+
+/* 1004K */
+#define IS_UNSUPPORTED_1004K_EVENT(r, b)                                \
+        ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 ||           \
+         (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_1004K_EVENT(b)                                 \
+        ((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+#define IS_RANGE_P_1004K_EVENT(r, b)                                    \
+        ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
+         (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 ||            \
+         (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) ||        \
+         (r) == 188 || (b) == 61 || (b) == 62 ||                        \
+         ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_1004K_EVENT(r)       ((r) == 47)
+#endif
+
+/*
+ * User can use 0-255 raw events, where 0-127 for the events of even
+ * counters, and 128-255 for odd counters. Note that bit 7 is used to
+ * indicate the parity. So, for example, when user wants to take the
+ * Event Num of 15 for odd counters (by referring to the user manual),
+ * then 128 needs to be added to 15 as the input for the event config,
+ * i.e., 143 (0x8F) to be used.
+ */
+static const struct mips_perf_event *
+mipsxx_pmu_map_raw_event(u64 config)
+{
+        unsigned int raw_id = config & 0xff;
+        unsigned int base_id = raw_id & 0x7f;
+
+        switch (current_cpu_type()) {
+        case CPU_24K:
+                if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
+                        return ERR_PTR(-EOPNOTSUPP);
+                raw_event.event_id = base_id;
+                if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                /*
+                 * This is actually doing nothing. Non-multithreading
+                 * CPUs will not check and calculate the range.
+                 */
+                raw_event.range = P;
+#endif
+                break;
+        case CPU_34K:
+                if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
+                        return ERR_PTR(-EOPNOTSUPP);
+                raw_event.event_id = base_id;
+                if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
+                        raw_event.range = P;
+                else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
+                        raw_event.range = V;
+                else
+                        raw_event.range = T;
+#endif
+                break;
+        case CPU_74K:
+                if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
+                        return ERR_PTR(-EOPNOTSUPP);
+                raw_event.event_id = base_id;
+                if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                raw_event.range = P;
+#endif
+                break;
+        case CPU_1004K:
+                if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
+                        return ERR_PTR(-EOPNOTSUPP);
+                raw_event.event_id = base_id;
+                if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
+                        raw_event.range = P;
+                else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
+                        raw_event.range = V;
+                else
+                        raw_event.range = T;
+#endif
+                break;
+        }
+
+        return &raw_event;
+}
+
+static struct mips_pmu mipsxxcore_pmu = {
+        .handle_irq = mipsxx_pmu_handle_irq,
+        .handle_shared_irq = mipsxx_pmu_handle_shared_irq,
+        .start = mipsxx_pmu_start,
+        .stop = mipsxx_pmu_stop,
+        .alloc_counter = mipsxx_pmu_alloc_counter,
+        .read_counter = mipsxx_pmu_read_counter,
+        .write_counter = mipsxx_pmu_write_counter,
+        .enable_event = mipsxx_pmu_enable_event,
+        .disable_event = mipsxx_pmu_disable_event,
+        .map_raw_event = mipsxx_pmu_map_raw_event,
+        .general_event_map = &mipsxxcore_event_map,
+        .cache_event_map = &mipsxxcore_cache_map,
+};
+
+static struct mips_pmu mipsxx74Kcore_pmu = {
+        .handle_irq = mipsxx_pmu_handle_irq,
+        .handle_shared_irq = mipsxx_pmu_handle_shared_irq,
+        .start = mipsxx_pmu_start,
+        .stop = mipsxx_pmu_stop,
+        .alloc_counter = mipsxx_pmu_alloc_counter,
+        .read_counter = mipsxx_pmu_read_counter,
+        .write_counter = mipsxx_pmu_write_counter,
+        .enable_event = mipsxx_pmu_enable_event,
+        .disable_event = mipsxx_pmu_disable_event,
+        .map_raw_event = mipsxx_pmu_map_raw_event,
+        .general_event_map = &mipsxx74Kcore_event_map,
+        .cache_event_map = &mipsxx74Kcore_cache_map,
+};
+
+static int __init
+init_hw_perf_events(void)
+{
+        int counters, irq;
+
+        pr_info("Performance counters: ");
+
+        counters = n_counters();
+        if (counters == 0) {
+                pr_cont("No available PMU.\n");
+                return -ENODEV;
+        }
+
+#ifdef CONFIG_MIPS_MT_SMP
+        cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
+        if (!cpu_has_mipsmt_pertccounters)
+                counters = counters_total_to_per_cpu(counters);
+#endif
+
+#ifdef MSC01E_INT_BASE
+        if (cpu_has_veic) {
+                /*
+                 * Using platform specific interrupt controller defines.
+                 */
+                irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
+        } else {
+#endif
+                if (cp0_perfcount_irq >= 0)
+                        irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
+                else
+                        irq = -1;
+#ifdef MSC01E_INT_BASE
+        }
+#endif
+
+        on_each_cpu(reset_counters, (void *)(long)counters, 1);
+
+        switch (current_cpu_type()) {
+        case CPU_24K:
+                mipsxxcore_pmu.name = "mips/24K";
+                mipsxxcore_pmu.num_counters = counters;
+                mipsxxcore_pmu.irq = irq;
+                mipspmu = &mipsxxcore_pmu;
+                break;
+        case CPU_34K:
+                mipsxxcore_pmu.name = "mips/34K";
+                mipsxxcore_pmu.num_counters = counters;
+                mipsxxcore_pmu.irq = irq;
+                mipspmu = &mipsxxcore_pmu;
+                break;
+        case CPU_74K:
+                mipsxx74Kcore_pmu.name = "mips/74K";
+                mipsxx74Kcore_pmu.num_counters = counters;
+                mipsxx74Kcore_pmu.irq = irq;
+                mipspmu = &mipsxx74Kcore_pmu;
+                break;
+        case CPU_1004K:
+                mipsxxcore_pmu.name = "mips/1004K";
+                mipsxxcore_pmu.num_counters = counters;
+                mipsxxcore_pmu.irq = irq;
+                mipspmu = &mipsxxcore_pmu;
+                break;
+        default:
+                pr_cont("Either hardware does not support performance "
+                        "counters, or not yet implemented.\n");
+                return -ENODEV;
+        }
+
+        if (mipspmu)
+                pr_cont("%s PMU enabled, %d counters available to each "
+                        "CPU, irq %d%s\n", mipspmu->name, counters, irq,
+                        irq < 0 ? " (share with timer interrupt)" : "");
+
+        return 0;
+}
+arch_initcall(init_hw_perf_events);
+
+#endif /* defined(CONFIG_CPU_MIPS32)... */
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index a6b900f2962b..acd3f2c49c06 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -490,6 +490,7 @@ static void __init arch_mem_init(char **cmdline_p)
         bootmem_init();
         device_tree_init();
         sparse_init();
+        plat_swiotlb_setup();
         paging_init();
 }
 
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index d053bf4759e4..8e9fbe75894e 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -29,6 +29,7 @@
 #include <linux/notifier.h>
 #include <linux/kdb.h>
 #include <linux/irq.h>
+#include <linux/perf_event.h>
 
 #include <asm/bootinfo.h>
 #include <asm/branch.h>
@@ -576,10 +577,16 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
  */
 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
 {
-        if ((opcode & OPCODE) == LL)
+        if ((opcode & OPCODE) == LL) {
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 return simulate_ll(regs, opcode);
-        if ((opcode & OPCODE) == SC)
+        }
+        if ((opcode & OPCODE) == SC) {
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 return simulate_sc(regs, opcode);
+        }
 
         return -1;                      /* Must be something else ... */
 }
@@ -595,6 +602,8 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
         if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
                 int rd = (opcode & RD) >> 11;
                 int rt = (opcode & RT) >> 16;
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 switch (rd) {
                 case 0:         /* CPU number */
                         regs->regs[rt] = smp_processor_id();
@@ -630,8 +639,11 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
 
 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
 {
-        if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
+        if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 return 0;
+        }
 
         return -1;                      /* Must be something else ... */
 }
@@ -1469,6 +1481,7 @@ void __cpuinit per_cpu_trap_init(void)
 {
         unsigned int cpu = smp_processor_id();
         unsigned int status_set = ST0_CU0;
+        unsigned int hwrena = cpu_hwrena_impl_bits;
 #ifdef CONFIG_MIPS_MT_SMTC
         int secondaryTC = 0;
         int bootTC = (cpu == 0);
@@ -1501,14 +1514,14 @@ void __cpuinit per_cpu_trap_init(void)
         change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
                          status_set);
 
-        if (cpu_has_mips_r2) {
-                unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
+        if (cpu_has_mips_r2)
+                hwrena |= 0x0000000f;
 
-                if (!noulri && cpu_has_userlocal)
-                        enable |= (1 << 29);
+        if (!noulri && cpu_has_userlocal)
+                hwrena |= (1 << 29);
 
-                write_c0_hwrena(enable);
-        }
+        if (hwrena)
+                write_c0_hwrena(hwrena);
 
 #ifdef CONFIG_MIPS_MT_SMTC
         if (!secondaryTC) {
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 33d5a5ce4a29..cfea1adfa153 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -78,6 +78,8 @@
 #include <linux/smp.h>
 #include <linux/sched.h>
 #include <linux/debugfs.h>
+#include <linux/perf_event.h>
+
 #include <asm/asm.h>
 #include <asm/branch.h>
 #include <asm/byteorder.h>
@@ -109,6 +111,9 @@ static void emulate_load_store_insn(struct pt_regs *regs,
         unsigned long value;
         unsigned int res;
 
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                      1, 0, regs, 0);
+
         /*
          * This load never faults.
          */
@@ -511,6 +516,8 @@ asmlinkage void do_ade(struct pt_regs *regs)
         unsigned int __user *pc;
         mm_segment_t seg;
 
+        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
+                        1, 0, regs, regs->cp0_badvaddr);
         /*
          * Did we catch a fault trying to load an instruction?
          * Or are we running in MIPS16 mode?
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index c97ca69b94e0..6e1b77fec7ea 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -20,7 +20,6 @@ config LEMOTE_FULOONG2E
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_SUPPORTS_HIGHMEM
         select SYS_HAS_EARLY_PRINTK
-        select GENERIC_HARDIRQS_NO__DO_IRQ
         select GENERIC_ISA_DMA_SUPPORT_BROKEN
         select CPU_HAS_WB
         select LOONGSON_MC146818
@@ -40,7 +39,6 @@ config LEMOTE_MACH2F
         select CS5536
         select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
         select DMA_NONCOHERENT
-        select GENERIC_HARDIRQS_NO__DO_IRQ
         select GENERIC_ISA_DMA_SUPPORT_BROKEN
         select HW_HAS_PCI
         select I8259
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index ec3faa413f3b..b2ad1b0910ff 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -36,6 +36,7 @@
 #include <linux/sched.h>
 #include <linux/module.h>
 #include <linux/debugfs.h>
+#include <linux/perf_event.h>
 
 #include <asm/inst.h>
 #include <asm/bootinfo.h>
@@ -258,6 +259,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
         }
 
       emul:
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                        1, 0, xcp, 0);
         MIPS_FPU_EMU_INC_STATS(emulated);
         switch (MIPSInst_OPCODE(ir)) {
         case ldc1_op:{
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 0f9c488044d1..16c4d256b76f 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -181,10 +181,10 @@ static void __cpuinit probe_octeon(void)
         unsigned int config1;
         struct cpuinfo_mips *c = &current_cpu_data;
 
+        config1 = read_c0_config1();
         switch (c->cputype) {
         case CPU_CAVIUM_OCTEON:
         case CPU_CAVIUM_OCTEON_PLUS:
-                config1 = read_c0_config1();
                 c->icache.linesz = 2 << ((config1 >> 19) & 7);
                 c->icache.sets = 64 << ((config1 >> 22) & 7);
                 c->icache.ways = 1 + ((config1 >> 16) & 7);
@@ -204,6 +204,20 @@ static void __cpuinit probe_octeon(void)
                 c->options |= MIPS_CPU_PREFETCH;
                 break;
 
+        case CPU_CAVIUM_OCTEON2:
+                c->icache.linesz = 2 << ((config1 >> 19) & 7);
+                c->icache.sets = 8;
+                c->icache.ways = 37;
+                c->icache.flags |= MIPS_CACHE_VTAG;
+                icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
+
+                c->dcache.linesz = 128;
+                c->dcache.ways = 32;
+                c->dcache.sets = 8;
+                dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+                c->options |= MIPS_CPU_PREFETCH;
+                break;
+
         default:
                 panic("Unsupported Cavium Networks CPU type\n");
                 break;
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6721ee2b1e8b..b4923a75cb4b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -42,14 +42,14 @@
  *  o collapses to normal function call on UP kernels
  *  o collapses to normal function call on systems with a single shared
  *    primary cache.
+ *  o doesn't disable interrupts on the local CPU
  */
-static inline void r4k_on_each_cpu(void (*func) (void *info), void *info,
-                                   int wait)
+static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
 {
         preempt_disable();
 
 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
-        smp_call_function(func, info, wait);
+        smp_call_function(func, info, 1);
 #endif
         func(info);
         preempt_enable();
@@ -363,7 +363,7 @@ static inline void local_r4k___flush_cache_all(void * args)
 
 static void r4k___flush_cache_all(void)
 {
-        r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1);
+        r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
 }
 
 static inline int has_valid_asid(const struct mm_struct *mm)
@@ -410,7 +410,7 @@ static void r4k_flush_cache_range(struct vm_area_struct *vma,
         int exec = vma->vm_flags & VM_EXEC;
 
         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
-                r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1);
+                r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
 }
 
 static inline void local_r4k_flush_cache_mm(void * args)
@@ -442,7 +442,7 @@ static void r4k_flush_cache_mm(struct mm_struct *mm)
         if (!cpu_has_dc_aliases)
                 return;
 
-        r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
 }
 
 struct flush_cache_page_args {
@@ -534,7 +534,7 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
         args.addr = addr;
         args.pfn = pfn;
 
-        r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
 }
 
 static inline void local_r4k_flush_data_cache_page(void * addr)
@@ -547,8 +547,7 @@ static void r4k_flush_data_cache_page(unsigned long addr)
         if (in_atomic())
                 local_r4k_flush_data_cache_page((void *)addr);
         else
-                r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr,
-                                1);
+                r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
 }
 
 struct flush_icache_range_args {
@@ -589,7 +588,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
         args.start = start;
         args.end = end;
 
-        r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args, 1);
+        r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
         instruction_hazard();
 }
 
@@ -710,7 +709,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
 
 static void r4k_flush_cache_sigtramp(unsigned long addr)
 {
-        r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
 }
 
 static void r4k_flush_icache_all(void)
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 469d4019f795..4fc1a0fbe007 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -95,10 +95,9 @@ void *dma_alloc_noncoherent(struct device *dev, size_t size,
 
         return ret;
 }
-
 EXPORT_SYMBOL(dma_alloc_noncoherent);
 
-void *dma_alloc_coherent(struct device *dev, size_t size,
+static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
         dma_addr_t * dma_handle, gfp_t gfp)
 {
         void *ret;
@@ -123,7 +122,6 @@ void *dma_alloc_coherent(struct device *dev, size_t size,
         return ret;
 }
 
-EXPORT_SYMBOL(dma_alloc_coherent);
 
 void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
         dma_addr_t dma_handle)
@@ -131,10 +129,9 @@ void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
         plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
         free_pages((unsigned long) vaddr, get_order(size));
 }
-
 EXPORT_SYMBOL(dma_free_noncoherent);
 
-void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
         dma_addr_t dma_handle)
 {
         unsigned long addr = (unsigned long) vaddr;
@@ -151,8 +148,6 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
         free_pages(addr, get_order(size));
 }
 
-EXPORT_SYMBOL(dma_free_coherent);
-
 static inline void __dma_sync(unsigned long addr, size_t size,
         enum dma_data_direction direction)
 {
@@ -174,21 +169,8 @@ static inline void __dma_sync(unsigned long addr, size_t size,
         }
 }
 
-dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
-        enum dma_data_direction direction)
-{
-        unsigned long addr = (unsigned long) ptr;
-
-        if (!plat_device_is_coherent(dev))
-                __dma_sync(addr, size, direction);
-
-        return plat_map_dma_mem(dev, ptr, size);
-}
-
-EXPORT_SYMBOL(dma_map_single);
-
-void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-        enum dma_data_direction direction)
+static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction, struct dma_attrs *attrs)
 {
         if (cpu_is_noncoherent_r10000(dev))
                 __dma_sync(dma_addr_to_virt(dev, dma_addr), size,
@@ -197,15 +179,11 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
         plat_unmap_dma_mem(dev, dma_addr, size, direction);
 }
 
-EXPORT_SYMBOL(dma_unmap_single);
-
-int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-        enum dma_data_direction direction)
+static int mips_dma_map_sg(struct device *dev, struct scatterlist *sg,
+        int nents, enum dma_data_direction direction, struct dma_attrs *attrs)
 {
         int i;
 
-        BUG_ON(direction == DMA_NONE);
-
         for (i = 0; i < nents; i++, sg++) {
                 unsigned long addr;
 
@@ -219,33 +197,27 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
         return nents;
 }
 
-EXPORT_SYMBOL(dma_map_sg);
-
-dma_addr_t dma_map_page(struct device *dev, struct page *page,
-        unsigned long offset, size_t size, enum dma_data_direction direction)
+static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page,
+        unsigned long offset, size_t size, enum dma_data_direction direction,
+        struct dma_attrs *attrs)
 {
-        BUG_ON(direction == DMA_NONE);
+        unsigned long addr;
 
-        if (!plat_device_is_coherent(dev)) {
-                unsigned long addr;
+        addr = (unsigned long) page_address(page) + offset;
 
-                addr = (unsigned long) page_address(page) + offset;
+        if (!plat_device_is_coherent(dev))
                 __dma_sync(addr, size, direction);
-        }
 
-        return plat_map_dma_mem_page(dev, page) + offset;
+        return plat_map_dma_mem(dev, (void *)addr, size);
 }
 
-EXPORT_SYMBOL(dma_map_page);
-
-void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
-        enum dma_data_direction direction)
+static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+        int nhwentries, enum dma_data_direction direction,
+        struct dma_attrs *attrs)
 {
         unsigned long addr;
         int i;
 
-        BUG_ON(direction == DMA_NONE);
-
         for (i = 0; i < nhwentries; i++, sg++) {
                 if (!plat_device_is_coherent(dev) &&
                     direction != DMA_TO_DEVICE) {
@@ -257,13 +229,9 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
         }
 }
 
-EXPORT_SYMBOL(dma_unmap_sg);
-
-void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
-        size_t size, enum dma_data_direction direction)
+static void mips_dma_sync_single_for_cpu(struct device *dev,
+        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
 {
-        BUG_ON(direction == DMA_NONE);
-
         if (cpu_is_noncoherent_r10000(dev)) {
                 unsigned long addr;
 
@@ -272,13 +240,9 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
         }
 }
 
-EXPORT_SYMBOL(dma_sync_single_for_cpu);
-
-void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
-        size_t size, enum dma_data_direction direction)
+static void mips_dma_sync_single_for_device(struct device *dev,
+        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
 {
-        BUG_ON(direction == DMA_NONE);
-
         plat_extra_sync_for_device(dev);
         if (!plat_device_is_coherent(dev)) {
                 unsigned long addr;
@@ -288,46 +252,11 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
         }
 }
 
-EXPORT_SYMBOL(dma_sync_single_for_device);
-
-void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
-        unsigned long offset, size_t size, enum dma_data_direction direction)
-{
-        BUG_ON(direction == DMA_NONE);
-
-        if (cpu_is_noncoherent_r10000(dev)) {
-                unsigned long addr;
-
-                addr = dma_addr_to_virt(dev, dma_handle);
-                __dma_sync(addr + offset, size, direction);
-        }
-}
-
-EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
-
-void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
-        unsigned long offset, size_t size, enum dma_data_direction direction)
-{
-        BUG_ON(direction == DMA_NONE);
-
-        plat_extra_sync_for_device(dev);
-        if (!plat_device_is_coherent(dev)) {
-                unsigned long addr;
-
-                addr = dma_addr_to_virt(dev, dma_handle);
-                __dma_sync(addr + offset, size, direction);
-        }
-}
-
-EXPORT_SYMBOL(dma_sync_single_range_for_device);
-
-void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
-        enum dma_data_direction direction)
+static void mips_dma_sync_sg_for_cpu(struct device *dev,
+        struct scatterlist *sg, int nelems, enum dma_data_direction direction)
 {
         int i;
 
-        BUG_ON(direction == DMA_NONE);
-
         /* Make sure that gcc doesn't leave the empty loop body.  */
         for (i = 0; i < nelems; i++, sg++) {
                 if (cpu_is_noncoherent_r10000(dev))
@@ -336,15 +265,11 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
         }
 }
 
-EXPORT_SYMBOL(dma_sync_sg_for_cpu);
-
-void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
-        enum dma_data_direction direction)
+static void mips_dma_sync_sg_for_device(struct device *dev,
+        struct scatterlist *sg, int nelems, enum dma_data_direction direction)
 {
         int i;
 
-        BUG_ON(direction == DMA_NONE);
-
         /* Make sure that gcc doesn't leave the empty loop body.  */
         for (i = 0; i < nelems; i++, sg++) {
                 if (!plat_device_is_coherent(dev))
@@ -353,24 +278,18 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nele
         }
 }
 
-EXPORT_SYMBOL(dma_sync_sg_for_device);
-
-int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
         return plat_dma_mapping_error(dev, dma_addr);
 }
 
-EXPORT_SYMBOL(dma_mapping_error);
-
-int dma_supported(struct device *dev, u64 mask)
+int mips_dma_supported(struct device *dev, u64 mask)
 {
         return plat_dma_supported(dev, mask);
 }
 
-EXPORT_SYMBOL(dma_supported);
-
-void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
-               enum dma_data_direction direction)
+void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+                         enum dma_data_direction direction)
 {
         BUG_ON(direction == DMA_NONE);
 
@@ -379,4 +298,30 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                 __dma_sync((unsigned long)vaddr, size, direction);
 }
 
-EXPORT_SYMBOL(dma_cache_sync);
+static struct dma_map_ops mips_default_dma_map_ops = {
+        .alloc_coherent = mips_dma_alloc_coherent,
+        .free_coherent = mips_dma_free_coherent,
+        .map_page = mips_dma_map_page,
+        .unmap_page = mips_dma_unmap_page,
+        .map_sg = mips_dma_map_sg,
+        .unmap_sg = mips_dma_unmap_sg,
+        .sync_single_for_cpu = mips_dma_sync_single_for_cpu,
+        .sync_single_for_device = mips_dma_sync_single_for_device,
+        .sync_sg_for_cpu = mips_dma_sync_sg_for_cpu,
+        .sync_sg_for_device = mips_dma_sync_sg_for_device,
+        .mapping_error = mips_dma_mapping_error,
+        .dma_supported = mips_dma_supported
+};
+
+struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops;
+EXPORT_SYMBOL(mips_dma_map_ops);
+
+#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
+
+static int __init mips_dma_init(void)
+{
+        dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+
+        return 0;
+}
+fs_initcall(mips_dma_init);
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 783ad0065fdf..137ee76a0045 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -18,6 +18,7 @@
 #include <linux/smp.h>
 #include <linux/module.h>
 #include <linux/kprobes.h>
+#include <linux/perf_event.h>
 
 #include <asm/branch.h>
 #include <asm/mmu_context.h>
@@ -144,6 +145,7 @@ good_area:
          * the fault.
          */
         fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
         if (unlikely(fault & VM_FAULT_ERROR)) {
                 if (fault & VM_FAULT_OOM)
                         goto out_of_memory;
@@ -151,10 +153,15 @@ good_area:
                         goto do_sigbus;
                 BUG();
         }
-        if (fault & VM_FAULT_MAJOR)
+        if (fault & VM_FAULT_MAJOR) {
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ,
+                                1, 0, regs, address);
                 tsk->maj_flt++;
-        else
+        } else {
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN,
+                                1, 0, regs, address);
                 tsk->min_flt++;
+        }
 
         up_read(&mm->mmap_sem);
         return;
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5ab5fa8c1d82..505fecad4684 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -57,6 +57,34 @@ static struct bcache_ops mips_sc_ops = {
         .bc_inv = mips_sc_inv
 };
 
+/*
+ * Check if the L2 cache controller is activated on a particular platform.
+ * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
+ * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
+ * cache being disabled.  However there is no guarantee for this to be
+ * true on all platforms.  In an act of stupidity the spec defined bits
+ * 12..15 as implementation defined so below function will eventually have
+ * to be replaced by a platform specific probe.
+ */
+static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
+{
+        /* Check the bypass bit (L2B) */
+        switch (c->cputype) {
+        case CPU_34K:
+        case CPU_74K:
+        case CPU_1004K:
+        case CPU_BMIPS5000:
+                if (config2 & (1 << 12))
+                        return 0;
+        }
+
+        tmp = (config2 >> 4) & 0x0f;
+        if (0 < tmp && tmp <= 7)
+                c->scache.linesz = 2 << tmp;
+        else
+                return 0;
+}
+
 static inline int __init mips_sc_probe(void)
 {
         struct cpuinfo_mips *c = &current_cpu_data;
@@ -79,10 +107,8 @@ static inline int __init mips_sc_probe(void)
                 return 0;
 
         config2 = read_c0_config2();
-        tmp = (config2 >> 4) & 0x0f;
-        if (0 < tmp && tmp <= 7)
-                c->scache.linesz = 2 << tmp;
-        else
+
+        if (!mips_sc_is_activated(c))
                 return 0;
 
         tmp = (config2 >> 8) & 0x0f;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 4510e61883eb..93816f3bca67 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -338,13 +338,12 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         case CPU_4KSC:
         case CPU_20KC:
         case CPU_25KF:
-        case CPU_BCM3302:
-        case CPU_BCM4710:
+        case CPU_BMIPS32:
+        case CPU_BMIPS3300:
+        case CPU_BMIPS4350:
+        case CPU_BMIPS4380:
+        case CPU_BMIPS5000:
         case CPU_LOONGSON2:
-        case CPU_BCM6338:
-        case CPU_BCM6345:
-        case CPU_BCM6348:
-        case CPU_BCM6358:
         case CPU_R5500:
                 if (m4kc_tlbp_war())
                         uasm_i_nop(p);
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index d2647a4e012b..23afdebc8e5c 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -405,7 +405,6 @@ I_u1u2u3(_mfc0)
 I_u1u2u3(_mtc0)
 I_u2u1u3(_ori)
 I_u3u1u2(_or)
-I_u2s3u1(_pref)
 I_0(_rfe)
 I_u2s3u1(_sc)
 I_u2s3u1(_scd)
@@ -427,6 +426,25 @@ I_u1(_syscall);
 I_u1u2s3(_bbit0);
 I_u1u2s3(_bbit1);
 
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#include <asm/octeon/octeon.h>
+void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b,
+                            unsigned int c)
+{
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
+                /*
+                 * As per erratum Core-14449, replace prefetches 0-4,
+                 * 6-24 with 'pref 28'.
+                 */
+                build_insn(buf, insn_pref, c, 28, b);
+        else
+                build_insn(buf, insn_pref, c, a, b);
+}
+UASM_EXPORT_SYMBOL(uasm_i_pref);
+#else
+I_u2s3u1(_pref)
+#endif
+
 /* Handle labels. */
 void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
 {
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index d248b707eff3..2d74fc9ae3ba 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -11,6 +11,7 @@
 #include <linux/interrupt.h>
 #include <linux/time.h>
 #include <linux/delay.h>
+#include <linux/swiotlb.h>
 
 #include <asm/time.h>
 
@@ -19,6 +20,8 @@
 #include <asm/octeon/cvmx-pci-defs.h>
 #include <asm/octeon/pci-octeon.h>
 
+#include <dma-coherence.h>
+
 #define USE_OCTEON_INTERNAL_ARBITER
 
 /*
@@ -32,6 +35,8 @@
 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
 #define OCTEON_PCI_MEMSPACE_OFFSET  (0x00011b0000000000ull)
 
+u64 octeon_bar1_pci_phys;
+
 /**
  * This is the bit decoding used for the Octeon PCI controller addresses
  */
@@ -170,6 +175,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
                 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
         }
 
+        dev->dev.archdata.dma_ops = octeon_pci_dma_map_ops;
+
         return 0;
 }
 
@@ -618,12 +625,10 @@ static int __init octeon_pci_setup(void)
          * before the readl()'s below. We don't want BAR2 overlapping
          * with BAR0/BAR1 during these reads.
          */
-        octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0);
-        octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80);
-
-        /* Disable the BAR1 movable mappings */
-        for (index = 0; index < 32; index++)
-                octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
+        octeon_npi_write32(CVMX_NPI_PCI_CFG08,
+                           (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
+        octeon_npi_write32(CVMX_NPI_PCI_CFG09,
+                           (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
 
         if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
                 /* Remap the Octeon BAR 0 to 0-2GB */
@@ -637,6 +642,25 @@ static int __init octeon_pci_setup(void)
                 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
                 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
 
+                /* BAR1 movable mappings set for identity mapping */
+                octeon_bar1_pci_phys = 0x80000000ull;
+                for (index = 0; index < 32; index++) {
+                        union cvmx_pci_bar1_indexx bar1_index;
+
+                        bar1_index.u32 = 0;
+                        /* Address bits[35:22] sent to L2C */
+                        bar1_index.s.addr_idx =
+                                (octeon_bar1_pci_phys >> 22) + index;
+                        /* Don't put PCI accesses in L2. */
+                        bar1_index.s.ca = 1;
+                        /* Endian Swap Mode */
+                        bar1_index.s.end_swp = 1;
+                        /* Set '1' when the selected address range is valid. */
+                        bar1_index.s.addr_v = 1;
+                        octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
+                                           bar1_index.u32);
+                }
+
                 /* Devices go after BAR1 */
                 octeon_pci_mem_resource.start =
                         OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
@@ -652,6 +676,27 @@ static int __init octeon_pci_setup(void)
                 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
                 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
 
+                /* BAR1 movable regions contiguous to cover the swiotlb */
+                octeon_bar1_pci_phys =
+                        virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1);
+
+                for (index = 0; index < 32; index++) {
+                        union cvmx_pci_bar1_indexx bar1_index;
+
+                        bar1_index.u32 = 0;
+                        /* Address bits[35:22] sent to L2C */
+                        bar1_index.s.addr_idx =
+                                (octeon_bar1_pci_phys >> 22) + index;
+                        /* Don't put PCI accesses in L2. */
+                        bar1_index.s.ca = 1;
+                        /* Endian Swap Mode */
+                        bar1_index.s.end_swp = 1;
+                        /* Set '1' when the selected address range is valid. */
+                        bar1_index.s.addr_v = 1;
+                        octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
+                                           bar1_index.u32);
+                }
+
                 /* Devices go after BAR0 */
                 octeon_pci_mem_resource.start =
                         OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
@@ -667,6 +712,9 @@ static int __init octeon_pci_setup(void)
          * was setup properly.
          */
         cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
+
+        octeon_pci_dma_init();
+
         return 0;
 }
 
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 861361e0c9af..385f035b24e4 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -75,6 +75,8 @@ union cvmx_pcie_address {
         } mem;
 };
 
+#include <dma-coherence.h>
+
 /**
  * Return the Core virtual base address for PCIe IO access. IOs are
  * read/written as an offset from this address.
@@ -1391,6 +1393,9 @@ static int __init octeon_pcie_setup(void)
                         cvmx_pcie_get_io_size(1) - 1;
                 register_pci_controller(&octeon_pcie1_controller);
         }
+
+        octeon_pci_dma_init();
+
         return 0;
 }
 
diff --git a/drivers/ata/pata_octeon_cf.c b/drivers/ata/pata_octeon_cf.c
index 06ddd91ffeda..74b829817891 100644
--- a/drivers/ata/pata_octeon_cf.c
+++ b/drivers/ata/pata_octeon_cf.c
@@ -60,7 +60,7 @@ static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs)
          * Compute # of eclock periods to get desired duration in
          * nanoseconds.
          */
-        val = DIV_ROUND_UP(nsecs * (octeon_get_clock_rate() / 1000000),
+        val = DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000),
                           1000 * tim_mult);
 
         return val;
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index bf2e7d234533..2391c396ca32 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -93,8 +93,9 @@ config USB_EHCI_TT_NEWSCHED
 
 config USB_EHCI_BIG_ENDIAN_MMIO
         bool
-        depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX || \
-                                    XPS_USB_HCD_XILINX || PPC_MPC512x)
+        depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \
+                                    ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
+                                    PPC_MPC512x || CPU_CAVIUM_OCTEON)
         default y
 
 config USB_EHCI_BIG_ENDIAN_DESC
@@ -434,3 +435,28 @@ config USB_IMX21_HCD
          To compile this driver as a module, choose M here: the
          module will be called "imx21-hcd".
 
+config USB_OCTEON_EHCI
+        bool "Octeon on-chip EHCI support"
+        depends on USB && USB_EHCI_HCD && CPU_CAVIUM_OCTEON
+        default n
+        select USB_EHCI_BIG_ENDIAN_MMIO
+        help
+          Enable support for the Octeon II SOC's on-chip EHCI
+          controller.  It is needed for high-speed (480Mbit/sec)
+          USB 2.0 device support.  All CN6XXX based chips with USB are
+          supported.
+
+config USB_OCTEON_OHCI
+        bool "Octeon on-chip OHCI support"
+        depends on USB && USB_OHCI_HCD && CPU_CAVIUM_OCTEON
+        default USB_OCTEON_EHCI
+        select USB_OHCI_BIG_ENDIAN_MMIO
+        select USB_OHCI_LITTLE_ENDIAN
+        help
+          Enable support for the Octeon II SOC's on-chip OHCI
+          controller.  It is needed for low-speed USB 1.0 device
+          support.  All CN6XXX based chips with USB are supported.
+
+config USB_OCTEON2_COMMON
+        bool
+        default y if USB_OCTEON_EHCI || USB_OCTEON_OHCI
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 91c5a1bd1026..624a362f2fee 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -34,3 +34,4 @@ obj-$(CONFIG_USB_ISP1760_HCD)	+= isp1760.o
 obj-$(CONFIG_USB_HWA_HCD)       += hwa-hc.o
 obj-$(CONFIG_USB_IMX21_HCD)     += imx21-hcd.o
 obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o
+obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2adae8e39bba..502a7e6fef42 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1211,6 +1211,11 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER         ehci_atmel_driver
 #endif
 
+#ifdef CONFIG_USB_OCTEON_EHCI
+#include "ehci-octeon.c"
+#define PLATFORM_DRIVER         ehci_octeon_driver
+#endif
+
 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
     !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
     !defined(XILINX_OF_PLATFORM_DRIVER)
diff --git a/drivers/usb/host/ehci-octeon.c b/drivers/usb/host/ehci-octeon.c
new file mode 100644
index 000000000000..a31a031178a8
--- /dev/null
+++ b/drivers/usb/host/ehci-octeon.c
@@ -0,0 +1,207 @@
+/*
+ * EHCI HCD glue for Cavium Octeon II SOCs.
+ *
+ * Loosely based on ehci-au1xxx.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2010 Cavium Networks
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-uctlx-defs.h>
+
+#define OCTEON_EHCI_HCD_NAME "octeon-ehci"
+
+/* Common clock init code.  */
+void octeon2_usb_clocks_start(void);
+void octeon2_usb_clocks_stop(void);
+
+static void ehci_octeon_start(void)
+{
+        union cvmx_uctlx_ehci_ctl ehci_ctl;
+
+        octeon2_usb_clocks_start();
+
+        ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
+        /* Use 64-bit addressing. */
+        ehci_ctl.s.ehci_64b_addr_en = 1;
+        ehci_ctl.s.l2c_addr_msb = 0;
+        ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
+        ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
+        cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
+}
+
+static void ehci_octeon_stop(void)
+{
+        octeon2_usb_clocks_stop();
+}
+
+static const struct hc_driver ehci_octeon_hc_driver = {
+        .description            = hcd_name,
+        .product_desc           = "Octeon EHCI",
+        .hcd_priv_size          = sizeof(struct ehci_hcd),
+
+        /*
+         * generic hardware linkage
+         */
+        .irq                    = ehci_irq,
+        .flags                  = HCD_MEMORY | HCD_USB2,
+
+        /*
+         * basic lifecycle operations
+         */
+        .reset                  = ehci_init,
+        .start                  = ehci_run,
+        .stop                   = ehci_stop,
+        .shutdown               = ehci_shutdown,
+
+        /*
+         * managing i/o requests and associated device resources
+         */
+        .urb_enqueue            = ehci_urb_enqueue,
+        .urb_dequeue            = ehci_urb_dequeue,
+        .endpoint_disable       = ehci_endpoint_disable,
+        .endpoint_reset         = ehci_endpoint_reset,
+
+        /*
+         * scheduling support
+         */
+        .get_frame_number       = ehci_get_frame,
+
+        /*
+         * root hub support
+         */
+        .hub_status_data        = ehci_hub_status_data,
+        .hub_control            = ehci_hub_control,
+        .bus_suspend            = ehci_bus_suspend,
+        .bus_resume             = ehci_bus_resume,
+        .relinquish_port        = ehci_relinquish_port,
+        .port_handed_over       = ehci_port_handed_over,
+
+        .clear_tt_buffer_complete       = ehci_clear_tt_buffer_complete,
+};
+
+static u64 ehci_octeon_dma_mask = DMA_BIT_MASK(64);
+
+static int ehci_octeon_drv_probe(struct platform_device *pdev)
+{
+        struct usb_hcd *hcd;
+        struct ehci_hcd *ehci;
+        struct resource *res_mem;
+        int irq;
+        int ret;
+
+        if (usb_disabled())
+                return -ENODEV;
+
+        irq = platform_get_irq(pdev, 0);
+        if (irq < 0) {
+                dev_err(&pdev->dev, "No irq assigned\n");
+                return -ENODEV;
+        }
+
+        res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res_mem == NULL) {
+                dev_err(&pdev->dev, "No register space assigned\n");
+                return -ENODEV;
+        }
+
+        /*
+         * We can DMA from anywhere. But the descriptors must be in
+         * the lower 4GB.
+         */
+        pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+        pdev->dev.dma_mask = &ehci_octeon_dma_mask;
+
+        hcd = usb_create_hcd(&ehci_octeon_hc_driver, &pdev->dev, "octeon");
+        if (!hcd)
+                return -ENOMEM;
+
+        hcd->rsrc_start = res_mem->start;
+        hcd->rsrc_len = res_mem->end - res_mem->start + 1;
+
+        if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
+                                OCTEON_EHCI_HCD_NAME)) {
+                dev_err(&pdev->dev, "request_mem_region failed\n");
+                ret = -EBUSY;
+                goto err1;
+        }
+
+        hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+        if (!hcd->regs) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err2;
+        }
+
+        ehci_octeon_start();
+
+        ehci = hcd_to_ehci(hcd);
+
+        /* Octeon EHCI matches CPU endianness. */
+#ifdef __BIG_ENDIAN
+        ehci->big_endian_mmio = 1;
+#endif
+
+        ehci->caps = hcd->regs;
+        ehci->regs = hcd->regs +
+                HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+        /* cache this readonly data; minimize chip reads */
+        ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+
+        ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
+        if (ret) {
+                dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
+                goto err3;
+        }
+
+        platform_set_drvdata(pdev, hcd);
+
+        /* root ports should always stay powered */
+        ehci_port_power(ehci, 1);
+
+        return 0;
+err3:
+        ehci_octeon_stop();
+
+        iounmap(hcd->regs);
+err2:
+        release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err1:
+        usb_put_hcd(hcd);
+        return ret;
+}
+
+static int ehci_octeon_drv_remove(struct platform_device *pdev)
+{
+        struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+        usb_remove_hcd(hcd);
+
+        ehci_octeon_stop();
+        iounmap(hcd->regs);
+        release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+        usb_put_hcd(hcd);
+
+        platform_set_drvdata(pdev, NULL);
+
+        return 0;
+}
+
+static struct platform_driver ehci_octeon_driver = {
+        .probe          = ehci_octeon_drv_probe,
+        .remove         = ehci_octeon_drv_remove,
+        .shutdown       = usb_hcd_platform_shutdown,
+        .driver = {
+                .name   = OCTEON_EHCI_HCD_NAME,
+                .owner  = THIS_MODULE,
+        }
+};
+
+MODULE_ALIAS("platform:" OCTEON_EHCI_HCD_NAME);
diff --git a/drivers/usb/host/octeon2-common.c b/drivers/usb/host/octeon2-common.c
new file mode 100644
index 000000000000..72d672cfcf39
--- /dev/null
+++ b/drivers/usb/host/octeon2-common.c
@@ -0,0 +1,185 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2010 Cavium Networks
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+
+#include <asm/atomic.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-uctlx-defs.h>
+
+static atomic_t  octeon2_usb_clock_start_cnt = ATOMIC_INIT(0);
+
+void octeon2_usb_clocks_start(void)
+{
+        u64 div;
+        union cvmx_uctlx_if_ena if_ena;
+        union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
+        union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
+        union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
+        int i;
+        unsigned long io_clk_64_to_ns;
+
+        if (atomic_inc_return(&octeon2_usb_clock_start_cnt) != 1)
+                return;
+
+        io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
+
+        /*
+         * Step 1: Wait for voltages stable.  That surely happened
+         * before starting the kernel.
+         *
+         * Step 2: Enable  SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
+         */
+        if_ena.u64 = 0;
+        if_ena.s.en = 1;
+        cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
+
+        /* Step 3: Configure the reference clock, PHY, and HCLK */
+        clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
+        /* 3a */
+        clk_rst_ctl.s.p_por = 1;
+        clk_rst_ctl.s.hrst = 0;
+        clk_rst_ctl.s.p_prst = 0;
+        clk_rst_ctl.s.h_clkdiv_rst = 0;
+        clk_rst_ctl.s.o_clkdiv_rst = 0;
+        clk_rst_ctl.s.h_clkdiv_en = 0;
+        clk_rst_ctl.s.o_clkdiv_en = 0;
+        cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+        /* 3b */
+        /* 12MHz crystal. */
+        clk_rst_ctl.s.p_refclk_sel = 0;
+        clk_rst_ctl.s.p_refclk_div = 0;
+        cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+        /* 3c */
+        div = octeon_get_io_clock_rate() / 130000000ull;
+
+        switch (div) {
+        case 0:
+                div = 1;
+                break;
+        case 1:
+        case 2:
+        case 3:
+        case 4:
+                break;
+        case 5:
+                div = 4;
+                break;
+        case 6:
+        case 7:
+                div = 6;
+                break;
+        case 8:
+        case 9:
+        case 10:
+        case 11:
+                div = 8;
+                break;
+        default:
+                div = 12;
+                break;
+        }
+        clk_rst_ctl.s.h_div = div;
+        cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+        /* Read it back, */
+        clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
+        clk_rst_ctl.s.h_clkdiv_en = 1;
+        cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+        /* 3d */
+        clk_rst_ctl.s.h_clkdiv_rst = 1;
+        cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+        /* 3e: delay 64 io clocks */
+        ndelay(io_clk_64_to_ns);
+
+        /*
+         * Step 4: Program the power-on reset field in the UCTL
+         * clock-reset-control register.
+         */
+        clk_rst_ctl.s.p_por = 0;
+        cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+        /* Step 5:    Wait 1 ms for the PHY clock to start. */
+        mdelay(1);
+
+        /*
+         * Step 6: Program the reset input from automatic test
+         * equipment field in the UPHY CSR
+         */
+        uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
+        uphy_ctl_status.s.ate_reset = 1;
+        cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
+
+        /* Step 7: Wait for at least 10ns. */
+        ndelay(10);
+
+        /* Step 8: Clear the ATE_RESET field in the UPHY CSR. */
+        uphy_ctl_status.s.ate_reset = 0;
+        cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
+
+        /*
+         * Step 9: Wait for at least 20ns for UPHY to output PHY clock
+         * signals and OHCI_CLK48
+         */
+        ndelay(20);
+
+        /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
+        /* 10a */
+        clk_rst_ctl.s.o_clkdiv_rst = 1;
+        cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+        /* 10b */
+        clk_rst_ctl.s.o_clkdiv_en = 1;
+        cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+        /* 10c */
+        ndelay(io_clk_64_to_ns);
+
+        /*
+         * Step 11: Program the PHY reset field:
+         * UCTL0_CLK_RST_CTL[P_PRST] = 1
+         */
+        clk_rst_ctl.s.p_prst = 1;
+        cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+        /* Step 12: Wait 1 uS. */
+        udelay(1);
+
+        /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
+        clk_rst_ctl.s.hrst = 1;
+        cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+        /* Now we can set some other registers.  */
+
+        for (i = 0; i <= 1; i++) {
+                port_ctl_status.u64 =
+                        cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
+                /* Set txvreftune to 15 to obtain complient 'eye' diagram. */
+                port_ctl_status.s.txvreftune = 15;
+                cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
+                               port_ctl_status.u64);
+        }
+}
+EXPORT_SYMBOL(octeon2_usb_clocks_start);
+
+void octeon2_usb_clocks_stop(void)
+{
+        union cvmx_uctlx_if_ena if_ena;
+
+        if (atomic_dec_return(&octeon2_usb_clock_start_cnt) != 0)
+                return;
+
+        if_ena.u64 = 0;
+        if_ena.s.en = 0;
+        cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
+}
+EXPORT_SYMBOL(octeon2_usb_clocks_stop);
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index f3713f43f3fe..5179acb7aa2f 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1106,6 +1106,11 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
 #endif
 
+#ifdef CONFIG_USB_OCTEON_OHCI
+#include "ohci-octeon.c"
+#define PLATFORM_DRIVER         ohci_octeon_driver
+#endif
+
 #if     !defined(PCI_DRIVER) &&         \
         !defined(PLATFORM_DRIVER) &&    \
         !defined(OMAP1_PLATFORM_DRIVER) &&      \
diff --git a/drivers/usb/host/ohci-octeon.c b/drivers/usb/host/ohci-octeon.c
new file mode 100644
index 000000000000..e4ddfaf8870f
--- /dev/null
+++ b/drivers/usb/host/ohci-octeon.c
@@ -0,0 +1,214 @@
+/*
+ * EHCI HCD glue for Cavium Octeon II SOCs.
+ *
+ * Loosely based on ehci-au1xxx.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2010 Cavium Networks
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-uctlx-defs.h>
+
+#define OCTEON_OHCI_HCD_NAME "octeon-ohci"
+
+/* Common clock init code.  */
+void octeon2_usb_clocks_start(void);
+void octeon2_usb_clocks_stop(void);
+
+static void ohci_octeon_hw_start(void)
+{
+        union cvmx_uctlx_ohci_ctl ohci_ctl;
+
+        octeon2_usb_clocks_start();
+
+        ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
+        ohci_ctl.s.l2c_addr_msb = 0;
+        ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
+        ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
+        cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
+
+}
+
+static void ohci_octeon_hw_stop(void)
+{
+        /* Undo ohci_octeon_start() */
+        octeon2_usb_clocks_stop();
+}
+
+static int __devinit ohci_octeon_start(struct usb_hcd *hcd)
+{
+        struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+        int ret;
+
+        ret = ohci_init(ohci);
+
+        if (ret < 0)
+                return ret;
+
+        ret = ohci_run(ohci);
+
+        if (ret < 0) {
+                ohci_err(ohci, "can't start %s", hcd->self.bus_name);
+                ohci_stop(hcd);
+                return ret;
+        }
+
+        return 0;
+}
+
+static const struct hc_driver ohci_octeon_hc_driver = {
+        .description            = hcd_name,
+        .product_desc           = "Octeon OHCI",
+        .hcd_priv_size          = sizeof(struct ohci_hcd),
+
+        /*
+         * generic hardware linkage
+         */
+        .irq =                  ohci_irq,
+        .flags =                HCD_USB11 | HCD_MEMORY,
+
+        /*
+         * basic lifecycle operations
+         */
+        .start =                ohci_octeon_start,
+        .stop =                 ohci_stop,
+        .shutdown =             ohci_shutdown,
+
+        /*
+         * managing i/o requests and associated device resources
+         */
+        .urb_enqueue =          ohci_urb_enqueue,
+        .urb_dequeue =          ohci_urb_dequeue,
+        .endpoint_disable =     ohci_endpoint_disable,
+
+        /*
+         * scheduling support
+         */
+        .get_frame_number =     ohci_get_frame,
+
+        /*
+         * root hub support
+         */
+        .hub_status_data =      ohci_hub_status_data,
+        .hub_control =          ohci_hub_control,
+
+        .start_port_reset =     ohci_start_port_reset,
+};
+
+static int ohci_octeon_drv_probe(struct platform_device *pdev)
+{
+        struct usb_hcd *hcd;
+        struct ohci_hcd *ohci;
+        void *reg_base;
+        struct resource *res_mem;
+        int irq;
+        int ret;
+
+        if (usb_disabled())
+                return -ENODEV;
+
+        irq = platform_get_irq(pdev, 0);
+        if (irq < 0) {
+                dev_err(&pdev->dev, "No irq assigned\n");
+                return -ENODEV;
+        }
+
+        res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res_mem == NULL) {
+                dev_err(&pdev->dev, "No register space assigned\n");
+                return -ENODEV;
+        }
+
+        /* Ohci is a 32-bit device. */
+        pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+        pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+
+        hcd = usb_create_hcd(&ohci_octeon_hc_driver, &pdev->dev, "octeon");
+        if (!hcd)
+                return -ENOMEM;
+
+        hcd->rsrc_start = res_mem->start;
+        hcd->rsrc_len = res_mem->end - res_mem->start + 1;
+
+        if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
+                                OCTEON_OHCI_HCD_NAME)) {
+                dev_err(&pdev->dev, "request_mem_region failed\n");
+                ret = -EBUSY;
+                goto err1;
+        }
+
+        reg_base = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+        if (!reg_base) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err2;
+        }
+
+        ohci_octeon_hw_start();
+
+        hcd->regs = reg_base;
+
+        ohci = hcd_to_ohci(hcd);
+
+        /* Octeon OHCI matches CPU endianness. */
+#ifdef __BIG_ENDIAN
+        ohci->flags |= OHCI_QUIRK_BE_MMIO;
+#endif
+
+        ohci_hcd_init(ohci);
+
+        ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
+        if (ret) {
+                dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
+                goto err3;
+        }
+
+        platform_set_drvdata(pdev, hcd);
+
+        return 0;
+
+err3:
+        ohci_octeon_hw_stop();
+
+        iounmap(hcd->regs);
+err2:
+        release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err1:
+        usb_put_hcd(hcd);
+        return ret;
+}
+
+static int ohci_octeon_drv_remove(struct platform_device *pdev)
+{
+        struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+        usb_remove_hcd(hcd);
+
+        ohci_octeon_hw_stop();
+        iounmap(hcd->regs);
+        release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+        usb_put_hcd(hcd);
+
+        platform_set_drvdata(pdev, NULL);
+
+        return 0;
+}
+
+static struct platform_driver ohci_octeon_driver = {
+        .probe          = ohci_octeon_drv_probe,
+        .remove         = ohci_octeon_drv_remove,
+        .shutdown       = usb_hcd_platform_shutdown,
+        .driver = {
+                .name   = OCTEON_OHCI_HCD_NAME,
+                .owner  = THIS_MODULE,
+        }
+};
+
+MODULE_ALIAS("platform:" OCTEON_OHCI_HCD_NAME);
diff --git a/drivers/watchdog/octeon-wdt-main.c b/drivers/watchdog/octeon-wdt-main.c
index 909923800a02..945ee8300306 100644
--- a/drivers/watchdog/octeon-wdt-main.c
+++ b/drivers/watchdog/octeon-wdt-main.c
@@ -478,7 +478,7 @@ static void octeon_wdt_calc_parameters(int t)
 
         countdown_reset = periods > 2 ? periods - 2 : 0;
         heartbeat = t;
-        timeout_cnt = ((octeon_get_clock_rate() >> 8) * timeout_sec) >> 8;
+        timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8;
 }
 
 static int octeon_wdt_set_heartbeat(int t)
@@ -677,7 +677,7 @@ static int __init octeon_wdt_init(void)
         max_timeout_sec = 6;
         do {
                 max_timeout_sec--;
-                timeout_cnt = ((octeon_get_clock_rate() >> 8) * max_timeout_sec) >> 8;
+                timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * max_timeout_sec) >> 8;
         } while (timeout_cnt > 65535);
 
         BUG_ON(timeout_cnt == 0);
diff --git a/scripts/recordmcount.c b/scripts/recordmcount.c
index 26e1271259ba..f2f32eee2c5b 100644
--- a/scripts/recordmcount.c
+++ b/scripts/recordmcount.c
@@ -217,6 +217,39 @@ is_mcounted_section_name(char const *const txtname)
 #define RECORD_MCOUNT_64
 #include "recordmcount.h"
 
+/* 64-bit EM_MIPS has weird ELF64_Rela.r_info.
+ * http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf
+ * We interpret Table 29 Relocation Operation (Elf64_Rel, Elf64_Rela) [p.40]
+ * to imply the order of the members; the spec does not say so.
+ *      typedef unsigned char Elf64_Byte;
+ * fails on MIPS64 because their <elf.h> already has it!
+ */
+
+typedef uint8_t myElf64_Byte;           /* Type for a 8-bit quantity.  */
+
+union mips_r_info {
+        Elf64_Xword r_info;
+        struct {
+                Elf64_Word r_sym;               /* Symbol index.  */
+                myElf64_Byte r_ssym;            /* Special symbol.  */
+                myElf64_Byte r_type3;           /* Third relocation.  */
+                myElf64_Byte r_type2;           /* Second relocation.  */
+                myElf64_Byte r_type;            /* First relocation.  */
+        } r_mips;
+};
+
+static uint64_t MIPS64_r_sym(Elf64_Rel const *rp)
+{
+        return w(((union mips_r_info){ .r_info = rp->r_info }).r_mips.r_sym);
+}
+
+static void MIPS64_r_info(Elf64_Rel *const rp, unsigned sym, unsigned type)
+{
+        rp->r_info = ((union mips_r_info){
+                .r_mips = { .r_sym = w(sym), .r_type = type }
+        }).r_info;
+}
+
 static void
 do_file(char const *const fname)
 {
@@ -268,6 +301,7 @@ do_file(char const *const fname)
         case EM_386:     reltype = R_386_32;                   break;
         case EM_ARM:     reltype = R_ARM_ABS32;                break;
         case EM_IA_64:   reltype = R_IA64_IMM64;   gpfx = '_'; break;
+        case EM_MIPS:    /* reltype: e_class    */ gpfx = '_'; break;
         case EM_PPC:     reltype = R_PPC_ADDR32;   gpfx = '_'; break;
         case EM_PPC64:   reltype = R_PPC64_ADDR64; gpfx = '_'; break;
         case EM_S390:    /* reltype: e_class    */ gpfx = '_'; break;
@@ -291,6 +325,10 @@ do_file(char const *const fname)
                 }
                 if (EM_S390 == w2(ehdr->e_machine))
                         reltype = R_390_32;
+                if (EM_MIPS == w2(ehdr->e_machine)) {
+                        reltype = R_MIPS_32;
+                        is_fake_mcount32 = MIPS32_is_fake_mcount;
+                }
                 do32(ehdr, fname, reltype);
         } break;
         case ELFCLASS64: {
@@ -303,6 +341,12 @@ do_file(char const *const fname)
                 }
                 if (EM_S390 == w2(ghdr->e_machine))
                         reltype = R_390_64;
+                if (EM_MIPS == w2(ghdr->e_machine)) {
+                        reltype = R_MIPS_64;
+                        Elf64_r_sym = MIPS64_r_sym;
+                        Elf64_r_info = MIPS64_r_info;
+                        is_fake_mcount64 = MIPS64_is_fake_mcount;
+                }
                 do64(ghdr, fname, reltype);
         } break;
         }  /* end switch */
diff --git a/scripts/recordmcount.h b/scripts/recordmcount.h
index 7f39d0943d2d..58e933a20544 100644
--- a/scripts/recordmcount.h
+++ b/scripts/recordmcount.h
@@ -19,20 +19,28 @@
  * Licensed under the GNU General Public License, version 2 (GPLv2).
  */
 #undef append_func
+#undef is_fake_mcount
+#undef fn_is_fake_mcount
+#undef MIPS_is_fake_mcount
 #undef sift_rel_mcount
 #undef find_secsym_ndx
 #undef __has_rel_mcount
 #undef has_rel_mcount
 #undef tot_relsize
 #undef do_func
+#undef Elf_Addr
 #undef Elf_Ehdr
 #undef Elf_Shdr
 #undef Elf_Rel
 #undef Elf_Rela
 #undef Elf_Sym
 #undef ELF_R_SYM
+#undef Elf_r_sym
 #undef ELF_R_INFO
+#undef Elf_r_info
 #undef ELF_ST_BIND
+#undef fn_ELF_R_SYM
+#undef fn_ELF_R_INFO
 #undef uint_t
 #undef _w
 #undef _align
@@ -46,14 +54,22 @@
 # define has_rel_mcount         has64_rel_mcount
 # define tot_relsize            tot64_relsize
 # define do_func                do64
+# define is_fake_mcount         is_fake_mcount64
+# define fn_is_fake_mcount      fn_is_fake_mcount64
+# define MIPS_is_fake_mcount    MIPS64_is_fake_mcount
+# define Elf_Addr               Elf64_Addr
 # define Elf_Ehdr               Elf64_Ehdr
 # define Elf_Shdr               Elf64_Shdr
 # define Elf_Rel                Elf64_Rel
 # define Elf_Rela               Elf64_Rela
 # define Elf_Sym                Elf64_Sym
 # define ELF_R_SYM              ELF64_R_SYM
+# define Elf_r_sym              Elf64_r_sym
 # define ELF_R_INFO             ELF64_R_INFO
+# define Elf_r_info             Elf64_r_info
 # define ELF_ST_BIND            ELF64_ST_BIND
+# define fn_ELF_R_SYM           fn_ELF64_R_SYM
+# define fn_ELF_R_INFO          fn_ELF64_R_INFO
 # define uint_t                 uint64_t
 # define _w                     w8
 # define _align                 7u
@@ -66,20 +82,81 @@
 # define has_rel_mcount         has32_rel_mcount
 # define tot_relsize            tot32_relsize
 # define do_func                do32
+# define is_fake_mcount         is_fake_mcount32
+# define fn_is_fake_mcount      fn_is_fake_mcount32
+# define MIPS_is_fake_mcount    MIPS32_is_fake_mcount
+# define Elf_Addr               Elf32_Addr
 # define Elf_Ehdr               Elf32_Ehdr
 # define Elf_Shdr               Elf32_Shdr
 # define Elf_Rel                Elf32_Rel
 # define Elf_Rela               Elf32_Rela
 # define Elf_Sym                Elf32_Sym
 # define ELF_R_SYM              ELF32_R_SYM
+# define Elf_r_sym              Elf32_r_sym
 # define ELF_R_INFO             ELF32_R_INFO
+# define Elf_r_info             Elf32_r_info
 # define ELF_ST_BIND            ELF32_ST_BIND
+# define fn_ELF_R_SYM           fn_ELF32_R_SYM
+# define fn_ELF_R_INFO          fn_ELF32_R_INFO
 # define uint_t                 uint32_t
 # define _w                     w
 # define _align                 3u
 # define _size                  4
 #endif
 
+/* Functions and pointers that do_file() may override for specific e_machine. */
+static int fn_is_fake_mcount(Elf_Rel const *rp)
+{
+        return 0;
+}
+static int (*is_fake_mcount)(Elf_Rel const *rp) = fn_is_fake_mcount;
+
+static uint_t fn_ELF_R_SYM(Elf_Rel const *rp)
+{
+        return ELF_R_SYM(_w(rp->r_info));
+}
+static uint_t (*Elf_r_sym)(Elf_Rel const *rp) = fn_ELF_R_SYM;
+
+static void fn_ELF_R_INFO(Elf_Rel *const rp, unsigned sym, unsigned type)
+{
+        rp->r_info = ELF_R_INFO(sym, type);
+}
+static void (*Elf_r_info)(Elf_Rel *const rp, unsigned sym, unsigned type) = fn_ELF_R_INFO;
+
+/*
+ * MIPS mcount long call has 2 _mcount symbols, only the position of the 1st
+ * _mcount symbol is needed for dynamic function tracer, with it, to disable
+ * tracing(ftrace_make_nop), the instruction in the position is replaced with
+ * the "b label" instruction, to enable tracing(ftrace_make_call), replace the
+ * instruction back. So, here, we set the 2nd one as fake and filter it.
+ *
+ * c:   3c030000        lui     v1,0x0          <-->    b       label
+ *              c: R_MIPS_HI16  _mcount
+ *              c: R_MIPS_NONE  *ABS*
+ *              c: R_MIPS_NONE  *ABS*
+ * 10:  64630000        daddiu  v1,v1,0
+ *              10: R_MIPS_LO16 _mcount
+ *              10: R_MIPS_NONE *ABS*
+ *              10: R_MIPS_NONE *ABS*
+ * 14:  03e0082d        move    at,ra
+ * 18:  0060f809        jalr    v1
+ * label:
+ */
+#define MIPS_FAKEMCOUNT_OFFSET  4
+
+static int MIPS_is_fake_mcount(Elf_Rel const *rp)
+{
+        static Elf_Addr old_r_offset;
+        Elf_Addr current_r_offset = _w(rp->r_offset);
+        int is_fake;
+
+        is_fake = old_r_offset &&
+                (current_r_offset - old_r_offset == MIPS_FAKEMCOUNT_OFFSET);
+        old_r_offset = current_r_offset;
+
+        return is_fake;
+}
+
 /* Append the new shstrtab, Elf_Shdr[], __mcount_loc and its relocations. */
 static void append_func(Elf_Ehdr *const ehdr,
                         Elf_Shdr *const shstr,
@@ -157,7 +234,6 @@ static void append_func(Elf_Ehdr *const ehdr,
         uwrite(fd_map, ehdr, sizeof(*ehdr));
 }
 
-
 /*
  * Look at the relocations in order to find the calls to mcount.
  * Accumulate the section offsets that are found, and their relocation info,
@@ -197,22 +273,22 @@ static uint_t *sift_rel_mcount(uint_t *mlocp,
         for (t = nrel; t; --t) {
                 if (!mcountsym) {
                         Elf_Sym const *const symp =
-                                &sym0[ELF_R_SYM(_w(relp->r_info))];
+                                &sym0[Elf_r_sym(relp)];
                         char const *symname = &str0[w(symp->st_name)];
 
                         if ('.' == symname[0])
                                 ++symname;  /* ppc64 hack */
                         if (0 == strcmp((('_' == gpfx) ? "_mcount" : "mcount"),
                                         symname))
-                                mcountsym = ELF_R_SYM(_w(relp->r_info));
+                                mcountsym = Elf_r_sym(relp);
                 }
 
-                if (mcountsym == ELF_R_SYM(_w(relp->r_info))) {
+                if (mcountsym == Elf_r_sym(relp) && !is_fake_mcount(relp)) {
                         uint_t const addend = _w(_w(relp->r_offset) - recval);
 
                         mrelp->r_offset = _w(offbase
                                 + ((void *)mlocp - (void *)mloc0));
-                        mrelp->r_info = _w(ELF_R_INFO(recsym, reltype));
+                        Elf_r_info(mrelp, recsym, reltype);
                         if (sizeof(Elf_Rela) == rel_entsize) {
                                 ((Elf_Rela *)mrelp)->r_addend = addend;
                                 *mlocp++ = 0;