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-rw-r--r--arch/arm/configs/mx51_defconfig17
-rw-r--r--arch/arm/mach-mx2/devices.c9
-rw-r--r--arch/arm/mach-mx2/mach-pca100.c1
-rw-r--r--arch/arm/mach-mx2/mach-pcm038.c1
-rw-r--r--arch/arm/mach-mx25/devices.c15
-rw-r--r--arch/arm/mach-mx25/devices.h1
-rw-r--r--arch/arm/mach-mx3/Kconfig1
-rw-r--r--arch/arm/mach-mx3/devices.c40
-rw-r--r--arch/arm/mach-mx3/devices.h2
-rw-r--r--arch/arm/mach-mx3/mach-mx31_3ds.c87
-rw-r--r--arch/arm/mach-mx3/mach-mx31lilly.c145
-rw-r--r--arch/arm/mach-mx3/mach-mx31moboard.c104
-rw-r--r--arch/arm/mach-mx3/mach-pcm037.c1
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c1
-rw-r--r--arch/arm/mach-mx3/mx31lite-db.c1
-rw-r--r--arch/arm/mach-mx3/mx31moboard-devboard.c9
-rw-r--r--arch/arm/mach-mx3/mx31moboard-marxbot.c8
-rw-r--r--arch/arm/mach-mx3/mx31moboard-smartbot.c53
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c167
-rw-r--r--arch/arm/mach-mx5/clock-mx51.c45
-rw-r--r--arch/arm/mach-mx5/devices.c109
-rw-r--r--arch/arm/mach-mx5/devices.h4
-rw-r--r--arch/arm/plat-mxc/ehci.c100
-rw-r--r--arch/arm/plat-mxc/gpio.c5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31moboard.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h34
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_ehci.h14
-rw-r--r--arch/arm/plat-mxc/time.c46
-rw-r--r--arch/arm/plat-mxc/tzic.c4
-rw-r--r--drivers/mmc/core/sdio.c6
-rw-r--r--drivers/mmc/host/mxcmmc.c114
-rw-r--r--drivers/mtd/nand/mxc_nand.c125
-rw-r--r--drivers/usb/host/ehci-mxc.c4
-rw-r--r--include/linux/mmc/host.h3
35 files changed, 1097 insertions, 199 deletions
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index c88e9527a8ec..a708fd6d6ffe 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -809,7 +809,22 @@ CONFIG_SSB_POSSIBLE=y
809CONFIG_DUMMY_CONSOLE=y 809CONFIG_DUMMY_CONSOLE=y
810# CONFIG_SOUND is not set 810# CONFIG_SOUND is not set
811# CONFIG_HID_SUPPORT is not set 811# CONFIG_HID_SUPPORT is not set
812# CONFIG_USB_SUPPORT is not set 812CONFIG_USB_SUPPORT=y
813CONFIG_USB_ARCH_HAS_HCD=y
814# CONFIG_USB_ARCH_HAS_OHCI is not set
815CONFIG_USB_ARCH_HAS_EHCI=y
816CONFIG_USB=y
817
818#
819# USB Host Controller Drivers
820#
821# CONFIG_USB_C67X00_HCD is not set
822CONFIG_USB_EHCI_HCD=y
823CONFIG_USB_EHCI_ROOT_HUB_TT=y
824# CONFIG_USB_EHCI_TT_NEWSCHED is not set
825CONFIG_USB_EHCI_MXC=y
826
827
813CONFIG_MMC=y 828CONFIG_MMC=y
814# CONFIG_MMC_DEBUG is not set 829# CONFIG_MMC_DEBUG is not set
815# CONFIG_MMC_UNSAFE_RESUME is not set 830# CONFIG_MMC_UNSAFE_RESUME is not set
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index b91e412f7b3e..a9377cec662a 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -109,12 +109,7 @@ DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
109DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); 109DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
110#endif 110#endif
111 111
112/* 112/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
113 * Watchdog:
114 * - i.MX1
115 * - i.MX21
116 * - i.MX27
117 */
118static struct resource mxc_wdt_resources[] = { 113static struct resource mxc_wdt_resources[] = {
119 { 114 {
120 .start = MX2x_WDOG_BASE_ADDR, 115 .start = MX2x_WDOG_BASE_ADDR,
@@ -124,7 +119,7 @@ static struct resource mxc_wdt_resources[] = {
124}; 119};
125 120
126struct platform_device mxc_wdt = { 121struct platform_device mxc_wdt = {
127 .name = "mxc_wdt", 122 .name = "imx2-wdt",
128 .id = 0, 123 .id = 0,
129 .num_resources = ARRAY_SIZE(mxc_wdt_resources), 124 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
130 .resource = mxc_wdt_resources, 125 .resource = mxc_wdt_resources,
diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c
index 778fff230918..a87422ed4ff5 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-mx2/mach-pca100.c
@@ -145,6 +145,7 @@ static struct mxc_nand_platform_data pca100_nand_board_info = {
145static struct platform_device *platform_devices[] __initdata = { 145static struct platform_device *platform_devices[] __initdata = {
146 &mxc_w1_master_device, 146 &mxc_w1_master_device,
147 &mxc_fec_device, 147 &mxc_fec_device,
148 &mxc_wdt,
148}; 149};
149 150
150static struct imxi2c_platform_data pca100_i2c_1_data = { 151static struct imxi2c_platform_data pca100_i2c_1_data = {
diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c
index 035fbe046ec0..36c89431679a 100644
--- a/arch/arm/mach-mx2/mach-pcm038.c
+++ b/arch/arm/mach-mx2/mach-pcm038.c
@@ -182,6 +182,7 @@ static struct platform_device *platform_devices[] __initdata = {
182 &mxc_w1_master_device, 182 &mxc_w1_master_device,
183 &mxc_fec_device, 183 &mxc_fec_device,
184 &pcm038_sram_mtd_device, 184 &pcm038_sram_mtd_device,
185 &mxc_wdt,
185}; 186};
186 187
187/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and 188/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3f4b8a0b5fac..3a405fa400eb 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -500,3 +500,18 @@ struct platform_device mx25_fb_device = {
500 .coherent_dma_mask = 0xFFFFFFFF, 500 .coherent_dma_mask = 0xFFFFFFFF,
501 }, 501 },
502}; 502};
503
504static struct resource mxc_wdt_resources[] = {
505 {
506 .start = MX25_WDOG_BASE_ADDR,
507 .end = MX25_WDOG_BASE_ADDR + SZ_16K - 1,
508 .flags = IORESOURCE_MEM,
509 },
510};
511
512struct platform_device mxc_wdt = {
513 .name = "imx2-wdt",
514 .id = 0,
515 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
516 .resource = mxc_wdt_resources,
517};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index 39560e13bc0d..cee12c0a0be6 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -21,3 +21,4 @@ extern struct platform_device mx25_fec_device;
21extern struct platform_device mxc_nand_device; 21extern struct platform_device mxc_nand_device;
22extern struct platform_device mx25_rtc_device; 22extern struct platform_device mx25_rtc_device;
23extern struct platform_device mx25_fb_device; 23extern struct platform_device mx25_fb_device;
24extern struct platform_device mxc_wdt;
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 170f68e46dd5..344753fdf25e 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -82,6 +82,7 @@ config MACH_MX31MOBOARD
82config MACH_MX31LILLY 82config MACH_MX31LILLY
83 bool "Support MX31 LILLY-1131 platforms (INCO startec)" 83 bool "Support MX31 LILLY-1131 platforms (INCO startec)"
84 select ARCH_MX31 84 select ARCH_MX31
85 select MXC_ULPI if USB_ULPI
85 help 86 help
86 Include support for mx31 based LILLY1131 modules. This includes 87 Include support for mx31 based LILLY1131 modules. This includes
87 specific configurations for the board and its peripherals. 88 specific configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index f8911154a9fa..db7acd6e9101 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -582,12 +582,50 @@ static struct resource imx_wdt_resources[] = {
582}; 582};
583 583
584struct platform_device imx_wdt_device0 = { 584struct platform_device imx_wdt_device0 = {
585 .name = "imx-wdt", 585 .name = "imx2-wdt",
586 .id = 0, 586 .id = 0,
587 .num_resources = ARRAY_SIZE(imx_wdt_resources), 587 .num_resources = ARRAY_SIZE(imx_wdt_resources),
588 .resource = imx_wdt_resources, 588 .resource = imx_wdt_resources,
589}; 589};
590 590
591static struct resource imx_rtc_resources[] = {
592 {
593 .start = MX31_RTC_BASE_ADDR,
594 .end = MX31_RTC_BASE_ADDR + 0x3fff,
595 .flags = IORESOURCE_MEM,
596 },
597 {
598 .start = MX31_INT_RTC,
599 .flags = IORESOURCE_IRQ,
600 },
601};
602
603struct platform_device imx_rtc_device0 = {
604 .name = "mxc_rtc",
605 .id = -1,
606 .num_resources = ARRAY_SIZE(imx_rtc_resources),
607 .resource = imx_rtc_resources,
608};
609
610static struct resource imx_kpp_resources[] = {
611 {
612 .start = MX3x_KPP_BASE_ADDR,
613 .end = MX3x_KPP_BASE_ADDR + 0xf,
614 .flags = IORESOURCE_MEM
615 }, {
616 .start = MX3x_INT_KPP,
617 .end = MX3x_INT_KPP,
618 .flags = IORESOURCE_IRQ,
619 },
620};
621
622struct platform_device imx_kpp_device = {
623 .name = "imx-keypad",
624 .id = -1,
625 .num_resources = ARRAY_SIZE(imx_kpp_resources),
626 .resource = imx_kpp_resources,
627};
628
591static int __init mx3_devices_init(void) 629static int __init mx3_devices_init(void)
592{ 630{
593 if (cpu_is_mx31()) { 631 if (cpu_is_mx31()) {
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 4f77eb501274..2c3c8646a29e 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -27,3 +27,5 @@ extern struct platform_device imx_ssi_device0;
27extern struct platform_device imx_ssi_device1; 27extern struct platform_device imx_ssi_device1;
28extern struct platform_device imx_ssi_device1; 28extern struct platform_device imx_ssi_device1;
29extern struct platform_device imx_wdt_device0; 29extern struct platform_device imx_wdt_device0;
30extern struct platform_device imx_rtc_device0;
31extern struct platform_device imx_kpp_device;
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index f54af1e29ca4..58e57291b79d 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -16,6 +16,7 @@
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 17 */
18 18
19#include <linux/delay.h>
19#include <linux/types.h> 20#include <linux/types.h>
20#include <linux/init.h> 21#include <linux/init.h>
21#include <linux/clk.h> 22#include <linux/clk.h>
@@ -26,6 +27,8 @@
26#include <linux/mfd/mc13783.h> 27#include <linux/mfd/mc13783.h>
27#include <linux/spi/spi.h> 28#include <linux/spi/spi.h>
28#include <linux/regulator/machine.h> 29#include <linux/regulator/machine.h>
30#include <linux/fsl_devices.h>
31#include <linux/input/matrix_keypad.h>
29 32
30#include <mach/hardware.h> 33#include <mach/hardware.h>
31#include <asm/mach-types.h> 34#include <asm/mach-types.h>
@@ -65,6 +68,50 @@ static int mx31_3ds_pins[] = {
65 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ 68 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
66 /* MC13783 IRQ */ 69 /* MC13783 IRQ */
67 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), 70 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
71 /* USB OTG reset */
72 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
73 /* USB OTG */
74 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
75 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
76 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
77 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
78 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
79 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
80 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
81 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
82 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
83 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
84 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
85 MX31_PIN_USBOTG_STP__USBOTG_STP,
86 /*Keyboard*/
87 MX31_PIN_KEY_ROW0_KEY_ROW0,
88 MX31_PIN_KEY_ROW1_KEY_ROW1,
89 MX31_PIN_KEY_ROW2_KEY_ROW2,
90 MX31_PIN_KEY_COL0_KEY_COL0,
91 MX31_PIN_KEY_COL1_KEY_COL1,
92 MX31_PIN_KEY_COL2_KEY_COL2,
93 MX31_PIN_KEY_COL3_KEY_COL3,
94};
95
96/*
97 * Matrix keyboard
98 */
99
100static const uint32_t mx31_3ds_keymap[] = {
101 KEY(0, 0, KEY_UP),
102 KEY(0, 1, KEY_DOWN),
103 KEY(1, 0, KEY_RIGHT),
104 KEY(1, 1, KEY_LEFT),
105 KEY(1, 2, KEY_ENTER),
106 KEY(2, 0, KEY_F6),
107 KEY(2, 1, KEY_F8),
108 KEY(2, 2, KEY_F9),
109 KEY(2, 3, KEY_F10),
110};
111
112static struct matrix_keymap_data mx31_3ds_keymap_data = {
113 .keymap = mx31_3ds_keymap,
114 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
68}; 115};
69 116
70/* Regulators */ 117/* Regulators */
@@ -126,6 +173,41 @@ static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
126#endif 173#endif
127}; 174};
128 175
176/*
177 * USB OTG
178 */
179
180#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
181 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
182
183#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
184
185static void mx31_3ds_usbotg_init(void)
186{
187 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
188 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
189 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
190 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
191 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
192 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
193 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
194 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
195 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
196 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
197 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
198 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
199
200 gpio_request(USBOTG_RST_B, "otgusb-reset");
201 gpio_direction_output(USBOTG_RST_B, 0);
202 mdelay(1);
203 gpio_set_value(USBOTG_RST_B, 1);
204}
205
206static struct fsl_usb2_platform_data usbotg_pdata = {
207 .operating_mode = FSL_USB2_DR_DEVICE,
208 .phy_mode = FSL_USB2_PHY_ULPI,
209};
210
129static struct imxuart_platform_data uart_pdata = { 211static struct imxuart_platform_data uart_pdata = {
130 .flags = IMXUART_HAVE_RTSCTS, 212 .flags = IMXUART_HAVE_RTSCTS,
131}; 213};
@@ -315,6 +397,11 @@ static void __init mxc_board_init(void)
315 spi_register_board_info(mx31_3ds_spi_devs, 397 spi_register_board_info(mx31_3ds_spi_devs,
316 ARRAY_SIZE(mx31_3ds_spi_devs)); 398 ARRAY_SIZE(mx31_3ds_spi_devs));
317 399
400 mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);
401
402 mx31_3ds_usbotg_init();
403 mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
404
318 if (!mx31_3ds_init_expio()) 405 if (!mx31_3ds_init_expio())
319 platform_device_register(&smsc911x_device); 406 platform_device_register(&smsc911x_device);
320} 407}
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 80847b04c063..d3d5877c750e 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -27,12 +27,15 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/clk.h> 29#include <linux/clk.h>
30#include <linux/gpio.h>
30#include <linux/platform_device.h> 31#include <linux/platform_device.h>
31#include <linux/interrupt.h> 32#include <linux/interrupt.h>
32#include <linux/smsc911x.h> 33#include <linux/smsc911x.h>
33#include <linux/mtd/physmap.h> 34#include <linux/mtd/physmap.h>
34#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
35#include <linux/mfd/mc13783.h> 36#include <linux/mfd/mc13783.h>
37#include <linux/usb/otg.h>
38#include <linux/usb/ulpi.h>
36 39
37#include <asm/mach-types.h> 40#include <asm/mach-types.h>
38#include <asm/mach/arch.h> 41#include <asm/mach/arch.h>
@@ -44,6 +47,8 @@
44#include <mach/iomux-mx3.h> 47#include <mach/iomux-mx3.h>
45#include <mach/board-mx31lilly.h> 48#include <mach/board-mx31lilly.h>
46#include <mach/spi.h> 49#include <mach/spi.h>
50#include <mach/mxc_ehci.h>
51#include <mach/ulpi.h>
47 52
48#include "devices.h" 53#include "devices.h"
49 54
@@ -108,6 +113,137 @@ static struct platform_device physmap_flash_device = {
108 .num_resources = 1, 113 .num_resources = 1,
109}; 114};
110 115
116/* USB */
117
118#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
119 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
120
121static int usbotg_init(struct platform_device *pdev)
122{
123 unsigned int pins[] = {
124 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
125 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
126 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
127 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
128 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
129 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
130 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
131 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
132 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
133 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
134 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
135 MX31_PIN_USBOTG_STP__USBOTG_STP,
136 };
137
138 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG");
139
140 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
141 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
142 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
143 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
144 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
145 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
146 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
147 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
148 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
149 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
150 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
151 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
152
153 mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true);
154 mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true);
155
156 /* chip select */
157 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO),
158 "USBOTG_CS");
159 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS");
160 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0);
161
162 return 0;
163}
164
165static int usbh1_init(struct platform_device *pdev)
166{
167 int pins[] = {
168 MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
169 MX31_PIN_CSPI1_MISO__USBH1_RXDP,
170 MX31_PIN_CSPI1_SS0__USBH1_TXDM,
171 MX31_PIN_CSPI1_SS1__USBH1_TXDP,
172 MX31_PIN_CSPI1_SS2__USBH1_RCV,
173 MX31_PIN_CSPI1_SCLK__USBH1_OEB,
174 MX31_PIN_CSPI1_SPI_RDY__USBH1_FS,
175 };
176
177 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1");
178
179 mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
180 mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
181 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
182 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
183 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
184 mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
185 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
186
187 mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
188
189 return 0;
190}
191
192static int usbh2_init(struct platform_device *pdev)
193{
194 int pins[] = {
195 MX31_PIN_USBH2_DATA0__USBH2_DATA0,
196 MX31_PIN_USBH2_DATA1__USBH2_DATA1,
197 MX31_PIN_USBH2_CLK__USBH2_CLK,
198 MX31_PIN_USBH2_DIR__USBH2_DIR,
199 MX31_PIN_USBH2_NXT__USBH2_NXT,
200 MX31_PIN_USBH2_STP__USBH2_STP,
201 };
202
203 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
204
205 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
206 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
207 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
208 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
209 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
210 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
211 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
212 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
213 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
214 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
215 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
216 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
217
218 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
219
220 /* chip select */
221 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
222 "USBH2_CS");
223 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
224 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
225
226 return 0;
227}
228
229static struct mxc_usbh_platform_data usbotg_pdata = {
230 .init = usbotg_init,
231 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
232 .flags = MXC_EHCI_POWER_PINS_ENABLED,
233};
234
235static struct mxc_usbh_platform_data usbh1_pdata = {
236 .init = usbh1_init,
237 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
238 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
239};
240
241static struct mxc_usbh_platform_data usbh2_pdata = {
242 .init = usbh2_init,
243 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
244 .flags = MXC_EHCI_POWER_PINS_ENABLED,
245};
246
111static struct platform_device *devices[] __initdata = { 247static struct platform_device *devices[] __initdata = {
112 &smsc91x_device, 248 &smsc91x_device,
113 &physmap_flash_device, 249 &physmap_flash_device,
@@ -183,6 +319,15 @@ static void __init mx31lilly_board_init(void)
183 spi_register_board_info(&mc13783_dev, 1); 319 spi_register_board_info(&mc13783_dev, 1);
184 320
185 platform_add_devices(devices, ARRAY_SIZE(devices)); 321 platform_add_devices(devices, ARRAY_SIZE(devices));
322
323 /* USB */
324 usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
325 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
326 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
327 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
328
329 mxc_register_device(&mxc_usbh1, &usbh1_pdata);
330 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
186} 331}
187 332
188static void __init mx31lilly_timer_init(void) 333static void __init mx31lilly_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index fccb9207b78d..33a8d35498a7 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -18,7 +18,6 @@
18 18
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/dma-mapping.h> 20#include <linux/dma-mapping.h>
21#include <linux/fsl_devices.h>
22#include <linux/gfp.h> 21#include <linux/gfp.h>
23#include <linux/gpio.h> 22#include <linux/gpio.h>
24#include <linux/init.h> 23#include <linux/init.h>
@@ -306,84 +305,56 @@ static struct imxmmc_platform_data sdhc1_pdata = {
306 * this pin is dedicated for all mx31moboard systems, so we do it here 305 * this pin is dedicated for all mx31moboard systems, so we do it here
307 */ 306 */
308#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0) 307#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
309
310static void usb_xcvr_reset(void)
311{
312 gpio_request(USB_RESET_B, "usb-reset");
313 gpio_direction_output(USB_RESET_B, 0);
314 mdelay(1);
315 gpio_set_value(USB_RESET_B, 1);
316}
317
318#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ 308#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
319 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) 309 PAD_CTL_ODE_CMOS)
320 310
321#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC) 311#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
322
323static void moboard_usbotg_init(void)
324{
325 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
326 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
327 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
328 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
329 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
330 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
331 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
332 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
333 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
334 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
335 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
336 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
337
338 gpio_request(OTG_EN_B, "usb-udc-en");
339 gpio_direction_output(OTG_EN_B, 0);
340}
341
342static struct fsl_usb2_platform_data usb_pdata = {
343 .operating_mode = FSL_USB2_DR_DEVICE,
344 .phy_mode = FSL_USB2_PHY_ULPI,
345};
346
347#if defined(CONFIG_USB_ULPI)
348
349#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) 312#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
350 313
351static int moboard_usbh2_hw_init(struct platform_device *pdev) 314static void usb_xcvr_reset(void)
352{ 315{
353 int ret; 316 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
317 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
318 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD);
319 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD);
320 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD);
321 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD);
322 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD);
323 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD);
324 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
325 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
326 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
327 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
354 328
355 mxc_iomux_set_gpr(MUX_PGP_UH2, true); 329 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
330 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
331 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
332 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
333 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
334 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
335 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
336 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
337 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
338 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD);
339 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD);
340 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
341 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
356 342
357 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); 343 gpio_request(OTG_EN_B, "usb-udc-en");
358 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); 344 gpio_direction_output(OTG_EN_B, 0);
359 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); 345 gpio_request(USBH2_EN_B, "usbh2-en");
360 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
361 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
362 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
363 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
364 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
365 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
366 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
367 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
368 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
369
370 ret = gpio_request(USBH2_EN_B, "usbh2-en");
371 if (ret)
372 return ret;
373 gpio_direction_output(USBH2_EN_B, 0); 346 gpio_direction_output(USBH2_EN_B, 0);
374 347
375 return 0; 348 gpio_request(USB_RESET_B, "usb-reset");
349 gpio_direction_output(USB_RESET_B, 0);
350 mdelay(1);
351 gpio_set_value(USB_RESET_B, 1);
352 mdelay(1);
376} 353}
377 354
378static int moboard_usbh2_hw_exit(struct platform_device *pdev) 355#if defined(CONFIG_USB_ULPI)
379{
380 gpio_free(USBH2_EN_B);
381 return 0;
382}
383 356
384static struct mxc_usbh_platform_data usbh2_pdata = { 357static struct mxc_usbh_platform_data usbh2_pdata = {
385 .init = moboard_usbh2_hw_init,
386 .exit = moboard_usbh2_hw_exit,
387 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 358 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
388 .flags = MXC_EHCI_POWER_PINS_ENABLED, 359 .flags = MXC_EHCI_POWER_PINS_ENABLED,
389}; 360};
@@ -508,8 +479,6 @@ static void __init mxc_board_init(void)
508 479
509 usb_xcvr_reset(); 480 usb_xcvr_reset();
510 481
511 moboard_usbotg_init();
512 mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
513 moboard_usbh2_init(); 482 moboard_usbh2_init();
514 483
515 switch (mx31moboard_baseboard) { 484 switch (mx31moboard_baseboard) {
@@ -522,7 +491,8 @@ static void __init mxc_board_init(void)
522 mx31moboard_marxbot_init(); 491 mx31moboard_marxbot_init();
523 break; 492 break;
524 case MX31SMARTBOT: 493 case MX31SMARTBOT:
525 mx31moboard_smartbot_init(); 494 case MX31EYEBOT:
495 mx31moboard_smartbot_init(mx31moboard_baseboard);
526 break; 496 break;
527 default: 497 default:
528 printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", 498 printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n",
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 2df1ec55a97e..5024284d6455 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -449,6 +449,7 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size)
449static struct platform_device *devices[] __initdata = { 449static struct platform_device *devices[] __initdata = {
450 &pcm037_flash, 450 &pcm037_flash,
451 &pcm037_sram_device, 451 &pcm037_sram_device,
452 &imx_wdt_device0,
452 &pcm037_mt9t031, 453 &pcm037_mt9t031,
453 &pcm037_mt9v022, 454 &pcm037_mt9v022,
454}; 455};
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 1bf1ec2eef5e..78d9185a9d4b 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -150,6 +150,7 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
150static struct platform_device *devices[] __initdata = { 150static struct platform_device *devices[] __initdata = {
151 &pcm043_flash, 151 &pcm043_flash,
152 &mxc_fec_device, 152 &mxc_fec_device,
153 &imx_wdt_device0,
153}; 154};
154 155
155static struct pad_desc pcm043_pads[] = { 156static struct pad_desc pcm043_pads[] = {
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index 093c595ca581..5f05bfbec380 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -206,5 +206,6 @@ void __init mx31lite_db_init(void)
206 mxc_register_device(&mxc_spi_device0, &spi0_pdata); 206 mxc_register_device(&mxc_spi_device0, &spi0_pdata);
207 platform_device_register(&litekit_led_device); 207 platform_device_register(&litekit_led_device);
208 mxc_register_device(&imx_wdt_device0, NULL); 208 mxc_register_device(&imx_wdt_device0, NULL);
209 mxc_register_device(&imx_rtc_device0, NULL);
209} 210}
210 211
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 11b906ce7eae..582299cb2c08 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -22,6 +22,7 @@
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/slab.h> 23#include <linux/slab.h>
24#include <linux/types.h> 24#include <linux/types.h>
25#include <linux/fsl_devices.h>
25 26
26#include <linux/usb/otg.h> 27#include <linux/usb/otg.h>
27 28
@@ -213,6 +214,12 @@ static int __init devboard_usbh1_init(void)
213 return mxc_register_device(&mxc_usbh1, &usbh1_pdata); 214 return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
214} 215}
215 216
217
218static struct fsl_usb2_platform_data usb_pdata = {
219 .operating_mode = FSL_USB2_DR_DEVICE,
220 .phy_mode = FSL_USB2_PHY_ULPI,
221};
222
216/* 223/*
217 * system init for baseboard usage. Will be called by mx31moboard init. 224 * system init for baseboard usage. Will be called by mx31moboard init.
218 */ 225 */
@@ -229,5 +236,7 @@ void __init mx31moboard_devboard_init(void)
229 236
230 devboard_init_sel_gpios(); 237 devboard_init_sel_gpios();
231 238
239 mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
240
232 devboard_usbh1_init(); 241 devboard_usbh1_init();
233} 242}
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index ffb105e14d88..4930f8c27e66 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -25,6 +25,7 @@
25#include <linux/slab.h> 25#include <linux/slab.h>
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/types.h> 27#include <linux/types.h>
28#include <linux/fsl_devices.h>
28 29
29#include <linux/usb/otg.h> 30#include <linux/usb/otg.h>
30 31
@@ -329,6 +330,11 @@ static int __init marxbot_usbh1_init(void)
329 return mxc_register_device(&mxc_usbh1, &usbh1_pdata); 330 return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
330} 331}
331 332
333static struct fsl_usb2_platform_data usb_pdata = {
334 .operating_mode = FSL_USB2_DR_DEVICE,
335 .phy_mode = FSL_USB2_PHY_ULPI,
336};
337
332/* 338/*
333 * system init for baseboard usage. Will be called by mx31moboard init. 339 * system init for baseboard usage. Will be called by mx31moboard init.
334 */ 340 */
@@ -356,5 +362,7 @@ void __init mx31moboard_marxbot_init(void)
356 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); 362 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
357 gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); 363 gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
358 364
365 mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
366
359 marxbot_usbh1_init(); 367 marxbot_usbh1_init();
360} 368}
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index 52a69fc8b14f..293eea6d9d97 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -23,11 +23,18 @@
23#include <linux/i2c.h> 23#include <linux/i2c.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/types.h> 25#include <linux/types.h>
26#include <linux/fsl_devices.h>
27
28#include <linux/usb/otg.h>
29#include <linux/usb/ulpi.h>
26 30
27#include <mach/common.h> 31#include <mach/common.h>
28#include <mach/hardware.h> 32#include <mach/hardware.h>
29#include <mach/imx-uart.h> 33#include <mach/imx-uart.h>
30#include <mach/iomux-mx3.h> 34#include <mach/iomux-mx3.h>
35#include <mach/board-mx31moboard.h>
36#include <mach/mxc_ehci.h>
37#include <mach/ulpi.h>
31 38
32#include <media/soc_camera.h> 39#include <media/soc_camera.h>
33 40
@@ -116,10 +123,33 @@ static int __init smartbot_cam_init(void)
116 return 0; 123 return 0;
117} 124}
118 125
126static struct fsl_usb2_platform_data usb_pdata = {
127 .operating_mode = FSL_USB2_DR_DEVICE,
128 .phy_mode = FSL_USB2_PHY_ULPI,
129};
130
131#if defined(CONFIG_USB_ULPI)
132
133static struct mxc_usbh_platform_data otg_host_pdata = {
134 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
135 .flags = MXC_EHCI_POWER_PINS_ENABLED,
136};
137
138static int __init smartbot_otg_host_init(void)
139{
140 otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
141 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
142
143 return mxc_register_device(&mxc_otg_host, &otg_host_pdata);
144}
145#else
146static inline int smartbot_otg_host_init(void) { return 0; }
147#endif
148
119#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) 149#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
120#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) 150#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
121#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) 151#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
122#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) 152#define TRSLAT_SRC_CHOICE IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
123 153
124static void smartbot_resets_init(void) 154static void smartbot_resets_init(void)
125{ 155{
@@ -138,15 +168,15 @@ static void smartbot_resets_init(void)
138 gpio_export(TRSLAT_RST_B, false); 168 gpio_export(TRSLAT_RST_B, false);
139 } 169 }
140 170
141 if (!gpio_request(SEL3, "sel3")) { 171 if (!gpio_request(TRSLAT_SRC_CHOICE, "translator-src-choice")) {
142 gpio_direction_input(SEL3); 172 gpio_direction_output(TRSLAT_SRC_CHOICE, 0);
143 gpio_export(SEL3, true); 173 gpio_export(TRSLAT_SRC_CHOICE, false);
144 } 174 }
145} 175}
146/* 176/*
147 * system init for baseboard usage. Will be called by mx31moboard init. 177 * system init for baseboard usage. Will be called by mx31moboard init.
148 */ 178 */
149void __init mx31moboard_smartbot_init(void) 179void __init mx31moboard_smartbot_init(int board)
150{ 180{
151 printk(KERN_INFO "Initializing mx31smartbot peripherals\n"); 181 printk(KERN_INFO "Initializing mx31smartbot peripherals\n");
152 182
@@ -155,6 +185,19 @@ void __init mx31moboard_smartbot_init(void)
155 185
156 mxc_register_device(&mxc_uart_device1, &uart_pdata); 186 mxc_register_device(&mxc_uart_device1, &uart_pdata);
157 187
188
189 switch (board) {
190 case MX31SMARTBOT:
191 mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
192 break;
193 case MX31EYEBOT:
194 smartbot_otg_host_init();
195 break;
196 default:
197 printk(KERN_WARNING "Unknown board %d, USB OTG not initialized",
198 board);
199 }
200
158 smartbot_resets_init(); 201 smartbot_resets_init();
159 202
160 smartbot_cam_init(); 203 smartbot_cam_init();
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index ee67a71db80d..ed885f9d7b73 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -12,11 +12,16 @@
12 12
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/gpio.h>
16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/fsl_devices.h>
15 19
16#include <mach/common.h> 20#include <mach/common.h>
17#include <mach/hardware.h> 21#include <mach/hardware.h>
18#include <mach/imx-uart.h> 22#include <mach/imx-uart.h>
19#include <mach/iomux-mx51.h> 23#include <mach/iomux-mx51.h>
24#include <mach/mxc_ehci.h>
20 25
21#include <asm/irq.h> 26#include <asm/irq.h>
22#include <asm/setup.h> 27#include <asm/setup.h>
@@ -26,6 +31,18 @@
26 31
27#include "devices.h" 32#include "devices.h"
28 33
34#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
35#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
36#define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */
37
38/* USB_CTRL_1 */
39#define MX51_USB_CTRL_1_OFFSET 0x10
40#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
41
42#define MX51_USB_PLLDIV_12_MHZ 0x00
43#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
44#define MX51_USB_PLL_DIV_24_MHZ 0x02
45
29static struct platform_device *devices[] __initdata = { 46static struct platform_device *devices[] __initdata = {
30 &mxc_fec_device, 47 &mxc_fec_device,
31}; 48};
@@ -46,6 +63,22 @@ static struct pad_desc mx51babbage_pads[] = {
46 MX51_PAD_EIM_D26__UART3_TXD, 63 MX51_PAD_EIM_D26__UART3_TXD,
47 MX51_PAD_EIM_D27__UART3_RTS, 64 MX51_PAD_EIM_D27__UART3_RTS,
48 MX51_PAD_EIM_D24__UART3_CTS, 65 MX51_PAD_EIM_D24__UART3_CTS,
66
67 /* USB HOST1 */
68 MX51_PAD_USBH1_CLK__USBH1_CLK,
69 MX51_PAD_USBH1_DIR__USBH1_DIR,
70 MX51_PAD_USBH1_NXT__USBH1_NXT,
71 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
72 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
73 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
74 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
75 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
76 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
77 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
78 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
79
80 /* USB HUB reset line*/
81 MX51_PAD_GPIO_1_7__GPIO1_7,
49}; 82};
50 83
51/* Serial ports */ 84/* Serial ports */
@@ -66,15 +99,149 @@ static inline void mxc_init_imx_uart(void)
66} 99}
67#endif /* SERIAL_IMX */ 100#endif /* SERIAL_IMX */
68 101
102static int gpio_usbh1_active(void)
103{
104 struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
105 struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
106 int ret;
107
108 /* Set USBH1_STP to GPIO and toggle it */
109 mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
110 ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
111
112 if (ret) {
113 pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
114 return ret;
115 }
116 gpio_direction_output(BABBAGE_USBH1_STP, 0);
117 gpio_set_value(BABBAGE_USBH1_STP, 1);
118 msleep(100);
119 gpio_free(BABBAGE_USBH1_STP);
120
121 /* De-assert USB PHY RESETB */
122 mxc_iomux_v3_setup_pad(&phyreset_gpio);
123 ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
124
125 if (ret) {
126 pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
127 return ret;
128 }
129 gpio_direction_output(BABBAGE_PHY_RESET, 1);
130 return 0;
131}
132
133static inline void babbage_usbhub_reset(void)
134{
135 int ret;
136
137 /* Bring USB hub out of reset */
138 ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
139 if (ret) {
140 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
141 return;
142 }
143 gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
144
145 /* USB HUB RESET - De-assert USB HUB RESET_N */
146 msleep(1);
147 gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
148 msleep(1);
149 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
150}
151
152/* This function is board specific as the bit mask for the plldiv will also
153be different for other Freescale SoCs, thus a common bitmask is not
154possible and cannot get place in /plat-mxc/ehci.c.*/
155static int initialize_otg_port(struct platform_device *pdev)
156{
157 u32 v;
158 void __iomem *usb_base;
159 u32 usbother_base;
160
161 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
162 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
163
164 /* Set the PHY clock to 19.2MHz */
165 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
166 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
167 v |= MX51_USB_PLL_DIV_19_2_MHZ;
168 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
169 iounmap(usb_base);
170 return 0;
171}
172
173static int initialize_usbh1_port(struct platform_device *pdev)
174{
175 u32 v;
176 void __iomem *usb_base;
177 u32 usbother_base;
178
179 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
180 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
181
182 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
183 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
184 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
185 iounmap(usb_base);
186 return 0;
187}
188
189static struct mxc_usbh_platform_data dr_utmi_config = {
190 .init = initialize_otg_port,
191 .portsc = MXC_EHCI_UTMI_16BIT,
192 .flags = MXC_EHCI_INTERNAL_PHY,
193};
194
195static struct fsl_usb2_platform_data usb_pdata = {
196 .operating_mode = FSL_USB2_DR_DEVICE,
197 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
198};
199
200static struct mxc_usbh_platform_data usbh1_config = {
201 .init = initialize_usbh1_port,
202 .portsc = MXC_EHCI_MODE_ULPI,
203 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
204};
205
206static int otg_mode_host;
207
208static int __init babbage_otg_mode(char *options)
209{
210 if (!strcmp(options, "host"))
211 otg_mode_host = 1;
212 else if (!strcmp(options, "device"))
213 otg_mode_host = 0;
214 else
215 pr_info("otg_mode neither \"host\" nor \"device\". "
216 "Defaulting to device\n");
217 return 0;
218}
219__setup("otg_mode=", babbage_otg_mode);
220
69/* 221/*
70 * Board specific initialization. 222 * Board specific initialization.
71 */ 223 */
72static void __init mxc_board_init(void) 224static void __init mxc_board_init(void)
73{ 225{
226 struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
227
74 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, 228 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
75 ARRAY_SIZE(mx51babbage_pads)); 229 ARRAY_SIZE(mx51babbage_pads));
76 mxc_init_imx_uart(); 230 mxc_init_imx_uart();
77 platform_add_devices(devices, ARRAY_SIZE(devices)); 231 platform_add_devices(devices, ARRAY_SIZE(devices));
232
233 if (otg_mode_host)
234 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
235 else {
236 initialize_otg_port(NULL);
237 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
238 }
239
240 gpio_usbh1_active();
241 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
242 /* setback USBH1_STP to be function */
243 mxc_iomux_v3_setup_pad(&usbh1stp);
244 babbage_usbhub_reset();
78} 245}
79 246
80static void __init mx51_babbage_timer_init(void) 247static void __init mx51_babbage_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 1ee6ce4087b8..d9f612d3370e 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -37,6 +37,7 @@ static struct clk lp_apm_clk;
37static struct clk periph_apm_clk; 37static struct clk periph_apm_clk;
38static struct clk ahb_clk; 38static struct clk ahb_clk;
39static struct clk ipg_clk; 39static struct clk ipg_clk;
40static struct clk usboh3_clk;
40 41
41#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ 42#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
42 43
@@ -570,6 +571,35 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
570 return 0; 571 return 0;
571} 572}
572 573
574static unsigned long clk_usboh3_get_rate(struct clk *clk)
575{
576 u32 reg, prediv, podf;
577 unsigned long parent_rate;
578
579 parent_rate = clk_get_rate(clk->parent);
580
581 reg = __raw_readl(MXC_CCM_CSCDR1);
582 prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
583 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
584 podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
585 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
586
587 return parent_rate / (prediv * podf);
588}
589
590static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent)
591{
592 u32 reg, mux;
593
594 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
595 &lp_apm_clk);
596 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
597 reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
598 __raw_writel(reg, MXC_CCM_CSCMR1);
599
600 return 0;
601}
602
573static unsigned long get_high_reference_clock_rate(struct clk *clk) 603static unsigned long get_high_reference_clock_rate(struct clk *clk)
574{ 604{
575 return external_high_reference; 605 return external_high_reference;
@@ -691,6 +721,12 @@ static struct clk uart_root_clk = {
691 .set_parent = _clk_uart_set_parent, 721 .set_parent = _clk_uart_set_parent,
692}; 722};
693 723
724static struct clk usboh3_clk = {
725 .parent = &pll2_sw_clk,
726 .get_rate = clk_usboh3_get_rate,
727 .set_parent = _clk_usboh3_set_parent,
728};
729
694static struct clk ahb_max_clk = { 730static struct clk ahb_max_clk = {
695 .parent = &ahb_clk, 731 .parent = &ahb_clk,
696 .enable_reg = MXC_CCM_CCGR0, 732 .enable_reg = MXC_CCM_CCGR0,
@@ -779,6 +815,12 @@ static struct clk_lookup lookups[] = {
779 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) 815 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
780 _REGISTER_CLOCK(NULL, "gpt", gpt_clk) 816 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
781 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 817 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
818 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
819 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
820 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
821 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
822 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
823 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
782}; 824};
783 825
784static void clk_tree_init(void) 826static void clk_tree_init(void)
@@ -819,6 +861,9 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
819 clk_enable(&cpu_clk); 861 clk_enable(&cpu_clk);
820 clk_enable(&main_bus_clk); 862 clk_enable(&main_bus_clk);
821 863
864 /* set the usboh3_clk parent to pll2_sw_clk */
865 clk_set_parent(&usboh3_clk, &pll2_sw_clk);
866
822 /* System timer */ 867 /* System timer */
823 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), 868 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
824 MX51_MXC_INT_GPT); 869 MX51_MXC_INT_GPT);
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index d6fd3961ade9..7130449aacdc 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com> 2 * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 * 4 *
4 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License 6 * License. You may obtain a copy of the GNU General Public License
@@ -10,8 +11,11 @@
10 */ 11 */
11 12
12#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h>
15#include <linux/gpio.h>
13#include <mach/hardware.h> 16#include <mach/hardware.h>
14#include <mach/imx-uart.h> 17#include <mach/imx-uart.h>
18#include <mach/irqs.h>
15 19
16static struct resource uart0[] = { 20static struct resource uart0[] = {
17 { 21 {
@@ -89,8 +93,109 @@ struct platform_device mxc_fec_device = {
89 .resource = mxc_fec_resources, 93 .resource = mxc_fec_resources,
90}; 94};
91 95
92/* Dummy definition to allow compiling in AVIC and TZIC simultaneously */ 96static u64 usb_dma_mask = DMA_BIT_MASK(32);
97
98static struct resource usbotg_resources[] = {
99 {
100 .start = MX51_OTG_BASE_ADDR,
101 .end = MX51_OTG_BASE_ADDR + 0x1ff,
102 .flags = IORESOURCE_MEM,
103 },
104 {
105 .start = MX51_MXC_INT_USB_OTG,
106 .flags = IORESOURCE_IRQ,
107 },
108};
109
110/* OTG gadget device */
111struct platform_device mxc_usbdr_udc_device = {
112 .name = "fsl-usb2-udc",
113 .id = -1,
114 .num_resources = ARRAY_SIZE(usbotg_resources),
115 .resource = usbotg_resources,
116 .dev = {
117 .dma_mask = &usb_dma_mask,
118 .coherent_dma_mask = DMA_BIT_MASK(32),
119 },
120};
121
122struct platform_device mxc_usbdr_host_device = {
123 .name = "mxc-ehci",
124 .id = 0,
125 .num_resources = ARRAY_SIZE(usbotg_resources),
126 .resource = usbotg_resources,
127 .dev = {
128 .dma_mask = &usb_dma_mask,
129 .coherent_dma_mask = DMA_BIT_MASK(32),
130 },
131};
132
133static struct resource usbh1_resources[] = {
134 {
135 .start = MX51_OTG_BASE_ADDR + 0x200,
136 .end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff,
137 .flags = IORESOURCE_MEM,
138 },
139 {
140 .start = MX51_MXC_INT_USB_H1,
141 .flags = IORESOURCE_IRQ,
142 },
143};
144
145struct platform_device mxc_usbh1_device = {
146 .name = "mxc-ehci",
147 .id = 1,
148 .num_resources = ARRAY_SIZE(usbh1_resources),
149 .resource = usbh1_resources,
150 .dev = {
151 .dma_mask = &usb_dma_mask,
152 .coherent_dma_mask = DMA_BIT_MASK(32),
153 },
154};
155
156static struct resource mxc_wdt_resources[] = {
157 {
158 .start = MX51_WDOG_BASE_ADDR,
159 .end = MX51_WDOG_BASE_ADDR + SZ_16K - 1,
160 .flags = IORESOURCE_MEM,
161 },
162};
163
164struct platform_device mxc_wdt = {
165 .name = "imx2-wdt",
166 .id = 0,
167 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
168 .resource = mxc_wdt_resources,
169};
170
171static struct mxc_gpio_port mxc_gpio_ports[] = {
172 {
173 .chip.label = "gpio-0",
174 .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR),
175 .irq = MX51_MXC_INT_GPIO1_LOW,
176 .virtual_irq_start = MXC_GPIO_IRQ_START
177 },
178 {
179 .chip.label = "gpio-1",
180 .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR),
181 .irq = MX51_MXC_INT_GPIO2_LOW,
182 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
183 },
184 {
185 .chip.label = "gpio-2",
186 .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR),
187 .irq = MX51_MXC_INT_GPIO3_LOW,
188 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
189 },
190 {
191 .chip.label = "gpio-3",
192 .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR),
193 .irq = MX51_MXC_INT_GPIO4_LOW,
194 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
195 },
196};
197
93int __init mxc_register_gpios(void) 198int __init mxc_register_gpios(void)
94{ 199{
95 return 0; 200 return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
96} 201}
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index f339ab8c19be..c879ae71cd5b 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -2,3 +2,7 @@ extern struct platform_device mxc_uart_device0;
2extern struct platform_device mxc_uart_device1; 2extern struct platform_device mxc_uart_device1;
3extern struct platform_device mxc_uart_device2; 3extern struct platform_device mxc_uart_device2;
4extern struct platform_device mxc_fec_device; 4extern struct platform_device mxc_fec_device;
5extern struct platform_device mxc_usbdr_host_device;
6extern struct platform_device mxc_usbh1_device;
7extern struct platform_device mxc_usbdr_udc_device;
8extern struct platform_device mxc_wdt;
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index cb0b63874482..2a8646173c2f 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -50,7 +51,26 @@
50#define MX35_H1_TLL_BIT (1 << 5) 51#define MX35_H1_TLL_BIT (1 << 5)
51#define MX35_H1_USBTE_BIT (1 << 4) 52#define MX35_H1_USBTE_BIT (1 << 4)
52 53
53int mxc_set_usbcontrol(int port, unsigned int flags) 54#define MXC_OTG_OFFSET 0
55#define MXC_H1_OFFSET 0x200
56
57/* USB_CTRL */
58#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
59#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
60#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
61#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
62#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
63
64/* USB_PHY_CTRL_FUNC */
65#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
66#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
67
68#define MXC_USBCMD_OFFSET 0x140
69
70/* USBCMD */
71#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
72
73int mxc_initialize_usb_hw(int port, unsigned int flags)
54{ 74{
55 unsigned int v; 75 unsigned int v;
56#ifdef CONFIG_ARCH_MX3 76#ifdef CONFIG_ARCH_MX3
@@ -186,9 +206,85 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
186 return 0; 206 return 0;
187 } 207 }
188#endif /* CONFIG_MACH_MX27 */ 208#endif /* CONFIG_MACH_MX27 */
209#ifdef CONFIG_ARCH_MX51
210 if (cpu_is_mx51()) {
211 void __iomem *usb_base;
212 u32 usbotg_base;
213 u32 usbother_base;
214 int ret = 0;
215
216 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
217
218 switch (port) {
219 case 0: /* OTG port */
220 usbotg_base = usb_base + MXC_OTG_OFFSET;
221 break;
222 case 1: /* Host 1 port */
223 usbotg_base = usb_base + MXC_H1_OFFSET;
224 break;
225 default:
226 printk(KERN_ERR"%s no such port %d\n", __func__, port);
227 ret = -ENOENT;
228 goto error;
229 }
230 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
231
232 switch (port) {
233 case 0: /*OTG port */
234 if (flags & MXC_EHCI_INTERNAL_PHY) {
235 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
236
237 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
238 v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */
239 else
240 v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */
241 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
242
243 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
244 if (flags & MXC_EHCI_WAKEUP_ENABLED)
245 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
246 else
247 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
248 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
249 }
250 break;
251 case 1: /* Host 1 */
252 /*Host ULPI */
253 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
254 if (flags & MXC_EHCI_WAKEUP_ENABLED)
255 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
256 else
257 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
258
259 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
260 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
261 else
262 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
263 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
264
265 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
266 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
267 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
268 else
269 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
270 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
271
272 v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
273 if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
274 /* Interrupt Threshold Control:Immediate (no threshold) */
275 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
276 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
277 break;
278 }
279
280error:
281 iounmap(usb_base);
282 return ret;
283 }
284#endif
189 printk(KERN_WARNING 285 printk(KERN_WARNING
190 "%s() unable to setup USBCONTROL for this CPU\n", __func__); 286 "%s() unable to setup USBCONTROL for this CPU\n", __func__);
191 return -EINVAL; 287 return -EINVAL;
192} 288}
193EXPORT_SYMBOL(mxc_set_usbcontrol); 289EXPORT_SYMBOL(mxc_initialize_usb_hw);
194 290
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 70b23893f094..71437c61cfd7 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -3,7 +3,7 @@
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * 4 *
5 * Based on code from Freescale, 5 * Based on code from Freescale,
6 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. 6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License 9 * modify it under the terms of the GNU General Public License
@@ -38,7 +38,6 @@ static int gpio_table_size;
38#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10) 38#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
39#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14) 39#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
40#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) 40#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
41#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
42 41
43#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0) 42#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
44#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1) 43#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
@@ -289,7 +288,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
289 /* its a serious configuration bug when it fails */ 288 /* its a serious configuration bug when it fails */
290 BUG_ON( gpiochip_add(&port[i].chip) < 0 ); 289 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
291 290
292 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) { 291 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
293 /* setup one handler for each entry */ 292 /* setup one handler for each entry */
294 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); 293 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
295 set_irq_data(port[i].irq, &port[i]); 294 set_irq_data(port[i].irq, &port[i]);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index fc5fec9b55f0..36ff3cedee1a 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -26,6 +26,7 @@ enum mx31moboard_boards {
26 MX31DEVBOARD = 1, 26 MX31DEVBOARD = 1,
27 MX31MARXBOT = 2, 27 MX31MARXBOT = 2,
28 MX31SMARTBOT = 3, 28 MX31SMARTBOT = 3,
29 MX31EYEBOT = 4,
29}; 30};
30 31
31/* 32/*
@@ -35,7 +36,7 @@ enum mx31moboard_boards {
35 36
36extern void mx31moboard_devboard_init(void); 37extern void mx31moboard_devboard_init(void);
37extern void mx31moboard_marxbot_init(void); 38extern void mx31moboard_marxbot_init(void);
38extern void mx31moboard_smartbot_init(void); 39extern void mx31moboard_smartbot_init(int board);
39 40
40#endif 41#endif
41 42
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index e51465d7b224..cbaed295a2bf 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -719,6 +719,23 @@ enum iomux_pins {
719#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) 719#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
720#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) 720#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
721#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) 721#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
722#define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC)
723#define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC)
724#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
725#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
726#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
727#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
728#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
729#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
730#define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC)
731#define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC)
732#define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC)
733#define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC)
734#define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC)
735#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC)
736#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC)
737#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC)
738
722 739
723/* 740/*
724 * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, 741 * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index b4f975e6a665..ab0f95d953d0 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> 2 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 * 4 *
4 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License 6 * License. You may obtain a copy of the GNU General Public License
@@ -37,6 +38,11 @@ typedef enum iomux_config {
37 PAD_CTL_SRE_FAST) 38 PAD_CTL_SRE_FAST)
38#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ 39#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
39 PAD_CTL_SRE_FAST) 40 PAD_CTL_SRE_FAST)
41#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
42 PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
43 PAD_CTL_PKE | PAD_CTL_HYS)
44#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
45 PAD_CTL_SRE_FAST)
40 46
41/* 47/*
42 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> 48 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
@@ -57,6 +63,7 @@ typedef enum iomux_config {
57#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) 63#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL)
58#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) 64#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL)
59#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) 65#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL)
66#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_GPIO_PAD_CTRL)
60#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) 67#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL)
61#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) 68#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL)
62 69
@@ -208,18 +215,19 @@ typedef enum iomux_config {
208#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) 215#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
209#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) 216#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
210#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) 217#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
211#define MX51_PAD_GPIO_1_25__USBH1_CLK IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL) 218#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
212#define MX51_PAD_GPIO_1_26__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL) 219#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
213#define MX51_PAD_GPIO_1_27__USBH1_STP IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL) 220#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
214#define MX51_PAD_GPIO_1_28__USBH1_NXT IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL) 221#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
215#define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL) 222#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
216#define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL) 223#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
217#define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL) 224#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
218#define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL) 225#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
219#define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL) 226#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
220#define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) 227#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
221#define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL) 228#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
222#define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL) 229#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
230#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
223#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) 231#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
224#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) 232#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
225#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) 233#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
@@ -299,7 +307,7 @@ typedef enum iomux_config {
299#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) 307#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
300#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) 308#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
301#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) 309#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
302#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL) 310#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
303#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ 311#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
304 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) 312 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS))
305#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) 313#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 4b9b8368c0c0..7fc5f9946199 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -25,6 +25,18 @@
25#define MXC_EHCI_INTERNAL_PHY (1 << 7) 25#define MXC_EHCI_INTERNAL_PHY (1 << 7)
26#define MXC_EHCI_IPPUE_DOWN (1 << 8) 26#define MXC_EHCI_IPPUE_DOWN (1 << 8)
27#define MXC_EHCI_IPPUE_UP (1 << 9) 27#define MXC_EHCI_IPPUE_UP (1 << 9)
28#define MXC_EHCI_WAKEUP_ENABLED (1 << 10)
29#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 11)
30
31#define MXC_USBCTRL_OFFSET 0
32#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
33#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
34
35#define MX5_USBOTHER_REGS_OFFSET 0x800
36
37/* USB_PHY_CTRL_FUNC2*/
38#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK 0x3
39#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_SHIFT 0
28 40
29struct mxc_usbh_platform_data { 41struct mxc_usbh_platform_data {
30 int (*init)(struct platform_device *pdev); 42 int (*init)(struct platform_device *pdev);
@@ -35,7 +47,7 @@ struct mxc_usbh_platform_data {
35 struct otg_transceiver *otg; 47 struct otg_transceiver *otg;
36}; 48};
37 49
38int mxc_set_usbcontrol(int port, unsigned int flags); 50int mxc_initialize_usb_hw(int port, unsigned int flags);
39 51
40#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */ 52#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
41 53
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index c1ce51abdba6..f9a1b059a76c 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -54,14 +54,14 @@
54#define MX2_TSTAT_COMP (1 << 0) 54#define MX2_TSTAT_COMP (1 << 0)
55 55
56/* MX31, MX35, MX25, MXC91231, MX5 */ 56/* MX31, MX35, MX25, MXC91231, MX5 */
57#define MX3_TCTL_WAITEN (1 << 3) /* Wait enable mode */ 57#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
58#define MX3_TCTL_CLK_IPG (1 << 6) 58#define V2_TCTL_CLK_IPG (1 << 6)
59#define MX3_TCTL_FRR (1 << 9) 59#define V2_TCTL_FRR (1 << 9)
60#define MX3_IR 0x0c 60#define V2_IR 0x0c
61#define MX3_TSTAT 0x08 61#define V2_TSTAT 0x08
62#define MX3_TSTAT_OF1 (1 << 0) 62#define V2_TSTAT_OF1 (1 << 0)
63#define MX3_TCN 0x24 63#define V2_TCN 0x24
64#define MX3_TCMP 0x10 64#define V2_TCMP 0x10
65 65
66#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) 66#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
67#define timer_is_v2() (!timer_is_v1()) 67#define timer_is_v2() (!timer_is_v1())
@@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void)
76 unsigned int tmp; 76 unsigned int tmp;
77 77
78 if (timer_is_v2()) 78 if (timer_is_v2())
79 __raw_writel(0, timer_base + MX3_IR); 79 __raw_writel(0, timer_base + V2_IR);
80 else { 80 else {
81 tmp = __raw_readl(timer_base + MXC_TCTL); 81 tmp = __raw_readl(timer_base + MXC_TCTL);
82 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); 82 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
@@ -86,7 +86,7 @@ static inline void gpt_irq_disable(void)
86static inline void gpt_irq_enable(void) 86static inline void gpt_irq_enable(void)
87{ 87{
88 if (timer_is_v2()) 88 if (timer_is_v2())
89 __raw_writel(1<<0, timer_base + MX3_IR); 89 __raw_writel(1<<0, timer_base + V2_IR);
90 else { 90 else {
91 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, 91 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
92 timer_base + MXC_TCTL); 92 timer_base + MXC_TCTL);
@@ -102,7 +102,7 @@ static void gpt_irq_acknowledge(void)
102 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, 102 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
103 timer_base + MX1_2_TSTAT); 103 timer_base + MX1_2_TSTAT);
104 } else if (timer_is_v2()) 104 } else if (timer_is_v2())
105 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); 105 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
106} 106}
107 107
108static cycle_t mx1_2_get_cycles(struct clocksource *cs) 108static cycle_t mx1_2_get_cycles(struct clocksource *cs)
@@ -110,9 +110,9 @@ static cycle_t mx1_2_get_cycles(struct clocksource *cs)
110 return __raw_readl(timer_base + MX1_2_TCN); 110 return __raw_readl(timer_base + MX1_2_TCN);
111} 111}
112 112
113static cycle_t mx3_get_cycles(struct clocksource *cs) 113static cycle_t v2_get_cycles(struct clocksource *cs)
114{ 114{
115 return __raw_readl(timer_base + MX3_TCN); 115 return __raw_readl(timer_base + V2_TCN);
116} 116}
117 117
118static struct clocksource clocksource_mxc = { 118static struct clocksource clocksource_mxc = {
@@ -129,7 +129,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
129 unsigned int c = clk_get_rate(timer_clk); 129 unsigned int c = clk_get_rate(timer_clk);
130 130
131 if (timer_is_v2()) 131 if (timer_is_v2())
132 clocksource_mxc.read = mx3_get_cycles; 132 clocksource_mxc.read = v2_get_cycles;
133 133
134 clocksource_mxc.mult = clocksource_hz2mult(c, 134 clocksource_mxc.mult = clocksource_hz2mult(c,
135 clocksource_mxc.shift); 135 clocksource_mxc.shift);
@@ -153,16 +153,16 @@ static int mx1_2_set_next_event(unsigned long evt,
153 -ETIME : 0; 153 -ETIME : 0;
154} 154}
155 155
156static int mx3_set_next_event(unsigned long evt, 156static int v2_set_next_event(unsigned long evt,
157 struct clock_event_device *unused) 157 struct clock_event_device *unused)
158{ 158{
159 unsigned long tcmp; 159 unsigned long tcmp;
160 160
161 tcmp = __raw_readl(timer_base + MX3_TCN) + evt; 161 tcmp = __raw_readl(timer_base + V2_TCN) + evt;
162 162
163 __raw_writel(tcmp, timer_base + MX3_TCMP); 163 __raw_writel(tcmp, timer_base + V2_TCMP);
164 164
165 return (int)(tcmp - __raw_readl(timer_base + MX3_TCN)) < 0 ? 165 return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
166 -ETIME : 0; 166 -ETIME : 0;
167} 167}
168 168
@@ -192,8 +192,8 @@ static void mxc_set_mode(enum clock_event_mode mode,
192 if (mode != clockevent_mode) { 192 if (mode != clockevent_mode) {
193 /* Set event time into far-far future */ 193 /* Set event time into far-far future */
194 if (timer_is_v2()) 194 if (timer_is_v2())
195 __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, 195 __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
196 timer_base + MX3_TCMP); 196 timer_base + V2_TCMP);
197 else 197 else
198 __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, 198 __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
199 timer_base + MX1_2_TCMP); 199 timer_base + MX1_2_TCMP);
@@ -245,7 +245,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
245 uint32_t tstat; 245 uint32_t tstat;
246 246
247 if (timer_is_v2()) 247 if (timer_is_v2())
248 tstat = __raw_readl(timer_base + MX3_TSTAT); 248 tstat = __raw_readl(timer_base + V2_TSTAT);
249 else 249 else
250 tstat = __raw_readl(timer_base + MX1_2_TSTAT); 250 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
251 251
@@ -276,7 +276,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
276 unsigned int c = clk_get_rate(timer_clk); 276 unsigned int c = clk_get_rate(timer_clk);
277 277
278 if (timer_is_v2()) 278 if (timer_is_v2())
279 clockevent_mxc.set_next_event = mx3_set_next_event; 279 clockevent_mxc.set_next_event = v2_set_next_event;
280 280
281 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, 281 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
282 clockevent_mxc.shift); 282 clockevent_mxc.shift);
@@ -308,7 +308,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
308 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ 308 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
309 309
310 if (timer_is_v2()) 310 if (timer_is_v2())
311 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; 311 tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
312 else 312 else
313 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; 313 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
314 314
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index afa6709db0b3..9b86d2a60d43 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License 5 * License. You may obtain a copy of the GNU General Public License
@@ -19,6 +19,7 @@
19#include <asm/mach/irq.h> 19#include <asm/mach/irq.h>
20 20
21#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <mach/common.h>
22 23
23/* 24/*
24 ***************************************** 25 *****************************************
@@ -144,6 +145,7 @@ void __init tzic_init_irq(void __iomem *irqbase)
144 set_irq_handler(i, handle_level_irq); 145 set_irq_handler(i, handle_level_irq);
145 set_irq_flags(i, IRQF_VALID); 146 set_irq_flags(i, IRQF_VALID);
146 } 147 }
148 mxc_register_gpios();
147 149
148 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); 150 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
149} 151}
diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
index 2dd4cfe7ca17..b9dee28ee7d0 100644
--- a/drivers/mmc/core/sdio.c
+++ b/drivers/mmc/core/sdio.c
@@ -296,6 +296,12 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr,
296 card->type = MMC_TYPE_SDIO; 296 card->type = MMC_TYPE_SDIO;
297 297
298 /* 298 /*
299 * Call the optional HC's init_card function to handle quirks.
300 */
301 if (host->ops->init_card)
302 host->ops->init_card(host, card);
303
304 /*
299 * For native busses: set card RCA and quit open drain mode. 305 * For native busses: set card RCA and quit open drain mode.
300 */ 306 */
301 if (!powered_resume && !mmc_host_is_spi(host)) { 307 if (!powered_resume && !mmc_host_is_spi(host)) {
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index 2df90412abb5..ec18e3b60342 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -119,6 +119,7 @@ struct mxcmci_host {
119 int detect_irq; 119 int detect_irq;
120 int dma; 120 int dma;
121 int do_dma; 121 int do_dma;
122 int use_sdio;
122 unsigned int power_mode; 123 unsigned int power_mode;
123 struct imxmmc_platform_data *pdata; 124 struct imxmmc_platform_data *pdata;
124 125
@@ -138,6 +139,7 @@ struct mxcmci_host {
138 int clock; 139 int clock;
139 140
140 struct work_struct datawork; 141 struct work_struct datawork;
142 spinlock_t lock;
141}; 143};
142 144
143static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 145static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
@@ -151,6 +153,8 @@ static void mxcmci_softreset(struct mxcmci_host *host)
151{ 153{
152 int i; 154 int i;
153 155
156 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
157
154 /* reset sequence */ 158 /* reset sequence */
155 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK); 159 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
156 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, 160 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
@@ -224,6 +228,9 @@ static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
224static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, 228static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
225 unsigned int cmdat) 229 unsigned int cmdat)
226{ 230{
231 u32 int_cntr;
232 unsigned long flags;
233
227 WARN_ON(host->cmd != NULL); 234 WARN_ON(host->cmd != NULL);
228 host->cmd = cmd; 235 host->cmd = cmd;
229 236
@@ -247,12 +254,16 @@ static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
247 return -EINVAL; 254 return -EINVAL;
248 } 255 }
249 256
257 int_cntr = INT_END_CMD_RES_EN;
258
250 if (mxcmci_use_dma(host)) 259 if (mxcmci_use_dma(host))
251 writel(INT_READ_OP_EN | INT_WRITE_OP_DONE_EN | 260 int_cntr |= INT_READ_OP_EN | INT_WRITE_OP_DONE_EN;
252 INT_END_CMD_RES_EN, 261
253 host->base + MMC_REG_INT_CNTR); 262 spin_lock_irqsave(&host->lock, flags);
254 else 263 if (host->use_sdio)
255 writel(INT_END_CMD_RES_EN, host->base + MMC_REG_INT_CNTR); 264 int_cntr |= INT_SDIO_IRQ_EN;
265 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
266 spin_unlock_irqrestore(&host->lock, flags);
256 267
257 writew(cmd->opcode, host->base + MMC_REG_CMD); 268 writew(cmd->opcode, host->base + MMC_REG_CMD);
258 writel(cmd->arg, host->base + MMC_REG_ARG); 269 writel(cmd->arg, host->base + MMC_REG_ARG);
@@ -264,7 +275,14 @@ static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
264static void mxcmci_finish_request(struct mxcmci_host *host, 275static void mxcmci_finish_request(struct mxcmci_host *host,
265 struct mmc_request *req) 276 struct mmc_request *req)
266{ 277{
267 writel(0, host->base + MMC_REG_INT_CNTR); 278 u32 int_cntr = 0;
279 unsigned long flags;
280
281 spin_lock_irqsave(&host->lock, flags);
282 if (host->use_sdio)
283 int_cntr |= INT_SDIO_IRQ_EN;
284 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
285 spin_unlock_irqrestore(&host->lock, flags);
268 286
269 host->req = NULL; 287 host->req = NULL;
270 host->cmd = NULL; 288 host->cmd = NULL;
@@ -290,16 +308,25 @@ static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
290 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", 308 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
291 stat); 309 stat);
292 if (stat & STATUS_CRC_READ_ERR) { 310 if (stat & STATUS_CRC_READ_ERR) {
311 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
293 data->error = -EILSEQ; 312 data->error = -EILSEQ;
294 } else if (stat & STATUS_CRC_WRITE_ERR) { 313 } else if (stat & STATUS_CRC_WRITE_ERR) {
295 u32 err_code = (stat >> 9) & 0x3; 314 u32 err_code = (stat >> 9) & 0x3;
296 if (err_code == 2) /* No CRC response */ 315 if (err_code == 2) { /* No CRC response */
316 dev_err(mmc_dev(host->mmc),
317 "%s: No CRC -ETIMEDOUT\n", __func__);
297 data->error = -ETIMEDOUT; 318 data->error = -ETIMEDOUT;
298 else 319 } else {
320 dev_err(mmc_dev(host->mmc),
321 "%s: -EILSEQ\n", __func__);
299 data->error = -EILSEQ; 322 data->error = -EILSEQ;
323 }
300 } else if (stat & STATUS_TIME_OUT_READ) { 324 } else if (stat & STATUS_TIME_OUT_READ) {
325 dev_err(mmc_dev(host->mmc),
326 "%s: read -ETIMEDOUT\n", __func__);
301 data->error = -ETIMEDOUT; 327 data->error = -ETIMEDOUT;
302 } else { 328 } else {
329 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
303 data->error = -EIO; 330 data->error = -EIO;
304 } 331 }
305 } else { 332 } else {
@@ -433,8 +460,6 @@ static int mxcmci_transfer_data(struct mxcmci_host *host)
433 struct scatterlist *sg; 460 struct scatterlist *sg;
434 int stat, i; 461 int stat, i;
435 462
436 host->datasize = 0;
437
438 host->data = data; 463 host->data = data;
439 host->datasize = 0; 464 host->datasize = 0;
440 465
@@ -464,6 +489,9 @@ static void mxcmci_datawork(struct work_struct *work)
464 struct mxcmci_host *host = container_of(work, struct mxcmci_host, 489 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
465 datawork); 490 datawork);
466 int datastat = mxcmci_transfer_data(host); 491 int datastat = mxcmci_transfer_data(host);
492
493 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
494 host->base + MMC_REG_STATUS);
467 mxcmci_finish_data(host, datastat); 495 mxcmci_finish_data(host, datastat);
468 496
469 if (host->req->stop) { 497 if (host->req->stop) {
@@ -523,15 +551,35 @@ static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
523static irqreturn_t mxcmci_irq(int irq, void *devid) 551static irqreturn_t mxcmci_irq(int irq, void *devid)
524{ 552{
525 struct mxcmci_host *host = devid; 553 struct mxcmci_host *host = devid;
554 unsigned long flags;
555 bool sdio_irq;
526 u32 stat; 556 u32 stat;
527 557
528 stat = readl(host->base + MMC_REG_STATUS); 558 stat = readl(host->base + MMC_REG_STATUS);
529 writel(stat, host->base + MMC_REG_STATUS); 559 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
560 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS);
530 561
531 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 562 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
532 563
564 spin_lock_irqsave(&host->lock, flags);
565 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
566 spin_unlock_irqrestore(&host->lock, flags);
567
568#ifdef HAS_DMA
569 if (mxcmci_use_dma(host) &&
570 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
571 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
572 host->base + MMC_REG_STATUS);
573#endif
574
575 if (sdio_irq) {
576 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS);
577 mmc_signal_sdio_irq(host->mmc);
578 }
579
533 if (stat & STATUS_END_CMD_RESP) 580 if (stat & STATUS_END_CMD_RESP)
534 mxcmci_cmd_done(host, stat); 581 mxcmci_cmd_done(host, stat);
582
535#ifdef HAS_DMA 583#ifdef HAS_DMA
536 if (mxcmci_use_dma(host) && 584 if (mxcmci_use_dma(host) &&
537 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) 585 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
@@ -668,11 +716,46 @@ static int mxcmci_get_ro(struct mmc_host *mmc)
668 return -ENOSYS; 716 return -ENOSYS;
669} 717}
670 718
719static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
720{
721 struct mxcmci_host *host = mmc_priv(mmc);
722 unsigned long flags;
723 u32 int_cntr;
724
725 spin_lock_irqsave(&host->lock, flags);
726 host->use_sdio = enable;
727 int_cntr = readl(host->base + MMC_REG_INT_CNTR);
728
729 if (enable)
730 int_cntr |= INT_SDIO_IRQ_EN;
731 else
732 int_cntr &= ~INT_SDIO_IRQ_EN;
733
734 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
735 spin_unlock_irqrestore(&host->lock, flags);
736}
737
738static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
739{
740 /*
741 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
742 * multi-block transfers when connected SDIO peripheral doesn't
743 * drive the BUSY line as required by the specs.
744 * One way to prevent this is to only allow 1-bit transfers.
745 */
746
747 if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO)
748 host->caps &= ~MMC_CAP_4_BIT_DATA;
749 else
750 host->caps |= MMC_CAP_4_BIT_DATA;
751}
671 752
672static const struct mmc_host_ops mxcmci_ops = { 753static const struct mmc_host_ops mxcmci_ops = {
673 .request = mxcmci_request, 754 .request = mxcmci_request,
674 .set_ios = mxcmci_set_ios, 755 .set_ios = mxcmci_set_ios,
675 .get_ro = mxcmci_get_ro, 756 .get_ro = mxcmci_get_ro,
757 .enable_sdio_irq = mxcmci_enable_sdio_irq,
758 .init_card = mxcmci_init_card,
676}; 759};
677 760
678static int mxcmci_probe(struct platform_device *pdev) 761static int mxcmci_probe(struct platform_device *pdev)
@@ -700,7 +783,7 @@ static int mxcmci_probe(struct platform_device *pdev)
700 } 783 }
701 784
702 mmc->ops = &mxcmci_ops; 785 mmc->ops = &mxcmci_ops;
703 mmc->caps = MMC_CAP_4_BIT_DATA; 786 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
704 787
705 /* MMC core transfer sizes tunable parameters */ 788 /* MMC core transfer sizes tunable parameters */
706 mmc->max_hw_segs = 64; 789 mmc->max_hw_segs = 64;
@@ -719,6 +802,7 @@ static int mxcmci_probe(struct platform_device *pdev)
719 802
720 host->mmc = mmc; 803 host->mmc = mmc;
721 host->pdata = pdev->dev.platform_data; 804 host->pdata = pdev->dev.platform_data;
805 spin_lock_init(&host->lock);
722 806
723 if (host->pdata && host->pdata->ocr_avail) 807 if (host->pdata && host->pdata->ocr_avail)
724 mmc->ocr_avail = host->pdata->ocr_avail; 808 mmc->ocr_avail = host->pdata->ocr_avail;
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index b2900d8406d3..fb03aff8e83a 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -38,7 +38,7 @@
38#define DRIVER_NAME "mxc_nand" 38#define DRIVER_NAME "mxc_nand"
39 39
40#define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35()) 40#define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
41#define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27()) 41#define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
42 42
43/* Addresses for NFC registers */ 43/* Addresses for NFC registers */
44#define NFC_BUF_SIZE 0xE00 44#define NFC_BUF_SIZE 0xE00
@@ -168,11 +168,7 @@ static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
168{ 168{
169 struct mxc_nand_host *host = dev_id; 169 struct mxc_nand_host *host = dev_id;
170 170
171 uint16_t tmp; 171 disable_irq_nosync(irq);
172
173 tmp = readw(host->regs + NFC_CONFIG1);
174 tmp |= NFC_INT_MSK; /* Disable interrupt */
175 writew(tmp, host->regs + NFC_CONFIG1);
176 172
177 wake_up(&host->irq_waitq); 173 wake_up(&host->irq_waitq);
178 174
@@ -184,15 +180,13 @@ static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
184 */ 180 */
185static void wait_op_done(struct mxc_nand_host *host, int useirq) 181static void wait_op_done(struct mxc_nand_host *host, int useirq)
186{ 182{
187 uint32_t tmp; 183 uint16_t tmp;
188 int max_retries = 2000; 184 int max_retries = 8000;
189 185
190 if (useirq) { 186 if (useirq) {
191 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) { 187 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
192 188
193 tmp = readw(host->regs + NFC_CONFIG1); 189 enable_irq(host->irq);
194 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
195 writew(tmp, host->regs + NFC_CONFIG1);
196 190
197 wait_event(host->irq_waitq, 191 wait_event(host->irq_waitq,
198 readw(host->regs + NFC_CONFIG2) & NFC_INT); 192 readw(host->regs + NFC_CONFIG2) & NFC_INT);
@@ -226,8 +220,23 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
226 writew(cmd, host->regs + NFC_FLASH_CMD); 220 writew(cmd, host->regs + NFC_FLASH_CMD);
227 writew(NFC_CMD, host->regs + NFC_CONFIG2); 221 writew(NFC_CMD, host->regs + NFC_CONFIG2);
228 222
229 /* Wait for operation to complete */ 223 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
230 wait_op_done(host, useirq); 224 int max_retries = 100;
225 /* Reset completion is indicated by NFC_CONFIG2 */
226 /* being set to 0 */
227 while (max_retries-- > 0) {
228 if (readw(host->regs + NFC_CONFIG2) == 0) {
229 break;
230 }
231 udelay(1);
232 }
233 if (max_retries < 0)
234 DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
235 __func__);
236 } else {
237 /* Wait for operation to complete */
238 wait_op_done(host, useirq);
239 }
231} 240}
232 241
233/* This function sends an address (or partial address) to the 242/* This function sends an address (or partial address) to the
@@ -542,6 +551,41 @@ static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
542 } 551 }
543} 552}
544 553
554static void preset(struct mtd_info *mtd)
555{
556 struct nand_chip *nand_chip = mtd->priv;
557 struct mxc_nand_host *host = nand_chip->priv;
558 uint16_t tmp;
559
560 /* enable interrupt, disable spare enable */
561 tmp = readw(host->regs + NFC_CONFIG1);
562 tmp &= ~NFC_INT_MSK;
563 tmp &= ~NFC_SP_EN;
564 if (nand_chip->ecc.mode == NAND_ECC_HW) {
565 tmp |= NFC_ECC_EN;
566 } else {
567 tmp &= ~NFC_ECC_EN;
568 }
569 writew(tmp, host->regs + NFC_CONFIG1);
570 /* preset operation */
571
572 /* Unlock the internal RAM Buffer */
573 writew(0x2, host->regs + NFC_CONFIG);
574
575 /* Blocks to be unlocked */
576 if (nfc_is_v21()) {
577 writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
578 writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
579 } else if (nfc_is_v1()) {
580 writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
581 writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
582 } else
583 BUG();
584
585 /* Unlock Block Command for given address range */
586 writew(0x4, host->regs + NFC_WRPROT);
587}
588
545/* Used by the upper layer to write command to NAND Flash for 589/* Used by the upper layer to write command to NAND Flash for
546 * different operations to be carried out on NAND Flash */ 590 * different operations to be carried out on NAND Flash */
547static void mxc_nand_command(struct mtd_info *mtd, unsigned command, 591static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
@@ -559,6 +603,10 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
559 603
560 /* Command pre-processing step */ 604 /* Command pre-processing step */
561 switch (command) { 605 switch (command) {
606 case NAND_CMD_RESET:
607 send_cmd(host, command, false);
608 preset(mtd);
609 break;
562 610
563 case NAND_CMD_STATUS: 611 case NAND_CMD_STATUS:
564 host->buf_start = 0; 612 host->buf_start = 0;
@@ -679,7 +727,6 @@ static int __init mxcnd_probe(struct platform_device *pdev)
679 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data; 727 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
680 struct mxc_nand_host *host; 728 struct mxc_nand_host *host;
681 struct resource *res; 729 struct resource *res;
682 uint16_t tmp;
683 int err = 0, nr_parts = 0; 730 int err = 0, nr_parts = 0;
684 struct nand_ecclayout *oob_smallpage, *oob_largepage; 731 struct nand_ecclayout *oob_smallpage, *oob_largepage;
685 732
@@ -743,51 +790,17 @@ static int __init mxcnd_probe(struct platform_device *pdev)
743 host->spare_len = 64; 790 host->spare_len = 64;
744 oob_smallpage = &nandv2_hw_eccoob_smallpage; 791 oob_smallpage = &nandv2_hw_eccoob_smallpage;
745 oob_largepage = &nandv2_hw_eccoob_largepage; 792 oob_largepage = &nandv2_hw_eccoob_largepage;
793 this->ecc.bytes = 9;
746 } else if (nfc_is_v1()) { 794 } else if (nfc_is_v1()) {
747 host->regs = host->base; 795 host->regs = host->base;
748 host->spare0 = host->base + 0x800; 796 host->spare0 = host->base + 0x800;
749 host->spare_len = 16; 797 host->spare_len = 16;
750 oob_smallpage = &nandv1_hw_eccoob_smallpage; 798 oob_smallpage = &nandv1_hw_eccoob_smallpage;
751 oob_largepage = &nandv1_hw_eccoob_largepage; 799 oob_largepage = &nandv1_hw_eccoob_largepage;
752 } else
753 BUG();
754
755 /* disable interrupt and spare enable */
756 tmp = readw(host->regs + NFC_CONFIG1);
757 tmp |= NFC_INT_MSK;
758 tmp &= ~NFC_SP_EN;
759 writew(tmp, host->regs + NFC_CONFIG1);
760
761 init_waitqueue_head(&host->irq_waitq);
762
763 host->irq = platform_get_irq(pdev, 0);
764
765 err = request_irq(host->irq, mxc_nfc_irq, 0, DRIVER_NAME, host);
766 if (err)
767 goto eirq;
768
769 /* Reset NAND */
770 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
771
772 /* preset operation */
773 /* Unlock the internal RAM Buffer */
774 writew(0x2, host->regs + NFC_CONFIG);
775
776 /* Blocks to be unlocked */
777 if (nfc_is_v21()) {
778 writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
779 writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
780 this->ecc.bytes = 9;
781 } else if (nfc_is_v1()) {
782 writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
783 writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
784 this->ecc.bytes = 3; 800 this->ecc.bytes = 3;
785 } else 801 } else
786 BUG(); 802 BUG();
787 803
788 /* Unlock Block Command for given address range */
789 writew(0x4, host->regs + NFC_WRPROT);
790
791 this->ecc.size = 512; 804 this->ecc.size = 512;
792 this->ecc.layout = oob_smallpage; 805 this->ecc.layout = oob_smallpage;
793 806
@@ -796,14 +809,8 @@ static int __init mxcnd_probe(struct platform_device *pdev)
796 this->ecc.hwctl = mxc_nand_enable_hwecc; 809 this->ecc.hwctl = mxc_nand_enable_hwecc;
797 this->ecc.correct = mxc_nand_correct_data; 810 this->ecc.correct = mxc_nand_correct_data;
798 this->ecc.mode = NAND_ECC_HW; 811 this->ecc.mode = NAND_ECC_HW;
799 tmp = readw(host->regs + NFC_CONFIG1);
800 tmp |= NFC_ECC_EN;
801 writew(tmp, host->regs + NFC_CONFIG1);
802 } else { 812 } else {
803 this->ecc.mode = NAND_ECC_SOFT; 813 this->ecc.mode = NAND_ECC_SOFT;
804 tmp = readw(host->regs + NFC_CONFIG1);
805 tmp &= ~NFC_ECC_EN;
806 writew(tmp, host->regs + NFC_CONFIG1);
807 } 814 }
808 815
809 /* NAND bus width determines access funtions used by upper layer */ 816 /* NAND bus width determines access funtions used by upper layer */
@@ -817,6 +824,14 @@ static int __init mxcnd_probe(struct platform_device *pdev)
817 this->options |= NAND_USE_FLASH_BBT; 824 this->options |= NAND_USE_FLASH_BBT;
818 } 825 }
819 826
827 init_waitqueue_head(&host->irq_waitq);
828
829 host->irq = platform_get_irq(pdev, 0);
830
831 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
832 if (err)
833 goto eirq;
834
820 /* first scan to find the device and get the page size */ 835 /* first scan to find the device and get the page size */
821 if (nand_scan_ident(mtd, 1)) { 836 if (nand_scan_ident(mtd, 1)) {
822 err = -ENXIO; 837 err = -ENXIO;
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index ead59f42e69b..544ccfd7056e 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -199,8 +199,8 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
199 writel(pdata->portsc, hcd->regs + PORTSC_OFFSET); 199 writel(pdata->portsc, hcd->regs + PORTSC_OFFSET);
200 mdelay(10); 200 mdelay(10);
201 201
202 /* setup USBCONTROL. */ 202 /* setup specific usb hw */
203 ret = mxc_set_usbcontrol(pdev->id, pdata->flags); 203 ret = mxc_initialize_usb_hw(pdev->id, pdata->flags);
204 if (ret < 0) 204 if (ret < 0)
205 goto err_init; 205 goto err_init;
206 206
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 43eaf5ca5848..3196c84cc630 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -108,6 +108,9 @@ struct mmc_host_ops {
108 int (*get_cd)(struct mmc_host *host); 108 int (*get_cd)(struct mmc_host *host);
109 109
110 void (*enable_sdio_irq)(struct mmc_host *host, int enable); 110 void (*enable_sdio_irq)(struct mmc_host *host, int enable);
111
112 /* optional callback for HC quirks */
113 void (*init_card)(struct mmc_host *host, struct mmc_card *card);
111}; 114};
112 115
113struct mmc_card; 116struct mmc_card;
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-15 21:15:35 -0500