658 files changed, 15409 insertions, 4816 deletions
diff --git a/.gitignore b/.gitignore
index 8faa6c02b39e..5d56a3fd0de6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -28,6 +28,7 @@ modules.builtin
 *.gz
 *.bz2
 *.lzma
+*.xz
 *.lzo
 *.patch
 *.gcno
diff --git a/Documentation/networking/00-INDEX b/Documentation/networking/00-INDEX
index fe5c099b8fc8..4edd78dfb362 100644
--- a/Documentation/networking/00-INDEX
+++ b/Documentation/networking/00-INDEX
@@ -40,8 +40,6 @@ decnet.txt
        - info on using the DECnet networking layer in Linux.
 depca.txt
        - the Digital DEPCA/EtherWORKS DE1?? and DE2?? LANCE Ethernet driver
-dgrs.txt
-        - the Digi International RightSwitch SE-X Ethernet driver
 dmfe.txt
        - info on the Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver.
 e100.txt
@@ -50,8 +48,6 @@ e1000.txt
        - info on Intel's E1000 line of gigabit ethernet boards
 eql.txt
        - serial IP load balancing
-ethertap.txt
-        - the Ethertap user space packet reception and transmission driver
 ewrk3.txt
        - the Digital EtherWORKS 3 DE203/4/5 Ethernet driver
 filter.txt
@@ -104,8 +100,6 @@ tuntap.txt
        - TUN/TAP device driver, allowing user space Rx/Tx of packets.
 vortex.txt
        - info on using 3Com Vortex (3c590, 3c592, 3c595, 3c597) Ethernet cards.
-wavelan.txt
-        - AT&T GIS (nee NCR) WaveLAN card: An Ethernet-like radio transceiver
 x25.txt
        - general info on X.25 development.
 x25-iface.txt
diff --git a/Documentation/networking/dns_resolver.txt b/Documentation/networking/dns_resolver.txt
index aefd1e681804..04ca06325b08 100644
--- a/Documentation/networking/dns_resolver.txt
+++ b/Documentation/networking/dns_resolver.txt
@@ -61,7 +61,6 @@ before the more general line given above as the first match is the one taken.
        create  dns_resolver    foo:*   *       /usr/sbin/dns.foo %k
 =====
 USAGE
 =====
@@ -104,6 +103,14 @@ implemented in the module can be called after doing:
     returned also.
+===============================
+READING DNS KEYS FROM USERSPACE
+===============================
+Keys of dns_resolver type can be read from userspace using keyctl_read() or
+"keyctl read/print/pipe".
 =========
 MECHANISM
 =========
diff --git a/MAINTAINERS b/MAINTAINERS
index f8f76b0f350f..b64776c4aeea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1010,6 +1010,15 @@ L:	linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
 S:      Maintained
 F:      arch/arm/mach-s5p*/
+ARM/SAMSUNG MOBILE MACHINE SUPPORT
+M:      Kyungmin Park <kyungmin.park@samsung.com>
+L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:      Maintained
+F:      arch/arm/mach-s5pv210/mach-aquila.c
+F:      arch/arm/mach-s5pv210/mach-goni.c
+F:      arch/arm/mach-exynos4/mach-universal_c210.c
+F:      arch/arm/mach-exynos4/mach-nuri.c
 ARM/SAMSUNG S5P SERIES FIMC SUPPORT
 M:      Kyungmin Park <kyungmin.park@samsung.com>
 M:      Sylwester Nawrocki <s.nawrocki@samsung.com>
@@ -1467,6 +1476,7 @@ F:	include/net/bluetooth/
 BONDING DRIVER
 M:      Jay Vosburgh <fubar@us.ibm.com>
+M:      Andy Gospodarek <andy@greyhouse.net>
 L:      netdev@vger.kernel.org
 W:      http://sourceforge.net/projects/bonding/
 S:      Supported
@@ -1692,6 +1702,13 @@ M:	Andy Whitcroft <apw@canonical.com>
 S:      Supported
 F:      scripts/checkpatch.pl
+CHINESE DOCUMENTATION
+M:      Harry Wei <harryxiyou@gmail.com>
+L:      xiyoulinuxkernelgroup@googlegroups.com
+L:      linux-kernel@zh-kernel.org (moderated for non-subscribers)
+S:      Maintained
+F:      Documentation/zh_CN/
 CISCO VIC ETHERNET NIC DRIVER
 M:      Vasanthy Kolluri <vkolluri@cisco.com>
 M:      Roopa Prabhu <roprabhu@cisco.com>
@@ -2026,7 +2043,7 @@ F:	Documentation/scsi/dc395x.txt
 F:      drivers/scsi/dc395x.*
 DCCP PROTOCOL
-M:      Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
+M:      Gerrit Renker <gerrit@erg.abdn.ac.uk>
 L:      dccp@vger.kernel.org
 W:      http://www.linuxfoundation.org/collaborate/workgroups/networking/dccp
 S:      Maintained
@@ -3512,7 +3529,7 @@ F:	drivers/hwmon/jc42.c
 F:      Documentation/hwmon/jc42
 JFS FILESYSTEM
-M:      Dave Kleikamp <shaggy@linux.vnet.ibm.com>
+M:      Dave Kleikamp <shaggy@kernel.org>
 L:      jfs-discussion@lists.sourceforge.net
 W:      http://jfs.sourceforge.net/
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/shaggy/jfs-2.6.git
@@ -5164,6 +5181,7 @@ F:	drivers/char/random.c
 RAPIDIO SUBSYSTEM
 M:      Matt Porter <mporter@kernel.crashing.org>
+M:      Alexandre Bounine <alexandre.bounine@idt.com>
 S:      Maintained
 F:      drivers/rapidio/
@@ -5266,7 +5284,7 @@ S:	Maintained
 F:      drivers/net/wireless/rtl818x/rtl8180/
 RTL8187 WIRELESS DRIVER
-M:      Herton Ronaldo Krzesinski <herton@mandriva.com.br>
+M:      Herton Ronaldo Krzesinski <herton@canonical.com>
 M:      Hin-Tak Leung <htl10@users.sourceforge.net>
 M:      Larry Finger <Larry.Finger@lwfinger.net>
 L:      linux-wireless@vger.kernel.org
@@ -6105,7 +6123,7 @@ S:	Maintained
 F:      security/tomoyo/
 TOPSTAR LAPTOP EXTRAS DRIVER
-M:      Herton Ronaldo Krzesinski <herton@mandriva.com.br>
+M:      Herton Ronaldo Krzesinski <herton@canonical.com>
 L:      platform-driver-x86@vger.kernel.org
 S:      Maintained
 F:      drivers/platform/x86/topstar-laptop.c
diff --git a/Makefile b/Makefile
index 26d7d824db51..504f788773e5 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 38
-EXTRAVERSION = -rc6
+EXTRAVERSION = -rc8
 NAME = Flesh-Eating Bats with Fangs
 # *DOCUMENTATION*
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 47f63d480141..cc31bec2e316 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -11,6 +11,7 @@ config ALPHA
        select HAVE_GENERIC_HARDIRQS
        select GENERIC_IRQ_PROBE
        select AUTO_IRQ_AFFINITY if SMP
+        select GENERIC_HARDIRQS_NO_DEPRECATED
        help
          The Alpha is a 64-bit general-purpose processor designed and
          marketed by the Digital Equipment Corporation of blessed memory,
diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c
index 9ab234f48dd8..a19d60082299 100644
--- a/arch/alpha/kernel/irq.c
+++ b/arch/alpha/kernel/irq.c
@@ -44,11 +44,16 @@ static char irq_user_affinity[NR_IRQS];
 int irq_select_affinity(unsigned int irq)
 {
-        struct irq_desc *desc = irq_to_desc[irq];
+        struct irq_data *data = irq_get_irq_data(irq);
+        struct irq_chip *chip;
        static int last_cpu;
        int cpu = last_cpu + 1;
-        if (!desc || !get_irq_desc_chip(desc)->set_affinity || irq_user_affinity[irq])
+        if (!data)
+                return 1;
+        chip = irq_data_get_irq_chip(data);
+        if (!chip->irq_set_affinity || irq_user_affinity[irq])
                return 1;
        while (!cpu_possible(cpu) ||
@@ -56,8 +61,8 @@ int irq_select_affinity(unsigned int irq)
                cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);
        last_cpu = cpu;
-        cpumask_copy(desc->affinity, cpumask_of(cpu));
+        cpumask_copy(data->affinity, cpumask_of(cpu));
-        get_irq_desc_chip(desc)->set_affinity(irq, cpumask_of(cpu));
+        chip->irq_set_affinity(data, cpumask_of(cpu), false);
        return 0;
 }
 #endif /* CONFIG_SMP */
diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c
index 2d0679b60939..411ca11d0a18 100644
--- a/arch/alpha/kernel/irq_alpha.c
+++ b/arch/alpha/kernel/irq_alpha.c
@@ -228,14 +228,9 @@ struct irqaction timer_irqaction = {
 void __init
 init_rtc_irq(void)
 {
-        struct irq_desc *desc = irq_to_desc(RTC_IRQ);
+        set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
+                                      handle_simple_irq, "RTC");
-        if (desc) {
+        setup_irq(RTC_IRQ, &timer_irqaction);
-                desc->status |= IRQ_DISABLED;
-                set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
-                        handle_simple_irq, "RTC");
-                setup_irq(RTC_IRQ, &timer_irqaction);
-        }
 }
 /* Dummy irqactions.  */
diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c
index 956ea0ed1694..c7cc9813e45f 100644
--- a/arch/alpha/kernel/irq_i8259.c
+++ b/arch/alpha/kernel/irq_i8259.c
@@ -33,10 +33,10 @@ i8259_update_irq_hw(unsigned int irq, unsigned long mask)
 }
 inline void
-i8259a_enable_irq(unsigned int irq)
+i8259a_enable_irq(struct irq_data *d)
 {
        spin_lock(&i8259_irq_lock);
-        i8259_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
+        i8259_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
        spin_unlock(&i8259_irq_lock);
 }
@@ -47,16 +47,18 @@ __i8259a_disable_irq(unsigned int irq)
 }
 void
-i8259a_disable_irq(unsigned int irq)
+i8259a_disable_irq(struct irq_data *d)
 {
        spin_lock(&i8259_irq_lock);
-        __i8259a_disable_irq(irq);
+        __i8259a_disable_irq(d->irq);
        spin_unlock(&i8259_irq_lock);
 }
 void
-i8259a_mask_and_ack_irq(unsigned int irq)
+i8259a_mask_and_ack_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
        spin_lock(&i8259_irq_lock);
        __i8259a_disable_irq(irq);
@@ -71,9 +73,9 @@ i8259a_mask_and_ack_irq(unsigned int irq)
 struct irq_chip i8259a_irq_type = {
        .name           = "XT-PIC",
-        .unmask         = i8259a_enable_irq,
+        .irq_unmask     = i8259a_enable_irq,
-        .mask           = i8259a_disable_irq,
+        .irq_mask       = i8259a_disable_irq,
-        .mask_ack       = i8259a_mask_and_ack_irq,
+        .irq_mask_ack   = i8259a_mask_and_ack_irq,
 };
 void __init
diff --git a/arch/alpha/kernel/irq_impl.h b/arch/alpha/kernel/irq_impl.h
index b63ccd7386f1..d507a234b05d 100644
--- a/arch/alpha/kernel/irq_impl.h
+++ b/arch/alpha/kernel/irq_impl.h
@@ -31,11 +31,9 @@ extern void init_rtc_irq(void);
 extern void common_init_isa_dma(void);
-extern void i8259a_enable_irq(unsigned int);
+extern void i8259a_enable_irq(struct irq_data *d);
-extern void i8259a_disable_irq(unsigned int);
+extern void i8259a_disable_irq(struct irq_data *d);
-extern void i8259a_mask_and_ack_irq(unsigned int);
+extern void i8259a_mask_and_ack_irq(struct irq_data *d);
-extern unsigned int i8259a_startup_irq(unsigned int);
-extern void i8259a_end_irq(unsigned int);
 extern struct irq_chip i8259a_irq_type;
 extern void init_i8259a_irqs(void);
diff --git a/arch/alpha/kernel/irq_pyxis.c b/arch/alpha/kernel/irq_pyxis.c
index 2863458c853e..b30227fa7f5f 100644
--- a/arch/alpha/kernel/irq_pyxis.c
+++ b/arch/alpha/kernel/irq_pyxis.c
@@ -29,21 +29,21 @@ pyxis_update_irq_hw(unsigned long mask)
 }
 static inline void
-pyxis_enable_irq(unsigned int irq)
+pyxis_enable_irq(struct irq_data *d)
 {
-        pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
+        pyxis_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
 }
 static void
-pyxis_disable_irq(unsigned int irq)
+pyxis_disable_irq(struct irq_data *d)
 {
-        pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
+        pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
 }
 static void
-pyxis_mask_and_ack_irq(unsigned int irq)
+pyxis_mask_and_ack_irq(struct irq_data *d)
 {
-        unsigned long bit = 1UL << (irq - 16);
+        unsigned long bit = 1UL << (d->irq - 16);
        unsigned long mask = cached_irq_mask &= ~bit;
        /* Disable the interrupt.  */
@@ -58,9 +58,9 @@ pyxis_mask_and_ack_irq(unsigned int irq)
 static struct irq_chip pyxis_irq_type = {
        .name           = "PYXIS",
-        .mask_ack       = pyxis_mask_and_ack_irq,
+        .irq_mask_ack   = pyxis_mask_and_ack_irq,
-        .mask           = pyxis_disable_irq,
+        .irq_mask       = pyxis_disable_irq,
-        .unmask         = pyxis_enable_irq,
+        .irq_unmask     = pyxis_enable_irq,
 };
 void 
@@ -103,7 +103,7 @@ init_pyxis_irqs(unsigned long ignore_mask)
                if ((ignore_mask >> i) & 1)
                        continue;
                set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
-                irq_to_desc(i)->status |= IRQ_LEVEL;
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
        setup_irq(16+7, &isa_cascade_irqaction);
diff --git a/arch/alpha/kernel/irq_srm.c b/arch/alpha/kernel/irq_srm.c
index 0e57e828b413..82a47bba41c4 100644
--- a/arch/alpha/kernel/irq_srm.c
+++ b/arch/alpha/kernel/irq_srm.c
@@ -18,27 +18,27 @@
 DEFINE_SPINLOCK(srm_irq_lock);
 static inline void
-srm_enable_irq(unsigned int irq)
+srm_enable_irq(struct irq_data *d)
 {
        spin_lock(&srm_irq_lock);
-        cserve_ena(irq - 16);
+        cserve_ena(d->irq - 16);
        spin_unlock(&srm_irq_lock);
 }
 static void
-srm_disable_irq(unsigned int irq)
+srm_disable_irq(struct irq_data *d)
 {
        spin_lock(&srm_irq_lock);
-        cserve_dis(irq - 16);
+        cserve_dis(d->irq - 16);
        spin_unlock(&srm_irq_lock);
 }
 /* Handle interrupts from the SRM, assuming no additional weirdness.  */
 static struct irq_chip srm_irq_type = {
        .name           = "SRM",
-        .unmask         = srm_enable_irq,
+        .irq_unmask     = srm_enable_irq,
-        .mask           = srm_disable_irq,
+        .irq_mask       = srm_disable_irq,
-        .mask_ack       = srm_disable_irq,
+        .irq_mask_ack   = srm_disable_irq,
 };
 void __init
@@ -52,7 +52,7 @@ init_srm_irqs(long max, unsigned long ignore_mask)
                if (i < 64 && ((ignore_mask >> i) & 1))
                        continue;
                set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq);
-                irq_to_desc(i)->status |= IRQ_LEVEL;
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
 }
diff --git a/arch/alpha/kernel/sys_alcor.c b/arch/alpha/kernel/sys_alcor.c
index 7bef61768236..88d95e872f55 100644
--- a/arch/alpha/kernel/sys_alcor.c
+++ b/arch/alpha/kernel/sys_alcor.c
@@ -44,31 +44,31 @@ alcor_update_irq_hw(unsigned long mask)
 }
 static inline void
-alcor_enable_irq(unsigned int irq)
+alcor_enable_irq(struct irq_data *d)
 {
-        alcor_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
+        alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
 }
 static void
-alcor_disable_irq(unsigned int irq)
+alcor_disable_irq(struct irq_data *d)
 {
-        alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
+        alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
 }
 static void
-alcor_mask_and_ack_irq(unsigned int irq)
+alcor_mask_and_ack_irq(struct irq_data *d)
 {
-        alcor_disable_irq(irq);
+        alcor_disable_irq(d);
        /* On ALCOR/XLT, need to dismiss interrupt via GRU. */
-        *(vuip)GRU_INT_CLEAR = 1 << (irq - 16); mb();
+        *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb();
        *(vuip)GRU_INT_CLEAR = 0; mb();
 }
 static void
-alcor_isa_mask_and_ack_irq(unsigned int irq)
+alcor_isa_mask_and_ack_irq(struct irq_data *d)
 {
-        i8259a_mask_and_ack_irq(irq);
+        i8259a_mask_and_ack_irq(d);
        /* On ALCOR/XLT, need to dismiss interrupt via GRU. */
        *(vuip)GRU_INT_CLEAR = 0x80000000; mb();
@@ -77,9 +77,9 @@ alcor_isa_mask_and_ack_irq(unsigned int irq)
 static struct irq_chip alcor_irq_type = {
        .name           = "ALCOR",
-        .unmask         = alcor_enable_irq,
+        .irq_unmask     = alcor_enable_irq,
-        .mask           = alcor_disable_irq,
+        .irq_mask       = alcor_disable_irq,
-        .mask_ack       = alcor_mask_and_ack_irq,
+        .irq_mask_ack   = alcor_mask_and_ack_irq,
 };
 static void
@@ -126,9 +126,9 @@ alcor_init_irq(void)
                if (i >= 16+20 && i <= 16+30)
                        continue;
                set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
-                irq_to_desc(i)->status |= IRQ_LEVEL;
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
-        i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq;
+        i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq;
        init_i8259a_irqs();
        common_init_isa_dma();
diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c
index b0c916493aea..57eb6307bc27 100644
--- a/arch/alpha/kernel/sys_cabriolet.c
+++ b/arch/alpha/kernel/sys_cabriolet.c
@@ -46,22 +46,22 @@ cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
 }
 static inline void
-cabriolet_enable_irq(unsigned int irq)
+cabriolet_enable_irq(struct irq_data *d)
 {
-        cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
+        cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq));
 }
 static void
-cabriolet_disable_irq(unsigned int irq)
+cabriolet_disable_irq(struct irq_data *d)
 {
-        cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
+        cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq);
 }
 static struct irq_chip cabriolet_irq_type = {
        .name           = "CABRIOLET",
-        .unmask         = cabriolet_enable_irq,
+        .irq_unmask     = cabriolet_enable_irq,
-        .mask           = cabriolet_disable_irq,
+        .irq_mask       = cabriolet_disable_irq,
-        .mask_ack       = cabriolet_disable_irq,
+        .irq_mask_ack   = cabriolet_disable_irq,
 };
 static void 
@@ -107,7 +107,7 @@ common_init_irq(void (*srm_dev_int)(unsigned long v))
                for (i = 16; i < 35; ++i) {
                        set_irq_chip_and_handler(i, &cabriolet_irq_type,
                                handle_level_irq);
-                        irq_to_desc(i)->status |= IRQ_LEVEL;
+                        irq_set_status_flags(i, IRQ_LEVEL);
                }
        }
diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c
index edad5f759ccd..481df4ecb651 100644
--- a/arch/alpha/kernel/sys_dp264.c
+++ b/arch/alpha/kernel/sys_dp264.c
@@ -98,37 +98,37 @@ tsunami_update_irq_hw(unsigned long mask)
 }
 static void
-dp264_enable_irq(unsigned int irq)
+dp264_enable_irq(struct irq_data *d)
 {
        spin_lock(&dp264_irq_lock);
-        cached_irq_mask |= 1UL << irq;
+        cached_irq_mask |= 1UL << d->irq;
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
 }
 static void
-dp264_disable_irq(unsigned int irq)
+dp264_disable_irq(struct irq_data *d)
 {
        spin_lock(&dp264_irq_lock);
-        cached_irq_mask &= ~(1UL << irq);
+        cached_irq_mask &= ~(1UL << d->irq);
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
 }
 static void
-clipper_enable_irq(unsigned int irq)
+clipper_enable_irq(struct irq_data *d)
 {
        spin_lock(&dp264_irq_lock);
-        cached_irq_mask |= 1UL << (irq - 16);
+        cached_irq_mask |= 1UL << (d->irq - 16);
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
 }
 static void
-clipper_disable_irq(unsigned int irq)
+clipper_disable_irq(struct irq_data *d)
 {
        spin_lock(&dp264_irq_lock);
-        cached_irq_mask &= ~(1UL << (irq - 16));
+        cached_irq_mask &= ~(1UL << (d->irq - 16));
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
 }
@@ -149,10 +149,11 @@ cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
 }
 static int
-dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
+dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
-{ 
+                   bool force)
+{
        spin_lock(&dp264_irq_lock);
-        cpu_set_irq_affinity(irq, *affinity);
+        cpu_set_irq_affinity(d->irq, *affinity);
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
@@ -160,10 +161,11 @@ dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
 }
 static int
-clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
+clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
-{ 
+                     bool force)
+{
        spin_lock(&dp264_irq_lock);
-        cpu_set_irq_affinity(irq - 16, *affinity);
+        cpu_set_irq_affinity(d->irq - 16, *affinity);
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
@@ -171,19 +173,19 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
 }
 static struct irq_chip dp264_irq_type = {
-        .name           = "DP264",
+        .name                   = "DP264",
-        .unmask         = dp264_enable_irq,
+        .irq_unmask             = dp264_enable_irq,
-        .mask           = dp264_disable_irq,
+        .irq_mask               = dp264_disable_irq,
-        .mask_ack       = dp264_disable_irq,
+        .irq_mask_ack           = dp264_disable_irq,
-        .set_affinity   = dp264_set_affinity,
+        .irq_set_affinity       = dp264_set_affinity,
 };
 static struct irq_chip clipper_irq_type = {
-        .name           = "CLIPPER",
+        .name                   = "CLIPPER",
-        .unmask         = clipper_enable_irq,
+        .irq_unmask             = clipper_enable_irq,
-        .mask           = clipper_disable_irq,
+        .irq_mask               = clipper_disable_irq,
-        .mask_ack       = clipper_disable_irq,
+        .irq_mask_ack           = clipper_disable_irq,
-        .set_affinity   = clipper_set_affinity,
+        .irq_set_affinity       = clipper_set_affinity,
 };
 static void
@@ -268,8 +270,8 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
 {
        long i;
        for (i = imin; i <= imax; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, ops, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
 }
diff --git a/arch/alpha/kernel/sys_eb64p.c b/arch/alpha/kernel/sys_eb64p.c
index ae5f29d127b0..402e908ffb3e 100644
--- a/arch/alpha/kernel/sys_eb64p.c
+++ b/arch/alpha/kernel/sys_eb64p.c
@@ -44,22 +44,22 @@ eb64p_update_irq_hw(unsigned int irq, unsigned long mask)
 }
 static inline void
-eb64p_enable_irq(unsigned int irq)
+eb64p_enable_irq(struct irq_data *d)
 {
-        eb64p_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
+        eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
 }
 static void
-eb64p_disable_irq(unsigned int irq)
+eb64p_disable_irq(struct irq_data *d)
 {
-        eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
+        eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq);
 }
 static struct irq_chip eb64p_irq_type = {
        .name           = "EB64P",
-        .unmask         = eb64p_enable_irq,
+        .irq_unmask     = eb64p_enable_irq,
-        .mask           = eb64p_disable_irq,
+        .irq_mask       = eb64p_disable_irq,
-        .mask_ack       = eb64p_disable_irq,
+        .irq_mask_ack   = eb64p_disable_irq,
 };
 static void 
@@ -118,9 +118,9 @@ eb64p_init_irq(void)
        init_i8259a_irqs();
        for (i = 16; i < 32; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
-        }               
+                irq_set_status_flags(i, IRQ_LEVEL);
+        }
        common_init_isa_dma();
        setup_irq(16+5, &isa_cascade_irqaction);
diff --git a/arch/alpha/kernel/sys_eiger.c b/arch/alpha/kernel/sys_eiger.c
index 1121bc5c6c6c..0b44a54c1522 100644
--- a/arch/alpha/kernel/sys_eiger.c
+++ b/arch/alpha/kernel/sys_eiger.c
@@ -51,16 +51,18 @@ eiger_update_irq_hw(unsigned long irq, unsigned long mask)
 }
 static inline void
-eiger_enable_irq(unsigned int irq)
+eiger_enable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
        unsigned long mask;
        mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
        eiger_update_irq_hw(irq, mask);
 }
 static void
-eiger_disable_irq(unsigned int irq)
+eiger_disable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
        unsigned long mask;
        mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
        eiger_update_irq_hw(irq, mask);
@@ -68,9 +70,9 @@ eiger_disable_irq(unsigned int irq)
 static struct irq_chip eiger_irq_type = {
        .name           = "EIGER",
-        .unmask         = eiger_enable_irq,
+        .irq_unmask     = eiger_enable_irq,
-        .mask           = eiger_disable_irq,
+        .irq_mask       = eiger_disable_irq,
-        .mask_ack       = eiger_disable_irq,
+        .irq_mask_ack   = eiger_disable_irq,
 };
 static void
@@ -136,8 +138,8 @@ eiger_init_irq(void)
        init_i8259a_irqs();
        for (i = 16; i < 128; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
 }
diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c
index 34f55e03d331..00341b75c8b2 100644
--- a/arch/alpha/kernel/sys_jensen.c
+++ b/arch/alpha/kernel/sys_jensen.c
@@ -63,34 +63,34 @@
 */
 static void
-jensen_local_enable(unsigned int irq)
+jensen_local_enable(struct irq_data *d)
 {
        /* the parport is really hw IRQ 1, silly Jensen.  */
-        if (irq == 7)
+        if (d->irq == 7)
-                i8259a_enable_irq(1);
+                i8259a_enable_irq(d);
 }
 static void
-jensen_local_disable(unsigned int irq)
+jensen_local_disable(struct irq_data *d)
 {
        /* the parport is really hw IRQ 1, silly Jensen.  */
-        if (irq == 7)
+        if (d->irq == 7)
-                i8259a_disable_irq(1);
+                i8259a_disable_irq(d);
 }
 static void
-jensen_local_mask_ack(unsigned int irq)
+jensen_local_mask_ack(struct irq_data *d)
 {
        /* the parport is really hw IRQ 1, silly Jensen.  */
-        if (irq == 7)
+        if (d->irq == 7)
-                i8259a_mask_and_ack_irq(1);
+                i8259a_mask_and_ack_irq(d);
 }
 static struct irq_chip jensen_local_irq_type = {
        .name           = "LOCAL",
-        .unmask         = jensen_local_enable,
+        .irq_unmask     = jensen_local_enable,
-        .mask           = jensen_local_disable,
+        .irq_mask       = jensen_local_disable,
-        .mask_ack       = jensen_local_mask_ack,
+        .irq_mask_ack   = jensen_local_mask_ack,
 };
 static void 
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index 2bfc9f1b1ddc..e61910734e41 100644
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -104,9 +104,10 @@ io7_get_irq_ctl(unsigned int irq, struct io7 **pio7)
 }
 static void
-io7_enable_irq(unsigned int irq)
+io7_enable_irq(struct irq_data *d)
 {
        volatile unsigned long *ctl;
+        unsigned int irq = d->irq;
        struct io7 *io7;
        ctl = io7_get_irq_ctl(irq, &io7);
@@ -115,7 +116,7 @@ io7_enable_irq(unsigned int irq)
                       __func__, irq);
                return;
        }
-                
        spin_lock(&io7->irq_lock);
        *ctl |= 1UL << 24;
        mb();
@@ -124,9 +125,10 @@ io7_enable_irq(unsigned int irq)
 }
 static void
-io7_disable_irq(unsigned int irq)
+io7_disable_irq(struct irq_data *d)
 {
        volatile unsigned long *ctl;
+        unsigned int irq = d->irq;
        struct io7 *io7;
        ctl = io7_get_irq_ctl(irq, &io7);
@@ -135,7 +137,7 @@ io7_disable_irq(unsigned int irq)
                       __func__, irq);
                return;
        }
-                
        spin_lock(&io7->irq_lock);
        *ctl &= ~(1UL << 24);
        mb();
@@ -144,35 +146,29 @@ io7_disable_irq(unsigned int irq)
 }
 static void
-marvel_irq_noop(unsigned int irq) 
+marvel_irq_noop(struct irq_data *d)
-{ 
+{
-        return; 
+        return;
-}
-static unsigned int
-marvel_irq_noop_return(unsigned int irq) 
-{ 
-        return 0; 
 }
 static struct irq_chip marvel_legacy_irq_type = {
        .name           = "LEGACY",
-        .mask           = marvel_irq_noop,
+        .irq_mask       = marvel_irq_noop,
-        .unmask         = marvel_irq_noop,
+        .irq_unmask     = marvel_irq_noop,
 };
 static struct irq_chip io7_lsi_irq_type = {
        .name           = "LSI",
-        .unmask         = io7_enable_irq,
+        .irq_unmask     = io7_enable_irq,
-        .mask           = io7_disable_irq,
+        .irq_mask       = io7_disable_irq,
-        .mask_ack       = io7_disable_irq,
+        .irq_mask_ack   = io7_disable_irq,
 };
 static struct irq_chip io7_msi_irq_type = {
        .name           = "MSI",
-        .unmask         = io7_enable_irq,
+        .irq_unmask     = io7_enable_irq,
-        .mask           = io7_disable_irq,
+        .irq_mask       = io7_disable_irq,
-        .ack            = marvel_irq_noop,
+        .irq_ack        = marvel_irq_noop,
 };
 static void
@@ -280,8 +276,8 @@ init_io7_irqs(struct io7 *io7,
        /* Set up the lsi irqs.  */
        for (i = 0; i < 128; ++i) {
-                irq_to_desc(base + i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
        /* Disable the implemented irqs in hardware.  */
@@ -294,8 +290,8 @@ init_io7_irqs(struct io7 *io7,
        /* Set up the msi irqs.  */
        for (i = 128; i < (128 + 512); ++i) {
-                irq_to_desc(base + i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
        for (i = 0; i < 16; ++i)
diff --git a/arch/alpha/kernel/sys_mikasa.c b/arch/alpha/kernel/sys_mikasa.c
index bcc1639e8efb..cf7f43dd3147 100644
--- a/arch/alpha/kernel/sys_mikasa.c
+++ b/arch/alpha/kernel/sys_mikasa.c
@@ -43,22 +43,22 @@ mikasa_update_irq_hw(int mask)
 }
 static inline void
-mikasa_enable_irq(unsigned int irq)
+mikasa_enable_irq(struct irq_data *d)
 {
-        mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16));
+        mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16));
 }
 static void
-mikasa_disable_irq(unsigned int irq)
+mikasa_disable_irq(struct irq_data *d)
 {
-        mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
+        mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16)));
 }
 static struct irq_chip mikasa_irq_type = {
        .name           = "MIKASA",
-        .unmask         = mikasa_enable_irq,
+        .irq_unmask     = mikasa_enable_irq,
-        .mask           = mikasa_disable_irq,
+        .irq_mask       = mikasa_disable_irq,
-        .mask_ack       = mikasa_disable_irq,
+        .irq_mask_ack   = mikasa_disable_irq,
 };
 static void 
@@ -98,8 +98,8 @@ mikasa_init_irq(void)
        mikasa_update_irq_hw(0);
        for (i = 16; i < 32; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
        init_i8259a_irqs();
diff --git a/arch/alpha/kernel/sys_noritake.c b/arch/alpha/kernel/sys_noritake.c
index e88f4ae1260e..92bc188e94a9 100644
--- a/arch/alpha/kernel/sys_noritake.c
+++ b/arch/alpha/kernel/sys_noritake.c
@@ -48,22 +48,22 @@ noritake_update_irq_hw(int irq, int mask)
 }
 static void
-noritake_enable_irq(unsigned int irq)
+noritake_enable_irq(struct irq_data *d)
 {
-        noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16));
+        noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16));
 }
 static void
-noritake_disable_irq(unsigned int irq)
+noritake_disable_irq(struct irq_data *d)
 {
-        noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
+        noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16)));
 }
 static struct irq_chip noritake_irq_type = {
        .name           = "NORITAKE",
-        .unmask         = noritake_enable_irq,
+        .irq_unmask     = noritake_enable_irq,
-        .mask           = noritake_disable_irq,
+        .irq_mask       = noritake_disable_irq,
-        .mask_ack       = noritake_disable_irq,
+        .irq_mask_ack   = noritake_disable_irq,
 };
 static void 
@@ -127,8 +127,8 @@ noritake_init_irq(void)
        outw(0, 0x54c);
        for (i = 16; i < 48; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
        init_i8259a_irqs();
diff --git a/arch/alpha/kernel/sys_rawhide.c b/arch/alpha/kernel/sys_rawhide.c
index 6a51364dd1cc..936d4140ed5f 100644
--- a/arch/alpha/kernel/sys_rawhide.c
+++ b/arch/alpha/kernel/sys_rawhide.c
@@ -56,9 +56,10 @@ rawhide_update_irq_hw(int hose, int mask)
  (((h) < MCPCIA_MAX_HOSES) && (cached_irq_masks[(h)] != 0))
 static inline void 
-rawhide_enable_irq(unsigned int irq)
+rawhide_enable_irq(struct irq_data *d)
 {
        unsigned int mask, hose;
+        unsigned int irq = d->irq;
        irq -= 16;
        hose = irq / 24;
@@ -76,9 +77,10 @@ rawhide_enable_irq(unsigned int irq)
 }
 static void 
-rawhide_disable_irq(unsigned int irq)
+rawhide_disable_irq(struct irq_data *d)
 {
        unsigned int mask, hose;
+        unsigned int irq = d->irq;
        irq -= 16;
        hose = irq / 24;
@@ -96,9 +98,10 @@ rawhide_disable_irq(unsigned int irq)
 }
 static void
-rawhide_mask_and_ack_irq(unsigned int irq)
+rawhide_mask_and_ack_irq(struct irq_data *d)
 {
        unsigned int mask, mask1, hose;
+        unsigned int irq = d->irq;
        irq -= 16;
        hose = irq / 24;
@@ -123,9 +126,9 @@ rawhide_mask_and_ack_irq(unsigned int irq)
 static struct irq_chip rawhide_irq_type = {
        .name           = "RAWHIDE",
-        .unmask         = rawhide_enable_irq,
+        .irq_unmask     = rawhide_enable_irq,
-        .mask           = rawhide_disable_irq,
+        .irq_mask       = rawhide_disable_irq,
-        .mask_ack       = rawhide_mask_and_ack_irq,
+        .irq_mask_ack   = rawhide_mask_and_ack_irq,
 };
 static void 
@@ -177,8 +180,8 @@ rawhide_init_irq(void)
        }
        for (i = 16; i < 128; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
        init_i8259a_irqs();
diff --git a/arch/alpha/kernel/sys_rx164.c b/arch/alpha/kernel/sys_rx164.c
index 89e7e37ec84c..cea22a62913b 100644
--- a/arch/alpha/kernel/sys_rx164.c
+++ b/arch/alpha/kernel/sys_rx164.c
@@ -47,22 +47,22 @@ rx164_update_irq_hw(unsigned long mask)
 }
 static inline void
-rx164_enable_irq(unsigned int irq)
+rx164_enable_irq(struct irq_data *d)
 {
-        rx164_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
+        rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
 }
 static void
-rx164_disable_irq(unsigned int irq)
+rx164_disable_irq(struct irq_data *d)
 {
-        rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
+        rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
 }
 static struct irq_chip rx164_irq_type = {
        .name           = "RX164",
-        .unmask         = rx164_enable_irq,
+        .irq_unmask     = rx164_enable_irq,
-        .mask           = rx164_disable_irq,
+        .irq_mask       = rx164_disable_irq,
-        .mask_ack       = rx164_disable_irq,
+        .irq_mask_ack   = rx164_disable_irq,
 };
 static void 
@@ -99,8 +99,8 @@ rx164_init_irq(void)
        rx164_update_irq_hw(0);
        for (i = 16; i < 40; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
        init_i8259a_irqs();
diff --git a/arch/alpha/kernel/sys_sable.c b/arch/alpha/kernel/sys_sable.c
index 5c4423d1b06c..a349538aabc9 100644
--- a/arch/alpha/kernel/sys_sable.c
+++ b/arch/alpha/kernel/sys_sable.c
@@ -443,11 +443,11 @@ lynx_swizzle(struct pci_dev *dev, u8 *pinp)
 /* GENERIC irq routines */
 static inline void
-sable_lynx_enable_irq(unsigned int irq)
+sable_lynx_enable_irq(struct irq_data *d)
 {
        unsigned long bit, mask;
-        bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
+        bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
        spin_lock(&sable_lynx_irq_lock);
        mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
        sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@@ -459,11 +459,11 @@ sable_lynx_enable_irq(unsigned int irq)
 }
 static void
-sable_lynx_disable_irq(unsigned int irq)
+sable_lynx_disable_irq(struct irq_data *d)
 {
        unsigned long bit, mask;
-        bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
+        bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
        spin_lock(&sable_lynx_irq_lock);
        mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
        sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@@ -475,11 +475,11 @@ sable_lynx_disable_irq(unsigned int irq)
 }
 static void
-sable_lynx_mask_and_ack_irq(unsigned int irq)
+sable_lynx_mask_and_ack_irq(struct irq_data *d)
 {
        unsigned long bit, mask;
-        bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
+        bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
        spin_lock(&sable_lynx_irq_lock);
        mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
        sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@@ -489,9 +489,9 @@ sable_lynx_mask_and_ack_irq(unsigned int irq)
 static struct irq_chip sable_lynx_irq_type = {
        .name           = "SABLE/LYNX",
-        .unmask         = sable_lynx_enable_irq,
+        .irq_unmask     = sable_lynx_enable_irq,
-        .mask           = sable_lynx_disable_irq,
+        .irq_mask       = sable_lynx_disable_irq,
-        .mask_ack       = sable_lynx_mask_and_ack_irq,
+        .irq_mask_ack   = sable_lynx_mask_and_ack_irq,
 };
 static void 
@@ -518,9 +518,9 @@ sable_lynx_init_irq(int nr_of_irqs)
        long i;
        for (i = 0; i < nr_of_irqs; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &sable_lynx_irq_type,
                        handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
        common_init_isa_dma();
diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c
index f8a1e8a862fb..42a5331f13c4 100644
--- a/arch/alpha/kernel/sys_takara.c
+++ b/arch/alpha/kernel/sys_takara.c
@@ -45,16 +45,18 @@ takara_update_irq_hw(unsigned long irq, unsigned long mask)
 }
 static inline void
-takara_enable_irq(unsigned int irq)
+takara_enable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
        unsigned long mask;
        mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
        takara_update_irq_hw(irq, mask);
 }
 static void
-takara_disable_irq(unsigned int irq)
+takara_disable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
        unsigned long mask;
        mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
        takara_update_irq_hw(irq, mask);
@@ -62,9 +64,9 @@ takara_disable_irq(unsigned int irq)
 static struct irq_chip takara_irq_type = {
        .name           = "TAKARA",
-        .unmask         = takara_enable_irq,
+        .irq_unmask     = takara_enable_irq,
-        .mask           = takara_disable_irq,
+        .irq_mask       = takara_disable_irq,
-        .mask_ack       = takara_disable_irq,
+        .irq_mask_ack   = takara_disable_irq,
 };
 static void
@@ -136,8 +138,8 @@ takara_init_irq(void)
                takara_update_irq_hw(i, -1);
        for (i = 16; i < 128; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
        common_init_isa_dma();
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index e02494bf5ef3..f6c108a3d673 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -112,8 +112,9 @@ titan_update_irq_hw(unsigned long mask)
 }
 static inline void
-titan_enable_irq(unsigned int irq)
+titan_enable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
        spin_lock(&titan_irq_lock);
        titan_cached_irq_mask |= 1UL << (irq - 16);
        titan_update_irq_hw(titan_cached_irq_mask);
@@ -121,8 +122,9 @@ titan_enable_irq(unsigned int irq)
 }
 static inline void
-titan_disable_irq(unsigned int irq)
+titan_disable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
        spin_lock(&titan_irq_lock);
        titan_cached_irq_mask &= ~(1UL << (irq - 16));
        titan_update_irq_hw(titan_cached_irq_mask);
@@ -144,7 +146,8 @@ titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
 }
 static int
-titan_set_irq_affinity(unsigned int irq, const struct cpumask *affinity)
+titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
+                       bool force)
 { 
        spin_lock(&titan_irq_lock);
        titan_cpu_set_irq_affinity(irq - 16, *affinity);
@@ -175,17 +178,17 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax)
 {
        long i;
        for (i = imin; i <= imax; ++i) {
-                irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, ops, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
        }
 }
 static struct irq_chip titan_irq_type = {
-       .name            = "TITAN",
+       .name                    = "TITAN",
-       .unmask          = titan_enable_irq,
+       .irq_unmask              = titan_enable_irq,
-       .mask            = titan_disable_irq,
+       .irq_mask                = titan_disable_irq,
-       .mask_ack        = titan_disable_irq,
+       .irq_mask_ack            = titan_disable_irq,
-       .set_affinity    = titan_set_irq_affinity,
+       .irq_set_affinity        = titan_set_irq_affinity,
 };
 static irqreturn_t
diff --git a/arch/alpha/kernel/sys_wildfire.c b/arch/alpha/kernel/sys_wildfire.c
index eec52594d410..ca60a387ef0a 100644
--- a/arch/alpha/kernel/sys_wildfire.c
+++ b/arch/alpha/kernel/sys_wildfire.c
@@ -104,10 +104,12 @@ wildfire_init_irq_hw(void)
 }
 static void
-wildfire_enable_irq(unsigned int irq)
+wildfire_enable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
        if (irq < 16)
-                i8259a_enable_irq(irq);
+                i8259a_enable_irq(d);
        spin_lock(&wildfire_irq_lock);
        set_bit(irq, &cached_irq_mask);
@@ -116,10 +118,12 @@ wildfire_enable_irq(unsigned int irq)
 }
 static void
-wildfire_disable_irq(unsigned int irq)
+wildfire_disable_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
        if (irq < 16)
-                i8259a_disable_irq(irq);
+                i8259a_disable_irq(d);
        spin_lock(&wildfire_irq_lock);
        clear_bit(irq, &cached_irq_mask);
@@ -128,10 +132,12 @@ wildfire_disable_irq(unsigned int irq)
 }
 static void
-wildfire_mask_and_ack_irq(unsigned int irq)
+wildfire_mask_and_ack_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
        if (irq < 16)
-                i8259a_mask_and_ack_irq(irq);
+                i8259a_mask_and_ack_irq(d);
        spin_lock(&wildfire_irq_lock);
        clear_bit(irq, &cached_irq_mask);
@@ -141,9 +147,9 @@ wildfire_mask_and_ack_irq(unsigned int irq)
 static struct irq_chip wildfire_irq_type = {
        .name           = "WILDFIRE",
-        .unmask         = wildfire_enable_irq,
+        .irq_unmask     = wildfire_enable_irq,
-        .mask           = wildfire_disable_irq,
+        .irq_mask       = wildfire_disable_irq,
-        .mask_ack       = wildfire_mask_and_ack_irq,
+        .irq_mask_ack   = wildfire_mask_and_ack_irq,
 };
 static void __init
@@ -177,21 +183,21 @@ wildfire_init_irq_per_pca(int qbbno, int pcano)
        for (i = 0; i < 16; ++i) {
                if (i == 2)
                        continue;
-                irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
                        handle_level_irq);
+                irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
        }
-        irq_to_desc(36+irq_bias)->status |= IRQ_LEVEL;
        set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type,
                handle_level_irq);
+        irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
        for (i = 40; i < 64; ++i) {
-                irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
                        handle_level_irq);
+                irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
        }
-        setup_irq(32+irq_bias, &isa_enable);    
+        setup_irq(32+irq_bias, &isa_enable);
 }
 static void __init
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 778655f0257a..ea5ee4d067f3 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -6,6 +6,8 @@ config ARM_VIC
 config ARM_VIC_NR
        int
+        default 4 if ARCH_S5PV210
+        default 3 if ARCH_S5P6442 || ARCH_S5PC100
        default 2
        depends on ARM_VIC
        help
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 2f7042813765..aeb3af541fed 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -24,6 +24,7 @@ CONFIG_MACH_OPENRD_ULTIMATE=y
 CONFIG_MACH_NETSPACE_V2=y
 CONFIG_MACH_INETSPACE_V2=y
 CONFIG_MACH_NETSPACE_MAX_V2=y
+CONFIG_MACH_D2NET_V2=y
 CONFIG_MACH_NET2BIG_V2=y
 CONFIG_MACH_NET5BIG_V2=y
 CONFIG_MACH_T5325=y
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index 9cba68cfa51a..e3c903281f70 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -110,7 +110,7 @@ CONFIG_MMC=y
 CONFIG_MMC_BLOCK=m
 CONFIG_MMC_SDHCI=m
 CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_CLASS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index c0094d8edae4..c2b9b4bdec00 100644
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -50,6 +50,9 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
        }
 }
+/* Function pointer to optional machine-specific reinitialization */
+extern void (*kexec_reinit)(void);
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_KEXEC */
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 3a0893a76a3b..bf13b814c1b8 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -15,10 +15,6 @@ struct meminfo;
 struct sys_timer;
 struct machine_desc {
-        /*
-         * Note! The first two elements are used
-         * by assembler code in head.S, head-common.S
-         */
        unsigned int            nr;             /* architecture number  */
        const char              *name;          /* architecture name    */
        unsigned long           boot_params;    /* tagged list          */
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h
index 9763be04f77e..22de005f159c 100644
--- a/arch/arm/include/asm/pgalloc.h
+++ b/arch/arm/include/asm/pgalloc.h
@@ -10,6 +10,8 @@
 #ifndef _ASMARM_PGALLOC_H
 #define _ASMARM_PGALLOC_H
+#include <linux/pagemap.h>
 #include <asm/domain.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/processor.h>
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 8ccea012722c..7544ce6b481a 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -12,11 +12,25 @@
 #ifndef __ARM_PMU_H__
 #define __ARM_PMU_H__
+#include <linux/interrupt.h>
 enum arm_pmu_type {
        ARM_PMU_DEVICE_CPU      = 0,
        ARM_NUM_PMU_DEVICES,
 };
+/*
+ * struct arm_pmu_platdata - ARM PMU platform data
+ *
+ * @handle_irq: an optional handler which will be called from the interrupt and
+ * passed the address of the low level handler, and can be used to implement
+ * any platform specific handling before or after calling it.
+ */
+struct arm_pmu_platdata {
+        irqreturn_t (*handle_irq)(int irq, void *dev,
+                                  irq_handler_t pmu_handler);
+};
 #ifdef CONFIG_CPU_HAS_PMU
 /**
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index d600bd350704..44b84fe6e1b0 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -836,9 +836,11 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
 /*
 * One-time initialisation.
 */
-static void reset_ctrl_regs(void *unused)
+static void reset_ctrl_regs(void *info)
 {
-        int i;
+        int i, cpu = smp_processor_id();
+        u32 dbg_power;
+        cpumask_t *cpumask = info;
        /*
         * v7 debug contains save and restore registers so that debug state
@@ -850,6 +852,17 @@ static void reset_ctrl_regs(void *unused)
         */
        if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
                /*
+                 * Ensure sticky power-down is clear (i.e. debug logic is
+                 * powered up).
+                 */
+                asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));
+                if ((dbg_power & 0x1) == 0) {
+                        pr_warning("CPU %d debug is powered down!\n", cpu);
+                        cpumask_or(cpumask, cpumask, cpumask_of(cpu));
+                        return;
+                }
+                /*
                 * Unconditionally clear the lock by writing a value
                 * other than 0xC5ACCE55 to the access register.
                 */
@@ -887,6 +900,7 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = {
 static int __init arch_hw_breakpoint_init(void)
 {
        u32 dscr;
+        cpumask_t cpumask = { CPU_BITS_NONE };
        debug_arch = get_debug_arch();
@@ -911,7 +925,13 @@ static int __init arch_hw_breakpoint_init(void)
         * Reset the breakpoint resources. We assume that a halting
         * debugger will leave the world in a nice state for us.
         */
-        on_each_cpu(reset_ctrl_regs, NULL, 1);
+        on_each_cpu(reset_ctrl_regs, &cpumask, 1);
+        if (!cpumask_empty(&cpumask)) {
+                core_num_brps = 0;
+                core_num_reserved_brps = 0;
+                core_num_wrps = 0;
+                return 0;
+        }
        ARM_DBG_READ(c1, 0, dscr);
        if (dscr & ARM_DSCR_HDBGEN) {
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 30ead135ff5f..e59bbd496c39 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -75,6 +75,11 @@ void machine_crash_shutdown(struct pt_regs *regs)
        printk(KERN_INFO "Loading crashdump kernel...\n");
 }
+/*
+ * Function pointer to optional machine-specific reinitialization
+ */
+void (*kexec_reinit)(void);
 void machine_kexec(struct kimage *image)
 {
        unsigned long page_list;
@@ -104,6 +109,8 @@ void machine_kexec(struct kimage *image)
                           (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
        printk(KERN_INFO "Bye!\n");
+        if (kexec_reinit)
+                kexec_reinit();
        local_irq_disable();
        local_fiq_disable();
        setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index d150ad1ccb5d..22e194eb8536 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -377,9 +377,18 @@ validate_group(struct perf_event *event)
        return 0;
 }
+static irqreturn_t armpmu_platform_irq(int irq, void *dev)
+{
+        struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev);
+        return plat->handle_irq(irq, dev, armpmu->handle_irq);
+}
 static int
 armpmu_reserve_hardware(void)
 {
+        struct arm_pmu_platdata *plat;
+        irq_handler_t handle_irq;
        int i, err = -ENODEV, irq;
        pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
@@ -390,6 +399,12 @@ armpmu_reserve_hardware(void)
        init_pmu(ARM_PMU_DEVICE_CPU);
+        plat = dev_get_platdata(&pmu_device->dev);
+        if (plat && plat->handle_irq)
+                handle_irq = armpmu_platform_irq;
+        else
+                handle_irq = armpmu->handle_irq;
        if (pmu_device->num_resources < 1) {
                pr_err("no irqs for PMUs defined\n");
                return -ENODEV;
@@ -400,7 +415,7 @@ armpmu_reserve_hardware(void)
                if (irq < 0)
                        continue;
-                err = request_irq(irq, armpmu->handle_irq,
+                err = request_irq(irq, handle_irq,
                                  IRQF_DISABLED | IRQF_NOBALANCING,
                                  "armpmu", NULL);
                if (err) {
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 19c6816db61e..b13e70f63d71 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -996,10 +996,10 @@ static int ptrace_gethbpregs(struct task_struct *tsk, long num,
                while (!(arch_ctrl.len & 0x1))
                        arch_ctrl.len >>= 1;
-                if (idx & 0x1)
+                if (num & 0x1)
-                        reg = encode_ctrl_reg(arch_ctrl);
-                else
                        reg = bp->attr.bp_addr;
+                else
+                        reg = encode_ctrl_reg(arch_ctrl);
        }
 put:
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
index 343de73161fa..4a68c2b1ec11 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -132,7 +132,7 @@ out:
        return ret;
 }
-static int __init davinci_cpu_init(struct cpufreq_policy *policy)
+static int davinci_cpu_init(struct cpufreq_policy *policy)
 {
        int result = 0;
        struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index ec7e84b21143..625d4b66718b 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -491,8 +491,15 @@ static struct platform_device da850_mcasp_device = {
        .resource       = da850_mcasp_resources,
 };
+struct platform_device davinci_pcm_device = {
+        .name   = "davinci-pcm-audio",
+        .id     = -1,
+};
 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 {
+        platform_device_register(&davinci_pcm_device);
        /* DA830/OMAP-L137 has 3 instances of McASP */
        if (cpu_is_davinci_da830() && id == 1) {
                da830_mcasp1_device.dev.platform_data = pdata;
diff --git a/arch/arm/mach-davinci/gpio-tnetv107x.c b/arch/arm/mach-davinci/gpio-tnetv107x.c
index d10298620e2c..3fa3e2867e19 100644
--- a/arch/arm/mach-davinci/gpio-tnetv107x.c
+++ b/arch/arm/mach-davinci/gpio-tnetv107x.c
@@ -58,7 +58,7 @@ static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
        spin_lock_irqsave(&ctlr->lock, flags);
-        gpio_reg_set_bit(&regs->enable, gpio);
+        gpio_reg_set_bit(regs->enable, gpio);
        spin_unlock_irqrestore(&ctlr->lock, flags);
@@ -74,7 +74,7 @@ static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
        spin_lock_irqsave(&ctlr->lock, flags);
-        gpio_reg_clear_bit(&regs->enable, gpio);
+        gpio_reg_clear_bit(regs->enable, gpio);
        spin_unlock_irqrestore(&ctlr->lock, flags);
 }
@@ -88,7 +88,7 @@ static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
        spin_lock_irqsave(&ctlr->lock, flags);
-        gpio_reg_set_bit(&regs->direction, gpio);
+        gpio_reg_set_bit(regs->direction, gpio);
        spin_unlock_irqrestore(&ctlr->lock, flags);
@@ -106,11 +106,11 @@ static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
        spin_lock_irqsave(&ctlr->lock, flags);
        if (value)
-                gpio_reg_set_bit(&regs->data_out, gpio);
+                gpio_reg_set_bit(regs->data_out, gpio);
        else
-                gpio_reg_clear_bit(&regs->data_out, gpio);
+                gpio_reg_clear_bit(regs->data_out, gpio);
-        gpio_reg_clear_bit(&regs->direction, gpio);
+        gpio_reg_clear_bit(regs->direction, gpio);
        spin_unlock_irqrestore(&ctlr->lock, flags);
@@ -124,7 +124,7 @@ static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
        unsigned gpio = chip->base + offset;
        int ret;
-        ret = gpio_reg_get_bit(&regs->data_in, gpio);
+        ret = gpio_reg_get_bit(regs->data_in, gpio);
        return ret ? 1 : 0;
 }
@@ -140,9 +140,9 @@ static void tnetv107x_gpio_set(struct gpio_chip *chip,
        spin_lock_irqsave(&ctlr->lock, flags);
        if (value)
-                gpio_reg_set_bit(&regs->data_out, gpio);
+                gpio_reg_set_bit(regs->data_out, gpio);
        else
-                gpio_reg_clear_bit(&regs->data_out, gpio);
+                gpio_reg_clear_bit(regs->data_out, gpio);
        spin_unlock_irqrestore(&ctlr->lock, flags);
 }
diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h
index 730c49d1ebd8..14a504887189 100644
--- a/arch/arm/mach-davinci/include/mach/clkdev.h
+++ b/arch/arm/mach-davinci/include/mach/clkdev.h
@@ -1,6 +1,8 @@
 #ifndef __MACH_CLKDEV_H
 #define __MACH_CLKDEV_H
+struct clk;
 static inline int __clk_get(struct clk *clk)
 {
        return 1;
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 96e0e94e5fa9..03e11f9dca97 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -90,6 +90,7 @@ MACHINE_START(CM_A510, "Compulab CM-A510 Board")
        .boot_params    = 0x00000100,
        .init_machine   = cm_a510_init,
        .map_io         = dove_map_io,
+        .init_early     = dove_init_early,
        .init_irq       = dove_init_irq,
        .timer          = &dove_timer,
 MACHINE_END
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index fe627aba6da7..e06a88f1f81d 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -532,6 +532,11 @@ void __init dove_i2c_init(void)
 /*****************************************************************************
 * Time handling
 ****************************************************************************/
+void __init dove_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
 static int get_tclk(void)
 {
        /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
@@ -540,7 +545,8 @@ static int get_tclk(void)
 static void dove_timer_init(void)
 {
-        orion_time_init(IRQ_DOVE_BRIDGE, get_tclk());
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_DOVE_BRIDGE, get_tclk());
 }
 struct sys_timer dove_timer = {
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index a51517c3fe76..6a2046e44706 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -22,6 +22,7 @@ extern struct mbus_dram_target_info dove_mbus_dram_info;
 */
 void dove_map_io(void);
 void dove_init(void);
+void dove_init_early(void);
 void dove_init_irq(void);
 void dove_setup_cpu_mbus(void);
 void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index 95925aa76dd9..2ac34ecfa745 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -97,6 +97,7 @@ MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
        .boot_params    = 0x00000100,
        .init_machine   = dove_db_init,
        .map_io         = dove_map_io,
+        .init_early     = dove_init_early,
        .init_irq       = dove_init_irq,
        .timer          = &dove_timer,
 MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index 214a4c31f069..226949dc4ac0 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -26,10 +26,6 @@
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
 #define  SOFT_RESET             0x00000001
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define  BRIDGE_INT_TIMER0      0x0002
-#define  BRIDGE_INT_TIMER1      0x0004
 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index 27b414578f2e..e5fcdd3f5bf5 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -130,7 +130,8 @@
 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
 #define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
 #define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
-#define DOVE_GPIO_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
 #define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
 #define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
 #define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
index 340bb7af529d..e7e5101e35a5 100644
--- a/arch/arm/mach-dove/include/mach/gpio.h
+++ b/arch/arm/mach-dove/include/mach/gpio.h
@@ -6,46 +6,4 @@
 * warranty of any kind, whether express or implied.
 */
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-#include <asm/errno.h>
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-#define GPIO_MAX        72
-#define GPIO_BASE_LO            (DOVE_GPIO_VIRT_BASE + 0x00)
-#define GPIO_BASE_HI            (DOVE_GPIO_VIRT_BASE + 0x20)
-#define GPIO_BASE(pin)          ((pin < 32) ? GPIO_BASE_LO :            \
-                                 ((pin < 64) ? GPIO_BASE_HI :           \
-                                  DOVE_GPIO2_VIRT_BASE))
-#define GPIO_OUT(pin)           (GPIO_BASE(pin) + 0x00)
-#define GPIO_IO_CONF(pin)       (GPIO_BASE(pin) + 0x04)
-#define GPIO_BLINK_EN(pin)      (GPIO_BASE(pin) + 0x08)
-#define GPIO_IN_POL(pin)        (GPIO_BASE(pin) + 0x0c)
-#define GPIO_DATA_IN(pin)       (GPIO_BASE(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin)    (GPIO_BASE(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)     (GPIO_BASE(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin)    (GPIO_BASE(pin) + 0x1c)
-static inline int gpio_to_irq(int pin)
-{
-        if (pin < NR_GPIO_IRQS)
-                return pin + IRQ_DOVE_GPIO_START;
-        return -EINVAL;
-}
-static inline int irq_to_gpio(int irq)
-{
-        if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)
-                return irq - IRQ_DOVE_GPIO_START;
-        return -EINVAL;
-}
-#endif
diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h
index 46681466f92b..03d401d20453 100644
--- a/arch/arm/mach-dove/include/mach/irqs.h
+++ b/arch/arm/mach-dove/include/mach/irqs.h
@@ -92,10 +92,5 @@
 #define NR_IRQS                 (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
-/* Required for compatability with PXA AC97 driver.     */
-#define IRQ_AC97                IRQ_DOVE_AC97
-/* Required for compatability with PXA DMA driver.      */
-#define IRQ_DMA                 IRQ_DOVE_PDMA
-/* Required for compatability with PXA NAND driver      */
-#define IRQ_NAND                IRQ_DOVE_NAND
 #endif
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 9317f0558b57..101707fa2e2c 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -99,11 +99,21 @@ void __init dove_init_irq(void)
        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
        /*
-         * Mask and clear GPIO IRQ interrupts.
+         * Initialize gpiolib for GPIOs 0-71.
         */
-        writel(0, GPIO_LEVEL_MASK(0));
+        orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
-        writel(0, GPIO_EDGE_MASK(0));
+                        IRQ_DOVE_GPIO_START);
-        writel(0, GPIO_EDGE_CAUSE(0));
+        set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
+        orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
+                        IRQ_DOVE_GPIO_START + 32);
+        set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
+        orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
+                        IRQ_DOVE_GPIO_START + 64);
        /*
         * Mask and clear PMU interrupts
@@ -111,18 +121,6 @@ void __init dove_init_irq(void)
        writel(0, PMU_INTERRUPT_MASK);
        writel(0, PMU_INTERRUPT_CAUSE);
-        for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
-        set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
        for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
                set_irq_chip(i, &pmu_irq_chip);
                set_irq_handler(i, handle_level_irq);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 56684b517070..5eec099e0c72 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -100,6 +100,7 @@ config MACH_MX25_3DS
        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
        select IMX_HAVE_PLATFORM_IMX2_WDT
        select IMX_HAVE_PLATFORM_IMXDI_RTC
+        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_FB
        select IMX_HAVE_PLATFORM_IMX_KEYPAD
        select IMX_HAVE_PLATFORM_IMX_UART
@@ -238,6 +239,7 @@ config MACH_MX27_3DS
        select SOC_IMX27
        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_KEYPAD
        select IMX_HAVE_PLATFORM_IMX_UART
        select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -265,6 +267,7 @@ config MACH_IMX27LITE
        bool "LogicPD MX27 LITEKIT platform"
        select SOC_IMX27
        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX_SSI
        help
          Include support for MX27 LITEKIT platform. This includes specific
          configurations for the board and its peripherals.
@@ -300,4 +303,13 @@ config MACH_MXT_TD60
          Include support for i-MXT (aka td60) platform. This
          includes specific configurations for the module and its peripherals.
+config MACH_IMX27IPCAM
+        bool "IMX27 IPCAM platform"
+        select SOC_IMX27
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for IMX27 IPCAM platform. This includes specific
+          configurations for the board and its peripherals.
 endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 77100bf26153..b85794d27991 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -9,10 +9,10 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
 obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
-obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o
+obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
 obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
-obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
+obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -36,3 +36,4 @@ obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
 obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
+obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
index 3938a563b280..dcc41728fe72 100644
--- a/arch/arm/mach-imx/clock-imx1.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -592,6 +592,7 @@ static struct clk_lookup lookups[] __initdata = {
        _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
        _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
+        _REGISTER_CLOCK("imx1-cspi.1", NULL, spi_clk)
        _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
        _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c
index daa0165b6772..a65838fc061c 100644
--- a/arch/arm/mach-imx/clock-imx25.c
+++ b/arch/arm/mach-imx/clock-imx25.c
@@ -228,6 +228,7 @@ DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0,  3, get_rate_esdhc1,	 NULL,
 DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2,  NULL, NULL);
 DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0,  4, get_rate_esdhc2,  NULL,
                &esdhc2_ahb_clk);
+DEFINE_CLOCK(sdma_ahb_clk, 0, CCM_CGCR0, 26, NULL,       NULL, NULL);
 DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,        NULL, NULL);
 DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,       NULL, NULL);
 DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,       NULL, &lcdc_ahb_clk);
@@ -253,6 +254,7 @@ DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
 DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
 DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
 DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
+DEFINE_CLOCK(sdma_clk, 0, CCM_CGCR2,  6, get_rate_ipg, NULL, &sdma_ahb_clk);
 DEFINE_CLOCK(esdhc1_clk,  0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
                &esdhc1_per_clk);
 DEFINE_CLOCK(esdhc2_clk,  1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
@@ -304,6 +306,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
        _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
        _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
+        _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
 };
 int __init mx25_clocks_init(void)
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index 81979486218e..da593657ff3f 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -9,6 +9,10 @@
 #include <mach/mx1.h>
 #include <mach/devices-common.h>
+extern const struct imx_imx_fb_data imx1_imx_fb_data __initconst;
+#define imx1_add_imx_fb(pdata) \
+    imx_add_imx_fb(&imx1_imx_fb_data, pdata)
 extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
 #define imx1_add_imx_i2c(pdata)         \
        imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
@@ -18,3 +22,10 @@ extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
        imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
 #define imx1_add_imx_uart0(pdata)       imx1_add_imx_uart(0, pdata)
 #define imx1_add_imx_uart1(pdata)       imx1_add_imx_uart(1, pdata)
+extern const struct imx_spi_imx_data imx1_cspi_data[] __initconst;
+#define imx1_add_cspi(id, pdata)   \
+        imx_add_spi_imx(&imx1_cspi_data[id], pdata)
+#define imx1_add_spi_imx0(pdata) imx1_add_cspi(0, pdata)
+#define imx1_add_spi_imx1(pdata) imx1_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index bde33caf1b90..b591d72f6037 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -81,7 +81,11 @@ imx25_sdhci_esdhc_imx_data[] __initconst;
 extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
 #define imx25_add_spi_imx(id, pdata)    \
-        imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
+        imx_add_spi_imx(&imx25_cspi_data[id], pdata)
 #define imx25_add_spi_imx0(pdata)       imx25_add_spi_imx(0, pdata)
 #define imx25_add_spi_imx1(pdata)       imx25_add_spi_imx(1, pdata)
 #define imx25_add_spi_imx2(pdata)       imx25_add_spi_imx(2, pdata)
+extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst;
+#define imx25_add_mxc_pwm(id)   \
+        imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index e9f1769b49f5..236f1495efad 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -699,7 +699,7 @@ int imx_dma_request(int channel, const char *name)
                local_irq_restore(flags);
                return -EBUSY;
        }
-        memset(imxdma, 0, sizeof(imxdma));
+        memset(imxdma, 0, sizeof(*imxdma));
        imxdma->name = name;
        local_irq_restore(flags); /* request_irq() can block */
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
new file mode 100644
index 000000000000..865daf0b09e9
--- /dev/null
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+#define USBCTRL_OTGBASE_OFFSET  0x600
+#define MX25_OTG_SIC_SHIFT      29
+#define MX25_OTG_SIC_MASK       (0x3 << MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BIT         (1 << 24)
+#define MX25_H1_SIC_SHIFT       21
+#define MX25_H1_SIC_MASK        (0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PM_BIT          (1 << 8)
+#define MX25_H1_IPPUE_UP_BIT    (1 << 7)
+#define MX25_H1_IPPUE_DOWN_BIT  (1 << 6)
+#define MX25_H1_TLL_BIT         (1 << 5)
+#define MX25_H1_USBTE_BIT       (1 << 4)
+int mx25_initialize_usb_hw(int port, unsigned int flags)
+{
+        unsigned int v;
+        v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+        switch (port) {
+        case 0: /* OTG port */
+                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX25_OTG_PM_BIT;
+                break;
+        case 1: /* H1 port */
+                v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT |
+                        MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX25_H1_PM_BIT;
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX25_H1_TLL_BIT;
+                if (flags & MXC_EHCI_INTERNAL_PHY)
+                        v |= MX25_H1_USBTE_BIT;
+                if (flags & MXC_EHCI_IPPUE_DOWN)
+                        v |= MX25_H1_IPPUE_DOWN_BIT;
+                if (flags & MXC_EHCI_IPPUE_UP)
+                        v |= MX25_H1_IPPUE_UP_BIT;
+                break;
+        default:
+                return -EINVAL;
+        }
+        writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+        return 0;
+}
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
new file mode 100644
index 000000000000..fa69419eabdd
--- /dev/null
+++ b/arch/arm/mach-imx/ehci-imx27.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+#define USBCTRL_OTGBASE_OFFSET  0x600
+#define MX27_OTG_SIC_SHIFT      29
+#define MX27_OTG_SIC_MASK       (0x3 << MX27_OTG_SIC_SHIFT)
+#define MX27_OTG_PM_BIT         (1 << 24)
+#define MX27_H2_SIC_SHIFT       21
+#define MX27_H2_SIC_MASK        (0x3 << MX27_H2_SIC_SHIFT)
+#define MX27_H2_PM_BIT          (1 << 16)
+#define MX27_H2_DT_BIT          (1 << 5)
+#define MX27_H1_SIC_SHIFT       13
+#define MX27_H1_SIC_MASK        (0x3 << MX27_H1_SIC_SHIFT)
+#define MX27_H1_PM_BIT          (1 << 8)
+#define MX27_H1_DT_BIT          (1 << 4)
+int mx27_initialize_usb_hw(int port, unsigned int flags)
+{
+        unsigned int v;
+        v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+        switch (port) {
+        case 0: /* OTG port */
+                v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT;
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX27_OTG_PM_BIT;
+                break;
+        case 1: /* H1 port */
+                v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT;
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX27_H1_PM_BIT;
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX27_H1_DT_BIT;
+                break;
+        case 2: /* H2 port */
+                v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT;
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX27_H2_PM_BIT;
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX27_H2_DT_BIT;
+                break;
+        default:
+                return -EINVAL;
+        }
+        writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+        return 0;
+}
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 275c8589d797..fa5288018ba7 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -249,7 +249,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 #define ADS7846_PENDOWN (GPIO_PORTD | 25)
-static void ads7846_dev_init(void)
+static void __maybe_unused ads7846_dev_init(void)
 {
        if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
@@ -268,7 +268,8 @@ static struct ads7846_platform_data ads7846_config __initdata = {
        .keep_vref_on           = 1,
 };
-static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
+static struct spi_board_info __maybe_unused
+                eukrea_mbimx27_spi_board_info[] __initdata = {
        [0] = {
                .modalias       = "ads7846",
                .bus_num        = 0,
@@ -357,13 +358,11 @@ void __init eukrea_mbimx27_baseboard_init(void)
        ads7846_dev_init();
 #endif
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
        /* SPI_CS0 init */
        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
        imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
        spi_register_board_info(eukrea_mbimx27_spi_board_info,
                        ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
-#endif
        /* Leds configuration */
        mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 6cf04da2456a..759299bb035b 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -209,17 +209,25 @@ static struct platform_device serial_device = {
 };
 #endif
-#if defined(CONFIG_USB_ULPI)
+static int eukrea_cpuimx27_otg_init(struct platform_device *pdev)
+{
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = eukrea_cpuimx27_otg_init,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev)
+{
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+        .init   = eukrea_cpuimx27_usbh2_init,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
-#endif
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
        .operating_mode = FSL_USB2_DR_DEVICE,
@@ -273,21 +281,19 @@ static void __init eukrea_cpuimx27_init(void)
        platform_device_register(&serial_device);
 #endif
-#if defined(CONFIG_USB_ULPI)
        if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                                ULPI_OTG_DRVVBUS_EXT);
+                if (otg_pdata.otg)
-                imx27_add_mxc_ehci_otg(&otg_pdata);
+                        imx27_add_mxc_ehci_otg(&otg_pdata);
+        } else {
+                imx27_add_fsl_usb2_udc(&otg_device_pdata);
        }
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (usbh2_pdata.otg)
-        imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
+                imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
-        if (!otg_mode_host)
-                imx27_add_fsl_usb2_udc(&otg_device_pdata);
 #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
        eukrea_mbimx27_baseboard_init();
@@ -304,9 +310,10 @@ static struct sys_timer eukrea_cpuimx27_timer = {
 };
 MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
+        .map_io = mx27_map_io,
-        .init_irq       = mx27_init_irq,
+        .init_early = imx27_init_early,
-        .init_machine   = eukrea_cpuimx27_init,
+        .init_irq = mx27_init_irq,
-        .timer          = &eukrea_cpuimx27_timer,
+        .timer = &eukrea_cpuimx27_timer,
+        .init_machine = eukrea_cpuimx27_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index eb395aba9237..9da8d18eeb00 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -84,15 +84,25 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
        },
 };
+static int eukrea_cpuimx25_otg_init(struct platform_device *pdev)
+{
+        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
 static const struct mxc_usbh_platform_data otg_pdata __initconst = {
+        .init   = eukrea_cpuimx25_otg_init,
        .portsc = MXC_EHCI_MODE_UTMI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev)
+{
+        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
+                        MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
+}
 static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
+        .init   = eukrea_cpuimx25_usbh2_init,
        .portsc = MXC_EHCI_MODE_SERIAL,
-        .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
-                  MXC_EHCI_IPPUE_DOWN,
 };
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -153,9 +163,10 @@ static struct sys_timer eukrea_cpuimx25_timer = {
 MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
        /* Maintainer: Eukrea Electromatique */
-        .boot_params    = MX25_PHYS_OFFSET + 0x100,
+        .boot_params = MX25_PHYS_OFFSET + 0x100,
-        .map_io         = mx25_map_io,
+        .map_io = mx25_map_io,
-        .init_irq       = mx25_init_irq,
+        .init_early = imx25_init_early,
-        .init_machine   = eukrea_cpuimx25_init,
+        .init_irq = mx25_init_irq,
-        .timer          = &eukrea_cpuimx25_timer,
+        .timer = &eukrea_cpuimx25_timer,
+        .init_machine = eukrea_cpuimx25_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 40a3666ea632..d7e0d219726a 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -30,6 +30,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/delay.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -66,6 +67,11 @@ static const int visstrim_m10_pins[] __initconst = {
        PD15_AOUT_FEC_COL,
        PD16_AIN_FEC_TX_ER,
        PF23_AIN_FEC_TX_EN,
+        /* SSI1 */
+        PC20_PF_SSI1_FS,
+        PC21_PF_SSI1_RXD,
+        PC22_PF_SSI1_TXD,
+        PC23_PF_SSI1_CLK,
        /* SDHC1 */
        PE18_PF_SD1_D0,
        PE19_PF_SD1_D1,
@@ -204,20 +210,30 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = {
                I2C_BOARD_INFO("pca9555", 0x20),
                .platform_data = &visstrim_m10_pca9555_pdata,
        },
+        {
+                I2C_BOARD_INFO("tlv320aic32x4", 0x18),
+        }
 };
 /* USB OTG */
 static int otg_phy_init(struct platform_device *pdev)
 {
        gpio_set_value(OTG_PHY_CS_GPIO, 0);
-        return 0;
+        mdelay(10);
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
 }
 static const struct mxc_usbh_platform_data
 visstrim_m10_usbotg_pdata __initconst = {
        .init = otg_phy_init,
        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+/* SSI */
+static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
+        .flags                  = IMX_SSI_DMA | IMX_SSI_SYN,
 };
 static void __init visstrim_m10_board_init(void)
@@ -229,6 +245,7 @@ static void __init visstrim_m10_board_init(void)
        if (ret)
                pr_err("Failed to setup pins (%d)\n", ret);
+        imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
        imx27_add_imx_uart0(&uart_pdata);
        i2c_register_board_info(0, visstrim_m10_i2c_devices,
@@ -251,9 +268,10 @@ static struct sys_timer visstrim_m10_timer = {
 };
 MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
+        .map_io = mx27_map_io,
-        .init_irq       = mx27_init_irq,
+        .init_early = imx27_init_early,
-        .init_machine   = visstrim_m10_board_init,
+        .init_irq = mx27_init_irq,
-        .timer          = &visstrim_m10_timer,
+        .timer = &visstrim_m10_timer,
+        .init_machine = visstrim_m10_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
new file mode 100644
index 000000000000..9be6cd6fbf8c
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx27.h>
+#include "devices-imx27.h"
+static const int mx27ipcam_pins[] __initconst = {
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+};
+static void __init mx27ipcam_init(void)
+{
+        mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins),
+                "mx27ipcam");
+        imx27_add_imx_uart0(NULL);
+        imx27_add_fec(NULL);
+        imx27_add_imx2_wdt(NULL);
+}
+static void __init mx27ipcam_timer_init(void)
+{
+        mx27_clocks_init(25000000);
+}
+static struct sys_timer mx27ipcam_timer = {
+        .init   = mx27ipcam_timer_init,
+};
+MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
+        /* maintainer: Freescale Semiconductor, Inc. */
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .map_io = mx27_map_io,
+        .init_early = imx27_init_early,
+        .init_irq = mx27_init_irq,
+        .timer = &mx27ipcam_timer,
+        .init_machine = mx27ipcam_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 3a1202e47212..841140516ede 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -75,9 +75,10 @@ static struct sys_timer mx27lite_timer = {
 };
 MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
+        .map_io = mx27_map_io,
-        .init_irq       = mx27_init_irq,
+        .init_early = imx27_init_early,
-        .init_machine   = mx27lite_init,
+        .init_irq = mx27_init_irq,
-        .timer          = &mx27lite_timer,
+        .timer = &mx27lite_timer,
+        .init_machine = mx27lite_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 1f446e5eb636..47cf56ac6d5b 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -144,17 +144,19 @@ struct sys_timer mx1ads_timer = {
 MACHINE_START(MX1ADS, "Freescale MX1ADS")
        /* Maintainer: Sascha Hauer, Pengutronix */
-        .boot_params    = MX1_PHYS_OFFSET + 0x100,
+        .boot_params = MX1_PHYS_OFFSET + 0x100,
-        .map_io         = mx1_map_io,
+        .map_io = mx1_map_io,
-        .init_irq       = mx1_init_irq,
+        .init_early = imx1_init_early,
-        .timer          = &mx1ads_timer,
+        .init_irq = mx1_init_irq,
-        .init_machine   = mx1ads_init,
+        .timer = &mx1ads_timer,
+        .init_machine = mx1ads_init,
 MACHINE_END
 MACHINE_START(MXLADS, "Freescale MXLADS")
-        .boot_params    = MX1_PHYS_OFFSET + 0x100,
+        .boot_params = MX1_PHYS_OFFSET + 0x100,
-        .map_io         = mx1_map_io,
+        .map_io = mx1_map_io,
-        .init_irq       = mx1_init_irq,
+        .init_early = imx1_init_early,
-        .timer          = &mx1ads_timer,
+        .init_irq = mx1_init_irq,
-        .init_machine   = mx1ads_init,
+        .timer = &mx1ads_timer,
+        .init_machine = mx1ads_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 0a372577c2ac..fa52a1086eae 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -304,9 +304,10 @@ static struct sys_timer mx21ads_timer = {
 MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
        /* maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX21_PHYS_OFFSET + 0x100,
+        .boot_params = MX21_PHYS_OFFSET + 0x100,
-        .map_io         = mx21ads_map_io,
+        .map_io = mx21ads_map_io,
-        .init_irq       = mx21_init_irq,
+        .init_early = imx21_init_early,
-        .init_machine   = mx21ads_board_init,
+        .init_irq = mx21_init_irq,
-        .timer          = &mx21ads_timer,
+        .timer = &mx21ads_timer,
+        .init_machine = mx21ads_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 8382e7902078..06da438282aa 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -103,14 +103,18 @@ static iomux_v3_cfg_t mx25pdk_pads[] = {
        MX25_PAD_SD1_DATA1__SD1_DATA1,
        MX25_PAD_SD1_DATA2__SD1_DATA2,
        MX25_PAD_SD1_DATA3__SD1_DATA3,
+        /* I2C1 */
+        MX25_PAD_I2C1_CLK__I2C1_CLK,
+        MX25_PAD_I2C1_DAT__I2C1_DAT,
 };
 static const struct fec_platform_data mx25_fec_pdata __initconst = {
        .phy    = PHY_INTERFACE_MODE_RMII,
 };
-#define FEC_ENABLE_GPIO         35
+#define FEC_ENABLE_GPIO         IMX_GPIO_NR(2, 3)
-#define FEC_RESET_B_GPIO        104
+#define FEC_RESET_B_GPIO        IMX_GPIO_NR(4, 8)
 static void __init mx25pdk_fec_reset(void)
 {
@@ -185,9 +189,14 @@ static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
        .keymap_size    = ARRAY_SIZE(mx25pdk_keymap),
 };
+static int mx25pdk_usbh2_init(struct platform_device *pdev)
+{
+        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
+}
 static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
+        .init   = mx25pdk_usbh2_init,
        .portsc = MXC_EHCI_MODE_SERIAL,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -195,6 +204,10 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
        .phy_mode       = FSL_USB2_PHY_UTMI,
 };
+static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
+        .bitrate = 100000,
+};
 static void __init mx25pdk_init(void)
 {
        mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
@@ -213,6 +226,7 @@ static void __init mx25pdk_init(void)
        imx25_add_imx_keypad(&mx25pdk_keymap_data);
        imx25_add_sdhci_esdhc_imx(0, NULL);
+        imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
 }
 static void __init mx25pdk_timer_init(void)
@@ -226,10 +240,10 @@ static struct sys_timer mx25pdk_timer = {
 MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
        /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX25_PHYS_OFFSET + 0x100,
+        .boot_params = MX25_PHYS_OFFSET + 0x100,
-        .map_io         = mx25_map_io,
+        .map_io = mx25_map_io,
-        .init_irq       = mx25_init_irq,
+        .init_early = imx25_init_early,
-        .init_machine   = mx25pdk_init,
+        .init_irq = mx25_init_irq,
-        .timer          = &mx25pdk_timer,
+        .timer = &mx25pdk_timer,
+        .init_machine = mx25pdk_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 164331518bdd..614b3c00c4a0 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -98,6 +98,9 @@ static const int mx27pdk_pins[] __initconst = {
        PD22_PF_CSPI2_SCLK,
        PD23_PF_CSPI2_MISO,
        PD24_PF_CSPI2_MOSI,
+        /* I2C1 */
+        PD17_PF_I2C_DATA,
+        PD18_PF_I2C_CLK,
 };
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -159,13 +162,15 @@ static int otg_phy_init(void)
        return 0;
 }
-#if defined(CONFIG_USB_ULPI)
+static int mx27_3ds_otg_init(struct platform_device *pdev)
+{
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = mx27_3ds_otg_init,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
-#endif
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
        .operating_mode = FSL_USB2_DR_DEVICE,
@@ -216,7 +221,7 @@ static struct regulator_init_data vgen_init = {
        .consumer_supplies = vgen_consumers,
 };
-static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
+static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
        {
                .id = MC13783_REG_VMMC1,
                .init_data = &vmmc1_init,
@@ -227,10 +232,10 @@ static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
 };
 /* MC13783 */
-static struct mc13783_platform_data mc13783_pdata __initdata = {
+static struct mc13xxx_platform_data mc13783_pdata __initdata = {
        .regulators = mx27_3ds_regulators,
        .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
-        .flags  = MC13783_USE_REGULATOR,
+        .flags  = MC13XXX_USE_REGULATOR,
 };
 /* SPI */
@@ -253,6 +258,9 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
        },
 };
+static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
+        .bitrate = 100000,
+};
 static void __init mx27pdk_init(void)
 {
@@ -265,14 +273,15 @@ static void __init mx27pdk_init(void)
        imx27_add_mxc_mmc(0, &sdhc1_pdata);
        imx27_add_imx2_wdt(NULL);
        otg_phy_init();
-#if defined(CONFIG_USB_ULPI)
        if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                                ULPI_OTG_DRVVBUS_EXT);
-                imx27_add_mxc_ehci_otg(&otg_pdata);
+                if (otg_pdata.otg)
+                        imx27_add_mxc_ehci_otg(&otg_pdata);
        }
-#endif
        if (!otg_mode_host)
                imx27_add_fsl_usb2_udc(&otg_device_pdata);
@@ -282,6 +291,7 @@ static void __init mx27pdk_init(void)
        if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
+        imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
 }
 static void __init mx27pdk_timer_init(void)
@@ -295,9 +305,10 @@ static struct sys_timer mx27pdk_timer = {
 MACHINE_START(MX27_3DS, "Freescale MX27PDK")
        /* maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
+        .map_io = mx27_map_io,
-        .init_irq       = mx27_init_irq,
+        .init_early = imx27_init_early,
-        .init_machine   = mx27pdk_init,
+        .init_irq = mx27_init_irq,
-        .timer          = &mx27pdk_timer,
+        .timer = &mx27pdk_timer,
+        .init_machine = mx27pdk_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index b832f960fec4..367d1e4384c7 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -344,9 +344,10 @@ static void __init mx27ads_map_io(void)
 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
        /* maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27ads_map_io,
+        .map_io = mx27ads_map_io,
-        .init_irq       = mx27_init_irq,
+        .init_early = imx27_init_early,
-        .init_machine   = mx27ads_board_init,
+        .init_irq = mx27_init_irq,
-        .timer          = &mx27ads_timer,
+        .timer = &mx27ads_timer,
+        .init_machine = mx27ads_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 4ce71b0401db..69787c30c320 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -266,10 +266,10 @@ static struct sys_timer mxt_td60_timer = {
 MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
        /* maintainer: Maxtrack Industrial */
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
+        .map_io = mx27_map_io,
-        .init_irq       = mx27_init_irq,
+        .init_early = imx27_init_early,
-        .init_machine   = mxt_td60_board_init,
+        .init_irq = mx27_init_irq,
-        .timer          = &mxt_td60_timer,
+        .timer = &mxt_td60_timer,
+        .init_machine = mxt_td60_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index cccc0a0a9c72..63e182556778 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -187,7 +187,6 @@ static struct i2c_board_info pca100_i2c_devices[] = {
        }
 };
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
 static struct spi_eeprom at25320 = {
        .name           = "at25320an",
        .byte_len       = 4096,
@@ -211,7 +210,6 @@ static const struct spi_imx_master pca100_spi0_data __initconst = {
        .chipselect     = pca100_spi_cs,
        .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
 };
-#endif
 static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
 {
@@ -269,31 +267,33 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = {
        .exit = pca100_sdhc2_exit,
 };
-#if defined(CONFIG_USB_ULPI)
 static int otg_phy_init(struct platform_device *pdev)
 {
        gpio_set_value(OTG_PHY_CS_GPIO, 0);
-        return 0;
+        mdelay(10);
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
 }
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
        .init   = otg_phy_init,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 static int usbh2_phy_init(struct platform_device *pdev)
 {
        gpio_set_value(USBH2_PHY_CS_GPIO, 0);
-        return 0;
+        mdelay(10);
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
 }
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
        .init   = usbh2_phy_init,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
-#endif
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
        .operating_mode = FSL_USB2_DR_DEVICE,
@@ -389,36 +389,33 @@ static void __init pca100_init(void)
        imx27_add_imx_i2c(1, &pca100_i2c1_data);
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
        mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
        spi_register_board_info(pca100_spi_board_info,
                                ARRAY_SIZE(pca100_spi_board_info));
        imx27_add_spi_imx0(&pca100_spi0_data);
-#endif
        gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
        gpio_direction_output(OTG_PHY_CS_GPIO, 1);
        gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
        gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
-#if defined(CONFIG_USB_ULPI)
        if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                                ULPI_OTG_DRVVBUS_EXT);
-                imx27_add_mxc_ehci_otg(&otg_pdata);
+                if (otg_pdata.otg)
+                        imx27_add_mxc_ehci_otg(&otg_pdata);
+        } else {
+                gpio_set_value(OTG_PHY_CS_GPIO, 0);
+                imx27_add_fsl_usb2_udc(&otg_device_pdata);
        }
        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-        imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
+        if (usbh2_pdata.otg)
-#endif
+                imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
-        if (!otg_mode_host) {
-                gpio_set_value(OTG_PHY_CS_GPIO, 0);
-                imx27_add_fsl_usb2_udc(&otg_device_pdata);
-        }
        imx27_add_imx_fb(&pca100_fb_data);
@@ -437,10 +434,10 @@ static struct sys_timer pca100_timer = {
 };
 MACHINE_START(PCA100, "phyCARD-i.MX27")
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
+        .map_io = mx27_map_io,
-        .init_irq       = mx27_init_irq,
+        .init_early = imx27_init_early,
-        .init_machine   = pca100_init,
+        .init_irq = mx27_init_irq,
-        .timer          = &pca100_timer,
+        .init_machine = pca100_init,
+        .timer = &pca100_timer,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 505614803bc6..38c77084b615 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -252,7 +252,7 @@ static struct regulator_init_data cam_data = {
        .consumer_supplies = cam_consumers,
 };
-static struct mc13783_regulator_init_data pcm038_regulators[] = {
+static struct mc13xxx_regulator_init_data pcm038_regulators[] = {
        {
                .id = MC13783_REG_VCAM,
                .init_data = &cam_data,
@@ -262,11 +262,11 @@ static struct mc13783_regulator_init_data pcm038_regulators[] = {
        },
 };
-static struct mc13783_platform_data pcm038_pmic = {
+static struct mc13xxx_platform_data pcm038_pmic = {
        .regulators = pcm038_regulators,
        .num_regulators = ARRAY_SIZE(pcm038_regulators),
-        .flags = MC13783_USE_ADC | MC13783_USE_REGULATOR |
+        .flags = MC13XXX_USE_ADC | MC13XXX_USE_REGULATOR |
-                 MC13783_USE_TOUCHSCREEN,
+                 MC13XXX_USE_TOUCHSCREEN,
 };
 static struct spi_board_info pcm038_spi_board_info[] __initdata = {
@@ -281,9 +281,15 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
        }
 };
+static int pcm038_usbh2_init(struct platform_device *pdev)
+{
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_DIFF_UNI);
+}
 static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
+        .init   = pcm038_usbh2_init,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 static void __init pcm038_init(void)
@@ -340,9 +346,10 @@ static struct sys_timer pcm038_timer = {
 };
 MACHINE_START(PCM038, "phyCORE-i.MX27")
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
+        .map_io = mx27_map_io,
-        .init_irq       = mx27_init_irq,
+        .init_early = imx27_init_early,
-        .init_machine   = pcm038_init,
+        .init_irq = mx27_init_irq,
-        .timer          = &pcm038_timer,
+        .timer = &pcm038_timer,
+        .init_machine = pcm038_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index eae878f306c6..dcaee043628e 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -145,10 +145,11 @@ static struct sys_timer scb9328_timer = {
 };
 MACHINE_START(SCB9328, "Synertronixx scb9328")
-    /* Sascha Hauer */
+        /* Sascha Hauer */
-        .boot_params    = 0x08000100,
+        .boot_params = 0x08000100,
-        .map_io         = mx1_map_io,
+        .map_io = mx1_map_io,
-        .init_irq       = mx1_init_irq,
+        .init_early = imx1_init_early,
-        .timer          = &scb9328_timer,
+        .init_irq = mx1_init_irq,
-        .init_machine   = scb9328_init,
+        .timer = &scb9328_timer,
+        .init_machine = scb9328_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 729ae0915af8..2e482ba5a0e7 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -23,6 +23,9 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
 static struct map_desc imx_io_desc[] __initdata = {
        imx_map_entry(MX1, IO, MT_DEVICE),
@@ -30,16 +33,26 @@ static struct map_desc imx_io_desc[] __initdata = {
 void __init mx1_map_io(void)
 {
+        iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
+}
+void __init imx1_init_early(void)
+{
        mxc_set_cpu_type(MXC_CPU_MX1);
        mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
+        imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
-        iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
+                        MX1_NUM_GPIO_PORT);
 }
-int imx1_register_gpios(void);
+static struct mxc_gpio_port imx1_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
+};
 void __init mx1_init_irq(void)
 {
        mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
-        imx1_register_gpios();
+        mxc_gpio_init(imx1_gpio_ports,  ARRAY_SIZE(imx1_gpio_ports));
 }
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index e728af81d1b1..7a0c500ac2c8 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -24,6 +24,9 @@
 #include <mach/common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
 /* MX21 memory map definition */
 static struct map_desc imx21_io_desc[] __initdata = {
@@ -56,16 +59,28 @@ static struct map_desc imx21_io_desc[] __initdata = {
 */
 void __init mx21_map_io(void)
 {
+        iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
+}
+void __init imx21_init_early(void)
+{
        mxc_set_cpu_type(MXC_CPU_MX21);
        mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
+        imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
-        iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
+                        MX21_NUM_GPIO_PORT);
 }
-int imx21_register_gpios(void);
+static struct mxc_gpio_port imx21_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
+        DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
+        DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
+        DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
+        DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
+        DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
+};
 void __init mx21_init_irq(void)
 {
        mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
-        imx21_register_gpios();
+        mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
 }
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 2edec6ce8fe7..02f7b5c7fa8e 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -27,6 +27,8 @@
 #include <mach/hardware.h>
 #include <mach/mx25.h>
 #include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
 /*
 * This table defines static virtual address mappings for I/O regions.
@@ -45,18 +47,26 @@ static struct map_desc mx25_io_desc[] __initdata = {
 */
 void __init mx25_map_io(void)
 {
+        iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
+}
+void __init imx25_init_early(void)
+{
        mxc_set_cpu_type(MXC_CPU_MX25);
        mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
-        iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
 }
-int imx25_register_gpios(void);
+static struct mxc_gpio_port imx25_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
+};
 void __init mx25_init_irq(void)
 {
        mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
-        imx25_register_gpios();
+        mxc_gpio_init(imx25_gpio_ports, ARRAY_SIZE(imx25_gpio_ports));
 }
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 374e48b7a412..a6761a39f08c 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -24,6 +24,9 @@
 #include <mach/common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
 /* MX27 memory map definition */
 static struct map_desc imx27_io_desc[] __initdata = {
@@ -56,16 +59,28 @@ static struct map_desc imx27_io_desc[] __initdata = {
 */
 void __init mx27_map_io(void)
 {
+        iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
+}
+void __init imx27_init_early(void)
+{
        mxc_set_cpu_type(MXC_CPU_MX27);
        mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
+        imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
-        iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
+                        MX27_NUM_GPIO_PORT);
 }
-int imx27_register_gpios(void);
+static struct mxc_gpio_port imx27_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
+        DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
+        DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
+        DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
+        DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
+        DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
+};
 void __init mx27_init_irq(void)
 {
        mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
-        imx27_register_gpios();
+        mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
 }
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 3688123b5ad8..20e71df3e3bb 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -21,6 +21,7 @@
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
+#include <asm/kexec.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
@@ -846,9 +847,14 @@ static void __init kirkwood_wdt_init(void)
 /*****************************************************************************
 * Time handling
 ****************************************************************************/
+void __init kirkwood_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
 int kirkwood_tclk;
-int __init kirkwood_find_tclk(void)
+static int __init kirkwood_find_tclk(void)
 {
        u32 dev, rev;
@@ -864,7 +870,9 @@ int __init kirkwood_find_tclk(void)
 static void __init kirkwood_timer_init(void)
 {
        kirkwood_tclk = kirkwood_find_tclk();
-        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
 }
 struct sys_timer kirkwood_timer = {
@@ -1003,6 +1011,10 @@ void __init kirkwood_init(void)
        kirkwood_xor0_init();
        kirkwood_xor1_init();
        kirkwood_crypto_init();
+#ifdef CONFIG_KEXEC 
+        kexec_reinit = kirkwood_enable_pcie;
+#endif
 }
 static int __init kirkwood_clock_gate(void)
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 95bb0a73adfb..b9b0f0968a36 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -27,11 +27,13 @@ struct kirkwood_asoc_platform_data;
 */
 void kirkwood_map_io(void);
 void kirkwood_init(void);
+void kirkwood_init_early(void);
 void kirkwood_init_irq(void);
 extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
 void kirkwood_setup_cpu_mbus(void);
+void kirkwood_enable_pcie(void);
 void kirkwood_pcie_id(u32 *dev, u32 *rev);
 void kirkwood_ehci_init(void);
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index a31c9499ab36..043cfd5e140b 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -224,6 +224,7 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
        .boot_params    = 0x00000100,
        .init_machine   = d2net_v2_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 9ea71182d31a..bff04e04d679 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -100,6 +100,7 @@ MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
        .boot_params    = 0x00000100,
        .init_machine   = db88f6281_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index 433ea368c060..f14dfb8508c5 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -105,6 +105,7 @@ MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
        .boot_params    = 0x00000100,
        .init_machine   = dockstar_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 8f47dc0a2fef..41d1b40696a3 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -124,6 +124,7 @@ MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
        .boot_params    = 0x00000100,
        .init_machine   = guruplug_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index aff0e1327e38..957bd7997d7e 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -29,9 +29,6 @@
 #define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
 #define WDT_INT_REQ             0x0008
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-kirkwood/include/mach/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h
index 81b335eb62ec..84f340b546c0 100644
--- a/arch/arm/mach-kirkwood/include/mach/gpio.h
+++ b/arch/arm/mach-kirkwood/include/mach/gpio.h
@@ -6,33 +6,4 @@
 * warranty of any kind, whether express or implied.
 */
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-#define GPIO_MAX                50
-#define GPIO_OFF(pin)           (((pin) >> 5) ? 0x0140 : 0x0100)
-#define GPIO_OUT(pin)           (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x00)
-#define GPIO_IO_CONF(pin)       (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x04)
-#define GPIO_BLINK_EN(pin)      (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x08)
-#define GPIO_IN_POL(pin)        (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x0c)
-#define GPIO_DATA_IN(pin)       (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin)    (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)     (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin)    (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x1c)
-static inline int gpio_to_irq(int pin)
-{
-        return pin + IRQ_KIRKWOOD_GPIO_START;
-}
-static inline int irq_to_gpio(int irq)
-{
-        return irq - IRQ_KIRKWOOD_GPIO_START;
-}
-#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 6e924b398919..010bdeb4ac5f 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -69,6 +69,8 @@
 #define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
 #define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
 #define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
+#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE | 0x0100)
+#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE | 0x0140)
 #define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
 #define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
 #define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x1000)
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 28020abf49e1..cbdb5863d13b 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -27,31 +27,21 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 void __init kirkwood_init_irq(void)
 {
-        int i;
        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
        /*
-         * Mask and clear GPIO IRQ interrupts.
+         * Initialize gpiolib for GPIOs 0-49.
         */
-        writel(0, GPIO_LEVEL_MASK(0));
+        orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
-        writel(0, GPIO_EDGE_MASK(0));
+                        IRQ_KIRKWOOD_GPIO_START);
-        writel(0, GPIO_EDGE_CAUSE(0));
-        writel(0, GPIO_LEVEL_MASK(32));
-        writel(0, GPIO_EDGE_MASK(32));
-        writel(0, GPIO_EDGE_CAUSE(32));
-        for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
+        orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
+                        IRQ_KIRKWOOD_GPIO_START + 32);
        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 27901f702feb..7ce201848067 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -49,9 +49,6 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
        if (!variant_mask)
                return;
-        /* Initialize gpiolib. */
-        orion_gpio_init();
        printk(KERN_DEBUG "initial MPP regs:");
        for (i = 0; i < MPP_NR_REGS; i++) {
                mpp_ctrl[i] = readl(MPP_CTRL(i));
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 1e5266f57e2a..00cca22eca6f 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -166,6 +166,7 @@ MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
        .boot_params    = 0x00000100,
        .init_machine   = mv88f6281gtw_ge_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 65ee21fd2f3b..7cdab5776452 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -261,6 +261,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
        .boot_params    = 0x00000100,
        .init_machine   = netspace_v2_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
@@ -271,6 +272,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
        .boot_params    = 0x00000100,
        .init_machine   = netspace_v2_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
@@ -281,6 +283,7 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
        .boot_params    = 0x00000100,
        .init_machine   = netspace_v2_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 93afd3c8bfd8..6be627deb0fc 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -402,6 +402,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
        .boot_params    = 0x00000100,
        .init_machine   = netxbig_v2_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
@@ -412,6 +413,7 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
        .boot_params    = 0x00000100,
        .init_machine   = netxbig_v2_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index cfcca4174e25..f69beeff4450 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -217,6 +217,7 @@ MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
        .boot_params    = 0x00000100,
        .init_machine   = openrd_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
@@ -228,6 +229,7 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
        .boot_params    = 0x00000100,
        .init_machine   = openrd_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
@@ -239,6 +241,7 @@ MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
        .boot_params    = 0x00000100,
        .init_machine   = openrd_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 513ad3102d7c..ca294ff6d5be 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,8 +18,16 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
+void kirkwood_enable_pcie(void)
+{
+        u32 curr = readl(CLOCK_GATING_CTRL);
+        if (!(curr & CGC_PEX0))
+                writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
+}
 void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
 {
+        kirkwood_enable_pcie();
        *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
        *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 0049614cd324..75c6601b8d87 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -82,6 +82,7 @@ MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
        .boot_params    = 0x00000100,
        .init_machine   = rd88f6192_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 0998a08cf42d..0f75494d5902 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -118,6 +118,7 @@ MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
        .boot_params    = 0x00000100,
        .init_machine   = rd88f6281_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index d2eec35dfe0f..0a95063f6d32 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -134,6 +134,7 @@ MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
        .boot_params    = 0x00000100,
        .init_machine   = sheevaplug_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
@@ -144,6 +145,7 @@ MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
        .boot_params    = 0x00000100,
        .init_machine   = sheevaplug_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index ce50e61aac9f..e6b9b1b22a35 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -23,6 +23,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <sound/alc5623.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
@@ -134,6 +135,7 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
        MPP33_GE1_TXCTL,
        MPP39_AU_I2SBCLK,
        MPP40_AU_I2SDO,
+        MPP43_AU_I2SDI,
        MPP41_AU_I2SLRCLK,
        MPP42_AU_I2SMCLK,
        MPP45_GPIO,             /* Power button */
@@ -141,6 +143,18 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
        0
 };
+static struct alc5623_platform_data alc5621_data = {
+        .add_ctrl = 0x3700,
+        .jack_det_ctrl = 0x4810,
+};
+static struct i2c_board_info i2c_board_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("alc5621", 0x1a),
+                .platform_data = &alc5621_data,
+        },
+};
 #define HP_T5325_GPIO_POWER_OFF         48
 static void hp_t5325_power_off(void)
@@ -166,6 +180,9 @@ static void __init hp_t5325_init(void)
        kirkwood_ehci_init();
        platform_device_register(&hp_t5325_button_device);
+        i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info));
+        kirkwood_audio_init();
        if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
            gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
                pm_power_off = hp_t5325_power_off;
@@ -187,6 +204,7 @@ MACHINE_START(T5325, "HP t5325 Thin Client")
        .boot_params    = 0x00000100,
        .init_machine   = hp_t5325_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index dc999c4c5806..68f32f2bf552 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -135,6 +135,7 @@ MACHINE_START(TS219, "QNAP TS-119/TS-219")
        .boot_params    = 0x00000100,
        .init_machine   = qnap_ts219_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 9a44029915e2..d5d009970705 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -154,6 +154,8 @@ static void __init qnap_ts41x_init(void)
 static int __init ts41x_pci_init(void)
 {
        if (machine_is_ts41x()) {
+                u32 dev, rev;
                /*
                 * Without this explicit reset, the PCIe SATA controller
                 * (Marvell 88sx7042/sata_mv) is known to stop working
@@ -161,7 +163,11 @@ static int __init ts41x_pci_init(void)
                 */
                orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
-                kirkwood_pcie_init(KW_PCIE0);
+                kirkwood_pcie_id(&dev, &rev);
+                if (dev == MV88F6282_DEV_ID)
+                        kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
+                else
+                        kirkwood_pcie_init(KW_PCIE0);
        }
   return 0;
@@ -173,6 +179,7 @@ MACHINE_START(TS41X, "QNAP TS-41x")
        .boot_params    = 0x00000100,
        .init_machine   = qnap_ts41x_init,
        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
index 818f19d7ab1f..e41e909cf8f4 100644
--- a/arch/arm/mach-loki/common.c
+++ b/arch/arm/mach-loki/common.c
@@ -18,6 +18,7 @@
 #include <asm/timex.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <mach/bridge-regs.h>
 #include <mach/loki.h>
 #include <plat/orion_nand.h>
 #include <plat/time.h>
@@ -290,9 +291,15 @@ void __init loki_uart1_init(void)
 /*****************************************************************************
 * Time handling
 ****************************************************************************/
+void __init loki_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
 static void loki_timer_init(void)
 {
-        orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK);
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_LOKI_BRIDGE, LOKI_TCLK);
 }
 struct sys_timer loki_timer = {
diff --git a/arch/arm/mach-loki/common.h b/arch/arm/mach-loki/common.h
index 26054fd0f05e..a315dcf8887c 100644
--- a/arch/arm/mach-loki/common.h
+++ b/arch/arm/mach-loki/common.h
@@ -18,6 +18,7 @@ struct mv643xx_eth_platform_data;
 */
 void loki_map_io(void);
 void loki_init(void);
+void loki_init_early(void);
 void loki_init_irq(void);
 extern struct mbus_dram_target_info loki_mbus_dram_info;
diff --git a/arch/arm/mach-loki/include/mach/bridge-regs.h b/arch/arm/mach-loki/include/mach/bridge-regs.h
index a3fabf70044f..fd87732097cd 100644
--- a/arch/arm/mach-loki/include/mach/bridge-regs.h
+++ b/arch/arm/mach-loki/include/mach/bridge-regs.h
@@ -17,11 +17,6 @@
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
 #define SOFT_RESET              0x00000001
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   0x0004
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
index a1e75e7fc500..35eae4e6abb2 100644
--- a/arch/arm/mach-loki/lb88rc8480-setup.c
+++ b/arch/arm/mach-loki/lb88rc8480-setup.c
@@ -93,6 +93,7 @@ MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
        .boot_params    = 0x00000100,
        .init_machine   = lb88rc8480_init,
        .map_io         = loki_map_io,
+        .init_early     = loki_init_early,
        .init_irq       = loki_init_irq,
        .timer          = &loki_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index 29e390e89ff4..20f3f125ed2b 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -148,6 +148,7 @@ MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
        .boot_params    = 0x00000100,
        .init_machine   = wxl_init,
        .map_io         = mv78xx0_map_io,
+        .init_early     = mv78xx0_init_early,
        .init_irq       = mv78xx0_init_irq,
        .timer          = &mv78xx0_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 08465eb6a2c2..44fb4e55be0d 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -818,9 +818,15 @@ void __init mv78xx0_uart3_init(void)
 /*****************************************************************************
 * Time handling
 ****************************************************************************/
+void __init mv78xx0_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
 static void mv78xx0_timer_init(void)
 {
-        orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_MV78XX0_TIMER_1, get_tclk());
 }
 struct sys_timer mv78xx0_timer = {
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index befc22475469..632e63d65e7a 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -20,6 +20,7 @@ struct mv_sata_platform_data;
 int mv78xx0_core_index(void);
 void mv78xx0_map_io(void);
 void mv78xx0_init(void);
+void mv78xx0_init_early(void);
 void mv78xx0_init_irq(void);
 extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index 207c95e403b9..df5aebe5b0fa 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -96,6 +96,7 @@ MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
        .boot_params    = 0x00000100,
        .init_machine   = db78x00_init,
        .map_io         = mv78xx0_map_io,
+        .init_early     = mv78xx0_init_early,
        .init_irq       = mv78xx0_init_irq,
        .timer          = &mv78xx0_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index 2d14c4fe294d..c64dbb96dbad 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -20,10 +20,6 @@
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
 #define SOFT_RESET              0x00000001
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-mv78xx0/include/mach/gpio.h b/arch/arm/mach-mv78xx0/include/mach/gpio.h
index d9d1535ea100..77e1b843e768 100644
--- a/arch/arm/mach-mv78xx0/include/mach/gpio.h
+++ b/arch/arm/mach-mv78xx0/include/mach/gpio.h
@@ -6,35 +6,4 @@
 * warranty of any kind, whether express or implied.
 */
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-extern int mv78xx0_core_index(void);
-#define GPIO_MAX                32
-#define GPIO_OUT(pin)           (DEV_BUS_VIRT_BASE + 0x0100)
-#define GPIO_IO_CONF(pin)       (DEV_BUS_VIRT_BASE + 0x0104)
-#define GPIO_BLINK_EN(pin)      (DEV_BUS_VIRT_BASE + 0x0108)
-#define GPIO_IN_POL(pin)        (DEV_BUS_VIRT_BASE + 0x010c)
-#define GPIO_DATA_IN(pin)       (DEV_BUS_VIRT_BASE + 0x0110)
-#define GPIO_EDGE_CAUSE(pin)    (DEV_BUS_VIRT_BASE + 0x0114)
-#define GPIO_MASK_OFF           (mv78xx0_core_index() ? 0x18 : 0)
-#define GPIO_EDGE_MASK(pin)     (DEV_BUS_VIRT_BASE + 0x0118 + GPIO_MASK_OFF)
-#define GPIO_LEVEL_MASK(pin)    (DEV_BUS_VIRT_BASE + 0x011c + GPIO_MASK_OFF)
-static inline int gpio_to_irq(int pin)
-{
-        return pin + IRQ_MV78XX0_GPIO_START;
-}
-static inline int irq_to_gpio(int irq)
-{
-        return irq - IRQ_MV78XX0_GPIO_START;
-}
-#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index 3eff39921d4d..3674497162e3 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -71,6 +71,7 @@
 #define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
 #define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
 #define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
+#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE | 0x0100)
 #define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1000)
 #define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1100)
 #define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 22b4ff893b3c..08da497c39c2 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -26,28 +26,18 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 void __init mv78xx0_init_irq(void)
 {
-        int i;
-        /* Initialize gpiolib. */
-        orion_gpio_init();
        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
        orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
        /*
-         * Mask and clear GPIO IRQ interrupts.
+         * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
+         * registers for core #1 are at an offset of 0x18 from those of
+         * core #0.)
         */
-        writel(0, GPIO_LEVEL_MASK(0));
+        orion_gpio_init(0, 32, GPIO_VIRT_BASE,
-        writel(0, GPIO_EDGE_MASK(0));
+                        mv78xx0_core_index() ? 0x18 : 0,
-        writel(0, GPIO_EDGE_CAUSE(0));
+                        IRQ_MV78XX0_GPIO_START);
-        for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
        set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
        set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
        set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 84db2dfc475c..65b72c454cb0 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -44,9 +44,6 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
        if (!variant_mask)
                return;
-        /* Initialize gpiolib. */
-        orion_gpio_init();
        printk(KERN_DEBUG "initial MPP regs:");
        for (i = 0; i < MPP_NR_REGS; i++) {
                mpp_ctrl[i] = readl(MPP_CTRL(i));
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index 3511ad4d973b..d927f14c6810 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -81,6 +81,7 @@ MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
        .boot_params    = 0x00000100,
        .init_machine   = rd78x00_masa_init,
        .map_io         = mv78xx0_map_io,
+        .init_early     = mv78xx0_init_early,
        .init_irq       = mv78xx0_init_irq,
        .timer          = &mv78xx0_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 0717f887cba0..340809a7d233 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -94,6 +94,7 @@ config MACH_MX31_3DS
        select MXC_DEBUG_BOARD
        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_KEYPAD
        select IMX_HAVE_PLATFORM_IMX_UART
        select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -183,6 +184,7 @@ config MACH_MX35_3DS
        select MXC_DEBUG_BOARD
        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_UART
        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_NAND
@@ -199,6 +201,15 @@ config MACH_KZM_ARM11_01
          Include support for KZM-ARM11-01. This includes specific
          configurations for the board and its peripherals.
+config MACH_BUG
+        bool "Support Buglabs BUGBase platform"
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_IMX_UART
+        default y
+        help
+          Include support for BUGBase 1.3 platform. This includes specific
+          configurations for the board and its peripherals.
 config MACH_EUKREA_CPUIMX35
        bool "Support Eukrea CPUIMX35 Platform"
        select SOC_IMX35
@@ -229,4 +240,18 @@ config MACH_EUKREA_MBIMXSD35_BASEBOARD
 endchoice
+config MACH_VPR200
+        bool "Support VPR200 platform"
+        select SOC_IMX35
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        help
+          Include support for VPR200 platform. This includes specific
+          configurations for the board and its peripherals.
 endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 8db13294ad27..a54faf2cf5fa 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -5,8 +5,8 @@
 # Object file lists.
 obj-y                           := mm.o devices.o cpu.o
-obj-$(CONFIG_SOC_IMX31)         += clock-imx31.o iomux-imx31.o
+obj-$(CONFIG_SOC_IMX31)         += clock-imx31.o iomux-imx31.o ehci-imx31.o
-obj-$(CONFIG_SOC_IMX35)         += clock-imx35.o
+obj-$(CONFIG_SOC_IMX35)         += clock-imx35.o ehci-imx35.o
 obj-$(CONFIG_MACH_MX31ADS)      += mach-mx31ads.o
 obj-$(CONFIG_MACH_MX31LILLY)    += mach-mx31lilly.o mx31lilly-db.o
 obj-$(CONFIG_MACH_MX31LITE)     += mach-mx31lite.o mx31lite-db.o
@@ -20,5 +20,7 @@ obj-$(CONFIG_MACH_PCM043)	+= mach-pcm043.o
 obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
 obj-$(CONFIG_MACH_MX35_3DS)     += mach-mx35_3ds.o
 obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
+obj-$(CONFIG_MACH_BUG)          += mach-bug.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX35)      += mach-cpuimx35.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD)   += eukrea_mbimxsd-baseboard.o
+obj-$(CONFIG_MACH_VPR200)       += mach-vpr200.o
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index 677b18aa7ae6..d545d86cc202 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -35,7 +35,7 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
 #define imx35_add_imx_i2c2(pdata)       imx35_add_imx_i2c(2, pdata)
 extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
-#define imx31_add_imx_keypad(pdata)     \
+#define imx35_add_imx_keypad(pdata)     \
        imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
 extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
diff --git a/arch/arm/mach-mx3/ehci-imx31.c b/arch/arm/mach-mx3/ehci-imx31.c
new file mode 100644
index 000000000000..314a983ac614
--- /dev/null
+++ b/arch/arm/mach-mx3/ehci-imx31.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+#define USBCTRL_OTGBASE_OFFSET  0x600
+#define MX31_OTG_SIC_SHIFT      29
+#define MX31_OTG_SIC_MASK       (0x3 << MX31_OTG_SIC_SHIFT)
+#define MX31_OTG_PM_BIT         (1 << 24)
+#define MX31_H2_SIC_SHIFT       21
+#define MX31_H2_SIC_MASK        (0x3 << MX31_H2_SIC_SHIFT)
+#define MX31_H2_PM_BIT          (1 << 16)
+#define MX31_H2_DT_BIT          (1 << 5)
+#define MX31_H1_SIC_SHIFT       13
+#define MX31_H1_SIC_MASK        (0x3 << MX31_H1_SIC_SHIFT)
+#define MX31_H1_PM_BIT          (1 << 8)
+#define MX31_H1_DT_BIT          (1 << 4)
+int mx31_initialize_usb_hw(int port, unsigned int flags)
+{
+        unsigned int v;
+        v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+        switch (port) {
+        case 0: /* OTG port */
+                v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX31_OTG_PM_BIT;
+                break;
+        case 1: /* H1 port */
+                v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX31_H1_PM_BIT;
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX31_H1_DT_BIT;
+                break;
+        case 2: /* H2 port */
+                v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX31_H2_PM_BIT;
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX31_H2_DT_BIT;
+                break;
+        default:
+                return -EINVAL;
+        }
+        writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+        return 0;
+}
diff --git a/arch/arm/mach-mx3/ehci-imx35.c b/arch/arm/mach-mx3/ehci-imx35.c
new file mode 100644
index 000000000000..33983a478c6b
--- /dev/null
+++ b/arch/arm/mach-mx3/ehci-imx35.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+#define USBCTRL_OTGBASE_OFFSET  0x600
+#define MX35_OTG_SIC_SHIFT      29
+#define MX35_OTG_SIC_MASK       (0x3 << MX35_OTG_SIC_SHIFT)
+#define MX35_OTG_PM_BIT         (1 << 24)
+#define MX35_H1_SIC_SHIFT       21
+#define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PM_BIT          (1 << 8)
+#define MX35_H1_IPPUE_UP_BIT    (1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
+#define MX35_H1_TLL_BIT         (1 << 5)
+#define MX35_H1_USBTE_BIT       (1 << 4)
+int mx35_initialize_usb_hw(int port, unsigned int flags)
+{
+        unsigned int v;
+        v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+        switch (port) {
+        case 0: /* OTG port */
+                v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX35_OTG_PM_BIT;
+                break;
+        case 1: /* H1 port */
+                v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+                        MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX35_H1_PM_BIT;
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX35_H1_TLL_BIT;
+                if (flags & MXC_EHCI_INTERNAL_PHY)
+                        v |= MX35_H1_USBTE_BIT;
+                if (flags & MXC_EHCI_IPPUE_DOWN)
+                        v |= MX35_H1_IPPUE_DOWN_BIT;
+                if (flags & MXC_EHCI_IPPUE_UP)
+                        v |= MX35_H1_IPPUE_UP_BIT;
+                break;
+        default:
+                return -EINVAL;
+        }
+        writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+        return 0;
+}
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index 14a5ffc939ad..80761474c0f8 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -165,8 +165,8 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
        MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 };
-#define GPIO_LED1       (2 * 32 + 29)
+#define GPIO_LED1       IMX_GPIO_NR(3, 29)
-#define GPIO_SWITCH1    (2 * 32 + 25)
+#define GPIO_SWITCH1    IMX_GPIO_NR(3, 25)
 #define GPIO_LCDPWR     (4)
 static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
diff --git a/arch/arm/mach-mx3/iomux-imx31.c b/arch/arm/mach-mx3/iomux-imx31.c
index a1d7fa5123dc..cf8f8099ebd7 100644
--- a/arch/arm/mach-mx3/iomux-imx31.c
+++ b/arch/arm/mach-mx3/iomux-imx31.c
@@ -97,7 +97,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad);
 *      - reserves the pin so that it is not claimed by another driver
 *      - setups the iomux according to the configuration
 */
-int mxc_iomux_alloc_pin(const unsigned int pin, const char *label)
+int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
 {
        unsigned pad = pin & IOMUX_PADNUM_MASK;
@@ -118,10 +118,10 @@ int mxc_iomux_alloc_pin(const unsigned int pin, const char *label)
 }
 EXPORT_SYMBOL(mxc_iomux_alloc_pin);
-int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
                const char *label)
 {
-        unsigned int *p = pin_list;
+        const unsigned int *p = pin_list;
        int i;
        int ret = -EINVAL;
@@ -139,7 +139,7 @@ setup_error:
 }
 EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
-void mxc_iomux_release_pin(const unsigned int pin)
+void mxc_iomux_release_pin(unsigned int pin)
 {
        unsigned pad = pin & IOMUX_PADNUM_MASK;
@@ -148,9 +148,9 @@ void mxc_iomux_release_pin(const unsigned int pin)
 }
 EXPORT_SYMBOL(mxc_iomux_release_pin);
-void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
+void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
 {
-        unsigned int *p = pin_list;
+        const unsigned int *p = pin_list;
        int i;
        for (i = 0; i < count; i++) {
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 28b6f414b5d5..226829bf7c25 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -133,7 +133,6 @@ static int armadillo5x0_pins[] = {
 };
 /* USB */
-#if defined(CONFIG_USB_ULPI)
 #define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
 #define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
@@ -176,8 +175,10 @@ static int usbotg_init(struct platform_device *pdev)
        gpio_set_value(OTG_RESET, 0/*LOW*/);
        mdelay(5);
        gpio_set_value(OTG_RESET, 1/*HIGH*/);
+        mdelay(10);
-        return 0;
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_DIFF_UNI);
 otg_free_reset:
        gpio_free(OTG_RESET);
@@ -233,8 +234,10 @@ static int usbh2_init(struct platform_device *pdev)
        gpio_set_value(USBH2_RESET, 0/*LOW*/);
        mdelay(5);
        gpio_set_value(USBH2_RESET, 1/*HIGH*/);
+        mdelay(10);
-        return 0;
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_DIFF_UNI);
 h2_free_reset:
        gpio_free(USBH2_RESET);
@@ -246,15 +249,12 @@ h2_free_cs:
 static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
        .init   = usbotg_init,
        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
        .init   = usbh2_init,
        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
 };
-#endif /* CONFIG_USB_ULPI */
 /* RTC over I2C*/
 #define ARMADILLO5X0_RTC_GPIO   IOMUX_TO_GPIO(MX31_PIN_SRXD4)
@@ -547,15 +547,15 @@ static void __init armadillo5x0_init(void)
        i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
        /* USB */
-#if defined(CONFIG_USB_ULPI)
-        usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+        usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                        ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                        ULPI_OTG_DRVVBUS_EXT);
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+        if (usbotg_pdata.otg)
-                        ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                imx31_add_mxc_ehci_otg(&usbotg_pdata);
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-        imx31_add_mxc_ehci_otg(&usbotg_pdata);
+                        ULPI_OTG_DRVVBUS_EXT);
-        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+        if (usbh2_pdata.otg)
-#endif
+                imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 }
 static void __init armadillo5x0_timer_init(void)
@@ -569,9 +569,10 @@ static struct sys_timer armadillo5x0_timer = {
 MACHINE_START(ARMADILLO5X0, "Armadillo-500")
        /* Maintainer: Alberto Panizzo  */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_map_io,
+        .map_io = mx31_map_io,
-        .init_irq       = mx31_init_irq,
+        .init_early = imx31_init_early,
-        .timer          = &armadillo5x0_timer,
+        .init_irq = mx31_init_irq,
-        .init_machine   = armadillo5x0_init,
+        .timer = &armadillo5x0_timer,
+        .init_machine = armadillo5x0_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-bug.c b/arch/arm/mach-mx3/mach-bug.c
new file mode 100644
index 000000000000..d137d7078ee9
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-bug.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <mach/iomux-mx3.h>
+#include <mach/imx-uart.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include "devices-imx31.h"
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+static const unsigned int bug_pins[] __initconst = {
+        MX31_PIN_PC_RST__CTS5,
+        MX31_PIN_PC_VS2__RTS5,
+        MX31_PIN_PC_BVD2__TXD5,
+        MX31_PIN_PC_BVD1__RXD5,
+};
+static void __init bug_board_init(void)
+{
+        mxc_iomux_setup_multiple_pins(bug_pins,
+                                      ARRAY_SIZE(bug_pins), "uart-4");
+        imx31_add_imx_uart4(&uart_pdata);
+}
+static void __init bug_timer_init(void)
+{
+        mx31_clocks_init(26000000);
+}
+static struct sys_timer bug_timer = {
+        .init = bug_timer_init,
+};
+MACHINE_START(BUG, "BugLabs BUGBase")
+        .map_io = mx31_map_io,
+        .init_early = imx31_init_early,
+        .init_irq = mx31_init_irq,
+        .timer = &bug_timer,
+        .init_machine = bug_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 26ae90f02582..ec63d998f647 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -60,7 +60,7 @@ static struct tsc2007_platform_data tsc2007_info = {
        .x_plate_ohms           = 180,
 };
-#define TSC2007_IRQGPIO         (2 * 32 + 2)
+#define TSC2007_IRQGPIO         IMX_GPIO_NR(3, 2)
 static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
        {
                I2C_BOARD_INFO("pcf8563", 0x51),
@@ -111,15 +111,25 @@ static const struct mxc_nand_platform_data
        .flash_bbt      = 1,
 };
+static int eukrea_cpuimx35_otg_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
 static const struct mxc_usbh_platform_data otg_pdata __initconst = {
+        .init   = eukrea_cpuimx35_otg_init,
        .portsc = MXC_EHCI_MODE_UTMI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
+                        MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
+}
 static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
+        .init   = eukrea_cpuimx35_usbh1_init,
        .portsc = MXC_EHCI_MODE_SERIAL,
-        .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
-                  MXC_EHCI_IPPUE_DOWN,
 };
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -146,7 +156,7 @@ __setup("otg_mode=", eukrea_cpuimx35_otg_mode);
 /*
 * Board specific initialization.
 */
-static void __init mxc_board_init(void)
+static void __init eukrea_cpuimx35_init(void)
 {
        mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
                        ARRAY_SIZE(eukrea_cpuimx35_pads));
@@ -184,9 +194,10 @@ struct sys_timer eukrea_cpuimx35_timer = {
 MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
        /* Maintainer: Eukrea Electromatique */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx35_map_io,
+        .map_io = mx35_map_io,
-        .init_irq       = mx35_init_irq,
+        .init_early = imx35_init_early,
-        .init_machine   = mxc_board_init,
+        .init_irq = mx35_init_irq,
-        .timer          = &eukrea_cpuimx35_timer,
+        .timer = &eukrea_cpuimx35_timer,
+        .init_machine = eukrea_cpuimx35_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index a5f3eb24e4d5..d3cc7393a6b1 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -266,17 +266,14 @@ static void __init kzm_timer_init(void)
 }
 static struct sys_timer kzm_timer = {
-        .init   = kzm_timer_init,
+        .init = kzm_timer_init,
 };
-/*
- * The following uses standard kernel macros define in arch.h in order to
- * initialize __mach_desc_KZM_ARM11_01 data structure.
- */
 MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = kzm_map_io,
+        .map_io = kzm_map_io,
-        .init_irq       = mx31_init_irq,
+        .init_early = imx31_init_early,
-        .init_machine   = kzm_board_init,
+        .init_irq = mx31_init_irq,
-        .timer          = &kzm_timer,
+        .timer = &kzm_timer,
+        .init_machine = kzm_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 0d65db885be7..544d3e414f58 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -21,9 +21,13 @@
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/l4f00242t03.h>
 #include <linux/regulator/machine.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
+#include <linux/memblock.h>
+#include <media/soc_camera.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -35,6 +39,10 @@
 #include <mach/iomux-mx3.h>
 #include <mach/3ds_debugboard.h>
 #include <mach/ulpi.h>
+#include <mach/mmc.h>
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include <mach/mx3_camera.h>
 #include "devices-imx31.h"
 #include "devices.h"
@@ -42,10 +50,6 @@
 /* CPLD IRQ line for external uart, external ethernet etc */
 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
-/*
- * This file contains the board-specific initialization routines.
- */
 static int mx31_3ds_pins[] = {
        /* UART1 */
        MX31_PIN_CTS1__CTS1,
@@ -53,6 +57,12 @@ static int mx31_3ds_pins[] = {
        MX31_PIN_TXD1__TXD1,
        MX31_PIN_RXD1__RXD1,
        IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
+        /*SPI0*/
+        MX31_PIN_CSPI1_SCLK__SCLK,
+        MX31_PIN_CSPI1_MOSI__MOSI,
+        MX31_PIN_CSPI1_MISO__MISO,
+        MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
        /* SPI 1 */
        MX31_PIN_CSPI2_SCLK__SCLK,
        MX31_PIN_CSPI2_MOSI__MOSI,
@@ -100,6 +110,252 @@ static int mx31_3ds_pins[] = {
        IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
        /* USB Host2 reset */
        IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
+        /* I2C1 */
+        MX31_PIN_I2C_CLK__I2C1_SCL,
+        MX31_PIN_I2C_DAT__I2C1_SDA,
+        /* SDHC1 */
+        MX31_PIN_SD1_DATA3__SD1_DATA3,
+        MX31_PIN_SD1_DATA2__SD1_DATA2,
+        MX31_PIN_SD1_DATA1__SD1_DATA1,
+        MX31_PIN_SD1_DATA0__SD1_DATA0,
+        MX31_PIN_SD1_CLK__SD1_CLK,
+        MX31_PIN_SD1_CMD__SD1_CMD,
+        MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
+        MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
+        /* Framebuffer */
+        MX31_PIN_LD0__LD0,
+        MX31_PIN_LD1__LD1,
+        MX31_PIN_LD2__LD2,
+        MX31_PIN_LD3__LD3,
+        MX31_PIN_LD4__LD4,
+        MX31_PIN_LD5__LD5,
+        MX31_PIN_LD6__LD6,
+        MX31_PIN_LD7__LD7,
+        MX31_PIN_LD8__LD8,
+        MX31_PIN_LD9__LD9,
+        MX31_PIN_LD10__LD10,
+        MX31_PIN_LD11__LD11,
+        MX31_PIN_LD12__LD12,
+        MX31_PIN_LD13__LD13,
+        MX31_PIN_LD14__LD14,
+        MX31_PIN_LD15__LD15,
+        MX31_PIN_LD16__LD16,
+        MX31_PIN_LD17__LD17,
+        MX31_PIN_VSYNC3__VSYNC3,
+        MX31_PIN_HSYNC__HSYNC,
+        MX31_PIN_FPSHIFT__FPSHIFT,
+        MX31_PIN_CONTRAST__CONTRAST,
+        /* CSI */
+        MX31_PIN_CSI_D6__CSI_D6,
+        MX31_PIN_CSI_D7__CSI_D7,
+        MX31_PIN_CSI_D8__CSI_D8,
+        MX31_PIN_CSI_D9__CSI_D9,
+        MX31_PIN_CSI_D10__CSI_D10,
+        MX31_PIN_CSI_D11__CSI_D11,
+        MX31_PIN_CSI_D12__CSI_D12,
+        MX31_PIN_CSI_D13__CSI_D13,
+        MX31_PIN_CSI_D14__CSI_D14,
+        MX31_PIN_CSI_D15__CSI_D15,
+        MX31_PIN_CSI_HSYNC__CSI_HSYNC,
+        MX31_PIN_CSI_MCLK__CSI_MCLK,
+        MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
+        MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+        MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
+        IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
+};
+/*
+ * Camera support
+ */
+static phys_addr_t mx3_camera_base __initdata;
+#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
+#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
+#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
+static struct gpio mx31_3ds_camera_gpios[] = {
+        { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
+        { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
+};
+static int __init mx31_3ds_camera_alloc_dma(void)
+{
+        int dma;
+        if (!mx3_camera_base)
+                return -ENOMEM;
+        dma = dma_declare_coherent_memory(&mx3_camera.dev,
+                                        mx3_camera_base, mx3_camera_base,
+                                        MX31_3DS_CAMERA_BUF_SIZE,
+                                        DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                return -ENOMEM;
+        return 0;
+}
+static int mx31_3ds_camera_power(struct device *dev, int on)
+{
+        /* enable or disable the camera */
+        pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
+        gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
+        if (!on)
+                goto out;
+        /* If enabled, give a reset impulse */
+        gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
+        msleep(20);
+        gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
+        msleep(100);
+out:
+        return 0;
+}
+static struct i2c_board_info mx31_3ds_i2c_camera = {
+        I2C_BOARD_INFO("ov2640", 0x30),
+};
+static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
+        { .supply = "cmos_vcore" },
+        { .supply = "cmos_2v8" },
+};
+static struct soc_camera_link iclink_ov2640 = {
+        .bus_id         = 0,
+        .board_info     = &mx31_3ds_i2c_camera,
+        .i2c_adapter_id = 0,
+        .power          = mx31_3ds_camera_power,
+        .regulators     = mx31_3ds_camera_regs,
+        .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
+};
+static struct platform_device mx31_3ds_ov2640 = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &iclink_ov2640,
+        },
+};
+struct mx3_camera_pdata mx31_3ds_camera_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .flags          = MX3_CAMERA_DATAWIDTH_10,
+        .mclk_10khz     = 2600,
+};
+/*
+ * FB support
+ */
+static const struct fb_videomode fb_modedb[] = {
+        {       /* 480x640 @ 60 Hz */
+                .name           = "Epson-VGA",
+                .refresh        = 60,
+                .xres           = 480,
+                .yres           = 640,
+                .pixclock       = 41701,
+                .left_margin    = 20,
+                .right_margin   = 41,
+                .upper_margin   = 10,
+                .lower_margin   = 5,
+                .hsync_len      = 20,
+                .vsync_len      = 10,
+                .sync           = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        },
+};
+static struct ipu_platform_data mx3_ipu_data = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+static struct mx3fb_platform_data mx3fb_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .name           = "Epson-VGA",
+        .mode           = fb_modedb,
+        .num_modes      = ARRAY_SIZE(fb_modedb),
+};
+/* LCD */
+static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
+        .reset_gpio             = IOMUX_TO_GPIO(MX31_PIN_LCS1),
+        .data_enable_gpio       = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
+        .core_supply            = "lcd_2v8",
+        .io_supply              = "vdd_lcdio",
+};
+/*
+ * Support for SD card slot in personality board
+ */
+#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
+#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
+static struct gpio mx31_3ds_sdhc1_gpios[] = {
+        { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
+        { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
+};
+static int mx31_3ds_sdhc1_init(struct device *dev,
+                               irq_handler_t detect_irq,
+                               void *data)
+{
+        int ret;
+        ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
+                                 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
+        if (ret) {
+                pr_warning("Unable to request the SD/MMC GPIOs.\n");
+                return ret;
+        }
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+                          detect_irq, IRQF_DISABLED |
+                          IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+                          "sdhc1-detect", data);
+        if (ret) {
+                pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
+                goto gpio_free;
+        }
+        return 0;
+gpio_free:
+        gpio_free_array(mx31_3ds_sdhc1_gpios,
+                        ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
+        return ret;
+}
+static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
+{
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
+        gpio_free_array(mx31_3ds_sdhc1_gpios,
+                         ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
+}
+static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
+{
+        /*
+         * While the voltage stuff is done by the driver, activate the
+         * Buffer Enable Pin only if there is a card in slot to fix the card
+         * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
+         * Done here because at this stage we have for sure a debounced value
+         * of the presence of the card, showed by the value of vdd.
+         * 7 == ilog2(MMC_VDD_165_195)
+         */
+        if (vdd > 7)
+                gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
+        else
+                gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
+}
+static struct imxmmc_platform_data sdhc1_pdata = {
+        .init           = mx31_3ds_sdhc1_init,
+        .exit           = mx31_3ds_sdhc1_exit,
+        .setpower       = mx31_3ds_sdhc1_setpower,
 };
 /*
@@ -138,7 +394,71 @@ static struct regulator_init_data gpo_init = {
        }
 };
-static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
+static struct regulator_consumer_supply vmmc2_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
+};
+static struct regulator_init_data vmmc2_init = {
+        .constraints = {
+                .min_uV = 3000000,
+                .max_uV = 3000000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
+        .consumer_supplies = vmmc2_consumers,
+};
+static struct regulator_consumer_supply vmmc1_consumers[] = {
+        REGULATOR_SUPPLY("lcd_2v8", NULL),
+        REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
+};
+static struct regulator_init_data vmmc1_init = {
+        .constraints = {
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+                .apply_uV = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
+        .consumer_supplies = vmmc1_consumers,
+};
+static struct regulator_consumer_supply vgen_consumers[] = {
+        REGULATOR_SUPPLY("vdd_lcdio", NULL),
+};
+static struct regulator_init_data vgen_init = {
+        .constraints = {
+                .min_uV = 1800000,
+                .max_uV = 1800000,
+                .apply_uV = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
+        .consumer_supplies = vgen_consumers,
+};
+static struct regulator_consumer_supply vvib_consumers[] = {
+        REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
+};
+static struct regulator_init_data vvib_init = {
+        .constraints = {
+                .min_uV = 1300000,
+                .max_uV = 1300000,
+                .apply_uV = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
+        .consumer_supplies = vvib_consumers,
+};
+static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
        {
                .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
                .init_data = &pwgtx_init,
@@ -152,17 +472,38 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
        }, {
                .id = MC13783_REG_GPO3, /* Turn on 3.3V */
                .init_data = &gpo_init,
+        }, {
+                .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
+                .init_data = &vmmc2_init,
+        }, {
+                .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
+                .init_data = &vmmc1_init,
+        }, {
+                .id = MC13783_REG_VGEN,  /* Power LCD */
+                .init_data = &vgen_init,
+        }, {
+                .id = MC13783_REG_VVIB,  /* Power CMOS */
+                .init_data = &vvib_init,
        },
 };
 /* MC13783 */
-static struct mc13783_platform_data mc13783_pdata __initdata = {
+static struct mc13xxx_platform_data mc13783_pdata __initdata = {
        .regulators = mx31_3ds_regulators,
        .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
-        .flags  = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN,
+        .flags  = MC13XXX_USE_REGULATOR | MC13XXX_USE_TOUCHSCREEN
 };
 /* SPI */
+static int spi0_internal_chipselect[] = {
+        MXC_SPI_CS(2),
+};
+static const struct spi_imx_master spi0_pdata __initconst = {
+        .chipselect     = spi0_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
+};
 static int spi1_internal_chipselect[] = {
        MXC_SPI_CS(0),
        MXC_SPI_CS(2),
@@ -182,6 +523,12 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
                .platform_data  = &mc13783_pdata,
                .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
                .mode = SPI_CS_HIGH,
+        }, {
+                .modalias       = "l4f00242t03",
+                .max_speed_hz   = 5000000,
+                .bus_num        = 0,
+                .chip_select    = 0, /* SS2 */
+                .platform_data  = &mx31_3ds_l4f00242t03_pdata,
        },
 };
@@ -245,6 +592,11 @@ usbotg_free_reset:
        return err;
 }
+static int mx31_3ds_otg_init(struct platform_device *pdev)
+{
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
 static int mx31_3ds_host2_init(struct platform_device *pdev)
 {
        int err;
@@ -276,25 +628,25 @@ static int mx31_3ds_host2_init(struct platform_device *pdev)
        mdelay(1);
        gpio_set_value(USBH2_RST_B, 1);
-        return 0;
+        mdelay(10);
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
 usbotg_free_reset:
        gpio_free(USBH2_RST_B);
        return err;
 }
-#if defined(CONFIG_USB_ULPI)
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = mx31_3ds_otg_init,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
        .init = mx31_3ds_host2_init,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
-#endif
 static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
        .operating_mode = FSL_USB2_DR_DEVICE,
@@ -320,19 +672,18 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
-/*
+static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
- * Set up static virtual mappings.
+        .bitrate = 100000,
- */
+};
-static void __init mx31_3ds_map_io(void)
-{
-        mx31_map_io();
-}
-/*!
+static struct platform_device *devices[] __initdata = {
- * Board specific initialization.
+        &mx31_3ds_ov2640,
- */
+};
-static void __init mxc_board_init(void)
+static void __init mx31_3ds_init(void)
 {
+        int ret;
        mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
                                      "mx31_3ds");
@@ -343,20 +694,22 @@ static void __init mxc_board_init(void)
        spi_register_board_info(mx31_3ds_spi_devs,
                                                ARRAY_SIZE(mx31_3ds_spi_devs));
+        platform_add_devices(devices, ARRAY_SIZE(devices));
        imx31_add_imx_keypad(&mx31_3ds_keymap_data);
        mx31_3ds_usbotg_init();
-#if defined(CONFIG_USB_ULPI)
        if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                                ULPI_OTG_DRVVBUS_EXT);
+                if (otg_pdata.otg)
-                imx31_add_mxc_ehci_otg(&otg_pdata);
+                        imx31_add_mxc_ehci_otg(&otg_pdata);
        }
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                        ULPI_OTG_DRVVBUS_EXT);
-        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+        if (usbh2_pdata.otg)
-#endif
+                imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
        if (!otg_mode_host)
                imx31_add_fsl_usb2_udc(&usbotg_pdata);
@@ -364,6 +717,26 @@ static void __init mxc_board_init(void)
                printk(KERN_WARNING "Init of the debug board failed, all "
                                    "devices on the debug board are unusable.\n");
        imx31_add_imx2_wdt(NULL);
+        imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
+        imx31_add_mxc_mmc(0, &sdhc1_pdata);
+        imx31_add_spi_imx0(&spi0_pdata);
+        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+        /* CSI */
+        /* Camera power: default - off */
+        ret = gpio_request_array(mx31_3ds_camera_gpios,
+                                 ARRAY_SIZE(mx31_3ds_camera_gpios));
+        if (ret) {
+                pr_err("Failed to request camera gpios");
+                iclink_ov2640.power = NULL;
+        }
+        if (!mx31_3ds_camera_alloc_dma())
+                mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata);
+        else
+                pr_err("Failed to allocate dma memory for camera");
 }
 static void __init mx31_3ds_timer_init(void)
@@ -375,15 +748,22 @@ static struct sys_timer mx31_3ds_timer = {
        .init   = mx31_3ds_timer_init,
 };
-/*
+static void __init mx31_3ds_reserve(void)
- * The following uses standard kernel macros defined in arch.h in order to
+{
- * initialize __mach_desc_MX31_3DS data structure.
+        /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
- */
+        mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
+                                         MX31_3DS_CAMERA_BUF_SIZE);
+        memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
+        memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
+}
 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
        /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_3ds_map_io,
+        .map_io = mx31_map_io,
-        .init_irq       = mx31_init_irq,
+        .init_early = imx31_init_early,
-        .init_machine   = mxc_board_init,
+        .init_irq = mx31_init_irq,
-        .timer          = &mx31_3ds_timer,
+        .timer = &mx31_3ds_timer,
+        .init_machine = mx31_3ds_init,
+        .reserve = mx31_3ds_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 88b97d62b57e..4e4b780c481d 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -69,12 +69,8 @@
 #define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
 #define MXC_MAX_EXP_IO_LINES    16
-/*
- * This file contains the board-specific initialization routines.
- */
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+/*
-/*!
 * The serial port definition structure.
 */
 static struct plat_serial8250_port serial_platform_data[] = {
@@ -110,14 +106,7 @@ static int __init mxc_init_extuart(void)
 {
        return platform_device_register(&serial_device);
 }
-#else
-static inline int mxc_init_extuart(void)
-{
-        return 0;
-}
-#endif
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -134,11 +123,6 @@ static inline void mxc_init_imx_uart(void)
        mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
        imx31_add_imx_uart0(&uart_pdata);
 }
-#else /* !SERIAL_IMX */
-static inline void mxc_init_imx_uart(void)
-{
-}
-#endif /* !SERIAL_IMX */
 static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
 {
@@ -160,7 +144,7 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
 /*
 * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param irq           an expio virtual irq number
+ * @param d     an expio virtual irq description
 */
 static void expio_mask_irq(struct irq_data *d)
 {
@@ -172,7 +156,7 @@ static void expio_mask_irq(struct irq_data *d)
 /*
 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param irq           an expanded io virtual irq number
+ * @param d     an expio virtual irq description
 */
 static void expio_ack_irq(struct irq_data *d)
 {
@@ -183,7 +167,7 @@ static void expio_ack_irq(struct irq_data *d)
 /*
 * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param irq           a expio virtual irq number
+ * @param d     an expio virtual irq description
 */
 static void expio_unmask_irq(struct irq_data *d)
 {
@@ -476,7 +460,6 @@ static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
 };
 #endif
-#if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
 static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
        {
@@ -497,11 +480,6 @@ static void mxc_init_i2c(void)
        imx31_add_imx_i2c1(NULL);
 }
-#else
-static void mxc_init_i2c(void)
-{
-}
-#endif
 static unsigned int ssi_pins[] = {
        MX31_PIN_SFS5__SFS5,
@@ -516,9 +494,7 @@ static void mxc_init_audio(void)
        mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 }
-/*!
+/* static mappings */
- * This structure defines static mappings for the i.MX31ADS board.
- */
 static struct map_desc mx31ads_io_desc[] __initdata = {
        {
                .virtual        = MX31_CS4_BASE_ADDR_VIRT,
@@ -528,9 +504,6 @@ static struct map_desc mx31ads_io_desc[] __initdata = {
        },
 };
-/*!
- * Set up static virtual mappings.
- */
 static void __init mx31ads_map_io(void)
 {
        mx31_map_io();
@@ -543,10 +516,7 @@ static void __init mx31ads_init_irq(void)
        mx31ads_init_expio();
 }
-/*!
+static void __init mx31ads_init(void)
- * Board specific initialization.
- */
-static void __init mxc_board_init(void)
 {
        mxc_init_extuart();
        mxc_init_imx_uart();
@@ -563,15 +533,12 @@ static struct sys_timer mx31ads_timer = {
        .init   = mx31ads_timer_init,
 };
-/*
- * The following uses standard kernel macros defined in arch.h in order to
- * initialize __mach_desc_MX31ADS data structure.
- */
 MACHINE_START(MX31ADS, "Freescale MX31ADS")
        /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31ads_map_io,
+        .map_io = mx31ads_map_io,
-        .init_irq       = mx31ads_init_irq,
+        .init_early = imx31_init_early,
-        .init_machine   = mxc_board_init,
+        .init_irq = mx31ads_init_irq,
-        .timer          = &mx31ads_timer,
+        .timer = &mx31ads_timer,
+        .init_machine = mx31ads_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 2c595483f356..ed95745163b8 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -24,6 +24,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/gpio.h>
+#include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/smsc911x.h>
@@ -110,55 +111,9 @@ static struct platform_device physmap_flash_device = {
 /* USB */
-#if defined(CONFIG_USB_ULPI)
 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-static int usbotg_init(struct platform_device *pdev)
-{
-        unsigned int pins[] = {
-                MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
-                MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
-                MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
-                MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
-                MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
-                MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
-                MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
-                MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
-                MX31_PIN_USBOTG_CLK__USBOTG_CLK,
-                MX31_PIN_USBOTG_DIR__USBOTG_DIR,
-                MX31_PIN_USBOTG_NXT__USBOTG_NXT,
-                MX31_PIN_USBOTG_STP__USBOTG_STP,
-        };
-        mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG");
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
-        mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true);
-        mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true);
-        /* chip select */
-        mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO),
-                                "USBOTG_CS");
-        gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS");
-        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0);
-        return 0;
-}
 static int usbh1_init(struct platform_device *pdev)
 {
        int pins[] = {
@@ -183,7 +138,10 @@ static int usbh1_init(struct platform_device *pdev)
        mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
-        return 0;
+        mdelay(10);
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_SINGLE_UNI);
 }
 static int usbh2_init(struct platform_device *pdev)
@@ -220,41 +178,30 @@ static int usbh2_init(struct platform_device *pdev)
        gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
-        return 0;
+        mdelay(10);
-}
-static struct mxc_usbh_platform_data usbotg_pdata = {
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-        .init   = usbotg_init,
+}
-        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
-};
 static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
        .init   = usbh1_init,
        .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
 };
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
        .init   = usbh2_init,
        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
 static void lilly1131_usb_init(void)
 {
-        usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
        imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
-        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-}
-#else
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-static inline void lilly1131_usb_init(void) {}
+                        ULPI_OTG_DRVVBUS_EXT);
-#endif /* CONFIG_USB_ULPI */
+        if (usbh2_pdata.otg)
+                imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+}
 /* SPI */
@@ -274,8 +221,8 @@ static const struct spi_imx_master spi1_pdata __initconst = {
        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
-static struct mc13783_platform_data mc13783_pdata __initdata = {
+static struct mc13xxx_platform_data mc13783_pdata __initdata = {
-        .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN,
+        .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
 };
 static struct spi_board_info mc13783_dev __initdata = {
@@ -347,10 +294,10 @@ static struct sys_timer mx31lilly_timer = {
 };
 MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_map_io,
+        .map_io = mx31_map_io,
-        .init_irq       = mx31_init_irq,
+        .init_early = imx31_init_early,
-        .init_machine   = mx31lilly_board_init,
+        .init_irq = mx31_init_irq,
-        .timer          = &mx31lilly_timer,
+        .timer = &mx31lilly_timer,
+        .init_machine = mx31lilly_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 9e64c66396e0..24a21a384bf1 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -27,6 +27,7 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <linux/mtd/physmap.h>
+#include <linux/delay.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -111,9 +112,9 @@ static const struct spi_imx_master spi1_pdata __initconst = {
        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
-static struct mc13783_platform_data mc13783_pdata __initdata = {
+static struct mc13xxx_platform_data mc13783_pdata __initdata = {
-        .flags  = MC13783_USE_RTC |
+        .flags  = MC13XXX_USE_RTC |
-                  MC13783_USE_REGULATOR,
+                  MC13XXX_USE_REGULATOR,
 };
 static struct spi_board_info mc13783_spi_dev __initdata = {
@@ -129,7 +130,6 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
 * USB
 */
-#if defined(CONFIG_USB_ULPI)
 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
@@ -167,15 +167,15 @@ static int usbh2_init(struct platform_device *pdev)
        gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
-        return 0;
+        mdelay(10);
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
 }
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
        .init   = usbh2_init,
        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
-#endif
 /*
 * NOR flash
@@ -227,7 +227,7 @@ void __init mx31lite_map_io(void)
 static int mx31lite_baseboard;
 core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
-static void __init mxc_board_init(void)
+static void __init mx31lite_init(void)
 {
        int ret;
@@ -252,13 +252,11 @@ static void __init mxc_board_init(void)
        imx31_add_spi_imx1(&spi1_pdata);
        spi_register_board_info(&mc13783_spi_dev, 1);
-#if defined(CONFIG_USB_ULPI)
        /* USB */
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (usbh2_pdata.otg)
-        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+                imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
        /* SMSC9117 IRQ pin */
        ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
@@ -281,9 +279,10 @@ struct sys_timer mx31lite_timer = {
 MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
        /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31lite_map_io,
+        .map_io = mx31lite_map_io,
-        .init_irq       = mx31_init_irq,
+        .init_early = imx31_init_early,
-        .init_machine   = mxc_board_init,
+        .init_irq = mx31_init_irq,
-        .timer          = &mx31lite_timer,
+        .timer = &mx31lite_timer,
+        .init_machine = mx31lite_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 1aa8d65fccbb..6f3692bccb8a 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -214,7 +214,7 @@ static struct regulator_init_data cam_vreg_data = {
        .consumer_supplies = cam_consumers,
 };
-static struct mc13783_regulator_init_data moboard_regulators[] = {
+static struct mc13xxx_regulator_init_data moboard_regulators[] = {
        {
                .id = MC13783_REG_VMMC1,
                .init_data = &sdhc_vreg_data,
@@ -267,12 +267,12 @@ static struct mc13783_leds_platform_data moboard_leds = {
        .tc2_period = MC13783_LED_PERIOD_10MS,
 };
-static struct mc13783_platform_data moboard_pmic = {
+static struct mc13xxx_platform_data moboard_pmic = {
        .regulators = moboard_regulators,
        .num_regulators = ARRAY_SIZE(moboard_regulators),
        .leds = &moboard_leds,
-        .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC |
+        .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_RTC |
-                MC13783_USE_ADC | MC13783_USE_LED,
+                MC13XXX_USE_ADC | MC13XXX_USE_LED,
 };
 static struct spi_board_info moboard_spi_board_info[] __initdata = {
@@ -400,19 +400,24 @@ static void usb_xcvr_reset(void)
        mdelay(1);
 }
-#if defined(CONFIG_USB_ULPI)
+static int moboard_usbh2_init_hw(struct platform_device *pdev)
+{
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+        .init   = moboard_usbh2_init_hw,
        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
 static int __init moboard_usbh2_init(void)
 {
        struct platform_device *pdev;
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                        ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (!usbh2_pdata.otg)
+                return -ENODEV;
        pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
        if (IS_ERR(pdev))
@@ -420,10 +425,6 @@ static int __init moboard_usbh2_init(void)
        return 0;
 }
-#else
-static inline int moboard_usbh2_init(void) { return 0; }
-#endif
 static struct gpio_led mx31moboard_leds[] = {
        {
@@ -503,7 +504,7 @@ core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
 /*
 * Board specific initialization.
 */
-static void __init mxc_board_init(void)
+static void __init mx31moboard_init(void)
 {
        mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
                "moboard");
@@ -564,10 +565,10 @@ struct sys_timer mx31moboard_timer = {
 MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
        /* Maintainer: Valentin Longchamp, EPFL Mobots group */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_map_io,
+        .map_io = mx31_map_io,
-        .init_irq       = mx31_init_irq,
+        .init_early = imx31_init_early,
-        .init_machine   = mxc_board_init,
+        .init_irq = mx31_init_irq,
-        .timer          = &mx31moboard_timer,
+        .timer = &mx31moboard_timer,
+        .init_machine = mx31moboard_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index b1963f257c20..ff5fe231b8d6 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -118,24 +118,42 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
        MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
        MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
        MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+        /* I2C1 */
+        MX35_PAD_I2C1_CLK__I2C1_SCL,
+        MX35_PAD_I2C1_DAT__I2C1_SDA,
 };
+static int mx35_3ds_otg_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
+}
 /* OTG config */
 static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
        .operating_mode = FSL_USB2_DR_DEVICE,
        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
+        .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
+/*
+ * ENGCM09152 also requires a hardware change.
+ * Please check the MX35 Chip Errata document for details.
+ */
 };
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = mx35_3ds_otg_init,
        .portsc = MXC_EHCI_MODE_UTMI,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
+static int mx35_3ds_usbh_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
+                          MXC_EHCI_INTERNAL_PHY);
+}
 /* USB HOST config */
 static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
+        .init           = mx35_3ds_usbh_init,
        .portsc         = MXC_EHCI_MODE_SERIAL,
-        .flags          = MXC_EHCI_INTERFACE_SINGLE_UNI |
-                          MXC_EHCI_INTERNAL_PHY,
 };
 static int otg_mode_host;
@@ -153,10 +171,14 @@ static int __init mx35_3ds_otg_mode(char *options)
 }
 __setup("otg_mode=", mx35_3ds_otg_mode);
+static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
+        .bitrate = 100000,
+};
 /*
 * Board specific initialization.
 */
-static void __init mxc_board_init(void)
+static void __init mx35_3ds_init(void)
 {
        mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
@@ -180,6 +202,7 @@ static void __init mxc_board_init(void)
        if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                pr_warn("Init of the debugboard failed, all "
                                "devices on the debugboard are unusable.\n");
+        imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
 }
 static void __init mx35pdk_timer_init(void)
@@ -193,9 +216,10 @@ struct sys_timer mx35pdk_timer = {
 MACHINE_START(MX35_3DS, "Freescale MX35PDK")
        /* Maintainer: Freescale Semiconductor, Inc */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx35_map_io,
+        .map_io = mx35_map_io,
-        .init_irq       = mx35_init_irq,
+        .init_early = imx35_init_early,
-        .init_machine   = mxc_board_init,
+        .init_irq = mx35_init_irq,
-        .timer          = &mx35pdk_timer,
+        .timer = &mx35pdk_timer,
+        .init_machine = mx35_3ds_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index b752f6bc20a2..f07d3bded674 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -533,17 +533,25 @@ static struct platform_device pcm970_sja1000 = {
        .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
 };
-#if defined(CONFIG_USB_ULPI)
+static int pcm037_otg_init(struct platform_device *pdev)
+{
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = pcm037_otg_init,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+static int pcm037_usbh2_init(struct platform_device *pdev)
+{
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+        .init   = pcm037_usbh2_init,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
-#endif
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
        .operating_mode = FSL_USB2_DR_DEVICE,
@@ -568,7 +576,7 @@ __setup("otg_mode=", pcm037_otg_mode);
 /*
 * Board specific initialization.
 */
-static void __init mxc_board_init(void)
+static void __init pcm037_init(void)
 {
        int ret;
@@ -646,19 +654,18 @@ static void __init mxc_board_init(void)
        platform_device_register(&pcm970_sja1000);
-#if defined(CONFIG_USB_ULPI)
        if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                                ULPI_OTG_DRVVBUS_EXT);
+                if (otg_pdata.otg)
-                imx31_add_mxc_ehci_otg(&otg_pdata);
+                        imx31_add_mxc_ehci_otg(&otg_pdata);
        }
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (usbh2_pdata.otg)
+                imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
        if (!otg_mode_host)
                imx31_add_fsl_usb2_udc(&otg_device_pdata);
@@ -675,9 +682,10 @@ struct sys_timer pcm037_timer = {
 MACHINE_START(PCM037, "Phytec Phycore pcm037")
        /* Maintainer: Pengutronix */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_map_io,
+        .map_io = mx31_map_io,
-        .init_irq       = mx31_init_irq,
+        .init_early = imx31_init_early,
-        .init_machine   = mxc_board_init,
+        .init_irq = mx31_init_irq,
-        .timer          = &pcm037_timer,
+        .timer = &pcm037_timer,
+        .init_machine = pcm037_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index fda56545d2fd..df6fb07d037e 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -180,9 +180,7 @@ static int __init eet_init_devices(void)
        /* SPI */
        spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
        imx31_add_spi_imx0(&pcm037_spi1_pdata);
-#endif
        platform_device_register(&pcm037_gpio_keys_device);
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index bcf83fc7e701..b3ecfb22d241 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -115,7 +115,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
-#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
 static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
        .bitrate = 50000,
 };
@@ -134,7 +133,6 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
                I2C_BOARD_INFO("pcf8563", 0x51),
        }
 };
-#endif
 static struct platform_device *devices[] __initdata = {
        &pcm043_flash,
@@ -221,9 +219,9 @@ static iomux_v3_cfg_t pcm043_pads[] = {
        MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 };
-#define AC97_GPIO_TXFS  (1 * 32 + 31)
+#define AC97_GPIO_TXFS  IMX_GPIO_NR(2, 31)
-#define AC97_GPIO_TXD   (1 * 32 + 28)
+#define AC97_GPIO_TXD   IMX_GPIO_NR(2, 28)
-#define AC97_GPIO_RESET (1 * 32 + 0)
+#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
 static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
 {
@@ -307,18 +305,26 @@ pcm037_nand_board_info __initconst = {
        .hw_ecc = 1,
 };
-#if defined(CONFIG_USB_ULPI)
+static int pcm043_otg_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = pcm043_otg_init,
        .portsc = MXC_EHCI_MODE_UTMI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+static int pcm043_usbh1_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
+                        MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
+}
 static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
+        .init   = pcm043_usbh1_init,
        .portsc = MXC_EHCI_MODE_SERIAL,
-        .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
-                  MXC_EHCI_IPPUE_DOWN,
 };
-#endif
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
        .operating_mode = FSL_USB2_DR_DEVICE,
@@ -343,7 +349,7 @@ __setup("otg_mode=", pcm043_otg_mode);
 /*
 * Board specific initialization.
 */
-static void __init mxc_board_init(void)
+static void __init pcm043_init(void)
 {
        mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
@@ -369,26 +375,22 @@ static void __init mxc_board_init(void)
        imx35_add_imx_uart1(&uart_pdata);
-#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
        i2c_register_board_info(0, pcm043_i2c_devices,
                        ARRAY_SIZE(pcm043_i2c_devices));
        imx35_add_imx_i2c0(&pcm043_i2c0_data);
-#endif
        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
        mxc_register_device(&mx3_fb, &mx3fb_pdata);
-#if defined(CONFIG_USB_ULPI)
        if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                                ULPI_OTG_DRVVBUS_EXT);
+                if (otg_pdata.otg)
-                imx35_add_mxc_ehci_otg(&otg_pdata);
+                        imx35_add_mxc_ehci_otg(&otg_pdata);
        }
        imx35_add_mxc_ehci_hs(&usbh1_pdata);
-#endif
        if (!otg_mode_host)
                imx35_add_fsl_usb2_udc(&otg_device_pdata);
@@ -407,10 +409,10 @@ struct sys_timer pcm043_timer = {
 MACHINE_START(PCM043, "Phytec Phycore pcm043")
        /* Maintainer: Pengutronix */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx35_map_io,
+        .map_io = mx35_map_io,
-        .init_irq       = mx35_init_irq,
+        .init_early = imx35_init_early,
-        .init_machine   = mxc_board_init,
+        .init_irq = mx35_init_irq,
-        .timer          = &pcm043_timer,
+        .timer = &pcm043_timer,
+        .init_machine = pcm043_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index fd1050c40964..17f758b77623 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -54,10 +54,6 @@
 #define QONG_FPGA_IRQ           IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
-/*
- * This file contains the board-specific initialization routines.
- */
 static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -247,7 +243,7 @@ static void __init qong_init_fpga(void)
 /*
 * Board specific initialization.
 */
-static void __init mxc_board_init(void)
+static void __init qong_init(void)
 {
        mxc_init_imx_uart();
        qong_init_nor_mtd();
@@ -263,16 +259,12 @@ static struct sys_timer qong_timer = {
        .init   = qong_timer_init,
 };
-/*
- * The following uses standard kernel macros defined in arch.h in order to
- * initialize __mach_desc_QONG data structure.
- */
 MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
        /* Maintainer: DENX Software Engineering GmbH */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_map_io,
+        .map_io = mx31_map_io,
-        .init_irq       = mx31_init_irq,
+        .init_early = imx31_init_early,
-        .init_machine   = mxc_board_init,
+        .init_irq = mx31_init_irq,
-        .timer          = &qong_timer,
+        .timer = &qong_timer,
+        .init_machine = qong_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-mx3/mach-vpr200.c
new file mode 100644
index 000000000000..2cf390fbd980
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-vpr200.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
+ * Copyright 2010 Creative Product Design
+ *
+ * Derived from mx35 3stack.
+ * Original author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/irqs.h>
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/mfd/mc13xxx.h>
+#include <linux/gpio_keys.h>
+#include "devices-imx35.h"
+#include "devices.h"
+#define GPIO_LCDPWR     IMX_GPIO_NR(1, 2)
+#define GPIO_PMIC_INT   IMX_GPIO_NR(2, 0)
+#define GPIO_BUTTON1    IMX_GPIO_NR(1, 4)
+#define GPIO_BUTTON2    IMX_GPIO_NR(1, 5)
+#define GPIO_BUTTON3    IMX_GPIO_NR(1, 7)
+#define GPIO_BUTTON4    IMX_GPIO_NR(1, 8)
+#define GPIO_BUTTON5    IMX_GPIO_NR(1, 9)
+#define GPIO_BUTTON6    IMX_GPIO_NR(1, 10)
+#define GPIO_BUTTON7    IMX_GPIO_NR(1, 11)
+#define GPIO_BUTTON8    IMX_GPIO_NR(1, 12)
+static const struct fb_videomode fb_modedb[] = {
+        {
+                /* 800x480 @ 60 Hz */
+                .name           = "PT0708048",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = KHZ2PICOS(33260),
+                .left_margin    = 50,
+                .right_margin   = 156,
+                .upper_margin   = 10,
+                .lower_margin   = 10,
+                .hsync_len      = 1,    /* note: DE only display */
+                .vsync_len      = 1,    /* note: DE only display */
+                .sync           = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        }, {
+                /* 800x480 @ 60 Hz */
+                .name           = "CTP-CLAA070LC0ACW",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = KHZ2PICOS(27000),
+                .left_margin    = 50,
+                .right_margin   = 50,   /* whole line should have 900 clocks */
+                .upper_margin   = 10,
+                .lower_margin   = 10,   /* whole frame should have 500 lines */
+                .hsync_len      = 1,    /* note: DE only display */
+                .vsync_len      = 1,    /* note: DE only display */
+                .sync           = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        }
+};
+static struct ipu_platform_data mx3_ipu_data = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+static struct mx3fb_platform_data mx3fb_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .name           = "PT0708048",
+        .mode           = fb_modedb,
+        .num_modes      = ARRAY_SIZE(fb_modedb),
+};
+static struct physmap_flash_data vpr200_flash_data = {
+        .width  = 2,
+};
+static struct resource vpr200_flash_resource = {
+        .start  = MX35_CS0_BASE_ADDR,
+        .end    = MX35_CS0_BASE_ADDR + SZ_64M - 1,
+        .flags  = IORESOURCE_MEM,
+};
+static struct platform_device vpr200_flash = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &vpr200_flash_data,
+        },
+        .resource = &vpr200_flash_resource,
+        .num_resources = 1,
+};
+static const struct mxc_nand_platform_data
+                vpr200_nand_board_info __initconst = {
+        .width = 1,
+        .hw_ecc = 1,
+        .flash_bbt = 1,
+};
+#define VPR_KEY_DEBOUNCE        500
+static struct gpio_keys_button vpr200_gpio_keys_table[] = {
+        {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE},
+        {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
+};
+static struct gpio_keys_platform_data vpr200_gpio_keys_data = {
+        .buttons = vpr200_gpio_keys_table,
+        .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
+};
+static struct platform_device vpr200_device_gpiokeys = {
+        .name = "gpio-keys",
+        .dev = {
+                .platform_data = &vpr200_gpio_keys_data,
+        }
+};
+static struct mc13xxx_platform_data vpr200_pmic = {
+        .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
+};
+static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = {
+        .bitrate = 50000,
+};
+static struct at24_platform_data vpr200_eeprom = {
+        .byte_len = 2048 / 8,
+        .page_size = 1,
+};
+static struct i2c_board_info vpr200_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("at24", 0x50), /* E0=0, E1=0, E2=0 */
+                .platform_data = &vpr200_eeprom,
+        }, {
+                I2C_BOARD_INFO("mc13892", 0x08),
+                .platform_data = &vpr200_pmic,
+                .irq = gpio_to_irq(GPIO_PMIC_INT),
+        }
+};
+static iomux_v3_cfg_t vpr200_pads[] = {
+        /* UART1 */
+        MX35_PAD_TXD1__UART1_TXD_MUX,
+        MX35_PAD_RXD1__UART1_RXD_MUX,
+        /* UART3 */
+        MX35_PAD_ATA_DATA10__UART3_RXD_MUX,
+        MX35_PAD_ATA_DATA11__UART3_TXD_MUX,
+        /* FEC */
+        MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+        MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+        MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+        MX35_PAD_FEC_COL__FEC_COL,
+        MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+        MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+        MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX35_PAD_FEC_MDC__FEC_MDC,
+        MX35_PAD_FEC_MDIO__FEC_MDIO,
+        MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+        MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+        MX35_PAD_FEC_CRS__FEC_CRS,
+        MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+        MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+        MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+        MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+        MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+        MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+        /* Display */
+        MX35_PAD_LD0__IPU_DISPB_DAT_0,
+        MX35_PAD_LD1__IPU_DISPB_DAT_1,
+        MX35_PAD_LD2__IPU_DISPB_DAT_2,
+        MX35_PAD_LD3__IPU_DISPB_DAT_3,
+        MX35_PAD_LD4__IPU_DISPB_DAT_4,
+        MX35_PAD_LD5__IPU_DISPB_DAT_5,
+        MX35_PAD_LD6__IPU_DISPB_DAT_6,
+        MX35_PAD_LD7__IPU_DISPB_DAT_7,
+        MX35_PAD_LD8__IPU_DISPB_DAT_8,
+        MX35_PAD_LD9__IPU_DISPB_DAT_9,
+        MX35_PAD_LD10__IPU_DISPB_DAT_10,
+        MX35_PAD_LD11__IPU_DISPB_DAT_11,
+        MX35_PAD_LD12__IPU_DISPB_DAT_12,
+        MX35_PAD_LD13__IPU_DISPB_DAT_13,
+        MX35_PAD_LD14__IPU_DISPB_DAT_14,
+        MX35_PAD_LD15__IPU_DISPB_DAT_15,
+        MX35_PAD_LD16__IPU_DISPB_DAT_16,
+        MX35_PAD_LD17__IPU_DISPB_DAT_17,
+        MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+        MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+        MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+        /* LCD Enable */
+        MX35_PAD_D3_VSYNC__GPIO1_2,
+        /* USBOTG */
+        MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
+        MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+        /* SDCARD */
+        MX35_PAD_SD1_CMD__ESDHC1_CMD,
+        MX35_PAD_SD1_CLK__ESDHC1_CLK,
+        MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+        /* PMIC */
+        MX35_PAD_GPIO2_0__GPIO2_0,
+        /* GPIO keys */
+        MX35_PAD_SCKR__GPIO1_4,
+        MX35_PAD_COMPARE__GPIO1_5,
+        MX35_PAD_SCKT__GPIO1_7,
+        MX35_PAD_FST__GPIO1_8,
+        MX35_PAD_HCKT__GPIO1_9,
+        MX35_PAD_TX5_RX0__GPIO1_10,
+        MX35_PAD_TX4_RX1__GPIO1_11,
+        MX35_PAD_TX3_RX2__GPIO1_12,
+};
+/* USB Device config */
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI,
+        .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
+};
+/* USB HOST config */
+static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
+        .portsc         = MXC_EHCI_MODE_SERIAL,
+        .flags          = MXC_EHCI_INTERFACE_SINGLE_UNI |
+                          MXC_EHCI_INTERNAL_PHY,
+};
+static struct platform_device *devices[] __initdata = {
+        &vpr200_flash,
+        &vpr200_device_gpiokeys,
+};
+/*
+ * Board specific initialization.
+ */
+static void __init vpr200_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
+        imx35_add_fec(NULL);
+        imx35_add_imx2_wdt(NULL);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+        if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR"))
+                printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n");
+        else
+                gpio_direction_output(GPIO_LCDPWR, 0);
+        if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT"))
+                printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n");
+        else
+                gpio_direction_input(GPIO_PMIC_INT);
+        imx35_add_imx_uart0(NULL);
+        imx35_add_imx_uart2(NULL);
+        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+        imx35_add_fsl_usb2_udc(&otg_device_pdata);
+        imx35_add_mxc_ehci_hs(&usb_host_pdata);
+        imx35_add_mxc_nand(&vpr200_nand_board_info);
+        imx35_add_sdhci_esdhc_imx(0, NULL);
+        i2c_register_board_info(0, vpr200_i2c_devices,
+                        ARRAY_SIZE(vpr200_i2c_devices));
+        imx35_add_imx_i2c0(&vpr200_i2c0_data);
+}
+static void __init vpr200_timer_init(void)
+{
+        mx35_clocks_init();
+}
+struct sys_timer vpr200_timer = {
+        .init   = vpr200_timer_init,
+};
+MACHINE_START(VPR200, "VPR200")
+        /* Maintainer: Creative Product Design */
+        .map_io = mx35_map_io,
+        .init_early = imx35_init_early,
+        .init_irq = mx35_init_irq,
+        .timer = &vpr200_timer,
+        .init_machine = vpr200_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 47118f760244..54d7174b4202 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -27,14 +27,8 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-v3.h>
+#include <mach/gpio.h>
-/*!
+#include <mach/irqs.h>
- * @file mm.c
- *
- * @brief This file creates static virtual to physical mappings, common to all MX3 boards.
- *
- * @ingroup Memory
- */
 #ifdef CONFIG_SOC_IMX31
 static struct map_desc mx31_io_desc[] __initdata = {
@@ -52,17 +46,25 @@ static struct map_desc mx31_io_desc[] __initdata = {
 */
 void __init mx31_map_io(void)
 {
+        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
+}
+void __init imx31_init_early(void)
+{
        mxc_set_cpu_type(MXC_CPU_MX31);
        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
 }
-int imx31_register_gpios(void);
+static struct mxc_gpio_port imx31_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
+};
 void __init mx31_init_irq(void)
 {
        mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
-        imx31_register_gpios();
+        mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
 }
 #endif /* ifdef CONFIG_SOC_IMX31 */
@@ -77,18 +79,26 @@ static struct map_desc mx35_io_desc[] __initdata = {
 void __init mx35_map_io(void)
 {
+        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
+}
+void __init imx35_init_early(void)
+{
        mxc_set_cpu_type(MXC_CPU_MX35);
        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
-        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
 }
-int imx35_register_gpios(void);
+static struct mxc_gpio_port imx35_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
+};
 void __init mx35_init_irq(void)
 {
        mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
-        imx35_register_gpios();
+        mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
 }
 #endif /* ifdef CONFIG_SOC_IMX35 */
@@ -129,4 +139,3 @@ static int mxc_init_l2x0(void)
 arch_initcall(mxc_init_l2x0);
 #endif
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 94a0b9e4b7f3..6410b9c48a02 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -15,6 +15,7 @@
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/types.h>
@@ -149,7 +150,10 @@ static int devboard_usbh1_hw_init(struct platform_device *pdev)
        mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
        mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
-        return 0;
+        mdelay(10);
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_SINGLE_UNI);
 }
 #define USBH1_VBUSEN_B  IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
@@ -187,7 +191,6 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
 static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
        .init   = devboard_usbh1_hw_init,
        .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
 };
 static int __init devboard_usbh1_init(void)
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index f449a97ae1a2..57f7b00cb709 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -265,7 +265,10 @@ static int marxbot_usbh1_hw_init(struct platform_device *pdev)
        mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
        mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
-        return 0;
+        mdelay(10);
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_SINGLE_UNI);
 }
 #define USBH1_VBUSEN_B  IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
@@ -303,7 +306,6 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
 static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
        .init   = marxbot_usbh1_hw_init,
        .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
 };
 static int __init marxbot_usbh1_init(void)
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index bbec3c82264a..35f806e737c1 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -123,17 +123,24 @@ static const struct fsl_usb2_platform_data usb_pdata __initconst = {
 #if defined(CONFIG_USB_ULPI)
+static int smartbot_otg_init(struct platform_device *pdev)
+{
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
 static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
+        .init   = smartbot_otg_init,
        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
 static int __init smartbot_otg_host_init(void)
 {
        struct platform_device *pdev;
-        otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+        otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                        ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                ULPI_OTG_DRVVBUS_EXT);
+        if (!otg_host_pdata.otg)
+                return -ENODEV;
        pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
        if (IS_ERR(pdev))
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index de4fa992fc3e..83ee08847d4d 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,5 +1,6 @@
 if ARCH_MX5
-# ARCH_MX51 and ARCH_MX50 are left for compatibility
+# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single
+# image. So for most time, SOC_IMX50/51/53 should be used.
 config ARCH_MX50
        bool
@@ -50,6 +51,7 @@ config MACH_MX51_BABBAGE
 config MACH_MX51_3DS
        bool "Support MX51PDK (3DS)"
        select SOC_IMX51
+        select IMX_HAVE_PLATFORM_IMX2_WDT
        select IMX_HAVE_PLATFORM_IMX_KEYPAD
        select IMX_HAVE_PLATFORM_IMX_UART
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
@@ -112,19 +114,32 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
 endchoice
-config MACH_MX51_EFIKAMX
+config MX51_EFIKA_COMMON
-        bool "Support MX51 Genesi Efika MX nettop"
+        bool
        select SOC_IMX51
        select IMX_HAVE_PLATFORM_IMX_UART
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
        select IMX_HAVE_PLATFORM_SPI_IMX
+        select MXC_ULPI if USB_ULPI
+config MACH_MX51_EFIKAMX
+        bool "Support MX51 Genesi Efika MX nettop"
+        select MX51_EFIKA_COMMON
        help
          Include support for Genesi Efika MX nettop. This includes specific
          configurations for the board and its peripherals.
+config MACH_MX51_EFIKASB
+        bool "Support MX51 Genesi Efika Smartbook"
+        select MX51_EFIKA_COMMON
+        help
+          Include support for Genesi Efika Smartbook. This includes specific
+          configurations for the board and its peripherals.
 config MACH_MX53_EVK
        bool "Support MX53 EVK platforms"
        select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX2_WDT
        select IMX_HAVE_PLATFORM_IMX_UART
        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
@@ -136,6 +151,8 @@ config MACH_MX53_EVK
 config MACH_MX53_SMD
        bool "Support MX53 SMD platforms"
        select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_UART
        help
          Include support for MX53 SMD platform. This includes specific
@@ -144,7 +161,10 @@ config MACH_MX53_SMD
 config MACH_MX53_LOCO
        bool "Support MX53 LOCO platforms"
        select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
        help
          Include support for MX53 LOCO platform. This includes specific
          configurations for the board and its peripherals.
@@ -157,6 +177,7 @@ config MACH_MX50_RDP
        select IMX_HAVE_PLATFORM_IMX_UART
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
        select IMX_HAVE_PLATFORM_SPI_IMX
+        select IMX_HAVE_PLATFORM_FEC
        help
          Include support for MX50 reference design platform (RDP) board. This
          includes specific configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 0d43be98e51c..4f63048be3ca 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,7 +3,7 @@
 #
 # Object file lists.
-obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o
+obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o
 obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
@@ -16,5 +16,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
+obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
 obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
+obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
 obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index f8652ef25f85..d0296a94c475 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -60,7 +60,6 @@
 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
 #define MX51_USB_PLL_DIV_24_MHZ         0x02
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
 static struct plat_serial8250_port serial_platform_data[] = {
        {
                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
@@ -105,12 +104,9 @@ static struct platform_device serial_device = {
                .platform_data = serial_platform_data,
        },
 };
-#endif
 static struct platform_device *devices[] __initdata = {
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
        &serial_device,
-#endif
 };
 static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
@@ -188,7 +184,10 @@ static int initialize_otg_port(struct platform_device *pdev)
        v |= MX51_USB_PLL_DIV_19_2_MHZ;
        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
        iounmap(usb_base);
-        return 0;
+        mdelay(10);
+        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 }
 static int initialize_usbh1_port(struct platform_device *pdev)
@@ -206,13 +205,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
        v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
        iounmap(usb_base);
-        return 0;
+        mdelay(10);
+        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
 static struct mxc_usbh_platform_data dr_utmi_config = {
        .init           = initialize_otg_port,
        .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 static struct fsl_usb2_platform_data usb_pdata = {
@@ -223,7 +225,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
 static struct mxc_usbh_platform_data usbh1_config = {
        .init           = initialize_usbh1_port,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 };
 static int otg_mode_host;
@@ -298,7 +299,8 @@ MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
        /* Maintainer: Eric Bénard <eric@eukrea.com> */
        .boot_params = MX51_PHYS_OFFSET + 0x100,
        .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
-        .init_machine = eukrea_cpuimx51_init,
        .timer = &mxc_timer,
+        .init_machine = eukrea_cpuimx51_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index ad931895d8b6..29b180823bf5 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -42,6 +42,7 @@
 #include "devices-imx51.h"
 #include "devices.h"
+#include "cpu_op-mx51.h"
 #define USBH1_RST               IMX_GPIO_NR(2, 28)
 #define ETH_RST                 IMX_GPIO_NR(2, 31)
@@ -109,7 +110,7 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
        /* Touchscreen */
        /* IRQ */
-        _MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+        _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 };
@@ -118,15 +119,9 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
-static int ts_get_pendown_state(void)
-{
-        return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1;
-}
 static struct tsc2007_platform_data tsc2007_info = {
        .model                  = 2007,
        .x_plate_ohms           = 180,
-        .get_pendown_state      = ts_get_pendown_state,
 };
 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
@@ -167,7 +162,10 @@ static int initialize_otg_port(struct platform_device *pdev)
        v |= MX51_USB_PLL_DIV_19_2_MHZ;
        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
        iounmap(usb_base);
-        return 0;
+        mdelay(10);
+        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 }
 static int initialize_usbh1_port(struct platform_device *pdev)
@@ -186,13 +184,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
                        usbother_base + MX51_USB_CTRL_1_OFFSET);
        iounmap(usb_base);
-        return 0;
+        mdelay(10);
+        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
 static struct mxc_usbh_platform_data dr_utmi_config = {
        .init           = initialize_otg_port,
        .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 static struct fsl_usb2_platform_data usb_pdata = {
@@ -203,7 +204,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
 static struct mxc_usbh_platform_data usbh1_config = {
        .init           = initialize_usbh1_port,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 };
 static int otg_mode_host;
@@ -242,7 +242,7 @@ static struct mcp251x_platform_data mcp251x_info = {
 static struct spi_board_info cpuimx51sd_spi_device[] = {
        {
                .modalias        = "mcp2515",
-                .max_speed_hz    = 6500000,
+                .max_speed_hz    = 10000000,
                .bus_num         = 0,
                .mode           = SPI_MODE_0,
                .chip_select     = 0,
@@ -269,6 +269,10 @@ static void __init eukrea_cpuimx51sd_init(void)
        mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
                                        ARRAY_SIZE(eukrea_cpuimx51sd_pads));
+#if defined(CONFIG_CPU_FREQ_IMX)
+        get_cpu_op = mx51_get_cpu_op;
+#endif
        imx51_add_imx_uart(0, &uart_pdata);
        imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
@@ -329,7 +333,8 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
        /* Maintainer: Eric Bénard <eric@eukrea.com> */
        .boot_params = MX51_PHYS_OFFSET + 0x100,
        .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
-        .init_machine = eukrea_cpuimx51sd_init,
        .timer = &mxc_timer,
+        .init_machine = eukrea_cpuimx51sd_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index fd32e4c450e8..dedf7f2d6d0f 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -35,7 +35,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include "devices-mx50.h"
+#include "devices-imx50.h"
+#define FEC_EN          IMX_GPIO_NR(6, 23)
+#define FEC_RESET_B     IMX_GPIO_NR(4, 12)
 static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
        /* SD1 */
@@ -102,7 +105,7 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
        MX50_PAD_I2C3_SCL__USBOTG_OC,
        MX50_PAD_SSI_RXC__FEC_MDIO,
-        MX50_PAD_SSI_RXC__FEC_MDIO,
+        MX50_PAD_SSI_RXFS__FEC_MDC,
        MX50_PAD_DISP_D0__FEC_TXCLK,
        MX50_PAD_DISP_D1__FEC_RX_ER,
        MX50_PAD_DISP_D2__FEC_RX_DV,
@@ -111,7 +114,6 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
        MX50_PAD_DISP_D5__FEC_TX_EN,
        MX50_PAD_DISP_D6__FEC_TXD1,
        MX50_PAD_DISP_D7__FEC_TXD0,
-        MX50_PAD_SSI_RXFS__FEC_MDC,
        MX50_PAD_I2C3_SDA__GPIO_6_23,
        MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
@@ -168,6 +170,24 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
+static const struct fec_platform_data fec_data __initconst = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+static inline void mx50_rdp_fec_reset(void)
+{
+        gpio_request(FEC_EN, "fec-en");
+        gpio_direction_output(FEC_EN, 0);
+        gpio_request(FEC_RESET_B, "fec-reset_b");
+        gpio_direction_output(FEC_RESET_B, 0);
+        msleep(1);
+        gpio_set_value(FEC_RESET_B, 1);
+}
+static const struct imxi2c_platform_data i2c_data __initconst = {
+        .bitrate = 100000,
+};
 /*
 * Board specific initialization.
 */
@@ -178,6 +198,11 @@ static void __init mx50_rdp_board_init(void)
        imx50_add_imx_uart(0, &uart_pdata);
        imx50_add_imx_uart(1, &uart_pdata);
+        mx50_rdp_fec_reset();
+        imx50_add_fec(&fec_data);
+        imx50_add_imx_i2c(0, &i2c_data);
+        imx50_add_imx_i2c(1, &i2c_data);
+        imx50_add_imx_i2c(2, &i2c_data);
 }
 static void __init mx50_rdp_timer_init(void)
@@ -191,7 +216,8 @@ static struct sys_timer mx50_rdp_timer = {
 MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
        .map_io = mx50_map_io,
+        .init_early = imx50_init_early,
        .init_irq = mx50_init_irq,
-        .init_machine = mx50_rdp_board_init,
        .timer = &mx50_rdp_timer,
+        .init_machine = mx50_rdp_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 49d644842379..63dfbeafbc1e 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -71,24 +71,10 @@ static iomux_v3_cfg_t mx51_3ds_pads[] = {
 };
 /* Serial ports */
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
-static inline void mxc_init_imx_uart(void)
-{
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, &uart_pdata);
-        imx51_add_imx_uart(2, &uart_pdata);
-}
-#else /* !SERIAL_IMX */
-static inline void mxc_init_imx_uart(void)
-{
-}
-#endif /* SERIAL_IMX */
-#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
 static int mx51_3ds_board_keymap[] = {
        KEY(0, 0, KEY_1),
        KEY(0, 1, KEY_2),
@@ -124,16 +110,6 @@ static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
        .keymap_size    = ARRAY_SIZE(mx51_3ds_board_keymap),
 };
-static void mxc_init_keypad(void)
-{
-        imx51_add_imx_keypad(&mx51_3ds_map_data);
-}
-#else
-static inline void mxc_init_keypad(void)
-{
-}
-#endif
 static int mx51_3ds_spi2_cs[] = {
        MXC_SPI_CS(0),
        MX51_3DS_ECSPI2_CS,
@@ -157,11 +133,14 @@ static struct spi_board_info mx51_3ds_spi_nor_device[] = {
 /*
 * Board specific initialization.
 */
-static void __init mxc_board_init(void)
+static void __init mx51_3ds_init(void)
 {
        mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
                                        ARRAY_SIZE(mx51_3ds_pads));
-        mxc_init_imx_uart();
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
        imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
        spi_register_board_info(mx51_3ds_spi_nor_device,
@@ -172,7 +151,8 @@ static void __init mxc_board_init(void)
                                    "devices on the board are unusable.\n");
        imx51_add_sdhci_esdhc_imx(0, NULL);
-        mxc_init_keypad();
+        imx51_add_imx_keypad(&mx51_3ds_map_data);
+        imx51_add_imx2_wdt(0, NULL);
 }
 static void __init mx51_3ds_timer_init(void)
@@ -180,15 +160,16 @@ static void __init mx51_3ds_timer_init(void)
        mx51_clocks_init(32768, 24000000, 22579200, 0);
 }
-static struct sys_timer mxc_timer = {
+static struct sys_timer mx51_3ds_timer = {
-        .init   = mx51_3ds_timer_init,
+        .init = mx51_3ds_timer_init,
 };
 MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
        /* Maintainer: Freescale Semiconductor, Inc. */
        .boot_params = MX51_PHYS_OFFSET + 0x100,
        .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
-        .init_machine = mxc_board_init,
+        .timer = &mx51_3ds_timer,
-        .timer = &mxc_timer,
+        .init_machine = mx51_3ds_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 1d231e84107c..b2ecd194e76d 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -161,23 +161,10 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
 };
 /* Serial ports */
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
-static inline void mxc_init_imx_uart(void)
-{
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, &uart_pdata);
-        imx51_add_imx_uart(2, &uart_pdata);
-}
-#else /* !SERIAL_IMX */
-static inline void mxc_init_imx_uart(void)
-{
-}
-#endif /* SERIAL_IMX */
 static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
        .bitrate = 100000,
 };
@@ -272,7 +259,10 @@ static int initialize_otg_port(struct platform_device *pdev)
        v |= MX51_USB_PLL_DIV_19_2_MHZ;
        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
        iounmap(usb_base);
-        return 0;
+        mdelay(10);
+        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 }
 static int initialize_usbh1_port(struct platform_device *pdev)
@@ -290,13 +280,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
        v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
        iounmap(usb_base);
-        return 0;
+        mdelay(10);
+        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
 static struct mxc_usbh_platform_data dr_utmi_config = {
        .init           = initialize_otg_port,
        .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 static struct fsl_usb2_platform_data usb_pdata = {
@@ -307,7 +300,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
 static struct mxc_usbh_platform_data usbh1_config = {
        .init           = initialize_usbh1_port,
        .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 };
 static int otg_mode_host;
@@ -349,7 +341,7 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
 /*
 * Board specific initialization.
 */
-static void __init mxc_board_init(void)
+static void __init mx51_babbage_init(void)
 {
        iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
        iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
@@ -360,7 +352,11 @@ static void __init mxc_board_init(void)
 #endif
        mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
                                        ARRAY_SIZE(mx51babbage_pads));
-        mxc_init_imx_uart();
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
        babbage_fec_reset();
        imx51_add_fec(NULL);
@@ -399,15 +395,16 @@ static void __init mx51_babbage_timer_init(void)
        mx51_clocks_init(32768, 24000000, 22579200, 0);
 }
-static struct sys_timer mxc_timer = {
+static struct sys_timer mx51_babbage_timer = {
-        .init   = mx51_babbage_timer_init,
+        .init = mx51_babbage_timer_init,
 };
 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
        /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
        .boot_params = MX51_PHYS_OFFSET + 0x100,
        .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
-        .init_machine = mxc_board_init,
+        .timer = &mx51_babbage_timer,
-        .timer = &mxc_timer,
+        .init_machine = mx51_babbage_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index b7946f8e8d40..acab1911cb3c 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -25,6 +25,9 @@
 #include <linux/fsl_devices.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
@@ -40,8 +43,7 @@
 #include "devices-imx51.h"
 #include "devices.h"
+#include "efika.h"
-#define MX51_USB_PLL_DIV_24_MHZ 0x01
 #define EFIKAMX_PCBID0          IMX_GPIO_NR(3, 16)
 #define EFIKAMX_PCBID1          IMX_GPIO_NR(3, 17)
@@ -53,13 +55,14 @@
 #define EFIKAMX_POWER_KEY       IMX_GPIO_NR(2, 31)
-#define EFIKAMX_SPI_CS0         IMX_GPIO_NR(4, 24)
-#define EFIKAMX_SPI_CS1         IMX_GPIO_NR(4, 25)
 /* board 1.1 doesn't have same reset gpio */
 #define EFIKAMX_RESET1_1        IMX_GPIO_NR(3, 2)
 #define EFIKAMX_RESET           IMX_GPIO_NR(1, 4)
+#define EFIKAMX_POWEROFF        IMX_GPIO_NR(4, 13)
+#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
 /* the pci ids pin have pull up. they're driven low according to board id */
 #define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
 #define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
@@ -67,38 +70,11 @@
 #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
 static iomux_v3_cfg_t mx51efikamx_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
        /* board id */
        MX51_PAD_PCBID0,
        MX51_PAD_PCBID1,
        MX51_PAD_PCBID2,
-        /* SD 1 */
-        MX51_PAD_SD1_CMD__SD1_CMD,
-        MX51_PAD_SD1_CLK__SD1_CLK,
-        MX51_PAD_SD1_DATA0__SD1_DATA0,
-        MX51_PAD_SD1_DATA1__SD1_DATA1,
-        MX51_PAD_SD1_DATA2__SD1_DATA2,
-        MX51_PAD_SD1_DATA3__SD1_DATA3,
-        /* SD 2 */
-        MX51_PAD_SD2_CMD__SD2_CMD,
-        MX51_PAD_SD2_CLK__SD2_CLK,
-        MX51_PAD_SD2_DATA0__SD2_DATA0,
-        MX51_PAD_SD2_DATA1__SD2_DATA1,
-        MX51_PAD_SD2_DATA2__SD2_DATA2,
-        MX51_PAD_SD2_DATA3__SD2_DATA3,
-        /* SD/MMC WP/CD */
-        MX51_PAD_GPIO1_0__SD1_CD,
-        MX51_PAD_GPIO1_1__SD1_WP,
-        MX51_PAD_GPIO1_7__SD2_WP,
-        MX51_PAD_GPIO1_8__SD2_CD,
        /* leds */
        MX51_PAD_CSI1_D9__GPIO3_13,
        MX51_PAD_CSI1_VSYNC__GPIO3_14,
@@ -107,64 +83,12 @@ static iomux_v3_cfg_t mx51efikamx_pads[] = {
        /* power key */
        MX51_PAD_PWRKEY,
-        /* spi */
-        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-        MX51_PAD_CSPI1_SS0__GPIO4_24,
-        MX51_PAD_CSPI1_SS1__GPIO4_25,
-        MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
-        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
        /* reset */
        MX51_PAD_DI1_PIN13__GPIO3_2,
        MX51_PAD_GPIO1_4__GPIO1_4,
-};
-/* Serial ports */
+        /* power off */
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+        MX51_PAD_CSI2_VSYNC__GPIO4_13,
-static const struct imxuart_platform_data uart_pdata = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static inline void mxc_init_imx_uart(void)
-{
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, &uart_pdata);
-        imx51_add_imx_uart(2, &uart_pdata);
-}
-#else /* !SERIAL_IMX */
-static inline void mxc_init_imx_uart(void)
-{
-}
-#endif /* SERIAL_IMX */
-/* This function is board specific as the bit mask for the plldiv will also
- * be different for other Freescale SoCs, thus a common bitmask is not
- * possible and cannot get place in /plat-mxc/ehci.c.
- */
-static int initialize_otg_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-        /* Set the PHY clock to 19.2MHz */
-        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-        v |= MX51_USB_PLL_DIV_24_MHZ;
-        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        iounmap(usb_base);
-        return 0;
-}
-static struct mxc_usbh_platform_data dr_utmi_config = {
-        .init   = initialize_otg_port,
-        .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 /*   PCBID2  PCBID1 PCBID0  STATE
@@ -265,47 +189,6 @@ static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initcon
        .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
 };
-static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = {
-        {
-         .name = "u-boot",
-         .offset = 0,
-         .size = SZ_256K,
-        },
-        {
-          .name = "config",
-          .offset = MTDPART_OFS_APPEND,
-          .size = SZ_64K,
-        },
-};
-static struct flash_platform_data mx51_efikamx_spi_flash_data = {
-        .name           = "spi_flash",
-        .parts          = mx51_efikamx_spi_nor_partitions,
-        .nr_parts       = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions),
-        .type           = "sst25vf032b",
-};
-static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = {
-        {
-                .modalias = "m25p80",
-                .max_speed_hz = 25000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .platform_data = &mx51_efikamx_spi_flash_data,
-                .irq = -1,
-        },
-};
-static int mx51_efikamx_spi_cs[] = {
-        EFIKAMX_SPI_CS0,
-        EFIKAMX_SPI_CS1,
-};
-static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = {
-        .chipselect     = mx51_efikamx_spi_cs,
-        .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs),
-};
 void mx51_efikamx_reset(void)
 {
        if (system_rev == 0x11)
@@ -314,14 +197,53 @@ void mx51_efikamx_reset(void)
                gpio_direction_output(EFIKAMX_RESET, 0);
 }
-static void __init mxc_board_init(void)
+static struct regulator *pwgt1, *pwgt2, *coincell;
+static void mx51_efikamx_power_off(void)
+{
+        if (!IS_ERR(coincell))
+                regulator_disable(coincell);
+        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                regulator_disable(pwgt2);
+                regulator_disable(pwgt1);
+        }
+        gpio_direction_output(EFIKAMX_POWEROFF, 1);
+}
+static int __init mx51_efikamx_power_init(void)
+{
+        if (machine_is_mx51_efikamx()) {
+                pwgt1 = regulator_get(NULL, "pwgt1");
+                pwgt2 = regulator_get(NULL, "pwgt2");
+                if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                        regulator_enable(pwgt1);
+                        regulator_enable(pwgt2);
+                }
+                gpio_request(EFIKAMX_POWEROFF, "poweroff");
+                pm_power_off = mx51_efikamx_power_off;
+                /* enable coincell charger. maybe need a small power driver ? */
+                coincell = regulator_get(NULL, "coincell");
+                if (!IS_ERR(coincell)) {
+                        regulator_set_voltage(coincell, 3000000, 3000000);
+                        regulator_enable(coincell);
+                }
+                regulator_has_full_constraints();
+        }
+        return 0;
+}
+late_initcall(mx51_efikamx_power_init);
+static void __init mx51_efikamx_init(void)
 {
        mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
                                        ARRAY_SIZE(mx51efikamx_pads));
+        efika_board_common_init();
        mx51_efikamx_board_id();
-        mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
-        mxc_init_imx_uart();
-        imx51_add_sdhci_esdhc_imx(0, NULL);
        /* on < 1.2 boards both SD controllers are used */
        if (system_rev < 0x12) {
@@ -332,10 +254,6 @@ static void __init mxc_board_init(void)
        platform_device_register(&mx51_efikamx_leds_device);
        imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
-        spi_register_board_info(mx51_efikamx_spi_board_info,
-                ARRAY_SIZE(mx51_efikamx_spi_board_info));
-        imx51_add_ecspi(0, &mx51_efikamx_spi_pdata);
        if (system_rev == 0x11) {
                gpio_request(EFIKAMX_RESET1_1, "reset");
                gpio_direction_output(EFIKAMX_RESET1_1, 1);
@@ -343,6 +261,20 @@ static void __init mxc_board_init(void)
                gpio_request(EFIKAMX_RESET, "reset");
                gpio_direction_output(EFIKAMX_RESET, 1);
        }
+        /*
+         * enable wifi by default only on mx
+         * sb and mx have same wlan pin but the value to enable it are
+         * different :/
+         */
+        gpio_request(EFIKA_WLAN_EN, "wlan_en");
+        gpio_direction_output(EFIKA_WLAN_EN, 0);
+        msleep(10);
+        gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
+        gpio_direction_output(EFIKA_WLAN_RESET, 0);
+        msleep(10);
+        gpio_set_value(EFIKA_WLAN_RESET, 1);
 }
 static void __init mx51_efikamx_timer_init(void)
@@ -350,15 +282,16 @@ static void __init mx51_efikamx_timer_init(void)
        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
 }
-static struct sys_timer mxc_timer = {
+static struct sys_timer mx51_efikamx_timer = {
-        .init   = mx51_efikamx_timer_init,
+        .init = mx51_efikamx_timer_init,
 };
 MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
        /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
        .boot_params = MX51_PHYS_OFFSET + 0x100,
        .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
-        .init_machine =  mxc_board_init,
+        .timer = &mx51_efikamx_timer,
-        .timer = &mxc_timer,
+        .init_machine = mx51_efikamx_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
new file mode 100644
index 000000000000..db04ce8462dc
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <mach/ulpi.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include "devices-imx51.h"
+#include "devices.h"
+#include "efika.h"
+#define EFIKASB_USBH2_STP       IMX_GPIO_NR(2, 20)
+#define EFIKASB_GREEN_LED       IMX_GPIO_NR(1, 3)
+#define EFIKASB_WHITE_LED       IMX_GPIO_NR(2, 25)
+#define EFIKASB_PCBID0          IMX_GPIO_NR(2, 28)
+#define EFIKASB_PCBID1          IMX_GPIO_NR(2, 29)
+#define EFIKASB_PWRKEY          IMX_GPIO_NR(2, 31)
+#define EFIKASB_LID             IMX_GPIO_NR(3, 14)
+#define EFIKASB_POWEROFF        IMX_GPIO_NR(4, 13)
+#define EFIKASB_RFKILL          IMX_GPIO_NR(3, 1)
+#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
+static iomux_v3_cfg_t mx51efikasb_pads[] = {
+        /* USB HOST2 */
+        MX51_PAD_EIM_D16__USBH2_DATA0,
+        MX51_PAD_EIM_D17__USBH2_DATA1,
+        MX51_PAD_EIM_D18__USBH2_DATA2,
+        MX51_PAD_EIM_D19__USBH2_DATA3,
+        MX51_PAD_EIM_D20__USBH2_DATA4,
+        MX51_PAD_EIM_D21__USBH2_DATA5,
+        MX51_PAD_EIM_D22__USBH2_DATA6,
+        MX51_PAD_EIM_D23__USBH2_DATA7,
+        MX51_PAD_EIM_A24__USBH2_CLK,
+        MX51_PAD_EIM_A25__USBH2_DIR,
+        MX51_PAD_EIM_A26__USBH2_STP,
+        MX51_PAD_EIM_A27__USBH2_NXT,
+        /* leds */
+        MX51_PAD_EIM_CS0__GPIO2_25,
+        MX51_PAD_GPIO1_3__GPIO1_3,
+        /* pcb id */
+        MX51_PAD_EIM_CS3__GPIO2_28,
+        MX51_PAD_EIM_CS4__GPIO2_29,
+        /* lid */
+        MX51_PAD_CSI1_VSYNC__GPIO3_14,
+        /* power key*/
+        MX51_PAD_PWRKEY,
+        /* wifi/bt button */
+        MX51_PAD_DI1_PIN12__GPIO3_1,
+        /* power off */
+        MX51_PAD_CSI2_VSYNC__GPIO4_13,
+        /* wdog reset */
+        MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
+        /* BT */
+        MX51_PAD_EIM_A17__GPIO2_11,
+};
+static int initialize_usbh2_port(struct platform_device *pdev)
+{
+        iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
+        iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
+        mxc_iomux_v3_setup_pad(usbh2gpio);
+        gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
+        gpio_direction_output(EFIKASB_USBH2_STP, 0);
+        msleep(1);
+        gpio_set_value(EFIKASB_USBH2_STP, 1);
+        msleep(1);
+        gpio_free(EFIKASB_USBH2_STP);
+        mxc_iomux_v3_setup_pad(usbh2stp);
+        mdelay(10);
+        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
+}
+static struct mxc_usbh_platform_data usbh2_config = {
+        .init   = initialize_usbh2_port,
+        .portsc = MXC_EHCI_MODE_ULPI,
+};
+static void __init mx51_efikasb_usb(void)
+{
+        usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
+        if (usbh2_config.otg)
+                mxc_register_device(&mxc_usbh2_device, &usbh2_config);
+}
+static struct gpio_led mx51_efikasb_leds[] = {
+        {
+                .name = "efikasb:green",
+                .default_trigger = "default-on",
+                .gpio = EFIKASB_GREEN_LED,
+                .active_low = 1,
+        },
+        {
+                .name = "efikasb:white",
+                .default_trigger = "caps",
+                .gpio = EFIKASB_WHITE_LED,
+        },
+};
+static struct gpio_led_platform_data mx51_efikasb_leds_data = {
+        .leds = mx51_efikasb_leds,
+        .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
+};
+static struct platform_device mx51_efikasb_leds_device = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev = {
+                .platform_data = &mx51_efikasb_leds_data,
+        },
+};
+static struct gpio_keys_button mx51_efikasb_keys[] = {
+        {
+                .code = KEY_POWER,
+                .gpio = EFIKASB_PWRKEY,
+                .type = EV_PWR,
+                .desc = "Power Button",
+                .wakeup = 1,
+                .debounce_interval = 10, /* ms */
+        },
+        {
+                .code = SW_LID,
+                .gpio = EFIKASB_LID,
+                .type = EV_SW,
+                .desc = "Lid Switch",
+        },
+        {
+                /* SW_RFKILLALL vs KEY_RFKILL ? */
+                .code = SW_RFKILL_ALL,
+                .gpio = EFIKASB_RFKILL,
+                .type = EV_SW,
+                .desc = "rfkill",
+        },
+};
+static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
+        .buttons = mx51_efikasb_keys,
+        .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
+};
+static struct regulator *pwgt1, *pwgt2;
+static void mx51_efikasb_power_off(void)
+{
+        gpio_set_value(EFIKA_USB_PHY_RESET, 0);
+        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                regulator_disable(pwgt2);
+                regulator_disable(pwgt1);
+        }
+        gpio_direction_output(EFIKASB_POWEROFF, 1);
+}
+static int __init mx51_efikasb_power_init(void)
+{
+        if (machine_is_mx51_efikasb()) {
+                pwgt1 = regulator_get(NULL, "pwgt1");
+                pwgt2 = regulator_get(NULL, "pwgt2");
+                if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                        regulator_enable(pwgt1);
+                        regulator_enable(pwgt2);
+                }
+                gpio_request(EFIKASB_POWEROFF, "poweroff");
+                pm_power_off = mx51_efikasb_power_off;
+                regulator_has_full_constraints();
+        }
+        return 0;
+}
+late_initcall(mx51_efikasb_power_init);
+/* 01     R1.3 board
+   10     R2.0 board */
+static void __init mx51_efikasb_board_id(void)
+{
+        int id;
+        gpio_request(EFIKASB_PCBID0, "pcb id0");
+        gpio_direction_input(EFIKASB_PCBID0);
+        gpio_request(EFIKASB_PCBID1, "pcb id1");
+        gpio_direction_input(EFIKASB_PCBID1);
+        id = gpio_get_value(EFIKASB_PCBID0);
+        id |= gpio_get_value(EFIKASB_PCBID1) << 1;
+        switch (id) {
+        default:
+                break;
+        case 1:
+                system_rev = 0x13;
+                break;
+        case 2:
+                system_rev = 0x20;
+                break;
+        }
+}
+static void __init efikasb_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
+                                        ARRAY_SIZE(mx51efikasb_pads));
+        efika_board_common_init();
+        mx51_efikasb_board_id();
+        mx51_efikasb_usb();
+        imx51_add_sdhci_esdhc_imx(1, NULL);
+        platform_device_register(&mx51_efikasb_leds_device);
+        imx51_add_gpio_keys(&mx51_efikasb_keys_data);
+}
+static void __init mx51_efikasb_timer_init(void)
+{
+        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
+}
+static struct sys_timer mx51_efikasb_timer = {
+        .init   = mx51_efikasb_timer_init,
+};
+MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
+        .init_irq = mx51_init_irq,
+        .init_machine =  efikasb_board_init,
+        .timer = &mx51_efikasb_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index caee04c08238..7b5735c5ea59 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
 */
@@ -42,28 +42,24 @@
 #include "devices-imx53.h"
 static iomux_v3_cfg_t mx53_evk_pads[] = {
-        MX53_PAD_CSI0_D10__UART1_TXD,
+        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-        MX53_PAD_CSI0_D11__UART1_RXD,
+        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-        MX53_PAD_ATA_DIOW__UART1_TXD,
-        MX53_PAD_ATA_DMACK__UART1_RXD,
-        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
+        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-        MX53_PAD_ATA_DMARQ__UART2_TXD,
+        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-        MX53_PAD_ATA_DIOR__UART2_RTS,
+        MX53_PAD_PATA_DIOR__UART2_RTS,
-        MX53_PAD_ATA_INTRQ__UART2_CTS,
+        MX53_PAD_PATA_INTRQ__UART2_CTS,
-        MX53_PAD_ATA_CS_0__UART3_TXD,
+        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-        MX53_PAD_ATA_CS_1__UART3_RXD,
+        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-        MX53_PAD_ATA_DA_1__UART3_CTS,
-        MX53_PAD_ATA_DA_2__UART3_RTS,
-        MX53_PAD_EIM_D16__CSPI1_SCLK,
+        MX53_PAD_EIM_D16__ECSPI1_SCLK,
-        MX53_PAD_EIM_D17__CSPI1_MISO,
+        MX53_PAD_EIM_D17__ECSPI1_MISO,
-        MX53_PAD_EIM_D18__CSPI1_MOSI,
+        MX53_PAD_EIM_D18__ECSPI1_MOSI,
        /* ecspi chip select lines */
-        MX53_PAD_EIM_EB2__GPIO_2_30,
+        MX53_PAD_EIM_EB2__GPIO2_30,
-        MX53_PAD_EIM_D19__GPIO_3_19,
+        MX53_PAD_EIM_D19__GPIO3_19,
 };
 static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
@@ -72,9 +68,9 @@ static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
 static inline void mx53_evk_init_uart(void)
 {
-        imx53_add_imx_uart(0, &mx53_evk_uart_pdata);
+        imx53_add_imx_uart(0, NULL);
        imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
-        imx53_add_imx_uart(2, &mx53_evk_uart_pdata);
+        imx53_add_imx_uart(2, NULL);
 }
 static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
@@ -139,6 +135,7 @@ static void __init mx53_evk_board_init(void)
        spi_register_board_info(mx53_evk_spi_board_info,
                ARRAY_SIZE(mx53_evk_spi_board_info));
        imx53_add_ecspi(0, &mx53_evk_spi_data);
+        imx53_add_imx2_wdt(0, NULL);
 }
 static void __init mx53_evk_timer_init(void)
@@ -152,7 +149,8 @@ static struct sys_timer mx53_evk_timer = {
 MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
        .map_io = mx53_map_io,
+        .init_early = imx53_init_early,
        .init_irq = mx53_init_irq,
-        .init_machine = mx53_evk_board_init,
        .timer = &mx53_evk_timer,
+        .init_machine = mx53_evk_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index d1348e04ace3..0a18f8d23eb0 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -39,33 +39,147 @@
 #define LOCO_FEC_PHY_RST                IMX_GPIO_NR(7, 6)
 static iomux_v3_cfg_t mx53_loco_pads[] = {
-        MX53_PAD_CSI0_D10__UART1_TXD,
+        /* FEC */
-        MX53_PAD_CSI0_D11__UART1_RXD,
+        MX53_PAD_FEC_MDC__FEC_MDC,
-        MX53_PAD_ATA_DIOW__UART1_TXD,
+        MX53_PAD_FEC_MDIO__FEC_MDIO,
-        MX53_PAD_ATA_DMACK__UART1_RXD,
+        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+        MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
+        MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
-        MX53_PAD_ATA_DMARQ__UART2_TXD,
+        MX53_PAD_FEC_RXD1__FEC_RDATA_1,
-        MX53_PAD_ATA_DIOR__UART2_RTS,
+        MX53_PAD_FEC_RXD0__FEC_RDATA_0,
-        MX53_PAD_ATA_INTRQ__UART2_CTS,
+        MX53_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX53_PAD_FEC_TXD1__FEC_TDATA_1,
-        MX53_PAD_ATA_CS_0__UART3_TXD,
+        MX53_PAD_FEC_TXD0__FEC_TDATA_0,
-        MX53_PAD_ATA_CS_1__UART3_RXD,
+        /* FEC_nRST */
-        MX53_PAD_ATA_DA_1__UART3_CTS,
+        MX53_PAD_PATA_DA_0__GPIO7_6,
-        MX53_PAD_ATA_DA_2__UART3_RTS,
+        /* FEC_nINT */
+        MX53_PAD_PATA_DATA4__GPIO2_4,
+        /* AUDMUX5 */
+        MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
+        MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
+        MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
+        MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
+        /* I2C2 */
+        MX53_PAD_KEY_COL3__I2C2_SCL,
+        MX53_PAD_KEY_ROW3__I2C2_SDA,
+        /* SD1 */
+        MX53_PAD_SD1_CMD__ESDHC1_CMD,
+        MX53_PAD_SD1_CLK__ESDHC1_CLK,
+        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+        /* SD3 */
+        MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
+        MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
+        MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
+        MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
+        MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
+        MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
+        MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
+        MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
+        MX53_PAD_PATA_IORDY__ESDHC3_CLK,
+        MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+        /* SD3_CD */
+        MX53_PAD_EIM_DA11__GPIO3_11,
+        /* SD3_WP */
+        MX53_PAD_EIM_DA12__GPIO3_12,
+        /* VGA */
+        MX53_PAD_EIM_OE__IPU_DI1_PIN7,
+        MX53_PAD_EIM_RW__IPU_DI1_PIN8,
+        /* DISPLB */
+        MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
+        MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
+        MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
+        MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
+        /* DISP0_POWER_EN */
+        MX53_PAD_EIM_D24__GPIO3_24,
+        /* DISP0 DET INT */
+        MX53_PAD_EIM_D31__GPIO3_31,
+        /* LVDS */
+        MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
+        MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
+        MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
+        MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
+        MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
+        MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
+        MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
+        MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
+        MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
+        MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
+        /* I2C1 */
+        MX53_PAD_CSI0_DAT8__I2C1_SDA,
+        MX53_PAD_CSI0_DAT9__I2C1_SCL,
+        /* UART1 */
+        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
+        /* CSI0 */
+        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
+        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
+        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
+        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
+        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
+        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
+        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
+        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
+        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
+        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
+        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
+        /* DISPLAY */
+        MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+        MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+        MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+        MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+        MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+        MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+        MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+        MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+        MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+        MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+        MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+        MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+        MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+        MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+        MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+        MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+        MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+        MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+        MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+        MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+        MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+        MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+        MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+        MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+        MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+        MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+        MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+        MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+        /* Audio CLK*/
+        MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
+        /* PWM */
+        MX53_PAD_GPIO_1__PWM2_PWMO,
+        /* SPDIF */
+        MX53_PAD_GPIO_7__SPDIF_PLOCK,
+        MX53_PAD_GPIO_17__SPDIF_OUT1,
+        /* GPIO */
+        MX53_PAD_PATA_DA_1__GPIO7_7,
+        MX53_PAD_PATA_DA_2__GPIO7_8,
+        MX53_PAD_PATA_DATA5__GPIO2_5,
+        MX53_PAD_PATA_DATA6__GPIO2_6,
+        MX53_PAD_PATA_DATA14__GPIO2_14,
+        MX53_PAD_PATA_DATA15__GPIO2_15,
+        MX53_PAD_PATA_INTRQ__GPIO7_2,
+        MX53_PAD_EIM_WAIT__GPIO5_0,
+        MX53_PAD_NANDF_WP_B__GPIO6_9,
+        MX53_PAD_NANDF_RB0__GPIO6_10,
+        MX53_PAD_NANDF_CS1__GPIO6_14,
+        MX53_PAD_NANDF_CS2__GPIO6_15,
+        MX53_PAD_NANDF_CS3__GPIO6_16,
+        MX53_PAD_GPIO_5__GPIO1_5,
+        MX53_PAD_GPIO_16__GPIO7_11,
+        MX53_PAD_GPIO_8__GPIO1_8,
 };
-static const struct imxuart_platform_data mx53_loco_uart_data __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static inline void mx53_loco_init_uart(void)
-{
-        imx53_add_imx_uart(0, &mx53_loco_uart_data);
-        imx53_add_imx_uart(1, &mx53_loco_uart_data);
-        imx53_add_imx_uart(2, &mx53_loco_uart_data);
-}
 static inline void mx53_loco_fec_reset(void)
 {
        int ret;
@@ -85,13 +199,22 @@ static struct fec_platform_data mx53_loco_fec_data = {
        .phy = PHY_INTERFACE_MODE_RMII,
 };
+static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
+        .bitrate = 100000,
+};
 static void __init mx53_loco_board_init(void)
 {
        mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
                                        ARRAY_SIZE(mx53_loco_pads));
-        mx53_loco_init_uart();
+        imx53_add_imx_uart(0, NULL);
        mx53_loco_fec_reset();
        imx53_add_fec(&mx53_loco_fec_data);
+        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
+        imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
+        imx53_add_sdhci_esdhc_imx(0, NULL);
+        imx53_add_sdhci_esdhc_imx(2, NULL);
 }
 static void __init mx53_loco_timer_init(void)
@@ -105,7 +228,8 @@ static struct sys_timer mx53_loco_timer = {
 MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
        .map_io = mx53_map_io,
+        .init_early = imx53_init_early,
        .init_irq = mx53_init_irq,
-        .init_machine = mx53_loco_board_init,
        .timer = &mx53_loco_timer,
+        .init_machine = mx53_loco_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index 7970f7a48588..31e173267edf 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -39,20 +39,19 @@
 #define SMD_FEC_PHY_RST         IMX_GPIO_NR(7, 6)
 static iomux_v3_cfg_t mx53_smd_pads[] = {
-        MX53_PAD_CSI0_D10__UART1_TXD,
+        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-        MX53_PAD_CSI0_D11__UART1_RXD,
+        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-        MX53_PAD_ATA_DIOW__UART1_TXD,
-        MX53_PAD_ATA_DMACK__UART1_RXD,
+        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
-        MX53_PAD_ATA_DMARQ__UART2_TXD,
+        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-        MX53_PAD_ATA_DIOR__UART2_RTS,
+        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-        MX53_PAD_ATA_INTRQ__UART2_CTS,
+        MX53_PAD_PATA_DA_1__UART3_CTS,
+        MX53_PAD_PATA_DA_2__UART3_RTS,
-        MX53_PAD_ATA_CS_0__UART3_TXD,
+        /* I2C1 */
-        MX53_PAD_ATA_CS_1__UART3_RXD,
+        MX53_PAD_CSI0_DAT8__I2C1_SDA,
-        MX53_PAD_ATA_DA_1__UART3_CTS,
+        MX53_PAD_CSI0_DAT9__I2C1_SCL,
-        MX53_PAD_ATA_DA_2__UART3_RTS,
 };
 static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
@@ -61,8 +60,8 @@ static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
 static inline void mx53_smd_init_uart(void)
 {
-        imx53_add_imx_uart(0, &mx53_smd_uart_data);
+        imx53_add_imx_uart(0, NULL);
-        imx53_add_imx_uart(1, &mx53_smd_uart_data);
+        imx53_add_imx_uart(1, NULL);
        imx53_add_imx_uart(2, &mx53_smd_uart_data);
 }
@@ -85,6 +84,10 @@ static struct fec_platform_data mx53_smd_fec_data = {
        .phy = PHY_INTERFACE_MODE_RMII,
 };
+static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
+        .bitrate = 100000,
+};
 static void __init mx53_smd_board_init(void)
 {
        mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
@@ -92,6 +95,8 @@ static void __init mx53_smd_board_init(void)
        mx53_smd_init_uart();
        mx53_smd_fec_reset();
        imx53_add_fec(&mx53_smd_fec_data);
+        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
 }
 static void __init mx53_smd_timer_init(void)
@@ -105,7 +110,8 @@ static struct sys_timer mx53_smd_timer = {
 MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
        .map_io = mx53_map_io,
+        .init_early = imx53_init_early,
        .init_irq = mx53_init_irq,
-        .init_machine = mx53_smd_board_init,
        .timer = &mx53_smd_timer,
+        .init_machine = mx53_smd_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 0a19e7567c0b..652ace413825 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -42,6 +42,9 @@ static struct clk usboh3_clk;
 static struct clk emi_fast_clk;
 static struct clk ipu_clk;
 static struct clk mipi_hsc1_clk;
+static struct clk esdhc1_clk;
+static struct clk esdhc2_clk;
+static struct clk esdhc3_mx53_clk;
 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
@@ -867,10 +870,6 @@ static struct clk gpt_32k_clk = {
        .parent = &ckil_clk,
 };
-static struct clk kpp_clk = {
-        .id = 0,
-};
 static struct clk dummy_clk = {
        .id = 0,
 };
@@ -1147,10 +1146,80 @@ CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
 CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
 CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
+/* mx51 specific */
 CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
 CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
 CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
+static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+        else if (parent == &esdhc2_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+        return 0;
+}
+static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else if (parent == &esdhc2_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+        return 0;
+}
+/* mx53 specific */
+static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+        else if (parent == &esdhc3_mx53_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+        return 0;
+}
+CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else if (parent == &esdhc3_mx53_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+        return 0;
+}
 #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)          \
        static struct clk name = {                                      \
                .id             = i,                                    \
@@ -1255,9 +1324,62 @@ DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
        clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
 DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
+        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
+        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+/* mx51 specific */
 DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
        clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
+static struct clk esdhc3_clk = {
+        .id = 2,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc3_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc3_ipg_clk,
+};
+static struct clk esdhc4_clk = {
+        .id = 3,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc4_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc4_ipg_clk,
+};
+/* mx53 specific */
+static struct clk esdhc2_mx53_clk = {
+        .id = 2,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc2_mx53_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc3_ipg_clk,
+};
+DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
+        clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
+static struct clk esdhc4_mx53_clk = {
+        .id = 3,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc4_mx53_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc4_ipg_clk,
+};
 DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
 DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
 DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
@@ -1302,7 +1424,7 @@ static struct clk_lookup mx51_lookups[] = {
        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
-        _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
+        _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
        _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
@@ -1316,6 +1438,8 @@ static struct clk_lookup mx51_lookups[] = {
        _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
        _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_clk)
        _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
        _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
        _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
@@ -1336,10 +1460,14 @@ static struct clk_lookup mx53_lookups[] = {
        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
        _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk)
        _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
        _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
        _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
+        _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
 };
 static void clk_tree_init(void)
@@ -1427,6 +1555,14 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
        mx53_revision();
        clk_disable(&iim_clk);
+        /* Set SDHC parents to be PLL2 */
+        clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
+        clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
+        /* set SDHC root clock as 200MHZ*/
+        clk_set_rate(&esdhc1_clk, 200000000);
+        clk_set_rate(&esdhc3_mx53_clk, 200000000);
        /* System timer */
        mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
                MX53_INT_GPT);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index d40671da4372..df46b5e60857 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -78,11 +78,16 @@ static int get_mx53_srev(void)
        void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
-        if (rev == 0x0)
+        switch (rev) {
+        case 0x0:
                return IMX_CHIP_REVISION_1_0;
-        else if (rev == 0x10)
+        case 0x2:
                return IMX_CHIP_REVISION_2_0;
-        return 0;
+        case 0x3:
+                return IMX_CHIP_REVISION_2_1;
+        default:
+                return IMX_CHIP_REVISION_UNKNOWN;
+        }
 }
 /*
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index b462c22f53d8..87c0c58f27a7 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -217,9 +217,12 @@
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET      (20)
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK        (0x3 << 20)
 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL                   (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL        (0x1 << 19)
 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL                   (0x1 << 18)
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET      (16)
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK        (0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET       (16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK         (0x3 << 16)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET              (14)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK                (0x3 << 14)
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET              (12)
@@ -271,6 +274,10 @@
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK       (0x7 << 22)
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET     (19)
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK       (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET      (22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK        (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET      (19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK        (0x7 << 19)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET     (16)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK       (0x7 << 16)
 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET              (14)
diff --git a/arch/arm/mach-mx5/devices-mx50.h b/arch/arm/mach-mx5/devices-imx50.h
index 98ab07468a0e..c9e42823c7e3 100644
--- a/arch/arm/mach-mx5/devices-mx50.h
+++ b/arch/arm/mach-mx5/devices-imx50.h
@@ -24,3 +24,11 @@
 extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst;
 #define imx50_add_imx_uart(id, pdata)   \
        imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
+extern const struct imx_fec_data imx50_fec_data __initconst;
+#define imx50_add_fec(pdata)    \
+        imx_add_fec(&imx50_fec_data, pdata)
+extern const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst;
+#define imx50_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 8639735a117b..9251008dad1f 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -29,3 +29,7 @@ imx53_sdhci_esdhc_imx_data[] __initconst;
 extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
 #define imx53_add_ecspi(id, pdata)      \
        imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
+extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst;
+#define imx53_add_imx2_wdt(id, pdata)   \
+        imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-mx5/efika.h
new file mode 100644
index 000000000000..014aa985faae
--- /dev/null
+++ b/arch/arm/mach-mx5/efika.h
@@ -0,0 +1,10 @@
+#ifndef _EFIKA_H
+#define _EFIKA_H
+#define EFIKA_WLAN_EN           IMX_GPIO_NR(2, 16)
+#define EFIKA_WLAN_RESET        IMX_GPIO_NR(2, 10)
+#define EFIKA_USB_PHY_RESET     IMX_GPIO_NR(2, 9)
+void __init efika_board_common_init(void);
+#endif
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c
new file mode 100644
index 000000000000..7ce12c804a32
--- /dev/null
+++ b/arch/arm/mach-mx5/ehci.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+#define MXC_OTG_OFFSET                  0
+#define MXC_H1_OFFSET                   0x200
+#define MXC_H2_OFFSET                   0x400
+/* USB_CTRL */
+#define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
+#define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)               /* HOST1 power mask */
+/* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT               (1 << 5)        /* UH1 Disable Overcurrent Event */
+/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT          (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT           (1 << 4)
+#define MXC_USBCMD_OFFSET               0x140
+/* USBCMD */
+#define MXC_UCMD_ITC_NO_THRESHOLD_MASK  (~(0xff << 16)) /* Interrupt Threshold Control */
+int mx51_initialize_usb_hw(int port, unsigned int flags)
+{
+        unsigned int v;
+        void __iomem *usb_base;
+        void __iomem *usbotg_base;
+        void __iomem *usbother_base;
+        int ret = 0;
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base) {
+                printk(KERN_ERR "%s(): ioremap failed\n", __func__);
+                return -ENOMEM;
+        }
+        switch (port) {
+        case 0: /* OTG port */
+                usbotg_base = usb_base + MXC_OTG_OFFSET;
+                break;
+        case 1: /* Host 1 port */
+                usbotg_base = usb_base + MXC_H1_OFFSET;
+                break;
+        case 2: /* Host 2 port */
+                usbotg_base = usb_base + MXC_H2_OFFSET;
+                break;
+        default:
+                printk(KERN_ERR"%s no such port %d\n", __func__, port);
+                ret = -ENOENT;
+                goto error;
+        }
+        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+        switch (port) {
+        case 0: /*OTG port */
+                if (flags & MXC_EHCI_INTERNAL_PHY) {
+                        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+                        if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
+                                /* OC/USBPWR is not used */
+                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                        } else {
+                                /* OC/USBPWR is used */
+                                v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                        }
+                        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+                        if (flags & MXC_EHCI_WAKEUP_ENABLED)
+                                v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
+                        else
+                                v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
+                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                                v |= MXC_OTG_UCTRL_OPM_BIT;
+                        else
+                                v &= ~MXC_OTG_UCTRL_OPM_BIT;
+                        __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+                }
+                break;
+        case 1: /* Host 1 */
+                /*Host ULPI */
+                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                        /* HOST1 wakeup/ULPI intr enable */
+                        v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+                } else {
+                        /* HOST1 wakeup/ULPI intr disable */
+                        v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+                }
+                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+                else
+                        v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+                __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+                v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                        v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
+                else
+                        v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
+                __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+                v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
+                if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
+                        /* Interrupt Threshold Control:Immediate (no threshold) */
+                        v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
+                __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
+                break;
+        case 2: /* Host 2 ULPI */
+                v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                        /* HOST1 wakeup/ULPI intr enable */
+                        v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+                } else {
+                        /* HOST1 wakeup/ULPI intr disable */
+                        v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+                }
+                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                else
+                        v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
+                break;
+        }
+error:
+        iounmap(usb_base);
+        return ret;
+}
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
index 8c6540e58390..b9c363b514a9 100644
--- a/arch/arm/mach-mx5/mm-mx50.c
+++ b/arch/arm/mach-mx5/mm-mx50.c
@@ -26,6 +26,8 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
 /*
 * Define the MX50 memory map.
@@ -44,16 +46,27 @@ static struct map_desc mx50_io_desc[] __initdata = {
 */
 void __init mx50_map_io(void)
 {
+        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
+}
+void __init imx50_init_early(void)
+{
        mxc_set_cpu_type(MXC_CPU_MX50);
        mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
-        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
 }
-int imx50_register_gpios(void);
+static struct mxc_gpio_port imx50_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+};
 void __init mx50_init_irq(void)
 {
        tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
-        imx50_register_gpios();
+        mxc_gpio_init(imx50_gpio_ports, ARRAY_SIZE(imx50_gpio_ports));
 }
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 457f9f95204b..ff557301b42b 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -47,18 +47,26 @@ static struct map_desc mx53_io_desc[] __initdata = {
 */
 void __init mx51_map_io(void)
 {
+        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
+}
+void __init imx51_init_early(void)
+{
        mxc_set_cpu_type(MXC_CPU_MX51);
        mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
 }
 void __init mx53_map_io(void)
 {
+        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
+}
+void __init imx53_init_early(void)
+{
        mxc_set_cpu_type(MXC_CPU_MX53);
        mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR));
+        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
-        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
 }
 int imx51_register_gpios(void);
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
new file mode 100644
index 000000000000..51a67fc7f0ef
--- /dev/null
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -0,0 +1,636 @@
+/*
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <mach/ulpi.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach-types.h>
+#include "devices-imx51.h"
+#include "devices.h"
+#include "efika.h"
+#include "cpu_op-mx51.h"
+#define MX51_USB_CTRL_1_OFFSET          0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
+#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
+#define EFIKAMX_USB_HUB_RESET   IMX_GPIO_NR(1, 5)
+#define EFIKAMX_USBH1_STP       IMX_GPIO_NR(1, 27)
+#define EFIKAMX_SPI_CS0         IMX_GPIO_NR(4, 24)
+#define EFIKAMX_SPI_CS1         IMX_GPIO_NR(4, 25)
+#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
+static iomux_v3_cfg_t mx51efika_pads[] = {
+        /* UART1 */
+        MX51_PAD_UART1_RXD__UART1_RXD,
+        MX51_PAD_UART1_TXD__UART1_TXD,
+        MX51_PAD_UART1_RTS__UART1_RTS,
+        MX51_PAD_UART1_CTS__UART1_CTS,
+        /* SD 1 */
+        MX51_PAD_SD1_CMD__SD1_CMD,
+        MX51_PAD_SD1_CLK__SD1_CLK,
+        MX51_PAD_SD1_DATA0__SD1_DATA0,
+        MX51_PAD_SD1_DATA1__SD1_DATA1,
+        MX51_PAD_SD1_DATA2__SD1_DATA2,
+        MX51_PAD_SD1_DATA3__SD1_DATA3,
+        /* SD 2 */
+        MX51_PAD_SD2_CMD__SD2_CMD,
+        MX51_PAD_SD2_CLK__SD2_CLK,
+        MX51_PAD_SD2_DATA0__SD2_DATA0,
+        MX51_PAD_SD2_DATA1__SD2_DATA1,
+        MX51_PAD_SD2_DATA2__SD2_DATA2,
+        MX51_PAD_SD2_DATA3__SD2_DATA3,
+        /* SD/MMC WP/CD */
+        MX51_PAD_GPIO1_0__SD1_CD,
+        MX51_PAD_GPIO1_1__SD1_WP,
+        MX51_PAD_GPIO1_7__SD2_WP,
+        MX51_PAD_GPIO1_8__SD2_CD,
+        /* spi */
+        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+        MX51_PAD_CSPI1_SS0__GPIO4_24,
+        MX51_PAD_CSPI1_SS1__GPIO4_25,
+        MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
+        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+        MX51_PAD_GPIO1_6__GPIO1_6,
+        /* USB HOST1 */
+        MX51_PAD_USBH1_CLK__USBH1_CLK,
+        MX51_PAD_USBH1_DIR__USBH1_DIR,
+        MX51_PAD_USBH1_NXT__USBH1_NXT,
+        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+        /* USB HUB RESET */
+        MX51_PAD_GPIO1_5__GPIO1_5,
+        /* WLAN */
+        MX51_PAD_EIM_A22__GPIO2_16,
+        MX51_PAD_EIM_A16__GPIO2_10,
+        /* USB PHY RESET */
+        MX51_PAD_EIM_D27__GPIO2_9,
+};
+/* Serial ports */
+static const struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+/* This function is board specific as the bit mask for the plldiv will also
+ * be different for other Freescale SoCs, thus a common bitmask is not
+ * possible and cannot get place in /plat-mxc/ehci.c.
+ */
+static int initialize_otg_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base)
+                return -ENOMEM;
+        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
+        /* Set the PHY clock to 19.2MHz */
+        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+        v |= MX51_USB_PLL_DIV_19_2_MHZ;
+        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        iounmap(usb_base);
+        mdelay(10);
+        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
+}
+static struct mxc_usbh_platform_data dr_utmi_config = {
+        .init   = initialize_otg_port,
+        .portsc = MXC_EHCI_UTMI_16BIT,
+};
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+        iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
+        iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *socregs_base;
+        mxc_iomux_v3_setup_pad(usbh1gpio);
+        gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
+        gpio_direction_output(EFIKAMX_USBH1_STP, 0);
+        msleep(1);
+        gpio_set_value(EFIKAMX_USBH1_STP, 1);
+        msleep(1);
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
+        /* The clock for the USBH1 ULPI port will come externally */
+        /* from the PHY. */
+        v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
+        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
+                        socregs_base + MX51_USB_CTRL_1_OFFSET);
+        iounmap(usb_base);
+        gpio_free(EFIKAMX_USBH1_STP);
+        mxc_iomux_v3_setup_pad(usbh1stp);
+        mdelay(10);
+        return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD);
+}
+static struct mxc_usbh_platform_data usbh1_config = {
+        .init   = initialize_usbh1_port,
+        .portsc = MXC_EHCI_MODE_ULPI,
+};
+static void mx51_efika_hubreset(void)
+{
+        gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
+        gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
+        msleep(1);
+        gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
+        msleep(1);
+        gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
+}
+static void __init mx51_efika_usb(void)
+{
+        mx51_efika_hubreset();
+        /* pulling it low, means no USB at all... */
+        gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
+        gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
+        msleep(1);
+        gpio_set_value(EFIKA_USB_PHY_RESET, 1);
+        usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
+        mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        if (usbh1_config.otg)
+                mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+}
+static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
+        {
+         .name = "u-boot",
+         .offset = 0,
+         .size = SZ_256K,
+        },
+        {
+          .name = "config",
+          .offset = MTDPART_OFS_APPEND,
+          .size = SZ_64K,
+        },
+};
+static struct flash_platform_data mx51_efika_spi_flash_data = {
+        .name           = "spi_flash",
+        .parts          = mx51_efika_spi_nor_partitions,
+        .nr_parts       = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
+        .type           = "sst25vf032b",
+};
+static struct regulator_consumer_supply sw1_consumers[] = {
+        {
+                .supply = "cpu_vcc",
+        }
+};
+static struct regulator_consumer_supply vdig_consumers[] = {
+        /* sgtl5000 */
+        REGULATOR_SUPPLY("VDDA", "1-000a"),
+        REGULATOR_SUPPLY("VDDD", "1-000a"),
+};
+static struct regulator_consumer_supply vvideo_consumers[] = {
+        /* sgtl5000 */
+        REGULATOR_SUPPLY("VDDIO", "1-000a"),
+};
+static struct regulator_consumer_supply vsd_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"),
+        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
+};
+static struct regulator_consumer_supply pwgt1_consumer[] = {
+        {
+                .supply = "pwgt1",
+        }
+};
+static struct regulator_consumer_supply pwgt2_consumer[] = {
+        {
+                .supply = "pwgt2",
+        }
+};
+static struct regulator_consumer_supply coincell_consumer[] = {
+        {
+                .supply = "coincell",
+        }
+};
+static struct regulator_init_data sw1_init = {
+        .constraints = {
+                .name = "SW1",
+                .min_uV = 600000,
+                .max_uV = 1375000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .valid_modes_mask = 0,
+                .always_on = 1,
+                .boot_on = 1,
+                .state_mem = {
+                        .uV = 850000,
+                        .mode = REGULATOR_MODE_NORMAL,
+                        .enabled = 1,
+                },
+        },
+        .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+        .consumer_supplies = sw1_consumers,
+};
+static struct regulator_init_data sw2_init = {
+        .constraints = {
+                .name = "SW2",
+                .min_uV = 900000,
+                .max_uV = 1850000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on = 1,
+                .boot_on = 1,
+                .state_mem = {
+                        .uV = 950000,
+                        .mode = REGULATOR_MODE_NORMAL,
+                        .enabled = 1,
+                },
+        }
+};
+static struct regulator_init_data sw3_init = {
+        .constraints = {
+                .name = "SW3",
+                .min_uV = 1100000,
+                .max_uV = 1850000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on = 1,
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data sw4_init = {
+        .constraints = {
+                .name = "SW4",
+                .min_uV = 1100000,
+                .max_uV = 1850000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on = 1,
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data viohi_init = {
+        .constraints = {
+                .name = "VIOHI",
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+static struct regulator_init_data vusb_init = {
+        .constraints = {
+                .name = "VUSB",
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+static struct regulator_init_data swbst_init = {
+        .constraints = {
+                .name = "SWBST",
+        }
+};
+static struct regulator_init_data vdig_init = {
+        .constraints = {
+                .name = "VDIG",
+                .min_uV = 1050000,
+                .max_uV = 1800000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
+        .consumer_supplies = vdig_consumers,
+};
+static struct regulator_init_data vpll_init = {
+        .constraints = {
+                .name = "VPLL",
+                .min_uV = 1050000,
+                .max_uV = 1800000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+static struct regulator_init_data vusb2_init = {
+        .constraints = {
+                .name = "VUSB2",
+                .min_uV = 2400000,
+                .max_uV = 2775000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+static struct regulator_init_data vvideo_init = {
+        .constraints = {
+                .name = "VVIDEO",
+                .min_uV = 2775000,
+                .max_uV = 2775000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .apply_uV = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
+        .consumer_supplies = vvideo_consumers,
+};
+static struct regulator_init_data vaudio_init = {
+        .constraints = {
+                .name = "VAUDIO",
+                .min_uV = 2300000,
+                .max_uV = 3000000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data vsd_init = {
+        .constraints = {
+                .name = "VSD",
+                .min_uV = 1800000,
+                .max_uV = 3150000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE,
+                .boot_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
+        .consumer_supplies = vsd_consumers,
+};
+static struct regulator_init_data vcam_init = {
+        .constraints = {
+                .name = "VCAM",
+                .min_uV = 2500000,
+                .max_uV = 3000000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE |
+                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+                .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data vgen1_init = {
+        .constraints = {
+                .name = "VGEN1",
+                .min_uV = 1200000,
+                .max_uV = 3150000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+static struct regulator_init_data vgen2_init = {
+        .constraints = {
+                .name = "VGEN2",
+                .min_uV = 1200000,
+                .max_uV = 3150000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+static struct regulator_init_data vgen3_init = {
+        .constraints = {
+                .name = "VGEN3",
+                .min_uV = 1800000,
+                .max_uV = 2900000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+static struct regulator_init_data gpo1_init = {
+        .constraints = {
+                .name = "GPO1",
+        }
+};
+static struct regulator_init_data gpo2_init = {
+        .constraints = {
+                .name = "GPO2",
+        }
+};
+static struct regulator_init_data gpo3_init = {
+        .constraints = {
+                .name = "GPO3",
+        }
+};
+static struct regulator_init_data gpo4_init = {
+        .constraints = {
+                .name = "GPO4",
+        }
+};
+static struct regulator_init_data pwgt1_init = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .boot_on        = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
+        .consumer_supplies = pwgt1_consumer,
+};
+static struct regulator_init_data pwgt2_init = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .boot_on        = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
+        .consumer_supplies = pwgt2_consumer,
+};
+static struct regulator_init_data vcoincell_init = {
+        .constraints = {
+                .name = "COINCELL",
+                .min_uV = 3000000,
+                .max_uV = 3000000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
+        .consumer_supplies = coincell_consumer,
+};
+static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
+        { .id = MC13892_SW1,            .init_data =  &sw1_init },
+        { .id = MC13892_SW2,            .init_data =  &sw2_init },
+        { .id = MC13892_SW3,            .init_data =  &sw3_init },
+        { .id = MC13892_SW4,            .init_data =  &sw4_init },
+        { .id = MC13892_SWBST,          .init_data =  &swbst_init },
+        { .id = MC13892_VIOHI,          .init_data =  &viohi_init },
+        { .id = MC13892_VPLL,           .init_data =  &vpll_init },
+        { .id = MC13892_VDIG,           .init_data =  &vdig_init },
+        { .id = MC13892_VSD,            .init_data =  &vsd_init },
+        { .id = MC13892_VUSB2,          .init_data =  &vusb2_init },
+        { .id = MC13892_VVIDEO,         .init_data =  &vvideo_init },
+        { .id = MC13892_VAUDIO,         .init_data =  &vaudio_init },
+        { .id = MC13892_VCAM,           .init_data =  &vcam_init },
+        { .id = MC13892_VGEN1,          .init_data =  &vgen1_init },
+        { .id = MC13892_VGEN2,          .init_data =  &vgen2_init },
+        { .id = MC13892_VGEN3,          .init_data =  &vgen3_init },
+        { .id = MC13892_VUSB,           .init_data =  &vusb_init },
+        { .id = MC13892_GPO1,           .init_data =  &gpo1_init },
+        { .id = MC13892_GPO2,           .init_data =  &gpo2_init },
+        { .id = MC13892_GPO3,           .init_data =  &gpo3_init },
+        { .id = MC13892_GPO4,           .init_data =  &gpo4_init },
+        { .id = MC13892_PWGT1SPI,       .init_data = &pwgt1_init },
+        { .id = MC13892_PWGT2SPI,       .init_data = &pwgt2_init },
+        { .id = MC13892_VCOINCELL,      .init_data = &vcoincell_init },
+};
+static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
+        .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
+        .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
+        .regulators = mx51_efika_regulators,
+};
+static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
+        {
+                .modalias = "m25p80",
+                .max_speed_hz = 25000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .platform_data = &mx51_efika_spi_flash_data,
+                .irq = -1,
+        },
+        {
+                .modalias = "mc13892",
+                .max_speed_hz = 1000000,
+                .bus_num = 0,
+                .chip_select = 0,
+                .platform_data = &mx51_efika_mc13892_data,
+                .irq = gpio_to_irq(EFIKAMX_PMIC),
+        },
+};
+static int mx51_efika_spi_cs[] = {
+        EFIKAMX_SPI_CS0,
+        EFIKAMX_SPI_CS1,
+};
+static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
+        .chipselect     = mx51_efika_spi_cs,
+        .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
+};
+void __init efika_board_common_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
+                                        ARRAY_SIZE(mx51efika_pads));
+        imx51_add_imx_uart(0, &uart_pdata);
+        mx51_efika_usb();
+        imx51_add_sdhci_esdhc_imx(0, NULL);
+        /* FIXME: comes from original code. check this. */
+        if (mx51_revision() < IMX_CHIP_REVISION_2_0)
+                sw2_init.constraints.state_mem.uV = 1100000;
+        else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
+                sw2_init.constraints.state_mem.uV = 1250000;
+                sw1_init.constraints.state_mem.uV = 1000000;
+        }
+        if (machine_is_mx51_efikasb())
+                vgen1_init.constraints.max_uV = 1200000;
+        gpio_request(EFIKAMX_PMIC, "pmic irq");
+        gpio_direction_input(EFIKAMX_PMIC);
+        spi_register_board_info(mx51_efika_spi_board_info,
+                ARRAY_SIZE(mx51_efika_spi_board_info));
+        imx51_add_ecspi(0, &mx51_efika_spi_pdata);
+#if defined(CONFIG_CPU_FREQ_IMX)
+        get_cpu_op = mx51_get_cpu_op;
+#endif
+}
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
index 405d9b19d891..66fc41cbf2ca 100644
--- a/arch/arm/mach-mxc91231/iomux.c
+++ b/arch/arm/mach-mxc91231/iomux.c
@@ -50,7 +50,7 @@ unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
 /*
 * set the mode for a IOMUX pin.
 */
-int mxc_iomux_mode(const unsigned int pin_mode)
+int mxc_iomux_mode(unsigned int pin_mode)
 {
        u32 side, field, l, mode, ret = 0;
        void __iomem *reg;
@@ -114,7 +114,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad);
 *      - reserves the pin so that it is not claimed by another driver
 *      - setups the iomux according to the configuration
 */
-int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
+int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label)
 {
        unsigned pad = PIN_GLOBAL_NUM(pin_mode);
        if (pad >= (PIN_MAX + 1)) {
@@ -134,10 +134,10 @@ int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
 }
 EXPORT_SYMBOL(mxc_iomux_alloc_pin);
-int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
                const char *label)
 {
-        unsigned int *p = pin_list;
+        const unsigned int *p = pin_list;
        int i;
        int ret = -EINVAL;
@@ -155,7 +155,7 @@ setup_error:
 }
 EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
-void mxc_iomux_release_pin(const unsigned int pin_mode)
+void mxc_iomux_release_pin(unsigned int pin_mode)
 {
        unsigned pad = PIN_GLOBAL_NUM(pin_mode);
@@ -164,9 +164,9 @@ void mxc_iomux_release_pin(const unsigned int pin_mode)
 }
 EXPORT_SYMBOL(mxc_iomux_release_pin);
-void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
+void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
 {
-        unsigned int *p = pin_list;
+        const unsigned int *p = pin_list;
        int i;
        for (i = 0; i < count; i++) {
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
index 395d83be8c98..f31a45e5a0b8 100644
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -53,9 +53,10 @@ struct sys_timer zn5_timer = {
 };
 MACHINE_START(MAGX_ZN5, "Motorola Zn5")
-        .boot_params    = MXC91231_PHYS_OFFSET + 0x100,
+        .boot_params = MXC91231_PHYS_OFFSET + 0x100,
-        .map_io         = mxc91231_map_io,
+        .map_io = mxc91231_map_io,
-        .init_irq       = mxc91231_init_irq,
+        .init_early = mxc91231_init_early,
-        .timer          = &zn5_timer,
+        .init_irq = mxc91231_init_irq,
-        .init_machine   = zn5_init,
+        .timer = &zn5_timer,
+        .init_machine = zn5_init,
 MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index 7652c301da88..a77f6daf6a26 100644
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -45,11 +45,14 @@ static struct map_desc mxc91231_io_desc[] __initdata = {
 */
 void __init mxc91231_map_io(void)
 {
-        mxc_set_cpu_type(MXC_CPU_MXC91231);
        iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
 }
+void __init mxc91231_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MXC91231);
+}
 int mxc91231_register_gpios(void);
 void __init mxc91231_init_irq(void)
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 8bfc8df54617..4f6f174af6c8 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -2,13 +2,18 @@ if ARCH_MXS
 source "arch/arm/mach-mxs/devices/Kconfig"
+config MXS_OCOTP
+        bool
 config SOC_IMX23
        bool
        select CPU_ARM926T
+        select HAVE_PWM
 config SOC_IMX28
        bool
        select CPU_ARM926T
+        select HAVE_PWM
 comment "MXS platforms:"
@@ -16,6 +21,8 @@ config MACH_MX23EVK
        bool "Support MX23EVK Platform"
        select SOC_IMX23
        select MXS_HAVE_AMBA_DUART
+        select MXS_HAVE_PLATFORM_AUART
+        select MXS_HAVE_PLATFORM_MXSFB
        default y
        help
          Include support for MX23EVK platform. This includes specific
@@ -25,10 +32,27 @@ config MACH_MX28EVK
        bool "Support MX28EVK Platform"
        select SOC_IMX28
        select MXS_HAVE_AMBA_DUART
+        select MXS_HAVE_PLATFORM_AUART
        select MXS_HAVE_PLATFORM_FEC
+        select MXS_HAVE_PLATFORM_FLEXCAN
+        select MXS_HAVE_PLATFORM_MXSFB
+        select MXS_OCOTP
        default y
        help
          Include support for MX28EVK platform. This includes specific
          configurations for the board and its peripherals.
+config MODULE_TX28
+        bool
+        select SOC_IMX28
+        select MXS_HAVE_AMBA_DUART
+        select MXS_HAVE_PLATFORM_AUART
+        select MXS_HAVE_PLATFORM_FEC
+        select MXS_HAVE_PLATFORM_MXS_I2C
+        select MXS_HAVE_PLATFORM_MXS_PWM
+config MACH_TX28
+        bool "Ka-Ro TX28 module"
+        select MODULE_TX28
 endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 39d3f9c2a841..2f1f6141ca71 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,10 +1,15 @@
 # Common support
 obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
+obj-$(CONFIG_MXS_OCOTP) += ocotp.o
+obj-$(CONFIG_PM) += pm.o
 obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
 obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
+obj-$(CONFIG_MODULE_TX28) += module-tx28.o
+obj-$(CONFIG_MACH_TX28)    += mach-tx28.o
 obj-y += devices/
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index ca72a05ed9c1..d133c7f30940 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -442,11 +442,18 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
        /* for amba-pl011 driver */
        _REGISTER_CLOCK("duart", NULL, uart_clk)
+        _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
        _REGISTER_CLOCK("rtc", NULL, rtc_clk)
-        _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
+        _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
+        _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
        _REGISTER_CLOCK(NULL, "usb", usb_clk)
        _REGISTER_CLOCK(NULL, "audio", audio_clk)
-        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
+        _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
 };
 static int clk_misc_init(void)
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index fd1c4c54b8e5..5e489a2b2023 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -609,17 +609,30 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("duart", NULL, uart_clk)
        _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
        _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
+        _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
+        _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
+        _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
+        _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
+        _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
        _REGISTER_CLOCK("rtc", NULL, rtc_clk)
        _REGISTER_CLOCK("pll2", NULL, pll2_clk)
-        _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
+        _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
-        _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
+        _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
-        _REGISTER_CLOCK(NULL, "can0", can0_clk)
+        _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
-        _REGISTER_CLOCK(NULL, "can1", can1_clk)
+        _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
        _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
        _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
-        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
        _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
        _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
+        _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
 };
 static int clk_misc_init(void)
@@ -737,6 +750,8 @@ int __init mx28_clocks_init(void)
        clk_enable(&emi_clk);
        clk_enable(&uart_clk);
+        clk_set_parent(&lcdif_clk, &ref_pix_clk);
        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
        mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 1256788561d0..c7e14f4e3669 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -10,7 +10,18 @@
 */
 #include <mach/mx23.h>
 #include <mach/devices-common.h>
+#include <mach/mxsfb.h>
 extern const struct amba_device mx23_duart_device __initconst;
 #define mx23_add_duart() \
        mxs_add_duart(&mx23_duart_device)
+extern const struct mxs_auart_data mx23_auart_data[] __initconst;
+#define mx23_add_auart(id)      mxs_add_auart(&mx23_auart_data[id])
+#define mx23_add_auart0()               mx23_add_auart(0)
+#define mx23_add_auart1()               mx23_add_auart(1)
+#define mx23_add_mxs_pwm(id)            mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id)
+struct platform_device *__init mx23_add_mxsfb(
+                const struct mxsfb_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 33773a6333a2..9d08555c4cf0 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -10,11 +10,34 @@
 */
 #include <mach/mx28.h>
 #include <mach/devices-common.h>
+#include <mach/mxsfb.h>
 extern const struct amba_device mx28_duart_device __initconst;
 #define mx28_add_duart() \
        mxs_add_duart(&mx28_duart_device)
+extern const struct mxs_auart_data mx28_auart_data[] __initconst;
+#define mx28_add_auart(id)      mxs_add_auart(&mx28_auart_data[id])
+#define mx28_add_auart0()               mx28_add_auart(0)
+#define mx28_add_auart1()               mx28_add_auart(1)
+#define mx28_add_auart2()               mx28_add_auart(2)
+#define mx28_add_auart3()               mx28_add_auart(3)
+#define mx28_add_auart4()               mx28_add_auart(4)
 extern const struct mxs_fec_data mx28_fec_data[] __initconst;
 #define mx28_add_fec(id, pdata) \
        mxs_add_fec(&mx28_fec_data[id], pdata)
+extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
+#define mx28_add_flexcan(id, pdata)     \
+        mxs_add_flexcan(&mx28_flexcan_data[id], pdata)
+#define mx28_add_flexcan0(pdata)        mx28_add_flexcan(0, pdata)
+#define mx28_add_flexcan1(pdata)        mx28_add_flexcan(1, pdata)
+extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
+#define mx28_add_mxs_i2c(id)            mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
+#define mx28_add_mxs_pwm(id)            mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id)
+struct platform_device *__init mx28_add_mxsfb(
+                const struct mxsfb_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
index c20d54740b0b..cfdb6b284702 100644
--- a/arch/arm/mach-mxs/devices.c
+++ b/arch/arm/mach-mxs/devices.c
@@ -66,6 +66,8 @@ struct platform_device *__init mxs_add_platform_device_dmamask(
        ret = platform_device_add(pdev);
        if (ret) {
 err:
+                if (dmamask)
+                        kfree(pdev->dev.dma_mask);
                platform_device_put(pdev);
                return ERR_PTR(ret);
        }
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index cf7dc1ae575b..1451ad060d82 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -2,5 +2,21 @@ config MXS_HAVE_AMBA_DUART
        bool
        select ARM_AMBA
+config MXS_HAVE_PLATFORM_AUART
+        bool
 config MXS_HAVE_PLATFORM_FEC
        bool
+config MXS_HAVE_PLATFORM_FLEXCAN
+        select HAVE_CAN_FLEXCAN if CAN
+        bool
+config MXS_HAVE_PLATFORM_MXS_I2C
+        bool
+config MXS_HAVE_PLATFORM_MXS_PWM
+        bool
+config MXS_HAVE_PLATFORM_MXSFB
+        bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index d0a09f6934b8..0d9bea30b0a2 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -1,2 +1,8 @@
 obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
+obj-y += platform-dma.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c
new file mode 100644
index 000000000000..796606cce0ce
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-auart.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+#define mxs_auart_data_entry_single(soc, _id, hwid)                     \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _AUART ## hwid ## _BASE_ADDR,          \
+                .irq = soc ## _INT_AUART ## hwid,                       \
+        }
+#define mxs_auart_data_entry(soc, _id, hwid)                            \
+        [_id] = mxs_auart_data_entry_single(soc, _id, hwid)
+#ifdef CONFIG_SOC_IMX23
+const struct mxs_auart_data mx23_auart_data[] __initconst = {
+#define mx23_auart_data_entry(_id, hwid)                                \
+        mxs_auart_data_entry(MX23, _id, hwid)
+        mx23_auart_data_entry(0, 1),
+        mx23_auart_data_entry(1, 2),
+};
+#endif
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_auart_data mx28_auart_data[] __initconst = {
+#define mx28_auart_data_entry(_id)                                      \
+        mxs_auart_data_entry(MX28, _id, _id)
+        mx28_auart_data_entry(0),
+        mx28_auart_data_entry(1),
+        mx28_auart_data_entry(2),
+        mx28_auart_data_entry(3),
+        mx28_auart_data_entry(4),
+};
+#endif
+struct platform_device *__init mxs_add_auart(
+                const struct mxs_auart_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return mxs_add_platform_device_dmamask("mxs-auart", data->id,
+                                        res, ARRAY_SIZE(res), NULL, 0,
+                                        DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
new file mode 100644
index 000000000000..295c4424d5d9
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-dma.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+static struct platform_device *__init mxs_add_dma(const char *devid,
+                                                resource_size_t base)
+{
+        struct resource res[] = {
+                {
+                        .start = base,
+                        .end = base + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }
+        };
+        return mxs_add_platform_device_dmamask(devid, -1,
+                                res, ARRAY_SIZE(res), NULL, 0,
+                                DMA_BIT_MASK(32));
+}
+static int __init mxs_add_mxs_dma(void)
+{
+        char *apbh = "mxs-dma-apbh";
+        char *apbx = "mxs-dma-apbx";
+        if (cpu_is_mx23()) {
+                mxs_add_dma(apbh, MX23_APBH_DMA_BASE_ADDR);
+                mxs_add_dma(apbx, MX23_APBX_DMA_BASE_ADDR);
+        }
+        if (cpu_is_mx28()) {
+                mxs_add_dma(apbh, MX28_APBH_DMA_BASE_ADDR);
+                mxs_add_dma(apbx, MX28_APBX_DMA_BASE_ADDR);
+        }
+        return 0;
+}
+arch_initcall(mxs_add_mxs_dma);
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
index c42dff72b46c..9859cf283335 100644
--- a/arch/arm/mach-mxs/devices/platform-fec.c
+++ b/arch/arm/mach-mxs/devices/platform-fec.c
@@ -45,6 +45,7 @@ struct platform_device *__init mxs_add_fec(
                },
        };
-        return mxs_add_platform_device("imx28-fec", data->id,
+        return mxs_add_platform_device_dmamask("imx28-fec", data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
+                        DMA_BIT_MASK(32));
 }
diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c
new file mode 100644
index 000000000000..43a6b4bae6fe
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-flexcan.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2010, 2011 Pengutronix,
+ *                          Marc Kleine-Budde <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)           \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR,           \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_CAN ## _hwid,                        \
+        }
+#define mxs_flexcan_data_entry(soc, _id, _hwid, _size)                  \
+        [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = {
+#define mx28_flexcan_data_entry(_id, _hwid)                             \
+        mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K)
+        mx28_flexcan_data_entry(0, 0),
+        mx28_flexcan_data_entry(1, 1),
+};
+#endif /* ifdef CONFIG_SOC_IMX28 */
+struct platform_device *__init mxs_add_flexcan(
+                const struct mxs_flexcan_data *data,
+                const struct flexcan_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return mxs_add_platform_device("flexcan", data->id,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
new file mode 100644
index 000000000000..eab3a06836d6
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2011 Pengutronix
+ * Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+#define mxs_i2c_data_entry_single(soc, _id)                             \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _I2C ## _id ## _BASE_ADDR,             \
+                .errirq = soc ## _INT_I2C ## _id ## _ERROR,             \
+                .dmairq = soc ## _INT_I2C ## _id ## _DMA,               \
+        }
+#define mxs_i2c_data_entry(soc, _id)                                    \
+        [_id] = mxs_i2c_data_entry_single(soc, _id)
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
+        mxs_i2c_data_entry(MX28, 0),
+        mxs_i2c_data_entry(MX28, 1),
+};
+#endif
+struct platform_device *__init mxs_add_mxs_i2c(const struct mxs_i2c_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->errirq,
+                        .end = data->errirq,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->dmairq,
+                        .end = data->dmairq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return mxs_add_platform_device("mxs-i2c", data->id, res,
+                                        ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
new file mode 100644
index 000000000000..680f5a902936
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/devices-common.h>
+struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id)
+{
+        struct resource res = {
+                .flags = IORESOURCE_MEM,
+        };
+        res.start = iobase + 0x10 + 0x20 * id;
+        res.end = res.start + 0x1f;
+        return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0);
+}
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
new file mode 100644
index 000000000000..bf72c9b8dbdd
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+#include <mach/mxsfb.h>
+#ifdef CONFIG_SOC_IMX23
+struct platform_device *__init mx23_add_mxsfb(
+                const struct mxsfb_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = MX23_LCDIF_BASE_ADDR,
+                        .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+        };
+        return mxs_add_platform_device_dmamask("imx23-fb", -1,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
+#endif /* ifdef CONFIG_SOC_IMX23 */
+#ifdef CONFIG_SOC_IMX28
+struct platform_device *__init mx28_add_mxsfb(
+                const struct mxsfb_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = MX28_LCDIF_BASE_ADDR,
+                        .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+        };
+        return mxs_add_platform_device_dmamask("imx28-fb", -1,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
+#endif /* ifdef CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
index cb0c0e83a527..5120ab58707c 100644
--- a/arch/arm/mach-mxs/gpio.c
+++ b/arch/arm/mach-mxs/gpio.c
@@ -182,6 +182,7 @@ static int mxs_gpio_set_wake_irq(u32 irq, u32 enable)
 }
 static struct irq_chip gpio_irq_chip = {
+        .name = "mxs gpio",
        .ack = mxs_gpio_ack_irq,
        .mask = mxs_gpio_mask_irq,
        .unmask = mxs_gpio_unmask_irq,
@@ -289,39 +290,42 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
        return 0;
 }
-#define DEFINE_MXS_GPIO_PORT(soc, _id)                                  \
+#define MX23_GPIO_BASE  MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR)
+#define MX28_GPIO_BASE  MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR)
+#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id)                          \
        {                                                               \
                .chip.label = "gpio-" #_id,                             \
                .id = _id,                                              \
-                .irq = soc ## _INT_GPIO ## _id,                         \
+                .irq = _irq,                                            \
-                .base = soc ## _IO_ADDRESS(                             \
+                .base = _base,                                          \
-                                soc ## _PINCTRL ## _BASE_ADDR),         \
                .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32,   \
        }
-#define DEFINE_REGISTER_FUNCTION(prefix)                                \
-int __init prefix ## _register_gpios(void)                              \
-{                                                                       \
-        return mxs_gpio_init(prefix ## _gpio_ports,                     \
-                        ARRAY_SIZE(prefix ## _gpio_ports));             \
-}
 #ifdef CONFIG_SOC_IMX23
 static struct mxs_gpio_port mx23_gpio_ports[] = {
-        DEFINE_MXS_GPIO_PORT(MX23, 0),
+        DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0),
-        DEFINE_MXS_GPIO_PORT(MX23, 1),
+        DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1),
-        DEFINE_MXS_GPIO_PORT(MX23, 2),
+        DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2),
 };
-DEFINE_REGISTER_FUNCTION(mx23)
+int __init mx23_register_gpios(void)
+{
+        return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports));
+}
 #endif
 #ifdef CONFIG_SOC_IMX28
 static struct mxs_gpio_port mx28_gpio_ports[] = {
-        DEFINE_MXS_GPIO_PORT(MX28, 0),
+        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0),
-        DEFINE_MXS_GPIO_PORT(MX28, 1),
+        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1),
-        DEFINE_MXS_GPIO_PORT(MX28, 2),
+        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2),
-        DEFINE_MXS_GPIO_PORT(MX28, 3),
+        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3),
-        DEFINE_MXS_GPIO_PORT(MX28, 4),
+        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4),
 };
-DEFINE_REGISTER_FUNCTION(mx28)
+int __init mx28_register_gpios(void)
+{
+        return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports));
+}
 #endif
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 59133eb3cc96..635bb5d9a20a 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -13,6 +13,7 @@
 struct clk;
+extern const u32 *mxs_get_ocotp(void);
 extern int mxs_reset_block(void __iomem *);
 extern void mxs_timer_init(struct clk *, int);
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 6c3d1a103433..71f24484b044 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -30,6 +30,16 @@ int __init mxs_add_amba_device(const struct amba_device *dev);
 /* duart */
 int __init mxs_add_duart(const struct amba_device *dev);
+/* auart */
+struct mxs_auart_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init mxs_add_auart(
+                const struct mxs_auart_data *data);
 /* fec */
 #include <linux/fec.h>
 struct mxs_fec_data {
@@ -41,3 +51,28 @@ struct mxs_fec_data {
 struct platform_device *__init mxs_add_fec(
                const struct mxs_fec_data *data,
                const struct fec_platform_data *pdata);
+/* flexcan */
+#include <linux/can/platform/flexcan.h>
+struct mxs_flexcan_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init mxs_add_flexcan(
+                const struct mxs_flexcan_data *data,
+                const struct flexcan_platform_data *pdata);
+/* i2c */
+struct mxs_i2c_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t errirq;
+        resource_size_t dmairq;
+};
+struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data);
+/* pwm */
+struct platform_device *__init mxs_add_mxs_pwm(
+                resource_size_t iobase, int id);
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
index 94e5dd83cdb8..b0190a4822f2 100644
--- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h
+++ b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
@@ -254,102 +254,102 @@
 #define MX23_PAD_ROTARYB__GPMI_CE3N             MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
 /* MUXSEL_GPIO */
-#define MX23_PAD_GPMI_D00__GPO_0_0              MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D00__GPIO_0_0             MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D01__GPO_0_1              MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D01__GPIO_0_1             MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D02__GPO_0_2              MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D02__GPIO_0_2             MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D03__GPO_0_3              MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D03__GPIO_0_3             MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D04__GPO_0_4              MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D04__GPIO_0_4             MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D05__GPO_0_5              MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D05__GPIO_0_5             MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D06__GPO_0_6              MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D06__GPIO_0_6             MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D07__GPO_0_7              MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D07__GPIO_0_7             MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D08__GPO_0_8              MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D08__GPIO_0_8             MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D09__GPO_0_9              MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D09__GPIO_0_9             MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D10__GPO_0_10             MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D10__GPIO_0_10            MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D11__GPO_0_11             MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D11__GPIO_0_11            MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D12__GPO_0_12             MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D12__GPIO_0_12            MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D13__GPO_0_13             MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D13__GPIO_0_13            MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D14__GPO_0_14             MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D14__GPIO_0_14            MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D15__GPO_0_15             MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D15__GPIO_0_15            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CLE__GPO_0_16             MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CLE__GPIO_0_16            MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_ALE__GPO_0_17             MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_ALE__GPIO_0_17            MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE2N__GPO_0_18            MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE2N__GPIO_0_18           MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY0__GPO_0_19            MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY0__GPIO_0_19           MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY1__GPO_0_20            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY1__GPIO_0_20           MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY2__GPO_0_21            MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY2__GPIO_0_21           MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY3__GPO_0_22            MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY3__GPIO_0_22           MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WPN__GPO_0_23             MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WPN__GPIO_0_23            MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WRN__GPO_0_24             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WRN__GPIO_0_24            MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDN__GPO_0_25             MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDN__GPIO_0_25            MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_CTS__GPO_0_26           MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_CTS__GPIO_0_26          MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RTS__GPO_0_27           MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RTS__GPIO_0_27          MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RX__GPO_0_28            MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RX__GPIO_0_28           MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_TX__GPO_0_29            MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_TX__GPIO_0_29           MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SCL__GPO_0_30              MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SCL__GPIO_0_30             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SDA__GPO_0_31              MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SDA__GPIO_0_31             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D00__GPO_1_0               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D00__GPIO_1_0              MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D01__GPO_1_1               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D01__GPIO_1_1              MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D02__GPO_1_2               MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D02__GPIO_1_2              MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D03__GPO_1_3               MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D03__GPIO_1_3              MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D04__GPO_1_4               MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D04__GPIO_1_4              MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D05__GPO_1_5               MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D05__GPIO_1_5              MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D06__GPO_1_6               MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D06__GPIO_1_6              MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D07__GPO_1_7               MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D07__GPIO_1_7              MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D08__GPO_1_8               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D08__GPIO_1_8              MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D09__GPO_1_9               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D09__GPIO_1_9              MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D10__GPO_1_10              MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D10__GPIO_1_10             MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D11__GPO_1_11              MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D11__GPIO_1_11             MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D12__GPO_1_12              MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D12__GPIO_1_12             MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D13__GPO_1_13              MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D13__GPIO_1_13             MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D14__GPO_1_14              MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D14__GPIO_1_14             MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D15__GPO_1_15              MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D15__GPIO_1_15             MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D16__GPO_1_16              MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D16__GPIO_1_16             MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D17__GPO_1_17              MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D17__GPIO_1_17             MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RESET__GPO_1_18            MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RESET__GPIO_1_18           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RS__GPO_1_19               MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RS__GPIO_1_19              MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_WR__GPO_1_20               MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_WR__GPIO_1_20              MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_CS__GPO_1_21               MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_CS__GPIO_1_21              MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_DOTCK__GPO_1_22            MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_DOTCK__GPIO_1_22           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_ENABLE__GPO_1_23           MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_ENABLE__GPIO_1_23          MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_HSYNC__GPO_1_24            MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_HSYNC__GPIO_1_24           MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_VSYNC__GPO_1_25            MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_VSYNC__GPIO_1_25           MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM0__GPO_1_26                 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM0__GPIO_1_26                MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM1__GPO_1_27                 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM1__GPIO_1_27                MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM2__GPO_1_28                 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM2__GPIO_1_28                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM3__GPO_1_29                 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM3__GPIO_1_29                MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM4__GPO_1_30                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM4__GPIO_1_30                MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_CMD__GPO_2_0              MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_CMD__GPIO_2_0             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DETECT__GPO_2_1           MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DETECT__GPIO_2_1          MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA0__GPO_2_2            MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA0__GPIO_2_2           MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA1__GPO_2_3            MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA1__GPIO_2_3           MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA2__GPO_2_4            MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA2__GPIO_2_4           MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA3__GPO_2_5            MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA3__GPIO_2_5           MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_SCK__GPO_2_6              MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_SCK__GPIO_2_6             MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYA__GPO_2_7               MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYA__GPIO_2_7              MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYB__GPO_2_8               MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYB__GPIO_2_8              MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A00__GPO_2_9               MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A00__GPIO_2_9              MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A01__GPO_2_10              MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A01__GPIO_2_10             MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A02__GPO_2_11              MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A02__GPIO_2_11             MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A03__GPO_2_12              MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A03__GPIO_2_12             MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A04__GPO_2_13              MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A04__GPIO_2_13             MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A05__GPO_2_14              MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A05__GPIO_2_14             MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A06__GPO_2_15              MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A06__GPIO_2_15             MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A07__GPO_2_16              MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A07__GPIO_2_16             MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A08__GPO_2_17              MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A08__GPIO_2_17             MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A09__GPO_2_18              MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A09__GPIO_2_18             MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A10__GPO_2_19              MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A10__GPIO_2_19             MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A11__GPO_2_20              MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A11__GPIO_2_20             MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A12__GPO_2_21              MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A12__GPIO_2_21             MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA0__GPO_2_22              MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA0__GPIO_2_22             MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA1__GPO_2_23              MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA1__GPIO_2_23             MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CASN__GPO_2_24             MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CASN__GPIO_2_24            MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE0N__GPO_2_25             MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE0N__GPIO_2_25            MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE1N__GPO_2_26             MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE1N__GPIO_2_26            MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE1N__GPO_2_27            MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE1N__GPIO_2_27           MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE0N__GPO_2_28            MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE0N__GPIO_2_28           MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CKE__GPO_2_29              MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CKE__GPIO_2_29             MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_RASN__GPO_2_30             MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_RASN__GPIO_2_30            MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_WEN__GPO_2_31              MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_WEN__GPIO_2_31             MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
 #endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
index fe558e3c5a9a..7abdf58b8bb7 100644
--- a/arch/arm/mach-mxs/include/mach/iomux.h
+++ b/arch/arm/mach-mxs/include/mach/iomux.h
@@ -91,6 +91,9 @@ typedef u32 iomux_cfg_t;
 #define MXS_PAD_PULLUP  ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
                                        MXS_PAD_PULL_VALID_MASK)
+/* generic pad control used in most cases */
+#define MXS_PAD_CTRL    (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
 #define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull)           \
                (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) |         \
                ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) |            \
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
index 9edd02ec8e30..c0a18c23084a 100644
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -93,7 +93,7 @@
 #define MX23_INT_USB_WAKEUP             12
 #define MX23_INT_GPMI_DMA               13
 #define MX23_INT_SSP1_DMA               14
-#define MX23_INT_SSP_ERROR              15
+#define MX23_INT_SSP1_ERROR             15
 #define MX23_INT_GPIO0                  16
 #define MX23_INT_GPIO1                  17
 #define MX23_INT_GPIO2                  18
@@ -101,9 +101,9 @@
 #define MX23_INT_SSP2_DMA               20
 #define MX23_INT_ECC8_IRQ               21
 #define MX23_INT_RTC_ALARM              22
-#define MX23_INT_UARTAPP_TX_DMA         23
+#define MX23_INT_AUART1_TX_DMA          23
-#define MX23_INT_UARTAPP_INTERNAL       24
+#define MX23_INT_AUART1                 24
-#define MX23_INT_UARTAPP_RX_DMA         25
+#define MX23_INT_AUART1_RX_DMA          25
 #define MX23_INT_I2C_DMA                26
 #define MX23_INT_I2C_ERROR              27
 #define MX23_INT_TIMER0                 28
@@ -135,11 +135,35 @@
 #define MX23_INT_DCP                    54
 #define MX23_INT_BCH                    56
 #define MX23_INT_PXP                    57
-#define MX23_INT_UARTAPP2_TX_DMA        58
+#define MX23_INT_AUART2_TX_DMA          58
-#define MX23_INT_UARTAPP2_INTERNAL      59
+#define MX23_INT_AUART2                 59
-#define MX23_INT_UARTAPP2_RX_DMA        60
+#define MX23_INT_AUART2_RX_DMA          60
 #define MX23_INT_VDAC_DETECT            61
 #define MX23_INT_VDD5V_DROOP            64
 #define MX23_INT_DCDC4P2_BO             65
+/*
+ * APBH DMA
+ */
+#define MX23_DMA_SSP1                   1
+#define MX23_DMA_SSP2                   2
+#define MX23_DMA_GPMI0                  4
+#define MX23_DMA_GPMI1                  5
+#define MX23_DMA_GPMI2                  6
+#define MX23_DMA_GPMI3                  7
+/*
+ * APBX DMA
+ */
+#define MX23_DMA_ADC                    0
+#define MX23_DMA_DAC                    1
+#define MX23_DMA_SPDIF                  2
+#define MX23_DMA_I2C                    3
+#define MX23_DMA_SAIF0                  4
+#define MX23_DMA_UART0_RX               6
+#define MX23_DMA_UART0_TX               7
+#define MX23_DMA_UART1_RX               8
+#define MX23_DMA_UART1_TX               9
+#define MX23_DMA_SAIF1                  10
 #endif /* __MACH_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
index 0716745267ad..75d86118b76a 100644
--- a/arch/arm/mach-mxs/include/mach/mx28.h
+++ b/arch/arm/mach-mxs/include/mach/mx28.h
@@ -163,10 +163,10 @@
 #define MX28_INT_USB0                   93
 #define MX28_INT_USB1_WAKEUP            94
 #define MX28_INT_USB0_WAKEUP            95
-#define MX28_INT_SSP0                   96
+#define MX28_INT_SSP0_ERROR             96
-#define MX28_INT_SSP1                   97
+#define MX28_INT_SSP1_ERROR             97
-#define MX28_INT_SSP2                   98
+#define MX28_INT_SSP2_ERROR             98
-#define MX28_INT_SSP3                   99
+#define MX28_INT_SSP3_ERROR             99
 #define MX28_INT_ENET_SWI               100
 #define MX28_INT_ENET_MAC0              101
 #define MX28_INT_ENET_MAC1              102
@@ -185,4 +185,41 @@
 #define MX28_INT_GPIO1                  126
 #define MX28_INT_GPIO0                  127
+/*
+ * APBH DMA
+ */
+#define MX28_DMA_SSP0                   0
+#define MX28_DMA_SSP1                   1
+#define MX28_DMA_SSP2                   2
+#define MX28_DMA_SSP3                   3
+#define MX28_DMA_GPMI0                  4
+#define MX28_DMA_GPMI1                  5
+#define MX28_DMA_GPMI2                  6
+#define MX28_DMA_GPMI3                  7
+#define MX28_DMA_GPMI4                  8
+#define MX28_DMA_GPMI5                  9
+#define MX28_DMA_GPMI6                  10
+#define MX28_DMA_GPMI7                  11
+#define MX28_DMA_HSADC                  12
+#define MX28_DMA_LCDIF                  13
+/*
+ * APBX DMA
+ */
+#define MX28_DMA_AUART4_RX              0
+#define MX28_DMA_AUART4_TX              1
+#define MX28_DMA_SPDIF_TX               2
+#define MX28_DMA_SAIF0                  4
+#define MX28_DMA_SAIF1                  5
+#define MX28_DMA_I2C0                   6
+#define MX28_DMA_I2C1                   7
+#define MX28_DMA_AUART0_RX              8
+#define MX28_DMA_AUART0_TX              9
+#define MX28_DMA_AUART1_RX              10
+#define MX28_DMA_AUART1_TX              11
+#define MX28_DMA_AUART2_RX              12
+#define MX28_DMA_AUART2_TX              13
+#define MX28_DMA_AUART3_RX              14
+#define MX28_DMA_AUART3_TX              15
 #endif /* __MACH_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index f186c08c2911..35a89dd27242 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -28,8 +28,13 @@
 /*
 * MXS CPU types
 */
-#define cpu_is_mx23()           (machine_is_mx23evk())
+#define cpu_is_mx23()           (                                       \
-#define cpu_is_mx28()           (machine_is_mx28evk())
+                machine_is_mx23evk() ||                                 \
+                0)
+#define cpu_is_mx28()           (                                       \
+                machine_is_mx28evk() ||                                 \
+                machine_is_tx28() ||                                    \
+                0)
 /*
 * IO addresses common to MXS-based
diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h
new file mode 100644
index 000000000000..e4d79791515e
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mxsfb.h
@@ -0,0 +1,49 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __MACH_FB_H
+#define __MACH_FB_H
+#include <linux/fb.h>
+#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */
+#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
+#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
+#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
+#define FB_SYNC_DATA_ENABLE_HIGH_ACT    (1 << 6)
+#define FB_SYNC_DOTCLK_FAILING_ACT      (1 << 7) /* failing/negtive edge sampling */
+struct mxsfb_platform_data {
+        struct fb_videomode *mode_list;
+        unsigned mode_count;
+        unsigned default_bpp;
+        unsigned dotclk_delay;  /* refer manual HW_LCDIF_VDCTRL4 register */
+        unsigned ld_intf_width; /* refer STMLCDIF_* macros */
+        unsigned fb_size;       /* Size of the video memory. If zero a
+                                 * default will be used
+                                 */
+        unsigned long fb_phys;  /* physical address for the video memory. If
+                                 * zero the framebuffer memory will be dynamically
+                                 * allocated. If specified,fb_size must also be specified.
+                                 * fb_phys must be unused by Linux.
+                                 */
+};
+#endif /* __MACH_FB_H */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index a005e76f34f9..f12a1732d8b8 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -63,6 +63,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                mxs_duart_base = MX23_DUART_BASE_ADDR;
                break;
        case MACH_TYPE_MX28EVK:
+        case MACH_TYPE_TX28:
                mxs_duart_base = MX28_DUART_BASE_ADDR;
                break;
        default:
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index aa0640052f58..a66994f0518f 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -26,17 +26,103 @@
 #include "devices-mx23.h"
+#define MX23EVK_LCD_ENABLE      MXS_GPIO_NR(1, 18)
+#define MX23EVK_BL_ENABLE       MXS_GPIO_NR(1, 28)
 static const iomux_cfg_t mx23evk_pads[] __initconst = {
        /* duart */
-        MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA,
+        MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-        MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA,
+        MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
+        /* auart */
+        MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
+        MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
+        MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL,
+        MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL,
+        /* mxsfb (lcdif) */
+        MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
+        MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
+        MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL,
+        MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
+        /* LCD panel enable */
+        MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL,
+        /* backlight control */
+        MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL,
+};
+/* mxsfb (lcdif) */
+static struct fb_videomode mx23evk_video_modes[] = {
+        {
+                .name           = "Samsung-LMS430HF02",
+                .refresh        = 60,
+                .xres           = 480,
+                .yres           = 272,
+                .pixclock       = 108096, /* picosecond (9.2 MHz) */
+                .left_margin    = 15,
+                .right_margin   = 8,
+                .upper_margin   = 12,
+                .lower_margin   = 4,
+                .hsync_len      = 1,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                  FB_SYNC_DOTCLK_FAILING_ACT,
+        },
+};
+static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = {
+        .mode_list      = mx23evk_video_modes,
+        .mode_count     = ARRAY_SIZE(mx23evk_video_modes),
+        .default_bpp    = 32,
+        .ld_intf_width  = STMLCDIF_24BIT,
 };
 static void __init mx23evk_init(void)
 {
+        int ret;
        mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
        mx23_add_duart();
+        mx23_add_auart0();
+        ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
+        if (ret)
+                pr_warn("failed to request gpio lcd-enable: %d\n", ret);
+        else
+                gpio_set_value(MX23EVK_LCD_ENABLE, 1);
+        ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
+        if (ret)
+                pr_warn("failed to request gpio bl-enable: %d\n", ret);
+        else
+                gpio_set_value(MX23EVK_BL_ENABLE, 1);
+        mx23_add_mxsfb(&mx23evk_mxsfb_pdata);
 }
 static void __init mx23evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 8e2c5975001e..08002d02267a 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -28,54 +28,93 @@
 #include "devices-mx28.h"
 #include "gpio.h"
+#define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
 #define MX28EVK_FEC_PHY_POWER   MXS_GPIO_NR(2, 15)
+#define MX28EVK_BL_ENABLE       MXS_GPIO_NR(3, 18)
+#define MX28EVK_LCD_ENABLE      MXS_GPIO_NR(3, 30)
 #define MX28EVK_FEC_PHY_RESET   MXS_GPIO_NR(4, 13)
 static const iomux_cfg_t mx28evk_pads[] __initconst = {
        /* duart */
-        MX28_PAD_PWM0__DUART_RX |
+        MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-        MX28_PAD_PWM1__DUART_TX |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        /* auart0 */
+        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
+        /* auart3 */
+        MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
+        MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
+        MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
+        MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
+#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
        /* fec0 */
-        MX28_PAD_ENET0_MDC__ENET0_MDC |
+        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO |
+        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN |
+        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 |
+        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 |
+        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
        /* fec1 */
-        MX28_PAD_ENET0_CRS__ENET1_RX_EN |
+        MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD2__ENET1_RXD0 |
+        MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD3__ENET1_RXD1 |
+        MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_COL__ENET1_TX_EN |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_TXD2__ENET1_TXD0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_TXD3__ENET1_TXD1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
        /* phy power line */
-        MX28_PAD_SSP1_DATA3__GPIO_2_15 |
+        MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL,
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
        /* phy reset line */
-        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL,
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        /* flexcan0 */
+        MX28_PAD_GPMI_RDY2__CAN0_TX,
+        MX28_PAD_GPMI_RDY3__CAN0_RX,
+        /* flexcan1 */
+        MX28_PAD_GPMI_CE2N__CAN1_TX,
+        MX28_PAD_GPMI_CE3N__CAN1_RX,
+        /* transceiver power control */
+        MX28_PAD_SSP1_CMD__GPIO_2_13,
+        /* mxsfb (lcdif) */
+        MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
+        MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
+        MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
+        MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL,
+        /* LCD panel enable */
+        MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
+        /* backlight control */
+        MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL,
 };
 /* fec */
@@ -119,7 +158,7 @@ static void __init mx28evk_fec_reset(void)
        gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
 }
-static struct fec_platform_data mx28_fec_pdata[] = {
+static struct fec_platform_data mx28_fec_pdata[] __initdata = {
        {
                /* fec0 */
                .phy = PHY_INTERFACE_MODE_RMII,
@@ -129,15 +168,135 @@ static struct fec_platform_data mx28_fec_pdata[] = {
        },
 };
+static int __init mx28evk_fec_get_mac(void)
+{
+        int i;
+        u32 val;
+        const u32 *ocotp = mxs_get_ocotp();
+        if (!ocotp)
+                goto error;
+        /*
+         * OCOTP only stores the last 4 octets for each mac address,
+         * so hard-code Freescale OUI (00:04:9f) here.
+         */
+        for (i = 0; i < 2; i++) {
+                val = ocotp[i * 4];
+                mx28_fec_pdata[i].mac[0] = 0x00;
+                mx28_fec_pdata[i].mac[1] = 0x04;
+                mx28_fec_pdata[i].mac[2] = 0x9f;
+                mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
+                mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
+                mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
+        }
+        return 0;
+error:
+        pr_err("%s: timeout when reading fec mac from OCOTP\n", __func__);
+        return -ETIMEDOUT;
+}
+/*
+ * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
+ */
+static int flexcan0_en, flexcan1_en;
+static void mx28evk_flexcan_switch(void)
+{
+        if (flexcan0_en || flexcan1_en)
+                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
+        else
+                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
+}
+static void mx28evk_flexcan0_switch(int enable)
+{
+        flexcan0_en = enable;
+        mx28evk_flexcan_switch();
+}
+static void mx28evk_flexcan1_switch(int enable)
+{
+        flexcan1_en = enable;
+        mx28evk_flexcan_switch();
+}
+static const struct flexcan_platform_data
+                mx28evk_flexcan_pdata[] __initconst = {
+        {
+                .transceiver_switch = mx28evk_flexcan0_switch,
+        }, {
+                .transceiver_switch = mx28evk_flexcan1_switch,
+        }
+};
+/* mxsfb (lcdif) */
+static struct fb_videomode mx28evk_video_modes[] = {
+        {
+                .name           = "Seiko-43WVF1G",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = 29851, /* picosecond (33.5 MHz) */
+                .left_margin    = 89,
+                .right_margin   = 164,
+                .upper_margin   = 23,
+                .lower_margin   = 10,
+                .hsync_len      = 10,
+                .vsync_len      = 10,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                  FB_SYNC_DOTCLK_FAILING_ACT,
+        },
+};
+static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = {
+        .mode_list      = mx28evk_video_modes,
+        .mode_count     = ARRAY_SIZE(mx28evk_video_modes),
+        .default_bpp    = 32,
+        .ld_intf_width  = STMLCDIF_24BIT,
+};
 static void __init mx28evk_init(void)
 {
+        int ret;
        mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
        mx28_add_duart();
+        mx28_add_auart0();
+        mx28_add_auart3();
+        if (mx28evk_fec_get_mac())
+                pr_warn("%s: failed on fec mac setup\n", __func__);
        mx28evk_fec_reset();
        mx28_add_fec(0, &mx28_fec_pdata[0]);
        mx28_add_fec(1, &mx28_fec_pdata[1]);
+        ret = gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
+                                "flexcan-switch");
+        if (ret) {
+                pr_err("failed to request gpio flexcan-switch: %d\n", ret);
+        } else {
+                mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
+                mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
+        }
+        ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
+        if (ret)
+                pr_warn("failed to request gpio lcd-enable: %d\n", ret);
+        else
+                gpio_set_value(MX28EVK_LCD_ENABLE, 1);
+        ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
+        if (ret)
+                pr_warn("failed to request gpio bl-enable: %d\n", ret);
+        else
+                gpio_set_value(MX28EVK_BL_ENABLE, 1);
+        mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
 }
 static void __init mx28evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
new file mode 100644
index 000000000000..b65e3719cbc4
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2010 <LW@KARO-electronics.de>
+ *
+ * based on: mach-mx28_evk.c
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation
+ */
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/i2c.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/iomux-mx28.h>
+#include "devices-mx28.h"
+#include "module-tx28.h"
+#define TX28_STK5_GPIO_LED              MXS_GPIO_NR(4, 10)
+static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = {
+        /* LED */
+        MX28_PAD_ENET0_RXD3__GPIO_4_10 |
+                MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL,
+        /* framebuffer */
+#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA)
+        MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE,
+        MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE,
+        MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE,
+        MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE,
+        MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE,
+        MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE,
+        MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE,
+        MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE,
+        MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE,
+        MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE,
+        MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE,
+        MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE,
+        MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE,
+        MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE,
+        MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE,
+        MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE,
+        MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE,
+        MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE,
+        MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE,
+        MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE,
+        MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE,
+        MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE,
+        MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE,
+        MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE,
+        MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE,
+        MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE,
+        MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE,
+        MX28_PAD_LCD_CS__LCD_CS | LCD_MODE,
+        MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE,
+        MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE,
+        MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE,
+        MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE,
+        MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE,
+        MX28_PAD_PWM0__PWM_0 | LCD_MODE,
+        /* UART1 */
+        MX28_PAD_AUART0_CTS__DUART_RX,
+        MX28_PAD_AUART0_RTS__DUART_TX,
+        MX28_PAD_AUART0_TX__DUART_RTS,
+        MX28_PAD_AUART0_RX__DUART_CTS,
+        /* UART2 */
+        MX28_PAD_AUART1_RX__AUART1_RX,
+        MX28_PAD_AUART1_TX__AUART1_TX,
+        MX28_PAD_AUART1_RTS__AUART1_RTS,
+        MX28_PAD_AUART1_CTS__AUART1_CTS,
+        /* CAN */
+        MX28_PAD_GPMI_RDY2__CAN0_TX,
+        MX28_PAD_GPMI_RDY3__CAN0_RX,
+        /* I2C */
+        MX28_PAD_I2C0_SCL__I2C0_SCL,
+        MX28_PAD_I2C0_SDA__I2C0_SDA,
+        /* TSC2007 */
+        MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
+        /* MMC0 */
+        MX28_PAD_SSP0_DATA0__SSP0_D0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA1__SSP0_D1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA2__SSP0_D2 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA3__SSP0_D3 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA4__SSP0_D4 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA5__SSP0_D5 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA6__SSP0_D6 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA7__SSP0_D7 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_CMD__SSP0_CMD |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_SSP0_SCK__SSP0_SCK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+};
+static struct gpio_led tx28_stk5v3_leds[] = {
+        {
+                .name = "GPIO-LED",
+                .default_trigger = "heartbeat",
+                .gpio = TX28_STK5_GPIO_LED,
+        },
+};
+static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = {
+        .leds = tx28_stk5v3_leds,
+        .num_leds = ARRAY_SIZE(tx28_stk5v3_leds),
+};
+static struct spi_board_info tx28_spi_board_info[] = {
+        {
+                .modalias = "spidev",
+                .max_speed_hz = 20000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT,
+                .mode = SPI_MODE_0,
+        },
+};
+static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
+        {
+                I2C_BOARD_INFO("ds1339", 0x68),
+        },
+};
+static void __init tx28_stk5v3_init(void)
+{
+        mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
+                        ARRAY_SIZE(tx28_stk5v3_pads));
+        mx28_add_duart(); /* UART1 */
+        mx28_add_auart(1); /* UART2 */
+        tx28_add_fec0();
+        /* spi via ssp will be added when available */
+        spi_register_board_info(tx28_spi_board_info,
+                        ARRAY_SIZE(tx28_spi_board_info));
+        mxs_add_platform_device("leds-gpio", 0, NULL, 0,
+                        &tx28_stk5v3_led_data, sizeof(tx28_stk5v3_led_data));
+        mx28_add_mxs_i2c(0);
+        i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
+                        ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
+}
+static void __init tx28_timer_init(void)
+{
+        mx28_clocks_init();
+}
+static struct sys_timer tx28_timer = {
+        .init = tx28_timer_init,
+};
+MACHINE_START(TX28, "Ka-Ro electronics TX28 module")
+        .map_io = mx28_map_io,
+        .init_irq = mx28_init_irq,
+        .init_machine = tx28_stk5v3_init,
+        .timer = &tx28_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
new file mode 100644
index 000000000000..fa0b154da67b
--- /dev/null
+++ b/arch/arm/mach-mxs/module-tx28.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2010 <LW@KARO-electronics.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/delay.h>
+#include <linux/fec.h>
+#include <linux/gpio.h>
+#include <mach/iomux-mx28.h>
+#include "../devices-mx28.h"
+#include "module-tx28.h"
+#define TX28_FEC_PHY_POWER      MXS_GPIO_NR(3, 29)
+#define TX28_FEC_PHY_RESET      MXS_GPIO_NR(4, 13)
+static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = {
+        /* PHY POWER */
+        MX28_PAD_PWM4__GPIO_3_29 |
+                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
+        /* PHY RESET */
+        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
+        /* Mode strap pins 0-2 */
+        MX28_PAD_ENET0_RXD0__GPIO_4_3 |
+                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
+        MX28_PAD_ENET0_RXD1__GPIO_4_4 |
+                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
+        MX28_PAD_ENET0_RX_EN__GPIO_4_2 |
+                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
+        /* nINT */
+        MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
+                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
+        MX28_PAD_ENET0_MDC__GPIO_4_0,
+        MX28_PAD_ENET0_MDIO__GPIO_4_1,
+        MX28_PAD_ENET0_TX_EN__GPIO_4_6,
+        MX28_PAD_ENET0_TXD0__GPIO_4_7,
+        MX28_PAD_ENET0_TXD1__GPIO_4_8,
+        MX28_PAD_ENET_CLK__GPIO_4_16,
+};
+#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3)
+static const iomux_cfg_t tx28_fec_pads[] __initconst = {
+        MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE,
+        MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE,
+        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE,
+        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE,
+        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE,
+        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE,
+        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE,
+        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE,
+        MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE,
+};
+static const struct fec_platform_data tx28_fec_data __initconst = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+int __init tx28_add_fec0(void)
+{
+        int i, ret;
+        pr_debug("%s: Switching FEC PHY power off\n", __func__);
+        ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads,
+                        ARRAY_SIZE(tx28_fec_gpio_pads));
+        for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) {
+                unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
+                        PAD_PIN(tx28_fec_gpio_pads[i]));
+                ret = gpio_request(gpio, "FEC");
+                if (ret) {
+                        pr_err("Failed to request GPIO_%d_%d: %d\n",
+                                PAD_BANK(tx28_fec_gpio_pads[i]),
+                                PAD_PIN(tx28_fec_gpio_pads[i]), ret);
+                        goto free_gpios;
+                }
+                ret = gpio_direction_output(gpio, 0);
+                if (ret) {
+                        pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n",
+                                        gpio / 32 + 1, gpio % 32, ret);
+                        goto free_gpios;
+                }
+        }
+        /* Power up fec phy */
+        pr_debug("%s: Switching FEC PHY power on\n", __func__);
+        ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1);
+        if (ret) {
+                pr_err("Failed to power on PHY: %d\n", ret);
+                goto free_gpios;
+        }
+        mdelay(26); /* 25ms according to data sheet */
+        /* nINT */
+        gpio_direction_input(MXS_GPIO_NR(4, 5));
+        /* Mode strap pins */
+        gpio_direction_output(MXS_GPIO_NR(4, 2), 1);
+        gpio_direction_output(MXS_GPIO_NR(4, 3), 1);
+        gpio_direction_output(MXS_GPIO_NR(4, 4), 1);
+        udelay(100); /* minimum assertion time for nRST */
+        pr_debug("%s: Deasserting FEC PHY RESET\n", __func__);
+        gpio_set_value(TX28_FEC_PHY_RESET, 1);
+        ret = mxs_iomux_setup_multiple_pads(tx28_fec_pads,
+                        ARRAY_SIZE(tx28_fec_pads));
+        if (ret) {
+                pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
+                                __func__, ret);
+                goto free_gpios;
+        }
+        pr_debug("%s: Registering FEC device\n", __func__);
+        mx28_add_fec(0, &tx28_fec_data);
+        return 0;
+free_gpios:
+        while (--i >= 0) {
+                unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
+                        PAD_PIN(tx28_fec_gpio_pads[i]));
+                gpio_free(gpio);
+        }
+        return ret;
+}
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h
new file mode 100644
index 000000000000..df9e1b6e81bf
--- /dev/null
+++ b/arch/arm/mach-mxs/module-tx28.h
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ *   Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+int __init tx28_add_fec0(void);
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
new file mode 100644
index 000000000000..65157a35dbba
--- /dev/null
+++ b/arch/arm/mach-mxs/ocotp.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/mutex.h>
+#include <mach/mxs.h>
+#define OCOTP_WORD_OFFSET               0x20
+#define OCOTP_WORD_COUNT                0x20
+#define BM_OCOTP_CTRL_BUSY              (1 << 8)
+#define BM_OCOTP_CTRL_ERROR             (1 << 9)
+#define BM_OCOTP_CTRL_RD_BANK_OPEN      (1 << 12)
+static DEFINE_MUTEX(ocotp_mutex);
+static u32 ocotp_words[OCOTP_WORD_COUNT];
+const u32 *mxs_get_ocotp(void)
+{
+        void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
+        int timeout = 0x400;
+        size_t i;
+        static int once = 0;
+        if (once)
+                return ocotp_words;
+        mutex_lock(&ocotp_mutex);
+        /*
+         * clk_enable(hbus_clk) for ocotp can be skipped
+         * as it must be on when system is running.
+         */
+        /* try to clear ERROR bit */
+        __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
+        /* check both BUSY and ERROR cleared */
+        while ((__raw_readl(ocotp_base) &
+                (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
+                cpu_relax();
+        if (unlikely(!timeout))
+                goto error_unlock;
+        /* open OCOTP banks for read */
+        __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
+        /* approximately wait 32 hclk cycles */
+        udelay(1);
+        /* poll BUSY bit becoming cleared */
+        timeout = 0x400;
+        while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
+                cpu_relax();
+        if (unlikely(!timeout))
+                goto error_unlock;
+        for (i = 0; i < OCOTP_WORD_COUNT; i++)
+                ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
+                                                i * 0x10);
+        /* close banks for power saving */
+        __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
+        once = 1;
+        mutex_unlock(&ocotp_mutex);
+        return ocotp_words;
+error_unlock:
+        mutex_unlock(&ocotp_mutex);
+        pr_err("%s: timeout in reading OCOTP\n", __func__);
+        return NULL;
+}
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
new file mode 100644
index 000000000000..fb042da29bda
--- /dev/null
+++ b/arch/arm/mach-mxs/pm.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <mach/system.h>
+static int mxs_suspend_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                arch_idle();
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+static struct platform_suspend_ops mxs_suspend_ops = {
+        .enter = mxs_suspend_enter,
+        .valid = suspend_valid_only_mem,
+};
+static int __init mxs_pm_init(void)
+{
+        suspend_set_ops(&mxs_suspend_ops);
+        return 0;
+}
+device_initcall(mxs_pm_init);
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
index dbc04747b691..0ea5c9d0e2b2 100644
--- a/arch/arm/mach-mxs/regs-clkctrl-mx23.h
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
@@ -33,10 +33,6 @@
 #define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
 #define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
-#define BP_CLKCTRL_PLLCTRL0_RSRVD6      30
-#define BM_CLKCTRL_PLLCTRL0_RSRVD6      0xC0000000
-#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
-                (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
 #define BP_CLKCTRL_PLLCTRL0_LFR_SEL     28
 #define BM_CLKCTRL_PLLCTRL0_LFR_SEL     0x30000000
 #define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)  \
@@ -45,10 +41,6 @@
 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLLCTRL0_RSRVD5      26
-#define BM_CLKCTRL_PLLCTRL0_RSRVD5      0x0C000000
-#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v)  \
-                (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
 #define BP_CLKCTRL_PLLCTRL0_CP_SEL      24
 #define BM_CLKCTRL_PLLCTRL0_CP_SEL      0x03000000
 #define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)  \
@@ -57,10 +49,6 @@
 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLLCTRL0_RSRVD4      22
-#define BM_CLKCTRL_PLLCTRL0_RSRVD4      0x00C00000
-#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v)  \
-                (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
 #define BP_CLKCTRL_PLLCTRL0_DIV_SEL     20
 #define BM_CLKCTRL_PLLCTRL0_DIV_SEL     0x00300000
 #define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)  \
@@ -69,23 +57,13 @@
 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER     0x1
 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST    0x2
 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLLCTRL0_RSRVD3      0x00080000
 #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
-#define BM_CLKCTRL_PLLCTRL0_RSRVD2      0x00020000
 #define BM_CLKCTRL_PLLCTRL0_POWER       0x00010000
-#define BP_CLKCTRL_PLLCTRL0_RSRVD1      0
-#define BM_CLKCTRL_PLLCTRL0_RSRVD1      0x0000FFFF
-#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
 #define HW_CLKCTRL_PLLCTRL1     (0x00000010)
 #define BM_CLKCTRL_PLLCTRL1_LOCK        0x80000000
 #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK  0x40000000
-#define BP_CLKCTRL_PLLCTRL1_RSRVD1      16
-#define BM_CLKCTRL_PLLCTRL1_RSRVD1      0x3FFF0000
-#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v)  \
-                (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
 #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT  0
 #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT  0x0000FFFF
 #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)  \
@@ -96,29 +74,15 @@
 #define HW_CLKCTRL_CPU_CLR      (0x00000028)
 #define HW_CLKCTRL_CPU_TOG      (0x0000002c)
-#define BP_CLKCTRL_CPU_RSRVD5   30
-#define BM_CLKCTRL_CPU_RSRVD5   0xC0000000
-#define BF_CLKCTRL_CPU_RSRVD5(v) \
-                (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
 #define BM_CLKCTRL_CPU_BUSY_REF_XTAL    0x20000000
 #define BM_CLKCTRL_CPU_BUSY_REF_CPU     0x10000000
-#define BM_CLKCTRL_CPU_RSRVD4   0x08000000
 #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
 #define BP_CLKCTRL_CPU_DIV_XTAL 16
 #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
 #define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
                (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
-#define BP_CLKCTRL_CPU_RSRVD3   13
-#define BM_CLKCTRL_CPU_RSRVD3   0x0000E000
-#define BF_CLKCTRL_CPU_RSRVD3(v)  \
-                (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
 #define BM_CLKCTRL_CPU_INTERRUPT_WAIT   0x00001000
-#define BM_CLKCTRL_CPU_RSRVD2   0x00000800
 #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN  0x00000400
-#define BP_CLKCTRL_CPU_RSRVD1   6
-#define BM_CLKCTRL_CPU_RSRVD1   0x000003C0
-#define BF_CLKCTRL_CPU_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
 #define BP_CLKCTRL_CPU_DIV_CPU  0
 #define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
 #define BF_CLKCTRL_CPU_DIV_CPU(v)  \
@@ -129,10 +93,6 @@
 #define HW_CLKCTRL_HBUS_CLR     (0x00000038)
 #define HW_CLKCTRL_HBUS_TOG     (0x0000003c)
-#define BP_CLKCTRL_HBUS_RSRVD4  30
-#define BM_CLKCTRL_HBUS_RSRVD4  0xC0000000
-#define BF_CLKCTRL_HBUS_RSRVD4(v) \
-                (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
 #define BM_CLKCTRL_HBUS_BUSY    0x20000000
 #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE   0x10000000
 #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE   0x08000000
@@ -143,7 +103,6 @@
 #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE      0x00400000
 #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE     0x00200000
 #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE  0x00100000
-#define BM_CLKCTRL_HBUS_RSRVD2  0x00080000
 #define BP_CLKCTRL_HBUS_SLOW_DIV        16
 #define BM_CLKCTRL_HBUS_SLOW_DIV        0x00070000
 #define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
@@ -154,10 +113,6 @@
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
-#define BP_CLKCTRL_HBUS_RSRVD1  6
-#define BM_CLKCTRL_HBUS_RSRVD1  0x0000FFC0
-#define BF_CLKCTRL_HBUS_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
 #define BM_CLKCTRL_HBUS_DIV_FRAC_EN     0x00000020
 #define BP_CLKCTRL_HBUS_DIV     0
 #define BM_CLKCTRL_HBUS_DIV     0x0000001F
@@ -167,10 +122,6 @@
 #define HW_CLKCTRL_XBUS (0x00000040)
 #define BM_CLKCTRL_XBUS_BUSY    0x80000000
-#define BP_CLKCTRL_XBUS_RSRVD1  11
-#define BM_CLKCTRL_XBUS_RSRVD1  0x7FFFF800
-#define BF_CLKCTRL_XBUS_RSRVD1(v)  \
-                (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
 #define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x00000400
 #define BP_CLKCTRL_XBUS_DIV     0
 #define BM_CLKCTRL_XBUS_DIV     0x000003FF
@@ -192,10 +143,6 @@
 #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      0x08000000
 #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
 #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x04000000
-#define BP_CLKCTRL_XTAL_RSRVD1  2
-#define BM_CLKCTRL_XTAL_RSRVD1  0x03FFFFFC
-#define BF_CLKCTRL_XTAL_RSRVD1(v)  \
-                (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
 #define BP_CLKCTRL_XTAL_DIV_UART        0
 #define BM_CLKCTRL_XTAL_DIV_UART        0x00000003
 #define BF_CLKCTRL_XTAL_DIV_UART(v)  \
@@ -205,12 +152,7 @@
 #define BP_CLKCTRL_PIX_CLKGATE  31
 #define BM_CLKCTRL_PIX_CLKGATE  0x80000000
-#define BM_CLKCTRL_PIX_RSRVD2   0x40000000
 #define BM_CLKCTRL_PIX_BUSY     0x20000000
-#define BP_CLKCTRL_PIX_RSRVD1   13
-#define BM_CLKCTRL_PIX_RSRVD1   0x1FFFE000
-#define BF_CLKCTRL_PIX_RSRVD1(v)  \
-                (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
 #define BM_CLKCTRL_PIX_DIV_FRAC_EN      0x00001000
 #define BP_CLKCTRL_PIX_DIV      0
 #define BM_CLKCTRL_PIX_DIV      0x00000FFF
@@ -221,12 +163,7 @@
 #define BP_CLKCTRL_SSP_CLKGATE  31
 #define BM_CLKCTRL_SSP_CLKGATE  0x80000000
-#define BM_CLKCTRL_SSP_RSRVD2   0x40000000
 #define BM_CLKCTRL_SSP_BUSY     0x20000000
-#define BP_CLKCTRL_SSP_RSRVD1   10
-#define BM_CLKCTRL_SSP_RSRVD1   0x1FFFFC00
-#define BF_CLKCTRL_SSP_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
 #define BM_CLKCTRL_SSP_DIV_FRAC_EN      0x00000200
 #define BP_CLKCTRL_SSP_DIV      0
 #define BM_CLKCTRL_SSP_DIV      0x000001FF
@@ -237,12 +174,7 @@
 #define BP_CLKCTRL_GPMI_CLKGATE 31
 #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
-#define BM_CLKCTRL_GPMI_RSRVD2  0x40000000
 #define BM_CLKCTRL_GPMI_BUSY    0x20000000
-#define BP_CLKCTRL_GPMI_RSRVD1  11
-#define BM_CLKCTRL_GPMI_RSRVD1  0x1FFFF800
-#define BF_CLKCTRL_GPMI_RSRVD1(v)  \
-                (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
 #define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x00000400
 #define BP_CLKCTRL_GPMI_DIV     0
 #define BM_CLKCTRL_GPMI_DIV     0x000003FF
@@ -252,10 +184,6 @@
 #define HW_CLKCTRL_SPDIF        (0x00000090)
 #define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
-#define BP_CLKCTRL_SPDIF_RSRVD  0
-#define BM_CLKCTRL_SPDIF_RSRVD  0x7FFFFFFF
-#define BF_CLKCTRL_SPDIF_RSRVD(v)  \
-                (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
 #define HW_CLKCTRL_EMI  (0x000000a0)
@@ -266,24 +194,12 @@
 #define BM_CLKCTRL_EMI_BUSY_REF_EMI     0x10000000
 #define BM_CLKCTRL_EMI_BUSY_REF_CPU     0x08000000
 #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE   0x04000000
-#define BP_CLKCTRL_EMI_RSRVD3   18
-#define BM_CLKCTRL_EMI_RSRVD3   0x03FC0000
-#define BF_CLKCTRL_EMI_RSRVD3(v)  \
-                (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
 #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC  0x00020000
 #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x00010000
-#define BP_CLKCTRL_EMI_RSRVD2   12
-#define BM_CLKCTRL_EMI_RSRVD2   0x0000F000
-#define BF_CLKCTRL_EMI_RSRVD2(v)  \
-                (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
 #define BP_CLKCTRL_EMI_DIV_XTAL 8
 #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
 #define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
                (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
-#define BP_CLKCTRL_EMI_RSRVD1   6
-#define BM_CLKCTRL_EMI_RSRVD1   0x000000C0
-#define BF_CLKCTRL_EMI_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
 #define BP_CLKCTRL_EMI_DIV_EMI  0
 #define BM_CLKCTRL_EMI_DIV_EMI  0x0000003F
 #define BF_CLKCTRL_EMI_DIV_EMI(v)  \
@@ -292,22 +208,13 @@
 #define HW_CLKCTRL_IR   (0x000000b0)
 #define BM_CLKCTRL_IR_CLKGATE   0x80000000
-#define BM_CLKCTRL_IR_RSRVD3    0x40000000
 #define BM_CLKCTRL_IR_AUTO_DIV  0x20000000
 #define BM_CLKCTRL_IR_IR_BUSY   0x10000000
 #define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
-#define BP_CLKCTRL_IR_RSRVD2    25
-#define BM_CLKCTRL_IR_RSRVD2    0x06000000
-#define BF_CLKCTRL_IR_RSRVD2(v)  \
-                (((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
 #define BP_CLKCTRL_IR_IROV_DIV  16
 #define BM_CLKCTRL_IR_IROV_DIV  0x01FF0000
 #define BF_CLKCTRL_IR_IROV_DIV(v)  \
                (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
-#define BP_CLKCTRL_IR_RSRVD1    10
-#define BM_CLKCTRL_IR_RSRVD1    0x0000FC00
-#define BF_CLKCTRL_IR_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
 #define BP_CLKCTRL_IR_IR_DIV    0
 #define BM_CLKCTRL_IR_IR_DIV    0x000003FF
 #define BF_CLKCTRL_IR_IR_DIV(v)  \
@@ -316,12 +223,7 @@
 #define HW_CLKCTRL_SAIF (0x000000c0)
 #define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
-#define BM_CLKCTRL_SAIF_RSRVD2  0x40000000
 #define BM_CLKCTRL_SAIF_BUSY    0x20000000
-#define BP_CLKCTRL_SAIF_RSRVD1  17
-#define BM_CLKCTRL_SAIF_RSRVD1  0x1FFE0000
-#define BF_CLKCTRL_SAIF_RSRVD1(v)  \
-                (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
 #define BM_CLKCTRL_SAIF_DIV_FRAC_EN     0x00010000
 #define BP_CLKCTRL_SAIF_DIV     0
 #define BM_CLKCTRL_SAIF_DIV     0x0000FFFF
@@ -332,20 +234,11 @@
 #define BM_CLKCTRL_TV_CLK_TV108M_GATE   0x80000000
 #define BM_CLKCTRL_TV_CLK_TV_GATE       0x40000000
-#define BP_CLKCTRL_TV_RSRVD     0
-#define BM_CLKCTRL_TV_RSRVD     0x3FFFFFFF
-#define BF_CLKCTRL_TV_RSRVD(v)  \
-                (((v) << 0) & BM_CLKCTRL_TV_RSRVD)
 #define HW_CLKCTRL_ETM  (0x000000e0)
 #define BM_CLKCTRL_ETM_CLKGATE  0x80000000
-#define BM_CLKCTRL_ETM_RSRVD2   0x40000000
 #define BM_CLKCTRL_ETM_BUSY     0x20000000
-#define BP_CLKCTRL_ETM_RSRVD1   7
-#define BM_CLKCTRL_ETM_RSRVD1   0x1FFFFF80
-#define BF_CLKCTRL_ETM_RSRVD1(v)  \
-                (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
 #define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x00000040
 #define BP_CLKCTRL_ETM_DIV      0
 #define BM_CLKCTRL_ETM_DIV      0x0000003F
@@ -393,36 +286,23 @@
 #define BM_CLKCTRL_FRAC1_CLKGATEVID     0x80000000
 #define BM_CLKCTRL_FRAC1_VID_STABLE     0x40000000
-#define BP_CLKCTRL_FRAC1_RSRVD1 0
-#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
-#define BF_CLKCTRL_FRAC1_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
 #define HW_CLKCTRL_CLKSEQ       (0x00000110)
 #define HW_CLKCTRL_CLKSEQ_SET   (0x00000114)
 #define HW_CLKCTRL_CLKSEQ_CLR   (0x00000118)
 #define HW_CLKCTRL_CLKSEQ_TOG   (0x0000011c)
-#define BP_CLKCTRL_CLKSEQ_RSRVD1        9
-#define BM_CLKCTRL_CLKSEQ_RSRVD1        0xFFFFFE00
-#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
-                (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
 #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM    0x00000100
 #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU    0x00000080
 #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI    0x00000040
 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP    0x00000020
 #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI   0x00000010
 #define BM_CLKCTRL_CLKSEQ_BYPASS_IR     0x00000008
-#define BM_CLKCTRL_CLKSEQ_RSRVD0        0x00000004
 #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX    0x00000002
 #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF   0x00000001
 #define HW_CLKCTRL_RESET        (0x00000120)
-#define BP_CLKCTRL_RESET_RSRVD  2
-#define BM_CLKCTRL_RESET_RSRVD  0xFFFFFFFC
-#define BF_CLKCTRL_RESET_RSRVD(v) \
-                (((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
 #define BM_CLKCTRL_RESET_CHIP   0x00000002
 #define BM_CLKCTRL_RESET_DIG    0x00000001
@@ -432,10 +312,6 @@
 #define BM_CLKCTRL_STATUS_CPU_LIMIT     0xC0000000
 #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
                (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
-#define BP_CLKCTRL_STATUS_RSRVD 0
-#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
-#define BF_CLKCTRL_STATUS_RSRVD(v)  \
-                (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
 #define HW_CLKCTRL_VERSION      (0x00000140)
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
index 661df18755f7..7d1b061d7943 100644
--- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
@@ -31,10 +31,6 @@
 #define HW_CLKCTRL_PLL0CTRL0_CLR        (0x00000008)
 #define HW_CLKCTRL_PLL0CTRL0_TOG        (0x0000000c)
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD6     30
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD6     0xC0000000
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
-                (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
 #define BP_CLKCTRL_PLL0CTRL0_LFR_SEL    28
 #define BM_CLKCTRL_PLL0CTRL0_LFR_SEL    0x30000000
 #define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v)  \
@@ -43,10 +39,6 @@
 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD5     26
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD5     0x0C000000
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v)  \
-                (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
 #define BP_CLKCTRL_PLL0CTRL0_CP_SEL     24
 #define BM_CLKCTRL_PLL0CTRL0_CP_SEL     0x03000000
 #define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v)  \
@@ -55,10 +47,6 @@
 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD4     22
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD4     0x00C00000
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v)  \
-                (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
 #define BP_CLKCTRL_PLL0CTRL0_DIV_SEL    20
 #define BM_CLKCTRL_PLL0CTRL0_DIV_SEL    0x00300000
 #define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v)  \
@@ -67,22 +55,13 @@
 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER     0x1
 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST    0x2
 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD3     0x00080000
 #define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS        0x00040000
 #define BM_CLKCTRL_PLL0CTRL0_POWER      0x00020000
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD1     0
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD1     0x0001FFFF
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
 #define HW_CLKCTRL_PLL0CTRL1    (0x00000010)
 #define BM_CLKCTRL_PLL0CTRL1_LOCK       0x80000000
 #define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
-#define BP_CLKCTRL_PLL0CTRL1_RSRVD1     16
-#define BM_CLKCTRL_PLL0CTRL1_RSRVD1     0x3FFF0000
-#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v)  \
-                (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
 #define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
 #define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
 #define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v)  \
@@ -94,7 +73,6 @@
 #define HW_CLKCTRL_PLL1CTRL0_TOG        (0x0000002c)
 #define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD6     0x40000000
 #define BP_CLKCTRL_PLL1CTRL0_LFR_SEL    28
 #define BM_CLKCTRL_PLL1CTRL0_LFR_SEL    0x30000000
 #define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v)  \
@@ -103,10 +81,6 @@
 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL1CTRL0_RSRVD5     26
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD5     0x0C000000
-#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v)  \
-                (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
 #define BP_CLKCTRL_PLL1CTRL0_CP_SEL     24
 #define BM_CLKCTRL_PLL1CTRL0_CP_SEL     0x03000000
 #define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v)  \
@@ -115,10 +89,6 @@
 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL1CTRL0_RSRVD4     22
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD4     0x00C00000
-#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v)  \
-                (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
 #define BP_CLKCTRL_PLL1CTRL0_DIV_SEL    20
 #define BM_CLKCTRL_PLL1CTRL0_DIV_SEL    0x00300000
 #define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v)  \
@@ -127,22 +97,13 @@
 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER     0x1
 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST    0x2
 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD3     0x00080000
 #define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS        0x00040000
 #define BM_CLKCTRL_PLL1CTRL0_POWER      0x00020000
-#define BP_CLKCTRL_PLL1CTRL0_RSRVD1     0
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD1     0x0001FFFF
-#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
 #define HW_CLKCTRL_PLL1CTRL1    (0x00000030)
 #define BM_CLKCTRL_PLL1CTRL1_LOCK       0x80000000
 #define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
-#define BP_CLKCTRL_PLL1CTRL1_RSRVD1     16
-#define BM_CLKCTRL_PLL1CTRL1_RSRVD1     0x3FFF0000
-#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v)  \
-                (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
 #define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
 #define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
 #define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v)  \
@@ -154,51 +115,31 @@
 #define HW_CLKCTRL_PLL2CTRL0_TOG        (0x0000004c)
 #define BM_CLKCTRL_PLL2CTRL0_CLKGATE    0x80000000
-#define BM_CLKCTRL_PLL2CTRL0_RSRVD3     0x40000000
 #define BP_CLKCTRL_PLL2CTRL0_LFR_SEL    28
 #define BM_CLKCTRL_PLL2CTRL0_LFR_SEL    0x30000000
 #define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v)  \
                (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
-#define BM_CLKCTRL_PLL2CTRL0_RSRVD2     0x08000000
 #define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B    0x04000000
 #define BP_CLKCTRL_PLL2CTRL0_CP_SEL     24
 #define BM_CLKCTRL_PLL2CTRL0_CP_SEL     0x03000000
 #define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v)  \
                (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
 #define BM_CLKCTRL_PLL2CTRL0_POWER      0x00800000
-#define BP_CLKCTRL_PLL2CTRL0_RSRVD1     0
-#define BM_CLKCTRL_PLL2CTRL0_RSRVD1     0x007FFFFF
-#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
 #define HW_CLKCTRL_CPU  (0x00000050)
 #define HW_CLKCTRL_CPU_SET      (0x00000054)
 #define HW_CLKCTRL_CPU_CLR      (0x00000058)
 #define HW_CLKCTRL_CPU_TOG      (0x0000005c)
-#define BP_CLKCTRL_CPU_RSRVD5   30
-#define BM_CLKCTRL_CPU_RSRVD5   0xC0000000
-#define BF_CLKCTRL_CPU_RSRVD5(v) \
-                (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
 #define BM_CLKCTRL_CPU_BUSY_REF_XTAL    0x20000000
 #define BM_CLKCTRL_CPU_BUSY_REF_CPU     0x10000000
-#define BM_CLKCTRL_CPU_RSRVD4   0x08000000
 #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
 #define BP_CLKCTRL_CPU_DIV_XTAL 16
 #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
 #define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
                (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
-#define BP_CLKCTRL_CPU_RSRVD3   13
-#define BM_CLKCTRL_CPU_RSRVD3   0x0000E000
-#define BF_CLKCTRL_CPU_RSRVD3(v)  \
-                (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
 #define BM_CLKCTRL_CPU_INTERRUPT_WAIT   0x00001000
-#define BM_CLKCTRL_CPU_RSRVD2   0x00000800
 #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN  0x00000400
-#define BP_CLKCTRL_CPU_RSRVD1   6
-#define BM_CLKCTRL_CPU_RSRVD1   0x000003C0
-#define BF_CLKCTRL_CPU_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
 #define BP_CLKCTRL_CPU_DIV_CPU  0
 #define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
 #define BF_CLKCTRL_CPU_DIV_CPU(v)  \
@@ -212,7 +153,6 @@
 #define BM_CLKCTRL_HBUS_ASM_BUSY        0x80000000
 #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE   0x40000000
 #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE   0x20000000
-#define BM_CLKCTRL_HBUS_RSRVD2  0x10000000
 #define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE   0x08000000
 #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE       0x04000000
 #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE       0x02000000
@@ -232,10 +172,6 @@
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
-#define BP_CLKCTRL_HBUS_RSRVD1  6
-#define BM_CLKCTRL_HBUS_RSRVD1  0x0000FFC0
-#define BF_CLKCTRL_HBUS_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
 #define BM_CLKCTRL_HBUS_DIV_FRAC_EN     0x00000020
 #define BP_CLKCTRL_HBUS_DIV     0
 #define BM_CLKCTRL_HBUS_DIV     0x0000001F
@@ -245,10 +181,6 @@
 #define HW_CLKCTRL_XBUS (0x00000070)
 #define BM_CLKCTRL_XBUS_BUSY    0x80000000
-#define BP_CLKCTRL_XBUS_RSRVD1  12
-#define BM_CLKCTRL_XBUS_RSRVD1  0x7FFFF000
-#define BF_CLKCTRL_XBUS_RSRVD1(v)  \
-                (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
 #define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE   0x00000800
 #define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x00000400
 #define BP_CLKCTRL_XBUS_DIV     0
@@ -263,19 +195,10 @@
 #define BP_CLKCTRL_XTAL_UART_CLK_GATE   31
 #define BM_CLKCTRL_XTAL_UART_CLK_GATE   0x80000000
-#define BM_CLKCTRL_XTAL_RSRVD3  0x40000000
 #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
 #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
-#define BP_CLKCTRL_XTAL_RSRVD2  27
-#define BM_CLKCTRL_XTAL_RSRVD2  0x18000000
-#define BF_CLKCTRL_XTAL_RSRVD2(v)  \
-                (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
 #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
 #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x04000000
-#define BP_CLKCTRL_XTAL_RSRVD1  2
-#define BM_CLKCTRL_XTAL_RSRVD1  0x03FFFFFC
-#define BF_CLKCTRL_XTAL_RSRVD1(v)  \
-                (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
 #define BP_CLKCTRL_XTAL_DIV_UART        0
 #define BM_CLKCTRL_XTAL_DIV_UART        0x00000003
 #define BF_CLKCTRL_XTAL_DIV_UART(v)  \
@@ -285,12 +208,7 @@
 #define BP_CLKCTRL_SSP0_CLKGATE 31
 #define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP0_RSRVD2  0x40000000
 #define BM_CLKCTRL_SSP0_BUSY    0x20000000
-#define BP_CLKCTRL_SSP0_RSRVD1  10
-#define BM_CLKCTRL_SSP0_RSRVD1  0x1FFFFC00
-#define BF_CLKCTRL_SSP0_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
 #define BM_CLKCTRL_SSP0_DIV_FRAC_EN     0x00000200
 #define BP_CLKCTRL_SSP0_DIV     0
 #define BM_CLKCTRL_SSP0_DIV     0x000001FF
@@ -301,12 +219,7 @@
 #define BP_CLKCTRL_SSP1_CLKGATE 31
 #define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP1_RSRVD2  0x40000000
 #define BM_CLKCTRL_SSP1_BUSY    0x20000000
-#define BP_CLKCTRL_SSP1_RSRVD1  10
-#define BM_CLKCTRL_SSP1_RSRVD1  0x1FFFFC00
-#define BF_CLKCTRL_SSP1_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
 #define BM_CLKCTRL_SSP1_DIV_FRAC_EN     0x00000200
 #define BP_CLKCTRL_SSP1_DIV     0
 #define BM_CLKCTRL_SSP1_DIV     0x000001FF
@@ -317,12 +230,7 @@
 #define BP_CLKCTRL_SSP2_CLKGATE 31
 #define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP2_RSRVD2  0x40000000
 #define BM_CLKCTRL_SSP2_BUSY    0x20000000
-#define BP_CLKCTRL_SSP2_RSRVD1  10
-#define BM_CLKCTRL_SSP2_RSRVD1  0x1FFFFC00
-#define BF_CLKCTRL_SSP2_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
 #define BM_CLKCTRL_SSP2_DIV_FRAC_EN     0x00000200
 #define BP_CLKCTRL_SSP2_DIV     0
 #define BM_CLKCTRL_SSP2_DIV     0x000001FF
@@ -333,12 +241,7 @@
 #define BP_CLKCTRL_SSP3_CLKGATE 31
 #define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP3_RSRVD2  0x40000000
 #define BM_CLKCTRL_SSP3_BUSY    0x20000000
-#define BP_CLKCTRL_SSP3_RSRVD1  10
-#define BM_CLKCTRL_SSP3_RSRVD1  0x1FFFFC00
-#define BF_CLKCTRL_SSP3_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
 #define BM_CLKCTRL_SSP3_DIV_FRAC_EN     0x00000200
 #define BP_CLKCTRL_SSP3_DIV     0
 #define BM_CLKCTRL_SSP3_DIV     0x000001FF
@@ -349,12 +252,7 @@
 #define BP_CLKCTRL_GPMI_CLKGATE 31
 #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
-#define BM_CLKCTRL_GPMI_RSRVD2  0x40000000
 #define BM_CLKCTRL_GPMI_BUSY    0x20000000
-#define BP_CLKCTRL_GPMI_RSRVD1  11
-#define BM_CLKCTRL_GPMI_RSRVD1  0x1FFFF800
-#define BF_CLKCTRL_GPMI_RSRVD1(v)  \
-                (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
 #define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x00000400
 #define BP_CLKCTRL_GPMI_DIV     0
 #define BM_CLKCTRL_GPMI_DIV     0x000003FF
@@ -365,10 +263,6 @@
 #define BP_CLKCTRL_SPDIF_CLKGATE        31
 #define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
-#define BP_CLKCTRL_SPDIF_RSRVD  0
-#define BM_CLKCTRL_SPDIF_RSRVD  0x7FFFFFFF
-#define BF_CLKCTRL_SPDIF_RSRVD(v)  \
-                (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
 #define HW_CLKCTRL_EMI  (0x000000f0)
@@ -379,24 +273,12 @@
 #define BM_CLKCTRL_EMI_BUSY_REF_EMI     0x10000000
 #define BM_CLKCTRL_EMI_BUSY_REF_CPU     0x08000000
 #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE   0x04000000
-#define BP_CLKCTRL_EMI_RSRVD3   18
-#define BM_CLKCTRL_EMI_RSRVD3   0x03FC0000
-#define BF_CLKCTRL_EMI_RSRVD3(v)  \
-                (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
 #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC  0x00020000
 #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x00010000
-#define BP_CLKCTRL_EMI_RSRVD2   12
-#define BM_CLKCTRL_EMI_RSRVD2   0x0000F000
-#define BF_CLKCTRL_EMI_RSRVD2(v)  \
-                (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
 #define BP_CLKCTRL_EMI_DIV_XTAL 8
 #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
 #define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
                (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
-#define BP_CLKCTRL_EMI_RSRVD1   6
-#define BM_CLKCTRL_EMI_RSRVD1   0x000000C0
-#define BF_CLKCTRL_EMI_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
 #define BP_CLKCTRL_EMI_DIV_EMI  0
 #define BM_CLKCTRL_EMI_DIV_EMI  0x0000003F
 #define BF_CLKCTRL_EMI_DIV_EMI(v)  \
@@ -406,12 +288,7 @@
 #define BP_CLKCTRL_SAIF0_CLKGATE        31
 #define BM_CLKCTRL_SAIF0_CLKGATE        0x80000000
-#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
 #define BM_CLKCTRL_SAIF0_BUSY   0x20000000
-#define BP_CLKCTRL_SAIF0_RSRVD1 17
-#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
-#define BF_CLKCTRL_SAIF0_RSRVD1(v)  \
-                (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
 #define BM_CLKCTRL_SAIF0_DIV_FRAC_EN    0x00010000
 #define BP_CLKCTRL_SAIF0_DIV    0
 #define BM_CLKCTRL_SAIF0_DIV    0x0000FFFF
@@ -422,12 +299,7 @@
 #define BP_CLKCTRL_SAIF1_CLKGATE        31
 #define BM_CLKCTRL_SAIF1_CLKGATE        0x80000000
-#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
 #define BM_CLKCTRL_SAIF1_BUSY   0x20000000
-#define BP_CLKCTRL_SAIF1_RSRVD1 17
-#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
-#define BF_CLKCTRL_SAIF1_RSRVD1(v)  \
-                (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
 #define BM_CLKCTRL_SAIF1_DIV_FRAC_EN    0x00010000
 #define BP_CLKCTRL_SAIF1_DIV    0
 #define BM_CLKCTRL_SAIF1_DIV    0x0000FFFF
@@ -438,12 +310,7 @@
 #define BP_CLKCTRL_DIS_LCDIF_CLKGATE    31
 #define BM_CLKCTRL_DIS_LCDIF_CLKGATE    0x80000000
-#define BM_CLKCTRL_DIS_LCDIF_RSRVD2     0x40000000
 #define BM_CLKCTRL_DIS_LCDIF_BUSY       0x20000000
-#define BP_CLKCTRL_DIS_LCDIF_RSRVD1     14
-#define BM_CLKCTRL_DIS_LCDIF_RSRVD1     0x1FFFC000
-#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v)  \
-                (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
 #define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN        0x00002000
 #define BP_CLKCTRL_DIS_LCDIF_DIV        0
 #define BM_CLKCTRL_DIS_LCDIF_DIV        0x00001FFF
@@ -453,12 +320,7 @@
 #define HW_CLKCTRL_ETM  (0x00000130)
 #define BM_CLKCTRL_ETM_CLKGATE  0x80000000
-#define BM_CLKCTRL_ETM_RSRVD2   0x40000000
 #define BM_CLKCTRL_ETM_BUSY     0x20000000
-#define BP_CLKCTRL_ETM_RSRVD1   8
-#define BM_CLKCTRL_ETM_RSRVD1   0x1FFFFF00
-#define BF_CLKCTRL_ETM_RSRVD1(v)  \
-                (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
 #define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x00000080
 #define BP_CLKCTRL_ETM_DIV      0
 #define BM_CLKCTRL_ETM_DIV      0x0000007F
@@ -471,7 +333,6 @@
 #define BP_CLKCTRL_ENET_DISABLE 30
 #define BM_CLKCTRL_ENET_DISABLE 0x40000000
 #define BM_CLKCTRL_ENET_STATUS  0x20000000
-#define BM_CLKCTRL_ENET_RSRVD1  0x10000000
 #define BM_CLKCTRL_ENET_BUSY_TIME       0x08000000
 #define BP_CLKCTRL_ENET_DIV_TIME        21
 #define BM_CLKCTRL_ENET_DIV_TIME        0x07E00000
@@ -493,37 +354,23 @@
 #define BM_CLKCTRL_ENET_CLK_OUT_EN      0x00040000
 #define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP        0x00020000
 #define BM_CLKCTRL_ENET_RESET_BY_SW     0x00010000
-#define BP_CLKCTRL_ENET_RSRVD0  0
-#define BM_CLKCTRL_ENET_RSRVD0  0x0000FFFF
-#define BF_CLKCTRL_ENET_RSRVD0(v)  \
-                (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
 #define HW_CLKCTRL_HSADC        (0x00000150)
-#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
 #define BM_CLKCTRL_HSADC_RESETB 0x40000000
 #define BP_CLKCTRL_HSADC_FREQDIV        28
 #define BM_CLKCTRL_HSADC_FREQDIV        0x30000000
 #define BF_CLKCTRL_HSADC_FREQDIV(v)  \
                (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
-#define BP_CLKCTRL_HSADC_RSRVD1 0
-#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
-#define BF_CLKCTRL_HSADC_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
 #define HW_CLKCTRL_FLEXCAN      (0x00000160)
-#define BM_CLKCTRL_FLEXCAN_RSRVD2       0x80000000
 #define BP_CLKCTRL_FLEXCAN_STOP_CAN0    30
 #define BM_CLKCTRL_FLEXCAN_STOP_CAN0    0x40000000
 #define BM_CLKCTRL_FLEXCAN_CAN0_STATUS  0x20000000
 #define BP_CLKCTRL_FLEXCAN_STOP_CAN1    28
 #define BM_CLKCTRL_FLEXCAN_STOP_CAN1    0x10000000
 #define BM_CLKCTRL_FLEXCAN_CAN1_STATUS  0x08000000
-#define BP_CLKCTRL_FLEXCAN_RSRVD1       0
-#define BM_CLKCTRL_FLEXCAN_RSRVD1       0x07FFFFFF
-#define BF_CLKCTRL_FLEXCAN_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
 #define HW_CLKCTRL_FRAC0        (0x000001b0)
 #define HW_CLKCTRL_FRAC0_SET    (0x000001b4)
@@ -564,10 +411,6 @@
 #define HW_CLKCTRL_FRAC1_CLR    (0x000001c8)
 #define HW_CLKCTRL_FRAC1_TOG    (0x000001cc)
-#define BP_CLKCTRL_FRAC1_RSRVD2 24
-#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
-#define BF_CLKCTRL_FRAC1_RSRVD2(v) \
-                (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
 #define BP_CLKCTRL_FRAC1_CLKGATEGPMI    23
 #define BM_CLKCTRL_FRAC1_CLKGATEGPMI    0x00800000
 #define BM_CLKCTRL_FRAC1_GPMI_STABLE    0x00400000
@@ -595,22 +438,10 @@
 #define HW_CLKCTRL_CLKSEQ_CLR   (0x000001d8)
 #define HW_CLKCTRL_CLKSEQ_TOG   (0x000001dc)
-#define BP_CLKCTRL_CLKSEQ_RSRVD0        19
-#define BM_CLKCTRL_CLKSEQ_RSRVD0        0xFFF80000
-#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
-                (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
 #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU    0x00040000
-#define BP_CLKCTRL_CLKSEQ_RSRVD1        15
-#define BM_CLKCTRL_CLKSEQ_RSRVD1        0x00038000
-#define BF_CLKCTRL_CLKSEQ_RSRVD1(v)  \
-                (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
 #define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF      0x00004000
 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD    0x0
-#define BP_CLKCTRL_CLKSEQ_RSRVD2        9
-#define BM_CLKCTRL_CLKSEQ_RSRVD2        0x00003E00
-#define BF_CLKCTRL_CLKSEQ_RSRVD2(v)  \
-                (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
 #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM    0x00000100
 #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI    0x00000080
 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3   0x00000040
@@ -623,10 +454,6 @@
 #define HW_CLKCTRL_RESET        (0x000001e0)
-#define BP_CLKCTRL_RESET_RSRVD  6
-#define BM_CLKCTRL_RESET_RSRVD  0xFFFFFFC0
-#define BF_CLKCTRL_RESET_RSRVD(v) \
-                (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
 #define BM_CLKCTRL_RESET_WDOG_POR_DISABLE       0x00000020
 #define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE  0x00000010
 #define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE   0x00000008
@@ -640,10 +467,6 @@
 #define BM_CLKCTRL_STATUS_CPU_LIMIT     0xC0000000
 #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
                (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
-#define BP_CLKCTRL_STATUS_RSRVD 0
-#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
-#define BF_CLKCTRL_STATUS_RSRVD(v)  \
-                (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
 #define HW_CLKCTRL_VERSION      (0x00000200)
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 9343d7edd4f6..20ec3bddf7cd 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -22,6 +22,7 @@
 #include <linux/err.h>
 #include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/module.h>
 #include <asm/proc-fns.h>
 #include <asm/system.h>
@@ -135,3 +136,4 @@ error:
        pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
        return -ETIMEDOUT;
 }
+EXPORT_SYMBOL(mxs_reset_block);
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 337392c3f549..acb7ae5b0a25 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -77,7 +77,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
        dd = clk->dpll_data;
        /* DPLL divider must result in a valid jitter correction val */
-        fint = clk->parent->rate / (n + 1);
+        fint = clk->parent->rate / n;
        if (fint < DPLL_FINT_BAND1_MIN) {
                pr_debug("rejecting n=%d due to Fint failure, "
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 394413dc7deb..24b88504df0f 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -193,10 +193,12 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
                omap_mbox_type_t irq)
 {
        struct omap_mbox2_priv *p = mbox->priv;
-        u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
+        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
-        l = mbox_read_reg(p->irqdisable);
-        l &= ~bit;
+        if (!cpu_is_omap44xx())
-        mbox_write_reg(l, p->irqdisable);
+                bit = mbox_read_reg(p->irqdisable) & ~bit;
+        mbox_write_reg(bit, p->irqdisable);
 }
 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
@@ -334,7 +336,7 @@ static struct omap_mbox mbox_iva_info = {
        .priv   = &omap2_mbox_iva_priv,
 };
-struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
+struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
 #endif
 #if defined(CONFIG_ARCH_OMAP4)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 98148b6c36e9..6c84659cf846 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -605,7 +605,7 @@ static void __init omap_mux_dbg_create_entry(
        list_for_each_entry(e, &partition->muxmodes, node) {
                struct omap_mux *m = &e->mux;
-                (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
+                (void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir,
                                          m, &omap_mux_dbg_signal_fops);
        }
 }
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 125f56591fb5..a5a83b358ddd 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -637,14 +637,14 @@ static int __init pm_dbg_init(void)
                }
-        (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
+        (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
                                   &enable_off_mode, &pm_dbg_option_fops);
-        (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
+        (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
                                   &sleep_while_idle, &pm_dbg_option_fops);
-        (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
+        (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
                                   &wakeup_timer_seconds, &pm_dbg_option_fops);
        (void) debugfs_create_file("wakeup_timer_milliseconds",
-                        S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds,
+                        S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
                        &pm_dbg_option_fops);
        pm_dbg_init_done = 1;
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 729a644ce852..3300ff6e3cfe 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -38,8 +38,8 @@
 #define OMAP4430_PRCM_MPU_CPU1_INST             0x0800
 /* PRCM_MPU clockdomain register offsets (from instance start) */
-#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS       0x0000
+#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS       0x0018
-#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS       0x0000
+#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS       0x0018
 /*
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index c37e823266d3..1a777e34d0c2 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -282,6 +282,7 @@ error:
                dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
                        "interrupt handler. Smartreflex will"
                        "not function as desired\n", __func__);
+                kfree(name);
                kfree(sr_info);
                return ret;
 }
@@ -879,7 +880,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                ret = sr_late_init(sr_info);
                if (ret) {
                        pr_warning("%s: Error in SR late init\n", __func__);
-                        return ret;
+                        goto err_release_region;
                }
        }
@@ -890,17 +891,20 @@ static int __init omap_sr_probe(struct platform_device *pdev)
         * not try to create rest of the debugfs entries.
         */
        vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
-        if (!vdd_dbg_dir)
+        if (!vdd_dbg_dir) {
-                return -EINVAL;
+                ret = -EINVAL;
+                goto err_release_region;
+        }
        dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
        if (IS_ERR(dbg_dir)) {
                dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
                        __func__);
-                return PTR_ERR(dbg_dir);
+                ret = PTR_ERR(dbg_dir);
+                goto err_release_region;
        }
-        (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir,
+        (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, dbg_dir,
                                (void *)sr_info, &pm_sr_fops);
        (void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir,
                        &sr_info->err_weight);
@@ -913,7 +917,8 @@ static int __init omap_sr_probe(struct platform_device *pdev)
        if (IS_ERR(nvalue_dir)) {
                dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
                        "for n-values\n", __func__);
-                return PTR_ERR(nvalue_dir);
+                ret = PTR_ERR(nvalue_dir);
+                goto err_release_region;
        }
        omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
@@ -922,24 +927,16 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                        " corresponding vdd vdd_%s. Cannot create debugfs"
                        "entries for n-values\n",
                        __func__, sr_info->voltdm->name);
-                return -ENODATA;
+                ret = -ENODATA;
+                goto err_release_region;
        }
        for (i = 0; i < sr_info->nvalue_count; i++) {
-                char *name;
+                char name[NVALUE_NAME_LEN + 1];
-                char volt_name[32];
-                name = kzalloc(NVALUE_NAME_LEN + 1, GFP_KERNEL);
-                if (!name) {
-                        dev_err(&pdev->dev, "%s: Unable to allocate memory"
-                                " for n-value directory name\n",  __func__);
-                        return -ENOMEM;
-                }
-                strcpy(name, "volt_");
+                snprintf(name, sizeof(name), "volt_%d",
-                sprintf(volt_name, "%d", volt_data[i].volt_nominal);
+                         volt_data[i].volt_nominal);
-                strcat(name, volt_name);
+                (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
-                (void) debugfs_create_x32(name, S_IRUGO | S_IWUGO, nvalue_dir,
                                &(sr_info->nvalue_table[i].nvalue));
        }
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 7b7c2683ae7b..0fc550e7e482 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -39,6 +39,7 @@
 #include <asm/mach/time.h>
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
+#include <asm/sched_clock.h>
 #include "timer-gp.h"
@@ -190,6 +191,7 @@ static void __init omap2_gp_clocksource_init(void)
 /*
 * clocksource
 */
+static DEFINE_CLOCK_DATA(cd);
 static struct omap_dm_timer *gpt_clocksource;
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
@@ -204,6 +206,15 @@ static struct clocksource clocksource_gpt = {
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
+static void notrace dmtimer_update_sched_clock(void)
+{
+        u32 cyc;
+        cyc = omap_dm_timer_read_counter(gpt_clocksource);
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
 /* Setup free-running counter for clocksource */
 static void __init omap2_gp_clocksource_init(void)
 {
@@ -224,6 +235,8 @@ static void __init omap2_gp_clocksource_init(void)
        omap_dm_timer_set_load_start(gpt, 1, 0);
+        init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
        if (clocksource_register_hz(&clocksource_gpt, tick_rate))
                printk(err2, clocksource_gpt.name);
 }
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 8dc2c76d2260..986c3bf4e6b8 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -26,6 +26,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <mach/bridge-regs.h>
 #include <mach/hardware.h>
 #include <mach/orion5x.h>
 #include <plat/ehci-orion.h>
@@ -599,6 +600,11 @@ void __init orion5x_wdt_init(void)
 /*****************************************************************************
 * Time handling
 ****************************************************************************/
+void __init orion5x_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
 int orion5x_tclk;
 int __init orion5x_find_tclk(void)
@@ -616,7 +622,9 @@ int __init orion5x_find_tclk(void)
 static void orion5x_timer_init(void)
 {
        orion5x_tclk = orion5x_find_tclk();
-        orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
+        orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_ORION5X_BRIDGE, orion5x_tclk);
 }
 struct sys_timer orion5x_timer = {
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 8f004503c96d..f2b2b35e8646 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -9,6 +9,7 @@ struct mv_sata_platform_data;
 * Basic Orion init functions used early by machine-setup.
 */
 void orion5x_map_io(void);
+void orion5x_init_early(void);
 void orion5x_init_irq(void);
 void orion5x_init(void);
 extern int orion5x_tclk;
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index b1c451f5ee27..425807579303 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -339,6 +339,7 @@ MACHINE_START(D2NET, "LaCie d2 Network")
        .boot_params    = 0x00000100,
        .init_machine   = d2net_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
@@ -350,6 +351,7 @@ MACHINE_START(BIGDISK, "LaCie Big Disk Network")
        .boot_params    = 0x00000100,
        .init_machine   = d2net_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index df1083f5b6eb..c10a11715376 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -361,6 +361,7 @@ MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
        .boot_params    = 0x00000100,
        .init_machine   = db88f5281_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 3a7bc0e36982..90ab022eabeb 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -733,6 +733,7 @@ MACHINE_START(DNS323, "D-Link DNS-323")
        .boot_params    = 0x00000100,
        .init_machine   = dns323_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index ba98459f44b0..d037a90c216c 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -254,6 +254,7 @@ MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
        .boot_params    = 0x00000100,
        .init_machine   = edmini_v2_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 5c9744cd8ef6..96484bcd34ca 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -22,14 +22,12 @@
 #define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
+#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
 #define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
-#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
 #define WDT_INT_REQ             0x0008
-#define BRIDGE_MASK             (ORION5X_BRIDGE_VIRT_BASE | 0x114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 #define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE | 0x200)
diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h
index d8182e87ac16..a1d0b78decb1 100644
--- a/arch/arm/mach-orion5x/include/mach/gpio.h
+++ b/arch/arm/mach-orion5x/include/mach/gpio.h
@@ -6,32 +6,4 @@
 * warranty of any kind, whether express or implied.
 */
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-#define GPIO_MAX                32
-#define GPIO_OUT(pin)           ORION5X_DEV_BUS_REG(0x100)
-#define GPIO_IO_CONF(pin)       ORION5X_DEV_BUS_REG(0x104)
-#define GPIO_BLINK_EN(pin)      ORION5X_DEV_BUS_REG(0x108)
-#define GPIO_IN_POL(pin)        ORION5X_DEV_BUS_REG(0x10c)
-#define GPIO_DATA_IN(pin)       ORION5X_DEV_BUS_REG(0x110)
-#define GPIO_EDGE_CAUSE(pin)    ORION5X_DEV_BUS_REG(0x114)
-#define GPIO_EDGE_MASK(pin)     ORION5X_DEV_BUS_REG(0x118)
-#define GPIO_LEVEL_MASK(pin)    ORION5X_DEV_BUS_REG(0x11c)
-static inline int gpio_to_irq(int pin)
-{
-        return pin + IRQ_ORION5X_GPIO_START;
-}
-static inline int irq_to_gpio(int irq)
-{
-        return irq - IRQ_ORION5X_GPIO_START;
-}
-#endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 2d8766570531..0a28bbc76891 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -73,6 +73,7 @@
 #define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
 #define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
 #define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define  GPIO_VIRT_BASE                 ORION5X_DEV_BUS_REG(0x0100)
 #define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
 #define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
 #define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index d7512b925a85..ed85891f8699 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -28,27 +28,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 void __init orion5x_init_irq(void)
 {
-        int i;
        orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
        /*
-         * Mask and clear GPIO IRQ interrupts
+         * Initialize gpiolib for GPIOs 0-31.
-         */
-        writel(0x0, GPIO_LEVEL_MASK(0));
-        writel(0x0, GPIO_EDGE_MASK(0));
-        writel(0x0, GPIO_EDGE_CAUSE(0));
-        /*
-         * Register chained level handlers for GPIO IRQs by default.
-         * User can use set_type() if he wants to use edge types handlers.
         */
-        for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
+        orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
        set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
        set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
        set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 4be9aa08de69..47497c76162a 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -382,6 +382,7 @@ MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
        .boot_params    = 0x00000100,
        .init_machine   = kurobox_pro_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
@@ -394,6 +395,7 @@ MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
        .boot_params    = 0x00000100,
        .init_machine   = kurobox_pro_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 20a9b66cbafa..6ae12aa6d759 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -321,6 +321,7 @@ MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
        .boot_params    = 0x00000100,
        .init_machine   = lschl_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 437364b7168e..7adafd79cf98 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -268,6 +268,7 @@ MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
        .boot_params    = 0x00000100,
        .init_machine   = ls_hgl_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index ab9b0cf0a90b..869958f5c394 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -270,6 +270,7 @@ MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
        .boot_params    = 0x00000100,
        .init_machine   = lsmini_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index db485d3b8144..2288207726e4 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -124,9 +124,6 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
        u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
        u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
-        /* Initialize gpiolib. */
-        orion_gpio_init();
        for ( ; mode->mpp >= 0; mode++) {
                u32 *reg;
                int num_type;
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 2f0e16cd7e81..b43b208153cb 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -264,6 +264,7 @@ MACHINE_START(MSS2, "Maxtor Shared Storage II")
        .boot_params    = 0x00000100,
        .init_machine   = mss2_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index b3d90f25de9f..c55d071707f5 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -232,6 +232,7 @@ MACHINE_START(MV2120, "HP Media Vault mv2120")
        .boot_params    = 0x00000100,
        .init_machine   = mv2120_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index d6665b31665f..429ecafe9fdd 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -422,6 +422,7 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network")
        .boot_params    = 0x00000100,
        .init_machine   = net2big_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index f4c26fd731f4..34310ab56e29 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -172,6 +172,7 @@ MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
        .boot_params    = 0x00000100,
        .init_machine   = rd88f5181l_fxo_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index b5942909bab0..c1f79fa014ed 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -184,6 +184,7 @@ MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
        .boot_params    = 0x00000100,
        .init_machine   = rd88f5181l_ge_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 165ed87029b2..67ec6959b267 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -308,6 +308,7 @@ MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
        .boot_params    = 0x00000100,
        .init_machine   = rd88f5182_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 02ff45f3e2e3..b080c6966d10 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -126,6 +126,7 @@ MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
        .boot_params    = 0x00000100,
        .init_machine   = rd88f6183ap_ge_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 4403fae5ab0e..5653ee6c71d8 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -361,6 +361,7 @@ MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
        .boot_params    = 0x00000100,
        .init_machine   = tsp2_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 1e196129d763..8bbd27ea6735 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -325,6 +325,7 @@ MACHINE_START(TS209, "QNAP TS-109/TS-209")
        .boot_params    = 0x00000100,
        .init_machine   = qnap_ts209_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 428af2046e36..92f393f08fa4 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -314,6 +314,7 @@ MACHINE_START(TS409, "QNAP TS-409")
        .boot_params    = 0x00000100,
        .init_machine   = qnap_ts409_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h
index 37b3d4875291..151e89e1e676 100644
--- a/arch/arm/mach-orion5x/ts78xx-fpga.h
+++ b/arch/arm/mach-orion5x/ts78xx-fpga.h
@@ -1,3 +1,4 @@
+#define TS7800_FPGA_MAGIC 0x00b480
 #define FPGAID(_magic, _rev) ((_magic << 8) + _rev)
 /*
@@ -6,11 +7,15 @@
 */
 enum fpga_ids {
        /* Technologic Systems */
-        TS7800_REV_1    = FPGAID(0x00b480, 0x01),
+        TS7800_REV_1    = FPGAID(TS7800_FPGA_MAGIC, 0x01),
-        TS7800_REV_2    = FPGAID(0x00b480, 0x02),
+        TS7800_REV_2    = FPGAID(TS7800_FPGA_MAGIC, 0x02),
-        TS7800_REV_3    = FPGAID(0x00b480, 0x03),
+        TS7800_REV_3    = FPGAID(TS7800_FPGA_MAGIC, 0x03),
-        TS7800_REV_4    = FPGAID(0x00b480, 0x04),
+        TS7800_REV_4    = FPGAID(TS7800_FPGA_MAGIC, 0x04),
-        TS7800_REV_5    = FPGAID(0x00b480, 0x05),
+        TS7800_REV_5    = FPGAID(TS7800_FPGA_MAGIC, 0x05),
+        TS7800_REV_6    = FPGAID(TS7800_FPGA_MAGIC, 0x06),
+        TS7800_REV_7    = FPGAID(TS7800_FPGA_MAGIC, 0x07),
+        TS7800_REV_8    = FPGAID(TS7800_FPGA_MAGIC, 0x08),
+        TS7800_REV_9    = FPGAID(TS7800_FPGA_MAGIC, 0x09),
        /* Unaffordable & Expensive */
        UAE_DUMMY       = FPGAID(0xffffff, 0x01),
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index c1c1cd04bdde..8554707d20a9 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -191,6 +191,60 @@ static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
        return readb(TS_NAND_CTRL) & 0x20;
 }
+static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
+                        const uint8_t *buf, int len)
+{
+        struct nand_chip *chip = mtd->priv;
+        void __iomem *io_base = chip->IO_ADDR_W;
+        unsigned long off = ((unsigned long)buf & 3);
+        int sz;
+        if (off) {
+                sz = min_t(int, 4 - off, len);
+                writesb(io_base, buf, sz);
+                buf += sz;
+                len -= sz;
+        }
+        sz = len >> 2;
+        if (sz) {
+                u32 *buf32 = (u32 *)buf;
+                writesl(io_base, buf32, sz);
+                buf += sz << 2;
+                len -= sz << 2;
+        }
+        if (len)
+                writesb(io_base, buf, len);
+}
+static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
+                        uint8_t *buf, int len)
+{
+        struct nand_chip *chip = mtd->priv;
+        void __iomem *io_base = chip->IO_ADDR_R;
+        unsigned long off = ((unsigned long)buf & 3);
+        int sz;
+        if (off) {
+                sz = min_t(int, 4 - off, len);
+                readsb(io_base, buf, sz);
+                buf += sz;
+                len -= sz;
+        }
+        sz = len >> 2;
+        if (sz) {
+                u32 *buf32 = (u32 *)buf;
+                readsl(io_base, buf32, sz);
+                buf += sz << 2;
+                len -= sz << 2;
+        }
+        if (len)
+                readsb(io_base, buf, len);
+}
 const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
 static struct mtd_partition ts78xx_ts_nand_parts[] = {
@@ -233,6 +287,8 @@ static struct platform_nand_data ts78xx_ts_nand_data = {
                 */
                .cmd_ctrl               = ts78xx_ts_nand_cmd_ctrl,
                .dev_ready              = ts78xx_ts_nand_dev_ready,
+                .write_buf              = ts78xx_ts_nand_write_buf,
+                .read_buf               = ts78xx_ts_nand_read_buf,
        },
 };
@@ -334,14 +390,29 @@ static void ts78xx_fpga_supports(void)
        case TS7800_REV_3:
        case TS7800_REV_4:
        case TS7800_REV_5:
+        case TS7800_REV_6:
+        case TS7800_REV_7:
+        case TS7800_REV_8:
+        case TS7800_REV_9:
                ts78xx_fpga.supports.ts_rtc.present = 1;
                ts78xx_fpga.supports.ts_nand.present = 1;
                ts78xx_fpga.supports.ts_rng.present = 1;
                break;
        default:
-                ts78xx_fpga.supports.ts_rtc.present = 0;
+                /* enable devices if magic matches */
-                ts78xx_fpga.supports.ts_nand.present = 0;
+                switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
-                ts78xx_fpga.supports.ts_rng.present = 0;
+                case TS7800_FPGA_MAGIC:
+                        printk(KERN_WARNING "TS-7800 FPGA: unrecognized revision 0x%.2x\n",
+                                        ts78xx_fpga.id & 0xff);
+                        ts78xx_fpga.supports.ts_rtc.present = 1;
+                        ts78xx_fpga.supports.ts_nand.present = 1;
+                        ts78xx_fpga.supports.ts_rng.present = 1;
+                        break;
+                default:
+                        ts78xx_fpga.supports.ts_rtc.present = 0;
+                        ts78xx_fpga.supports.ts_nand.present = 0;
+                        ts78xx_fpga.supports.ts_rng.present = 0;
+                }
        }
 }
@@ -553,6 +624,7 @@ MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
        .boot_params    = 0x00000100,
        .init_machine   = ts78xx_init,
        .map_io         = ts78xx_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 7994d6ec08a8..4e5216be0745 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -175,6 +175,7 @@ MACHINE_START(WNR854T, "Netgear WNR854T")
        .boot_params    = 0x00000100,
        .init_machine   = wnr854t_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index a5989b7eb53e..fab79d09cc5c 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -263,6 +263,7 @@ MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
        .boot_params    = 0x00000100,
        .init_machine   = wrt350n_v2_init,
        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index fbc5b775f895..b166b1d845d7 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -347,6 +347,7 @@ static struct platform_device *pxa25x_devices[] __initdata = {
        &pxa25x_device_assp,
        &pxa25x_device_pwm0,
        &pxa25x_device_pwm1,
+        &pxa_device_asoc_platform,
 };
 static struct sys_device pxa25x_sysdev[] = {
diff --git a/arch/arm/mach-pxa/tosa-bt.c b/arch/arm/mach-pxa/tosa-bt.c
index c31e601eb49c..b9b1e5c2b290 100644
--- a/arch/arm/mach-pxa/tosa-bt.c
+++ b/arch/arm/mach-pxa/tosa-bt.c
@@ -81,8 +81,6 @@ static int tosa_bt_probe(struct platform_device *dev)
                goto err_rfk_alloc;
        }
-        rfkill_set_led_trigger_name(rfk, "tosa-bt");
        rc = rfkill_register(rfk);
        if (rc)
                goto err_rfkill;
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index af152e70cfcf..f2582ec300d9 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -875,6 +875,11 @@ static struct platform_device sharpsl_rom_device = {
        .dev.platform_data = &sharpsl_rom_data,
 };
+static struct platform_device wm9712_device = {
+        .name   = "wm9712-codec",
+        .id     = -1,
+};
 static struct platform_device *devices[] __initdata = {
        &tosascoop_device,
        &tosascoop_jc_device,
@@ -885,6 +890,7 @@ static struct platform_device *devices[] __initdata = {
        &tosaled_device,
        &tosa_bt_device,
        &sharpsl_rom_device,
+        &wm9712_device,
 };
 static void tosa_poweroff(void)
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index a0cb2581894f..50825a3f91cc 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -99,6 +99,7 @@ config MACH_NEO1973_GTA02
        select POWER_SUPPLY
        select MACH_NEO1973
        select S3C2410_PWM
+        select S3C_DEV_USB_HOST
        help
           Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
diff --git a/arch/arm/mach-s3c2440/include/mach/gta02.h b/arch/arm/mach-s3c2440/include/mach/gta02.h
index 953331d8d56a..3a56a229cac6 100644
--- a/arch/arm/mach-s3c2440/include/mach/gta02.h
+++ b/arch/arm/mach-s3c2440/include/mach/gta02.h
@@ -44,19 +44,19 @@
 #define GTA02v3_GPIO_nUSB_FLT   S3C2410_GPG(10) /* v3 + v4 only */
 #define GTA02v3_GPIO_nGSM_OC    S3C2410_GPG(11) /* v3 + v4 only */
-#define GTA02_GPIO_AMP_SHUT     S3C2440_GPJ1    /* v2 + v3 + v4 only */
+#define GTA02_GPIO_AMP_SHUT     S3C2410_GPJ(1)  /* v2 + v3 + v4 only */
-#define GTA02v1_GPIO_WLAN_GPIO10        S3C2440_GPJ2
+#define GTA02v1_GPIO_WLAN_GPIO10        S3C2410_GPJ(2)
-#define GTA02_GPIO_HP_IN        S3C2440_GPJ2    /* v2 + v3 + v4 only */
+#define GTA02_GPIO_HP_IN        S3C2410_GPJ(2)  /* v2 + v3 + v4 only */
-#define GTA02_GPIO_INT0         S3C2440_GPJ3    /* v2 + v3 + v4 only */
+#define GTA02_GPIO_INT0         S3C2410_GPJ(3)  /* v2 + v3 + v4 only */
-#define GTA02_GPIO_nGSM_EN      S3C2440_GPJ4
+#define GTA02_GPIO_nGSM_EN      S3C2410_GPJ(4)
-#define GTA02_GPIO_3D_RESET     S3C2440_GPJ5
+#define GTA02_GPIO_3D_RESET     S3C2410_GPJ(5)
-#define GTA02_GPIO_nDL_GSM      S3C2440_GPJ6    /* v4 + v5 only */
+#define GTA02_GPIO_nDL_GSM      S3C2410_GPJ(6)  /* v4 + v5 only */
-#define GTA02_GPIO_WLAN_GPIO0   S3C2440_GPJ7
+#define GTA02_GPIO_WLAN_GPIO0   S3C2410_GPJ(7)
-#define GTA02v1_GPIO_BAT_ID     S3C2440_GPJ8
+#define GTA02v1_GPIO_BAT_ID     S3C2410_GPJ(8)
-#define GTA02_GPIO_KEEPACT      S3C2440_GPJ8
+#define GTA02_GPIO_KEEPACT      S3C2410_GPJ(8)
-#define GTA02v1_GPIO_HP_IN      S3C2440_GPJ10
+#define GTA02v1_GPIO_HP_IN      S3C2410_GPJ(10)
-#define GTA02_CHIP_PWD          S3C2440_GPJ11   /* v2 + v3 + v4 only */
+#define GTA02_CHIP_PWD          S3C2410_GPJ(11) /* v2 + v3 + v4 only */
-#define GTA02_GPIO_nWLAN_RESET  S3C2440_GPJ12   /* v2 + v3 + v4 only */
+#define GTA02_GPIO_nWLAN_RESET  S3C2410_GPJ(12) /* v2 + v3 + v4 only */
 #define GTA02_IRQ_GSENSOR_1     IRQ_EINT0
 #define GTA02_IRQ_MODEM         IRQ_EINT1
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index dd3782064508..fdfc4d5e37a1 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -151,6 +151,12 @@ static struct clk init_clocks_off[] = {
                .enable         = s3c64xx_pclk_ctrl,
                .ctrlbit        = S3C_CLKCON_PCLK_IIC,
        }, {
+                .name           = "i2c",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s3c64xx_pclk_ctrl,
+                .ctrlbit        = S3C6410_CLKCON_PCLK_I2C1,
+        }, {
                .name           = "iis",
                .id             = 0,
                .parent         = &clk_p,
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 135db1b41252..c35585cf8c4f 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -690,12 +690,12 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
        regptr = regs + PL080_Cx_BASE(0);
-        for (ch = 0; ch < 8; ch++, chno++, chptr++) {
+        for (ch = 0; ch < 8; ch++, chptr++) {
-                printk(KERN_INFO "%s: registering DMA %d (%p)\n",
+                pr_debug("%s: registering DMA %d (%p)\n",
-                       __func__, chno, regptr);
+                         __func__, chno + ch, regptr);
                chptr->bit = 1 << ch;
-                chptr->number = chno;
+                chptr->number = chno + ch;
                chptr->dmac = dmac;
                chptr->regs = regptr;
                regptr += PL080_Cx_STRIDE;
@@ -704,7 +704,8 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
        /* for the moment, permanently enable the controller */
        writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
-        printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
+        printk(KERN_INFO "PL080: IRQ %d, at %p, channels %d..%d\n",
+               irq, regs, chno, chno+8);
        return 0;
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c
index fd99a82e82c4..92b09085caaa 100644
--- a/arch/arm/mach-s3c64xx/gpiolib.c
+++ b/arch/arm/mach-s3c64xx/gpiolib.c
@@ -72,7 +72,7 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
        .get_pull       = s3c_gpio_getpull_updown,
 };
-int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
+static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
 {
        return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
 }
@@ -138,7 +138,7 @@ static struct s3c_gpio_chip gpio_4bit[] = {
        },
 };
-int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
+static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
 {
        return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
 }
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index e85192a86fbe..a80a3163dd30 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -28,6 +28,7 @@
 #include <linux/delay.h>
 #include <linux/smsc911x.h>
 #include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -351,7 +352,7 @@ static struct regulator_init_data smdk6410_vddpll = {
 /* VDD_UH_MMC, LDO5 on J5 */
 static struct regulator_init_data smdk6410_vdduh_mmc = {
        .constraints = {
-                .name = "PVDD_UH/PVDD_MMC",
+                .name = "PVDD_UH+PVDD_MMC",
                .always_on = 1,
        },
 };
@@ -417,7 +418,7 @@ static struct regulator_init_data smdk6410_vddaudio = {
 /* S3C64xx internal logic & PLL */
 static struct regulator_init_data wm8350_dcdc1_data = {
        .constraints = {
-                .name = "PVDD_INT/PVDD_PLL",
+                .name = "PVDD_INT+PVDD_PLL",
                .min_uV = 1200000,
                .max_uV = 1200000,
                .always_on = 1,
@@ -452,7 +453,7 @@ static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
 static struct regulator_init_data wm8350_dcdc4_data = {
        .constraints = {
-                .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
+                .name = "PVDD_HI+PVDD_EXT+PVDD_SYS+PVCCM2MTV",
                .min_uV = 3000000,
                .max_uV = 3000000,
                .always_on = 1,
@@ -464,7 +465,7 @@ static struct regulator_init_data wm8350_dcdc4_data = {
 /* OTGi/1190-EV1 HPVDD & AVDD */
 static struct regulator_init_data wm8350_ldo4_data = {
        .constraints = {
-                .name = "PVDD_OTGI/HPVDD/AVDD",
+                .name = "PVDD_OTGI+HPVDD+AVDD",
                .min_uV = 1200000,
                .max_uV = 1200000,
                .apply_uV = 1,
@@ -552,7 +553,7 @@ static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
 static struct regulator_init_data wm1192_dcdc3 = {
        .constraints = {
-                .name = "PVDD_MEM/PVDD_GPS",
+                .name = "PVDD_MEM+PVDD_GPS",
                .always_on = 1,
        },
 };
@@ -563,7 +564,7 @@ static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
 static struct regulator_init_data wm1192_ldo1 = {
        .constraints = {
-                .name = "PVDD_LCD/PVDD_EXT",
+                .name = "PVDD_LCD+PVDD_EXT",
                .always_on = 1,
        },
        .consumer_supplies = wm1192_ldo1_consumers,
diff --git a/arch/arm/mach-s3c64xx/setup-keypad.c b/arch/arm/mach-s3c64xx/setup-keypad.c
index f8ed0d22db70..1d4d0ee9e870 100644
--- a/arch/arm/mach-s3c64xx/setup-keypad.c
+++ b/arch/arm/mach-s3c64xx/setup-keypad.c
@@ -17,7 +17,7 @@
 void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
 {
        /* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */
-        s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), 8 + rows, S3C_GPIO_SFN(3));
+        s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), rows, S3C_GPIO_SFN(3));
        /* Set all the necessary GPL pins to special-function 3: KP_COL[x] */
        s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3));
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
index 1a942037c4ef..f344a222bc84 100644
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ b/arch/arm/mach-s3c64xx/setup-sdhci.c
@@ -56,7 +56,7 @@ void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
        else
                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
-        printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
+        pr_debug("%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
        writel(ctrl2, r + S3C_SDHCI_CONTROL2);
        writel(ctrl3, r + S3C_SDHCI_CONTROL3);
 }
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
index 5486c8f01f1d..adb5f298ead8 100644
--- a/arch/arm/mach-s5p64x0/include/mach/gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/gpio.h
@@ -23,7 +23,7 @@
 #define S5P6440_GPIO_A_NR       (6)
 #define S5P6440_GPIO_B_NR       (7)
 #define S5P6440_GPIO_C_NR       (8)
-#define S5P6440_GPIO_F_NR       (2)
+#define S5P6440_GPIO_F_NR       (16)
 #define S5P6440_GPIO_G_NR       (7)
 #define S5P6440_GPIO_H_NR       (10)
 #define S5P6440_GPIO_I_NR       (16)
@@ -36,7 +36,7 @@
 #define S5P6450_GPIO_B_NR       (7)
 #define S5P6450_GPIO_C_NR       (8)
 #define S5P6450_GPIO_D_NR       (8)
-#define S5P6450_GPIO_F_NR       (2)
+#define S5P6450_GPIO_F_NR       (16)
 #define S5P6450_GPIO_G_NR       (14)
 #define S5P6450_GPIO_H_NR       (10)
 #define S5P6450_GPIO_I_NR       (16)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 2123b96b5638..4303a86e6e38 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -454,6 +454,7 @@ static void __init ag5evm_init(void)
        gpio_direction_output(GPIO_PORT217, 0);
        mdelay(1);
        gpio_set_value(GPIO_PORT217, 1);
+        mdelay(100);
        /* LCD backlight controller */
        gpio_request(GPIO_PORT235, NULL); /* RESET */
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 3cf0951caa2d..81d6536552a9 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1303,7 +1303,7 @@ static void __init ap4evb_init(void)
        lcdc_info.clock_source                  = LCDC_CLK_BUS;
        lcdc_info.ch[0].interface_type          = RGB18;
-        lcdc_info.ch[0].clock_divider           = 2;
+        lcdc_info.ch[0].clock_divider           = 3;
        lcdc_info.ch[0].flags                   = 0;
        lcdc_info.ch[0].lcd_size_cfg.width      = 152;
        lcdc_info.ch[0].lcd_size_cfg.height     = 91;
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index fb4213a4e15a..1657eac5dde2 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -303,7 +303,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
                .lcd_cfg = mackerel_lcdc_modes,
                .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
                .interface_type         = RGB24,
-                .clock_divider          = 2,
+                .clock_divider          = 3,
                .flags                  = 0,
                .lcd_size_cfg.width     = 152,
                .lcd_size_cfg.height    = 91,
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index ddd4a1b775f0..7e58904c1c8c 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -263,7 +263,7 @@ static struct clk div6_clks[DIV6_NR] = {
 };
 enum { MSTP001,
-        MSTP125, MSTP118, MSTP116, MSTP100,
+        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
        MSTP219,
        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
        MSTP331, MSTP329, MSTP325, MSTP323, MSTP312,
@@ -275,6 +275,10 @@ enum { MSTP001,
 static struct clk mstp_clks[MSTP_NR] = {
        [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
+        [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* CEU1 */
+        [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* CSI2-RX1 */
+        [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU0 */
+        [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2-RX0 */
        [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
        [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
        [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
@@ -306,6 +310,9 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("r_clk", &r_clk),
        /* DIV6 clocks */
+        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
+        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
+        CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
        CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
@@ -313,11 +320,15 @@ static struct clk_lookup lookups[] = {
        /* MSTP32 clocks */
        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
-        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
+        CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
+        CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
+        CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
+        CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
-        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
+        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
+        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
        CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
index efd3687ba190..3029aba38688 100644
--- a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
@@ -6,13 +6,10 @@ LIST "RWT Setting"
 EW 0xE6020004, 0xA500
 EW 0xE6030004, 0xA500
-DD 0x01001000, 0x01001000
 LIST "GPIO Setting"
 EB 0xE6051013, 0xA2
 LIST "CPG"
-ED 0xE6150080, 0x00000180
 ED 0xE61500C0, 0x00000002
 WAIT 1, 0xFE40009C
@@ -37,6 +34,9 @@ ED 0xE615002C, 0x93000040
 WAIT 1, 0xFE40009C
+LIST "SUB/USBClk"
+ED 0xE6150080, 0x00000180
 LIST "BSC"
 ED 0xFEC10000, 0x00E0001B
@@ -53,7 +53,7 @@ ED 0xFE400048, 0x20C18505
 ED 0xFE40004C, 0x00110209
 ED 0xFE400010, 0x00000087
-WAIT 10, 0xFE40009C
+WAIT 30, 0xFE40009C
 ED 0xFE400084, 0x0000003F
 EB 0xFE500000, 0x00
@@ -84,7 +84,7 @@ ED 0xE6150004, 0x80331050
 WAIT 1, 0xFE40009C
-ED 0xE6150354, 0x00000002
+ED 0xFE400354, 0x01AD8002
 LIST "SCIF0 - Serial port for earlyprintk"
 EB 0xE6053098, 0x11
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
index efd3687ba190..3029aba38688 100644
--- a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
@@ -6,13 +6,10 @@ LIST "RWT Setting"
 EW 0xE6020004, 0xA500
 EW 0xE6030004, 0xA500
-DD 0x01001000, 0x01001000
 LIST "GPIO Setting"
 EB 0xE6051013, 0xA2
 LIST "CPG"
-ED 0xE6150080, 0x00000180
 ED 0xE61500C0, 0x00000002
 WAIT 1, 0xFE40009C
@@ -37,6 +34,9 @@ ED 0xE615002C, 0x93000040
 WAIT 1, 0xFE40009C
+LIST "SUB/USBClk"
+ED 0xE6150080, 0x00000180
 LIST "BSC"
 ED 0xFEC10000, 0x00E0001B
@@ -53,7 +53,7 @@ ED 0xFE400048, 0x20C18505
 ED 0xFE40004C, 0x00110209
 ED 0xFE400010, 0x00000087
-WAIT 10, 0xFE40009C
+WAIT 30, 0xFE40009C
 ED 0xFE400084, 0x0000003F
 EB 0xFE500000, 0x00
@@ -84,7 +84,7 @@ ED 0xE6150004, 0x80331050
 WAIT 1, 0xFE40009C
-ED 0xE6150354, 0x00000002
+ED 0xFE400354, 0x01AD8002
 LIST "SCIF0 - Serial port for earlyprintk"
 EB 0xE6053098, 0x11
diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
index 7991415e666b..c25cf3f84566 100644
--- a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
+++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
@@ -6,6 +6,7 @@
 * published by the Free Software Foundation.
 */
+#include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
@@ -17,6 +18,8 @@
 #include <asm/mach/time.h>
 #include <mach/clock.h>
+#include <mach/tcc-nand.h>
+#include <mach/tcc8k-regs.h>
 #include "common.h"
@@ -51,6 +54,22 @@ static struct sys_timer tcc8k_timer = {
 static void __init tcc8k_map_io(void)
 {
        tcc8k_map_common_io();
+        /* set PLL0 clock to 96MHz, adapt UART0 divisor */
+        __raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS);
+        __raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS);
+        /* set PLL1 clock to 192MHz */
+        __raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS);
+        /* set PLL2 clock to 48MHz */
+        __raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS);
+        /* with CPU freq higher than 150 MHz, need extra DTCM wait */
+        __raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS);
+        /* PLL locking time as specified */
+        udelay(300);
 }
 MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
index 3970a9cdce26..e7cdae5c77a4 100644
--- a/arch/arm/mach-tcc8k/clock.c
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -45,11 +45,12 @@
 #define ACLKGSB1        (CKC_BASE + ACLKGSB1_OFFS)
 #define ACLKGSB2        (CKC_BASE + ACLKGSB2_OFFS)
 #define ACLKGSB3        (CKC_BASE + ACLKGSB3_OFFS)
-#define ACLKUSBH        (CKC_BASE + ACLKUSBH_OFFS)
 #define ACLKTCT         (CKC_BASE + ACLKTCT_OFFS)
 #define ACLKTCX         (CKC_BASE + ACLKTCX_OFFS)
 #define ACLKTCZ         (CKC_BASE + ACLKTCZ_OFFS)
+#define ACLK_MAX_DIV    (0xfff + 1)
 /* Crystal frequencies */
 static unsigned long xi_rate, xti_rate;
@@ -106,9 +107,9 @@ static int root_clk_enable(enum root_clks src)
        return 0;
 }
-static int root_clk_disable(enum root_clks root_src)
+static int root_clk_disable(enum root_clks src)
 {
-        switch (root_src) {
+        switch (src) {
        case CLK_SRC_PLL0: return pll_enable(0, 0);
        case CLK_SRC_PLL1: return pll_enable(1, 0);
        case CLK_SRC_PLL2: return pll_enable(2, 0);
@@ -197,7 +198,7 @@ static unsigned long get_rate_pll_div(int pll)
                addr = CKC_BASE + CLKDIVC1_OFFS;
                reg = __raw_readl(addr);
                if (reg & CLKDIVC1_P2E)
-                        div = __raw_readl(addr) & 0x3f;
+                        div = reg & 0x3f;
                break;
        }
        return get_rate_pll(pll) / (div + 1);
@@ -258,14 +259,19 @@ static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
 {
        unsigned long div, src, freq, r1, r2;
+        if (!rate)
+                return ACLK_MAX_DIV;
        src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
        src &= CLK_SRC_MASK;
        freq = root_clk_get_rate(src);
-        div = freq / rate + 1;
+        div = freq / rate;
+        if (!div)
+                return 1;
+        if (div >= ACLK_MAX_DIV)
+                return ACLK_MAX_DIV;
        r1 = freq / div;
        r2 = freq / (div + 1);
-        if (r2 >= rate)
-                return div + 1;
        if ((rate - r2) < (r1 - rate))
                return div + 1;
@@ -287,7 +293,8 @@ static int aclk_set_rate(struct clk *clk, unsigned long rate)
        u32 reg;
        reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
-        reg |= aclk_best_div(clk, rate);
+        reg |= aclk_best_div(clk, rate) - 1;
+        __raw_writel(reg, clk->aclkreg);
        return 0;
 }
@@ -296,15 +303,22 @@ static unsigned long get_rate_sys(struct clk *clk)
        unsigned int src;
        src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
-                return root_clk_get_rate(src);
+        return root_clk_get_rate(src);
 }
 static unsigned long get_rate_bus(struct clk *clk)
 {
-        unsigned int div;
+        unsigned int reg, sdiv, bdiv, rate;
-        div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
+        reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
-        return get_rate_sys(clk) / (div + 1);
+        rate = get_rate_sys(clk);
+        sdiv = (reg >> 20) & 3;
+        if (sdiv)
+                rate /= sdiv + 1;
+        bdiv = (reg >> 4) & 0xff;
+        if (bdiv)
+                rate /= bdiv + 1;
+        return rate;
 }
 static unsigned long get_rate_cpu(struct clk *clk)
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
index 66ad2760c621..04c779832c78 100644
--- a/arch/arm/mach-tegra/include/mach/kbc.h
+++ b/arch/arm/mach-tegra/include/mach/kbc.h
@@ -57,5 +57,6 @@ struct tegra_kbc_platform_data {
        const struct matrix_keymap_data *keymap_data;
        bool wakeup;
+        bool use_fn_map;
 };
 #endif
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index aa53ee22438f..513d6abec1f5 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
 * arch/arm/mach-u300/core.c
 *
 *
- * Copyright (C) 2007-2010 ST-Ericsson AB
+ * Copyright (C) 2007-2010 ST-Ericsson SA
 * License terms: GNU General Public License (GPL) version 2
 * Core platform support, IRQ handling and device definitions.
 * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -16,7 +16,9 @@
 #include <linux/device.h>
 #include <linux/mm.h>
 #include <linux/termios.h>
+#include <linux/dmaengine.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/serial.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/clk.h>
@@ -96,10 +98,20 @@ void __init u300_map_io(void)
 * Declaration of devices found on the U300 board and
 * their respective memory locations.
 */
+static struct amba_pl011_data uart0_plat_data = {
+#ifdef CONFIG_COH901318
+        .dma_filter = coh901318_filter_id,
+        .dma_rx_param = (void *) U300_DMA_UART0_RX,
+        .dma_tx_param = (void *) U300_DMA_UART0_TX,
+#endif
+};
 static struct amba_device uart0_device = {
        .dev = {
+                .coherent_dma_mask = ~0,
                .init_name = "uart0", /* Slow device at 0x3000 offset */
-                .platform_data = NULL,
+                .platform_data = &uart0_plat_data,
        },
        .res = {
                .start = U300_UART0_BASE,
@@ -111,10 +123,19 @@ static struct amba_device uart0_device = {
 /* The U335 have an additional UART1 on the APP CPU */
 #ifdef CONFIG_MACH_U300_BS335
+static struct amba_pl011_data uart1_plat_data = {
+#ifdef CONFIG_COH901318
+        .dma_filter = coh901318_filter_id,
+        .dma_rx_param = (void *) U300_DMA_UART1_RX,
+        .dma_tx_param = (void *) U300_DMA_UART1_TX,
+#endif
+};
 static struct amba_device uart1_device = {
        .dev = {
+                .coherent_dma_mask = ~0,
                .init_name = "uart1", /* Fast device at 0x7000 offset */
-                .platform_data = NULL,
+                .platform_data = &uart1_plat_data,
        },
        .res = {
                .start = U300_UART1_BASE,
@@ -960,42 +981,37 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 0,
                .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
        },
+        /*
+         * Don't set up device address, burst count or size of src
+         * or dst bus for this peripheral - handled by PrimeCell
+         * DMA extension.
+         */
        {
                .number = U300_DMA_MMCSD_RX_TX,
                .name = "MMCSD RX TX",
                .priority_high = 0,
-                .dev_addr =  U300_MMCSD_BASE + 0x080,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
                .param.ctrl_lli_chained = 0 |
                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
                                COH901318_CX_CTRL_HSP_ENABLE |
                                COH901318_CX_CTRL_HSS_DISABLE |
                                COH901318_CX_CTRL_DDMA_LEGACY,
                .param.ctrl_lli = 0 |
                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
                                COH901318_CX_CTRL_HSP_ENABLE |
                                COH901318_CX_CTRL_HSS_DISABLE |
                                COH901318_CX_CTRL_DDMA_LEGACY,
                .param.ctrl_lli_last = 0 |
                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
                                COH901318_CX_CTRL_TCP_DISABLE |
                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
@@ -1014,15 +1030,76 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .name = "MSPRO RX",
                .priority_high = 0,
        },
+        /*
+         * Don't set up device address, burst count or size of src
+         * or dst bus for this peripheral - handled by PrimeCell
+         * DMA extension.
+         */
        {
                .number = U300_DMA_UART0_TX,
                .name = "UART0 TX",
                .priority_high = 0,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
        },
        {
                .number = U300_DMA_UART0_RX,
                .name = "UART0 RX",
                .priority_high = 0,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
        },
        {
                .number = U300_DMA_APEX_TX,
@@ -1080,7 +1157,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
                                COH901318_CX_CTRL_HSP_ENABLE |
                                COH901318_CX_CTRL_HSS_DISABLE |
                                COH901318_CX_CTRL_DDMA_LEGACY |
@@ -1252,15 +1329,77 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .name = "XGAM PDI",
                .priority_high = 0,
        },
+        /*
+         * Don't set up device address, burst count or size of src
+         * or dst bus for this peripheral - handled by PrimeCell
+         * DMA extension.
+         */
        {
                .number = U300_DMA_SPI_TX,
                .name = "SPI TX",
                .priority_high = 0,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
        },
        {
                .number = U300_DMA_SPI_RX,
                .name = "SPI RX",
                .priority_high = 0,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
        },
        {
                .number = U300_DMA_GENERAL_PURPOSE_0,
@@ -1617,7 +1756,7 @@ static void __init u300_init_check_chip(void)
 #endif
 #ifdef CONFIG_MACH_U300_BS335
        if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
-                printk(KERN_ERR "Platform configured for BS365 " \
+                printk(KERN_ERR "Platform configured for BS335 " \
                       " with DB3350 but %s detected, expect problems!",
                       chipname);
        }
@@ -1692,12 +1831,12 @@ void __init u300_init_devices(void)
        /* Register subdevices on the I2C buses */
        u300_i2c_register_board_devices();
-        /* Register subdevices on the SPI bus */
-        u300_spi_register_board_devices();
        /* Register the platform devices */
        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
+        /* Register subdevices on the SPI bus */
+        u300_spi_register_board_devices();
 #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
        /*
         * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h
index 6193aaa47794..7c3b2b2d25b6 100644
--- a/arch/arm/mach-u300/include/mach/coh901318.h
+++ b/arch/arm/mach-u300/include/mach/coh901318.h
@@ -102,6 +102,7 @@ struct coh901318_platform {
        const int max_channels;
 };
+#ifdef CONFIG_COH901318
 /**
 * coh901318_filter_id() - DMA channel filter function
 * @chan: dma channel handle
@@ -110,6 +111,12 @@ struct coh901318_platform {
 * In dma_request_channel() it specifies what channel id to be requested
 */
 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
+#else
+static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
+{
+        return false;
+}
+#endif
 /*
 * DMA Controller - this access the static mappings of the coh901318 dma.
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
index de1ac9ad2213..677ccef5cd32 100644
--- a/arch/arm/mach-u300/mmc.c
+++ b/arch/arm/mach-u300/mmc.c
@@ -3,159 +3,52 @@
 * arch/arm/mach-u300/mmc.c
 *
 *
- * Copyright (C) 2009 ST-Ericsson AB
+ * Copyright (C) 2009 ST-Ericsson SA
 * License terms: GNU General Public License (GPL) version 2
 *
 * Author: Linus Walleij <linus.walleij@stericsson.com>
- * Author: Johan Lundin <johan.lundin@stericsson.com>
+ * Author: Johan Lundin
 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
 */
 #include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/mmc/host.h>
-#include <linux/input.h>
-#include <linux/workqueue.h>
-#include <linux/delay.h>
-#include <linux/regulator/consumer.h>
-#include <linux/regulator/machine.h>
 #include <linux/gpio.h>
+#include <linux/dmaengine.h>
 #include <linux/amba/mmci.h>
 #include <linux/slab.h>
+#include <mach/coh901318.h>
+#include <mach/dma_channels.h>
 #include "mmc.h"
 #include "padmux.h"
-struct mmci_card_event {
+static struct mmci_platform_data mmc0_plat_data = {
-        struct input_dev *mmc_input;
+        /*
-        int mmc_inserted;
+         * Do not set ocr_mask or voltage translation function,
-        struct work_struct workq;
+         * we have a regulator we can control instead.
-        struct mmci_platform_data mmc0_plat_data;
+         */
+        /* Nominally 2.85V on our platform */
+        .f_max = 24000000,
+        .gpio_wp = -1,
+        .gpio_cd = U300_GPIO_PIN_MMC_CD,
+        .cd_invert = true,
+        .capabilities = MMC_CAP_MMC_HIGHSPEED |
+        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+#ifdef CONFIG_COH901318
+        .dma_filter = coh901318_filter_id,
+        .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
+        /* Don't specify a TX channel, this RX channel is bidirectional */
+#endif
 };
-static unsigned int mmc_status(struct device *dev)
-{
-        struct mmci_card_event *mmci_card = container_of(
-                dev->platform_data,
-                struct mmci_card_event, mmc0_plat_data);
-        return mmci_card->mmc_inserted;
-}
-static int mmci_callback(void *data)
-{
-        struct mmci_card_event *mmci_card = data;
-        disable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD);
-        schedule_work(&mmci_card->workq);
-        return 0;
-}
-static ssize_t gpio_show(struct device *dev, struct device_attribute *attr,
-                  char *buf)
-{
-        struct mmci_card_event *mmci_card = container_of(
-                dev->platform_data,
-                struct mmci_card_event, mmc0_plat_data);
-        return sprintf(buf, "%d\n", !mmci_card->mmc_inserted);
-}
-static DEVICE_ATTR(mmc_inserted, S_IRUGO, gpio_show, NULL);
-static void _mmci_callback(struct work_struct *ws)
-{
-        struct mmci_card_event *mmci_card = container_of(
-                ws,
-                struct mmci_card_event, workq);
-        mdelay(20);
-        mmci_card->mmc_inserted = !gpio_get_value(U300_GPIO_PIN_MMC_CD);
-        input_report_switch(mmci_card->mmc_input, KEY_INSERT,
-                            mmci_card->mmc_inserted);
-        input_sync(mmci_card->mmc_input);
-        pr_debug("MMC/SD card was %s\n",
-                 mmci_card->mmc_inserted ? "inserted" : "removed");
-        enable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD, mmci_card->mmc_inserted);
-}
 int __devinit mmc_init(struct amba_device *adev)
 {
-        struct mmci_card_event *mmci_card;
        struct device *mmcsd_device = &adev->dev;
        struct pmx *pmx;
        int ret = 0;
-        mmci_card = kzalloc(sizeof(struct mmci_card_event), GFP_KERNEL);
+        mmcsd_device->platform_data = &mmc0_plat_data;
-        if (!mmci_card)
-                return -ENOMEM;
-        /*
-         * Do not set ocr_mask or voltage translation function,
-         * we have a regulator we can control instead.
-         */
-        /* Nominally 2.85V on our platform */
-        mmci_card->mmc0_plat_data.f_max = 24000000;
-        mmci_card->mmc0_plat_data.status = mmc_status;
-        mmci_card->mmc0_plat_data.gpio_wp = -1;
-        mmci_card->mmc0_plat_data.gpio_cd = -1;
-        mmci_card->mmc0_plat_data.capabilities = MMC_CAP_MMC_HIGHSPEED |
-                MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
-        mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data;
-        INIT_WORK(&mmci_card->workq, _mmci_callback);
-        ret = gpio_request(U300_GPIO_PIN_MMC_CD, "MMC card detection");
-        if (ret) {
-                printk(KERN_CRIT "Could not allocate MMC card detection " \
-                       "GPIO pin\n");
-                goto out;
-        }
-        ret = gpio_direction_input(U300_GPIO_PIN_MMC_CD);
-        if (ret) {
-                printk(KERN_CRIT "Invalid GPIO pin requested\n");
-                goto out;
-        }
-        ret = sysfs_create_file(&mmcsd_device->kobj,
-                               &dev_attr_mmc_inserted.attr);
-        if (ret)
-                goto out;
-        mmci_card->mmc_input = input_allocate_device();
-        if (!mmci_card->mmc_input) {
-                printk(KERN_CRIT "Could not allocate MMC input device\n");
-                return -ENOMEM;
-        }
-        mmci_card->mmc_input->name = "MMC insert notification";
-        mmci_card->mmc_input->id.bustype = BUS_HOST;
-        mmci_card->mmc_input->id.vendor = 0;
-        mmci_card->mmc_input->id.product = 0;
-        mmci_card->mmc_input->id.version = 0x0100;
-        mmci_card->mmc_input->dev.parent = mmcsd_device;
-        input_set_capability(mmci_card->mmc_input, EV_SW, KEY_INSERT);
-        /*
-         * Since this must always be compiled into the kernel, this input
-         * is never unregistered or free:ed.
-         */
-        ret = input_register_device(mmci_card->mmc_input);
-        if (ret) {
-                input_free_device(mmci_card->mmc_input);
-                goto out;
-        }
-        input_set_drvdata(mmci_card->mmc_input, mmci_card);
        /*
         * Setup padmuxing for MMC. Since this must always be
@@ -171,12 +64,5 @@ int __devinit mmc_init(struct amba_device *adev)
                        pr_warning("Could not activate padmuxing\n");
        }
-        ret = gpio_register_callback(U300_GPIO_PIN_MMC_CD, mmci_callback,
-                                     mmci_card);
-        schedule_work(&mmci_card->workq);
-        printk(KERN_INFO "Registered MMC insert/remove notification\n");
-out:
        return ret;
 }
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index 00869def5420..5767208f1c1d 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -11,6 +11,9 @@
 #include <linux/spi/spi.h>
 #include <linux/amba/pl022.h>
 #include <linux/err.h>
+#include <mach/coh901318.h>
+#include <mach/dma_channels.h>
 #include "padmux.h"
 /*
@@ -30,11 +33,8 @@ static void select_dummy_chip(u32 chipselect)
 }
 struct pl022_config_chip dummy_chip_info = {
-        /*
+        /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
-         * available POLLING_TRANSFER and INTERRUPT_TRANSFER,
+        .com_mode = DMA_TRANSFER,
-         * DMA_TRANSFER does not work
-         */
-        .com_mode = INTERRUPT_TRANSFER,
        .iface = SSP_INTERFACE_MOTOROLA_SPI,
        /* We can only act as master but SSP_SLAVE is possible in theory */
        .hierarchy = SSP_MASTER,
@@ -75,8 +75,6 @@ static struct spi_board_info u300_spi_devices[] = {
 static struct pl022_ssp_controller ssp_platform_data = {
        /* If you have several SPI buses this varies, we have only bus 0 */
        .bus_id = 0,
-        /* Set this to 1 when we think we got DMA working */
-        .enable_dma = 0,
        /*
         * On the APP CPU GPIO 4, 5 and 6 are connected as generic
         * chip selects for SPI. (Same on U330, U335 and U365.)
@@ -84,6 +82,14 @@ static struct pl022_ssp_controller ssp_platform_data = {
         * and do padmuxing accordingly too.
         */
        .num_chipselect = 3,
+#ifdef CONFIG_COH901318
+        .enable_dma = 1,
+        .dma_filter = coh901318_filter_id,
+        .dma_rx_param = (void *) U300_DMA_SPI_RX,
+        .dma_tx_param = (void *) U300_DMA_SPI_TX,
+#else
+        .enable_dma = 0,
+#endif
 };
@@ -109,6 +115,7 @@ void __init u300_spi_init(struct amba_device *adev)
        }
 }
 void __init u300_spi_register_board_devices(void)
 {
        /* Register any SPI devices */
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 53ebb429e971..b549a8fb4231 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -3,16 +3,18 @@
 #
 obj-y                           := clock.o cpu.o devices.o devices-common.o \
-                                   id.o
+                                   id.o usb.o
 obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o prcmu.o
 obj-$(CONFIG_MACH_U8500)        += board-mop500.o board-mop500-sdi.o \
-                                board-mop500-keypads.o
+                                board-mop500-regulators.o \
+                                board-mop500-uib.o board-mop500-stuib.o \
+                                board-mop500-u8500uib.o \
+                                board-mop500-pins.o
 obj-$(CONFIG_MACH_U5500)        += board-u5500.o board-u5500-sdi.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
-obj-$(CONFIG_REGULATOR_AB8500)  += board-mop500-regulators.o
 obj-$(CONFIG_U5500_MODEM_IRQ)   += modem-irq-db5500.o
 obj-$(CONFIG_U5500_MBOX)        += mbox-db5500.o
 obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
diff --git a/arch/arm/mach-ux500/board-mop500-keypads.c b/arch/arm/mach-ux500/board-mop500-keypads.c
deleted file mode 100644
index 70318c354d32..000000000000
--- a/arch/arm/mach-ux500/board-mop500-keypads.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License Terms: GNU General Public License v2
- *
- * Keypad layouts for various boards
- */
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/stmpe.h>
-#include <linux/mfd/tc3589x.h>
-#include <linux/input/matrix_keypad.h>
-#include <plat/pincfg.h>
-#include <plat/ske.h>
-#include <mach/devices.h>
-#include <mach/hardware.h>
-#include "devices-db8500.h"
-#include "board-mop500.h"
-/* STMPE/SKE keypad use this key layout */
-static const unsigned int mop500_keymap[] = {
-        KEY(2, 5, KEY_END),
-        KEY(4, 1, KEY_POWER),
-        KEY(3, 5, KEY_VOLUMEDOWN),
-        KEY(1, 3, KEY_3),
-        KEY(5, 2, KEY_RIGHT),
-        KEY(5, 0, KEY_9),
-        KEY(0, 5, KEY_MENU),
-        KEY(7, 6, KEY_ENTER),
-        KEY(4, 5, KEY_0),
-        KEY(6, 7, KEY_2),
-        KEY(3, 4, KEY_UP),
-        KEY(3, 3, KEY_DOWN),
-        KEY(6, 4, KEY_SEND),
-        KEY(6, 2, KEY_BACK),
-        KEY(4, 2, KEY_VOLUMEUP),
-        KEY(5, 5, KEY_1),
-        KEY(4, 3, KEY_LEFT),
-        KEY(3, 2, KEY_7),
-};
-static const struct matrix_keymap_data mop500_keymap_data = {
-        .keymap         = mop500_keymap,
-        .keymap_size    = ARRAY_SIZE(mop500_keymap),
-};
-/*
- * Nomadik SKE keypad
- */
-#define ROW_PIN_I0      164
-#define ROW_PIN_I1      163
-#define ROW_PIN_I2      162
-#define ROW_PIN_I3      161
-#define ROW_PIN_I4      156
-#define ROW_PIN_I5      155
-#define ROW_PIN_I6      154
-#define ROW_PIN_I7      153
-#define COL_PIN_O0      168
-#define COL_PIN_O1      167
-#define COL_PIN_O2      166
-#define COL_PIN_O3      165
-#define COL_PIN_O4      160
-#define COL_PIN_O5      159
-#define COL_PIN_O6      158
-#define COL_PIN_O7      157
-#define SKE_KPD_MAX_ROWS        8
-#define SKE_KPD_MAX_COLS        8
-static int ske_kp_rows[] = {
-        ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3,
-        ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7,
-};
-/*
- * ske_set_gpio_row: request and set gpio rows
- */
-static int ske_set_gpio_row(int gpio)
-{
-        int ret;
-        ret = gpio_request(gpio, "ske-kp");
-        if (ret < 0) {
-                pr_err("ske_set_gpio_row: gpio request failed\n");
-                return ret;
-        }
-        ret = gpio_direction_output(gpio, 1);
-        if (ret < 0) {
-                pr_err("ske_set_gpio_row: gpio direction failed\n");
-                gpio_free(gpio);
-        }
-        return ret;
-}
-/*
- * ske_kp_init - enable the gpio configuration
- */
-static int ske_kp_init(void)
-{
-        int ret, i;
-        for (i = 0; i < SKE_KPD_MAX_ROWS; i++) {
-                ret = ske_set_gpio_row(ske_kp_rows[i]);
-                if (ret < 0) {
-                        pr_err("ske_kp_init: failed init\n");
-                        return ret;
-                }
-        }
-        return 0;
-}
-static struct ske_keypad_platform_data ske_keypad_board = {
-        .init           = ske_kp_init,
-        .keymap_data    = &mop500_keymap_data,
-        .no_autorepeat  = true,
-        .krow           = SKE_KPD_MAX_ROWS,     /* 8x8 matrix */
-        .kcol           = SKE_KPD_MAX_COLS,
-        .debounce_ms    = 40,                   /* in millisecs */
-};
-/*
- * STMPE1601
- */
-static struct stmpe_keypad_platform_data stmpe1601_keypad_data = {
-        .debounce_ms    = 64,
-        .scan_count     = 8,
-        .no_autorepeat  = true,
-        .keymap_data    = &mop500_keymap_data,
-};
-static struct stmpe_platform_data stmpe1601_data = {
-        .id             = 1,
-        .blocks         = STMPE_BLOCK_KEYPAD,
-        .irq_trigger    = IRQF_TRIGGER_FALLING,
-        .irq_base       = MOP500_STMPE1601_IRQ(0),
-        .keypad         = &stmpe1601_keypad_data,
-        .autosleep      = true,
-        .autosleep_timeout = 1024,
-};
-static struct i2c_board_info mop500_i2c0_devices_stuib[] = {
-        {
-                I2C_BOARD_INFO("stmpe1601", 0x40),
-                .irq = NOMADIK_GPIO_TO_IRQ(218),
-                .platform_data = &stmpe1601_data,
-                .flags = I2C_CLIENT_WAKE,
-        },
-};
-/*
- * TC35893
- */
-static const unsigned int uib_keymap[] = {
-        KEY(3, 1, KEY_END),
-        KEY(4, 1, KEY_POWER),
-        KEY(6, 4, KEY_VOLUMEDOWN),
-        KEY(4, 2, KEY_EMAIL),
-        KEY(3, 3, KEY_RIGHT),
-        KEY(2, 5, KEY_BACKSPACE),
-        KEY(6, 7, KEY_MENU),
-        KEY(5, 0, KEY_ENTER),
-        KEY(4, 3, KEY_0),
-        KEY(3, 4, KEY_DOT),
-        KEY(5, 2, KEY_UP),
-        KEY(3, 5, KEY_DOWN),
-        KEY(4, 5, KEY_SEND),
-        KEY(0, 5, KEY_BACK),
-        KEY(6, 2, KEY_VOLUMEUP),
-        KEY(1, 3, KEY_SPACE),
-        KEY(7, 6, KEY_LEFT),
-        KEY(5, 5, KEY_SEARCH),
-};
-static struct matrix_keymap_data uib_keymap_data = {
-        .keymap         = uib_keymap,
-        .keymap_size    = ARRAY_SIZE(uib_keymap),
-};
-static struct tc3589x_keypad_platform_data tc35893_data = {
-        .krow = TC_KPD_ROWS,
-        .kcol = TC_KPD_COLUMNS,
-        .debounce_period = TC_KPD_DEBOUNCE_PERIOD,
-        .settle_time = TC_KPD_SETTLE_TIME,
-        .irqtype = IRQF_TRIGGER_FALLING,
-        .enable_wakeup = true,
-        .keymap_data    = &uib_keymap_data,
-        .no_autorepeat  = true,
-};
-static struct tc3589x_platform_data tc3589x_keypad_data = {
-        .block = TC3589x_BLOCK_KEYPAD,
-        .keypad = &tc35893_data,
-        .irq_base = MOP500_EGPIO_IRQ_BASE,
-};
-static struct i2c_board_info mop500_i2c0_devices_uib[] = {
-        {
-                I2C_BOARD_INFO("tc3589x", 0x44),
-                .platform_data = &tc3589x_keypad_data,
-                .irq = NOMADIK_GPIO_TO_IRQ(218),
-                .flags = I2C_CLIENT_WAKE,
-        },
-};
-void mop500_keypad_init(void)
-{
-        db8500_add_ske_keypad(&ske_keypad_board);
-        i2c_register_board_info(0, mop500_i2c0_devices_stuib,
-                        ARRAY_SIZE(mop500_i2c0_devices_stuib));
-        i2c_register_board_info(0, mop500_i2c0_devices_uib,
-                        ARRAY_SIZE(mop500_i2c0_devices_uib));
-}
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
new file mode 100644
index 000000000000..fd4cf1ca5efd
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <plat/pincfg.h>
+#include <mach/hardware.h>
+#include "pins-db8500.h"
+static pin_cfg_t mop500_pins_common[] = {
+        /* I2C */
+        GPIO147_I2C0_SCL,
+        GPIO148_I2C0_SDA,
+        GPIO16_I2C1_SCL,
+        GPIO17_I2C1_SDA,
+        GPIO10_I2C2_SDA,
+        GPIO11_I2C2_SCL,
+        GPIO229_I2C3_SDA,
+        GPIO230_I2C3_SCL,
+        /* MSP0 */
+        GPIO12_MSP0_TXD,
+        GPIO13_MSP0_TFS,
+        GPIO14_MSP0_TCK,
+        GPIO15_MSP0_RXD,
+        /* MSP2: HDMI */
+        GPIO193_MSP2_TXD,
+        GPIO194_MSP2_TCK,
+        GPIO195_MSP2_TFS,
+        GPIO196_MSP2_RXD | PIN_OUTPUT_LOW,
+        /* Touch screen INTERFACE */
+        GPIO84_GPIO     | PIN_INPUT_PULLUP, /* TOUCH_INT1 */
+        /* STMPE1601/tc35893 keypad  IRQ */
+        GPIO218_GPIO    | PIN_INPUT_PULLUP,
+        /* MMC0 (MicroSD card) */
+        GPIO18_MC0_CMDDIR       | PIN_OUTPUT_HIGH,
+        GPIO19_MC0_DAT0DIR      | PIN_OUTPUT_HIGH,
+        GPIO20_MC0_DAT2DIR      | PIN_OUTPUT_HIGH,
+        GPIO22_MC0_FBCLK        | PIN_INPUT_NOPULL,
+        GPIO23_MC0_CLK          | PIN_OUTPUT_LOW,
+        GPIO24_MC0_CMD          | PIN_INPUT_PULLUP,
+        GPIO25_MC0_DAT0         | PIN_INPUT_PULLUP,
+        GPIO26_MC0_DAT1         | PIN_INPUT_PULLUP,
+        GPIO27_MC0_DAT2         | PIN_INPUT_PULLUP,
+        GPIO28_MC0_DAT3         | PIN_INPUT_PULLUP,
+        /* SDI1 (SDIO) */
+        GPIO208_MC1_CLK         | PIN_OUTPUT_LOW,
+        GPIO209_MC1_FBCLK       | PIN_INPUT_NOPULL,
+        GPIO210_MC1_CMD         | PIN_INPUT_PULLUP,
+        GPIO211_MC1_DAT0        | PIN_INPUT_PULLUP,
+        GPIO212_MC1_DAT1        | PIN_INPUT_PULLUP,
+        GPIO213_MC1_DAT2        | PIN_INPUT_PULLUP,
+        GPIO214_MC1_DAT3        | PIN_INPUT_PULLUP,
+        /* MMC2 (On-board DATA INTERFACE eMMC) */
+        GPIO128_MC2_CLK         | PIN_OUTPUT_LOW,
+        GPIO129_MC2_CMD         | PIN_INPUT_PULLUP,
+        GPIO130_MC2_FBCLK       | PIN_INPUT_NOPULL,
+        GPIO131_MC2_DAT0        | PIN_INPUT_PULLUP,
+        GPIO132_MC2_DAT1        | PIN_INPUT_PULLUP,
+        GPIO133_MC2_DAT2        | PIN_INPUT_PULLUP,
+        GPIO134_MC2_DAT3        | PIN_INPUT_PULLUP,
+        GPIO135_MC2_DAT4        | PIN_INPUT_PULLUP,
+        GPIO136_MC2_DAT5        | PIN_INPUT_PULLUP,
+        GPIO137_MC2_DAT6        | PIN_INPUT_PULLUP,
+        GPIO138_MC2_DAT7        | PIN_INPUT_PULLUP,
+        /* MMC4 (On-board STORAGE INTERFACE eMMC) */
+        GPIO197_MC4_DAT3        | PIN_INPUT_PULLUP,
+        GPIO198_MC4_DAT2        | PIN_INPUT_PULLUP,
+        GPIO199_MC4_DAT1        | PIN_INPUT_PULLUP,
+        GPIO200_MC4_DAT0        | PIN_INPUT_PULLUP,
+        GPIO201_MC4_CMD         | PIN_INPUT_PULLUP,
+        GPIO202_MC4_FBCLK       | PIN_INPUT_NOPULL,
+        GPIO203_MC4_CLK         | PIN_OUTPUT_LOW,
+        GPIO204_MC4_DAT7        | PIN_INPUT_PULLUP,
+        GPIO205_MC4_DAT6        | PIN_INPUT_PULLUP,
+        GPIO206_MC4_DAT5        | PIN_INPUT_PULLUP,
+        GPIO207_MC4_DAT4        | PIN_INPUT_PULLUP,
+        /* SKE keypad */
+        GPIO153_KP_I7,
+        GPIO154_KP_I6,
+        GPIO155_KP_I5,
+        GPIO156_KP_I4,
+        GPIO157_KP_O7,
+        GPIO158_KP_O6,
+        GPIO159_KP_O5,
+        GPIO160_KP_O4,
+        GPIO161_KP_I3,
+        GPIO162_KP_I2,
+        GPIO163_KP_I1,
+        GPIO164_KP_I0,
+        GPIO165_KP_O3,
+        GPIO166_KP_O2,
+        GPIO167_KP_O1,
+        GPIO168_KP_O0,
+        /* UART */
+        GPIO0_U0_CTSn   | PIN_INPUT_PULLUP,
+        GPIO1_U0_RTSn   | PIN_OUTPUT_HIGH,
+        GPIO2_U0_RXD    | PIN_INPUT_PULLUP,
+        GPIO3_U0_TXD    | PIN_OUTPUT_HIGH,
+        GPIO29_U2_RXD   | PIN_INPUT_PULLUP,
+        GPIO30_U2_TXD   | PIN_OUTPUT_HIGH,
+        GPIO31_U2_CTSn  | PIN_INPUT_PULLUP,
+        GPIO32_U2_RTSn  | PIN_OUTPUT_HIGH,
+        /* Display & HDMI HW sync */
+        GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP,
+        GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP,
+};
+static pin_cfg_t mop500_pins_default[] = {
+        /* SSP0 */
+        GPIO143_SSP0_CLK,
+        GPIO144_SSP0_FRM,
+        GPIO145_SSP0_RXD | PIN_PULL_DOWN,
+        GPIO146_SSP0_TXD,
+        GPIO217_GPIO    | PIN_INPUT_PULLUP, /* TC35892 IRQ */
+        /* SDI0 (MicroSD card) */
+        GPIO21_MC0_DAT31DIR     | PIN_OUTPUT_HIGH,
+        /* UART */
+        GPIO4_U1_RXD    | PIN_INPUT_PULLUP,
+        GPIO5_U1_TXD    | PIN_OUTPUT_HIGH,
+        GPIO6_U1_CTSn   | PIN_INPUT_PULLUP,
+        GPIO7_U1_RTSn   | PIN_OUTPUT_HIGH,
+};
+static pin_cfg_t mop500_pins_hrefv60[] = {
+        /* WLAN */
+        GPIO4_GPIO              | PIN_INPUT_PULLUP,/* WLAN_IRQ */
+        GPIO85_GPIO             | PIN_OUTPUT_LOW,/* WLAN_ENA */
+        /* XENON Flashgun INTERFACE */
+        GPIO6_IP_GPIO0  | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */
+        GPIO7_IP_GPIO1  | PIN_INPUT_PULLUP,/* XENON_READY */
+        GPIO170_GPIO    | PIN_OUTPUT_LOW, /* XENON_CHARGE */
+        /* Assistant LED INTERFACE */
+        GPIO21_GPIO | PIN_OUTPUT_LOW,  /* XENON_EN1 */
+        GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW,  /* XENON_EN2 */
+        /* Magnetometer */
+        GPIO31_GPIO | PIN_INPUT_PULLUP,  /* magnetometer_INT */
+        GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */
+        /* Display Interface */
+        GPIO65_GPIO             | PIN_OUTPUT_LOW, /* DISP1 RST */
+        GPIO66_GPIO             | PIN_OUTPUT_LOW, /* DISP2 RST */
+        /* Touch screen INTERFACE */
+        GPIO143_GPIO    | PIN_OUTPUT_LOW,/*TOUCH_RST1 */
+        /* Touch screen INTERFACE 2 */
+        GPIO67_GPIO     | PIN_INPUT_PULLUP, /* TOUCH_INT2 */
+        GPIO146_GPIO    | PIN_OUTPUT_LOW,/*TOUCH_RST2 */
+        /* ETM_PTM_TRACE INTERFACE */
+        GPIO70_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */
+        GPIO71_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */
+        GPIO72_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */
+        GPIO73_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */
+        GPIO74_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */
+        /* NAHJ INTERFACE */
+        GPIO76_GPIO     | PIN_OUTPUT_LOW,/* NAHJ_CTRL */
+        GPIO216_GPIO    | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */
+        /* NFC INTERFACE */
+        GPIO77_GPIO     | PIN_OUTPUT_LOW, /* NFC_ENA */
+        GPIO144_GPIO    | PIN_INPUT_PULLDOWN, /* NFC_IRQ */
+        GPIO142_GPIO    | PIN_OUTPUT_LOW, /* NFC_RESET */
+        /* Keyboard MATRIX INTERFACE */
+        GPIO90_MC5_CMD  | PIN_OUTPUT_LOW, /* KP_O_1 */
+        GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */
+        GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */
+        GPIO96_KP_O6    | PIN_OUTPUT_LOW, /* KP_O_6 */
+        GPIO94_KP_O7    | PIN_OUTPUT_LOW, /* KP_O_7 */
+        GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */
+        GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */
+        GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */
+        GPIO91_GPIO     | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */
+        GPIO92_GPIO     | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */
+        GPIO97_GPIO     | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */
+        /* DiPro Sensor Interface */
+        GPIO139_GPIO    | PIN_INPUT_PULLUP, /* DIPRO_INT */
+        /* HAL SWITCH INTERFACE */
+        GPIO145_GPIO    | PIN_INPUT_PULLDOWN,/* HAL_SW */
+        /* Audio Amplifier Interface */
+        GPIO149_GPIO    | PIN_OUTPUT_LOW, /* VAUDIO_HF_EN */
+        /* GBF INTERFACE */
+        GPIO171_GPIO    | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */
+        /* MSP : HDTV INTERFACE */
+        GPIO192_GPIO    | PIN_INPUT_PULLDOWN,
+        /* ACCELEROMETER_INTERFACE */
+        GPIO82_GPIO             | PIN_INPUT_PULLUP, /* ACC_INT1 */
+        GPIO83_GPIO             | PIN_INPUT_PULLUP, /* ACC_INT2 */
+        /* Proximity Sensor */
+        GPIO217_GPIO            | PIN_INPUT_PULLUP,
+};
+void __init mop500_pins_init(void)
+{
+        nmk_config_pins(mop500_pins_common,
+                                ARRAY_SIZE(mop500_pins_common));
+        if (machine_is_hrefv60())
+                nmk_config_pins(mop500_pins_hrefv60,
+                                ARRAY_SIZE(mop500_pins_hrefv60));
+        else
+                nmk_config_pins(mop500_pins_default,
+                                ARRAY_SIZE(mop500_pins_default));
+}
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 533967c2d095..875c91b2f8a4 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -11,6 +11,56 @@
 #include <linux/kernel.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/ab8500.h>
+#include "board-mop500-regulators.h"
+static struct regulator_consumer_supply ab8500_vaux1_consumers[] = {
+        /* External displays, connector on board 2v5 power supply */
+        REGULATOR_SUPPLY("vaux12v5", "mcde.0"),
+        /* SFH7741 proximity sensor */
+        REGULATOR_SUPPLY("vcc", "gpio-keys.0"),
+        /* BH1780GLS ambient light sensor */
+        REGULATOR_SUPPLY("vcc", "2-0029"),
+        /* lsm303dlh accelerometer */
+        REGULATOR_SUPPLY("vdd", "3-0018"),
+        /* lsm303dlh magnetometer */
+        REGULATOR_SUPPLY("vdd", "3-001e"),
+        /* Rohm BU21013 Touchscreen devices */
+        REGULATOR_SUPPLY("avdd", "3-005c"),
+        REGULATOR_SUPPLY("avdd", "3-005d"),
+        /* Synaptics RMI4 Touchscreen device */
+        REGULATOR_SUPPLY("vdd", "3-004b"),
+};
+static struct regulator_consumer_supply ab8500_vaux2_consumers[] = {
+        /* On-board eMMC power */
+        REGULATOR_SUPPLY("vmmc", "sdi4"),
+        /* AB8500 audio codec */
+        REGULATOR_SUPPLY("vcc-N2158", "ab8500-codec.0"),
+};
+static struct regulator_consumer_supply ab8500_vaux3_consumers[] = {
+        /* External MMC slot power */
+        REGULATOR_SUPPLY("vmmc", "sdi0"),
+};
+static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
+        /* TV-out DENC supply */
+        REGULATOR_SUPPLY("vtvout", "ab8500-denc.0"),
+        /* Internal general-purpose ADC */
+        REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"),
+};
+static struct regulator_consumer_supply ab8500_vintcore_consumers[] = {
+        /* SoC core supply, no device */
+        REGULATOR_SUPPLY("v-intcore", NULL),
+        /* USB Transciever */
+        REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"),
+};
+static struct regulator_consumer_supply ab8500_vana_consumers[] = {
+        /* External displays, connector on board, 1v8 power supply */
+        REGULATOR_SUPPLY("vsmps2", "mcde.0"),
+};
 /* AB8500 regulators */
 struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
@@ -23,6 +73,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                          REGULATOR_CHANGE_STATUS,
                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
+                .consumer_supplies = ab8500_vaux1_consumers,
        },
        /* supplies to the on-board eMMC */
        [AB8500_LDO_AUX2] = {
@@ -33,6 +85,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                          REGULATOR_CHANGE_STATUS,
                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers),
+                .consumer_supplies = ab8500_vaux2_consumers,
        },
        /* supply for VAUX3, supplies to SDcard slots */
        [AB8500_LDO_AUX3] = {
@@ -43,6 +97,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                          REGULATOR_CHANGE_STATUS,
                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers),
+                .consumer_supplies = ab8500_vaux3_consumers,
        },
        /* supply for tvout, gpadc, TVOUT LDO */
        [AB8500_LDO_TVOUT] = {
@@ -50,6 +106,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                        .name = "V-TVOUT",
                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vtvout_consumers),
+                .consumer_supplies = ab8500_vtvout_consumers,
        },
        /* supply for ab8500-vaudio, VAUDIO LDO */
        [AB8500_LDO_AUDIO] = {
@@ -85,6 +143,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                        .name = "V-INTCORE",
                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers),
+                .consumer_supplies = ab8500_vintcore_consumers,
        },
        /* supply for U8500 CSI/DSI, VANA LDO */
        [AB8500_LDO_ANA] = {
@@ -92,5 +152,7 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                        .name = "V-CSI/DSI",
                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers),
+                .consumer_supplies = ab8500_vana_consumers,
        },
 };
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 4b996676594e..bf0b02414e5b 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -12,56 +12,14 @@
 #include <linux/mmc/host.h>
 #include <linux/platform_device.h>
-#include <plat/pincfg.h>
+#include <asm/mach-types.h>
+#include <plat/ste_dma40.h>
 #include <mach/devices.h>
 #include <mach/hardware.h>
 #include "devices-db8500.h"
-#include "pins-db8500.h"
 #include "board-mop500.h"
+#include "ste-dma40-db8500.h"
-static pin_cfg_t mop500_sdi_pins[] = {
-        /* SDI0 (MicroSD slot) */
-        GPIO18_MC0_CMDDIR,
-        GPIO19_MC0_DAT0DIR,
-        GPIO20_MC0_DAT2DIR,
-        GPIO21_MC0_DAT31DIR,
-        GPIO22_MC0_FBCLK,
-        GPIO23_MC0_CLK,
-        GPIO24_MC0_CMD,
-        GPIO25_MC0_DAT0,
-        GPIO26_MC0_DAT1,
-        GPIO27_MC0_DAT2,
-        GPIO28_MC0_DAT3,
-        /* SDI4 (on-board eMMC) */
-        GPIO197_MC4_DAT3,
-        GPIO198_MC4_DAT2,
-        GPIO199_MC4_DAT1,
-        GPIO200_MC4_DAT0,
-        GPIO201_MC4_CMD,
-        GPIO202_MC4_FBCLK,
-        GPIO203_MC4_CLK,
-        GPIO204_MC4_DAT7,
-        GPIO205_MC4_DAT6,
-        GPIO206_MC4_DAT5,
-        GPIO207_MC4_DAT4,
-};
-static pin_cfg_t mop500_sdi2_pins[] = {
-        /* SDI2 (POP eMMC) */
-        GPIO128_MC2_CLK,
-        GPIO129_MC2_CMD,
-        GPIO130_MC2_FBCLK,
-        GPIO131_MC2_DAT0,
-        GPIO132_MC2_DAT1,
-        GPIO133_MC2_DAT2,
-        GPIO134_MC2_DAT3,
-        GPIO135_MC2_DAT4,
-        GPIO136_MC2_DAT5,
-        GPIO137_MC2_DAT6,
-        GPIO138_MC2_DAT7,
-};
 /*
 * SDI 0 (MicroSD slot)
@@ -86,48 +44,134 @@ static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
               MCI_DATA2DIREN | MCI_DATA31DIREN;
 }
+#ifdef CONFIG_STE_DMA40
+struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+#endif
 static struct mmci_platform_data mop500_sdi0_data = {
        .vdd_handler    = mop500_sdi0_vdd_handler,
        .ocr_mask       = MMC_VDD_29_30,
        .f_max          = 100000000,
        .capabilities   = MMC_CAP_4_BIT_DATA,
-        .gpio_cd        = GPIO_SDMMC_CD,
        .gpio_wp        = -1,
+#ifdef CONFIG_STE_DMA40
+        .dma_filter     = stedma40_filter,
+        .dma_rx_param   = &mop500_sdi0_dma_cfg_rx,
+        .dma_tx_param   = &mop500_sdi0_dma_cfg_tx,
+#endif
 };
-void mop500_sdi_tc35892_init(void)
+/* GPIO pins used by the sdi0 level shifter */
+static int sdi0_en = -1;
+static int sdi0_vsel = -1;
+static void sdi0_configure(void)
 {
        int ret;
-        ret = gpio_request(GPIO_SDMMC_EN, "SDMMC_EN");
+        ret = gpio_request(sdi0_en, "level shifter enable");
        if (!ret)
-                ret = gpio_request(GPIO_SDMMC_1V8_3V_SEL,
+                ret = gpio_request(sdi0_vsel,
-                                   "GPIO_SDMMC_1V8_3V_SEL");
+                                   "level shifter 1v8-3v select");
-        if (ret)
+        if (ret) {
+                pr_warning("unable to config sdi0 gpios for level shifter.\n");
                return;
+        }
-        gpio_direction_output(GPIO_SDMMC_1V8_3V_SEL, 1);
+        /* Select the default 2.9V and enable level shifter */
-        gpio_direction_output(GPIO_SDMMC_EN, 0);
+        gpio_direction_output(sdi0_vsel, 0);
+        gpio_direction_output(sdi0_en, 1);
+        /* Add the device */
        db8500_add_sdi0(&mop500_sdi0_data);
 }
+void mop500_sdi_tc35892_init(void)
+{
+        mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
+        sdi0_en = GPIO_SDMMC_EN;
+        sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
+        sdi0_configure();
+}
 /*
 * SDI 2 (POP eMMC, not on DB8500ed)
 */
+#ifdef CONFIG_STE_DMA40
+struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV28_SD_MM2_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+#endif
 static struct mmci_platform_data mop500_sdi2_data = {
        .ocr_mask       = MMC_VDD_165_195,
        .f_max          = 100000000,
        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
        .gpio_cd        = -1,
        .gpio_wp        = -1,
+#ifdef CONFIG_STE_DMA40
+        .dma_filter     = stedma40_filter,
+        .dma_rx_param   = &mop500_sdi2_dma_cfg_rx,
+        .dma_tx_param   = &mop500_sdi2_dma_cfg_tx,
+#endif
 };
 /*
 * SDI 4 (on-board eMMC)
 */
+#ifdef CONFIG_STE_DMA40
+struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV42_SD_MM4_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+#endif
 static struct mmci_platform_data mop500_sdi4_data = {
        .ocr_mask       = MMC_VDD_29_30,
        .f_max          = 100000000,
@@ -135,26 +179,32 @@ static struct mmci_platform_data mop500_sdi4_data = {
                          MMC_CAP_MMC_HIGHSPEED,
        .gpio_cd        = -1,
        .gpio_wp        = -1,
+#ifdef CONFIG_STE_DMA40
+        .dma_filter     = stedma40_filter,
+        .dma_rx_param   = &mop500_sdi4_dma_cfg_rx,
+        .dma_tx_param   = &mop500_sdi4_dma_cfg_tx,
+#endif
 };
 void __init mop500_sdi_init(void)
 {
-        nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins));
+        /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
+        if (!cpu_is_u8500v10())
+                mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
+        db8500_add_sdi2(&mop500_sdi2_data);
+        /* On-board eMMC */
+        db8500_add_sdi4(&mop500_sdi4_data);
+        if (machine_is_hrefv60()) {
+                mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
+                sdi0_en = HREFV60_SDMMC_EN_GPIO;
+                sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
+                sdi0_configure();
+        }
        /*
-         * sdi0 will finally be added when the TC35892 initializes and calls
+         * On boards with the TC35892 GPIO expander, sdi0 will finally
+         * be added when the TC35892 initializes and calls
         * mop500_sdi_tc35892_init() above.
         */
-        /* PoP:ed eMMC */
-        if (!cpu_is_u8500ed()) {
-                nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins));
-                /* POP eMMC on v1.0 has problems with high speed */
-                if (!cpu_is_u8500v10())
-                        mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
-                db8500_add_sdi2(&mop500_sdi2_data);
-        }
-        /* On-board eMMC */
-        db8500_add_sdi4(&mop500_sdi4_data);
 }
diff --git a/arch/arm/mach-ux500/board-mop500-stuib.c b/arch/arm/mach-ux500/board-mop500-stuib.c
new file mode 100644
index 000000000000..8c979770d872
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-stuib.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mfd/stmpe.h>
+#include <linux/input/bu21013.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/input/matrix_keypad.h>
+#include <asm/mach-types.h>
+#include "board-mop500.h"
+/* STMPE/SKE keypad use this key layout */
+static const unsigned int mop500_keymap[] = {
+        KEY(2, 5, KEY_END),
+        KEY(4, 1, KEY_POWER),
+        KEY(3, 5, KEY_VOLUMEDOWN),
+        KEY(1, 3, KEY_3),
+        KEY(5, 2, KEY_RIGHT),
+        KEY(5, 0, KEY_9),
+        KEY(0, 5, KEY_MENU),
+        KEY(7, 6, KEY_ENTER),
+        KEY(4, 5, KEY_0),
+        KEY(6, 7, KEY_2),
+        KEY(3, 4, KEY_UP),
+        KEY(3, 3, KEY_DOWN),
+        KEY(6, 4, KEY_SEND),
+        KEY(6, 2, KEY_BACK),
+        KEY(4, 2, KEY_VOLUMEUP),
+        KEY(5, 5, KEY_1),
+        KEY(4, 3, KEY_LEFT),
+        KEY(3, 2, KEY_7),
+};
+static const struct matrix_keymap_data mop500_keymap_data = {
+        .keymap         = mop500_keymap,
+        .keymap_size    = ARRAY_SIZE(mop500_keymap),
+};
+/*
+ * STMPE1601
+ */
+static struct stmpe_keypad_platform_data stmpe1601_keypad_data = {
+        .debounce_ms    = 64,
+        .scan_count     = 8,
+        .no_autorepeat  = true,
+        .keymap_data    = &mop500_keymap_data,
+};
+static struct stmpe_platform_data stmpe1601_data = {
+        .id             = 1,
+        .blocks         = STMPE_BLOCK_KEYPAD,
+        .irq_trigger    = IRQF_TRIGGER_FALLING,
+        .irq_base       = MOP500_STMPE1601_IRQ(0),
+        .keypad         = &stmpe1601_keypad_data,
+        .autosleep      = true,
+        .autosleep_timeout = 1024,
+};
+static struct i2c_board_info __initdata mop500_i2c0_devices_stuib[] = {
+        {
+                I2C_BOARD_INFO("stmpe1601", 0x40),
+                .irq = NOMADIK_GPIO_TO_IRQ(218),
+                .platform_data = &stmpe1601_data,
+                .flags = I2C_CLIENT_WAKE,
+        },
+};
+/*
+ * BU21013 ROHM touchscreen interface on the STUIBs
+ */
+/* tracks number of bu21013 devices being enabled */
+static int bu21013_devices;
+#define TOUCH_GPIO_PIN  84
+#define TOUCH_XMAX      384
+#define TOUCH_YMAX      704
+#define PRCMU_CLOCK_OCR         0x1CC
+#define TSC_EXT_CLOCK_9_6MHZ    0x840000
+/**
+ * bu21013_gpio_board_init : configures the touch panel.
+ * @reset_pin: reset pin number
+ * This function can be used to configures
+ * the voltage and reset the touch panel controller.
+ */
+static int bu21013_gpio_board_init(int reset_pin)
+{
+        int retval = 0;
+        bu21013_devices++;
+        if (bu21013_devices == 1) {
+                retval = gpio_request(reset_pin, "touchp_reset");
+                if (retval) {
+                        printk(KERN_ERR "Unable to request gpio reset_pin");
+                        return retval;
+                }
+                retval = gpio_direction_output(reset_pin, 1);
+                if (retval < 0) {
+                        printk(KERN_ERR "%s: gpio direction failed\n",
+                                        __func__);
+                        return retval;
+                }
+        }
+        return retval;
+}
+/**
+ * bu21013_gpio_board_exit : deconfigures the touch panel controller
+ * @reset_pin: reset pin number
+ * This function can be used to deconfigures the chip selection
+ * for touch panel controller.
+ */
+static int bu21013_gpio_board_exit(int reset_pin)
+{
+        int retval = 0;
+        if (bu21013_devices == 1) {
+                retval = gpio_direction_output(reset_pin, 0);
+                if (retval < 0) {
+                        printk(KERN_ERR "%s: gpio direction failed\n",
+                                        __func__);
+                        return retval;
+                }
+                gpio_set_value(reset_pin, 0);
+        }
+        bu21013_devices--;
+        return retval;
+}
+/**
+ * bu21013_read_pin_val : get the interrupt pin value
+ * This function can be used to get the interrupt pin value for touch panel
+ * controller.
+ */
+static int bu21013_read_pin_val(void)
+{
+        return gpio_get_value(TOUCH_GPIO_PIN);
+}
+static struct bu21013_platform_device tsc_plat_device = {
+        .cs_en = bu21013_gpio_board_init,
+        .cs_dis = bu21013_gpio_board_exit,
+        .irq_read_val = bu21013_read_pin_val,
+        .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN),
+        .touch_x_max = TOUCH_XMAX,
+        .touch_y_max = TOUCH_YMAX,
+        .ext_clk = false,
+        .x_flip = false,
+        .y_flip = true,
+};
+static struct bu21013_platform_device tsc_plat2_device = {
+        .cs_en = bu21013_gpio_board_init,
+        .cs_dis = bu21013_gpio_board_exit,
+        .irq_read_val = bu21013_read_pin_val,
+        .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN),
+        .touch_x_max = TOUCH_XMAX,
+        .touch_y_max = TOUCH_YMAX,
+        .ext_clk = false,
+        .x_flip = false,
+        .y_flip = true,
+};
+static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = {
+        {
+                I2C_BOARD_INFO("bu21013_tp", 0x5C),
+                .platform_data = &tsc_plat_device,
+        },
+        {
+                I2C_BOARD_INFO("bu21013_tp", 0x5D),
+                .platform_data = &tsc_plat2_device,
+        },
+};
+void __init mop500_stuib_init(void)
+{
+        if (machine_is_hrefv60()) {
+                tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
+                tsc_plat2_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
+        } else {
+                tsc_plat_device.cs_pin = GPIO_BU21013_CS;
+                tsc_plat2_device.cs_pin = GPIO_BU21013_CS;
+        }
+        mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib,
+                        ARRAY_SIZE(mop500_i2c0_devices_stuib));
+        mop500_uib_i2c_add(3, u8500_i2c3_devices_stuib,
+                        ARRAY_SIZE(u8500_i2c3_devices_stuib));
+}
diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c
new file mode 100644
index 000000000000..d8a8734a0eba
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Board data for the U8500 UIB, also known as the New UIB
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/tc3589x.h>
+#include <linux/input/matrix_keypad.h>
+#include <../drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include "board-mop500.h"
+/*
+ * Synaptics RMI4 touchscreen interface on the U8500 UIB
+ */
+/*
+ * Descriptor structure.
+ * Describes the number of i2c devices on the bus that speak RMI.
+ */
+static struct synaptics_rmi4_platform_data rmi4_i2c_dev_platformdata = {
+        .irq_number     = NOMADIK_GPIO_TO_IRQ(84),
+        .irq_type       = (IRQF_TRIGGER_FALLING | IRQF_SHARED),
+        .x_flip         = false,
+        .y_flip         = true,
+        .regulator_en   = false,
+};
+static struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = {
+        {
+                I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B),
+                .platform_data = &rmi4_i2c_dev_platformdata,
+        },
+};
+/*
+ * TC35893
+ */
+static const unsigned int u8500_keymap[] = {
+        KEY(3, 1, KEY_END),
+        KEY(4, 1, KEY_POWER),
+        KEY(6, 4, KEY_VOLUMEDOWN),
+        KEY(4, 2, KEY_EMAIL),
+        KEY(3, 3, KEY_RIGHT),
+        KEY(2, 5, KEY_BACKSPACE),
+        KEY(6, 7, KEY_MENU),
+        KEY(5, 0, KEY_ENTER),
+        KEY(4, 3, KEY_0),
+        KEY(3, 4, KEY_DOT),
+        KEY(5, 2, KEY_UP),
+        KEY(3, 5, KEY_DOWN),
+        KEY(4, 5, KEY_SEND),
+        KEY(0, 5, KEY_BACK),
+        KEY(6, 2, KEY_VOLUMEUP),
+        KEY(1, 3, KEY_SPACE),
+        KEY(7, 6, KEY_LEFT),
+        KEY(5, 5, KEY_SEARCH),
+};
+static struct matrix_keymap_data u8500_keymap_data = {
+        .keymap         = u8500_keymap,
+        .keymap_size    = ARRAY_SIZE(u8500_keymap),
+};
+static struct tc3589x_keypad_platform_data tc35893_data = {
+        .krow = TC_KPD_ROWS,
+        .kcol = TC_KPD_COLUMNS,
+        .debounce_period = TC_KPD_DEBOUNCE_PERIOD,
+        .settle_time = TC_KPD_SETTLE_TIME,
+        .irqtype = IRQF_TRIGGER_FALLING,
+        .enable_wakeup = true,
+        .keymap_data    = &u8500_keymap_data,
+        .no_autorepeat  = true,
+};
+static struct tc3589x_platform_data tc3589x_keypad_data = {
+        .block = TC3589x_BLOCK_KEYPAD,
+        .keypad = &tc35893_data,
+        .irq_base = MOP500_EGPIO_IRQ_BASE,
+};
+static struct i2c_board_info __initdata mop500_i2c0_devices_u8500[] = {
+        {
+                I2C_BOARD_INFO("tc3589x", 0x44),
+                .platform_data = &tc3589x_keypad_data,
+                .irq = NOMADIK_GPIO_TO_IRQ(218),
+                .flags = I2C_CLIENT_WAKE,
+        },
+};
+void __init mop500_u8500uib_init(void)
+{
+        mop500_uib_i2c_add(3, mop500_i2c3_devices_u8500,
+                        ARRAY_SIZE(mop500_i2c3_devices_u8500));
+        mop500_uib_i2c_add(0, mop500_i2c0_devices_u8500,
+                        ARRAY_SIZE(mop500_i2c0_devices_u8500));
+}
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c
new file mode 100644
index 000000000000..69cce41f602a
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-uib.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#define pr_fmt(fmt)     "mop500-uib: " fmt
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <mach/hardware.h>
+#include "board-mop500.h"
+enum mop500_uib {
+        STUIB,
+        U8500UIB,
+};
+struct uib {
+        const char *name;
+        const char *option;
+        void (*init)(void);
+};
+static struct __initdata uib mop500_uibs[] = {
+        [STUIB] = {
+                .name   = "ST-UIB",
+                .option = "stuib",
+                .init   = mop500_stuib_init,
+        },
+        [U8500UIB] = {
+                .name   = "U8500-UIB",
+                .option = "u8500uib",
+                .init   = mop500_u8500uib_init,
+        },
+};
+static struct uib *mop500_uib;
+static int __init mop500_uib_setup(char *str)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(mop500_uibs); i++) {
+                struct uib *uib = &mop500_uibs[i];
+                if (!strcmp(str, uib->option)) {
+                        mop500_uib = uib;
+                        break;
+                }
+        }
+        if (i == ARRAY_SIZE(mop500_uibs))
+                pr_err("invalid uib= option (%s)\n", str);
+        return 1;
+}
+__setup("uib=", mop500_uib_setup);
+/*
+ * The UIBs are detected after the I2C host controllers are registered, so
+ * i2c_register_board_info() can't be used.
+ */
+void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
+                unsigned n)
+{
+        struct i2c_adapter *adap;
+        struct i2c_client *client;
+        int i;
+        adap = i2c_get_adapter(busnum);
+        if (!adap) {
+                pr_err("failed to get adapter i2c%d\n", busnum);
+                return;
+        }
+        for (i = 0; i < n; i++) {
+                client = i2c_new_device(adap, &info[i]);
+                if (!client)
+                        pr_err("failed to register %s to i2c%d\n",
+                                        info[i].type, busnum);
+        }
+        i2c_put_adapter(adap);
+}
+static void __init __mop500_uib_init(struct uib *uib, const char *why)
+{
+        pr_info("%s (%s)\n", uib->name, why);
+        uib->init();
+}
+/*
+ * Detect the UIB attached based on the presence or absence of i2c devices.
+ */
+static int __init mop500_uib_init(void)
+{
+        struct uib *uib = mop500_uib;
+        struct i2c_adapter *i2c0;
+        int ret;
+        if (!cpu_is_u8500())
+                return -ENODEV;
+        if (uib) {
+                __mop500_uib_init(uib, "from uib= boot argument");
+                return 0;
+        }
+        i2c0 = i2c_get_adapter(0);
+        if (!i2c0) {
+                __mop500_uib_init(&mop500_uibs[STUIB],
+                                "fallback, could not get i2c0");
+                return -ENODEV;
+        }
+        /* U8500-UIB has the TC35893 at 0x44 on I2C0, the ST-UIB doesn't. */
+        ret = i2c_smbus_xfer(i2c0, 0x44, 0, I2C_SMBUS_WRITE, 0,
+                        I2C_SMBUS_QUICK, NULL);
+        i2c_put_adapter(i2c0);
+        if (ret == 0)
+                uib = &mop500_uibs[U8500UIB];
+        else
+                uib = &mop500_uibs[STUIB];
+        __mop500_uib_init(uib, "detected");
+        return 0;
+}
+module_init(mop500_uib_init);
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index a393f57ed2a8..8790d984cac8 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -17,68 +17,30 @@
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
+#include <linux/amba/serial.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/ab8500.h>
 #include <linux/mfd/tc3589x.h>
+#include <linux/leds-lp5521.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <plat/pincfg.h>
 #include <plat/i2c.h>
+#include <plat/ste_dma40.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
 #include <mach/irqs.h>
+#include "ste-dma40-db8500.h"
 #include "devices-db8500.h"
-#include "pins-db8500.h"
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
-static pin_cfg_t mop500_pins[] = {
-        /* SSP0 */
-        GPIO143_SSP0_CLK,
-        GPIO144_SSP0_FRM,
-        GPIO145_SSP0_RXD,
-        GPIO146_SSP0_TXD,
-        /* I2C */
-        GPIO147_I2C0_SCL,
-        GPIO148_I2C0_SDA,
-        GPIO16_I2C1_SCL,
-        GPIO17_I2C1_SDA,
-        GPIO10_I2C2_SDA,
-        GPIO11_I2C2_SCL,
-        GPIO229_I2C3_SDA,
-        GPIO230_I2C3_SCL,
-        /* SKE keypad */
-        GPIO153_KP_I7,
-        GPIO154_KP_I6,
-        GPIO155_KP_I5,
-        GPIO156_KP_I4,
-        GPIO157_KP_O7,
-        GPIO158_KP_O6,
-        GPIO159_KP_O5,
-        GPIO160_KP_O4,
-        GPIO161_KP_I3,
-        GPIO162_KP_I2,
-        GPIO163_KP_I1,
-        GPIO164_KP_I0,
-        GPIO165_KP_O3,
-        GPIO166_KP_O2,
-        GPIO167_KP_O1,
-        GPIO168_KP_O0,
-        /* GPIO_EXP_INT */
-        GPIO217_GPIO,
-        /* STMPE1601 IRQ */
-        GPIO218_GPIO    | PIN_INPUT_PULLUP,
-};
 static struct ab8500_platform_data ab8500_platdata = {
        .irq_base       = MOP500_AB8500_IRQ_BASE,
        .regulator      = ab8500_regulators,
@@ -103,16 +65,6 @@ struct platform_device ab8500_device = {
        .resource = ab8500_resources,
 };
-static struct pl022_ssp_controller ssp0_platform_data = {
-        .bus_id = 0,
-        /* pl022 not yet supports dma */
-        .enable_dma = 0,
-        /* on this platform, gpio 31,142,144,214 &
-         * 224 are connected as chip selects
-         */
-        .num_chipselect = 5,
-};
 /*
 * TC35892
 */
@@ -133,14 +85,81 @@ static struct tc3589x_platform_data mop500_tc35892_data = {
        .irq_base       = MOP500_EGPIO_IRQ_BASE,
 };
+static struct lp5521_led_config lp5521_pri_led[] = {
+       [0] = {
+               .chan_nr = 0,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+       [1] = {
+               .chan_nr = 1,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+       [2] = {
+               .chan_nr = 2,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+};
+static struct lp5521_platform_data __initdata lp5521_pri_data = {
+       .label = "lp5521_pri",
+       .led_config     = &lp5521_pri_led[0],
+       .num_channels   = 3,
+       .clock_mode     = LP5521_CLOCK_EXT,
+};
+static struct lp5521_led_config lp5521_sec_led[] = {
+       [0] = {
+               .chan_nr = 0,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+       [1] = {
+               .chan_nr = 1,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+       [2] = {
+               .chan_nr = 2,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+};
+static struct lp5521_platform_data __initdata lp5521_sec_data = {
+       .label = "lp5521_sec",
+       .led_config     = &lp5521_sec_led[0],
+       .num_channels   = 3,
+       .clock_mode     = LP5521_CLOCK_EXT,
+};
 static struct i2c_board_info mop500_i2c0_devices[] = {
        {
                I2C_BOARD_INFO("tc3589x", 0x42),
-                .irq            = NOMADIK_GPIO_TO_IRQ(217),
+                .irq            = NOMADIK_GPIO_TO_IRQ(217),
                .platform_data  = &mop500_tc35892_data,
        },
 };
+static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
+        {
+                /* lp5521 LED driver, 1st device */
+                I2C_BOARD_INFO("lp5521", 0x33),
+                .platform_data = &lp5521_pri_data,
+        },
+        {
+                /* lp5521 LED driver, 2st device */
+                I2C_BOARD_INFO("lp5521", 0x34),
+                .platform_data = &lp5521_sec_data,
+        },
+        {
+                /* Light sensor Rohm BH1780GLI */
+                I2C_BOARD_INFO("bh1780", 0x29),
+        },
+};
 #define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
 static struct nmk_i2c_controller u8500_i2c##id##_data = { \
        /*                              \
@@ -178,8 +197,93 @@ static void __init mop500_i2c_init(void)
        db8500_add_i2c3(&u8500_i2c3_data);
 }
+static struct gpio_keys_button mop500_gpio_keys[] = {
+        {
+                .desc                   = "SFH7741 Proximity Sensor",
+                .type                   = EV_SW,
+                .code                   = SW_FRONT_PROXIMITY,
+                .active_low             = 0,
+                .can_disable            = 1,
+        }
+};
+static struct regulator *prox_regulator;
+static int mop500_prox_activate(struct device *dev);
+static void mop500_prox_deactivate(struct device *dev);
+static struct gpio_keys_platform_data mop500_gpio_keys_data = {
+        .buttons        = mop500_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(mop500_gpio_keys),
+        .enable         = mop500_prox_activate,
+        .disable        = mop500_prox_deactivate,
+};
+static struct platform_device mop500_gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &mop500_gpio_keys_data,
+        },
+};
+static int mop500_prox_activate(struct device *dev)
+{
+        prox_regulator = regulator_get(&mop500_gpio_keys_device.dev,
+                                                "vcc");
+        if (IS_ERR(prox_regulator)) {
+                dev_err(&mop500_gpio_keys_device.dev,
+                        "no regulator\n");
+                return PTR_ERR(prox_regulator);
+        }
+        regulator_enable(prox_regulator);
+        return 0;
+}
+static void mop500_prox_deactivate(struct device *dev)
+{
+        regulator_disable(prox_regulator);
+        regulator_put(prox_regulator);
+}
 /* add any platform devices here - TODO */
 static struct platform_device *platform_devs[] __initdata = {
+        &mop500_gpio_keys_device,
+};
+#ifdef CONFIG_STE_DMA40
+static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV8_SSP0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+#endif
+static struct pl022_ssp_controller ssp0_platform_data = {
+        .bus_id = 0,
+#ifdef CONFIG_STE_DMA40
+        .enable_dma = 1,
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &ssp0_dma_cfg_rx,
+        .dma_tx_param = &ssp0_dma_cfg_tx,
+#else
+        .enable_dma = 0,
+#endif
+        /* on this platform, gpio 31,142,144,214 &
+         * 224 are connected as chip selects
+         */
+        .num_chipselect = 5,
 };
 static void __init mop500_spi_init(void)
@@ -187,18 +291,108 @@ static void __init mop500_spi_init(void)
        db8500_add_ssp0(&ssp0_platform_data);
 }
+#ifdef CONFIG_STE_DMA40
+static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV13_UART0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV12_UART1_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV11_UART2_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+#endif
+static struct amba_pl011_data uart0_plat = {
+#ifdef CONFIG_STE_DMA40
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &uart0_dma_cfg_rx,
+        .dma_tx_param = &uart0_dma_cfg_tx,
+#endif
+};
+static struct amba_pl011_data uart1_plat = {
+#ifdef CONFIG_STE_DMA40
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &uart1_dma_cfg_rx,
+        .dma_tx_param = &uart1_dma_cfg_tx,
+#endif
+};
+static struct amba_pl011_data uart2_plat = {
+#ifdef CONFIG_STE_DMA40
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &uart2_dma_cfg_rx,
+        .dma_tx_param = &uart2_dma_cfg_tx,
+#endif
+};
 static void __init mop500_uart_init(void)
 {
-        db8500_add_uart0();
+        db8500_add_uart0(&uart0_plat);
-        db8500_add_uart1();
+        db8500_add_uart1(&uart1_plat);
-        db8500_add_uart2();
+        db8500_add_uart2(&uart2_plat);
 }
-static void __init u8500_init_machine(void)
+static void __init mop500_init_machine(void)
 {
+        /*
+         * The HREFv60 board removed a GPIO expander and routed
+         * all these GPIO pins to the internal GPIO controller
+         * instead.
+         */
+        if (machine_is_hrefv60())
+                mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
+        else
+                mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
        u8500_init_devices();
-        nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins));
+        mop500_pins_init();
        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
@@ -207,12 +401,12 @@ static void __init u8500_init_machine(void)
        mop500_spi_init();
        mop500_uart_init();
-        mop500_keypad_init();
        platform_device_register(&ab8500_device);
        i2c_register_board_info(0, mop500_i2c0_devices,
                                ARRAY_SIZE(mop500_i2c0_devices));
+        i2c_register_board_info(2, mop500_i2c2_devices,
+                                ARRAY_SIZE(mop500_i2c2_devices));
 }
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
@@ -222,5 +416,13 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
        .init_irq       = ux500_init_irq,
        /* we re-use nomadik timer here */
        .timer          = &ux500_timer,
-        .init_machine   = u8500_init_machine,
+        .init_machine   = mop500_init_machine,
+MACHINE_END
+MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
+        .boot_params    = 0x100,
+        .map_io         = u8500_map_io,
+        .init_irq       = ux500_init_irq,
+        .timer          = &ux500_timer,
+        .init_machine   = mop500_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 3104ae2a02c2..56722f4be71b 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,15 +7,36 @@
 #ifndef __BOARD_MOP500_H
 #define __BOARD_MOP500_H
-#define MOP500_EGPIO(x)                 (NOMADIK_NR_GPIO + (x))
+/* HREFv60-specific GPIO assignments, this board has no GPIO expander */
+#define HREFV60_TOUCH_RST_GPIO          143
+#define HREFV60_PROX_SENSE_GPIO         217
+#define HREFV60_HAL_SW_GPIO             145
+#define HREFV60_SDMMC_EN_GPIO           169
+#define HREFV60_SDMMC_1V8_3V_GPIO       5
+#define HREFV60_SDMMC_CD_GPIO           95
+#define HREFV60_ACCEL_INT1_GPIO         82
+#define HREFV60_ACCEL_INT2_GPIO         83
+#define HREFV60_MAGNET_DRDY_GPIO        32
+#define HREFV60_DISP1_RST_GPIO          65
+#define HREFV60_DISP2_RST_GPIO          66
 /* GPIOs on the TC35892 expander */
+#define MOP500_EGPIO(x)                 (NOMADIK_NR_GPIO + (x))
 #define GPIO_SDMMC_CD                   MOP500_EGPIO(3)
+#define GPIO_PROX_SENSOR                MOP500_EGPIO(7)
+#define GPIO_BU21013_CS                 MOP500_EGPIO(13)
 #define GPIO_SDMMC_EN                   MOP500_EGPIO(17)
 #define GPIO_SDMMC_1V8_3V_SEL           MOP500_EGPIO(18)
+struct i2c_board_info;
 extern void mop500_sdi_init(void);
 extern void mop500_sdi_tc35892_init(void);
-extern void mop500_keypad_init(void);
+void __init mop500_u8500uib_init(void);
+void __init mop500_stuib_init(void);
+void __init mop500_pins_init(void);
+void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
+                unsigned n);
 #endif
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c
index 54712acc0394..739fb4c5b160 100644
--- a/arch/arm/mach-ux500/board-u5500-sdi.c
+++ b/arch/arm/mach-ux500/board-u5500-sdi.c
@@ -31,6 +31,26 @@ static pin_cfg_t u5500_sdi_pins[] = {
        GPIO14_MC0_CLK          | PIN_DIR_OUTPUT | PIN_VAL_LOW,
 };
+#ifdef CONFIG_STE_DMA40
+struct stedma40_chan_cfg u5500_sdi0_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type = DB5500_DMA_DEV24_SDMMC0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+static struct stedma40_chan_cfg u5500_sdi0_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB5500_DMA_DEV24_SDMMC0_TX,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+#endif
 static struct mmci_platform_data u5500_sdi0_data = {
        .ocr_mask       = MMC_VDD_165_195,
        .f_max          = 50000000,
@@ -39,6 +59,11 @@ static struct mmci_platform_data u5500_sdi0_data = {
                                MMC_CAP_MMC_HIGHSPEED,
        .gpio_cd        = -1,
        .gpio_wp        = -1,
+#ifdef CONFIG_STE_DMA40
+        .dma_filter     = stedma40_filter,
+        .dma_rx_param   = &u5500_sdi0_dma_cfg_rx,
+        .dma_tx_param   = &u5500_sdi0_dma_cfg_tx,
+#endif
 };
 void __init u5500_sdi_init(void)
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 39d370c1f3b4..44fd3b5c33ec 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -22,9 +22,9 @@
 static void __init u5500_uart_init(void)
 {
-        db5500_add_uart0();
+        db5500_add_uart0(NULL);
-        db5500_add_uart1();
+        db5500_add_uart1(NULL);
-        db5500_add_uart2();
+        db5500_add_uart2(NULL);
 }
 static void __init u5500_init_machine(void)
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index b2b0a3b9be8f..32ce90840ee1 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -313,7 +313,7 @@ static DEFINE_PRCMU_CLK_RATE(uartclk,	0x0, 5, UARTCLK, 38400000);
 static DEFINE_PRCMU_CLK(msp02clk,       0x0, 6, MSP02CLK);
 static DEFINE_PRCMU_CLK(msp1clk,        0x0, 7, MSP1CLK); /* v1 */
 static DEFINE_PRCMU_CLK_RATE(i2cclk,    0x0, 8, I2CCLK, 48000000);
-static DEFINE_PRCMU_CLK_RATE(sdmmcclk,  0x0, 9, SDMMCCLK, 50000000);
+static DEFINE_PRCMU_CLK_RATE(sdmmcclk,  0x0, 9, SDMMCCLK, 100000000);
 static DEFINE_PRCMU_CLK(slimclk,        0x0, 10, SLIMCLK);
 static DEFINE_PRCMU_CLK(per1clk,        0x0, 11, PER1CLK);
 static DEFINE_PRCMU_CLK(per2clk,        0x0, 12, PER2CLK);
@@ -520,7 +520,7 @@ static struct clk_lookup u8500_ed_clks[] = {
        CLK(ssp0_ed,    "ssp0",         NULL),
        /* Peripheral Cluster #5 */
-        CLK(usb_ed,     "musb_hdrc.0",  "usb"),
+        CLK(usb_ed,     "musb-ux500.0", "usb"),
        /* Peripheral Cluster #6 */
        CLK(dmc_ed,     "dmc",          NULL),
@@ -561,7 +561,7 @@ static struct clk_lookup u8500_v1_clks[] = {
        CLK(ssp0_v1,    "ssp0",         NULL),
        /* Peripheral Cluster #5 */
-        CLK(usb_v1,     "musb_hdrc.0",  "usb"),
+        CLK(usb_v1,     "musb-ux500.0", "usb"),
        /* Peripheral Cluster #6 */
        CLK(mtu1_v1,    "mtu1",         NULL),
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index af04e0891a78..c9dc2eff3cb2 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -11,6 +11,7 @@
 #include <linux/irq.h>
 #include <asm/mach/map.h>
+#include <asm/pmu.h>
 #include <plat/gpio.h>
@@ -18,8 +19,10 @@
 #include <mach/devices.h>
 #include <mach/setup.h>
 #include <mach/irqs.h>
+#include <mach/usb.h>
 #include "devices-db5500.h"
+#include "ste-dma40-db5500.h"
 static struct map_desc u5500_uart_io_desc[] __initdata = {
        __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K),
@@ -43,6 +46,26 @@ static struct map_desc u5500_io_desc[] __initdata = {
        __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
 };
+static struct resource db5500_pmu_resources[] = {
+        [0] = {
+                .start          = IRQ_DB5500_PMU0,
+                .end            = IRQ_DB5500_PMU0,
+                .flags          = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start          = IRQ_DB5500_PMU1,
+                .end            = IRQ_DB5500_PMU1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device db5500_pmu_device = {
+        .name                   = "arm-pmu",
+        .id                     = ARM_PMU_DEVICE_CPU,
+        .num_resources          = ARRAY_SIZE(db5500_pmu_resources),
+        .resource               = db5500_pmu_resources,
+};
 static struct resource mbox0_resources[] = {
        {
                .name = "mbox_peer",
@@ -127,7 +150,8 @@ static struct platform_device mbox2_device = {
        .num_resources = ARRAY_SIZE(mbox2_resources),
 };
-static struct platform_device *u5500_platform_devs[] __initdata = {
+static struct platform_device *db5500_platform_devs[] __initdata = {
+        &db5500_pmu_device,
        &mbox0_device,
        &mbox1_device,
        &mbox2_device,
@@ -166,12 +190,35 @@ void __init u5500_map_io(void)
        iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
 }
+static int usb_db5500_rx_dma_cfg[] = {
+        DB5500_DMA_DEV4_USB_OTG_IEP_1_9,
+        DB5500_DMA_DEV5_USB_OTG_IEP_2_10,
+        DB5500_DMA_DEV6_USB_OTG_IEP_3_11,
+        DB5500_DMA_DEV20_USB_OTG_IEP_4_12,
+        DB5500_DMA_DEV21_USB_OTG_IEP_5_13,
+        DB5500_DMA_DEV22_USB_OTG_IEP_6_14,
+        DB5500_DMA_DEV23_USB_OTG_IEP_7_15,
+        DB5500_DMA_DEV38_USB_OTG_IEP_8
+};
+static int usb_db5500_tx_dma_cfg[] = {
+        DB5500_DMA_DEV4_USB_OTG_OEP_1_9,
+        DB5500_DMA_DEV5_USB_OTG_OEP_2_10,
+        DB5500_DMA_DEV6_USB_OTG_OEP_3_11,
+        DB5500_DMA_DEV20_USB_OTG_OEP_4_12,
+        DB5500_DMA_DEV21_USB_OTG_OEP_5_13,
+        DB5500_DMA_DEV22_USB_OTG_OEP_6_14,
+        DB5500_DMA_DEV23_USB_OTG_OEP_7_15,
+        DB5500_DMA_DEV38_USB_OTG_OEP_8
+};
 void __init u5500_init_devices(void)
 {
        db5500_add_gpios();
        db5500_dma_init();
        db5500_add_rtc();
+        db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
-        platform_add_devices(u5500_platform_devs,
+        platform_add_devices(db5500_platform_devs,
-                             ARRAY_SIZE(u5500_platform_devs));
+                             ARRAY_SIZE(db5500_platform_devs));
 }
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 1748fbc58530..516126cb357d 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -12,21 +12,21 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/amba/bus.h>
+#include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <asm/mach/map.h>
+#include <asm/pmu.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
+#include <mach/usb.h>
 #include "devices-db8500.h"
+#include "ste-dma40-db8500.h"
-static struct platform_device *platform_devs[] __initdata = {
-        &u8500_dma40_device,
-};
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_uart_io_desc[] __initdata = {
@@ -89,6 +89,51 @@ void __init u8500_map_io(void)
                iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
 }
+static struct resource db8500_pmu_resources[] = {
+        [0] = {
+                .start          = IRQ_DB8500_PMU,
+                .end            = IRQ_DB8500_PMU,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+/*
+ * The PMU IRQ lines of two cores are wired together into a single interrupt.
+ * Bounce the interrupt to the other core if it's not ours.
+ */
+static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
+{
+        irqreturn_t ret = handler(irq, dev);
+        int other = !smp_processor_id();
+        if (ret == IRQ_NONE && cpu_online(other))
+                irq_set_affinity(irq, cpumask_of(other));
+        /*
+         * We should be able to get away with the amount of IRQ_NONEs we give,
+         * while still having the spurious IRQ detection code kick in if the
+         * interrupt really starts hitting spuriously.
+         */
+        return ret;
+}
+static struct arm_pmu_platdata db8500_pmu_platdata = {
+        .handle_irq             = db8500_pmu_handler,
+};
+static struct platform_device db8500_pmu_device = {
+        .name                   = "arm-pmu",
+        .id                     = ARM_PMU_DEVICE_CPU,
+        .num_resources          = ARRAY_SIZE(db8500_pmu_resources),
+        .resource               = db8500_pmu_resources,
+        .dev.platform_data      = &db8500_pmu_platdata,
+};
+static struct platform_device *platform_devs[] __initdata = {
+        &u8500_dma40_device,
+        &db8500_pmu_device,
+};
 static resource_size_t __initdata db8500_gpio_base[] = {
        U8500_GPIOBANK0_BASE,
        U8500_GPIOBANK1_BASE,
@@ -111,6 +156,28 @@ static void __init db8500_add_gpios(void)
                         IRQ_DB8500_GPIO0, &pdata);
 }
+static int usb_db8500_rx_dma_cfg[] = {
+        DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
+        DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
+        DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
+        DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
+        DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
+        DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
+        DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
+        DB8500_DMA_DEV39_USB_OTG_IEP_8
+};
+static int usb_db8500_tx_dma_cfg[] = {
+        DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
+        DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
+        DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
+        DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
+        DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
+        DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
+        DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
+        DB8500_DMA_DEV39_USB_OTG_OEP_8
+};
 /*
 * This function is called from the board init
 */
@@ -121,6 +188,7 @@ void __init u8500_init_devices(void)
        db8500_add_rtc();
        db8500_add_gpios();
+        db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
        platform_device_register_simple("cpufreq-u8500", -1, NULL, 0);
        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index fe69f5fac1bb..13a4ce046ae5 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -139,6 +139,7 @@ void dbx500_add_gpios(resource_size_t *base, int num, int irq,
        for (i = 0; i < num; i++, first += 32, irq++) {
                pdata->first_gpio = first;
                pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
+                pdata->num_gpio = 32;
                dbx500_add_gpio(i, base[i], irq, pdata);
        }
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index cbadc117d2db..c719b5a1d913 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -42,10 +42,13 @@ dbx500_add_sdi(const char *name, resource_size_t base, int irq,
        return dbx500_add_amba_device(name, base, irq, pdata, 0);
 }
+struct amba_pl011_data;
 static inline struct amba_device *
-dbx500_add_uart(const char *name, resource_size_t base, int irq)
+dbx500_add_uart(const char *name, resource_size_t base, int irq,
+                struct amba_pl011_data *pdata)
 {
-        return dbx500_add_amba_device(name, base, irq, NULL, 0);
+        return dbx500_add_amba_device(name, base, irq, pdata, 0);
 }
 struct nmk_i2c_controller;
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
index c8d7901c1f2d..94627f7783b0 100644
--- a/arch/arm/mach-ux500/devices-db5500.h
+++ b/arch/arm/mach-ux500/devices-db5500.h
@@ -34,6 +34,9 @@
 #define db5500_add_rtc() \
        dbx500_add_rtc(U5500_RTC_BASE, IRQ_DB5500_RTC);
+#define db5500_add_usb(rx_cfg, tx_cfg) \
+        ux500_add_usb(U5500_USBOTG_BASE, IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
 #define db5500_add_sdi0(pdata) \
        dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata)
 #define db5500_add_sdi1(pdata) \
@@ -54,13 +57,13 @@
 #define db5500_add_spi3(pdata) \
        dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata)
-#define db5500_add_uart0() \
+#define db5500_add_uart0(plat) \
-        dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0)
+        dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0, plat)
-#define db5500_add_uart1() \
+#define db5500_add_uart1(plat) \
-        dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1)
+        dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1, plat)
-#define db5500_add_uart2() \
+#define db5500_add_uart2(plat) \
-        dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2)
+        dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2, plat)
-#define db5500_add_uart3() \
+#define db5500_add_uart3(plat) \
-        dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3)
+        dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3, plat)
 #endif
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 23c695d54977..73b17404b194 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -11,6 +11,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl022.h>
 #include <plat/ste_dma40.h>
@@ -67,12 +68,72 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
 /*
 * Mapping between destination event lines and physical device address.
- * The event line is tied to a device and therefor the address is constant.
+ * The event line is tied to a device and therefore the address is constant.
+ * When the address comes from a primecell it will be configured in runtime
+ * and we set the address to -1 as a placeholder.
 */
-static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV];
+static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
+        /* MUSB - these will be runtime-reconfigured */
+        [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
+        [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
+        [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
+        [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
+        [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
+        [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
+        [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
+        [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
+        /* PrimeCells - run-time configured */
+        [DB8500_DMA_DEV0_SPI0_TX] = -1,
+        [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
+        [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
+        [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
+        [DB8500_DMA_DEV8_SSP0_TX] = -1,
+        [DB8500_DMA_DEV9_SSP1_TX] = -1,
+        [DB8500_DMA_DEV11_UART2_TX] = -1,
+        [DB8500_DMA_DEV12_UART1_TX] = -1,
+        [DB8500_DMA_DEV13_UART0_TX] = -1,
+        [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
+        [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
+        [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
+        [DB8500_DMA_DEV33_SPI2_TX] = -1,
+        [DB8500_DMA_DEV35_SPI1_TX] = -1,
+        [DB8500_DMA_DEV40_SPI3_TX] = -1,
+        [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
+        [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
+        [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
+};
 /* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV];
+static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
+        /* MUSB - these will be runtime-reconfigured */
+        [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
+        [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
+        [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
+        [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
+        [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
+        [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
+        [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
+        [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
+        /* PrimeCells */
+        [DB8500_DMA_DEV0_SPI0_RX] = -1,
+        [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
+        [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
+        [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
+        [DB8500_DMA_DEV8_SSP0_RX] = -1,
+        [DB8500_DMA_DEV9_SSP1_RX] = -1,
+        [DB8500_DMA_DEV11_UART2_RX] = -1,
+        [DB8500_DMA_DEV12_UART1_RX] = -1,
+        [DB8500_DMA_DEV13_UART0_RX] = -1,
+        [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
+        [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
+        [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
+        [DB8500_DMA_DEV33_SPI2_RX] = -1,
+        [DB8500_DMA_DEV35_SPI1_RX] = -1,
+        [DB8500_DMA_DEV40_SPI3_RX] = -1,
+        [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
+        [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
+        [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
+};
 /* Reserved event lines for memcpy only */
 static int dma40_memcpy_event[] = {
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 3a770c756979..9cc6f8f5d3e6 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -61,6 +61,9 @@ db8500_add_ssp(const char *name, resource_size_t base, int irq,
 #define db8500_add_rtc() \
        dbx500_add_rtc(U8500_RTC_BASE, IRQ_DB8500_RTC);
+#define db8500_add_usb(rx_cfg, tx_cfg) \
+        ux500_add_usb(U8500_USBOTG_BASE, IRQ_DB8500_USBOTG, rx_cfg, tx_cfg)
 #define db8500_add_sdi0(pdata) \
        dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata)
 #define db8500_add_sdi1(pdata) \
@@ -88,11 +91,11 @@ db8500_add_ssp(const char *name, resource_size_t base, int irq,
 #define db8500_add_spi3(pdata) \
        dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata)
-#define db8500_add_uart0() \
+#define db8500_add_uart0(pdata) \
-        dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0)
+        dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0, pdata)
-#define db8500_add_uart1() \
+#define db8500_add_uart1(pdata) \
-        dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1)
+        dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1, pdata)
-#define db8500_add_uart2() \
+#define db8500_add_uart2(pdata) \
-        dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2)
+        dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2, pdata)
 #endif
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c
index 32a061f8a95b..1cfab68ae417 100644
--- a/arch/arm/mach-ux500/dma-db5500.c
+++ b/arch/arm/mach-ux500/dma-db5500.c
@@ -73,11 +73,27 @@ static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
 */
 static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = {
        [DB5500_DMA_DEV24_SDMMC0_RX] = -1,
+        [DB5500_DMA_DEV38_USB_OTG_IEP_8] = -1,
+        [DB5500_DMA_DEV23_USB_OTG_IEP_7_15] = -1,
+        [DB5500_DMA_DEV22_USB_OTG_IEP_6_14] = -1,
+        [DB5500_DMA_DEV21_USB_OTG_IEP_5_13] = -1,
+        [DB5500_DMA_DEV20_USB_OTG_IEP_4_12] = -1,
+        [DB5500_DMA_DEV6_USB_OTG_IEP_3_11] = -1,
+        [DB5500_DMA_DEV5_USB_OTG_IEP_2_10] = -1,
+        [DB5500_DMA_DEV4_USB_OTG_IEP_1_9] = -1,
 };
 /* Mapping between destination event lines and physical device address */
 static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = {
        [DB5500_DMA_DEV24_SDMMC0_TX] = -1,
+        [DB5500_DMA_DEV38_USB_OTG_OEP_8] = -1,
+        [DB5500_DMA_DEV23_USB_OTG_OEP_7_15] = -1,
+        [DB5500_DMA_DEV22_USB_OTG_OEP_6_14] = -1,
+        [DB5500_DMA_DEV21_USB_OTG_OEP_5_13] = -1,
+        [DB5500_DMA_DEV20_USB_OTG_OEP_4_12] = -1,
+        [DB5500_DMA_DEV6_USB_OTG_OEP_3_11] = -1,
+        [DB5500_DMA_DEV5_USB_OTG_OEP_2_10] = -1,
+        [DB5500_DMA_DEV4_USB_OTG_OEP_1_9] = -1,
 };
 static int dma40_memcpy_event[] = {
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 9a6614c6808e..ab0fe1432fae 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -50,7 +50,11 @@ static void flush(void)
 static inline void arch_decomp_setup(void)
 {
-        if (machine_is_u8500())
+        /* Check in run time if we run on an U8500 or U5500 */
+        if (machine_is_u8500() ||
+            machine_is_svp8500v1() ||
+            machine_is_svp8500v2() ||
+            machine_is_hrefv60())
                ux500_uart_base = U8500_UART2_BASE;
        else if (machine_is_u5500())
                ux500_uart_base = U5500_UART0_BASE;
diff --git a/arch/arm/mach-ux500/include/mach/usb.h b/arch/arm/mach-ux500/include/mach/usb.h
new file mode 100644
index 000000000000..d3739d418813
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/usb.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __ASM_ARCH_USB_H
+#define __ASM_ARCH_USB_H
+#include <linux/dmaengine.h>
+#define UX500_MUSB_DMA_NUM_RX_CHANNELS 8
+#define UX500_MUSB_DMA_NUM_TX_CHANNELS 8
+struct ux500_musb_board_data {
+        void    **dma_rx_param_array;
+        void    **dma_tx_param_array;
+        u32     num_rx_channels;
+        u32     num_tx_channels;
+        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+};
+void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg,
+        int *dma_tx_cfg);
+#endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
new file mode 100644
index 000000000000..82e535953fd9
--- /dev/null
+++ b/arch/arm/mach-ux500/usb.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#include <linux/platform_device.h>
+#include <linux/usb/musb.h>
+#include <plat/ste_dma40.h>
+#include <mach/hardware.h>
+#include <mach/usb.h>
+#define MUSB_DMA40_RX_CH { \
+                .mode = STEDMA40_MODE_LOGICAL, \
+                .dir = STEDMA40_PERIPH_TO_MEM, \
+                .dst_dev_type = STEDMA40_DEV_DST_MEMORY, \
+                .src_info.data_width = STEDMA40_WORD_WIDTH, \
+                .dst_info.data_width = STEDMA40_WORD_WIDTH, \
+                .src_info.psize = STEDMA40_PSIZE_LOG_16, \
+                .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
+        }
+#define MUSB_DMA40_TX_CH { \
+                .mode = STEDMA40_MODE_LOGICAL, \
+                .dir = STEDMA40_MEM_TO_PERIPH, \
+                .src_dev_type = STEDMA40_DEV_SRC_MEMORY, \
+                .src_info.data_width = STEDMA40_WORD_WIDTH, \
+                .dst_info.data_width = STEDMA40_WORD_WIDTH, \
+                .src_info.psize = STEDMA40_PSIZE_LOG_16, \
+                .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
+        }
+static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
+        = {
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH
+};
+static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
+        = {
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+};
+static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
+        &musb_dma_rx_ch[0],
+        &musb_dma_rx_ch[1],
+        &musb_dma_rx_ch[2],
+        &musb_dma_rx_ch[3],
+        &musb_dma_rx_ch[4],
+        &musb_dma_rx_ch[5],
+        &musb_dma_rx_ch[6],
+        &musb_dma_rx_ch[7]
+};
+static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
+        &musb_dma_tx_ch[0],
+        &musb_dma_tx_ch[1],
+        &musb_dma_tx_ch[2],
+        &musb_dma_tx_ch[3],
+        &musb_dma_tx_ch[4],
+        &musb_dma_tx_ch[5],
+        &musb_dma_tx_ch[6],
+        &musb_dma_tx_ch[7]
+};
+static struct ux500_musb_board_data musb_board_data = {
+        .dma_rx_param_array = ux500_dma_rx_param_array,
+        .dma_tx_param_array = ux500_dma_tx_param_array,
+        .num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS,
+        .num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS,
+        .dma_filter = stedma40_filter,
+};
+static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
+static struct musb_hdrc_config musb_hdrc_config = {
+        .multipoint     = true,
+        .dyn_fifo       = true,
+        .num_eps        = 16,
+        .ram_bits       = 16,
+};
+static struct musb_hdrc_platform_data musb_platform_data = {
+#if defined(CONFIG_USB_MUSB_OTG)
+        .mode = MUSB_OTG,
+#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
+        .mode = MUSB_PERIPHERAL,
+#else /* defined(CONFIG_USB_MUSB_HOST) */
+        .mode = MUSB_HOST,
+#endif
+        .config = &musb_hdrc_config,
+        .board_data = &musb_board_data,
+};
+static struct resource usb_resources[] = {
+        [0] = {
+                .name   = "usb-mem",
+                .flags  =  IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "mc", /* hard-coded in musb */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device ux500_musb_device = {
+        .name = "musb-ux500",
+        .id = 0,
+        .dev = {
+                .platform_data = &musb_platform_data,
+                .dma_mask = &ux500_musb_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources = ARRAY_SIZE(usb_resources),
+        .resource = usb_resources,
+};
+static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type)
+{
+        u32 idx;
+        for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
+                musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx];
+}
+static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type)
+{
+        u32 idx;
+        for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
+                musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx];
+}
+void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg,
+        int *dma_tx_cfg)
+{
+        ux500_musb_device.resource[0].start = base;
+        ux500_musb_device.resource[0].end = base + SZ_64K - 1;
+        ux500_musb_device.resource[1].start = irq;
+        ux500_musb_device.resource[1].end = irq;
+        ux500_usb_dma_update_rx_ch_config(dma_rx_cfg);
+        ux500_usb_dma_update_tx_ch_config(dma_tx_cfg);
+        platform_device_register(&ux500_musb_device);
+}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e4509bae8fc4..2bd4ccfb3538 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -811,7 +811,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"
        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
+                   REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
                   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
                   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
        default y
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 389f21795015..b0cb4258e382 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -33,6 +33,7 @@ config ARCH_MX3
 config ARCH_MXC91231
        bool "MXC91231-based"
        select CPU_V6
+        select MXC_AVIC
        help
          This enables support for systems based on the Freescale MXC91231 family
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 5fd20e96876c..a1387875a491 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -13,7 +13,6 @@ obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
-obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index e9bcefe79a43..eee1b6096a08 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -81,6 +81,8 @@ struct platform_device *__init imx_add_platform_device_dmamask(
        ret = platform_device_add(pdev);
        if (ret) {
 err:
+                if (dmamask)
+                        kfree(pdev->dev.dma_mask);
                platform_device_put(pdev);
                return ERR_PTR(ret);
        }
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index b50c3517d083..6561c9df5f0d 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -31,6 +31,11 @@ const struct imx_fec_data imx35_fec_data __initconst =
        imx_fec_data_entry_single(MX35);
 #endif
+#ifdef CONFIG_SOC_IMX50
+const struct imx_fec_data imx50_fec_data __initconst =
+        imx_fec_data_entry_single(MX50);
+#endif
 #ifdef CONFIG_SOC_IMX51
 const struct imx_fec_data imx51_fec_data __initconst =
        imx_fec_data_entry_single(MX51);
@@ -57,7 +62,7 @@ struct platform_device *__init imx_add_fec(
                },
        };
-        return imx_add_platform_device("fec", 0 /* -1? */,
+        return imx_add_platform_device_dmamask("fec", 0,
                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata));
+                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
 }
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
index 33530d2d5ed1..3538b85ede91 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -94,7 +94,7 @@ static struct sdma_script_start_addrs addr_imx25_to1 = {
 };
 #endif
-#ifdef CONFIG_ARCH_MX31
+#ifdef CONFIG_SOC_IMX31
 static struct sdma_script_start_addrs addr_imx31_to1 = {
        .per_2_per_addr = 1677,
 };
@@ -106,7 +106,7 @@ static struct sdma_script_start_addrs addr_imx31_to2 = {
 };
 #endif
-#ifdef CONFIG_ARCH_MX35
+#ifdef CONFIG_SOC_IMX35
 static struct sdma_script_start_addrs addr_imx35_to1 = {
        .ap_2_ap_addr = 642,
        .uart_2_mcu_addr = 817,
@@ -194,7 +194,7 @@ static int __init imxXX_add_imx_dma(void)
        } else
 #endif
-#if defined(CONFIG_ARCH_MX51)
+#if defined(CONFIG_SOC_IMX51)
        if (cpu_is_mx51()) {
                imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1;
                ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c
index 6100a7d824dd..79a1cb18a5b0 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-fb.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c
@@ -16,6 +16,11 @@
                .irq = soc ## _INT_LCDC,                                \
        }
+#ifdef CONFIG_SOC_IMX1
+const struct imx_imx_fb_data imx1_imx_fb_data __initconst =
+        imx_imx_fb_data_entry_single(MX1, SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX1 */
 #ifdef CONFIG_SOC_IMX21
 const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
        imx_imx_fb_data_entry_single(MX21, SZ_4K);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index 7ba94e1bbda3..2ab74f0da9a6 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -69,6 +69,16 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
+#ifdef CONFIG_SOC_IMX50
+const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = {
+#define imx50_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX50, _id, _hwid, SZ_4K)
+        imx50_imx_i2c_data_entry(0, 1),
+        imx50_imx_i2c_data_entry(1, 2),
+        imx50_imx_i2c_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_SOC_IMX51 */
 #ifdef CONFIG_SOC_IMX51
 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
 #define imx51_imx_i2c_data_entry(_id, _hwid)                            \
diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
index e0aec61177f4..5e07ef2bf1c4 100644
--- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
+++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
@@ -53,6 +53,15 @@ const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX51 */
+#ifdef CONFIG_SOC_IMX53
+const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = {
+#define imx53_imx2_wdt_data_entry(_id, _hwid)                           \
+        imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K)
+        imx53_imx2_wdt_data_entry(0, 1),
+        imx53_imx2_wdt_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX53 */
 struct platform_device *__init imx_add_imx2_wdt(
                const struct imx_imx2_wdt_data *data)
 {
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 013c85f20b58..f4a60ab6763b 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -21,6 +21,15 @@
 #define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size)        \
        [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
+#ifdef CONFIG_SOC_IMX1
+const struct imx_spi_imx_data imx1_cspi_data[] __initconst = {
+#define imx1_cspi_data_entry(_id, _hwid) \
+        imx_spi_imx_data_entry(MX1, CSPI, "imx1-cspi", _id, _hwid, SZ_4K)
+        imx1_cspi_data_entry(0, 1),
+        imx1_cspi_data_entry(1, 2),
+};
+#endif
 #ifdef CONFIG_SOC_IMX21
 const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
 #define imx21_cspi_data_entry(_id, _hwid)                            \
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
deleted file mode 100644
index 8772ce346a58..000000000000
--- a/arch/arm/plat-mxc/ehci.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- */
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
-#define USBCTRL_OTGBASE_OFFSET  0x600
-#define MX31_OTG_SIC_SHIFT      29
-#define MX31_OTG_SIC_MASK       (0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT         (1 << 24)
-#define MX31_H2_SIC_SHIFT       21
-#define MX31_H2_SIC_MASK        (0x3 << MX31_H2_SIC_SHIFT)
-#define MX31_H2_PM_BIT          (1 << 16)
-#define MX31_H2_DT_BIT          (1 << 5)
-#define MX31_H1_SIC_SHIFT       13
-#define MX31_H1_SIC_MASK        (0x3 << MX31_H1_SIC_SHIFT)
-#define MX31_H1_PM_BIT          (1 << 8)
-#define MX31_H1_DT_BIT          (1 << 4)
-#define MX35_OTG_SIC_SHIFT      29
-#define MX35_OTG_SIC_MASK       (0x3 << MX35_OTG_SIC_SHIFT)
-#define MX35_OTG_PM_BIT         (1 << 24)
-#define MX35_H1_SIC_SHIFT       21
-#define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
-#define MX35_H1_PM_BIT          (1 << 8)
-#define MX35_H1_IPPUE_UP_BIT    (1 << 7)
-#define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
-#define MX35_H1_TLL_BIT         (1 << 5)
-#define MX35_H1_USBTE_BIT       (1 << 4)
-#define MXC_OTG_OFFSET          0
-#define MXC_H1_OFFSET           0x200
-#define MXC_H2_OFFSET           0x400
-/* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)               /* HOST1 power mask */
-/* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT                       (1 << 5)        /* UH1 Disable Overcurrent Event */
-/* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT          (1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT           (1 << 4)
-#define MXC_USBCMD_OFFSET                       0x140
-/* USBCMD */
-#define MXC_UCMD_ITC_NO_THRESHOLD_MASK  (~(0xff << 16)) /* Interrupt Threshold Control */
-int mxc_initialize_usb_hw(int port, unsigned int flags)
-{
-        unsigned int v;
-#if defined(CONFIG_SOC_IMX25)
-        if (cpu_is_mx25()) {
-                v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                switch (port) {
-                case 0: /* OTG port */
-                        v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                        << MX35_OTG_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX35_OTG_PM_BIT;
-                        break;
-                case 1: /* H1 port */
-                        v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
-                                MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX35_H1_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX35_H1_PM_BIT;
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX35_H1_TLL_BIT;
-                        if (flags & MXC_EHCI_INTERNAL_PHY)
-                                v |= MX35_H1_USBTE_BIT;
-                        if (flags & MXC_EHCI_IPPUE_DOWN)
-                                v |= MX35_H1_IPPUE_DOWN_BIT;
-                        if (flags & MXC_EHCI_IPPUE_UP)
-                                v |= MX35_H1_IPPUE_UP_BIT;
-                        break;
-                default:
-                        return -EINVAL;
-                }
-                writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                return 0;
-        }
-#endif /* if defined(CONFIG_SOC_IMX25) */
-#if defined(CONFIG_ARCH_MX3)
-        if (cpu_is_mx31()) {
-                v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                switch (port) {
-                case 0: /* OTG port */
-                        v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                        << MX31_OTG_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_OTG_PM_BIT;
-                        break;
-                case 1: /* H1 port */
-                        v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX31_H1_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_H1_PM_BIT;
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX31_H1_DT_BIT;
-                        break;
-                case 2: /* H2 port */
-                        v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX31_H2_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_H2_PM_BIT;
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX31_H2_DT_BIT;
-                        break;
-                default:
-                        return -EINVAL;
-                }
-                writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                return 0;
-        }
-        if (cpu_is_mx35()) {
-                v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                switch (port) {
-                case 0: /* OTG port */
-                        v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                        << MX35_OTG_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX35_OTG_PM_BIT;
-                        break;
-                case 1: /* H1 port */
-                        v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
-                                MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX35_H1_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX35_H1_PM_BIT;
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX35_H1_TLL_BIT;
-                        if (flags & MXC_EHCI_INTERNAL_PHY)
-                                v |= MX35_H1_USBTE_BIT;
-                        if (flags & MXC_EHCI_IPPUE_DOWN)
-                                v |= MX35_H1_IPPUE_DOWN_BIT;
-                        if (flags & MXC_EHCI_IPPUE_UP)
-                                v |= MX35_H1_IPPUE_UP_BIT;
-                        break;
-                default:
-                        return -EINVAL;
-                }
-                writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                return 0;
-        }
-#endif /* CONFIG_ARCH_MX3 */
-#ifdef CONFIG_MACH_MX27
-        if (cpu_is_mx27()) {
-                /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
-                 * are identical
-                 */
-                v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                switch (port) {
-                case 0: /* OTG port */
-                        v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                        << MX31_OTG_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_OTG_PM_BIT;
-                        break;
-                case 1: /* H1 port */
-                        v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX31_H1_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_H1_PM_BIT;
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX31_H1_DT_BIT;
-                        break;
-                case 2: /* H2 port */
-                        v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX31_H2_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_H2_PM_BIT;
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX31_H2_DT_BIT;
-                        break;
-                default:
-                        return -EINVAL;
-                }
-                writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                return 0;
-        }
-#endif /* CONFIG_MACH_MX27 */
-#ifdef CONFIG_SOC_IMX51
-        if (cpu_is_mx51()) {
-                void __iomem *usb_base;
-                void __iomem *usbotg_base;
-                void __iomem *usbother_base;
-                int ret = 0;
-                usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
-                if (!usb_base) {
-                        printk(KERN_ERR "%s(): ioremap failed\n", __func__);
-                        return -ENOMEM;
-                }
-                switch (port) {
-                case 0: /* OTG port */
-                        usbotg_base = usb_base + MXC_OTG_OFFSET;
-                        break;
-                case 1: /* Host 1 port */
-                        usbotg_base = usb_base + MXC_H1_OFFSET;
-                        break;
-                case 2: /* Host 2 port */
-                        usbotg_base = usb_base + MXC_H2_OFFSET;
-                        break;
-                default:
-                        printk(KERN_ERR"%s no such port %d\n", __func__, port);
-                        ret = -ENOENT;
-                        goto error;
-                }
-                usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-                switch (port) {
-                case 0: /*OTG port */
-                        if (flags & MXC_EHCI_INTERNAL_PHY) {
-                                v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-                                if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
-                                        /* OC/USBPWR is not used */
-                                        v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                                } else {
-                                        /* OC/USBPWR is used */
-                                        v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                                }
-                                __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-                                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                                if (flags & MXC_EHCI_WAKEUP_ENABLED)
-                                        v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
-                                else
-                                        v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
-                                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                        v |= MXC_OTG_UCTRL_OPM_BIT;
-                                else
-                                        v &= ~MXC_OTG_UCTRL_OPM_BIT;
-                                __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-                        }
-                        break;
-                case 1: /* Host 1 */
-                        /*Host ULPI */
-                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                        if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                                /* HOST1 wakeup/ULPI intr enable */
-                                v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-                        } else {
-                                /* HOST1 wakeup/ULPI intr disable */
-                                v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-                        }
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
-                        else
-                                v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
-                        __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-                        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
-                        else
-                                v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
-                        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-                        v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
-                        if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
-                                /* Interrupt Threshold Control:Immediate (no threshold) */
-                                v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
-                        __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
-                        break;
-                case 2: /* Host 2 ULPI */
-                        v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
-                        if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                                /* HOST1 wakeup/ULPI intr enable */
-                                v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-                        } else {
-                                /* HOST1 wakeup/ULPI intr disable */
-                                v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-                        }
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
-                        else
-                                v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
-                        __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
-                        break;
-                }
-error:
-                iounmap(usb_base);
-                return ret;
-        }
-#endif
-        printk(KERN_WARNING
-                "%s() unable to setup USBCONTROL for this CPU\n", __func__);
-        return -EINVAL;
-}
-EXPORT_SYMBOL(mxc_initialize_usb_hw);
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index d17b3c996b84..57d59855f9ec 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -233,6 +233,7 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
 }
 static struct irq_chip gpio_irq_chip = {
+        .name = "GPIO",
        .irq_ack = gpio_ack_irq,
        .irq_mask = gpio_mask_irq,
        .irq_unmask = gpio_unmask_irq,
@@ -349,113 +350,3 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
        return 0;
 }
-#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
-        {                                                               \
-                .chip.label = "gpio-" #_id,                             \
-                .irq = _irq,                                            \
-                .irq_high = _irq_high,                                  \
-                .base = soc ## _IO_ADDRESS(                             \
-                                soc ## _GPIO ## _hwid ## _BASE_ADDR),   \
-                .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32,   \
-        }
-#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq)                 \
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
-#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid)                           \
-        DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
-#define DEFINE_REGISTER_FUNCTION(prefix)                                \
-int __init prefix ## _register_gpios(void)                              \
-{                                                                       \
-        return mxc_gpio_init(prefix ## _gpio_ports,                     \
-                        ARRAY_SIZE(prefix ## _gpio_ports));             \
-}
-#if defined(CONFIG_SOC_IMX1)
-static struct mxc_gpio_port imx1_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
-};
-DEFINE_REGISTER_FUNCTION(imx1)
-#endif /* if defined(CONFIG_SOC_IMX1) */
-#if defined(CONFIG_SOC_IMX21)
-static struct mxc_gpio_port imx21_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
-        DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
-        DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
-        DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
-        DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
-        DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
-};
-DEFINE_REGISTER_FUNCTION(imx21)
-#endif /* if defined(CONFIG_SOC_IMX21) */
-#if defined(CONFIG_SOC_IMX25)
-static struct mxc_gpio_port imx25_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
-};
-DEFINE_REGISTER_FUNCTION(imx25)
-#endif /* if defined(CONFIG_SOC_IMX25) */
-#if defined(CONFIG_SOC_IMX27)
-static struct mxc_gpio_port imx27_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
-        DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
-        DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
-        DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
-        DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
-        DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
-};
-DEFINE_REGISTER_FUNCTION(imx27)
-#endif /* if defined(CONFIG_SOC_IMX27) */
-#if defined(CONFIG_SOC_IMX31)
-static struct mxc_gpio_port imx31_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
-};
-DEFINE_REGISTER_FUNCTION(imx31)
-#endif /* if defined(CONFIG_SOC_IMX31) */
-#if defined(CONFIG_SOC_IMX35)
-static struct mxc_gpio_port imx35_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
-};
-DEFINE_REGISTER_FUNCTION(imx35)
-#endif /* if defined(CONFIG_SOC_IMX35) */
-#if defined(CONFIG_SOC_IMX50)
-static struct mxc_gpio_port imx50_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-};
-DEFINE_REGISTER_FUNCTION(imx50)
-#endif /* if defined(CONFIG_SOC_IMX50) */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index aea2cd3b6d15..a22ebe11a602 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -24,6 +24,16 @@ extern void mx50_map_io(void);
 extern void mx51_map_io(void);
 extern void mx53_map_io(void);
 extern void mxc91231_map_io(void);
+extern void imx1_init_early(void);
+extern void imx21_init_early(void);
+extern void imx25_init_early(void);
+extern void imx27_init_early(void);
+extern void imx31_init_early(void);
+extern void imx35_init_early(void);
+extern void imx50_init_early(void);
+extern void imx51_init_early(void);
+extern void imx53_init_early(void);
+extern void mxc91231_init_early(void);
 extern void mxc_init_irq(void __iomem *);
 extern void tzic_init_irq(void __iomem *);
 extern void mx1_init_irq(void);
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 0044e2f1bea8..a2747f12813e 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -46,6 +46,21 @@ struct mxc_gpio_port {
        spinlock_t lock;
 };
+#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
+        {                                                               \
+                .chip.label = "gpio-" #_id,                             \
+                .irq = _irq,                                            \
+                .irq_high = _irq_high,                                  \
+                .base = soc ## _IO_ADDRESS(                             \
+                                soc ## _GPIO ## _hwid ## _BASE_ADDR),   \
+                .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32,   \
+        }
+#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq)                 \
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
+#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid)                           \
+        DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
 int mxc_gpio_init(struct mxc_gpio_port*, int);
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index cbaed295a2bf..c92f0b1f216f 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -112,12 +112,12 @@ enum iomux_gp_func {
 *      - setups the iomux according to the configuration
 *      - if the pin is configured as a GPIO, we claim it through kernel gpiolib
 */
-int mxc_iomux_alloc_pin(const unsigned int pin, const char *label);
+int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
 /*
 * setups mutliple pins
 * convenient way to call the above function with tables
 */
-int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
                const char *label);
 /*
@@ -126,12 +126,12 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
 *      - frees the GPIO if the pin was configured as GPIO
 *      - DOES NOT reconfigure the IOMUX in its reset state
 */
-void mxc_iomux_release_pin(const unsigned int pin);
+void mxc_iomux_release_pin(unsigned int pin);
 /*
 * releases multiple pins
 * convenvient way to call the above function with tables
 */
-void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
+void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
 /*
 * This function enables/disables the general purpose function for a particular
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
index 2a24bae1b878..3117c18bbbd9 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
@@ -989,13 +989,13 @@
 #define MX35_PAD_ATA_DATA2__IPU_DIAGB_9                         IOMUX_PAD(0x6e8, 0x284, 6, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28                 IOMUX_PAD(0x6e8, 0x284, 7, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__ATA_DATA_3                          IOMUX_PAD(0x6e8, 0x288, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__ATA_DATA_3                          IOMUX_PAD(0x6ec, 0x288, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__ESDHC3_CLK                          IOMUX_PAD(0x6e8, 0x288, 1, 0x814, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__ESDHC3_CLK                          IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5               IOMUX_PAD(0x6e8, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5               IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__CSPI2_SCLK                          IOMUX_PAD(0x6e8, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__CSPI2_SCLK                          IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__GPIO2_16                            IOMUX_PAD(0x6e8, 0x288, 5, 0x884, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__GPIO2_16                            IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10                        IOMUX_PAD(0x6e8, 0x288, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10                        IOMUX_PAD(0x6ec, 0x288, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29                 IOMUX_PAD(0x6e8, 0x288, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29                 IOMUX_PAD(0x6ec, 0x288, 7, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_ATA_DATA4__ATA_DATA_4                          IOMUX_PAD(0x6f0, 0x28c, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_ATA_DATA4__ESDHC3_CMD                          IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
index 058a922ca147..98e7fd0b9083 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx50.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
@@ -86,7 +86,7 @@
 #define MX50_PAD_I2C1_SCL__I2C1_SCL     IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \
                                                        MX50_I2C_PAD_CTRL)
 #define MX50_PAD_I2C1_SCL__GPIO_6_18    IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C1_SCL__UART2_TXD    IOMUX_PAD(0x2EC, 0x40, 2, 0x7cc, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_I2C1_SCL__UART2_TXD    IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_I2C1_SDA__I2C1_SDA     IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \
                                                        MX50_I2C_PAD_CTRL)
@@ -96,7 +96,7 @@
 #define MX50_PAD_I2C2_SCL__I2C2_SCL     IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \
                                                        MX50_I2C_PAD_CTRL)
 #define MX50_PAD_I2C2_SCL__GPIO_6_20    IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__UART2_CTS    IOMUX_PAD(0x2F4, 0x48, 2, 0x7c8, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_I2C2_SCL__UART2_CTS    IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_I2C2_SCL__DCDC_OK      IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_I2C2_SDA__I2C2_SDA     IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \
@@ -172,7 +172,7 @@
 #define MX50_PAD_SSI_RXFS__AUD3_RXFS    IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_SSI_RXFS__GPIO_6_4     IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__UART5_TXD    IOMUX_PAD(0x328, 0x7C, 2, 0x7e4, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_SSI_RXFS__UART5_TXD    IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_SSI_RXFS__WEIM_D6      IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL)
 #define MX50_PAD_SSI_RXFS__CSPI_SS2     IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD)
 #define MX50_PAD_SSI_RXFS__FEC_COL      IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH)
@@ -186,25 +186,25 @@
 #define MX50_PAD_SSI_RXC__FEC_RX_CLK    IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL)
 #define MX50_PAD_SSI_RXC__FEC_MDIO      IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL)
-#define MX50_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x330, 0x84, 0, 0x7c4, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART1_TXD__GPIO_6_6    IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART1_RXD__GPIO_6_7    IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x338, 0x8C, 0, 0x7c0, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART1_CTS__GPIO_6_8    IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__UART5_TXD   IOMUX_PAD(0x338, 0x8C, 2, 0x7e4, 2, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_CTS__UART5_TXD   IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART1_CTS__SD4_D4      IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART1_CTS__SD4_CMD     IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART1_RTS__GPIO_6_9    IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_UART1_RTS__UART5_RXD   IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__SD4_D5      IOMUX_PAD(0x33C, 0x90, 4, 0x0, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART1_RTS__SD4_D5      IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__SD4_CLK     IOMUX_PAD(0x33C, 0x90, 5, 0x0, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART1_RTS__SD4_CLK     IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x340, 0x94, 0, 0x7cc, 2, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART2_TXD__GPIO_6_10   IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_UART2_TXD__SD4_D6      IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART2_TXD__SD4_D4      IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL)
@@ -214,7 +214,7 @@
 #define MX50_PAD_UART2_RXD__SD4_D7      IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART2_RXD__SD4_D5      IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x348, 0x9C, 0, 0x7c8, 2, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART2_CTS__GPIO_6_12   IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_UART2_CTS__SD4_CMD     IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART2_CTS__SD4_D6      IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL)
@@ -224,7 +224,7 @@
 #define MX50_PAD_UART2_RTS__SD4_CLK     IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART2_RTS__SD4_D7      IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__UART3_TXD   IOMUX_PAD(0x350, 0xA4, 0, 0x7d4, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART3_TXD__UART3_TXD   IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART3_TXD__GPIO_6_14   IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_UART3_TXD__SD1_D4      IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART3_TXD__SD4_D0      IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL)
@@ -238,9 +238,9 @@
 #define MX50_PAD_UART3_RXD__SD2_CD      IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART3_RXD__WEIM_D13    IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__UART4_TXD   IOMUX_PAD(0x358, 0xAC, 0, 0x7dc, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART4_TXD__UART4_TXD   IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART4_TXD__GPIO_6_16   IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__UART3_CTS   IOMUX_PAD(0x358, 0xAC, 2, 0x7d0, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART4_TXD__UART3_CTS   IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART4_TXD__SD1_D6      IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART4_TXD__SD4_D2      IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART4_TXD__SD2_LCTL    IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL)
@@ -278,7 +278,7 @@
 #define MX50_PAD_ECSPI1_MOSI__GPIO_4_13         IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI1_MOSI__CSPI_SS1          IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD)
 #define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1        IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_MOSI__UART3_CTS         IOMUX_PAD(0x374, 0xC8, 4, 0x7d0, 3, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MOSI__UART3_CTS         IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7        IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI1_MOSI__WEIM_D9           IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL)
@@ -294,7 +294,7 @@
 #define MX50_PAD_ECSPI1_SS0__GPIO_4_15          IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
 #define MX50_PAD_ECSPI1_SS0__CSPI_SS3           IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD)
 #define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3         IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_SS0__UART4_CTS          IOMUX_PAD(0x37C, 0xD0, 4, 0x7d8, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI1_SS0__UART4_CTS          IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9         IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI1_SS0__WEIM_D11           IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL)
@@ -311,17 +311,17 @@
 #define MX50_PAD_ECSPI2_MOSI__GPIO_4_17         IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD         IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1        IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_MOSI__UART5_CTS         IOMUX_PAD(0x384, 0xD8, 4, 0x7e0, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MOSI__UART5_CTS         IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN         IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5        IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MOSI__WEIM_D9           IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO       IOMUX_PAD(0x388, 0xDC, 0, 0x73c, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO       IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MISO__GPIO_4_18         IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
 #define MX50_PAD_ECSPI2_MISO__ELCDIF_RS         IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2        IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_MISO__UART5_TXD         IOMUX_PAD(0x388, 0xDC, 4, 0x7e4, 4, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__UART5_TXD         IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC      IOMUX_PAD(0x388, 0xDC, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC      IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MISO__NANDF_CEN6        IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MISO__WEIM_D10          IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL)
@@ -503,7 +503,7 @@
 #define MX50_PAD_DISP_RD__ELCDIF_EN     IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
 #define MX50_PAD_DISP_RD__WEIM_A25      IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RS__ELCDIF_RS     IOMUX_PAD(0x434, 0x154, 0, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_RS__ELCDIF_RS     IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
 #define MX50_PAD_DISP_RS__GPIO_2_17     IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_DISP_RS__ELCDIF_VSYNC  IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
 #define MX50_PAD_DISP_RS__WEIM_A26      IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
@@ -691,8 +691,8 @@
 #define MX50_PAD_EPDC_D9__EPDC_D9       IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_EPDC_D9__GPIO_3_9      IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__WEIM_D9       IOMUX_PAD(0x570, 0x1D4, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D9__WEIM_D9       IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__ELCDIF_D25    IOMUX_PAD(0x570, 0x1D4, 3, 0x810, 2, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_D9__ELCDIF_D25    IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
 #define MX50_PAD_EPDC_D10__EPDC_D10     IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_EPDC_D10__GPIO_3_10    IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index b6767f90ef14..df6acc066fb1 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -473,7 +473,7 @@
 #define _MX51_PAD_UART2_RXD__UART2_RXD          IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0)
 #define _MX51_PAD_UART2_TXD__FIRI_RXD           IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0)
 #define _MX51_PAD_UART2_TXD__GPIO1_21           IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_TXD__UART2_TXD          IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0)
+#define _MX51_PAD_UART2_TXD__UART2_TXD          IOMUX_PAD(0x62c, 0x23c, 0, 0x0000, 0, 0)
 #define _MX51_PAD_UART3_RXD__CSI1_D0            IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0)
 #define _MX51_PAD_UART3_RXD__GPIO1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0)
 #define _MX51_PAD_UART3_RXD__UART1_DTR          IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0)
@@ -528,7 +528,7 @@
 #define _MX51_PAD_USBH1_DATA1__UART2_RXD        IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0)
 #define _MX51_PAD_USBH1_DATA1__USBH1_DATA1      IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0)
 #define _MX51_PAD_USBH1_DATA2__GPIO1_13         IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA2__UART2_TXD        IOMUX_PAD(0x690, 0x290, 1, 0x09ec, 5, 0)
+#define _MX51_PAD_USBH1_DATA2__UART2_TXD        IOMUX_PAD(0x690, 0x290, 1, 0x0000, 0, 0)
 #define _MX51_PAD_USBH1_DATA2__USBH1_DATA2      IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0)
 #define _MX51_PAD_USBH1_DATA3__GPIO1_14         IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0)
 #define _MX51_PAD_USBH1_DATA3__UART2_RTS        IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0)
@@ -985,11 +985,11 @@
 #define MX51_PAD_NANDF_WE_B__GPIO3_3            (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_WE_B__NANDF_WE_B         (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_WE_B__PATA_DIOW          (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_WE_B__SD3_DATA0          (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WE_B__SD3_DATA0          (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_RE_B__GPIO3_4            (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_RE_B__NANDF_RE_B         (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_RE_B__PATA_DIOR          (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RE_B__SD3_DATA1          (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RE_B__SD3_DATA1          (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_ALE__GPIO3_5             (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_ALE__NANDF_ALE           (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -999,18 +999,18 @@
 #define MX51_PAD_NANDF_WP_B__GPIO3_7            (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_WP_B__NANDF_WP_B         (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_WP_B__PATA_DMACK         (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_WP_B__SD3_DATA2          (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WP_B__SD3_DATA2          (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB0__ECSPI2_SS1          (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB0__GPIO3_8             (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_RB0__NANDF_RB0           (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_RB0__PATA_DMARQ          (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB0__SD3_DATA3           (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__SD3_DATA3           (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB1__CSPI_MOSI           (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB1__ECSPI2_RDY          (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB1__GPIO3_9             (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_RB1__NANDF_RB1           (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_RB1__PATA_IORDY          (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB1__SD4_CMD             (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__SD4_CMD             (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB2__DISP2_WAIT          (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB2__FEC_COL             (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
@@ -1036,41 +1036,41 @@
 #define MX51_PAD_NANDF_CS2__GPIO3_18            (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS2__NANDF_CS2           (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS2__PATA_CS_0           (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS2__SD4_CLK             (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__SD4_CLK             (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
 #define MX51_PAD_NANDF_CS2__USBH3_H1_DP         (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS3__FEC_MDC             (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
 #define MX51_PAD_NANDF_CS3__GPIO3_19            (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS3__NANDF_CS3           (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS3__PATA_CS_1           (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS3__SD4_DAT0            (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__SD4_DAT0            (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_CS3__USBH3_H1_DM         (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS4__FEC_TDATA1          (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
 #define MX51_PAD_NANDF_CS4__GPIO3_20            (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS4__NANDF_CS4           (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS4__PATA_DA_0           (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS4__SD4_DAT1            (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__SD4_DAT1            (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_CS4__USBH3_STP           (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS5__FEC_TDATA2          (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
 #define MX51_PAD_NANDF_CS5__GPIO3_21            (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS5__NANDF_CS5           (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS5__PATA_DA_1           (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS5__SD4_DAT2            (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__SD4_DAT2            (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_CS5__USBH3_DIR           (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS6__CSPI_SS3            (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_CS6__FEC_TDATA3          (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
 #define MX51_PAD_NANDF_CS6__GPIO3_22            (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS6__NANDF_CS6           (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS6__PATA_DA_2           (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS6__SD4_DAT3            (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__SD4_DAT3            (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_CS7__FEC_TX_EN           (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
 #define MX51_PAD_NANDF_CS7__GPIO3_23            (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS7__NANDF_CS7           (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS7__SD3_CLK             (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS7__SD3_CLK             (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
 #define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0      (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
 #define MX51_PAD_NANDF_RDY_INT__GPIO3_24        (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_D15__ECSPI2_MOSI         (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_D15__GPIO3_25            (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_D15__NANDF_D15           (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1479,26 +1479,26 @@
 #define MX51_PAD_SD1_CLK__SD1_CLK               (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
 #define MX51_PAD_SD1_DATA0__AUD5_TXD            (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD1_DATA0__CSPI_MISO           (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_SD1_DATA0__SD1_DATA0           (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_EIM_DA0__EIM_DA0               (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA1__EIM_DA1               (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA2__EIM_DA2               (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA3__EIM_DA3               (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD1_DATA1__AUD5_RXD            (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_DATA1__SD1_DATA1           (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_EIM_DA4__EIM_DA4               (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA5__EIM_DA5               (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA6__EIM_DA6               (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA7__EIM_DA7               (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD1_DATA2__AUD5_TXC            (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_DATA2__SD1_DATA2           (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_EIM_DA10__EIM_DA10             (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA11__EIM_DA11             (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA8__EIM_DA8               (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA9__EIM_DA9               (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD1_DATA3__AUD5_TXFS           (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD1_DATA3__CSPI_SS1            (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_SD1_DATA3__SD1_DATA3           (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_GPIO1_0__CSPI_SS2              (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_GPIO1_0__GPIO1_0               (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_GPIO1_0__SD1_CD                (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
@@ -1517,16 +1517,16 @@
 #define MX51_PAD_SD2_CLK__SD2_CLK               (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
 #define MX51_PAD_SD2_DATA0__CSPI_MISO           (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_SD2_DATA0__SD1_DAT4            (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA0__SD2_DATA0           (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_SD2_DATA1__SD1_DAT5            (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA1__SD2_DATA1           (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_SD2_DATA1__USBH3_H2_DP         (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD2_DATA2__SD1_DAT6            (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA2__SD2_DATA2           (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_SD2_DATA2__USBH3_H2_DM         (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD2_DATA3__CSPI_SS2            (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_SD2_DATA3__SD1_DAT7            (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA3__SD2_DATA3           (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_GPIO1_2__CCM_OUT_2             (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_GPIO1_2__GPIO1_2               (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_GPIO1_2__I2C2_SCL              (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index 68e11d7ab79d..e95d9cb8aeb7 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -21,305 +21,2358 @@
 #include <mach/iomux-v3.h>
-/*
- * various IOMUX alternate output functions (1-7)
- */
-typedef enum iomux_config {
-        IOMUX_CONFIG_ALT0,
-        IOMUX_CONFIG_ALT1,
-        IOMUX_CONFIG_ALT2,
-        IOMUX_CONFIG_ALT3,
-        IOMUX_CONFIG_ALT4,
-        IOMUX_CONFIG_ALT5,
-        IOMUX_CONFIG_ALT6,
-        IOMUX_CONFIG_ALT7,
-        IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
-} iomux_pin_cfg_t;
 /* These 2 defines are for pins that may not have a mux register, but could
 * have a pad setting register, and vice-versa. */
-#define NON_MUX_I       0x00
 #define NON_PAD_I       0x00
 #define MX53_UART_PAD_CTRL              (PAD_CTL_PKE | PAD_CTL_PUE |    \
                PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-/* UART1 */
+#define MX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-#define MX53_PAD_CSI0_D10__UART1_TXD    IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL)
+                                PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
-#define MX53_PAD_CSI0_D11__UART1_RXD    IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
+                                PAD_CTL_SRE_FAST)
-#define MX53_PAD_ATA_DIOW__UART1_TXD    IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_DMACK__UART1_RXD   IOMUX_PAD(0x5F4, 0x274, 3, 0x880, 3, MX53_UART_PAD_CTRL)
-/* UART2 */
-#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD       IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_DMARQ__UART2_TXD   IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_DIOR__UART2_RTS    IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_INTRQ__UART2_CTS   IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, MX53_UART_PAD_CTRL)
-/* UART3 */
+#define _MX53_PAD_GPIO_19__KPP_COL_5            IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0)
-#define MX53_PAD_ATA_CS_0__UART3_TXD    IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL)
+#define _MX53_PAD_GPIO_19__GPIO4_5              IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0)
-#define MX53_PAD_ATA_CS_1__UART3_RXD    IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
+#define _MX53_PAD_GPIO_19__CCM_CLKO             IOMUX_PAD(0x348, 0x20, 2, 0x0, 0, 0)
-#define MX53_PAD_ATA_DA_1__UART3_CTS    IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, MX53_UART_PAD_CTRL)
+#define _MX53_PAD_GPIO_19__SPDIF_OUT1   IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, 0)
-#define MX53_PAD_ATA_DA_2__UART3_RTS    IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
+#define _MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x20, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_19__ECSPI1_RDY   IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_19__FEC_TDATA_3  IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL0__KPP_COL_0   IOMUX_PAD(0x34C, 0x24, o, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL0__GPIO4_6             IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC     IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0)
+#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX       IOMUX_PAD(0x34C, 0x24, 4, 0x890, 0, 0)
+#define _MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0)
+#define _MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL0__SRC_ANY_PU_RST      IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW0__KPP_ROW_0   IOMUX_PAD(0x350, 0x28, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW0__GPIO4_7             IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD     IOMUX_PAD(0x350, 0x28, 2, 0x74C, 0, 0)
+#define _MX53_PAD_KEY_ROW0__UART4_RXD_MUX       IOMUX_PAD(0x350, 0x28, 4, 0x890, 1, 0)
+#define _MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x28, 5, 0x7A4, 0, 0)
+#define _MX53_PAD_KEY_ROW0__FEC_TX_ER   IOMUX_PAD(0x350, 0x28, 6, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL1__KPP_COL_1   IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL1__GPIO4_8             IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS    IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0)
+#define _MX53_PAD_KEY_COL1__UART5_TXD_MUX       IOMUX_PAD(0x354, 0x2C, 4, 0x898, 0, 0)
+#define _MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0)
+#define _MX53_PAD_KEY_COL1__FEC_RX_CLK  IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0)
+#define _MX53_PAD_KEY_COL1__USBPHY1_TXREADY     IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW1__KPP_ROW_1   IOMUX_PAD(0x358, 0x30, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW1__GPIO4_9             IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD     IOMUX_PAD(0x358, 0x30, 2, 0x748, 0, 0)
+#define _MX53_PAD_KEY_ROW1__UART5_RXD_MUX       IOMUX_PAD(0x358, 0x30, 4, 0x898, 1, 0)
+#define _MX53_PAD_KEY_ROW1__ECSPI1_SS0  IOMUX_PAD(0x358, 0x30, 5, 0x7A8, 0, 0)
+#define _MX53_PAD_KEY_ROW1__FEC_COL             IOMUX_PAD(0x358, 0x30, 6, 0x800, 0, 0)
+#define _MX53_PAD_KEY_ROW1__USBPHY1_RXVALID     IOMUX_PAD(0x358, 0x30, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL2__KPP_COL_2   IOMUX_PAD(0x35C, 0x34, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL2__GPIO4_10            IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL2__CAN1_TXCAN  IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL2__FEC_MDIO            IOMUX_PAD(0x35C, 0x34, 4, 0x804, 0, 0)
+#define _MX53_PAD_KEY_COL2__ECSPI1_SS1  IOMUX_PAD(0x35C, 0x34, 5, 0x7AC, 0, 0)
+#define _MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x34, 6, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE    IOMUX_PAD(0x35C, 0x34, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__KPP_ROW_2   IOMUX_PAD(0x360, 0x38, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__GPIO4_11    IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__CAN1_RXCAN  IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, 0)
+#define _MX53_PAD_KEY_ROW2__FEC_MDC             IOMUX_PAD(0x360, 0x38, 4, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__ECSPI1_SS2  IOMUX_PAD(0x360, 0x38, 5, 0x7B0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x38, 6, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__USBPHY1_RXERROR     IOMUX_PAD(0x360, 0x38, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL3__KPP_COL_3   IOMUX_PAD(0x364, 0x3C, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL3__GPIO4_12            IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL3__USBOH3_H2_DP        IOMUX_PAD(0x364, 0x3C, 2, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL3__SPDIF_IN1   IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, 0)
+#define _MX53_PAD_KEY_COL3__I2C2_SCL            IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, 0)
+#define _MX53_PAD_KEY_COL3__ECSPI1_SS3  IOMUX_PAD(0x364, 0x3C, 5, 0x7B4, 0, 0)
+#define _MX53_PAD_KEY_COL3__FEC_CRS             IOMUX_PAD(0x364, 0x3C, 6, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK    IOMUX_PAD(0x364, 0x3C, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW3__KPP_ROW_3   IOMUX_PAD(0x368, 0x40, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW3__GPIO4_13    IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW3__USBOH3_H2_DM        IOMUX_PAD(0x368, 0x40, 2, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK    IOMUX_PAD(0x368, 0x40, 3, 0x768, 0, 0)
+#define _MX53_PAD_KEY_ROW3__I2C2_SDA    IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, 0)
+#define _MX53_PAD_KEY_ROW3__OSC32K_32K_OUT      IOMUX_PAD(0x368, 0x40, 5, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW3__CCM_PLL4_BYP        IOMUX_PAD(0x368, 0x40, 6, 0x77C, 0, 0)
+#define _MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x40, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL4__KPP_COL_4   IOMUX_PAD(0x36C, 0x44, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL4__GPIO4_14            IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL4__CAN2_TXCAN  IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL4__IPU_SISG_4  IOMUX_PAD(0x36C, 0x44, 3, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL4__UART5_RTS   IOMUX_PAD(0x36C, 0x44, 4, 0x894, 0, 0)
+#define _MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC    IOMUX_PAD(0x36C, 0x44, 5, 0x89C, 0, 0)
+#define _MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x44, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW4__KPP_ROW_4   IOMUX_PAD(0x370, 0x48, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW4__GPIO4_15    IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW4__CAN2_RXCAN  IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0)
+#define _MX53_PAD_KEY_ROW4__IPU_SISG_5  IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW4__UART5_CTS   IOMUX_PAD(0x370, 0x48, 4, 0x894, 1, 0)
+#define _MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR   IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID   IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK        IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__GPIO4_16                IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR        IOMUX_PAD(0x378, 0x4C, 2, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x4C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x4C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID  IOMUX_PAD(0x378, 0x4C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__IPU_DI0_PIN15              IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__GPIO4_17           IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC    IOMUX_PAD(0x37C, 0x50, 2, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1    IOMUX_PAD(0x37C, 0x50, 5, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1    IOMUX_PAD(0x37C, 0x50, 6, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__USBPHY1_BVALID             IOMUX_PAD(0x37C, 0x50, 7, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__GPIO4_18                    IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD     IOMUX_PAD(0x380, 0x54, 2, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2     IOMUX_PAD(0x380, 0x54, 5, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2             IOMUX_PAD(0x380, 0x54, 6, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION  IOMUX_PAD(0x380, 0x54, 7, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__GPIO4_19                    IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS    IOMUX_PAD(0x384, 0x58, 2, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3     IOMUX_PAD(0x384, 0x58, 5, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3             IOMUX_PAD(0x384, 0x58, 6, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__USBPHY1_IDDIG               IOMUX_PAD(0x384, 0x58, 7, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                IOMUX_PAD(0x388, 0x5C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__GPIO4_20                    IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD     IOMUX_PAD(0x388, 0x5C, 2, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__ESDHC1_WP           IOMUX_PAD(0x388, 0x5C, 3, 0x7FC, 0, 0)
+#define _MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD    IOMUX_PAD(0x388, 0x5C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4             IOMUX_PAD(0x388, 0x5C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT      IOMUX_PAD(0x388, 0x5C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0   IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__GPIO4_21          IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__CSPI_SCLK         IOMUX_PAD(0x38C, 0x60, 2, 0x780, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0       IOMUX_PAD(0x38C, 0x60, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN       IOMUX_PAD(0x38C, 0x60, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5   IOMUX_PAD(0x38C, 0x60, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY   IOMUX_PAD(0x38C, 0x60, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1   IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__GPIO4_22          IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__CSPI_MOSI         IOMUX_PAD(0x390, 0x64, 2, 0x788, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1       IOMUX_PAD(0x390, 0x64, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL      IOMUX_PAD(0x390, 0x64, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6   IOMUX_PAD(0x390, 0x64, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID   IOMUX_PAD(0x390, 0x64, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2   IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__GPIO4_23          IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__CSPI_MISO         IOMUX_PAD(0x394, 0x68, 2, 0x784, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2       IOMUX_PAD(0x394, 0x68, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE   IOMUX_PAD(0x394, 0x68, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7   IOMUX_PAD(0x394, 0x68, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE  IOMUX_PAD(0x394, 0x68, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3   IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__GPIO4_24          IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__CSPI_SS0          IOMUX_PAD(0x398, 0x6C, 2, 0x78C, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3       IOMUX_PAD(0x398, 0x6C, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR      IOMUX_PAD(0x398, 0x6C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8   IOMUX_PAD(0x398, 0x6C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR   IOMUX_PAD(0x398, 0x6C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4   IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__GPIO4_25          IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__CSPI_SS1          IOMUX_PAD(0x39C, 0x70, 2, 0x790, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4       IOMUX_PAD(0x39C, 0x70, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB        IOMUX_PAD(0x39C, 0x70, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9   IOMUX_PAD(0x39C, 0x70, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK  IOMUX_PAD(0x39C, 0x70, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5   IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__GPIO4_26          IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__CSPI_SS2          IOMUX_PAD(0x3A0, 0x74, 2, 0x794, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5       IOMUX_PAD(0x3A0, 0x74, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS  IOMUX_PAD(0x3A0, 0x74, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10  IOMUX_PAD(0x3A0, 0x74, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0       IOMUX_PAD(0x3A0, 0x74, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6   IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__GPIO4_27          IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__CSPI_SS3          IOMUX_PAD(0x3A4, 0x78, 2, 0x798, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6       IOMUX_PAD(0x3A4, 0x78, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x78, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11  IOMUX_PAD(0x3A4, 0x78, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1       IOMUX_PAD(0x3A4, 0x78, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7   IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__GPIO4_28          IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__CSPI_RDY          IOMUX_PAD(0x3A8, 0x7C, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7       IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0        IOMUX_PAD(0x3A8, 0x7C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12  IOMUX_PAD(0x3A8, 0x7C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x7C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8   IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__GPIO4_29          IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__PWM1_PWMO         IOMUX_PAD(0x3AC, 0x80, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B      IOMUX_PAD(0x3AC, 0x80, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1        IOMUX_PAD(0x3AC, 0x80, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13  IOMUX_PAD(0x3AC, 0x80, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__USBPHY2_AVALID    IOMUX_PAD(0x3AC, 0x80, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9   IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__GPIO4_30          IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__PWM2_PWMO         IOMUX_PAD(0x3B0, 0x84, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B      IOMUX_PAD(0x3B0, 0x84, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2                IOMUX_PAD(0x3B0, 0x84, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14  IOMUX_PAD(0x3B0, 0x84, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x84, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__GPIO4_31         IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3       IOMUX_PAD(0x3B4, 0x88, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x88, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1        IOMUX_PAD(0x3B4, 0x88, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__GPIO5_5          IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4       IOMUX_PAD(0x3B8, 0x8C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x8C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2        IOMUX_PAD(0x3B8, 0x8C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__GPIO5_6          IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5       IOMUX_PAD(0x3BC, 0x90, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x90, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3        IOMUX_PAD(0x3BC, 0x90, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__GPIO5_7          IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x94, 3, 0x754, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0       IOMUX_PAD(0x3C0, 0x94, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x94, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4        IOMUX_PAD(0x3C0, 0x94, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__GPIO5_8          IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC  IOMUX_PAD(0x3C4, 0x98, 3, 0x750, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1       IOMUX_PAD(0x3C4, 0x98, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x98, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5        IOMUX_PAD(0x3C4, 0x98, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__GPIO5_9          IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__ECSPI1_SS1               IOMUX_PAD(0x3C8, 0x9C, 2, 0x7AC, 1, 0)
+#define _MX53_PAD_DISP0_DAT15__ECSPI2_SS1               IOMUX_PAD(0x3C8, 0x9C, 3, 0x7C8, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2       IOMUX_PAD(0x3C8, 0x9C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x9C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6        IOMUX_PAD(0x3C8, 0x9C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__GPIO5_10         IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__ECSPI2_MOSI              IOMUX_PAD(0x3CC, 0xA0, 2, 0x7C0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC  IOMUX_PAD(0x3CC, 0xA0, 3, 0x758, 1, 0)
+#define _MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0xA0, 4, 0x868, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3       IOMUX_PAD(0x3CC, 0xA0, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0xA0, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7        IOMUX_PAD(0x3CC, 0xA0, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__GPIO5_11         IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__ECSPI2_MISO              IOMUX_PAD(0x3D0, 0xA4, 2, 0x7BC, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD  IOMUX_PAD(0x3D0, 0xA4, 3, 0x74C, 1, 0)
+#define _MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0xA4, 4, 0x86C, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4       IOMUX_PAD(0x3D0, 0xA4, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0xA4, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__GPIO5_12         IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__ECSPI2_SS0               IOMUX_PAD(0x3D4, 0xA8, 2, 0x7C4, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0xA8, 3, 0x75C, 1, 0)
+#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0xA8, 4, 0x73C, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5       IOMUX_PAD(0x3D4, 0xA8, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0xA8, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2    IOMUX_PAD(0x3D4, 0xA8, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__GPIO5_13         IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__ECSPI2_SCLK              IOMUX_PAD(0x3D8, 0xAC, 2, 0x7B8, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD  IOMUX_PAD(0x3D8, 0xAC, 3, 0x748, 1, 0)
+#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC  IOMUX_PAD(0x3D8, 0xAC, 4, 0x738, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6       IOMUX_PAD(0x3D8, 0xAC, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0xAC, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3    IOMUX_PAD(0x3D8, 0xAC, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__GPIO5_14         IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__ECSPI1_SCLK              IOMUX_PAD(0x3DC, 0xB0, 2, 0x79C, 1, 0)
+#define _MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC  IOMUX_PAD(0x3DC, 0xB0, 3, 0x740, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7       IOMUX_PAD(0x3DC, 0xB0, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0xB0, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__SATA_PHY_TDI             IOMUX_PAD(0x3DC, 0xB0, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__GPIO5_15         IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__ECSPI1_MOSI              IOMUX_PAD(0x3E0, 0xB4, 2, 0x7A4, 1, 0)
+#define _MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD  IOMUX_PAD(0x3E0, 0xB4, 3, 0x734, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0  IOMUX_PAD(0x3E0, 0xB4, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0xB4, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__SATA_PHY_TDO     IOMUX_PAD(0x3E0, 0xB4, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__GPIO5_16         IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__ECSPI1_MISO              IOMUX_PAD(0x3E4, 0xB8, 2, 0x7A0, 1, 0)
+#define _MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, 0x744, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1  IOMUX_PAD(0x3E4, 0xB8, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0xB8, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__SATA_PHY_TCK     IOMUX_PAD(0x3E4, 0xB8, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__GPIO5_17         IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__ECSPI1_SS0               IOMUX_PAD(0x3E8, 0xBC, 2, 0x7A8, 1, 0)
+#define _MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD  IOMUX_PAD(0x3E8, 0xBC, 3, 0x730, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2  IOMUX_PAD(0x3E8, 0xBC, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0xBC, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__SATA_PHY_TMS     IOMUX_PAD(0x3E8, 0xBC, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK  IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_PIXCLK__GPIO5_18         IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0  IOMUX_PAD(0x3EC, 0xC0, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0xC0, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC             IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__GPIO5_19           IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK              IOMUX_PAD(0x3F0, 0xC4, 2, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1    IOMUX_PAD(0x3F0, 0xC4, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30   IOMUX_PAD(0x3F0, 0xC4, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__TPIU_TRCTL         IOMUX_PAD(0x3F0, 0xC4, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN        IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DATA_EN__GPIO5_20                IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0xC8, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31        IOMUX_PAD(0x3F4, 0xC8, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK              IOMUX_PAD(0x3F4, 0xC8, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC    IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_VSYNC__GPIO5_21          IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3   IOMUX_PAD(0x3F8, 0xCC, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32  IOMUX_PAD(0x3F8, 0xCC, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0              IOMUX_PAD(0x3F8, 0xCC, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4               IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__GPIO5_22           IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__KPP_COL_5          IOMUX_PAD(0x3FC, 0xD0, 2, 0x840, 1, 0)
+#define _MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                IOMUX_PAD(0x3FC, 0xD0, 3, 0x79C, 2, 0)
+#define _MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP   IOMUX_PAD(0x3FC, 0xD0, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC    IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33   IOMUX_PAD(0x3FC, 0xD0, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__TPIU_TRACE_1               IOMUX_PAD(0x3FC, 0xD0, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5               IOMUX_PAD(0x400, 0xD4, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__GPIO5_23           IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__KPP_ROW_5          IOMUX_PAD(0x400, 0xD4, 2, 0x84C, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                IOMUX_PAD(0x400, 0xD4, 3, 0x7A4, 2, 0)
+#define _MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT   IOMUX_PAD(0x400, 0xD4, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD    IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34   IOMUX_PAD(0x400, 0xD4, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__TPIU_TRACE_2               IOMUX_PAD(0x400, 0xD4, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6               IOMUX_PAD(0x404, 0xD8, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__GPIO5_24           IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__KPP_COL_6          IOMUX_PAD(0x404, 0xD8, 2, 0x844, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__ECSPI1_MISO                IOMUX_PAD(0x404, 0xD8, 3, 0x7A0, 2, 0)
+#define _MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK   IOMUX_PAD(0x404, 0xD8, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS   IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35   IOMUX_PAD(0x404, 0xD8, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__TPIU_TRACE_3               IOMUX_PAD(0x404, 0xD8, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7               IOMUX_PAD(0x408, 0xDC, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__GPIO5_25           IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__KPP_ROW_6          IOMUX_PAD(0x408, 0xDC, 2, 0x850, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__ECSPI1_SS0         IOMUX_PAD(0x408, 0xDC, 3, 0x7A8, 2, 0)
+#define _MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR   IOMUX_PAD(0x408, 0xDC, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD    IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36   IOMUX_PAD(0x408, 0xDC, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__TPIU_TRACE_4               IOMUX_PAD(0x408, 0xDC, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8               IOMUX_PAD(0x40C, 0xE0, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__GPIO5_26           IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__KPP_COL_7          IOMUX_PAD(0x40C, 0xE0, 2, 0x848, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                IOMUX_PAD(0x40C, 0xE0, 3, 0x7B8, 1, 0)
+#define _MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC    IOMUX_PAD(0x40C, 0xE0, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__I2C1_SDA           IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37   IOMUX_PAD(0x40C, 0xE0, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__TPIU_TRACE_5               IOMUX_PAD(0x40C, 0xE0, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9               IOMUX_PAD(0x410, 0xE4, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__GPIO5_27           IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__KPP_ROW_7          IOMUX_PAD(0x410, 0xE4, 2, 0x854, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                IOMUX_PAD(0x410, 0xE4, 3, 0x7C0, 1, 0)
+#define _MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR   IOMUX_PAD(0x410, 0xE4, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__I2C1_SCL           IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38   IOMUX_PAD(0x410, 0xE4, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__TPIU_TRACE_6               IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10             IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__GPIO5_28          IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX     IOMUX_PAD(0x414, 0xE8, 2, 0x878, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__ECSPI2_MISO               IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0)
+#define _MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC   IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4   IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39  IOMUX_PAD(0x414, 0xE8, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__TPIU_TRACE_7              IOMUX_PAD(0x414, 0xE8, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11             IOMUX_PAD(0x418, 0xEC, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__GPIO5_29          IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__UART1_RXD_MUX     IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, 0)
+#define _MX53_PAD_CSI0_DAT11__ECSPI2_SS0                IOMUX_PAD(0x418, 0xEC, 3, 0x7C4, 1, 0)
+#define _MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS  IOMUX_PAD(0x418, 0xEC, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5   IOMUX_PAD(0x418, 0xEC, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40  IOMUX_PAD(0x418, 0xEC, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__TPIU_TRACE_8              IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12             IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__GPIO5_30          IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX     IOMUX_PAD(0x41C, 0xF0, 2, 0x890, 2, 0)
+#define _MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0       IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6   IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41  IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__TPIU_TRACE_9              IOMUX_PAD(0x41C, 0xF0, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13             IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__GPIO5_31          IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__UART4_RXD_MUX     IOMUX_PAD(0x420, 0xF4, 2, 0x890, 3, 0)
+#define _MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1       IOMUX_PAD(0x420, 0xF4, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7   IOMUX_PAD(0x420, 0xF4, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42  IOMUX_PAD(0x420, 0xF4, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__TPIU_TRACE_10             IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14             IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__GPIO6_0           IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX     IOMUX_PAD(0x424, 0xF8, 2, 0x898, 2, 0)
+#define _MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2       IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8   IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43  IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__TPIU_TRACE_11             IOMUX_PAD(0x424, 0xF8, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15             IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__GPIO6_1           IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__UART5_RXD_MUX     IOMUX_PAD(0x428, 0xFC, 2, 0x898, 3, 0)
+#define _MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3       IOMUX_PAD(0x428, 0xFC, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9   IOMUX_PAD(0x428, 0xFC, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44  IOMUX_PAD(0x428, 0xFC, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__TPIU_TRACE_12             IOMUX_PAD(0x428, 0xFC, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16             IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__GPIO6_2           IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__UART4_RTS         IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4       IOMUX_PAD(0x42C, 0x100, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10  IOMUX_PAD(0x42C, 0x100, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45  IOMUX_PAD(0x42C, 0x100, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__TPIU_TRACE_13             IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17             IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__GPIO6_3           IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__UART4_CTS         IOMUX_PAD(0x430, 0x104, 2, 0x88C, 1, 0)
+#define _MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5       IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11  IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46  IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__TPIU_TRACE_14             IOMUX_PAD(0x430, 0x104, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18             IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__GPIO6_4           IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__UART5_RTS         IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, 0)
+#define _MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6       IOMUX_PAD(0x434, 0x108, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12  IOMUX_PAD(0x434, 0x108, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47  IOMUX_PAD(0x434, 0x108, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__TPIU_TRACE_15             IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19             IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__GPIO6_5           IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__UART5_CTS         IOMUX_PAD(0x438, 0x10C, 2, 0x894, 3, 0)
+#define _MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7       IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13  IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48  IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK    IOMUX_PAD(0x438, 0x10C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__EMI_WEIM_A_25                IOMUX_PAD(0x458, 0x110, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__GPIO5_2                      IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__ECSPI2_RDY           IOMUX_PAD(0x458, 0x110, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__IPU_DI1_PIN12                IOMUX_PAD(0x458, 0x110, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__CSPI_SS1                     IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, 0)
+#define _MX53_PAD_EIM_A25__IPU_DI0_D1_CS                IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__USBPHY1_BISTOK               IOMUX_PAD(0x458, 0x110, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                IOMUX_PAD(0x45C, 0x114, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB2__GPIO2_30                     IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK              IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, 0)
+#define _MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS             IOMUX_PAD(0x45C, 0x114, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB2__ECSPI1_SS0           IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, 0)
+#define _MX53_PAD_EIM_EB2__I2C2_SCL                     IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, 0)
+#define _MX53_PAD_EIM_D16__EMI_WEIM_D_16                IOMUX_PAD(0x460, 0x118, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D16__GPIO3_16                     IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D16__IPU_DI0_PIN5         IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK   IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D16__ECSPI1_SCLK          IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0)
+#define _MX53_PAD_EIM_D16__I2C2_SDA                     IOMUX_PAD(0x460, 0x118, 5, 0x820, 1, 0)
+#define _MX53_PAD_EIM_D17__EMI_WEIM_D_17                IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D17__GPIO3_17                     IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D17__IPU_DI0_PIN6         IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN   IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0)
+#define _MX53_PAD_EIM_D17__ECSPI1_MISO          IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0)
+#define _MX53_PAD_EIM_D17__I2C3_SCL                     IOMUX_PAD(0x464, 0x11C, 5, 0x824, 0, 0)
+#define _MX53_PAD_EIM_D18__EMI_WEIM_D_18                IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D18__GPIO3_18                     IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D18__IPU_DI0_PIN7         IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO   IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0)
+#define _MX53_PAD_EIM_D18__ECSPI1_MOSI          IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0)
+#define _MX53_PAD_EIM_D18__I2C3_SDA                     IOMUX_PAD(0x468, 0x120, 5, 0x828, 0, 0)
+#define _MX53_PAD_EIM_D18__IPU_DI1_D0_CS                IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__EMI_WEIM_D_19                IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__GPIO3_19                     IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__IPU_DI0_PIN8         IOMUX_PAD(0x46C, 0x124, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS    IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__ECSPI1_SS1           IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0)
+#define _MX53_PAD_EIM_D19__EPIT1_EPITO          IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__UART1_CTS                    IOMUX_PAD(0x46C, 0x124, 6, 0x874, 0, 0)
+#define _MX53_PAD_EIM_D19__USBOH3_USBH2_OC              IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0)
+#define _MX53_PAD_EIM_D20__EMI_WEIM_D_20                IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D20__GPIO3_20                     IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D20__IPU_DI0_PIN16                IOMUX_PAD(0x470, 0x128, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D20__IPU_SER_DISP0_CS             IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D20__CSPI_SS0                     IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, 0)
+#define _MX53_PAD_EIM_D20__EPIT2_EPITO          IOMUX_PAD(0x470, 0x128, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D20__UART1_RTS                    IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, 0)
+#define _MX53_PAD_EIM_D20__USBOH3_USBH2_PWR     IOMUX_PAD(0x470, 0x128, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D21__EMI_WEIM_D_21                IOMUX_PAD(0x474, 0x12C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D21__GPIO3_21                     IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D21__IPU_DI0_PIN17                IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK   IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D21__CSPI_SCLK                    IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0)
+#define _MX53_PAD_EIM_D21__I2C1_SCL                     IOMUX_PAD(0x474, 0x12C, 5, 0x814, 1, 0)
+#define _MX53_PAD_EIM_D21__USBOH3_USBOTG_OC     IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0)
+#define _MX53_PAD_EIM_D22__EMI_WEIM_D_22                IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D22__GPIO3_22                     IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D22__IPU_DI0_PIN1         IOMUX_PAD(0x478, 0x130, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN   IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, 0)
+#define _MX53_PAD_EIM_D22__CSPI_MISO                    IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, 0)
+#define _MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR    IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__EMI_WEIM_D_23                IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__GPIO3_23                     IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__UART3_CTS                    IOMUX_PAD(0x47C, 0x134, 2, 0x884, 0, 0)
+#define _MX53_PAD_EIM_D23__UART1_DCD            IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__IPU_DI0_D0_CS                IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__IPU_DI1_PIN2         IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN             IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, 0)
+#define _MX53_PAD_EIM_D23__IPU_DI1_PIN14                IOMUX_PAD(0x47C, 0x134, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                IOMUX_PAD(0x480, 0x138, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB3__GPIO2_31                     IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB3__UART3_RTS                    IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, 0)
+#define _MX53_PAD_EIM_EB3__UART1_RI                     IOMUX_PAD(0x480, 0x138, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN3         IOMUX_PAD(0x480, 0x138, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC               IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, 0)
+#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN16                IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D24__EMI_WEIM_D_24                IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D24__GPIO3_24                     IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D24__UART3_TXD_MUX                IOMUX_PAD(0x484, 0x13C, 2, 0x888, 0, 0)
+#define _MX53_PAD_EIM_D24__ECSPI1_SS2           IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0)
+#define _MX53_PAD_EIM_D24__CSPI_SS2                     IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0)
+#define _MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS     IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0)
+#define _MX53_PAD_EIM_D24__ECSPI2_SS2           IOMUX_PAD(0x484, 0x13C, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D24__UART1_DTR            IOMUX_PAD(0x484, 0x13C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D25__EMI_WEIM_D_25                IOMUX_PAD(0x488, 0x140, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D25__GPIO3_25                     IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D25__UART3_RXD_MUX                IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, 0)
+#define _MX53_PAD_EIM_D25__ECSPI1_SS3           IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, 0)
+#define _MX53_PAD_EIM_D25__CSPI_SS3                     IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, 0)
+#define _MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC              IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, 0)
+#define _MX53_PAD_EIM_D25__ECSPI2_SS3           IOMUX_PAD(0x488, 0x140, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D25__UART1_DSR            IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__EMI_WEIM_D_26                IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__GPIO3_26                     IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__UART2_TXD_MUX                IOMUX_PAD(0x48C, 0x144, 2, 0x880, 0, 0)
+#define _MX53_PAD_EIM_D26__FIRI_RXD                     IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0)
+#define _MX53_PAD_EIM_D26__IPU_CSI0_D_1         IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__IPU_DI1_PIN11                IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__IPU_SISG_2           IOMUX_PAD(0x48C, 0x144, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__IPU_DISP1_DAT_22             IOMUX_PAD(0x48C, 0x144, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__EMI_WEIM_D_27                IOMUX_PAD(0x490, 0x148, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__GPIO3_27                     IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__UART2_RXD_MUX                IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, 0)
+#define _MX53_PAD_EIM_D27__FIRI_TXD                     IOMUX_PAD(0x490, 0x148, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__IPU_CSI0_D_0         IOMUX_PAD(0x490, 0x148, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__IPU_DI1_PIN13                IOMUX_PAD(0x490, 0x148, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__IPU_SISG_3           IOMUX_PAD(0x490, 0x148, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__IPU_DISP1_DAT_23             IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D28__EMI_WEIM_D_28                IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D28__GPIO3_28                     IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D28__UART2_CTS                    IOMUX_PAD(0x494, 0x14C, 2, 0x87C, 0, 0)
+#define _MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO   IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0)
+#define _MX53_PAD_EIM_D28__CSPI_MOSI                    IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0)
+#define _MX53_PAD_EIM_D28__I2C1_SDA                     IOMUX_PAD(0x494, 0x14C, 5, 0x818, 1, 0)
+#define _MX53_PAD_EIM_D28__IPU_EXT_TRIG         IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D28__IPU_DI0_PIN13                IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D29__EMI_WEIM_D_29                IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D29__GPIO3_29                     IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D29__UART2_RTS                    IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, 0)
+#define _MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS    IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D29__CSPI_SS0                     IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, 0)
+#define _MX53_PAD_EIM_D29__IPU_DI1_PIN15                IOMUX_PAD(0x498, 0x150, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D29__IPU_CSI1_VSYNC               IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, 0)
+#define _MX53_PAD_EIM_D29__IPU_DI0_PIN14                IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__EMI_WEIM_D_30                IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__GPIO3_30                     IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__UART3_CTS                    IOMUX_PAD(0x49C, 0x154, 2, 0x884, 2, 0)
+#define _MX53_PAD_EIM_D30__IPU_CSI0_D_3         IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__IPU_DI0_PIN11                IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__IPU_DISP1_DAT_21             IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__USBOH3_USBH1_OC              IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, 0)
+#define _MX53_PAD_EIM_D30__USBOH3_USBH2_OC              IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, 0)
+#define _MX53_PAD_EIM_D31__EMI_WEIM_D_31                IOMUX_PAD(0x4A0, 0x158, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__GPIO3_31                     IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__UART3_RTS                    IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, 0)
+#define _MX53_PAD_EIM_D31__IPU_CSI0_D_2         IOMUX_PAD(0x4A0, 0x158, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__IPU_DI0_PIN12                IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__IPU_DISP1_DAT_20             IOMUX_PAD(0x4A0, 0x158, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__USBOH3_USBH1_PWR     IOMUX_PAD(0x4A0, 0x158, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__USBOH3_USBH2_PWR     IOMUX_PAD(0x4A0, 0x158, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__EMI_WEIM_A_24                IOMUX_PAD(0x4A8, 0x15C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__GPIO5_4                      IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__IPU_DISP1_DAT_19             IOMUX_PAD(0x4A8, 0x15C, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__IPU_CSI1_D_19                IOMUX_PAD(0x4A8, 0x15C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__IPU_SISG_2           IOMUX_PAD(0x4A8, 0x15C, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__USBPHY2_BVALID               IOMUX_PAD(0x4A8, 0x15C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__EMI_WEIM_A_23                IOMUX_PAD(0x4AC, 0x160, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__GPIO6_6                      IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__IPU_DISP1_DAT_18             IOMUX_PAD(0x4AC, 0x160, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__IPU_CSI1_D_18                IOMUX_PAD(0x4AC, 0x160, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__IPU_SISG_3           IOMUX_PAD(0x4AC, 0x160, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__USBPHY2_ENDSESSION   IOMUX_PAD(0x4AC, 0x160, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A22__EMI_WEIM_A_22                IOMUX_PAD(0x4B0, 0x164, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A22__GPIO2_16                     IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A22__IPU_DISP1_DAT_17             IOMUX_PAD(0x4B0, 0x164, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A22__IPU_CSI1_D_17                IOMUX_PAD(0x4B0, 0x164, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A22__SRC_BT_CFG1_7                IOMUX_PAD(0x4B0, 0x164, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A21__EMI_WEIM_A_21                IOMUX_PAD(0x4B4, 0x168, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A21__GPIO2_17                     IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A21__IPU_DISP1_DAT_16             IOMUX_PAD(0x4B4, 0x168, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A21__IPU_CSI1_D_16                IOMUX_PAD(0x4B4, 0x168, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A21__SRC_BT_CFG1_6                IOMUX_PAD(0x4B4, 0x168, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A20__EMI_WEIM_A_20                IOMUX_PAD(0x4B8, 0x16C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A20__GPIO2_18                     IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A20__IPU_DISP1_DAT_15             IOMUX_PAD(0x4B8, 0x16C, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A20__IPU_CSI1_D_15                IOMUX_PAD(0x4B8, 0x16C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A20__SRC_BT_CFG1_5                IOMUX_PAD(0x4B8, 0x16C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A19__EMI_WEIM_A_19                IOMUX_PAD(0x4BC, 0x170, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A19__GPIO2_19                     IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A19__IPU_DISP1_DAT_14             IOMUX_PAD(0x4BC, 0x170, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A19__IPU_CSI1_D_14                IOMUX_PAD(0x4BC, 0x170, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A19__SRC_BT_CFG1_4                IOMUX_PAD(0x4BC, 0x170, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A18__EMI_WEIM_A_18                IOMUX_PAD(0x4C0, 0x174, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A18__GPIO2_20                     IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A18__IPU_DISP1_DAT_13             IOMUX_PAD(0x4C0, 0x174, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A18__IPU_CSI1_D_13                IOMUX_PAD(0x4C0, 0x174, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A18__SRC_BT_CFG1_3                IOMUX_PAD(0x4C0, 0x174, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A17__EMI_WEIM_A_17                IOMUX_PAD(0x4C4, 0x178, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A17__GPIO2_21                     IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A17__IPU_DISP1_DAT_12             IOMUX_PAD(0x4C4, 0x178, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A17__IPU_CSI1_D_12                IOMUX_PAD(0x4C4, 0x178, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A17__SRC_BT_CFG1_2                IOMUX_PAD(0x4C4, 0x178, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A16__EMI_WEIM_A_16                IOMUX_PAD(0x4C8, 0x17C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A16__GPIO2_22                     IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK             IOMUX_PAD(0x4C8, 0x17C, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK              IOMUX_PAD(0x4C8, 0x17C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A16__SRC_BT_CFG1_1                IOMUX_PAD(0x4C8, 0x17C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                IOMUX_PAD(0x4CC, 0x180, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS0__GPIO2_23                     IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS0__ECSPI2_SCLK          IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, 0)
+#define _MX53_PAD_EIM_CS0__IPU_DI1_PIN5         IOMUX_PAD(0x4CC, 0x180, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                IOMUX_PAD(0x4D0, 0x184, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS1__GPIO2_24                     IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS1__ECSPI2_MOSI          IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, 0)
+#define _MX53_PAD_EIM_CS1__IPU_DI1_PIN6         IOMUX_PAD(0x4D0, 0x184, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_OE__EMI_WEIM_OE           IOMUX_PAD(0x4D4, 0x188, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_OE__GPIO2_25                      IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_OE__ECSPI2_MISO           IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, 0)
+#define _MX53_PAD_EIM_OE__IPU_DI1_PIN7          IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_OE__USBPHY2_IDDIG         IOMUX_PAD(0x4D4, 0x188, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_RW__EMI_WEIM_RW           IOMUX_PAD(0x4D8, 0x18C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_RW__GPIO2_26                      IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_RW__ECSPI2_SS0                    IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, 0)
+#define _MX53_PAD_EIM_RW__IPU_DI1_PIN8          IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT        IOMUX_PAD(0x4D8, 0x18C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_LBA__EMI_WEIM_LBA         IOMUX_PAD(0x4DC, 0x190, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_LBA__GPIO2_27                     IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_LBA__ECSPI2_SS1           IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, 0)
+#define _MX53_PAD_EIM_LBA__IPU_DI1_PIN17                IOMUX_PAD(0x4DC, 0x190, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                IOMUX_PAD(0x4DC, 0x190, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                IOMUX_PAD(0x4E4, 0x194, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB0__GPIO2_28                     IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11             IOMUX_PAD(0x4E4, 0x194, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB0__IPU_CSI1_D_11                IOMUX_PAD(0x4E4, 0x194, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB0__GPC_PMIC_RDY         IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, 0)
+#define _MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                IOMUX_PAD(0x4E4, 0x194, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                IOMUX_PAD(0x4E8, 0x198, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB1__GPIO2_29                     IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10             IOMUX_PAD(0x4E8, 0x198, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB1__IPU_CSI1_D_10                IOMUX_PAD(0x4E8, 0x198, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                IOMUX_PAD(0x4E8, 0x198, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0   IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA0__GPIO3_0                      IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9              IOMUX_PAD(0x4EC, 0x19C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA0__IPU_CSI1_D_9         IOMUX_PAD(0x4EC, 0x19C, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                IOMUX_PAD(0x4EC, 0x19C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1   IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA1__GPIO3_1                      IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8              IOMUX_PAD(0x4F0, 0x1A0, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA1__IPU_CSI1_D_8         IOMUX_PAD(0x4F0, 0x1A0, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                IOMUX_PAD(0x4F0, 0x1A0, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2   IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA2__GPIO3_2                      IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7              IOMUX_PAD(0x4F4, 0x1A4, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA2__IPU_CSI1_D_7         IOMUX_PAD(0x4F4, 0x1A4, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                IOMUX_PAD(0x4F4, 0x1A4, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3   IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA3__GPIO3_3                      IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6              IOMUX_PAD(0x4F8, 0x1A8, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA3__IPU_CSI1_D_6         IOMUX_PAD(0x4F8, 0x1A8, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                IOMUX_PAD(0x4F8, 0x1A8, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4   IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA4__GPIO3_4                      IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5              IOMUX_PAD(0x4FC, 0x1AC, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA4__IPU_CSI1_D_5         IOMUX_PAD(0x4FC, 0x1AC, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                IOMUX_PAD(0x4FC, 0x1AC, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5   IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA5__GPIO3_5                      IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4              IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4         IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                IOMUX_PAD(0x500, 0x1B0, 17, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6   IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA6__GPIO3_6                      IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3              IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA6__IPU_CSI1_D_3         IOMUX_PAD(0x504, 0x1B4, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                IOMUX_PAD(0x504, 0x1B4, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7   IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA7__GPIO3_7                      IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2              IOMUX_PAD(0x508, 0x1B8, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA7__IPU_CSI1_D_2         IOMUX_PAD(0x508, 0x1B8, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                IOMUX_PAD(0x508, 0x1B8, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8   IOMUX_PAD(0x50C, 0x1BC, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA8__GPIO3_8                      IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1              IOMUX_PAD(0x50C, 0x1BC, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA8__IPU_CSI1_D_1         IOMUX_PAD(0x50C, 0x1BC, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                IOMUX_PAD(0x50C, 0x1BC, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9   IOMUX_PAD(0x510, 0x1C0, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA9__GPIO3_9                      IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0              IOMUX_PAD(0x510, 0x1C0, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA9__IPU_CSI1_D_0         IOMUX_PAD(0x510, 0x1C0, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                IOMUX_PAD(0x510, 0x1C0, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA10__GPIO3_10                    IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA10__IPU_DI1_PIN15               IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN    IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, 0)
+#define _MX53_PAD_EIM_DA10__SRC_BT_CFG3_1               IOMUX_PAD(0x514, 0x1C4, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA11__GPIO3_11                    IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA11__IPU_DI1_PIN2                IOMUX_PAD(0x518, 0x1C8, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC              IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, 0)
+#define _MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA12__GPIO3_12                    IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA12__IPU_DI1_PIN3                IOMUX_PAD(0x51C, 0x1CC, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC              IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, 0)
+#define _MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA13__GPIO3_13                    IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA13__IPU_DI1_D0_CS               IOMUX_PAD(0x520, 0x1D0, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK             IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, 0)
+#define _MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA14__GPIO3_14                    IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA14__IPU_DI1_D1_CS               IOMUX_PAD(0x524, 0x1D4, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK             IOMUX_PAD(0x524, 0x1D4, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA15__GPIO3_15                    IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN1                IOMUX_PAD(0x528, 0x1D8, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN4                IOMUX_PAD(0x528, 0x1D8, 4, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B    IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_WE_B__GPIO6_12          IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B    IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_RE_B__GPIO6_13          IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT               IOMUX_PAD(0x534, 0x1E4, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_WAIT__GPIO5_0                     IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B    IOMUX_PAD(0x534, 0x1E4, 2, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX3_P__GPIO6_22         IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3    IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX2_P__GPIO6_24         IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2    IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_CLK_P__GPIO6_26         IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK    IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX1_P__GPIO6_28         IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1    IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX0_P__GPIO6_30         IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0    IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX3_P__GPIO7_22         IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3    IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_CLK_P__GPIO7_24         IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK    IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX2_P__GPIO7_26         IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2    IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX1_P__GPIO7_28         IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1    IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX0_P__GPIO7_30         IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0    IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_10__GPIO4_0                      IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_10__OSC32k_32K_OUT               IOMUX_PAD(0x540, 0x214, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_11__GPIO4_1                      IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_12__GPIO4_2                      IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_13__GPIO4_3                      IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_14__GPIO4_4                      IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CLE__EMI_NANDF_CLE              IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CLE__GPIO6_7                    IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0  IOMUX_PAD(0x5A0, 0x228, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_ALE__EMI_NANDF_ALE              IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_ALE__GPIO6_8            IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1  IOMUX_PAD(0x5A4, 0x22C, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B    IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_WP_B__GPIO6_9           IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0     IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_RB0__GPIO6_10           IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3  IOMUX_PAD(0x5AC, 0x234, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0     IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS0__GPIO6_11           IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4  IOMUX_PAD(0x5B0, 0x238, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1     IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS1__GPIO6_14           IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS1__MLB_MLBCLK         IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, 0)
+#define _MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5  IOMUX_PAD(0x5B4, 0x23C, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2     IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__GPIO6_15           IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__IPU_SISG_0         IOMUX_PAD(0x5B8, 0x240, 2, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__ESAI1_TX0          IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, 0)
+#define _MX53_PAD_NANDF_CS2__EMI_WEIM_CRE               IOMUX_PAD(0x5B8, 0x240, 4, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK              IOMUX_PAD(0x5B8, 0x240, 5, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__MLB_MLBSIG         IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, 0)
+#define _MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6  IOMUX_PAD(0x5B8, 0x240, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3     IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS3__GPIO6_16           IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS3__IPU_SISG_1         IOMUX_PAD(0x5BC, 0x244, 2, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS3__ESAI1_TX1          IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, 0)
+#define _MX53_PAD_NANDF_CS3__EMI_WEIM_A_26              IOMUX_PAD(0x5BC, 0x244, 4, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS3__MLB_MLBDAT         IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, 0)
+#define _MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7  IOMUX_PAD(0x5BC, 0x244, 7, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDIO__FEC_MDIO            IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, 0)
+#define _MX53_PAD_FEC_MDIO__GPIO1_22                    IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDIO__ESAI1_SCKR          IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, 0)
+#define _MX53_PAD_FEC_MDIO__FEC_COL                     IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, 0)
+#define _MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2              IOMUX_PAD(0x5C4, 0x248, 4, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3     IOMUX_PAD(0x5C4, 0x248, 5, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49    IOMUX_PAD(0x5C4, 0x248, 6, 0x0, 0, 0)
+#define _MX53_PAD_FEC_REF_CLK__FEC_TX_CLK               IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_REF_CLK__GPIO1_23         IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_REF_CLK__ESAI1_FSR                IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, 0)
+#define _MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4  IOMUX_PAD(0x5C8, 0x24C, 5, 0x0, 0, 0)
+#define _MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RX_ER__FEC_RX_ER          IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RX_ER__GPIO1_24           IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RX_ER__ESAI1_HCKR         IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, 0)
+#define _MX53_PAD_FEC_RX_ER__FEC_RX_CLK         IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, 0)
+#define _MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3             IOMUX_PAD(0x5CC, 0x250, 4, 0x0, 0, 0)
+#define _MX53_PAD_FEC_CRS_DV__FEC_RX_DV         IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_CRS_DV__GPIO1_25          IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, 0)
+#define _MX53_PAD_FEC_RXD1__FEC_RDATA_1         IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RXD1__GPIO1_26                    IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RXD1__ESAI1_FST           IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, 0)
+#define _MX53_PAD_FEC_RXD1__MLB_MLBSIG          IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, 0)
+#define _MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1              IOMUX_PAD(0x5D4, 0x258, 4, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RXD0__FEC_RDATA_0         IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RXD0__GPIO1_27                    IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RXD0__ESAI1_HCKT          IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, 0)
+#define _MX53_PAD_FEC_RXD0__OSC32k_32K_OUT              IOMUX_PAD(0x5D8, 0x25C, 3, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TX_EN__FEC_TX_EN          IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TX_EN__GPIO1_28           IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2              IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, 0)
+#define _MX53_PAD_FEC_TXD1__FEC_TDATA_1         IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TXD1__GPIO1_29                    IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3               IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, 0)
+#define _MX53_PAD_FEC_TXD1__MLB_MLBCLK          IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, 0)
+#define _MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TXD0__FEC_TDATA_0         IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TXD0__GPIO1_30                    IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1               IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, 0)
+#define _MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0   IOMUX_PAD(0x5E4, 0x268, 7, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDC__FEC_MDC                      IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDC__GPIO1_31                     IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, 0)
+#define _MX53_PAD_FEC_MDC__MLB_MLBDAT           IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, 0)
+#define _MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG       IOMUX_PAD(0x5E8, 0x26C, 4, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1    IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOW__PATA_DIOW          IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOW__GPIO6_17           IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX      IOMUX_PAD(0x5F0, 0x270, 3, 0x878, 2, 0)
+#define _MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2  IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMACK__PATA_DMACK                IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMACK__GPIO6_18          IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMACK__UART1_RXD_MUX     IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, 0)
+#define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMARQ__PATA_DMARQ                IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMARQ__GPIO7_0           IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     IOMUX_PAD(0x5F8, 0x278, 3, 0x880, 2, 0)
+#define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0     IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN        IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_BUFFER_EN__GPIO7_1               IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, 0)
+#define _MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5     IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_INTRQ__PATA_INTRQ                IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_INTRQ__GPIO7_2           IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_INTRQ__UART2_CTS         IOMUX_PAD(0x600, 0x280, 3, 0x87C, 2, 0)
+#define _MX53_PAD_PATA_INTRQ__CAN1_TXCAN                IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2     IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOR__PATA_DIOR          IOMUX_PAD(0x604, 0x284, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOR__GPIO7_3                    IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOR__UART2_RTS          IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, 0)
+#define _MX53_PAD_PATA_DIOR__CAN1_RXCAN         IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, 0)
+#define _MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7  IOMUX_PAD(0x604, 0x284, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B       IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_RESET_B__GPIO7_4         IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_RESET_B__ESDHC3_CMD              IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_RESET_B__UART1_CTS               IOMUX_PAD(0x608, 0x288, 3, 0x874, 2, 0)
+#define _MX53_PAD_PATA_RESET_B__CAN2_TXCAN              IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0       IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_IORDY__PATA_IORDY                IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_IORDY__GPIO7_5           IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_IORDY__ESDHC3_CLK                IOMUX_PAD(0x60C, 0x28C, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_IORDY__UART1_RTS         IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, 0)
+#define _MX53_PAD_PATA_IORDY__CAN2_RXCAN                IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, 0)
+#define _MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_0__PATA_DA_0          IOMUX_PAD(0x610, 0x290, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_0__GPIO7_6            IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_0__ESDHC3_RST         IOMUX_PAD(0x610, 0x290, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_0__OWIRE_LINE         IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, 0)
+#define _MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2  IOMUX_PAD(0x610, 0x290, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_1__PATA_DA_1          IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_1__GPIO7_7            IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_1__ESDHC4_CMD         IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_1__UART3_CTS          IOMUX_PAD(0x614, 0x294, 4, 0x884, 4, 0)
+#define _MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3  IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_2__PATA_DA_2          IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_2__GPIO7_8            IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_2__ESDHC4_CLK         IOMUX_PAD(0x618, 0x298, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_2__UART3_RTS          IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, 0)
+#define _MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4  IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_0__PATA_CS_0          IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_0__GPIO7_9                    IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX              IOMUX_PAD(0x61C, 0x29C, 4, 0x888, 2, 0)
+#define _MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5  IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_1__PATA_CS_1          IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_1__GPIO7_10           IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_1__UART3_RXD_MUX              IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, 0)
+#define _MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6  IOMUX_PAD(0x620, 0x2A0, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__PATA_DATA_0               IOMUX_PAD(0x628, 0x2A4, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__GPIO2_0           IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__EMI_NANDF_D_0     IOMUX_PAD(0x628, 0x2A4, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__ESDHC3_DAT4               IOMUX_PAD(0x628, 0x2A4, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0     IOMUX_PAD(0x628, 0x2A4, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0    IOMUX_PAD(0x628, 0x2A4, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__PATA_DATA_1               IOMUX_PAD(0x62C, 0x2A8, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__GPIO2_1           IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__EMI_NANDF_D_1     IOMUX_PAD(0x62C, 0x2A8, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__ESDHC3_DAT5               IOMUX_PAD(0x62C, 0x2A8, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1     IOMUX_PAD(0x62C, 0x2A8, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1    IOMUX_PAD(0x62C, 0x2A8, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__PATA_DATA_2               IOMUX_PAD(0x630, 0x2AC, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__GPIO2_2           IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__EMI_NANDF_D_2     IOMUX_PAD(0x630, 0x2AC, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__ESDHC3_DAT6               IOMUX_PAD(0x630, 0x2AC, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2     IOMUX_PAD(0x630, 0x2AC, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2    IOMUX_PAD(0x630, 0x2AC, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__PATA_DATA_3               IOMUX_PAD(0x634, 0x2B0, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__GPIO2_3           IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__EMI_NANDF_D_3     IOMUX_PAD(0x634, 0x2B0, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__ESDHC3_DAT7               IOMUX_PAD(0x634, 0x2B0, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3     IOMUX_PAD(0x634, 0x2B0, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3    IOMUX_PAD(0x634, 0x2B0, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__PATA_DATA_4               IOMUX_PAD(0x638, 0x2B4, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__GPIO2_4           IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__EMI_NANDF_D_4     IOMUX_PAD(0x638, 0x2B4, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__ESDHC4_DAT4               IOMUX_PAD(0x638, 0x2B4, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4     IOMUX_PAD(0x638, 0x2B4, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4    IOMUX_PAD(0x638, 0x2B4, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__PATA_DATA_5       IOMUX_PAD(0x63C, 0x2B8, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__GPIO2_5           IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__EMI_NANDF_D_5     IOMUX_PAD(0x63C, 0x2B8, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5               IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5     IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5    IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__PATA_DATA_6       IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__GPIO2_6           IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6     IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6               IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6     IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6    IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__PATA_DATA_7               IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__GPIO2_7           IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7     IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__ESDHC4_DAT7               IOMUX_PAD(0x644, 0x2C0, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7     IOMUX_PAD(0x644, 0x2C0, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7    IOMUX_PAD(0x644, 0x2C0, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__PATA_DATA_8               IOMUX_PAD(0x648, 0x2C4, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__GPIO2_8           IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__ESDHC1_DAT4               IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__EMI_NANDF_D_8     IOMUX_PAD(0x648, 0x2C4, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__ESDHC3_DAT0               IOMUX_PAD(0x648, 0x2C4, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8     IOMUX_PAD(0x648, 0x2C4, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8    IOMUX_PAD(0x648, 0x2C4, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__PATA_DATA_9               IOMUX_PAD(0x64C, 0x2C8, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__GPIO2_9           IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__ESDHC1_DAT5               IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__EMI_NANDF_D_9     IOMUX_PAD(0x64C, 0x2C8, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__ESDHC3_DAT1               IOMUX_PAD(0x64C, 0x2C8, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9     IOMUX_PAD(0x64C, 0x2C8, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9    IOMUX_PAD(0x64C, 0x2C8, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__PATA_DATA_10     IOMUX_PAD(0x650, 0x2CC, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__GPIO2_10         IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__ESDHC1_DAT6              IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__EMI_NANDF_D_10   IOMUX_PAD(0x650, 0x2CC, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__ESDHC3_DAT2              IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10   IOMUX_PAD(0x650, 0x2CC, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10  IOMUX_PAD(0x650, 0x2CC, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__PATA_DATA_11     IOMUX_PAD(0x654, 0x2D0, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__GPIO2_11         IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__ESDHC1_DAT7              IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__EMI_NANDF_D_11   IOMUX_PAD(0x654, 0x2D0, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__ESDHC3_DAT3              IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11   IOMUX_PAD(0x654, 0x2D0, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11  IOMUX_PAD(0x654, 0x2D0, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__PATA_DATA_12     IOMUX_PAD(0x658, 0x2D4, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__GPIO2_12         IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__ESDHC2_DAT4              IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__EMI_NANDF_D_12   IOMUX_PAD(0x658, 0x2D4, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__ESDHC4_DAT0              IOMUX_PAD(0x658, 0x2D4, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12   IOMUX_PAD(0x658, 0x2D4, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12  IOMUX_PAD(0x658, 0x2D4, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__PATA_DATA_13     IOMUX_PAD(0x65C, 0x2D8, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__GPIO2_13         IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__ESDHC2_DAT5              IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__EMI_NANDF_D_13   IOMUX_PAD(0x65C, 0x2D8, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__ESDHC4_DAT1              IOMUX_PAD(0x65C, 0x2D8, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13   IOMUX_PAD(0x65C, 0x2D8, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13  IOMUX_PAD(0x65C, 0x2D8, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__PATA_DATA_14     IOMUX_PAD(0x660, 0x2DC, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__GPIO2_14         IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__ESDHC2_DAT6              IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__EMI_NANDF_D_14   IOMUX_PAD(0x660, 0x2DC, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__ESDHC4_DAT2              IOMUX_PAD(0x660, 0x2DC, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14   IOMUX_PAD(0x660, 0x2DC, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14  IOMUX_PAD(0x660, 0x2DC, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__PATA_DATA_15     IOMUX_PAD(0x664, 0x2E0, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__GPIO2_15         IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__ESDHC2_DAT7              IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__EMI_NANDF_D_15   IOMUX_PAD(0x664, 0x2E0, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__ESDHC4_DAT3              IOMUX_PAD(0x664, 0x2E0, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15   IOMUX_PAD(0x664, 0x2E0, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15  IOMUX_PAD(0x664, 0x2E0, 6, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA0__ESDHC1_DAT0        IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA0__GPIO1_16   IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA0__CSPI_MISO  IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, 0)
+#define _MX53_PAD_SD1_DATA0__CCM_PLL3_BYP       IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, 0)
+#define _MX53_PAD_SD1_DATA1__ESDHC1_DAT1        IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA1__GPIO1_17   IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA1__CSPI_SS0   IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, 0)
+#define _MX53_PAD_SD1_DATA1__CCM_PLL4_BYP       IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, 0)
+#define _MX53_PAD_SD1_CMD__ESDHC1_CMD   IOMUX_PAD(0x674, 0x2EC, IOMUX_CONFIG_SION, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CMD__GPIO1_18             IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CMD__GPT_CMPOUT1  IOMUX_PAD(0x674, 0x2EC, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CMD__CSPI_MOSI            IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, 0)
+#define _MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, 0)
+#define _MX53_PAD_SD1_DATA2__ESDHC1_DAT2                IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__GPIO1_19           IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__GPT_CMPOUT2                IOMUX_PAD(0x678, 0x2F0, 2, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__PWM2_PWMO          IOMUX_PAD(0x678, 0x2F0, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_B               IOMUX_PAD(0x678, 0x2F0, 4, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__CSPI_SS1           IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, 0)
+#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB       IOMUX_PAD(0x678, 0x2F0, 6, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__CCM_PLL2_BYP               IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, 0)
+#define _MX53_PAD_SD1_CLK__ESDHC1_CLK   IOMUX_PAD(0x67C, 0x2F4, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CLK__GPIO1_20             IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CLK__OSC32k_32K_OUT       IOMUX_PAD(0x67C, 0x2F4, 2, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CLK__GPT_CLKIN            IOMUX_PAD(0x67C, 0x2F4, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CLK__CSPI_SCLK            IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, 0)
+#define _MX53_PAD_SD1_CLK__SATA_PHY_DTB_0       IOMUX_PAD(0x67C, 0x2F4, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__ESDHC1_DAT3        IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__GPIO1_21   IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__GPT_CMPOUT3        IOMUX_PAD(0x680, 0x2F8, 2, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__PWM1_PWMO  IOMUX_PAD(0x680, 0x2F8, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_B       IOMUX_PAD(0x680, 0x2F8, 4, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__CSPI_SS2   IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, 0)
+#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB       IOMUX_PAD(0x680, 0x2F8, 6, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1     IOMUX_PAD(0x680, 0x2F8, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CLK__ESDHC2_CLK   IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CLK__GPIO1_10             IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CLK__KPP_COL_5            IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, 0)
+#define _MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS     IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, 0)
+#define _MX53_PAD_SD2_CLK__CSPI_SCLK            IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, 0)
+#define _MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CMD__ESDHC2_CMD   IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CMD__GPIO1_11             IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CMD__KPP_ROW_5    IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, 0)
+#define _MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC      IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, 0)
+#define _MX53_PAD_SD2_CMD__CSPI_MOSI            IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, 0)
+#define _MX53_PAD_SD2_CMD__SCC_RANDOM   IOMUX_PAD(0x68C, 0x300, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA3__ESDHC2_DAT3        IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA3__GPIO1_12   IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA3__KPP_COL_6  IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, 0)
+#define _MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC    IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, 0)
+#define _MX53_PAD_SD2_DATA3__CSPI_SS2   IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, 0)
+#define _MX53_PAD_SD2_DATA3__SJC_DONE   IOMUX_PAD(0x690, 0x304, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA2__ESDHC2_DAT2        IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA2__GPIO1_13   IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA2__KPP_ROW_6  IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, 0)
+#define _MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD    IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, 0)
+#define _MX53_PAD_SD2_DATA2__CSPI_SS1   IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, 0)
+#define _MX53_PAD_SD2_DATA2__SJC_FAIL   IOMUX_PAD(0x694, 0x308, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA1__ESDHC2_DAT1        IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA1__GPIO1_14   IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA1__KPP_COL_7  IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, 0)
+#define _MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS   IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, 0)
+#define _MX53_PAD_SD2_DATA1__CSPI_SS0   IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, 0)
+#define _MX53_PAD_SD2_DATA1__RTIC_SEC_VIO       IOMUX_PAD(0x698, 0x30C, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA0__ESDHC2_DAT0        IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA0__GPIO1_15   IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA0__KPP_ROW_7  IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, 0)
+#define _MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD    IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, 0)
+#define _MX53_PAD_SD2_DATA0__CSPI_MISO  IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, 0)
+#define _MX53_PAD_SD2_DATA0__RTIC_DONE_INT      IOMUX_PAD(0x69C, 0x310, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__CCM_CLKO              IOMUX_PAD(0x6A4, 0x314, 0, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__GPIO1_0               IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__KPP_COL_5             IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, 0)
+#define _MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK      IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__EPIT1_EPITO   IOMUX_PAD(0x6A4, 0x314, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__SRTC_ALARM_DEB        IOMUX_PAD(0x6A4, 0x314, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__USBOH3_USBH1_PWR      IOMUX_PAD(0x6A4, 0x314, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__CSU_TD                IOMUX_PAD(0x6A4, 0x314, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__ESAI1_SCKR            IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, 0)
+#define _MX53_PAD_GPIO_1__GPIO1_1               IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__KPP_ROW_5             IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, 0)
+#define _MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK      IOMUX_PAD(0x6A8, 0x318, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__PWM2_PWMO     IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__WDOG2_WDOG_B  IOMUX_PAD(0x6A8, 0x318, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__ESDHC1_CD             IOMUX_PAD(0x6A8, 0x318, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__SRC_TESTER_ACK        IOMUX_PAD(0x6A8, 0x318, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_9__ESAI1_FSR             IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, 0)
+#define _MX53_PAD_GPIO_9__GPIO1_9               IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_9__KPP_COL_6             IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, 0)
+#define _MX53_PAD_GPIO_9__CCM_REF_EN_B  IOMUX_PAD(0x6AC, 0x31C, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_9__PWM1_PWMO     IOMUX_PAD(0x6AC, 0x31C, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_9__WDOG1_WDOG_B  IOMUX_PAD(0x6AC, 0x31C, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_9__ESDHC1_WP             IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, 0)
+#define _MX53_PAD_GPIO_9__SCC_FAIL_STATE        IOMUX_PAD(0x6AC, 0x31C, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_3__ESAI1_HCKR            IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, 0)
+#define _MX53_PAD_GPIO_3__GPIO1_3               IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_3__I2C3_SCL              IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, 0)
+#define _MX53_PAD_GPIO_3__DPLLIP1_TOG_EN        IOMUX_PAD(0x6B0, 0x320, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_3__CCM_CLKO2             IOMUX_PAD(0x6B0, 0x320, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0    IOMUX_PAD(0x6B0, 0x320, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_3__USBOH3_USBH1_OC       IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, 0)
+#define _MX53_PAD_GPIO_3__MLB_MLBCLK            IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, 0)
+#define _MX53_PAD_GPIO_6__ESAI1_SCKT            IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, 0)
+#define _MX53_PAD_GPIO_6__GPIO1_6               IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_6__I2C3_SDA              IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, 0)
+#define _MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_6__CSU_CSU_INT_DEB       IOMUX_PAD(0x6B4, 0x324, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1    IOMUX_PAD(0x6B4, 0x324, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_6__ESDHC2_LCTL   IOMUX_PAD(0x6B4, 0x324, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_6__MLB_MLBSIG            IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, 0)
+#define _MX53_PAD_GPIO_2__ESAI1_FST             IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, 0)
+#define _MX53_PAD_GPIO_2__GPIO1_2               IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_2__KPP_ROW_6             IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, 0)
+#define _MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0   IOMUX_PAD(0x6B8, 0x328, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2    IOMUX_PAD(0x6B8, 0x328, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_2__ESDHC2_WP             IOMUX_PAD(0x6B8, 0x328, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_2__MLB_MLBDAT    IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, 0)
+#define _MX53_PAD_GPIO_4__ESAI1_HCKT            IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, 0)
+#define _MX53_PAD_GPIO_4__GPIO1_4               IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_4__KPP_COL_7             IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, 0)
+#define _MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1   IOMUX_PAD(0x6BC, 0x32C, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3    IOMUX_PAD(0x6BC, 0x32C, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_4__ESDHC2_CD             IOMUX_PAD(0x6BC, 0x32C, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, 0)
+#define _MX53_PAD_GPIO_5__GPIO1_5               IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_5__KPP_ROW_7             IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, 0)
+#define _MX53_PAD_GPIO_5__CCM_CLKO              IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2   IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4    IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_5__I2C3_SCL              IOMUX_PAD(0x6C0, 0x330, 6, 0x824, 2, 0)
+#define _MX53_PAD_GPIO_5__CCM_PLL1_BYP  IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0)
+#define _MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0)
+#define _MX53_PAD_GPIO_7__GPIO1_7               IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_7__EPIT1_EPITO   IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_7__CAN1_TXCAN    IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x880, 4, 0)
+#define _MX53_PAD_GPIO_7__FIRI_RXD              IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0)
+#define _MX53_PAD_GPIO_7__SPDIF_PLOCK   IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_7__CCM_PLL2_BYP  IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0)
+#define _MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, 0)
+#define _MX53_PAD_GPIO_8__GPIO1_8               IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_8__EPIT2_EPITO   IOMUX_PAD(0x6C8, 0x338, 2, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_8__CAN1_RXCAN    IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, 0)
+#define _MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, 0)
+#define _MX53_PAD_GPIO_8__FIRI_TXD              IOMUX_PAD(0x6C8, 0x338, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_8__SPDIF_SRCLK   IOMUX_PAD(0x6C8, 0x338, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_8__CCM_PLL3_BYP  IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, 0)
+#define _MX53_PAD_GPIO_16__ESAI1_TX3_RX2        IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, 0)
+#define _MX53_PAD_GPIO_16__GPIO7_11             IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT     IOMUX_PAD(0x6CC, 0x33C, 2, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_16__SPDIF_IN1            IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, 0)
+#define _MX53_PAD_GPIO_16__I2C3_SDA             IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, 0)
+#define _MX53_PAD_GPIO_16__SJC_DE_B             IOMUX_PAD(0x6CC, 0x33C, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_17__ESAI1_TX0            IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, 0)
+#define _MX53_PAD_GPIO_17__GPIO7_12             IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0     IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, 0)
+#define _MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, 0)
+#define _MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG  IOMUX_PAD(0x6D0, 0x340, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_17__SPDIF_OUT1   IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_17__IPU_SNOOP2   IOMUX_PAD(0x6D0, 0x340, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_18__ESAI1_TX1            IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, 0)
+#define _MX53_PAD_GPIO_18__GPIO7_13             IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1     IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, 0)
+#define _MX53_PAD_GPIO_18__OWIRE_LINE   IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, 0)
+#define _MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG       IOMUX_PAD(0x6D4, 0x344, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK     IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, 0)
+#define _MX53_PAD_GPIO_18__ESDHC1_LCTL  IOMUX_PAD(0x6D4, 0x344, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_18__SRC_SYSTEM_RST       IOMUX_PAD(0x6D4, 0x344, 7, 0x0, 0, 0)
-#define MX53_PAD_GPIO_19__GPIO_4_5              IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__KPP_COL_5             (_MX53_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL0__GPIO_4_6             IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__GPIO4_5               (_MX53_PAD_GPIO_19__GPIO4_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW0__GPIO_4_7             IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__CCM_CLKO              (_MX53_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL1__GPIO_4_8             IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__SPDIF_OUT1            (_MX53_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW1__GPIO_4_9             IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2          (_MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL2__GPIO_4_10            IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__ECSPI1_RDY            (_MX53_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW2__GPIO_4_11    IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__FEC_TDATA_3           (_MX53_PAD_GPIO_19__FEC_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL3__GPIO_4_12            IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__SRC_INT_BOOT          (_MX53_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW3__GPIO_4_13    IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__KPP_COL_0            (_MX53_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL4__GPIO_4_14            IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__GPIO4_6              (_MX53_PAD_KEY_COL0__GPIO4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW4__GPIO_4_15    IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC              (_MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD       IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__UART4_TXD_MUX                (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16        IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__ECSPI1_SCLK          (_MX53_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN15__GPIO_4_17   IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__FEC_RDATA_3          (_MX53_PAD_KEY_COL0__FEC_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN2__GPIO_4_18            IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST               (_MX53_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN3__GPIO_4_19            IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__KPP_ROW_0            (_MX53_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DI0_PIN4__GPIO_4_20            IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__GPIO4_7              (_MX53_PAD_KEY_ROW0__GPIO4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT0__GPIO_4_21  IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD              (_MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT1__GPIO_4_22  IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX                (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT2__GPIO_4_23  IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI          (_MX53_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT3__GPIO_4_24  IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__FEC_TX_ER            (_MX53_PAD_KEY_ROW0__FEC_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT4__GPIO_4_25  IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__KPP_COL_1            (_MX53_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT5__GPIO_4_26  IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__GPIO4_8              (_MX53_PAD_KEY_COL1__GPIO4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT6__GPIO_4_27  IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS             (_MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT7__GPIO_4_28  IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__UART5_TXD_MUX                (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT8__GPIO_4_29  IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__ECSPI1_MISO          (_MX53_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT9__GPIO_4_30  IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__FEC_RX_CLK           (_MX53_PAD_KEY_COL1__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY              (_MX53_PAD_KEY_COL1__USBPHY1_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT11__GPIO_5_5  IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__KPP_ROW_1            (_MX53_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT12__GPIO_5_6  IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__GPIO4_9              (_MX53_PAD_KEY_ROW1__GPIO4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT13__GPIO_5_7  IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD              (_MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT14__GPIO_5_8  IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX                (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT15__GPIO_5_9  IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__ECSPI1_SS0           (_MX53_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__FEC_COL              (_MX53_PAD_KEY_ROW1__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID              (_MX53_PAD_KEY_ROW1__USBPHY1_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__KPP_COL_2            (_MX53_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__GPIO4_10             (_MX53_PAD_KEY_COL2__GPIO4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__CAN1_TXCAN           (_MX53_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__FEC_MDIO             (_MX53_PAD_KEY_COL2__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__ECSPI1_SS1           (_MX53_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__FEC_RDATA_2          (_MX53_PAD_KEY_COL2__FEC_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE             (_MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_MCLK__GPIO_5_19   IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__KPP_ROW_2            (_MX53_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20        IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__GPIO4_11             (_MX53_PAD_KEY_ROW2__GPIO4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_VSYNC__GPIO_5_21  IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__CAN1_RXCAN           (_MX53_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D4__GPIO_5_22             IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__FEC_MDC              (_MX53_PAD_KEY_ROW2__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D5__GPIO_5_23             IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__ECSPI1_SS2           (_MX53_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D6__GPIO_5_24             IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__FEC_TDATA_2          (_MX53_PAD_KEY_ROW2__FEC_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D7__GPIO_5_25             IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR              (_MX53_PAD_KEY_ROW2__USBPHY1_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D8__GPIO_5_26             IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__KPP_COL_3            (_MX53_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D9__GPIO_5_27             IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__GPIO4_12             (_MX53_PAD_KEY_COL3__GPIO4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D10__GPIO_5_28            IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__USBOH3_H2_DP         (_MX53_PAD_KEY_COL3__USBOH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D11__GPIO_5_29            IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__SPDIF_IN1            (_MX53_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D12__GPIO_5_30            IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__I2C2_SCL             (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D13__GPIO_5_31            IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__ECSPI1_SS3           (_MX53_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D14__GPIO_6_0             IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__FEC_CRS              (_MX53_PAD_KEY_COL3__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D15__GPIO_6_1             IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK             (_MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D16__GPIO_6_2             IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__KPP_ROW_3            (_MX53_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D17__GPIO_6_3             IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__GPIO4_13             (_MX53_PAD_KEY_ROW3__GPIO4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D18__GPIO_6_4             IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM         (_MX53_PAD_KEY_ROW3__USBOH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_D19__GPIO_6_5             IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK             (_MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_CSI0__NVCC_CSI0   IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__I2C2_SDA             (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_JTAG_TMS__JTAG_TMS             IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT               (_MX53_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_JTAG_MOD__JTAG_MOD             IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP         (_MX53_PAD_KEY_ROW3__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0          (_MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_JTAG_TDI__JTAG_TDI             IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__KPP_COL_4            (_MX53_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_JTAG_TCK__JTAG_TCK             IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__GPIO4_14             (_MX53_PAD_KEY_COL4__GPIO4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_JTAG_TDO__JTAG_TDO             IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__CAN2_TXCAN           (_MX53_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A25__GPIO_5_2              IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__IPU_SISG_4           (_MX53_PAD_KEY_COL4__IPU_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB2__GPIO_2_30             IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__UART5_RTS            (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D16__GPIO_3_16             IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC             (_MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D17__GPIO_3_17             IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1          (_MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D18__GPIO_3_18             IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__KPP_ROW_4            (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D16__CSPI1_SCLK            IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT4, 0x79c, 3, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__GPIO4_15             (_MX53_PAD_KEY_ROW4__GPIO4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D17__CSPI1_MISO            IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT4, 0x7a0, 3, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__CAN2_RXCAN           (_MX53_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D18__CSPI1_MOSI            IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT4, 0x7a4, 3, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__IPU_SISG_5           (_MX53_PAD_KEY_ROW4__IPU_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D19__GPIO_3_19             IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__UART5_CTS            (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D20__GPIO_3_20             IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR            (_MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D21__GPIO_3_21             IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID            (_MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D22__GPIO_3_22             IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK         (_MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D23__GPIO_3_23             IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__GPIO4_16         (_MX53_PAD_DI0_DISP_CLK__GPIO4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB3__GPIO_2_31             IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR         (_MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D24__GPIO_3_24             IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0          (_MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D25__GPIO_3_25             IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0          (_MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D26__GPIO_3_26             IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID           (_MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D27__GPIO_3_27             IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               (_MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D28__GPIO_3_28             IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__GPIO4_17            (_MX53_PAD_DI0_PIN15__GPIO4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D29__GPIO_3_29             IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC             (_MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D30__GPIO_3_30             IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1             (_MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D31__GPIO_3_31             IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1             (_MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_EIM1__NVCC_EIM1   IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID              (_MX53_PAD_DI0_PIN15__USBPHY1_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A24__GPIO_5_4              IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         (_MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A23__GPIO_6_6              IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__GPIO4_18             (_MX53_PAD_DI0_PIN2__GPIO4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD              (_MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A21__GPIO_2_17             IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2              (_MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A20__GPIO_2_18             IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2              (_MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A19__GPIO_2_19             IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION           (_MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A18__GPIO_2_20             IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3         (_MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A17__GPIO_2_21             IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__GPIO4_19             (_MX53_PAD_DI0_PIN3__GPIO4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_A16__GPIO_2_22             IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS             (_MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_CS0__GPIO_2_23             IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3              (_MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_CS1__GPIO_2_24             IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3              (_MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_OE__GPIO_2_25              IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG                (_MX53_PAD_DI0_PIN3__USBPHY1_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_RW__GPIO_2_26              IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4         (_MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_LBA__GPIO_2_27             IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__GPIO4_20             (_MX53_PAD_DI0_PIN4__GPIO4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_EIM4__NVCC_EIM4   IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD              (_MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB0__GPIO_2_28             IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__ESDHC1_WP            (_MX53_PAD_DI0_PIN4__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB1__GPIO_2_29             IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD             (_MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA0__GPIO_3_0              IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4              (_MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA1__GPIO_3_1              IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT               (_MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA2__GPIO_3_2              IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            (_MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA3__GPIO_3_3              IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__GPIO4_21           (_MX53_PAD_DISP0_DAT0__GPIO4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA4__GPIO_3_4              IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__CSPI_SCLK          (_MX53_PAD_DISP0_DAT0__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA5__GPIO_3_5              IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0                (_MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA6__GPIO_3_6              IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN                (_MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA7__GPIO_3_7              IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5            (_MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA8__GPIO_3_8              IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY            (_MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA9__GPIO_3_9              IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            (_MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA10__GPIO_3_10            IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__GPIO4_22           (_MX53_PAD_DISP0_DAT1__GPIO4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA11__GPIO_3_11            IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__CSPI_MOSI          (_MX53_PAD_DISP0_DAT1__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA12__GPIO_3_12            IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1                (_MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA13__GPIO_3_13            IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL               (_MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA14__GPIO_3_14            IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6            (_MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_DA15__GPIO_3_15            IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID            (_MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_WE_B__GPIO_6_12  IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            (_MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_RE_B__GPIO_6_13  IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__GPIO4_23           (_MX53_PAD_DISP0_DAT2__GPIO4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_WAIT__GPIO_5_0             IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__CSPI_MISO          (_MX53_PAD_DISP0_DAT2__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_BCLK__EIM_BCLK             IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2                (_MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_EIM7__NVCC_EIM7   IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE            (_MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7            (_MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE           (_MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            (_MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__GPIO4_24           (_MX53_PAD_DISP0_DAT3__GPIO4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__CSPI_SS0           (_MX53_PAD_DISP0_DAT3__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3                (_MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR               (_MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8            (_MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR            (_MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            (_MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_10__GPIO_4_0              IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__GPIO4_25           (_MX53_PAD_DISP0_DAT4__GPIO4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_11__GPIO_4_1              IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__CSPI_SS1           (_MX53_PAD_DISP0_DAT4__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_12__GPIO_4_2              IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4                (_MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_13__GPIO_4_3              IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB         (_MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_14__GPIO_4_4              IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9            (_MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_DQM3__DRAM_DQM3   IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK           (_MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            (_MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1       IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__GPIO4_26           (_MX53_PAD_DISP0_DAT5__GPIO4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_DQM2__DRAM_DQM2   IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__CSPI_SS2           (_MX53_PAD_DISP0_DAT5__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1       IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5                (_MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS           (_MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10           (_MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1       IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0                (_MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_CAS__DRAM_CAS             IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            (_MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0       IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__GPIO4_27           (_MX53_PAD_DISP0_DAT6__GPIO4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__CSPI_SS3           (_MX53_PAD_DISP0_DAT6__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0       IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6                (_MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_DQM0__DRAM_DQM0   IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE          (_MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_RAS__DRAM_RAS             IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11           (_MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0       IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1                (_MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            (_MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_DRAM_DQM1__DRAM_DQM1   IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__GPIO4_28           (_MX53_PAD_DISP0_DAT7__GPIO4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ       IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__CSPI_RDY           (_MX53_PAD_DISP0_DAT7__CSPI_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ   IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7                (_MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CLE__GPIO_6_7            IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0         (_MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_ALE__GPIO_6_8    IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12           (_MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_WP_B__GPIO_6_9   IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID          (_MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_RB0__GPIO_6_10   IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            (_MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS0__GPIO_6_11   IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__GPIO4_29           (_MX53_PAD_DISP0_DAT8__GPIO4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS1__GPIO_6_14   IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__PWM1_PWMO          (_MX53_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS2__GPIO_6_15   IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B               (_MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NANDF_CS3__GPIO_6_16   IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1         (_MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13           (_MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDIO__GPIO_1_22            IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID             (_MX53_PAD_DISP0_DAT8__USBPHY2_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            (_MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RX_ER__GPIO_1_24   IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__GPIO4_30           (_MX53_PAD_DISP0_DAT9__GPIO4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_CRS_DV__GPIO_1_25  IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__PWM2_PWMO          (_MX53_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RXD1__GPIO_1_26            IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B               (_MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_RXD0__GPIO_1_27            IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2         (_MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TX_EN__GPIO_1_28   IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14           (_MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TXD1__GPIO_1_29            IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0          (_MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_TXD0__GPIO_1_30            IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          (_MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_FEC_MDC__GPIO_1_31             IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__GPIO4_31          (_MX53_PAD_DISP0_DAT10__GPIO4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_FEC__NVCC_FEC             IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP          (_MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DIOW__GPIO_6_17    IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3                (_MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DMACK__GPIO_6_18   IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15          (_MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DMARQ__GPIO_7_0    IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1         (_MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1        IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          (_MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_INTRQ__GPIO_7_2            IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__GPIO5_5           (_MX53_PAD_DISP0_DAT11__GPIO5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DIOR__GPIO_7_3             IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT          (_MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_RESET_B__GPIO_7_4  IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4                (_MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_IORDY__GPIO_7_5            IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16          (_MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DA_0__GPIO_7_6             IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2         (_MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DA_1__GPIO_7_7             IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          (_MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DA_2__GPIO_7_8             IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__GPIO5_6           (_MX53_PAD_DISP0_DAT12__GPIO5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_CS_0__GPIO_7_9             IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK          (_MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_CS_1__GPIO_7_10            IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5                (_MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_ATA2__NVCC_ATA2   IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17          (_MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA0__GPIO_2_0    IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3         (_MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA1__GPIO_2_1    IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          (_MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA2__GPIO_2_2    IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__GPIO5_7           (_MX53_PAD_DISP0_DAT13__GPIO5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA3__GPIO_2_3    IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS          (_MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA4__GPIO_2_4    IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0                (_MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA5__GPIO_2_5    IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18          (_MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA6__GPIO_2_6    IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4         (_MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA7__GPIO_2_7    IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          (_MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA8__GPIO_2_8    IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__GPIO5_8           (_MX53_PAD_DISP0_DAT14__GPIO5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA9__GPIO_2_9    IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC           (_MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA10__GPIO_2_10  IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1                (_MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA11__GPIO_2_11  IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19          (_MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA12__GPIO_2_12  IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5         (_MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA13__GPIO_2_13  IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          (_MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA14__GPIO_2_14  IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__GPIO5_9           (_MX53_PAD_DISP0_DAT15__GPIO5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_ATA_DATA15__GPIO_2_15  IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1                (_MX53_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_ATA0__NVCC_ATA0   IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1                (_MX53_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA0__GPIO_1_16   IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2                (_MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA1__GPIO_1_17   IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20          (_MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_CMD__GPIO_1_18             IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6         (_MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA2__GPIO_1_19   IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          (_MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_CLK__GPIO_1_20             IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__GPIO5_10          (_MX53_PAD_DISP0_DAT16__GPIO5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD1_DATA3__GPIO_1_21   IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI               (_MX53_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_SD1__NVCC_SD1             IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC           (_MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CLK__GPIO_1_10             IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0          (_MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_CMD__GPIO_1_11             IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3                (_MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA3__GPIO_1_12   IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21          (_MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA2__GPIO_1_13   IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7         (_MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA1__GPIO_1_14   IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          (_MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_SD2_DATA0__GPIO_1_15   IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__GPIO5_11          (_MX53_PAD_DISP0_DAT17__GPIO5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_SD2__NVCC_SD2             IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO               (_MX53_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_0__GPIO_1_0               IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD           (_MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_1__GPIO_1_1               IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1          (_MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_9__GPIO_1_9               IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4                (_MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_3__GPIO_1_3               IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22          (_MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_6__GPIO_1_6               IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          (_MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_2__GPIO_1_2               IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__GPIO5_12          (_MX53_PAD_DISP0_DAT18__GPIO5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_4__GPIO_1_4               IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0                (_MX53_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_5__GPIO_1_5               IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS          (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_7__GPIO_1_7               IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS          (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_8__GPIO_1_8               IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5                (_MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_16__GPIO_7_11             IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23          (_MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_17__GPIO_7_12             IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2             (_MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_18__GPIO_7_13             IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          (_MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_NVCC_GPIO__NVCC_GPIO   IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__GPIO5_13          (_MX53_PAD_DISP0_DAT19__GPIO5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_POR_B__POR_B                   IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK               (_MX53_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD           (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC           (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6                (_MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_TEST_MODE__TEST_MODE   IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24          (_MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_ADDDS__GRP_ADDDS   IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3             (_MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL       IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          (_MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__GPIO5_14          (_MX53_PAD_DISP0_DAT20__GPIO5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_DDRPK__GRP_DDRPK   IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK               (_MX53_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3   IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC           (_MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7                (_MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE       IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25          (_MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_B0DS__GRP_B0DS             IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI              (_MX53_PAD_DISP0_DAT20__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_B1DS__GRP_B1DS             IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          (_MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_CTLDS__GRP_CTLDS   IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__GPIO5_15          (_MX53_PAD_DISP0_DAT21__GPIO5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE     IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI               (_MX53_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_B2DS__GRP_B2DS             IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD           (_MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GRP_B3DS__GRP_B3DS             IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0           (_MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26          (_MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO              (_MX53_PAD_DISP0_DAT21__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          (_MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__GPIO5_16          (_MX53_PAD_DISP0_DAT22__GPIO5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO               (_MX53_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS          (_MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1           (_MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27          (_MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK              (_MX53_PAD_DISP0_DAT22__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          (_MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__GPIO5_17          (_MX53_PAD_DISP0_DAT23__GPIO5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0                (_MX53_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD           (_MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2           (_MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28          (_MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS              (_MX53_PAD_DISP0_DAT23__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK           (_MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__GPIO5_18          (_MX53_PAD_CSI0_PIXCLK__GPIO5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0           (_MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29          (_MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC              (_MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__GPIO5_19            (_MX53_PAD_CSI0_MCLK__GPIO5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK               (_MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1             (_MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30            (_MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL          (_MX53_PAD_CSI0_MCLK__TPIU_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN         (_MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__GPIO5_20         (_MX53_PAD_CSI0_DATA_EN__GPIO5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2          (_MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31         (_MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK               (_MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC             (_MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__GPIO5_21           (_MX53_PAD_CSI0_VSYNC__GPIO5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3            (_MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32           (_MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0               (_MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4                (_MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__GPIO5_22            (_MX53_PAD_CSI0_DAT4__GPIO5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__KPP_COL_5           (_MX53_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK         (_MX53_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP            (_MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC             (_MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33            (_MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1                (_MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5                (_MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__GPIO5_23            (_MX53_PAD_CSI0_DAT5__GPIO5_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__KPP_ROW_5           (_MX53_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI         (_MX53_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT            (_MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD             (_MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34            (_MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2                (_MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6                (_MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__GPIO5_24            (_MX53_PAD_CSI0_DAT6__GPIO5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__KPP_COL_6           (_MX53_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO         (_MX53_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK            (_MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS            (_MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35            (_MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3                (_MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7                (_MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__GPIO5_25            (_MX53_PAD_CSI0_DAT7__GPIO5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__KPP_ROW_6           (_MX53_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0          (_MX53_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR            (_MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD             (_MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36            (_MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4                (_MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8                (_MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__GPIO5_26            (_MX53_PAD_CSI0_DAT8__GPIO5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__KPP_COL_7           (_MX53_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK         (_MX53_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC             (_MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__I2C1_SDA            (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37            (_MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5                (_MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9                (_MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__GPIO5_27            (_MX53_PAD_CSI0_DAT9__GPIO5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__KPP_ROW_7           (_MX53_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI         (_MX53_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR            (_MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__I2C1_SCL            (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38            (_MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6                (_MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10              (_MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__GPIO5_28           (_MX53_PAD_CSI0_DAT10__GPIO5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX              (_MX53_PAD_CSI0_DAT10__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO                (_MX53_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC            (_MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4            (_MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39           (_MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7               (_MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11              (_MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__GPIO5_29           (_MX53_PAD_CSI0_DAT11__GPIO5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX              (_MX53_PAD_CSI0_DAT11__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0         (_MX53_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS           (_MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5            (_MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40           (_MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8               (_MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12              (_MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__GPIO5_30           (_MX53_PAD_CSI0_DAT12__GPIO5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX              (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0                (_MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6            (_MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41           (_MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9               (_MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13              (_MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__GPIO5_31           (_MX53_PAD_CSI0_DAT13__GPIO5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX              (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1                (_MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7            (_MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42           (_MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10              (_MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14              (_MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__GPIO6_0            (_MX53_PAD_CSI0_DAT14__GPIO6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX              (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2                (_MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8            (_MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43           (_MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11              (_MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15              (_MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__GPIO6_1            (_MX53_PAD_CSI0_DAT15__GPIO6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX              (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3                (_MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9            (_MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44           (_MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12              (_MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16              (_MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__GPIO6_2            (_MX53_PAD_CSI0_DAT16__GPIO6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__UART4_RTS          (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4                (_MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10           (_MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45           (_MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13              (_MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17              (_MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__GPIO6_3            (_MX53_PAD_CSI0_DAT17__GPIO6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__UART4_CTS          (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5                (_MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11           (_MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46           (_MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14              (_MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18              (_MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__GPIO6_4            (_MX53_PAD_CSI0_DAT18__GPIO6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__UART5_RTS          (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6                (_MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12           (_MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47           (_MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15              (_MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19              (_MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__GPIO6_5            (_MX53_PAD_CSI0_DAT19__GPIO6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__UART5_CTS          (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7                (_MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13           (_MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48           (_MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK             (_MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__EMI_WEIM_A_25         (_MX53_PAD_EIM_A25__EMI_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__GPIO5_2               (_MX53_PAD_EIM_A25__GPIO5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__ECSPI2_RDY            (_MX53_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__IPU_DI1_PIN12         (_MX53_PAD_EIM_A25__IPU_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__CSPI_SS1              (_MX53_PAD_EIM_A25__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS         (_MX53_PAD_EIM_A25__IPU_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__USBPHY1_BISTOK                (_MX53_PAD_EIM_A25__USBPHY1_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2         (_MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__GPIO2_30              (_MX53_PAD_EIM_EB2__GPIO2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK               (_MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS              (_MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__ECSPI1_SS0            (_MX53_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__I2C2_SCL              (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__EMI_WEIM_D_16         (_MX53_PAD_EIM_D16__EMI_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__GPIO3_16              (_MX53_PAD_EIM_D16__GPIO3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__IPU_DI0_PIN5          (_MX53_PAD_EIM_D16__IPU_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK            (_MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__ECSPI1_SCLK           (_MX53_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__I2C2_SDA              (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__EMI_WEIM_D_17         (_MX53_PAD_EIM_D17__EMI_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__GPIO3_17              (_MX53_PAD_EIM_D17__GPIO3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__IPU_DI0_PIN6          (_MX53_PAD_EIM_D17__IPU_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN            (_MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__ECSPI1_MISO           (_MX53_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__I2C3_SCL              (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__EMI_WEIM_D_18         (_MX53_PAD_EIM_D18__EMI_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__GPIO3_18              (_MX53_PAD_EIM_D18__GPIO3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__IPU_DI0_PIN7          (_MX53_PAD_EIM_D18__IPU_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO            (_MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__ECSPI1_MOSI           (_MX53_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__I2C3_SDA              (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS         (_MX53_PAD_EIM_D18__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__EMI_WEIM_D_19         (_MX53_PAD_EIM_D19__EMI_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__GPIO3_19              (_MX53_PAD_EIM_D19__GPIO3_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__IPU_DI0_PIN8          (_MX53_PAD_EIM_D19__IPU_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS             (_MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__ECSPI1_SS1            (_MX53_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__EPIT1_EPITO           (_MX53_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__UART1_CTS             (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC               (_MX53_PAD_EIM_D19__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__EMI_WEIM_D_20         (_MX53_PAD_EIM_D20__EMI_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__GPIO3_20              (_MX53_PAD_EIM_D20__GPIO3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__IPU_DI0_PIN16         (_MX53_PAD_EIM_D20__IPU_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS              (_MX53_PAD_EIM_D20__IPU_SER_DISP0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__CSPI_SS0              (_MX53_PAD_EIM_D20__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__EPIT2_EPITO           (_MX53_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__UART1_RTS             (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR              (_MX53_PAD_EIM_D20__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__EMI_WEIM_D_21         (_MX53_PAD_EIM_D21__EMI_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__GPIO3_21              (_MX53_PAD_EIM_D21__GPIO3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__IPU_DI0_PIN17         (_MX53_PAD_EIM_D21__IPU_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK            (_MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__CSPI_SCLK             (_MX53_PAD_EIM_D21__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__I2C1_SCL              (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC              (_MX53_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__EMI_WEIM_D_22         (_MX53_PAD_EIM_D22__EMI_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__GPIO3_22              (_MX53_PAD_EIM_D22__GPIO3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__IPU_DI0_PIN1          (_MX53_PAD_EIM_D22__IPU_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN            (_MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__CSPI_MISO             (_MX53_PAD_EIM_D22__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR             (_MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__EMI_WEIM_D_23         (_MX53_PAD_EIM_D23__EMI_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__GPIO3_23              (_MX53_PAD_EIM_D23__GPIO3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__UART3_CTS             (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__UART1_DCD             (_MX53_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS         (_MX53_PAD_EIM_D23__IPU_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN2          (_MX53_PAD_EIM_D23__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN              (_MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN14         (_MX53_PAD_EIM_D23__IPU_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3         (_MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__GPIO2_31              (_MX53_PAD_EIM_EB3__GPIO2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__UART3_RTS             (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__UART1_RI              (_MX53_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3          (_MX53_PAD_EIM_EB3__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC                (_MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16         (_MX53_PAD_EIM_EB3__IPU_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__EMI_WEIM_D_24         (_MX53_PAD_EIM_D24__EMI_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__GPIO3_24              (_MX53_PAD_EIM_D24__GPIO3_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__UART3_TXD_MUX         (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__ECSPI1_SS2            (_MX53_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__CSPI_SS2              (_MX53_PAD_EIM_D24__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS              (_MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__ECSPI2_SS2            (_MX53_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__UART1_DTR             (_MX53_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__EMI_WEIM_D_25         (_MX53_PAD_EIM_D25__EMI_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__GPIO3_25              (_MX53_PAD_EIM_D25__GPIO3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__UART3_RXD_MUX         (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__ECSPI1_SS3            (_MX53_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__CSPI_SS3              (_MX53_PAD_EIM_D25__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC               (_MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__ECSPI2_SS3            (_MX53_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__UART1_DSR             (_MX53_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__EMI_WEIM_D_26         (_MX53_PAD_EIM_D26__EMI_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__GPIO3_26              (_MX53_PAD_EIM_D26__GPIO3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__UART2_TXD_MUX         (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__FIRI_RXD              (_MX53_PAD_EIM_D26__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_CSI0_D_1          (_MX53_PAD_EIM_D26__IPU_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_DI1_PIN11         (_MX53_PAD_EIM_D26__IPU_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_SISG_2            (_MX53_PAD_EIM_D26__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22              (_MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__EMI_WEIM_D_27         (_MX53_PAD_EIM_D27__EMI_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__GPIO3_27              (_MX53_PAD_EIM_D27__GPIO3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__UART2_RXD_MUX         (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__FIRI_TXD              (_MX53_PAD_EIM_D27__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_CSI0_D_0          (_MX53_PAD_EIM_D27__IPU_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_DI1_PIN13         (_MX53_PAD_EIM_D27__IPU_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_SISG_3            (_MX53_PAD_EIM_D27__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23              (_MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__EMI_WEIM_D_28         (_MX53_PAD_EIM_D28__EMI_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__GPIO3_28              (_MX53_PAD_EIM_D28__GPIO3_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__UART2_CTS             (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO            (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__CSPI_MOSI             (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__I2C1_SDA              (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__IPU_EXT_TRIG          (_MX53_PAD_EIM_D28__IPU_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__IPU_DI0_PIN13         (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__EMI_WEIM_D_29         (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__GPIO3_29              (_MX53_PAD_EIM_D29__GPIO3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__UART2_RTS             (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS             (_MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__CSPI_SS0              (_MX53_PAD_EIM_D29__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_DI1_PIN15         (_MX53_PAD_EIM_D29__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC                (_MX53_PAD_EIM_D29__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_DI0_PIN14         (_MX53_PAD_EIM_D29__IPU_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__EMI_WEIM_D_30         (_MX53_PAD_EIM_D30__EMI_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__GPIO3_30              (_MX53_PAD_EIM_D30__GPIO3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__UART3_CTS             (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__IPU_CSI0_D_3          (_MX53_PAD_EIM_D30__IPU_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__IPU_DI0_PIN11         (_MX53_PAD_EIM_D30__IPU_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21              (_MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC               (_MX53_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC               (_MX53_PAD_EIM_D30__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__EMI_WEIM_D_31         (_MX53_PAD_EIM_D31__EMI_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__GPIO3_31              (_MX53_PAD_EIM_D31__GPIO3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__UART3_RTS             (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__IPU_CSI0_D_2          (_MX53_PAD_EIM_D31__IPU_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__IPU_DI0_PIN12         (_MX53_PAD_EIM_D31__IPU_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20              (_MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR              (_MX53_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR              (_MX53_PAD_EIM_D31__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__EMI_WEIM_A_24         (_MX53_PAD_EIM_A24__EMI_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__GPIO5_4               (_MX53_PAD_EIM_A24__GPIO5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19              (_MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__IPU_CSI1_D_19         (_MX53_PAD_EIM_A24__IPU_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__IPU_SISG_2            (_MX53_PAD_EIM_A24__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__USBPHY2_BVALID                (_MX53_PAD_EIM_A24__USBPHY2_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__EMI_WEIM_A_23         (_MX53_PAD_EIM_A23__EMI_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__GPIO6_6               (_MX53_PAD_EIM_A23__GPIO6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18              (_MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__IPU_CSI1_D_18         (_MX53_PAD_EIM_A23__IPU_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__IPU_SISG_3            (_MX53_PAD_EIM_A23__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION            (_MX53_PAD_EIM_A23__USBPHY2_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__EMI_WEIM_A_22         (_MX53_PAD_EIM_A22__EMI_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__GPIO2_16              (_MX53_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17              (_MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__IPU_CSI1_D_17         (_MX53_PAD_EIM_A22__IPU_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7         (_MX53_PAD_EIM_A22__SRC_BT_CFG1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__EMI_WEIM_A_21         (_MX53_PAD_EIM_A21__EMI_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__GPIO2_17              (_MX53_PAD_EIM_A21__GPIO2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16              (_MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__IPU_CSI1_D_16         (_MX53_PAD_EIM_A21__IPU_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6         (_MX53_PAD_EIM_A21__SRC_BT_CFG1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__EMI_WEIM_A_20         (_MX53_PAD_EIM_A20__EMI_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__GPIO2_18              (_MX53_PAD_EIM_A20__GPIO2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15              (_MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__IPU_CSI1_D_15         (_MX53_PAD_EIM_A20__IPU_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5         (_MX53_PAD_EIM_A20__SRC_BT_CFG1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__EMI_WEIM_A_19         (_MX53_PAD_EIM_A19__EMI_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__GPIO2_19              (_MX53_PAD_EIM_A19__GPIO2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14              (_MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__IPU_CSI1_D_14         (_MX53_PAD_EIM_A19__IPU_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4         (_MX53_PAD_EIM_A19__SRC_BT_CFG1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__EMI_WEIM_A_18         (_MX53_PAD_EIM_A18__EMI_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__GPIO2_20              (_MX53_PAD_EIM_A18__GPIO2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13              (_MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__IPU_CSI1_D_13         (_MX53_PAD_EIM_A18__IPU_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3         (_MX53_PAD_EIM_A18__SRC_BT_CFG1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__EMI_WEIM_A_17         (_MX53_PAD_EIM_A17__EMI_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__GPIO2_21              (_MX53_PAD_EIM_A17__GPIO2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12              (_MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__IPU_CSI1_D_12         (_MX53_PAD_EIM_A17__IPU_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2         (_MX53_PAD_EIM_A17__SRC_BT_CFG1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__EMI_WEIM_A_16         (_MX53_PAD_EIM_A16__EMI_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__GPIO2_22              (_MX53_PAD_EIM_A16__GPIO2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK              (_MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK               (_MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1         (_MX53_PAD_EIM_A16__SRC_BT_CFG1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0         (_MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__GPIO2_23              (_MX53_PAD_EIM_CS0__GPIO2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__ECSPI2_SCLK           (_MX53_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5          (_MX53_PAD_EIM_CS0__IPU_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1         (_MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__GPIO2_24              (_MX53_PAD_EIM_CS1__GPIO2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__ECSPI2_MOSI           (_MX53_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6          (_MX53_PAD_EIM_CS1__IPU_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__EMI_WEIM_OE            (_MX53_PAD_EIM_OE__EMI_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__GPIO2_25               (_MX53_PAD_EIM_OE__GPIO2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__ECSPI2_MISO            (_MX53_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__IPU_DI1_PIN7           (_MX53_PAD_EIM_OE__IPU_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__USBPHY2_IDDIG          (_MX53_PAD_EIM_OE__USBPHY2_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__EMI_WEIM_RW            (_MX53_PAD_EIM_RW__EMI_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__GPIO2_26               (_MX53_PAD_EIM_RW__GPIO2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__ECSPI2_SS0             (_MX53_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__IPU_DI1_PIN8           (_MX53_PAD_EIM_RW__IPU_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT         (_MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA          (_MX53_PAD_EIM_LBA__EMI_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__GPIO2_27              (_MX53_PAD_EIM_LBA__GPIO2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__ECSPI2_SS1            (_MX53_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17         (_MX53_PAD_EIM_LBA__IPU_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0         (_MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0         (_MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__GPIO2_28              (_MX53_PAD_EIM_EB0__GPIO2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11              (_MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11         (_MX53_PAD_EIM_EB0__IPU_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY          (_MX53_PAD_EIM_EB0__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7         (_MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1         (_MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__GPIO2_29              (_MX53_PAD_EIM_EB1__GPIO2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10              (_MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10         (_MX53_PAD_EIM_EB1__IPU_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6         (_MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0            (_MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__GPIO3_0               (_MX53_PAD_EIM_DA0__GPIO3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9               (_MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9          (_MX53_PAD_EIM_DA0__IPU_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5         (_MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1            (_MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__GPIO3_1               (_MX53_PAD_EIM_DA1__GPIO3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8               (_MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8          (_MX53_PAD_EIM_DA1__IPU_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4         (_MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2            (_MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__GPIO3_2               (_MX53_PAD_EIM_DA2__GPIO3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7               (_MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7          (_MX53_PAD_EIM_DA2__IPU_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3         (_MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3            (_MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__GPIO3_3               (_MX53_PAD_EIM_DA3__GPIO3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6               (_MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6          (_MX53_PAD_EIM_DA3__IPU_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2         (_MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4            (_MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__GPIO3_4               (_MX53_PAD_EIM_DA4__GPIO3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5               (_MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5          (_MX53_PAD_EIM_DA4__IPU_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7         (_MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5            (_MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__GPIO3_5               (_MX53_PAD_EIM_DA5__GPIO3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4               (_MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4          (_MX53_PAD_EIM_DA5__IPU_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6         (_MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6            (_MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__GPIO3_6               (_MX53_PAD_EIM_DA6__GPIO3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3               (_MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3          (_MX53_PAD_EIM_DA6__IPU_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5         (_MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7            (_MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__GPIO3_7               (_MX53_PAD_EIM_DA7__GPIO3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2               (_MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2          (_MX53_PAD_EIM_DA7__IPU_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4         (_MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8            (_MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__GPIO3_8               (_MX53_PAD_EIM_DA8__GPIO3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1               (_MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1          (_MX53_PAD_EIM_DA8__IPU_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3         (_MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9            (_MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__GPIO3_9               (_MX53_PAD_EIM_DA9__GPIO3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0               (_MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0          (_MX53_PAD_EIM_DA9__IPU_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2         (_MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10          (_MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__GPIO3_10             (_MX53_PAD_EIM_DA10__GPIO3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15                (_MX53_PAD_EIM_DA10__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN             (_MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1                (_MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11          (_MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__GPIO3_11             (_MX53_PAD_EIM_DA11__GPIO3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2         (_MX53_PAD_EIM_DA11__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC               (_MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12          (_MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__GPIO3_12             (_MX53_PAD_EIM_DA12__GPIO3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3         (_MX53_PAD_EIM_DA12__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC               (_MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13          (_MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__GPIO3_13             (_MX53_PAD_EIM_DA13__GPIO3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS                (_MX53_PAD_EIM_DA13__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK              (_MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14          (_MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__GPIO3_14             (_MX53_PAD_EIM_DA14__GPIO3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS                (_MX53_PAD_EIM_DA14__IPU_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK              (_MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15          (_MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__GPIO3_15             (_MX53_PAD_EIM_DA15__GPIO3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1         (_MX53_PAD_EIM_DA15__IPU_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4         (_MX53_PAD_EIM_DA15__IPU_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B             (_MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WE_B__GPIO6_12           (_MX53_PAD_NANDF_WE_B__GPIO6_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B             (_MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RE_B__GPIO6_13           (_MX53_PAD_NANDF_RE_B__GPIO6_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT                (_MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_WAIT__GPIO5_0              (_MX53_PAD_EIM_WAIT__GPIO5_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B             (_MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX3_P__GPIO6_22          (_MX53_PAD_LVDS1_TX3_P__GPIO6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3             (_MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX2_P__GPIO6_24          (_MX53_PAD_LVDS1_TX2_P__GPIO6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2             (_MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_CLK_P__GPIO6_26          (_MX53_PAD_LVDS1_CLK_P__GPIO6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK             (_MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX1_P__GPIO6_28          (_MX53_PAD_LVDS1_TX1_P__GPIO6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1             (_MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX0_P__GPIO6_30          (_MX53_PAD_LVDS1_TX0_P__GPIO6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0             (_MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX3_P__GPIO7_22          (_MX53_PAD_LVDS0_TX3_P__GPIO7_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3             (_MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_CLK_P__GPIO7_24          (_MX53_PAD_LVDS0_CLK_P__GPIO7_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK             (_MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX2_P__GPIO7_26          (_MX53_PAD_LVDS0_TX2_P__GPIO7_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2             (_MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX1_P__GPIO7_28          (_MX53_PAD_LVDS0_TX1_P__GPIO7_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1             (_MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX0_P__GPIO7_30          (_MX53_PAD_LVDS0_TX0_P__GPIO7_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0             (_MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_10__GPIO4_0               (_MX53_PAD_GPIO_10__GPIO4_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_10__OSC32k_32K_OUT                (_MX53_PAD_GPIO_10__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_11__GPIO4_1               (_MX53_PAD_GPIO_11__GPIO4_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_12__GPIO4_2               (_MX53_PAD_GPIO_12__GPIO4_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_13__GPIO4_3               (_MX53_PAD_GPIO_13__GPIO4_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_14__GPIO4_4               (_MX53_PAD_GPIO_14__GPIO4_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE               (_MX53_PAD_NANDF_CLE__EMI_NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CLE__GPIO6_7             (_MX53_PAD_NANDF_CLE__GPIO6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0           (_MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE               (_MX53_PAD_NANDF_ALE__EMI_NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_ALE__GPIO6_8             (_MX53_PAD_NANDF_ALE__GPIO6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1           (_MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B             (_MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WP_B__GPIO6_9            (_MX53_PAD_NANDF_WP_B__GPIO6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2          (_MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0              (_MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RB0__GPIO6_10            (_MX53_PAD_NANDF_RB0__GPIO6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3           (_MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0              (_MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS0__GPIO6_11            (_MX53_PAD_NANDF_CS0__GPIO6_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4           (_MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1              (_MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__GPIO6_14            (_MX53_PAD_NANDF_CS1__GPIO6_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__MLB_MLBCLK          (_MX53_PAD_NANDF_CS1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5           (_MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2              (_MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__GPIO6_15            (_MX53_PAD_NANDF_CS2__GPIO6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__IPU_SISG_0          (_MX53_PAD_NANDF_CS2__IPU_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__ESAI1_TX0           (_MX53_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE                (_MX53_PAD_NANDF_CS2__EMI_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK               (_MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__MLB_MLBSIG          (_MX53_PAD_NANDF_CS2__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6           (_MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3              (_MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__GPIO6_16            (_MX53_PAD_NANDF_CS3__GPIO6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__IPU_SISG_1          (_MX53_PAD_NANDF_CS3__IPU_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__ESAI1_TX1           (_MX53_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26               (_MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__MLB_MLBDAT          (_MX53_PAD_NANDF_CS3__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7           (_MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__FEC_MDIO             (_MX53_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__GPIO1_22             (_MX53_PAD_FEC_MDIO__GPIO1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__ESAI1_SCKR           (_MX53_PAD_FEC_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__FEC_COL              (_MX53_PAD_FEC_MDIO__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2               (_MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3              (_MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49             (_MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK                (_MX53_PAD_FEC_REF_CLK__FEC_TX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__GPIO1_23          (_MX53_PAD_FEC_REF_CLK__GPIO1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR         (_MX53_PAD_FEC_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4           (_MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50          (_MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__FEC_RX_ER           (_MX53_PAD_FEC_RX_ER__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__GPIO1_24            (_MX53_PAD_FEC_RX_ER__GPIO1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR          (_MX53_PAD_FEC_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK          (_MX53_PAD_FEC_RX_ER__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3              (_MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV          (_MX53_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_CRS_DV__GPIO1_25           (_MX53_PAD_FEC_CRS_DV__GPIO1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT         (_MX53_PAD_FEC_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__FEC_RDATA_1          (_MX53_PAD_FEC_RXD1__FEC_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__GPIO1_26             (_MX53_PAD_FEC_RXD1__GPIO1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__ESAI1_FST            (_MX53_PAD_FEC_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__MLB_MLBSIG           (_MX53_PAD_FEC_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1               (_MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__FEC_RDATA_0          (_MX53_PAD_FEC_RXD0__FEC_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__GPIO1_27             (_MX53_PAD_FEC_RXD0__GPIO1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__ESAI1_HCKT           (_MX53_PAD_FEC_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT               (_MX53_PAD_FEC_RXD0__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TX_EN__FEC_TX_EN           (_MX53_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TX_EN__GPIO1_28            (_MX53_PAD_FEC_TX_EN__GPIO1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2               (_MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__FEC_TDATA_1          (_MX53_PAD_FEC_TXD1__FEC_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__GPIO1_29             (_MX53_PAD_FEC_TXD1__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3                (_MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__MLB_MLBCLK           (_MX53_PAD_FEC_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK          (_MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__FEC_TDATA_0          (_MX53_PAD_FEC_TXD0__FEC_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__GPIO1_30             (_MX53_PAD_FEC_TXD0__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1                (_MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0            (_MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__FEC_MDC               (_MX53_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__GPIO1_31              (_MX53_PAD_FEC_MDC__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0         (_MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__MLB_MLBDAT            (_MX53_PAD_FEC_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG                (_MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1             (_MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__PATA_DIOW           (_MX53_PAD_PATA_DIOW__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__GPIO6_17            (_MX53_PAD_PATA_DIOW__GPIO6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX               (_MX53_PAD_PATA_DIOW__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2           (_MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__PATA_DMACK         (_MX53_PAD_PATA_DMACK__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__GPIO6_18           (_MX53_PAD_PATA_DMACK__GPIO6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX              (_MX53_PAD_PATA_DMACK__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3          (_MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__PATA_DMARQ         (_MX53_PAD_PATA_DMARQ__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__GPIO7_0            (_MX53_PAD_PATA_DMARQ__GPIO7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX              (_MX53_PAD_PATA_DMARQ__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0              (_MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4          (_MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN         (_MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1                (_MX53_PAD_PATA_BUFFER_EN__GPIO7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX          (_MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1          (_MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5              (_MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__PATA_INTRQ         (_MX53_PAD_PATA_INTRQ__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__GPIO7_2            (_MX53_PAD_PATA_INTRQ__GPIO7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__UART2_CTS          (_MX53_PAD_PATA_INTRQ__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN         (_MX53_PAD_PATA_INTRQ__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2              (_MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6          (_MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__PATA_DIOR           (_MX53_PAD_PATA_DIOR__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__GPIO7_3             (_MX53_PAD_PATA_DIOR__GPIO7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__UART2_RTS           (_MX53_PAD_PATA_DIOR__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__CAN1_RXCAN          (_MX53_PAD_PATA_DIOR__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7           (_MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B                (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__GPIO7_4          (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD               (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__UART1_CTS                (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN               (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0                (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__PATA_IORDY         (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__GPIO7_5            (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__ESDHC3_CLK         (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__UART1_RTS          (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__CAN2_RXCAN         (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1          (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__PATA_DA_0           (_MX53_PAD_PATA_DA_0__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__GPIO7_6             (_MX53_PAD_PATA_DA_0__GPIO7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__ESDHC3_RST          (_MX53_PAD_PATA_DA_0__ESDHC3_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__OWIRE_LINE          (_MX53_PAD_PATA_DA_0__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2           (_MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__PATA_DA_1           (_MX53_PAD_PATA_DA_1__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__GPIO7_7             (_MX53_PAD_PATA_DA_1__GPIO7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__ESDHC4_CMD          (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__UART3_CTS           (_MX53_PAD_PATA_DA_1__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3           (_MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__PATA_DA_2           (_MX53_PAD_PATA_DA_2__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__GPIO7_8             (_MX53_PAD_PATA_DA_2__GPIO7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__ESDHC4_CLK          (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__UART3_RTS           (_MX53_PAD_PATA_DA_2__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4           (_MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__PATA_CS_0           (_MX53_PAD_PATA_CS_0__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__GPIO7_9             (_MX53_PAD_PATA_CS_0__GPIO7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX               (_MX53_PAD_PATA_CS_0__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5           (_MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__PATA_CS_1           (_MX53_PAD_PATA_CS_1__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__GPIO7_10            (_MX53_PAD_PATA_CS_1__GPIO7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX               (_MX53_PAD_PATA_CS_1__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6           (_MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__PATA_DATA_0                (_MX53_PAD_PATA_DATA0__PATA_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__GPIO2_0            (_MX53_PAD_PATA_DATA0__GPIO2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0              (_MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4                (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0              (_MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0             (_MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7          (_MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__PATA_DATA_1                (_MX53_PAD_PATA_DATA1__PATA_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__GPIO2_1            (_MX53_PAD_PATA_DATA1__GPIO2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1              (_MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5                (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1              (_MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1             (_MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__PATA_DATA_2                (_MX53_PAD_PATA_DATA2__PATA_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__GPIO2_2            (_MX53_PAD_PATA_DATA2__GPIO2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2              (_MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6                (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2              (_MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2             (_MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__PATA_DATA_3                (_MX53_PAD_PATA_DATA3__PATA_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__GPIO2_3            (_MX53_PAD_PATA_DATA3__GPIO2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3              (_MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7                (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3              (_MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3             (_MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__PATA_DATA_4                (_MX53_PAD_PATA_DATA4__PATA_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__GPIO2_4            (_MX53_PAD_PATA_DATA4__GPIO2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4              (_MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4                (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4              (_MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4             (_MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__PATA_DATA_5                (_MX53_PAD_PATA_DATA5__PATA_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__GPIO2_5            (_MX53_PAD_PATA_DATA5__GPIO2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5              (_MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5                (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5              (_MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5             (_MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__PATA_DATA_6                (_MX53_PAD_PATA_DATA6__PATA_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__GPIO2_6            (_MX53_PAD_PATA_DATA6__GPIO2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6              (_MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6                (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6              (_MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6             (_MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__PATA_DATA_7                (_MX53_PAD_PATA_DATA7__PATA_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__GPIO2_7            (_MX53_PAD_PATA_DATA7__GPIO2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7              (_MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7                (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7              (_MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7             (_MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__PATA_DATA_8                (_MX53_PAD_PATA_DATA8__PATA_DATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__GPIO2_8            (_MX53_PAD_PATA_DATA8__GPIO2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4                (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8              (_MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0                (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8              (_MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8             (_MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__PATA_DATA_9                (_MX53_PAD_PATA_DATA9__PATA_DATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__GPIO2_9            (_MX53_PAD_PATA_DATA9__GPIO2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5                (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9              (_MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1                (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9              (_MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9             (_MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__PATA_DATA_10              (_MX53_PAD_PATA_DATA10__PATA_DATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__GPIO2_10          (_MX53_PAD_PATA_DATA10__GPIO2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6               (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10            (_MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2               (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10            (_MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10           (_MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__PATA_DATA_11              (_MX53_PAD_PATA_DATA11__PATA_DATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__GPIO2_11          (_MX53_PAD_PATA_DATA11__GPIO2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7               (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11            (_MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3               (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11            (_MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11           (_MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__PATA_DATA_12              (_MX53_PAD_PATA_DATA12__PATA_DATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__GPIO2_12          (_MX53_PAD_PATA_DATA12__GPIO2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4               (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12            (_MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0               (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12            (_MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12           (_MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__PATA_DATA_13              (_MX53_PAD_PATA_DATA13__PATA_DATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__GPIO2_13          (_MX53_PAD_PATA_DATA13__GPIO2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5               (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13            (_MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1               (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13            (_MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13           (_MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__PATA_DATA_14              (_MX53_PAD_PATA_DATA14__PATA_DATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__GPIO2_14          (_MX53_PAD_PATA_DATA14__GPIO2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6               (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14            (_MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2               (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14            (_MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14           (_MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__PATA_DATA_15              (_MX53_PAD_PATA_DATA15__PATA_DATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__GPIO2_15          (_MX53_PAD_PATA_DATA15__GPIO2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7               (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15            (_MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3               (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15            (_MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15           (_MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0         (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__GPIO1_16            (_MX53_PAD_SD1_DATA0__GPIO1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__GPT_CAPIN1          (_MX53_PAD_SD1_DATA0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__CSPI_MISO           (_MX53_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP                (_MX53_PAD_SD1_DATA0__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1         (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__GPIO1_17            (_MX53_PAD_SD1_DATA1__GPIO1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__GPT_CAPIN2          (_MX53_PAD_SD1_DATA1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__CSPI_SS0            (_MX53_PAD_SD1_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP                (_MX53_PAD_SD1_DATA1__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__ESDHC1_CMD            (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__GPIO1_18              (_MX53_PAD_SD1_CMD__GPIO1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__GPT_CMPOUT1           (_MX53_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__CSPI_MOSI             (_MX53_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP          (_MX53_PAD_SD1_CMD__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2         (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__GPIO1_19            (_MX53_PAD_SD1_DATA2__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2         (_MX53_PAD_SD1_DATA2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__PWM2_PWMO           (_MX53_PAD_SD1_DATA2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B                (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__CSPI_SS1            (_MX53_PAD_SD1_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB                (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP                (_MX53_PAD_SD1_DATA2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__ESDHC1_CLK            (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__GPIO1_20              (_MX53_PAD_SD1_CLK__GPIO1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT                (_MX53_PAD_SD1_CLK__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__GPT_CLKIN             (_MX53_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__CSPI_SCLK             (_MX53_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0                (_MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3         (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__GPIO1_21            (_MX53_PAD_SD1_DATA3__GPIO1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3         (_MX53_PAD_SD1_DATA3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__PWM1_PWMO           (_MX53_PAD_SD1_DATA3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B                (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__CSPI_SS2            (_MX53_PAD_SD1_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB                (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1              (_MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__ESDHC2_CLK            (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__GPIO1_10              (_MX53_PAD_SD2_CLK__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__KPP_COL_5             (_MX53_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS              (_MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__CSPI_SCLK             (_MX53_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__SCC_RANDOM_V          (_MX53_PAD_SD2_CLK__SCC_RANDOM_V | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__ESDHC2_CMD            (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__GPIO1_11              (_MX53_PAD_SD2_CMD__GPIO1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__KPP_ROW_5             (_MX53_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC               (_MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__CSPI_MOSI             (_MX53_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__SCC_RANDOM            (_MX53_PAD_SD2_CMD__SCC_RANDOM | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3         (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__GPIO1_12            (_MX53_PAD_SD2_DATA3__GPIO1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__KPP_COL_6           (_MX53_PAD_SD2_DATA3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC             (_MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__CSPI_SS2            (_MX53_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__SJC_DONE            (_MX53_PAD_SD2_DATA3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2         (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__GPIO1_13            (_MX53_PAD_SD2_DATA2__GPIO1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__KPP_ROW_6           (_MX53_PAD_SD2_DATA2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD             (_MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__CSPI_SS1            (_MX53_PAD_SD2_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__SJC_FAIL            (_MX53_PAD_SD2_DATA2__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1         (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__GPIO1_14            (_MX53_PAD_SD2_DATA1__GPIO1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__KPP_COL_7           (_MX53_PAD_SD2_DATA1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS            (_MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__CSPI_SS0            (_MX53_PAD_SD2_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO                (_MX53_PAD_SD2_DATA1__RTIC_SEC_VIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0         (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__GPIO1_15            (_MX53_PAD_SD2_DATA0__GPIO1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__KPP_ROW_7           (_MX53_PAD_SD2_DATA0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD             (_MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__CSPI_MISO           (_MX53_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT               (_MX53_PAD_SD2_DATA0__RTIC_DONE_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__CCM_CLKO               (_MX53_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__GPIO1_0                (_MX53_PAD_GPIO_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__KPP_COL_5              (_MX53_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK               (_MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__EPIT1_EPITO            (_MX53_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB         (_MX53_PAD_GPIO_0__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR               (_MX53_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__CSU_TD         (_MX53_PAD_GPIO_0__CSU_TD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__ESAI1_SCKR             (_MX53_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__GPIO1_1                (_MX53_PAD_GPIO_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__KPP_ROW_5              (_MX53_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK               (_MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__PWM2_PWMO              (_MX53_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__WDOG2_WDOG_B           (_MX53_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__ESDHC1_CD              (_MX53_PAD_GPIO_1__ESDHC1_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__SRC_TESTER_ACK         (_MX53_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__ESAI1_FSR              (_MX53_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__GPIO1_9                (_MX53_PAD_GPIO_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__KPP_COL_6              (_MX53_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__CCM_REF_EN_B           (_MX53_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__PWM1_PWMO              (_MX53_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__WDOG1_WDOG_B           (_MX53_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__ESDHC1_WP              (_MX53_PAD_GPIO_9__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__SCC_FAIL_STATE         (_MX53_PAD_GPIO_9__SCC_FAIL_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__ESAI1_HCKR             (_MX53_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__GPIO1_3                (_MX53_PAD_GPIO_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__I2C3_SCL               (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN         (_MX53_PAD_GPIO_3__DPLLIP1_TOG_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__CCM_CLKO2              (_MX53_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0             (_MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC                (_MX53_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__MLB_MLBCLK             (_MX53_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__ESAI1_SCKT             (_MX53_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__GPIO1_6                (_MX53_PAD_GPIO_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__I2C3_SDA               (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0          (_MX53_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB                (_MX53_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1             (_MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__ESDHC2_LCTL            (_MX53_PAD_GPIO_6__ESDHC2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__MLB_MLBSIG             (_MX53_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__ESAI1_FST              (_MX53_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__GPIO1_2                (_MX53_PAD_GPIO_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__KPP_ROW_6              (_MX53_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1          (_MX53_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0            (_MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2             (_MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__ESDHC2_WP              (_MX53_PAD_GPIO_2__ESDHC2_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__MLB_MLBDAT             (_MX53_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__ESAI1_HCKT             (_MX53_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__GPIO1_4                (_MX53_PAD_GPIO_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__KPP_COL_7              (_MX53_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2          (_MX53_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1            (_MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3             (_MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__ESDHC2_CD              (_MX53_PAD_GPIO_4__ESDHC2_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__SCC_SEC_STATE          (_MX53_PAD_GPIO_4__SCC_SEC_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3          (_MX53_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__GPIO1_5                (_MX53_PAD_GPIO_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__KPP_ROW_7              (_MX53_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__CCM_CLKO               (_MX53_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2            (_MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4             (_MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__I2C3_SCL               (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__CCM_PLL1_BYP           (_MX53_PAD_GPIO_5__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1          (_MX53_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__GPIO1_7                (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__EPIT1_EPITO            (_MX53_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__CAN1_TXCAN             (_MX53_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__UART2_TXD_MUX          (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__FIRI_RXD               (_MX53_PAD_GPIO_7__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__SPDIF_PLOCK            (_MX53_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__CCM_PLL2_BYP           (_MX53_PAD_GPIO_7__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0          (_MX53_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__GPIO1_8                (_MX53_PAD_GPIO_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__EPIT2_EPITO            (_MX53_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__CAN1_RXCAN             (_MX53_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__UART2_RXD_MUX          (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__FIRI_TXD               (_MX53_PAD_GPIO_8__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__SPDIF_SRCLK            (_MX53_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__CCM_PLL3_BYP           (_MX53_PAD_GPIO_8__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2         (_MX53_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__GPIO7_11              (_MX53_PAD_GPIO_16__GPIO7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT              (_MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1          (_MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__SPDIF_IN1             (_MX53_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__I2C3_SDA              (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__SJC_DE_B              (_MX53_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__ESAI1_TX0             (_MX53_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__GPIO7_12              (_MX53_PAD_GPIO_17__GPIO7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0              (_MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__GPC_PMIC_RDY          (_MX53_PAD_GPIO_17__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG           (_MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__SPDIF_OUT1            (_MX53_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__IPU_SNOOP2            (_MX53_PAD_GPIO_17__IPU_SNOOP2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__SJC_JTAG_ACT          (_MX53_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__ESAI1_TX1             (_MX53_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__GPIO7_13              (_MX53_PAD_GPIO_18__GPIO7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1              (_MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__OWIRE_LINE            (_MX53_PAD_GPIO_18__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG                (_MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK              (_MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__ESDHC1_LCTL           (_MX53_PAD_GPIO_18__ESDHC1_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST                (_MX53_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
 #endif  /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 15d59510f597..bf28df0d58b7 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -46,12 +46,12 @@
 *      - setups the iomux according to the configuration
 *      - if the pin is configured as a GPIO, we claim it through kernel gpiolib
 */
-int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label);
+int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label);
 /*
 * setups mutliple pins
 * convenient way to call the above function with tables
 */
-int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
                const char *label);
 /*
@@ -60,12 +60,12 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
 *      - frees the GPIO if the pin was configured as GPIO
 *      - DOES NOT reconfigure the IOMUX in its reset state
 */
-void mxc_iomux_release_pin(const unsigned int pin_mode);
+void mxc_iomux_release_pin(unsigned int pin_mode);
 /*
 * releases multiple pins
 * convenvient way to call the above function with tables
 */
-void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
+void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
 #define MUX_SIDE_AP             (0)
 #define MUX_SIDE_SP             (1)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index 884f5753f279..c07d30210c57 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -100,4 +100,6 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
                const char *label);
 extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
+extern int __init imx_iomuxv1_init(void __iomem *base, int numports);
 #endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index ba65c9231a78..a3d930d3e65d 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -23,17 +23,17 @@
 #define MXC_GPIO_IRQ_START      MXC_INTERNAL_IRQS
 /* these are ordered by size to support multi-SoC kernels */
-#if defined CONFIG_ARCH_MX53
+#if defined CONFIG_SOC_IMX53
 #define MXC_GPIO_IRQS           (32 * 7)
 #elif defined CONFIG_ARCH_MX2
 #define MXC_GPIO_IRQS           (32 * 6)
-#elif defined CONFIG_ARCH_MX50
+#elif defined CONFIG_SOC_IMX50
 #define MXC_GPIO_IRQS           (32 * 6)
 #elif defined CONFIG_ARCH_MX1
 #define MXC_GPIO_IRQS           (32 * 4)
 #elif defined CONFIG_ARCH_MX25
 #define MXC_GPIO_IRQS           (32 * 4)
-#elif defined CONFIG_ARCH_MX51
+#elif defined CONFIG_SOC_IMX51
 #define MXC_GPIO_IRQS           (32 * 4)
 #elif defined CONFIG_ARCH_MXC91231
 #define MXC_GPIO_IRQS           (32 * 4)
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 75d96214b831..97b19e7800bc 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -54,13 +54,13 @@
 #define MX1_AIPI2_BASE_ADDR             (0x10000 + MX1_IO_BASE_ADDR)
 #define MX1_SIM_BASE_ADDR               (0x11000 + MX1_IO_BASE_ADDR)
 #define MX1_USBD_BASE_ADDR              (0x12000 + MX1_IO_BASE_ADDR)
-#define MX1_SPI1_BASE_ADDR              (0x13000 + MX1_IO_BASE_ADDR)
+#define MX1_CSPI1_BASE_ADDR             (0x13000 + MX1_IO_BASE_ADDR)
 #define MX1_MMC_BASE_ADDR               (0x14000 + MX1_IO_BASE_ADDR)
 #define MX1_ASP_BASE_ADDR               (0x15000 + MX1_IO_BASE_ADDR)
 #define MX1_BTA_BASE_ADDR               (0x16000 + MX1_IO_BASE_ADDR)
 #define MX1_I2C_BASE_ADDR               (0x17000 + MX1_IO_BASE_ADDR)
 #define MX1_SSI_BASE_ADDR               (0x18000 + MX1_IO_BASE_ADDR)
-#define MX1_SPI2_BASE_ADDR              (0x19000 + MX1_IO_BASE_ADDR)
+#define MX1_CSPI2_BASE_ADDR             (0x19000 + MX1_IO_BASE_ADDR)
 #define MX1_MSHC_BASE_ADDR              (0x1A000 + MX1_IO_BASE_ADDR)
 #define MX1_CCM_BASE_ADDR               (0x1B000 + MX1_IO_BASE_ADDR)
 #define MX1_SCM_BASE_ADDR               (0x1B804 + MX1_IO_BASE_ADDR)
@@ -89,7 +89,7 @@
 #define MX1_GPIO_INT_PORTA      11
 #define MX1_GPIO_INT_PORTB      12
 #define MX1_GPIO_INT_PORTC      13
-#define MX1_LCDC_INT            14
+#define MX1_INT_LCDC            14
 #define MX1_SIM_INT             15
 #define MX1_SIM_DATA_INT        16
 #define MX1_RTC_INT             17
@@ -112,7 +112,8 @@
 #define MX1_PWM_INT             34
 #define MX1_SDHC_INT            35
 #define MX1_INT_I2C             39
-#define MX1_CSPI_INT            41
+#define MX1_INT_CSPI2           40
+#define MX1_INT_CSPI1           41
 #define MX1_SSI_TX_INT          42
 #define MX1_SSI_TX_ERR_INT      43
 #define MX1_SSI_RX_INT          44
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index d7a8e52181ea..ace17864575e 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -79,7 +79,7 @@
 #define MX53_GPIO3_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0008C000)
 #define MX53_GPIO4_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00090000)
 #define MX53_KPP_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x00094000)
-#define MX53_WDOG_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x00098000)
+#define MX53_WDOG1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00098000)
 #define MX53_WDOG2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0009C000)
 #define MX53_GPT1_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A0000)
 #define MX53_SRTC_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A4000)
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 04c7a26b1f26..7e072637eefa 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -103,7 +103,7 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx27()          (0)
 #endif
-#ifdef CONFIG_ARCH_MX31
+#ifdef CONFIG_SOC_IMX31
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
 #  define mxc_cpu_type __mxc_cpu_type
@@ -115,7 +115,7 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx31()          (0)
 #endif
-#ifdef CONFIG_ARCH_MX35
+#ifdef CONFIG_SOC_IMX35
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
 #  define mxc_cpu_type __mxc_cpu_type
@@ -127,7 +127,7 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx35()          (0)
 #endif
-#ifdef CONFIG_ARCH_MX50
+#ifdef CONFIG_SOC_IMX50
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
 #  define mxc_cpu_type __mxc_cpu_type
@@ -139,7 +139,7 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx50()          (0)
 #endif
-#ifdef CONFIG_ARCH_MX51
+#ifdef CONFIG_SOC_IMX51
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
 #  define mxc_cpu_type __mxc_cpu_type
@@ -151,7 +151,7 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx51()          (0)
 #endif
-#ifdef CONFIG_ARCH_MX53
+#ifdef CONFIG_SOC_IMX53
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
 #  define mxc_cpu_type __mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index a523a4079299..2c159dc2398b 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -44,11 +44,14 @@ struct mxc_usbh_platform_data {
        int (*exit)(struct platform_device *pdev);
        unsigned int             portsc;
-        unsigned int             flags;
        struct otg_transceiver  *otg;
 };
-int mxc_initialize_usb_hw(int port, unsigned int flags);
+int mx51_initialize_usb_hw(int port, unsigned int flags);
+int mx25_initialize_usb_hw(int port, unsigned int flags);
+int mx31_initialize_usb_hw(int port, unsigned int flags);
+int mx35_initialize_usb_hw(int port, unsigned int flags);
+int mx27_initialize_usb_hw(int port, unsigned int flags);
 #endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h
index 96b6ab4c40c3..f9161c96d7bd 100644
--- a/arch/arm/plat-mxc/include/mach/ulpi.h
+++ b/arch/arm/plat-mxc/include/mach/ulpi.h
@@ -1,6 +1,15 @@
 #ifndef __MACH_ULPI_H
 #define __MACH_ULPI_H
+#ifdef CONFIG_USB_ULPI
+struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags);
+#else
+static inline struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags)
+{
+        return NULL;
+}
+#endif
 extern struct otg_io_access_ops mxc_ulpi_access_ops;
 #endif /* __MACH_ULPI_H */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index ff469c4f1d76..4864b0afd440 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -62,6 +62,7 @@ static inline void flush(void)
 #define MX2X_UART1_BASE_ADDR    0x1000a000
 #define MX3X_UART1_BASE_ADDR    0x43F90000
 #define MX3X_UART2_BASE_ADDR    0x43F94000
+#define MX3X_UART5_BASE_ADDR    0x43FB4000
 #define MX51_UART1_BASE_ADDR    0x73fbc000
 #define MX50_UART1_BASE_ADDR    0x53fbc000
 #define MX53_UART1_BASE_ADDR    0x53fbc000
@@ -83,6 +84,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
        case MACH_TYPE_MX21ADS:
        case MACH_TYPE_PCA100:
        case MACH_TYPE_MXT_TD60:
+        case MACH_TYPE_IMX27IPCAM:
                uart_base = MX2X_UART1_BASE_ADDR;
                break;
        case MACH_TYPE_MX31LITE:
@@ -101,6 +103,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
        case MACH_TYPE_MAGX_ZN5:
                uart_base = MX3X_UART2_BASE_ADDR;
                break;
+        case MACH_TYPE_BUG:
+                uart_base = MX3X_UART5_BASE_ADDR;
+                break;
        case MACH_TYPE_MX51_BABBAGE:
        case MACH_TYPE_EUKREA_CPUIMX51SD:
        case MACH_TYPE_MX51_3DS:
@@ -110,6 +115,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
                uart_base = MX50_UART1_BASE_ADDR;
                break;
        case MACH_TYPE_MX53_EVK:
+        case MACH_TYPE_MX53_LOCO:
+        case MACH_TYPE_MX53_SMD:
                uart_base = MX53_UART1_BASE_ADDR;
                break;
        default:
diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c
index 960a02cbcbaf..3238c10d4e02 100644
--- a/arch/arm/plat-mxc/iomux-v1.c
+++ b/arch/arm/plat-mxc/iomux-v1.c
@@ -211,28 +211,10 @@ void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
 }
 EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
-static int imx_iomuxv1_init(void)
+int __init imx_iomuxv1_init(void __iomem *base, int numports)
 {
-#ifdef CONFIG_ARCH_MX1
+        imx_iomuxv1_baseaddr = base;
-        if (cpu_is_mx1()) {
+        imx_iomuxv1_numports = numports;
-                imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR);
-                imx_iomuxv1_numports = MX1_NUM_GPIO_PORT;
-        } else
-#endif
-#ifdef CONFIG_MACH_MX21
-        if (cpu_is_mx21()) {
-                imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR);
-                imx_iomuxv1_numports = MX21_NUM_GPIO_PORT;
-        } else
-#endif
-#ifdef CONFIG_MACH_MX27
-        if (cpu_is_mx27()) {
-                imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR);
-                imx_iomuxv1_numports = MX27_NUM_GPIO_PORT;
-        } else
-#endif
-                return -ENODEV;
        return 0;
 }
-pure_initcall(imx_iomuxv1_init);
diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
index 582c6dfaba4a..477e45bea1be 100644
--- a/arch/arm/plat-mxc/ulpi.c
+++ b/arch/arm/plat-mxc/ulpi.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
 #include <mach/ulpi.h>
@@ -111,3 +112,7 @@ struct otg_io_access_ops mxc_ulpi_access_ops = {
 };
 EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
+struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags)
+{
+        return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
+}
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 1e88ecb846d1..70620426ee55 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -30,23 +30,39 @@
 /*
 * The GPIO module in the Nomadik family of Systems-on-Chip is an
 * AMBA device, managing 32 pins and alternate functions.  The logic block
- * is currently only used in the Nomadik.
+ * is currently used in the Nomadik and ux500.
 *
 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
 */
-#define NMK_GPIO_PER_CHIP 32
+#define NMK_GPIO_PER_CHIP       32
 struct nmk_gpio_chip {
        struct gpio_chip chip;
        void __iomem *addr;
        struct clk *clk;
+        unsigned int bank;
        unsigned int parent_irq;
+        int secondary_parent_irq;
+        u32 (*get_secondary_status)(unsigned int bank);
+        void (*set_ioforce)(bool enable);
        spinlock_t lock;
        /* Keep track of configured edges */
        u32 edge_rising;
        u32 edge_falling;
+        u32 real_wake;
+        u32 rwimsc;
+        u32 fwimsc;
+        u32 slpm;
 };
+static struct nmk_gpio_chip *
+nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
+static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
+#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
                                unsigned offset, int gpio_mode)
 {
@@ -118,8 +134,35 @@ static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
        __nmk_gpio_set_output(nmk_chip, offset, val);
 }
+static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
+                                     unsigned offset, int gpio_mode,
+                                     bool glitch)
+{
+        u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
+        u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
+        if (glitch && nmk_chip->set_ioforce) {
+                u32 bit = BIT(offset);
+                /* Prevent spurious wakeups */
+                writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
+                writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
+                nmk_chip->set_ioforce(true);
+        }
+        __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
+        if (glitch && nmk_chip->set_ioforce) {
+                nmk_chip->set_ioforce(false);
+                writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
+                writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
+        }
+}
 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
-                             pin_cfg_t cfg, bool sleep)
+                             pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
 {
        static const char *afnames[] = {
                [NMK_GPIO_ALT_GPIO]     = "GPIO",
@@ -144,6 +187,7 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
        int slpm = PIN_SLPM(cfg);
        int output = PIN_DIR(cfg);
        int val = PIN_VAL(cfg);
+        bool glitch = af == NMK_GPIO_ALT_C;
        dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
                pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
@@ -155,6 +199,8 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
                int slpm_output = PIN_SLPM_DIR(cfg);
                int slpm_val = PIN_SLPM_VAL(cfg);
+                af = NMK_GPIO_ALT_GPIO;
                /*
                 * The SLPM_* values are normal values + 1 to allow zero to
                 * mean "same as normal".
@@ -180,8 +226,116 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
                __nmk_gpio_set_pull(nmk_chip, offset, pull);
        }
-        __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
+        /*
-        __nmk_gpio_set_mode(nmk_chip, offset, af);
+         * If we've backed up the SLPM registers (glitch workaround), modify
+         * the backups since they will be restored.
+         */
+        if (slpmregs) {
+                if (slpm == NMK_GPIO_SLPM_NOCHANGE)
+                        slpmregs[nmk_chip->bank] |= BIT(offset);
+                else
+                        slpmregs[nmk_chip->bank] &= ~BIT(offset);
+        } else
+                __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
+        __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
+}
+/*
+ * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
+ *  - Save SLPM registers
+ *  - Set SLPM=0 for the IOs you want to switch and others to 1
+ *  - Configure the GPIO registers for the IOs that are being switched
+ *  - Set IOFORCE=1
+ *  - Modify the AFLSA/B registers for the IOs that are being switched
+ *  - Set IOFORCE=0
+ *  - Restore SLPM registers
+ *  - Any spurious wake up event during switch sequence to be ignored and
+ *    cleared
+ */
+static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
+{
+        int i;
+        for (i = 0; i < NUM_BANKS; i++) {
+                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
+                unsigned int temp = slpm[i];
+                if (!chip)
+                        break;
+                slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
+                writel(temp, chip->addr + NMK_GPIO_SLPC);
+        }
+}
+static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
+{
+        int i;
+        for (i = 0; i < NUM_BANKS; i++) {
+                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
+                if (!chip)
+                        break;
+                writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
+        }
+}
+static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
+{
+        static unsigned int slpm[NUM_BANKS];
+        unsigned long flags;
+        bool glitch = false;
+        int ret = 0;
+        int i;
+        for (i = 0; i < num; i++) {
+                if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
+                        glitch = true;
+                        break;
+                }
+        }
+        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
+        if (glitch) {
+                memset(slpm, 0xff, sizeof(slpm));
+                for (i = 0; i < num; i++) {
+                        int pin = PIN_NUM(cfgs[i]);
+                        int offset = pin % NMK_GPIO_PER_CHIP;
+                        if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
+                                slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
+                }
+                nmk_gpio_glitch_slpm_init(slpm);
+        }
+        for (i = 0; i < num; i++) {
+                struct nmk_gpio_chip *nmk_chip;
+                int pin = PIN_NUM(cfgs[i]);
+                nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
+                if (!nmk_chip) {
+                        ret = -EINVAL;
+                        break;
+                }
+                spin_lock(&nmk_chip->lock);
+                __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
+                                 cfgs[i], sleep, glitch ? slpm : NULL);
+                spin_unlock(&nmk_chip->lock);
+        }
+        if (glitch)
+                nmk_gpio_glitch_slpm_restore(slpm);
+        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
+        return ret;
 }
 /**
@@ -200,19 +354,7 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
 */
 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
 {
-        struct nmk_gpio_chip *nmk_chip;
+        return __nmk_config_pins(&cfg, 1, sleep);
-        int gpio = PIN_NUM(cfg);
-        unsigned long flags;
-        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
-        if (!nmk_chip)
-                return -EINVAL;
-        spin_lock_irqsave(&nmk_chip->lock, flags);
-        __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg, sleep);
-        spin_unlock_irqrestore(&nmk_chip->lock, flags);
-        return 0;
 }
 EXPORT_SYMBOL(nmk_config_pin);
@@ -226,31 +368,13 @@ EXPORT_SYMBOL(nmk_config_pin);
 */
 int nmk_config_pins(pin_cfg_t *cfgs, int num)
 {
-        int ret = 0;
+        return __nmk_config_pins(cfgs, num, false);
-        int i;
-        for (i = 0; i < num; i++) {
-                ret = nmk_config_pin(cfgs[i], false);
-                if (ret)
-                        break;
-        }
-        return ret;
 }
 EXPORT_SYMBOL(nmk_config_pins);
 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
 {
-        int ret = 0;
+        return __nmk_config_pins(cfgs, num, true);
-        int i;
-        for (i = 0; i < num; i++) {
-                ret = nmk_config_pin(cfgs[i], true);
-                if (ret)
-                        break;
-        }
-        return ret;
 }
 EXPORT_SYMBOL(nmk_config_pins_sleep);
@@ -277,9 +401,13 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
        if (!nmk_chip)
                return -EINVAL;
-        spin_lock_irqsave(&nmk_chip->lock, flags);
+        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
+        spin_lock(&nmk_chip->lock);
        __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
-        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+        spin_unlock(&nmk_chip->lock);
+        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
        return 0;
 }
@@ -314,6 +442,15 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
 }
 /* Mode functions */
+/**
+ * nmk_gpio_set_mode() - set the mux mode of a gpio pin
+ * @gpio: pin number
+ * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
+ *             NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
+ *
+ * Sets the mode of the specified pin to one of the alternate functions or
+ * plain GPIO.
+ */
 int nmk_gpio_set_mode(int gpio, int gpio_mode)
 {
        struct nmk_gpio_chip *nmk_chip;
@@ -401,8 +538,20 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
        }
 }
-static int nmk_gpio_irq_modify(struct irq_data *d, enum nmk_gpio_irq_type which,
+static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
-                               bool enable)
+                                int gpio, bool on)
+{
+#ifdef CONFIG_ARCH_U8500
+        if (cpu_is_u8500v2()) {
+                __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
+                                    on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
+                                       : NMK_GPIO_SLPM_WAKEUP_DISABLE);
+        }
+#endif
+        __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
+}
+static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
 {
        int gpio;
        struct nmk_gpio_chip *nmk_chip;
@@ -415,44 +564,58 @@ static int nmk_gpio_irq_modify(struct irq_data *d, enum nmk_gpio_irq_type which,
        if (!nmk_chip)
                return -EINVAL;
-        spin_lock_irqsave(&nmk_chip->lock, flags);
+        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
-        __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable);
+        spin_lock(&nmk_chip->lock);
-        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+        __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
+        if (!(nmk_chip->real_wake & bitmask))
+                __nmk_gpio_set_wake(nmk_chip, gpio, enable);
+        spin_unlock(&nmk_chip->lock);
+        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
        return 0;
 }
 static void nmk_gpio_irq_mask(struct irq_data *d)
 {
-        nmk_gpio_irq_modify(d, NORMAL, false);
+        nmk_gpio_irq_maskunmask(d, false);
 }
 static void nmk_gpio_irq_unmask(struct irq_data *d)
 {
-        nmk_gpio_irq_modify(d, NORMAL, true);
+        nmk_gpio_irq_maskunmask(d, true);
 }
 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 {
+        struct irq_desc *desc = irq_to_desc(d->irq);
+        bool enabled = !(desc->status & IRQ_DISABLED);
        struct nmk_gpio_chip *nmk_chip;
        unsigned long flags;
+        u32 bitmask;
        int gpio;
        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
        nmk_chip = irq_data_get_irq_chip_data(d);
        if (!nmk_chip)
                return -EINVAL;
+        bitmask = nmk_gpio_get_bitmask(gpio);
-        spin_lock_irqsave(&nmk_chip->lock, flags);
+        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
-#ifdef CONFIG_ARCH_U8500
+        spin_lock(&nmk_chip->lock);
-        if (cpu_is_u8500v2()) {
-                __nmk_gpio_set_slpm(nmk_chip, gpio,
+        if (!enabled)
-                                    on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
+                __nmk_gpio_set_wake(nmk_chip, gpio, on);
-                                       : NMK_GPIO_SLPM_WAKEUP_DISABLE);
-        }
+        if (on)
-#endif
+                nmk_chip->real_wake |= bitmask;
-        __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
+        else
-        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+                nmk_chip->real_wake &= ~bitmask;
+        spin_unlock(&nmk_chip->lock);
+        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
        return 0;
 }
@@ -483,7 +646,7 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
        if (enabled)
                __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
-        if (wake)
+        if (enabled || wake)
                __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
        nmk_chip->edge_rising &= ~bitmask;
@@ -497,7 +660,7 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
        if (enabled)
                __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
-        if (wake)
+        if (enabled || wake)
                __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
        spin_unlock_irqrestore(&nmk_chip->lock, flags);
@@ -514,12 +677,11 @@ static struct irq_chip nmk_gpio_irq_chip = {
        .irq_set_wake   = nmk_gpio_irq_set_wake,
 };
-static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
+                                   u32 status)
 {
        struct nmk_gpio_chip *nmk_chip;
        struct irq_chip *host_chip = get_irq_chip(irq);
-        unsigned int gpio_irq;
-        u32 pending;
        unsigned int first_irq;
        if (host_chip->irq_mask_ack)
@@ -532,29 +694,56 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
        nmk_chip = get_irq_data(irq);
        first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
-        while ( (pending = readl(nmk_chip->addr + NMK_GPIO_IS)) ) {
+        while (status) {
-                gpio_irq = first_irq + __ffs(pending);
+                int bit = __ffs(status);
-                generic_handle_irq(gpio_irq);
+                generic_handle_irq(first_irq + bit);
+                status &= ~BIT(bit);
        }
        host_chip->irq_unmask(&desc->irq_data);
 }
+static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
+        u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
+        __nmk_gpio_irq_handler(irq, desc, status);
+}
+static void nmk_gpio_secondary_irq_handler(unsigned int irq,
+                                           struct irq_desc *desc)
+{
+        struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
+        u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
+        __nmk_gpio_irq_handler(irq, desc, status);
+}
 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
 {
        unsigned int first_irq;
        int i;
        first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
-        for (i = first_irq; i < first_irq + NMK_GPIO_PER_CHIP; i++) {
+        for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
                set_irq_chip(i, &nmk_gpio_irq_chip);
                set_irq_handler(i, handle_edge_irq);
                set_irq_flags(i, IRQF_VALID);
                set_irq_chip_data(i, nmk_chip);
                set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
        }
        set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
        set_irq_data(nmk_chip->parent_irq, nmk_chip);
+        if (nmk_chip->secondary_parent_irq >= 0) {
+                set_irq_chained_handler(nmk_chip->secondary_parent_irq,
+                                        nmk_gpio_secondary_irq_handler);
+                set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip);
+        }
        return 0;
 }
@@ -605,6 +794,97 @@ static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
        return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
 }
+#ifdef CONFIG_DEBUG_FS
+#include <linux/seq_file.h>
+static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+        int mode;
+        unsigned                i;
+        unsigned                gpio = chip->base;
+        int                     is_out;
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+        const char *modes[] = {
+                [NMK_GPIO_ALT_GPIO]     = "gpio",
+                [NMK_GPIO_ALT_A]        = "altA",
+                [NMK_GPIO_ALT_B]        = "altB",
+                [NMK_GPIO_ALT_C]        = "altC",
+        };
+        for (i = 0; i < chip->ngpio; i++, gpio++) {
+                const char *label = gpiochip_is_requested(chip, i);
+                bool pull;
+                u32 bit = 1 << i;
+                if (!label)
+                        continue;
+                is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
+                pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
+                mode = nmk_gpio_get_mode(gpio);
+                seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
+                        gpio, label,
+                        is_out ? "out" : "in ",
+                        chip->get
+                                ? (chip->get(chip, i) ? "hi" : "lo")
+                                : "?  ",
+                        (mode < 0) ? "unknown" : modes[mode],
+                        pull ? "pull" : "none");
+                if (!is_out) {
+                        int             irq = gpio_to_irq(gpio);
+                        struct irq_desc *desc = irq_to_desc(irq);
+                        /* This races with request_irq(), set_irq_type(),
+                         * and set_irq_wake() ... but those are "rare".
+                         *
+                         * More significantly, trigger type flags aren't
+                         * currently maintained by genirq.
+                         */
+                        if (irq >= 0 && desc->action) {
+                                char *trigger;
+                                switch (desc->status & IRQ_TYPE_SENSE_MASK) {
+                                case IRQ_TYPE_NONE:
+                                        trigger = "(default)";
+                                        break;
+                                case IRQ_TYPE_EDGE_FALLING:
+                                        trigger = "edge-falling";
+                                        break;
+                                case IRQ_TYPE_EDGE_RISING:
+                                        trigger = "edge-rising";
+                                        break;
+                                case IRQ_TYPE_EDGE_BOTH:
+                                        trigger = "edge-both";
+                                        break;
+                                case IRQ_TYPE_LEVEL_HIGH:
+                                        trigger = "level-high";
+                                        break;
+                                case IRQ_TYPE_LEVEL_LOW:
+                                        trigger = "level-low";
+                                        break;
+                                default:
+                                        trigger = "?trigger?";
+                                        break;
+                                }
+                                seq_printf(s, " irq-%d %s%s",
+                                        irq, trigger,
+                                        (desc->status & IRQ_WAKEUP)
+                                                ? " wakeup" : "");
+                        }
+                }
+                seq_printf(s, "\n");
+        }
+}
+#else
+#define nmk_gpio_dbg_show       NULL
+#endif
 /* This structure is replicated for each GPIO block allocated at probe time */
 static struct gpio_chip nmk_gpio_template = {
        .direction_input        = nmk_gpio_make_input,
@@ -612,10 +892,64 @@ static struct gpio_chip nmk_gpio_template = {
        .direction_output       = nmk_gpio_make_output,
        .set                    = nmk_gpio_set_output,
        .to_irq                 = nmk_gpio_to_irq,
-        .ngpio                  = NMK_GPIO_PER_CHIP,
+        .dbg_show               = nmk_gpio_dbg_show,
        .can_sleep              = 0,
 };
+/*
+ * Called from the suspend/resume path to only keep the real wakeup interrupts
+ * (those that have had set_irq_wake() called on them) as wakeup interrupts,
+ * and not the rest of the interrupts which we needed to have as wakeups for
+ * cpuidle.
+ *
+ * PM ops are not used since this needs to be done at the end, after all the
+ * other drivers are done with their suspend callbacks.
+ */
+void nmk_gpio_wakeups_suspend(void)
+{
+        int i;
+        for (i = 0; i < NUM_BANKS; i++) {
+                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
+                if (!chip)
+                        break;
+                chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
+                chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
+                writel(chip->rwimsc & chip->real_wake,
+                       chip->addr + NMK_GPIO_RWIMSC);
+                writel(chip->fwimsc & chip->real_wake,
+                       chip->addr + NMK_GPIO_FWIMSC);
+                if (cpu_is_u8500v2()) {
+                        chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
+                        /* 0 -> wakeup enable */
+                        writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
+                }
+        }
+}
+void nmk_gpio_wakeups_resume(void)
+{
+        int i;
+        for (i = 0; i < NUM_BANKS; i++) {
+                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
+                if (!chip)
+                        break;
+                writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
+                writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
+                if (cpu_is_u8500v2())
+                        writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
+        }
+}
 static int __devinit nmk_gpio_probe(struct platform_device *dev)
 {
        struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
@@ -623,6 +957,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
        struct gpio_chip *chip;
        struct resource *res;
        struct clk *clk;
+        int secondary_irq;
        int irq;
        int ret;
@@ -641,6 +976,12 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
                goto out;
        }
+        secondary_irq = platform_get_irq(dev, 1);
+        if (secondary_irq >= 0 && !pdata->get_secondary_status) {
+                ret = -EINVAL;
+                goto out;
+        }
        if (request_mem_region(res->start, resource_size(res),
                               dev_name(&dev->dev)) == NULL) {
                ret = -EBUSY;
@@ -664,14 +1005,19 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
         * The virt address in nmk_chip->addr is in the nomadik register space,
         * so we can simply convert the resource address, without remapping
         */
+        nmk_chip->bank = dev->id;
        nmk_chip->clk = clk;
        nmk_chip->addr = io_p2v(res->start);
        nmk_chip->chip = nmk_gpio_template;
        nmk_chip->parent_irq = irq;
+        nmk_chip->secondary_parent_irq = secondary_irq;
+        nmk_chip->get_secondary_status = pdata->get_secondary_status;
+        nmk_chip->set_ioforce = pdata->set_ioforce;
        spin_lock_init(&nmk_chip->lock);
        chip = &nmk_chip->chip;
        chip->base = pdata->first_gpio;
+        chip->ngpio = pdata->num_gpio;
        chip->label = pdata->name ?: dev_name(&dev->dev);
        chip->dev = &dev->dev;
        chip->owner = THIS_MODULE;
@@ -680,6 +1026,9 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
        if (ret)
                goto out_free;
+        BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
+        nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
        platform_set_drvdata(dev, nmk_chip);
        nmk_gpio_init_irq(nmk_chip);
@@ -705,10 +1054,8 @@ static struct platform_driver nmk_gpio_driver = {
        .driver = {
                .owner = THIS_MODULE,
                .name = "gpio",
-                },
+        },
        .probe = nmk_gpio_probe,
-        .suspend = NULL, /* to be done */
-        .resume = NULL,
 };
 static int __init nmk_gpio_init(void)
diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h
index 67b113d639d8..1b9f6f0843d1 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio.h
@@ -75,6 +75,9 @@ extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
 extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
 extern int nmk_gpio_get_mode(int gpio);
+extern void nmk_gpio_wakeups_suspend(void);
+extern void nmk_gpio_wakeups_resume(void);
 /*
 * Platform data to register a block: only the initial gpio/irq number.
 */
@@ -82,6 +85,9 @@ struct nmk_gpio_platform_data {
        char *name;
        int first_gpio;
        int first_irq;
+        int num_gpio;
+        u32 (*get_secondary_status)(unsigned int bank);
+        void (*set_ioforce)(bool enable);
 };
 #endif /* __ASM_PLAT_GPIO_H */
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 459b319a9fad..49d3208793e5 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -322,15 +322,18 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
 struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
 {
-        struct omap_mbox *mbox;
+        struct omap_mbox *_mbox, *mbox = NULL;
-        int ret;
+        int i, ret;
        if (!mboxes)
                return ERR_PTR(-EINVAL);
-        for (mbox = *mboxes; mbox; mbox++)
+        for (i = 0; (_mbox = mboxes[i]); i++) {
-                if (!strcmp(mbox->name, name))
+                if (!strcmp(_mbox->name, name)) {
+                        mbox = _mbox;
                        break;
+                }
+        }
        if (!mbox)
                return ERR_PTR(-ENOENT);
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 5f3522314815..078894bc3b9a 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -17,55 +17,123 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
-static DEFINE_SPINLOCK(gpio_lock);
+/*
-static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
+ * GPIO unit register offsets.
-static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
+ */
+#define GPIO_OUT_OFF            0x0000
+#define GPIO_IO_CONF_OFF        0x0004
+#define GPIO_BLINK_EN_OFF       0x0008
+#define GPIO_IN_POL_OFF         0x000c
+#define GPIO_DATA_IN_OFF        0x0010
+#define GPIO_EDGE_CAUSE_OFF     0x0014
+#define GPIO_EDGE_MASK_OFF      0x0018
+#define GPIO_LEVEL_MASK_OFF     0x001c
+struct orion_gpio_chip {
+        struct gpio_chip        chip;
+        spinlock_t              lock;
+        void __iomem            *base;
+        unsigned long           valid_input;
+        unsigned long           valid_output;
+        int                     mask_offset;
+        int                     secondary_irq_base;
+};
+static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_OUT_OFF;
+}
+static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_IO_CONF_OFF;
+}
+static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_BLINK_EN_OFF;
+}
+static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_IN_POL_OFF;
+}
+static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_DATA_IN_OFF;
+}
+static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_EDGE_CAUSE_OFF;
+}
+static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
+}
+static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
+}
-static inline void __set_direction(unsigned pin, int input)
+static struct orion_gpio_chip orion_gpio_chips[2];
+static int orion_gpio_chip_count;
+static inline void
+__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
 {
        u32 u;
-        u = readl(GPIO_IO_CONF(pin));
+        u = readl(GPIO_IO_CONF(ochip));
        if (input)
-                u |= 1 << (pin & 31);
+                u |= 1 << pin;
        else
-                u &= ~(1 << (pin & 31));
+                u &= ~(1 << pin);
-        writel(u, GPIO_IO_CONF(pin));
+        writel(u, GPIO_IO_CONF(ochip));
 }
-static void __set_level(unsigned pin, int high)
+static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
 {
        u32 u;
-        u = readl(GPIO_OUT(pin));
+        u = readl(GPIO_OUT(ochip));
        if (high)
-                u |= 1 << (pin & 31);
+                u |= 1 << pin;
        else
-                u &= ~(1 << (pin & 31));
+                u &= ~(1 << pin);
-        writel(u, GPIO_OUT(pin));
+        writel(u, GPIO_OUT(ochip));
 }
-static inline void __set_blinking(unsigned pin, int blink)
+static inline void
+__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
 {
        u32 u;
-        u = readl(GPIO_BLINK_EN(pin));
+        u = readl(GPIO_BLINK_EN(ochip));
        if (blink)
-                u |= 1 << (pin & 31);
+                u |= 1 << pin;
        else
-                u &= ~(1 << (pin & 31));
+                u &= ~(1 << pin);
-        writel(u, GPIO_BLINK_EN(pin));
+        writel(u, GPIO_BLINK_EN(ochip));
 }
-static inline int orion_gpio_is_valid(unsigned pin, int mode)
+static inline int
+orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
 {
-        if (pin < GPIO_MAX) {
+        if (pin >= ochip->chip.ngpio)
-                if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input))
+                goto err_out;
-                        goto err_out;
-                if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output))
+        if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
-                        goto err_out;
+                goto err_out;
-                return true;
-        }
+        if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
+                goto err_out;
+        return 1;
 err_out:
        pr_debug("%s: invalid GPIO %d\n", __func__, pin);
@@ -75,134 +143,155 @@ err_out:
 /*
 * GENERIC_GPIO primitives.
 */
+static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
+{
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
+        if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
+            orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
+                return 0;
+        return -EINVAL;
+}
 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
        unsigned long flags;
-        if (!orion_gpio_is_valid(pin, GPIO_INPUT_OK))
+        if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
                return -EINVAL;
-        spin_lock_irqsave(&gpio_lock, flags);
+        spin_lock_irqsave(&ochip->lock, flags);
+        __set_direction(ochip, pin, 1);
-        /* Configure GPIO direction. */
+        spin_unlock_irqrestore(&ochip->lock, flags);
-        __set_direction(pin, 1);
-        spin_unlock_irqrestore(&gpio_lock, flags);
        return 0;
 }
-static int orion_gpio_get_value(struct gpio_chip *chip, unsigned pin)
+static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
        int val;
-        if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)))
+        if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
-                val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin));
+                val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
-        else
+        } else {
-                val = readl(GPIO_OUT(pin));
+                val = readl(GPIO_OUT(ochip));
+        }
-        return (val >> (pin & 31)) & 1;
+        return (val >> pin) & 1;
 }
-static int orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
+static int
-        int value)
+orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
        unsigned long flags;
-        if (!orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
+        if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
                return -EINVAL;
-        spin_lock_irqsave(&gpio_lock, flags);
+        spin_lock_irqsave(&ochip->lock, flags);
+        __set_blinking(ochip, pin, 0);
-        /* Disable blinking. */
+        __set_level(ochip, pin, value);
-        __set_blinking(pin, 0);
+        __set_direction(ochip, pin, 0);
+        spin_unlock_irqrestore(&ochip->lock, flags);
-        /* Configure GPIO output value. */
-        __set_level(pin, value);
-        /* Configure GPIO direction. */
-        __set_direction(pin, 0);
-        spin_unlock_irqrestore(&gpio_lock, flags);
        return 0;
 }
-static void orion_gpio_set_value(struct gpio_chip *chip, unsigned pin,
+static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
-        int value)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
        unsigned long flags;
-        spin_lock_irqsave(&gpio_lock, flags);
+        spin_lock_irqsave(&ochip->lock, flags);
+        __set_level(ochip, pin, value);
-        /* Configure GPIO output value. */
+        spin_unlock_irqrestore(&ochip->lock, flags);
-        __set_level(pin, value);
-        spin_unlock_irqrestore(&gpio_lock, flags);
 }
-static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
+static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 {
-        if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) ||
+        struct orion_gpio_chip *ochip =
-            orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
+                container_of(chip, struct orion_gpio_chip, chip);
-                return 0;
-        return -EINVAL;
-}
-static struct gpio_chip orion_gpiochip = {
+        return ochip->secondary_irq_base + pin;
-        .label                  = "orion_gpio",
-        .direction_input        = orion_gpio_direction_input,
-        .get                    = orion_gpio_get_value,
-        .direction_output       = orion_gpio_direction_output,
-        .set                    = orion_gpio_set_value,
-        .request                = orion_gpio_request,
-        .base                   = 0,
-        .ngpio                  = GPIO_MAX,
-        .can_sleep              = 0,
-};
-void __init orion_gpio_init(void)
-{
-        gpiochip_add(&orion_gpiochip);
 }
 /*
 * Orion-specific GPIO API extensions.
 */
+static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
+{
+        int i;
+        for (i = 0; i < orion_gpio_chip_count; i++) {
+                struct orion_gpio_chip *ochip = orion_gpio_chips + i;
+                struct gpio_chip *chip = &ochip->chip;
+                if (pin >= chip->base && pin < chip->base + chip->ngpio)
+                        return ochip;
+        }
+        return NULL;
+}
 void __init orion_gpio_set_unused(unsigned pin)
 {
+        struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
+        if (ochip == NULL)
+                return;
+        pin -= ochip->chip.base;
        /* Configure as output, drive low. */
-        __set_level(pin, 0);
+        __set_level(ochip, pin, 0);
-        __set_direction(pin, 0);
+        __set_direction(ochip, pin, 0);
 }
 void __init orion_gpio_set_valid(unsigned pin, int mode)
 {
+        struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
+        if (ochip == NULL)
+                return;
+        pin -= ochip->chip.base;
        if (mode == 1)
                mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
        if (mode & GPIO_INPUT_OK)
-                __set_bit(pin, gpio_valid_input);
+                __set_bit(pin, &ochip->valid_input);
        else
-                __clear_bit(pin, gpio_valid_input);
+                __clear_bit(pin, &ochip->valid_input);
        if (mode & GPIO_OUTPUT_OK)
-                __set_bit(pin, gpio_valid_output);
+                __set_bit(pin, &ochip->valid_output);
        else
-                __clear_bit(pin, gpio_valid_output);
+                __clear_bit(pin, &ochip->valid_output);
 }
 void orion_gpio_set_blink(unsigned pin, int blink)
 {
+        struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
        unsigned long flags;
-        spin_lock_irqsave(&gpio_lock, flags);
+        if (ochip == NULL)
+                return;
-        /* Set output value to zero. */
+        spin_lock_irqsave(&ochip->lock, flags);
-        __set_level(pin, 0);
+        __set_level(ochip, pin, 0);
+        __set_blinking(ochip, pin, blink);
-        /* Set blinking. */
+        spin_unlock_irqrestore(&ochip->lock, flags);
-        __set_blinking(pin, blink);
-        spin_unlock_irqrestore(&gpio_lock, flags);
 }
 EXPORT_SYMBOL(orion_gpio_set_blink);
@@ -234,59 +323,78 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
 ****************************************************************************/
 static void gpio_irq_ack(struct irq_data *d)
 {
-        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+        int type;
+        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                int pin = irq_to_gpio(d->irq);
+                int pin = d->irq - ochip->secondary_irq_base;
-                writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
+                writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
        }
 }
 static void gpio_irq_mask(struct irq_data *d)
 {
-        int pin = irq_to_gpio(d->irq);
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
+        int type;
-        u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
+        void __iomem *reg;
-                GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
+        int pin;
-        u32 u = readl(reg);
-        u &= ~(1 << (pin & 31));
+        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
-        writel(u, reg);
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+                reg = GPIO_EDGE_MASK(ochip);
+        else
+                reg = GPIO_LEVEL_MASK(ochip);
+        pin = d->irq - ochip->secondary_irq_base;
+        writel(readl(reg) & ~(1 << pin), reg);
 }
 static void gpio_irq_unmask(struct irq_data *d)
 {
-        int pin = irq_to_gpio(d->irq);
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
+        int type;
-        u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
+        void __iomem *reg;
-                GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
+        int pin;
-        u32 u = readl(reg);
-        u |= 1 << (pin & 31);
+        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
-        writel(u, reg);
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+                reg = GPIO_EDGE_MASK(ochip);
+        else
+                reg = GPIO_LEVEL_MASK(ochip);
+        pin = d->irq - ochip->secondary_irq_base;
+        writel(readl(reg) | (1 << pin), reg);
 }
 static int gpio_irq_set_type(struct irq_data *d, u32 type)
 {
-        int pin = irq_to_gpio(d->irq);
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        struct irq_desc *desc;
+        int pin;
        u32 u;
-        u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
+        pin = d->irq - ochip->secondary_irq_base;
+        u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
        if (!u) {
                printk(KERN_ERR "orion gpio_irq_set_type failed "
                                "(irq %d, pin %d).\n", d->irq, pin);
                return -EINVAL;
        }
-        desc = irq_desc + d->irq;
        /*
         * Set edge/level type.
         */
        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                desc->handle_irq = handle_edge_irq;
+                set_irq_handler(d->irq, handle_edge_irq);
        } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-                desc->handle_irq = handle_level_irq;
+                set_irq_handler(d->irq, handle_level_irq);
        } else {
-                printk(KERN_ERR "failed to set irq=%d (type=%d)\n", d->irq, type);
+                printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
+                       d->irq, type);
                return -EINVAL;
        }
@@ -294,31 +402,29 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
         * Configure interrupt polarity.
         */
        if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
-                u = readl(GPIO_IN_POL(pin));
+                u = readl(GPIO_IN_POL(ochip));
-                u &= ~(1 << (pin & 31));
+                u &= ~(1 << pin);
-                writel(u, GPIO_IN_POL(pin));
+                writel(u, GPIO_IN_POL(ochip));
        } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
-                u = readl(GPIO_IN_POL(pin));
+                u = readl(GPIO_IN_POL(ochip));
-                u |= 1 << (pin & 31);
+                u |= 1 << pin;
-                writel(u, GPIO_IN_POL(pin));
+                writel(u, GPIO_IN_POL(ochip));
        } else if (type == IRQ_TYPE_EDGE_BOTH) {
                u32 v;
-                v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));
+                v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
                /*
                 * set initial polarity based on current input level
                 */
-                u = readl(GPIO_IN_POL(pin));
+                u = readl(GPIO_IN_POL(ochip));
-                if (v & (1 << (pin & 31)))
+                if (v & (1 << pin))
-                        u |= 1 << (pin & 31);           /* falling */
+                        u |= 1 << pin;          /* falling */
                else
-                        u &= ~(1 << (pin & 31));        /* rising */
+                        u &= ~(1 << pin);       /* rising */
-                writel(u, GPIO_IN_POL(pin));
+                writel(u, GPIO_IN_POL(ochip));
        }
-        desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
        return 0;
 }
@@ -330,29 +436,87 @@ struct irq_chip orion_gpio_irq_chip = {
        .irq_set_type   = gpio_irq_set_type,
 };
+void __init orion_gpio_init(int gpio_base, int ngpio,
+                            u32 base, int mask_offset, int secondary_irq_base)
+{
+        struct orion_gpio_chip *ochip;
+        int i;
+        if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
+                return;
+        ochip = orion_gpio_chips + orion_gpio_chip_count;
+        ochip->chip.label = "orion_gpio";
+        ochip->chip.request = orion_gpio_request;
+        ochip->chip.direction_input = orion_gpio_direction_input;
+        ochip->chip.get = orion_gpio_get;
+        ochip->chip.direction_output = orion_gpio_direction_output;
+        ochip->chip.set = orion_gpio_set;
+        ochip->chip.to_irq = orion_gpio_to_irq;
+        ochip->chip.base = gpio_base;
+        ochip->chip.ngpio = ngpio;
+        ochip->chip.can_sleep = 0;
+        spin_lock_init(&ochip->lock);
+        ochip->base = (void __iomem *)base;
+        ochip->valid_input = 0;
+        ochip->valid_output = 0;
+        ochip->mask_offset = mask_offset;
+        ochip->secondary_irq_base = secondary_irq_base;
+        gpiochip_add(&ochip->chip);
+        orion_gpio_chip_count++;
+        /*
+         * Mask and clear GPIO interrupts.
+         */
+        writel(0, GPIO_EDGE_CAUSE(ochip));
+        writel(0, GPIO_EDGE_MASK(ochip));
+        writel(0, GPIO_LEVEL_MASK(ochip));
+        for (i = 0; i < ngpio; i++) {
+                unsigned int irq = secondary_irq_base + i;
+                set_irq_chip(irq, &orion_gpio_irq_chip);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_chip_data(irq, ochip);
+                irq_desc[irq].status |= IRQ_LEVEL;
+                set_irq_flags(irq, IRQF_VALID);
+        }
+}
 void orion_gpio_irq_handler(int pinoff)
 {
+        struct orion_gpio_chip *ochip;
        u32 cause;
-        int pin;
+        int i;
-        cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
+        ochip = orion_gpio_chip_find(pinoff);
-        cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));
+        if (ochip == NULL)
+                return;
-        for (pin = pinoff; pin < pinoff + 8; pin++) {
+        cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
-                int irq = gpio_to_irq(pin);
+        cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
-                struct irq_desc *desc = irq_desc + irq;
-                if (!(cause & (1 << (pin & 31))))
+        for (i = 0; i < ochip->chip.ngpio; i++) {
+                int irq;
+                struct irq_desc *desc;
+                irq = ochip->secondary_irq_base + i;
+                if (!(cause & (1 << i)))
                        continue;
+                desc = irq_desc + irq;
                if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
                        /* Swap polarity (race with GPIO line) */
                        u32 polarity;
-                        polarity = readl(GPIO_IN_POL(pin));
+                        polarity = readl(GPIO_IN_POL(ochip));
-                        polarity ^= 1 << (pin & 31);
+                        polarity ^= 1 << i;
-                        writel(polarity, GPIO_IN_POL(pin));
+                        writel(polarity, GPIO_IN_POL(ochip));
                }
                desc_handle_irq(irq, desc);
        }
 }
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 07c430fdc9ef..5578b9803fc6 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -12,6 +12,7 @@
 #define __PLAT_GPIO_H
 #include <linux/init.h>
+#include <asm-generic/gpio.h>
 /*
 * GENERIC_GPIO primitives.
@@ -19,6 +20,7 @@
 #define gpio_get_value  __gpio_get_value
 #define gpio_set_value  __gpio_set_value
 #define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
 /*
 * Orion-specific GPIO API extensions.
@@ -31,7 +33,8 @@ void orion_gpio_set_blink(unsigned pin, int blink);
 void orion_gpio_set_valid(unsigned pin, int mode);
 /* Initialize gpiolib. */
-void __init orion_gpio_init(void);
+void __init orion_gpio_init(int gpio_base, int ngpio,
+                            u32 base, int mask_offset, int secondary_irq_base);
 /*
 * GPIO interrupt handling.
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index c06ca35f3613..4d5f1f6e18df 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -11,7 +11,10 @@
 #ifndef __PLAT_TIME_H
 #define __PLAT_TIME_H
-void orion_time_init(unsigned int irq, unsigned int tclk);
+void orion_time_set_base(u32 timer_base);
+void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
+                     unsigned int irq, unsigned int tclk);
 #endif
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index c3da2478b2aa..742b0323c57b 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -18,28 +18,42 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <asm/sched_clock.h>
-#include <asm/mach/time.h>
-#include <mach/bridge-regs.h>
-#include <mach/hardware.h>
 /*
- * Number of timer ticks per jiffy.
+ * MBus bridge block registers.
 */
-static u32 ticks_per_jiffy;
+#define BRIDGE_CAUSE_OFF        0x0110
+#define BRIDGE_MASK_OFF         0x0114
+#define  BRIDGE_INT_TIMER0       0x0002
+#define  BRIDGE_INT_TIMER1       0x0004
 /*
 * Timer block registers.
 */
-#define TIMER_CTRL              (TIMER_VIRT_BASE + 0x0000)
+#define TIMER_CTRL_OFF          0x0000
-#define  TIMER0_EN              0x0001
+#define  TIMER0_EN               0x0001
-#define  TIMER0_RELOAD_EN       0x0002
+#define  TIMER0_RELOAD_EN        0x0002
-#define  TIMER1_EN              0x0004
+#define  TIMER1_EN               0x0004
-#define  TIMER1_RELOAD_EN       0x0008
+#define  TIMER1_RELOAD_EN        0x0008
-#define TIMER0_RELOAD           (TIMER_VIRT_BASE + 0x0010)
+#define TIMER0_RELOAD_OFF       0x0010
-#define TIMER0_VAL              (TIMER_VIRT_BASE + 0x0014)
+#define TIMER0_VAL_OFF          0x0014
-#define TIMER1_RELOAD           (TIMER_VIRT_BASE + 0x0018)
+#define TIMER1_RELOAD_OFF       0x0018
-#define TIMER1_VAL              (TIMER_VIRT_BASE + 0x001c)
+#define TIMER1_VAL_OFF          0x001c
+/*
+ * SoC-specific data.
+ */
+static void __iomem *bridge_base;
+static u32 bridge_timer1_clr_mask;
+static void __iomem *timer_base;
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
 /*
@@ -50,14 +64,14 @@ static DEFINE_CLOCK_DATA(cd);
 unsigned long long notrace sched_clock(void)
 {
-        u32 cyc = 0xffffffff - readl(TIMER0_VAL);
+        u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 }
 static void notrace orion_update_sched_clock(void)
 {
-        u32 cyc = 0xffffffff - readl(TIMER0_VAL);
+        u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
        update_sched_clock(&cd, cyc, (u32)~0);
 }
@@ -71,7 +85,7 @@ static void __init setup_sched_clock(unsigned long tclk)
 */
 static cycle_t orion_clksrc_read(struct clocksource *cs)
 {
-        return 0xffffffff - readl(TIMER0_VAL);
+        return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF);
 }
 static struct clocksource orion_clksrc = {
@@ -101,23 +115,23 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
        /*
         * Clear and enable clockevent timer interrupt.
         */
-        writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+        writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
-        u = readl(BRIDGE_MASK);
+        u = readl(bridge_base + BRIDGE_MASK_OFF);
        u |= BRIDGE_INT_TIMER1;
-        writel(u, BRIDGE_MASK);
+        writel(u, bridge_base + BRIDGE_MASK_OFF);
        /*
         * Setup new clockevent timer value.
         */
-        writel(delta, TIMER1_VAL);
+        writel(delta, timer_base + TIMER1_VAL_OFF);
        /*
         * Enable the timer.
         */
-        u = readl(TIMER_CTRL);
+        u = readl(timer_base + TIMER_CTRL_OFF);
        u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
-        writel(u, TIMER_CTRL);
+        writel(u, timer_base + TIMER_CTRL_OFF);
        local_irq_restore(flags);
@@ -135,37 +149,38 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
                /*
                 * Setup timer to fire at 1/HZ intervals.
                 */
-                writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
+                writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
-                writel(ticks_per_jiffy - 1, TIMER1_VAL);
+                writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
                /*
                 * Enable timer interrupt.
                 */
-                u = readl(BRIDGE_MASK);
+                u = readl(bridge_base + BRIDGE_MASK_OFF);
-                writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
+                writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
                /*
                 * Enable timer.
                 */
-                u = readl(TIMER_CTRL);
+                u = readl(timer_base + TIMER_CTRL_OFF);
-                writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
+                writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
+                       timer_base + TIMER_CTRL_OFF);
        } else {
                /*
                 * Disable timer.
                 */
-                u = readl(TIMER_CTRL);
+                u = readl(timer_base + TIMER_CTRL_OFF);
-                writel(u & ~TIMER1_EN, TIMER_CTRL);
+                writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
                /*
                 * Disable timer interrupt.
                 */
-                u = readl(BRIDGE_MASK);
+                u = readl(bridge_base + BRIDGE_MASK_OFF);
-                writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
+                writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
                /*
                 * ACK pending timer interrupt.
                 */
-                writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+                writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
        }
        local_irq_restore(flags);
@@ -185,7 +200,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
        /*
         * ACK timer interrupt and call event handler.
         */
-        writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+        writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
        orion_clkevt.event_handler(&orion_clkevt);
        return IRQ_HANDLED;
@@ -197,31 +212,45 @@ static struct irqaction orion_timer_irq = {
        .handler        = orion_timer_interrupt
 };
-void __init orion_time_init(unsigned int irq, unsigned int tclk)
+void __init
+orion_time_set_base(u32 _timer_base)
+{
+        timer_base = (void __iomem *)_timer_base;
+}
+void __init
+orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
+                unsigned int irq, unsigned int tclk)
 {
        u32 u;
+        /*
+         * Set SoC-specific data.
+         */
+        bridge_base = (void __iomem *)_bridge_base;
+        bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
        ticks_per_jiffy = (tclk + HZ/2) / HZ;
        /*
-         * Set scale and timer for sched_clock
+         * Set scale and timer for sched_clock.
         */
        setup_sched_clock(tclk);
        /*
         * Setup free-running clocksource timer (interrupts
-         * disabled.)
+         * disabled).
         */
-        writel(0xffffffff, TIMER0_VAL);
+        writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
-        writel(0xffffffff, TIMER0_RELOAD);
+        writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
-        u = readl(BRIDGE_MASK);
+        u = readl(bridge_base + BRIDGE_MASK_OFF);
-        writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
+        writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
-        u = readl(TIMER_CTRL);
+        u = readl(timer_base + TIMER_CTRL_OFF);
-        writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
+        writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
        clocksource_register_hz(&orion_clksrc, tclk);
        /*
-         * Setup clockevent timer (interrupt-driven.)
+         * Setup clockevent timer (interrupt-driven).
         */
        setup_irq(irq, &orion_timer_irq);
        orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
diff --git a/arch/arm/plat-samsung/dev-uart.c b/arch/arm/plat-samsung/dev-uart.c
index 3776cd952450..5928105490fa 100644
--- a/arch/arm/plat-samsung/dev-uart.c
+++ b/arch/arm/plat-samsung/dev-uart.c
@@ -15,6 +15,8 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <plat/devs.h>
 /* uart devices */
 static struct platform_device s3c24xx_uart_device0 = {
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
index 250f4d4b9436..06a5e674401f 100644
--- a/arch/blackfin/lib/outs.S
+++ b/arch/blackfin/lib/outs.S
@@ -13,6 +13,8 @@
 .align 2
 ENTRY(_outsl)
+        CC = R2 == 0;
+        IF CC JUMP 1f;
        P0 = R0;        /* P0 = port */
        P1 = R1;        /* P1 = address */
        P2 = R2;        /* P2 = count */
@@ -20,10 +22,12 @@ ENTRY(_outsl)
        LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
 .Llong_loop_s: R0 = [P1++];
 .Llong_loop_e: [P0] = R0;
-        RTS;
+1:      RTS;
 ENDPROC(_outsl)
 ENTRY(_outsw)
+        CC = R2 == 0;
+        IF CC JUMP 1f;
        P0 = R0;        /* P0 = port */
        P1 = R1;        /* P1 = address */
        P2 = R2;        /* P2 = count */
@@ -31,10 +35,12 @@ ENTRY(_outsw)
        LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
 .Lword_loop_s: R0 = W[P1++];
 .Lword_loop_e: W[P0] = R0;
-        RTS;
+1:      RTS;
 ENDPROC(_outsw)
 ENTRY(_outsb)
+        CC = R2 == 0;
+        IF CC JUMP 1f;
        P0 = R0;        /* P0 = port */
        P1 = R1;        /* P1 = address */
        P2 = R2;        /* P2 = count */
@@ -42,10 +48,12 @@ ENTRY(_outsb)
        LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
 .Lbyte_loop_s: R0 = B[P1++];
 .Lbyte_loop_e: B[P0] = R0;
-        RTS;
+1:      RTS;
 ENDPROC(_outsb)
 ENTRY(_outsw_8)
+        CC = R2 == 0;
+        IF CC JUMP 1f;
        P0 = R0;        /* P0 = port */
        P1 = R1;        /* P1 = address */
        P2 = R2;        /* P2 = count */
@@ -56,5 +64,5 @@ ENTRY(_outsw_8)
                R0 = R0 << 8;
                R0 = R0 + R1;
 .Lword8_loop_e: W[P0] = R0;
-        RTS;
+1:      RTS;
 ENDPROC(_outsw_8)
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 790c767ca95a..ab4a925a443e 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -58,6 +58,8 @@
 1:
 .ifeqs "\flushins", BROK_FLUSH_INST
        \flushins [P0++];
+        nop;
+        nop;
 2:      nop;
 .else
 2:      \flushins [P0++];
diff --git a/arch/cris/kernel/vmlinux.lds.S b/arch/cris/kernel/vmlinux.lds.S
index 442218980db0..c49be845f96a 100644
--- a/arch/cris/kernel/vmlinux.lds.S
+++ b/arch/cris/kernel/vmlinux.lds.S
@@ -72,11 +72,6 @@ SECTIONS
        INIT_TEXT_SECTION(PAGE_SIZE)
        .init.data : { INIT_DATA }
        .init.setup : { INIT_SETUP(16) }
-#ifdef CONFIG_ETRAX_ARCH_V32
-        __start___param = .;
-        __param : { *(__param) }
-        __stop___param = .;
-#endif
        .initcall.init : {
                INIT_CALLS
        }
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 991d5998d6be..fe56a23e1ff0 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -240,6 +240,12 @@ struct machdep_calls {
         * claims to support kexec.
         */
        int (*machine_kexec_prepare)(struct kimage *image);
+        /* Called to perform the _real_ kexec.
+         * Do NOT allocate memory or fail here. We are past the point of
+         * no return.
+         */
+        void (*machine_kexec)(struct kimage *image);
 #endif /* CONFIG_KEXEC */
 #ifdef CONFIG_SUSPEND
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index 49a170af8145..a5f8672eeff3 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -87,7 +87,10 @@ void machine_kexec(struct kimage *image)
        save_ftrace_enabled = __ftrace_enabled_save();
-        default_machine_kexec(image);
+        if (ppc_md.machine_kexec)
+                ppc_md.machine_kexec(image);
+        else
+                default_machine_kexec(image);
        __ftrace_enabled_restore(save_ftrace_enabled);
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 7a1d5cb76932..8303a6c65ef7 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -353,6 +353,7 @@ static void switch_booke_debug_regs(struct thread_struct *new_thread)
                        prime_debug_regs(new_thread);
 }
 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
+#ifndef CONFIG_HAVE_HW_BREAKPOINT
 static void set_debug_reg_defaults(struct thread_struct *thread)
 {
        if (thread->dabr) {
@@ -360,6 +361,7 @@ static void set_debug_reg_defaults(struct thread_struct *thread)
                set_dabr(0);
        }
 }
+#endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 int set_dabr(unsigned long dabr)
@@ -670,11 +672,11 @@ void flush_thread(void)
 {
        discard_lazy_cpu_state();
-#ifdef CONFIG_HAVE_HW_BREAKPOINTS
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
        flush_ptrace_hw_breakpoint(current);
-#else /* CONFIG_HAVE_HW_BREAKPOINTS */
+#else /* CONFIG_HAVE_HW_BREAKPOINT */
        set_debug_reg_defaults(&current->thread);
-#endif /* CONFIG_HAVE_HW_BREAKPOINTS */
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 }
 void
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 1ec06576f619..c14d09f614f3 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -38,13 +38,11 @@ DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
 * neesd to be flushed. This function will either perform the flush
 * immediately or will batch it up if the current CPU has an active
 * batch on it.
- *
- * Must be called from within some kind of spinlock/non-preempt region...
 */
 void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
                     pte_t *ptep, unsigned long pte, int huge)
 {
-        struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
+        struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
        unsigned long vsid, vaddr;
        unsigned int psize;
        int ssize;
@@ -99,6 +97,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
         */
        if (!batch->active) {
                flush_hash_page(vaddr, rpte, psize, ssize, 0);
+                put_cpu_var(ppc64_tlb_batch);
                return;
        }
@@ -127,6 +126,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
        batch->index = ++i;
        if (i >= PPC64_TLB_BATCH_NR)
                __flush_tlb_pending(batch);
+        put_cpu_var(ppc64_tlb_batch);
 }
 /*
diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
index a78701da775b..4a5350037c8f 100644
--- a/arch/sh/include/asm/sections.h
+++ b/arch/sh/include/asm/sections.h
@@ -3,7 +3,7 @@
 #include <asm-generic/sections.h>
-extern void __nosave_begin, __nosave_end;
+extern long __nosave_begin, __nosave_end;
 extern long __machvec_start, __machvec_end;
 extern char __uncached_start, __uncached_end;
 extern char _ebss[];
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 672944f5b19c..e53b4b38bd11 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -14,7 +14,7 @@
 #include <linux/io.h>
 #include <linux/sh_timer.h>
 #include <linux/serial_sci.h>
-#include <asm/machtypes.h>
+#include <generated/machtypes.h>
 static struct resource rtc_resources[] = {
        [0] = {
@@ -255,12 +255,17 @@ static struct platform_device *sh7750_early_devices[] __initdata = {
 void __init plat_early_device_setup(void)
 {
+        struct platform_device *dev[1];
        if (mach_is_rts7751r2d()) {
                scif_platform_data.scscr |= SCSCR_CKE1;
-                early_platform_add_devices(&scif_device, 1);
+                dev[0] = &scif_device;
+                early_platform_add_devices(dev, 1);
        } else {
-                early_platform_add_devices(&sci_device, 1);
+                dev[0] = &sci_device;
-                early_platform_add_devices(&scif_device, 1);
+                early_platform_add_devices(dev, 1);
+                dev[0] = &scif_device;
+                early_platform_add_devices(dev, 1);
        }
        early_platform_add_devices(sh7750_early_devices,
diff --git a/arch/sh/lib/delay.c b/arch/sh/lib/delay.c
index faa8f86c0db4..0901b2f14e15 100644
--- a/arch/sh/lib/delay.c
+++ b/arch/sh/lib/delay.c
@@ -10,6 +10,16 @@
 void __delay(unsigned long loops)
 {
        __asm__ __volatile__(
+                /*
+                 * ST40-300 appears to have an issue with this code,
+                 * normally taking two cycles each loop, as with all
+                 * other SH variants. If however the branch and the
+                 * delay slot straddle an 8 byte boundary, this increases
+                 * to 3 cycles.
+                 * This align directive ensures this doesn't occur.
+                 */
+                ".balign 8\n\t"
                "tst    %0, %0\n\t"
                "1:\t"
                "bf/s   1b\n\t"
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index 88d3dc3d30d5..5a580ea04429 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -108,7 +108,8 @@ void copy_user_highpage(struct page *to, struct page *from,
                kunmap_atomic(vfrom, KM_USER0);
        }
-        if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+        if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK) ||
+            (vma->vm_flags & VM_EXEC))
                __flush_purge_region(vto, PAGE_SIZE);
        kunmap_atomic(vto, KM_USER1);
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index 211ca3f7fd16..4ea15ca89b2b 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -88,6 +88,7 @@ extern int acpi_disabled;
 extern int acpi_pci_disabled;
 extern int acpi_skip_timer_override;
 extern int acpi_use_timer_override;
+extern int acpi_fix_pin2_polarity;
 extern u8 acpi_sci_flags;
 extern int acpi_sci_override_gsi;
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 4d0dfa0d998e..43a18c77676d 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -36,6 +36,11 @@
 #define MSR_IA32_PERFCTR1               0x000000c2
 #define MSR_FSB_FREQ                    0x000000cd
+#define MSR_NHM_SNB_PKG_CST_CFG_CTL     0x000000e2
+#define NHM_C3_AUTO_DEMOTE              (1UL << 25)
+#define NHM_C1_AUTO_DEMOTE              (1UL << 26)
+#define ATM_LNC_C6_AUTO_DEMOTE          (1UL << 25)
 #define MSR_MTRRcap                     0x000000fe
 #define MSR_IA32_BBL_CR_CTL             0x00000119
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index e2f6a99f14ab..cc29086e30cd 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -22,6 +22,7 @@
 #define ARCH_P4_CNTRVAL_BITS    (40)
 #define ARCH_P4_CNTRVAL_MASK    ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
+#define ARCH_P4_UNFLAGGED_BIT   ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
 #define P4_ESCR_EVENT_MASK      0x7e000000U
 #define P4_ESCR_EVENT_SHIFT     25
diff --git a/arch/x86/include/asm/smpboot_hooks.h b/arch/x86/include/asm/smpboot_hooks.h
index 6c22bf353f26..725b77831993 100644
--- a/arch/x86/include/asm/smpboot_hooks.h
+++ b/arch/x86/include/asm/smpboot_hooks.h
@@ -34,7 +34,7 @@ static inline void smpboot_restore_warm_reset_vector(void)
         */
        CMOS_WRITE(0, 0xf);
-        *((volatile long *)phys_to_virt(apic->trampoline_phys_low)) = 0;
+        *((volatile u32 *)phys_to_virt(apic->trampoline_phys_low)) = 0;
 }
 static inline void __init smpboot_setup_io_apic(void)
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index b3a71137983a..3e6e2d68f761 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -72,6 +72,7 @@ u8 acpi_sci_flags __initdata;
 int acpi_sci_override_gsi __initdata;
 int acpi_skip_timer_override __initdata;
 int acpi_use_timer_override __initdata;
+int acpi_fix_pin2_polarity __initdata;
 #ifdef CONFIG_X86_LOCAL_APIC
 static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
@@ -415,10 +416,15 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header,
                return 0;
        }
-        if (acpi_skip_timer_override &&
+        if (intsrc->source_irq == 0 && intsrc->global_irq == 2) {
-            intsrc->source_irq == 0 && intsrc->global_irq == 2) {
+                if (acpi_skip_timer_override) {
-                printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n");
+                        printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n");
-                return 0;
+                        return 0;
+                }
+                if (acpi_fix_pin2_polarity && (intsrc->inti_flags & ACPI_MADT_POLARITY_MASK)) {
+                        intsrc->inti_flags &= ~ACPI_MADT_POLARITY_MASK;
+                        printk(PREFIX "BIOS IRQ0 pin2 override: forcing polarity to high active.\n");
+                }
        }
        mp_override_legacy_irq(intsrc->source_irq,
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index 51ef31a89be9..51d4e1663066 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -284,7 +284,7 @@ static int __init apbt_clockevent_register(void)
        memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
        if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
-                apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100;
+                adev->evt.rating = APBT_CLOCKEVENT_RATING - 100;
                global_clock_event = &adev->evt;
                printk(KERN_DEBUG "%s clockevent registered as global\n",
                       global_clock_event->name);
diff --git a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
index bd1cac747f67..52c93648e492 100644
--- a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
+++ b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
@@ -158,9 +158,9 @@ static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
 {
        if (c->x86 == 0x06) {
                if (cpu_has(c, X86_FEATURE_EST))
-                        printk(KERN_WARNING PFX "Warning: EST-capable CPU "
+                        printk_once(KERN_WARNING PFX "Warning: EST-capable "
-                               "detected. The acpi-cpufreq module offers "
+                               "CPU detected. The acpi-cpufreq module offers "
-                               "voltage scaling in addition of frequency "
+                               "voltage scaling in addition to frequency "
                               "scaling. You should use that instead of "
                               "p4-clockmod, if possible.\n");
                switch (c->x86_model) {
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 35c7e65e59be..c567dec854f6 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -1537,6 +1537,7 @@ static struct notifier_block cpb_nb = {
 static int __cpuinit powernowk8_init(void)
 {
        unsigned int i, supported_cpus = 0, cpu;
+        int rv;
        for_each_online_cpu(i) {
                int rc;
@@ -1555,14 +1556,14 @@ static int __cpuinit powernowk8_init(void)
                cpb_capable = true;
-                register_cpu_notifier(&cpb_nb);
                msrs = msrs_alloc();
                if (!msrs) {
                        printk(KERN_ERR "%s: Error allocating msrs!\n", __func__);
                        return -ENOMEM;
                }
+                register_cpu_notifier(&cpb_nb);
                rdmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs);
                for_each_cpu(cpu, cpu_online_mask) {
@@ -1574,7 +1575,13 @@ static int __cpuinit powernowk8_init(void)
                        (cpb_enabled ? "on" : "off"));
        }
-        return cpufreq_register_driver(&cpufreq_amd64_driver);
+        rv = cpufreq_register_driver(&cpufreq_amd64_driver);
+        if (rv < 0 && boot_cpu_has(X86_FEATURE_CPB)) {
+                unregister_cpu_notifier(&cpb_nb);
+                msrs_free(msrs);
+                msrs = NULL;
+        }
+        return rv;
 }
 /* driver entry point for term */
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index f7a0993c1e7c..ff751a9f182b 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -770,9 +770,14 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
                return 1;
        }
-        /* it might be unflagged overflow */
+        /*
-        rdmsrl(hwc->event_base + hwc->idx, v);
+         * In some circumstances the overflow might issue an NMI but did
-        if (!(v & ARCH_P4_CNTRVAL_MASK))
+         * not set P4_CCCR_OVF bit. Because a counter holds a negative value
+         * we simply check for high bit being set, if it's cleared it means
+         * the counter has reached zero value and continued counting before
+         * real NMI signal was received:
+         */
+        if (!(v & ARCH_P4_UNFLAGGED_BIT))
                return 1;
        return 0;
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 76b8cd953dee..9efbdcc56425 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -143,15 +143,10 @@ static void __init ati_bugs(int num, int slot, int func)
 static u32 __init ati_sbx00_rev(int num, int slot, int func)
 {
-        u32 old, d;
+        u32 d;
-        d = read_pci_config(num, slot, func, 0x70);
-        old = d;
-        d &= ~(1<<8);
-        write_pci_config(num, slot, func, 0x70, d);
        d = read_pci_config(num, slot, func, 0x8);
        d &= 0xff;
-        write_pci_config(num, slot, func, 0x70, old);
        return d;
 }
@@ -160,13 +155,16 @@ static void __init ati_bugs_contd(int num, int slot, int func)
 {
        u32 d, rev;
-        if (acpi_use_timer_override)
-                return;
        rev = ati_sbx00_rev(num, slot, func);
+        if (rev >= 0x40)
+                acpi_fix_pin2_polarity = 1;
        if (rev > 0x13)
                return;
+        if (acpi_use_timer_override)
+                return;
        /* check for IRQ0 interrupt swap */
        d = read_pci_config(num, slot, func, 0x64);
        if (!(d & (1<<14)))
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index fc7aae1e2bc7..715037caeb43 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -285,6 +285,14 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = {
                        DMI_MATCH(DMI_BOARD_NAME, "P4S800"),
                },
        },
+        {       /* Handle problems with rebooting on VersaLogic Menlow boards */
+                .callback = set_bios_reboot,
+                .ident = "VersaLogic Menlow based board",
+                .matches = {
+                        DMI_MATCH(DMI_BOARD_VENDOR, "VersaLogic Corporation"),
+                        DMI_MATCH(DMI_BOARD_NAME, "VersaLogic Menlow board"),
+                },
+        },
        { }
 };
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 54ce246a383e..63fec1531e89 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -2777,6 +2777,8 @@ static int dr_interception(struct vcpu_svm *svm)
                        kvm_register_write(&svm->vcpu, reg, val);
        }
+        skip_emulated_instruction(&svm->vcpu);
        return 1;
 }
diff --git a/arch/x86/platform/olpc/olpc_dt.c b/arch/x86/platform/olpc/olpc_dt.c
index dab874647530..044bda5b3174 100644
--- a/arch/x86/platform/olpc/olpc_dt.c
+++ b/arch/x86/platform/olpc/olpc_dt.c
@@ -140,8 +140,7 @@ void * __init prom_early_alloc(unsigned long size)
                 * wasted bootmem) and hand off chunks of it to callers.
                 */
                res = alloc_bootmem(chunk_size);
-                if (!res)
+                BUG_ON(!res);
-                        return NULL;
                prom_early_allocated += chunk_size;
                memset(res, 0, chunk_size);
                free_mem = chunk_size;
diff --git a/block/blk-core.c b/block/blk-core.c
index 2f4002f79a24..518dd423a5fe 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -352,7 +352,7 @@ void blk_start_queue(struct request_queue *q)
        WARN_ON(!irqs_disabled());
        queue_flag_clear(QUEUE_FLAG_STOPPED, q);
-        __blk_run_queue(q);
+        __blk_run_queue(q, false);
 }
 EXPORT_SYMBOL(blk_start_queue);
@@ -403,13 +403,14 @@ EXPORT_SYMBOL(blk_sync_queue);
 /**
 * __blk_run_queue - run a single device queue
 * @q:  The queue to run
+ * @force_kblockd: Don't run @q->request_fn directly.  Use kblockd.
 *
 * Description:
 *    See @blk_run_queue. This variant must be called with the queue lock
 *    held and interrupts disabled.
 *
 */
-void __blk_run_queue(struct request_queue *q)
+void __blk_run_queue(struct request_queue *q, bool force_kblockd)
 {
        blk_remove_plug(q);
@@ -423,7 +424,7 @@ void __blk_run_queue(struct request_queue *q)
         * Only recurse once to avoid overrunning the stack, let the unplug
         * handling reinvoke the handler shortly if we already got there.
         */
-        if (!queue_flag_test_and_set(QUEUE_FLAG_REENTER, q)) {
+        if (!force_kblockd && !queue_flag_test_and_set(QUEUE_FLAG_REENTER, q)) {
                q->request_fn(q);
                queue_flag_clear(QUEUE_FLAG_REENTER, q);
        } else {
@@ -446,7 +447,7 @@ void blk_run_queue(struct request_queue *q)
        unsigned long flags;
        spin_lock_irqsave(q->queue_lock, flags);
-        __blk_run_queue(q);
+        __blk_run_queue(q, false);
        spin_unlock_irqrestore(q->queue_lock, flags);
 }
 EXPORT_SYMBOL(blk_run_queue);
@@ -1053,7 +1054,7 @@ void blk_insert_request(struct request_queue *q, struct request *rq,
        drive_stat_acct(rq, 1);
        __elv_add_request(q, rq, where, 0);
-        __blk_run_queue(q);
+        __blk_run_queue(q, false);
        spin_unlock_irqrestore(q->queue_lock, flags);
 }
 EXPORT_SYMBOL(blk_insert_request);
@@ -2610,13 +2611,6 @@ int kblockd_schedule_work(struct request_queue *q, struct work_struct *work)
 }
 EXPORT_SYMBOL(kblockd_schedule_work);
-int kblockd_schedule_delayed_work(struct request_queue *q,
-                        struct delayed_work *dwork, unsigned long delay)
-{
-        return queue_delayed_work(kblockd_workqueue, dwork, delay);
-}
-EXPORT_SYMBOL(kblockd_schedule_delayed_work);
 int __init blk_dev_init(void)
 {
        BUILD_BUG_ON(__REQ_NR_BITS > 8 *
diff --git a/block/blk-flush.c b/block/blk-flush.c
index 54b123d6563e..b27d0208611b 100644
--- a/block/blk-flush.c
+++ b/block/blk-flush.c
@@ -66,10 +66,12 @@ static void blk_flush_complete_seq_end_io(struct request_queue *q,
        /*
         * Moving a request silently to empty queue_head may stall the
-         * queue.  Kick the queue in those cases.
+         * queue.  Kick the queue in those cases.  This function is called
+         * from request completion path and calling directly into
+         * request_fn may confuse the driver.  Always use kblockd.
         */
        if (was_empty && next_rq)
-                __blk_run_queue(q);
+                __blk_run_queue(q, true);
 }
 static void pre_flush_end_io(struct request *rq, int error)
@@ -130,7 +132,7 @@ static struct request *queue_next_fseq(struct request_queue *q)
                BUG();
        }
-        elv_insert(q, rq, ELEVATOR_INSERT_FRONT);
+        elv_insert(q, rq, ELEVATOR_INSERT_REQUEUE);
        return rq;
 }
diff --git a/block/blk-lib.c b/block/blk-lib.c
index 1a320d2406b0..eec78becb355 100644
--- a/block/blk-lib.c
+++ b/block/blk-lib.c
@@ -132,7 +132,7 @@ static void bio_batch_end_io(struct bio *bio, int err)
 }
 /**
- * blkdev_issue_zeroout generate number of zero filed write bios
+ * blkdev_issue_zeroout - generate number of zero filed write bios
 * @bdev:       blockdev to issue
 * @sector:     start sector
 * @nr_sects:   number of sectors to write
diff --git a/block/blk-throttle.c b/block/blk-throttle.c
index a89043a3caa4..e36cc10a346c 100644
--- a/block/blk-throttle.c
+++ b/block/blk-throttle.c
@@ -20,6 +20,11 @@ static int throtl_quantum = 32;
 /* Throttling is performed over 100ms slice and after that slice is renewed */
 static unsigned long throtl_slice = HZ/10;      /* 100 ms */
+/* A workqueue to queue throttle related work */
+static struct workqueue_struct *kthrotld_workqueue;
+static void throtl_schedule_delayed_work(struct throtl_data *td,
+                                unsigned long delay);
 struct throtl_rb_root {
        struct rb_root rb;
        struct rb_node *left;
@@ -345,10 +350,9 @@ static void throtl_schedule_next_dispatch(struct throtl_data *td)
        update_min_dispatch_time(st);
        if (time_before_eq(st->min_disptime, jiffies))
-                throtl_schedule_delayed_work(td->queue, 0);
+                throtl_schedule_delayed_work(td, 0);
        else
-                throtl_schedule_delayed_work(td->queue,
+                throtl_schedule_delayed_work(td, (st->min_disptime - jiffies));
-                                (st->min_disptime - jiffies));
 }
 static inline void
@@ -815,10 +819,10 @@ void blk_throtl_work(struct work_struct *work)
 }
 /* Call with queue lock held */
-void throtl_schedule_delayed_work(struct request_queue *q, unsigned long delay)
+static void
+throtl_schedule_delayed_work(struct throtl_data *td, unsigned long delay)
 {
-        struct throtl_data *td = q->td;
        struct delayed_work *dwork = &td->throtl_work;
        if (total_nr_queued(td) > 0) {
@@ -827,12 +831,11 @@ void throtl_schedule_delayed_work(struct request_queue *q, unsigned long delay)
                 * Cancel that and schedule a new one.
                 */
                __cancel_delayed_work(dwork);
-                kblockd_schedule_delayed_work(q, dwork, delay);
+                queue_delayed_work(kthrotld_workqueue, dwork, delay);
                throtl_log(td, "schedule work. delay=%lu jiffies=%lu",
                                delay, jiffies);
        }
 }
-EXPORT_SYMBOL(throtl_schedule_delayed_work);
 static void
 throtl_destroy_tg(struct throtl_data *td, struct throtl_grp *tg)
@@ -920,7 +923,7 @@ static void throtl_update_blkio_group_read_bps(void *key,
        smp_mb__after_atomic_inc();
        /* Schedule a work now to process the limit change */
-        throtl_schedule_delayed_work(td->queue, 0);
+        throtl_schedule_delayed_work(td, 0);
 }
 static void throtl_update_blkio_group_write_bps(void *key,
@@ -934,7 +937,7 @@ static void throtl_update_blkio_group_write_bps(void *key,
        smp_mb__before_atomic_inc();
        atomic_inc(&td->limits_changed);
        smp_mb__after_atomic_inc();
-        throtl_schedule_delayed_work(td->queue, 0);
+        throtl_schedule_delayed_work(td, 0);
 }
 static void throtl_update_blkio_group_read_iops(void *key,
@@ -948,7 +951,7 @@ static void throtl_update_blkio_group_read_iops(void *key,
        smp_mb__before_atomic_inc();
        atomic_inc(&td->limits_changed);
        smp_mb__after_atomic_inc();
-        throtl_schedule_delayed_work(td->queue, 0);
+        throtl_schedule_delayed_work(td, 0);
 }
 static void throtl_update_blkio_group_write_iops(void *key,
@@ -962,7 +965,7 @@ static void throtl_update_blkio_group_write_iops(void *key,
        smp_mb__before_atomic_inc();
        atomic_inc(&td->limits_changed);
        smp_mb__after_atomic_inc();
-        throtl_schedule_delayed_work(td->queue, 0);
+        throtl_schedule_delayed_work(td, 0);
 }
 void throtl_shutdown_timer_wq(struct request_queue *q)
@@ -1135,6 +1138,10 @@ void blk_throtl_exit(struct request_queue *q)
 static int __init throtl_init(void)
 {
+        kthrotld_workqueue = alloc_workqueue("kthrotld", WQ_MEM_RECLAIM, 0);
+        if (!kthrotld_workqueue)
+                panic("Failed to create kthrotld\n");
        blkio_policy_register(&blkio_policy_throtl);
        return 0;
 }
diff --git a/block/cfq-iosched.c b/block/cfq-iosched.c
index 7be4c7959625..ea83a4f0c27d 100644
--- a/block/cfq-iosched.c
+++ b/block/cfq-iosched.c
@@ -3355,7 +3355,7 @@ cfq_rq_enqueued(struct cfq_data *cfqd, struct cfq_queue *cfqq,
                            cfqd->busy_queues > 1) {
                                cfq_del_timer(cfqd, cfqq);
                                cfq_clear_cfqq_wait_request(cfqq);
-                                __blk_run_queue(cfqd->queue);
+                                __blk_run_queue(cfqd->queue, false);
                        } else {
                                cfq_blkiocg_update_idle_time_stats(
                                                &cfqq->cfqg->blkg);
@@ -3370,7 +3370,7 @@ cfq_rq_enqueued(struct cfq_data *cfqd, struct cfq_queue *cfqq,
                 * this new queue is RT and the current one is BE
                 */
                cfq_preempt_queue(cfqd, cfqq);
-                __blk_run_queue(cfqd->queue);
+                __blk_run_queue(cfqd->queue, false);
        }
 }
@@ -3731,7 +3731,7 @@ static void cfq_kick_queue(struct work_struct *work)
        struct request_queue *q = cfqd->queue;
        spin_lock_irq(q->queue_lock);
-        __blk_run_queue(cfqd->queue);
+        __blk_run_queue(cfqd->queue, false);
        spin_unlock_irq(q->queue_lock);
 }
diff --git a/block/elevator.c b/block/elevator.c
index 2569512830d3..236e93c1f46c 100644
--- a/block/elevator.c
+++ b/block/elevator.c
@@ -602,7 +602,7 @@ void elv_quiesce_start(struct request_queue *q)
         */
        elv_drain_elevator(q);
        while (q->rq.elvpriv) {
-                __blk_run_queue(q);
+                __blk_run_queue(q, false);
                spin_unlock_irq(q->queue_lock);
                msleep(10);
                spin_lock_irq(q->queue_lock);
@@ -651,7 +651,7 @@ void elv_insert(struct request_queue *q, struct request *rq, int where)
                 *   with anything.  There's no point in delaying queue
                 *   processing.
                 */
-                __blk_run_queue(q);
+                __blk_run_queue(q, false);
                break;
        case ELEVATOR_INSERT_SORT:
diff --git a/block/genhd.c b/block/genhd.c
index 6a5b772aa201..cbf1112a885c 100644
--- a/block/genhd.c
+++ b/block/genhd.c
@@ -1355,7 +1355,7 @@ int invalidate_partition(struct gendisk *disk, int partno)
        struct block_device *bdev = bdget_disk(disk, partno);
        if (bdev) {
                fsync_bdev(bdev);
-                res = __invalidate_device(bdev);
+                res = __invalidate_device(bdev, true);
                bdput(bdev);
        }
        return res;
diff --git a/block/ioctl.c b/block/ioctl.c
index 9049d460fa89..1124cd297263 100644
--- a/block/ioctl.c
+++ b/block/ioctl.c
@@ -294,9 +294,11 @@ int blkdev_ioctl(struct block_device *bdev, fmode_t mode, unsigned cmd,
                        return -EINVAL;
                if (get_user(n, (int __user *) arg))
                        return -EFAULT;
-                if (!(mode & FMODE_EXCL) &&
+                if (!(mode & FMODE_EXCL)) {
-                    blkdev_get(bdev, mode | FMODE_EXCL, &bdev) < 0)
+                        bdgrab(bdev);
-                        return -EBUSY;
+                        if (blkdev_get(bdev, mode | FMODE_EXCL, &bdev) < 0)
+                                return -EBUSY;
+                }
                ret = set_blocksize(bdev, n);
                if (!(mode & FMODE_EXCL))
                        blkdev_put(bdev, mode | FMODE_EXCL);
diff --git a/drivers/acpi/acpica/aclocal.h b/drivers/acpi/acpica/aclocal.h
index 54784bb42cec..edc25867ad9d 100644
--- a/drivers/acpi/acpica/aclocal.h
+++ b/drivers/acpi/acpica/aclocal.h
@@ -416,10 +416,15 @@ struct acpi_gpe_handler_info {
        u8 originally_enabled;  /* True if GPE was originally enabled */
 };
+struct acpi_gpe_notify_object {
+        struct acpi_namespace_node *node;
+        struct acpi_gpe_notify_object *next;
+};
 union acpi_gpe_dispatch_info {
        struct acpi_namespace_node *method_node;        /* Method node for this GPE level */
        struct acpi_gpe_handler_info *handler;  /* Installed GPE handler */
-        struct acpi_namespace_node *device_node;        /* Parent _PRW device for implicit notify */
+        struct acpi_gpe_notify_object device;   /* List of _PRW devices for implicit notify */
 };
 /*
diff --git a/drivers/acpi/acpica/evgpe.c b/drivers/acpi/acpica/evgpe.c
index 14988a86066f..f4725212eb48 100644
--- a/drivers/acpi/acpica/evgpe.c
+++ b/drivers/acpi/acpica/evgpe.c
@@ -457,6 +457,7 @@ static void ACPI_SYSTEM_XFACE acpi_ev_asynch_execute_gpe_method(void *context)
        acpi_status status;
        struct acpi_gpe_event_info *local_gpe_event_info;
        struct acpi_evaluate_info *info;
+        struct acpi_gpe_notify_object *notify_object;
        ACPI_FUNCTION_TRACE(ev_asynch_execute_gpe_method);
@@ -508,10 +509,18 @@ static void ACPI_SYSTEM_XFACE acpi_ev_asynch_execute_gpe_method(void *context)
                 * from this thread -- because handlers may in turn run other
                 * control methods.
                 */
-                status =
+                status = acpi_ev_queue_notify_request(
-                    acpi_ev_queue_notify_request(local_gpe_event_info->dispatch.
+                                local_gpe_event_info->dispatch.device.node,
-                                                 device_node,
+                                ACPI_NOTIFY_DEVICE_WAKE);
-                                                 ACPI_NOTIFY_DEVICE_WAKE);
+                notify_object = local_gpe_event_info->dispatch.device.next;
+                while (ACPI_SUCCESS(status) && notify_object) {
+                        status = acpi_ev_queue_notify_request(
+                                        notify_object->node,
+                                        ACPI_NOTIFY_DEVICE_WAKE);
+                        notify_object = notify_object->next;
+                }
                break;
        case ACPI_GPE_DISPATCH_METHOD:
diff --git a/drivers/acpi/acpica/evxfgpe.c b/drivers/acpi/acpica/evxfgpe.c
index 3b20a3401b64..52aaff3df562 100644
--- a/drivers/acpi/acpica/evxfgpe.c
+++ b/drivers/acpi/acpica/evxfgpe.c
@@ -198,7 +198,9 @@ acpi_setup_gpe_for_wake(acpi_handle wake_device,
        acpi_status status = AE_BAD_PARAMETER;
        struct acpi_gpe_event_info *gpe_event_info;
        struct acpi_namespace_node *device_node;
+        struct acpi_gpe_notify_object *notify_object;
        acpi_cpu_flags flags;
+        u8 gpe_dispatch_mask;
        ACPI_FUNCTION_TRACE(acpi_setup_gpe_for_wake);
@@ -221,27 +223,49 @@ acpi_setup_gpe_for_wake(acpi_handle wake_device,
                goto unlock_and_exit;
        }
+        if (wake_device == ACPI_ROOT_OBJECT) {
+                goto out;
+        }
        /*
         * If there is no method or handler for this GPE, then the
         * wake_device will be notified whenever this GPE fires (aka
         * "implicit notify") Note: The GPE is assumed to be
         * level-triggered (for windows compatibility).
         */
-        if (((gpe_event_info->flags & ACPI_GPE_DISPATCH_MASK) ==
+        gpe_dispatch_mask = gpe_event_info->flags & ACPI_GPE_DISPATCH_MASK;
-              ACPI_GPE_DISPATCH_NONE) && (wake_device != ACPI_ROOT_OBJECT)) {
+        if (gpe_dispatch_mask != ACPI_GPE_DISPATCH_NONE
+            && gpe_dispatch_mask != ACPI_GPE_DISPATCH_NOTIFY) {
+                goto out;
+        }
-                /* Validate wake_device is of type Device */
+        /* Validate wake_device is of type Device */
-                device_node = ACPI_CAST_PTR(struct acpi_namespace_node,
+        device_node = ACPI_CAST_PTR(struct acpi_namespace_node, wake_device);
-                                            wake_device);
+        if (device_node->type != ACPI_TYPE_DEVICE) {
-                if (device_node->type != ACPI_TYPE_DEVICE) {
+                goto unlock_and_exit;
-                        goto unlock_and_exit;
+        }
-                }
+        if (gpe_dispatch_mask == ACPI_GPE_DISPATCH_NONE) {
                gpe_event_info->flags = (ACPI_GPE_DISPATCH_NOTIFY |
                                         ACPI_GPE_LEVEL_TRIGGERED);
-                gpe_event_info->dispatch.device_node = device_node;
+                gpe_event_info->dispatch.device.node = device_node;
+                gpe_event_info->dispatch.device.next = NULL;
+        } else {
+                /* There are multiple devices to notify implicitly. */
+                notify_object = ACPI_ALLOCATE_ZEROED(sizeof(*notify_object));
+                if (!notify_object) {
+                        status = AE_NO_MEMORY;
+                        goto unlock_and_exit;
+                }
+                notify_object->node = device_node;
+                notify_object->next = gpe_event_info->dispatch.device.next;
+                gpe_event_info->dispatch.device.next = notify_object;
        }
+ out:
        gpe_event_info->flags |= ACPI_GPE_CAN_WAKE;
        status = AE_OK;
diff --git a/drivers/acpi/debugfs.c b/drivers/acpi/debugfs.c
index 5df67f1d6c61..384f7abcff77 100644
--- a/drivers/acpi/debugfs.c
+++ b/drivers/acpi/debugfs.c
@@ -26,7 +26,9 @@ static ssize_t cm_write(struct file *file, const char __user * user_buf,
                        size_t count, loff_t *ppos)
 {
        static char *buf;
-        static int uncopied_bytes;
+        static u32 max_size;
+        static u32 uncopied_bytes;
        struct acpi_table_header table;
        acpi_status status;
@@ -37,19 +39,24 @@ static ssize_t cm_write(struct file *file, const char __user * user_buf,
                if (copy_from_user(&table, user_buf,
                                   sizeof(struct acpi_table_header)))
                        return -EFAULT;
-                uncopied_bytes = table.length;
+                uncopied_bytes = max_size = table.length;
-                buf = kzalloc(uncopied_bytes, GFP_KERNEL);
+                buf = kzalloc(max_size, GFP_KERNEL);
                if (!buf)
                        return -ENOMEM;
        }
-        if (uncopied_bytes < count) {
+        if (buf == NULL)
-                kfree(buf);
+                return -EINVAL;
+        if ((*ppos > max_size) ||
+            (*ppos + count > max_size) ||
+            (*ppos + count < count) ||
+            (count > uncopied_bytes))
                return -EINVAL;
-        }
        if (copy_from_user(buf + (*ppos), user_buf, count)) {
                kfree(buf);
+                buf = NULL;
                return -EFAULT;
        }
@@ -59,6 +66,7 @@ static ssize_t cm_write(struct file *file, const char __user * user_buf,
        if (!uncopied_bytes) {
                status = acpi_install_method(buf);
                kfree(buf);
+                buf = NULL;
                if (ACPI_FAILURE(status))
                        return -EINVAL;
                add_taint(TAINT_OVERRIDDEN_ACPI_TABLE);
diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c
index b9ba04fc2b34..77fc76f8aea9 100644
--- a/drivers/block/floppy.c
+++ b/drivers/block/floppy.c
@@ -3281,7 +3281,7 @@ static int set_geometry(unsigned int cmd, struct floppy_struct *g,
                        struct block_device *bdev = opened_bdev[cnt];
                        if (!bdev || ITYPE(drive_state[cnt].fd_device) != type)
                                continue;
-                        __invalidate_device(bdev);
+                        __invalidate_device(bdev, true);
                }
                mutex_unlock(&open_lock);
        } else {
diff --git a/drivers/block/loop.c b/drivers/block/loop.c
index 49e6a545eb63..dbf31ec9114d 100644
--- a/drivers/block/loop.c
+++ b/drivers/block/loop.c
@@ -78,7 +78,6 @@
 #include <asm/uaccess.h>
-static DEFINE_MUTEX(loop_mutex);
 static LIST_HEAD(loop_devices);
 static DEFINE_MUTEX(loop_devices_mutex);
@@ -1501,11 +1500,9 @@ static int lo_open(struct block_device *bdev, fmode_t mode)
 {
        struct loop_device *lo = bdev->bd_disk->private_data;
-        mutex_lock(&loop_mutex);
        mutex_lock(&lo->lo_ctl_mutex);
        lo->lo_refcnt++;
        mutex_unlock(&lo->lo_ctl_mutex);
-        mutex_unlock(&loop_mutex);
        return 0;
 }
@@ -1515,7 +1512,6 @@ static int lo_release(struct gendisk *disk, fmode_t mode)
        struct loop_device *lo = disk->private_data;
        int err;
-        mutex_lock(&loop_mutex);
        mutex_lock(&lo->lo_ctl_mutex);
        if (--lo->lo_refcnt)
@@ -1540,7 +1536,6 @@ static int lo_release(struct gendisk *disk, fmode_t mode)
 out:
        mutex_unlock(&lo->lo_ctl_mutex);
 out_unlocked:
-        mutex_unlock(&loop_mutex);
        return 0;
 }
diff --git a/drivers/bluetooth/ath3k.c b/drivers/bluetooth/ath3k.c
index 333c21289d97..6dcd55a74c0a 100644
--- a/drivers/bluetooth/ath3k.c
+++ b/drivers/bluetooth/ath3k.c
@@ -41,6 +41,9 @@ static struct usb_device_id ath3k_table[] = {
        /* Atheros AR9285 Malbec with sflash firmware */
        { USB_DEVICE(0x03F0, 0x311D) },
+        /* Atheros AR5BBU12 with sflash firmware */
+        { USB_DEVICE(0x0489, 0xE02C) },
        { }     /* Terminating entry */
 };
diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c
index 4cefa91e6c34..700a3840fddc 100644
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
@@ -105,6 +105,9 @@ static struct usb_device_id blacklist_table[] = {
        /* Atheros AR9285 Malbec with sflash firmware */
        { USB_DEVICE(0x03f0, 0x311d), .driver_info = BTUSB_IGNORE },
+        /* Atheros AR5BBU12 with sflash firmware */
+        { USB_DEVICE(0x0489, 0xe02c), .driver_info = BTUSB_IGNORE },
        /* Broadcom BCM2035 */
        { USB_DEVICE(0x0a5c, 0x2035), .driver_info = BTUSB_WRONG_SCO_MTU },
        { USB_DEVICE(0x0a5c, 0x200a), .driver_info = BTUSB_WRONG_SCO_MTU },
@@ -829,7 +832,7 @@ static void btusb_work(struct work_struct *work)
        if (hdev->conn_hash.sco_num > 0) {
                if (!test_bit(BTUSB_DID_ISO_RESUME, &data->flags)) {
-                        err = usb_autopm_get_interface(data->isoc);
+                        err = usb_autopm_get_interface(data->isoc ? data->isoc : data->intf);
                        if (err < 0) {
                                clear_bit(BTUSB_ISOC_RUNNING, &data->flags);
                                usb_kill_anchored_urbs(&data->isoc_anchor);
@@ -858,7 +861,7 @@ static void btusb_work(struct work_struct *work)
                __set_isoc_interface(hdev, 0);
                if (test_and_clear_bit(BTUSB_DID_ISO_RESUME, &data->flags))
-                        usb_autopm_put_interface(data->isoc);
+                        usb_autopm_put_interface(data->isoc ? data->isoc : data->intf);
        }
 }
@@ -1041,8 +1044,6 @@ static int btusb_probe(struct usb_interface *intf,
        usb_set_intfdata(intf, data);
-        usb_enable_autosuspend(interface_to_usbdev(intf));
        return 0;
 }
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index 9252e85706ef..780498d76581 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -773,18 +773,23 @@ int __init agp_amd64_init(void)
 #else
                        printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
 #endif
+                        pci_unregister_driver(&agp_amd64_pci_driver);
                        return -ENODEV;
                }
                /* First check that we have at least one AMD64 NB */
-                if (!pci_dev_present(amd_nb_misc_ids))
+                if (!pci_dev_present(amd_nb_misc_ids)) {
+                        pci_unregister_driver(&agp_amd64_pci_driver);
                        return -ENODEV;
+                }
                /* Look for any AGP bridge */
                agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table;
                err = driver_attach(&agp_amd64_pci_driver.driver);
-                if (err == 0 && agp_bridges_found == 0)
+                if (err == 0 && agp_bridges_found == 0) {
+                        pci_unregister_driver(&agp_amd64_pci_driver);
                        err = -ENODEV;
+                }
        }
        return err;
 }
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index c195bfeade11..5feebe2800e9 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -130,6 +130,7 @@
 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
 #define I915_IFPADDR    0x60
+#define I830_HIC        0x70
 /* Intel 965G registers */
 #define I965_MSAC 0x62
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index fab3d3265adb..0d09b537bb9a 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -21,6 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/pagemap.h>
 #include <linux/agp_backend.h>
+#include <linux/delay.h>
 #include <asm/smp.h>
 #include "agp.h"
 #include "intel-agp.h"
@@ -70,12 +71,8 @@ static struct _intel_private {
        u32 __iomem *gtt;               /* I915G */
        bool clear_fake_agp; /* on first access via agp, fill with scratch */
        int num_dcache_entries;
-        union {
+        void __iomem *i9xx_flush_page;
-                void __iomem *i9xx_flush_page;
-                void *i8xx_flush_page;
-        };
        char *i81x_gtt_table;
-        struct page *i8xx_page;
        struct resource ifp_resource;
        int resource_valid;
        struct page *scratch_page;
@@ -722,28 +719,6 @@ static int intel_fake_agp_fetch_size(void)
 static void i830_cleanup(void)
 {
-        if (intel_private.i8xx_flush_page) {
-                kunmap(intel_private.i8xx_flush_page);
-                intel_private.i8xx_flush_page = NULL;
-        }
-        __free_page(intel_private.i8xx_page);
-        intel_private.i8xx_page = NULL;
-}
-static void intel_i830_setup_flush(void)
-{
-        /* return if we've already set the flush mechanism up */
-        if (intel_private.i8xx_page)
-                return;
-        intel_private.i8xx_page = alloc_page(GFP_KERNEL);
-        if (!intel_private.i8xx_page)
-                return;
-        intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
-        if (!intel_private.i8xx_flush_page)
-                i830_cleanup();
 }
 /* The chipset_flush interface needs to get data that has already been
@@ -758,14 +733,27 @@ static void intel_i830_setup_flush(void)
 */
 static void i830_chipset_flush(void)
 {
-        unsigned int *pg = intel_private.i8xx_flush_page;
+        unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+        /* Forcibly evict everything from the CPU write buffers.
+         * clflush appears to be insufficient.
+         */
+        wbinvd_on_all_cpus();
+        /* Now we've only seen documents for this magic bit on 855GM,
+         * we hope it exists for the other gen2 chipsets...
+         *
+         * Also works as advertised on my 845G.
+         */
+        writel(readl(intel_private.registers+I830_HIC) | (1<<31),
+               intel_private.registers+I830_HIC);
-        memset(pg, 0, 1024);
+        while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
+                if (time_after(jiffies, timeout))
+                        break;
-        if (cpu_has_clflush)
+                udelay(50);
-                clflush_cache_range(pg, 1024);
+        }
-        else if (wbinvd_on_all_cpus() != 0)
-                printk(KERN_ERR "Timed out waiting for cache flush.\n");
 }
 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
@@ -849,8 +837,6 @@ static int i830_setup(void)
        intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
-        intel_i830_setup_flush();
        return 0;
 }
diff --git a/drivers/char/pcmcia/cm4000_cs.c b/drivers/char/pcmcia/cm4000_cs.c
index 777181a2e603..bcbbc71febb7 100644
--- a/drivers/char/pcmcia/cm4000_cs.c
+++ b/drivers/char/pcmcia/cm4000_cs.c
@@ -830,8 +830,7 @@ static void monitor_card(unsigned long p)
                            test_bit(IS_ANY_T1, &dev->flags))) {
                                DEBUGP(4, dev, "Perform AUTOPPS\n");
                                set_bit(IS_AUTOPPS_ACT, &dev->flags);
-                                ptsreq.protocol = ptsreq.protocol =
+                                ptsreq.protocol = (0x01 << dev->proto);
-                                    (0x01 << dev->proto);
                                ptsreq.flags = 0x01;
                                ptsreq.pts1 = 0x00;
                                ptsreq.pts2 = 0x00;
diff --git a/drivers/char/pcmcia/ipwireless/main.c b/drivers/char/pcmcia/ipwireless/main.c
index 94b8eb4d691d..444155a305ae 100644
--- a/drivers/char/pcmcia/ipwireless/main.c
+++ b/drivers/char/pcmcia/ipwireless/main.c
@@ -78,7 +78,6 @@ static void signalled_reboot_callback(void *callback_data)
 static int ipwireless_probe(struct pcmcia_device *p_dev, void *priv_data)
 {
        struct ipw_dev *ipw = priv_data;
-        struct resource *io_resource;
        int ret;
        p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
@@ -92,9 +91,12 @@ static int ipwireless_probe(struct pcmcia_device *p_dev, void *priv_data)
        if (ret)
                return ret;
-        io_resource = request_region(p_dev->resource[0]->start,
+        if (!request_region(p_dev->resource[0]->start,
-                                resource_size(p_dev->resource[0]),
+                            resource_size(p_dev->resource[0]),
-                                IPWIRELESS_PCCARD_NAME);
+                            IPWIRELESS_PCCARD_NAME)) {
+                ret = -EBUSY;
+                goto exit;
+        }
        p_dev->resource[2]->flags |=
                WIN_DATA_WIDTH_16 | WIN_MEMORY_TYPE_CM | WIN_ENABLE;
@@ -105,22 +107,25 @@ static int ipwireless_probe(struct pcmcia_device *p_dev, void *priv_data)
        ret = pcmcia_map_mem_page(p_dev, p_dev->resource[2], p_dev->card_addr);
        if (ret != 0)
-                goto exit2;
+                goto exit1;
        ipw->is_v2_card = resource_size(p_dev->resource[2]) == 0x100;
-        ipw->attr_memory = ioremap(p_dev->resource[2]->start,
+        ipw->common_memory = ioremap(p_dev->resource[2]->start,
                                resource_size(p_dev->resource[2]));
-        request_mem_region(p_dev->resource[2]->start,
+        if (!request_mem_region(p_dev->resource[2]->start,
-                        resource_size(p_dev->resource[2]),
+                                resource_size(p_dev->resource[2]),
-                        IPWIRELESS_PCCARD_NAME);
+                                IPWIRELESS_PCCARD_NAME)) {
+                ret = -EBUSY;
+                goto exit2;
+        }
        p_dev->resource[3]->flags |= WIN_DATA_WIDTH_16 | WIN_MEMORY_TYPE_AM |
                                        WIN_ENABLE;
        p_dev->resource[3]->end = 0; /* this used to be 0x1000 */
        ret = pcmcia_request_window(p_dev, p_dev->resource[3], 0);
        if (ret != 0)
-                goto exit2;
+                goto exit3;
        ret = pcmcia_map_mem_page(p_dev, p_dev->resource[3], 0);
        if (ret != 0)
@@ -128,23 +133,28 @@ static int ipwireless_probe(struct pcmcia_device *p_dev, void *priv_data)
        ipw->attr_memory = ioremap(p_dev->resource[3]->start,
                                resource_size(p_dev->resource[3]));
-        request_mem_region(p_dev->resource[3]->start,
+        if (!request_mem_region(p_dev->resource[3]->start,
-                        resource_size(p_dev->resource[3]),
+                                resource_size(p_dev->resource[3]),
-                        IPWIRELESS_PCCARD_NAME);
+                                IPWIRELESS_PCCARD_NAME)) {
+                ret = -EBUSY;
+                goto exit4;
+        }
        return 0;
+exit4:
+        iounmap(ipw->attr_memory);
 exit3:
+        release_mem_region(p_dev->resource[2]->start,
+                        resource_size(p_dev->resource[2]));
 exit2:
-        if (ipw->common_memory) {
+        iounmap(ipw->common_memory);
-                release_mem_region(p_dev->resource[2]->start,
-                                resource_size(p_dev->resource[2]));
-                iounmap(ipw->common_memory);
-        }
 exit1:
-        release_resource(io_resource);
+        release_region(p_dev->resource[0]->start,
+                       resource_size(p_dev->resource[0]));
+exit:
        pcmcia_disable_device(p_dev);
-        return -1;
+        return ret;
 }
 static int config_ipwireless(struct ipw_dev *ipw)
@@ -219,6 +229,8 @@ exit:
 static void release_ipwireless(struct ipw_dev *ipw)
 {
+        release_region(ipw->link->resource[0]->start,
+                       resource_size(ipw->link->resource[0]));
        if (ipw->common_memory) {
                release_mem_region(ipw->link->resource[2]->start,
                                resource_size(ipw->link->resource[2]));
diff --git a/drivers/char/tpm/tpm.c b/drivers/char/tpm/tpm.c
index 36e0fa161c2b..1f46f1cd9225 100644
--- a/drivers/char/tpm/tpm.c
+++ b/drivers/char/tpm/tpm.c
@@ -364,14 +364,12 @@ unsigned long tpm_calc_ordinal_duration(struct tpm_chip *chip,
                    tpm_protected_ordinal_duration[ordinal &
                                                   TPM_PROTECTED_ORDINAL_MASK];
-        if (duration_idx != TPM_UNDEFINED) {
+        if (duration_idx != TPM_UNDEFINED)
                duration = chip->vendor.duration[duration_idx];
-                /* if duration is 0, it's because chip->vendor.duration wasn't */
+        if (duration <= 0)
-                /* filled yet, so we set the lowest timeout just to give enough */
-                /* time for tpm_get_timeouts() to succeed */
-                return (duration <= 0 ? HZ : duration);
-        } else
                return 2 * 60 * HZ;
+        else
+                return duration;
 }
 EXPORT_SYMBOL_GPL(tpm_calc_ordinal_duration);
diff --git a/drivers/char/virtio_console.c b/drivers/char/virtio_console.c
index 490393186338..84b164d1eb2b 100644
--- a/drivers/char/virtio_console.c
+++ b/drivers/char/virtio_console.c
@@ -388,6 +388,10 @@ static void discard_port_data(struct port *port)
        unsigned int len;
        int ret;
+        if (!port->portdev) {
+                /* Device has been unplugged.  vqs are already gone. */
+                return;
+        }
        vq = port->in_vq;
        if (port->inbuf)
                buf = port->inbuf;
@@ -470,6 +474,10 @@ static void reclaim_consumed_buffers(struct port *port)
        void *buf;
        unsigned int len;
+        if (!port->portdev) {
+                /* Device has been unplugged.  vqs are already gone. */
+                return;
+        }
        while ((buf = virtqueue_get_buf(port->out_vq, &len))) {
                kfree(buf);
                port->outvq_full = false;
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index 1109f6848a43..5cb4d09919d6 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -1919,8 +1919,10 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data)
        ret = sysdev_driver_register(&cpu_sysdev_class,
                                        &cpufreq_sysdev_driver);
+        if (ret)
+                goto err_null_driver;
-        if ((!ret) && !(cpufreq_driver->flags & CPUFREQ_STICKY)) {
+        if (!(cpufreq_driver->flags & CPUFREQ_STICKY)) {
                int i;
                ret = -ENODEV;
@@ -1935,21 +1937,22 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data)
                if (ret) {
                        dprintk("no CPU initialized for driver %s\n",
                                                        driver_data->name);
-                        sysdev_driver_unregister(&cpu_sysdev_class,
+                        goto err_sysdev_unreg;
-                                                &cpufreq_sysdev_driver);
-                        spin_lock_irqsave(&cpufreq_driver_lock, flags);
-                        cpufreq_driver = NULL;
-                        spin_unlock_irqrestore(&cpufreq_driver_lock, flags);
                }
        }
-        if (!ret) {
+        register_hotcpu_notifier(&cpufreq_cpu_notifier);
-                register_hotcpu_notifier(&cpufreq_cpu_notifier);
+        dprintk("driver %s up and running\n", driver_data->name);
-                dprintk("driver %s up and running\n", driver_data->name);
+        cpufreq_debug_enable_ratelimit();
-                cpufreq_debug_enable_ratelimit();
-        }
+        return 0;
+err_sysdev_unreg:
+        sysdev_driver_unregister(&cpu_sysdev_class,
+                        &cpufreq_sysdev_driver);
+err_null_driver:
+        spin_lock_irqsave(&cpufreq_driver_lock, flags);
+        cpufreq_driver = NULL;
+        spin_unlock_irqrestore(&cpufreq_driver_lock, flags);
        return ret;
 }
 EXPORT_SYMBOL_GPL(cpufreq_register_driver);
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 6977a1ce9d98..f73ef4390db6 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -672,7 +672,7 @@ int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info)
        struct drm_crtc_helper_funcs *crtc_funcs;
        u16 *red, *green, *blue, *transp;
        struct drm_crtc *crtc;
-        int i, rc = 0;
+        int i, j, rc = 0;
        int start;
        for (i = 0; i < fb_helper->crtc_count; i++) {
@@ -685,7 +685,7 @@ int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info)
                transp = cmap->transp;
                start = cmap->start;
-                for (i = 0; i < cmap->len; i++) {
+                for (j = 0; j < cmap->len; j++) {
                        u16 hred, hgreen, hblue, htransp = 0xffff;
                        hred = *red++;
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 3dadfa2a8528..28d1d3c24d65 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -164,8 +164,10 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc)
         * available. In that case we can't account for this and just
         * hope for the best.
         */
-        if ((vblrc > 0) && (abs(diff_ns) > 1000000))
+        if ((vblrc > 0) && (abs64(diff_ns) > 1000000)) {
                atomic_inc(&dev->_vblank_count[crtc]);
+                smp_mb__after_atomic_inc();
+        }
        /* Invalidate all timestamps while vblank irq's are off. */
        clear_vblank_timestamps(dev, crtc);
@@ -491,6 +493,12 @@ void drm_calc_timestamping_constants(struct drm_crtc *crtc)
        /* Dot clock in Hz: */
        dotclock = (u64) crtc->hwmode.clock * 1000;
+        /* Fields of interlaced scanout modes are only halve a frame duration.
+         * Double the dotclock to get halve the frame-/line-/pixelduration.
+         */
+        if (crtc->hwmode.flags & DRM_MODE_FLAG_INTERLACE)
+                dotclock *= 2;
        /* Valid dotclock? */
        if (dotclock > 0) {
                /* Convert scanline length in pixels and video dot clock to
@@ -603,14 +611,6 @@ int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, int crtc,
                return -EAGAIN;
        }
-        /* Don't know yet how to handle interlaced or
-         * double scan modes. Just no-op for now.
-         */
-        if (mode->flags & (DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLSCAN)) {
-                DRM_DEBUG("crtc %d: Noop due to unsupported mode.\n", crtc);
-                return -ENOTSUPP;
-        }
        /* Get current scanout position with system timestamp.
         * Repeat query up to DRM_TIMESTAMP_MAXRETRIES times
         * if single query takes longer than max_error nanoseconds.
@@ -858,10 +858,11 @@ static void drm_update_vblank_count(struct drm_device *dev, int crtc)
        if (rc) {
                tslot = atomic_read(&dev->_vblank_count[crtc]) + diff;
                vblanktimestamp(dev, crtc, tslot) = t_vblank;
-                smp_wmb();
        }
+        smp_mb__before_atomic_inc();
        atomic_add(diff, &dev->_vblank_count[crtc]);
+        smp_mb__after_atomic_inc();
 }
 /**
@@ -1011,7 +1012,8 @@ int drm_modeset_ctl(struct drm_device *dev, void *data,
                    struct drm_file *file_priv)
 {
        struct drm_modeset_ctl *modeset = data;
-        int crtc, ret = 0;
+        int ret = 0;
+        unsigned int crtc;
        /* If drm_vblank_init() hasn't been called yet, just no-op */
        if (!dev->num_crtcs)
@@ -1293,15 +1295,16 @@ bool drm_handle_vblank(struct drm_device *dev, int crtc)
         * e.g., due to spurious vblank interrupts. We need to
         * ignore those for accounting.
         */
-        if (abs(diff_ns) > DRM_REDUNDANT_VBLIRQ_THRESH_NS) {
+        if (abs64(diff_ns) > DRM_REDUNDANT_VBLIRQ_THRESH_NS) {
                /* Store new timestamp in ringbuffer. */
                vblanktimestamp(dev, crtc, vblcount + 1) = tvblank;
-                smp_wmb();
                /* Increment cooked vblank count. This also atomically commits
                 * the timestamp computed above.
                 */
+                smp_mb__before_atomic_inc();
                atomic_inc(&dev->_vblank_count[crtc]);
+                smp_mb__after_atomic_inc();
        } else {
                DRM_DEBUG("crtc %d: Redundant vblirq ignored. diff_ns = %d\n",
                          crtc, (int) diff_ns);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3601466c5502..4ff9b6cc973f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -865,7 +865,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
                int max_freq;
                /* RPSTAT1 is in the GT power well */
-                __gen6_force_wake_get(dev_priv);
+                __gen6_gt_force_wake_get(dev_priv);
                seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
                seq_printf(m, "RPSTAT1: 0x%08x\n", I915_READ(GEN6_RPSTAT1));
@@ -888,7 +888,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
                seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
                           max_freq * 100);
-                __gen6_force_wake_put(dev_priv);
+                __gen6_gt_force_wake_put(dev_priv);
        } else {
                seq_printf(m, "no P-state info available\n");
        }
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 17bd766f2081..e33d9be7df3b 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1895,6 +1895,17 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        if (IS_GEN2(dev))
                dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
+        /* 965GM sometimes incorrectly writes to hardware status page (HWS)
+         * using 32bit addressing, overwriting memory if HWS is located
+         * above 4GB.
+         *
+         * The documentation also mentions an issue with undefined
+         * behaviour if any general state is accessed within a page above 4GB,
+         * which also needs to be handled carefully.
+         */
+        if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
+                dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
        mmio_bar = IS_GEN2(dev) ? 1 : 0;
        dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
        if (!dev_priv->regs) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0ad533f06af9..22ec066adae6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -46,6 +46,9 @@ module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
 unsigned int i915_powersave = 1;
 module_param_named(powersave, i915_powersave, int, 0600);
+unsigned int i915_semaphores = 0;
+module_param_named(semaphores, i915_semaphores, int, 0600);
 unsigned int i915_enable_rc6 = 0;
 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
@@ -254,7 +257,7 @@ void intel_detect_pch (struct drm_device *dev)
        }
 }
-void __gen6_force_wake_get(struct drm_i915_private *dev_priv)
+void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 {
        int count;
@@ -270,12 +273,22 @@ void __gen6_force_wake_get(struct drm_i915_private *dev_priv)
                udelay(10);
 }
-void __gen6_force_wake_put(struct drm_i915_private *dev_priv)
+void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 {
        I915_WRITE_NOTRACE(FORCEWAKE, 0);
        POSTING_READ(FORCEWAKE);
 }
+void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
+{
+        int loop = 500;
+        u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
+        while (fifo < 20 && loop--) {
+                udelay(10);
+                fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
+        }
+}
 static int i915_drm_freeze(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 65dfe81d0035..456f40484838 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -956,6 +956,7 @@ extern struct drm_ioctl_desc i915_ioctls[];
 extern int i915_max_ioctl;
 extern unsigned int i915_fbpercrtc;
 extern unsigned int i915_powersave;
+extern unsigned int i915_semaphores;
 extern unsigned int i915_lvds_downclock;
 extern unsigned int i915_panel_use_ssc;
 extern unsigned int i915_enable_rc6;
@@ -1177,6 +1178,9 @@ void i915_gem_detach_phys_object(struct drm_device *dev,
 void i915_gem_free_all_phys_object(struct drm_device *dev);
 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
+uint32_t
+i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);
 /* i915_gem_gtt.c */
 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
@@ -1353,22 +1357,32 @@ __i915_write(64, q)
 * must be set to prevent GT core from power down and stale values being
 * returned.
 */
-void __gen6_force_wake_get(struct drm_i915_private *dev_priv);
+void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
-void __gen6_force_wake_put (struct drm_i915_private *dev_priv);
+void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
-static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
+void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
+static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)
 {
        u32 val;
        if (dev_priv->info->gen >= 6) {
-                __gen6_force_wake_get(dev_priv);
+                __gen6_gt_force_wake_get(dev_priv);
                val = I915_READ(reg);
-                __gen6_force_wake_put(dev_priv);
+                __gen6_gt_force_wake_put(dev_priv);
        } else
                val = I915_READ(reg);
        return val;
 }
+static inline void i915_gt_write(struct drm_i915_private *dev_priv,
+                                u32 reg, u32 val)
+{
+        if (dev_priv->info->gen >= 6)
+                __gen6_gt_wait_for_fifo(dev_priv);
+        I915_WRITE(reg, val);
+}
 static inline void
 i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
 {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index cf4f74c7c6fb..36e66cc5225e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1398,7 +1398,7 @@ i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
 * Return the required GTT alignment for an object, only taking into account
 * unfenced tiled surface requirements.
 */
-static uint32_t
+uint32_t
 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
 {
        struct drm_device *dev = obj->base.dev;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index d2f445e825f2..50ab1614571c 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -772,8 +772,8 @@ i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
        if (from == NULL || to == from)
                return 0;
-        /* XXX gpu semaphores are currently causing hard hangs on SNB mobile */
+        /* XXX gpu semaphores are implicated in various hard hangs on SNB */
-        if (INTEL_INFO(obj->base.dev)->gen < 6 || IS_MOBILE(obj->base.dev))
+        if (INTEL_INFO(obj->base.dev)->gen < 6 || !i915_semaphores)
                return i915_gem_object_wait_rendering(obj, true);
        idx = intel_ring_sync_index(from, to);
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 22a32b9932c5..d64843e18df2 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -349,14 +349,27 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
                        (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
                         i915_gem_object_fence_ok(obj, args->tiling_mode));
-                obj->tiling_changed = true;
+                /* Rebind if we need a change of alignment */
-                obj->tiling_mode = args->tiling_mode;
+                if (!obj->map_and_fenceable) {
-                obj->stride = args->stride;
+                        u32 unfenced_alignment =
+                                i915_gem_get_unfenced_gtt_alignment(obj);
+                        if (obj->gtt_offset & (unfenced_alignment - 1))
+                                ret = i915_gem_object_unbind(obj);
+                }
+                if (ret == 0) {
+                        obj->tiling_changed = true;
+                        obj->tiling_mode = args->tiling_mode;
+                        obj->stride = args->stride;
+                }
        }
+        /* we have to maintain this existing ABI... */
+        args->stride = obj->stride;
+        args->tiling_mode = obj->tiling_mode;
        drm_gem_object_unreference(&obj->base);
        mutex_unlock(&dev->struct_mutex);
-        return 0;
+        return ret;
 }
 /**
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 97f946dcc1aa..8a9e08bf1cf7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -316,6 +316,8 @@ static void i915_hotplug_work_func(struct work_struct *work)
        struct drm_mode_config *mode_config = &dev->mode_config;
        struct intel_encoder *encoder;
+        DRM_DEBUG_KMS("running encoder hotplug functions\n");
        list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
                if (encoder->hot_plug)
                        encoder->hot_plug(encoder);
@@ -1649,9 +1651,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
        } else {
                hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
                               SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
-                hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK;
+                hotplug_mask |= SDE_AUX_MASK;
-                I915_WRITE(FDI_RXA_IMR, 0);
-                I915_WRITE(FDI_RXB_IMR, 0);
        }
        dev_priv->pch_irq_mask = ~hotplug_mask;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 729d4233b763..3e6f486f4605 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3261,6 +3261,8 @@
 #define  FORCEWAKE                              0xA18C
 #define  FORCEWAKE_ACK                          0x130090
+#define  GT_FIFO_FREE_ENTRIES                   0x120008
 #define GEN6_RPNSWREQ                           0xA008
 #define   GEN6_TURBO_DISABLE                    (1<<31)
 #define   GEN6_FREQUENCY(x)                     ((x)<<25)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b006536b3d2..49fb54fd9a18 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1219,7 +1219,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
        u32 blt_ecoskpd;
        /* Make sure blitter notifies FBC of writes */
-        __gen6_force_wake_get(dev_priv);
+        __gen6_gt_force_wake_get(dev_priv);
        blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
        blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
                GEN6_BLITTER_LOCK_SHIFT;
@@ -1230,7 +1230,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
                         GEN6_BLITTER_LOCK_SHIFT);
        I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
        POSTING_READ(GEN6_BLITTER_ECOSKPD);
-        __gen6_force_wake_put(dev_priv);
+        __gen6_gt_force_wake_put(dev_priv);
 }
 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
@@ -1630,19 +1630,19 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
                wait_event(dev_priv->pending_flip_queue,
+                           atomic_read(&dev_priv->mm.wedged) ||
                           atomic_read(&obj->pending_flip) == 0);
                /* Big Hammer, we also need to ensure that any pending
                 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
                 * current scanout is retired before unpinning the old
                 * framebuffer.
+                 *
+                 * This should only fail upon a hung GPU, in which case we
+                 * can safely continue.
                 */
                ret = i915_gem_object_flush_gpu(obj, false);
-                if (ret) {
+                (void) ret;
-                        i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
-                        mutex_unlock(&dev->struct_mutex);
-                        return ret;
-                }
        }
        ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
@@ -2045,6 +2045,31 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
                   atomic_read(&obj->pending_flip) == 0);
 }
+static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
+{
+        struct drm_device *dev = crtc->dev;
+        struct drm_mode_config *mode_config = &dev->mode_config;
+        struct intel_encoder *encoder;
+        /*
+         * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
+         * must be driven by its own crtc; no sharing is possible.
+         */
+        list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
+                if (encoder->base.crtc != crtc)
+                        continue;
+                switch (encoder->type) {
+                case INTEL_OUTPUT_EDP:
+                        if (!intel_encoder_is_pch_edp(&encoder->base))
+                                return false;
+                        continue;
+                }
+        }
+        return true;
+}
 static void ironlake_crtc_enable(struct drm_crtc *crtc)
 {
        struct drm_device *dev = crtc->dev;
@@ -2053,6 +2078,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
        int pipe = intel_crtc->pipe;
        int plane = intel_crtc->plane;
        u32 reg, temp;
+        bool is_pch_port = false;
        if (intel_crtc->active)
                return;
@@ -2066,7 +2092,56 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
                        I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
        }
-        ironlake_fdi_enable(crtc);
+        is_pch_port = intel_crtc_driving_pch(crtc);
+        if (is_pch_port)
+                ironlake_fdi_enable(crtc);
+        else {
+                /* disable CPU FDI tx and PCH FDI rx */
+                reg = FDI_TX_CTL(pipe);
+                temp = I915_READ(reg);
+                I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
+                POSTING_READ(reg);
+                reg = FDI_RX_CTL(pipe);
+                temp = I915_READ(reg);
+                temp &= ~(0x7 << 16);
+                temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
+                I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
+                POSTING_READ(reg);
+                udelay(100);
+                /* Ironlake workaround, disable clock pointer after downing FDI */
+                if (HAS_PCH_IBX(dev))
+                        I915_WRITE(FDI_RX_CHICKEN(pipe),
+                                   I915_READ(FDI_RX_CHICKEN(pipe) &
+                                             ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
+                /* still set train pattern 1 */
+                reg = FDI_TX_CTL(pipe);
+                temp = I915_READ(reg);
+                temp &= ~FDI_LINK_TRAIN_NONE;
+                temp |= FDI_LINK_TRAIN_PATTERN_1;
+                I915_WRITE(reg, temp);
+                reg = FDI_RX_CTL(pipe);
+                temp = I915_READ(reg);
+                if (HAS_PCH_CPT(dev)) {
+                        temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+                        temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+                } else {
+                        temp &= ~FDI_LINK_TRAIN_NONE;
+                        temp |= FDI_LINK_TRAIN_PATTERN_1;
+                }
+                /* BPC in FDI rx is consistent with that in PIPECONF */
+                temp &= ~(0x07 << 16);
+                temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
+                I915_WRITE(reg, temp);
+                POSTING_READ(reg);
+                udelay(100);
+        }
        /* Enable panel fitting for LVDS */
        if (dev_priv->pch_pf_size &&
@@ -2100,6 +2175,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
                intel_flush_display_plane(dev, plane);
        }
+        /* Skip the PCH stuff if possible */
+        if (!is_pch_port)
+                goto done;
        /* For PCH output, training FDI link */
        if (IS_GEN6(dev))
                gen6_fdi_link_train(crtc);
@@ -2184,7 +2263,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
        I915_WRITE(reg, temp | TRANS_ENABLE);
        if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
                DRM_ERROR("failed to enable transcoder %d\n", pipe);
+done:
        intel_crtc_load_lut(crtc);
        intel_update_fbc(dev);
        intel_crtc_update_cursor(crtc, true);
@@ -6203,7 +6282,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
         * userspace...
         */
        I915_WRITE(GEN6_RC_STATE, 0);
-        __gen6_force_wake_get(dev_priv);
+        __gen6_gt_force_wake_get(dev_priv);
        /* disable the counters and set deterministic thresholds */
        I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -6301,7 +6380,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
        /* enable all PM interrupts */
        I915_WRITE(GEN6_PMINTRMSK, 0);
-        __gen6_force_wake_put(dev_priv);
+        __gen6_gt_force_wake_put(dev_priv);
 }
 void intel_enable_clock_gating(struct drm_device *dev)
@@ -6496,7 +6575,7 @@ static void ironlake_disable_rc6(struct drm_device *dev)
                POSTING_READ(RSTDBYCTL);
        }
-        ironlake_disable_rc6(dev);
+        ironlake_teardown_rc6(dev);
 }
 static int ironlake_setup_rc6(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 6d6fde85a636..34306865a5df 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -14,22 +14,23 @@ struct  intel_hw_status_page {
        struct          drm_i915_gem_object *obj;
 };
-#define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
+#define I915_RING_READ(reg) i915_gt_read(dev_priv, reg)
+#define I915_RING_WRITE(reg, val) i915_gt_write(dev_priv, reg, val)
 #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
-#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
+#define I915_WRITE_TAIL(ring, val) I915_RING_WRITE(RING_TAIL((ring)->mmio_base), val)
 #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
-#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
+#define I915_WRITE_START(ring, val) I915_RING_WRITE(RING_START((ring)->mmio_base), val)
 #define I915_READ_HEAD(ring)  I915_RING_READ(RING_HEAD((ring)->mmio_base))
-#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
+#define I915_WRITE_HEAD(ring, val) I915_RING_WRITE(RING_HEAD((ring)->mmio_base), val)
 #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
-#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
+#define I915_WRITE_CTL(ring, val) I915_RING_WRITE(RING_CTL((ring)->mmio_base), val)
-#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
 #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
+#define I915_WRITE_IMR(ring, val) I915_RING_WRITE(RING_IMR((ring)->mmio_base), val)
 #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
 #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index d38a4d9f9b0b..a52184007f5f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -49,7 +49,10 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
                DRM_ERROR("bo %p still attached to GEM object\n", bo);
        nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
-        nouveau_vm_put(&nvbo->vma);
+        if (nvbo->vma.node) {
+                nouveau_vm_unmap(&nvbo->vma);
+                nouveau_vm_put(&nvbo->vma);
+        }
        kfree(nvbo);
 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c
index 65699bfaaaea..b368ed74aad7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c
@@ -83,7 +83,8 @@ nouveau_dma_init(struct nouveau_channel *chan)
                return ret;
        /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
-        ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
+        ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfd0, 0x1000,
+                                     &chan->m2mf_ntfy);
        if (ret)
                return ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 9821fcacc3d2..982d70b12722 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -852,7 +852,8 @@ extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
 extern int  nouveau_notifier_init_channel(struct nouveau_channel *);
 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
 extern int  nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
-                                   int cout, uint32_t *offset);
+                                   int cout, uint32_t start, uint32_t end,
+                                   uint32_t *offset);
 extern int  nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
 extern int  nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
                                         struct drm_file *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 26347b7cd872..b0fb9bdcddb7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -725,8 +725,10 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
        ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
                        mem->page_alignment << PAGE_SHIFT, size_nc,
                        (nvbo->tile_flags >> 8) & 0xff, &node);
-        if (ret)
+        if (ret) {
-                return ret;
+                mem->mm_node = NULL;
+                return (ret == -ENOSPC) ? 0 : ret;
+        }
        node->page_shift = 12;
        if (nvbo->vma.node)
diff --git a/drivers/gpu/drm/nouveau/nouveau_mm.c b/drivers/gpu/drm/nouveau/nouveau_mm.c
index 8844b50c3e54..7609756b6faf 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mm.c
@@ -123,7 +123,7 @@ nouveau_mm_get(struct nouveau_mm *rmm, int type, u32 size, u32 size_nc,
                return 0;
        }
-        return -ENOMEM;
+        return -ENOSPC;
 }
 int
diff --git a/drivers/gpu/drm/nouveau/nouveau_notifier.c b/drivers/gpu/drm/nouveau/nouveau_notifier.c
index fe29d604b820..5ea167623a82 100644
--- a/drivers/gpu/drm/nouveau/nouveau_notifier.c
+++ b/drivers/gpu/drm/nouveau/nouveau_notifier.c
@@ -96,7 +96,8 @@ nouveau_notifier_gpuobj_dtor(struct drm_device *dev,
 int
 nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle,
-                       int size, uint32_t *b_offset)
+                       int size, uint32_t start, uint32_t end,
+                       uint32_t *b_offset)
 {
        struct drm_device *dev = chan->dev;
        struct nouveau_gpuobj *nobj = NULL;
@@ -104,9 +105,10 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle,
        uint32_t offset;
        int target, ret;
-        mem = drm_mm_search_free(&chan->notifier_heap, size, 0, 0);
+        mem = drm_mm_search_free_in_range(&chan->notifier_heap, size, 0,
+                                          start, end, 0);
        if (mem)
-                mem = drm_mm_get_block(mem, size, 0);
+                mem = drm_mm_get_block_range(mem, size, 0, start, end);
        if (!mem) {
                NV_ERROR(dev, "Channel %d notifier block full\n", chan->id);
                return -ENOMEM;
@@ -177,7 +179,8 @@ nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data,
        if (IS_ERR(chan))
                return PTR_ERR(chan);
-        ret = nouveau_notifier_alloc(chan, na->handle, na->size, &na->offset);
+        ret = nouveau_notifier_alloc(chan, na->handle, na->size, 0, 0x1000,
+                                     &na->offset);
        nouveau_channel_put(&chan);
        return ret;
 }
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
index ea0041810ae3..e57caa2a00e3 100644
--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
@@ -403,16 +403,24 @@ nv50_instmem_unmap(struct nouveau_gpuobj *gpuobj)
 void
 nv50_instmem_flush(struct drm_device *dev)
 {
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        spin_lock(&dev_priv->ramin_lock);
        nv_wr32(dev, 0x00330c, 0x00000001);
        if (!nv_wait(dev, 0x00330c, 0x00000002, 0x00000000))
                NV_ERROR(dev, "PRAMIN flush timeout\n");
+        spin_unlock(&dev_priv->ramin_lock);
 }
 void
 nv84_instmem_flush(struct drm_device *dev)
 {
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        spin_lock(&dev_priv->ramin_lock);
        nv_wr32(dev, 0x070000, 0x00000001);
        if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000))
                NV_ERROR(dev, "PRAMIN flush timeout\n");
+        spin_unlock(&dev_priv->ramin_lock);
 }
diff --git a/drivers/gpu/drm/nouveau/nv50_vm.c b/drivers/gpu/drm/nouveau/nv50_vm.c
index 459ff08241e5..6144156f255a 100644
--- a/drivers/gpu/drm/nouveau/nv50_vm.c
+++ b/drivers/gpu/drm/nouveau/nv50_vm.c
@@ -169,7 +169,11 @@ nv50_vm_flush(struct nouveau_vm *vm)
 void
 nv50_vm_flush_engine(struct drm_device *dev, int engine)
 {
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        spin_lock(&dev_priv->ramin_lock);
        nv_wr32(dev, 0x100c80, (engine << 16) | 1);
        if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000))
                NV_ERROR(dev, "vm flush timeout: engine %d\n", engine);
+        spin_unlock(&dev_priv->ramin_lock);
 }
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 56deae5bf02e..93fa735c8c1a 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3490,7 +3490,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
                track->num_texture = 16;
                track->maxy = 4096;
                track->separate_cube = 0;
-                track->aaresolve = true;
+                track->aaresolve = false;
                track->aa.robj = NULL;
        }
@@ -3801,8 +3801,6 @@ static int r100_startup(struct radeon_device *rdev)
        r100_mc_program(rdev);
        /* Resume clock */
        r100_clock_startup(rdev);
-        /* Initialize GPU configuration (# pipes, ...) */
-//      r100_gpu_init(rdev);
        /* Initialize GART (initialize after TTM so we can allocate
         * memory through TTM but finalize after TTM) */
        r100_enable_bm(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 0e657095de7c..3e7e7f9eb781 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -971,7 +971,7 @@ void radeon_compute_pll_legacy(struct radeon_pll *pll,
                max_fractional_feed_div = pll->max_frac_feedback_div;
        }
-        for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
+        for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
                uint32_t ref_div;
                if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 66324b5bb5ba..cc44bdfec80f 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -113,11 +113,14 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
        u32 tiling_flags = 0;
        int ret;
        int aligned_size, size;
+        int height = mode_cmd->height;
        /* need to align pitch with crtc limits */
        mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);
-        size = mode_cmd->pitch * mode_cmd->height;
+        if (rdev->family >= CHIP_R600)
+                height = ALIGN(mode_cmd->height, 8);
+        size = mode_cmd->pitch * height;
        aligned_size = ALIGN(size, PAGE_SIZE);
        ret = radeon_gem_object_create(rdev, aligned_size, 0,
                                       RADEON_GEM_DOMAIN_VRAM,
diff --git a/drivers/hwmon/ad7414.c b/drivers/hwmon/ad7414.c
index 86d822aa9bbf..d46c0c758ddf 100644
--- a/drivers/hwmon/ad7414.c
+++ b/drivers/hwmon/ad7414.c
@@ -242,6 +242,7 @@ static const struct i2c_device_id ad7414_id[] = {
        { "ad7414", 0 },
        {}
 };
+MODULE_DEVICE_TABLE(i2c, ad7414_id);
 static struct i2c_driver ad7414_driver = {
        .driver = {
diff --git a/drivers/hwmon/adt7411.c b/drivers/hwmon/adt7411.c
index f13c843a2964..5cc3e3784b42 100644
--- a/drivers/hwmon/adt7411.c
+++ b/drivers/hwmon/adt7411.c
@@ -334,6 +334,7 @@ static const struct i2c_device_id adt7411_id[] = {
        { "adt7411", 0 },
        { }
 };
+MODULE_DEVICE_TABLE(i2c, adt7411_id);
 static struct i2c_driver adt7411_driver = {
        .driver         = {
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index b605ff3a1fa0..829a2a1029f7 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -847,11 +847,15 @@ complete:
                        dev_err(dev->dev, "Arbitration lost\n");
                        err |= OMAP_I2C_STAT_AL;
                }
+                /*
+                 * ProDB0017052: Clear ARDY bit twice
+                 */
                if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
                                        OMAP_I2C_STAT_AL)) {
                        omap_i2c_ack_stat(dev, stat &
                                (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
-                                OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
+                                OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
+                                OMAP_I2C_STAT_ARDY));
                        omap_i2c_complete_cmd(dev, err);
                        return IRQ_HANDLED;
                }
@@ -1137,12 +1141,41 @@ omap_i2c_remove(struct platform_device *pdev)
        return 0;
 }
+#ifdef CONFIG_SUSPEND
+static int omap_i2c_suspend(struct device *dev)
+{
+        if (!pm_runtime_suspended(dev))
+                if (dev->bus && dev->bus->pm && dev->bus->pm->runtime_suspend)
+                        dev->bus->pm->runtime_suspend(dev);
+        return 0;
+}
+static int omap_i2c_resume(struct device *dev)
+{
+        if (!pm_runtime_suspended(dev))
+                if (dev->bus && dev->bus->pm && dev->bus->pm->runtime_resume)
+                        dev->bus->pm->runtime_resume(dev);
+        return 0;
+}
+static struct dev_pm_ops omap_i2c_pm_ops = {
+        .suspend = omap_i2c_suspend,
+        .resume = omap_i2c_resume,
+};
+#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
+#else
+#define OMAP_I2C_PM_OPS NULL
+#endif
 static struct platform_driver omap_i2c_driver = {
        .probe          = omap_i2c_probe,
        .remove         = omap_i2c_remove,
        .driver         = {
                .name   = "omap_i2c",
                .owner  = THIS_MODULE,
+                .pm     = OMAP_I2C_PM_OPS,
        },
 };
diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
index 495be451d326..266135ddf7fa 100644
--- a/drivers/i2c/busses/i2c-stu300.c
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -942,7 +942,7 @@ stu300_probe(struct platform_device *pdev)
        adap->owner = THIS_MODULE;
        /* DDC class but actually often used for more generic I2C */
        adap->class = I2C_CLASS_DDC;
-        strncpy(adap->name, "ST Microelectronics DDC I2C adapter",
+        strlcpy(adap->name, "ST Microelectronics DDC I2C adapter",
                sizeof(adap->name));
        adap->nr = bus_nr;
        adap->algo = &stu300_algo;
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 1fa091e05690..4a5c4a44ffb1 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -62,6 +62,7 @@
 #include <linux/notifier.h>
 #include <linux/cpu.h>
 #include <asm/mwait.h>
+#include <asm/msr.h>
 #define INTEL_IDLE_VERSION "0.4"
 #define PREFIX "intel_idle: "
@@ -85,6 +86,12 @@ static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
 static struct cpuidle_state *cpuidle_state_table;
 /*
+ * Hardware C-state auto-demotion may not always be optimal.
+ * Indicate which enable bits to clear here.
+ */
+static unsigned long long auto_demotion_disable_flags;
+/*
 * Set this flag for states where the HW flushes the TLB for us
 * and so we don't need cross-calls to keep it consistent.
 * If this flag is set, SW flushes the TLB, so even if the
@@ -281,6 +288,15 @@ static struct notifier_block setup_broadcast_notifier = {
        .notifier_call = setup_broadcast_cpuhp_notify,
 };
+static void auto_demotion_disable(void *dummy)
+{
+        unsigned long long msr_bits;
+        rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
+        msr_bits &= ~auto_demotion_disable_flags;
+        wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
+}
 /*
 * intel_idle_probe()
 */
@@ -324,11 +340,17 @@ static int intel_idle_probe(void)
        case 0x25:      /* Westmere */
        case 0x2C:      /* Westmere */
                cpuidle_state_table = nehalem_cstates;
+                auto_demotion_disable_flags =
+                        (NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE);
                break;
        case 0x1C:      /* 28 - Atom Processor */
+                cpuidle_state_table = atom_cstates;
+                break;
        case 0x26:      /* 38 - Lincroft Atom Processor */
                cpuidle_state_table = atom_cstates;
+                auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE;
                break;
        case 0x2A:      /* SNB */
@@ -436,6 +458,8 @@ static int intel_idle_cpuidle_devices_init(void)
                        return -EIO;
                }
        }
+        if (auto_demotion_disable_flags)
+                smp_call_function(auto_demotion_disable, NULL, 1);
        return 0;
 }
diff --git a/drivers/input/gameport/gameport.c b/drivers/input/gameport/gameport.c
index 23cf8fc933ec..5b8f59d6c3e8 100644
--- a/drivers/input/gameport/gameport.c
+++ b/drivers/input/gameport/gameport.c
@@ -360,7 +360,7 @@ static int gameport_queue_event(void *object, struct module *owner,
        event->owner = owner;
        list_add_tail(&event->node, &gameport_event_list);
-        schedule_work(&gameport_event_work);
+        queue_work(system_long_wq, &gameport_event_work);
 out:
        spin_unlock_irqrestore(&gameport_event_lock, flags);
diff --git a/drivers/input/keyboard/tegra-kbc.c b/drivers/input/keyboard/tegra-kbc.c
index ac471b77c18e..99ce9032d08c 100644
--- a/drivers/input/keyboard/tegra-kbc.c
+++ b/drivers/input/keyboard/tegra-kbc.c
@@ -71,8 +71,9 @@ struct tegra_kbc {
        spinlock_t lock;
        unsigned int repoll_dly;
        unsigned long cp_dly_jiffies;
+        bool use_fn_map;
        const struct tegra_kbc_platform_data *pdata;
-        unsigned short keycode[KBC_MAX_KEY];
+        unsigned short keycode[KBC_MAX_KEY * 2];
        unsigned short current_keys[KBC_MAX_KPENT];
        unsigned int num_pressed_keys;
        struct timer_list timer;
@@ -178,6 +179,40 @@ static const u32 tegra_kbc_default_keymap[] = {
        KEY(15, 5, KEY_F2),
        KEY(15, 6, KEY_CAPSLOCK),
        KEY(15, 7, KEY_F6),
+        /* Software Handled Function Keys */
+        KEY(20, 0, KEY_KP7),
+        KEY(21, 0, KEY_KP9),
+        KEY(21, 1, KEY_KP8),
+        KEY(21, 2, KEY_KP4),
+        KEY(21, 4, KEY_KP1),
+        KEY(22, 1, KEY_KPSLASH),
+        KEY(22, 2, KEY_KP6),
+        KEY(22, 3, KEY_KP5),
+        KEY(22, 4, KEY_KP3),
+        KEY(22, 5, KEY_KP2),
+        KEY(22, 7, KEY_KP0),
+        KEY(27, 1, KEY_KPASTERISK),
+        KEY(27, 3, KEY_KPMINUS),
+        KEY(27, 4, KEY_KPPLUS),
+        KEY(27, 5, KEY_KPDOT),
+        KEY(28, 5, KEY_VOLUMEUP),
+        KEY(29, 3, KEY_HOME),
+        KEY(29, 4, KEY_END),
+        KEY(29, 5, KEY_BRIGHTNESSDOWN),
+        KEY(29, 6, KEY_VOLUMEDOWN),
+        KEY(29, 7, KEY_BRIGHTNESSUP),
+        KEY(30, 0, KEY_NUMLOCK),
+        KEY(30, 1, KEY_SCROLLLOCK),
+        KEY(30, 2, KEY_MUTE),
+        KEY(31, 4, KEY_HELP),
 };
 static const struct matrix_keymap_data tegra_kbc_default_keymap_data = {
@@ -224,6 +259,7 @@ static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
        unsigned int i;
        unsigned int num_down = 0;
        unsigned long flags;
+        bool fn_keypress = false;
        spin_lock_irqsave(&kbc->lock, flags);
        for (i = 0; i < KBC_MAX_KPENT; i++) {
@@ -237,11 +273,28 @@ static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
                                MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
                        scancodes[num_down] = scancode;
-                        keycodes[num_down++] = kbc->keycode[scancode];
+                        keycodes[num_down] = kbc->keycode[scancode];
+                        /* If driver uses Fn map, do not report the Fn key. */
+                        if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
+                                fn_keypress = true;
+                        else
+                                num_down++;
                }
                val >>= 8;
        }
+        /*
+         * If the platform uses Fn keymaps, translate keys on a Fn keypress.
+         * Function keycodes are KBC_MAX_KEY apart from the plain keycodes.
+         */
+        if (fn_keypress) {
+                for (i = 0; i < num_down; i++) {
+                        scancodes[i] += KBC_MAX_KEY;
+                        keycodes[i] = kbc->keycode[scancodes[i]];
+                }
+        }
        spin_unlock_irqrestore(&kbc->lock, flags);
        tegra_kbc_report_released_keys(kbc->idev,
@@ -594,8 +647,11 @@ static int __devinit tegra_kbc_probe(struct platform_device *pdev)
        input_dev->keycode = kbc->keycode;
        input_dev->keycodesize = sizeof(kbc->keycode[0]);
-        input_dev->keycodemax = ARRAY_SIZE(kbc->keycode);
+        input_dev->keycodemax = KBC_MAX_KEY;
+        if (pdata->use_fn_map)
+                input_dev->keycodemax *= 2;
+        kbc->use_fn_map = pdata->use_fn_map;
        keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data;
        matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT,
                                   input_dev->keycode, input_dev->keybit);
diff --git a/drivers/input/mouse/synaptics.h b/drivers/input/mouse/synaptics.h
index 25e5d042a72c..7453938bf5ef 100644
--- a/drivers/input/mouse/synaptics.h
+++ b/drivers/input/mouse/synaptics.h
@@ -51,6 +51,29 @@
 #define SYN_EXT_CAP_REQUESTS(c)         (((c) & 0x700000) >> 20)
 #define SYN_CAP_MULTI_BUTTON_NO(ec)     (((ec) & 0x00f000) >> 12)
 #define SYN_CAP_PRODUCT_ID(ec)          (((ec) & 0xff0000) >> 16)
+/*
+ * The following describes response for the 0x0c query.
+ *
+ * byte mask    name                    meaning
+ * ---- ----    -------                 ------------
+ * 1    0x01    adjustable threshold    capacitive button sensitivity
+ *                                      can be adjusted
+ * 1    0x02    report max              query 0x0d gives max coord reported
+ * 1    0x04    clearpad                sensor is ClearPad product
+ * 1    0x08    advanced gesture        not particularly meaningful
+ * 1    0x10    clickpad bit 0          1-button ClickPad
+ * 1    0x60    multifinger mode        identifies firmware finger counting
+ *                                      (not reporting!) algorithm.
+ *                                      Not particularly meaningful
+ * 1    0x80    covered pad             W clipped to 14, 15 == pad mostly covered
+ * 2    0x01    clickpad bit 1          2-button ClickPad
+ * 2    0x02    deluxe LED controls     touchpad support LED commands
+ *                                      ala multimedia control bar
+ * 2    0x04    reduced filtering       firmware does less filtering on
+ *                                      position data, driver should watch
+ *                                      for noise.
+ */
 #define SYN_CAP_CLICKPAD(ex0c)          ((ex0c) & 0x100000) /* 1-button ClickPad */
 #define SYN_CAP_CLICKPAD2BTN(ex0c)      ((ex0c) & 0x000100) /* 2-button ClickPad */
 #define SYN_CAP_MAX_DIMENSIONS(ex0c)    ((ex0c) & 0x020000)
diff --git a/drivers/input/serio/serio.c b/drivers/input/serio/serio.c
index 7c38d1fbabf2..ba70058e2be3 100644
--- a/drivers/input/serio/serio.c
+++ b/drivers/input/serio/serio.c
@@ -299,7 +299,7 @@ static int serio_queue_event(void *object, struct module *owner,
        event->owner = owner;
        list_add_tail(&event->node, &serio_event_list);
-        schedule_work(&serio_event_work);
+        queue_work(system_long_wq, &serio_event_work);
 out:
        spin_unlock_irqrestore(&serio_event_lock, flags);
diff --git a/drivers/isdn/hardware/eicon/istream.c b/drivers/isdn/hardware/eicon/istream.c
index 18f8798442fa..7bd5baa547be 100644
--- a/drivers/isdn/hardware/eicon/istream.c
+++ b/drivers/isdn/hardware/eicon/istream.c
@@ -62,7 +62,7 @@ void diva_xdi_provide_istream_info (ADAPTER* a,
  stream interface.
  If synchronous service was requested, then function
  does return amount of data written to stream.
-  'final' does indicate that pice of data to be written is
+  'final' does indicate that piece of data to be written is
  final part of frame (necessary only by structured datatransfer)
  return  0 if zero lengh packet was written
  return -1 if stream is full
diff --git a/drivers/md/linear.c b/drivers/md/linear.c
index 8a2f767f26d8..0ed7f6bc2a7f 100644
--- a/drivers/md/linear.c
+++ b/drivers/md/linear.c
@@ -216,7 +216,6 @@ static int linear_run (mddev_t *mddev)
        if (md_check_no_bitmap(mddev))
                return -EINVAL;
-        mddev->queue->queue_lock = &mddev->queue->__queue_lock;
        conf = linear_conf(mddev, mddev->raid_disks);
        if (!conf)
diff --git a/drivers/md/md.c b/drivers/md/md.c
index 0cc30ecda4c1..818313e277e7 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -553,6 +553,9 @@ static mddev_t * mddev_find(dev_t unit)
 {
        mddev_t *mddev, *new = NULL;
+        if (unit && MAJOR(unit) != MD_MAJOR)
+                unit &= ~((1<<MdpMinorShift)-1);
 retry:
        spin_lock(&all_mddevs_lock);
@@ -4138,10 +4141,10 @@ array_size_store(mddev_t *mddev, const char *buf, size_t len)
        }
        mddev->array_sectors = sectors;
-        set_capacity(mddev->gendisk, mddev->array_sectors);
+        if (mddev->pers) {
-        if (mddev->pers)
+                set_capacity(mddev->gendisk, mddev->array_sectors);
                revalidate_disk(mddev->gendisk);
+        }
        return len;
 }
@@ -4624,6 +4627,7 @@ static int do_md_run(mddev_t *mddev)
        }
        set_capacity(mddev->gendisk, mddev->array_sectors);
        revalidate_disk(mddev->gendisk);
+        mddev->changed = 1;
        kobject_uevent(&disk_to_dev(mddev->gendisk)->kobj, KOBJ_CHANGE);
 out:
        return err;
@@ -4712,6 +4716,7 @@ static void md_clean(mddev_t *mddev)
        mddev->sync_speed_min = mddev->sync_speed_max = 0;
        mddev->recovery = 0;
        mddev->in_sync = 0;
+        mddev->changed = 0;
        mddev->degraded = 0;
        mddev->safemode = 0;
        mddev->bitmap_info.offset = 0;
@@ -4827,6 +4832,7 @@ static int do_md_stop(mddev_t * mddev, int mode, int is_open)
                set_capacity(disk, 0);
                mutex_unlock(&mddev->open_mutex);
+                mddev->changed = 1;
                revalidate_disk(disk);
                if (mddev->ro)
@@ -6011,7 +6017,7 @@ static int md_open(struct block_device *bdev, fmode_t mode)
        atomic_inc(&mddev->openers);
        mutex_unlock(&mddev->open_mutex);
-        check_disk_size_change(mddev->gendisk, bdev);
+        check_disk_change(bdev);
 out:
        return err;
 }
@@ -6026,6 +6032,21 @@ static int md_release(struct gendisk *disk, fmode_t mode)
        return 0;
 }
+static int md_media_changed(struct gendisk *disk)
+{
+        mddev_t *mddev = disk->private_data;
+        return mddev->changed;
+}
+static int md_revalidate(struct gendisk *disk)
+{
+        mddev_t *mddev = disk->private_data;
+        mddev->changed = 0;
+        return 0;
+}
 static const struct block_device_operations md_fops =
 {
        .owner          = THIS_MODULE,
@@ -6036,6 +6057,8 @@ static const struct block_device_operations md_fops =
        .compat_ioctl   = md_compat_ioctl,
 #endif
        .getgeo         = md_getgeo,
+        .media_changed  = md_media_changed,
+        .revalidate_disk= md_revalidate,
 };
 static int md_thread(void * arg)
diff --git a/drivers/md/md.h b/drivers/md/md.h
index 7e90b8593b2a..12215d437fcc 100644
--- a/drivers/md/md.h
+++ b/drivers/md/md.h
@@ -274,6 +274,8 @@ struct mddev_s
        atomic_t                        active;         /* general refcount */
        atomic_t                        openers;        /* number of active opens */
+        int                             changed;        /* True if we might need to
+                                                         * reread partition info */
        int                             degraded;       /* whether md should consider
                                                         * adding a spare
                                                         */
diff --git a/drivers/md/multipath.c b/drivers/md/multipath.c
index 6d7ddf32ef2e..3a62d440e27b 100644
--- a/drivers/md/multipath.c
+++ b/drivers/md/multipath.c
@@ -435,7 +435,6 @@ static int multipath_run (mddev_t *mddev)
         * bookkeeping area. [whatever we allocate in multipath_run(),
         * should be freed in multipath_stop()]
         */
-        mddev->queue->queue_lock = &mddev->queue->__queue_lock;
        conf = kzalloc(sizeof(multipath_conf_t), GFP_KERNEL);
        mddev->private = conf;
diff --git a/drivers/md/raid0.c b/drivers/md/raid0.c
index 637a96855edb..c0ac457f1218 100644
--- a/drivers/md/raid0.c
+++ b/drivers/md/raid0.c
@@ -361,7 +361,6 @@ static int raid0_run(mddev_t *mddev)
        if (md_check_no_bitmap(mddev))
                return -EINVAL;
        blk_queue_max_hw_sectors(mddev->queue, mddev->chunk_sectors);
-        mddev->queue->queue_lock = &mddev->queue->__queue_lock;
        /* if private is not null, we are here after takeover */
        if (mddev->private == NULL) {
@@ -670,6 +669,7 @@ static void *raid0_takeover_raid1(mddev_t *mddev)
        mddev->new_layout = 0;
        mddev->new_chunk_sectors = 128; /* by default set chunk size to 64k */
        mddev->delta_disks = 1 - mddev->raid_disks;
+        mddev->raid_disks = 1;
        /* make sure it will be not marked as dirty */
        mddev->recovery_cp = MaxSector;
diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c
index a23ffa397ba9..06cd712807d0 100644
--- a/drivers/md/raid1.c
+++ b/drivers/md/raid1.c
@@ -593,7 +593,10 @@ static int flush_pending_writes(conf_t *conf)
        if (conf->pending_bio_list.head) {
                struct bio *bio;
                bio = bio_list_get(&conf->pending_bio_list);
+                /* Only take the spinlock to quiet a warning */
+                spin_lock(conf->mddev->queue->queue_lock);
                blk_remove_plug(conf->mddev->queue);
+                spin_unlock(conf->mddev->queue->queue_lock);
                spin_unlock_irq(&conf->device_lock);
                /* flush any pending bitmap writes to
                 * disk before proceeding w/ I/O */
@@ -959,7 +962,7 @@ static int make_request(mddev_t *mddev, struct bio * bio)
                atomic_inc(&r1_bio->remaining);
                spin_lock_irqsave(&conf->device_lock, flags);
                bio_list_add(&conf->pending_bio_list, mbio);
-                blk_plug_device(mddev->queue);
+                blk_plug_device_unlocked(mddev->queue);
                spin_unlock_irqrestore(&conf->device_lock, flags);
        }
        r1_bio_write_done(r1_bio, bio->bi_vcnt, behind_pages, behind_pages != NULL);
@@ -2021,7 +2024,6 @@ static int run(mddev_t *mddev)
        if (IS_ERR(conf))
                return PTR_ERR(conf);
-        mddev->queue->queue_lock = &conf->device_lock;
        list_for_each_entry(rdev, &mddev->disks, same_set) {
                disk_stack_limits(mddev->gendisk, rdev->bdev,
                                  rdev->data_offset << 9);
diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
index 3b607b28741b..747d061d8e05 100644
--- a/drivers/md/raid10.c
+++ b/drivers/md/raid10.c
@@ -662,7 +662,10 @@ static int flush_pending_writes(conf_t *conf)
        if (conf->pending_bio_list.head) {
                struct bio *bio;
                bio = bio_list_get(&conf->pending_bio_list);
+                /* Spinlock only taken to quiet a warning */
+                spin_lock(conf->mddev->queue->queue_lock);
                blk_remove_plug(conf->mddev->queue);
+                spin_unlock(conf->mddev->queue->queue_lock);
                spin_unlock_irq(&conf->device_lock);
                /* flush any pending bitmap writes to disk
                 * before proceeding w/ I/O */
@@ -971,7 +974,7 @@ static int make_request(mddev_t *mddev, struct bio * bio)
                atomic_inc(&r10_bio->remaining);
                spin_lock_irqsave(&conf->device_lock, flags);
                bio_list_add(&conf->pending_bio_list, mbio);
-                blk_plug_device(mddev->queue);
+                blk_plug_device_unlocked(mddev->queue);
                spin_unlock_irqrestore(&conf->device_lock, flags);
        }
@@ -2304,8 +2307,6 @@ static int run(mddev_t *mddev)
        if (!conf)
                goto out;
-        mddev->queue->queue_lock = &conf->device_lock;
        mddev->thread = conf->thread;
        conf->thread = NULL;
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index 702812824195..78536fdbd87f 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -5204,7 +5204,6 @@ static int run(mddev_t *mddev)
                mddev->queue->backing_dev_info.congested_data = mddev;
                mddev->queue->backing_dev_info.congested_fn = raid5_congested;
-                mddev->queue->queue_lock = &conf->device_lock;
                mddev->queue->unplug_fn = raid5_unplug_queue;
                chunk_size = mddev->chunk_sectors << 9;
diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c
index 6a1f94042612..c45e6305b26f 100644
--- a/drivers/mfd/asic3.c
+++ b/drivers/mfd/asic3.c
@@ -143,9 +143,9 @@ static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
        unsigned long flags;
        struct asic3 *asic;
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
-        asic = desc->handler_data;
+        asic = get_irq_data(irq);
        for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
                u32 status;
diff --git a/drivers/mfd/davinci_voicecodec.c b/drivers/mfd/davinci_voicecodec.c
index 33c923d215c7..fdd8a1b8bc67 100644
--- a/drivers/mfd/davinci_voicecodec.c
+++ b/drivers/mfd/davinci_voicecodec.c
@@ -118,12 +118,12 @@ static int __init davinci_vc_probe(struct platform_device *pdev)
        /* Voice codec interface client */
        cell = &davinci_vc->cells[DAVINCI_VC_VCIF_CELL];
-        cell->name = "davinci_vcif";
+        cell->name = "davinci-vcif";
        cell->driver_data = davinci_vc;
        /* Voice codec CQ93VC client */
        cell = &davinci_vc->cells[DAVINCI_VC_CQ93VC_CELL];
-        cell->name = "cq93vc";
+        cell->name = "cq93vc-codec";
        cell->driver_data = davinci_vc;
        ret = mfd_add_devices(&pdev->dev, pdev->id, davinci_vc->cells,
diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index 627cf577b16d..e9018d1394ee 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -150,12 +150,12 @@ static inline int __tps6586x_write(struct i2c_client *client,
 static inline int __tps6586x_writes(struct i2c_client *client, int reg,
                                  int len, uint8_t *val)
 {
-        int ret;
+        int ret, i;
-        ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
+        for (i = 0; i < len; i++) {
-        if (ret < 0) {
+                ret = __tps6586x_write(client, reg + i, *(val + i));
-                dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
+                if (ret < 0)
-                return ret;
+                        return ret;
        }
        return 0;
diff --git a/drivers/mfd/ucb1x00-ts.c b/drivers/mfd/ucb1x00-ts.c
index 000cb414a78a..92b85e28a15e 100644
--- a/drivers/mfd/ucb1x00-ts.c
+++ b/drivers/mfd/ucb1x00-ts.c
@@ -385,12 +385,18 @@ static int ucb1x00_ts_add(struct ucb1x00_dev *dev)
        idev->close      = ucb1x00_ts_close;
        __set_bit(EV_ABS, idev->evbit);
-        __set_bit(ABS_X, idev->absbit);
-        __set_bit(ABS_Y, idev->absbit);
-        __set_bit(ABS_PRESSURE, idev->absbit);
        input_set_drvdata(idev, ts);
+        ucb1x00_adc_enable(ts->ucb);
+        ts->x_res = ucb1x00_ts_read_xres(ts);
+        ts->y_res = ucb1x00_ts_read_yres(ts);
+        ucb1x00_adc_disable(ts->ucb);
+        input_set_abs_params(idev, ABS_X, 0, ts->x_res, 0, 0);
+        input_set_abs_params(idev, ABS_Y, 0, ts->y_res, 0, 0);
+        input_set_abs_params(idev, ABS_PRESSURE, 0, 0, 0, 0);
        err = input_register_device(idev);
        if (err)
                goto fail;
diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c
index 41233c7fa581..f4016a075fd6 100644
--- a/drivers/mfd/wm8994-core.c
+++ b/drivers/mfd/wm8994-core.c
@@ -246,6 +246,16 @@ static int wm8994_suspend(struct device *dev)
        struct wm8994 *wm8994 = dev_get_drvdata(dev);
        int ret;
+        /* Don't actually go through with the suspend if the CODEC is
+         * still active (eg, for audio passthrough from CP. */
+        ret = wm8994_reg_read(wm8994, WM8994_POWER_MANAGEMENT_1);
+        if (ret < 0) {
+                dev_err(dev, "Failed to read power status: %d\n", ret);
+        } else if (ret & WM8994_VMID_SEL_MASK) {
+                dev_dbg(dev, "CODEC still active, ignoring suspend\n");
+                return 0;
+        }
        /* GPIO configuration state is saved here since we may be configuring
         * the GPIO alternate functions even if we're not using the gpiolib
         * driver for them.
@@ -261,6 +271,8 @@ static int wm8994_suspend(struct device *dev)
        if (ret < 0)
                dev_err(dev, "Failed to save LDO registers: %d\n", ret);
+        wm8994->suspended = true;
        ret = regulator_bulk_disable(wm8994->num_supplies,
                                     wm8994->supplies);
        if (ret != 0) {
@@ -276,6 +288,10 @@ static int wm8994_resume(struct device *dev)
        struct wm8994 *wm8994 = dev_get_drvdata(dev);
        int ret;
+        /* We may have lied to the PM core about suspending */
+        if (!wm8994->suspended)
+                return 0;
        ret = regulator_bulk_enable(wm8994->num_supplies,
                                    wm8994->supplies);
        if (ret != 0) {
@@ -298,6 +314,8 @@ static int wm8994_resume(struct device *dev)
        if (ret < 0)
                dev_err(dev, "Failed to restore GPIO registers: %d\n", ret);
+        wm8994->suspended = false;
        return 0;
 }
 #endif
diff --git a/drivers/misc/bmp085.c b/drivers/misc/bmp085.c
index 63ee4c1a5315..b6e1c9a6679e 100644
--- a/drivers/misc/bmp085.c
+++ b/drivers/misc/bmp085.c
@@ -449,6 +449,7 @@ static const struct i2c_device_id bmp085_id[] = {
        { "bmp085", 0 },
        { }
 };
+MODULE_DEVICE_TABLE(i2c, bmp085_id);
 static struct i2c_driver bmp085_driver = {
        .driver = {
diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
index 5c4a54d9b6a4..ebc62ad4cc56 100644
--- a/drivers/mmc/core/sdio.c
+++ b/drivers/mmc/core/sdio.c
@@ -792,7 +792,6 @@ int mmc_attach_sdio(struct mmc_host *host)
         */
        mmc_release_host(host);
        err = mmc_add_card(host->card);
-        mmc_claim_host(host);
        if (err)
                goto remove_added;
@@ -805,12 +804,12 @@ int mmc_attach_sdio(struct mmc_host *host)
                        goto remove_added;
        }
+        mmc_claim_host(host);
        return 0;
 remove_added:
        /* Remove without lock if the device has been added. */
-        mmc_release_host(host);
        mmc_sdio_remove(host);
        mmc_claim_host(host);
 remove:
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index c89592239bc7..450afc5df0bd 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -476,7 +476,7 @@ config MTD_NAND_MPC5121_NFC
 config MTD_NAND_MXC
        tristate "MXC NAND support"
-        depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX51
+        depends on IMX_HAVE_PLATFORM_MXC_NAND
        help
          This enables the driver for the NAND flash controller on the
          MXC processors.
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 03823327db25..9928115496e6 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1944,7 +1944,7 @@ config 68360_ENET
 config FEC
        bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)"
        depends on M523x || M527x || M5272 || M528x || M520x || M532x || \
-                MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5 || SOC_IMX28
+                IMX_HAVE_PLATFORM_FEC || SOC_IMX28
        select PHYLIB
        help
          Say Y here if you want to use the built-in 10/100 Fast ethernet
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 653c62475cb6..7897d114b290 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -22,7 +22,7 @@
 * (you will need to reboot afterwards) */
 /* #define BNX2X_STOP_ON_ERROR */
-#define DRV_MODULE_VERSION      "1.62.00-5"
+#define DRV_MODULE_VERSION      "1.62.00-6"
 #define DRV_MODULE_RELDATE      "2011/01/30"
 #define BNX2X_BC_VER            0x040200
@@ -1613,19 +1613,23 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
 #define BNX2X_BTR                       4
 #define MAX_SPQ_PENDING                 8
+/* CMNG constants, as derived from system spec calculations */
-/* CMNG constants
+/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
-   derived from lab experiments, and not from system spec calculations !!! */
+#define DEF_MIN_RATE                                    100
-#define DEF_MIN_RATE                    100
 /* resolution of the rate shaping timer - 100 usec */
-#define RS_PERIODIC_TIMEOUT_USEC        100
+#define RS_PERIODIC_TIMEOUT_USEC                        100
-/* resolution of fairness algorithm in usecs -
-   coefficient for calculating the actual t fair */
-#define T_FAIR_COEF                     10000000
 /* number of bytes in single QM arbitration cycle -
-   coefficient for calculating the fairness timer */
+ * coefficient for calculating the fairness timer */
-#define QM_ARB_BYTES                    40000
+#define QM_ARB_BYTES                                    160000
-#define FAIR_MEM                        2
+/* resolution of Min algorithm 1:100 */
+#define MIN_RES                                         100
+/* how many bytes above threshold for the minimal credit of Min algorithm*/
+#define MIN_ABOVE_THRESH                                32768
+/* Fairness algorithm integration time coefficient -
+ * for calculating the actual Tfair */
+#define T_FAIR_COEF     ((MIN_ABOVE_THRESH +  QM_ARB_BYTES) * 8 * MIN_RES)
+/* Memory of fairness algorithm . 2 cycles */
+#define FAIR_MEM                                        2
 #define ATTN_NIG_FOR_FUNC               (1L << 8)
diff --git a/drivers/net/bnx2x/bnx2x_cmn.c b/drivers/net/bnx2x/bnx2x_cmn.c
index 710ce5d04c53..93798129061b 100644
--- a/drivers/net/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/bnx2x/bnx2x_cmn.c
@@ -259,10 +259,44 @@ static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
 #endif
 }
+/* Timestamp option length allowed for TPA aggregation:
+ *
+ *              nop nop kind length echo val
+ */
+#define TPA_TSTAMP_OPT_LEN      12
+/**
+ * Calculate the approximate value of the MSS for this
+ * aggregation using the first packet of it.
+ *
+ * @param bp
+ * @param parsing_flags Parsing flags from the START CQE
+ * @param len_on_bd Total length of the first packet for the
+ *                   aggregation.
+ */
+static inline u16 bnx2x_set_lro_mss(struct bnx2x *bp, u16 parsing_flags,
+                                    u16 len_on_bd)
+{
+        /* TPA arrgregation won't have an IP options and TCP options
+         * other than timestamp.
+         */
+        u16 hdrs_len = ETH_HLEN + sizeof(struct iphdr) + sizeof(struct tcphdr);
+        /* Check if there was a TCP timestamp, if there is it's will
+         * always be 12 bytes length: nop nop kind length echo val.
+         *
+         * Otherwise FW would close the aggregation.
+         */
+        if (parsing_flags & PARSING_FLAGS_TIME_STAMP_EXIST_FLAG)
+                hdrs_len += TPA_TSTAMP_OPT_LEN;
+        return len_on_bd - hdrs_len;
+}
 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
                               struct sk_buff *skb,
                               struct eth_fast_path_rx_cqe *fp_cqe,
-                               u16 cqe_idx)
+                               u16 cqe_idx, u16 parsing_flags)
 {
        struct sw_rx_page *rx_pg, old_rx_pg;
        u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
@@ -275,8 +309,8 @@ static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
        /* This is needed in order to enable forwarding support */
        if (frag_size)
-                skb_shinfo(skb)->gso_size = min((u32)SGE_PAGE_SIZE,
+                skb_shinfo(skb)->gso_size = bnx2x_set_lro_mss(bp, parsing_flags,
-                                               max(frag_size, (u32)len_on_bd));
+                                                              len_on_bd);
 #ifdef BNX2X_STOP_ON_ERROR
        if (pages > min_t(u32, 8, MAX_SKB_FRAGS)*SGE_PAGE_SIZE*PAGES_PER_SGE) {
@@ -344,6 +378,8 @@ static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
        if (likely(new_skb)) {
                /* fix ip xsum and give it to the stack */
                /* (no need to map the new skb) */
+                u16 parsing_flags =
+                        le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags);
                prefetch(skb);
                prefetch(((char *)(skb)) + L1_CACHE_BYTES);
@@ -373,9 +409,9 @@ static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
                }
                if (!bnx2x_fill_frag_skb(bp, fp, skb,
-                                         &cqe->fast_path_cqe, cqe_idx)) {
+                                         &cqe->fast_path_cqe, cqe_idx,
-                        if ((le16_to_cpu(cqe->fast_path_cqe.
+                                         parsing_flags)) {
-                            pars_flags.flags) & PARSING_FLAGS_VLAN))
+                        if (parsing_flags & PARSING_FLAGS_VLAN)
                                __vlan_hwaccel_put_tag(skb,
                                                 le16_to_cpu(cqe->fast_path_cqe.
                                                             vlan_tag));
@@ -703,19 +739,20 @@ u16 bnx2x_get_mf_speed(struct bnx2x *bp)
 {
        u16 line_speed = bp->link_vars.line_speed;
        if (IS_MF(bp)) {
-                u16 maxCfg = (bp->mf_config[BP_VN(bp)] &
+                u16 maxCfg = bnx2x_extract_max_cfg(bp,
-                                                FUNC_MF_CFG_MAX_BW_MASK) >>
+                                                   bp->mf_config[BP_VN(bp)]);
-                                                FUNC_MF_CFG_MAX_BW_SHIFT;
-                /* Calculate the current MAX line speed limit for the DCC
+                /* Calculate the current MAX line speed limit for the MF
-                 * capable devices
+                 * devices
                 */
-                if (IS_MF_SD(bp)) {
+                if (IS_MF_SI(bp))
+                        line_speed = (line_speed * maxCfg) / 100;
+                else { /* SD mode */
                        u16 vn_max_rate = maxCfg * 100;
                        if (vn_max_rate < line_speed)
                                line_speed = vn_max_rate;
-                } else /* IS_MF_SI(bp)) */
+                }
-                        line_speed = (line_speed * maxCfg) / 100;
        }
        return line_speed;
diff --git a/drivers/net/bnx2x/bnx2x_cmn.h b/drivers/net/bnx2x/bnx2x_cmn.h
index 03eb4d68e6bb..326ba44b3ded 100644
--- a/drivers/net/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/bnx2x/bnx2x_cmn.h
@@ -1044,4 +1044,24 @@ static inline void storm_memset_cmng(struct bnx2x *bp,
 void bnx2x_acquire_phy_lock(struct bnx2x *bp);
 void bnx2x_release_phy_lock(struct bnx2x *bp);
+/**
+ * Extracts MAX BW part from MF configuration.
+ *
+ * @param bp
+ * @param mf_cfg
+ *
+ * @return u16
+ */
+static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
+{
+        u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
+                              FUNC_MF_CFG_MAX_BW_SHIFT;
+        if (!max_cfg) {
+                BNX2X_ERR("Illegal configuration detected for Max BW - "
+                          "using 100 instead\n");
+                max_cfg = 100;
+        }
+        return max_cfg;
+}
 #endif /* BNX2X_CMN_H */
diff --git a/drivers/net/bnx2x/bnx2x_ethtool.c b/drivers/net/bnx2x/bnx2x_ethtool.c
index 5b44a8b48509..ef2919987a10 100644
--- a/drivers/net/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/bnx2x/bnx2x_ethtool.c
@@ -238,7 +238,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
        speed |= (cmd->speed_hi << 16);
        if (IS_MF_SI(bp)) {
-                u32 param = 0;
+                u32 param = 0, part;
                u32 line_speed = bp->link_vars.line_speed;
                /* use 10G if no link detected */
@@ -251,9 +251,11 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
                                       REQ_BC_VER_4_SET_MF_BW);
                        return -EINVAL;
                }
-                if (line_speed < speed) {
+                part = (speed * 100) / line_speed;
-                        BNX2X_DEV_INFO("New speed should be less or equal "
+                if (line_speed < speed || !part) {
-                                       "to actual line speed\n");
+                        BNX2X_DEV_INFO("Speed setting should be in a range "
+                                       "from 1%% to 100%% "
+                                       "of actual line speed\n");
                        return -EINVAL;
                }
                /* load old values */
@@ -263,8 +265,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
                param &= FUNC_MF_CFG_MIN_BW_MASK;
                /* set new MAX value */
-                param |= (((speed * 100) / line_speed)
+                param |= (part << FUNC_MF_CFG_MAX_BW_SHIFT)
-                                 << FUNC_MF_CFG_MAX_BW_SHIFT)
                                  & FUNC_MF_CFG_MAX_BW_MASK;
                bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, param);
@@ -1781,9 +1782,7 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
                { 0x100, 0x350 }, /* manuf_info */
                { 0x450,  0xf0 }, /* feature_info */
                { 0x640,  0x64 }, /* upgrade_key_info */
-                { 0x6a4,  0x64 },
                { 0x708,  0x70 }, /* manuf_key_info */
-                { 0x778,  0x70 },
                {     0,     0 }
        };
        __be32 buf[0x350 / 4];
@@ -1933,11 +1932,11 @@ static void bnx2x_self_test(struct net_device *dev,
                buf[4] = 1;
                etest->flags |= ETH_TEST_FL_FAILED;
        }
-        if (bp->port.pmf)
-                if (bnx2x_link_test(bp, is_serdes) != 0) {
+        if (bnx2x_link_test(bp, is_serdes) != 0) {
-                        buf[5] = 1;
+                buf[5] = 1;
-                        etest->flags |= ETH_TEST_FL_FAILED;
+                etest->flags |= ETH_TEST_FL_FAILED;
-                }
+        }
 #ifdef BNX2X_EXTRA_DEBUG
        bnx2x_panic_dump(bp);
diff --git a/drivers/net/bnx2x/bnx2x_init.h b/drivers/net/bnx2x/bnx2x_init.h
index 5a268e9a0895..fa6dbe3f2058 100644
--- a/drivers/net/bnx2x/bnx2x_init.h
+++ b/drivers/net/bnx2x/bnx2x_init.h
@@ -241,7 +241,7 @@ static const struct {
        /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
         * want to handle "system kill" flow at the moment.
         */
-        BLOCK_PRTY_INFO(PXP, 0x3ffffff, 0x3ffffff, 0x3ffffff, 0x3ffffff),
+        BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff),
        BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff),
        BLOCK_PRTY_INFO_1(PXP2, 0x7ff, 0x7f, 0x7f, 0x7ff),
        BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0),
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index d584d32c747d..032ae184b605 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -1974,13 +1974,22 @@ static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
                vn_max_rate = 0;
        } else {
+                u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
                vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
                                FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
-                /* If min rate is zero - set it to 1 */
+                /* If fairness is enabled (not all min rates are zeroes) and
+                   if current min rate is zero - set it to 1.
+                   This is a requirement of the algorithm. */
                if (bp->vn_weight_sum && (vn_min_rate == 0))
                        vn_min_rate = DEF_MIN_RATE;
-                vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
-                                FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
+                if (IS_MF_SI(bp))
+                        /* maxCfg in percents of linkspeed */
+                        vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
+                else
+                        /* maxCfg is absolute in 100Mb units */
+                        vn_max_rate = maxCfg * 100;
        }
        DP(NETIF_MSG_IFUP,
@@ -2006,7 +2015,8 @@ static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
                m_fair_vn.vn_credit_delta =
                        max_t(u32, (vn_min_rate * (T_FAIR_COEF /
                                                   (8 * bp->vn_weight_sum))),
-                              (bp->cmng.fair_vars.fair_threshold * 2));
+                              (bp->cmng.fair_vars.fair_threshold +
+                                                        MIN_ABOVE_THRESH));
                DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
                   m_fair_vn.vn_credit_delta);
        }
diff --git a/drivers/net/bnx2x/bnx2x_stats.c b/drivers/net/bnx2x/bnx2x_stats.c
index bda60d590fa8..3445ded6674f 100644
--- a/drivers/net/bnx2x/bnx2x_stats.c
+++ b/drivers/net/bnx2x/bnx2x_stats.c
@@ -1239,14 +1239,14 @@ void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
        if (unlikely(bp->panic))
                return;
+        bnx2x_stats_stm[bp->stats_state][event].action(bp);
        /* Protect a state change flow */
        spin_lock_bh(&bp->stats_lock);
        state = bp->stats_state;
        bp->stats_state = bnx2x_stats_stm[state][event].next_state;
        spin_unlock_bh(&bp->stats_lock);
-        bnx2x_stats_stm[state][event].action(bp);
        if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
                DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
                   state, event, bp->stats_state);
diff --git a/drivers/net/can/softing/softing_main.c b/drivers/net/can/softing/softing_main.c
index 5157e15e96eb..aeea9f9ff6e8 100644
--- a/drivers/net/can/softing/softing_main.c
+++ b/drivers/net/can/softing/softing_main.c
@@ -633,6 +633,7 @@ static const struct net_device_ops softing_netdev_ops = {
 };
 static const struct can_bittiming_const softing_btr_const = {
+        .name = "softing",
        .tseg1_min = 1,
        .tseg1_max = 16,
        .tseg2_min = 1,
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 7ff170cbc7dc..302be4aa69d6 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -2760,6 +2760,8 @@ static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
        u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
        int kcqe_cnt;
+        /* status block index must be read before reading other fields */
+        rmb();
        cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
        while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
@@ -2770,6 +2772,8 @@ static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
                barrier();
                if (status_idx != *cp->kcq1.status_idx_ptr) {
                        status_idx = (u16) *cp->kcq1.status_idx_ptr;
+                        /* status block index must be read first */
+                        rmb();
                        cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
                } else
                        break;
@@ -2888,6 +2892,8 @@ static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
        u32 last_status = *info->status_idx_ptr;
        int kcqe_cnt;
+        /* status block index must be read before reading the KCQ */
+        rmb();
        while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
                service_kcqes(dev, kcqe_cnt);
@@ -2898,6 +2904,8 @@ static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
                        break;
                last_status = *info->status_idx_ptr;
+                /* status block index must be read before reading the KCQ */
+                rmb();
        }
        return last_status;
 }
@@ -2906,26 +2914,35 @@ static void cnic_service_bnx2x_bh(unsigned long data)
 {
        struct cnic_dev *dev = (struct cnic_dev *) data;
        struct cnic_local *cp = dev->cnic_priv;
-        u32 status_idx;
+        u32 status_idx, new_status_idx;
        if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
                return;
-        status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
+        while (1) {
+                status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
-        CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
+                CNIC_WR16(dev, cp->kcq1.io_addr,
+                          cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
-        if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+                if (!BNX2X_CHIP_IS_E2(cp->chip_id)) {
-                status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
+                        cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
+                                           status_idx, IGU_INT_ENABLE, 1);
+                        break;
+                }
+                new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
+                if (new_status_idx != status_idx)
+                        continue;
                CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
                          MAX_KCQ_IDX);
                cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
                                status_idx, IGU_INT_ENABLE, 1);
-        } else {
-                cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
+                break;
-                                   status_idx, IGU_INT_ENABLE, 1);
        }
 }
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 2a628d17d178..7018bfe408a4 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -1008,7 +1008,7 @@ static void emac_rx_handler(void *token, int len, int status)
        int                     ret;
        /* free and bail if we are shutting down */
-        if (unlikely(!netif_running(ndev))) {
+        if (unlikely(!netif_running(ndev) || !netif_carrier_ok(ndev))) {
                dev_kfree_skb_any(skb);
                return;
        }
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 2d4c4fc1d900..461dd6f905f7 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c
@@ -802,10 +802,7 @@ dm9000_init_dm9000(struct net_device *dev)
        /* Checksum mode */
        dm9000_set_rx_csum_unlocked(dev, db->rx_csum);
-        /* GPIO0 on pre-activate PHY */
-        iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
        iow(db, DM9000_GPCR, GPCR_GEP_CNTL);    /* Let GPIO0 output */
-        iow(db, DM9000_GPR, 0); /* Enable PHY */
        ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;
@@ -852,8 +849,8 @@ static void dm9000_timeout(struct net_device *dev)
        unsigned long flags;
        /* Save previous register address */
-        reg_save = readb(db->io_addr);
        spin_lock_irqsave(&db->lock, flags);
+        reg_save = readb(db->io_addr);
        netif_stop_queue(dev);
        dm9000_reset(db);
@@ -1194,6 +1191,10 @@ dm9000_open(struct net_device *dev)
        if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev))
                return -EAGAIN;
+        /* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */
+        iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
+        mdelay(1); /* delay needs by DM9000B */
        /* Initialize DM9000 board */
        dm9000_reset(db);
        dm9000_init_dm9000(dev);
diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c
index 9d8a20b72fa9..8318ea06cb6d 100644
--- a/drivers/net/dnet.c
+++ b/drivers/net/dnet.c
@@ -337,8 +337,6 @@ static int dnet_mii_init(struct dnet *bp)
        for (i = 0; i < PHY_MAX_ADDR; i++)
                bp->mii_bus->irq[i] = PHY_POLL;
-        platform_set_drvdata(bp->dev, bp->mii_bus);
        if (mdiobus_register(bp->mii_bus)) {
                err = -ENXIO;
                goto err_out_free_mdio_irq;
@@ -863,6 +861,7 @@ static int __devinit dnet_probe(struct platform_device *pdev)
        bp = netdev_priv(dev);
        bp->dev = dev;
+        platform_set_drvdata(pdev, dev);
        SET_NETDEV_DEV(dev, &pdev->dev);
        spin_lock_init(&bp->lock);
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
index 55c1711f1688..33e7c45a4fe4 100644
--- a/drivers/net/e1000/e1000_osdep.h
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -42,7 +42,8 @@
 #define GBE_CONFIG_RAM_BASE \
        ((unsigned int)(CONFIG_RAM_BASE + GBE_CONFIG_OFFSET))
-#define GBE_CONFIG_BASE_VIRT    phys_to_virt(GBE_CONFIG_RAM_BASE)
+#define GBE_CONFIG_BASE_VIRT \
+        ((void __iomem *)phys_to_virt(GBE_CONFIG_RAM_BASE))
 #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \
        (iowrite16_rep(base + offset, data, count))
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index 3fa110ddb041..2e5022849f18 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -5967,7 +5967,8 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
                /* APME bit in EEPROM is mapped to WUC.APME */
                eeprom_data = er32(WUC);
                eeprom_apme_mask = E1000_WUC_APME;
-                if (eeprom_data & E1000_WUC_PHY_WAKE)
+                if ((hw->mac.type > e1000_ich10lan) &&
+                    (eeprom_data & E1000_WUC_PHY_WAKE))
                        adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
        } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
                if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 2a71373719ae..cd0282d5d40f 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -74,7 +74,8 @@ static struct platform_device_id fec_devtype[] = {
        }, {
                .name = "imx28-fec",
                .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
-        }
+        },
+        { }
 };
 static unsigned char macaddr[ETH_ALEN];
diff --git a/drivers/net/igbvf/vf.c b/drivers/net/igbvf/vf.c
index 74486a8b009a..af3822f9ea9a 100644
--- a/drivers/net/igbvf/vf.c
+++ b/drivers/net/igbvf/vf.c
@@ -220,7 +220,7 @@ static u32 e1000_hash_mc_addr_vf(struct e1000_hw *hw, u8 *mc_addr)
 *  The parameter rar_count will usually be hw->mac.rar_entry_count
 *  unless there are workarounds that change this.
 **/
-void e1000_update_mc_addr_list_vf(struct e1000_hw *hw,
+static void e1000_update_mc_addr_list_vf(struct e1000_hw *hw,
                                  u8 *mc_addr_list, u32 mc_addr_count,
                                  u32 rar_used_count, u32 rar_count)
 {
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index f69e73e2191e..79ccb54ab00c 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -260,7 +260,7 @@ static int macb_mii_init(struct macb *bp)
        for (i = 0; i < PHY_MAX_ADDR; i++)
                bp->mii_bus->irq[i] = PHY_POLL;
-        platform_set_drvdata(bp->dev, bp->mii_bus);
+        dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
        if (mdiobus_register(bp->mii_bus))
                goto err_out_free_mdio_irq;
diff --git a/drivers/net/pcmcia/fmvj18x_cs.c b/drivers/net/pcmcia/fmvj18x_cs.c
index 9226cda4d054..530ab5a10bd3 100644
--- a/drivers/net/pcmcia/fmvj18x_cs.c
+++ b/drivers/net/pcmcia/fmvj18x_cs.c
@@ -691,6 +691,7 @@ static struct pcmcia_device_id fmvj18x_ids[] = {
        PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0105, 0x0e0a),
        PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0032, 0x0e01),
        PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0032, 0x0a05),
+        PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0032, 0x0b05),
        PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0032, 0x1101),
        PCMCIA_DEVICE_NULL,
 };
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 469ab0b7ce31..7ffdb80adf40 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -25,6 +25,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/pm_runtime.h>
 #include <linux/firmware.h>
+#include <linux/pci-aspm.h>
 #include <asm/system.h>
 #include <asm/io.h>
@@ -617,8 +618,9 @@ static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
        }
 }
-static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
+static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 {
+        void __iomem *ioaddr = tp->mmio_addr;
        int i;
        RTL_W8(ERIDR, cmd);
@@ -630,7 +632,7 @@ static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
                        break;
        }
-        ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
+        ocp_write(tp, 0x1, 0x30, 0x00000001);
 }
 #define OOB_CMD_RESET           0x00
@@ -2868,8 +2870,11 @@ static void r8168_pll_power_down(struct rtl8169_private *tp)
 {
        void __iomem *ioaddr = tp->mmio_addr;
-        if (tp->mac_version == RTL_GIGA_MAC_VER_27)
+        if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
+             (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
+            (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
                return;
+        }
        if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
             (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
@@ -2891,6 +2896,8 @@ static void r8168_pll_power_down(struct rtl8169_private *tp)
        switch (tp->mac_version) {
        case RTL_GIGA_MAC_VER_25:
        case RTL_GIGA_MAC_VER_26:
+        case RTL_GIGA_MAC_VER_27:
+        case RTL_GIGA_MAC_VER_28:
                RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
                break;
        }
@@ -2900,12 +2907,17 @@ static void r8168_pll_power_up(struct rtl8169_private *tp)
 {
        void __iomem *ioaddr = tp->mmio_addr;
-        if (tp->mac_version == RTL_GIGA_MAC_VER_27)
+        if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
+             (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
+            (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
                return;
+        }
        switch (tp->mac_version) {
        case RTL_GIGA_MAC_VER_25:
        case RTL_GIGA_MAC_VER_26:
+        case RTL_GIGA_MAC_VER_27:
+        case RTL_GIGA_MAC_VER_28:
                RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
                break;
        }
@@ -3009,6 +3021,11 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
        mii->reg_num_mask = 0x1f;
        mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
+        /* disable ASPM completely as that cause random device stop working
+         * problems as well as full system hangs for some PCIe devices users */
+        pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
+                                     PCIE_LINK_STATE_CLKPM);
        /* enable device (incl. PCI PM wakeup and hotplug setup) */
        rc = pci_enable_device(pdev);
        if (rc < 0) {
@@ -3042,7 +3059,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
                goto err_out_mwi_2;
        }
-        tp->cp_cmd = PCIMulRW | RxChkSum;
+        tp->cp_cmd = RxChkSum;
        if ((sizeof(dma_addr_t) > 4) &&
            !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
@@ -3318,7 +3335,8 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
        /* Disable interrupts */
        rtl8169_irq_mask_and_ack(ioaddr);
-        if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
+        if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
+            tp->mac_version == RTL_GIGA_MAC_VER_28) {
                while (RTL_R8(TxPoll) & NPQ)
                        udelay(20);
@@ -3847,8 +3865,7 @@ static void rtl_hw_start_8168(struct net_device *dev)
        Cxpl_dbg_sel | \
        ASF | \
        PktCntrDisable | \
-        PCIDAC | \
+        Mac_dbgo_sel)
-        PCIMulRW)
 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
 {
@@ -3878,8 +3895,6 @@ static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
        if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
                RTL_W8(Config1, cfg1 & ~LEDS0);
-        RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
        rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
 }
@@ -3891,8 +3906,6 @@ static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
        RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
        RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
-        RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
 }
 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
@@ -3918,6 +3931,8 @@ static void rtl_hw_start_8101(struct net_device *dev)
                }
        }
+        RTL_W8(Cfg9346, Cfg9346_Unlock);
        switch (tp->mac_version) {
        case RTL_GIGA_MAC_VER_07:
                rtl_hw_start_8102e_1(ioaddr, pdev);
@@ -3932,14 +3947,13 @@ static void rtl_hw_start_8101(struct net_device *dev)
                break;
        }
-        RTL_W8(Cfg9346, Cfg9346_Unlock);
+        RTL_W8(Cfg9346, Cfg9346_Lock);
        RTL_W8(MaxTxPacketSize, TxPacketMax);
        rtl_set_rx_max_size(ioaddr, rx_buf_sz);
-        tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
+        tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
        RTL_W16(CPlusCmd, tp->cp_cmd);
        RTL_W16(IntrMitigate, 0x0000);
@@ -3949,14 +3963,10 @@ static void rtl_hw_start_8101(struct net_device *dev)
        RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
        rtl_set_rx_tx_config_registers(tp);
-        RTL_W8(Cfg9346, Cfg9346_Lock);
        RTL_R8(IntrMask);
        rtl_set_rx_mode(dev);
-        RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
        RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
        RTL_W16(IntrMask, tp->intr_event);
diff --git a/drivers/net/sfc/ethtool.c b/drivers/net/sfc/ethtool.c
index 0e8bb19ed60d..ca886d98bdc7 100644
--- a/drivers/net/sfc/ethtool.c
+++ b/drivers/net/sfc/ethtool.c
@@ -569,9 +569,14 @@ static void efx_ethtool_self_test(struct net_device *net_dev,
                                  struct ethtool_test *test, u64 *data)
 {
        struct efx_nic *efx = netdev_priv(net_dev);
-        struct efx_self_tests efx_tests;
+        struct efx_self_tests *efx_tests;
        int already_up;
-        int rc;
+        int rc = -ENOMEM;
+        efx_tests = kzalloc(sizeof(*efx_tests), GFP_KERNEL);
+        if (!efx_tests)
+                goto fail;
        ASSERT_RTNL();
        if (efx->state != STATE_RUNNING) {
@@ -589,13 +594,11 @@ static void efx_ethtool_self_test(struct net_device *net_dev,
                if (rc) {
                        netif_err(efx, drv, efx->net_dev,
                                  "failed opening device.\n");
-                        goto fail2;
+                        goto fail1;
                }
        }
-        memset(&efx_tests, 0, sizeof(efx_tests));
+        rc = efx_selftest(efx, efx_tests, test->flags);
-        rc = efx_selftest(efx, &efx_tests, test->flags);
        if (!already_up)
                dev_close(efx->net_dev);
@@ -604,10 +607,11 @@ static void efx_ethtool_self_test(struct net_device *net_dev,
                   rc == 0 ? "passed" : "failed",
                   (test->flags & ETH_TEST_FL_OFFLINE) ? "off" : "on");
- fail2:
+fail1:
- fail1:
        /* Fill ethtool results structures */
-        efx_ethtool_fill_self_tests(efx, &efx_tests, NULL, data);
+        efx_ethtool_fill_self_tests(efx, efx_tests, NULL, data);
+        kfree(efx_tests);
+fail:
        if (rc)
                test->flags |= ETH_TEST_FL_FAILED;
 }
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 42daf98ba736..35b28f42d208 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -3856,9 +3856,6 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
        memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
        memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
-        /* device is off until link detection */
-        netif_carrier_off(dev);
        return dev;
 }
diff --git a/drivers/net/usb/dm9601.c b/drivers/net/usb/dm9601.c
index 02b622e3b9fb..5002f5be47be 100644
--- a/drivers/net/usb/dm9601.c
+++ b/drivers/net/usb/dm9601.c
@@ -651,6 +651,10 @@ static const struct usb_device_id products[] = {
        .driver_info = (unsigned long)&dm9601_info,
         },
        {
+         USB_DEVICE(0x0fe6, 0x9700),    /* DM9601 USB to Fast Ethernet Adapter */
+         .driver_info = (unsigned long)&dm9601_info,
+         },
+        {
         USB_DEVICE(0x0a46, 0x9000),    /* DM9000E */
         .driver_info = (unsigned long)&dm9601_info,
         },
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index 78c26fdccad1..62ce2f4e8605 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -282,6 +282,34 @@ int ath5k_hw_phy_disable(struct ath5k_hw *ah)
        return 0;
 }
+/*
+ * Wait for synth to settle
+ */
+static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
+                        struct ieee80211_channel *channel)
+{
+        /*
+         * On 5211+ read activation -> rx delay
+         * and use it (100ns steps).
+         */
+        if (ah->ah_version != AR5K_AR5210) {
+                u32 delay;
+                delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
+                        AR5K_PHY_RX_DELAY_M;
+                delay = (channel->hw_value & CHANNEL_CCK) ?
+                        ((delay << 2) / 22) : (delay / 10);
+                if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
+                        delay = delay << 1;
+                if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
+                        delay = delay << 2;
+                /* XXX: /2 on turbo ? Let's be safe
+                 * for now */
+                udelay(100 + delay);
+        } else {
+                mdelay(1);
+        }
+}
 /**********************\
 * RF Gain optimization *
@@ -1253,6 +1281,7 @@ static int ath5k_hw_channel(struct ath5k_hw *ah,
        case AR5K_RF5111:
                ret = ath5k_hw_rf5111_channel(ah, channel);
                break;
+        case AR5K_RF2317:
        case AR5K_RF2425:
                ret = ath5k_hw_rf2425_channel(ah, channel);
                break;
@@ -3237,6 +3266,13 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                /* Failed */
                if (i >= 100)
                        return -EIO;
+                /* Set channel and wait for synth */
+                ret = ath5k_hw_channel(ah, channel);
+                if (ret)
+                        return ret;
+                ath5k_hw_wait_for_synth(ah, channel);
        }
        /*
@@ -3251,13 +3287,53 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
        if (ret)
                return ret;
+        /* Write OFDM timings on 5212*/
+        if (ah->ah_version == AR5K_AR5212 &&
+                channel->hw_value & CHANNEL_OFDM) {
+                ret = ath5k_hw_write_ofdm_timings(ah, channel);
+                if (ret)
+                        return ret;
+                /* Spur info is available only from EEPROM versions
+                 * greater than 5.3, but the EEPROM routines will use
+                 * static values for older versions */
+                if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
+                        ath5k_hw_set_spur_mitigation_filter(ah,
+                                                            channel);
+        }
+        /* If we used fast channel switching
+         * we are done, release RF bus and
+         * fire up NF calibration.
+         *
+         * Note: Only NF calibration due to
+         * channel change, not AGC calibration
+         * since AGC is still running !
+         */
+        if (fast) {
+                /*
+                 * Release RF Bus grant
+                 */
+                AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
+                                    AR5K_PHY_RFBUS_REQ_REQUEST);
+                /*
+                 * Start NF calibration
+                 */
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
+                                        AR5K_PHY_AGCCTL_NF);
+                return ret;
+        }
        /*
         * For 5210 we do all initialization using
         * initvals, so we don't have to modify
         * any settings (5210 also only supports
         * a/aturbo modes)
         */
-        if ((ah->ah_version != AR5K_AR5210) && !fast) {
+        if (ah->ah_version != AR5K_AR5210) {
                /*
                 * Write initial RF gain settings
@@ -3276,22 +3352,6 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                if (ret)
                        return ret;
-                /* Write OFDM timings on 5212*/
-                if (ah->ah_version == AR5K_AR5212 &&
-                        channel->hw_value & CHANNEL_OFDM) {
-                        ret = ath5k_hw_write_ofdm_timings(ah, channel);
-                        if (ret)
-                                return ret;
-                        /* Spur info is available only from EEPROM versions
-                         * greater than 5.3, but the EEPROM routines will use
-                         * static values for older versions */
-                        if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
-                                ath5k_hw_set_spur_mitigation_filter(ah,
-                                                                    channel);
-                }
                /*Enable/disable 802.11b mode on 5111
                (enable 2111 frequency converter + CCK)*/
                if (ah->ah_radio == AR5K_RF5111) {
@@ -3322,47 +3382,20 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
         */
        ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
+        ath5k_hw_wait_for_synth(ah, channel);
        /*
-         * On 5211+ read activation -> rx delay
+         * Perform ADC test to see if baseband is ready
-         * and use it.
+         * Set tx hold and check adc test register
         */
-        if (ah->ah_version != AR5K_AR5210) {
+        phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
-                u32 delay;
+        ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
-                delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
+        for (i = 0; i <= 20; i++) {
-                        AR5K_PHY_RX_DELAY_M;
+                if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
-                delay = (channel->hw_value & CHANNEL_CCK) ?
+                        break;
-                        ((delay << 2) / 22) : (delay / 10);
+                udelay(200);
-                if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
-                        delay = delay << 1;
-                if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
-                        delay = delay << 2;
-                /* XXX: /2 on turbo ? Let's be safe
-                 * for now */
-                udelay(100 + delay);
-        } else {
-                mdelay(1);
-        }
-        if (fast)
-                /*
-                 * Release RF Bus grant
-                 */
-                AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
-                                    AR5K_PHY_RFBUS_REQ_REQUEST);
-        else {
-                /*
-                 * Perform ADC test to see if baseband is ready
-                 * Set tx hold and check adc test register
-                 */
-                phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
-                ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
-                for (i = 0; i <= 20; i++) {
-                        if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
-                                break;
-                        udelay(200);
-                }
-                ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
        }
+        ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
        /*
         * Start automatic gain control calibration
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 23838e37d45f..1a7fa6ea4cf5 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -21,7 +21,6 @@
 #include <linux/device.h>
 #include <linux/leds.h>
 #include <linux/completion.h>
-#include <linux/pm_qos_params.h>
 #include "debug.h"
 #include "common.h"
@@ -57,8 +56,6 @@ struct ath_node;
 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
-#define ATH9K_PM_QOS_DEFAULT_VALUE      55
 #define TSF_TO_TU(_h,_l) \
        ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
@@ -633,8 +630,6 @@ struct ath_softc {
        struct ath_descdma txsdma;
        struct ath_ant_comb ant_comb;
-        struct pm_qos_request_list pm_qos_req;
 };
 struct ath_wiphy {
@@ -666,7 +661,6 @@ static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 extern struct ieee80211_ops ath9k_ops;
 extern int ath9k_modparam_nohwcrypt;
 extern int led_blink;
-extern int ath9k_pm_qos_value;
 extern bool is_ath9k_unloaded;
 irqreturn_t ath_isr(int irq, void *dev);
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
index 5ab3084eb9cb..07b1633b7f3f 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -219,8 +219,9 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
        struct tx_buf *tx_buf = NULL;
        struct sk_buff *nskb = NULL;
        int ret = 0, i;
-        u16 *hdr, tx_skb_cnt = 0;
+        u16 tx_skb_cnt = 0;
        u8 *buf;
+        __le16 *hdr;
        if (hif_dev->tx.tx_skb_cnt == 0)
                return 0;
@@ -245,9 +246,9 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
                buf = tx_buf->buf;
                buf += tx_buf->offset;
-                hdr = (u16 *)buf;
+                hdr = (__le16 *)buf;
-                *hdr++ = nskb->len;
+                *hdr++ = cpu_to_le16(nskb->len);
-                *hdr++ = ATH_USB_TX_STREAM_MODE_TAG;
+                *hdr++ = cpu_to_le16(ATH_USB_TX_STREAM_MODE_TAG);
                buf += 4;
                memcpy(buf, nskb->data, nskb->len);
                tx_buf->len = nskb->len + 4;
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 087a6a95edd5..a033d01bf8a0 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -41,10 +41,6 @@ static int ath9k_btcoex_enable;
 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
-int ath9k_pm_qos_value = ATH9K_PM_QOS_DEFAULT_VALUE;
-module_param_named(pmqos, ath9k_pm_qos_value, int, S_IRUSR | S_IRGRP | S_IROTH);
-MODULE_PARM_DESC(pmqos, "User specified PM-QOS value");
 bool is_ath9k_unloaded;
 /* We use the hw_value as an index into our private channel structure */
@@ -762,9 +758,6 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
        ath_init_leds(sc);
        ath_start_rfkill_poll(sc);
-        pm_qos_add_request(&sc->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
-                           PM_QOS_DEFAULT_VALUE);
        return 0;
 error_world:
@@ -831,7 +824,6 @@ void ath9k_deinit_device(struct ath_softc *sc)
        }
        ieee80211_unregister_hw(hw);
-        pm_qos_remove_request(&sc->pm_qos_req);
        ath_rx_cleanup(sc);
        ath_tx_cleanup(sc);
        ath9k_deinit_softc(sc);
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 180170d3ce25..2915b11edefb 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -885,7 +885,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
        struct ath_common *common = ath9k_hw_common(ah);
        if (!(ints & ATH9K_INT_GLOBAL))
-                ath9k_hw_enable_interrupts(ah);
+                ath9k_hw_disable_interrupts(ah);
        ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
@@ -963,7 +963,8 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
                        REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
        }
-        ath9k_hw_enable_interrupts(ah);
+        if (ints & ATH9K_INT_GLOBAL)
+                ath9k_hw_enable_interrupts(ah);
        return;
 }
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index da5c64597c1f..a09d15f7aa6e 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -1173,12 +1173,6 @@ static int ath9k_start(struct ieee80211_hw *hw)
                        ath9k_btcoex_timer_resume(sc);
        }
-        /* User has the option to provide pm-qos value as a module
-         * parameter rather than using the default value of
-         * 'ATH9K_PM_QOS_DEFAULT_VALUE'.
-         */
-        pm_qos_update_request(&sc->pm_qos_req, ath9k_pm_qos_value);
        if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
                common->bus_ops->extn_synch_en(common);
@@ -1345,8 +1339,6 @@ static void ath9k_stop(struct ieee80211_hw *hw)
        sc->sc_flags |= SC_OP_INVALID;
-        pm_qos_update_request(&sc->pm_qos_req, PM_QOS_DEFAULT_VALUE);
        mutex_unlock(&sc->mutex);
        ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
diff --git a/drivers/net/wireless/ath/carl9170/usb.c b/drivers/net/wireless/ath/carl9170/usb.c
index 537732e5964f..f82c400be288 100644
--- a/drivers/net/wireless/ath/carl9170/usb.c
+++ b/drivers/net/wireless/ath/carl9170/usb.c
@@ -118,6 +118,8 @@ static struct usb_device_id carl9170_usb_ids[] = {
        { USB_DEVICE(0x057c, 0x8402) },
        /* Qwest/Actiontec 802AIN Wireless N USB Network Adapter */
        { USB_DEVICE(0x1668, 0x1200) },
+        /* Airlive X.USB a/b/g/n */
+        { USB_DEVICE(0x1b75, 0x9170) },
        /* terminate */
        {}
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index 79ab0a6b1386..537fb8c84e3a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -51,7 +51,7 @@
 #include "iwl-agn-debugfs.h"
 /* Highest firmware API version supported */
-#define IWL5000_UCODE_API_MAX 2
+#define IWL5000_UCODE_API_MAX 5
 #define IWL5150_UCODE_API_MAX 2
 /* Lowest firmware API version supported */
diff --git a/drivers/net/wireless/p54/p54pci.c b/drivers/net/wireless/p54/p54pci.c
index 1eacba4daa5b..0494d7b102d4 100644
--- a/drivers/net/wireless/p54/p54pci.c
+++ b/drivers/net/wireless/p54/p54pci.c
@@ -199,6 +199,7 @@ static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
        while (i != idx) {
                u16 len;
                struct sk_buff *skb;
+                dma_addr_t dma_addr;
                desc = &ring[i];
                len = le16_to_cpu(desc->len);
                skb = rx_buf[i];
@@ -216,17 +217,20 @@ static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
                        len = priv->common.rx_mtu;
                }
+                dma_addr = le32_to_cpu(desc->host_addr);
+                pci_dma_sync_single_for_cpu(priv->pdev, dma_addr,
+                        priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
                skb_put(skb, len);
                if (p54_rx(dev, skb)) {
-                        pci_unmap_single(priv->pdev,
+                        pci_unmap_single(priv->pdev, dma_addr,
-                                         le32_to_cpu(desc->host_addr),
+                                priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
-                                         priv->common.rx_mtu + 32,
-                                         PCI_DMA_FROMDEVICE);
                        rx_buf[i] = NULL;
-                        desc->host_addr = 0;
+                        desc->host_addr = cpu_to_le32(0);
                } else {
                        skb_trim(skb, 0);
+                        pci_dma_sync_single_for_device(priv->pdev, dma_addr,
+                                priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
                        desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
                }
diff --git a/drivers/net/wireless/p54/p54usb.c b/drivers/net/wireless/p54/p54usb.c
index 21713a7638c4..9b344a921e74 100644
--- a/drivers/net/wireless/p54/p54usb.c
+++ b/drivers/net/wireless/p54/p54usb.c
@@ -98,6 +98,7 @@ static struct usb_device_id p54u_table[] __devinitdata = {
        {USB_DEVICE(0x1413, 0x5400)},   /* Telsey 802.11g USB2.0 Adapter */
        {USB_DEVICE(0x1435, 0x0427)},   /* Inventel UR054G */
        {USB_DEVICE(0x1668, 0x1050)},   /* Actiontec 802UIG-1 */
+        {USB_DEVICE(0x1740, 0x1000)},   /* Senao NUB-350 */
        {USB_DEVICE(0x2001, 0x3704)},   /* DLink DWL-G122 rev A2 */
        {USB_DEVICE(0x2001, 0x3705)},   /* D-Link DWL-G120 rev C1 */
        {USB_DEVICE(0x413c, 0x5513)},   /* Dell WLA3310 USB Wireless Adapter */
diff --git a/drivers/net/wireless/rndis_wlan.c b/drivers/net/wireless/rndis_wlan.c
index 848cc2cce247..518542b4bf9e 100644
--- a/drivers/net/wireless/rndis_wlan.c
+++ b/drivers/net/wireless/rndis_wlan.c
@@ -2597,6 +2597,9 @@ static int rndis_set_power_mgmt(struct wiphy *wiphy, struct net_device *dev,
        __le32 mode;
        int ret;
+        if (priv->device_type != RNDIS_BCM4320B)
+                return -ENOTSUPP;
        netdev_dbg(usbdev->net, "%s(): %s, %d\n", __func__,
                                enabled ? "enabled" : "disabled",
                                timeout);
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index aa97971a38af..3b3f1e45ab3e 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -652,6 +652,12 @@ static void rt2800pci_fill_rxdone(struct queue_entry *entry,
                 */
                rxdesc->flags |= RX_FLAG_IV_STRIPPED;
+                /*
+                 * The hardware has already checked the Michael Mic and has
+                 * stripped it from the frame. Signal this to mac80211.
+                 */
+                rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
                if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
                        rxdesc->flags |= RX_FLAG_DECRYPTED;
                else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
@@ -1065,6 +1071,8 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
        { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
 #endif
 #ifdef CONFIG_RT2800PCI_RT35XX
+        { PCI_DEVICE(0x1432, 0x7711), PCI_DEVICE_DATA(&rt2800pci_ops) },
+        { PCI_DEVICE(0x1432, 0x7722), PCI_DEVICE_DATA(&rt2800pci_ops) },
        { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
        { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
        { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index b97a4a54ff4c..197a36c05fda 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -486,6 +486,12 @@ static void rt2800usb_fill_rxdone(struct queue_entry *entry,
                 */
                rxdesc->flags |= RX_FLAG_IV_STRIPPED;
+                /*
+                 * The hardware has already checked the Michael Mic and has
+                 * stripped it from the frame. Signal this to mac80211.
+                 */
+                rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
                if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
                        rxdesc->flags |= RX_FLAG_DECRYPTED;
                else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
diff --git a/drivers/nfc/Kconfig b/drivers/nfc/Kconfig
index ffedfd492754..ea1580085347 100644
--- a/drivers/nfc/Kconfig
+++ b/drivers/nfc/Kconfig
@@ -3,7 +3,7 @@
 #
 menuconfig NFC_DEVICES
-        bool "NFC devices"
+        bool "Near Field Communication (NFC) devices"
        default n
        ---help---
          You'll have to say Y if your computer contains an NFC device that
diff --git a/drivers/nfc/pn544.c b/drivers/nfc/pn544.c
index bae647264dd6..724f65d8f9e4 100644
--- a/drivers/nfc/pn544.c
+++ b/drivers/nfc/pn544.c
@@ -60,7 +60,7 @@ enum pn544_irq {
 struct pn544_info {
        struct miscdevice miscdev;
        struct i2c_client *i2c_dev;
-        struct regulator_bulk_data regs[2];
+        struct regulator_bulk_data regs[3];
        enum pn544_state state;
        wait_queue_head_t read_wait;
@@ -74,6 +74,7 @@ struct pn544_info {
 static const char reg_vdd_io[]  = "Vdd_IO";
 static const char reg_vbat[]    = "VBat";
+static const char reg_vsim[]    = "VSim";
 /* sysfs interface */
 static ssize_t pn544_test(struct device *dev,
@@ -740,6 +741,7 @@ static int __devinit pn544_probe(struct i2c_client *client,
        info->regs[0].supply = reg_vdd_io;
        info->regs[1].supply = reg_vbat;
+        info->regs[2].supply = reg_vsim;
        r = regulator_bulk_get(&client->dev, ARRAY_SIZE(info->regs),
                                 info->regs);
        if (r < 0)
diff --git a/drivers/of/pdt.c b/drivers/of/pdt.c
index 28295d0a50f6..4d87b5dc9284 100644
--- a/drivers/of/pdt.c
+++ b/drivers/of/pdt.c
@@ -36,19 +36,55 @@ unsigned int of_pdt_unique_id __initdata;
        (p)->unique_id = of_pdt_unique_id++; \
 } while (0)
-static inline const char *of_pdt_node_name(struct device_node *dp)
+static char * __init of_pdt_build_full_name(struct device_node *dp)
 {
-        return dp->path_component_name;
+        int len, ourlen, plen;
+        char *n;
+        dp->path_component_name = build_path_component(dp);
+        plen = strlen(dp->parent->full_name);
+        ourlen = strlen(dp->path_component_name);
+        len = ourlen + plen + 2;
+        n = prom_early_alloc(len);
+        strcpy(n, dp->parent->full_name);
+        if (!of_node_is_root(dp->parent)) {
+                strcpy(n + plen, "/");
+                plen++;
+        }
+        strcpy(n + plen, dp->path_component_name);
+        return n;
 }
-#else
+#else /* CONFIG_SPARC */
 static inline void of_pdt_incr_unique_id(void *p) { }
 static inline void irq_trans_init(struct device_node *dp) { }
-static inline const char *of_pdt_node_name(struct device_node *dp)
+static char * __init of_pdt_build_full_name(struct device_node *dp)
 {
-        return dp->name;
+        static int failsafe_id = 0; /* for generating unique names on failure */
+        char *buf;
+        int len;
+        if (of_pdt_prom_ops->pkg2path(dp->phandle, NULL, 0, &len))
+                goto failsafe;
+        buf = prom_early_alloc(len + 1);
+        if (of_pdt_prom_ops->pkg2path(dp->phandle, buf, len, &len))
+                goto failsafe;
+        return buf;
+ failsafe:
+        buf = prom_early_alloc(strlen(dp->parent->full_name) +
+                               strlen(dp->name) + 16);
+        sprintf(buf, "%s/%s@unknown%i",
+                of_node_is_root(dp->parent) ? "" : dp->parent->full_name,
+                dp->name, failsafe_id++);
+        pr_err("%s: pkg2path failed; assigning %s\n", __func__, buf);
+        return buf;
 }
 #endif /* !CONFIG_SPARC */
@@ -132,47 +168,6 @@ static char * __init of_pdt_get_one_property(phandle node, const char *name)
        return buf;
 }
-static char * __init of_pdt_try_pkg2path(phandle node)
-{
-        char *res, *buf = NULL;
-        int len;
-        if (!of_pdt_prom_ops->pkg2path)
-                return NULL;
-        if (of_pdt_prom_ops->pkg2path(node, buf, 0, &len))
-                return NULL;
-        buf = prom_early_alloc(len + 1);
-        if (of_pdt_prom_ops->pkg2path(node, buf, len, &len)) {
-                pr_err("%s: package-to-path failed\n", __func__);
-                return NULL;
-        }
-        res = strrchr(buf, '/');
-        if (!res) {
-                pr_err("%s: couldn't find / in %s\n", __func__, buf);
-                return NULL;
-        }
-        return res+1;
-}
-/*
- * When fetching the node's name, first try using package-to-path; if
- * that fails (either because the arch hasn't supplied a PROM callback,
- * or some other random failure), fall back to just looking at the node's
- * 'name' property.
- */
-static char * __init of_pdt_build_name(phandle node)
-{
-        char *buf;
-        buf = of_pdt_try_pkg2path(node);
-        if (!buf)
-                buf = of_pdt_get_one_property(node, "name");
-        return buf;
-}
 static struct device_node * __init of_pdt_create_node(phandle node,
                                                    struct device_node *parent)
 {
@@ -187,7 +182,7 @@ static struct device_node * __init of_pdt_create_node(phandle node,
        kref_init(&dp->kref);
-        dp->name = of_pdt_build_name(node);
+        dp->name = of_pdt_get_one_property(node, "name");
        dp->type = of_pdt_get_one_property(node, "device_type");
        dp->phandle = node;
@@ -198,26 +193,6 @@ static struct device_node * __init of_pdt_create_node(phandle node,
        return dp;
 }
-static char * __init of_pdt_build_full_name(struct device_node *dp)
-{
-        int len, ourlen, plen;
-        char *n;
-        plen = strlen(dp->parent->full_name);
-        ourlen = strlen(of_pdt_node_name(dp));
-        len = ourlen + plen + 2;
-        n = prom_early_alloc(len);
-        strcpy(n, dp->parent->full_name);
-        if (!of_node_is_root(dp->parent)) {
-                strcpy(n + plen, "/");
-                plen++;
-        }
-        strcpy(n + plen, of_pdt_node_name(dp));
-        return n;
-}
 static struct device_node * __init of_pdt_build_tree(struct device_node *parent,
                                                   phandle node,
                                                   struct device_node ***nextp)
@@ -240,9 +215,6 @@ static struct device_node * __init of_pdt_build_tree(struct device_node *parent,
                *(*nextp) = dp;
                *nextp = &dp->allnext;
-#if defined(CONFIG_SPARC)
-                dp->path_component_name = build_path_component(dp);
-#endif
                dp->full_name = of_pdt_build_full_name(dp);
                dp->child = of_pdt_build_tree(dp,
diff --git a/drivers/pcmcia/pcmcia_resource.c b/drivers/pcmcia/pcmcia_resource.c
index 0bdda5b3ed55..42fbf1a75576 100644
--- a/drivers/pcmcia/pcmcia_resource.c
+++ b/drivers/pcmcia/pcmcia_resource.c
@@ -518,6 +518,8 @@ int pcmcia_enable_device(struct pcmcia_device *p_dev)
                flags |= CONF_ENABLE_IOCARD;
        if (flags & CONF_ENABLE_IOCARD)
                s->socket.flags |= SS_IOCARD;
+        if (flags & CONF_ENABLE_ZVCARD)
+                s->socket.flags |= SS_ZVCARD | SS_IOCARD;
        if (flags & CONF_ENABLE_SPKR) {
                s->socket.flags |= SS_SPKR_ENA;
                status = CCSR_AUDIO_ENA;
diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c
index 3755e7c8c715..2c540542b5af 100644
--- a/drivers/pcmcia/pxa2xx_base.c
+++ b/drivers/pcmcia/pxa2xx_base.c
@@ -215,7 +215,7 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
 }
 #endif
-static void pxa2xx_configure_sockets(struct device *dev)
+void pxa2xx_configure_sockets(struct device *dev)
 {
        struct pcmcia_low_level *ops = dev->platform_data;
        /*
diff --git a/drivers/pcmcia/pxa2xx_base.h b/drivers/pcmcia/pxa2xx_base.h
index bb62ea87b8f9..b609b45469ed 100644
--- a/drivers/pcmcia/pxa2xx_base.h
+++ b/drivers/pcmcia/pxa2xx_base.h
@@ -1,3 +1,4 @@
 int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt);
 void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops);
+void pxa2xx_configure_sockets(struct device *dev);
diff --git a/drivers/pcmcia/pxa2xx_colibri.c b/drivers/pcmcia/pxa2xx_colibri.c
index c3f72192af66..a52039564e74 100644
--- a/drivers/pcmcia/pxa2xx_colibri.c
+++ b/drivers/pcmcia/pxa2xx_colibri.c
@@ -181,6 +181,9 @@ static int __init colibri_pcmcia_init(void)
 {
        int ret;
+        if (!machine_is_colibri() && !machine_is_colibri320())
+                return -ENODEV;
        colibri_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
        if (!colibri_pcmcia_device)
                return -ENOMEM;
diff --git a/drivers/pcmcia/pxa2xx_lubbock.c b/drivers/pcmcia/pxa2xx_lubbock.c
index b9f8c8fb42bd..25afe637c657 100644
--- a/drivers/pcmcia/pxa2xx_lubbock.c
+++ b/drivers/pcmcia/pxa2xx_lubbock.c
@@ -226,6 +226,7 @@ int pcmcia_lubbock_init(struct sa1111_dev *sadev)
                lubbock_set_misc_wr((1 << 15) | (1 << 14), 0);
                pxa2xx_drv_pcmcia_ops(&lubbock_pcmcia_ops);
+                pxa2xx_configure_sockets(&sadev->dev);
                ret = sa1111_pcmcia_add(sadev, &lubbock_pcmcia_ops,
                                pxa2xx_drv_pcmcia_add_one);
        }
diff --git a/drivers/pps/generators/Kconfig b/drivers/pps/generators/Kconfig
index f3a73dd77660..e4c4f3dc0728 100644
--- a/drivers/pps/generators/Kconfig
+++ b/drivers/pps/generators/Kconfig
@@ -6,7 +6,7 @@ comment "PPS generators support"
 config PPS_GENERATOR_PARPORT
        tristate "Parallel port PPS signal generator"
-        depends on PARPORT
+        depends on PARPORT && BROKEN
        help
          If you say yes here you get support for a PPS signal generator which
          utilizes STROBE pin of a parallel port to send PPS signals. It uses
diff --git a/drivers/pps/kapi.c b/drivers/pps/kapi.c
index cba1b43f7519..a4e8eb9fece6 100644
--- a/drivers/pps/kapi.c
+++ b/drivers/pps/kapi.c
@@ -168,7 +168,7 @@ void pps_event(struct pps_device *pps, struct pps_event_time *ts, int event,
 {
        unsigned long flags;
        int captured = 0;
-        struct pps_ktime ts_real;
+        struct pps_ktime ts_real = { .sec = 0, .nsec = 0, .flags = 0 };
        /* check event type */
        BUG_ON((event & (PPS_CAPTUREASSERT | PPS_CAPTURECLEAR)) == 0);
diff --git a/drivers/rapidio/rio-sysfs.c b/drivers/rapidio/rio-sysfs.c
index 76b41853a877..1269fbd2deca 100644
--- a/drivers/rapidio/rio-sysfs.c
+++ b/drivers/rapidio/rio-sysfs.c
@@ -77,9 +77,9 @@ rio_read_config(struct file *filp, struct kobject *kobj,
        /* Several chips lock up trying to read undefined config space */
        if (capable(CAP_SYS_ADMIN))
-                size = 0x200000;
+                size = RIO_MAINT_SPACE_SZ;
-        if (off > size)
+        if (off >= size)
                return 0;
        if (off + count > size) {
                size -= off;
@@ -147,10 +147,10 @@ rio_write_config(struct file *filp, struct kobject *kobj,
        loff_t init_off = off;
        u8 *data = (u8 *) buf;
-        if (off > 0x200000)
+        if (off >= RIO_MAINT_SPACE_SZ)
                return 0;
-        if (off + count > 0x200000) {
+        if (off + count > RIO_MAINT_SPACE_SZ) {
-                size = 0x200000 - off;
+                size = RIO_MAINT_SPACE_SZ - off;
                count = size;
        }
@@ -200,7 +200,7 @@ static struct bin_attribute rio_config_attr = {
                 .name = "config",
                 .mode = S_IRUGO | S_IWUSR,
                 },
-        .size = 0x200000,
+        .size = RIO_MAINT_SPACE_SZ,
        .read = rio_read_config,
        .write = rio_write_config,
 };
diff --git a/drivers/regulator/mc13xxx-regulator-core.c b/drivers/regulator/mc13xxx-regulator-core.c
index f53d31b950d4..2bb5de1f2421 100644
--- a/drivers/regulator/mc13xxx-regulator-core.c
+++ b/drivers/regulator/mc13xxx-regulator-core.c
@@ -174,7 +174,7 @@ static int mc13xxx_regulator_get_voltage(struct regulator_dev *rdev)
        dev_dbg(rdev_get_dev(rdev), "%s id: %d val: %d\n", __func__, id, val);
-        BUG_ON(val < 0 || val > mc13xxx_regulators[id].desc.n_voltages);
+        BUG_ON(val > mc13xxx_regulators[id].desc.n_voltages);
        return mc13xxx_regulators[id].voltages[val];
 }
diff --git a/drivers/regulator/wm831x-dcdc.c b/drivers/regulator/wm831x-dcdc.c
index 8b0d2c4bde91..06df898842c0 100644
--- a/drivers/regulator/wm831x-dcdc.c
+++ b/drivers/regulator/wm831x-dcdc.c
@@ -120,6 +120,7 @@ static unsigned int wm831x_dcdc_get_mode(struct regulator_dev *rdev)
                return REGULATOR_MODE_IDLE;
        default:
                BUG();
+                return -EINVAL;
        }
 }
diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c
index c36749e4c926..5469c52cba3d 100644
--- a/drivers/rtc/rtc-at91sam9.c
+++ b/drivers/rtc/rtc-at91sam9.c
@@ -309,7 +309,7 @@ static const struct rtc_class_ops at91_rtc_ops = {
        .read_alarm     = at91_rtc_readalarm,
        .set_alarm      = at91_rtc_setalarm,
        .proc           = at91_rtc_proc,
-        .alarm_irq_enabled = at91_rtc_alarm_irq_enable,
+        .alarm_irq_enable = at91_rtc_alarm_irq_enable,
 };
 /*
diff --git a/drivers/rtc/rtc-ds3232.c b/drivers/rtc/rtc-ds3232.c
index 23a9ee19764c..950735415a7c 100644
--- a/drivers/rtc/rtc-ds3232.c
+++ b/drivers/rtc/rtc-ds3232.c
@@ -1,7 +1,7 @@
 /*
 * RTC client/driver for the Maxim/Dallas DS3232 Real-Time Clock over I2C
 *
- * Copyright (C) 2009-2010 Freescale Semiconductor.
+ * Copyright (C) 2009-2011 Freescale Semiconductor.
 * Author: Jack Lan <jack.lan@freescale.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
@@ -141,9 +141,11 @@ static int ds3232_read_time(struct device *dev, struct rtc_time *time)
                time->tm_hour = bcd2bin(hour);
        }
-        time->tm_wday = bcd2bin(week);
+        /* Day of the week in linux range is 0~6 while 1~7 in RTC chip */
+        time->tm_wday = bcd2bin(week) - 1;
        time->tm_mday = bcd2bin(day);
-        time->tm_mon = bcd2bin(month & 0x7F);
+        /* linux tm_mon range:0~11, while month range is 1~12 in RTC chip */
+        time->tm_mon = bcd2bin(month & 0x7F) - 1;
        if (century)
                add_century = 100;
@@ -162,9 +164,11 @@ static int ds3232_set_time(struct device *dev, struct rtc_time *time)
        buf[0] = bin2bcd(time->tm_sec);
        buf[1] = bin2bcd(time->tm_min);
        buf[2] = bin2bcd(time->tm_hour);
-        buf[3] = bin2bcd(time->tm_wday); /* Day of the week */
+        /* Day of the week in linux range is 0~6 while 1~7 in RTC chip */
+        buf[3] = bin2bcd(time->tm_wday + 1);
        buf[4] = bin2bcd(time->tm_mday); /* Date */
-        buf[5] = bin2bcd(time->tm_mon);
+        /* linux tm_mon range:0~11, while month range is 1~12 in RTC chip */
+        buf[5] = bin2bcd(time->tm_mon + 1);
        if (time->tm_year >= 100) {
                buf[5] |= 0x80;
                buf[6] = bin2bcd(time->tm_year - 100);
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index cf953ecbfca9..b80fa2882408 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -77,18 +77,20 @@ static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
 }
 /* Update control registers */
-static void s3c_rtc_setaie(int to)
+static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
 {
        unsigned int tmp;
-        pr_debug("%s: aie=%d\n", __func__, to);
+        pr_debug("%s: aie=%d\n", __func__, enabled);
        tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
-        if (to)
+        if (enabled)
                tmp |= S3C2410_RTCALM_ALMEN;
        writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
+        return 0;
 }
 static int s3c_rtc_setpie(struct device *dev, int enabled)
@@ -308,7 +310,7 @@ static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
        writeb(alrm_en, base + S3C2410_RTCALM);
-        s3c_rtc_setaie(alrm->enabled);
+        s3c_rtc_setaie(dev, alrm->enabled);
        return 0;
 }
@@ -440,7 +442,7 @@ static int __devexit s3c_rtc_remove(struct platform_device *dev)
        rtc_device_unregister(rtc);
        s3c_rtc_setpie(&dev->dev, 0);
-        s3c_rtc_setaie(0);
+        s3c_rtc_setaie(&dev->dev, 0);
        clk_disable(rtc_clk);
        clk_put(rtc_clk);
diff --git a/drivers/s390/block/xpram.c b/drivers/s390/block/xpram.c
index c881a14fa5dd..1f6a4d894e73 100644
--- a/drivers/s390/block/xpram.c
+++ b/drivers/s390/block/xpram.c
@@ -62,8 +62,8 @@ static int xpram_devs;
 /*
 * Parameter parsing functions.
 */
-static int __initdata devs = XPRAM_DEVS;
+static int devs = XPRAM_DEVS;
-static char __initdata *sizes[XPRAM_MAX_DEVS];
+static char *sizes[XPRAM_MAX_DEVS];
 module_param(devs, int, 0);
 module_param_array(sizes, charp, NULL, 0);
diff --git a/drivers/s390/char/keyboard.c b/drivers/s390/char/keyboard.c
index 8cd58e412b5e..5ad44daef73b 100644
--- a/drivers/s390/char/keyboard.c
+++ b/drivers/s390/char/keyboard.c
@@ -460,7 +460,8 @@ kbd_ioctl(struct kbd_data *kbd, struct file *file,
          unsigned int cmd, unsigned long arg)
 {
        void __user *argp;
-        int ct, perm;
+        unsigned int ct;
+        int perm;
        argp = (void __user *)arg;
diff --git a/drivers/s390/char/tape.h b/drivers/s390/char/tape.h
index 7a242f073632..267b54e8ff5a 100644
--- a/drivers/s390/char/tape.h
+++ b/drivers/s390/char/tape.h
@@ -280,6 +280,14 @@ tape_do_io_free(struct tape_device *device, struct tape_request *request)
        return rc;
 }
+static inline void
+tape_do_io_async_free(struct tape_device *device, struct tape_request *request)
+{
+        request->callback = (void *) tape_free_request;
+        request->callback_data = NULL;
+        tape_do_io_async(device, request);
+}
 extern int tape_oper_handler(int irq, int status);
 extern void tape_noper_handler(int irq, int status);
 extern int tape_open(struct tape_device *);
diff --git a/drivers/s390/char/tape_34xx.c b/drivers/s390/char/tape_34xx.c
index c17f35b6136a..c26511171ffe 100644
--- a/drivers/s390/char/tape_34xx.c
+++ b/drivers/s390/char/tape_34xx.c
@@ -53,23 +53,11 @@ static void tape_34xx_delete_sbid_from(struct tape_device *, int);
 * Medium sense for 34xx tapes. There is no 'real' medium sense call.
 * So we just do a normal sense.
 */
-static int
+static void __tape_34xx_medium_sense(struct tape_request *request)
-tape_34xx_medium_sense(struct tape_device *device)
 {
-        struct tape_request *request;
+        struct tape_device *device = request->device;
-        unsigned char       *sense;
+        unsigned char *sense;
-        int                  rc;
-        request = tape_alloc_request(1, 32);
-        if (IS_ERR(request)) {
-                DBF_EXCEPTION(6, "MSEN fail\n");
-                return PTR_ERR(request);
-        }
-        request->op = TO_MSEN;
-        tape_ccw_end(request->cpaddr, SENSE, 32, request->cpdata);
-        rc = tape_do_io_interruptible(device, request);
        if (request->rc == 0) {
                sense = request->cpdata;
@@ -88,15 +76,47 @@ tape_34xx_medium_sense(struct tape_device *device)
                        device->tape_generic_status |= GMT_WR_PROT(~0);
                else
                        device->tape_generic_status &= ~GMT_WR_PROT(~0);
-        } else {
+        } else
                DBF_EVENT(4, "tape_34xx: medium sense failed with rc=%d\n",
                        request->rc);
-        }
        tape_free_request(request);
+}
+static int tape_34xx_medium_sense(struct tape_device *device)
+{
+        struct tape_request *request;
+        int rc;
+        request = tape_alloc_request(1, 32);
+        if (IS_ERR(request)) {
+                DBF_EXCEPTION(6, "MSEN fail\n");
+                return PTR_ERR(request);
+        }
+        request->op = TO_MSEN;
+        tape_ccw_end(request->cpaddr, SENSE, 32, request->cpdata);
+        rc = tape_do_io_interruptible(device, request);
+        __tape_34xx_medium_sense(request);
        return rc;
 }
+static void tape_34xx_medium_sense_async(struct tape_device *device)
+{
+        struct tape_request *request;
+        request = tape_alloc_request(1, 32);
+        if (IS_ERR(request)) {
+                DBF_EXCEPTION(6, "MSEN fail\n");
+                return;
+        }
+        request->op = TO_MSEN;
+        tape_ccw_end(request->cpaddr, SENSE, 32, request->cpdata);
+        request->callback = (void *) __tape_34xx_medium_sense;
+        request->callback_data = NULL;
+        tape_do_io_async(device, request);
+}
 struct tape_34xx_work {
        struct tape_device      *device;
        enum tape_op             op;
@@ -109,6 +129,9 @@ struct tape_34xx_work {
 * is inserted but cannot call tape_do_io* from an interrupt context.
 * Maybe that's useful for other actions we want to start from the
 * interrupt handler.
+ * Note: the work handler is called by the system work queue. The tape
+ * commands started by the handler need to be asynchrounous, otherwise
+ * a deadlock can occur e.g. in case of a deferred cc=1 (see __tape_do_irq).
 */
 static void
 tape_34xx_work_handler(struct work_struct *work)
@@ -119,7 +142,7 @@ tape_34xx_work_handler(struct work_struct *work)
        switch(p->op) {
                case TO_MSEN:
-                        tape_34xx_medium_sense(device);
+                        tape_34xx_medium_sense_async(device);
                        break;
                default:
                        DBF_EVENT(3, "T34XX: internal error: unknown work\n");
diff --git a/drivers/s390/char/tape_3590.c b/drivers/s390/char/tape_3590.c
index fbe361fcd2c0..de2e99e0a71b 100644
--- a/drivers/s390/char/tape_3590.c
+++ b/drivers/s390/char/tape_3590.c
@@ -329,17 +329,17 @@ out:
 /*
 * Enable encryption
 */
-static int tape_3592_enable_crypt(struct tape_device *device)
+static struct tape_request *__tape_3592_enable_crypt(struct tape_device *device)
 {
        struct tape_request *request;
        char *data;
        DBF_EVENT(6, "tape_3592_enable_crypt\n");
        if (!crypt_supported(device))
-                return -ENOSYS;
+                return ERR_PTR(-ENOSYS);
        request = tape_alloc_request(2, 72);
        if (IS_ERR(request))
-                return PTR_ERR(request);
+                return request;
        data = request->cpdata;
        memset(data,0,72);
@@ -354,23 +354,42 @@ static int tape_3592_enable_crypt(struct tape_device *device)
        request->op = TO_CRYPT_ON;
        tape_ccw_cc(request->cpaddr, MODE_SET_CB, 36, data);
        tape_ccw_end(request->cpaddr + 1, MODE_SET_CB, 36, data + 36);
+        return request;
+}
+static int tape_3592_enable_crypt(struct tape_device *device)
+{
+        struct tape_request *request;
+        request = __tape_3592_enable_crypt(device);
+        if (IS_ERR(request))
+                return PTR_ERR(request);
        return tape_do_io_free(device, request);
 }
+static void tape_3592_enable_crypt_async(struct tape_device *device)
+{
+        struct tape_request *request;
+        request = __tape_3592_enable_crypt(device);
+        if (!IS_ERR(request))
+                tape_do_io_async_free(device, request);
+}
 /*
 * Disable encryption
 */
-static int tape_3592_disable_crypt(struct tape_device *device)
+static struct tape_request *__tape_3592_disable_crypt(struct tape_device *device)
 {
        struct tape_request *request;
        char *data;
        DBF_EVENT(6, "tape_3592_disable_crypt\n");
        if (!crypt_supported(device))
-                return -ENOSYS;
+                return ERR_PTR(-ENOSYS);
        request = tape_alloc_request(2, 72);
        if (IS_ERR(request))
-                return PTR_ERR(request);
+                return request;
        data = request->cpdata;
        memset(data,0,72);
@@ -383,9 +402,28 @@ static int tape_3592_disable_crypt(struct tape_device *device)
        tape_ccw_cc(request->cpaddr, MODE_SET_CB, 36, data);
        tape_ccw_end(request->cpaddr + 1, MODE_SET_CB, 36, data + 36);
+        return request;
+}
+static int tape_3592_disable_crypt(struct tape_device *device)
+{
+        struct tape_request *request;
+        request = __tape_3592_disable_crypt(device);
+        if (IS_ERR(request))
+                return PTR_ERR(request);
        return tape_do_io_free(device, request);
 }
+static void tape_3592_disable_crypt_async(struct tape_device *device)
+{
+        struct tape_request *request;
+        request = __tape_3592_disable_crypt(device);
+        if (!IS_ERR(request))
+                tape_do_io_async_free(device, request);
+}
 /*
 * IOCTL: Set encryption status
 */
@@ -457,8 +495,7 @@ tape_3590_ioctl(struct tape_device *device, unsigned int cmd, unsigned long arg)
 /*
 * SENSE Medium: Get Sense data about medium state
 */
-static int
+static int tape_3590_sense_medium(struct tape_device *device)
-tape_3590_sense_medium(struct tape_device *device)
 {
        struct tape_request *request;
@@ -470,6 +507,18 @@ tape_3590_sense_medium(struct tape_device *device)
        return tape_do_io_free(device, request);
 }
+static void tape_3590_sense_medium_async(struct tape_device *device)
+{
+        struct tape_request *request;
+        request = tape_alloc_request(1, 128);
+        if (IS_ERR(request))
+                return;
+        request->op = TO_MSEN;
+        tape_ccw_end(request->cpaddr, MEDIUM_SENSE, 128, request->cpdata);
+        tape_do_io_async_free(device, request);
+}
 /*
 * MTTELL: Tell block. Return the number of block relative to current file.
 */
@@ -546,15 +595,14 @@ tape_3590_read_opposite(struct tape_device *device,
 * 2. The attention msg is written to the "read subsystem data" buffer.
 * In this case we probably should print it to the console.
 */
-static int
+static void tape_3590_read_attmsg_async(struct tape_device *device)
-tape_3590_read_attmsg(struct tape_device *device)
 {
        struct tape_request *request;
        char *buf;
        request = tape_alloc_request(3, 4096);
        if (IS_ERR(request))
-                return PTR_ERR(request);
+                return;
        request->op = TO_READ_ATTMSG;
        buf = request->cpdata;
        buf[0] = PREP_RD_SS_DATA;
@@ -562,12 +610,15 @@ tape_3590_read_attmsg(struct tape_device *device)
        tape_ccw_cc(request->cpaddr, PERFORM_SS_FUNC, 12, buf);
        tape_ccw_cc(request->cpaddr + 1, READ_SS_DATA, 4096 - 12, buf + 12);
        tape_ccw_end(request->cpaddr + 2, NOP, 0, NULL);
-        return tape_do_io_free(device, request);
+        tape_do_io_async_free(device, request);
 }
 /*
 * These functions are used to schedule follow-up actions from within an
 * interrupt context (like unsolicited interrupts).
+ * Note: the work handler is called by the system work queue. The tape
+ * commands started by the handler need to be asynchrounous, otherwise
+ * a deadlock can occur e.g. in case of a deferred cc=1 (see __tape_do_irq).
 */
 struct work_handler_data {
        struct tape_device *device;
@@ -583,16 +634,16 @@ tape_3590_work_handler(struct work_struct *work)
        switch (p->op) {
        case TO_MSEN:
-                tape_3590_sense_medium(p->device);
+                tape_3590_sense_medium_async(p->device);
                break;
        case TO_READ_ATTMSG:
-                tape_3590_read_attmsg(p->device);
+                tape_3590_read_attmsg_async(p->device);
                break;
        case TO_CRYPT_ON:
-                tape_3592_enable_crypt(p->device);
+                tape_3592_enable_crypt_async(p->device);
                break;
        case TO_CRYPT_OFF:
-                tape_3592_disable_crypt(p->device);
+                tape_3592_disable_crypt_async(p->device);
                break;
        default:
                DBF_EVENT(3, "T3590: work handler undefined for "
diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c
index 9045c52abd25..fb2bb35c62cb 100644
--- a/drivers/scsi/scsi_lib.c
+++ b/drivers/scsi/scsi_lib.c
@@ -443,7 +443,7 @@ static void scsi_run_queue(struct request_queue *q)
                                        &sdev->request_queue->queue_flags);
                if (flagset)
                        queue_flag_set(QUEUE_FLAG_REENTER, sdev->request_queue);
-                __blk_run_queue(sdev->request_queue);
+                __blk_run_queue(sdev->request_queue, false);
                if (flagset)
                        queue_flag_clear(QUEUE_FLAG_REENTER, sdev->request_queue);
                spin_unlock(sdev->request_queue->queue_lock);
diff --git a/drivers/scsi/scsi_transport_fc.c b/drivers/scsi/scsi_transport_fc.c
index 998c01be3234..5c3ccfc6b622 100644
--- a/drivers/scsi/scsi_transport_fc.c
+++ b/drivers/scsi/scsi_transport_fc.c
@@ -3829,7 +3829,7 @@ fc_bsg_goose_queue(struct fc_rport *rport)
                  !test_bit(QUEUE_FLAG_REENTER, &rport->rqst_q->queue_flags);
        if (flagset)
                queue_flag_set(QUEUE_FLAG_REENTER, rport->rqst_q);
-        __blk_run_queue(rport->rqst_q);
+        __blk_run_queue(rport->rqst_q, false);
        if (flagset)
                queue_flag_clear(QUEUE_FLAG_REENTER, rport->rqst_q);
        spin_unlock_irqrestore(rport->rqst_q->queue_lock, flags);
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 42f5a8d7c817..7b90fc361b52 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -161,13 +161,13 @@ config SPI_IMX_VER_0_0
        def_bool y if SOC_IMX21 || SOC_IMX27
 config SPI_IMX_VER_0_4
-        def_bool y if ARCH_MX31
+        def_bool y if SOC_IMX31
 config SPI_IMX_VER_0_7
-        def_bool y if ARCH_MX25 || ARCH_MX35 || ARCH_MX51 || ARCH_MX53
+        def_bool y if ARCH_MX25 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
 config SPI_IMX_VER_2_3
-        def_bool y if ARCH_MX51 || ARCH_MX53
+        def_bool y if SOC_IMX51 || SOC_IMX53
 config SPI_IMX
        tristate "Freescale i.MX SPI controllers"
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index f7a5dba3ca23..bf7c687519ef 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -4,7 +4,6 @@
 menuconfig THERMAL
        tristate "Generic Thermal sysfs driver"
-        depends on NET
        help
          Generic Thermal Sysfs driver offers a generic mechanism for
          thermal management. Usually it's made up of one or more thermal
diff --git a/drivers/thermal/thermal_sys.c b/drivers/thermal/thermal_sys.c
index 7d0e63c79280..713b7ea4a607 100644
--- a/drivers/thermal/thermal_sys.c
+++ b/drivers/thermal/thermal_sys.c
@@ -62,20 +62,6 @@ static DEFINE_MUTEX(thermal_list_lock);
 static unsigned int thermal_event_seqnum;
-static struct genl_family thermal_event_genl_family = {
-        .id = GENL_ID_GENERATE,
-        .name = THERMAL_GENL_FAMILY_NAME,
-        .version = THERMAL_GENL_VERSION,
-        .maxattr = THERMAL_GENL_ATTR_MAX,
-};
-static struct genl_multicast_group thermal_event_mcgrp = {
-        .name = THERMAL_GENL_MCAST_GROUP_NAME,
-};
-static int genetlink_init(void);
-static void genetlink_exit(void);
 static int get_idr(struct idr *idr, struct mutex *lock, int *id)
 {
        int err;
@@ -1225,6 +1211,18 @@ void thermal_zone_device_unregister(struct thermal_zone_device *tz)
 EXPORT_SYMBOL(thermal_zone_device_unregister);
+#ifdef CONFIG_NET
+static struct genl_family thermal_event_genl_family = {
+        .id = GENL_ID_GENERATE,
+        .name = THERMAL_GENL_FAMILY_NAME,
+        .version = THERMAL_GENL_VERSION,
+        .maxattr = THERMAL_GENL_ATTR_MAX,
+};
+static struct genl_multicast_group thermal_event_mcgrp = {
+        .name = THERMAL_GENL_MCAST_GROUP_NAME,
+};
 int generate_netlink_event(u32 orig, enum events event)
 {
        struct sk_buff *skb;
@@ -1301,6 +1299,15 @@ static int genetlink_init(void)
        return result;
 }
+static void genetlink_exit(void)
+{
+        genl_unregister_family(&thermal_event_genl_family);
+}
+#else /* !CONFIG_NET */
+static inline int genetlink_init(void) { return 0; }
+static inline void genetlink_exit(void) {}
+#endif /* !CONFIG_NET */
 static int __init thermal_init(void)
 {
        int result = 0;
@@ -1316,11 +1323,6 @@ static int __init thermal_init(void)
        return result;
 }
-static void genetlink_exit(void)
-{
-        genl_unregister_family(&thermal_event_genl_family);
-}
 static void __exit thermal_exit(void)
 {
        class_unregister(&thermal_class);
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 2b8334601c8b..5c4b3475621f 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1596,4 +1596,19 @@ config SERIAL_PCH_UART
          This driver is for PCH(Platform controller Hub) UART of Intel EG20T
          which is an IOH(Input/Output Hub) for x86 embedded processor.
          Enabling PCH_DMA, this PCH UART works as DMA mode.
+config SERIAL_MXS_AUART
+        depends on ARCH_MXS
+        tristate "MXS AUART support"
+        select SERIAL_CORE
+        help
+          This driver supports the MXS Application UART (AUART) port.
+config SERIAL_MXS_AUART_CONSOLE
+        bool "MXS AUART console support"
+        depends on SERIAL_MXS_AUART=y
+        select SERIAL_CORE_CONSOLE
+        help
+          Enable a MXS AUART port to be the system console.
 endmenu
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 8ea92e9c73b0..c8550719de5a 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -92,3 +92,4 @@ obj-$(CONFIG_SERIAL_MRST_MAX3110)	+= mrst_max3110.o
 obj-$(CONFIG_SERIAL_MFD_HSU)    += mfd.o
 obj-$(CONFIG_SERIAL_IFX6X60)    += ifx6x60.o
 obj-$(CONFIG_SERIAL_PCH_UART)   += pch_uart.o
+obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
new file mode 100644
index 000000000000..7e02c9c344fe
--- /dev/null
+++ b/drivers/tty/serial/mxs-auart.c
@@ -0,0 +1,798 @@
+/*
+ * Freescale STMP37XX/STMP378X Application UART driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/wait.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <asm/cacheflush.h>
+#define MXS_AUART_PORTS 5
+#define AUART_CTRL0                     0x00000000
+#define AUART_CTRL0_SET                 0x00000004
+#define AUART_CTRL0_CLR                 0x00000008
+#define AUART_CTRL0_TOG                 0x0000000c
+#define AUART_CTRL1                     0x00000010
+#define AUART_CTRL1_SET                 0x00000014
+#define AUART_CTRL1_CLR                 0x00000018
+#define AUART_CTRL1_TOG                 0x0000001c
+#define AUART_CTRL2                     0x00000020
+#define AUART_CTRL2_SET                 0x00000024
+#define AUART_CTRL2_CLR                 0x00000028
+#define AUART_CTRL2_TOG                 0x0000002c
+#define AUART_LINECTRL                  0x00000030
+#define AUART_LINECTRL_SET              0x00000034
+#define AUART_LINECTRL_CLR              0x00000038
+#define AUART_LINECTRL_TOG              0x0000003c
+#define AUART_LINECTRL2                 0x00000040
+#define AUART_LINECTRL2_SET             0x00000044
+#define AUART_LINECTRL2_CLR             0x00000048
+#define AUART_LINECTRL2_TOG             0x0000004c
+#define AUART_INTR                      0x00000050
+#define AUART_INTR_SET                  0x00000054
+#define AUART_INTR_CLR                  0x00000058
+#define AUART_INTR_TOG                  0x0000005c
+#define AUART_DATA                      0x00000060
+#define AUART_STAT                      0x00000070
+#define AUART_DEBUG                     0x00000080
+#define AUART_VERSION                   0x00000090
+#define AUART_AUTOBAUD                  0x000000a0
+#define AUART_CTRL0_SFTRST                      (1 << 31)
+#define AUART_CTRL0_CLKGATE                     (1 << 30)
+#define AUART_CTRL2_CTSEN                       (1 << 15)
+#define AUART_CTRL2_RTS                         (1 << 11)
+#define AUART_CTRL2_RXE                         (1 << 9)
+#define AUART_CTRL2_TXE                         (1 << 8)
+#define AUART_CTRL2_UARTEN                      (1 << 0)
+#define AUART_LINECTRL_BAUD_DIVINT_SHIFT        16
+#define AUART_LINECTRL_BAUD_DIVINT_MASK         0xffff0000
+#define AUART_LINECTRL_BAUD_DIVINT(v)           (((v) & 0xffff) << 16)
+#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT       8
+#define AUART_LINECTRL_BAUD_DIVFRAC_MASK        0x00003f00
+#define AUART_LINECTRL_BAUD_DIVFRAC(v)          (((v) & 0x3f) << 8)
+#define AUART_LINECTRL_WLEN_MASK                0x00000060
+#define AUART_LINECTRL_WLEN(v)                  (((v) & 0x3) << 5)
+#define AUART_LINECTRL_FEN                      (1 << 4)
+#define AUART_LINECTRL_STP2                     (1 << 3)
+#define AUART_LINECTRL_EPS                      (1 << 2)
+#define AUART_LINECTRL_PEN                      (1 << 1)
+#define AUART_LINECTRL_BRK                      (1 << 0)
+#define AUART_INTR_RTIEN                        (1 << 22)
+#define AUART_INTR_TXIEN                        (1 << 21)
+#define AUART_INTR_RXIEN                        (1 << 20)
+#define AUART_INTR_CTSMIEN                      (1 << 17)
+#define AUART_INTR_RTIS                         (1 << 6)
+#define AUART_INTR_TXIS                         (1 << 5)
+#define AUART_INTR_RXIS                         (1 << 4)
+#define AUART_INTR_CTSMIS                       (1 << 1)
+#define AUART_STAT_BUSY                         (1 << 29)
+#define AUART_STAT_CTS                          (1 << 28)
+#define AUART_STAT_TXFE                         (1 << 27)
+#define AUART_STAT_TXFF                         (1 << 25)
+#define AUART_STAT_RXFE                         (1 << 24)
+#define AUART_STAT_OERR                         (1 << 19)
+#define AUART_STAT_BERR                         (1 << 18)
+#define AUART_STAT_PERR                         (1 << 17)
+#define AUART_STAT_FERR                         (1 << 16)
+static struct uart_driver auart_driver;
+struct mxs_auart_port {
+        struct uart_port port;
+        unsigned int flags;
+        unsigned int ctrl;
+        unsigned int irq;
+        struct clk *clk;
+        struct device *dev;
+};
+static void mxs_auart_stop_tx(struct uart_port *u);
+#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
+static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
+{
+        struct circ_buf *xmit = &s->port.state->xmit;
+        while (!(readl(s->port.membase + AUART_STAT) &
+                 AUART_STAT_TXFF)) {
+                if (s->port.x_char) {
+                        s->port.icount.tx++;
+                        writel(s->port.x_char,
+                                     s->port.membase + AUART_DATA);
+                        s->port.x_char = 0;
+                        continue;
+                }
+                if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
+                        s->port.icount.tx++;
+                        writel(xmit->buf[xmit->tail],
+                                     s->port.membase + AUART_DATA);
+                        xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+                        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                                uart_write_wakeup(&s->port);
+                } else
+                        break;
+        }
+        if (uart_circ_empty(&(s->port.state->xmit)))
+                writel(AUART_INTR_TXIEN,
+                             s->port.membase + AUART_INTR_CLR);
+        else
+                writel(AUART_INTR_TXIEN,
+                             s->port.membase + AUART_INTR_SET);
+        if (uart_tx_stopped(&s->port))
+                mxs_auart_stop_tx(&s->port);
+}
+static void mxs_auart_rx_char(struct mxs_auart_port *s)
+{
+        int flag;
+        u32 stat;
+        u8 c;
+        c = readl(s->port.membase + AUART_DATA);
+        stat = readl(s->port.membase + AUART_STAT);
+        flag = TTY_NORMAL;
+        s->port.icount.rx++;
+        if (stat & AUART_STAT_BERR) {
+                s->port.icount.brk++;
+                if (uart_handle_break(&s->port))
+                        goto out;
+        } else if (stat & AUART_STAT_PERR) {
+                s->port.icount.parity++;
+        } else if (stat & AUART_STAT_FERR) {
+                s->port.icount.frame++;
+        }
+        /*
+         * Mask off conditions which should be ingored.
+         */
+        stat &= s->port.read_status_mask;
+        if (stat & AUART_STAT_BERR) {
+                flag = TTY_BREAK;
+        } else if (stat & AUART_STAT_PERR)
+                flag = TTY_PARITY;
+        else if (stat & AUART_STAT_FERR)
+                flag = TTY_FRAME;
+        if (stat & AUART_STAT_OERR)
+                s->port.icount.overrun++;
+        if (uart_handle_sysrq_char(&s->port, c))
+                goto out;
+        uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
+out:
+        writel(stat, s->port.membase + AUART_STAT);
+}
+static void mxs_auart_rx_chars(struct mxs_auart_port *s)
+{
+        struct tty_struct *tty = s->port.state->port.tty;
+        u32 stat = 0;
+        for (;;) {
+                stat = readl(s->port.membase + AUART_STAT);
+                if (stat & AUART_STAT_RXFE)
+                        break;
+                mxs_auart_rx_char(s);
+        }
+        writel(stat, s->port.membase + AUART_STAT);
+        tty_flip_buffer_push(tty);
+}
+static int mxs_auart_request_port(struct uart_port *u)
+{
+        return 0;
+}
+static int mxs_auart_verify_port(struct uart_port *u,
+                                    struct serial_struct *ser)
+{
+        if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
+                return -EINVAL;
+        return 0;
+}
+static void mxs_auart_config_port(struct uart_port *u, int flags)
+{
+}
+static const char *mxs_auart_type(struct uart_port *u)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+        return dev_name(s->dev);
+}
+static void mxs_auart_release_port(struct uart_port *u)
+{
+}
+static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+        u32 ctrl = readl(u->membase + AUART_CTRL2);
+        ctrl &= ~AUART_CTRL2_RTS;
+        if (mctrl & TIOCM_RTS)
+                ctrl |= AUART_CTRL2_RTS;
+        s->ctrl = mctrl;
+        writel(ctrl, u->membase + AUART_CTRL2);
+}
+static u32 mxs_auart_get_mctrl(struct uart_port *u)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+        u32 stat = readl(u->membase + AUART_STAT);
+        int ctrl2 = readl(u->membase + AUART_CTRL2);
+        u32 mctrl = s->ctrl;
+        mctrl &= ~TIOCM_CTS;
+        if (stat & AUART_STAT_CTS)
+                mctrl |= TIOCM_CTS;
+        if (ctrl2 & AUART_CTRL2_RTS)
+                mctrl |= TIOCM_RTS;
+        return mctrl;
+}
+static void mxs_auart_settermios(struct uart_port *u,
+                                 struct ktermios *termios,
+                                 struct ktermios *old)
+{
+        u32 bm, ctrl, ctrl2, div;
+        unsigned int cflag, baud;
+        cflag = termios->c_cflag;
+        ctrl = AUART_LINECTRL_FEN;
+        ctrl2 = readl(u->membase + AUART_CTRL2);
+        /* byte size */
+        switch (cflag & CSIZE) {
+        case CS5:
+                bm = 0;
+                break;
+        case CS6:
+                bm = 1;
+                break;
+        case CS7:
+                bm = 2;
+                break;
+        case CS8:
+                bm = 3;
+                break;
+        default:
+                return;
+        }
+        ctrl |= AUART_LINECTRL_WLEN(bm);
+        /* parity */
+        if (cflag & PARENB) {
+                ctrl |= AUART_LINECTRL_PEN;
+                if ((cflag & PARODD) == 0)
+                        ctrl |= AUART_LINECTRL_EPS;
+        }
+        u->read_status_mask = 0;
+        if (termios->c_iflag & INPCK)
+                u->read_status_mask |= AUART_STAT_PERR;
+        if (termios->c_iflag & (BRKINT | PARMRK))
+                u->read_status_mask |= AUART_STAT_BERR;
+        /*
+         * Characters to ignore
+         */
+        u->ignore_status_mask = 0;
+        if (termios->c_iflag & IGNPAR)
+                u->ignore_status_mask |= AUART_STAT_PERR;
+        if (termios->c_iflag & IGNBRK) {
+                u->ignore_status_mask |= AUART_STAT_BERR;
+                /*
+                 * If we're ignoring parity and break indicators,
+                 * ignore overruns too (for real raw support).
+                 */
+                if (termios->c_iflag & IGNPAR)
+                        u->ignore_status_mask |= AUART_STAT_OERR;
+        }
+        /*
+         * ignore all characters if CREAD is not set
+         */
+        if (cflag & CREAD)
+                ctrl2 |= AUART_CTRL2_RXE;
+        else
+                ctrl2 &= ~AUART_CTRL2_RXE;
+        /* figure out the stop bits requested */
+        if (cflag & CSTOPB)
+                ctrl |= AUART_LINECTRL_STP2;
+        /* figure out the hardware flow control settings */
+        if (cflag & CRTSCTS)
+                ctrl2 |= AUART_CTRL2_CTSEN;
+        else
+                ctrl2 &= ~AUART_CTRL2_CTSEN;
+        /* set baud rate */
+        baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
+        div = u->uartclk * 32 / baud;
+        ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
+        ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
+        writel(ctrl, u->membase + AUART_LINECTRL);
+        writel(ctrl2, u->membase + AUART_CTRL2);
+}
+static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
+{
+        u32 istatus, istat;
+        struct mxs_auart_port *s = context;
+        u32 stat = readl(s->port.membase + AUART_STAT);
+        istatus = istat = readl(s->port.membase + AUART_INTR);
+        if (istat & AUART_INTR_CTSMIS) {
+                uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
+                writel(AUART_INTR_CTSMIS,
+                                s->port.membase + AUART_INTR_CLR);
+                istat &= ~AUART_INTR_CTSMIS;
+        }
+        if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
+                mxs_auart_rx_chars(s);
+                istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
+        }
+        if (istat & AUART_INTR_TXIS) {
+                mxs_auart_tx_chars(s);
+                istat &= ~AUART_INTR_TXIS;
+        }
+        writel(istatus & (AUART_INTR_RTIS
+                | AUART_INTR_TXIS
+                | AUART_INTR_RXIS
+                | AUART_INTR_CTSMIS),
+                        s->port.membase + AUART_INTR_CLR);
+        return IRQ_HANDLED;
+}
+static void mxs_auart_reset(struct uart_port *u)
+{
+        int i;
+        unsigned int reg;
+        writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
+        for (i = 0; i < 10000; i++) {
+                reg = readl(u->membase + AUART_CTRL0);
+                if (!(reg & AUART_CTRL0_SFTRST))
+                        break;
+                udelay(3);
+        }
+        writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
+}
+static int mxs_auart_startup(struct uart_port *u)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+        clk_enable(s->clk);
+        writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
+        writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
+        writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
+                        u->membase + AUART_INTR);
+        /*
+         * Enable fifo so all four bytes of a DMA word are written to
+         * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
+         */
+        writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
+        return 0;
+}
+static void mxs_auart_shutdown(struct uart_port *u)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+        writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
+        writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
+        writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
+                        u->membase + AUART_INTR_CLR);
+        clk_disable(s->clk);
+}
+static unsigned int mxs_auart_tx_empty(struct uart_port *u)
+{
+        if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
+                return TIOCSER_TEMT;
+        else
+                return 0;
+}
+static void mxs_auart_start_tx(struct uart_port *u)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+        /* enable transmitter */
+        writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
+        mxs_auart_tx_chars(s);
+}
+static void mxs_auart_stop_tx(struct uart_port *u)
+{
+        writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
+}
+static void mxs_auart_stop_rx(struct uart_port *u)
+{
+        writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
+}
+static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
+{
+        if (ctl)
+                writel(AUART_LINECTRL_BRK,
+                             u->membase + AUART_LINECTRL_SET);
+        else
+                writel(AUART_LINECTRL_BRK,
+                             u->membase + AUART_LINECTRL_CLR);
+}
+static void mxs_auart_enable_ms(struct uart_port *port)
+{
+        /* just empty */
+}
+static struct uart_ops mxs_auart_ops = {
+        .tx_empty       = mxs_auart_tx_empty,
+        .start_tx       = mxs_auart_start_tx,
+        .stop_tx        = mxs_auart_stop_tx,
+        .stop_rx        = mxs_auart_stop_rx,
+        .enable_ms      = mxs_auart_enable_ms,
+        .break_ctl      = mxs_auart_break_ctl,
+        .set_mctrl      = mxs_auart_set_mctrl,
+        .get_mctrl      = mxs_auart_get_mctrl,
+        .startup        = mxs_auart_startup,
+        .shutdown       = mxs_auart_shutdown,
+        .set_termios    = mxs_auart_settermios,
+        .type           = mxs_auart_type,
+        .release_port   = mxs_auart_release_port,
+        .request_port   = mxs_auart_request_port,
+        .config_port    = mxs_auart_config_port,
+        .verify_port    = mxs_auart_verify_port,
+};
+static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
+#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
+static void mxs_auart_console_putchar(struct uart_port *port, int ch)
+{
+        unsigned int to = 1000;
+        while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
+                if (!to--)
+                        break;
+                udelay(1);
+        }
+        writel(ch, port->membase + AUART_DATA);
+}
+static void
+auart_console_write(struct console *co, const char *str, unsigned int count)
+{
+        struct mxs_auart_port *s;
+        struct uart_port *port;
+        unsigned int old_ctrl0, old_ctrl2;
+        unsigned int to = 1000;
+        if (co->index > MXS_AUART_PORTS || co->index < 0)
+                return;
+        s = auart_port[co->index];
+        port = &s->port;
+        clk_enable(s->clk);
+        /* First save the CR then disable the interrupts */
+        old_ctrl2 = readl(port->membase + AUART_CTRL2);
+        old_ctrl0 = readl(port->membase + AUART_CTRL0);
+        writel(AUART_CTRL0_CLKGATE,
+                     port->membase + AUART_CTRL0_CLR);
+        writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
+                     port->membase + AUART_CTRL2_SET);
+        uart_console_write(port, str, count, mxs_auart_console_putchar);
+        /*
+         * Finally, wait for transmitter to become empty
+         * and restore the TCR
+         */
+        while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
+                if (!to--)
+                        break;
+                udelay(1);
+        }
+        writel(old_ctrl0, port->membase + AUART_CTRL0);
+        writel(old_ctrl2, port->membase + AUART_CTRL2);
+        clk_disable(s->clk);
+}
+static void __init
+auart_console_get_options(struct uart_port *port, int *baud,
+                          int *parity, int *bits)
+{
+        unsigned int lcr_h, quot;
+        if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
+                return;
+        lcr_h = readl(port->membase + AUART_LINECTRL);
+        *parity = 'n';
+        if (lcr_h & AUART_LINECTRL_PEN) {
+                if (lcr_h & AUART_LINECTRL_EPS)
+                        *parity = 'e';
+                else
+                        *parity = 'o';
+        }
+        if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
+                *bits = 7;
+        else
+                *bits = 8;
+        quot = ((readl(port->membase + AUART_LINECTRL)
+                        & AUART_LINECTRL_BAUD_DIVINT_MASK))
+                            >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
+        quot |= ((readl(port->membase + AUART_LINECTRL)
+                        & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
+                                >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
+        if (quot == 0)
+                quot = 1;
+        *baud = (port->uartclk << 2) / quot;
+}
+static int __init
+auart_console_setup(struct console *co, char *options)
+{
+        struct mxs_auart_port *s;
+        int baud = 9600;
+        int bits = 8;
+        int parity = 'n';
+        int flow = 'n';
+        int ret;
+        /*
+         * Check whether an invalid uart number has been specified, and
+         * if so, search for the first available port that does have
+         * console support.
+         */
+        if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
+                co->index = 0;
+        s = auart_port[co->index];
+        if (!s)
+                return -ENODEV;
+        clk_enable(s->clk);
+        if (options)
+                uart_parse_options(options, &baud, &parity, &bits, &flow);
+        else
+                auart_console_get_options(&s->port, &baud, &parity, &bits);
+        ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
+        clk_disable(s->clk);
+        return ret;
+}
+static struct console auart_console = {
+        .name           = "ttyAPP",
+        .write          = auart_console_write,
+        .device         = uart_console_device,
+        .setup          = auart_console_setup,
+        .flags          = CON_PRINTBUFFER,
+        .index          = -1,
+        .data           = &auart_driver,
+};
+#endif
+static struct uart_driver auart_driver = {
+        .owner          = THIS_MODULE,
+        .driver_name    = "ttyAPP",
+        .dev_name       = "ttyAPP",
+        .major          = 0,
+        .minor          = 0,
+        .nr             = MXS_AUART_PORTS,
+#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
+        .cons =         &auart_console,
+#endif
+};
+static int __devinit mxs_auart_probe(struct platform_device *pdev)
+{
+        struct mxs_auart_port *s;
+        u32 version;
+        int ret = 0;
+        struct resource *r;
+        s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
+        if (!s) {
+                ret = -ENOMEM;
+                goto out;
+        }
+        s->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(s->clk)) {
+                ret = PTR_ERR(s->clk);
+                goto out_free;
+        }
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!r) {
+                ret = -ENXIO;
+                goto out_free_clk;
+        }
+        s->port.mapbase = r->start;
+        s->port.membase = ioremap(r->start, resource_size(r));
+        s->port.ops = &mxs_auart_ops;
+        s->port.iotype = UPIO_MEM;
+        s->port.line = pdev->id < 0 ? 0 : pdev->id;
+        s->port.fifosize = 16;
+        s->port.uartclk = clk_get_rate(s->clk);
+        s->port.type = PORT_IMX;
+        s->port.dev = s->dev = get_device(&pdev->dev);
+        s->flags = 0;
+        s->ctrl = 0;
+        s->irq = platform_get_irq(pdev, 0);
+        s->port.irq = s->irq;
+        ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
+        if (ret)
+                goto out_free_clk;
+        platform_set_drvdata(pdev, s);
+        auart_port[pdev->id] = s;
+        mxs_auart_reset(&s->port);
+        ret = uart_add_one_port(&auart_driver, &s->port);
+        if (ret)
+                goto out_free_irq;
+        version = readl(s->port.membase + AUART_VERSION);
+        dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
+               (version >> 24) & 0xff,
+               (version >> 16) & 0xff, version & 0xffff);
+        return 0;
+out_free_irq:
+        auart_port[pdev->id] = NULL;
+        free_irq(s->irq, s);
+out_free_clk:
+        clk_put(s->clk);
+out_free:
+        kfree(s);
+out:
+        return ret;
+}
+static int __devexit mxs_auart_remove(struct platform_device *pdev)
+{
+        struct mxs_auart_port *s = platform_get_drvdata(pdev);
+        uart_remove_one_port(&auart_driver, &s->port);
+        auart_port[pdev->id] = NULL;
+        clk_put(s->clk);
+        free_irq(s->irq, s);
+        kfree(s);
+        return 0;
+}
+static struct platform_driver mxs_auart_driver = {
+        .probe = mxs_auart_probe,
+        .remove = __devexit_p(mxs_auart_remove),
+        .driver = {
+                .name = "mxs-auart",
+                .owner = THIS_MODULE,
+        },
+};
+static int __init mxs_auart_init(void)
+{
+        int r;
+        r = uart_register_driver(&auart_driver);
+        if (r)
+                goto out;
+        r = platform_driver_register(&mxs_auart_driver);
+        if (r)
+                goto out_err;
+        return 0;
+out_err:
+        uart_unregister_driver(&auart_driver);
+out:
+        return r;
+}
+static void __exit mxs_auart_exit(void)
+{
+        platform_driver_unregister(&mxs_auart_driver);
+        uart_unregister_driver(&auart_driver);
+}
+module_init(mxs_auart_init);
+module_exit(mxs_auart_exit);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Freescale MXS application uart driver");
diff --git a/drivers/tty/serial/serial_cs.c b/drivers/tty/serial/serial_cs.c
index 93760b2ea172..1ef4df9bf7e4 100644
--- a/drivers/tty/serial/serial_cs.c
+++ b/drivers/tty/serial/serial_cs.c
@@ -712,6 +712,7 @@ static struct pcmcia_device_id serial_ids[] = {
        PCMCIA_PFC_DEVICE_PROD_ID12(1, "Xircom", "CreditCard Ethernet+Modem II", 0x2e3ee845, 0xeca401bf),
        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0e01),
        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0a05),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0b05),
        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x1101),
        PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0104, 0x0070),
        PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0101, 0x0562),
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index d041c6826e43..0f299b7aad60 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -2681,17 +2681,13 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
        mutex_lock(&usb_address0_mutex);
-        if (!udev->config && oldspeed == USB_SPEED_SUPER) {
+        /* Reset the device; full speed may morph to high speed */
-                /* Don't reset USB 3.0 devices during an initial setup */
+        /* FIXME a USB 2.0 device may morph into SuperSpeed on reset. */
-                usb_set_device_state(udev, USB_STATE_DEFAULT);
+        retval = hub_port_reset(hub, port1, udev, delay);
-        } else {
+        if (retval < 0)         /* error or disconnect */
-                /* Reset the device; full speed may morph to high speed */
+                goto fail;
-                /* FIXME a USB 2.0 device may morph into SuperSpeed on reset. */
+        /* success, speed is known */
-                retval = hub_port_reset(hub, port1, udev, delay);
-                if (retval < 0)         /* error or disconnect */
-                        goto fail;
-                /* success, speed is known */
-        }
        retval = -ENODEV;
        if (oldspeed != USB_SPEED_UNKNOWN && oldspeed != udev->speed) {
diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c
index 44c595432d6f..81ce6a8e1d94 100644
--- a/drivers/usb/core/quirks.c
+++ b/drivers/usb/core/quirks.c
@@ -48,6 +48,10 @@ static const struct usb_device_id usb_quirk_list[] = {
        { USB_DEVICE(0x04b4, 0x0526), .driver_info =
                        USB_QUIRK_CONFIG_INTF_STRINGS },
+        /* Samsung Android phone modem - ID conflict with SPH-I500 */
+        { USB_DEVICE(0x04e8, 0x6601), .driver_info =
+                        USB_QUIRK_CONFIG_INTF_STRINGS },
        /* Roland SC-8820 */
        { USB_DEVICE(0x0582, 0x0007), .driver_info = USB_QUIRK_RESET_RESUME },
@@ -68,6 +72,10 @@ static const struct usb_device_id usb_quirk_list[] = {
        /* M-Systems Flash Disk Pioneers */
        { USB_DEVICE(0x08ec, 0x1000), .driver_info = USB_QUIRK_RESET_RESUME },
+        /* Keytouch QWERTY Panel keyboard */
+        { USB_DEVICE(0x0926, 0x3333), .driver_info =
+                        USB_QUIRK_CONFIG_INTF_STRINGS },
        /* X-Rite/Gretag-Macbeth Eye-One Pro display colorimeter */
        { USB_DEVICE(0x0971, 0x2000), .driver_info = USB_QUIRK_NO_SET_INTF },
diff --git a/drivers/usb/gadget/f_phonet.c b/drivers/usb/gadget/f_phonet.c
index 3c6e1a058745..5e1495097ec3 100644
--- a/drivers/usb/gadget/f_phonet.c
+++ b/drivers/usb/gadget/f_phonet.c
@@ -346,14 +346,19 @@ static void pn_rx_complete(struct usb_ep *ep, struct usb_request *req)
                if (unlikely(!skb))
                        break;
-                skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0,
-                                req->actual);
-                page = NULL;
-                if (req->actual < req->length) { /* Last fragment */
+                if (skb->len == 0) { /* First fragment */
                        skb->protocol = htons(ETH_P_PHONET);
                        skb_reset_mac_header(skb);
-                        pskb_pull(skb, 1);
+                        /* Can't use pskb_pull() on page in IRQ */
+                        memcpy(skb_put(skb, 1), page_address(page), 1);
+                }
+                skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
+                                skb->len == 0, req->actual);
+                page = NULL;
+                if (req->actual < req->length) { /* Last fragment */
                        skb->dev = dev;
                        dev->stats.rx_packets++;
                        dev->stats.rx_bytes += skb->len;
diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c
index 77b1eb577029..834fe945f9dd 100644
--- a/drivers/usb/gadget/fsl_mxc_udc.c
+++ b/drivers/usb/gadget/fsl_mxc_udc.c
@@ -88,7 +88,7 @@ eenahb:
 void fsl_udc_clk_finalize(struct platform_device *pdev)
 {
        struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
-#if defined(CONFIG_ARCH_MX35)
+#if defined(CONFIG_SOC_IMX35)
        unsigned int v;
        /* workaround ENGcm09152 for i.MX35 */
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index c8e360d7d975..25c8c10bb689 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -203,11 +203,6 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
                mdelay(10);
        }
-        /* setup specific usb hw */
-        ret = mxc_initialize_usb_hw(pdev->id, pdata->flags);
-        if (ret < 0)
-                goto err_init;
        ehci = hcd_to_ehci(hcd);
        /* EHCI registers start at offset 0x100 */
diff --git a/drivers/usb/host/ehci-xilinx-of.c b/drivers/usb/host/ehci-xilinx-of.c
index e8f4f36fdf0b..a6f21b891f68 100644
--- a/drivers/usb/host/ehci-xilinx-of.c
+++ b/drivers/usb/host/ehci-xilinx-of.c
@@ -29,6 +29,7 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/of_address.h>
 /**
 * ehci_xilinx_of_setup - Initialize the device for ehci_reset()
diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c
index fcbf4abbf381..0231814a97a5 100644
--- a/drivers/usb/host/xhci-dbg.c
+++ b/drivers/usb/host/xhci-dbg.c
@@ -169,9 +169,10 @@ static void xhci_print_ports(struct xhci_hcd *xhci)
        }
 }
-void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num)
+void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
 {
-        void *addr;
+        struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
+        void __iomem *addr;
        u32 temp;
        u64 temp_64;
@@ -449,7 +450,7 @@ char *xhci_get_slot_state(struct xhci_hcd *xhci,
        }
 }
-void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
+static void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
 {
        /* Fields are 32 bits wide, DMA addresses are in bytes */
        int field_size = 32 / 8;
@@ -488,7 +489,7 @@ void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
                dbg_rsvd64(xhci, (u64 *)slot_ctx, dma);
 }
-void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
+static void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
                     struct xhci_container_ctx *ctx,
                     unsigned int last_ep)
 {
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 1d0f45f0e7a6..a9534396e85b 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -307,7 +307,7 @@ struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 /***************** Streams structures manipulation *************************/
-void xhci_free_stream_ctx(struct xhci_hcd *xhci,
+static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
                unsigned int num_stream_ctxs,
                struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 {
@@ -335,7 +335,7 @@ void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 * The stream context array must be a power of 2, and can be as small as
 * 64 bytes or as large as 1MB.
 */
-struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
+static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
                unsigned int num_stream_ctxs, dma_addr_t *dma,
                gfp_t mem_flags)
 {
@@ -1900,11 +1900,11 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
        val &= DBOFF_MASK;
        xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
                        " from cap regs base addr\n", val);
-        xhci->dba = (void *) xhci->cap_regs + val;
+        xhci->dba = (void __iomem *) xhci->cap_regs + val;
        xhci_dbg_regs(xhci);
        xhci_print_run_regs(xhci);
        /* Set ir_set to interrupt register set 0 */
-        xhci->ir_set = (void *) xhci->run_regs->ir_set;
+        xhci->ir_set = &xhci->run_regs->ir_set[0];
        /*
         * Event ring setup: Allocate a normal ring, but also setup
@@ -1961,7 +1961,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
        /* Set the event ring dequeue address */
        xhci_set_hc_event_deq(xhci);
        xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
-        xhci_print_ir_set(xhci, xhci->ir_set, 0);
+        xhci_print_ir_set(xhci, 0);
        /*
         * XXX: Might need to set the Interrupter Moderation Register to
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 3e8211c1ce5a..3289bf4832c9 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -474,8 +474,11 @@ void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
        state->new_deq_seg = find_trb_seg(cur_td->start_seg,
                        dev->eps[ep_index].stopped_trb,
                        &state->new_cycle_state);
-        if (!state->new_deq_seg)
+        if (!state->new_deq_seg) {
-                BUG();
+                WARN_ON(1);
+                return;
+        }
        /* Dig out the cycle state saved by the xHC during the stop ep cmd */
        xhci_dbg(xhci, "Finding endpoint context\n");
        ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
@@ -486,8 +489,10 @@ void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
        state->new_deq_seg = find_trb_seg(state->new_deq_seg,
                        state->new_deq_ptr,
                        &state->new_cycle_state);
-        if (!state->new_deq_seg)
+        if (!state->new_deq_seg) {
-                BUG();
+                WARN_ON(1);
+                return;
+        }
        trb = &state->new_deq_ptr->generic;
        if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
@@ -2363,12 +2368,13 @@ static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
                /* Scatter gather list entries may cross 64KB boundaries */
                running_total = TRB_MAX_BUFF_SIZE -
-                        (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
+                        (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
+                running_total &= TRB_MAX_BUFF_SIZE - 1;
                if (running_total != 0)
                        num_trbs++;
                /* How many more 64KB chunks to transfer, how many more TRBs? */
-                while (running_total < sg_dma_len(sg)) {
+                while (running_total < sg_dma_len(sg) && running_total < temp) {
                        num_trbs++;
                        running_total += TRB_MAX_BUFF_SIZE;
                }
@@ -2394,11 +2400,11 @@ static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
 {
        if (num_trbs != 0)
-                dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
+                dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
                                "TRBs, %d left\n", __func__,
                                urb->ep->desc.bEndpointAddress, num_trbs);
        if (running_total != urb->transfer_buffer_length)
-                dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
+                dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
                                "queued %#x (%d), asked for %#x (%d)\n",
                                __func__,
                                urb->ep->desc.bEndpointAddress,
@@ -2533,8 +2539,7 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
        sg = urb->sg;
        addr = (u64) sg_dma_address(sg);
        this_sg_len = sg_dma_len(sg);
-        trb_buff_len = TRB_MAX_BUFF_SIZE -
+        trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
-                (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
        trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
        if (trb_buff_len > urb->transfer_buffer_length)
                trb_buff_len = urb->transfer_buffer_length;
@@ -2572,7 +2577,7 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
                                (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
                                (unsigned int) addr + trb_buff_len);
                if (TRB_MAX_BUFF_SIZE -
-                                (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
+                                (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
                        xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
                        xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
                                        (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
@@ -2616,7 +2621,7 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
                }
                trb_buff_len = TRB_MAX_BUFF_SIZE -
-                        (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
+                        (addr & (TRB_MAX_BUFF_SIZE - 1));
                trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
                if (running_total + trb_buff_len > urb->transfer_buffer_length)
                        trb_buff_len =
@@ -2656,7 +2661,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
        num_trbs = 0;
        /* How much data is (potentially) left before the 64KB boundary? */
        running_total = TRB_MAX_BUFF_SIZE -
-                (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
+                (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
+        running_total &= TRB_MAX_BUFF_SIZE - 1;
        /* If there's some data on this 64KB chunk, or we have to send a
         * zero-length transfer, we need at least one TRB
@@ -2700,8 +2706,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
        /* How much data is in the first TRB? */
        addr = (u64) urb->transfer_dma;
        trb_buff_len = TRB_MAX_BUFF_SIZE -
-                (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
+                (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
-        if (urb->transfer_buffer_length < trb_buff_len)
+        if (trb_buff_len > urb->transfer_buffer_length)
                trb_buff_len = urb->transfer_buffer_length;
        first_trb = true;
@@ -2879,8 +2885,8 @@ static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
        addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
        td_len = urb->iso_frame_desc[i].length;
-        running_total = TRB_MAX_BUFF_SIZE -
+        running_total = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
-                        (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
+        running_total &= TRB_MAX_BUFF_SIZE - 1;
        if (running_total != 0)
                num_trbs++;
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 34cf4e165877..2083fc2179b2 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -109,7 +109,7 @@ int xhci_halt(struct xhci_hcd *xhci)
 /*
 * Set the run bit and wait for the host to be running.
 */
-int xhci_start(struct xhci_hcd *xhci)
+static int xhci_start(struct xhci_hcd *xhci)
 {
        u32 temp;
        int ret;
@@ -329,7 +329,7 @@ int xhci_init(struct usb_hcd *hcd)
 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
-void xhci_event_ring_work(unsigned long arg)
+static void xhci_event_ring_work(unsigned long arg)
 {
        unsigned long flags;
        int temp;
@@ -473,7 +473,7 @@ int xhci_run(struct usb_hcd *hcd)
                        xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
        xhci_writel(xhci, ER_IRQ_ENABLE(temp),
                        &xhci->ir_set->irq_pending);
-        xhci_print_ir_set(xhci, xhci->ir_set, 0);
+        xhci_print_ir_set(xhci, 0);
        if (NUM_TEST_NOOPS > 0)
                doorbell = xhci_setup_one_noop(xhci);
@@ -528,7 +528,7 @@ void xhci_stop(struct usb_hcd *hcd)
        temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
        xhci_writel(xhci, ER_IRQ_DISABLE(temp),
                        &xhci->ir_set->irq_pending);
-        xhci_print_ir_set(xhci, xhci->ir_set, 0);
+        xhci_print_ir_set(xhci, 0);
        xhci_dbg(xhci, "cleaning up memory\n");
        xhci_mem_cleanup(xhci);
@@ -755,7 +755,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
                temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
                xhci_writel(xhci, ER_IRQ_DISABLE(temp),
                                &xhci->ir_set->irq_pending);
-                xhci_print_ir_set(xhci, xhci->ir_set, 0);
+                xhci_print_ir_set(xhci, 0);
                xhci_dbg(xhci, "cleaning up memory\n");
                xhci_mem_cleanup(xhci);
@@ -857,7 +857,7 @@ unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
 /* Returns 1 if the arguments are OK;
 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
 */
-int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
+static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
                struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
                const char *func) {
        struct xhci_hcd *xhci;
@@ -1693,7 +1693,7 @@ static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
        xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
 }
-void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
+static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
                unsigned int slot_id, unsigned int ep_index,
                struct xhci_dequeue_state *deq_state)
 {
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 7f236fd22015..7f127df6dd55 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1348,7 +1348,7 @@ static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
 }
 /* xHCI debugging */
-void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num);
+void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
 void xhci_print_registers(struct xhci_hcd *xhci);
 void xhci_dbg_regs(struct xhci_hcd *xhci);
 void xhci_print_run_regs(struct xhci_hcd *xhci);
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 54a8bd1047d6..c292d5c499e7 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -1864,6 +1864,7 @@ allocate_instance(struct device *dev,
        INIT_LIST_HEAD(&musb->out_bulk);
        hcd->uses_new_polling = 1;
+        hcd->has_tt = 1;
        musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
        musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index d74a8113ae74..e6400be8a0f8 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -488,6 +488,15 @@ struct musb {
        unsigned                set_address:1;
        unsigned                test_mode:1;
        unsigned                softconnect:1;
+        u8                      address;
+        u8                      test_mode_nr;
+        u16                     ackpend;                /* ep0 */
+        enum musb_g_ep0_state   ep0_state;
+        struct usb_gadget       g;                      /* the gadget */
+        struct usb_gadget_driver *gadget_driver;        /* its driver */
+#endif
        /*
         * FIXME: Remove this flag.
         *
@@ -501,14 +510,6 @@ struct musb {
         */
        unsigned                double_buffer_not_ok:1 __deprecated;
-        u8                      address;
-        u8                      test_mode_nr;
-        u16                     ackpend;                /* ep0 */
-        enum musb_g_ep0_state   ep0_state;
-        struct usb_gadget       g;                      /* the gadget */
-        struct usb_gadget_driver *gadget_driver;        /* its driver */
-#endif
        struct musb_hdrc_config *config;
 #ifdef MUSB_CONFIG_PROC_FS
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index a3f12333fc41..bc8badd16897 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -362,6 +362,7 @@ static int omap2430_musb_init(struct musb *musb)
 static int omap2430_musb_exit(struct musb *musb)
 {
+        del_timer_sync(&musb_idle_timer);
        omap2430_low_level_exit(musb);
        otg_put_transceiver(musb->xceiv);
diff --git a/drivers/usb/serial/sierra.c b/drivers/usb/serial/sierra.c
index 7481ff8a49e4..0457813eebee 100644
--- a/drivers/usb/serial/sierra.c
+++ b/drivers/usb/serial/sierra.c
@@ -301,6 +301,9 @@ static const struct usb_device_id id_table[] = {
        { USB_DEVICE(0x1199, 0x68A3),   /* Sierra Wireless Direct IP modems */
          .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist
        },
+        { USB_DEVICE(0x0f3d, 0x68A3),   /* Airprime/Sierra Wireless Direct IP modems */
+          .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist
+        },
       { USB_DEVICE(0x413C, 0x08133) }, /* Dell Computer Corp. Wireless 5720 VZW Mobile Broadband (EVDO Rev-A) Minicard GPS Port */
        { }
diff --git a/drivers/usb/serial/usb_wwan.c b/drivers/usb/serial/usb_wwan.c
index b004b2a485c3..9c014e2ecd68 100644
--- a/drivers/usb/serial/usb_wwan.c
+++ b/drivers/usb/serial/usb_wwan.c
@@ -295,12 +295,15 @@ static void usb_wwan_indat_callback(struct urb *urb)
                    __func__, status, endpoint);
        } else {
                tty = tty_port_tty_get(&port->port);
-                if (urb->actual_length) {
+                if (tty) {
-                        tty_insert_flip_string(tty, data, urb->actual_length);
+                        if (urb->actual_length) {
-                        tty_flip_buffer_push(tty);
+                                tty_insert_flip_string(tty, data,
-                } else
+                                                urb->actual_length);
-                        dbg("%s: empty read urb received", __func__);
+                                tty_flip_buffer_push(tty);
-                tty_kref_put(tty);
+                        } else
+                                dbg("%s: empty read urb received", __func__);
+                        tty_kref_put(tty);
+                }
                /* Resubmit urb so we continue receiving */
                if (status != -ESHUTDOWN) {
diff --git a/drivers/usb/serial/visor.c b/drivers/usb/serial/visor.c
index 15a5d89b7f39..1c11959a7d58 100644
--- a/drivers/usb/serial/visor.c
+++ b/drivers/usb/serial/visor.c
@@ -27,6 +27,7 @@
 #include <linux/uaccess.h>
 #include <linux/usb.h>
 #include <linux/usb/serial.h>
+#include <linux/usb/cdc.h>
 #include "visor.h"
 /*
@@ -479,6 +480,17 @@ static int visor_probe(struct usb_serial *serial,
        dbg("%s", __func__);
+        /*
+         * some Samsung Android phones in modem mode have the same ID
+         * as SPH-I500, but they are ACM devices, so dont bind to them
+         */
+        if (id->idVendor == SAMSUNG_VENDOR_ID &&
+                id->idProduct == SAMSUNG_SPH_I500_ID &&
+                serial->dev->descriptor.bDeviceClass == USB_CLASS_COMM &&
+                serial->dev->descriptor.bDeviceSubClass ==
+                        USB_CDC_SUBCLASS_ACM)
+                return -ENODEV;
        if (serial->dev->actconfig->desc.bConfigurationValue != 1) {
                dev_err(&serial->dev->dev, "active config #%d != 1 ??\n",
                        serial->dev->actconfig->desc.bConfigurationValue);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6bafb51bb437..e0ea23f07dd1 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2365,6 +2365,15 @@ config FB_JZ4740
        help
          Framebuffer support for the JZ4740 SoC.
+config FB_MXS
+        tristate "MXS LCD framebuffer support"
+        depends on FB && ARCH_MXS
+        select FB_CFB_FILLRECT
+        select FB_CFB_COPYAREA
+        select FB_CFB_IMAGEBLIT
+        help
+          Framebuffer support for the MXS SoC.
 source "drivers/video/omap/Kconfig"
 source "drivers/video/omap2/Kconfig"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 8c8fabdff9d0..9a096aebb855 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -153,6 +153,7 @@ obj-$(CONFIG_FB_BFIN_T350MCQB)	  += bfin-t350mcqb-fb.o
 obj-$(CONFIG_FB_BFIN_7393)        += bfin_adv7393fb.o
 obj-$(CONFIG_FB_MX3)              += mx3fb.o
 obj-$(CONFIG_FB_DA8XX)            += da8xx-fb.o
+obj-$(CONFIG_FB_MXS)              += mxsfb.o
 # the test framebuffer is last
 obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
diff --git a/drivers/video/backlight/ltv350qv.c b/drivers/video/backlight/ltv350qv.c
index 8010aaeb5adb..dd0e84a9bd2f 100644
--- a/drivers/video/backlight/ltv350qv.c
+++ b/drivers/video/backlight/ltv350qv.c
@@ -239,11 +239,15 @@ static int __devinit ltv350qv_probe(struct spi_device *spi)
        lcd->spi = spi;
        lcd->power = FB_BLANK_POWERDOWN;
        lcd->buffer = kzalloc(8, GFP_KERNEL);
+        if (!lcd->buffer) {
+                ret = -ENOMEM;
+                goto out_free_lcd;
+        }
        ld = lcd_device_register("ltv350qv", &spi->dev, lcd, &ltv_ops);
        if (IS_ERR(ld)) {
                ret = PTR_ERR(ld);
-                goto out_free_lcd;
+                goto out_free_buffer;
        }
        lcd->ld = ld;
@@ -257,6 +261,8 @@ static int __devinit ltv350qv_probe(struct spi_device *spi)
 out_unregister:
        lcd_device_unregister(ld);
+out_free_buffer:
+        kfree(lcd->buffer);
 out_free_lcd:
        kfree(lcd);
        return ret;
@@ -268,6 +274,7 @@ static int __devexit ltv350qv_remove(struct spi_device *spi)
        ltv350qv_power(lcd, FB_BLANK_POWERDOWN);
        lcd_device_unregister(lcd->ld);
+        kfree(lcd->buffer);
        kfree(lcd);
        return 0;
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
new file mode 100644
index 000000000000..7d0284882984
--- /dev/null
+++ b/drivers/video/mxsfb.c
@@ -0,0 +1,919 @@
+/*
+ * Copyright (C) 2010 Juergen Beisert, Pengutronix
+ *
+ * This code is based on:
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#define DRIVER_NAME "mxsfb"
+/**
+ * @file
+ * @brief LCDIF driver for i.MX23 and i.MX28
+ *
+ * The LCDIF support four modes of operation
+ * - MPU interface (to drive smart displays) -> not supported yet
+ * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
+ * - Dotclock interface (to drive LC displays with RGB data and sync signals)
+ * - DVI (to drive ITU-R BT656)  -> not supported yet
+ *
+ * This driver depends on a correct setup of the pins used for this purpose
+ * (platform specific).
+ *
+ * For the developer: Don't forget to set the data bus width to the display
+ * in the imx_fb_videomode structure. You will else end up with ugly colours.
+ * If you fight against jitter you can vary the clock delay. This is a feature
+ * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
+ * the required value in the imx_fb_videomode structure.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <mach/mxsfb.h>
+#define REG_SET 4
+#define REG_CLR 8
+#define LCDC_CTRL                       0x00
+#define LCDC_CTRL1                      0x10
+#define LCDC_V4_CTRL2                   0x20
+#define LCDC_V3_TRANSFER_COUNT          0x20
+#define LCDC_V4_TRANSFER_COUNT          0x30
+#define LCDC_V4_CUR_BUF                 0x40
+#define LCDC_V4_NEXT_BUF                0x50
+#define LCDC_V3_CUR_BUF                 0x30
+#define LCDC_V3_NEXT_BUF                0x40
+#define LCDC_TIMING                     0x60
+#define LCDC_VDCTRL0                    0x70
+#define LCDC_VDCTRL1                    0x80
+#define LCDC_VDCTRL2                    0x90
+#define LCDC_VDCTRL3                    0xa0
+#define LCDC_VDCTRL4                    0xb0
+#define LCDC_DVICTRL0                   0xc0
+#define LCDC_DVICTRL1                   0xd0
+#define LCDC_DVICTRL2                   0xe0
+#define LCDC_DVICTRL3                   0xf0
+#define LCDC_DVICTRL4                   0x100
+#define LCDC_V4_DATA                    0x180
+#define LCDC_V3_DATA                    0x1b0
+#define LCDC_V4_DEBUG0                  0x1d0
+#define LCDC_V3_DEBUG0                  0x1f0
+#define CTRL_SFTRST                     (1 << 31)
+#define CTRL_CLKGATE                    (1 << 30)
+#define CTRL_BYPASS_COUNT               (1 << 19)
+#define CTRL_VSYNC_MODE                 (1 << 18)
+#define CTRL_DOTCLK_MODE                (1 << 17)
+#define CTRL_DATA_SELECT                (1 << 16)
+#define CTRL_SET_BUS_WIDTH(x)           (((x) & 0x3) << 10)
+#define CTRL_GET_BUS_WIDTH(x)           (((x) >> 10) & 0x3)
+#define CTRL_SET_WORD_LENGTH(x)         (((x) & 0x3) << 8)
+#define CTRL_GET_WORD_LENGTH(x)         (((x) >> 8) & 0x3)
+#define CTRL_MASTER                     (1 << 5)
+#define CTRL_DF16                       (1 << 3)
+#define CTRL_DF18                       (1 << 2)
+#define CTRL_DF24                       (1 << 1)
+#define CTRL_RUN                        (1 << 0)
+#define CTRL1_FIFO_CLEAR                (1 << 21)
+#define CTRL1_SET_BYTE_PACKAGING(x)     (((x) & 0xf) << 16)
+#define CTRL1_GET_BYTE_PACKAGING(x)     (((x) >> 16) & 0xf)
+#define TRANSFER_COUNT_SET_VCOUNT(x)    (((x) & 0xffff) << 16)
+#define TRANSFER_COUNT_GET_VCOUNT(x)    (((x) >> 16) & 0xffff)
+#define TRANSFER_COUNT_SET_HCOUNT(x)    ((x) & 0xffff)
+#define TRANSFER_COUNT_GET_HCOUNT(x)    ((x) & 0xffff)
+#define VDCTRL0_ENABLE_PRESENT          (1 << 28)
+#define VDCTRL0_VSYNC_ACT_HIGH          (1 << 27)
+#define VDCTRL0_HSYNC_ACT_HIGH          (1 << 26)
+#define VDCTRL0_DOTCLK_ACT_FAILING      (1 << 25)
+#define VDCTRL0_ENABLE_ACT_HIGH         (1 << 24)
+#define VDCTRL0_VSYNC_PERIOD_UNIT       (1 << 21)
+#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT  (1 << 20)
+#define VDCTRL0_HALF_LINE               (1 << 19)
+#define VDCTRL0_HALF_LINE_MODE          (1 << 18)
+#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
+#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
+#define VDCTRL2_SET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
+#define VDCTRL2_GET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
+#define VDCTRL3_MUX_SYNC_SIGNALS        (1 << 29)
+#define VDCTRL3_VSYNC_ONLY              (1 << 28)
+#define SET_HOR_WAIT_CNT(x)             (((x) & 0xfff) << 16)
+#define GET_HOR_WAIT_CNT(x)             (((x) >> 16) & 0xfff)
+#define SET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
+#define GET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
+#define VDCTRL4_SET_DOTCLK_DLY(x)       (((x) & 0x7) << 29) /* v4 only */
+#define VDCTRL4_GET_DOTCLK_DLY(x)       (((x) >> 29) & 0x7) /* v4 only */
+#define VDCTRL4_SYNC_SIGNALS_ON         (1 << 18)
+#define SET_DOTCLK_H_VALID_DATA_CNT(x)  ((x) & 0x3ffff)
+#define DEBUG0_HSYNC                    (1 < 26)
+#define DEBUG0_VSYNC                    (1 < 25)
+#define MIN_XRES                        120
+#define MIN_YRES                        120
+#define RED 0
+#define GREEN 1
+#define BLUE 2
+#define TRANSP 3
+enum mxsfb_devtype {
+        MXSFB_V3,
+        MXSFB_V4,
+};
+/* CPU dependent register offsets */
+struct mxsfb_devdata {
+        unsigned transfer_count;
+        unsigned cur_buf;
+        unsigned next_buf;
+        unsigned debug0;
+        unsigned hs_wdth_mask;
+        unsigned hs_wdth_shift;
+        unsigned ipversion;
+};
+struct mxsfb_info {
+        struct fb_info fb_info;
+        struct platform_device *pdev;
+        struct clk *clk;
+        void __iomem *base;     /* registers */
+        unsigned allocated_size;
+        int enabled;
+        unsigned ld_intf_width;
+        unsigned dotclk_delay;
+        const struct mxsfb_devdata *devdata;
+        int mapped;
+};
+#define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
+#define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
+static const struct mxsfb_devdata mxsfb_devdata[] = {
+        [MXSFB_V3] = {
+                .transfer_count = LCDC_V3_TRANSFER_COUNT,
+                .cur_buf = LCDC_V3_CUR_BUF,
+                .next_buf = LCDC_V3_NEXT_BUF,
+                .debug0 = LCDC_V3_DEBUG0,
+                .hs_wdth_mask = 0xff,
+                .hs_wdth_shift = 24,
+                .ipversion = 3,
+        },
+        [MXSFB_V4] = {
+                .transfer_count = LCDC_V4_TRANSFER_COUNT,
+                .cur_buf = LCDC_V4_CUR_BUF,
+                .next_buf = LCDC_V4_NEXT_BUF,
+                .debug0 = LCDC_V4_DEBUG0,
+                .hs_wdth_mask = 0x3fff,
+                .hs_wdth_shift = 18,
+                .ipversion = 4,
+        },
+};
+#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
+/* mask and shift depends on architecture */
+static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
+{
+        return (val & host->devdata->hs_wdth_mask) <<
+                host->devdata->hs_wdth_shift;
+}
+static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
+{
+        return (val >> host->devdata->hs_wdth_shift) &
+                host->devdata->hs_wdth_mask;
+}
+static const struct fb_bitfield def_rgb565[] = {
+        [RED] = {
+                .offset = 11,
+                .length = 5,
+        },
+        [GREEN] = {
+                .offset = 5,
+                .length = 6,
+        },
+        [BLUE] = {
+                .offset = 0,
+                .length = 5,
+        },
+        [TRANSP] = {    /* no support for transparency */
+                .length = 0,
+        }
+};
+static const struct fb_bitfield def_rgb666[] = {
+        [RED] = {
+                .offset = 16,
+                .length = 6,
+        },
+        [GREEN] = {
+                .offset = 8,
+                .length = 6,
+        },
+        [BLUE] = {
+                .offset = 0,
+                .length = 6,
+        },
+        [TRANSP] = {    /* no support for transparency */
+                .length = 0,
+        }
+};
+static const struct fb_bitfield def_rgb888[] = {
+        [RED] = {
+                .offset = 16,
+                .length = 8,
+        },
+        [GREEN] = {
+                .offset = 8,
+                .length = 8,
+        },
+        [BLUE] = {
+                .offset = 0,
+                .length = 8,
+        },
+        [TRANSP] = {    /* no support for transparency */
+                .length = 0,
+        }
+};
+static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
+{
+        chan &= 0xffff;
+        chan >>= 16 - bf->length;
+        return chan << bf->offset;
+}
+static int mxsfb_check_var(struct fb_var_screeninfo *var,
+                struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        const struct fb_bitfield *rgb = NULL;
+        if (var->xres < MIN_XRES)
+                var->xres = MIN_XRES;
+        if (var->yres < MIN_YRES)
+                var->yres = MIN_YRES;
+        var->xres_virtual = var->xres;
+        var->yres_virtual = var->yres;
+        switch (var->bits_per_pixel) {
+        case 16:
+                /* always expect RGB 565 */
+                rgb = def_rgb565;
+                break;
+        case 32:
+                switch (host->ld_intf_width) {
+                case STMLCDIF_8BIT:
+                        pr_debug("Unsupported LCD bus width mapping\n");
+                        break;
+                case STMLCDIF_16BIT:
+                case STMLCDIF_18BIT:
+                        /* 24 bit to 18 bit mapping */
+                        rgb = def_rgb666;
+                        break;
+                case STMLCDIF_24BIT:
+                        /* real 24 bit */
+                        rgb = def_rgb888;
+                        break;
+                }
+                break;
+        default:
+                pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel);
+                return -EINVAL;
+        }
+        /*
+         * Copy the RGB parameters for this display
+         * from the machine specific parameters.
+         */
+        var->red    = rgb[RED];
+        var->green  = rgb[GREEN];
+        var->blue   = rgb[BLUE];
+        var->transp = rgb[TRANSP];
+        return 0;
+}
+static void mxsfb_enable_controller(struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        u32 reg;
+        dev_dbg(&host->pdev->dev, "%s\n", __func__);
+        clk_enable(host->clk);
+        clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
+        /* if it was disabled, re-enable the mode again */
+        writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
+        /* enable the SYNC signals first, then the DMA engine */
+        reg = readl(host->base + LCDC_VDCTRL4);
+        reg |= VDCTRL4_SYNC_SIGNALS_ON;
+        writel(reg, host->base + LCDC_VDCTRL4);
+        writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
+        host->enabled = 1;
+}
+static void mxsfb_disable_controller(struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        unsigned loop;
+        u32 reg;
+        dev_dbg(&host->pdev->dev, "%s\n", __func__);
+        /*
+         * Even if we disable the controller here, it will still continue
+         * until its FIFOs are running out of data
+         */
+        writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
+        loop = 1000;
+        while (loop) {
+                reg = readl(host->base + LCDC_CTRL);
+                if (!(reg & CTRL_RUN))
+                        break;
+                loop--;
+        }
+        writel(VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4 + REG_CLR);
+        clk_disable(host->clk);
+        host->enabled = 0;
+}
+static int mxsfb_set_par(struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        u32 ctrl, vdctrl0, vdctrl4;
+        int line_size, fb_size;
+        int reenable = 0;
+        line_size =  fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
+        fb_size = fb_info->var.yres_virtual * line_size;
+        if (fb_size > fb_info->fix.smem_len)
+                return -ENOMEM;
+        fb_info->fix.line_length = line_size;
+        /*
+         * It seems, you can't re-program the controller if it is still running.
+         * This may lead into shifted pictures (FIFO issue?).
+         * So, first stop the controller and drain its FIFOs
+         */
+        if (host->enabled) {
+                reenable = 1;
+                mxsfb_disable_controller(fb_info);
+        }
+        /* clear the FIFOs */
+        writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
+        ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
+                CTRL_SET_BUS_WIDTH(host->ld_intf_width);;
+        switch (fb_info->var.bits_per_pixel) {
+        case 16:
+                dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
+                ctrl |= CTRL_SET_WORD_LENGTH(0);
+                writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
+                break;
+        case 32:
+                dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
+                ctrl |= CTRL_SET_WORD_LENGTH(3);
+                switch (host->ld_intf_width) {
+                case STMLCDIF_8BIT:
+                        dev_dbg(&host->pdev->dev,
+                                        "Unsupported LCD bus width mapping\n");
+                        return -EINVAL;
+                case STMLCDIF_16BIT:
+                case STMLCDIF_18BIT:
+                        /* 24 bit to 18 bit mapping */
+                        ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
+                                            *  each colour component
+                                            */
+                        break;
+                case STMLCDIF_24BIT:
+                        /* real 24 bit */
+                        break;
+                }
+                /* do not use packed pixels = one pixel per word instead */
+                writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
+                break;
+        default:
+                dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n",
+                                fb_info->var.bits_per_pixel);
+                return -EINVAL;
+        }
+        writel(ctrl, host->base + LCDC_CTRL);
+        writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
+                        TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
+                        host->base + host->devdata->transfer_count);
+        vdctrl0 = VDCTRL0_ENABLE_PRESENT |      /* always in DOTCLOCK mode */
+                VDCTRL0_VSYNC_PERIOD_UNIT |
+                VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
+                VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
+        if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
+                vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
+        if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
+                vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
+        if (fb_info->var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT)
+                vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
+        if (fb_info->var.sync & FB_SYNC_DOTCLK_FAILING_ACT)
+                vdctrl0 |= VDCTRL0_DOTCLK_ACT_FAILING;
+        writel(vdctrl0, host->base + LCDC_VDCTRL0);
+        /* frame length in lines */
+        writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
+                fb_info->var.lower_margin + fb_info->var.yres,
+                host->base + LCDC_VDCTRL1);
+        /* line length in units of clocks or pixels */
+        writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
+                VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
+                fb_info->var.hsync_len + fb_info->var.right_margin +
+                fb_info->var.xres),
+                host->base + LCDC_VDCTRL2);
+        writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
+                fb_info->var.hsync_len) |
+                SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
+                        fb_info->var.vsync_len),
+                host->base + LCDC_VDCTRL3);
+        vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
+        if (mxsfb_is_v4(host))
+                vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
+        writel(vdctrl4, host->base + LCDC_VDCTRL4);
+        writel(fb_info->fix.smem_start +
+                        fb_info->fix.line_length * fb_info->var.yoffset,
+                        host->base + host->devdata->next_buf);
+        if (reenable)
+                mxsfb_enable_controller(fb_info);
+        return 0;
+}
+static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+                u_int transp, struct fb_info *fb_info)
+{
+        unsigned int val;
+        int ret = -EINVAL;
+        /*
+         * If greyscale is true, then we convert the RGB value
+         * to greyscale no matter what visual we are using.
+         */
+        if (fb_info->var.grayscale)
+                red = green = blue = (19595 * red + 38470 * green +
+                                        7471 * blue) >> 16;
+        switch (fb_info->fix.visual) {
+        case FB_VISUAL_TRUECOLOR:
+                /*
+                 * 12 or 16-bit True Colour.  We encode the RGB value
+                 * according to the RGB bitfield information.
+                 */
+                if (regno < 16) {
+                        u32 *pal = fb_info->pseudo_palette;
+                        val  = chan_to_field(red, &fb_info->var.red);
+                        val |= chan_to_field(green, &fb_info->var.green);
+                        val |= chan_to_field(blue, &fb_info->var.blue);
+                        pal[regno] = val;
+                        ret = 0;
+                }
+                break;
+        case FB_VISUAL_STATIC_PSEUDOCOLOR:
+        case FB_VISUAL_PSEUDOCOLOR:
+                break;
+        }
+        return ret;
+}
+static int mxsfb_blank(int blank, struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        switch (blank) {
+        case FB_BLANK_POWERDOWN:
+        case FB_BLANK_VSYNC_SUSPEND:
+        case FB_BLANK_HSYNC_SUSPEND:
+        case FB_BLANK_NORMAL:
+                if (host->enabled)
+                        mxsfb_disable_controller(fb_info);
+                break;
+        case FB_BLANK_UNBLANK:
+                if (!host->enabled)
+                        mxsfb_enable_controller(fb_info);
+                break;
+        }
+        return 0;
+}
+static int mxsfb_pan_display(struct fb_var_screeninfo *var,
+                struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        unsigned offset;
+        if (var->xoffset != 0)
+                return -EINVAL;
+        offset = fb_info->fix.line_length * var->yoffset;
+        /* update on next VSYNC */
+        writel(fb_info->fix.smem_start + offset,
+                        host->base + host->devdata->next_buf);
+        return 0;
+}
+static struct fb_ops mxsfb_ops = {
+        .owner = THIS_MODULE,
+        .fb_check_var = mxsfb_check_var,
+        .fb_set_par = mxsfb_set_par,
+        .fb_setcolreg = mxsfb_setcolreg,
+        .fb_blank = mxsfb_blank,
+        .fb_pan_display = mxsfb_pan_display,
+        .fb_fillrect = cfb_fillrect,
+        .fb_copyarea = cfb_copyarea,
+        .fb_imageblit = cfb_imageblit,
+};
+static int __devinit mxsfb_restore_mode(struct mxsfb_info *host)
+{
+        struct fb_info *fb_info = &host->fb_info;
+        unsigned line_count;
+        unsigned period;
+        unsigned long pa, fbsize;
+        int bits_per_pixel, ofs;
+        u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
+        struct fb_videomode vmode;
+        /* Only restore the mode when the controller is running */
+        ctrl = readl(host->base + LCDC_CTRL);
+        if (!(ctrl & CTRL_RUN))
+                return -EINVAL;
+        vdctrl0 = readl(host->base + LCDC_VDCTRL0);
+        vdctrl2 = readl(host->base + LCDC_VDCTRL2);
+        vdctrl3 = readl(host->base + LCDC_VDCTRL3);
+        vdctrl4 = readl(host->base + LCDC_VDCTRL4);
+        transfer_count = readl(host->base + host->devdata->transfer_count);
+        vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
+        vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
+        switch (CTRL_GET_WORD_LENGTH(ctrl)) {
+        case 0:
+                bits_per_pixel = 16;
+                break;
+        case 3:
+                bits_per_pixel = 32;
+        case 1:
+        default:
+                return -EINVAL;
+        }
+        fb_info->var.bits_per_pixel = bits_per_pixel;
+        vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
+        vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2);
+        vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len;
+        vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len -
+                vmode.left_margin - vmode.xres;
+        vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
+        period = readl(host->base + LCDC_VDCTRL1);
+        vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len;
+        vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres;
+        vmode.vmode = FB_VMODE_NONINTERLACED;
+        vmode.sync = 0;
+        if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
+                vmode.sync |= FB_SYNC_HOR_HIGH_ACT;
+        if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
+                vmode.sync |= FB_SYNC_VERT_HIGH_ACT;
+        pr_debug("Reconstructed video mode:\n");
+        pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
+                        vmode.xres, vmode.yres,
+                        vmode.hsync_len, vmode.left_margin, vmode.right_margin,
+                        vmode.vsync_len, vmode.upper_margin, vmode.lower_margin);
+        pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock));
+        fb_add_videomode(&vmode, &fb_info->modelist);
+        host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
+        host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
+        fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3);
+        pa = readl(host->base + host->devdata->cur_buf);
+        fbsize = fb_info->fix.line_length * vmode.yres;
+        if (pa < fb_info->fix.smem_start)
+                return -EINVAL;
+        if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len)
+                return -EINVAL;
+        ofs = pa - fb_info->fix.smem_start;
+        if (ofs) {
+                memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
+                writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
+        }
+        line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
+        fb_info->fix.ypanstep = 1;
+        clk_enable(host->clk);
+        host->enabled = 1;
+        return 0;
+}
+static int __devinit mxsfb_init_fbinfo(struct mxsfb_info *host)
+{
+        struct fb_info *fb_info = &host->fb_info;
+        struct fb_var_screeninfo *var = &fb_info->var;
+        struct mxsfb_platform_data *pdata = host->pdev->dev.platform_data;
+        dma_addr_t fb_phys;
+        void *fb_virt;
+        unsigned fb_size = pdata->fb_size;
+        fb_info->fbops = &mxsfb_ops;
+        fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
+        strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
+        fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
+        fb_info->fix.ypanstep = 1;
+        fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
+        fb_info->fix.accel = FB_ACCEL_NONE;
+        var->bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16;
+        var->nonstd = 0;
+        var->activate = FB_ACTIVATE_NOW;
+        var->accel_flags = 0;
+        var->vmode = FB_VMODE_NONINTERLACED;
+        host->dotclk_delay = pdata->dotclk_delay;
+        host->ld_intf_width = pdata->ld_intf_width;
+        /* Memory allocation for framebuffer */
+        if (pdata->fb_phys) {
+                if (!fb_size)
+                        return -EINVAL;
+                fb_phys = pdata->fb_phys;
+                if (!request_mem_region(fb_phys, fb_size, host->pdev->name))
+                        return -ENOMEM;
+                fb_virt = ioremap(fb_phys, fb_size);
+                if (!fb_virt) {
+                        release_mem_region(fb_phys, fb_size);
+                        return -ENOMEM;
+                }
+                host->mapped = 1;
+        } else {
+                if (!fb_size)
+                        fb_size = SZ_2M; /* default */
+                fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
+                if (!fb_virt)
+                        return -ENOMEM;
+                fb_phys = virt_to_phys(fb_virt);
+        }
+        fb_info->fix.smem_start = fb_phys;
+        fb_info->screen_base = fb_virt;
+        fb_info->screen_size = fb_info->fix.smem_len = fb_size;
+        if (mxsfb_restore_mode(host))
+                memset(fb_virt, 0, fb_size);
+        return 0;
+}
+static void __devexit mxsfb_free_videomem(struct mxsfb_info *host)
+{
+        struct fb_info *fb_info = &host->fb_info;
+        if (host->mapped) {
+                iounmap(fb_info->screen_base);
+                release_mem_region(fb_info->fix.smem_start,
+                                fb_info->screen_size);
+        } else {
+                free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
+        }
+}
+static int __devinit mxsfb_probe(struct platform_device *pdev)
+{
+        struct mxsfb_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *res;
+        struct mxsfb_info *host;
+        struct fb_info *fb_info;
+        struct fb_modelist *modelist;
+        int i, ret;
+        if (!pdata) {
+                dev_err(&pdev->dev, "No platformdata. Giving up\n");
+                return -ENODEV;
+        }
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "Cannot get memory IO resource\n");
+                return -ENODEV;
+        }
+        if (!request_mem_region(res->start, resource_size(res), pdev->name))
+                return -EBUSY;
+        fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
+        if (!fb_info) {
+                dev_err(&pdev->dev, "Failed to allocate fbdev\n");
+                ret = -ENOMEM;
+                goto error_alloc_info;
+        }
+        host = to_imxfb_host(fb_info);
+        host->base = ioremap(res->start, resource_size(res));
+        if (!host->base) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto error_ioremap;
+        }
+        host->pdev = pdev;
+        platform_set_drvdata(pdev, host);
+        host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
+        host->clk = clk_get(&host->pdev->dev, NULL);
+        if (IS_ERR(host->clk)) {
+                ret = PTR_ERR(host->clk);
+                goto error_getclock;
+        }
+        fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
+        if (!fb_info->pseudo_palette) {
+                ret = -ENOMEM;
+                goto error_pseudo_pallette;
+        }
+        INIT_LIST_HEAD(&fb_info->modelist);
+        ret = mxsfb_init_fbinfo(host);
+        if (ret != 0)
+                goto error_init_fb;
+        for (i = 0; i < pdata->mode_count; i++)
+                fb_add_videomode(&pdata->mode_list[i], &fb_info->modelist);
+        modelist = list_first_entry(&fb_info->modelist,
+                        struct fb_modelist, list);
+        fb_videomode_to_var(&fb_info->var, &modelist->mode);
+        /* init the color fields */
+        mxsfb_check_var(&fb_info->var, fb_info);
+        platform_set_drvdata(pdev, fb_info);
+        ret = register_framebuffer(fb_info);
+        if (ret != 0) {
+                dev_err(&pdev->dev,"Failed to register framebuffer\n");
+                goto error_register;
+        }
+        if (!host->enabled) {
+                writel(0, host->base + LCDC_CTRL);
+                mxsfb_set_par(fb_info);
+                mxsfb_enable_controller(fb_info);
+        }
+        dev_info(&pdev->dev, "initialized\n");
+        return 0;
+error_register:
+        if (host->enabled)
+                clk_disable(host->clk);
+        fb_destroy_modelist(&fb_info->modelist);
+error_init_fb:
+        kfree(fb_info->pseudo_palette);
+error_pseudo_pallette:
+        clk_put(host->clk);
+error_getclock:
+        iounmap(host->base);
+error_ioremap:
+        framebuffer_release(fb_info);
+error_alloc_info:
+        release_mem_region(res->start, resource_size(res));
+        return ret;
+}
+static int __devexit mxsfb_remove(struct platform_device *pdev)
+{
+        struct fb_info *fb_info = platform_get_drvdata(pdev);
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (host->enabled)
+                mxsfb_disable_controller(fb_info);
+        unregister_framebuffer(fb_info);
+        kfree(fb_info->pseudo_palette);
+        mxsfb_free_videomem(host);
+        iounmap(host->base);
+        clk_put(host->clk);
+        framebuffer_release(fb_info);
+        release_mem_region(res->start, resource_size(res));
+        platform_set_drvdata(pdev, NULL);
+        return 0;
+}
+static struct platform_device_id mxsfb_devtype[] = {
+        {
+                .name = "imx23-fb",
+                .driver_data = MXSFB_V3,
+        }, {
+                .name = "imx28-fb",
+                .driver_data = MXSFB_V4,
+        }, {
+                /* sentinel */
+        }
+};
+MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
+static struct platform_driver mxsfb_driver = {
+        .probe = mxsfb_probe,
+        .remove = __devexit_p(mxsfb_remove),
+        .id_table = mxsfb_devtype,
+        .driver = {
+                   .name = DRIVER_NAME,
+        },
+};
+static int __init mxsfb_init(void)
+{
+        return platform_driver_register(&mxsfb_driver);
+}
+static void __exit mxsfb_exit(void)
+{
+        platform_driver_unregister(&mxsfb_driver);
+}
+module_init(mxsfb_init);
+module_exit(mxsfb_exit);
+MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
+MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+MODULE_LICENSE("GPL");
diff --git a/fs/afs/write.c b/fs/afs/write.c
index 15690bb1d3b5..789b3afb3423 100644
--- a/fs/afs/write.c
+++ b/fs/afs/write.c
@@ -140,6 +140,7 @@ int afs_write_begin(struct file *file, struct address_space *mapping,
        candidate->first = candidate->last = index;
        candidate->offset_first = from;
        candidate->to_last = to;
+        INIT_LIST_HEAD(&candidate->link);
        candidate->usage = 1;
        candidate->state = AFS_WBACK_PENDING;
        init_waitqueue_head(&candidate->waitq);
diff --git a/fs/aio.c b/fs/aio.c
index fc557a3be0a9..26869cde3953 100644
--- a/fs/aio.c
+++ b/fs/aio.c
@@ -239,15 +239,23 @@ static void __put_ioctx(struct kioctx *ctx)
        call_rcu(&ctx->rcu_head, ctx_rcu_free);
 }
-#define get_ioctx(kioctx) do {                                          \
+static inline void get_ioctx(struct kioctx *kioctx)
-        BUG_ON(atomic_read(&(kioctx)->users) <= 0);                     \
+{
-        atomic_inc(&(kioctx)->users);                                   \
+        BUG_ON(atomic_read(&kioctx->users) <= 0);
-} while (0)
+        atomic_inc(&kioctx->users);
-#define put_ioctx(kioctx) do {                                          \
+}
-        BUG_ON(atomic_read(&(kioctx)->users) <= 0);                     \
-        if (unlikely(atomic_dec_and_test(&(kioctx)->users)))            \
+static inline int try_get_ioctx(struct kioctx *kioctx)
-                __put_ioctx(kioctx);                                    \
+{
-} while (0)
+        return atomic_inc_not_zero(&kioctx->users);
+}
+static inline void put_ioctx(struct kioctx *kioctx)
+{
+        BUG_ON(atomic_read(&kioctx->users) <= 0);
+        if (unlikely(atomic_dec_and_test(&kioctx->users)))
+                __put_ioctx(kioctx);
+}
 /* ioctx_alloc
 *      Allocates and initializes an ioctx.  Returns an ERR_PTR if it failed.
@@ -601,8 +609,13 @@ static struct kioctx *lookup_ioctx(unsigned long ctx_id)
        rcu_read_lock();
        hlist_for_each_entry_rcu(ctx, n, &mm->ioctx_list, list) {
-                if (ctx->user_id == ctx_id && !ctx->dead) {
+                /*
-                        get_ioctx(ctx);
+                 * RCU protects us against accessing freed memory but
+                 * we have to be careful not to get a reference when the
+                 * reference count already dropped to 0 (ctx->dead test
+                 * is unreliable because of races).
+                 */
+                if (ctx->user_id == ctx_id && !ctx->dead && try_get_ioctx(ctx)){
                        ret = ctx;
                        break;
                }
@@ -1629,6 +1642,23 @@ static int io_submit_one(struct kioctx *ctx, struct iocb __user *user_iocb,
                goto out_put_req;
        spin_lock_irq(&ctx->ctx_lock);
+        /*
+         * We could have raced with io_destroy() and are currently holding a
+         * reference to ctx which should be destroyed. We cannot submit IO
+         * since ctx gets freed as soon as io_submit() puts its reference.  The
+         * check here is reliable: io_destroy() sets ctx->dead before waiting
+         * for outstanding IO and the barrier between these two is realized by
+         * unlock of mm->ioctx_lock and lock of ctx->ctx_lock.  Analogously we
+         * increment ctx->reqs_active before checking for ctx->dead and the
+         * barrier is realized by unlock and lock of ctx->ctx_lock. Thus if we
+         * don't see ctx->dead set here, io_destroy() waits for our IO to
+         * finish.
+         */
+        if (ctx->dead) {
+                spin_unlock_irq(&ctx->ctx_lock);
+                ret = -EINVAL;
+                goto out_put_req;
+        }
        aio_run_iocb(req);
        if (!list_empty(&ctx->run_list)) {
                /* drain the run list */
diff --git a/fs/block_dev.c b/fs/block_dev.c
index 4fb8a3431531..889287019599 100644
--- a/fs/block_dev.c
+++ b/fs/block_dev.c
@@ -873,6 +873,11 @@ int bd_link_disk_holder(struct block_device *bdev, struct gendisk *disk)
        ret = add_symlink(bdev->bd_part->holder_dir, &disk_to_dev(disk)->kobj);
        if (ret)
                goto out_del;
+        /*
+         * bdev could be deleted beneath us which would implicitly destroy
+         * the holder directory.  Hold on to it.
+         */
+        kobject_get(bdev->bd_part->holder_dir);
        list_add(&holder->list, &bdev->bd_holder_disks);
        goto out_unlock;
@@ -909,6 +914,7 @@ void bd_unlink_disk_holder(struct block_device *bdev, struct gendisk *disk)
                del_symlink(disk->slave_dir, &part_to_dev(bdev->bd_part)->kobj);
                del_symlink(bdev->bd_part->holder_dir,
                            &disk_to_dev(disk)->kobj);
+                kobject_put(bdev->bd_part->holder_dir);
                list_del_init(&holder->list);
                kfree(holder);
        }
@@ -922,14 +928,15 @@ EXPORT_SYMBOL_GPL(bd_unlink_disk_holder);
 * flush_disk - invalidates all buffer-cache entries on a disk
 *
 * @bdev:      struct block device to be flushed
+ * @kill_dirty: flag to guide handling of dirty inodes
 *
 * Invalidates all buffer-cache entries on a disk. It should be called
 * when a disk has been changed -- either by a media change or online
 * resize.
 */
-static void flush_disk(struct block_device *bdev)
+static void flush_disk(struct block_device *bdev, bool kill_dirty)
 {
-        if (__invalidate_device(bdev)) {
+        if (__invalidate_device(bdev, kill_dirty)) {
                char name[BDEVNAME_SIZE] = "";
                if (bdev->bd_disk)
@@ -966,7 +973,7 @@ void check_disk_size_change(struct gendisk *disk, struct block_device *bdev)
                       "%s: detected capacity change from %lld to %lld\n",
                       name, bdev_size, disk_size);
                i_size_write(bdev->bd_inode, disk_size);
-                flush_disk(bdev);
+                flush_disk(bdev, false);
        }
 }
 EXPORT_SYMBOL(check_disk_size_change);
@@ -1019,7 +1026,7 @@ int check_disk_change(struct block_device *bdev)
        if (!(events & DISK_EVENT_MEDIA_CHANGE))
                return 0;
-        flush_disk(bdev);
+        flush_disk(bdev, true);
        if (bdops->revalidate_disk)
                bdops->revalidate_disk(bdev->bd_disk);
        return 1;
@@ -1600,7 +1607,7 @@ fail:
 }
 EXPORT_SYMBOL(lookup_bdev);
-int __invalidate_device(struct block_device *bdev)
+int __invalidate_device(struct block_device *bdev, bool kill_dirty)
 {
        struct super_block *sb = get_super(bdev);
        int res = 0;
@@ -1613,7 +1620,7 @@ int __invalidate_device(struct block_device *bdev)
                 * hold).
                 */
                shrink_dcache_sb(sb);
-                res = invalidate_inodes(sb);
+                res = invalidate_inodes(sb, kill_dirty);
                drop_super(sb);
        }
        invalidate_bdev(bdev);
diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h
index 2c98b3af6052..6f820fa23df4 100644
--- a/fs/btrfs/ctree.h
+++ b/fs/btrfs/ctree.h
@@ -1254,6 +1254,7 @@ struct btrfs_root {
 #define BTRFS_MOUNT_SPACE_CACHE         (1 << 12)
 #define BTRFS_MOUNT_CLEAR_CACHE         (1 << 13)
 #define BTRFS_MOUNT_USER_SUBVOL_RM_ALLOWED (1 << 14)
+#define BTRFS_MOUNT_ENOSPC_DEBUG         (1 << 15)
 #define btrfs_clear_opt(o, opt)         ((o) &= ~BTRFS_MOUNT_##opt)
 #define btrfs_set_opt(o, opt)           ((o) |= BTRFS_MOUNT_##opt)
@@ -2218,6 +2219,8 @@ int btrfs_error_unpin_extent_range(struct btrfs_root *root,
                                   u64 start, u64 end);
 int btrfs_error_discard_extent(struct btrfs_root *root, u64 bytenr,
                               u64 num_bytes);
+int btrfs_force_chunk_alloc(struct btrfs_trans_handle *trans,
+                            struct btrfs_root *root, u64 type);
 /* ctree.c */
 int btrfs_bin_search(struct extent_buffer *eb, struct btrfs_key *key,
diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c
index f3c96fc01439..588ff9849873 100644
--- a/fs/btrfs/extent-tree.c
+++ b/fs/btrfs/extent-tree.c
@@ -5376,7 +5376,7 @@ again:
                               num_bytes, data, 1);
                goto again;
        }
-        if (ret == -ENOSPC) {
+        if (ret == -ENOSPC && btrfs_test_opt(root, ENOSPC_DEBUG)) {
                struct btrfs_space_info *sinfo;
                sinfo = __find_space_info(root->fs_info, data);
@@ -8065,6 +8065,13 @@ out:
        return ret;
 }
+int btrfs_force_chunk_alloc(struct btrfs_trans_handle *trans,
+                            struct btrfs_root *root, u64 type)
+{
+        u64 alloc_flags = get_alloc_profile(root, type);
+        return do_chunk_alloc(trans, root, 2 * 1024 * 1024, alloc_flags, 1);
+}
 /*
 * helper to account the unused space of all the readonly block group in the
 * list. takes mirrors into account.
diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c
index 92ac5192c518..fd3f172e94e6 100644
--- a/fs/btrfs/extent_io.c
+++ b/fs/btrfs/extent_io.c
@@ -1433,12 +1433,13 @@ int extent_clear_unlock_delalloc(struct inode *inode,
 */
 u64 count_range_bits(struct extent_io_tree *tree,
                     u64 *start, u64 search_end, u64 max_bytes,
-                     unsigned long bits)
+                     unsigned long bits, int contig)
 {
        struct rb_node *node;
        struct extent_state *state;
        u64 cur_start = *start;
        u64 total_bytes = 0;
+        u64 last = 0;
        int found = 0;
        if (search_end <= cur_start) {
@@ -1463,7 +1464,9 @@ u64 count_range_bits(struct extent_io_tree *tree,
                state = rb_entry(node, struct extent_state, rb_node);
                if (state->start > search_end)
                        break;
-                if (state->end >= cur_start && (state->state & bits)) {
+                if (contig && found && state->start > last + 1)
+                        break;
+                if (state->end >= cur_start && (state->state & bits) == bits) {
                        total_bytes += min(search_end, state->end) + 1 -
                                       max(cur_start, state->start);
                        if (total_bytes >= max_bytes)
@@ -1472,6 +1475,9 @@ u64 count_range_bits(struct extent_io_tree *tree,
                                *start = state->start;
                                found = 1;
                        }
+                        last = state->end;
+                } else if (contig && found) {
+                        break;
                }
                node = rb_next(node);
                if (!node)
@@ -2912,6 +2918,46 @@ out:
        return sector;
 }
+/*
+ * helper function for fiemap, which doesn't want to see any holes.
+ * This maps until we find something past 'last'
+ */
+static struct extent_map *get_extent_skip_holes(struct inode *inode,
+                                                u64 offset,
+                                                u64 last,
+                                                get_extent_t *get_extent)
+{
+        u64 sectorsize = BTRFS_I(inode)->root->sectorsize;
+        struct extent_map *em;
+        u64 len;
+        if (offset >= last)
+                return NULL;
+        while(1) {
+                len = last - offset;
+                if (len == 0)
+                        break;
+                len = (len + sectorsize - 1) & ~(sectorsize - 1);
+                em = get_extent(inode, NULL, 0, offset, len, 0);
+                if (!em || IS_ERR(em))
+                        return em;
+                /* if this isn't a hole return it */
+                if (!test_bit(EXTENT_FLAG_VACANCY, &em->flags) &&
+                    em->block_start != EXTENT_MAP_HOLE) {
+                        return em;
+                }
+                /* this is a hole, advance to the next extent */
+                offset = extent_map_end(em);
+                free_extent_map(em);
+                if (offset >= last)
+                        break;
+        }
+        return NULL;
+}
 int extent_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo,
                __u64 start, __u64 len, get_extent_t *get_extent)
 {
@@ -2921,16 +2967,19 @@ int extent_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo,
        u32 flags = 0;
        u32 found_type;
        u64 last;
+        u64 last_for_get_extent = 0;
        u64 disko = 0;
+        u64 isize = i_size_read(inode);
        struct btrfs_key found_key;
        struct extent_map *em = NULL;
        struct extent_state *cached_state = NULL;
        struct btrfs_path *path;
        struct btrfs_file_extent_item *item;
        int end = 0;
-        u64 em_start = 0, em_len = 0;
+        u64 em_start = 0;
+        u64 em_len = 0;
+        u64 em_end = 0;
        unsigned long emflags;
-        int hole = 0;
        if (len == 0)
                return -EINVAL;
@@ -2940,6 +2989,10 @@ int extent_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo,
                return -ENOMEM;
        path->leave_spinning = 1;
+        /*
+         * lookup the last file extent.  We're not using i_size here
+         * because there might be preallocation past i_size
+         */
        ret = btrfs_lookup_file_extent(NULL, BTRFS_I(inode)->root,
                                       path, inode->i_ino, -1, 0);
        if (ret < 0) {
@@ -2953,18 +3006,38 @@ int extent_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo,
        btrfs_item_key_to_cpu(path->nodes[0], &found_key, path->slots[0]);
        found_type = btrfs_key_type(&found_key);
-        /* No extents, just return */
+        /* No extents, but there might be delalloc bits */
        if (found_key.objectid != inode->i_ino ||
            found_type != BTRFS_EXTENT_DATA_KEY) {
-                btrfs_free_path(path);
+                /* have to trust i_size as the end */
-                return 0;
+                last = (u64)-1;
+                last_for_get_extent = isize;
+        } else {
+                /*
+                 * remember the start of the last extent.  There are a
+                 * bunch of different factors that go into the length of the
+                 * extent, so its much less complex to remember where it started
+                 */
+                last = found_key.offset;
+                last_for_get_extent = last + 1;
        }
-        last = found_key.offset;
        btrfs_free_path(path);
+        /*
+         * we might have some extents allocated but more delalloc past those
+         * extents.  so, we trust isize unless the start of the last extent is
+         * beyond isize
+         */
+        if (last < isize) {
+                last = (u64)-1;
+                last_for_get_extent = isize;
+        }
        lock_extent_bits(&BTRFS_I(inode)->io_tree, start, start + len, 0,
                         &cached_state, GFP_NOFS);
-        em = get_extent(inode, NULL, 0, off, max - off, 0);
+        em = get_extent_skip_holes(inode, off, last_for_get_extent,
+                                   get_extent);
        if (!em)
                goto out;
        if (IS_ERR(em)) {
@@ -2973,19 +3046,14 @@ int extent_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo,
        }
        while (!end) {
-                hole = 0;
+                off = extent_map_end(em);
-                off = em->start + em->len;
                if (off >= max)
                        end = 1;
-                if (em->block_start == EXTENT_MAP_HOLE) {
-                        hole = 1;
-                        goto next;
-                }
                em_start = em->start;
                em_len = em->len;
+                em_end = extent_map_end(em);
+                emflags = em->flags;
                disko = 0;
                flags = 0;
@@ -3004,37 +3072,29 @@ int extent_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo,
                if (test_bit(EXTENT_FLAG_COMPRESSED, &em->flags))
                        flags |= FIEMAP_EXTENT_ENCODED;
-next:
-                emflags = em->flags;
                free_extent_map(em);
                em = NULL;
-                if (!end) {
+                if ((em_start >= last) || em_len == (u64)-1 ||
-                        em = get_extent(inode, NULL, 0, off, max - off, 0);
+                   (last == (u64)-1 && isize <= em_end)) {
-                        if (!em)
-                                goto out;
-                        if (IS_ERR(em)) {
-                                ret = PTR_ERR(em);
-                                goto out;
-                        }
-                        emflags = em->flags;
-                }
-                if (test_bit(EXTENT_FLAG_VACANCY, &emflags)) {
                        flags |= FIEMAP_EXTENT_LAST;
                        end = 1;
                }
-                if (em_start == last) {
+                /* now scan forward to see if this is really the last extent. */
+                em = get_extent_skip_holes(inode, off, last_for_get_extent,
+                                           get_extent);
+                if (IS_ERR(em)) {
+                        ret = PTR_ERR(em);
+                        goto out;
+                }
+                if (!em) {
                        flags |= FIEMAP_EXTENT_LAST;
                        end = 1;
                }
+                ret = fiemap_fill_next_extent(fieinfo, em_start, disko,
-                if (!hole) {
+                                              em_len, flags);
-                        ret = fiemap_fill_next_extent(fieinfo, em_start, disko,
+                if (ret)
-                                                em_len, flags);
+                        goto out_free;
-                        if (ret)
-                                goto out_free;
-                }
        }
 out_free:
        free_extent_map(em);
diff --git a/fs/btrfs/extent_io.h b/fs/btrfs/extent_io.h
index 7083cfafd061..9318dfefd59c 100644
--- a/fs/btrfs/extent_io.h
+++ b/fs/btrfs/extent_io.h
@@ -191,7 +191,7 @@ void extent_io_exit(void);
 u64 count_range_bits(struct extent_io_tree *tree,
                     u64 *start, u64 search_end,
-                     u64 max_bytes, unsigned long bits);
+                     u64 max_bytes, unsigned long bits, int contig);
 void free_extent_state(struct extent_state *state);
 int test_range_bit(struct extent_io_tree *tree, u64 start, u64 end,
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index fb9bd7832b6d..0efdb65953c5 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -1913,7 +1913,7 @@ static int btrfs_clean_io_failures(struct inode *inode, u64 start)
        private = 0;
        if (count_range_bits(&BTRFS_I(inode)->io_failure_tree, &private,
-                             (u64)-1, 1, EXTENT_DIRTY)) {
+                             (u64)-1, 1, EXTENT_DIRTY, 0)) {
                ret = get_state_private(&BTRFS_I(inode)->io_failure_tree,
                                        start, &private_failure);
                if (ret == 0) {
@@ -5280,6 +5280,128 @@ out:
        return em;
 }
+struct extent_map *btrfs_get_extent_fiemap(struct inode *inode, struct page *page,
+                                           size_t pg_offset, u64 start, u64 len,
+                                           int create)
+{
+        struct extent_map *em;
+        struct extent_map *hole_em = NULL;
+        u64 range_start = start;
+        u64 end;
+        u64 found;
+        u64 found_end;
+        int err = 0;
+        em = btrfs_get_extent(inode, page, pg_offset, start, len, create);
+        if (IS_ERR(em))
+                return em;
+        if (em) {
+                /*
+                 * if our em maps to a hole, there might
+                 * actually be delalloc bytes behind it
+                 */
+                if (em->block_start != EXTENT_MAP_HOLE)
+                        return em;
+                else
+                        hole_em = em;
+        }
+        /* check to see if we've wrapped (len == -1 or similar) */
+        end = start + len;
+        if (end < start)
+                end = (u64)-1;
+        else
+                end -= 1;
+        em = NULL;
+        /* ok, we didn't find anything, lets look for delalloc */
+        found = count_range_bits(&BTRFS_I(inode)->io_tree, &range_start,
+                                 end, len, EXTENT_DELALLOC, 1);
+        found_end = range_start + found;
+        if (found_end < range_start)
+                found_end = (u64)-1;
+        /*
+         * we didn't find anything useful, return
+         * the original results from get_extent()
+         */
+        if (range_start > end || found_end <= start) {
+                em = hole_em;
+                hole_em = NULL;
+                goto out;
+        }
+        /* adjust the range_start to make sure it doesn't
+         * go backwards from the start they passed in
+         */
+        range_start = max(start,range_start);
+        found = found_end - range_start;
+        if (found > 0) {
+                u64 hole_start = start;
+                u64 hole_len = len;
+                em = alloc_extent_map(GFP_NOFS);
+                if (!em) {
+                        err = -ENOMEM;
+                        goto out;
+                }
+                /*
+                 * when btrfs_get_extent can't find anything it
+                 * returns one huge hole
+                 *
+                 * make sure what it found really fits our range, and
+                 * adjust to make sure it is based on the start from
+                 * the caller
+                 */
+                if (hole_em) {
+                        u64 calc_end = extent_map_end(hole_em);
+                        if (calc_end <= start || (hole_em->start > end)) {
+                                free_extent_map(hole_em);
+                                hole_em = NULL;
+                        } else {
+                                hole_start = max(hole_em->start, start);
+                                hole_len = calc_end - hole_start;
+                        }
+                }
+                em->bdev = NULL;
+                if (hole_em && range_start > hole_start) {
+                        /* our hole starts before our delalloc, so we
+                         * have to return just the parts of the hole
+                         * that go until  the delalloc starts
+                         */
+                        em->len = min(hole_len,
+                                      range_start - hole_start);
+                        em->start = hole_start;
+                        em->orig_start = hole_start;
+                        /*
+                         * don't adjust block start at all,
+                         * it is fixed at EXTENT_MAP_HOLE
+                         */
+                        em->block_start = hole_em->block_start;
+                        em->block_len = hole_len;
+                } else {
+                        em->start = range_start;
+                        em->len = found;
+                        em->orig_start = range_start;
+                        em->block_start = EXTENT_MAP_DELALLOC;
+                        em->block_len = found;
+                }
+        } else if (hole_em) {
+                return hole_em;
+        }
+out:
+        free_extent_map(hole_em);
+        if (err) {
+                free_extent_map(em);
+                return ERR_PTR(err);
+        }
+        return em;
+}
 static struct extent_map *btrfs_new_extent_direct(struct inode *inode,
                                                  u64 start, u64 len)
 {
@@ -6102,7 +6224,7 @@ out:
 static int btrfs_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo,
                __u64 start, __u64 len)
 {
-        return extent_fiemap(inode, fieinfo, start, len, btrfs_get_extent);
+        return extent_fiemap(inode, fieinfo, start, len, btrfs_get_extent_fiemap);
 }
 int btrfs_readpage(struct file *file, struct page *page)
diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c
index be2d4f6aaa5e..5fdb2abc4fa7 100644
--- a/fs/btrfs/ioctl.c
+++ b/fs/btrfs/ioctl.c
@@ -1071,12 +1071,15 @@ static noinline int btrfs_ioctl_subvol_setflags(struct file *file,
        if (copy_from_user(&flags, arg, sizeof(flags)))
                return -EFAULT;
-        if (flags & ~BTRFS_SUBVOL_CREATE_ASYNC)
+        if (flags & BTRFS_SUBVOL_CREATE_ASYNC)
                return -EINVAL;
        if (flags & ~BTRFS_SUBVOL_RDONLY)
                return -EOPNOTSUPP;
+        if (!is_owner_or_cap(inode))
+                return -EACCES;
        down_write(&root->fs_info->subvol_sem);
        /* nothing to do */
@@ -1097,7 +1100,7 @@ static noinline int btrfs_ioctl_subvol_setflags(struct file *file,
                goto out_reset;
        }
-        ret = btrfs_update_root(trans, root,
+        ret = btrfs_update_root(trans, root->fs_info->tree_root,
                                &root->root_key, &root->root_item);
        btrfs_commit_transaction(trans, root);
diff --git a/fs/btrfs/lzo.c b/fs/btrfs/lzo.c
index cc9b450399df..a178f5ebea78 100644
--- a/fs/btrfs/lzo.c
+++ b/fs/btrfs/lzo.c
@@ -280,6 +280,7 @@ static int lzo_decompress_biovec(struct list_head *ws,
        unsigned long tot_out;
        unsigned long tot_len;
        char *buf;
+        bool may_late_unmap, need_unmap;
        data_in = kmap(pages_in[0]);
        tot_len = read_compress_length(data_in);
@@ -300,11 +301,13 @@ static int lzo_decompress_biovec(struct list_head *ws,
                tot_in += in_len;
                working_bytes = in_len;
+                may_late_unmap = need_unmap = false;
                /* fast path: avoid using the working buffer */
                if (in_page_bytes_left >= in_len) {
                        buf = data_in + in_offset;
                        bytes = in_len;
+                        may_late_unmap = true;
                        goto cont;
                }
@@ -329,14 +332,17 @@ cont:
                                if (working_bytes == 0 && tot_in >= tot_len)
                                        break;
-                                kunmap(pages_in[page_in_index]);
+                                if (page_in_index + 1 >= total_pages_in) {
-                                page_in_index++;
-                                if (page_in_index >= total_pages_in) {
                                        ret = -1;
-                                        data_in = NULL;
                                        goto done;
                                }
-                                data_in = kmap(pages_in[page_in_index]);
+                                if (may_late_unmap)
+                                        need_unmap = true;
+                                else
+                                        kunmap(pages_in[page_in_index]);
+                                data_in = kmap(pages_in[++page_in_index]);
                                in_page_bytes_left = PAGE_CACHE_SIZE;
                                in_offset = 0;
@@ -346,6 +352,8 @@ cont:
                out_len = lzo1x_worst_compress(PAGE_CACHE_SIZE);
                ret = lzo1x_decompress_safe(buf, in_len, workspace->buf,
                                            &out_len);
+                if (need_unmap)
+                        kunmap(pages_in[page_in_index - 1]);
                if (ret != LZO_E_OK) {
                        printk(KERN_WARNING "btrfs decompress failed\n");
                        ret = -1;
@@ -363,8 +371,7 @@ cont:
                        break;
        }
 done:
-        if (data_in)
+        kunmap(pages_in[page_in_index]);
-                kunmap(pages_in[page_in_index]);
        return ret;
 }
diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c
index 0825e4ed9447..31ade5802ae8 100644
--- a/fs/btrfs/relocation.c
+++ b/fs/btrfs/relocation.c
@@ -3654,6 +3654,7 @@ static noinline_for_stack int relocate_block_group(struct reloc_control *rc)
        u32 item_size;
        int ret;
        int err = 0;
+        int progress = 0;
        path = btrfs_alloc_path();
        if (!path)
@@ -3666,9 +3667,10 @@ static noinline_for_stack int relocate_block_group(struct reloc_control *rc)
        }
        while (1) {
+                progress++;
                trans = btrfs_start_transaction(rc->extent_root, 0);
                BUG_ON(IS_ERR(trans));
+restart:
                if (update_backref_cache(trans, &rc->backref_cache)) {
                        btrfs_end_transaction(trans, rc->extent_root);
                        continue;
@@ -3781,6 +3783,15 @@ static noinline_for_stack int relocate_block_group(struct reloc_control *rc)
                        }
                }
        }
+        if (trans && progress && err == -ENOSPC) {
+                ret = btrfs_force_chunk_alloc(trans, rc->extent_root,
+                                              rc->block_group->flags);
+                if (ret == 0) {
+                        err = 0;
+                        progress = 0;
+                        goto restart;
+                }
+        }
        btrfs_release_path(rc->extent_root, path);
        clear_extent_bits(&rc->processed_blocks, 0, (u64)-1, EXTENT_DIRTY,
diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
index a004008f7d28..d39a9895d932 100644
--- a/fs/btrfs/super.c
+++ b/fs/btrfs/super.c
@@ -155,7 +155,8 @@ enum {
        Opt_nossd, Opt_ssd_spread, Opt_thread_pool, Opt_noacl, Opt_compress,
        Opt_compress_type, Opt_compress_force, Opt_compress_force_type,
        Opt_notreelog, Opt_ratio, Opt_flushoncommit, Opt_discard,
-        Opt_space_cache, Opt_clear_cache, Opt_user_subvol_rm_allowed, Opt_err,
+        Opt_space_cache, Opt_clear_cache, Opt_user_subvol_rm_allowed,
+        Opt_enospc_debug, Opt_err,
 };
 static match_table_t tokens = {
@@ -184,6 +185,7 @@ static match_table_t tokens = {
        {Opt_space_cache, "space_cache"},
        {Opt_clear_cache, "clear_cache"},
        {Opt_user_subvol_rm_allowed, "user_subvol_rm_allowed"},
+        {Opt_enospc_debug, "enospc_debug"},
        {Opt_err, NULL},
 };
@@ -358,6 +360,9 @@ int btrfs_parse_options(struct btrfs_root *root, char *options)
                case Opt_user_subvol_rm_allowed:
                        btrfs_set_opt(info->mount_opt, USER_SUBVOL_RM_ALLOWED);
                        break;
+                case Opt_enospc_debug:
+                        btrfs_set_opt(info->mount_opt, ENOSPC_DEBUG);
+                        break;
                case Opt_err:
                        printk(KERN_INFO "btrfs: unrecognized mount option "
                               "'%s'\n", p);
diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c
index af7dbca15276..dd13eb81ee40 100644
--- a/fs/btrfs/volumes.c
+++ b/fs/btrfs/volumes.c
@@ -1338,11 +1338,11 @@ int btrfs_rm_device(struct btrfs_root *root, char *device_path)
        ret = btrfs_shrink_device(device, 0);
        if (ret)
-                goto error_brelse;
+                goto error_undo;
        ret = btrfs_rm_dev_item(root->fs_info->chunk_root, device);
        if (ret)
-                goto error_brelse;
+                goto error_undo;
        device->in_fs_metadata = 0;
@@ -1416,6 +1416,13 @@ out:
        mutex_unlock(&root->fs_info->volume_mutex);
        mutex_unlock(&uuid_mutex);
        return ret;
+error_undo:
+        if (device->writeable) {
+                list_add(&device->dev_alloc_list,
+                         &root->fs_info->fs_devices->alloc_list);
+                root->fs_info->fs_devices->rw_devices++;
+        }
+        goto error_brelse;
 }
 /*
@@ -1633,7 +1640,7 @@ int btrfs_init_new_device(struct btrfs_root *root, char *device_path)
        device->dev_root = root->fs_info->dev_root;
        device->bdev = bdev;
        device->in_fs_metadata = 1;
-        device->mode = 0;
+        device->mode = FMODE_EXCL;
        set_blocksize(device->bdev, 4096);
        if (seeding_dev) {
diff --git a/fs/ceph/dir.c b/fs/ceph/dir.c
index f0aef787a102..099a58615b90 100644
--- a/fs/ceph/dir.c
+++ b/fs/ceph/dir.c
@@ -60,7 +60,6 @@ int ceph_init_dentry(struct dentry *dentry)
        }
        di->dentry = dentry;
        di->lease_session = NULL;
-        di->parent_inode = igrab(dentry->d_parent->d_inode);
        dentry->d_fsdata = di;
        dentry->d_time = jiffies;
        ceph_dentry_lru_add(dentry);
@@ -410,7 +409,7 @@ more:
        spin_lock(&inode->i_lock);
        if (ci->i_release_count == fi->dir_release_count) {
                dout(" marking %p complete\n", inode);
-                ci->i_ceph_flags |= CEPH_I_COMPLETE;
+                /* ci->i_ceph_flags |= CEPH_I_COMPLETE; */
                ci->i_max_offset = filp->f_pos;
        }
        spin_unlock(&inode->i_lock);
@@ -497,6 +496,7 @@ struct dentry *ceph_finish_lookup(struct ceph_mds_request *req,
        /* .snap dir? */
        if (err == -ENOENT &&
+            ceph_snap(parent) == CEPH_NOSNAP &&
            strcmp(dentry->d_name.name,
                   fsc->mount_options->snapdir_name) == 0) {
                struct inode *inode = ceph_get_snapdir(parent);
@@ -1030,28 +1030,8 @@ out_touch:
 static void ceph_dentry_release(struct dentry *dentry)
 {
        struct ceph_dentry_info *di = ceph_dentry(dentry);
-        struct inode *parent_inode = NULL;
-        u64 snapid = CEPH_NOSNAP;
-        if (!IS_ROOT(dentry)) {
+        dout("dentry_release %p\n", dentry);
-                parent_inode = di->parent_inode;
-                if (parent_inode)
-                        snapid = ceph_snap(parent_inode);
-        }
-        dout("dentry_release %p parent %p\n", dentry, parent_inode);
-        if (parent_inode && snapid != CEPH_SNAPDIR) {
-                struct ceph_inode_info *ci = ceph_inode(parent_inode);
-                spin_lock(&parent_inode->i_lock);
-                if (ci->i_shared_gen == di->lease_shared_gen ||
-                    snapid <= CEPH_MAXSNAP) {
-                        dout(" clearing %p complete (d_release)\n",
-                             parent_inode);
-                        ci->i_ceph_flags &= ~CEPH_I_COMPLETE;
-                        ci->i_release_count++;
-                }
-                spin_unlock(&parent_inode->i_lock);
-        }
        if (di) {
                ceph_dentry_lru_del(dentry);
                if (di->lease_session)
@@ -1059,8 +1039,6 @@ static void ceph_dentry_release(struct dentry *dentry)
                kmem_cache_free(ceph_dentry_cachep, di);
                dentry->d_fsdata = NULL;
        }
-        if (parent_inode)
-                iput(parent_inode);
 }
 static int ceph_snapdir_d_revalidate(struct dentry *dentry,
diff --git a/fs/ceph/inode.c b/fs/ceph/inode.c
index 5625463aa479..193bfa5e9cbd 100644
--- a/fs/ceph/inode.c
+++ b/fs/ceph/inode.c
@@ -707,7 +707,7 @@ static int fill_inode(struct inode *inode,
                    (issued & CEPH_CAP_FILE_EXCL) == 0 &&
                    (ci->i_ceph_flags & CEPH_I_COMPLETE) == 0) {
                        dout(" marking %p complete (empty)\n", inode);
-                        ci->i_ceph_flags |= CEPH_I_COMPLETE;
+                        /* ci->i_ceph_flags |= CEPH_I_COMPLETE; */
                        ci->i_max_offset = 2;
                }
                break;
diff --git a/fs/ceph/super.h b/fs/ceph/super.h
index 88fcaa21b801..20b907d76ae2 100644
--- a/fs/ceph/super.h
+++ b/fs/ceph/super.h
@@ -207,7 +207,6 @@ struct ceph_dentry_info {
        struct dentry *dentry;
        u64 time;
        u64 offset;
-        struct inode *parent_inode;
 };
 struct ceph_inode_xattrs_info {
diff --git a/fs/eventpoll.c b/fs/eventpoll.c
index 267d0ada4541..4a09af9e9a63 100644
--- a/fs/eventpoll.c
+++ b/fs/eventpoll.c
@@ -63,6 +63,13 @@
 * cleanup path and it is also acquired by eventpoll_release_file()
 * if a file has been pushed inside an epoll set and it is then
 * close()d without a previous call toepoll_ctl(EPOLL_CTL_DEL).
+ * It is also acquired when inserting an epoll fd onto another epoll
+ * fd. We do this so that we walk the epoll tree and ensure that this
+ * insertion does not create a cycle of epoll file descriptors, which
+ * could lead to deadlock. We need a global mutex to prevent two
+ * simultaneous inserts (A into B and B into A) from racing and
+ * constructing a cycle without either insert observing that it is
+ * going to.
 * It is possible to drop the "ep->mtx" and to use the global
 * mutex "epmutex" (together with "ep->lock") to have it working,
 * but having "ep->mtx" will make the interface more scalable.
@@ -224,6 +231,9 @@ static long max_user_watches __read_mostly;
 */
 static DEFINE_MUTEX(epmutex);
+/* Used to check for epoll file descriptor inclusion loops */
+static struct nested_calls poll_loop_ncalls;
 /* Used for safe wake up implementation */
 static struct nested_calls poll_safewake_ncalls;
@@ -1198,6 +1208,62 @@ retry:
        return res;
 }
+/**
+ * ep_loop_check_proc - Callback function to be passed to the @ep_call_nested()
+ *                      API, to verify that adding an epoll file inside another
+ *                      epoll structure, does not violate the constraints, in
+ *                      terms of closed loops, or too deep chains (which can
+ *                      result in excessive stack usage).
+ *
+ * @priv: Pointer to the epoll file to be currently checked.
+ * @cookie: Original cookie for this call. This is the top-of-the-chain epoll
+ *          data structure pointer.
+ * @call_nests: Current dept of the @ep_call_nested() call stack.
+ *
+ * Returns: Returns zero if adding the epoll @file inside current epoll
+ *          structure @ep does not violate the constraints, or -1 otherwise.
+ */
+static int ep_loop_check_proc(void *priv, void *cookie, int call_nests)
+{
+        int error = 0;
+        struct file *file = priv;
+        struct eventpoll *ep = file->private_data;
+        struct rb_node *rbp;
+        struct epitem *epi;
+        mutex_lock(&ep->mtx);
+        for (rbp = rb_first(&ep->rbr); rbp; rbp = rb_next(rbp)) {
+                epi = rb_entry(rbp, struct epitem, rbn);
+                if (unlikely(is_file_epoll(epi->ffd.file))) {
+                        error = ep_call_nested(&poll_loop_ncalls, EP_MAX_NESTS,
+                                               ep_loop_check_proc, epi->ffd.file,
+                                               epi->ffd.file->private_data, current);
+                        if (error != 0)
+                                break;
+                }
+        }
+        mutex_unlock(&ep->mtx);
+        return error;
+}
+/**
+ * ep_loop_check - Performs a check to verify that adding an epoll file (@file)
+ *                 another epoll file (represented by @ep) does not create
+ *                 closed loops or too deep chains.
+ *
+ * @ep: Pointer to the epoll private data structure.
+ * @file: Pointer to the epoll file to be checked.
+ *
+ * Returns: Returns zero if adding the epoll @file inside current epoll
+ *          structure @ep does not violate the constraints, or -1 otherwise.
+ */
+static int ep_loop_check(struct eventpoll *ep, struct file *file)
+{
+        return ep_call_nested(&poll_loop_ncalls, EP_MAX_NESTS,
+                              ep_loop_check_proc, file, ep, current);
+}
 /*
 * Open an eventpoll file descriptor.
 */
@@ -1246,6 +1312,7 @@ SYSCALL_DEFINE4(epoll_ctl, int, epfd, int, op, int, fd,
                struct epoll_event __user *, event)
 {
        int error;
+        int did_lock_epmutex = 0;
        struct file *file, *tfile;
        struct eventpoll *ep;
        struct epitem *epi;
@@ -1287,6 +1354,25 @@ SYSCALL_DEFINE4(epoll_ctl, int, epfd, int, op, int, fd,
         */
        ep = file->private_data;
+        /*
+         * When we insert an epoll file descriptor, inside another epoll file
+         * descriptor, there is the change of creating closed loops, which are
+         * better be handled here, than in more critical paths.
+         *
+         * We hold epmutex across the loop check and the insert in this case, in
+         * order to prevent two separate inserts from racing and each doing the
+         * insert "at the same time" such that ep_loop_check passes on both
+         * before either one does the insert, thereby creating a cycle.
+         */
+        if (unlikely(is_file_epoll(tfile) && op == EPOLL_CTL_ADD)) {
+                mutex_lock(&epmutex);
+                did_lock_epmutex = 1;
+                error = -ELOOP;
+                if (ep_loop_check(ep, tfile) != 0)
+                        goto error_tgt_fput;
+        }
        mutex_lock(&ep->mtx);
        /*
@@ -1322,6 +1408,9 @@ SYSCALL_DEFINE4(epoll_ctl, int, epfd, int, op, int, fd,
        mutex_unlock(&ep->mtx);
 error_tgt_fput:
+        if (unlikely(did_lock_epmutex))
+                mutex_unlock(&epmutex);
        fput(tfile);
 error_fput:
        fput(file);
@@ -1441,6 +1530,12 @@ static int __init eventpoll_init(void)
                EP_ITEM_COST;
        BUG_ON(max_user_watches < 0);
+        /*
+         * Initialize the structure used to perform epoll file descriptor
+         * inclusion loops checks.
+         */
+        ep_nested_calls_init(&poll_loop_ncalls);
        /* Initialize the structure used to perform safe poll wait head wake ups */
        ep_nested_calls_init(&poll_safewake_ncalls);
diff --git a/fs/exofs/namei.c b/fs/exofs/namei.c
index 264e95d02830..4d70db110cfc 100644
--- a/fs/exofs/namei.c
+++ b/fs/exofs/namei.c
@@ -272,7 +272,6 @@ static int exofs_rename(struct inode *old_dir, struct dentry *old_dentry,
                new_de = exofs_find_entry(new_dir, new_dentry, &new_page);
                if (!new_de)
                        goto out_dir;
-                inode_inc_link_count(old_inode);
                err = exofs_set_link(new_dir, new_de, new_page, old_inode);
                new_inode->i_ctime = CURRENT_TIME;
                if (dir_de)
@@ -286,12 +285,9 @@ static int exofs_rename(struct inode *old_dir, struct dentry *old_dentry,
                        if (new_dir->i_nlink >= EXOFS_LINK_MAX)
                                goto out_dir;
                }
-                inode_inc_link_count(old_inode);
                err = exofs_add_link(new_dentry, old_inode);
-                if (err) {
+                if (err)
-                        inode_dec_link_count(old_inode);
                        goto out_dir;
-                }
                if (dir_de)
                        inode_inc_link_count(new_dir);
        }
@@ -299,7 +295,7 @@ static int exofs_rename(struct inode *old_dir, struct dentry *old_dentry,
        old_inode->i_ctime = CURRENT_TIME;
        exofs_delete_entry(old_de, old_page);
-        inode_dec_link_count(old_inode);
+        mark_inode_dirty(old_inode);
        if (dir_de) {
                err = exofs_set_link(old_inode, dir_de, dir_page, new_dir);
diff --git a/fs/ext2/namei.c b/fs/ext2/namei.c
index 2e1d8341d827..adb91855ccd0 100644
--- a/fs/ext2/namei.c
+++ b/fs/ext2/namei.c
@@ -344,7 +344,6 @@ static int ext2_rename (struct inode * old_dir, struct dentry * old_dentry,
                new_de = ext2_find_entry (new_dir, &new_dentry->d_name, &new_page);
                if (!new_de)
                        goto out_dir;
-                inode_inc_link_count(old_inode);
                ext2_set_link(new_dir, new_de, new_page, old_inode, 1);
                new_inode->i_ctime = CURRENT_TIME_SEC;
                if (dir_de)
@@ -356,12 +355,9 @@ static int ext2_rename (struct inode * old_dir, struct dentry * old_dentry,
                        if (new_dir->i_nlink >= EXT2_LINK_MAX)
                                goto out_dir;
                }
-                inode_inc_link_count(old_inode);
                err = ext2_add_link(new_dentry, old_inode);
-                if (err) {
+                if (err)
-                        inode_dec_link_count(old_inode);
                        goto out_dir;
-                }
                if (dir_de)
                        inode_inc_link_count(new_dir);
        }
@@ -369,12 +365,11 @@ static int ext2_rename (struct inode * old_dir, struct dentry * old_dentry,
        /*
         * Like most other Unix systems, set the ctime for inodes on a
         * rename.
-         * inode_dec_link_count() will mark the inode dirty.
         */
        old_inode->i_ctime = CURRENT_TIME_SEC;
+        mark_inode_dirty(old_inode);
        ext2_delete_entry (old_de, old_page);
-        inode_dec_link_count(old_inode);
        if (dir_de) {
                if (old_dir != new_dir)
diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c
index bfed8447ed80..83543b5ff941 100644
--- a/fs/fuse/dir.c
+++ b/fs/fuse/dir.c
@@ -1283,8 +1283,11 @@ static int fuse_do_setattr(struct dentry *entry, struct iattr *attr,
        if (err)
                return err;
-        if ((attr->ia_valid & ATTR_OPEN) && fc->atomic_o_trunc)
+        if (attr->ia_valid & ATTR_OPEN) {
-                return 0;
+                if (fc->atomic_o_trunc)
+                        return 0;
+                file = NULL;
+        }
        if (attr->ia_valid & ATTR_SIZE)
                is_truncate = true;
diff --git a/fs/fuse/file.c b/fs/fuse/file.c
index 95da1bc1c826..9e0832dbb1e3 100644
--- a/fs/fuse/file.c
+++ b/fs/fuse/file.c
@@ -86,18 +86,52 @@ struct fuse_file *fuse_file_get(struct fuse_file *ff)
        return ff;
 }
+static void fuse_release_async(struct work_struct *work)
+{
+        struct fuse_req *req;
+        struct fuse_conn *fc;
+        struct path path;
+        req = container_of(work, struct fuse_req, misc.release.work);
+        path = req->misc.release.path;
+        fc = get_fuse_conn(path.dentry->d_inode);
+        fuse_put_request(fc, req);
+        path_put(&path);
+}
 static void fuse_release_end(struct fuse_conn *fc, struct fuse_req *req)
 {
-        path_put(&req->misc.release.path);
+        if (fc->destroy_req) {
+                /*
+                 * If this is a fuseblk mount, then it's possible that
+                 * releasing the path will result in releasing the
+                 * super block and sending the DESTROY request.  If
+                 * the server is single threaded, this would hang.
+                 * For this reason do the path_put() in a separate
+                 * thread.
+                 */
+                atomic_inc(&req->count);
+                INIT_WORK(&req->misc.release.work, fuse_release_async);
+                schedule_work(&req->misc.release.work);
+        } else {
+                path_put(&req->misc.release.path);
+        }
 }
-static void fuse_file_put(struct fuse_file *ff)
+static void fuse_file_put(struct fuse_file *ff, bool sync)
 {
        if (atomic_dec_and_test(&ff->count)) {
                struct fuse_req *req = ff->reserved_req;
-                req->end = fuse_release_end;
+                if (sync) {
-                fuse_request_send_background(ff->fc, req);
+                        fuse_request_send(ff->fc, req);
+                        path_put(&req->misc.release.path);
+                        fuse_put_request(ff->fc, req);
+                } else {
+                        req->end = fuse_release_end;
+                        fuse_request_send_background(ff->fc, req);
+                }
                kfree(ff);
        }
 }
@@ -219,8 +253,12 @@ void fuse_release_common(struct file *file, int opcode)
         * Normally this will send the RELEASE request, however if
         * some asynchronous READ or WRITE requests are outstanding,
         * the sending will be delayed.
+         *
+         * Make the release synchronous if this is a fuseblk mount,
+         * synchronous RELEASE is allowed (and desirable) in this case
+         * because the server can be trusted not to screw up.
         */
-        fuse_file_put(ff);
+        fuse_file_put(ff, ff->fc->destroy_req != NULL);
 }
 static int fuse_open(struct inode *inode, struct file *file)
@@ -558,7 +596,7 @@ static void fuse_readpages_end(struct fuse_conn *fc, struct fuse_req *req)
                page_cache_release(page);
        }
        if (req->ff)
-                fuse_file_put(req->ff);
+                fuse_file_put(req->ff, false);
 }
 static void fuse_send_readpages(struct fuse_req *req, struct file *file)
@@ -1137,7 +1175,7 @@ static ssize_t fuse_direct_write(struct file *file, const char __user *buf,
 static void fuse_writepage_free(struct fuse_conn *fc, struct fuse_req *req)
 {
        __free_page(req->pages[0]);
-        fuse_file_put(req->ff);
+        fuse_file_put(req->ff, false);
 }
 static void fuse_writepage_finish(struct fuse_conn *fc, struct fuse_req *req)
diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h
index ae5744a2f9e9..d4286947bc2c 100644
--- a/fs/fuse/fuse_i.h
+++ b/fs/fuse/fuse_i.h
@@ -21,6 +21,7 @@
 #include <linux/rwsem.h>
 #include <linux/rbtree.h>
 #include <linux/poll.h>
+#include <linux/workqueue.h>
 /** Max number of pages that can be used in a single read request */
 #define FUSE_MAX_PAGES_PER_REQ 32
@@ -262,7 +263,10 @@ struct fuse_req {
        /** Data for asynchronous requests */
        union {
                struct {
-                        struct fuse_release_in in;
+                        union {
+                                struct fuse_release_in in;
+                                struct work_struct work;
+                        };
                        struct path path;
                } release;
                struct fuse_init_in init_in;
diff --git a/fs/gfs2/main.c b/fs/gfs2/main.c
index 85ba027d1c4d..72c31a315d96 100644
--- a/fs/gfs2/main.c
+++ b/fs/gfs2/main.c
@@ -59,14 +59,7 @@ static void gfs2_init_gl_aspace_once(void *foo)
        struct address_space *mapping = (struct address_space *)(gl + 1);
        gfs2_init_glock_once(gl);
-        memset(mapping, 0, sizeof(*mapping));
+        address_space_init_once(mapping);
-        INIT_RADIX_TREE(&mapping->page_tree, GFP_ATOMIC);
-        spin_lock_init(&mapping->tree_lock);
-        spin_lock_init(&mapping->i_mmap_lock);
-        INIT_LIST_HEAD(&mapping->private_list);
-        spin_lock_init(&mapping->private_lock);
-        INIT_RAW_PRIO_TREE_ROOT(&mapping->i_mmap);
-        INIT_LIST_HEAD(&mapping->i_mmap_nonlinear);
 }
 /**
diff --git a/fs/hfs/dir.c b/fs/hfs/dir.c
index afa66aaa2237..b4d70b13be92 100644
--- a/fs/hfs/dir.c
+++ b/fs/hfs/dir.c
@@ -238,46 +238,22 @@ static int hfs_mkdir(struct inode *dir, struct dentry *dentry, int mode)
 }
 /*
- * hfs_unlink()
+ * hfs_remove()
 *
- * This is the unlink() entry in the inode_operations structure for
+ * This serves as both unlink() and rmdir() in the inode_operations
- * regular HFS directories.  The purpose is to delete an existing
+ * structure for regular HFS directories.  The purpose is to delete
- * file, given the inode for the parent directory and the name
+ * an existing child, given the inode for the parent directory and
- * (and its length) of the existing file.
+ * the name (and its length) of the existing directory.
- */
-static int hfs_unlink(struct inode *dir, struct dentry *dentry)
-{
-        struct inode *inode;
-        int res;
-        inode = dentry->d_inode;
-        res = hfs_cat_delete(inode->i_ino, dir, &dentry->d_name);
-        if (res)
-                return res;
-        drop_nlink(inode);
-        hfs_delete_inode(inode);
-        inode->i_ctime = CURRENT_TIME_SEC;
-        mark_inode_dirty(inode);
-        return res;
-}
-/*
- * hfs_rmdir()
 *
- * This is the rmdir() entry in the inode_operations structure for
+ * HFS does not have hardlinks, so both rmdir and unlink set the
- * regular HFS directories.  The purpose is to delete an existing
+ * link count to 0.  The only difference is the emptiness check.
- * directory, given the inode for the parent directory and the name
- * (and its length) of the existing directory.
 */
-static int hfs_rmdir(struct inode *dir, struct dentry *dentry)
+static int hfs_remove(struct inode *dir, struct dentry *dentry)
 {
-        struct inode *inode;
+        struct inode *inode = dentry->d_inode;
        int res;
-        inode = dentry->d_inode;
+        if (S_ISDIR(inode->i_mode) && inode->i_size != 2)
-        if (inode->i_size != 2)
                return -ENOTEMPTY;
        res = hfs_cat_delete(inode->i_ino, dir, &dentry->d_name);
        if (res)
@@ -307,7 +283,7 @@ static int hfs_rename(struct inode *old_dir, struct dentry *old_dentry,
        /* Unlink destination if it already exists */
        if (new_dentry->d_inode) {
-                res = hfs_unlink(new_dir, new_dentry);
+                res = hfs_remove(new_dir, new_dentry);
                if (res)
                        return res;
        }
@@ -332,9 +308,9 @@ const struct file_operations hfs_dir_operations = {
 const struct inode_operations hfs_dir_inode_operations = {
        .create         = hfs_create,
        .lookup         = hfs_lookup,
-        .unlink         = hfs_unlink,
+        .unlink         = hfs_remove,
        .mkdir          = hfs_mkdir,
-        .rmdir          = hfs_rmdir,
+        .rmdir          = hfs_remove,
        .rename         = hfs_rename,
        .setattr        = hfs_inode_setattr,
 };
diff --git a/fs/inode.c b/fs/inode.c
index da85e56378f3..0647d80accf6 100644
--- a/fs/inode.c
+++ b/fs/inode.c
@@ -295,6 +295,20 @@ static void destroy_inode(struct inode *inode)
                call_rcu(&inode->i_rcu, i_callback);
 }
+void address_space_init_once(struct address_space *mapping)
+{
+        memset(mapping, 0, sizeof(*mapping));
+        INIT_RADIX_TREE(&mapping->page_tree, GFP_ATOMIC);
+        spin_lock_init(&mapping->tree_lock);
+        spin_lock_init(&mapping->i_mmap_lock);
+        INIT_LIST_HEAD(&mapping->private_list);
+        spin_lock_init(&mapping->private_lock);
+        INIT_RAW_PRIO_TREE_ROOT(&mapping->i_mmap);
+        INIT_LIST_HEAD(&mapping->i_mmap_nonlinear);
+        mutex_init(&mapping->unmap_mutex);
+}
+EXPORT_SYMBOL(address_space_init_once);
 /*
 * These are initializations that only need to be done
 * once, because the fields are idempotent across use
@@ -308,13 +322,7 @@ void inode_init_once(struct inode *inode)
        INIT_LIST_HEAD(&inode->i_devices);
        INIT_LIST_HEAD(&inode->i_wb_list);
        INIT_LIST_HEAD(&inode->i_lru);
-        INIT_RADIX_TREE(&inode->i_data.page_tree, GFP_ATOMIC);
+        address_space_init_once(&inode->i_data);
-        spin_lock_init(&inode->i_data.tree_lock);
-        spin_lock_init(&inode->i_data.i_mmap_lock);
-        INIT_LIST_HEAD(&inode->i_data.private_list);
-        spin_lock_init(&inode->i_data.private_lock);
-        INIT_RAW_PRIO_TREE_ROOT(&inode->i_data.i_mmap);
-        INIT_LIST_HEAD(&inode->i_data.i_mmap_nonlinear);
        i_size_ordered_init(inode);
 #ifdef CONFIG_FSNOTIFY
        INIT_HLIST_HEAD(&inode->i_fsnotify_marks);
@@ -540,11 +548,14 @@ void evict_inodes(struct super_block *sb)
 /**
 * invalidate_inodes    - attempt to free all inodes on a superblock
 * @sb:         superblock to operate on
+ * @kill_dirty: flag to guide handling of dirty inodes
 *
 * Attempts to free all inodes for a given superblock.  If there were any
 * busy inodes return a non-zero value, else zero.
+ * If @kill_dirty is set, discard dirty inodes too, otherwise treat
+ * them as busy.
 */
-int invalidate_inodes(struct super_block *sb)
+int invalidate_inodes(struct super_block *sb, bool kill_dirty)
 {
        int busy = 0;
        struct inode *inode, *next;
@@ -556,6 +567,10 @@ int invalidate_inodes(struct super_block *sb)
        list_for_each_entry_safe(inode, next, &sb->s_inodes, i_sb_list) {
                if (inode->i_state & (I_NEW | I_FREEING | I_WILL_FREE))
                        continue;
+                if (inode->i_state & I_DIRTY && !kill_dirty) {
+                        busy = 1;
+                        continue;
+                }
                if (atomic_read(&inode->i_count)) {
                        busy = 1;
                        continue;
diff --git a/fs/internal.h b/fs/internal.h
index 0663568b1247..9b976b57d7fe 100644
--- a/fs/internal.h
+++ b/fs/internal.h
@@ -112,4 +112,4 @@ extern void release_open_intent(struct nameidata *);
 */
 extern int get_nr_dirty_inodes(void);
 extern void evict_inodes(struct super_block *);
-extern int invalidate_inodes(struct super_block *);
+extern int invalidate_inodes(struct super_block *, bool);
diff --git a/fs/minix/namei.c b/fs/minix/namei.c
index ce7337ddfdbf..6e6777f1b4b2 100644
--- a/fs/minix/namei.c
+++ b/fs/minix/namei.c
@@ -213,7 +213,6 @@ static int minix_rename(struct inode * old_dir, struct dentry *old_dentry,
                new_de = minix_find_entry(new_dentry, &new_page);
                if (!new_de)
                        goto out_dir;
-                inode_inc_link_count(old_inode);
                minix_set_link(new_de, new_page, old_inode);
                new_inode->i_ctime = CURRENT_TIME_SEC;
                if (dir_de)
@@ -225,18 +224,15 @@ static int minix_rename(struct inode * old_dir, struct dentry *old_dentry,
                        if (new_dir->i_nlink >= info->s_link_max)
                                goto out_dir;
                }
-                inode_inc_link_count(old_inode);
                err = minix_add_link(new_dentry, old_inode);
-                if (err) {
+                if (err)
-                        inode_dec_link_count(old_inode);
                        goto out_dir;
-                }
                if (dir_de)
                        inode_inc_link_count(new_dir);
        }
        minix_delete_entry(old_de, old_page);
-        inode_dec_link_count(old_inode);
+        mark_inode_dirty(old_inode);
        if (dir_de) {
                minix_set_link(dir_de, dir_page, new_dir);
diff --git a/fs/namespace.c b/fs/namespace.c
index 7b0b95371696..d1edf26025dc 100644
--- a/fs/namespace.c
+++ b/fs/namespace.c
@@ -1244,7 +1244,7 @@ static int do_umount(struct vfsmount *mnt, int flags)
                 */
                br_write_lock(vfsmount_lock);
                if (mnt_get_count(mnt) != 2) {
-                        br_write_lock(vfsmount_lock);
+                        br_write_unlock(vfsmount_lock);
                        return -EBUSY;
                }
                br_write_unlock(vfsmount_lock);
diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c
index 78936a8f40ab..1ff76acc7e98 100644
--- a/fs/nfs/nfs4proc.c
+++ b/fs/nfs/nfs4proc.c
@@ -51,6 +51,7 @@
 #include <linux/sunrpc/bc_xprt.h>
 #include <linux/xattr.h>
 #include <linux/utsname.h>
+#include <linux/mm.h>
 #include "nfs4_fs.h"
 #include "delegation.h"
@@ -3252,6 +3253,35 @@ static void buf_to_pages(const void *buf, size_t buflen,
        }
 }
+static int buf_to_pages_noslab(const void *buf, size_t buflen,
+                struct page **pages, unsigned int *pgbase)
+{
+        struct page *newpage, **spages;
+        int rc = 0;
+        size_t len;
+        spages = pages;
+        do {
+                len = min(PAGE_CACHE_SIZE, buflen);
+                newpage = alloc_page(GFP_KERNEL);
+                if (newpage == NULL)
+                        goto unwind;
+                memcpy(page_address(newpage), buf, len);
+                buf += len;
+                buflen -= len;
+                *pages++ = newpage;
+                rc++;
+        } while (buflen != 0);
+        return rc;
+unwind:
+        for(; rc > 0; rc--)
+                __free_page(spages[rc-1]);
+        return -ENOMEM;
+}
 struct nfs4_cached_acl {
        int cached;
        size_t len;
@@ -3420,13 +3450,23 @@ static int __nfs4_proc_set_acl(struct inode *inode, const void *buf, size_t bufl
                .rpc_argp       = &arg,
                .rpc_resp       = &res,
        };
-        int ret;
+        int ret, i;
        if (!nfs4_server_supports_acls(server))
                return -EOPNOTSUPP;
+        i = buf_to_pages_noslab(buf, buflen, arg.acl_pages, &arg.acl_pgbase);
+        if (i < 0)
+                return i;
        nfs_inode_return_delegation(inode);
-        buf_to_pages(buf, buflen, arg.acl_pages, &arg.acl_pgbase);
        ret = nfs4_call_sync(server, &msg, &arg, &res, 1);
+        /*
+         * Free each page after tx, so the only ref left is
+         * held by the network stack
+         */
+        for (; i > 0; i--)
+                put_page(pages[i-1]);
        /*
         * Acl update can result in inode attribute update.
         * so mark the attribute cache invalid.
diff --git a/fs/nilfs2/btnode.c b/fs/nilfs2/btnode.c
index 388e9e8f5286..85f7baa15f5d 100644
--- a/fs/nilfs2/btnode.c
+++ b/fs/nilfs2/btnode.c
@@ -35,11 +35,6 @@
 #include "btnode.h"
-void nilfs_btnode_cache_init_once(struct address_space *btnc)
-{
-        nilfs_mapping_init_once(btnc);
-}
 static const struct address_space_operations def_btnode_aops = {
        .sync_page              = block_sync_page,
 };
diff --git a/fs/nilfs2/btnode.h b/fs/nilfs2/btnode.h
index 79037494f1e0..1b8ebd888c28 100644
--- a/fs/nilfs2/btnode.h
+++ b/fs/nilfs2/btnode.h
@@ -37,7 +37,6 @@ struct nilfs_btnode_chkey_ctxt {
        struct buffer_head *newbh;
 };
-void nilfs_btnode_cache_init_once(struct address_space *);
 void nilfs_btnode_cache_init(struct address_space *, struct backing_dev_info *);
 void nilfs_btnode_cache_clear(struct address_space *);
 struct buffer_head *nilfs_btnode_create_block(struct address_space *btnc,
diff --git a/fs/nilfs2/mdt.c b/fs/nilfs2/mdt.c
index 6a0e2a189f60..a0babd2bff6a 100644
--- a/fs/nilfs2/mdt.c
+++ b/fs/nilfs2/mdt.c
@@ -454,9 +454,9 @@ int nilfs_mdt_setup_shadow_map(struct inode *inode,
        struct backing_dev_info *bdi = inode->i_sb->s_bdi;
        INIT_LIST_HEAD(&shadow->frozen_buffers);
-        nilfs_mapping_init_once(&shadow->frozen_data);
+        address_space_init_once(&shadow->frozen_data);
        nilfs_mapping_init(&shadow->frozen_data, bdi, &shadow_map_aops);
-        nilfs_mapping_init_once(&shadow->frozen_btnodes);
+        address_space_init_once(&shadow->frozen_btnodes);
        nilfs_mapping_init(&shadow->frozen_btnodes, bdi, &shadow_map_aops);
        mi->mi_shadow = shadow;
        return 0;
diff --git a/fs/nilfs2/namei.c b/fs/nilfs2/namei.c
index 98034271cd02..161791d26458 100644
--- a/fs/nilfs2/namei.c
+++ b/fs/nilfs2/namei.c
@@ -397,7 +397,6 @@ static int nilfs_rename(struct inode *old_dir, struct dentry *old_dentry,
                new_de = nilfs_find_entry(new_dir, &new_dentry->d_name, &new_page);
                if (!new_de)
                        goto out_dir;
-                inc_nlink(old_inode);
                nilfs_set_link(new_dir, new_de, new_page, old_inode);
                nilfs_mark_inode_dirty(new_dir);
                new_inode->i_ctime = CURRENT_TIME;
@@ -411,13 +410,9 @@ static int nilfs_rename(struct inode *old_dir, struct dentry *old_dentry,
                        if (new_dir->i_nlink >= NILFS_LINK_MAX)
                                goto out_dir;
                }
-                inc_nlink(old_inode);
                err = nilfs_add_link(new_dentry, old_inode);
-                if (err) {
+                if (err)
-                        drop_nlink(old_inode);
-                        nilfs_mark_inode_dirty(old_inode);
                        goto out_dir;
-                }
                if (dir_de) {
                        inc_nlink(new_dir);
                        nilfs_mark_inode_dirty(new_dir);
@@ -431,7 +426,6 @@ static int nilfs_rename(struct inode *old_dir, struct dentry *old_dentry,
        old_inode->i_ctime = CURRENT_TIME;
        nilfs_delete_entry(old_de, old_page);
-        drop_nlink(old_inode);
        if (dir_de) {
                nilfs_set_link(old_inode, dir_de, dir_page, new_dir);
diff --git a/fs/nilfs2/page.c b/fs/nilfs2/page.c
index 0c432416cfef..a585b35fd6bc 100644
--- a/fs/nilfs2/page.c
+++ b/fs/nilfs2/page.c
@@ -492,19 +492,6 @@ unsigned nilfs_page_count_clean_buffers(struct page *page,
        return nc;
 }
-void nilfs_mapping_init_once(struct address_space *mapping)
-{
-        memset(mapping, 0, sizeof(*mapping));
-        INIT_RADIX_TREE(&mapping->page_tree, GFP_ATOMIC);
-        spin_lock_init(&mapping->tree_lock);
-        INIT_LIST_HEAD(&mapping->private_list);
-        spin_lock_init(&mapping->private_lock);
-        spin_lock_init(&mapping->i_mmap_lock);
-        INIT_RAW_PRIO_TREE_ROOT(&mapping->i_mmap);
-        INIT_LIST_HEAD(&mapping->i_mmap_nonlinear);
-}
 void nilfs_mapping_init(struct address_space *mapping,
                        struct backing_dev_info *bdi,
                        const struct address_space_operations *aops)
diff --git a/fs/nilfs2/page.h b/fs/nilfs2/page.h
index 622df27cd891..2a00953ebd5f 100644
--- a/fs/nilfs2/page.h
+++ b/fs/nilfs2/page.h
@@ -61,7 +61,6 @@ void nilfs_free_private_page(struct page *);
 int nilfs_copy_dirty_pages(struct address_space *, struct address_space *);
 void nilfs_copy_back_pages(struct address_space *, struct address_space *);
 void nilfs_clear_dirty_pages(struct address_space *);
-void nilfs_mapping_init_once(struct address_space *mapping);
 void nilfs_mapping_init(struct address_space *mapping,
                        struct backing_dev_info *bdi,
                        const struct address_space_operations *aops);
diff --git a/fs/nilfs2/segment.c b/fs/nilfs2/segment.c
index 55ebae5c7f39..2de9f636792a 100644
--- a/fs/nilfs2/segment.c
+++ b/fs/nilfs2/segment.c
@@ -430,7 +430,8 @@ static void nilfs_segctor_begin_finfo(struct nilfs_sc_info *sci,
        nilfs_segctor_map_segsum_entry(
                sci, &sci->sc_binfo_ptr, sizeof(struct nilfs_finfo));
-        if (inode->i_sb && !test_bit(NILFS_SC_HAVE_DELTA, &sci->sc_flags))
+        if (NILFS_I(inode)->i_root &&
+            !test_bit(NILFS_SC_HAVE_DELTA, &sci->sc_flags))
                set_bit(NILFS_SC_HAVE_DELTA, &sci->sc_flags);
        /* skip finfo */
 }
diff --git a/fs/nilfs2/super.c b/fs/nilfs2/super.c
index 58fd707174e1..1673b3d99842 100644
--- a/fs/nilfs2/super.c
+++ b/fs/nilfs2/super.c
@@ -1279,7 +1279,7 @@ static void nilfs_inode_init_once(void *obj)
 #ifdef CONFIG_NILFS_XATTR
        init_rwsem(&ii->xattr_sem);
 #endif
-        nilfs_btnode_cache_init_once(&ii->i_btnode_cache);
+        address_space_init_once(&ii->i_btnode_cache);
        ii->i_bmap = &ii->i_bmap_data;
        inode_init_once(&ii->vfs_inode);
 }
diff --git a/fs/ocfs2/journal.h b/fs/ocfs2/journal.h
index 43e56b97f9c0..6180da1e37e6 100644
--- a/fs/ocfs2/journal.h
+++ b/fs/ocfs2/journal.h
@@ -405,9 +405,9 @@ static inline int ocfs2_remove_extent_credits(struct super_block *sb)
               ocfs2_quota_trans_credits(sb);
 }
-/* data block for new dir/symlink, 2 for bitmap updates (bitmap fe +
+/* data block for new dir/symlink, allocation of directory block, dx_root
- * bitmap block for the new bit) dx_root update for free list */
+ * update for free list */
-#define OCFS2_DIR_LINK_ADDITIONAL_CREDITS (1 + 2 + 1)
+#define OCFS2_DIR_LINK_ADDITIONAL_CREDITS (1 + OCFS2_SUBALLOC_ALLOC + 1)
 static inline int ocfs2_add_dir_index_credits(struct super_block *sb)
 {
diff --git a/fs/ocfs2/refcounttree.c b/fs/ocfs2/refcounttree.c
index b5f9160e93e9..19ebc5aad391 100644
--- a/fs/ocfs2/refcounttree.c
+++ b/fs/ocfs2/refcounttree.c
@@ -3228,7 +3228,7 @@ static int ocfs2_make_clusters_writable(struct super_block *sb,
                                        u32 num_clusters, unsigned int e_flags)
 {
        int ret, delete, index, credits =  0;
-        u32 new_bit, new_len;
+        u32 new_bit, new_len, orig_num_clusters;
        unsigned int set_len;
        struct ocfs2_super *osb = OCFS2_SB(sb);
        handle_t *handle;
@@ -3261,6 +3261,8 @@ static int ocfs2_make_clusters_writable(struct super_block *sb,
                goto out;
        }
+        orig_num_clusters = num_clusters;
        while (num_clusters) {
                ret = ocfs2_get_refcount_rec(ref_ci, context->ref_root_bh,
                                             p_cluster, num_clusters,
@@ -3348,7 +3350,8 @@ static int ocfs2_make_clusters_writable(struct super_block *sb,
         * in write-back mode.
         */
        if (context->get_clusters == ocfs2_di_get_clusters) {
-                ret = ocfs2_cow_sync_writeback(sb, context, cpos, num_clusters);
+                ret = ocfs2_cow_sync_writeback(sb, context, cpos,
+                                               orig_num_clusters);
                if (ret)
                        mlog_errno(ret);
        }
diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c
index 38f986d2447e..36c423fb0635 100644
--- a/fs/ocfs2/super.c
+++ b/fs/ocfs2/super.c
@@ -1316,7 +1316,7 @@ static int ocfs2_parse_options(struct super_block *sb,
                               struct mount_options *mopt,
                               int is_remount)
 {
-        int status;
+        int status, user_stack = 0;
        char *p;
        u32 tmp;
@@ -1459,6 +1459,15 @@ static int ocfs2_parse_options(struct super_block *sb,
                        memcpy(mopt->cluster_stack, args[0].from,
                               OCFS2_STACK_LABEL_LEN);
                        mopt->cluster_stack[OCFS2_STACK_LABEL_LEN] = '\0';
+                        /*
+                         * Open code the memcmp here as we don't have
+                         * an osb to pass to
+                         * ocfs2_userspace_stack().
+                         */
+                        if (memcmp(mopt->cluster_stack,
+                                   OCFS2_CLASSIC_CLUSTER_STACK,
+                                   OCFS2_STACK_LABEL_LEN))
+                                user_stack = 1;
                        break;
                case Opt_inode64:
                        mopt->mount_opt |= OCFS2_MOUNT_INODE64;
@@ -1514,13 +1523,16 @@ static int ocfs2_parse_options(struct super_block *sb,
                }
        }
-        /* Ensure only one heartbeat mode */
+        if (user_stack == 0) {
-        tmp = mopt->mount_opt & (OCFS2_MOUNT_HB_LOCAL | OCFS2_MOUNT_HB_GLOBAL |
+                /* Ensure only one heartbeat mode */
-                                 OCFS2_MOUNT_HB_NONE);
+                tmp = mopt->mount_opt & (OCFS2_MOUNT_HB_LOCAL |
-        if (hweight32(tmp) != 1) {
+                                         OCFS2_MOUNT_HB_GLOBAL |
-                mlog(ML_ERROR, "Invalid heartbeat mount options\n");
+                                         OCFS2_MOUNT_HB_NONE);
-                status = 0;
+                if (hweight32(tmp) != 1) {
-                goto bail;
+                        mlog(ML_ERROR, "Invalid heartbeat mount options\n");
+                        status = 0;
+                        goto bail;
+                }
        }
        status = 1;
diff --git a/fs/partitions/ldm.c b/fs/partitions/ldm.c
index 789c625c7aa5..b10e3540d5b7 100644
--- a/fs/partitions/ldm.c
+++ b/fs/partitions/ldm.c
@@ -251,6 +251,11 @@ static bool ldm_parse_vmdb (const u8 *data, struct vmdb *vm)
        }
        vm->vblk_size     = get_unaligned_be32(data + 0x08);
+        if (vm->vblk_size == 0) {
+                ldm_error ("Illegal VBLK size");
+                return false;
+        }
        vm->vblk_offset   = get_unaligned_be32(data + 0x0C);
        vm->last_vblk_seq = get_unaligned_be32(data + 0x04);
diff --git a/fs/proc/proc_devtree.c b/fs/proc/proc_devtree.c
index d9396a4fc7ff..927cbd115e53 100644
--- a/fs/proc/proc_devtree.c
+++ b/fs/proc/proc_devtree.c
@@ -233,7 +233,7 @@ void __init proc_device_tree_init(void)
                return;
        root = of_find_node_by_path("/");
        if (root == NULL) {
-                printk(KERN_ERR "/proc/device-tree: can't find root\n");
+                pr_debug("/proc/device-tree: can't find root\n");
                return;
        }
        proc_device_tree_add_node(root, proc_device_tree);
diff --git a/fs/reiserfs/namei.c b/fs/reiserfs/namei.c
index ba5f51ec3458..68fdf45cc6c9 100644
--- a/fs/reiserfs/namei.c
+++ b/fs/reiserfs/namei.c
@@ -771,7 +771,7 @@ static int reiserfs_mkdir(struct inode *dir, struct dentry *dentry, int mode)
                                        EMPTY_DIR_SIZE_V1 : EMPTY_DIR_SIZE,
                                        dentry, inode, &security);
        if (retval) {
-                dir->i_nlink--;
+                DEC_DIR_INODE_NLINK(dir)
                goto out_failed;
        }
diff --git a/fs/sysv/namei.c b/fs/sysv/namei.c
index b427b1208c26..e474fbcf8bde 100644
--- a/fs/sysv/namei.c
+++ b/fs/sysv/namei.c
@@ -245,7 +245,6 @@ static int sysv_rename(struct inode * old_dir, struct dentry * old_dentry,
                new_de = sysv_find_entry(new_dentry, &new_page);
                if (!new_de)
                        goto out_dir;
-                inode_inc_link_count(old_inode);
                sysv_set_link(new_de, new_page, old_inode);
                new_inode->i_ctime = CURRENT_TIME_SEC;
                if (dir_de)
@@ -257,18 +256,15 @@ static int sysv_rename(struct inode * old_dir, struct dentry * old_dentry,
                        if (new_dir->i_nlink >= SYSV_SB(new_dir->i_sb)->s_link_max)
                                goto out_dir;
                }
-                inode_inc_link_count(old_inode);
                err = sysv_add_link(new_dentry, old_inode);
-                if (err) {
+                if (err)
-                        inode_dec_link_count(old_inode);
                        goto out_dir;
-                }
                if (dir_de)
                        inode_inc_link_count(new_dir);
        }
        sysv_delete_entry(old_de, old_page);
-        inode_dec_link_count(old_inode);
+        mark_inode_dirty(old_inode);
        if (dir_de) {
                sysv_set_link(dir_de, dir_page, new_dir);
diff --git a/fs/udf/namei.c b/fs/udf/namei.c
index 2be0f9eb86d2..b7c338d5e9df 100644
--- a/fs/udf/namei.c
+++ b/fs/udf/namei.c
@@ -32,6 +32,8 @@
 #include <linux/crc-itu-t.h>
 #include <linux/exportfs.h>
+enum { UDF_MAX_LINKS = 0xffff };
 static inline int udf_match(int len1, const unsigned char *name1, int len2,
                            const unsigned char *name2)
 {
@@ -650,7 +652,7 @@ static int udf_mkdir(struct inode *dir, struct dentry *dentry, int mode)
        struct udf_inode_info *iinfo;
        err = -EMLINK;
-        if (dir->i_nlink >= (256 << sizeof(dir->i_nlink)) - 1)
+        if (dir->i_nlink >= UDF_MAX_LINKS)
                goto out;
        err = -EIO;
@@ -1034,9 +1036,8 @@ static int udf_link(struct dentry *old_dentry, struct inode *dir,
        struct fileIdentDesc cfi, *fi;
        int err;
-        if (inode->i_nlink >= (256 << sizeof(inode->i_nlink)) - 1) {
+        if (inode->i_nlink >= UDF_MAX_LINKS)
                return -EMLINK;
-        }
        fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err);
        if (!fi) {
@@ -1131,9 +1132,7 @@ static int udf_rename(struct inode *old_dir, struct dentry *old_dentry,
                        goto end_rename;
                retval = -EMLINK;
-                if (!new_inode &&
+                if (!new_inode && new_dir->i_nlink >= UDF_MAX_LINKS)
-                        new_dir->i_nlink >=
-                                (256 << sizeof(new_dir->i_nlink)) - 1)
                        goto end_rename;
        }
        if (!nfi) {
diff --git a/fs/ufs/namei.c b/fs/ufs/namei.c
index 12f39b9e4437..d6f681535eb8 100644
--- a/fs/ufs/namei.c
+++ b/fs/ufs/namei.c
@@ -306,7 +306,6 @@ static int ufs_rename(struct inode *old_dir, struct dentry *old_dentry,
                new_de = ufs_find_entry(new_dir, &new_dentry->d_name, &new_page);
                if (!new_de)
                        goto out_dir;
-                inode_inc_link_count(old_inode);
                ufs_set_link(new_dir, new_de, new_page, old_inode);
                new_inode->i_ctime = CURRENT_TIME_SEC;
                if (dir_de)
@@ -318,12 +317,9 @@ static int ufs_rename(struct inode *old_dir, struct dentry *old_dentry,
                        if (new_dir->i_nlink >= UFS_LINK_MAX)
                                goto out_dir;
                }
-                inode_inc_link_count(old_inode);
                err = ufs_add_link(new_dentry, old_inode);
-                if (err) {
+                if (err)
-                        inode_dec_link_count(old_inode);
                        goto out_dir;
-                }
                if (dir_de)
                        inode_inc_link_count(new_dir);
        }
@@ -331,12 +327,11 @@ static int ufs_rename(struct inode *old_dir, struct dentry *old_dentry,
        /*
         * Like most other Unix systems, set the ctime for inodes on a
         * rename.
-         * inode_dec_link_count() will mark the inode dirty.
         */
        old_inode->i_ctime = CURRENT_TIME_SEC;
        ufs_delete_entry(old_dir, old_de, old_page);
-        inode_dec_link_count(old_inode);
+        mark_inode_dirty(old_inode);
        if (dir_de) {
                ufs_set_link(old_inode, dir_de, dir_page, new_dir);
diff --git a/fs/xfs/linux-2.6/xfs_discard.c b/fs/xfs/linux-2.6/xfs_discard.c
index 05201ae719e5..d61611c88012 100644
--- a/fs/xfs/linux-2.6/xfs_discard.c
+++ b/fs/xfs/linux-2.6/xfs_discard.c
@@ -152,6 +152,8 @@ xfs_ioc_trim(
        if (!capable(CAP_SYS_ADMIN))
                return -XFS_ERROR(EPERM);
+        if (!blk_queue_discard(q))
+                return -XFS_ERROR(EOPNOTSUPP);
        if (copy_from_user(&range, urange, sizeof(range)))
                return -XFS_ERROR(EFAULT);
diff --git a/fs/xfs/linux-2.6/xfs_ioctl.c b/fs/xfs/linux-2.6/xfs_ioctl.c
index f5e2a19e0f8e..0ca0e3c024d7 100644
--- a/fs/xfs/linux-2.6/xfs_ioctl.c
+++ b/fs/xfs/linux-2.6/xfs_ioctl.c
@@ -695,14 +695,19 @@ xfs_ioc_fsgeometry_v1(
        xfs_mount_t             *mp,
        void                    __user *arg)
 {
-        xfs_fsop_geom_v1_t      fsgeo;
+        xfs_fsop_geom_t         fsgeo;
        int                     error;
-        error = xfs_fs_geometry(mp, (xfs_fsop_geom_t *)&fsgeo, 3);
+        error = xfs_fs_geometry(mp, &fsgeo, 3);
        if (error)
                return -error;
-        if (copy_to_user(arg, &fsgeo, sizeof(fsgeo)))
+        /*
+         * Caller should have passed an argument of type
+         * xfs_fsop_geom_v1_t.  This is a proper subset of the
+         * xfs_fsop_geom_t that xfs_fs_geometry() fills in.
+         */
+        if (copy_to_user(arg, &fsgeo, sizeof(xfs_fsop_geom_v1_t)))
                return -XFS_ERROR(EFAULT);
        return 0;
 }
diff --git a/fs/xfs/xfs_fsops.c b/fs/xfs/xfs_fsops.c
index cec89dd5d7d2..85668efb3e3e 100644
--- a/fs/xfs/xfs_fsops.c
+++ b/fs/xfs/xfs_fsops.c
@@ -53,6 +53,9 @@ xfs_fs_geometry(
        xfs_fsop_geom_t         *geo,
        int                     new_version)
 {
+        memset(geo, 0, sizeof(*geo));
        geo->blocksize = mp->m_sb.sb_blocksize;
        geo->rtextsize = mp->m_sb.sb_rextsize;
        geo->agblocks = mp->m_sb.sb_agblocks;
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index 31b6188df221..b4bfe338ea0e 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -4,6 +4,8 @@
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_MMU
+#include <linux/mm_types.h>
 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 extern int ptep_set_access_flags(struct vm_area_struct *vma,
                                 unsigned long address, pte_t *ptep,
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index fe29aadb129d..348843b80150 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1101,7 +1101,7 @@ struct drm_device {
        struct platform_device *platformdev; /**< Platform device struture */
        struct drm_sg_mem *sg;  /**< Scatter gather memory */
-        int num_crtcs;                  /**< Number of CRTCs on this device */
+        unsigned int num_crtcs;                  /**< Number of CRTCs on this device */
        void *dev_private;              /**< device private data */
        void *mm_private;
        struct address_space *dev_mapping;
diff --git a/include/keys/rxrpc-type.h b/include/keys/rxrpc-type.h
index 5cb86c307f5d..fc4875433817 100644
--- a/include/keys/rxrpc-type.h
+++ b/include/keys/rxrpc-type.h
@@ -99,7 +99,6 @@ struct rxrpc_key_token {
 * structure of raw payloads passed to add_key() or instantiate key
 */
 struct rxrpc_key_data_v1 {
-        u32             kif_version;            /* 1 */
        u16             security_index;
        u16             ticket_length;
        u32             expiry;                 /* time_t */
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index 4d18ff34670a..d5063e1b5555 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -699,7 +699,7 @@ extern void blk_start_queue(struct request_queue *q);
 extern void blk_stop_queue(struct request_queue *q);
 extern void blk_sync_queue(struct request_queue *q);
 extern void __blk_stop_queue(struct request_queue *q);
-extern void __blk_run_queue(struct request_queue *);
+extern void __blk_run_queue(struct request_queue *q, bool force_kblockd);
 extern void blk_run_queue(struct request_queue *);
 extern int blk_rq_map_user(struct request_queue *, struct request *,
                           struct rq_map_data *, void __user *, unsigned long,
@@ -1088,7 +1088,6 @@ static inline void put_dev_sector(Sector p)
 struct work_struct;
 int kblockd_schedule_work(struct request_queue *q, struct work_struct *work);
-int kblockd_schedule_delayed_work(struct request_queue *q, struct delayed_work *dwork, unsigned long delay);
 #ifdef CONFIG_BLK_CGROUP
 /*
@@ -1136,7 +1135,6 @@ static inline uint64_t rq_io_start_time_ns(struct request *req)
 extern int blk_throtl_init(struct request_queue *q);
 extern void blk_throtl_exit(struct request_queue *q);
 extern int blk_throtl_bio(struct request_queue *q, struct bio **bio);
-extern void throtl_schedule_delayed_work(struct request_queue *q, unsigned long delay);
 extern void throtl_shutdown_timer_wq(struct request_queue *q);
 #else /* CONFIG_BLK_DEV_THROTTLING */
 static inline int blk_throtl_bio(struct request_queue *q, struct bio **bio)
@@ -1146,7 +1144,6 @@ static inline int blk_throtl_bio(struct request_queue *q, struct bio **bio)
 static inline int blk_throtl_init(struct request_queue *q) { return 0; }
 static inline int blk_throtl_exit(struct request_queue *q) { return 0; }
-static inline void throtl_schedule_delayed_work(struct request_queue *q, unsigned long delay) {}
 static inline void throtl_shutdown_timer_wq(struct request_queue *q) {}
 #endif /* CONFIG_BLK_DEV_THROTTLING */
diff --git a/include/linux/blktrace_api.h b/include/linux/blktrace_api.h
index 3395cf7130f5..b22fb0d3db0f 100644
--- a/include/linux/blktrace_api.h
+++ b/include/linux/blktrace_api.h
@@ -245,7 +245,6 @@ static inline int blk_cmd_buf_len(struct request *rq)
 extern void blk_dump_cmd(char *buf, struct request *rq);
 extern void blk_fill_rwbs(char *rwbs, u32 rw, int bytes);
-extern void blk_fill_rwbs_rq(char *rwbs, struct request *rq);
 #endif /* CONFIG_EVENT_TRACING && CONFIG_BLOCK */
diff --git a/include/linux/ceph/messenger.h b/include/linux/ceph/messenger.h
index c3011beac30d..31d91a64838b 100644
--- a/include/linux/ceph/messenger.h
+++ b/include/linux/ceph/messenger.h
@@ -123,6 +123,7 @@ struct ceph_msg_pos {
 #define SOCK_CLOSED     11 /* socket state changed to closed */
 #define OPENING         13 /* open connection w/ (possibly new) peer */
 #define DEAD            14 /* dead, about to kfree */
+#define BACKOFF         15
 /*
 * A single connection with another host.
@@ -160,7 +161,6 @@ struct ceph_connection {
        struct list_head out_queue;
        struct list_head out_sent;   /* sending or sent but unacked */
        u64 out_seq;                 /* last message queued for send */
-        bool out_keepalive_pending;
        u64 in_seq, in_seq_acked;  /* last message received, acked */
diff --git a/include/linux/dcbnl.h b/include/linux/dcbnl.h
index 68cd248f6d3e..66900e3c6eb1 100644
--- a/include/linux/dcbnl.h
+++ b/include/linux/dcbnl.h
@@ -101,8 +101,8 @@ struct ieee_pfc {
 */
 struct dcb_app {
        __u8    selector;
-        __u32   protocol;
        __u8    priority;
+        __u16   protocol;
 };
 struct dcbmsg {
diff --git a/include/linux/fs.h b/include/linux/fs.h
index bd3215940c37..e38b50a4b9d2 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -649,6 +649,7 @@ struct address_space {
        spinlock_t              private_lock;   /* for use by the address_space */
        struct list_head        private_list;   /* ditto */
        struct address_space    *assoc_mapping; /* ditto */
+        struct mutex            unmap_mutex;    /* to protect unmapping */
 } __attribute__((aligned(sizeof(long))));
        /*
         * On most architectures that alignment is already the case; but
@@ -2139,7 +2140,7 @@ extern void check_disk_size_change(struct gendisk *disk,
                                   struct block_device *bdev);
 extern int revalidate_disk(struct gendisk *);
 extern int check_disk_change(struct block_device *);
-extern int __invalidate_device(struct block_device *);
+extern int __invalidate_device(struct block_device *, bool);
 extern int invalidate_partition(struct gendisk *, int);
 #endif
 unsigned long invalidate_mapping_pages(struct address_space *mapping,
@@ -2225,6 +2226,7 @@ extern loff_t vfs_llseek(struct file *file, loff_t offset, int origin);
 extern int inode_init_always(struct super_block *, struct inode *);
 extern void inode_init_once(struct inode *);
+extern void address_space_init_once(struct address_space *mapping);
 extern void ihold(struct inode * inode);
 extern void iput(struct inode *);
 extern struct inode * igrab(struct inode *);
diff --git a/include/linux/gfp.h b/include/linux/gfp.h
index 0b84c61607e8..dca31761b311 100644
--- a/include/linux/gfp.h
+++ b/include/linux/gfp.h
@@ -332,16 +332,19 @@ alloc_pages(gfp_t gfp_mask, unsigned int order)
        return alloc_pages_current(gfp_mask, order);
 }
 extern struct page *alloc_pages_vma(gfp_t gfp_mask, int order,
-                        struct vm_area_struct *vma, unsigned long addr);
+                        struct vm_area_struct *vma, unsigned long addr,
+                        int node);
 #else
 #define alloc_pages(gfp_mask, order) \
                alloc_pages_node(numa_node_id(), gfp_mask, order)
-#define alloc_pages_vma(gfp_mask, order, vma, addr)     \
+#define alloc_pages_vma(gfp_mask, order, vma, addr, node)       \
        alloc_pages(gfp_mask, order)
 #endif
 #define alloc_page(gfp_mask) alloc_pages(gfp_mask, 0)
-#define alloc_page_vma(gfp_mask, vma, addr)     \
+#define alloc_page_vma(gfp_mask, vma, addr)                     \
-        alloc_pages_vma(gfp_mask, 0, vma, addr)
+        alloc_pages_vma(gfp_mask, 0, vma, addr, numa_node_id())
+#define alloc_page_vma_node(gfp_mask, vma, addr, node)          \
+        alloc_pages_vma(gfp_mask, 0, vma, addr, node)
 extern unsigned long __get_free_pages(gfp_t gfp_mask, unsigned int order);
 extern unsigned long get_zeroed_page(gfp_t gfp_mask);
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index 3fd36845ca45..ef4f0b6083a3 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -71,6 +71,7 @@ struct wm8994 {
        u16 irq_masks_cache[WM8994_NUM_IRQ_REGS];
        /* Used over suspend/resume */
+        bool suspended;
        u16 ldo_regs[WM8994_NUM_LDO_REGS];
        u16 gpio_regs[WM8994_NUM_GPIO_REGS];
diff --git a/include/linux/pm.h b/include/linux/pm.h
index dd9c7ab38270..21415cc91cbb 100644
--- a/include/linux/pm.h
+++ b/include/linux/pm.h
@@ -431,6 +431,8 @@ struct dev_pm_info {
        struct list_head        entry;
        struct completion       completion;
        struct wakeup_source    *wakeup;
+#else
+        unsigned int            should_wakeup:1;
 #endif
 #ifdef CONFIG_PM_RUNTIME
        struct timer_list       suspend_timer;
diff --git a/include/linux/pm_wakeup.h b/include/linux/pm_wakeup.h
index 9cff00dd6b63..03a67db03d01 100644
--- a/include/linux/pm_wakeup.h
+++ b/include/linux/pm_wakeup.h
@@ -109,11 +109,6 @@ static inline bool device_can_wakeup(struct device *dev)
        return dev->power.can_wakeup;
 }
-static inline bool device_may_wakeup(struct device *dev)
-{
-        return false;
-}
 static inline struct wakeup_source *wakeup_source_create(const char *name)
 {
        return NULL;
@@ -134,24 +129,32 @@ static inline void wakeup_source_unregister(struct wakeup_source *ws) {}
 static inline int device_wakeup_enable(struct device *dev)
 {
-        return -EINVAL;
+        dev->power.should_wakeup = true;
+        return 0;
 }
 static inline int device_wakeup_disable(struct device *dev)
 {
+        dev->power.should_wakeup = false;
        return 0;
 }
-static inline int device_init_wakeup(struct device *dev, bool val)
+static inline int device_set_wakeup_enable(struct device *dev, bool enable)
 {
-        dev->power.can_wakeup = val;
+        dev->power.should_wakeup = enable;
-        return val ? -EINVAL : 0;
+        return 0;
 }
+static inline int device_init_wakeup(struct device *dev, bool val)
+{
+        device_set_wakeup_capable(dev, val);
+        device_set_wakeup_enable(dev, val);
+        return 0;
+}
-static inline int device_set_wakeup_enable(struct device *dev, bool enable)
+static inline bool device_may_wakeup(struct device *dev)
 {
-        return -EINVAL;
+        return dev->power.can_wakeup && dev->power.should_wakeup;
 }
 static inline void __pm_stay_awake(struct wakeup_source *ws) {}
diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h
index 092a04f874a8..a1147e5dd245 100644
--- a/include/linux/ptrace.h
+++ b/include/linux/ptrace.h
@@ -102,11 +102,8 @@
 extern long arch_ptrace(struct task_struct *child, long request,
                        unsigned long addr, unsigned long data);
-extern int ptrace_traceme(void);
 extern int ptrace_readdata(struct task_struct *tsk, unsigned long src, char __user *dst, int len);
 extern int ptrace_writedata(struct task_struct *tsk, char __user *src, unsigned long dst, int len);
-extern int ptrace_attach(struct task_struct *tsk);
-extern int ptrace_detach(struct task_struct *, unsigned int);
 extern void ptrace_disable(struct task_struct *);
 extern int ptrace_check_attach(struct task_struct *task, int kill);
 extern int ptrace_request(struct task_struct *child, long request,
diff --git a/include/linux/rio_regs.h b/include/linux/rio_regs.h
index d63dcbaea169..9026b30238f3 100644
--- a/include/linux/rio_regs.h
+++ b/include/linux/rio_regs.h
@@ -14,10 +14,12 @@
 #define LINUX_RIO_REGS_H
 /*
- * In RapidIO, each device has a 2MB configuration space that is
+ * In RapidIO, each device has a 16MB configuration space that is
 * accessed via maintenance transactions.  Portions of configuration
 * space are standardized and/or reserved.
 */
+#define RIO_MAINT_SPACE_SZ      0x1000000 /* 16MB of RapidIO mainenance space */
 #define RIO_DEV_ID_CAR          0x00    /* [I] Device Identity CAR */
 #define RIO_DEV_INFO_CAR        0x04    /* [I] Device Information CAR */
 #define RIO_ASM_ID_CAR          0x08    /* [I] Assembly Identity CAR */
diff --git a/include/linux/thermal.h b/include/linux/thermal.h
index 8651556dbd52..d3ec89fb4122 100644
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -172,6 +172,14 @@ void thermal_zone_device_update(struct thermal_zone_device *);
 struct thermal_cooling_device *thermal_cooling_device_register(char *, void *,
                const struct thermal_cooling_device_ops *);
 void thermal_cooling_device_unregister(struct thermal_cooling_device *);
+#ifdef CONFIG_NET
 extern int generate_netlink_event(u32 orig, enum events event);
+#else
+static inline int generate_netlink_event(u32 orig, enum events event)
+{
+        return 0;
+}
+#endif
 #endif /* __THERMAL_H__ */
diff --git a/include/net/ipv6.h b/include/net/ipv6.h
index 4a3cd2cd2f5e..96e50e0ce3ca 100644
--- a/include/net/ipv6.h
+++ b/include/net/ipv6.h
@@ -89,6 +89,18 @@
 #define IPV6_ADDR_SCOPE_GLOBAL          0x0e
 /*
+ *      Addr flags
+ */
+#ifdef __KERNEL__
+#define IPV6_ADDR_MC_FLAG_TRANSIENT(a)  \
+        ((a)->s6_addr[1] & 0x10)
+#define IPV6_ADDR_MC_FLAG_PREFIX(a)     \
+        ((a)->s6_addr[1] & 0x20)
+#define IPV6_ADDR_MC_FLAG_RENDEZVOUS(a) \
+        ((a)->s6_addr[1] & 0x40)
+#endif
+/*
 *      fragmentation header
 */
diff --git a/include/net/netfilter/nf_tproxy_core.h b/include/net/netfilter/nf_tproxy_core.h
index cd85b3bc8327..e505358d8999 100644
--- a/include/net/netfilter/nf_tproxy_core.h
+++ b/include/net/netfilter/nf_tproxy_core.h
@@ -201,18 +201,8 @@ nf_tproxy_get_sock_v6(struct net *net, const u8 protocol,
 }
 #endif
-static inline void
-nf_tproxy_put_sock(struct sock *sk)
-{
-        /* TIME_WAIT inet sockets have to be handled differently */
-        if ((sk->sk_protocol == IPPROTO_TCP) && (sk->sk_state == TCP_TIME_WAIT))
-                inet_twsk_put(inet_twsk(sk));
-        else
-                sock_put(sk);
-}
 /* assign a socket to the skb -- consumes sk */
-int
+void
 nf_tproxy_assign_sock(struct sk_buff *skb, struct sock *sk);
 #endif
diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h
index 160a407c1963..04f8556313d5 100644
--- a/include/net/sch_generic.h
+++ b/include/net/sch_generic.h
@@ -199,7 +199,7 @@ struct tcf_proto {
 struct qdisc_skb_cb {
        unsigned int            pkt_len;
-        char                    data[];
+        long                    data[];
 };
 static inline int qdisc_qlen(struct Qdisc *q)
diff --git a/include/pcmcia/ds.h b/include/pcmcia/ds.h
index 8479b66c067b..3fd5064dd43a 100644
--- a/include/pcmcia/ds.h
+++ b/include/pcmcia/ds.h
@@ -261,6 +261,7 @@ void pcmcia_disable_device(struct pcmcia_device *p_dev);
 #define CONF_ENABLE_ESR         0x0008
 #define CONF_ENABLE_IOCARD      0x0010 /* auto-enabled if IO resources or IRQ
                                        * (CONF_ENABLE_IRQ) in use */
+#define CONF_ENABLE_ZVCARD      0x0020
 /* flags used by pcmcia_loop_config() autoconfiguration */
 #define CONF_AUTO_CHECK_VCC     0x0100 /* check for matching Vcc? */
diff --git a/include/sound/wm8903.h b/include/sound/wm8903.h
index b4a0db2307ef..1eeebd534f7e 100644
--- a/include/sound/wm8903.h
+++ b/include/sound/wm8903.h
@@ -17,13 +17,9 @@
 /*
 * R6 (0x06) - Mic Bias Control 0
 */
-#define WM8903_MICDET_HYST_ENA                  0x0080  /* MICDET_HYST_ENA */
+#define WM8903_MICDET_THR_MASK                  0x0030  /* MICDET_THR - [5:4] */
-#define WM8903_MICDET_HYST_ENA_MASK             0x0080  /* MICDET_HYST_ENA */
+#define WM8903_MICDET_THR_SHIFT                      4  /* MICDET_THR - [5:4] */
-#define WM8903_MICDET_HYST_ENA_SHIFT                 7  /* MICDET_HYST_ENA */
+#define WM8903_MICDET_THR_WIDTH                      2  /* MICDET_THR - [5:4] */
-#define WM8903_MICDET_HYST_ENA_WIDTH                 1  /* MICDET_HYST_ENA */
-#define WM8903_MICDET_THR_MASK                  0x0070  /* MICDET_THR - [6:4] */
-#define WM8903_MICDET_THR_SHIFT                      4  /* MICDET_THR - [6:4] */
-#define WM8903_MICDET_THR_WIDTH                      3  /* MICDET_THR - [6:4] */
 #define WM8903_MICSHORT_THR_MASK                0x000C  /* MICSHORT_THR - [3:2] */
 #define WM8903_MICSHORT_THR_SHIFT                    2  /* MICSHORT_THR - [3:2] */
 #define WM8903_MICSHORT_THR_WIDTH                    2  /* MICSHORT_THR - [3:2] */
diff --git a/include/trace/events/block.h b/include/trace/events/block.h
index aba421d68f6f..78f18adb49c8 100644
--- a/include/trace/events/block.h
+++ b/include/trace/events/block.h
@@ -31,7 +31,7 @@ DECLARE_EVENT_CLASS(block_rq_with_error,
                                        0 : blk_rq_sectors(rq);
                __entry->errors    = rq->errors;
-                blk_fill_rwbs_rq(__entry->rwbs, rq);
+                blk_fill_rwbs(__entry->rwbs, rq->cmd_flags, blk_rq_bytes(rq));
                blk_dump_cmd(__get_str(cmd), rq);
        ),
@@ -118,7 +118,7 @@ DECLARE_EVENT_CLASS(block_rq,
                __entry->bytes     = (rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
                                        blk_rq_bytes(rq) : 0;
-                blk_fill_rwbs_rq(__entry->rwbs, rq);
+                blk_fill_rwbs(__entry->rwbs, rq->cmd_flags, blk_rq_bytes(rq));
                blk_dump_cmd(__get_str(cmd), rq);
                memcpy(__entry->comm, current->comm, TASK_COMM_LEN);
        ),
@@ -563,7 +563,7 @@ TRACE_EVENT(block_rq_remap,
                __entry->nr_sector      = blk_rq_sectors(rq);
                __entry->old_dev        = dev;
                __entry->old_sector     = from;
-                blk_fill_rwbs_rq(__entry->rwbs, rq);
+                blk_fill_rwbs(__entry->rwbs, rq->cmd_flags, blk_rq_bytes(rq));
        ),
        TP_printk("%d,%d %s %llu + %u <- (%d,%d) %llu",
diff --git a/kernel/cpuset.c b/kernel/cpuset.c
index 4349935c2ad8..e92e98189032 100644
--- a/kernel/cpuset.c
+++ b/kernel/cpuset.c
@@ -1575,8 +1575,10 @@ static int cpuset_write_resmask(struct cgroup *cgrp, struct cftype *cft,
                return -ENODEV;
        trialcs = alloc_trial_cpuset(cs);
-        if (!trialcs)
+        if (!trialcs) {
-                return -ENOMEM;
+                retval = -ENOMEM;
+                goto out;
+        }
        switch (cft->private) {
        case FILE_CPULIST:
@@ -1591,6 +1593,7 @@ static int cpuset_write_resmask(struct cgroup *cgrp, struct cftype *cft,
        }
        free_trial_cpuset(trialcs);
+out:
        cgroup_unlock();
        return retval;
 }
diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h
index 4571ae7e085a..99c3bc8a6fb4 100644
--- a/kernel/irq/internals.h
+++ b/kernel/irq/internals.h
@@ -3,6 +3,12 @@
 */
 #include <linux/irqdesc.h>
+#ifdef CONFIG_SPARSE_IRQ
+# define IRQ_BITMAP_BITS        (NR_IRQS + 8196)
+#else
+# define IRQ_BITMAP_BITS        NR_IRQS
+#endif
 extern int noirqdebug;
 #define irq_data_to_desc(data)  container_of(data, struct irq_desc, irq_data)
diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c
index 282f20230e67..2039bea31bdf 100644
--- a/kernel/irq/irqdesc.c
+++ b/kernel/irq/irqdesc.c
@@ -94,7 +94,7 @@ int nr_irqs = NR_IRQS;
 EXPORT_SYMBOL_GPL(nr_irqs);
 static DEFINE_MUTEX(sparse_irq_lock);
-static DECLARE_BITMAP(allocated_irqs, NR_IRQS);
+static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS);
 #ifdef CONFIG_SPARSE_IRQ
@@ -217,6 +217,15 @@ int __init early_irq_init(void)
        initcnt = arch_probe_nr_irqs();
        printk(KERN_INFO "NR_IRQS:%d nr_irqs:%d %d\n", NR_IRQS, nr_irqs, initcnt);
+        if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS))
+                nr_irqs = IRQ_BITMAP_BITS;
+        if (WARN_ON(initcnt > IRQ_BITMAP_BITS))
+                initcnt = IRQ_BITMAP_BITS;
+        if (initcnt > nr_irqs)
+                nr_irqs = initcnt;
        for (i = 0; i < initcnt; i++) {
                desc = alloc_desc(i, node);
                set_bit(i, allocated_irqs);
diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c
index 0caa59f747dd..9033c1c70828 100644
--- a/kernel/irq/manage.c
+++ b/kernel/irq/manage.c
@@ -1100,7 +1100,7 @@ int request_threaded_irq(unsigned int irq, irq_handler_t handler,
        if (retval)
                kfree(action);
-#ifdef CONFIG_DEBUG_SHIRQ
+#ifdef CONFIG_DEBUG_SHIRQ_FIXME
        if (!retval && (irqflags & IRQF_SHARED)) {
                /*
                 * It's a shared IRQ -- the driver ought to be prepared for it
diff --git a/kernel/irq/resend.c b/kernel/irq/resend.c
index 891115a929aa..dc49358b73fa 100644
--- a/kernel/irq/resend.c
+++ b/kernel/irq/resend.c
@@ -23,7 +23,7 @@
 #ifdef CONFIG_HARDIRQS_SW_RESEND
 /* Bitmap to handle software resend of interrupts: */
-static DECLARE_BITMAP(irqs_resend, NR_IRQS);
+static DECLARE_BITMAP(irqs_resend, IRQ_BITMAP_BITS);
 /*
 * Run software resends of IRQ's
diff --git a/kernel/perf_event.c b/kernel/perf_event.c
index 999835b6112b..656222fcf767 100644
--- a/kernel/perf_event.c
+++ b/kernel/perf_event.c
@@ -782,6 +782,10 @@ retry:
        raw_spin_unlock_irq(&ctx->lock);
 }
+#define MAX_INTERRUPTS (~0ULL)
+static void perf_log_throttle(struct perf_event *event, int enable);
 static int
 event_sched_in(struct perf_event *event,
                 struct perf_cpu_context *cpuctx,
@@ -794,6 +798,17 @@ event_sched_in(struct perf_event *event,
        event->state = PERF_EVENT_STATE_ACTIVE;
        event->oncpu = smp_processor_id();
+        /*
+         * Unthrottle events, since we scheduled we might have missed several
+         * ticks already, also for a heavily scheduling task there is little
+         * guarantee it'll get a tick in a timely manner.
+         */
+        if (unlikely(event->hw.interrupts == MAX_INTERRUPTS)) {
+                perf_log_throttle(event, 1);
+                event->hw.interrupts = 0;
+        }
        /*
         * The new state must be visible before we turn it on in the hardware:
         */
@@ -1596,10 +1611,6 @@ void __perf_event_task_sched_in(struct task_struct *task)
        }
 }
-#define MAX_INTERRUPTS (~0ULL)
-static void perf_log_throttle(struct perf_event *event, int enable);
 static u64 perf_calculate_period(struct perf_event *event, u64 nsec, u64 count)
 {
        u64 frequency = event->attr.sample_freq;
diff --git a/kernel/ptrace.c b/kernel/ptrace.c
index 1708b1e2972d..e2302e40b360 100644
--- a/kernel/ptrace.c
+++ b/kernel/ptrace.c
@@ -163,7 +163,7 @@ bool ptrace_may_access(struct task_struct *task, unsigned int mode)
        return !err;
 }
-int ptrace_attach(struct task_struct *task)
+static int ptrace_attach(struct task_struct *task)
 {
        int retval;
@@ -219,7 +219,7 @@ out:
 * Performs checks and sets PT_PTRACED.
 * Should be used by all ptrace implementations for PTRACE_TRACEME.
 */
-int ptrace_traceme(void)
+static int ptrace_traceme(void)
 {
        int ret = -EPERM;
@@ -293,7 +293,7 @@ static bool __ptrace_detach(struct task_struct *tracer, struct task_struct *p)
        return false;
 }
-int ptrace_detach(struct task_struct *child, unsigned int data)
+static int ptrace_detach(struct task_struct *child, unsigned int data)
 {
        bool dead = false;
diff --git a/kernel/time/tick-broadcast.c b/kernel/time/tick-broadcast.c
index 48b2761b5668..a3b5aff62606 100644
--- a/kernel/time/tick-broadcast.c
+++ b/kernel/time/tick-broadcast.c
@@ -600,4 +600,14 @@ int tick_broadcast_oneshot_active(void)
        return tick_broadcast_device.mode == TICKDEV_MODE_ONESHOT;
 }
+/*
+ * Check whether the broadcast device supports oneshot.
+ */
+bool tick_broadcast_oneshot_available(void)
+{
+        struct clock_event_device *bc = tick_broadcast_device.evtdev;
+        return bc ? bc->features & CLOCK_EVT_FEAT_ONESHOT : false;
+}
 #endif
diff --git a/kernel/time/tick-common.c b/kernel/time/tick-common.c
index 051bc80a0c43..ed228ef6f6b8 100644
--- a/kernel/time/tick-common.c
+++ b/kernel/time/tick-common.c
@@ -51,7 +51,11 @@ int tick_is_oneshot_available(void)
 {
        struct clock_event_device *dev = __this_cpu_read(tick_cpu_device.evtdev);
-        return dev && (dev->features & CLOCK_EVT_FEAT_ONESHOT);
+        if (!dev || !(dev->features & CLOCK_EVT_FEAT_ONESHOT))
+                return 0;
+        if (!(dev->features & CLOCK_EVT_FEAT_C3STOP))
+                return 1;
+        return tick_broadcast_oneshot_available();
 }
 /*
diff --git a/kernel/time/tick-internal.h b/kernel/time/tick-internal.h
index 290eefbc1f60..f65d3a723a64 100644
--- a/kernel/time/tick-internal.h
+++ b/kernel/time/tick-internal.h
@@ -36,6 +36,7 @@ extern void tick_shutdown_broadcast_oneshot(unsigned int *cpup);
 extern int tick_resume_broadcast_oneshot(struct clock_event_device *bc);
 extern int tick_broadcast_oneshot_active(void);
 extern void tick_check_oneshot_broadcast(int cpu);
+bool tick_broadcast_oneshot_available(void);
 # else /* BROADCAST */
 static inline void tick_broadcast_setup_oneshot(struct clock_event_device *bc)
 {
@@ -46,6 +47,7 @@ static inline void tick_broadcast_switch_to_oneshot(void) { }
 static inline void tick_shutdown_broadcast_oneshot(unsigned int *cpup) { }
 static inline int tick_broadcast_oneshot_active(void) { return 0; }
 static inline void tick_check_oneshot_broadcast(int cpu) { }
+static inline bool tick_broadcast_oneshot_available(void) { return true; }
 # endif /* !BROADCAST */
 #else /* !ONESHOT */
@@ -76,6 +78,7 @@ static inline int tick_resume_broadcast_oneshot(struct clock_event_device *bc)
        return 0;
 }
 static inline int tick_broadcast_oneshot_active(void) { return 0; }
+static inline bool tick_broadcast_oneshot_available(void) { return false; }
 #endif /* !TICK_ONESHOT */
 /*
diff --git a/kernel/trace/blktrace.c b/kernel/trace/blktrace.c
index d95721f33702..cbafed7d4f38 100644
--- a/kernel/trace/blktrace.c
+++ b/kernel/trace/blktrace.c
@@ -1827,21 +1827,5 @@ void blk_fill_rwbs(char *rwbs, u32 rw, int bytes)
        rwbs[i] = '\0';
 }
-void blk_fill_rwbs_rq(char *rwbs, struct request *rq)
-{
-        int rw = rq->cmd_flags & 0x03;
-        int bytes;
-        if (rq->cmd_flags & REQ_DISCARD)
-                rw |= REQ_DISCARD;
-        if (rq->cmd_flags & REQ_SECURE)
-                rw |= REQ_SECURE;
-        bytes = blk_rq_bytes(rq);
-        blk_fill_rwbs(rwbs, rw, bytes);
-}
 #endif /* CONFIG_EVENT_TRACING */
diff --git a/lib/nlattr.c b/lib/nlattr.c
index 5021cbc34411..ac09f2226dc7 100644
--- a/lib/nlattr.c
+++ b/lib/nlattr.c
@@ -148,7 +148,7 @@ nla_policy_len(const struct nla_policy *p, int n)
 {
        int i, len = 0;
-        for (i = 0; i < n; i++) {
+        for (i = 0; i < n; i++, p++) {
                if (p->len)
                        len += nla_total_size(p->len);
                else if (nla_attr_minlen[p->type])
diff --git a/lib/swiotlb.c b/lib/swiotlb.c
index c47bbe11b804..93ca08b8a451 100644
--- a/lib/swiotlb.c
+++ b/lib/swiotlb.c
@@ -686,8 +686,10 @@ dma_addr_t swiotlb_map_page(struct device *dev, struct page *page,
        /*
         * Ensure that the address returned is DMA'ble
         */
-        if (!dma_capable(dev, dev_addr, size))
+        if (!dma_capable(dev, dev_addr, size)) {
-                panic("map_single: bounce buffer is not DMA'ble");
+                swiotlb_tbl_unmap_single(dev, map, size, dir);
+                dev_addr = swiotlb_virt_to_bus(dev, io_tlb_overflow_buffer);
+        }
        return dev_addr;
 }
diff --git a/mm/huge_memory.c b/mm/huge_memory.c
index 3e29781ee762..dbe99a5f2073 100644
--- a/mm/huge_memory.c
+++ b/mm/huge_memory.c
@@ -650,10 +650,10 @@ static inline gfp_t alloc_hugepage_gfpmask(int defrag)
 static inline struct page *alloc_hugepage_vma(int defrag,
                                              struct vm_area_struct *vma,
-                                              unsigned long haddr)
+                                              unsigned long haddr, int nd)
 {
        return alloc_pages_vma(alloc_hugepage_gfpmask(defrag),
-                               HPAGE_PMD_ORDER, vma, haddr);
+                               HPAGE_PMD_ORDER, vma, haddr, nd);
 }
 #ifndef CONFIG_NUMA
@@ -678,7 +678,7 @@ int do_huge_pmd_anonymous_page(struct mm_struct *mm, struct vm_area_struct *vma,
                if (unlikely(khugepaged_enter(vma)))
                        return VM_FAULT_OOM;
                page = alloc_hugepage_vma(transparent_hugepage_defrag(vma),
-                                          vma, haddr);
+                                          vma, haddr, numa_node_id());
                if (unlikely(!page))
                        goto out;
                if (unlikely(mem_cgroup_newpage_charge(page, mm, GFP_KERNEL))) {
@@ -799,8 +799,8 @@ static int do_huge_pmd_wp_page_fallback(struct mm_struct *mm,
        }
        for (i = 0; i < HPAGE_PMD_NR; i++) {
-                pages[i] = alloc_page_vma(GFP_HIGHUSER_MOVABLE,
+                pages[i] = alloc_page_vma_node(GFP_HIGHUSER_MOVABLE,
-                                          vma, address);
+                                               vma, address, page_to_nid(page));
                if (unlikely(!pages[i] ||
                             mem_cgroup_newpage_charge(pages[i], mm,
                                                       GFP_KERNEL))) {
@@ -902,7 +902,7 @@ int do_huge_pmd_wp_page(struct mm_struct *mm, struct vm_area_struct *vma,
        if (transparent_hugepage_enabled(vma) &&
            !transparent_hugepage_debug_cow())
                new_page = alloc_hugepage_vma(transparent_hugepage_defrag(vma),
-                                              vma, haddr);
+                                              vma, haddr, numa_node_id());
        else
                new_page = NULL;
@@ -1745,7 +1745,8 @@ static void __collapse_huge_page_copy(pte_t *pte, struct page *page,
 static void collapse_huge_page(struct mm_struct *mm,
                               unsigned long address,
                               struct page **hpage,
-                               struct vm_area_struct *vma)
+                               struct vm_area_struct *vma,
+                               int node)
 {
        pgd_t *pgd;
        pud_t *pud;
@@ -1773,7 +1774,8 @@ static void collapse_huge_page(struct mm_struct *mm,
         * mmap_sem in read mode is good idea also to allow greater
         * scalability.
         */
-        new_page = alloc_hugepage_vma(khugepaged_defrag(), vma, address);
+        new_page = alloc_hugepage_vma(khugepaged_defrag(), vma, address,
+                                      node);
        if (unlikely(!new_page)) {
                up_read(&mm->mmap_sem);
                *hpage = ERR_PTR(-ENOMEM);
@@ -1919,6 +1921,7 @@ static int khugepaged_scan_pmd(struct mm_struct *mm,
        struct page *page;
        unsigned long _address;
        spinlock_t *ptl;
+        int node = -1;
        VM_BUG_ON(address & ~HPAGE_PMD_MASK);
@@ -1949,6 +1952,13 @@ static int khugepaged_scan_pmd(struct mm_struct *mm,
                page = vm_normal_page(vma, _address, pteval);
                if (unlikely(!page))
                        goto out_unmap;
+                /*
+                 * Chose the node of the first page. This could
+                 * be more sophisticated and look at more pages,
+                 * but isn't for now.
+                 */
+                if (node == -1)
+                        node = page_to_nid(page);
                VM_BUG_ON(PageCompound(page));
                if (!PageLRU(page) || PageLocked(page) || !PageAnon(page))
                        goto out_unmap;
@@ -1965,7 +1975,7 @@ out_unmap:
        pte_unmap_unlock(pte, ptl);
        if (ret)
                /* collapse_huge_page will return with the mmap_sem released */
-                collapse_huge_page(mm, address, hpage, vma);
+                collapse_huge_page(mm, address, hpage, vma, node);
 out:
        return ret;
 }
diff --git a/mm/memory.c b/mm/memory.c
index 8e8c18324863..5823698c2b71 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -2648,6 +2648,7 @@ void unmap_mapping_range(struct address_space *mapping,
                details.last_index = ULONG_MAX;
        details.i_mmap_lock = &mapping->i_mmap_lock;
+        mutex_lock(&mapping->unmap_mutex);
        spin_lock(&mapping->i_mmap_lock);
        /* Protect against endless unmapping loops */
@@ -2664,6 +2665,7 @@ void unmap_mapping_range(struct address_space *mapping,
        if (unlikely(!list_empty(&mapping->i_mmap_nonlinear)))
                unmap_mapping_range_list(&mapping->i_mmap_nonlinear, &details);
        spin_unlock(&mapping->i_mmap_lock);
+        mutex_unlock(&mapping->unmap_mutex);
 }
 EXPORT_SYMBOL(unmap_mapping_range);
diff --git a/mm/mempolicy.c b/mm/mempolicy.c
index 368fc9d23610..b53ec99f1428 100644
--- a/mm/mempolicy.c
+++ b/mm/mempolicy.c
@@ -1524,10 +1524,9 @@ static nodemask_t *policy_nodemask(gfp_t gfp, struct mempolicy *policy)
 }
 /* Return a zonelist indicated by gfp for node representing a mempolicy */
-static struct zonelist *policy_zonelist(gfp_t gfp, struct mempolicy *policy)
+static struct zonelist *policy_zonelist(gfp_t gfp, struct mempolicy *policy,
+        int nd)
 {
-        int nd = numa_node_id();
        switch (policy->mode) {
        case MPOL_PREFERRED:
                if (!(policy->flags & MPOL_F_LOCAL))
@@ -1679,7 +1678,7 @@ struct zonelist *huge_zonelist(struct vm_area_struct *vma, unsigned long addr,
                zl = node_zonelist(interleave_nid(*mpol, vma, addr,
                                huge_page_shift(hstate_vma(vma))), gfp_flags);
        } else {
-                zl = policy_zonelist(gfp_flags, *mpol);
+                zl = policy_zonelist(gfp_flags, *mpol, numa_node_id());
                if ((*mpol)->mode == MPOL_BIND)
                        *nodemask = &(*mpol)->v.nodes;
        }
@@ -1820,7 +1819,7 @@ static struct page *alloc_page_interleave(gfp_t gfp, unsigned order,
 */
 struct page *
 alloc_pages_vma(gfp_t gfp, int order, struct vm_area_struct *vma,
-                unsigned long addr)
+                unsigned long addr, int node)
 {
        struct mempolicy *pol = get_vma_policy(current, vma, addr);
        struct zonelist *zl;
@@ -1830,13 +1829,13 @@ alloc_pages_vma(gfp_t gfp, int order, struct vm_area_struct *vma,
        if (unlikely(pol->mode == MPOL_INTERLEAVE)) {
                unsigned nid;
-                nid = interleave_nid(pol, vma, addr, PAGE_SHIFT);
+                nid = interleave_nid(pol, vma, addr, PAGE_SHIFT + order);
                mpol_cond_put(pol);
                page = alloc_page_interleave(gfp, order, nid);
                put_mems_allowed();
                return page;
        }
-        zl = policy_zonelist(gfp, pol);
+        zl = policy_zonelist(gfp, pol, node);
        if (unlikely(mpol_needs_cond_ref(pol))) {
                /*
                 * slow path: ref counted shared policy
@@ -1892,7 +1891,8 @@ struct page *alloc_pages_current(gfp_t gfp, unsigned order)
                page = alloc_page_interleave(gfp, order, interleave_nodes(pol));
        else
                page = __alloc_pages_nodemask(gfp, order,
-                        policy_zonelist(gfp, pol), policy_nodemask(gfp, pol));
+                                policy_zonelist(gfp, pol, numa_node_id()),
+                                policy_nodemask(gfp, pol));
        put_mems_allowed();
        return page;
 }
diff --git a/mm/migrate.c b/mm/migrate.c
index 766115253807..352de555626c 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -1287,14 +1287,14 @@ SYSCALL_DEFINE6(move_pages, pid_t, pid, unsigned long, nr_pages,
                return -EPERM;
        /* Find the mm_struct */
-        read_lock(&tasklist_lock);
+        rcu_read_lock();
        task = pid ? find_task_by_vpid(pid) : current;
        if (!task) {
-                read_unlock(&tasklist_lock);
+                rcu_read_unlock();
                return -ESRCH;
        }
        mm = get_task_mm(task);
-        read_unlock(&tasklist_lock);
+        rcu_read_unlock();
        if (!mm)
                return -EINVAL;
diff --git a/mm/mremap.c b/mm/mremap.c
index 9925b6391b80..1de98d492ddc 100644
--- a/mm/mremap.c
+++ b/mm/mremap.c
@@ -94,9 +94,7 @@ static void move_ptes(struct vm_area_struct *vma, pmd_t *old_pmd,
                 */
                mapping = vma->vm_file->f_mapping;
                spin_lock(&mapping->i_mmap_lock);
-                if (new_vma->vm_truncate_count &&
+                new_vma->vm_truncate_count = 0;
-                    new_vma->vm_truncate_count != vma->vm_truncate_count)
-                        new_vma->vm_truncate_count = 0;
        }
        /*
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index a873e61e312e..cdef1d4b4e47 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -5376,10 +5376,9 @@ __count_immobile_pages(struct zone *zone, struct page *page, int count)
        for (found = 0, iter = 0; iter < pageblock_nr_pages; iter++) {
                unsigned long check = pfn + iter;
-                if (!pfn_valid_within(check)) {
+                if (!pfn_valid_within(check))
-                        iter++;
                        continue;
-                }
                page = pfn_to_page(check);
                if (!page_count(page)) {
                        if (PageBuddy(page))
diff --git a/mm/swapfile.c b/mm/swapfile.c
index 07a458d72fa8..0341c5700e34 100644
--- a/mm/swapfile.c
+++ b/mm/swapfile.c
@@ -1940,7 +1940,7 @@ SYSCALL_DEFINE2(swapon, const char __user *, specialfile, int, swap_flags)
        error = -EINVAL;
        if (S_ISBLK(inode->i_mode)) {
-                bdev = I_BDEV(inode);
+                bdev = bdgrab(I_BDEV(inode));
                error = blkdev_get(bdev, FMODE_READ | FMODE_WRITE | FMODE_EXCL,
                                   sys_swapon);
                if (error < 0) {
diff --git a/mm/truncate.c b/mm/truncate.c
index 49feb46e77b8..d64296be00d3 100644
--- a/mm/truncate.c
+++ b/mm/truncate.c
@@ -225,6 +225,7 @@ void truncate_inode_pages_range(struct address_space *mapping,
        next = start;
        while (next <= end &&
               pagevec_lookup(&pvec, mapping, next, PAGEVEC_SIZE)) {
+                mem_cgroup_uncharge_start();
                for (i = 0; i < pagevec_count(&pvec); i++) {
                        struct page *page = pvec.pages[i];
                        pgoff_t page_index = page->index;
@@ -247,6 +248,7 @@ void truncate_inode_pages_range(struct address_space *mapping,
                        unlock_page(page);
                }
                pagevec_release(&pvec);
+                mem_cgroup_uncharge_end();
                cond_resched();
        }
diff --git a/mm/vmscan.c b/mm/vmscan.c
index 17497d0cd8b9..6771ea70bfe7 100644
--- a/mm/vmscan.c
+++ b/mm/vmscan.c
@@ -1841,16 +1841,28 @@ static inline bool should_continue_reclaim(struct zone *zone,
        if (!(sc->reclaim_mode & RECLAIM_MODE_COMPACTION))
                return false;
-        /*
+        /* Consider stopping depending on scan and reclaim activity */
-         * If we failed to reclaim and have scanned the full list, stop.
+        if (sc->gfp_mask & __GFP_REPEAT) {
-         * NOTE: Checking just nr_reclaimed would exit reclaim/compaction far
+                /*
-         *       faster but obviously would be less likely to succeed
+                 * For __GFP_REPEAT allocations, stop reclaiming if the
-         *       allocation. If this is desirable, use GFP_REPEAT to decide
+                 * full LRU list has been scanned and we are still failing
-         *       if both reclaimed and scanned should be checked or just
+                 * to reclaim pages. This full LRU scan is potentially
-         *       reclaimed
+                 * expensive but a __GFP_REPEAT caller really wants to succeed
-         */
+                 */
-        if (!nr_reclaimed && !nr_scanned)
+                if (!nr_reclaimed && !nr_scanned)
-                return false;
+                        return false;
+        } else {
+                /*
+                 * For non-__GFP_REPEAT allocations which can presumably
+                 * fail without consequence, stop if we failed to reclaim
+                 * any pages from the last SWAP_CLUSTER_MAX number of
+                 * pages that were scanned. This will return to the
+                 * caller faster at the risk reclaim/compaction and
+                 * the resulting allocation attempt fails
+                 */
+                if (!nr_reclaimed)
+                        return false;
+        }
        /*
         * If we have not reclaimed enough pages for compaction and the
diff --git a/net/bluetooth/rfcomm/tty.c b/net/bluetooth/rfcomm/tty.c
index 2575c2db6404..d7b9af4703d0 100644
--- a/net/bluetooth/rfcomm/tty.c
+++ b/net/bluetooth/rfcomm/tty.c
@@ -727,7 +727,9 @@ static int rfcomm_tty_open(struct tty_struct *tty, struct file *filp)
                        break;
                }
+                tty_unlock();
                schedule();
+                tty_lock();
        }
        set_current_state(TASK_RUNNING);
        remove_wait_queue(&dev->wait, &wait);
diff --git a/net/bridge/br_multicast.c b/net/bridge/br_multicast.c
index 09d5c0987925..030a002ff8ee 100644
--- a/net/bridge/br_multicast.c
+++ b/net/bridge/br_multicast.c
@@ -37,10 +37,9 @@
        rcu_dereference_protected(X, lockdep_is_held(&br->multicast_lock))
 #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
-static inline int ipv6_is_local_multicast(const struct in6_addr *addr)
+static inline int ipv6_is_transient_multicast(const struct in6_addr *addr)
 {
-        if (ipv6_addr_is_multicast(addr) &&
+        if (ipv6_addr_is_multicast(addr) && IPV6_ADDR_MC_FLAG_TRANSIENT(addr))
-            IPV6_ADDR_MC_SCOPE(addr) <= IPV6_ADDR_SCOPE_LINKLOCAL)
                return 1;
        return 0;
 }
@@ -435,7 +434,6 @@ static struct sk_buff *br_ip6_multicast_alloc_query(struct net_bridge *br,
        eth = eth_hdr(skb);
        memcpy(eth->h_source, br->dev->dev_addr, 6);
-        ipv6_eth_mc_map(group, eth->h_dest);
        eth->h_proto = htons(ETH_P_IPV6);
        skb_put(skb, sizeof(*eth));
@@ -447,8 +445,10 @@ static struct sk_buff *br_ip6_multicast_alloc_query(struct net_bridge *br,
        ip6h->payload_len = htons(8 + sizeof(*mldq));
        ip6h->nexthdr = IPPROTO_HOPOPTS;
        ip6h->hop_limit = 1;
-        ipv6_addr_set(&ip6h->saddr, 0, 0, 0, 0);
+        ipv6_dev_get_saddr(dev_net(br->dev), br->dev, &ip6h->daddr, 0,
+                           &ip6h->saddr);
        ipv6_addr_set(&ip6h->daddr, htonl(0xff020000), 0, 0, htonl(1));
+        ipv6_eth_mc_map(&ip6h->daddr, eth->h_dest);
        hopopt = (u8 *)(ip6h + 1);
        hopopt[0] = IPPROTO_ICMPV6;             /* next hdr */
@@ -780,11 +780,11 @@ static int br_ip6_multicast_add_group(struct net_bridge *br,
 {
        struct br_ip br_group;
-        if (ipv6_is_local_multicast(group))
+        if (!ipv6_is_transient_multicast(group))
                return 0;
        ipv6_addr_copy(&br_group.u.ip6, group);
-        br_group.proto = htons(ETH_P_IP);
+        br_group.proto = htons(ETH_P_IPV6);
        return br_multicast_add_group(br, port, &br_group);
 }
@@ -1013,18 +1013,19 @@ static int br_ip6_multicast_mld2_report(struct net_bridge *br,
                nsrcs = skb_header_pointer(skb,
                                           len + offsetof(struct mld2_grec,
-                                                          grec_mca),
+                                                          grec_nsrcs),
                                           sizeof(_nsrcs), &_nsrcs);
                if (!nsrcs)
                        return -EINVAL;
                if (!pskb_may_pull(skb,
                                   len + sizeof(*grec) +
-                                   sizeof(struct in6_addr) * (*nsrcs)))
+                                   sizeof(struct in6_addr) * ntohs(*nsrcs)))
                        return -EINVAL;
                grec = (struct mld2_grec *)(skb->data + len);
-                len += sizeof(*grec) + sizeof(struct in6_addr) * (*nsrcs);
+                len += sizeof(*grec) +
+                       sizeof(struct in6_addr) * ntohs(*nsrcs);
                /* We treat these as MLDv1 reports for now. */
                switch (grec->grec_type) {
@@ -1340,7 +1341,7 @@ static void br_ip6_multicast_leave_group(struct net_bridge *br,
 {
        struct br_ip br_group;
-        if (ipv6_is_local_multicast(group))
+        if (!ipv6_is_transient_multicast(group))
                return;
        ipv6_addr_copy(&br_group.u.ip6, group);
diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c
index 35b36b86d762..05f357828a2f 100644
--- a/net/ceph/messenger.c
+++ b/net/ceph/messenger.c
@@ -336,7 +336,6 @@ static void reset_connection(struct ceph_connection *con)
                ceph_msg_put(con->out_msg);
                con->out_msg = NULL;
        }
-        con->out_keepalive_pending = false;
        con->in_seq = 0;
        con->in_seq_acked = 0;
 }
@@ -1248,8 +1247,6 @@ static int process_connect(struct ceph_connection *con)
                     con->auth_retry);
                if (con->auth_retry == 2) {
                        con->error_msg = "connect authorization failure";
-                        reset_connection(con);
-                        set_bit(CLOSED, &con->state);
                        return -1;
                }
                con->auth_retry = 1;
@@ -1715,14 +1712,6 @@ more:
        /* open the socket first? */
        if (con->sock == NULL) {
-                /*
-                 * if we were STANDBY and are reconnecting _this_
-                 * connection, bump connect_seq now.  Always bump
-                 * global_seq.
-                 */
-                if (test_and_clear_bit(STANDBY, &con->state))
-                        con->connect_seq++;
                prepare_write_banner(msgr, con);
                prepare_write_connect(msgr, con, 1);
                prepare_read_banner(con);
@@ -1951,7 +1940,24 @@ static void con_work(struct work_struct *work)
                                                   work.work);
        mutex_lock(&con->mutex);
+        if (test_and_clear_bit(BACKOFF, &con->state)) {
+                dout("con_work %p backing off\n", con);
+                if (queue_delayed_work(ceph_msgr_wq, &con->work,
+                                       round_jiffies_relative(con->delay))) {
+                        dout("con_work %p backoff %lu\n", con, con->delay);
+                        mutex_unlock(&con->mutex);
+                        return;
+                } else {
+                        con->ops->put(con);
+                        dout("con_work %p FAILED to back off %lu\n", con,
+                             con->delay);
+                }
+        }
+        if (test_bit(STANDBY, &con->state)) {
+                dout("con_work %p STANDBY\n", con);
+                goto done;
+        }
        if (test_bit(CLOSED, &con->state)) { /* e.g. if we are replaced */
                dout("con_work CLOSED\n");
                con_close_socket(con);
@@ -2008,10 +2014,12 @@ static void ceph_fault(struct ceph_connection *con)
        /* Requeue anything that hasn't been acked */
        list_splice_init(&con->out_sent, &con->out_queue);
-        /* If there are no messages in the queue, place the connection
+        /* If there are no messages queued or keepalive pending, place
-         * in a STANDBY state (i.e., don't try to reconnect just yet). */
+         * the connection in a STANDBY state */
-        if (list_empty(&con->out_queue) && !con->out_keepalive_pending) {
+        if (list_empty(&con->out_queue) &&
-                dout("fault setting STANDBY\n");
+            !test_bit(KEEPALIVE_PENDING, &con->state)) {
+                dout("fault %p setting STANDBY clearing WRITE_PENDING\n", con);
+                clear_bit(WRITE_PENDING, &con->state);
                set_bit(STANDBY, &con->state);
        } else {
                /* retry after a delay. */
@@ -2019,11 +2027,24 @@ static void ceph_fault(struct ceph_connection *con)
                        con->delay = BASE_DELAY_INTERVAL;
                else if (con->delay < MAX_DELAY_INTERVAL)
                        con->delay *= 2;
-                dout("fault queueing %p delay %lu\n", con, con->delay);
                con->ops->get(con);
                if (queue_delayed_work(ceph_msgr_wq, &con->work,
-                                       round_jiffies_relative(con->delay)) == 0)
+                                       round_jiffies_relative(con->delay))) {
+                        dout("fault queued %p delay %lu\n", con, con->delay);
+                } else {
                        con->ops->put(con);
+                        dout("fault failed to queue %p delay %lu, backoff\n",
+                             con, con->delay);
+                        /*
+                         * In many cases we see a socket state change
+                         * while con_work is running and end up
+                         * queuing (non-delayed) work, such that we
+                         * can't backoff with a delay.  Set a flag so
+                         * that when con_work restarts we schedule the
+                         * delay then.
+                         */
+                        set_bit(BACKOFF, &con->state);
+                }
        }
 out_unlock:
@@ -2094,6 +2115,19 @@ void ceph_messenger_destroy(struct ceph_messenger *msgr)
 }
 EXPORT_SYMBOL(ceph_messenger_destroy);
+static void clear_standby(struct ceph_connection *con)
+{
+        /* come back from STANDBY? */
+        if (test_and_clear_bit(STANDBY, &con->state)) {
+                mutex_lock(&con->mutex);
+                dout("clear_standby %p and ++connect_seq\n", con);
+                con->connect_seq++;
+                WARN_ON(test_bit(WRITE_PENDING, &con->state));
+                WARN_ON(test_bit(KEEPALIVE_PENDING, &con->state));
+                mutex_unlock(&con->mutex);
+        }
+}
 /*
 * Queue up an outgoing message on the given connection.
 */
@@ -2126,6 +2160,7 @@ void ceph_con_send(struct ceph_connection *con, struct ceph_msg *msg)
        /* if there wasn't anything waiting to send before, queue
         * new work */
+        clear_standby(con);
        if (test_and_set_bit(WRITE_PENDING, &con->state) == 0)
                queue_con(con);
 }
@@ -2191,6 +2226,8 @@ void ceph_con_revoke_message(struct ceph_connection *con, struct ceph_msg *msg)
 */
 void ceph_con_keepalive(struct ceph_connection *con)
 {
+        dout("con_keepalive %p\n", con);
+        clear_standby(con);
        if (test_and_set_bit(KEEPALIVE_PENDING, &con->state) == 0 &&
            test_and_set_bit(WRITE_PENDING, &con->state) == 0)
                queue_con(con);
diff --git a/net/ceph/pagevec.c b/net/ceph/pagevec.c
index 1a040e64c69f..cd9c21df87d1 100644
--- a/net/ceph/pagevec.c
+++ b/net/ceph/pagevec.c
@@ -16,22 +16,30 @@ struct page **ceph_get_direct_page_vector(const char __user *data,
                                          int num_pages, bool write_page)
 {
        struct page **pages;
-        int rc;
+        int got = 0;
+        int rc = 0;
        pages = kmalloc(sizeof(*pages) * num_pages, GFP_NOFS);
        if (!pages)
                return ERR_PTR(-ENOMEM);
        down_read(&current->mm->mmap_sem);
-        rc = get_user_pages(current, current->mm, (unsigned long)data,
+        while (got < num_pages) {
-                            num_pages, write_page, 0, pages, NULL);
+                rc = get_user_pages(current, current->mm,
+                    (unsigned long)data + ((unsigned long)got * PAGE_SIZE),
+                    num_pages - got, write_page, 0, pages + got, NULL);
+                if (rc < 0)
+                        break;
+                BUG_ON(rc == 0);
+                got += rc;
+        }
        up_read(&current->mm->mmap_sem);
-        if (rc < num_pages)
+        if (rc < 0)
                goto fail;
        return pages;
 fail:
-        ceph_put_page_vector(pages, rc > 0 ? rc : 0, false);
+        ceph_put_page_vector(pages, got, false);
        return ERR_PTR(rc);
 }
 EXPORT_SYMBOL(ceph_get_direct_page_vector);
diff --git a/net/core/dev_addr_lists.c b/net/core/dev_addr_lists.c
index 508f9c18992f..133fd22ea287 100644
--- a/net/core/dev_addr_lists.c
+++ b/net/core/dev_addr_lists.c
@@ -144,7 +144,7 @@ void __hw_addr_del_multiple(struct netdev_hw_addr_list *to_list,
        list_for_each_entry(ha, &from_list->list, list) {
                type = addr_type ? addr_type : ha->type;
-                __hw_addr_del(to_list, ha->addr, addr_len, addr_type);
+                __hw_addr_del(to_list, ha->addr, addr_len, type);
        }
 }
 EXPORT_SYMBOL(__hw_addr_del_multiple);
diff --git a/net/dcb/dcbnl.c b/net/dcb/dcbnl.c
index d5074a567289..c44348adba3b 100644
--- a/net/dcb/dcbnl.c
+++ b/net/dcb/dcbnl.c
@@ -1193,7 +1193,7 @@ static int dcbnl_ieee_set(struct net_device *netdev, struct nlattr **tb,
                        goto err;
        }
-        if (ieee[DCB_ATTR_IEEE_PFC] && ops->ieee_setets) {
+        if (ieee[DCB_ATTR_IEEE_PFC] && ops->ieee_setpfc) {
                struct ieee_pfc *pfc = nla_data(ieee[DCB_ATTR_IEEE_PFC]);
                err = ops->ieee_setpfc(netdev, pfc);
                if (err)
diff --git a/net/dccp/input.c b/net/dccp/input.c
index 8cde009e8b85..4222e7a654b0 100644
--- a/net/dccp/input.c
+++ b/net/dccp/input.c
@@ -614,6 +614,9 @@ int dccp_rcv_state_process(struct sock *sk, struct sk_buff *skb,
                /* Caller (dccp_v4_do_rcv) will send Reset */
                dcb->dccpd_reset_code = DCCP_RESET_CODE_NO_CONNECTION;
                return 1;
+        } else if (sk->sk_state == DCCP_CLOSED) {
+                dcb->dccpd_reset_code = DCCP_RESET_CODE_NO_CONNECTION;
+                return 1;
        }
        if (sk->sk_state != DCCP_REQUESTING && sk->sk_state != DCCP_RESPOND) {
@@ -668,10 +671,6 @@ int dccp_rcv_state_process(struct sock *sk, struct sk_buff *skb,
        }
        switch (sk->sk_state) {
-        case DCCP_CLOSED:
-                dcb->dccpd_reset_code = DCCP_RESET_CODE_NO_CONNECTION;
-                return 1;
        case DCCP_REQUESTING:
                queued = dccp_rcv_request_sent_state_process(sk, skb, dh, len);
                if (queued >= 0)
diff --git a/net/dns_resolver/dns_key.c b/net/dns_resolver/dns_key.c
index 739435a6af39..cfa7a5e1c5c9 100644
--- a/net/dns_resolver/dns_key.c
+++ b/net/dns_resolver/dns_key.c
@@ -67,8 +67,9 @@ dns_resolver_instantiate(struct key *key, const void *_data, size_t datalen)
        size_t result_len = 0;
        const char *data = _data, *end, *opt;
-        kenter("%%%d,%s,'%s',%zu",
+        kenter("%%%d,%s,'%*.*s',%zu",
-               key->serial, key->description, data, datalen);
+               key->serial, key->description,
+               (int)datalen, (int)datalen, data, datalen);
        if (datalen <= 1 || !data || data[datalen - 1] != '\0')
                return -EINVAL;
@@ -217,6 +218,19 @@ static void dns_resolver_describe(const struct key *key, struct seq_file *m)
                seq_printf(m, ": %u", key->datalen);
 }
+/*
+ * read the DNS data
+ * - the key's semaphore is read-locked
+ */
+static long dns_resolver_read(const struct key *key,
+                              char __user *buffer, size_t buflen)
+{
+        if (key->type_data.x[0])
+                return key->type_data.x[0];
+        return user_read(key, buffer, buflen);
+}
 struct key_type key_type_dns_resolver = {
        .name           = "dns_resolver",
        .instantiate    = dns_resolver_instantiate,
@@ -224,7 +238,7 @@ struct key_type key_type_dns_resolver = {
        .revoke         = user_revoke,
        .destroy        = user_destroy,
        .describe       = dns_resolver_describe,
-        .read           = user_read,
+        .read           = dns_resolver_read,
 };
 static int __init init_dns_resolver(void)
diff --git a/net/ipv4/inet_timewait_sock.c b/net/ipv4/inet_timewait_sock.c
index c5af909cf701..3c8dfa16614d 100644
--- a/net/ipv4/inet_timewait_sock.c
+++ b/net/ipv4/inet_timewait_sock.c
@@ -505,7 +505,9 @@ restart:
                        }
                        rcu_read_unlock();
+                        local_bh_disable();
                        inet_twsk_deschedule(tw, twdr);
+                        local_bh_enable();
                        inet_twsk_put(tw);
                        goto restart_rcu;
                }
diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c
index eb7f82ebf4a3..65f6c0406245 100644
--- a/net/ipv4/tcp_input.c
+++ b/net/ipv4/tcp_input.c
@@ -1222,7 +1222,7 @@ static int tcp_check_dsack(struct sock *sk, struct sk_buff *ack_skb,
        }
        /* D-SACK for already forgotten data... Do dumb counting. */
-        if (dup_sack &&
+        if (dup_sack && tp->undo_marker && tp->undo_retrans &&
            !after(end_seq_0, prior_snd_una) &&
            after(end_seq_0, tp->undo_marker))
                tp->undo_retrans--;
@@ -1299,7 +1299,8 @@ static u8 tcp_sacktag_one(struct sk_buff *skb, struct sock *sk,
        /* Account D-SACK for retransmitted packet. */
        if (dup_sack && (sacked & TCPCB_RETRANS)) {
-                if (after(TCP_SKB_CB(skb)->end_seq, tp->undo_marker))
+                if (tp->undo_marker && tp->undo_retrans &&
+                    after(TCP_SKB_CB(skb)->end_seq, tp->undo_marker))
                        tp->undo_retrans--;
                if (sacked & TCPCB_SACKED_ACKED)
                        state->reord = min(fack_count, state->reord);
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index 406f320336e6..dfa5beb0c1c8 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -2162,7 +2162,7 @@ int tcp_retransmit_skb(struct sock *sk, struct sk_buff *skb)
                if (!tp->retrans_stamp)
                        tp->retrans_stamp = TCP_SKB_CB(skb)->when;
-                tp->undo_retrans++;
+                tp->undo_retrans += tcp_skb_pcount(skb);
                /* snd_nxt is stored to detect loss of retransmitted segment,
                 * see tcp_input.c tcp_sacktag_write_queue().
diff --git a/net/ipv6/netfilter/ip6t_LOG.c b/net/ipv6/netfilter/ip6t_LOG.c
index 09c88891a753..de338037a736 100644
--- a/net/ipv6/netfilter/ip6t_LOG.c
+++ b/net/ipv6/netfilter/ip6t_LOG.c
@@ -410,7 +410,7 @@ fallback:
                if (p != NULL) {
                        sb_add(m, "%02x", *p++);
                        for (i = 1; i < len; i++)
-                                sb_add(m, ":%02x", p[i]);
+                                sb_add(m, ":%02x", *p++);
                }
                sb_add(m, " ");
diff --git a/net/ipv6/route.c b/net/ipv6/route.c
index a998db6e7895..904312e25a3c 100644
--- a/net/ipv6/route.c
+++ b/net/ipv6/route.c
@@ -2557,14 +2557,16 @@ static
 int ipv6_sysctl_rtcache_flush(ctl_table *ctl, int write,
                              void __user *buffer, size_t *lenp, loff_t *ppos)
 {
-        struct net *net = current->nsproxy->net_ns;
+        struct net *net;
-        int delay = net->ipv6.sysctl.flush_delay;
+        int delay;
-        if (write) {
+        if (!write)
-                proc_dointvec(ctl, write, buffer, lenp, ppos);
-                fib6_run_gc(delay <= 0 ? ~0UL : (unsigned long)delay, net);
-                return 0;
-        } else
                return -EINVAL;
+        net = (struct net *)ctl->extra1;
+        delay = net->ipv6.sysctl.flush_delay;
+        proc_dointvec(ctl, write, buffer, lenp, ppos);
+        fib6_run_gc(delay <= 0 ? ~0UL : (unsigned long)delay, net);
+        return 0;
 }
 ctl_table ipv6_route_table_template[] = {
@@ -2651,6 +2653,7 @@ struct ctl_table * __net_init ipv6_route_sysctl_init(struct net *net)
        if (table) {
                table[0].data = &net->ipv6.sysctl.flush_delay;
+                table[0].extra1 = net;
                table[1].data = &net->ipv6.ip6_dst_ops.gc_thresh;
                table[2].data = &net->ipv6.sysctl.ip6_rt_max_size;
                table[3].data = &net->ipv6.sysctl.ip6_rt_gc_min_interval;
diff --git a/net/mac80211/iface.c b/net/mac80211/iface.c
index 8acba456744e..7a10a8d1b2d0 100644
--- a/net/mac80211/iface.c
+++ b/net/mac80211/iface.c
@@ -1229,6 +1229,7 @@ void ieee80211_remove_interfaces(struct ieee80211_local *local)
        }
        mutex_unlock(&local->iflist_mtx);
        unregister_netdevice_many(&unreg_list);
+        list_del(&unreg_list);
 }
 static u32 ieee80211_idle_off(struct ieee80211_local *local,
diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c
index 45fbb9e33746..c9ceb4d57ab0 100644
--- a/net/mac80211/mlme.c
+++ b/net/mac80211/mlme.c
@@ -1033,6 +1033,12 @@ void ieee80211_sta_rx_notify(struct ieee80211_sub_if_data *sdata,
        if (is_multicast_ether_addr(hdr->addr1))
                return;
+        /*
+         * In case we receive frames after disassociation.
+         */
+        if (!sdata->u.mgd.associated)
+                return;
        ieee80211_sta_reset_conn_monitor(sdata);
 }
diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c
index 22f7ad5101ab..ba98e1308f3c 100644
--- a/net/netfilter/ipvs/ip_vs_ctl.c
+++ b/net/netfilter/ipvs/ip_vs_ctl.c
@@ -808,9 +808,9 @@ __ip_vs_update_dest(struct ip_vs_service *svc, struct ip_vs_dest *dest,
        dest->u_threshold = udest->u_threshold;
        dest->l_threshold = udest->l_threshold;
-        spin_lock(&dest->dst_lock);
+        spin_lock_bh(&dest->dst_lock);
        ip_vs_dst_reset(dest);
-        spin_unlock(&dest->dst_lock);
+        spin_unlock_bh(&dest->dst_lock);
        if (add)
                ip_vs_new_estimator(&dest->stats);
diff --git a/net/netfilter/nf_log.c b/net/netfilter/nf_log.c
index b07393eab88e..91816998ed86 100644
--- a/net/netfilter/nf_log.c
+++ b/net/netfilter/nf_log.c
@@ -85,6 +85,8 @@ EXPORT_SYMBOL(nf_log_unregister);
 int nf_log_bind_pf(u_int8_t pf, const struct nf_logger *logger)
 {
+        if (pf >= ARRAY_SIZE(nf_loggers))
+                return -EINVAL;
        mutex_lock(&nf_log_mutex);
        if (__find_logger(pf, logger->name) == NULL) {
                mutex_unlock(&nf_log_mutex);
@@ -98,6 +100,8 @@ EXPORT_SYMBOL(nf_log_bind_pf);
 void nf_log_unbind_pf(u_int8_t pf)
 {
+        if (pf >= ARRAY_SIZE(nf_loggers))
+                return;
        mutex_lock(&nf_log_mutex);
        rcu_assign_pointer(nf_loggers[pf], NULL);
        mutex_unlock(&nf_log_mutex);
diff --git a/net/netfilter/nf_tproxy_core.c b/net/netfilter/nf_tproxy_core.c
index 4d87befb04c0..474d621cbc2e 100644
--- a/net/netfilter/nf_tproxy_core.c
+++ b/net/netfilter/nf_tproxy_core.c
@@ -28,26 +28,23 @@ nf_tproxy_destructor(struct sk_buff *skb)
        skb->destructor = NULL;
        if (sk)
-                nf_tproxy_put_sock(sk);
+                sock_put(sk);
 }
 /* consumes sk */
-int
+void
 nf_tproxy_assign_sock(struct sk_buff *skb, struct sock *sk)
 {
-        bool transparent = (sk->sk_state == TCP_TIME_WAIT) ?
+        /* assigning tw sockets complicates things; most
-                                inet_twsk(sk)->tw_transparent :
+         * skb->sk->X checks would have to test sk->sk_state first */
-                                inet_sk(sk)->transparent;
+        if (sk->sk_state == TCP_TIME_WAIT) {
+                inet_twsk_put(inet_twsk(sk));
-        if (transparent) {
+                return;
-                skb_orphan(skb);
+        }
-                skb->sk = sk;
-                skb->destructor = nf_tproxy_destructor;
+        skb_orphan(skb);
-                return 1;
+        skb->sk = sk;
-        } else
+        skb->destructor = nf_tproxy_destructor;
-                nf_tproxy_put_sock(sk);
-        return 0;
 }
 EXPORT_SYMBOL_GPL(nf_tproxy_assign_sock);
diff --git a/net/netfilter/xt_TPROXY.c b/net/netfilter/xt_TPROXY.c
index 640678f47a2a..dcfd57eb9d02 100644
--- a/net/netfilter/xt_TPROXY.c
+++ b/net/netfilter/xt_TPROXY.c
@@ -33,6 +33,20 @@
 #include <net/netfilter/nf_tproxy_core.h>
 #include <linux/netfilter/xt_TPROXY.h>
+static bool tproxy_sk_is_transparent(struct sock *sk)
+{
+        if (sk->sk_state != TCP_TIME_WAIT) {
+                if (inet_sk(sk)->transparent)
+                        return true;
+                sock_put(sk);
+        } else {
+                if (inet_twsk(sk)->tw_transparent)
+                        return true;
+                inet_twsk_put(inet_twsk(sk));
+        }
+        return false;
+}
 static inline __be32
 tproxy_laddr4(struct sk_buff *skb, __be32 user_laddr, __be32 daddr)
 {
@@ -141,7 +155,7 @@ tproxy_tg4(struct sk_buff *skb, __be32 laddr, __be16 lport,
                                           skb->dev, NFT_LOOKUP_LISTENER);
        /* NOTE: assign_sock consumes our sk reference */
-        if (sk && nf_tproxy_assign_sock(skb, sk)) {
+        if (sk && tproxy_sk_is_transparent(sk)) {
                /* This should be in a separate target, but we don't do multiple
                   targets on the same rule yet */
                skb->mark = (skb->mark & ~mark_mask) ^ mark_value;
@@ -149,6 +163,8 @@ tproxy_tg4(struct sk_buff *skb, __be32 laddr, __be16 lport,
                pr_debug("redirecting: proto %hhu %pI4:%hu -> %pI4:%hu, mark: %x\n",
                         iph->protocol, &iph->daddr, ntohs(hp->dest),
                         &laddr, ntohs(lport), skb->mark);
+                nf_tproxy_assign_sock(skb, sk);
                return NF_ACCEPT;
        }
@@ -306,7 +322,7 @@ tproxy_tg6_v1(struct sk_buff *skb, const struct xt_action_param *par)
                                           par->in, NFT_LOOKUP_LISTENER);
        /* NOTE: assign_sock consumes our sk reference */
-        if (sk && nf_tproxy_assign_sock(skb, sk)) {
+        if (sk && tproxy_sk_is_transparent(sk)) {
                /* This should be in a separate target, but we don't do multiple
                   targets on the same rule yet */
                skb->mark = (skb->mark & ~tgi->mark_mask) ^ tgi->mark_value;
@@ -314,6 +330,8 @@ tproxy_tg6_v1(struct sk_buff *skb, const struct xt_action_param *par)
                pr_debug("redirecting: proto %hhu %pI6:%hu -> %pI6:%hu, mark: %x\n",
                         tproto, &iph->saddr, ntohs(hp->source),
                         laddr, ntohs(lport), skb->mark);
+                nf_tproxy_assign_sock(skb, sk);
                return NF_ACCEPT;
        }
diff --git a/net/netfilter/xt_socket.c b/net/netfilter/xt_socket.c
index 00d6ae838303..9cc46356b577 100644
--- a/net/netfilter/xt_socket.c
+++ b/net/netfilter/xt_socket.c
@@ -35,6 +35,15 @@
 #include <net/netfilter/nf_conntrack.h>
 #endif
+static void
+xt_socket_put_sk(struct sock *sk)
+{
+        if (sk->sk_state == TCP_TIME_WAIT)
+                inet_twsk_put(inet_twsk(sk));
+        else
+                sock_put(sk);
+}
 static int
 extract_icmp4_fields(const struct sk_buff *skb,
                    u8 *protocol,
@@ -164,7 +173,7 @@ socket_match(const struct sk_buff *skb, struct xt_action_param *par,
                                       (sk->sk_state == TCP_TIME_WAIT &&
                                        inet_twsk(sk)->tw_transparent));
-                nf_tproxy_put_sock(sk);
+                xt_socket_put_sk(sk);
                if (wildcard || !transparent)
                        sk = NULL;
@@ -298,7 +307,7 @@ socket_mt6_v1(const struct sk_buff *skb, struct xt_action_param *par)
                                       (sk->sk_state == TCP_TIME_WAIT &&
                                        inet_twsk(sk)->tw_transparent));
-                nf_tproxy_put_sock(sk);
+                xt_socket_put_sk(sk);
                if (wildcard || !transparent)
                        sk = NULL;
diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c
index 478181d53c55..1f924595bdef 100644
--- a/net/netlink/af_netlink.c
+++ b/net/netlink/af_netlink.c
@@ -1407,7 +1407,7 @@ static int netlink_recvmsg(struct kiocb *kiocb, struct socket *sock,
        int noblock = flags&MSG_DONTWAIT;
        size_t copied;
        struct sk_buff *skb, *data_skb;
-        int err;
+        int err, ret;
        if (flags&MSG_OOB)
                return -EOPNOTSUPP;
@@ -1470,8 +1470,13 @@ static int netlink_recvmsg(struct kiocb *kiocb, struct socket *sock,
        skb_free_datagram(sk, skb);
-        if (nlk->cb && atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf / 2)
+        if (nlk->cb && atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf / 2) {
-                netlink_dump(sk);
+                ret = netlink_dump(sk);
+                if (ret) {
+                        sk->sk_err = ret;
+                        sk->sk_error_report(sk);
+                }
+        }
        scm_recv(sock, msg, siocb->scm, flags);
 out:
@@ -1736,6 +1741,7 @@ int netlink_dump_start(struct sock *ssk, struct sk_buff *skb,
        struct netlink_callback *cb;
        struct sock *sk;
        struct netlink_sock *nlk;
+        int ret;
        cb = kzalloc(sizeof(*cb), GFP_KERNEL);
        if (cb == NULL)
@@ -1764,9 +1770,13 @@ int netlink_dump_start(struct sock *ssk, struct sk_buff *skb,
        nlk->cb = cb;
        mutex_unlock(nlk->cb_mutex);
-        netlink_dump(sk);
+        ret = netlink_dump(sk);
        sock_put(sk);
+        if (ret)
+                return ret;
        /* We successfully started a dump, by returning -EINTR we
         * signal not to send ACK even if it was requested.
         */
diff --git a/net/rxrpc/ar-input.c b/net/rxrpc/ar-input.c
index 89315009bab1..1a2b0633fece 100644
--- a/net/rxrpc/ar-input.c
+++ b/net/rxrpc/ar-input.c
@@ -423,6 +423,7 @@ void rxrpc_fast_process_packet(struct rxrpc_call *call, struct sk_buff *skb)
                        goto protocol_error;
                }
+        case RXRPC_PACKET_TYPE_ACKALL:
        case RXRPC_PACKET_TYPE_ACK:
                /* ACK processing is done in process context */
                read_lock_bh(&call->state_lock);
diff --git a/net/rxrpc/ar-key.c b/net/rxrpc/ar-key.c
index 5ee16f0353fe..d763793d39de 100644
--- a/net/rxrpc/ar-key.c
+++ b/net/rxrpc/ar-key.c
@@ -89,11 +89,11 @@ static int rxrpc_instantiate_xdr_rxkad(struct key *key, const __be32 *xdr,
                return ret;
        plen -= sizeof(*token);
-        token = kmalloc(sizeof(*token), GFP_KERNEL);
+        token = kzalloc(sizeof(*token), GFP_KERNEL);
        if (!token)
                return -ENOMEM;
-        token->kad = kmalloc(plen, GFP_KERNEL);
+        token->kad = kzalloc(plen, GFP_KERNEL);
        if (!token->kad) {
                kfree(token);
                return -ENOMEM;
@@ -731,10 +731,10 @@ static int rxrpc_instantiate(struct key *key, const void *data, size_t datalen)
                goto error;
        ret = -ENOMEM;
-        token = kmalloc(sizeof(*token), GFP_KERNEL);
+        token = kzalloc(sizeof(*token), GFP_KERNEL);
        if (!token)
                goto error;
-        token->kad = kmalloc(plen, GFP_KERNEL);
+        token->kad = kzalloc(plen, GFP_KERNEL);
        if (!token->kad)
                goto error_free;
diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index 34dc598440a2..1bc698039ae2 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -839,6 +839,7 @@ void dev_deactivate(struct net_device *dev)
        list_add(&dev->unreg_list, &single);
        dev_deactivate_many(&single);
+        list_del(&single);
 }
 static void dev_init_scheduler_queue(struct net_device *dev,
diff --git a/net/sctp/sm_make_chunk.c b/net/sctp/sm_make_chunk.c
index 2cc46f0962ca..b23428f3c0dd 100644
--- a/net/sctp/sm_make_chunk.c
+++ b/net/sctp/sm_make_chunk.c
@@ -2029,11 +2029,11 @@ static sctp_ierror_t sctp_process_unk_param(const struct sctp_association *asoc,
                        *errp = sctp_make_op_error_fixed(asoc, chunk);
                if (*errp) {
-                        sctp_init_cause_fixed(*errp, SCTP_ERROR_UNKNOWN_PARAM,
+                        if (!sctp_init_cause_fixed(*errp, SCTP_ERROR_UNKNOWN_PARAM,
-                                        WORD_ROUND(ntohs(param.p->length)));
+                                        WORD_ROUND(ntohs(param.p->length))))
-                        sctp_addto_chunk_fixed(*errp,
+                                sctp_addto_chunk_fixed(*errp,
-                                        WORD_ROUND(ntohs(param.p->length)),
+                                                WORD_ROUND(ntohs(param.p->length)),
-                                        param.v);
+                                                param.v);
                } else {
                        /* If there is no memory for generating the ERROR
                         * report as specified, an ABORT will be triggered
diff --git a/net/wireless/wext-compat.c b/net/wireless/wext-compat.c
index 3e5dbd4e4cd5..d112f038edf0 100644
--- a/net/wireless/wext-compat.c
+++ b/net/wireless/wext-compat.c
@@ -802,11 +802,11 @@ int cfg80211_wext_siwfreq(struct net_device *dev,
                        return freq;
                if (freq == 0)
                        return -EINVAL;
-                wdev_lock(wdev);
                mutex_lock(&rdev->devlist_mtx);
+                wdev_lock(wdev);
                err = cfg80211_set_freq(rdev, wdev, freq, NL80211_CHAN_NO_HT);
-                mutex_unlock(&rdev->devlist_mtx);
                wdev_unlock(wdev);
+                mutex_unlock(&rdev->devlist_mtx);
                return err;
        default:
                return -EOPNOTSUPP;
diff --git a/sound/core/jack.c b/sound/core/jack.c
index 4902ae568730..53b53e97c896 100644
--- a/sound/core/jack.c
+++ b/sound/core/jack.c
@@ -141,6 +141,7 @@ int snd_jack_new(struct snd_card *card, const char *id, int type,
 fail_input:
        input_free_device(jack->input_dev);
+        kfree(jack->id);
        kfree(jack);
        return err;
 }
diff --git a/sound/pci/hda/patch_cirrus.c b/sound/pci/hda/patch_cirrus.c
index a07b031090d8..067982f4f182 100644
--- a/sound/pci/hda/patch_cirrus.c
+++ b/sound/pci/hda/patch_cirrus.c
@@ -1039,9 +1039,11 @@ static struct hda_verb cs_errata_init_verbs[] = {
        {0x11, AC_VERB_SET_PROC_COEF, 0x0008},
        {0x11, AC_VERB_SET_PROC_STATE, 0x00},
+#if 0 /* Don't to set to D3 as we are in power-up sequence */
        {0x07, AC_VERB_SET_POWER_STATE, 0x03}, /* S/PDIF Rx: D3 */
        {0x08, AC_VERB_SET_POWER_STATE, 0x03}, /* S/PDIF Tx: D3 */
        /*{0x01, AC_VERB_SET_POWER_STATE, 0x03},*/ /* AFG: D3 This is already handled */
+#endif
        {} /* terminator */
 };
diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c
index dd7c5c12225d..4d5004e693f0 100644
--- a/sound/pci/hda/patch_conexant.c
+++ b/sound/pci/hda/patch_conexant.c
@@ -3114,6 +3114,8 @@ static struct snd_pci_quirk cxt5066_cfg_tbl[] = {
        SND_PCI_QUIRK(0x1028, 0x0401, "Dell Vostro 1014", CXT5066_DELL_VOSTRO),
        SND_PCI_QUIRK(0x1028, 0x0402, "Dell Vostro", CXT5066_DELL_VOSTRO),
        SND_PCI_QUIRK(0x1028, 0x0408, "Dell Inspiron One 19T", CXT5066_IDEAPAD),
+        SND_PCI_QUIRK(0x1028, 0x050f, "Dell Inspiron", CXT5066_IDEAPAD),
+        SND_PCI_QUIRK(0x1028, 0x0510, "Dell Vostro", CXT5066_IDEAPAD),
        SND_PCI_QUIRK(0x103c, 0x360b, "HP G60", CXT5066_HP_LAPTOP),
        SND_PCI_QUIRK(0x1043, 0x13f3, "Asus A52J", CXT5066_ASUS),
        SND_PCI_QUIRK(0x1043, 0x1643, "Asus K52JU", CXT5066_ASUS),
@@ -3937,6 +3939,8 @@ static struct hda_codec_preset snd_hda_preset_conexant[] = {
          .patch = patch_cxt5066 },
        { .id = 0x14f15069, .name = "CX20585",
          .patch = patch_cxt5066 },
+        { .id = 0x14f1506e, .name = "CX20590",
+          .patch = patch_cxt5066 },
        { .id = 0x14f15097, .name = "CX20631",
          .patch = patch_conexant_auto },
        { .id = 0x14f15098, .name = "CX20632",
@@ -3963,6 +3967,7 @@ MODULE_ALIAS("snd-hda-codec-id:14f15066");
 MODULE_ALIAS("snd-hda-codec-id:14f15067");
 MODULE_ALIAS("snd-hda-codec-id:14f15068");
 MODULE_ALIAS("snd-hda-codec-id:14f15069");
+MODULE_ALIAS("snd-hda-codec-id:14f1506e");
 MODULE_ALIAS("snd-hda-codec-id:14f15097");
 MODULE_ALIAS("snd-hda-codec-id:14f15098");
 MODULE_ALIAS("snd-hda-codec-id:14f150a1");
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index a58767736727..ec0fa2dd0a27 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -1634,6 +1634,9 @@ static struct hda_codec_preset snd_hda_preset_hdmi[] = {
 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP",   .patch = patch_nvhdmi_8ch_89 },
 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP",   .patch = patch_nvhdmi_8ch_89 },
 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP",   .patch = patch_nvhdmi_8ch_89 },
+{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP",   .patch = patch_nvhdmi_8ch_89 },
+{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP",   .patch = patch_nvhdmi_8ch_89 },
+/* 17 is known to be absent */
 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP",   .patch = patch_nvhdmi_8ch_89 },
 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP",   .patch = patch_nvhdmi_8ch_89 },
 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP",   .patch = patch_nvhdmi_8ch_89 },
@@ -1676,6 +1679,8 @@ MODULE_ALIAS("snd-hda-codec-id:10de0011");
 MODULE_ALIAS("snd-hda-codec-id:10de0012");
 MODULE_ALIAS("snd-hda-codec-id:10de0013");
 MODULE_ALIAS("snd-hda-codec-id:10de0014");
+MODULE_ALIAS("snd-hda-codec-id:10de0015");
+MODULE_ALIAS("snd-hda-codec-id:10de0016");
 MODULE_ALIAS("snd-hda-codec-id:10de0018");
 MODULE_ALIAS("snd-hda-codec-id:10de0019");
 MODULE_ALIAS("snd-hda-codec-id:10de001a");
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 3328a259a242..4261bb8eec1d 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -1133,11 +1133,8 @@ static void alc_automute_speaker(struct hda_codec *codec, int pinctl)
                nid = spec->autocfg.hp_pins[i];
                if (!nid)
                        break;
-                if (snd_hda_jack_detect(codec, nid)) {
+                alc_report_jack(codec, nid);
-                        spec->jack_present = 1;
+                spec->jack_present |= snd_hda_jack_detect(codec, nid);
-                        break;
-                }
-                alc_report_jack(codec, spec->autocfg.hp_pins[i]);
        }
        mute = spec->jack_present ? HDA_AMP_MUTE : 0;
@@ -15015,7 +15012,7 @@ static struct snd_pci_quirk alc269_cfg_tbl[] = {
        SND_PCI_QUIRK(0x1043, 0x11e3, "ASUS U33Jc", ALC269VB_AMIC),
        SND_PCI_QUIRK(0x1043, 0x1273, "ASUS UL80Jt", ALC269VB_AMIC),
        SND_PCI_QUIRK(0x1043, 0x1283, "ASUS U53Jc", ALC269_AMIC),
-        SND_PCI_QUIRK(0x1043, 0x12b3, "ASUS N82Jv", ALC269_AMIC),
+        SND_PCI_QUIRK(0x1043, 0x12b3, "ASUS N82JV", ALC269VB_AMIC),
        SND_PCI_QUIRK(0x1043, 0x12d3, "ASUS N61Jv", ALC269_AMIC),
        SND_PCI_QUIRK(0x1043, 0x13a3, "ASUS UL30Vt", ALC269_AMIC),
        SND_PCI_QUIRK(0x1043, 0x1373, "ASUS G73JX", ALC269_AMIC),
diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c
index 9ea48b425d0b..bd7b123f6440 100644
--- a/sound/pci/hda/patch_sigmatel.c
+++ b/sound/pci/hda/patch_sigmatel.c
@@ -586,7 +586,12 @@ static hda_nid_t stac92hd83xxx_pin_nids[10] = {
        0x0f, 0x10, 0x11, 0x1f, 0x20,
 };
-static hda_nid_t stac92hd88xxx_pin_nids[10] = {
+static hda_nid_t stac92hd87xxx_pin_nids[6] = {
+        0x0a, 0x0b, 0x0c, 0x0d,
+        0x0f, 0x11,
+};
+static hda_nid_t stac92hd88xxx_pin_nids[8] = {
        0x0a, 0x0b, 0x0c, 0x0d,
        0x0f, 0x11, 0x1f, 0x20,
 };
@@ -5430,12 +5435,13 @@ again:
        switch (codec->vendor_id) {
        case 0x111d76d1:
        case 0x111d76d9:
+        case 0x111d76e5:
                spec->dmic_nids = stac92hd87b_dmic_nids;
                spec->num_dmics = stac92xx_connected_ports(codec,
                                stac92hd87b_dmic_nids,
                                STAC92HD87B_NUM_DMICS);
-                spec->num_pins = ARRAY_SIZE(stac92hd88xxx_pin_nids);
+                spec->num_pins = ARRAY_SIZE(stac92hd87xxx_pin_nids);
-                spec->pin_nids = stac92hd88xxx_pin_nids;
+                spec->pin_nids = stac92hd87xxx_pin_nids;
                spec->mono_nid = 0;
                spec->num_pwrs = 0;
                break;
@@ -5443,6 +5449,7 @@ again:
        case 0x111d7667:
        case 0x111d7668:
        case 0x111d7669:
+        case 0x111d76e3:
                spec->num_dmics = stac92xx_connected_ports(codec,
                                stac92hd88xxx_dmic_nids,
                                STAC92HD88XXX_NUM_DMICS);
@@ -6387,6 +6394,8 @@ static struct hda_codec_preset snd_hda_preset_sigmatel[] = {
        { .id = 0x111d76cd, .name = "92HD89F2", .patch = patch_stac92hd73xx },
        { .id = 0x111d76ce, .name = "92HD89F1", .patch = patch_stac92hd73xx },
        { .id = 0x111d76e0, .name = "92HD91BXX", .patch = patch_stac92hd83xxx},
+        { .id = 0x111d76e3, .name = "92HD98BXX", .patch = patch_stac92hd83xxx},
+        { .id = 0x111d76e5, .name = "92HD99BXX", .patch = patch_stac92hd83xxx},
        { .id = 0x111d76e7, .name = "92HD90BXX", .patch = patch_stac92hd83xxx},
        {} /* terminator */
 };
diff --git a/sound/pci/hda/patch_via.c b/sound/pci/hda/patch_via.c
index a76c3260d941..63b0054200a8 100644
--- a/sound/pci/hda/patch_via.c
+++ b/sound/pci/hda/patch_via.c
@@ -567,7 +567,7 @@ static void via_auto_init_analog_input(struct hda_codec *codec)
                hda_nid_t nid = cfg->inputs[i].pin;
                if (spec->smart51_enabled && is_smart51_pins(spec, nid))
                        ctl = PIN_OUT;
-                else if (i == AUTO_PIN_MIC)
+                else if (cfg->inputs[i].type == AUTO_PIN_MIC)
                        ctl = PIN_VREF50;
                else
                        ctl = PIN_IN;
diff --git a/sound/soc/codecs/cx20442.c b/sound/soc/codecs/cx20442.c
index bb4bf65b9e7e..0bb424af956f 100644
--- a/sound/soc/codecs/cx20442.c
+++ b/sound/soc/codecs/cx20442.c
@@ -367,7 +367,7 @@ static int cx20442_codec_remove(struct snd_soc_codec *codec)
        return 0;
 }
-static const u8 cx20442_reg = CX20442_TELOUT | CX20442_MIC;
+static const u8 cx20442_reg;
 static struct snd_soc_codec_driver cx20442_codec_dev = {
        .probe =        cx20442_codec_probe,
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index 987476a5895f..017d99ceb42e 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -1482,7 +1482,7 @@ int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
                            WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
                            irq_mask);
-        if (det && shrt) {
+        if (det || shrt) {
                /* Enable mic detection, this may not have been set through
                 * platform data (eg, if the defaults are OK). */
                snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
diff --git a/sound/soc/codecs/wm8903.h b/sound/soc/codecs/wm8903.h
index e8490f3edd03..e3ec2433b215 100644
--- a/sound/soc/codecs/wm8903.h
+++ b/sound/soc/codecs/wm8903.h
@@ -165,7 +165,7 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec,
 #define WM8903_VMID_RES_50K                          2
 #define WM8903_VMID_RES_250K                         3
-#define WM8903_VMID_RES_5K                           4
+#define WM8903_VMID_RES_5K                           6
 /*
 * R8 (0x08) - Analogue DAC 0
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 37b8aa8a680f..4afbe3b2e443 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -107,6 +107,12 @@ struct wm8994_priv {
        int revision;
        struct wm8994_pdata *pdata;
+        unsigned int aif1clk_enable:1;
+        unsigned int aif2clk_enable:1;
+        unsigned int aif1clk_disable:1;
+        unsigned int aif2clk_disable:1;
 };
 static int wm8994_readable(unsigned int reg)
@@ -1004,6 +1010,110 @@ static void wm8994_update_class_w(struct snd_soc_codec *codec)
        }
 }
+static int late_enable_ev(struct snd_soc_dapm_widget *w,
+                          struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                if (wm8994->aif1clk_enable) {
+                        snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
+                                            WM8994_AIF1CLK_ENA_MASK,
+                                            WM8994_AIF1CLK_ENA);
+                        wm8994->aif1clk_enable = 0;
+                }
+                if (wm8994->aif2clk_enable) {
+                        snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
+                                            WM8994_AIF2CLK_ENA_MASK,
+                                            WM8994_AIF2CLK_ENA);
+                        wm8994->aif2clk_enable = 0;
+                }
+                break;
+        }
+        return 0;
+}
+static int late_disable_ev(struct snd_soc_dapm_widget *w,
+                           struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMD:
+                if (wm8994->aif1clk_disable) {
+                        snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
+                                            WM8994_AIF1CLK_ENA_MASK, 0);
+                        wm8994->aif1clk_disable = 0;
+                }
+                if (wm8994->aif2clk_disable) {
+                        snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
+                                            WM8994_AIF2CLK_ENA_MASK, 0);
+                        wm8994->aif2clk_disable = 0;
+                }
+                break;
+        }
+        return 0;
+}
+static int aif1clk_ev(struct snd_soc_dapm_widget *w,
+                      struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                wm8994->aif1clk_enable = 1;
+                break;
+        case SND_SOC_DAPM_POST_PMD:
+                wm8994->aif1clk_disable = 1;
+                break;
+        }
+        return 0;
+}
+static int aif2clk_ev(struct snd_soc_dapm_widget *w,
+                      struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                wm8994->aif2clk_enable = 1;
+                break;
+        case SND_SOC_DAPM_POST_PMD:
+                wm8994->aif2clk_disable = 1;
+                break;
+        }
+        return 0;
+}
+static int adc_mux_ev(struct snd_soc_dapm_widget *w,
+                      struct snd_kcontrol *kcontrol, int event)
+{
+        late_enable_ev(w, kcontrol, event);
+        return 0;
+}
+static int dac_ev(struct snd_soc_dapm_widget *w,
+                  struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        unsigned int mask = 1 << w->shift;
+        snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+                            mask, mask);
+        return 0;
+}
 static const char *hp_mux_text[] = {
        "Mixer",
        "DAC",
@@ -1272,6 +1382,59 @@ static const struct soc_enum aif2dacr_src_enum =
 static const struct snd_kcontrol_new aif2dacr_src_mux =
        SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
+static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
+SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
+        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
+        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
+};
+static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
+SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
+};
+static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
+SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
+        dac_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
+        dac_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
+        dac_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
+        dac_ev, SND_SOC_DAPM_PRE_PMU),
+};
+static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
+SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
+SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
+SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
+SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
+};
+static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
+SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
+                   adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
+                   adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
+};
+static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
+SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
+SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
+};
 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
 SND_SOC_DAPM_INPUT("DMIC1DAT"),
 SND_SOC_DAPM_INPUT("DMIC2DAT"),
@@ -1284,9 +1447,6 @@ SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
-SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
-SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
                     0, WM8994_POWER_MANAGEMENT_4, 9, 0),
 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
@@ -1369,14 +1529,6 @@ SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
-SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
-SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
-SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
-SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
-SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
-SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
@@ -1516,14 +1668,12 @@ static const struct snd_soc_dapm_route intercon[] = {
        { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
        /* DAC1 inputs */
-        { "DAC1L", NULL, "DAC1L Mixer" },
        { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
        { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
        { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
        { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
        { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
-        { "DAC1R", NULL, "DAC1R Mixer" },
        { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
        { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
        { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
@@ -1532,7 +1682,6 @@ static const struct snd_soc_dapm_route intercon[] = {
        /* DAC2/AIF2 outputs  */
        { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
-        { "DAC2L", NULL, "AIF2DAC2L Mixer" },
        { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
        { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
        { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
@@ -1540,7 +1689,6 @@ static const struct snd_soc_dapm_route intercon[] = {
        { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
        { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
-        { "DAC2R", NULL, "AIF2DAC2R Mixer" },
        { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
        { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
        { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
@@ -1584,6 +1732,24 @@ static const struct snd_soc_dapm_route intercon[] = {
        { "Right Headphone Mux", "DAC", "DAC1R" },
 };
+static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
+        { "DAC1L", NULL, "Late DAC1L Enable PGA" },
+        { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
+        { "DAC1R", NULL, "Late DAC1R Enable PGA" },
+        { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
+        { "DAC2L", NULL, "Late DAC2L Enable PGA" },
+        { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
+        { "DAC2R", NULL, "Late DAC2R Enable PGA" },
+        { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
+};
+static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
+        { "DAC1L", NULL, "DAC1L Mixer" },
+        { "DAC1R", NULL, "DAC1R Mixer" },
+        { "DAC2L", NULL, "AIF2DAC2L Mixer" },
+        { "DAC2R", NULL, "AIF2DAC2R Mixer" },
+};
 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
        { "AIF1DACDAT", NULL, "AIF2DACDAT" },
        { "AIF2DACDAT", NULL, "AIF1DACDAT" },
@@ -2514,6 +2680,22 @@ static int wm8994_resume(struct snd_soc_codec *codec)
 {
        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
        int i, ret;
+        unsigned int val, mask;
+        if (wm8994->revision < 4) {
+                /* force a HW read */
+                val = wm8994_reg_read(codec->control_data,
+                                      WM8994_POWER_MANAGEMENT_5);
+                /* modify the cache only */
+                codec->cache_only = 1;
+                mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
+                        WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
+                val &= mask;
+                snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+                                    mask, val);
+                codec->cache_only = 0;
+        }
        /* Restore the registers */
        ret = snd_soc_cache_sync(codec);
@@ -2847,11 +3029,10 @@ static void wm8958_default_micdet(u16 status, void *data)
                report |= SND_JACK_BTN_5;
 done:
-        snd_soc_jack_report(wm8994->micdet[0].jack,
+        snd_soc_jack_report(wm8994->micdet[0].jack, report,
                            SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
                            SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
-                            SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT,
+                            SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT);
-                            report);
 }
 /**
@@ -3125,6 +3306,21 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec)
        case WM8994:
                snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
                                          ARRAY_SIZE(wm8994_specific_dapm_widgets));
+                if (wm8994->revision < 4) {
+                        snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
+                                                  ARRAY_SIZE(wm8994_lateclk_revd_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
+                                                  ARRAY_SIZE(wm8994_adc_revd_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
+                                                  ARRAY_SIZE(wm8994_dac_revd_widgets));
+                } else {
+                        snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
+                                                  ARRAY_SIZE(wm8994_lateclk_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
+                                                  ARRAY_SIZE(wm8994_adc_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
+                                                  ARRAY_SIZE(wm8994_dac_widgets));
+                }
                break;
        case WM8958:
                snd_soc_add_controls(codec, wm8958_snd_controls,
@@ -3143,10 +3339,15 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec)
                snd_soc_dapm_add_routes(dapm, wm8994_intercon,
                                        ARRAY_SIZE(wm8994_intercon));
-                if (wm8994->revision < 4)
+                if (wm8994->revision < 4) {
                        snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
                                                ARRAY_SIZE(wm8994_revd_intercon));
-                        
+                        snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
+                                                ARRAY_SIZE(wm8994_lateclk_revd_intercon));
+                } else {
+                        snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
+                                                ARRAY_SIZE(wm8994_lateclk_intercon));
+                }
                break;
        case WM8958:
                snd_soc_dapm_add_routes(dapm, wm8958_intercon,
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c
index 43825b2102a5..cce704c275c6 100644
--- a/sound/soc/codecs/wm9081.c
+++ b/sound/soc/codecs/wm9081.c
@@ -15,6 +15,7 @@
 #include <linux/moduleparam.h>
 #include <linux/init.h>
 #include <linux/delay.h>
+#include <linux/device.h>
 #include <linux/pm.h>
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
@@ -1341,6 +1342,10 @@ static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
        wm9081->control_type = SND_SOC_I2C;
        wm9081->control_data = i2c;
+        if (dev_get_platdata(&i2c->dev))
+                memcpy(&wm9081->retune, dev_get_platdata(&i2c->dev),
+                       sizeof(wm9081->retune));
        ret = snd_soc_register_codec(&i2c->dev,
                        &soc_codec_dev_wm9081, &wm9081_dai, 1);
        if (ret < 0)
diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c
index 613df5db0b32..516892706063 100644
--- a/sound/soc/codecs/wm_hubs.c
+++ b/sound/soc/codecs/wm_hubs.c
@@ -674,6 +674,9 @@ SND_SOC_DAPM_OUTPUT("LINEOUT2N"),
 };
 static const struct snd_soc_dapm_route analogue_routes[] = {
+        { "MICBIAS1", NULL, "CLK_SYS" },
+        { "MICBIAS2", NULL, "CLK_SYS" },
        { "IN1L PGA", "IN1LP Switch", "IN1LP" },
        { "IN1L PGA", "IN1LN Switch", "IN1LN" },
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index 642270a635ea..9eeb8f0d67e9 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -44,7 +44,8 @@ config SND_SOC_EUKREA_TLV320
        tristate "Eukrea TLV320"
        depends on MACH_EUKREA_MBIMX27_BASEBOARD \
                || MACH_EUKREA_MBIMXSD25_BASEBOARD \
-                || MACH_EUKREA_MBIMXSD35_BASEBOARD
+                || MACH_EUKREA_MBIMXSD35_BASEBOARD \
+                || MACH_EUKREA_MBIMXSD51_BASEBOARD
        select SND_SOC_TLV320AIC23
        select SND_MXC_SOC_SSI
        select SND_MXC_SOC_FIQ
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/imx/eukrea-tlv320.c
index e20c9e1457c0..75fb4b83548b 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/imx/eukrea-tlv320.c
@@ -79,7 +79,7 @@ static struct snd_soc_dai_link eukrea_tlv320_dai = {
        .name           = "tlv320aic23",
        .stream_name    = "TLV320AIC23",
        .codec_dai_name = "tlv320aic23-hifi",
-        .platform_name  = "imx-pcm-audio.0",
+        .platform_name  = "imx-fiq-pcm-audio.0",
        .codec_name     = "tlv320aic23-codec.0-001a",
        .cpu_dai_name   = "imx-ssi.0",
        .ops            = &eukrea_tlv320_snd_ops,
@@ -98,7 +98,8 @@ static int __init eukrea_tlv320_init(void)
        int ret;
        if (!machine_is_eukrea_cpuimx27() && !machine_is_eukrea_cpuimx25sd()
-                && !machine_is_eukrea_cpuimx35sd())
+                && !machine_is_eukrea_cpuimx35sd()
+                && !machine_is_eukrea_cpuimx51sd())
                /* return happy. We might run on a totally different machine */
                return 0;
diff --git a/sound/soc/pxa/e740_wm9705.c b/sound/soc/pxa/e740_wm9705.c
index 28333e7d9c50..dc65650a6fa1 100644
--- a/sound/soc/pxa/e740_wm9705.c
+++ b/sound/soc/pxa/e740_wm9705.c
@@ -117,7 +117,7 @@ static struct snd_soc_dai_link e740_dai[] = {
        {
                .name = "AC97",
                .stream_name = "AC97 HiFi",
-                .cpu_dai_name = "pxa-ac97.0",
+                .cpu_dai_name = "pxa2xx-ac97",
                .codec_dai_name = "wm9705-hifi",
                .platform_name = "pxa-pcm-audio",
                .codec_name = "wm9705-codec",
@@ -126,7 +126,7 @@ static struct snd_soc_dai_link e740_dai[] = {
        {
                .name = "AC97 Aux",
                .stream_name = "AC97 Aux",
-                .cpu_dai_name = "pxa-ac97.1",
+                .cpu_dai_name = "pxa2xx-ac97-aux",
                .codec_dai_name = "wm9705-aux",
                .platform_name = "pxa-pcm-audio",
                .codec_name = "wm9705-codec",
diff --git a/sound/soc/pxa/e750_wm9705.c b/sound/soc/pxa/e750_wm9705.c
index 01bf31675c55..51897fcd911b 100644
--- a/sound/soc/pxa/e750_wm9705.c
+++ b/sound/soc/pxa/e750_wm9705.c
@@ -99,7 +99,7 @@ static struct snd_soc_dai_link e750_dai[] = {
        {
                .name = "AC97",
                .stream_name = "AC97 HiFi",
-                .cpu_dai_name = "pxa-ac97.0",
+                .cpu_dai_name = "pxa2xx-ac97",
                .codec_dai_name = "wm9705-hifi",
                .platform_name = "pxa-pcm-audio",
                .codec_name = "wm9705-codec",
@@ -109,7 +109,7 @@ static struct snd_soc_dai_link e750_dai[] = {
        {
                .name = "AC97 Aux",
                .stream_name = "AC97 Aux",
-                .cpu_dai_name = "pxa-ac97.1",
+                .cpu_dai_name = "pxa2xx-ac97-aux",
                .codec_dai_name ="wm9705-aux",
                .platform_name = "pxa-pcm-audio",
                .codec_name = "wm9705-codec",
diff --git a/sound/soc/pxa/e800_wm9712.c b/sound/soc/pxa/e800_wm9712.c
index c6a37c6ef23b..053ed208e59f 100644
--- a/sound/soc/pxa/e800_wm9712.c
+++ b/sound/soc/pxa/e800_wm9712.c
@@ -89,7 +89,7 @@ static struct snd_soc_dai_link e800_dai[] = {
        {
                .name = "AC97",
                .stream_name = "AC97 HiFi",
-                .cpu_dai_name = "pxa-ac97.0",
+                .cpu_dai_name = "pxa2xx-ac97",
                .codec_dai_name = "wm9712-hifi",
                .platform_name = "pxa-pcm-audio",
                .codec_name = "wm9712-codec",
@@ -98,7 +98,7 @@ static struct snd_soc_dai_link e800_dai[] = {
        {
                .name = "AC97 Aux",
                .stream_name = "AC97 Aux",
-                .cpu_dai_name = "pxa-ac97.1",
+                .cpu_dai_name = "pxa2xx-ac97-aux",
                .codec_dai_name ="wm9712-aux",
                .platform_name = "pxa-pcm-audio",
                .codec_name = "wm9712-codec",
diff --git a/sound/soc/pxa/em-x270.c b/sound/soc/pxa/em-x270.c
index fc22e6eefc98..b13a4252812d 100644
--- a/sound/soc/pxa/em-x270.c
+++ b/sound/soc/pxa/em-x270.c
@@ -37,7 +37,7 @@ static struct snd_soc_dai_link em_x270_dai[] = {
        {
                .name = "AC97",
                .stream_name = "AC97 HiFi",
-                .cpu_dai_name = "pxa-ac97.0",
+                .cpu_dai_name = "pxa2xx-ac97",
                .codec_dai_name = "wm9712-hifi",
                .platform_name = "pxa-pcm-audio",
                .codec_name = "wm9712-codec",
@@ -45,7 +45,7 @@ static struct snd_soc_dai_link em_x270_dai[] = {
        {
                .name = "AC97 Aux",
                .stream_name = "AC97 Aux",
-                .cpu_dai_name = "pxa-ac97.1",
+                .cpu_dai_name = "pxa2xx-ac97-aux",
                .codec_dai_name ="wm9712-aux",
                .platform_name = "pxa-pcm-audio",
                .codec_name = "wm9712-codec",
diff --git a/sound/soc/pxa/mioa701_wm9713.c b/sound/soc/pxa/mioa701_wm9713.c
index 0d70fc8c12bd..38ca6759907e 100644
--- a/sound/soc/pxa/mioa701_wm9713.c
+++ b/sound/soc/pxa/mioa701_wm9713.c
@@ -162,7 +162,7 @@ static struct snd_soc_dai_link mioa701_dai[] = {
        {
                .name = "AC97",
                .stream_name = "AC97 HiFi",
-                .cpu_dai_name = "pxa-ac97.0",
+                .cpu_dai_name = "pxa2xx-ac97",
                .codec_dai_name = "wm9713-hifi",
                .codec_name = "wm9713-codec",
                .init = mioa701_wm9713_init,
@@ -172,7 +172,7 @@ static struct snd_soc_dai_link mioa701_dai[] = {
        {
                .name = "AC97 Aux",
                .stream_name = "AC97 Aux",
-                .cpu_dai_name = "pxa-ac97.1",
+                .cpu_dai_name = "pxa2xx-ac97-aux",
                .codec_dai_name ="wm9713-aux",
                .codec_name = "wm9713-codec",
                .platform_name = "pxa-pcm-audio",
diff --git a/sound/soc/pxa/palm27x.c b/sound/soc/pxa/palm27x.c
index 857db96d4a4f..504e4004f004 100644
--- a/sound/soc/pxa/palm27x.c
+++ b/sound/soc/pxa/palm27x.c
@@ -132,7 +132,7 @@ static struct snd_soc_dai_link palm27x_dai[] = {
 {
        .name = "AC97 HiFi",
        .stream_name = "AC97 HiFi",
-        .cpu_dai_name = "pxa-ac97.0",
+        .cpu_dai_name = "pxa2xx-ac97",
        .codec_dai_name =  "wm9712-hifi",
        .codec_name = "wm9712-codec",
        .platform_name = "pxa-pcm-audio",
@@ -141,7 +141,7 @@ static struct snd_soc_dai_link palm27x_dai[] = {
 {
        .name = "AC97 Aux",
        .stream_name = "AC97 Aux",
-        .cpu_dai_name = "pxa-ac97.1",
+        .cpu_dai_name = "pxa2xx-ac97-aux",
        .codec_dai_name = "wm9712-aux",
        .codec_name = "wm9712-codec",
        .platform_name = "pxa-pcm-audio",
diff --git a/sound/soc/pxa/tosa.c b/sound/soc/pxa/tosa.c
index f75804ef0897..4b6e5d608b42 100644
--- a/sound/soc/pxa/tosa.c
+++ b/sound/soc/pxa/tosa.c
@@ -219,7 +219,7 @@ static struct snd_soc_dai_link tosa_dai[] = {
 {
        .name = "AC97",
        .stream_name = "AC97 HiFi",
-        .cpu_dai_name = "pxa-ac97.0",
+        .cpu_dai_name = "pxa2xx-ac97",
        .codec_dai_name = "wm9712-hifi",
        .platform_name = "pxa-pcm-audio",
        .codec_name = "wm9712-codec",
@@ -229,7 +229,7 @@ static struct snd_soc_dai_link tosa_dai[] = {
 {
        .name = "AC97 Aux",
        .stream_name = "AC97 Aux",
-        .cpu_dai_name = "pxa-ac97.1",
+        .cpu_dai_name = "pxa2xx-ac97-aux",
        .codec_dai_name = "wm9712-aux",
        .platform_name = "pxa-pcm-audio",
        .codec_name = "wm9712-codec",
diff --git a/sound/soc/pxa/zylonite.c b/sound/soc/pxa/zylonite.c
index b222a7d72027..25bba108fea3 100644
--- a/sound/soc/pxa/zylonite.c
+++ b/sound/soc/pxa/zylonite.c
@@ -166,7 +166,7 @@ static struct snd_soc_dai_link zylonite_dai[] = {
        .stream_name = "AC97 HiFi",
        .codec_name = "wm9713-codec",
        .platform_name = "pxa-pcm-audio",
-        .cpu_dai_name = "pxa-ac97.0",
+        .cpu_dai_name = "pxa2xx-ac97",
        .codec_name = "wm9713-hifi",
        .init = zylonite_wm9713_init,
 },
@@ -175,7 +175,7 @@ static struct snd_soc_dai_link zylonite_dai[] = {
        .stream_name = "AC97 Aux",
        .codec_name = "wm9713-codec",
        .platform_name = "pxa-pcm-audio",
-        .cpu_dai_name = "pxa-ac97.1",
+        .cpu_dai_name = "pxa2xx-ac97-aux",
        .codec_name = "wm9713-aux",
 },
 {
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 8194f150bab7..25e54230cc6a 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -712,7 +712,15 @@ static int dapm_supply_check_power(struct snd_soc_dapm_widget *w)
                    !path->connected(path->source, path->sink))
                        continue;
-                if (path->sink && path->sink->power_check &&
+                if (!path->sink)
+                        continue;
+                if (path->sink->force) {
+                        power = 1;
+                        break;
+                }
+                if (path->sink->power_check &&
                    path->sink->power_check(path->sink)) {
                        power = 1;
                        break;
@@ -1627,6 +1635,7 @@ EXPORT_SYMBOL_GPL(snd_soc_dapm_add_routes);
 int snd_soc_dapm_new_widgets(struct snd_soc_dapm_context *dapm)
 {
        struct snd_soc_dapm_widget *w;
+        unsigned int val;
        list_for_each_entry(w, &dapm->card->widgets, list)
        {
@@ -1675,6 +1684,18 @@ int snd_soc_dapm_new_widgets(struct snd_soc_dapm_context *dapm)
                case snd_soc_dapm_post:
                        break;
                }
+                /* Read the initial power state from the device */
+                if (w->reg >= 0) {
+                        val = snd_soc_read(w->codec, w->reg);
+                        val &= 1 << w->shift;
+                        if (w->invert)
+                                val = !val;
+                        if (val)
+                                w->power = 1;
+                }
                w->new = 1;
        }
diff --git a/sound/usb/card.c b/sound/usb/card.c
index 800f7cb4f251..c0f8270bc199 100644
--- a/sound/usb/card.c
+++ b/sound/usb/card.c
@@ -323,6 +323,7 @@ static int snd_usb_audio_create(struct usb_device *dev, int idx,
                return -ENOMEM;
        }
+        mutex_init(&chip->shutdown_mutex);
        chip->index = idx;
        chip->dev = dev;
        chip->card = card;
@@ -531,6 +532,7 @@ static void snd_usb_audio_disconnect(struct usb_device *dev, void *ptr)
        chip = ptr;
        card = chip->card;
        mutex_lock(&register_mutex);
+        mutex_lock(&chip->shutdown_mutex);
        chip->shutdown = 1;
        chip->num_interfaces--;
        if (chip->num_interfaces <= 0) {
@@ -548,9 +550,11 @@ static void snd_usb_audio_disconnect(struct usb_device *dev, void *ptr)
                        snd_usb_mixer_disconnect(p);
                }
                usb_chip[chip->index] = NULL;
+                mutex_unlock(&chip->shutdown_mutex);
                mutex_unlock(&register_mutex);
                snd_card_free_when_closed(card);
        } else {
+                mutex_unlock(&chip->shutdown_mutex);
                mutex_unlock(&register_mutex);
        }
 }
diff --git a/sound/usb/pcm.c b/sound/usb/pcm.c
index 4132522ac90f..e3f680526cb5 100644
--- a/sound/usb/pcm.c
+++ b/sound/usb/pcm.c
@@ -361,6 +361,7 @@ static int snd_usb_hw_params(struct snd_pcm_substream *substream,
        }
        if (changed) {
+                mutex_lock(&subs->stream->chip->shutdown_mutex);
                /* format changed */
                snd_usb_release_substream_urbs(subs, 0);
                /* influenced: period_bytes, channels, rate, format, */
@@ -368,6 +369,7 @@ static int snd_usb_hw_params(struct snd_pcm_substream *substream,
                                                  params_rate(hw_params),
                                                  snd_pcm_format_physical_width(params_format(hw_params)) *
                                                        params_channels(hw_params));
+                mutex_unlock(&subs->stream->chip->shutdown_mutex);
        }
        return ret;
@@ -385,8 +387,9 @@ static int snd_usb_hw_free(struct snd_pcm_substream *substream)
        subs->cur_audiofmt = NULL;
        subs->cur_rate = 0;
        subs->period_bytes = 0;
-        if (!subs->stream->chip->shutdown)
+        mutex_lock(&subs->stream->chip->shutdown_mutex);
-                snd_usb_release_substream_urbs(subs, 0);
+        snd_usb_release_substream_urbs(subs, 0);
+        mutex_unlock(&subs->stream->chip->shutdown_mutex);
        return snd_pcm_lib_free_vmalloc_buffer(substream);
 }
diff --git a/sound/usb/usbaudio.h b/sound/usb/usbaudio.h
index db3eb21627ee..6e66fffe87f5 100644
--- a/sound/usb/usbaudio.h
+++ b/sound/usb/usbaudio.h
@@ -36,6 +36,7 @@ struct snd_usb_audio {
        struct snd_card *card;
        u32 usb_id;
        int shutdown;
+        struct mutex shutdown_mutex;
        unsigned int txfr_quirk:1; /* Subframe boundaries on transfers */
        int num_interfaces;
        int num_suspended_intf;
diff --git a/tools/perf/builtin-timechart.c b/tools/perf/builtin-timechart.c
index 746cf03cb05d..0ace786e83e0 100644
--- a/tools/perf/builtin-timechart.c
+++ b/tools/perf/builtin-timechart.c
@@ -264,9 +264,6 @@ pid_put_sample(int pid, int type, unsigned int cpu, u64 start, u64 end)
                c->start_time = start;
        if (p->start_time == 0 || p->start_time > start)
                p->start_time = start;
-        if (cpu > numcpus)
-                numcpus = cpu;
 }
 #define MAX_CPUS 4096
@@ -511,6 +508,9 @@ static int process_sample_event(event_t *event __used,
                if (!event_str)
                        return 0;
+                if (sample->cpu > numcpus)
+                        numcpus = sample->cpu;
                if (strcmp(event_str, "power:cpu_idle") == 0) {
                        struct power_processor_entry *ppe = (void *)te;
                        if (ppe->state == (u32)PWR_EVENT_EXIT)
diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c
index 32f4f1f2f6e4..df51560f16f7 100644
--- a/tools/perf/util/hist.c
+++ b/tools/perf/util/hist.c
@@ -585,6 +585,7 @@ int hist_entry__snprintf(struct hist_entry *self, char *s, size_t size,
 {
        struct sort_entry *se;
        u64 period, total, period_sys, period_us, period_guest_sys, period_guest_us;
+        u64 nr_events;
        const char *sep = symbol_conf.field_sep;
        int ret;
@@ -593,6 +594,7 @@ int hist_entry__snprintf(struct hist_entry *self, char *s, size_t size,
        if (pair_hists) {
                period = self->pair ? self->pair->period : 0;
+                nr_events = self->pair ? self->pair->nr_events : 0;
                total = pair_hists->stats.total_period;
                period_sys = self->pair ? self->pair->period_sys : 0;
                period_us = self->pair ? self->pair->period_us : 0;
@@ -600,6 +602,7 @@ int hist_entry__snprintf(struct hist_entry *self, char *s, size_t size,
                period_guest_us = self->pair ? self->pair->period_guest_us : 0;
        } else {
                period = self->period;
+                nr_events = self->nr_events;
                total = session_total;
                period_sys = self->period_sys;
                period_us = self->period_us;
@@ -640,9 +643,9 @@ int hist_entry__snprintf(struct hist_entry *self, char *s, size_t size,
        if (symbol_conf.show_nr_samples) {
                if (sep)
-                        ret += snprintf(s + ret, size - ret, "%c%" PRIu64, *sep, period);
+                        ret += snprintf(s + ret, size - ret, "%c%" PRIu64, *sep, nr_events);
                else
-                        ret += snprintf(s + ret, size - ret, "%11" PRIu64, period);
+                        ret += snprintf(s + ret, size - ret, "%11" PRIu64, nr_events);
        }
        if (pair_hists) {
diff --git a/tools/perf/util/svghelper.c b/tools/perf/util/svghelper.c
index fb737fe9be91..96c866045d60 100644
--- a/tools/perf/util/svghelper.c
+++ b/tools/perf/util/svghelper.c
@@ -456,9 +456,9 @@ void svg_legenda(void)
                return;
        svg_legenda_box(0,      "Running", "sample");
-        svg_legenda_box(100,    "Idle","rect.c1");
+        svg_legenda_box(100,    "Idle","c1");
-        svg_legenda_box(200,    "Deeper Idle", "rect.c3");
+        svg_legenda_box(200,    "Deeper Idle", "c3");
-        svg_legenda_box(350,    "Deepest Idle", "rect.c6");
+        svg_legenda_box(350,    "Deepest Idle", "c6");
        svg_legenda_box(550,    "Sleeping", "process2");
        svg_legenda_box(650,    "Waiting for cpu", "waiting");
        svg_legenda_box(800,    "Blocked on IO", "blocked");