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-rw-r--r--arch/arm/mach-dove/Kconfig6
-rw-r--r--arch/arm/mach-dove/Makefile3
-rw-r--r--arch/arm/mach-dove/cm-a510.c95
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h9
-rw-r--r--arch/arm/mach-dove/include/mach/gpio.h6
-rw-r--r--arch/arm/mach-dove/mpp.c212
-rw-r--r--arch/arm/mach-dove/mpp.h220
-rw-r--r--arch/arm/mach-kirkwood/Kconfig12
-rw-r--r--arch/arm/mach-kirkwood/ts219-setup.c16
-rw-r--r--arch/arm/mach-kirkwood/ts41x-setup.c9
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/mv78xx0.h2
-rw-r--r--arch/arm/mach-orion5x/Kconfig7
-rw-r--r--arch/arm/mach-orion5x/Makefile1
-rw-r--r--arch/arm/mach-orion5x/ls-chl-setup.c327
14 files changed, 912 insertions, 13 deletions
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 3b9a32ace909..a4ed3900912a 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -9,6 +9,12 @@ config MACH_DOVE_DB
9 Say 'Y' here if you want your kernel to support the 9 Say 'Y' here if you want your kernel to support the
10 Marvell DB-MV88AP510 Development Board. 10 Marvell DB-MV88AP510 Development Board.
11 11
12 config MACH_CM_A510
13 bool "CompuLab CM-A510 Board"
14 help
15 Say 'Y' here if you want your kernel to support the
16 CompuLab CM-A510 Board.
17
12endmenu 18endmenu
13 19
14endif 20endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 7ab3be53f642..fa0f01856060 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,3 +1,4 @@
1obj-y += common.o addr-map.o irq.o pcie.o 1obj-y += common.o addr-map.o irq.o pcie.o mpp.o
2 2
3obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o 3obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
4obj-$(CONFIG_MACH_CM_A510) += cm-a510.o
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
new file mode 100644
index 000000000000..96e0e94e5fa9
--- /dev/null
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -0,0 +1,95 @@
1/*
2 * arch/arm/mach-dove/cm-a510.c
3 *
4 * Copyright (C) 2010 CompuLab, Ltd.
5 * Konstantin Sinyuk <kostyas@compulab.co.il>
6 *
7 * Based on Marvell DB-MV88AP510-BP Development Board Setup
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/ata_platform.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/flash.h>
21
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24
25#include <mach/dove.h>
26
27#include "common.h"
28
29static struct mv643xx_eth_platform_data cm_a510_ge00_data = {
30 .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
31};
32
33static struct mv_sata_platform_data cm_a510_sata_data = {
34 .n_ports = 1,
35};
36
37/*
38 * SPI Devices:
39 * SPI0: 1M Flash Winbond w25q32bv
40 */
41static const struct flash_platform_data cm_a510_spi_flash_data = {
42 .type = "w25q32bv",
43};
44
45static struct spi_board_info __initdata cm_a510_spi_flash_info[] = {
46 {
47 .modalias = "m25p80",
48 .platform_data = &cm_a510_spi_flash_data,
49 .irq = -1,
50 .max_speed_hz = 20000000,
51 .bus_num = 0,
52 .chip_select = 0,
53 },
54};
55
56static int __init cm_a510_pci_init(void)
57{
58 if (machine_is_cm_a510())
59 dove_pcie_init(1, 1);
60
61 return 0;
62}
63
64subsys_initcall(cm_a510_pci_init);
65
66/* Board Init */
67static void __init cm_a510_init(void)
68{
69 /*
70 * Basic Dove setup. Needs to be called early.
71 */
72 dove_init();
73
74 dove_ge00_init(&cm_a510_ge00_data);
75 dove_ehci0_init();
76 dove_ehci1_init();
77 dove_sata_init(&cm_a510_sata_data);
78 dove_sdio0_init();
79 dove_sdio1_init();
80 dove_spi0_init();
81 dove_spi1_init();
82 dove_uart0_init();
83 dove_uart1_init();
84 dove_i2c_init();
85 spi_register_board_info(cm_a510_spi_flash_info,
86 ARRAY_SIZE(cm_a510_spi_flash_info));
87}
88
89MACHINE_START(CM_A510, "Compulab CM-A510 Board")
90 .boot_params = 0x00000100,
91 .init_machine = cm_a510_init,
92 .map_io = dove_map_io,
93 .init_irq = dove_init_irq,
94 .timer = &dove_timer,
95MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index f6a08397f046..27b414578f2e 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -131,14 +131,21 @@
131#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) 131#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
132#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) 132#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
133#define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) 133#define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
134#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
134#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) 135#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
135#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) 136#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
136#define DOVE_NAND_GPIO_EN (1 << 0) 137#define DOVE_NAND_GPIO_EN (1 << 0)
137#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) 138#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40)
138 139#define DOVE_SPI_GPIO_SEL (1 << 5)
140#define DOVE_UART1_GPIO_SEL (1 << 4)
141#define DOVE_AU1_GPIO_SEL (1 << 3)
142#define DOVE_CAM_GPIO_SEL (1 << 2)
143#define DOVE_SD1_GPIO_SEL (1 << 1)
144#define DOVE_SD0_GPIO_SEL (1 << 0)
139 145
140/* Power Management */ 146/* Power Management */
141#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) 147#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
148#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
142 149
143/* Real Time Clock */ 150/* Real Time Clock */
144#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500) 151#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
index 0ee70ff39e11..340bb7af529d 100644
--- a/arch/arm/mach-dove/include/mach/gpio.h
+++ b/arch/arm/mach-dove/include/mach/gpio.h
@@ -14,12 +14,14 @@
14#include <plat/gpio.h> 14#include <plat/gpio.h>
15#include <asm-generic/gpio.h> /* cansleep wrappers */ 15#include <asm-generic/gpio.h> /* cansleep wrappers */
16 16
17#define GPIO_MAX 64 17#define GPIO_MAX 72
18 18
19#define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00) 19#define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00)
20#define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20) 20#define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20)
21 21
22#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI) 22#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : \
23 ((pin < 64) ? GPIO_BASE_HI : \
24 DOVE_GPIO2_VIRT_BASE))
23 25
24#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00) 26#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00)
25#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04) 27#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04)
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
new file mode 100644
index 000000000000..71db2bdf2f28
--- /dev/null
+++ b/arch/arm/mach-dove/mpp.c
@@ -0,0 +1,212 @@
1/*
2 * arch/arm/mach-dove/mpp.c
3 *
4 * MPP functions for Marvell Dove SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/gpio.h>
13#include <linux/io.h>
14
15#include <mach/dove.h>
16
17#include "mpp.h"
18
19#define MPP_NR_REGS 4
20#define MPP_CTRL(i) ((i) == 3 ? \
21 DOVE_MPP_CTRL4_VIRT_BASE : \
22 DOVE_MPP_VIRT_BASE + (i) * 4)
23#define PMU_SIG_REGS 2
24#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
25
26struct dove_mpp_grp {
27 int start;
28 int end;
29};
30
31static struct dove_mpp_grp dove_mpp_grp[] = {
32 [MPP_24_39] = {
33 .start = 24,
34 .end = 39,
35 },
36 [MPP_40_45] = {
37 .start = 40,
38 .end = 45,
39 },
40 [MPP_46_51] = {
41 .start = 40,
42 .end = 45,
43 },
44 [MPP_58_61] = {
45 .start = 58,
46 .end = 61,
47 },
48 [MPP_62_63] = {
49 .start = 62,
50 .end = 63,
51 },
52};
53
54static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
55{
56 int i;
57
58 for (i = start; i <= end; i++)
59 orion_gpio_set_valid(i, gpio_mode);
60}
61
62static void dove_mpp_dump_regs(void)
63{
64#ifdef DEBUG
65 int i;
66
67 pr_debug("MPP_CTRL regs:");
68 for (i = 0; i < MPP_NR_REGS; i++)
69 printk(" %08x", readl(MPP_CTRL(i)));
70 printk("\n");
71
72 pr_debug("PMU_SIG_CTRL regs:");
73 for (i = 0; i < PMU_SIG_REGS; i++)
74 printk(" %08x", readl(PMU_SIG_CTRL(i)));
75 printk("\n");
76
77 pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
78 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
79#endif
80}
81
82static void dove_mpp_cfg_nfc(int sel)
83{
84 u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
85
86 mpp_gen_cfg &= ~0x1;
87 mpp_gen_cfg |= sel;
88 writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE);
89
90 dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
91}
92
93static void dove_mpp_cfg_au1(int sel)
94{
95 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
96 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
97 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
98 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
99
100 mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL);
101 ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1);
102 mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN);
103 global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO);
104
105 if (!sel || sel == 0x2)
106 dove_mpp_gpio_mode(52, 57, 0);
107 else
108 dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
109
110 if (sel & 0x1) {
111 global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO;
112 dove_mpp_gpio_mode(56, 57, 0);
113 }
114 if (sel & 0x2) {
115 mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN;
116 dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
117 }
118 if (sel & 0x4) {
119 ssp_ctrl1 |= DOVE_SSP_ON_AU1;
120 dove_mpp_gpio_mode(52, 55, 0);
121 }
122 if (sel & 0x8)
123 mpp_ctrl4 |= DOVE_AU1_GPIO_SEL;
124
125 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
126 writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1);
127 writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE);
128 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
129}
130
131static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl)
132{
133 int start = dove_mpp_grp[num].start;
134 int end = dove_mpp_grp[num].end;
135 int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
136
137 *mpp_ctrl &= ~(0x1 << num);
138 *mpp_ctrl |= sel << num;
139
140 dove_mpp_gpio_mode(start, end, gpio_mode);
141}
142
143void __init dove_mpp_conf(unsigned int *mpp_list)
144{
145 u32 mpp_ctrl[MPP_NR_REGS];
146 u32 pmu_mpp_ctrl = 0;
147 u32 pmu_sig_ctrl[PMU_SIG_REGS];
148 int i;
149
150 /* Initialize gpiolib. */
151 orion_gpio_init();
152
153 for (i = 0; i < MPP_NR_REGS; i++)
154 mpp_ctrl[i] = readl(MPP_CTRL(i));
155
156 for (i = 0; i < PMU_SIG_REGS; i++)
157 pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
158
159 pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
160
161 dove_mpp_dump_regs();
162
163 for ( ; *mpp_list != MPP_END; mpp_list++) {
164 unsigned int num = MPP_NUM(*mpp_list);
165 unsigned int sel = MPP_SEL(*mpp_list);
166 int shift, gpio_mode;
167
168 if (num > MPP_MAX) {
169 pr_err("dove: invalid MPP number (%u)\n", num);
170 continue;
171 }
172
173 if (*mpp_list & MPP_NFC_MASK) {
174 dove_mpp_cfg_nfc(sel);
175 continue;
176 }
177
178 if (*mpp_list & MPP_AU1_MASK) {
179 dove_mpp_cfg_au1(sel);
180 continue;
181 }
182
183 if (*mpp_list & MPP_GRP_MASK) {
184 dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]);
185 continue;
186 }
187
188 shift = (num & 7) << 2;
189 if (*mpp_list & MPP_PMU_MASK) {
190 pmu_mpp_ctrl |= (0x1 << num);
191 pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
192 pmu_sig_ctrl[num / 8] |= 0xf << shift;
193 gpio_mode = 0;
194 } else {
195 mpp_ctrl[num / 8] &= ~(0xf << shift);
196 mpp_ctrl[num / 8] |= sel << shift;
197 gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
198 }
199
200 orion_gpio_set_valid(num, gpio_mode);
201 }
202
203 for (i = 0; i < MPP_NR_REGS; i++)
204 writel(mpp_ctrl[i], MPP_CTRL(i));
205
206 for (i = 0; i < PMU_SIG_REGS; i++)
207 writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i));
208
209 writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL);
210
211 dove_mpp_dump_regs();
212}
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
new file mode 100644
index 000000000000..2a43ce413b15
--- /dev/null
+++ b/arch/arm/mach-dove/mpp.h
@@ -0,0 +1,220 @@
1#ifndef __ARCH_DOVE_MPP_CODED_H
2#define __ARCH_DOVE_MPP_CODED_H
3
4#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \
5/* MPP/group number */ ((_num) & 0xff) | \
6/* MPP select value */ (((_mode) & 0xf) << 8) | \
7/* MPP PMU */ ((!!(_pmu)) << 12) | \
8/* group flag */ ((!!(_grp)) << 13) | \
9/* AU1 flag */ ((!!(_au1)) << 14) | \
10/* NFCE flag */ ((!!(_nfc)) << 15))
11
12#define MPP_MAX 71
13
14#define MPP_NUM(x) ((x) & 0xff)
15#define MPP_SEL(x) (((x) >> 8) & 0xf)
16
17#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0)
18#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0)
19#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0)
20#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1)
21
22#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1)
23
24#define MPP_PMU_DRIVE_0 0x1
25#define MPP_PMU_DRIVE_1 0x2
26#define MPP_PMU_SDI 0x3
27#define MPP_PMU_CPU_PWRDWN 0x4
28#define MPP_PMU_STBY_PWRDWN 0x5
29#define MPP_PMU_CORE_PWR_GOOD 0x8
30#define MPP_PMU_BAT_FAULT 0xa
31#define MPP_PMU_EXT0_WU 0xb
32#define MPP_PMU_EXT1_WU 0xc
33#define MPP_PMU_EXT2_WU 0xd
34#define MPP_PMU_BLINK 0xe
35#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)
36
37#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0)
38#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0)
39#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0)
40#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1)
41
42#define MPP0_GPIO0 MPP_PIN(0, 0x0)
43#define MPP0_UA2_RTSn MPP_PIN(0, 0x2)
44#define MPP0_SDIO0_CD MPP_PIN(0, 0x3)
45#define MPP0_LCD0_PWM MPP_PIN(0, 0xf)
46
47#define MPP1_GPIO1 MPP_PIN(1, 0x0)
48#define MPP1_UA2_CTSn MPP_PIN(1, 0x2)
49#define MPP1_SDIO0_WP MPP_PIN(1, 0x3)
50#define MPP1_LCD1_PWM MPP_PIN(1, 0xf)
51
52#define MPP2_GPIO2 MPP_PIN(2, 0x0)
53#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1)
54#define MPP2_UA2_TXD MPP_PIN(2, 0x2)
55#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3)
56#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4)
57
58#define MPP3_GPIO3 MPP_PIN(3, 0x0)
59#define MPP3_SATA_ACT MPP_PIN(3, 0x1)
60#define MPP3_UA2_RXD MPP_PIN(3, 0x2)
61#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3)
62#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4)
63#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf)
64
65#define MPP4_GPIO4 MPP_PIN(4, 0x0)
66#define MPP4_UA3_RTSn MPP_PIN(4, 0x2)
67#define MPP4_SDIO1_CD MPP_PIN(4, 0x3)
68#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4)
69
70#define MPP5_GPIO5 MPP_PIN(5, 0x0)
71#define MPP5_UA3_CTSn MPP_PIN(5, 0x2)
72#define MPP5_SDIO1_WP MPP_PIN(5, 0x3)
73#define MPP5_SPI_1_CS MPP_PIN(5, 0x4)
74
75#define MPP6_GPIO6 MPP_PIN(6, 0x0)
76#define MPP6_UA3_TXD MPP_PIN(6, 0x2)
77#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3)
78#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4)
79
80#define MPP7_GPIO7 MPP_PIN(7, 0x0)
81#define MPP7_UA3_RXD MPP_PIN(7, 0x2)
82#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3)
83#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4)
84
85#define MPP8_GPIO8 MPP_PIN(8, 0x0)
86#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1)
87
88#define MPP9_GPIO9 MPP_PIN(9, 0x0)
89#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5)
90
91#define MPP10_GPIO10 MPP_PIN(10, 0x0)
92#define MPP10_SSP_SCLK MPP_PIN(10, 0x5)
93
94#define MPP11_GPIO11 MPP_PIN(11, 0x0)
95#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1)
96#define MPP11_SATA_ACT MPP_PIN(11, 0x2)
97#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3)
98#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4)
99#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5)
100
101#define MPP12_GPIO12 MPP_PIN(12, 0x0)
102#define MPP12_SATA_ACT MPP_PIN(12, 0x1)
103#define MPP12_UA2_RTSn MPP_PIN(12, 0x2)
104#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3)
105#define MPP12_SDIO1_CD MPP_PIN(12, 0x4)
106
107#define MPP13_GPIO13 MPP_PIN(13, 0x0)
108#define MPP13_UA2_CTSn MPP_PIN(13, 0x2)
109#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3)
110#define MPP13_SDIO1WP MPP_PIN(13, 0x4)
111#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5)
112
113#define MPP14_GPIO14 MPP_PIN(14, 0x0)
114#define MPP14_UA2_TXD MPP_PIN(14, 0x2)
115#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4)
116#define MPP14_SSP_RXD MPP_PIN(14, 0x5)
117
118#define MPP15_GPIO15 MPP_PIN(15, 0x0)
119#define MPP15_UA2_RXD MPP_PIN(15, 0x2)
120#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4)
121#define MPP15_SSP_SFRM MPP_PIN(15, 0x5)
122
123#define MPP16_GPIO16 MPP_PIN(16, 0x0)
124#define MPP16_UA3_RTSn MPP_PIN(16, 0x2)
125#define MPP16_SDIO0_CD MPP_PIN(16, 0x3)
126#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4)
127#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5)
128
129#define MPP17_GPIO17 MPP_PIN(17, 0x0)
130#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1)
131#define MPP17_UA3_CTSn MPP_PIN(17, 0x2)
132#define MPP17_SDIO0_WP MPP_PIN(17, 0x3)
133#define MPP17_TW_SDA2 MPP_PIN(17, 0x4)
134#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5)
135
136#define MPP18_GPIO18 MPP_PIN(18, 0x0)
137#define MPP18_UA3_TXD MPP_PIN(18, 0x2)
138#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3)
139#define MPP18_LCD0_PWM MPP_PIN(18, 0x4)
140#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5)
141
142#define MPP19_GPIO19 MPP_PIN(19, 0x0)
143#define MPP19_UA3_RXD MPP_PIN(19, 0x2)
144#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3)
145#define MPP19_TW_SCK2 MPP_PIN(19, 0x4)
146
147#define MPP20_GPIO20 MPP_PIN(20, 0x0)
148#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1)
149#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2)
150#define MPP20_SDIO1_CD MPP_PIN(20, 0x3)
151#define MPP20_SDIO0_CD MPP_PIN(20, 0x5)
152#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6)
153
154#define MPP21_GPIO21 MPP_PIN(21, 0x0)
155#define MPP21_UA1_RTSn MPP_PIN(21, 0x1)
156#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2)
157#define MPP21_SDIO1_WP MPP_PIN(21, 0x3)
158#define MPP21_SSP_SFRM MPP_PIN(21, 0x4)
159#define MPP21_SDIO0_WP MPP_PIN(21, 0x5)
160#define MPP21_SPI_1_CS MPP_PIN(21, 0x6)
161
162#define MPP22_GPIO22 MPP_PIN(22, 0x0)
163#define MPP22_UA1_CTSn MPP_PIN(22, 0x1)
164#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2)
165#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3)
166#define MPP22_SSP_TXD MPP_PIN(22, 0x4)
167#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5)
168#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6)
169
170#define MPP23_GPIO23 MPP_PIN(23, 0x0)
171#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2)
172#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3)
173#define MPP23_SSP_SCLK MPP_PIN(23, 0x4)
174#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5)
175#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6)
176
177/* for MPP groups _num is a group index */
178enum dove_mpp_grp_idx {
179 MPP_24_39 = 2,
180 MPP_40_45 = 0,
181 MPP_46_51 = 1,
182 MPP_58_61 = 5,
183 MPP_62_63 = 4,
184};
185
186#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
187#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0)
188
189#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
190#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
191
192#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
193#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
194
195#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
196#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0)
197
198#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
199#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
200
201/* The MPP[64:71] control differs from other groups */
202#define MPP64_71_GPO MPP_GRP_NFC(0x1)
203#define MPP64_71_NFC MPP_GRP_NFC(0x0)
204
205/*
206 * The MPP[52:57] functionality is encoded by 4 bits in different
207 * registers. The _num field in this case encodes those bits in
208 * correspodence with Table 135 of 88AP510 Functional specification
209 */
210#define MPP52_57_AU1 MPP_GRP_AU1(0x0)
211#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2)
212#define MPP52_57_GPIO MPP_GRP_AU1(0xa)
213#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb)
214#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc)
215#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe)
216#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf)
217
218void dove_mpp_conf(unsigned int *mpp_list);
219
220#endif /* __ARCH_DOVE_MPP_CODED_H */
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 34106335c728..7fc603b46891 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -45,18 +45,18 @@ config MACH_GURUPLUG
45 Marvell GuruPlug Reference Board. 45 Marvell GuruPlug Reference Board.
46 46
47config MACH_TS219 47config MACH_TS219
48 bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS" 48 bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
49 help 49 help
50 Say 'Y' here if you want your kernel to support the 50 Say 'Y' here if you want your kernel to support the
51 QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS 51 QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
52 devices. 52 TS-219P+ Turbo NAS devices.
53 53
54config MACH_TS41X 54config MACH_TS41X
55 bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS" 55 bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
56 help 56 help
57 Say 'Y' here if you want your kernel to support the 57 Say 'Y' here if you want your kernel to support the
58 QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS 58 QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
59 devices. 59 NAS devices.
60 60
61config MACH_DOCKSTAR 61config MACH_DOCKSTAR
62 bool "Seagate FreeAgent DockStar" 62 bool "Seagate FreeAgent DockStar"
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 6710bd7773b8..dc999c4c5806 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -80,15 +80,19 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
80 MPP11_UART0_RXD, 80 MPP11_UART0_RXD,
81 MPP13_UART1_TXD, /* PIC controller */ 81 MPP13_UART1_TXD, /* PIC controller */
82 MPP14_UART1_RXD, /* PIC controller */ 82 MPP14_UART1_RXD, /* PIC controller */
83 MPP15_GPIO, /* USB Copy button */ 83 MPP15_GPIO, /* USB Copy button (on devices with 88F6281) */
84 MPP16_GPIO, /* Reset button */ 84 MPP16_GPIO, /* Reset button (on devices with 88F6281) */
85 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ 85 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
86 MPP37_GPIO, /* Reset button (on devices with 88F6282) */
87 MPP43_GPIO, /* USB Copy button (on devices with 88F6282) */
86 MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */ 88 MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */
87 0 89 0
88}; 90};
89 91
90static void __init qnap_ts219_init(void) 92static void __init qnap_ts219_init(void)
91{ 93{
94 u32 dev, rev;
95
92 /* 96 /*
93 * Basic setup. Needs to be called early. 97 * Basic setup. Needs to be called early.
94 */ 98 */
@@ -100,6 +104,14 @@ static void __init qnap_ts219_init(void)
100 qnap_tsx1x_register_flash(); 104 qnap_tsx1x_register_flash();
101 kirkwood_i2c_init(); 105 kirkwood_i2c_init();
102 i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1); 106 i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1);
107
108 kirkwood_pcie_id(&dev, &rev);
109 if (dev == MV88F6282_DEV_ID) {
110 qnap_ts219_buttons[0].gpio = 43; /* USB Copy button */
111 qnap_ts219_buttons[1].gpio = 37; /* Reset button */
112 qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
113 }
114
103 kirkwood_ge00_init(&qnap_ts219_ge00_data); 115 kirkwood_ge00_init(&qnap_ts219_ge00_data);
104 kirkwood_sata_init(&qnap_ts219_sata_data); 116 kirkwood_sata_init(&qnap_ts219_sata_data);
105 kirkwood_ehci_init(); 117 kirkwood_ehci_init();
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 3587a281d993..9a44029915e2 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -119,6 +119,8 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
119 119
120static void __init qnap_ts41x_init(void) 120static void __init qnap_ts41x_init(void)
121{ 121{
122 u32 dev, rev;
123
122 /* 124 /*
123 * Basic setup. Needs to be called early. 125 * Basic setup. Needs to be called early.
124 */ 126 */
@@ -130,8 +132,15 @@ static void __init qnap_ts41x_init(void)
130 qnap_tsx1x_register_flash(); 132 qnap_tsx1x_register_flash();
131 kirkwood_i2c_init(); 133 kirkwood_i2c_init();
132 i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1); 134 i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1);
135
136 kirkwood_pcie_id(&dev, &rev);
137 if (dev == MV88F6282_DEV_ID) {
138 qnap_ts41x_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
139 qnap_ts41x_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
140 }
133 kirkwood_ge00_init(&qnap_ts41x_ge00_data); 141 kirkwood_ge00_init(&qnap_ts41x_ge00_data);
134 kirkwood_ge01_init(&qnap_ts41x_ge01_data); 142 kirkwood_ge01_init(&qnap_ts41x_ge01_data);
143
135 kirkwood_sata_init(&qnap_ts41x_sata_data); 144 kirkwood_sata_init(&qnap_ts41x_sata_data);
136 kirkwood_ehci_init(); 145 kirkwood_ehci_init();
137 platform_device_register(&qnap_ts41x_button_device); 146 platform_device_register(&qnap_ts41x_button_device);
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index 788bdace1304..3eff39921d4d 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -65,7 +65,7 @@
65 */ 65 */
66#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) 66#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000)
67#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) 67#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500)
68#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700) 68#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570)
69 69
70#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) 70#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000)
71#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) 71#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index c897e03e413d..6604fc6ca58a 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -51,6 +51,13 @@ config MACH_LINKSTATION_PRO
51 Buffalo Linkstation Pro/Live platform. Both v1 and 51 Buffalo Linkstation Pro/Live platform. Both v1 and
52 v2 devices are supported. 52 v2 devices are supported.
53 53
54config MACH_LINKSTATION_LSCHL
55 bool "Buffalo Linkstation Live v3 (LS-CHL)"
56 select I2C_BOARDINFO
57 help
58 Say 'Y' here if you want your kernel to support the
59 Buffalo Linkstation Live v3 (LS-CHL) platform.
60
54config MACH_LINKSTATION_MINI 61config MACH_LINKSTATION_MINI
55 bool "Buffalo Linkstation Mini" 62 bool "Buffalo Linkstation Mini"
56 select I2C_BOARDINFO 63 select I2C_BOARDINFO
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index eb6eabcb41e4..7f18cdacd487 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o
21obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o 21obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o
22obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o 22obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o
23obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o 23obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o
24obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
new file mode 100644
index 000000000000..20a9b66cbafa
--- /dev/null
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -0,0 +1,327 @@
1/*
2 * arch/arm/mach-orion5x/ls-chl-setup.c
3 *
4 * Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/mtd/physmap.h>
15#include <linux/mv643xx_eth.h>
16#include <linux/leds.h>
17#include <linux/gpio_keys.h>
18#include <linux/gpio-fan.h>
19#include <linux/input.h>
20#include <linux/i2c.h>
21#include <linux/ata_platform.h>
22#include <linux/gpio.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25#include <asm/system.h>
26#include <mach/orion5x.h>
27#include "common.h"
28#include "mpp.h"
29
30/*****************************************************************************
31 * Linkstation LS-CHL Info
32 ****************************************************************************/
33
34/*
35 * 256K NOR flash Device bus boot chip select
36 */
37
38#define LSCHL_NOR_BOOT_BASE 0xf4000000
39#define LSCHL_NOR_BOOT_SIZE SZ_256K
40
41/*****************************************************************************
42 * 256KB NOR Flash on BOOT Device
43 ****************************************************************************/
44
45static struct physmap_flash_data lschl_nor_flash_data = {
46 .width = 1,
47};
48
49static struct resource lschl_nor_flash_resource = {
50 .flags = IORESOURCE_MEM,
51 .start = LSCHL_NOR_BOOT_BASE,
52 .end = LSCHL_NOR_BOOT_BASE + LSCHL_NOR_BOOT_SIZE - 1,
53};
54
55static struct platform_device lschl_nor_flash = {
56 .name = "physmap-flash",
57 .id = 0,
58 .dev = {
59 .platform_data = &lschl_nor_flash_data,
60 },
61 .num_resources = 1,
62 .resource = &lschl_nor_flash_resource,
63};
64
65/*****************************************************************************
66 * Ethernet
67 ****************************************************************************/
68
69static struct mv643xx_eth_platform_data lschl_eth_data = {
70 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
71};
72
73/*****************************************************************************
74 * RTC 5C372a on I2C bus
75 ****************************************************************************/
76
77static struct i2c_board_info __initdata lschl_i2c_rtc = {
78 I2C_BOARD_INFO("rs5c372a", 0x32),
79};
80
81/*****************************************************************************
82 * LEDs attached to GPIO
83 ****************************************************************************/
84
85#define LSCHL_GPIO_LED_ALARM 2
86#define LSCHL_GPIO_LED_INFO 3
87#define LSCHL_GPIO_LED_FUNC 17
88#define LSCHL_GPIO_LED_PWR 0
89
90static struct gpio_led lschl_led_pins[] = {
91 {
92 .name = "alarm:red",
93 .gpio = LSCHL_GPIO_LED_ALARM,
94 .active_low = 1,
95 }, {
96 .name = "info:amber",
97 .gpio = LSCHL_GPIO_LED_INFO,
98 .active_low = 1,
99 }, {
100 .name = "func:blue:top",
101 .gpio = LSCHL_GPIO_LED_FUNC,
102 .active_low = 1,
103 }, {
104 .name = "power:blue:bottom",
105 .gpio = LSCHL_GPIO_LED_PWR,
106 },
107};
108
109static struct gpio_led_platform_data lschl_led_data = {
110 .leds = lschl_led_pins,
111 .num_leds = ARRAY_SIZE(lschl_led_pins),
112};
113
114static struct platform_device lschl_leds = {
115 .name = "leds-gpio",
116 .id = -1,
117 .dev = {
118 .platform_data = &lschl_led_data,
119 },
120};
121
122/*****************************************************************************
123 * SATA
124 ****************************************************************************/
125static struct mv_sata_platform_data lschl_sata_data = {
126 .n_ports = 2,
127};
128
129/*****************************************************************************
130 * LS-CHL specific power off method: reboot
131 ****************************************************************************/
132/*
133 * On the LS-CHL, the shutdown process is following:
134 * - Userland monitors key events until the power switch goes to off position
135 * - The board reboots
136 * - U-boot starts and goes into an idle mode waiting for the user
137 * to move the switch to ON position
138 *
139 */
140
141static void lschl_power_off(void)
142{
143 arm_machine_restart('h', NULL);
144}
145
146/*****************************************************************************
147 * General Setup
148 ****************************************************************************/
149#define LSCHL_GPIO_USB_POWER 9
150#define LSCHL_GPIO_AUTO_POWER 17
151#define LSCHL_GPIO_POWER 18
152
153/****************************************************************************
154 * GPIO Attached Keys
155 ****************************************************************************/
156#define LSCHL_GPIO_KEY_FUNC 15
157#define LSCHL_GPIO_KEY_POWER 8
158#define LSCHL_GPIO_KEY_AUTOPOWER 10
159#define LSCHL_SW_POWER 0x00
160#define LSCHL_SW_AUTOPOWER 0x01
161#define LSCHL_SW_FUNC 0x02
162
163static struct gpio_keys_button lschl_buttons[] = {
164 {
165 .type = EV_SW,
166 .code = LSCHL_SW_POWER,
167 .gpio = LSCHL_GPIO_KEY_POWER,
168 .desc = "Power-on Switch",
169 .active_low = 1,
170 }, {
171 .type = EV_SW,
172 .code = LSCHL_SW_AUTOPOWER,
173 .gpio = LSCHL_GPIO_KEY_AUTOPOWER,
174 .desc = "Power-auto Switch",
175 .active_low = 1,
176 }, {
177 .type = EV_SW,
178 .code = LSCHL_SW_FUNC,
179 .gpio = LSCHL_GPIO_KEY_FUNC,
180 .desc = "Function Switch",
181 .active_low = 1,
182 },
183};
184
185static struct gpio_keys_platform_data lschl_button_data = {
186 .buttons = lschl_buttons,
187 .nbuttons = ARRAY_SIZE(lschl_buttons),
188};
189
190static struct platform_device lschl_button_device = {
191 .name = "gpio-keys",
192 .id = -1,
193 .num_resources = 0,
194 .dev = {
195 .platform_data = &lschl_button_data,
196 },
197};
198
199#define LSCHL_GPIO_HDD_POWER 1
200
201/****************************************************************************
202 * GPIO Fan
203 ****************************************************************************/
204
205#define LSCHL_GPIO_FAN_LOW 16
206#define LSCHL_GPIO_FAN_HIGH 14
207#define LSCHL_GPIO_FAN_LOCK 6
208
209static struct gpio_fan_alarm lschl_alarm = {
210 .gpio = LSCHL_GPIO_FAN_LOCK,
211};
212
213static struct gpio_fan_speed lschl_speeds[] = {
214 {
215 .rpm = 0,
216 .ctrl_val = 3,
217 }, {
218 .rpm = 1500,
219 .ctrl_val = 2,
220 }, {
221 .rpm = 3250,
222 .ctrl_val = 1,
223 }, {
224 .rpm = 5000,
225 .ctrl_val = 0,
226 },
227};
228
229static int lschl_gpio_list[] = {
230 LSCHL_GPIO_FAN_HIGH, LSCHL_GPIO_FAN_LOW,
231};
232
233static struct gpio_fan_platform_data lschl_fan_data = {
234 .num_ctrl = ARRAY_SIZE(lschl_gpio_list),
235 .ctrl = lschl_gpio_list,
236 .alarm = &lschl_alarm,
237 .num_speed = ARRAY_SIZE(lschl_speeds),
238 .speed = lschl_speeds,
239};
240
241static struct platform_device lschl_fan_device = {
242 .name = "gpio-fan",
243 .id = -1,
244 .num_resources = 0,
245 .dev = {
246 .platform_data = &lschl_fan_data,
247 },
248};
249
250/****************************************************************************
251 * GPIO Data
252 ****************************************************************************/
253
254static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = {
255 { 0, MPP_GPIO }, /* LED POWER */
256 { 1, MPP_GPIO }, /* HDD POWER */
257 { 2, MPP_GPIO }, /* LED ALARM */
258 { 3, MPP_GPIO }, /* LED INFO */
259 { 4, MPP_UNUSED },
260 { 5, MPP_UNUSED },
261 { 6, MPP_GPIO }, /* FAN LOCK */
262 { 7, MPP_GPIO }, /* SW INIT */
263 { 8, MPP_GPIO }, /* SW POWER */
264 { 9, MPP_GPIO }, /* USB POWER */
265 { 10, MPP_GPIO }, /* SW AUTO POWER */
266 { 11, MPP_UNUSED },
267 { 12, MPP_UNUSED },
268 { 13, MPP_UNUSED },
269 { 14, MPP_GPIO }, /* FAN HIGH */
270 { 15, MPP_GPIO }, /* SW FUNC */
271 { 16, MPP_GPIO }, /* FAN LOW */
272 { 17, MPP_GPIO }, /* LED FUNC */
273 { 18, MPP_UNUSED },
274 { 19, MPP_UNUSED },
275 { -1 },
276};
277
278static void __init lschl_init(void)
279{
280 /*
281 * Setup basic Orion functions. Needs to be called early.
282 */
283 orion5x_init();
284
285 orion5x_mpp_conf(lschl_mpp_modes);
286
287 /*
288 * Configure peripherals.
289 */
290 orion5x_ehci0_init();
291 orion5x_ehci1_init();
292 orion5x_eth_init(&lschl_eth_data);
293 orion5x_i2c_init();
294 orion5x_sata_init(&lschl_sata_data);
295 orion5x_uart0_init();
296 orion5x_xor_init();
297
298 orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE,
299 LSCHL_NOR_BOOT_SIZE);
300 platform_device_register(&lschl_nor_flash);
301
302 platform_device_register(&lschl_leds);
303
304 platform_device_register(&lschl_button_device);
305
306 platform_device_register(&lschl_fan_device);
307
308 i2c_register_board_info(0, &lschl_i2c_rtc, 1);
309
310 /* usb power on */
311 gpio_set_value(LSCHL_GPIO_USB_POWER, 1);
312
313 /* register power-off method */
314 pm_power_off = lschl_power_off;
315
316 pr_info("%s: finished\n", __func__);
317}
318
319MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
320 /* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> */
321 .boot_params = 0x00000100,
322 .init_machine = lschl_init,
323 .map_io = orion5x_map_io,
324 .init_irq = orion5x_init_irq,
325 .timer = &orion5x_timer,
326 .fixup = tag_fixup_mem32,
327MACHINE_END
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