aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c78
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c18
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c5
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h104
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c253
-rw-r--r--drivers/gpu/drm/i915/i915_gem_debug.c45
-rw-r--r--drivers/gpu/drm/i915/i915_gem_evict.c5
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c60
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c5
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c239
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h478
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c429
-rw-r--r--drivers/gpu/drm/i915/i915_trace.h301
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c54
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h4
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c33
-rw-r--r--drivers/gpu/drm/i915/intel_display.c1906
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c130
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h8
-rw-r--r--drivers/gpu/drm/i915/intel_dvo.c2
-rw-r--r--drivers/gpu/drm/i915/intel_i2c.c3
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c11
-rw-r--r--drivers/gpu/drm/i915/intel_opregion.c2
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c15
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c14
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c30
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h29
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c39
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c10
29 files changed, 2577 insertions, 1733 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3601466c5502..d659f36419af 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -326,21 +326,21 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
326 struct intel_crtc *crtc; 326 struct intel_crtc *crtc;
327 327
328 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 328 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
329 const char *pipe = crtc->pipe ? "B" : "A"; 329 const char pipe = pipe_name(crtc->pipe);
330 const char *plane = crtc->plane ? "B" : "A"; 330 const char plane = plane_name(crtc->plane);
331 struct intel_unpin_work *work; 331 struct intel_unpin_work *work;
332 332
333 spin_lock_irqsave(&dev->event_lock, flags); 333 spin_lock_irqsave(&dev->event_lock, flags);
334 work = crtc->unpin_work; 334 work = crtc->unpin_work;
335 if (work == NULL) { 335 if (work == NULL) {
336 seq_printf(m, "No flip due on pipe %s (plane %s)\n", 336 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
337 pipe, plane); 337 pipe, plane);
338 } else { 338 } else {
339 if (!work->pending) { 339 if (!work->pending) {
340 seq_printf(m, "Flip queued on pipe %s (plane %s)\n", 340 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
341 pipe, plane); 341 pipe, plane);
342 } else { 342 } else {
343 seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n", 343 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
344 pipe, plane); 344 pipe, plane);
345 } 345 }
346 if (work->enable_stall_check) 346 if (work->enable_stall_check)
@@ -458,7 +458,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
458 struct drm_info_node *node = (struct drm_info_node *) m->private; 458 struct drm_info_node *node = (struct drm_info_node *) m->private;
459 struct drm_device *dev = node->minor->dev; 459 struct drm_device *dev = node->minor->dev;
460 drm_i915_private_t *dev_priv = dev->dev_private; 460 drm_i915_private_t *dev_priv = dev->dev_private;
461 int ret, i; 461 int ret, i, pipe;
462 462
463 ret = mutex_lock_interruptible(&dev->struct_mutex); 463 ret = mutex_lock_interruptible(&dev->struct_mutex);
464 if (ret) 464 if (ret)
@@ -471,10 +471,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
471 I915_READ(IIR)); 471 I915_READ(IIR));
472 seq_printf(m, "Interrupt mask: %08x\n", 472 seq_printf(m, "Interrupt mask: %08x\n",
473 I915_READ(IMR)); 473 I915_READ(IMR));
474 seq_printf(m, "Pipe A stat: %08x\n", 474 for_each_pipe(pipe)
475 I915_READ(PIPEASTAT)); 475 seq_printf(m, "Pipe %c stat: %08x\n",
476 seq_printf(m, "Pipe B stat: %08x\n", 476 pipe_name(pipe),
477 I915_READ(PIPEBSTAT)); 477 I915_READ(PIPESTAT(pipe)));
478 } else { 478 } else {
479 seq_printf(m, "North Display Interrupt enable: %08x\n", 479 seq_printf(m, "North Display Interrupt enable: %08x\n",
480 I915_READ(DEIER)); 480 I915_READ(DEIER));
@@ -544,11 +544,11 @@ static int i915_hws_info(struct seq_file *m, void *data)
544 struct drm_device *dev = node->minor->dev; 544 struct drm_device *dev = node->minor->dev;
545 drm_i915_private_t *dev_priv = dev->dev_private; 545 drm_i915_private_t *dev_priv = dev->dev_private;
546 struct intel_ring_buffer *ring; 546 struct intel_ring_buffer *ring;
547 volatile u32 *hws; 547 const volatile u32 __iomem *hws;
548 int i; 548 int i;
549 549
550 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; 550 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
551 hws = (volatile u32 *)ring->status_page.page_addr; 551 hws = (volatile u32 __iomem *)ring->status_page.page_addr;
552 if (hws == NULL) 552 if (hws == NULL)
553 return 0; 553 return 0;
554 554
@@ -615,7 +615,7 @@ static int i915_ringbuffer_data(struct seq_file *m, void *data)
615 if (!ring->obj) { 615 if (!ring->obj) {
616 seq_printf(m, "No ringbuffer setup\n"); 616 seq_printf(m, "No ringbuffer setup\n");
617 } else { 617 } else {
618 u8 *virt = ring->virtual_start; 618 const u8 __iomem *virt = ring->virtual_start;
619 uint32_t off; 619 uint32_t off;
620 620
621 for (off = 0; off < ring->size; off += 4) { 621 for (off = 0; off < ring->size; off += 4) {
@@ -805,15 +805,20 @@ static int i915_error_state(struct seq_file *m, void *unused)
805 } 805 }
806 } 806 }
807 807
808 if (error->ringbuffer) { 808 for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) {
809 struct drm_i915_error_object *obj = error->ringbuffer; 809 if (error->ringbuffer[i]) {
810 810 struct drm_i915_error_object *obj = error->ringbuffer[i];
811 seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset); 811 seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
812 offset = 0; 812 dev_priv->ring[i].name,
813 for (page = 0; page < obj->page_count; page++) { 813 obj->gtt_offset);
814 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 814 offset = 0;
815 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); 815 for (page = 0; page < obj->page_count; page++) {
816 offset += 4; 816 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
817 seq_printf(m, "%08x : %08x\n",
818 offset,
819 obj->pages[page][elt]);
820 offset += 4;
821 }
817 } 822 }
818 } 823 }
819 } 824 }
@@ -862,19 +867,44 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
862 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 867 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
863 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); 868 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
864 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 869 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
870 u32 rpstat;
871 u32 rpupei, rpcurup, rpprevup;
872 u32 rpdownei, rpcurdown, rpprevdown;
865 int max_freq; 873 int max_freq;
866 874
867 /* RPSTAT1 is in the GT power well */ 875 /* RPSTAT1 is in the GT power well */
868 __gen6_force_wake_get(dev_priv); 876 __gen6_force_wake_get(dev_priv);
869 877
878 rpstat = I915_READ(GEN6_RPSTAT1);
879 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
880 rpcurup = I915_READ(GEN6_RP_CUR_UP);
881 rpprevup = I915_READ(GEN6_RP_PREV_UP);
882 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
883 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
884 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
885
870 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 886 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
871 seq_printf(m, "RPSTAT1: 0x%08x\n", I915_READ(GEN6_RPSTAT1)); 887 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
872 seq_printf(m, "Render p-state ratio: %d\n", 888 seq_printf(m, "Render p-state ratio: %d\n",
873 (gt_perf_status & 0xff00) >> 8); 889 (gt_perf_status & 0xff00) >> 8);
874 seq_printf(m, "Render p-state VID: %d\n", 890 seq_printf(m, "Render p-state VID: %d\n",
875 gt_perf_status & 0xff); 891 gt_perf_status & 0xff);
876 seq_printf(m, "Render p-state limit: %d\n", 892 seq_printf(m, "Render p-state limit: %d\n",
877 rp_state_limits & 0xff); 893 rp_state_limits & 0xff);
894 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
895 GEN6_CAGF_SHIFT) * 100);
896 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
897 GEN6_CURICONT_MASK);
898 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
899 GEN6_CURBSYTAVG_MASK);
900 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
901 GEN6_CURBSYTAVG_MASK);
902 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
903 GEN6_CURIAVG_MASK);
904 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
905 GEN6_CURBSYTAVG_MASK);
906 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
907 GEN6_CURBSYTAVG_MASK);
878 908
879 max_freq = (rp_state_cap & 0xff0000) >> 16; 909 max_freq = (rp_state_cap & 0xff0000) >> 16;
880 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", 910 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
@@ -1259,7 +1289,7 @@ static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
1259} 1289}
1260 1290
1261static struct drm_info_list i915_debugfs_list[] = { 1291static struct drm_info_list i915_debugfs_list[] = {
1262 {"i915_capabilities", i915_capabilities, 0, 0}, 1292 {"i915_capabilities", i915_capabilities, 0},
1263 {"i915_gem_objects", i915_gem_object_info, 0}, 1293 {"i915_gem_objects", i915_gem_object_info, 0},
1264 {"i915_gem_gtt", i915_gem_gtt_info, 0}, 1294 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1265 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, 1295 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 17bd766f2081..ffa2196eb3b9 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -60,10 +60,11 @@ static int i915_init_phys_hws(struct drm_device *dev)
60 DRM_ERROR("Can not allocate hardware status page\n"); 60 DRM_ERROR("Can not allocate hardware status page\n");
61 return -ENOMEM; 61 return -ENOMEM;
62 } 62 }
63 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; 63 ring->status_page.page_addr =
64 (void __force __iomem *)dev_priv->status_page_dmah->vaddr;
64 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; 65 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
65 66
66 memset(ring->status_page.page_addr, 0, PAGE_SIZE); 67 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
67 68
68 if (INTEL_INFO(dev)->gen >= 4) 69 if (INTEL_INFO(dev)->gen >= 4)
69 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) & 70 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
@@ -859,8 +860,9 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
859 " G33 hw status page\n"); 860 " G33 hw status page\n");
860 return -ENOMEM; 861 return -ENOMEM;
861 } 862 }
862 ring->status_page.page_addr = dev_priv->hws_map.handle; 863 ring->status_page.page_addr =
863 memset(ring->status_page.page_addr, 0, PAGE_SIZE); 864 (void __force __iomem *)dev_priv->hws_map.handle;
865 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
864 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); 866 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
865 867
866 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", 868 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
@@ -2002,9 +2004,13 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2002 2004
2003 spin_lock_init(&dev_priv->irq_lock); 2005 spin_lock_init(&dev_priv->irq_lock);
2004 spin_lock_init(&dev_priv->error_lock); 2006 spin_lock_init(&dev_priv->error_lock);
2005 dev_priv->trace_irq_seqno = 0;
2006 2007
2007 ret = drm_vblank_init(dev, I915_NUM_PIPE); 2008 if (IS_MOBILE(dev) || !IS_GEN2(dev))
2009 dev_priv->num_pipe = 2;
2010 else
2011 dev_priv->num_pipe = 1;
2012
2013 ret = drm_vblank_init(dev, dev_priv->num_pipe);
2008 if (ret) 2014 if (ret)
2009 goto out_gem_unload; 2015 goto out_gem_unload;
2010 2016
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0ad533f06af9..64fb21e4bd2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -55,7 +55,10 @@ module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
55unsigned int i915_panel_use_ssc = 1; 55unsigned int i915_panel_use_ssc = 1;
56module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); 56module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
57 57
58bool i915_try_reset = true; 58int i915_vbt_sdvo_panel_type = -1;
59module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
60
61static bool i915_try_reset = true;
59module_param_named(reset, i915_try_reset, bool, 0600); 62module_param_named(reset, i915_try_reset, bool, 0600);
60 63
61static struct drm_driver driver; 64static struct drm_driver driver;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 65dfe81d0035..92f4d33216cd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -35,6 +35,7 @@
35#include "intel_ringbuffer.h" 35#include "intel_ringbuffer.h"
36#include <linux/io-mapping.h> 36#include <linux/io-mapping.h>
37#include <linux/i2c.h> 37#include <linux/i2c.h>
38#include <linux/pm_qos_params.h>
38#include <drm/intel-gtt.h> 39#include <drm/intel-gtt.h>
39 40
40/* General customization: 41/* General customization:
@@ -49,17 +50,22 @@
49enum pipe { 50enum pipe {
50 PIPE_A = 0, 51 PIPE_A = 0,
51 PIPE_B, 52 PIPE_B,
53 PIPE_C,
54 I915_MAX_PIPES
52}; 55};
56#define pipe_name(p) ((p) + 'A')
53 57
54enum plane { 58enum plane {
55 PLANE_A = 0, 59 PLANE_A = 0,
56 PLANE_B, 60 PLANE_B,
61 PLANE_C,
57}; 62};
58 63#define plane_name(p) ((p) + 'A')
59#define I915_NUM_PIPE 2
60 64
61#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 65#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
62 66
67#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
68
63/* Interface history: 69/* Interface history:
64 * 70 *
65 * 1.1: Original. 71 * 1.1: Original.
@@ -75,10 +81,7 @@ enum plane {
75#define DRIVER_PATCHLEVEL 0 81#define DRIVER_PATCHLEVEL 0
76 82
77#define WATCH_COHERENCY 0 83#define WATCH_COHERENCY 0
78#define WATCH_EXEC 0
79#define WATCH_RELOC 0
80#define WATCH_LISTS 0 84#define WATCH_LISTS 0
81#define WATCH_PWRITE 0
82 85
83#define I915_GEM_PHYS_CURSOR_0 1 86#define I915_GEM_PHYS_CURSOR_0 1
84#define I915_GEM_PHYS_CURSOR_1 2 87#define I915_GEM_PHYS_CURSOR_1 2
@@ -111,6 +114,7 @@ struct intel_opregion {
111 struct opregion_swsci *swsci; 114 struct opregion_swsci *swsci;
112 struct opregion_asle *asle; 115 struct opregion_asle *asle;
113 void *vbt; 116 void *vbt;
117 u32 __iomem *lid_state;
114}; 118};
115#define OPREGION_SIZE (8*1024) 119#define OPREGION_SIZE (8*1024)
116 120
@@ -144,8 +148,7 @@ struct intel_display_error_state;
144struct drm_i915_error_state { 148struct drm_i915_error_state {
145 u32 eir; 149 u32 eir;
146 u32 pgtbl_er; 150 u32 pgtbl_er;
147 u32 pipeastat; 151 u32 pipestat[I915_MAX_PIPES];
148 u32 pipebstat;
149 u32 ipeir; 152 u32 ipeir;
150 u32 ipehr; 153 u32 ipehr;
151 u32 instdone; 154 u32 instdone;
@@ -172,7 +175,7 @@ struct drm_i915_error_state {
172 int page_count; 175 int page_count;
173 u32 gtt_offset; 176 u32 gtt_offset;
174 u32 *pages[0]; 177 u32 *pages[0];
175 } *ringbuffer, *batchbuffer[I915_NUM_RINGS]; 178 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
176 struct drm_i915_error_buffer { 179 struct drm_i915_error_buffer {
177 u32 size; 180 u32 size;
178 u32 name; 181 u32 name;
@@ -200,9 +203,7 @@ struct drm_i915_display_funcs {
200 void (*disable_fbc)(struct drm_device *dev); 203 void (*disable_fbc)(struct drm_device *dev);
201 int (*get_display_clock_speed)(struct drm_device *dev); 204 int (*get_display_clock_speed)(struct drm_device *dev);
202 int (*get_fifo_size)(struct drm_device *dev, int plane); 205 int (*get_fifo_size)(struct drm_device *dev, int plane);
203 void (*update_wm)(struct drm_device *dev, int planea_clock, 206 void (*update_wm)(struct drm_device *dev);
204 int planeb_clock, int sr_hdisplay, int sr_htotal,
205 int pixel_size);
206 /* clock updates for mode set */ 207 /* clock updates for mode set */
207 /* cursor updates */ 208 /* cursor updates */
208 /* render clock increase/decrease */ 209 /* render clock increase/decrease */
@@ -289,7 +290,6 @@ typedef struct drm_i915_private {
289 int page_flipping; 290 int page_flipping;
290 291
291 atomic_t irq_received; 292 atomic_t irq_received;
292 u32 trace_irq_seqno;
293 293
294 /* protects the irq masks */ 294 /* protects the irq masks */
295 spinlock_t irq_lock; 295 spinlock_t irq_lock;
@@ -309,6 +309,10 @@ typedef struct drm_i915_private {
309 int vblank_pipe; 309 int vblank_pipe;
310 int num_pipe; 310 int num_pipe;
311 311
312 atomic_t vblank_enabled;
313 struct pm_qos_request_list vblank_pm_qos;
314 struct work_struct vblank_work;
315
312 /* For hangcheck timer */ 316 /* For hangcheck timer */
313#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 317#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
314 struct timer_list hangcheck_timer; 318 struct timer_list hangcheck_timer;
@@ -324,8 +328,6 @@ typedef struct drm_i915_private {
324 int cfb_plane; 328 int cfb_plane;
325 int cfb_y; 329 int cfb_y;
326 330
327 int irq_enabled;
328
329 struct intel_opregion opregion; 331 struct intel_opregion opregion;
330 332
331 /* overlay */ 333 /* overlay */
@@ -344,6 +346,7 @@ typedef struct drm_i915_private {
344 unsigned int lvds_vbt:1; 346 unsigned int lvds_vbt:1;
345 unsigned int int_crt_support:1; 347 unsigned int int_crt_support:1;
346 unsigned int lvds_use_ssc:1; 348 unsigned int lvds_use_ssc:1;
349 unsigned int display_clock_mode:1;
347 int lvds_ssc_freq; 350 int lvds_ssc_freq;
348 struct { 351 struct {
349 int rate; 352 int rate;
@@ -652,6 +655,7 @@ typedef struct drm_i915_private {
652 unsigned int lvds_border_bits; 655 unsigned int lvds_border_bits;
653 /* Panel fitter placement and size for Ironlake+ */ 656 /* Panel fitter placement and size for Ironlake+ */
654 u32 pch_pf_pos, pch_pf_size; 657 u32 pch_pf_pos, pch_pf_size;
658 int panel_t3, panel_t12;
655 659
656 struct drm_crtc *plane_to_crtc_mapping[2]; 660 struct drm_crtc *plane_to_crtc_mapping[2];
657 struct drm_crtc *pipe_to_crtc_mapping[2]; 661 struct drm_crtc *pipe_to_crtc_mapping[2];
@@ -958,6 +962,7 @@ extern unsigned int i915_fbpercrtc;
958extern unsigned int i915_powersave; 962extern unsigned int i915_powersave;
959extern unsigned int i915_lvds_downclock; 963extern unsigned int i915_lvds_downclock;
960extern unsigned int i915_panel_use_ssc; 964extern unsigned int i915_panel_use_ssc;
965extern int i915_vbt_sdvo_panel_type;
961extern unsigned int i915_enable_rc6; 966extern unsigned int i915_enable_rc6;
962 967
963extern int i915_suspend(struct drm_device *dev, pm_message_t state); 968extern int i915_suspend(struct drm_device *dev, pm_message_t state);
@@ -997,8 +1002,6 @@ extern int i915_irq_emit(struct drm_device *dev, void *data,
997 struct drm_file *file_priv); 1002 struct drm_file *file_priv);
998extern int i915_irq_wait(struct drm_device *dev, void *data, 1003extern int i915_irq_wait(struct drm_device *dev, void *data,
999 struct drm_file *file_priv); 1004 struct drm_file *file_priv);
1000void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
1001extern void i915_enable_interrupt (struct drm_device *dev);
1002 1005
1003extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 1006extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
1004extern void i915_driver_irq_preinstall(struct drm_device * dev); 1007extern void i915_driver_irq_preinstall(struct drm_device * dev);
@@ -1050,7 +1053,6 @@ extern void i915_mem_takedown(struct mem_block **heap);
1050extern void i915_mem_release(struct drm_device * dev, 1053extern void i915_mem_release(struct drm_device * dev,
1051 struct drm_file *file_priv, struct mem_block *heap); 1054 struct drm_file *file_priv, struct mem_block *heap);
1052/* i915_gem.c */ 1055/* i915_gem.c */
1053int i915_gem_check_is_wedged(struct drm_device *dev);
1054int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1056int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1055 struct drm_file *file_priv); 1057 struct drm_file *file_priv);
1056int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1058int i915_gem_create_ioctl(struct drm_device *dev, void *data,
@@ -1093,8 +1095,7 @@ int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1093 struct drm_file *file_priv); 1095 struct drm_file *file_priv);
1094void i915_gem_load(struct drm_device *dev); 1096void i915_gem_load(struct drm_device *dev);
1095int i915_gem_init_object(struct drm_gem_object *obj); 1097int i915_gem_init_object(struct drm_gem_object *obj);
1096int __must_check i915_gem_flush_ring(struct drm_device *dev, 1098int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1097 struct intel_ring_buffer *ring,
1098 uint32_t invalidate_domains, 1099 uint32_t invalidate_domains,
1099 uint32_t flush_domains); 1100 uint32_t flush_domains);
1100struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1101struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
@@ -1125,10 +1126,9 @@ i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1125} 1126}
1126 1127
1127static inline u32 1128static inline u32
1128i915_gem_next_request_seqno(struct drm_device *dev, 1129i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1129 struct intel_ring_buffer *ring)
1130{ 1130{
1131 drm_i915_private_t *dev_priv = dev->dev_private; 1131 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1132 return ring->outstanding_lazy_request = dev_priv->next_seqno; 1132 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1133} 1133}
1134 1134
@@ -1153,14 +1153,12 @@ void i915_gem_do_init(struct drm_device *dev,
1153 unsigned long end); 1153 unsigned long end);
1154int __must_check i915_gpu_idle(struct drm_device *dev); 1154int __must_check i915_gpu_idle(struct drm_device *dev);
1155int __must_check i915_gem_idle(struct drm_device *dev); 1155int __must_check i915_gem_idle(struct drm_device *dev);
1156int __must_check i915_add_request(struct drm_device *dev, 1156int __must_check i915_add_request(struct intel_ring_buffer *ring,
1157 struct drm_file *file_priv, 1157 struct drm_file *file,
1158 struct drm_i915_gem_request *request, 1158 struct drm_i915_gem_request *request);
1159 struct intel_ring_buffer *ring); 1159int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1160int __must_check i915_do_wait_request(struct drm_device *dev, 1160 uint32_t seqno,
1161 uint32_t seqno, 1161 bool interruptible);
1162 bool interruptible,
1163 struct intel_ring_buffer *ring);
1164int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1162int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1165int __must_check 1163int __must_check
1166i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1164i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
@@ -1309,7 +1307,7 @@ extern void intel_display_print_error_state(struct seq_file *m,
1309#define __i915_read(x, y) \ 1307#define __i915_read(x, y) \
1310static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 1308static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1311 u##x val = read##y(dev_priv->regs + reg); \ 1309 u##x val = read##y(dev_priv->regs + reg); \
1312 trace_i915_reg_rw('R', reg, val, sizeof(val)); \ 1310 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1313 return val; \ 1311 return val; \
1314} 1312}
1315__i915_read(8, b) 1313__i915_read(8, b)
@@ -1320,7 +1318,7 @@ __i915_read(64, q)
1320 1318
1321#define __i915_write(x, y) \ 1319#define __i915_write(x, y) \
1322static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ 1320static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1323 trace_i915_reg_rw('W', reg, val, sizeof(val)); \ 1321 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1324 write##y(val, dev_priv->regs + reg); \ 1322 write##y(val, dev_priv->regs + reg); \
1325} 1323}
1326__i915_write(8, b) 1324__i915_write(8, b)
@@ -1369,46 +1367,4 @@ static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
1369 return val; 1367 return val;
1370} 1368}
1371 1369
1372static inline void
1373i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
1374{
1375 /* Trace down the write operation before the real write */
1376 trace_i915_reg_rw('W', reg, val, len);
1377 switch (len) {
1378 case 8:
1379 writeq(val, dev_priv->regs + reg);
1380 break;
1381 case 4:
1382 writel(val, dev_priv->regs + reg);
1383 break;
1384 case 2:
1385 writew(val, dev_priv->regs + reg);
1386 break;
1387 case 1:
1388 writeb(val, dev_priv->regs + reg);
1389 break;
1390 }
1391}
1392
1393/**
1394 * Reads a dword out of the status page, which is written to from the command
1395 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1396 * MI_STORE_DATA_IMM.
1397 *
1398 * The following dwords have a reserved meaning:
1399 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1400 * 0x04: ring 0 head pointer
1401 * 0x05: ring 1 head pointer (915-class)
1402 * 0x06: ring 2 head pointer (915-class)
1403 * 0x10-0x1b: Context status DWords (GM45)
1404 * 0x1f: Last written status offset. (GM45)
1405 *
1406 * The area from dword 0x20 to 0x3ff is available for driver usage.
1407 */
1408#define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1409 (LP_RING(dev_priv)->status_page.page_addr))[reg])
1410#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1411#define I915_GEM_HWS_INDEX 0x20
1412#define I915_BREADCRUMB_INDEX 0x21
1413
1414#endif 1370#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index cf4f74c7c6fb..a8768e2bbebc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -75,8 +75,8 @@ static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
75 dev_priv->mm.object_memory -= size; 75 dev_priv->mm.object_memory -= size;
76} 76}
77 77
78int 78static int
79i915_gem_check_is_wedged(struct drm_device *dev) 79i915_gem_wait_for_error(struct drm_device *dev)
80{ 80{
81 struct drm_i915_private *dev_priv = dev->dev_private; 81 struct drm_i915_private *dev_priv = dev->dev_private;
82 struct completion *x = &dev_priv->error_completion; 82 struct completion *x = &dev_priv->error_completion;
@@ -90,27 +90,24 @@ i915_gem_check_is_wedged(struct drm_device *dev)
90 if (ret) 90 if (ret)
91 return ret; 91 return ret;
92 92
93 /* Success, we reset the GPU! */ 93 if (atomic_read(&dev_priv->mm.wedged)) {
94 if (!atomic_read(&dev_priv->mm.wedged)) 94 /* GPU is hung, bump the completion count to account for
95 return 0; 95 * the token we just consumed so that we never hit zero and
96 96 * end up waiting upon a subsequent completion event that
97 /* GPU is hung, bump the completion count to account for 97 * will never happen.
98 * the token we just consumed so that we never hit zero and 98 */
99 * end up waiting upon a subsequent completion event that 99 spin_lock_irqsave(&x->wait.lock, flags);
100 * will never happen. 100 x->done++;
101 */ 101 spin_unlock_irqrestore(&x->wait.lock, flags);
102 spin_lock_irqsave(&x->wait.lock, flags); 102 }
103 x->done++; 103 return 0;
104 spin_unlock_irqrestore(&x->wait.lock, flags);
105 return -EIO;
106} 104}
107 105
108int i915_mutex_lock_interruptible(struct drm_device *dev) 106int i915_mutex_lock_interruptible(struct drm_device *dev)
109{ 107{
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 int ret; 108 int ret;
112 109
113 ret = i915_gem_check_is_wedged(dev); 110 ret = i915_gem_wait_for_error(dev);
114 if (ret) 111 if (ret)
115 return ret; 112 return ret;
116 113
@@ -118,11 +115,6 @@ int i915_mutex_lock_interruptible(struct drm_device *dev)
118 if (ret) 115 if (ret)
119 return ret; 116 return ret;
120 117
121 if (atomic_read(&dev_priv->mm.wedged)) {
122 mutex_unlock(&dev->struct_mutex);
123 return -EAGAIN;
124 }
125
126 WARN_ON(i915_verify_lists(dev)); 118 WARN_ON(i915_verify_lists(dev));
127 return 0; 119 return 0;
128} 120}
@@ -526,6 +518,8 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
526 goto out; 518 goto out;
527 } 519 }
528 520
521 trace_i915_gem_object_pread(obj, args->offset, args->size);
522
529 ret = i915_gem_object_set_cpu_read_domain_range(obj, 523 ret = i915_gem_object_set_cpu_read_domain_range(obj,
530 args->offset, 524 args->offset,
531 args->size); 525 args->size);
@@ -967,6 +961,8 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
967 goto out; 961 goto out;
968 } 962 }
969 963
964 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
965
970 /* We can only do the GTT pwrite on untiled buffers, as otherwise 966 /* We can only do the GTT pwrite on untiled buffers, as otherwise
971 * it would end up going through the fenced access, and we'll get 967 * it would end up going through the fenced access, and we'll get
972 * different detiling behavior between reading and writing. 968 * different detiling behavior between reading and writing.
@@ -1121,7 +1117,6 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1121 struct drm_i915_private *dev_priv = dev->dev_private; 1117 struct drm_i915_private *dev_priv = dev->dev_private;
1122 struct drm_i915_gem_mmap *args = data; 1118 struct drm_i915_gem_mmap *args = data;
1123 struct drm_gem_object *obj; 1119 struct drm_gem_object *obj;
1124 loff_t offset;
1125 unsigned long addr; 1120 unsigned long addr;
1126 1121
1127 if (!(dev->driver->driver_features & DRIVER_GEM)) 1122 if (!(dev->driver->driver_features & DRIVER_GEM))
@@ -1136,8 +1131,6 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 return -E2BIG; 1131 return -E2BIG;
1137 } 1132 }
1138 1133
1139 offset = args->offset;
1140
1141 down_write(&current->mm->mmap_sem); 1134 down_write(&current->mm->mmap_sem);
1142 addr = do_mmap(obj->filp, 0, args->size, 1135 addr = do_mmap(obj->filp, 0, args->size,
1143 PROT_READ | PROT_WRITE, MAP_SHARED, 1136 PROT_READ | PROT_WRITE, MAP_SHARED,
@@ -1182,9 +1175,13 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1182 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> 1175 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1183 PAGE_SHIFT; 1176 PAGE_SHIFT;
1184 1177
1185 /* Now bind it into the GTT if needed */ 1178 ret = i915_mutex_lock_interruptible(dev);
1186 mutex_lock(&dev->struct_mutex); 1179 if (ret)
1180 goto out;
1181
1182 trace_i915_gem_object_fault(obj, page_offset, true, write);
1187 1183
1184 /* Now bind it into the GTT if needed */
1188 if (!obj->map_and_fenceable) { 1185 if (!obj->map_and_fenceable) {
1189 ret = i915_gem_object_unbind(obj); 1186 ret = i915_gem_object_unbind(obj);
1190 if (ret) 1187 if (ret)
@@ -1219,12 +1216,21 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1219 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); 1216 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1220unlock: 1217unlock:
1221 mutex_unlock(&dev->struct_mutex); 1218 mutex_unlock(&dev->struct_mutex);
1222 1219out:
1223 switch (ret) { 1220 switch (ret) {
1221 case -EIO:
1224 case -EAGAIN: 1222 case -EAGAIN:
1223 /* Give the error handler a chance to run and move the
1224 * objects off the GPU active list. Next time we service the
1225 * fault, we should be able to transition the page into the
1226 * GTT without touching the GPU (and so avoid further
1227 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1228 * with coherency, just lost writes.
1229 */
1225 set_need_resched(); 1230 set_need_resched();
1226 case 0: 1231 case 0:
1227 case -ERESTARTSYS: 1232 case -ERESTARTSYS:
1233 case -EINTR:
1228 return VM_FAULT_NOPAGE; 1234 return VM_FAULT_NOPAGE;
1229 case -ENOMEM: 1235 case -ENOMEM:
1230 return VM_FAULT_OOM; 1236 return VM_FAULT_OOM;
@@ -1669,9 +1675,8 @@ i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1669} 1675}
1670 1676
1671static void 1677static void
1672i915_gem_process_flushing_list(struct drm_device *dev, 1678i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1673 uint32_t flush_domains, 1679 uint32_t flush_domains)
1674 struct intel_ring_buffer *ring)
1675{ 1680{
1676 struct drm_i915_gem_object *obj, *next; 1681 struct drm_i915_gem_object *obj, *next;
1677 1682
@@ -1684,7 +1689,7 @@ i915_gem_process_flushing_list(struct drm_device *dev,
1684 obj->base.write_domain = 0; 1689 obj->base.write_domain = 0;
1685 list_del_init(&obj->gpu_write_list); 1690 list_del_init(&obj->gpu_write_list);
1686 i915_gem_object_move_to_active(obj, ring, 1691 i915_gem_object_move_to_active(obj, ring,
1687 i915_gem_next_request_seqno(dev, ring)); 1692 i915_gem_next_request_seqno(ring));
1688 1693
1689 trace_i915_gem_object_change_domain(obj, 1694 trace_i915_gem_object_change_domain(obj,
1690 obj->base.read_domains, 1695 obj->base.read_domains,
@@ -1694,27 +1699,22 @@ i915_gem_process_flushing_list(struct drm_device *dev,
1694} 1699}
1695 1700
1696int 1701int
1697i915_add_request(struct drm_device *dev, 1702i915_add_request(struct intel_ring_buffer *ring,
1698 struct drm_file *file, 1703 struct drm_file *file,
1699 struct drm_i915_gem_request *request, 1704 struct drm_i915_gem_request *request)
1700 struct intel_ring_buffer *ring)
1701{ 1705{
1702 drm_i915_private_t *dev_priv = dev->dev_private; 1706 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1703 struct drm_i915_file_private *file_priv = NULL;
1704 uint32_t seqno; 1707 uint32_t seqno;
1705 int was_empty; 1708 int was_empty;
1706 int ret; 1709 int ret;
1707 1710
1708 BUG_ON(request == NULL); 1711 BUG_ON(request == NULL);
1709 1712
1710 if (file != NULL)
1711 file_priv = file->driver_priv;
1712
1713 ret = ring->add_request(ring, &seqno); 1713 ret = ring->add_request(ring, &seqno);
1714 if (ret) 1714 if (ret)
1715 return ret; 1715 return ret;
1716 1716
1717 ring->outstanding_lazy_request = false; 1717 trace_i915_gem_request_add(ring, seqno);
1718 1718
1719 request->seqno = seqno; 1719 request->seqno = seqno;
1720 request->ring = ring; 1720 request->ring = ring;
@@ -1722,7 +1722,9 @@ i915_add_request(struct drm_device *dev,
1722 was_empty = list_empty(&ring->request_list); 1722 was_empty = list_empty(&ring->request_list);
1723 list_add_tail(&request->list, &ring->request_list); 1723 list_add_tail(&request->list, &ring->request_list);
1724 1724
1725 if (file_priv) { 1725 if (file) {
1726 struct drm_i915_file_private *file_priv = file->driver_priv;
1727
1726 spin_lock(&file_priv->mm.lock); 1728 spin_lock(&file_priv->mm.lock);
1727 request->file_priv = file_priv; 1729 request->file_priv = file_priv;
1728 list_add_tail(&request->client_list, 1730 list_add_tail(&request->client_list,
@@ -1730,6 +1732,8 @@ i915_add_request(struct drm_device *dev,
1730 spin_unlock(&file_priv->mm.lock); 1732 spin_unlock(&file_priv->mm.lock);
1731 } 1733 }
1732 1734
1735 ring->outstanding_lazy_request = false;
1736
1733 if (!dev_priv->mm.suspended) { 1737 if (!dev_priv->mm.suspended) {
1734 mod_timer(&dev_priv->hangcheck_timer, 1738 mod_timer(&dev_priv->hangcheck_timer,
1735 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); 1739 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
@@ -1846,18 +1850,15 @@ void i915_gem_reset(struct drm_device *dev)
1846 * This function clears the request list as sequence numbers are passed. 1850 * This function clears the request list as sequence numbers are passed.
1847 */ 1851 */
1848static void 1852static void
1849i915_gem_retire_requests_ring(struct drm_device *dev, 1853i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1850 struct intel_ring_buffer *ring)
1851{ 1854{
1852 drm_i915_private_t *dev_priv = dev->dev_private;
1853 uint32_t seqno; 1855 uint32_t seqno;
1854 int i; 1856 int i;
1855 1857
1856 if (!ring->status_page.page_addr || 1858 if (list_empty(&ring->request_list))
1857 list_empty(&ring->request_list))
1858 return; 1859 return;
1859 1860
1860 WARN_ON(i915_verify_lists(dev)); 1861 WARN_ON(i915_verify_lists(ring->dev));
1861 1862
1862 seqno = ring->get_seqno(ring); 1863 seqno = ring->get_seqno(ring);
1863 1864
@@ -1875,7 +1876,7 @@ i915_gem_retire_requests_ring(struct drm_device *dev,
1875 if (!i915_seqno_passed(seqno, request->seqno)) 1876 if (!i915_seqno_passed(seqno, request->seqno))
1876 break; 1877 break;
1877 1878
1878 trace_i915_gem_request_retire(dev, request->seqno); 1879 trace_i915_gem_request_retire(ring, request->seqno);
1879 1880
1880 list_del(&request->list); 1881 list_del(&request->list);
1881 i915_gem_request_remove_from_client(request); 1882 i915_gem_request_remove_from_client(request);
@@ -1901,13 +1902,13 @@ i915_gem_retire_requests_ring(struct drm_device *dev,
1901 i915_gem_object_move_to_inactive(obj); 1902 i915_gem_object_move_to_inactive(obj);
1902 } 1903 }
1903 1904
1904 if (unlikely (dev_priv->trace_irq_seqno && 1905 if (unlikely(ring->trace_irq_seqno &&
1905 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { 1906 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1906 ring->irq_put(ring); 1907 ring->irq_put(ring);
1907 dev_priv->trace_irq_seqno = 0; 1908 ring->trace_irq_seqno = 0;
1908 } 1909 }
1909 1910
1910 WARN_ON(i915_verify_lists(dev)); 1911 WARN_ON(i915_verify_lists(ring->dev));
1911} 1912}
1912 1913
1913void 1914void
@@ -1931,7 +1932,7 @@ i915_gem_retire_requests(struct drm_device *dev)
1931 } 1932 }
1932 1933
1933 for (i = 0; i < I915_NUM_RINGS; i++) 1934 for (i = 0; i < I915_NUM_RINGS; i++)
1934 i915_gem_retire_requests_ring(dev, &dev_priv->ring[i]); 1935 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1935} 1936}
1936 1937
1937static void 1938static void
@@ -1965,11 +1966,11 @@ i915_gem_retire_work_handler(struct work_struct *work)
1965 struct drm_i915_gem_request *request; 1966 struct drm_i915_gem_request *request;
1966 int ret; 1967 int ret;
1967 1968
1968 ret = i915_gem_flush_ring(dev, ring, 0, 1969 ret = i915_gem_flush_ring(ring,
1969 I915_GEM_GPU_DOMAINS); 1970 0, I915_GEM_GPU_DOMAINS);
1970 request = kzalloc(sizeof(*request), GFP_KERNEL); 1971 request = kzalloc(sizeof(*request), GFP_KERNEL);
1971 if (ret || request == NULL || 1972 if (ret || request == NULL ||
1972 i915_add_request(dev, NULL, request, ring)) 1973 i915_add_request(ring, NULL, request))
1973 kfree(request); 1974 kfree(request);
1974 } 1975 }
1975 1976
@@ -1982,18 +1983,33 @@ i915_gem_retire_work_handler(struct work_struct *work)
1982 mutex_unlock(&dev->struct_mutex); 1983 mutex_unlock(&dev->struct_mutex);
1983} 1984}
1984 1985
1986/**
1987 * Waits for a sequence number to be signaled, and cleans up the
1988 * request and object lists appropriately for that event.
1989 */
1985int 1990int
1986i915_do_wait_request(struct drm_device *dev, uint32_t seqno, 1991i915_wait_request(struct intel_ring_buffer *ring,
1987 bool interruptible, struct intel_ring_buffer *ring) 1992 uint32_t seqno,
1993 bool interruptible)
1988{ 1994{
1989 drm_i915_private_t *dev_priv = dev->dev_private; 1995 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1990 u32 ier; 1996 u32 ier;
1991 int ret = 0; 1997 int ret = 0;
1992 1998
1993 BUG_ON(seqno == 0); 1999 BUG_ON(seqno == 0);
1994 2000
1995 if (atomic_read(&dev_priv->mm.wedged)) 2001 if (atomic_read(&dev_priv->mm.wedged)) {
1996 return -EAGAIN; 2002 struct completion *x = &dev_priv->error_completion;
2003 bool recovery_complete;
2004 unsigned long flags;
2005
2006 /* Give the error handler a chance to run. */
2007 spin_lock_irqsave(&x->wait.lock, flags);
2008 recovery_complete = x->done > 0;
2009 spin_unlock_irqrestore(&x->wait.lock, flags);
2010
2011 return recovery_complete ? -EIO : -EAGAIN;
2012 }
1997 2013
1998 if (seqno == ring->outstanding_lazy_request) { 2014 if (seqno == ring->outstanding_lazy_request) {
1999 struct drm_i915_gem_request *request; 2015 struct drm_i915_gem_request *request;
@@ -2002,7 +2018,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
2002 if (request == NULL) 2018 if (request == NULL)
2003 return -ENOMEM; 2019 return -ENOMEM;
2004 2020
2005 ret = i915_add_request(dev, NULL, request, ring); 2021 ret = i915_add_request(ring, NULL, request);
2006 if (ret) { 2022 if (ret) {
2007 kfree(request); 2023 kfree(request);
2008 return ret; 2024 return ret;
@@ -2012,18 +2028,18 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
2012 } 2028 }
2013 2029
2014 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { 2030 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2015 if (HAS_PCH_SPLIT(dev)) 2031 if (HAS_PCH_SPLIT(ring->dev))
2016 ier = I915_READ(DEIER) | I915_READ(GTIER); 2032 ier = I915_READ(DEIER) | I915_READ(GTIER);
2017 else 2033 else
2018 ier = I915_READ(IER); 2034 ier = I915_READ(IER);
2019 if (!ier) { 2035 if (!ier) {
2020 DRM_ERROR("something (likely vbetool) disabled " 2036 DRM_ERROR("something (likely vbetool) disabled "
2021 "interrupts, re-enabling\n"); 2037 "interrupts, re-enabling\n");
2022 i915_driver_irq_preinstall(dev); 2038 i915_driver_irq_preinstall(ring->dev);
2023 i915_driver_irq_postinstall(dev); 2039 i915_driver_irq_postinstall(ring->dev);
2024 } 2040 }
2025 2041
2026 trace_i915_gem_request_wait_begin(dev, seqno); 2042 trace_i915_gem_request_wait_begin(ring, seqno);
2027 2043
2028 ring->waiting_seqno = seqno; 2044 ring->waiting_seqno = seqno;
2029 if (ring->irq_get(ring)) { 2045 if (ring->irq_get(ring)) {
@@ -2043,7 +2059,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
2043 ret = -EBUSY; 2059 ret = -EBUSY;
2044 ring->waiting_seqno = 0; 2060 ring->waiting_seqno = 0;
2045 2061
2046 trace_i915_gem_request_wait_end(dev, seqno); 2062 trace_i915_gem_request_wait_end(ring, seqno);
2047 } 2063 }
2048 if (atomic_read(&dev_priv->mm.wedged)) 2064 if (atomic_read(&dev_priv->mm.wedged))
2049 ret = -EAGAIN; 2065 ret = -EAGAIN;
@@ -2059,23 +2075,12 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
2059 * a separate wait queue to handle that. 2075 * a separate wait queue to handle that.
2060 */ 2076 */
2061 if (ret == 0) 2077 if (ret == 0)
2062 i915_gem_retire_requests_ring(dev, ring); 2078 i915_gem_retire_requests_ring(ring);
2063 2079
2064 return ret; 2080 return ret;
2065} 2081}
2066 2082
2067/** 2083/**
2068 * Waits for a sequence number to be signaled, and cleans up the
2069 * request and object lists appropriately for that event.
2070 */
2071static int
2072i915_wait_request(struct drm_device *dev, uint32_t seqno,
2073 struct intel_ring_buffer *ring)
2074{
2075 return i915_do_wait_request(dev, seqno, 1, ring);
2076}
2077
2078/**
2079 * Ensures that all rendering to the object has completed and the object is 2084 * Ensures that all rendering to the object has completed and the object is
2080 * safe to unbind from the GTT or access from the CPU. 2085 * safe to unbind from the GTT or access from the CPU.
2081 */ 2086 */
@@ -2083,7 +2088,6 @@ int
2083i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, 2088i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2084 bool interruptible) 2089 bool interruptible)
2085{ 2090{
2086 struct drm_device *dev = obj->base.dev;
2087 int ret; 2091 int ret;
2088 2092
2089 /* This function only exists to support waiting for existing rendering, 2093 /* This function only exists to support waiting for existing rendering,
@@ -2095,10 +2099,9 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2095 * it. 2099 * it.
2096 */ 2100 */
2097 if (obj->active) { 2101 if (obj->active) {
2098 ret = i915_do_wait_request(dev, 2102 ret = i915_wait_request(obj->ring,
2099 obj->last_rendering_seqno, 2103 obj->last_rendering_seqno,
2100 interruptible, 2104 interruptible);
2101 obj->ring);
2102 if (ret) 2105 if (ret)
2103 return ret; 2106 return ret;
2104 } 2107 }
@@ -2148,6 +2151,8 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2148 if (ret == -ERESTARTSYS) 2151 if (ret == -ERESTARTSYS)
2149 return ret; 2152 return ret;
2150 2153
2154 trace_i915_gem_object_unbind(obj);
2155
2151 i915_gem_gtt_unbind_object(obj); 2156 i915_gem_gtt_unbind_object(obj);
2152 i915_gem_object_put_pages_gtt(obj); 2157 i915_gem_object_put_pages_gtt(obj);
2153 2158
@@ -2163,29 +2168,27 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2163 if (i915_gem_object_is_purgeable(obj)) 2168 if (i915_gem_object_is_purgeable(obj))
2164 i915_gem_object_truncate(obj); 2169 i915_gem_object_truncate(obj);
2165 2170
2166 trace_i915_gem_object_unbind(obj);
2167
2168 return ret; 2171 return ret;
2169} 2172}
2170 2173
2171int 2174int
2172i915_gem_flush_ring(struct drm_device *dev, 2175i915_gem_flush_ring(struct intel_ring_buffer *ring,
2173 struct intel_ring_buffer *ring,
2174 uint32_t invalidate_domains, 2176 uint32_t invalidate_domains,
2175 uint32_t flush_domains) 2177 uint32_t flush_domains)
2176{ 2178{
2177 int ret; 2179 int ret;
2178 2180
2181 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2182
2179 ret = ring->flush(ring, invalidate_domains, flush_domains); 2183 ret = ring->flush(ring, invalidate_domains, flush_domains);
2180 if (ret) 2184 if (ret)
2181 return ret; 2185 return ret;
2182 2186
2183 i915_gem_process_flushing_list(dev, flush_domains, ring); 2187 i915_gem_process_flushing_list(ring, flush_domains);
2184 return 0; 2188 return 0;
2185} 2189}
2186 2190
2187static int i915_ring_idle(struct drm_device *dev, 2191static int i915_ring_idle(struct intel_ring_buffer *ring)
2188 struct intel_ring_buffer *ring)
2189{ 2192{
2190 int ret; 2193 int ret;
2191 2194
@@ -2193,15 +2196,15 @@ static int i915_ring_idle(struct drm_device *dev,
2193 return 0; 2196 return 0;
2194 2197
2195 if (!list_empty(&ring->gpu_write_list)) { 2198 if (!list_empty(&ring->gpu_write_list)) {
2196 ret = i915_gem_flush_ring(dev, ring, 2199 ret = i915_gem_flush_ring(ring,
2197 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); 2200 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2198 if (ret) 2201 if (ret)
2199 return ret; 2202 return ret;
2200 } 2203 }
2201 2204
2202 return i915_wait_request(dev, 2205 return i915_wait_request(ring,
2203 i915_gem_next_request_seqno(dev, ring), 2206 i915_gem_next_request_seqno(ring),
2204 ring); 2207 true);
2205} 2208}
2206 2209
2207int 2210int
@@ -2218,7 +2221,7 @@ i915_gpu_idle(struct drm_device *dev)
2218 2221
2219 /* Flush everything onto the inactive list. */ 2222 /* Flush everything onto the inactive list. */
2220 for (i = 0; i < I915_NUM_RINGS; i++) { 2223 for (i = 0; i < I915_NUM_RINGS; i++) {
2221 ret = i915_ring_idle(dev, &dev_priv->ring[i]); 2224 ret = i915_ring_idle(&dev_priv->ring[i]);
2222 if (ret) 2225 if (ret)
2223 return ret; 2226 return ret;
2224 } 2227 }
@@ -2409,8 +2412,7 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2409 2412
2410 if (obj->fenced_gpu_access) { 2413 if (obj->fenced_gpu_access) {
2411 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { 2414 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2412 ret = i915_gem_flush_ring(obj->base.dev, 2415 ret = i915_gem_flush_ring(obj->last_fenced_ring,
2413 obj->last_fenced_ring,
2414 0, obj->base.write_domain); 2416 0, obj->base.write_domain);
2415 if (ret) 2417 if (ret)
2416 return ret; 2418 return ret;
@@ -2422,10 +2424,10 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2422 if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { 2424 if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2423 if (!ring_passed_seqno(obj->last_fenced_ring, 2425 if (!ring_passed_seqno(obj->last_fenced_ring,
2424 obj->last_fenced_seqno)) { 2426 obj->last_fenced_seqno)) {
2425 ret = i915_do_wait_request(obj->base.dev, 2427 ret = i915_wait_request(obj->last_fenced_ring,
2426 obj->last_fenced_seqno, 2428 obj->last_fenced_seqno,
2427 interruptible, 2429 interruptible);
2428 obj->last_fenced_ring); 2430
2429 if (ret) 2431 if (ret)
2430 return ret; 2432 return ret;
2431 } 2433 }
@@ -2551,10 +2553,9 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2551 if (reg->setup_seqno) { 2553 if (reg->setup_seqno) {
2552 if (!ring_passed_seqno(obj->last_fenced_ring, 2554 if (!ring_passed_seqno(obj->last_fenced_ring,
2553 reg->setup_seqno)) { 2555 reg->setup_seqno)) {
2554 ret = i915_do_wait_request(obj->base.dev, 2556 ret = i915_wait_request(obj->last_fenced_ring,
2555 reg->setup_seqno, 2557 reg->setup_seqno,
2556 interruptible, 2558 interruptible);
2557 obj->last_fenced_ring);
2558 if (ret) 2559 if (ret)
2559 return ret; 2560 return ret;
2560 } 2561 }
@@ -2571,7 +2572,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2571 } else if (obj->tiling_changed) { 2572 } else if (obj->tiling_changed) {
2572 if (obj->fenced_gpu_access) { 2573 if (obj->fenced_gpu_access) {
2573 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { 2574 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2574 ret = i915_gem_flush_ring(obj->base.dev, obj->ring, 2575 ret = i915_gem_flush_ring(obj->ring,
2575 0, obj->base.write_domain); 2576 0, obj->base.write_domain);
2576 if (ret) 2577 if (ret)
2577 return ret; 2578 return ret;
@@ -2588,7 +2589,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2588 if (obj->tiling_changed) { 2589 if (obj->tiling_changed) {
2589 if (pipelined) { 2590 if (pipelined) {
2590 reg->setup_seqno = 2591 reg->setup_seqno =
2591 i915_gem_next_request_seqno(dev, pipelined); 2592 i915_gem_next_request_seqno(pipelined);
2592 obj->last_fenced_seqno = reg->setup_seqno; 2593 obj->last_fenced_seqno = reg->setup_seqno;
2593 obj->last_fenced_ring = pipelined; 2594 obj->last_fenced_ring = pipelined;
2594 } 2595 }
@@ -2628,7 +2629,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2628 old->fence_reg = I915_FENCE_REG_NONE; 2629 old->fence_reg = I915_FENCE_REG_NONE;
2629 old->last_fenced_ring = pipelined; 2630 old->last_fenced_ring = pipelined;
2630 old->last_fenced_seqno = 2631 old->last_fenced_seqno =
2631 pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0; 2632 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2632 2633
2633 drm_gem_object_unreference(&old->base); 2634 drm_gem_object_unreference(&old->base);
2634 } else if (obj->last_fenced_seqno == 0) 2635 } else if (obj->last_fenced_seqno == 0)
@@ -2640,7 +2641,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2640 obj->last_fenced_ring = pipelined; 2641 obj->last_fenced_ring = pipelined;
2641 2642
2642 reg->setup_seqno = 2643 reg->setup_seqno =
2643 pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0; 2644 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2644 obj->last_fenced_seqno = reg->setup_seqno; 2645 obj->last_fenced_seqno = reg->setup_seqno;
2645 2646
2646update: 2647update:
@@ -2837,7 +2838,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2837 2838
2838 obj->map_and_fenceable = mappable && fenceable; 2839 obj->map_and_fenceable = mappable && fenceable;
2839 2840
2840 trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable); 2841 trace_i915_gem_object_bind(obj, map_and_fenceable);
2841 return 0; 2842 return 0;
2842} 2843}
2843 2844
@@ -2860,13 +2861,11 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2860static int 2861static int
2861i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) 2862i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2862{ 2863{
2863 struct drm_device *dev = obj->base.dev;
2864
2865 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) 2864 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2866 return 0; 2865 return 0;
2867 2866
2868 /* Queue the GPU write cache flushing we need. */ 2867 /* Queue the GPU write cache flushing we need. */
2869 return i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain); 2868 return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2870} 2869}
2871 2870
2872/** Flushes the GTT write domain for the object if it's dirty. */ 2871/** Flushes the GTT write domain for the object if it's dirty. */
@@ -2933,6 +2932,9 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2933 if (obj->gtt_space == NULL) 2932 if (obj->gtt_space == NULL)
2934 return -EINVAL; 2933 return -EINVAL;
2935 2934
2935 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2936 return 0;
2937
2936 ret = i915_gem_object_flush_gpu_write_domain(obj); 2938 ret = i915_gem_object_flush_gpu_write_domain(obj);
2937 if (ret) 2939 if (ret)
2938 return ret; 2940 return ret;
@@ -3015,8 +3017,7 @@ i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
3015 return 0; 3017 return 0;
3016 3018
3017 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { 3019 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3018 ret = i915_gem_flush_ring(obj->base.dev, obj->ring, 3020 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3019 0, obj->base.write_domain);
3020 if (ret) 3021 if (ret)
3021 return ret; 3022 return ret;
3022 } 3023 }
@@ -3036,6 +3037,9 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3036 uint32_t old_write_domain, old_read_domains; 3037 uint32_t old_write_domain, old_read_domains;
3037 int ret; 3038 int ret;
3038 3039
3040 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3041 return 0;
3042
3039 ret = i915_gem_object_flush_gpu_write_domain(obj); 3043 ret = i915_gem_object_flush_gpu_write_domain(obj);
3040 if (ret) 3044 if (ret)
3041 return ret; 3045 return ret;
@@ -3209,6 +3213,9 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3209 u32 seqno = 0; 3213 u32 seqno = 0;
3210 int ret; 3214 int ret;
3211 3215
3216 if (atomic_read(&dev_priv->mm.wedged))
3217 return -EIO;
3218
3212 spin_lock(&file_priv->mm.lock); 3219 spin_lock(&file_priv->mm.lock);
3213 list_for_each_entry(request, &file_priv->mm.request_list, client_list) { 3220 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3214 if (time_after_eq(request->emitted_jiffies, recent_enough)) 3221 if (time_after_eq(request->emitted_jiffies, recent_enough))
@@ -3430,7 +3437,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3430 * flush earlier is beneficial. 3437 * flush earlier is beneficial.
3431 */ 3438 */
3432 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { 3439 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3433 ret = i915_gem_flush_ring(dev, obj->ring, 3440 ret = i915_gem_flush_ring(obj->ring,
3434 0, obj->base.write_domain); 3441 0, obj->base.write_domain);
3435 } else if (obj->ring->outstanding_lazy_request == 3442 } else if (obj->ring->outstanding_lazy_request ==
3436 obj->last_rendering_seqno) { 3443 obj->last_rendering_seqno) {
@@ -3441,9 +3448,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3441 */ 3448 */
3442 request = kzalloc(sizeof(*request), GFP_KERNEL); 3449 request = kzalloc(sizeof(*request), GFP_KERNEL);
3443 if (request) 3450 if (request)
3444 ret = i915_add_request(dev, 3451 ret = i915_add_request(obj->ring, NULL,request);
3445 NULL, request,
3446 obj->ring);
3447 else 3452 else
3448 ret = -ENOMEM; 3453 ret = -ENOMEM;
3449 } 3454 }
@@ -3453,7 +3458,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3453 * are actually unmasked, and our working set ends up being 3458 * are actually unmasked, and our working set ends up being
3454 * larger than required. 3459 * larger than required.
3455 */ 3460 */
3456 i915_gem_retire_requests_ring(dev, obj->ring); 3461 i915_gem_retire_requests_ring(obj->ring);
3457 3462
3458 args->busy = obj->active; 3463 args->busy = obj->active;
3459 } 3464 }
@@ -3583,6 +3588,8 @@ static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3583 kfree(obj->page_cpu_valid); 3588 kfree(obj->page_cpu_valid);
3584 kfree(obj->bit_17); 3589 kfree(obj->bit_17);
3585 kfree(obj); 3590 kfree(obj);
3591
3592 trace_i915_gem_object_destroy(obj);
3586} 3593}
3587 3594
3588void i915_gem_free_object(struct drm_gem_object *gem_obj) 3595void i915_gem_free_object(struct drm_gem_object *gem_obj)
@@ -3590,8 +3597,6 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
3590 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); 3597 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3591 struct drm_device *dev = obj->base.dev; 3598 struct drm_device *dev = obj->base.dev;
3592 3599
3593 trace_i915_gem_object_destroy(obj);
3594
3595 while (obj->pin_count > 0) 3600 while (obj->pin_count > 0)
3596 i915_gem_object_unpin(obj); 3601 i915_gem_object_unpin(obj);
3597 3602
diff --git a/drivers/gpu/drm/i915/i915_gem_debug.c b/drivers/gpu/drm/i915/i915_gem_debug.c
index 29d014c48ca2..8da1899bd24f 100644
--- a/drivers/gpu/drm/i915/i915_gem_debug.c
+++ b/drivers/gpu/drm/i915/i915_gem_debug.c
@@ -134,51 +134,6 @@ i915_verify_lists(struct drm_device *dev)
134} 134}
135#endif /* WATCH_INACTIVE */ 135#endif /* WATCH_INACTIVE */
136 136
137
138#if WATCH_EXEC | WATCH_PWRITE
139static void
140i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end,
141 uint32_t bias, uint32_t mark)
142{
143 uint32_t *mem = kmap_atomic(page, KM_USER0);
144 int i;
145 for (i = start; i < end; i += 4)
146 DRM_INFO("%08x: %08x%s\n",
147 (int) (bias + i), mem[i / 4],
148 (bias + i == mark) ? " ********" : "");
149 kunmap_atomic(mem, KM_USER0);
150 /* give syslog time to catch up */
151 msleep(1);
152}
153
154void
155i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
156 const char *where, uint32_t mark)
157{
158 int page;
159
160 DRM_INFO("%s: object at offset %08x\n", where, obj->gtt_offset);
161 for (page = 0; page < (len + PAGE_SIZE-1) / PAGE_SIZE; page++) {
162 int page_len, chunk, chunk_len;
163
164 page_len = len - page * PAGE_SIZE;
165 if (page_len > PAGE_SIZE)
166 page_len = PAGE_SIZE;
167
168 for (chunk = 0; chunk < page_len; chunk += 128) {
169 chunk_len = page_len - chunk;
170 if (chunk_len > 128)
171 chunk_len = 128;
172 i915_gem_dump_page(obj->pages[page],
173 chunk, chunk + chunk_len,
174 obj->gtt_offset +
175 page * PAGE_SIZE,
176 mark);
177 }
178 }
179}
180#endif
181
182#if WATCH_COHERENCY 137#if WATCH_COHERENCY
183void 138void
184i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, int handle) 139i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, int handle)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index 3d39005540aa..da05a2692a75 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -30,6 +30,7 @@
30#include "drm.h" 30#include "drm.h"
31#include "i915_drv.h" 31#include "i915_drv.h"
32#include "i915_drm.h" 32#include "i915_drm.h"
33#include "i915_trace.h"
33 34
34static bool 35static bool
35mark_free(struct drm_i915_gem_object *obj, struct list_head *unwind) 36mark_free(struct drm_i915_gem_object *obj, struct list_head *unwind)
@@ -63,6 +64,8 @@ i915_gem_evict_something(struct drm_device *dev, int min_size,
63 return 0; 64 return 0;
64 } 65 }
65 66
67 trace_i915_gem_evict(dev, min_size, alignment, mappable);
68
66 /* 69 /*
67 * The goal is to evict objects and amalgamate space in LRU order. 70 * The goal is to evict objects and amalgamate space in LRU order.
68 * The oldest idle objects reside on the inactive list, which is in 71 * The oldest idle objects reside on the inactive list, which is in
@@ -189,6 +192,8 @@ i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only)
189 if (lists_empty) 192 if (lists_empty)
190 return -ENOSPC; 193 return -ENOSPC;
191 194
195 trace_i915_gem_evict_everything(dev, purgeable_only);
196
192 /* Flush everything (on to the inactive lists) and evict */ 197 /* Flush everything (on to the inactive lists) and evict */
193 ret = i915_gpu_idle(dev); 198 ret = i915_gpu_idle(dev);
194 if (ret) 199 if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index d2f445e825f2..84fa24e6cca8 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -282,21 +282,6 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
282 282
283 target_offset = to_intel_bo(target_obj)->gtt_offset; 283 target_offset = to_intel_bo(target_obj)->gtt_offset;
284 284
285#if WATCH_RELOC
286 DRM_INFO("%s: obj %p offset %08x target %d "
287 "read %08x write %08x gtt %08x "
288 "presumed %08x delta %08x\n",
289 __func__,
290 obj,
291 (int) reloc->offset,
292 (int) reloc->target_handle,
293 (int) reloc->read_domains,
294 (int) reloc->write_domain,
295 (int) target_offset,
296 (int) reloc->presumed_offset,
297 reloc->delta);
298#endif
299
300 /* The target buffer should have appeared before us in the 285 /* The target buffer should have appeared before us in the
301 * exec_object list, so it should have a GTT space bound by now. 286 * exec_object list, so it should have a GTT space bound by now.
302 */ 287 */
@@ -690,8 +675,6 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
690 /* reacquire the objects */ 675 /* reacquire the objects */
691 eb_reset(eb); 676 eb_reset(eb);
692 for (i = 0; i < count; i++) { 677 for (i = 0; i < count; i++) {
693 struct drm_i915_gem_object *obj;
694
695 obj = to_intel_bo(drm_gem_object_lookup(dev, file, 678 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
696 exec[i].handle)); 679 exec[i].handle));
697 if (obj == NULL) { 680 if (obj == NULL) {
@@ -749,8 +732,7 @@ i915_gem_execbuffer_flush(struct drm_device *dev,
749 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { 732 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
750 for (i = 0; i < I915_NUM_RINGS; i++) 733 for (i = 0; i < I915_NUM_RINGS; i++)
751 if (flush_rings & (1 << i)) { 734 if (flush_rings & (1 << i)) {
752 ret = i915_gem_flush_ring(dev, 735 ret = i915_gem_flush_ring(&dev_priv->ring[i],
753 &dev_priv->ring[i],
754 invalidate_domains, 736 invalidate_domains,
755 flush_domains); 737 flush_domains);
756 if (ret) 738 if (ret)
@@ -789,7 +771,7 @@ i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
789 if (request == NULL) 771 if (request == NULL)
790 return -ENOMEM; 772 return -ENOMEM;
791 773
792 ret = i915_add_request(obj->base.dev, NULL, request, from); 774 ret = i915_add_request(from, NULL, request);
793 if (ret) { 775 if (ret) {
794 kfree(request); 776 kfree(request);
795 return ret; 777 return ret;
@@ -817,12 +799,6 @@ i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
817 i915_gem_object_set_to_gpu_domain(obj, ring, &cd); 799 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
818 800
819 if (cd.invalidate_domains | cd.flush_domains) { 801 if (cd.invalidate_domains | cd.flush_domains) {
820#if WATCH_EXEC
821 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
822 __func__,
823 cd.invalidate_domains,
824 cd.flush_domains);
825#endif
826 ret = i915_gem_execbuffer_flush(ring->dev, 802 ret = i915_gem_execbuffer_flush(ring->dev,
827 cd.invalidate_domains, 803 cd.invalidate_domains,
828 cd.flush_domains, 804 cd.flush_domains,
@@ -926,6 +902,10 @@ i915_gem_execbuffer_move_to_active(struct list_head *objects,
926 struct drm_i915_gem_object *obj; 902 struct drm_i915_gem_object *obj;
927 903
928 list_for_each_entry(obj, objects, exec_list) { 904 list_for_each_entry(obj, objects, exec_list) {
905 u32 old_read = obj->base.read_domains;
906 u32 old_write = obj->base.write_domain;
907
908
929 obj->base.read_domains = obj->base.pending_read_domains; 909 obj->base.read_domains = obj->base.pending_read_domains;
930 obj->base.write_domain = obj->base.pending_write_domain; 910 obj->base.write_domain = obj->base.pending_write_domain;
931 obj->fenced_gpu_access = obj->pending_fenced_gpu_access; 911 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
@@ -939,9 +919,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *objects,
939 intel_mark_busy(ring->dev, obj); 919 intel_mark_busy(ring->dev, obj);
940 } 920 }
941 921
942 trace_i915_gem_object_change_domain(obj, 922 trace_i915_gem_object_change_domain(obj, old_read, old_write);
943 obj->base.read_domains,
944 obj->base.write_domain);
945 } 923 }
946} 924}
947 925
@@ -963,14 +941,14 @@ i915_gem_execbuffer_retire_commands(struct drm_device *dev,
963 if (INTEL_INFO(dev)->gen >= 4) 941 if (INTEL_INFO(dev)->gen >= 4)
964 invalidate |= I915_GEM_DOMAIN_SAMPLER; 942 invalidate |= I915_GEM_DOMAIN_SAMPLER;
965 if (ring->flush(ring, invalidate, 0)) { 943 if (ring->flush(ring, invalidate, 0)) {
966 i915_gem_next_request_seqno(dev, ring); 944 i915_gem_next_request_seqno(ring);
967 return; 945 return;
968 } 946 }
969 947
970 /* Add a breadcrumb for the completion of the batch buffer */ 948 /* Add a breadcrumb for the completion of the batch buffer */
971 request = kzalloc(sizeof(*request), GFP_KERNEL); 949 request = kzalloc(sizeof(*request), GFP_KERNEL);
972 if (request == NULL || i915_add_request(dev, file, request, ring)) { 950 if (request == NULL || i915_add_request(ring, file, request)) {
973 i915_gem_next_request_seqno(dev, ring); 951 i915_gem_next_request_seqno(ring);
974 kfree(request); 952 kfree(request);
975 } 953 }
976} 954}
@@ -1000,10 +978,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1000 if (ret) 978 if (ret)
1001 return ret; 979 return ret;
1002 980
1003#if WATCH_EXEC
1004 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1005 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1006#endif
1007 switch (args->flags & I915_EXEC_RING_MASK) { 981 switch (args->flags & I915_EXEC_RING_MASK) {
1008 case I915_EXEC_DEFAULT: 982 case I915_EXEC_DEFAULT:
1009 case I915_EXEC_RENDER: 983 case I915_EXEC_RENDER:
@@ -1174,7 +1148,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1174 if (ret) 1148 if (ret)
1175 goto err; 1149 goto err;
1176 1150
1177 seqno = i915_gem_next_request_seqno(dev, ring); 1151 seqno = i915_gem_next_request_seqno(ring);
1178 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { 1152 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
1179 if (seqno < ring->sync_seqno[i]) { 1153 if (seqno < ring->sync_seqno[i]) {
1180 /* The GPU can not handle its semaphore value wrapping, 1154 /* The GPU can not handle its semaphore value wrapping,
@@ -1189,6 +1163,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1189 } 1163 }
1190 } 1164 }
1191 1165
1166 trace_i915_gem_ring_dispatch(ring, seqno);
1167
1192 exec_start = batch_obj->gtt_offset + args->batch_start_offset; 1168 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1193 exec_len = args->batch_len; 1169 exec_len = args->batch_len;
1194 if (cliprects) { 1170 if (cliprects) {
@@ -1245,11 +1221,6 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
1245 struct drm_i915_gem_exec_object2 *exec2_list = NULL; 1221 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1246 int ret, i; 1222 int ret, i;
1247 1223
1248#if WATCH_EXEC
1249 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1250 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1251#endif
1252
1253 if (args->buffer_count < 1) { 1224 if (args->buffer_count < 1) {
1254 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); 1225 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1255 return -EINVAL; 1226 return -EINVAL;
@@ -1330,11 +1301,6 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data,
1330 struct drm_i915_gem_exec_object2 *exec2_list = NULL; 1301 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1331 int ret; 1302 int ret;
1332 1303
1333#if WATCH_EXEC
1334 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1335 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1336#endif
1337
1338 if (args->buffer_count < 1) { 1304 if (args->buffer_count < 1) {
1339 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); 1305 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
1340 return -EINVAL; 1306 return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 22a32b9932c5..a093d67b94e2 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -284,11 +284,6 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
284 struct drm_i915_gem_set_tiling *args = data; 284 struct drm_i915_gem_set_tiling *args = data;
285 drm_i915_private_t *dev_priv = dev->dev_private; 285 drm_i915_private_t *dev_priv = dev->dev_private;
286 struct drm_i915_gem_object *obj; 286 struct drm_i915_gem_object *obj;
287 int ret;
288
289 ret = i915_gem_check_is_wedged(dev);
290 if (ret)
291 return ret;
292 287
293 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 288 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
294 if (obj == NULL) 289 if (obj == NULL)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8a9e08bf1cf7..346dd85cbbd3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -85,21 +85,11 @@ ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
85 } 85 }
86} 86}
87 87
88static inline u32
89i915_pipestat(int pipe)
90{
91 if (pipe == 0)
92 return PIPEASTAT;
93 if (pipe == 1)
94 return PIPEBSTAT;
95 BUG();
96}
97
98void 88void
99i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 89i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
100{ 90{
101 if ((dev_priv->pipestat[pipe] & mask) != mask) { 91 if ((dev_priv->pipestat[pipe] & mask) != mask) {
102 u32 reg = i915_pipestat(pipe); 92 u32 reg = PIPESTAT(pipe);
103 93
104 dev_priv->pipestat[pipe] |= mask; 94 dev_priv->pipestat[pipe] |= mask;
105 /* Enable the interrupt, clear any pending status */ 95 /* Enable the interrupt, clear any pending status */
@@ -112,7 +102,7 @@ void
112i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 102i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
113{ 103{
114 if ((dev_priv->pipestat[pipe] & mask) != 0) { 104 if ((dev_priv->pipestat[pipe] & mask) != 0) {
115 u32 reg = i915_pipestat(pipe); 105 u32 reg = PIPESTAT(pipe);
116 106
117 dev_priv->pipestat[pipe] &= ~mask; 107 dev_priv->pipestat[pipe] &= ~mask;
118 I915_WRITE(reg, dev_priv->pipestat[pipe]); 108 I915_WRITE(reg, dev_priv->pipestat[pipe]);
@@ -171,12 +161,12 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
171 161
172 if (!i915_pipe_enabled(dev, pipe)) { 162 if (!i915_pipe_enabled(dev, pipe)) {
173 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 163 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
174 "pipe %d\n", pipe); 164 "pipe %c\n", pipe_name(pipe));
175 return 0; 165 return 0;
176 } 166 }
177 167
178 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; 168 high_frame = PIPEFRAME(pipe);
179 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; 169 low_frame = PIPEFRAMEPIXEL(pipe);
180 170
181 /* 171 /*
182 * High & low register fields aren't synchronized, so make sure 172 * High & low register fields aren't synchronized, so make sure
@@ -197,11 +187,11 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
197u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 187u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
198{ 188{
199 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
200 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; 190 int reg = PIPE_FRMCOUNT_GM45(pipe);
201 191
202 if (!i915_pipe_enabled(dev, pipe)) { 192 if (!i915_pipe_enabled(dev, pipe)) {
203 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 193 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
204 "pipe %d\n", pipe); 194 "pipe %c\n", pipe_name(pipe));
205 return 0; 195 return 0;
206 } 196 }
207 197
@@ -219,7 +209,7 @@ int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
219 209
220 if (!i915_pipe_enabled(dev, pipe)) { 210 if (!i915_pipe_enabled(dev, pipe)) {
221 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " 211 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
222 "pipe %d\n", pipe); 212 "pipe %c\n", pipe_name(pipe));
223 return 0; 213 return 0;
224 } 214 }
225 215
@@ -367,7 +357,7 @@ static void notify_ring(struct drm_device *dev,
367 return; 357 return;
368 358
369 seqno = ring->get_seqno(ring); 359 seqno = ring->get_seqno(ring);
370 trace_i915_gem_request_complete(dev, seqno); 360 trace_i915_gem_request_complete(ring, seqno);
371 361
372 ring->irq_seqno = seqno; 362 ring->irq_seqno = seqno;
373 wake_up_all(&ring->irq_queue); 363 wake_up_all(&ring->irq_queue);
@@ -419,6 +409,7 @@ static void pch_irq_handler(struct drm_device *dev)
419{ 409{
420 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 410 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
421 u32 pch_iir; 411 u32 pch_iir;
412 int pipe;
422 413
423 pch_iir = I915_READ(SDEIIR); 414 pch_iir = I915_READ(SDEIIR);
424 415
@@ -439,13 +430,11 @@ static void pch_irq_handler(struct drm_device *dev)
439 if (pch_iir & SDE_POISON) 430 if (pch_iir & SDE_POISON)
440 DRM_ERROR("PCH poison interrupt\n"); 431 DRM_ERROR("PCH poison interrupt\n");
441 432
442 if (pch_iir & SDE_FDI_MASK) { 433 if (pch_iir & SDE_FDI_MASK)
443 u32 fdia, fdib; 434 for_each_pipe(pipe)
444 435 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
445 fdia = I915_READ(FDI_RXA_IIR); 436 pipe_name(pipe),
446 fdib = I915_READ(FDI_RXB_IIR); 437 I915_READ(FDI_RX_IIR(pipe)));
447 DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib);
448 }
449 438
450 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 439 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
451 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 440 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
@@ -650,9 +639,14 @@ static void
650i915_error_state_free(struct drm_device *dev, 639i915_error_state_free(struct drm_device *dev,
651 struct drm_i915_error_state *error) 640 struct drm_i915_error_state *error)
652{ 641{
653 i915_error_object_free(error->batchbuffer[0]); 642 int i;
654 i915_error_object_free(error->batchbuffer[1]); 643
655 i915_error_object_free(error->ringbuffer); 644 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
645 i915_error_object_free(error->batchbuffer[i]);
646
647 for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
648 i915_error_object_free(error->ringbuffer[i]);
649
656 kfree(error->active_bo); 650 kfree(error->active_bo);
657 kfree(error->overlay); 651 kfree(error->overlay);
658 kfree(error); 652 kfree(error);
@@ -767,7 +761,7 @@ static void i915_capture_error_state(struct drm_device *dev)
767 struct drm_i915_gem_object *obj; 761 struct drm_i915_gem_object *obj;
768 struct drm_i915_error_state *error; 762 struct drm_i915_error_state *error;
769 unsigned long flags; 763 unsigned long flags;
770 int i; 764 int i, pipe;
771 765
772 spin_lock_irqsave(&dev_priv->error_lock, flags); 766 spin_lock_irqsave(&dev_priv->error_lock, flags);
773 error = dev_priv->first_error; 767 error = dev_priv->first_error;
@@ -775,19 +769,21 @@ static void i915_capture_error_state(struct drm_device *dev)
775 if (error) 769 if (error)
776 return; 770 return;
777 771
772 /* Account for pipe specific data like PIPE*STAT */
778 error = kmalloc(sizeof(*error), GFP_ATOMIC); 773 error = kmalloc(sizeof(*error), GFP_ATOMIC);
779 if (!error) { 774 if (!error) {
780 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 775 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
781 return; 776 return;
782 } 777 }
783 778
784 DRM_DEBUG_DRIVER("generating error event\n"); 779 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
780 dev->primary->index);
785 781
786 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]); 782 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
787 error->eir = I915_READ(EIR); 783 error->eir = I915_READ(EIR);
788 error->pgtbl_er = I915_READ(PGTBL_ER); 784 error->pgtbl_er = I915_READ(PGTBL_ER);
789 error->pipeastat = I915_READ(PIPEASTAT); 785 for_each_pipe(pipe)
790 error->pipebstat = I915_READ(PIPEBSTAT); 786 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
791 error->instpm = I915_READ(INSTPM); 787 error->instpm = I915_READ(INSTPM);
792 error->error = 0; 788 error->error = 0;
793 if (INTEL_INFO(dev)->gen >= 6) { 789 if (INTEL_INFO(dev)->gen >= 6) {
@@ -826,15 +822,16 @@ static void i915_capture_error_state(struct drm_device *dev)
826 } 822 }
827 i915_gem_record_fences(dev, error); 823 i915_gem_record_fences(dev, error);
828 824
829 /* Record the active batchbuffers */ 825 /* Record the active batch and ring buffers */
830 for (i = 0; i < I915_NUM_RINGS; i++) 826 for (i = 0; i < I915_NUM_RINGS; i++) {
831 error->batchbuffer[i] = 827 error->batchbuffer[i] =
832 i915_error_first_batchbuffer(dev_priv, 828 i915_error_first_batchbuffer(dev_priv,
833 &dev_priv->ring[i]); 829 &dev_priv->ring[i]);
834 830
835 /* Record the ringbuffer */ 831 error->ringbuffer[i] =
836 error->ringbuffer = i915_error_object_create(dev_priv, 832 i915_error_object_create(dev_priv,
837 dev_priv->ring[RCS].obj); 833 dev_priv->ring[i].obj);
834 }
838 835
839 /* Record buffers on the active and pinned lists. */ 836 /* Record buffers on the active and pinned lists. */
840 error->active_bo = NULL; 837 error->active_bo = NULL;
@@ -907,6 +904,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
907{ 904{
908 struct drm_i915_private *dev_priv = dev->dev_private; 905 struct drm_i915_private *dev_priv = dev->dev_private;
909 u32 eir = I915_READ(EIR); 906 u32 eir = I915_READ(EIR);
907 int pipe;
910 908
911 if (!eir) 909 if (!eir)
912 return; 910 return;
@@ -955,14 +953,10 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
955 } 953 }
956 954
957 if (eir & I915_ERROR_MEMORY_REFRESH) { 955 if (eir & I915_ERROR_MEMORY_REFRESH) {
958 u32 pipea_stats = I915_READ(PIPEASTAT); 956 printk(KERN_ERR "memory refresh error:\n");
959 u32 pipeb_stats = I915_READ(PIPEBSTAT); 957 for_each_pipe(pipe)
960 958 printk(KERN_ERR "pipe %c stat: 0x%08x\n",
961 printk(KERN_ERR "memory refresh error\n"); 959 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
962 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
963 pipea_stats);
964 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
965 pipeb_stats);
966 /* pipestat has already been acked */ 960 /* pipestat has already been acked */
967 } 961 }
968 if (eir & I915_ERROR_INSTRUCTION) { 962 if (eir & I915_ERROR_INSTRUCTION) {
@@ -1076,10 +1070,10 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1076 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 1070 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1077 obj = work->pending_flip_obj; 1071 obj = work->pending_flip_obj;
1078 if (INTEL_INFO(dev)->gen >= 4) { 1072 if (INTEL_INFO(dev)->gen >= 4) {
1079 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF; 1073 int dspsurf = DSPSURF(intel_crtc->plane);
1080 stall_detected = I915_READ(dspsurf) == obj->gtt_offset; 1074 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1081 } else { 1075 } else {
1082 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR; 1076 int dspaddr = DSPADDR(intel_crtc->plane);
1083 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + 1077 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1084 crtc->y * crtc->fb->pitch + 1078 crtc->y * crtc->fb->pitch +
1085 crtc->x * crtc->fb->bits_per_pixel/8); 1079 crtc->x * crtc->fb->bits_per_pixel/8);
@@ -1099,12 +1093,13 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1099 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1093 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1100 struct drm_i915_master_private *master_priv; 1094 struct drm_i915_master_private *master_priv;
1101 u32 iir, new_iir; 1095 u32 iir, new_iir;
1102 u32 pipea_stats, pipeb_stats; 1096 u32 pipe_stats[I915_MAX_PIPES];
1103 u32 vblank_status; 1097 u32 vblank_status;
1104 int vblank = 0; 1098 int vblank = 0;
1105 unsigned long irqflags; 1099 unsigned long irqflags;
1106 int irq_received; 1100 int irq_received;
1107 int ret = IRQ_NONE; 1101 int ret = IRQ_NONE, pipe;
1102 bool blc_event = false;
1108 1103
1109 atomic_inc(&dev_priv->irq_received); 1104 atomic_inc(&dev_priv->irq_received);
1110 1105
@@ -1127,27 +1122,23 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1127 * interrupts (for non-MSI). 1122 * interrupts (for non-MSI).
1128 */ 1123 */
1129 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1124 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1130 pipea_stats = I915_READ(PIPEASTAT);
1131 pipeb_stats = I915_READ(PIPEBSTAT);
1132
1133 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 1125 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1134 i915_handle_error(dev, false); 1126 i915_handle_error(dev, false);
1135 1127
1136 /* 1128 for_each_pipe(pipe) {
1137 * Clear the PIPE(A|B)STAT regs before the IIR 1129 int reg = PIPESTAT(pipe);
1138 */ 1130 pipe_stats[pipe] = I915_READ(reg);
1139 if (pipea_stats & 0x8000ffff) { 1131
1140 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) 1132 /*
1141 DRM_DEBUG_DRIVER("pipe a underrun\n"); 1133 * Clear the PIPE*STAT regs before the IIR
1142 I915_WRITE(PIPEASTAT, pipea_stats); 1134 */
1143 irq_received = 1; 1135 if (pipe_stats[pipe] & 0x8000ffff) {
1144 } 1136 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1145 1137 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1146 if (pipeb_stats & 0x8000ffff) { 1138 pipe_name(pipe));
1147 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) 1139 I915_WRITE(reg, pipe_stats[pipe]);
1148 DRM_DEBUG_DRIVER("pipe b underrun\n"); 1140 irq_received = 1;
1149 I915_WRITE(PIPEBSTAT, pipeb_stats); 1141 }
1150 irq_received = 1;
1151 } 1142 }
1152 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1143 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1153 1144
@@ -1198,27 +1189,22 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1198 intel_finish_page_flip_plane(dev, 1); 1189 intel_finish_page_flip_plane(dev, 1);
1199 } 1190 }
1200 1191
1201 if (pipea_stats & vblank_status && 1192 for_each_pipe(pipe) {
1202 drm_handle_vblank(dev, 0)) { 1193 if (pipe_stats[pipe] & vblank_status &&
1203 vblank++; 1194 drm_handle_vblank(dev, pipe)) {
1204 if (!dev_priv->flip_pending_is_done) { 1195 vblank++;
1205 i915_pageflip_stall_check(dev, 0); 1196 if (!dev_priv->flip_pending_is_done) {
1206 intel_finish_page_flip(dev, 0); 1197 i915_pageflip_stall_check(dev, pipe);
1198 intel_finish_page_flip(dev, pipe);
1199 }
1207 } 1200 }
1208 }
1209 1201
1210 if (pipeb_stats & vblank_status && 1202 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1211 drm_handle_vblank(dev, 1)) { 1203 blc_event = true;
1212 vblank++;
1213 if (!dev_priv->flip_pending_is_done) {
1214 i915_pageflip_stall_check(dev, 1);
1215 intel_finish_page_flip(dev, 1);
1216 }
1217 } 1204 }
1218 1205
1219 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || 1206
1220 (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || 1207 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1221 (iir & I915_ASLE_INTERRUPT))
1222 intel_opregion_asle_intr(dev); 1208 intel_opregion_asle_intr(dev);
1223 1209
1224 /* With MSI, interrupts are only generated when iir 1210 /* With MSI, interrupts are only generated when iir
@@ -1268,16 +1254,6 @@ static int i915_emit_irq(struct drm_device * dev)
1268 return dev_priv->counter; 1254 return dev_priv->counter;
1269} 1255}
1270 1256
1271void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1272{
1273 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1274 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1275
1276 if (dev_priv->trace_irq_seqno == 0 &&
1277 ring->irq_get(ring))
1278 dev_priv->trace_irq_seqno = seqno;
1279}
1280
1281static int i915_wait_irq(struct drm_device * dev, int irq_nr) 1257static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1282{ 1258{
1283 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1259 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1356,6 +1332,22 @@ int i915_irq_wait(struct drm_device *dev, void *data,
1356 return i915_wait_irq(dev, irqwait->irq_seq); 1332 return i915_wait_irq(dev, irqwait->irq_seq);
1357} 1333}
1358 1334
1335static void i915_vblank_work_func(struct work_struct *work)
1336{
1337 drm_i915_private_t *dev_priv =
1338 container_of(work, drm_i915_private_t, vblank_work);
1339
1340 if (atomic_read(&dev_priv->vblank_enabled)) {
1341 if (!dev_priv->vblank_pm_qos.pm_qos_class)
1342 pm_qos_add_request(&dev_priv->vblank_pm_qos,
1343 PM_QOS_CPU_DMA_LATENCY,
1344 15); //>=20 won't work
1345 } else {
1346 if (dev_priv->vblank_pm_qos.pm_qos_class)
1347 pm_qos_remove_request(&dev_priv->vblank_pm_qos);
1348 }
1349}
1350
1359/* Called from drm generic code, passed 'crtc' which 1351/* Called from drm generic code, passed 'crtc' which
1360 * we use as a pipe index 1352 * we use as a pipe index
1361 */ 1353 */
@@ -1378,6 +1370,16 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
1378 i915_enable_pipestat(dev_priv, pipe, 1370 i915_enable_pipestat(dev_priv, pipe,
1379 PIPE_VBLANK_INTERRUPT_ENABLE); 1371 PIPE_VBLANK_INTERRUPT_ENABLE);
1380 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1372 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1373
1374 /* gen3 platforms have an issue with vsync interrupts not reaching
1375 * cpu during deep c-state sleep (>C1), so we need to install a
1376 * PM QoS handle to prevent C-state starvation of the GPU.
1377 */
1378 if (dev_priv->info->gen == 3 && !dev_priv->info->is_g33) {
1379 atomic_inc(&dev_priv->vblank_enabled);
1380 queue_work(dev_priv->wq, &dev_priv->vblank_work);
1381 }
1382
1381 return 0; 1383 return 0;
1382} 1384}
1383 1385
@@ -1389,6 +1391,11 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
1389 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1391 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1390 unsigned long irqflags; 1392 unsigned long irqflags;
1391 1393
1394 if (dev_priv->info->gen == 3 && !dev_priv->info->is_g33) {
1395 atomic_dec(&dev_priv->vblank_enabled);
1396 queue_work(dev_priv->wq, &dev_priv->vblank_work);
1397 }
1398
1392 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1399 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1393 if (HAS_PCH_SPLIT(dev)) 1400 if (HAS_PCH_SPLIT(dev))
1394 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1401 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
@@ -1400,16 +1407,6 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
1400 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1407 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1401} 1408}
1402 1409
1403void i915_enable_interrupt (struct drm_device *dev)
1404{
1405 struct drm_i915_private *dev_priv = dev->dev_private;
1406
1407 if (!HAS_PCH_SPLIT(dev))
1408 intel_opregion_enable_asle(dev);
1409 dev_priv->irq_enabled = 1;
1410}
1411
1412
1413/* Set the vblank monitor pipe 1410/* Set the vblank monitor pipe
1414 */ 1411 */
1415int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1412int i915_vblank_pipe_set(struct drm_device *dev, void *data,
@@ -1618,6 +1615,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1618 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1615 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1619 u32 render_irqs; 1616 u32 render_irqs;
1620 u32 hotplug_mask; 1617 u32 hotplug_mask;
1618 int pipe;
1621 1619
1622 dev_priv->irq_mask = ~display_mask; 1620 dev_priv->irq_mask = ~display_mask;
1623 1621
@@ -1646,12 +1644,16 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1646 POSTING_READ(GTIER); 1644 POSTING_READ(GTIER);
1647 1645
1648 if (HAS_PCH_CPT(dev)) { 1646 if (HAS_PCH_CPT(dev)) {
1649 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT | 1647 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1650 SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ; 1648 SDE_PORTB_HOTPLUG_CPT |
1649 SDE_PORTC_HOTPLUG_CPT |
1650 SDE_PORTD_HOTPLUG_CPT);
1651 } else { 1651 } else {
1652 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | 1652 hotplug_mask = (SDE_CRT_HOTPLUG |
1653 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; 1653 SDE_PORTB_HOTPLUG |
1654 hotplug_mask |= SDE_AUX_MASK; 1654 SDE_PORTC_HOTPLUG |
1655 SDE_PORTD_HOTPLUG |
1656 SDE_AUX_MASK);
1655 } 1657 }
1656 1658
1657 dev_priv->pch_irq_mask = ~hotplug_mask; 1659 dev_priv->pch_irq_mask = ~hotplug_mask;
@@ -1674,11 +1676,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1674void i915_driver_irq_preinstall(struct drm_device * dev) 1676void i915_driver_irq_preinstall(struct drm_device * dev)
1675{ 1677{
1676 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1678 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1679 int pipe;
1677 1680
1678 atomic_set(&dev_priv->irq_received, 0); 1681 atomic_set(&dev_priv->irq_received, 0);
1682 atomic_set(&dev_priv->vblank_enabled, 0);
1679 1683
1680 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 1684 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1681 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 1685 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1686 INIT_WORK(&dev_priv->vblank_work, i915_vblank_work_func);
1682 1687
1683 if (HAS_PCH_SPLIT(dev)) { 1688 if (HAS_PCH_SPLIT(dev)) {
1684 ironlake_irq_preinstall(dev); 1689 ironlake_irq_preinstall(dev);
@@ -1691,8 +1696,8 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
1691 } 1696 }
1692 1697
1693 I915_WRITE(HWSTAM, 0xeffe); 1698 I915_WRITE(HWSTAM, 0xeffe);
1694 I915_WRITE(PIPEASTAT, 0); 1699 for_each_pipe(pipe)
1695 I915_WRITE(PIPEBSTAT, 0); 1700 I915_WRITE(PIPESTAT(pipe), 0);
1696 I915_WRITE(IMR, 0xffffffff); 1701 I915_WRITE(IMR, 0xffffffff);
1697 I915_WRITE(IER, 0x0); 1702 I915_WRITE(IER, 0x0);
1698 POSTING_READ(IER); 1703 POSTING_READ(IER);
@@ -1804,6 +1809,7 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
1804void i915_driver_irq_uninstall(struct drm_device * dev) 1809void i915_driver_irq_uninstall(struct drm_device * dev)
1805{ 1810{
1806 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1811 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1812 int pipe;
1807 1813
1808 if (!dev_priv) 1814 if (!dev_priv)
1809 return; 1815 return;
@@ -1821,12 +1827,13 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
1821 } 1827 }
1822 1828
1823 I915_WRITE(HWSTAM, 0xffffffff); 1829 I915_WRITE(HWSTAM, 0xffffffff);
1824 I915_WRITE(PIPEASTAT, 0); 1830 for_each_pipe(pipe)
1825 I915_WRITE(PIPEBSTAT, 0); 1831 I915_WRITE(PIPESTAT(pipe), 0);
1826 I915_WRITE(IMR, 0xffffffff); 1832 I915_WRITE(IMR, 0xffffffff);
1827 I915_WRITE(IER, 0x0); 1833 I915_WRITE(IER, 0x0);
1828 1834
1829 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); 1835 for_each_pipe(pipe)
1830 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); 1836 I915_WRITE(PIPESTAT(pipe),
1837 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
1831 I915_WRITE(IIR, I915_READ(IIR)); 1838 I915_WRITE(IIR, I915_READ(IIR));
1832} 1839}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 15d94c63918c..139d15234ffb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -706,9 +706,9 @@
706#define VGA1_PD_P1_DIV_2 (1 << 13) 706#define VGA1_PD_P1_DIV_2 (1 << 13)
707#define VGA1_PD_P1_SHIFT 8 707#define VGA1_PD_P1_SHIFT 8
708#define VGA1_PD_P1_MASK (0x1f << 8) 708#define VGA1_PD_P1_MASK (0x1f << 8)
709#define DPLL_A 0x06014 709#define _DPLL_A 0x06014
710#define DPLL_B 0x06018 710#define _DPLL_B 0x06018
711#define DPLL(pipe) _PIPE(pipe, DPLL_A, DPLL_B) 711#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
712#define DPLL_VCO_ENABLE (1 << 31) 712#define DPLL_VCO_ENABLE (1 << 31)
713#define DPLL_DVO_HIGH_SPEED (1 << 30) 713#define DPLL_DVO_HIGH_SPEED (1 << 30)
714#define DPLL_SYNCLOCK_ENABLE (1 << 29) 714#define DPLL_SYNCLOCK_ENABLE (1 << 29)
@@ -779,7 +779,7 @@
779#define SDVO_MULTIPLIER_MASK 0x000000ff 779#define SDVO_MULTIPLIER_MASK 0x000000ff
780#define SDVO_MULTIPLIER_SHIFT_HIRES 4 780#define SDVO_MULTIPLIER_SHIFT_HIRES 4
781#define SDVO_MULTIPLIER_SHIFT_VGA 0 781#define SDVO_MULTIPLIER_SHIFT_VGA 0
782#define DPLL_A_MD 0x0601c /* 965+ only */ 782#define _DPLL_A_MD 0x0601c /* 965+ only */
783/* 783/*
784 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 784 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
785 * 785 *
@@ -816,14 +816,14 @@
816 */ 816 */
817#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 817#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
818#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 818#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
819#define DPLL_B_MD 0x06020 /* 965+ only */ 819#define _DPLL_B_MD 0x06020 /* 965+ only */
820#define DPLL_MD(pipe) _PIPE(pipe, DPLL_A_MD, DPLL_B_MD) 820#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
821#define FPA0 0x06040 821#define _FPA0 0x06040
822#define FPA1 0x06044 822#define _FPA1 0x06044
823#define FPB0 0x06048 823#define _FPB0 0x06048
824#define FPB1 0x0604c 824#define _FPB1 0x0604c
825#define FP0(pipe) _PIPE(pipe, FPA0, FPB0) 825#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
826#define FP1(pipe) _PIPE(pipe, FPA1, FPB1) 826#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
827#define FP_N_DIV_MASK 0x003f0000 827#define FP_N_DIV_MASK 0x003f0000
828#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 828#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
829#define FP_N_DIV_SHIFT 16 829#define FP_N_DIV_SHIFT 16
@@ -962,8 +962,9 @@
962 * Palette regs 962 * Palette regs
963 */ 963 */
964 964
965#define PALETTE_A 0x0a000 965#define _PALETTE_A 0x0a000
966#define PALETTE_B 0x0a800 966#define _PALETTE_B 0x0a800
967#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
967 968
968/* MCH MMIO space */ 969/* MCH MMIO space */
969 970
@@ -1267,32 +1268,32 @@
1267 */ 1268 */
1268 1269
1269/* Pipe A timing regs */ 1270/* Pipe A timing regs */
1270#define HTOTAL_A 0x60000 1271#define _HTOTAL_A 0x60000
1271#define HBLANK_A 0x60004 1272#define _HBLANK_A 0x60004
1272#define HSYNC_A 0x60008 1273#define _HSYNC_A 0x60008
1273#define VTOTAL_A 0x6000c 1274#define _VTOTAL_A 0x6000c
1274#define VBLANK_A 0x60010 1275#define _VBLANK_A 0x60010
1275#define VSYNC_A 0x60014 1276#define _VSYNC_A 0x60014
1276#define PIPEASRC 0x6001c 1277#define _PIPEASRC 0x6001c
1277#define BCLRPAT_A 0x60020 1278#define _BCLRPAT_A 0x60020
1278 1279
1279/* Pipe B timing regs */ 1280/* Pipe B timing regs */
1280#define HTOTAL_B 0x61000 1281#define _HTOTAL_B 0x61000
1281#define HBLANK_B 0x61004 1282#define _HBLANK_B 0x61004
1282#define HSYNC_B 0x61008 1283#define _HSYNC_B 0x61008
1283#define VTOTAL_B 0x6100c 1284#define _VTOTAL_B 0x6100c
1284#define VBLANK_B 0x61010 1285#define _VBLANK_B 0x61010
1285#define VSYNC_B 0x61014 1286#define _VSYNC_B 0x61014
1286#define PIPEBSRC 0x6101c 1287#define _PIPEBSRC 0x6101c
1287#define BCLRPAT_B 0x61020 1288#define _BCLRPAT_B 0x61020
1288 1289
1289#define HTOTAL(pipe) _PIPE(pipe, HTOTAL_A, HTOTAL_B) 1290#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1290#define HBLANK(pipe) _PIPE(pipe, HBLANK_A, HBLANK_B) 1291#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1291#define HSYNC(pipe) _PIPE(pipe, HSYNC_A, HSYNC_B) 1292#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1292#define VTOTAL(pipe) _PIPE(pipe, VTOTAL_A, VTOTAL_B) 1293#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1293#define VBLANK(pipe) _PIPE(pipe, VBLANK_A, VBLANK_B) 1294#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1294#define VSYNC(pipe) _PIPE(pipe, VSYNC_A, VSYNC_B) 1295#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1295#define BCLRPAT(pipe) _PIPE(pipe, BCLRPAT_A, BCLRPAT_B) 1296#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1296 1297
1297/* VGA port control */ 1298/* VGA port control */
1298#define ADPA 0x61100 1299#define ADPA 0x61100
@@ -1441,8 +1442,13 @@
1441#define LVDS_PORT_EN (1 << 31) 1442#define LVDS_PORT_EN (1 << 31)
1442/* Selects pipe B for LVDS data. Must be set on pre-965. */ 1443/* Selects pipe B for LVDS data. Must be set on pre-965. */
1443#define LVDS_PIPEB_SELECT (1 << 30) 1444#define LVDS_PIPEB_SELECT (1 << 30)
1445#define LVDS_PIPE_MASK (1 << 30)
1444/* LVDS dithering flag on 965/g4x platform */ 1446/* LVDS dithering flag on 965/g4x platform */
1445#define LVDS_ENABLE_DITHER (1 << 25) 1447#define LVDS_ENABLE_DITHER (1 << 25)
1448/* LVDS sync polarity flags. Set to invert (i.e. negative) */
1449#define LVDS_VSYNC_POLARITY (1 << 21)
1450#define LVDS_HSYNC_POLARITY (1 << 20)
1451
1446/* Enable border for unscaled (or aspect-scaled) display */ 1452/* Enable border for unscaled (or aspect-scaled) display */
1447#define LVDS_BORDER_ENABLE (1 << 15) 1453#define LVDS_BORDER_ENABLE (1 << 15)
1448/* 1454/*
@@ -1476,6 +1482,9 @@
1476#define LVDS_B0B3_POWER_DOWN (0 << 2) 1482#define LVDS_B0B3_POWER_DOWN (0 << 2)
1477#define LVDS_B0B3_POWER_UP (3 << 2) 1483#define LVDS_B0B3_POWER_UP (3 << 2)
1478 1484
1485#define LVDS_PIPE_ENABLED(V, P) \
1486 (((V) & (LVDS_PIPE_MASK | LVDS_PORT_EN)) == ((P) << 30 | LVDS_PORT_EN))
1487
1479/* Video Data Island Packet control */ 1488/* Video Data Island Packet control */
1480#define VIDEO_DIP_DATA 0x61178 1489#define VIDEO_DIP_DATA 0x61178
1481#define VIDEO_DIP_CTL 0x61170 1490#define VIDEO_DIP_CTL 0x61170
@@ -2064,6 +2073,10 @@
2064 2073
2065#define DP_PORT_EN (1 << 31) 2074#define DP_PORT_EN (1 << 31)
2066#define DP_PIPEB_SELECT (1 << 30) 2075#define DP_PIPEB_SELECT (1 << 30)
2076#define DP_PIPE_MASK (1 << 30)
2077
2078#define DP_PIPE_ENABLED(V, P) \
2079 (((V) & (DP_PIPE_MASK | DP_PORT_EN)) == ((P) << 30 | DP_PORT_EN))
2067 2080
2068/* Link training mode - select a suitable mode for each stage */ 2081/* Link training mode - select a suitable mode for each stage */
2069#define DP_LINK_TRAIN_PAT_1 (0 << 28) 2082#define DP_LINK_TRAIN_PAT_1 (0 << 28)
@@ -2206,8 +2219,8 @@
2206 * which is after the LUTs, so we want the bytes for our color format. 2219 * which is after the LUTs, so we want the bytes for our color format.
2207 * For our current usage, this is always 3, one byte for R, G and B. 2220 * For our current usage, this is always 3, one byte for R, G and B.
2208 */ 2221 */
2209#define PIPEA_GMCH_DATA_M 0x70050 2222#define _PIPEA_GMCH_DATA_M 0x70050
2210#define PIPEB_GMCH_DATA_M 0x71050 2223#define _PIPEB_GMCH_DATA_M 0x71050
2211 2224
2212/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2225/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2213#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2226#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
@@ -2215,8 +2228,8 @@
2215 2228
2216#define PIPE_GMCH_DATA_M_MASK (0xffffff) 2229#define PIPE_GMCH_DATA_M_MASK (0xffffff)
2217 2230
2218#define PIPEA_GMCH_DATA_N 0x70054 2231#define _PIPEA_GMCH_DATA_N 0x70054
2219#define PIPEB_GMCH_DATA_N 0x71054 2232#define _PIPEB_GMCH_DATA_N 0x71054
2220#define PIPE_GMCH_DATA_N_MASK (0xffffff) 2233#define PIPE_GMCH_DATA_N_MASK (0xffffff)
2221 2234
2222/* 2235/*
@@ -2230,20 +2243,25 @@
2230 * Attributes and VB-ID. 2243 * Attributes and VB-ID.
2231 */ 2244 */
2232 2245
2233#define PIPEA_DP_LINK_M 0x70060 2246#define _PIPEA_DP_LINK_M 0x70060
2234#define PIPEB_DP_LINK_M 0x71060 2247#define _PIPEB_DP_LINK_M 0x71060
2235#define PIPEA_DP_LINK_M_MASK (0xffffff) 2248#define PIPEA_DP_LINK_M_MASK (0xffffff)
2236 2249
2237#define PIPEA_DP_LINK_N 0x70064 2250#define _PIPEA_DP_LINK_N 0x70064
2238#define PIPEB_DP_LINK_N 0x71064 2251#define _PIPEB_DP_LINK_N 0x71064
2239#define PIPEA_DP_LINK_N_MASK (0xffffff) 2252#define PIPEA_DP_LINK_N_MASK (0xffffff)
2240 2253
2254#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2255#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2256#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2257#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2258
2241/* Display & cursor control */ 2259/* Display & cursor control */
2242 2260
2243/* Pipe A */ 2261/* Pipe A */
2244#define PIPEADSL 0x70000 2262#define _PIPEADSL 0x70000
2245#define DSL_LINEMASK 0x00000fff 2263#define DSL_LINEMASK 0x00000fff
2246#define PIPEACONF 0x70008 2264#define _PIPEACONF 0x70008
2247#define PIPECONF_ENABLE (1<<31) 2265#define PIPECONF_ENABLE (1<<31)
2248#define PIPECONF_DISABLE 0 2266#define PIPECONF_DISABLE 0
2249#define PIPECONF_DOUBLE_WIDE (1<<30) 2267#define PIPECONF_DOUBLE_WIDE (1<<30)
@@ -2269,7 +2287,7 @@
2269#define PIPECONF_DITHER_TYPE_ST1 (1<<2) 2287#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2270#define PIPECONF_DITHER_TYPE_ST2 (2<<2) 2288#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2271#define PIPECONF_DITHER_TYPE_TEMP (3<<2) 2289#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2272#define PIPEASTAT 0x70024 2290#define _PIPEASTAT 0x70024
2273#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 2291#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2274#define PIPE_CRC_ERROR_ENABLE (1UL<<29) 2292#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2275#define PIPE_CRC_DONE_ENABLE (1UL<<28) 2293#define PIPE_CRC_DONE_ENABLE (1UL<<28)
@@ -2305,10 +2323,12 @@
2305#define PIPE_6BPC (2 << 5) 2323#define PIPE_6BPC (2 << 5)
2306#define PIPE_12BPC (3 << 5) 2324#define PIPE_12BPC (3 << 5)
2307 2325
2308#define PIPESRC(pipe) _PIPE(pipe, PIPEASRC, PIPEBSRC) 2326#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2309#define PIPECONF(pipe) _PIPE(pipe, PIPEACONF, PIPEBCONF) 2327#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2310#define PIPEDSL(pipe) _PIPE(pipe, PIPEADSL, PIPEBDSL) 2328#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2311#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, PIPEAFRAMEPIXEL, PIPEBFRAMEPIXEL) 2329#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2330#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2331#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2312 2332
2313#define DSPARB 0x70030 2333#define DSPARB 0x70030
2314#define DSPARB_CSTART_MASK (0x7f << 7) 2334#define DSPARB_CSTART_MASK (0x7f << 7)
@@ -2470,20 +2490,21 @@
2470 * } while (high1 != high2); 2490 * } while (high1 != high2);
2471 * frame = (high1 << 8) | low1; 2491 * frame = (high1 << 8) | low1;
2472 */ 2492 */
2473#define PIPEAFRAMEHIGH 0x70040 2493#define _PIPEAFRAMEHIGH 0x70040
2474#define PIPE_FRAME_HIGH_MASK 0x0000ffff 2494#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2475#define PIPE_FRAME_HIGH_SHIFT 0 2495#define PIPE_FRAME_HIGH_SHIFT 0
2476#define PIPEAFRAMEPIXEL 0x70044 2496#define _PIPEAFRAMEPIXEL 0x70044
2477#define PIPE_FRAME_LOW_MASK 0xff000000 2497#define PIPE_FRAME_LOW_MASK 0xff000000
2478#define PIPE_FRAME_LOW_SHIFT 24 2498#define PIPE_FRAME_LOW_SHIFT 24
2479#define PIPE_PIXEL_MASK 0x00ffffff 2499#define PIPE_PIXEL_MASK 0x00ffffff
2480#define PIPE_PIXEL_SHIFT 0 2500#define PIPE_PIXEL_SHIFT 0
2481/* GM45+ just has to be different */ 2501/* GM45+ just has to be different */
2482#define PIPEA_FRMCOUNT_GM45 0x70040 2502#define _PIPEA_FRMCOUNT_GM45 0x70040
2483#define PIPEA_FLIPCOUNT_GM45 0x70044 2503#define _PIPEA_FLIPCOUNT_GM45 0x70044
2504#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2484 2505
2485/* Cursor A & B regs */ 2506/* Cursor A & B regs */
2486#define CURACNTR 0x70080 2507#define _CURACNTR 0x70080
2487/* Old style CUR*CNTR flags (desktop 8xx) */ 2508/* Old style CUR*CNTR flags (desktop 8xx) */
2488#define CURSOR_ENABLE 0x80000000 2509#define CURSOR_ENABLE 0x80000000
2489#define CURSOR_GAMMA_ENABLE 0x40000000 2510#define CURSOR_GAMMA_ENABLE 0x40000000
@@ -2504,23 +2525,23 @@
2504#define MCURSOR_PIPE_A 0x00 2525#define MCURSOR_PIPE_A 0x00
2505#define MCURSOR_PIPE_B (1 << 28) 2526#define MCURSOR_PIPE_B (1 << 28)
2506#define MCURSOR_GAMMA_ENABLE (1 << 26) 2527#define MCURSOR_GAMMA_ENABLE (1 << 26)
2507#define CURABASE 0x70084 2528#define _CURABASE 0x70084
2508#define CURAPOS 0x70088 2529#define _CURAPOS 0x70088
2509#define CURSOR_POS_MASK 0x007FF 2530#define CURSOR_POS_MASK 0x007FF
2510#define CURSOR_POS_SIGN 0x8000 2531#define CURSOR_POS_SIGN 0x8000
2511#define CURSOR_X_SHIFT 0 2532#define CURSOR_X_SHIFT 0
2512#define CURSOR_Y_SHIFT 16 2533#define CURSOR_Y_SHIFT 16
2513#define CURSIZE 0x700a0 2534#define CURSIZE 0x700a0
2514#define CURBCNTR 0x700c0 2535#define _CURBCNTR 0x700c0
2515#define CURBBASE 0x700c4 2536#define _CURBBASE 0x700c4
2516#define CURBPOS 0x700c8 2537#define _CURBPOS 0x700c8
2517 2538
2518#define CURCNTR(pipe) _PIPE(pipe, CURACNTR, CURBCNTR) 2539#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2519#define CURBASE(pipe) _PIPE(pipe, CURABASE, CURBBASE) 2540#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2520#define CURPOS(pipe) _PIPE(pipe, CURAPOS, CURBPOS) 2541#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2521 2542
2522/* Display A control */ 2543/* Display A control */
2523#define DSPACNTR 0x70180 2544#define _DSPACNTR 0x70180
2524#define DISPLAY_PLANE_ENABLE (1<<31) 2545#define DISPLAY_PLANE_ENABLE (1<<31)
2525#define DISPLAY_PLANE_DISABLE 0 2546#define DISPLAY_PLANE_DISABLE 0
2526#define DISPPLANE_GAMMA_ENABLE (1<<30) 2547#define DISPPLANE_GAMMA_ENABLE (1<<30)
@@ -2534,9 +2555,10 @@
2534#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) 2555#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2535#define DISPPLANE_STEREO_ENABLE (1<<25) 2556#define DISPPLANE_STEREO_ENABLE (1<<25)
2536#define DISPPLANE_STEREO_DISABLE 0 2557#define DISPPLANE_STEREO_DISABLE 0
2537#define DISPPLANE_SEL_PIPE_MASK (1<<24) 2558#define DISPPLANE_SEL_PIPE_SHIFT 24
2559#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
2538#define DISPPLANE_SEL_PIPE_A 0 2560#define DISPPLANE_SEL_PIPE_A 0
2539#define DISPPLANE_SEL_PIPE_B (1<<24) 2561#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
2540#define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2562#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2541#define DISPPLANE_SRC_KEY_DISABLE 0 2563#define DISPPLANE_SRC_KEY_DISABLE 0
2542#define DISPPLANE_LINE_DOUBLE (1<<20) 2564#define DISPPLANE_LINE_DOUBLE (1<<20)
@@ -2545,20 +2567,20 @@
2545#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2567#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2546#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 2568#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2547#define DISPPLANE_TILED (1<<10) 2569#define DISPPLANE_TILED (1<<10)
2548#define DSPAADDR 0x70184 2570#define _DSPAADDR 0x70184
2549#define DSPASTRIDE 0x70188 2571#define _DSPASTRIDE 0x70188
2550#define DSPAPOS 0x7018C /* reserved */ 2572#define _DSPAPOS 0x7018C /* reserved */
2551#define DSPASIZE 0x70190 2573#define _DSPASIZE 0x70190
2552#define DSPASURF 0x7019C /* 965+ only */ 2574#define _DSPASURF 0x7019C /* 965+ only */
2553#define DSPATILEOFF 0x701A4 /* 965+ only */ 2575#define _DSPATILEOFF 0x701A4 /* 965+ only */
2554 2576
2555#define DSPCNTR(plane) _PIPE(plane, DSPACNTR, DSPBCNTR) 2577#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2556#define DSPADDR(plane) _PIPE(plane, DSPAADDR, DSPBADDR) 2578#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2557#define DSPSTRIDE(plane) _PIPE(plane, DSPASTRIDE, DSPBSTRIDE) 2579#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2558#define DSPPOS(plane) _PIPE(plane, DSPAPOS, DSPBPOS) 2580#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2559#define DSPSIZE(plane) _PIPE(plane, DSPASIZE, DSPBSIZE) 2581#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2560#define DSPSURF(plane) _PIPE(plane, DSPASURF, DSPBSURF) 2582#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2561#define DSPTILEOFF(plane) _PIPE(plane, DSPATILEOFF, DSPBTILEOFF) 2583#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
2562 2584
2563/* VBIOS flags */ 2585/* VBIOS flags */
2564#define SWF00 0x71410 2586#define SWF00 0x71410
@@ -2576,27 +2598,27 @@
2576#define SWF32 0x7241c 2598#define SWF32 0x7241c
2577 2599
2578/* Pipe B */ 2600/* Pipe B */
2579#define PIPEBDSL 0x71000 2601#define _PIPEBDSL 0x71000
2580#define PIPEBCONF 0x71008 2602#define _PIPEBCONF 0x71008
2581#define PIPEBSTAT 0x71024 2603#define _PIPEBSTAT 0x71024
2582#define PIPEBFRAMEHIGH 0x71040 2604#define _PIPEBFRAMEHIGH 0x71040
2583#define PIPEBFRAMEPIXEL 0x71044 2605#define _PIPEBFRAMEPIXEL 0x71044
2584#define PIPEB_FRMCOUNT_GM45 0x71040 2606#define _PIPEB_FRMCOUNT_GM45 0x71040
2585#define PIPEB_FLIPCOUNT_GM45 0x71044 2607#define _PIPEB_FLIPCOUNT_GM45 0x71044
2586 2608
2587 2609
2588/* Display B control */ 2610/* Display B control */
2589#define DSPBCNTR 0x71180 2611#define _DSPBCNTR 0x71180
2590#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2612#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2591#define DISPPLANE_ALPHA_TRANS_DISABLE 0 2613#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2592#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2614#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2593#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2615#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2594#define DSPBADDR 0x71184 2616#define _DSPBADDR 0x71184
2595#define DSPBSTRIDE 0x71188 2617#define _DSPBSTRIDE 0x71188
2596#define DSPBPOS 0x7118C 2618#define _DSPBPOS 0x7118C
2597#define DSPBSIZE 0x71190 2619#define _DSPBSIZE 0x71190
2598#define DSPBSURF 0x7119C 2620#define _DSPBSURF 0x7119C
2599#define DSPBTILEOFF 0x711A4 2621#define _DSPBTILEOFF 0x711A4
2600 2622
2601/* VBIOS regs */ 2623/* VBIOS regs */
2602#define VGACNTRL 0x71400 2624#define VGACNTRL 0x71400
@@ -2650,68 +2672,80 @@
2650#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 2672#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2651 2673
2652 2674
2653#define PIPEA_DATA_M1 0x60030 2675#define _PIPEA_DATA_M1 0x60030
2654#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 2676#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2655#define TU_SIZE_MASK 0x7e000000 2677#define TU_SIZE_MASK 0x7e000000
2656#define PIPE_DATA_M1_OFFSET 0 2678#define PIPE_DATA_M1_OFFSET 0
2657#define PIPEA_DATA_N1 0x60034 2679#define _PIPEA_DATA_N1 0x60034
2658#define PIPE_DATA_N1_OFFSET 0 2680#define PIPE_DATA_N1_OFFSET 0
2659 2681
2660#define PIPEA_DATA_M2 0x60038 2682#define _PIPEA_DATA_M2 0x60038
2661#define PIPE_DATA_M2_OFFSET 0 2683#define PIPE_DATA_M2_OFFSET 0
2662#define PIPEA_DATA_N2 0x6003c 2684#define _PIPEA_DATA_N2 0x6003c
2663#define PIPE_DATA_N2_OFFSET 0 2685#define PIPE_DATA_N2_OFFSET 0
2664 2686
2665#define PIPEA_LINK_M1 0x60040 2687#define _PIPEA_LINK_M1 0x60040
2666#define PIPE_LINK_M1_OFFSET 0 2688#define PIPE_LINK_M1_OFFSET 0
2667#define PIPEA_LINK_N1 0x60044 2689#define _PIPEA_LINK_N1 0x60044
2668#define PIPE_LINK_N1_OFFSET 0 2690#define PIPE_LINK_N1_OFFSET 0
2669 2691
2670#define PIPEA_LINK_M2 0x60048 2692#define _PIPEA_LINK_M2 0x60048
2671#define PIPE_LINK_M2_OFFSET 0 2693#define PIPE_LINK_M2_OFFSET 0
2672#define PIPEA_LINK_N2 0x6004c 2694#define _PIPEA_LINK_N2 0x6004c
2673#define PIPE_LINK_N2_OFFSET 0 2695#define PIPE_LINK_N2_OFFSET 0
2674 2696
2675/* PIPEB timing regs are same start from 0x61000 */ 2697/* PIPEB timing regs are same start from 0x61000 */
2676 2698
2677#define PIPEB_DATA_M1 0x61030 2699#define _PIPEB_DATA_M1 0x61030
2678#define PIPEB_DATA_N1 0x61034 2700#define _PIPEB_DATA_N1 0x61034
2679 2701
2680#define PIPEB_DATA_M2 0x61038 2702#define _PIPEB_DATA_M2 0x61038
2681#define PIPEB_DATA_N2 0x6103c 2703#define _PIPEB_DATA_N2 0x6103c
2682 2704
2683#define PIPEB_LINK_M1 0x61040 2705#define _PIPEB_LINK_M1 0x61040
2684#define PIPEB_LINK_N1 0x61044 2706#define _PIPEB_LINK_N1 0x61044
2685 2707
2686#define PIPEB_LINK_M2 0x61048 2708#define _PIPEB_LINK_M2 0x61048
2687#define PIPEB_LINK_N2 0x6104c 2709#define _PIPEB_LINK_N2 0x6104c
2688 2710
2689#define PIPE_DATA_M1(pipe) _PIPE(pipe, PIPEA_DATA_M1, PIPEB_DATA_M1) 2711#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
2690#define PIPE_DATA_N1(pipe) _PIPE(pipe, PIPEA_DATA_N1, PIPEB_DATA_N1) 2712#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
2691#define PIPE_DATA_M2(pipe) _PIPE(pipe, PIPEA_DATA_M2, PIPEB_DATA_M2) 2713#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
2692#define PIPE_DATA_N2(pipe) _PIPE(pipe, PIPEA_DATA_N2, PIPEB_DATA_N2) 2714#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
2693#define PIPE_LINK_M1(pipe) _PIPE(pipe, PIPEA_LINK_M1, PIPEB_LINK_M1) 2715#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
2694#define PIPE_LINK_N1(pipe) _PIPE(pipe, PIPEA_LINK_N1, PIPEB_LINK_N1) 2716#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
2695#define PIPE_LINK_M2(pipe) _PIPE(pipe, PIPEA_LINK_M2, PIPEB_LINK_M2) 2717#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
2696#define PIPE_LINK_N2(pipe) _PIPE(pipe, PIPEA_LINK_N2, PIPEB_LINK_N2) 2718#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
2697 2719
2698/* CPU panel fitter */ 2720/* CPU panel fitter */
2699#define PFA_CTL_1 0x68080 2721/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2700#define PFB_CTL_1 0x68880 2722#define _PFA_CTL_1 0x68080
2723#define _PFB_CTL_1 0x68880
2701#define PF_ENABLE (1<<31) 2724#define PF_ENABLE (1<<31)
2702#define PF_FILTER_MASK (3<<23) 2725#define PF_FILTER_MASK (3<<23)
2703#define PF_FILTER_PROGRAMMED (0<<23) 2726#define PF_FILTER_PROGRAMMED (0<<23)
2704#define PF_FILTER_MED_3x3 (1<<23) 2727#define PF_FILTER_MED_3x3 (1<<23)
2705#define PF_FILTER_EDGE_ENHANCE (2<<23) 2728#define PF_FILTER_EDGE_ENHANCE (2<<23)
2706#define PF_FILTER_EDGE_SOFTEN (3<<23) 2729#define PF_FILTER_EDGE_SOFTEN (3<<23)
2707#define PFA_WIN_SZ 0x68074 2730#define _PFA_WIN_SZ 0x68074
2708#define PFB_WIN_SZ 0x68874 2731#define _PFB_WIN_SZ 0x68874
2709#define PFA_WIN_POS 0x68070 2732#define _PFA_WIN_POS 0x68070
2710#define PFB_WIN_POS 0x68870 2733#define _PFB_WIN_POS 0x68870
2734#define _PFA_VSCALE 0x68084
2735#define _PFB_VSCALE 0x68884
2736#define _PFA_HSCALE 0x68090
2737#define _PFB_HSCALE 0x68890
2738
2739#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
2740#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
2741#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
2742#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
2743#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2711 2744
2712/* legacy palette */ 2745/* legacy palette */
2713#define LGC_PALETTE_A 0x4a000 2746#define _LGC_PALETTE_A 0x4a000
2714#define LGC_PALETTE_B 0x4a800 2747#define _LGC_PALETTE_B 0x4a800
2748#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
2715 2749
2716/* interrupts */ 2750/* interrupts */
2717#define DE_MASTER_IRQ_CONTROL (1 << 31) 2751#define DE_MASTER_IRQ_CONTROL (1 << 31)
@@ -2877,17 +2911,17 @@
2877#define PCH_GMBUS4 0xc5110 2911#define PCH_GMBUS4 0xc5110
2878#define PCH_GMBUS5 0xc5120 2912#define PCH_GMBUS5 0xc5120
2879 2913
2880#define PCH_DPLL_A 0xc6014 2914#define _PCH_DPLL_A 0xc6014
2881#define PCH_DPLL_B 0xc6018 2915#define _PCH_DPLL_B 0xc6018
2882#define PCH_DPLL(pipe) _PIPE(pipe, PCH_DPLL_A, PCH_DPLL_B) 2916#define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)
2883 2917
2884#define PCH_FPA0 0xc6040 2918#define _PCH_FPA0 0xc6040
2885#define FP_CB_TUNE (0x3<<22) 2919#define FP_CB_TUNE (0x3<<22)
2886#define PCH_FPA1 0xc6044 2920#define _PCH_FPA1 0xc6044
2887#define PCH_FPB0 0xc6048 2921#define _PCH_FPB0 0xc6048
2888#define PCH_FPB1 0xc604c 2922#define _PCH_FPB1 0xc604c
2889#define PCH_FP0(pipe) _PIPE(pipe, PCH_FPA0, PCH_FPB0) 2923#define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)
2890#define PCH_FP1(pipe) _PIPE(pipe, PCH_FPA1, PCH_FPB1) 2924#define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)
2891 2925
2892#define PCH_DPLL_TEST 0xc606c 2926#define PCH_DPLL_TEST 0xc606c
2893 2927
@@ -2906,6 +2940,7 @@
2906#define DREF_NONSPREAD_SOURCE_MASK (3<<9) 2940#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2907#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 2941#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2908#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 2942#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2943#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
2909#define DREF_SSC4_DOWNSPREAD (0<<6) 2944#define DREF_SSC4_DOWNSPREAD (0<<6)
2910#define DREF_SSC4_CENTERSPREAD (1<<6) 2945#define DREF_SSC4_CENTERSPREAD (1<<6)
2911#define DREF_SSC1_DISABLE (0<<1) 2946#define DREF_SSC1_DISABLE (0<<1)
@@ -2938,60 +2973,69 @@
2938 2973
2939/* transcoder */ 2974/* transcoder */
2940 2975
2941#define TRANS_HTOTAL_A 0xe0000 2976#define _TRANS_HTOTAL_A 0xe0000
2942#define TRANS_HTOTAL_SHIFT 16 2977#define TRANS_HTOTAL_SHIFT 16
2943#define TRANS_HACTIVE_SHIFT 0 2978#define TRANS_HACTIVE_SHIFT 0
2944#define TRANS_HBLANK_A 0xe0004 2979#define _TRANS_HBLANK_A 0xe0004
2945#define TRANS_HBLANK_END_SHIFT 16 2980#define TRANS_HBLANK_END_SHIFT 16
2946#define TRANS_HBLANK_START_SHIFT 0 2981#define TRANS_HBLANK_START_SHIFT 0
2947#define TRANS_HSYNC_A 0xe0008 2982#define _TRANS_HSYNC_A 0xe0008
2948#define TRANS_HSYNC_END_SHIFT 16 2983#define TRANS_HSYNC_END_SHIFT 16
2949#define TRANS_HSYNC_START_SHIFT 0 2984#define TRANS_HSYNC_START_SHIFT 0
2950#define TRANS_VTOTAL_A 0xe000c 2985#define _TRANS_VTOTAL_A 0xe000c
2951#define TRANS_VTOTAL_SHIFT 16 2986#define TRANS_VTOTAL_SHIFT 16
2952#define TRANS_VACTIVE_SHIFT 0 2987#define TRANS_VACTIVE_SHIFT 0
2953#define TRANS_VBLANK_A 0xe0010 2988#define _TRANS_VBLANK_A 0xe0010
2954#define TRANS_VBLANK_END_SHIFT 16 2989#define TRANS_VBLANK_END_SHIFT 16
2955#define TRANS_VBLANK_START_SHIFT 0 2990#define TRANS_VBLANK_START_SHIFT 0
2956#define TRANS_VSYNC_A 0xe0014 2991#define _TRANS_VSYNC_A 0xe0014
2957#define TRANS_VSYNC_END_SHIFT 16 2992#define TRANS_VSYNC_END_SHIFT 16
2958#define TRANS_VSYNC_START_SHIFT 0 2993#define TRANS_VSYNC_START_SHIFT 0
2959 2994
2960#define TRANSA_DATA_M1 0xe0030 2995#define _TRANSA_DATA_M1 0xe0030
2961#define TRANSA_DATA_N1 0xe0034 2996#define _TRANSA_DATA_N1 0xe0034
2962#define TRANSA_DATA_M2 0xe0038 2997#define _TRANSA_DATA_M2 0xe0038
2963#define TRANSA_DATA_N2 0xe003c 2998#define _TRANSA_DATA_N2 0xe003c
2964#define TRANSA_DP_LINK_M1 0xe0040 2999#define _TRANSA_DP_LINK_M1 0xe0040
2965#define TRANSA_DP_LINK_N1 0xe0044 3000#define _TRANSA_DP_LINK_N1 0xe0044
2966#define TRANSA_DP_LINK_M2 0xe0048 3001#define _TRANSA_DP_LINK_M2 0xe0048
2967#define TRANSA_DP_LINK_N2 0xe004c 3002#define _TRANSA_DP_LINK_N2 0xe004c
2968 3003
2969#define TRANS_HTOTAL_B 0xe1000 3004#define _TRANS_HTOTAL_B 0xe1000
2970#define TRANS_HBLANK_B 0xe1004 3005#define _TRANS_HBLANK_B 0xe1004
2971#define TRANS_HSYNC_B 0xe1008 3006#define _TRANS_HSYNC_B 0xe1008
2972#define TRANS_VTOTAL_B 0xe100c 3007#define _TRANS_VTOTAL_B 0xe100c
2973#define TRANS_VBLANK_B 0xe1010 3008#define _TRANS_VBLANK_B 0xe1010
2974#define TRANS_VSYNC_B 0xe1014 3009#define _TRANS_VSYNC_B 0xe1014
2975 3010
2976#define TRANS_HTOTAL(pipe) _PIPE(pipe, TRANS_HTOTAL_A, TRANS_HTOTAL_B) 3011#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
2977#define TRANS_HBLANK(pipe) _PIPE(pipe, TRANS_HBLANK_A, TRANS_HBLANK_B) 3012#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
2978#define TRANS_HSYNC(pipe) _PIPE(pipe, TRANS_HSYNC_A, TRANS_HSYNC_B) 3013#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
2979#define TRANS_VTOTAL(pipe) _PIPE(pipe, TRANS_VTOTAL_A, TRANS_VTOTAL_B) 3014#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
2980#define TRANS_VBLANK(pipe) _PIPE(pipe, TRANS_VBLANK_A, TRANS_VBLANK_B) 3015#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
2981#define TRANS_VSYNC(pipe) _PIPE(pipe, TRANS_VSYNC_A, TRANS_VSYNC_B) 3016#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
2982 3017
2983#define TRANSB_DATA_M1 0xe1030 3018#define _TRANSB_DATA_M1 0xe1030
2984#define TRANSB_DATA_N1 0xe1034 3019#define _TRANSB_DATA_N1 0xe1034
2985#define TRANSB_DATA_M2 0xe1038 3020#define _TRANSB_DATA_M2 0xe1038
2986#define TRANSB_DATA_N2 0xe103c 3021#define _TRANSB_DATA_N2 0xe103c
2987#define TRANSB_DP_LINK_M1 0xe1040 3022#define _TRANSB_DP_LINK_M1 0xe1040
2988#define TRANSB_DP_LINK_N1 0xe1044 3023#define _TRANSB_DP_LINK_N1 0xe1044
2989#define TRANSB_DP_LINK_M2 0xe1048 3024#define _TRANSB_DP_LINK_M2 0xe1048
2990#define TRANSB_DP_LINK_N2 0xe104c 3025#define _TRANSB_DP_LINK_N2 0xe104c
2991 3026
2992#define TRANSACONF 0xf0008 3027#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
2993#define TRANSBCONF 0xf1008 3028#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
2994#define TRANSCONF(plane) _PIPE(plane, TRANSACONF, TRANSBCONF) 3029#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3030#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3031#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3032#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3033#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3034#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3035
3036#define _TRANSACONF 0xf0008
3037#define _TRANSBCONF 0xf1008
3038#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
2995#define TRANS_DISABLE (0<<31) 3039#define TRANS_DISABLE (0<<31)
2996#define TRANS_ENABLE (1<<31) 3040#define TRANS_ENABLE (1<<31)
2997#define TRANS_STATE_MASK (1<<30) 3041#define TRANS_STATE_MASK (1<<30)
@@ -3009,18 +3053,19 @@
3009#define TRANS_6BPC (2<<5) 3053#define TRANS_6BPC (2<<5)
3010#define TRANS_12BPC (3<<5) 3054#define TRANS_12BPC (3<<5)
3011 3055
3012#define FDI_RXA_CHICKEN 0xc200c 3056#define _FDI_RXA_CHICKEN 0xc200c
3013#define FDI_RXB_CHICKEN 0xc2010 3057#define _FDI_RXB_CHICKEN 0xc2010
3014#define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) 3058#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3015#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN) 3059#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3060#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3016 3061
3017#define SOUTH_DSPCLK_GATE_D 0xc2020 3062#define SOUTH_DSPCLK_GATE_D 0xc2020
3018#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 3063#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3019 3064
3020/* CPU: FDI_TX */ 3065/* CPU: FDI_TX */
3021#define FDI_TXA_CTL 0x60100 3066#define _FDI_TXA_CTL 0x60100
3022#define FDI_TXB_CTL 0x61100 3067#define _FDI_TXB_CTL 0x61100
3023#define FDI_TX_CTL(pipe) _PIPE(pipe, FDI_TXA_CTL, FDI_TXB_CTL) 3068#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3024#define FDI_TX_DISABLE (0<<31) 3069#define FDI_TX_DISABLE (0<<31)
3025#define FDI_TX_ENABLE (1<<31) 3070#define FDI_TX_ENABLE (1<<31)
3026#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 3071#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
@@ -3060,9 +3105,9 @@
3060#define FDI_SCRAMBLING_DISABLE (1<<7) 3105#define FDI_SCRAMBLING_DISABLE (1<<7)
3061 3106
3062/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 3107/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3063#define FDI_RXA_CTL 0xf000c 3108#define _FDI_RXA_CTL 0xf000c
3064#define FDI_RXB_CTL 0xf100c 3109#define _FDI_RXB_CTL 0xf100c
3065#define FDI_RX_CTL(pipe) _PIPE(pipe, FDI_RXA_CTL, FDI_RXB_CTL) 3110#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3066#define FDI_RX_ENABLE (1<<31) 3111#define FDI_RX_ENABLE (1<<31)
3067/* train, dp width same as FDI_TX */ 3112/* train, dp width same as FDI_TX */
3068#define FDI_DP_PORT_WIDTH_X8 (7<<19) 3113#define FDI_DP_PORT_WIDTH_X8 (7<<19)
@@ -3087,15 +3132,15 @@
3087#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 3132#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3088#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 3133#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3089 3134
3090#define FDI_RXA_MISC 0xf0010 3135#define _FDI_RXA_MISC 0xf0010
3091#define FDI_RXB_MISC 0xf1010 3136#define _FDI_RXB_MISC 0xf1010
3092#define FDI_RXA_TUSIZE1 0xf0030 3137#define _FDI_RXA_TUSIZE1 0xf0030
3093#define FDI_RXA_TUSIZE2 0xf0038 3138#define _FDI_RXA_TUSIZE2 0xf0038
3094#define FDI_RXB_TUSIZE1 0xf1030 3139#define _FDI_RXB_TUSIZE1 0xf1030
3095#define FDI_RXB_TUSIZE2 0xf1038 3140#define _FDI_RXB_TUSIZE2 0xf1038
3096#define FDI_RX_MISC(pipe) _PIPE(pipe, FDI_RXA_MISC, FDI_RXB_MISC) 3141#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3097#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, FDI_RXA_TUSIZE1, FDI_RXB_TUSIZE1) 3142#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3098#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, FDI_RXA_TUSIZE2, FDI_RXB_TUSIZE2) 3143#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3099 3144
3100/* FDI_RX interrupt register format */ 3145/* FDI_RX interrupt register format */
3101#define FDI_RX_INTER_LANE_ALIGN (1<<10) 3146#define FDI_RX_INTER_LANE_ALIGN (1<<10)
@@ -3110,12 +3155,12 @@
3110#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 3155#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3111#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 3156#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3112 3157
3113#define FDI_RXA_IIR 0xf0014 3158#define _FDI_RXA_IIR 0xf0014
3114#define FDI_RXA_IMR 0xf0018 3159#define _FDI_RXA_IMR 0xf0018
3115#define FDI_RXB_IIR 0xf1014 3160#define _FDI_RXB_IIR 0xf1014
3116#define FDI_RXB_IMR 0xf1018 3161#define _FDI_RXB_IMR 0xf1018
3117#define FDI_RX_IIR(pipe) _PIPE(pipe, FDI_RXA_IIR, FDI_RXB_IIR) 3162#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3118#define FDI_RX_IMR(pipe) _PIPE(pipe, FDI_RXA_IMR, FDI_RXB_IMR) 3163#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3119 3164
3120#define FDI_PLL_CTL_1 0xfe000 3165#define FDI_PLL_CTL_1 0xfe000
3121#define FDI_PLL_CTL_2 0xfe004 3166#define FDI_PLL_CTL_2 0xfe004
@@ -3145,11 +3190,15 @@
3145#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3190#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3146#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3191#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3147 3192
3193#define ADPA_PIPE_ENABLED(V, P) \
3194 (((V) & (ADPA_TRANS_SELECT_MASK | ADPA_DAC_ENABLE)) == ((P) << 30 | ADPA_DAC_ENABLE))
3195
3148/* or SDVOB */ 3196/* or SDVOB */
3149#define HDMIB 0xe1140 3197#define HDMIB 0xe1140
3150#define PORT_ENABLE (1 << 31) 3198#define PORT_ENABLE (1 << 31)
3151#define TRANSCODER_A (0) 3199#define TRANSCODER_A (0)
3152#define TRANSCODER_B (1 << 30) 3200#define TRANSCODER_B (1 << 30)
3201#define TRANSCODER_MASK (1 << 30)
3153#define COLOR_FORMAT_8bpc (0) 3202#define COLOR_FORMAT_8bpc (0)
3154#define COLOR_FORMAT_12bpc (3 << 26) 3203#define COLOR_FORMAT_12bpc (3 << 26)
3155#define SDVOB_HOTPLUG_ENABLE (1 << 23) 3204#define SDVOB_HOTPLUG_ENABLE (1 << 23)
@@ -3165,6 +3214,9 @@
3165#define HSYNC_ACTIVE_HIGH (1 << 3) 3214#define HSYNC_ACTIVE_HIGH (1 << 3)
3166#define PORT_DETECTED (1 << 2) 3215#define PORT_DETECTED (1 << 2)
3167 3216
3217#define HDMI_PIPE_ENABLED(V, P) \
3218 (((V) & (TRANSCODER_MASK | PORT_ENABLE)) == ((P) << 30 | PORT_ENABLE))
3219
3168/* PCH SDVOB multiplex with HDMIB */ 3220/* PCH SDVOB multiplex with HDMIB */
3169#define PCH_SDVOB HDMIB 3221#define PCH_SDVOB HDMIB
3170 3222
@@ -3240,6 +3292,7 @@
3240#define TRANS_DP_PORT_SEL_B (0<<29) 3292#define TRANS_DP_PORT_SEL_B (0<<29)
3241#define TRANS_DP_PORT_SEL_C (1<<29) 3293#define TRANS_DP_PORT_SEL_C (1<<29)
3242#define TRANS_DP_PORT_SEL_D (2<<29) 3294#define TRANS_DP_PORT_SEL_D (2<<29)
3295#define TRANS_DP_PORT_SEL_NONE (3<<29)
3243#define TRANS_DP_PORT_SEL_MASK (3<<29) 3296#define TRANS_DP_PORT_SEL_MASK (3<<29)
3244#define TRANS_DP_AUDIO_ONLY (1<<26) 3297#define TRANS_DP_AUDIO_ONLY (1<<26)
3245#define TRANS_DP_ENH_FRAMING (1<<18) 3298#define TRANS_DP_ENH_FRAMING (1<<18)
@@ -3288,15 +3341,28 @@
3288#define GEN6_RP_DOWN_TIMEOUT 0xA010 3341#define GEN6_RP_DOWN_TIMEOUT 0xA010
3289#define GEN6_RP_INTERRUPT_LIMITS 0xA014 3342#define GEN6_RP_INTERRUPT_LIMITS 0xA014
3290#define GEN6_RPSTAT1 0xA01C 3343#define GEN6_RPSTAT1 0xA01C
3344#define GEN6_CAGF_SHIFT 8
3345#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
3291#define GEN6_RP_CONTROL 0xA024 3346#define GEN6_RP_CONTROL 0xA024
3292#define GEN6_RP_MEDIA_TURBO (1<<11) 3347#define GEN6_RP_MEDIA_TURBO (1<<11)
3293#define GEN6_RP_USE_NORMAL_FREQ (1<<9) 3348#define GEN6_RP_USE_NORMAL_FREQ (1<<9)
3294#define GEN6_RP_MEDIA_IS_GFX (1<<8) 3349#define GEN6_RP_MEDIA_IS_GFX (1<<8)
3295#define GEN6_RP_ENABLE (1<<7) 3350#define GEN6_RP_ENABLE (1<<7)
3296#define GEN6_RP_UP_BUSY_MAX (0x2<<3) 3351#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
3297#define GEN6_RP_DOWN_BUSY_MIN (0x2<<0) 3352#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
3353#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
3354#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
3298#define GEN6_RP_UP_THRESHOLD 0xA02C 3355#define GEN6_RP_UP_THRESHOLD 0xA02C
3299#define GEN6_RP_DOWN_THRESHOLD 0xA030 3356#define GEN6_RP_DOWN_THRESHOLD 0xA030
3357#define GEN6_RP_CUR_UP_EI 0xA050
3358#define GEN6_CURICONT_MASK 0xffffff
3359#define GEN6_RP_CUR_UP 0xA054
3360#define GEN6_CURBSYTAVG_MASK 0xffffff
3361#define GEN6_RP_PREV_UP 0xA058
3362#define GEN6_RP_CUR_DOWN_EI 0xA05C
3363#define GEN6_CURIAVG_MASK 0xffffff
3364#define GEN6_RP_CUR_DOWN 0xA060
3365#define GEN6_RP_PREV_DOWN 0xA064
3300#define GEN6_RP_UP_EI 0xA068 3366#define GEN6_RP_UP_EI 0xA068
3301#define GEN6_RP_DOWN_EI 0xA06C 3367#define GEN6_RP_DOWN_EI 0xA06C
3302#define GEN6_RP_IDLE_HYSTERSIS 0xA070 3368#define GEN6_RP_IDLE_HYSTERSIS 0xA070
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 0521ecf26017..da474153a0a2 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -34,11 +34,10 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
34 struct drm_i915_private *dev_priv = dev->dev_private; 34 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg; 35 u32 dpll_reg;
36 36
37 if (HAS_PCH_SPLIT(dev)) { 37 if (HAS_PCH_SPLIT(dev))
38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B; 38 dpll_reg = (pipe == PIPE_A) ? _PCH_DPLL_A : _PCH_DPLL_B;
39 } else { 39 else
40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B; 40 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
41 }
42 41
43 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE); 42 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
44} 43}
@@ -46,7 +45,7 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
46static void i915_save_palette(struct drm_device *dev, enum pipe pipe) 45static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
47{ 46{
48 struct drm_i915_private *dev_priv = dev->dev_private; 47 struct drm_i915_private *dev_priv = dev->dev_private;
49 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 48 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
50 u32 *array; 49 u32 *array;
51 int i; 50 int i;
52 51
@@ -54,7 +53,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
54 return; 53 return;
55 54
56 if (HAS_PCH_SPLIT(dev)) 55 if (HAS_PCH_SPLIT(dev))
57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 56 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
58 57
59 if (pipe == PIPE_A) 58 if (pipe == PIPE_A)
60 array = dev_priv->save_palette_a; 59 array = dev_priv->save_palette_a;
@@ -68,7 +67,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
68static void i915_restore_palette(struct drm_device *dev, enum pipe pipe) 67static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
69{ 68{
70 struct drm_i915_private *dev_priv = dev->dev_private; 69 struct drm_i915_private *dev_priv = dev->dev_private;
71 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 70 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
72 u32 *array; 71 u32 *array;
73 int i; 72 int i;
74 73
@@ -76,7 +75,7 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
76 return; 75 return;
77 76
78 if (HAS_PCH_SPLIT(dev)) 77 if (HAS_PCH_SPLIT(dev))
79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 78 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
80 79
81 if (pipe == PIPE_A) 80 if (pipe == PIPE_A)
82 array = dev_priv->save_palette_a; 81 array = dev_priv->save_palette_a;
@@ -241,12 +240,12 @@ static void i915_save_modeset_reg(struct drm_device *dev)
241 return; 240 return;
242 241
243 /* Cursor state */ 242 /* Cursor state */
244 dev_priv->saveCURACNTR = I915_READ(CURACNTR); 243 dev_priv->saveCURACNTR = I915_READ(_CURACNTR);
245 dev_priv->saveCURAPOS = I915_READ(CURAPOS); 244 dev_priv->saveCURAPOS = I915_READ(_CURAPOS);
246 dev_priv->saveCURABASE = I915_READ(CURABASE); 245 dev_priv->saveCURABASE = I915_READ(_CURABASE);
247 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR); 246 dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR);
248 dev_priv->saveCURBPOS = I915_READ(CURBPOS); 247 dev_priv->saveCURBPOS = I915_READ(_CURBPOS);
249 dev_priv->saveCURBBASE = I915_READ(CURBBASE); 248 dev_priv->saveCURBBASE = I915_READ(_CURBBASE);
250 if (IS_GEN2(dev)) 249 if (IS_GEN2(dev))
251 dev_priv->saveCURSIZE = I915_READ(CURSIZE); 250 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
252 251
@@ -256,118 +255,118 @@ static void i915_save_modeset_reg(struct drm_device *dev)
256 } 255 }
257 256
258 /* Pipe & plane A info */ 257 /* Pipe & plane A info */
259 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 258 dev_priv->savePIPEACONF = I915_READ(_PIPEACONF);
260 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 259 dev_priv->savePIPEASRC = I915_READ(_PIPEASRC);
261 if (HAS_PCH_SPLIT(dev)) { 260 if (HAS_PCH_SPLIT(dev)) {
262 dev_priv->saveFPA0 = I915_READ(PCH_FPA0); 261 dev_priv->saveFPA0 = I915_READ(_PCH_FPA0);
263 dev_priv->saveFPA1 = I915_READ(PCH_FPA1); 262 dev_priv->saveFPA1 = I915_READ(_PCH_FPA1);
264 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A); 263 dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A);
265 } else { 264 } else {
266 dev_priv->saveFPA0 = I915_READ(FPA0); 265 dev_priv->saveFPA0 = I915_READ(_FPA0);
267 dev_priv->saveFPA1 = I915_READ(FPA1); 266 dev_priv->saveFPA1 = I915_READ(_FPA1);
268 dev_priv->saveDPLL_A = I915_READ(DPLL_A); 267 dev_priv->saveDPLL_A = I915_READ(_DPLL_A);
269 } 268 }
270 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) 269 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
271 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 270 dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
272 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 271 dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A);
273 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); 272 dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A);
274 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A); 273 dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A);
275 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 274 dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A);
276 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 275 dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A);
277 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 276 dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A);
278 if (!HAS_PCH_SPLIT(dev)) 277 if (!HAS_PCH_SPLIT(dev))
279 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 278 dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
280 279
281 if (HAS_PCH_SPLIT(dev)) { 280 if (HAS_PCH_SPLIT(dev)) {
282 dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1); 281 dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
283 dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1); 282 dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
284 dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1); 283 dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
285 dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1); 284 dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
286 285
287 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL); 286 dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
288 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL); 287 dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
289 288
290 dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1); 289 dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
291 dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ); 290 dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
292 dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS); 291 dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
293 292
294 dev_priv->saveTRANSACONF = I915_READ(TRANSACONF); 293 dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF);
295 dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A); 294 dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
296 dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A); 295 dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
297 dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A); 296 dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
298 dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A); 297 dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
299 dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A); 298 dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
300 dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A); 299 dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
301 } 300 }
302 301
303 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR); 302 dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR);
304 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); 303 dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
305 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE); 304 dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE);
306 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS); 305 dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS);
307 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR); 306 dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR);
308 if (INTEL_INFO(dev)->gen >= 4) { 307 if (INTEL_INFO(dev)->gen >= 4) {
309 dev_priv->saveDSPASURF = I915_READ(DSPASURF); 308 dev_priv->saveDSPASURF = I915_READ(_DSPASURF);
310 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); 309 dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
311 } 310 }
312 i915_save_palette(dev, PIPE_A); 311 i915_save_palette(dev, PIPE_A);
313 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT); 312 dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT);
314 313
315 /* Pipe & plane B info */ 314 /* Pipe & plane B info */
316 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 315 dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF);
317 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 316 dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC);
318 if (HAS_PCH_SPLIT(dev)) { 317 if (HAS_PCH_SPLIT(dev)) {
319 dev_priv->saveFPB0 = I915_READ(PCH_FPB0); 318 dev_priv->saveFPB0 = I915_READ(_PCH_FPB0);
320 dev_priv->saveFPB1 = I915_READ(PCH_FPB1); 319 dev_priv->saveFPB1 = I915_READ(_PCH_FPB1);
321 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B); 320 dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B);
322 } else { 321 } else {
323 dev_priv->saveFPB0 = I915_READ(FPB0); 322 dev_priv->saveFPB0 = I915_READ(_FPB0);
324 dev_priv->saveFPB1 = I915_READ(FPB1); 323 dev_priv->saveFPB1 = I915_READ(_FPB1);
325 dev_priv->saveDPLL_B = I915_READ(DPLL_B); 324 dev_priv->saveDPLL_B = I915_READ(_DPLL_B);
326 } 325 }
327 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) 326 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
328 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 327 dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
329 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 328 dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B);
330 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); 329 dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B);
331 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B); 330 dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B);
332 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 331 dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B);
333 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 332 dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B);
334 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 333 dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B);
335 if (!HAS_PCH_SPLIT(dev)) 334 if (!HAS_PCH_SPLIT(dev))
336 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B); 335 dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
337 336
338 if (HAS_PCH_SPLIT(dev)) { 337 if (HAS_PCH_SPLIT(dev)) {
339 dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1); 338 dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
340 dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1); 339 dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
341 dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1); 340 dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
342 dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1); 341 dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
343 342
344 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL); 343 dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
345 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL); 344 dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
346 345
347 dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1); 346 dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
348 dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ); 347 dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
349 dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS); 348 dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
350 349
351 dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF); 350 dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF);
352 dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B); 351 dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
353 dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B); 352 dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
354 dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B); 353 dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
355 dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B); 354 dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
356 dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B); 355 dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
357 dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B); 356 dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
358 } 357 }
359 358
360 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR); 359 dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR);
361 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); 360 dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
362 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE); 361 dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE);
363 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS); 362 dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS);
364 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR); 363 dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR);
365 if (INTEL_INFO(dev)->gen >= 4) { 364 if (INTEL_INFO(dev)->gen >= 4) {
366 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF); 365 dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF);
367 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); 366 dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
368 } 367 }
369 i915_save_palette(dev, PIPE_B); 368 i915_save_palette(dev, PIPE_B);
370 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT); 369 dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT);
371 370
372 /* Fences */ 371 /* Fences */
373 switch (INTEL_INFO(dev)->gen) { 372 switch (INTEL_INFO(dev)->gen) {
@@ -426,19 +425,19 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
426 425
427 426
428 if (HAS_PCH_SPLIT(dev)) { 427 if (HAS_PCH_SPLIT(dev)) {
429 dpll_a_reg = PCH_DPLL_A; 428 dpll_a_reg = _PCH_DPLL_A;
430 dpll_b_reg = PCH_DPLL_B; 429 dpll_b_reg = _PCH_DPLL_B;
431 fpa0_reg = PCH_FPA0; 430 fpa0_reg = _PCH_FPA0;
432 fpb0_reg = PCH_FPB0; 431 fpb0_reg = _PCH_FPB0;
433 fpa1_reg = PCH_FPA1; 432 fpa1_reg = _PCH_FPA1;
434 fpb1_reg = PCH_FPB1; 433 fpb1_reg = _PCH_FPB1;
435 } else { 434 } else {
436 dpll_a_reg = DPLL_A; 435 dpll_a_reg = _DPLL_A;
437 dpll_b_reg = DPLL_B; 436 dpll_b_reg = _DPLL_B;
438 fpa0_reg = FPA0; 437 fpa0_reg = _FPA0;
439 fpb0_reg = FPB0; 438 fpb0_reg = _FPB0;
440 fpa1_reg = FPA1; 439 fpa1_reg = _FPA1;
441 fpb1_reg = FPB1; 440 fpb1_reg = _FPB1;
442 } 441 }
443 442
444 if (HAS_PCH_SPLIT(dev)) { 443 if (HAS_PCH_SPLIT(dev)) {
@@ -461,60 +460,60 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
461 POSTING_READ(dpll_a_reg); 460 POSTING_READ(dpll_a_reg);
462 udelay(150); 461 udelay(150);
463 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { 462 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
464 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 463 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD);
465 POSTING_READ(DPLL_A_MD); 464 POSTING_READ(_DPLL_A_MD);
466 } 465 }
467 udelay(150); 466 udelay(150);
468 467
469 /* Restore mode */ 468 /* Restore mode */
470 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); 469 I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A);
471 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A); 470 I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A);
472 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A); 471 I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A);
473 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 472 I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A);
474 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 473 I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A);
475 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 474 I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A);
476 if (!HAS_PCH_SPLIT(dev)) 475 if (!HAS_PCH_SPLIT(dev))
477 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 476 I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A);
478 477
479 if (HAS_PCH_SPLIT(dev)) { 478 if (HAS_PCH_SPLIT(dev)) {
480 I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1); 479 I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
481 I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1); 480 I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
482 I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1); 481 I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
483 I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1); 482 I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
484 483
485 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL); 484 I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
486 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL); 485 I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
487 486
488 I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1); 487 I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1);
489 I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ); 488 I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
490 I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS); 489 I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
491 490
492 I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF); 491 I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF);
493 I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A); 492 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
494 I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A); 493 I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
495 I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A); 494 I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
496 I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A); 495 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
497 I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A); 496 I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
498 I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A); 497 I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
499 } 498 }
500 499
501 /* Restore plane info */ 500 /* Restore plane info */
502 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); 501 I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE);
503 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS); 502 I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS);
504 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC); 503 I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC);
505 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR); 504 I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR);
506 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE); 505 I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE);
507 if (INTEL_INFO(dev)->gen >= 4) { 506 if (INTEL_INFO(dev)->gen >= 4) {
508 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF); 507 I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF);
509 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF); 508 I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF);
510 } 509 }
511 510
512 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF); 511 I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF);
513 512
514 i915_restore_palette(dev, PIPE_A); 513 i915_restore_palette(dev, PIPE_A);
515 /* Enable the plane */ 514 /* Enable the plane */
516 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR); 515 I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR);
517 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR)); 516 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
518 517
519 /* Pipe & plane B info */ 518 /* Pipe & plane B info */
520 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 519 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
@@ -530,68 +529,68 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
530 POSTING_READ(dpll_b_reg); 529 POSTING_READ(dpll_b_reg);
531 udelay(150); 530 udelay(150);
532 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { 531 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
533 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); 532 I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD);
534 POSTING_READ(DPLL_B_MD); 533 POSTING_READ(_DPLL_B_MD);
535 } 534 }
536 udelay(150); 535 udelay(150);
537 536
538 /* Restore mode */ 537 /* Restore mode */
539 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B); 538 I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B);
540 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B); 539 I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B);
541 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B); 540 I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B);
542 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 541 I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B);
543 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 542 I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B);
544 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 543 I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B);
545 if (!HAS_PCH_SPLIT(dev)) 544 if (!HAS_PCH_SPLIT(dev))
546 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 545 I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B);
547 546
548 if (HAS_PCH_SPLIT(dev)) { 547 if (HAS_PCH_SPLIT(dev)) {
549 I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1); 548 I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
550 I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1); 549 I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
551 I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1); 550 I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
552 I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1); 551 I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
553 552
554 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL); 553 I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
555 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL); 554 I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
556 555
557 I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1); 556 I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1);
558 I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ); 557 I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
559 I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS); 558 I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
560 559
561 I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF); 560 I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF);
562 I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B); 561 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
563 I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B); 562 I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
564 I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B); 563 I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
565 I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B); 564 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
566 I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B); 565 I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
567 I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B); 566 I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
568 } 567 }
569 568
570 /* Restore plane info */ 569 /* Restore plane info */
571 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); 570 I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE);
572 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS); 571 I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS);
573 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC); 572 I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC);
574 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR); 573 I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR);
575 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); 574 I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
576 if (INTEL_INFO(dev)->gen >= 4) { 575 if (INTEL_INFO(dev)->gen >= 4) {
577 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF); 576 I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF);
578 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); 577 I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
579 } 578 }
580 579
581 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF); 580 I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF);
582 581
583 i915_restore_palette(dev, PIPE_B); 582 i915_restore_palette(dev, PIPE_B);
584 /* Enable the plane */ 583 /* Enable the plane */
585 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); 584 I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR);
586 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR)); 585 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
587 586
588 /* Cursor state */ 587 /* Cursor state */
589 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS); 588 I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS);
590 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR); 589 I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR);
591 I915_WRITE(CURABASE, dev_priv->saveCURABASE); 590 I915_WRITE(_CURABASE, dev_priv->saveCURABASE);
592 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS); 591 I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS);
593 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR); 592 I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR);
594 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE); 593 I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE);
595 if (IS_GEN2(dev)) 594 if (IS_GEN2(dev))
596 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); 595 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
597 596
@@ -653,14 +652,14 @@ void i915_save_display(struct drm_device *dev)
653 dev_priv->saveDP_B = I915_READ(DP_B); 652 dev_priv->saveDP_B = I915_READ(DP_B);
654 dev_priv->saveDP_C = I915_READ(DP_C); 653 dev_priv->saveDP_C = I915_READ(DP_C);
655 dev_priv->saveDP_D = I915_READ(DP_D); 654 dev_priv->saveDP_D = I915_READ(DP_D);
656 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M); 655 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
657 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M); 656 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
658 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N); 657 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
659 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N); 658 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
660 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M); 659 dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
661 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M); 660 dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
662 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N); 661 dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
663 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N); 662 dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
664 } 663 }
665 /* FIXME: save TV & SDVO state */ 664 /* FIXME: save TV & SDVO state */
666 665
@@ -699,14 +698,14 @@ void i915_restore_display(struct drm_device *dev)
699 698
700 /* Display port ratios (must be done before clock is set) */ 699 /* Display port ratios (must be done before clock is set) */
701 if (SUPPORTS_INTEGRATED_DP(dev)) { 700 if (SUPPORTS_INTEGRATED_DP(dev)) {
702 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M); 701 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
703 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M); 702 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
704 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N); 703 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
705 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N); 704 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
706 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M); 705 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
707 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M); 706 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
708 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N); 707 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
709 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N); 708 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
710 } 709 }
711 710
712 /* This is only meaningful in non-KMS mode */ 711 /* This is only meaningful in non-KMS mode */
@@ -808,8 +807,8 @@ int i915_save_state(struct drm_device *dev)
808 dev_priv->saveDEIMR = I915_READ(DEIMR); 807 dev_priv->saveDEIMR = I915_READ(DEIMR);
809 dev_priv->saveGTIER = I915_READ(GTIER); 808 dev_priv->saveGTIER = I915_READ(GTIER);
810 dev_priv->saveGTIMR = I915_READ(GTIMR); 809 dev_priv->saveGTIMR = I915_READ(GTIMR);
811 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR); 810 dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
812 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR); 811 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
813 dev_priv->saveMCHBAR_RENDER_STANDBY = 812 dev_priv->saveMCHBAR_RENDER_STANDBY =
814 I915_READ(RSTDBYCTL); 813 I915_READ(RSTDBYCTL);
815 } else { 814 } else {
@@ -857,11 +856,11 @@ int i915_restore_state(struct drm_device *dev)
857 I915_WRITE(DEIMR, dev_priv->saveDEIMR); 856 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
858 I915_WRITE(GTIER, dev_priv->saveGTIER); 857 I915_WRITE(GTIER, dev_priv->saveGTIER);
859 I915_WRITE(GTIMR, dev_priv->saveGTIMR); 858 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
860 I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR); 859 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
861 I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR); 860 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
862 } else { 861 } else {
863 I915_WRITE (IER, dev_priv->saveIER); 862 I915_WRITE(IER, dev_priv->saveIER);
864 I915_WRITE (IMR, dev_priv->saveIMR); 863 I915_WRITE(IMR, dev_priv->saveIMR);
865 } 864 }
866 865
867 /* Clock gating state */ 866 /* Clock gating state */
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 7f0fc3ed61aa..d623fefbfaca 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -7,6 +7,7 @@
7 7
8#include <drm/drmP.h> 8#include <drm/drmP.h>
9#include "i915_drv.h" 9#include "i915_drv.h"
10#include "intel_ringbuffer.h"
10 11
11#undef TRACE_SYSTEM 12#undef TRACE_SYSTEM
12#define TRACE_SYSTEM i915 13#define TRACE_SYSTEM i915
@@ -16,9 +17,7 @@
16/* object tracking */ 17/* object tracking */
17 18
18TRACE_EVENT(i915_gem_object_create, 19TRACE_EVENT(i915_gem_object_create,
19
20 TP_PROTO(struct drm_i915_gem_object *obj), 20 TP_PROTO(struct drm_i915_gem_object *obj),
21
22 TP_ARGS(obj), 21 TP_ARGS(obj),
23 22
24 TP_STRUCT__entry( 23 TP_STRUCT__entry(
@@ -35,33 +34,51 @@ TRACE_EVENT(i915_gem_object_create,
35); 34);
36 35
37TRACE_EVENT(i915_gem_object_bind, 36TRACE_EVENT(i915_gem_object_bind,
38 37 TP_PROTO(struct drm_i915_gem_object *obj, bool mappable),
39 TP_PROTO(struct drm_i915_gem_object *obj, u32 gtt_offset, bool mappable), 38 TP_ARGS(obj, mappable),
40
41 TP_ARGS(obj, gtt_offset, mappable),
42 39
43 TP_STRUCT__entry( 40 TP_STRUCT__entry(
44 __field(struct drm_i915_gem_object *, obj) 41 __field(struct drm_i915_gem_object *, obj)
45 __field(u32, gtt_offset) 42 __field(u32, offset)
43 __field(u32, size)
46 __field(bool, mappable) 44 __field(bool, mappable)
47 ), 45 ),
48 46
49 TP_fast_assign( 47 TP_fast_assign(
50 __entry->obj = obj; 48 __entry->obj = obj;
51 __entry->gtt_offset = gtt_offset; 49 __entry->offset = obj->gtt_space->start;
50 __entry->size = obj->gtt_space->size;
52 __entry->mappable = mappable; 51 __entry->mappable = mappable;
53 ), 52 ),
54 53
55 TP_printk("obj=%p, gtt_offset=%08x%s", 54 TP_printk("obj=%p, offset=%08x size=%x%s",
56 __entry->obj, __entry->gtt_offset, 55 __entry->obj, __entry->offset, __entry->size,
57 __entry->mappable ? ", mappable" : "") 56 __entry->mappable ? ", mappable" : "")
58); 57);
59 58
60TRACE_EVENT(i915_gem_object_change_domain, 59TRACE_EVENT(i915_gem_object_unbind,
60 TP_PROTO(struct drm_i915_gem_object *obj),
61 TP_ARGS(obj),
62
63 TP_STRUCT__entry(
64 __field(struct drm_i915_gem_object *, obj)
65 __field(u32, offset)
66 __field(u32, size)
67 ),
61 68
62 TP_PROTO(struct drm_i915_gem_object *obj, uint32_t old_read_domains, uint32_t old_write_domain), 69 TP_fast_assign(
70 __entry->obj = obj;
71 __entry->offset = obj->gtt_space->start;
72 __entry->size = obj->gtt_space->size;
73 ),
63 74
64 TP_ARGS(obj, old_read_domains, old_write_domain), 75 TP_printk("obj=%p, offset=%08x size=%x",
76 __entry->obj, __entry->offset, __entry->size)
77);
78
79TRACE_EVENT(i915_gem_object_change_domain,
80 TP_PROTO(struct drm_i915_gem_object *obj, u32 old_read, u32 old_write),
81 TP_ARGS(obj, old_read, old_write),
65 82
66 TP_STRUCT__entry( 83 TP_STRUCT__entry(
67 __field(struct drm_i915_gem_object *, obj) 84 __field(struct drm_i915_gem_object *, obj)
@@ -71,177 +88,264 @@ TRACE_EVENT(i915_gem_object_change_domain,
71 88
72 TP_fast_assign( 89 TP_fast_assign(
73 __entry->obj = obj; 90 __entry->obj = obj;
74 __entry->read_domains = obj->base.read_domains | (old_read_domains << 16); 91 __entry->read_domains = obj->base.read_domains | (old_read << 16);
75 __entry->write_domain = obj->base.write_domain | (old_write_domain << 16); 92 __entry->write_domain = obj->base.write_domain | (old_write << 16);
76 ), 93 ),
77 94
78 TP_printk("obj=%p, read=%04x, write=%04x", 95 TP_printk("obj=%p, read=%02x=>%02x, write=%02x=>%02x",
79 __entry->obj, 96 __entry->obj,
80 __entry->read_domains, __entry->write_domain) 97 __entry->read_domains >> 16,
98 __entry->read_domains & 0xffff,
99 __entry->write_domain >> 16,
100 __entry->write_domain & 0xffff)
81); 101);
82 102
83DECLARE_EVENT_CLASS(i915_gem_object, 103TRACE_EVENT(i915_gem_object_pwrite,
104 TP_PROTO(struct drm_i915_gem_object *obj, u32 offset, u32 len),
105 TP_ARGS(obj, offset, len),
84 106
85 TP_PROTO(struct drm_i915_gem_object *obj), 107 TP_STRUCT__entry(
108 __field(struct drm_i915_gem_object *, obj)
109 __field(u32, offset)
110 __field(u32, len)
111 ),
86 112
87 TP_ARGS(obj), 113 TP_fast_assign(
114 __entry->obj = obj;
115 __entry->offset = offset;
116 __entry->len = len;
117 ),
118
119 TP_printk("obj=%p, offset=%u, len=%u",
120 __entry->obj, __entry->offset, __entry->len)
121);
122
123TRACE_EVENT(i915_gem_object_pread,
124 TP_PROTO(struct drm_i915_gem_object *obj, u32 offset, u32 len),
125 TP_ARGS(obj, offset, len),
88 126
89 TP_STRUCT__entry( 127 TP_STRUCT__entry(
90 __field(struct drm_i915_gem_object *, obj) 128 __field(struct drm_i915_gem_object *, obj)
129 __field(u32, offset)
130 __field(u32, len)
91 ), 131 ),
92 132
93 TP_fast_assign( 133 TP_fast_assign(
94 __entry->obj = obj; 134 __entry->obj = obj;
135 __entry->offset = offset;
136 __entry->len = len;
95 ), 137 ),
96 138
97 TP_printk("obj=%p", __entry->obj) 139 TP_printk("obj=%p, offset=%u, len=%u",
140 __entry->obj, __entry->offset, __entry->len)
98); 141);
99 142
100DEFINE_EVENT(i915_gem_object, i915_gem_object_clflush, 143TRACE_EVENT(i915_gem_object_fault,
144 TP_PROTO(struct drm_i915_gem_object *obj, u32 index, bool gtt, bool write),
145 TP_ARGS(obj, index, gtt, write),
146
147 TP_STRUCT__entry(
148 __field(struct drm_i915_gem_object *, obj)
149 __field(u32, index)
150 __field(bool, gtt)
151 __field(bool, write)
152 ),
153
154 TP_fast_assign(
155 __entry->obj = obj;
156 __entry->index = index;
157 __entry->gtt = gtt;
158 __entry->write = write;
159 ),
101 160
161 TP_printk("obj=%p, %s index=%u %s",
162 __entry->obj,
163 __entry->gtt ? "GTT" : "CPU",
164 __entry->index,
165 __entry->write ? ", writable" : "")
166);
167
168DECLARE_EVENT_CLASS(i915_gem_object,
102 TP_PROTO(struct drm_i915_gem_object *obj), 169 TP_PROTO(struct drm_i915_gem_object *obj),
170 TP_ARGS(obj),
103 171
104 TP_ARGS(obj) 172 TP_STRUCT__entry(
173 __field(struct drm_i915_gem_object *, obj)
174 ),
175
176 TP_fast_assign(
177 __entry->obj = obj;
178 ),
179
180 TP_printk("obj=%p", __entry->obj)
105); 181);
106 182
107DEFINE_EVENT(i915_gem_object, i915_gem_object_unbind, 183DEFINE_EVENT(i915_gem_object, i915_gem_object_clflush,
184 TP_PROTO(struct drm_i915_gem_object *obj),
185 TP_ARGS(obj)
186);
108 187
188DEFINE_EVENT(i915_gem_object, i915_gem_object_destroy,
109 TP_PROTO(struct drm_i915_gem_object *obj), 189 TP_PROTO(struct drm_i915_gem_object *obj),
110
111 TP_ARGS(obj) 190 TP_ARGS(obj)
112); 191);
113 192
114DEFINE_EVENT(i915_gem_object, i915_gem_object_destroy, 193TRACE_EVENT(i915_gem_evict,
194 TP_PROTO(struct drm_device *dev, u32 size, u32 align, bool mappable),
195 TP_ARGS(dev, size, align, mappable),
115 196
116 TP_PROTO(struct drm_i915_gem_object *obj), 197 TP_STRUCT__entry(
198 __field(u32, dev)
199 __field(u32, size)
200 __field(u32, align)
201 __field(bool, mappable)
202 ),
117 203
118 TP_ARGS(obj) 204 TP_fast_assign(
205 __entry->dev = dev->primary->index;
206 __entry->size = size;
207 __entry->align = align;
208 __entry->mappable = mappable;
209 ),
210
211 TP_printk("dev=%d, size=%d, align=%d %s",
212 __entry->dev, __entry->size, __entry->align,
213 __entry->mappable ? ", mappable" : "")
119); 214);
120 215
121/* batch tracing */ 216TRACE_EVENT(i915_gem_evict_everything,
217 TP_PROTO(struct drm_device *dev, bool purgeable),
218 TP_ARGS(dev, purgeable),
122 219
123TRACE_EVENT(i915_gem_request_submit, 220 TP_STRUCT__entry(
221 __field(u32, dev)
222 __field(bool, purgeable)
223 ),
224
225 TP_fast_assign(
226 __entry->dev = dev->primary->index;
227 __entry->purgeable = purgeable;
228 ),
124 229
125 TP_PROTO(struct drm_device *dev, u32 seqno), 230 TP_printk("dev=%d%s",
231 __entry->dev,
232 __entry->purgeable ? ", purgeable only" : "")
233);
126 234
127 TP_ARGS(dev, seqno), 235TRACE_EVENT(i915_gem_ring_dispatch,
236 TP_PROTO(struct intel_ring_buffer *ring, u32 seqno),
237 TP_ARGS(ring, seqno),
128 238
129 TP_STRUCT__entry( 239 TP_STRUCT__entry(
130 __field(u32, dev) 240 __field(u32, dev)
241 __field(u32, ring)
131 __field(u32, seqno) 242 __field(u32, seqno)
132 ), 243 ),
133 244
134 TP_fast_assign( 245 TP_fast_assign(
135 __entry->dev = dev->primary->index; 246 __entry->dev = ring->dev->primary->index;
247 __entry->ring = ring->id;
136 __entry->seqno = seqno; 248 __entry->seqno = seqno;
137 i915_trace_irq_get(dev, seqno); 249 i915_trace_irq_get(ring, seqno);
138 ), 250 ),
139 251
140 TP_printk("dev=%u, seqno=%u", __entry->dev, __entry->seqno) 252 TP_printk("dev=%u, ring=%u, seqno=%u",
253 __entry->dev, __entry->ring, __entry->seqno)
141); 254);
142 255
143TRACE_EVENT(i915_gem_request_flush, 256TRACE_EVENT(i915_gem_ring_flush,
144 257 TP_PROTO(struct intel_ring_buffer *ring, u32 invalidate, u32 flush),
145 TP_PROTO(struct drm_device *dev, u32 seqno, 258 TP_ARGS(ring, invalidate, flush),
146 u32 flush_domains, u32 invalidate_domains),
147
148 TP_ARGS(dev, seqno, flush_domains, invalidate_domains),
149 259
150 TP_STRUCT__entry( 260 TP_STRUCT__entry(
151 __field(u32, dev) 261 __field(u32, dev)
152 __field(u32, seqno) 262 __field(u32, ring)
153 __field(u32, flush_domains) 263 __field(u32, invalidate)
154 __field(u32, invalidate_domains) 264 __field(u32, flush)
155 ), 265 ),
156 266
157 TP_fast_assign( 267 TP_fast_assign(
158 __entry->dev = dev->primary->index; 268 __entry->dev = ring->dev->primary->index;
159 __entry->seqno = seqno; 269 __entry->ring = ring->id;
160 __entry->flush_domains = flush_domains; 270 __entry->invalidate = invalidate;
161 __entry->invalidate_domains = invalidate_domains; 271 __entry->flush = flush;
162 ), 272 ),
163 273
164 TP_printk("dev=%u, seqno=%u, flush=%04x, invalidate=%04x", 274 TP_printk("dev=%u, ring=%x, invalidate=%04x, flush=%04x",
165 __entry->dev, __entry->seqno, 275 __entry->dev, __entry->ring,
166 __entry->flush_domains, __entry->invalidate_domains) 276 __entry->invalidate, __entry->flush)
167); 277);
168 278
169DECLARE_EVENT_CLASS(i915_gem_request, 279DECLARE_EVENT_CLASS(i915_gem_request,
170 280 TP_PROTO(struct intel_ring_buffer *ring, u32 seqno),
171 TP_PROTO(struct drm_device *dev, u32 seqno), 281 TP_ARGS(ring, seqno),
172
173 TP_ARGS(dev, seqno),
174 282
175 TP_STRUCT__entry( 283 TP_STRUCT__entry(
176 __field(u32, dev) 284 __field(u32, dev)
285 __field(u32, ring)
177 __field(u32, seqno) 286 __field(u32, seqno)
178 ), 287 ),
179 288
180 TP_fast_assign( 289 TP_fast_assign(
181 __entry->dev = dev->primary->index; 290 __entry->dev = ring->dev->primary->index;
291 __entry->ring = ring->id;
182 __entry->seqno = seqno; 292 __entry->seqno = seqno;
183 ), 293 ),
184 294
185 TP_printk("dev=%u, seqno=%u", __entry->dev, __entry->seqno) 295 TP_printk("dev=%u, ring=%u, seqno=%u",
296 __entry->dev, __entry->ring, __entry->seqno)
186); 297);
187 298
188DEFINE_EVENT(i915_gem_request, i915_gem_request_complete, 299DEFINE_EVENT(i915_gem_request, i915_gem_request_add,
189 300 TP_PROTO(struct intel_ring_buffer *ring, u32 seqno),
190 TP_PROTO(struct drm_device *dev, u32 seqno), 301 TP_ARGS(ring, seqno)
302);
191 303
192 TP_ARGS(dev, seqno) 304DEFINE_EVENT(i915_gem_request, i915_gem_request_complete,
305 TP_PROTO(struct intel_ring_buffer *ring, u32 seqno),
306 TP_ARGS(ring, seqno)
193); 307);
194 308
195DEFINE_EVENT(i915_gem_request, i915_gem_request_retire, 309DEFINE_EVENT(i915_gem_request, i915_gem_request_retire,
196 310 TP_PROTO(struct intel_ring_buffer *ring, u32 seqno),
197 TP_PROTO(struct drm_device *dev, u32 seqno), 311 TP_ARGS(ring, seqno)
198
199 TP_ARGS(dev, seqno)
200); 312);
201 313
202DEFINE_EVENT(i915_gem_request, i915_gem_request_wait_begin, 314DEFINE_EVENT(i915_gem_request, i915_gem_request_wait_begin,
203 315 TP_PROTO(struct intel_ring_buffer *ring, u32 seqno),
204 TP_PROTO(struct drm_device *dev, u32 seqno), 316 TP_ARGS(ring, seqno)
205
206 TP_ARGS(dev, seqno)
207); 317);
208 318
209DEFINE_EVENT(i915_gem_request, i915_gem_request_wait_end, 319DEFINE_EVENT(i915_gem_request, i915_gem_request_wait_end,
210 320 TP_PROTO(struct intel_ring_buffer *ring, u32 seqno),
211 TP_PROTO(struct drm_device *dev, u32 seqno), 321 TP_ARGS(ring, seqno)
212
213 TP_ARGS(dev, seqno)
214); 322);
215 323
216DECLARE_EVENT_CLASS(i915_ring, 324DECLARE_EVENT_CLASS(i915_ring,
217 325 TP_PROTO(struct intel_ring_buffer *ring),
218 TP_PROTO(struct drm_device *dev), 326 TP_ARGS(ring),
219
220 TP_ARGS(dev),
221 327
222 TP_STRUCT__entry( 328 TP_STRUCT__entry(
223 __field(u32, dev) 329 __field(u32, dev)
330 __field(u32, ring)
224 ), 331 ),
225 332
226 TP_fast_assign( 333 TP_fast_assign(
227 __entry->dev = dev->primary->index; 334 __entry->dev = ring->dev->primary->index;
335 __entry->ring = ring->id;
228 ), 336 ),
229 337
230 TP_printk("dev=%u", __entry->dev) 338 TP_printk("dev=%u, ring=%u", __entry->dev, __entry->ring)
231); 339);
232 340
233DEFINE_EVENT(i915_ring, i915_ring_wait_begin, 341DEFINE_EVENT(i915_ring, i915_ring_wait_begin,
234 342 TP_PROTO(struct intel_ring_buffer *ring),
235 TP_PROTO(struct drm_device *dev), 343 TP_ARGS(ring)
236
237 TP_ARGS(dev)
238); 344);
239 345
240DEFINE_EVENT(i915_ring, i915_ring_wait_end, 346DEFINE_EVENT(i915_ring, i915_ring_wait_end,
241 347 TP_PROTO(struct intel_ring_buffer *ring),
242 TP_PROTO(struct drm_device *dev), 348 TP_ARGS(ring)
243
244 TP_ARGS(dev)
245); 349);
246 350
247TRACE_EVENT(i915_flip_request, 351TRACE_EVENT(i915_flip_request,
@@ -281,26 +385,29 @@ TRACE_EVENT(i915_flip_complete,
281); 385);
282 386
283TRACE_EVENT(i915_reg_rw, 387TRACE_EVENT(i915_reg_rw,
284 TP_PROTO(int cmd, uint32_t reg, uint64_t val, int len), 388 TP_PROTO(bool write, u32 reg, u64 val, int len),
285 389
286 TP_ARGS(cmd, reg, val, len), 390 TP_ARGS(write, reg, val, len),
287 391
288 TP_STRUCT__entry( 392 TP_STRUCT__entry(
289 __field(int, cmd) 393 __field(u64, val)
290 __field(uint32_t, reg) 394 __field(u32, reg)
291 __field(uint64_t, val) 395 __field(u16, write)
292 __field(int, len) 396 __field(u16, len)
293 ), 397 ),
294 398
295 TP_fast_assign( 399 TP_fast_assign(
296 __entry->cmd = cmd; 400 __entry->val = (u64)val;
297 __entry->reg = reg; 401 __entry->reg = reg;
298 __entry->val = (uint64_t)val; 402 __entry->write = write;
299 __entry->len = len; 403 __entry->len = len;
300 ), 404 ),
301 405
302 TP_printk("cmd=%c, reg=0x%x, val=0x%llx, len=%d", 406 TP_printk("%s reg=0x%x, len=%d, val=(0x%x, 0x%x)",
303 __entry->cmd, __entry->reg, __entry->val, __entry->len) 407 __entry->write ? "write" : "read",
408 __entry->reg, __entry->len,
409 (u32)(__entry->val & 0xffffffff),
410 (u32)(__entry->val >> 32))
304); 411);
305 412
306#endif /* _I915_TRACE_H_ */ 413#endif /* _I915_TRACE_H_ */
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 0b44956c336b..48a0f03b60c3 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -226,29 +226,49 @@ static void
226parse_sdvo_panel_data(struct drm_i915_private *dev_priv, 226parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
227 struct bdb_header *bdb) 227 struct bdb_header *bdb)
228{ 228{
229 struct bdb_sdvo_lvds_options *sdvo_lvds_options;
230 struct lvds_dvo_timing *dvo_timing; 229 struct lvds_dvo_timing *dvo_timing;
231 struct drm_display_mode *panel_fixed_mode; 230 struct drm_display_mode *panel_fixed_mode;
231 int index;
232 232
233 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS); 233 index = i915_vbt_sdvo_panel_type;
234 if (!sdvo_lvds_options) 234 if (index == -1) {
235 return; 235 struct bdb_sdvo_lvds_options *sdvo_lvds_options;
236
237 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
238 if (!sdvo_lvds_options)
239 return;
240
241 index = sdvo_lvds_options->panel_type;
242 }
236 243
237 dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS); 244 dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
238 if (!dvo_timing) 245 if (!dvo_timing)
239 return; 246 return;
240 247
241 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); 248 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
242
243 if (!panel_fixed_mode) 249 if (!panel_fixed_mode)
244 return; 250 return;
245 251
246 fill_detail_timing_data(panel_fixed_mode, 252 fill_detail_timing_data(panel_fixed_mode, dvo_timing + index);
247 dvo_timing + sdvo_lvds_options->panel_type);
248 253
249 dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode; 254 dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode;
250 255
251 return; 256 DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n");
257 drm_mode_debug_printmodeline(panel_fixed_mode);
258}
259
260static int intel_bios_ssc_frequency(struct drm_device *dev,
261 bool alternate)
262{
263 switch (INTEL_INFO(dev)->gen) {
264 case 2:
265 return alternate ? 66 : 48;
266 case 3:
267 case 4:
268 return alternate ? 100 : 96;
269 default:
270 return alternate ? 100 : 120;
271 }
252} 272}
253 273
254static void 274static void
@@ -263,13 +283,9 @@ parse_general_features(struct drm_i915_private *dev_priv,
263 dev_priv->int_tv_support = general->int_tv_support; 283 dev_priv->int_tv_support = general->int_tv_support;
264 dev_priv->int_crt_support = general->int_crt_support; 284 dev_priv->int_crt_support = general->int_crt_support;
265 dev_priv->lvds_use_ssc = general->enable_ssc; 285 dev_priv->lvds_use_ssc = general->enable_ssc;
266 286 dev_priv->lvds_ssc_freq =
267 if (IS_I85X(dev)) 287 intel_bios_ssc_frequency(dev, general->ssc_freq);
268 dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48; 288 dev_priv->display_clock_mode = general->display_clock_mode;
269 else if (IS_GEN5(dev) || IS_GEN6(dev))
270 dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 120;
271 else
272 dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
273 } 289 }
274} 290}
275 291
@@ -553,6 +569,8 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
553static void 569static void
554init_vbt_defaults(struct drm_i915_private *dev_priv) 570init_vbt_defaults(struct drm_i915_private *dev_priv)
555{ 571{
572 struct drm_device *dev = dev_priv->dev;
573
556 dev_priv->crt_ddc_pin = GMBUS_PORT_VGADDC; 574 dev_priv->crt_ddc_pin = GMBUS_PORT_VGADDC;
557 575
558 /* LFP panel data */ 576 /* LFP panel data */
@@ -565,7 +583,11 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
565 /* general features */ 583 /* general features */
566 dev_priv->int_tv_support = 1; 584 dev_priv->int_tv_support = 1;
567 dev_priv->int_crt_support = 1; 585 dev_priv->int_crt_support = 1;
568 dev_priv->lvds_use_ssc = 0; 586
587 /* Default to using SSC */
588 dev_priv->lvds_use_ssc = 1;
589 dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
590 DRM_DEBUG("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq);
569 591
570 /* eDP data */ 592 /* eDP data */
571 dev_priv->edp.bpp = 18; 593 dev_priv->edp.bpp = 18;
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 5f8e4edcbbb9..02b1b62415df 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -120,7 +120,9 @@ struct bdb_general_features {
120 u8 ssc_freq:1; 120 u8 ssc_freq:1;
121 u8 enable_lfp_on_override:1; 121 u8 enable_lfp_on_override:1;
122 u8 disable_ssc_ddt:1; 122 u8 disable_ssc_ddt:1;
123 u8 rsvd8:3; /* finish byte */ 123 u8 rsvd7:1;
124 u8 display_clock_mode:1;
125 u8 rsvd8:1; /* finish byte */
124 126
125 /* bits 3 */ 127 /* bits 3 */
126 u8 disable_smooth_vision:1; 128 u8 disable_smooth_vision:1;
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 8a77ff4a7237..8342259f3160 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -129,10 +129,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
129 u32 adpa, dpll_md; 129 u32 adpa, dpll_md;
130 u32 adpa_reg; 130 u32 adpa_reg;
131 131
132 if (intel_crtc->pipe == 0) 132 dpll_md_reg = DPLL_MD(intel_crtc->pipe);
133 dpll_md_reg = DPLL_A_MD;
134 else
135 dpll_md_reg = DPLL_B_MD;
136 133
137 if (HAS_PCH_SPLIT(dev)) 134 if (HAS_PCH_SPLIT(dev))
138 adpa_reg = PCH_ADPA; 135 adpa_reg = PCH_ADPA;
@@ -160,17 +157,16 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
160 adpa |= PORT_TRANS_A_SEL_CPT; 157 adpa |= PORT_TRANS_A_SEL_CPT;
161 else 158 else
162 adpa |= ADPA_PIPE_A_SELECT; 159 adpa |= ADPA_PIPE_A_SELECT;
163 if (!HAS_PCH_SPLIT(dev))
164 I915_WRITE(BCLRPAT_A, 0);
165 } else { 160 } else {
166 if (HAS_PCH_CPT(dev)) 161 if (HAS_PCH_CPT(dev))
167 adpa |= PORT_TRANS_B_SEL_CPT; 162 adpa |= PORT_TRANS_B_SEL_CPT;
168 else 163 else
169 adpa |= ADPA_PIPE_B_SELECT; 164 adpa |= ADPA_PIPE_B_SELECT;
170 if (!HAS_PCH_SPLIT(dev))
171 I915_WRITE(BCLRPAT_B, 0);
172 } 165 }
173 166
167 if (!HAS_PCH_SPLIT(dev))
168 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
169
174 I915_WRITE(adpa_reg, adpa); 170 I915_WRITE(adpa_reg, adpa);
175} 171}
176 172
@@ -353,21 +349,12 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_crt *crt)
353 349
354 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 350 DRM_DEBUG_KMS("starting load-detect on CRT\n");
355 351
356 if (pipe == 0) { 352 bclrpat_reg = BCLRPAT(pipe);
357 bclrpat_reg = BCLRPAT_A; 353 vtotal_reg = VTOTAL(pipe);
358 vtotal_reg = VTOTAL_A; 354 vblank_reg = VBLANK(pipe);
359 vblank_reg = VBLANK_A; 355 vsync_reg = VSYNC(pipe);
360 vsync_reg = VSYNC_A; 356 pipeconf_reg = PIPECONF(pipe);
361 pipeconf_reg = PIPEACONF; 357 pipe_dsl_reg = PIPEDSL(pipe);
362 pipe_dsl_reg = PIPEADSL;
363 } else {
364 bclrpat_reg = BCLRPAT_B;
365 vtotal_reg = VTOTAL_B;
366 vblank_reg = VBLANK_B;
367 vsync_reg = VSYNC_B;
368 pipeconf_reg = PIPEBCONF;
369 pipe_dsl_reg = PIPEBDSL;
370 }
371 358
372 save_bclrpat = I915_READ(bclrpat_reg); 359 save_bclrpat = I915_READ(bclrpat_reg);
373 save_vtotal = I915_READ(vtotal_reg); 360 save_vtotal = I915_READ(vtotal_reg);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dcb821737f38..5e478338dc0a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -989,7 +989,7 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
989void intel_wait_for_vblank(struct drm_device *dev, int pipe) 989void intel_wait_for_vblank(struct drm_device *dev, int pipe)
990{ 990{
991 struct drm_i915_private *dev_priv = dev->dev_private; 991 struct drm_i915_private *dev_priv = dev->dev_private;
992 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT); 992 int pipestat_reg = PIPESTAT(pipe);
993 993
994 /* Clear existing vblank status. Note this will clear any other 994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well. 995 * sticky status fields as well.
@@ -1058,6 +1058,612 @@ void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1058 } 1058 }
1059} 1059}
1060 1060
1061static const char *state_string(bool enabled)
1062{
1063 return enabled ? "on" : "off";
1064}
1065
1066/* Only for pre-ILK configs */
1067static void assert_pll(struct drm_i915_private *dev_priv,
1068 enum pipe pipe, bool state)
1069{
1070 int reg;
1071 u32 val;
1072 bool cur_state;
1073
1074 reg = DPLL(pipe);
1075 val = I915_READ(reg);
1076 cur_state = !!(val & DPLL_VCO_ENABLE);
1077 WARN(cur_state != state,
1078 "PLL state assertion failure (expected %s, current %s)\n",
1079 state_string(state), state_string(cur_state));
1080}
1081#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1083
1084/* For ILK+ */
1085static void assert_pch_pll(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1087{
1088 int reg;
1089 u32 val;
1090 bool cur_state;
1091
1092 reg = PCH_DPLL(pipe);
1093 val = I915_READ(reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state assertion failure (expected %s, current %s)\n",
1097 state_string(state), state_string(cur_state));
1098}
1099#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
1108
1109 reg = FDI_TX_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & FDI_TX_ENABLE);
1112 WARN(cur_state != state,
1113 "FDI TX state assertion failure (expected %s, current %s)\n",
1114 state_string(state), state_string(cur_state));
1115}
1116#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1118
1119static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121{
1122 int reg;
1123 u32 val;
1124 bool cur_state;
1125
1126 reg = FDI_RX_CTL(pipe);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & FDI_RX_ENABLE);
1129 WARN(cur_state != state,
1130 "FDI RX state assertion failure (expected %s, current %s)\n",
1131 state_string(state), state_string(cur_state));
1132}
1133#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1135
1136static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1137 enum pipe pipe)
1138{
1139 int reg;
1140 u32 val;
1141
1142 /* ILK FDI PLL is always enabled */
1143 if (dev_priv->info->gen == 5)
1144 return;
1145
1146 reg = FDI_TX_CTL(pipe);
1147 val = I915_READ(reg);
1148 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1149}
1150
1151static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1152 enum pipe pipe)
1153{
1154 int reg;
1155 u32 val;
1156
1157 reg = FDI_RX_CTL(pipe);
1158 val = I915_READ(reg);
1159 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1160}
1161
1162static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164{
1165 int pp_reg, lvds_reg;
1166 u32 val;
1167 enum pipe panel_pipe = PIPE_A;
1168 bool locked = locked;
1169
1170 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1171 pp_reg = PCH_PP_CONTROL;
1172 lvds_reg = PCH_LVDS;
1173 } else {
1174 pp_reg = PP_CONTROL;
1175 lvds_reg = LVDS;
1176 }
1177
1178 val = I915_READ(pp_reg);
1179 if (!(val & PANEL_POWER_ON) ||
1180 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1181 locked = false;
1182
1183 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1184 panel_pipe = PIPE_B;
1185
1186 WARN(panel_pipe == pipe && locked,
1187 "panel assertion failure, pipe %c regs locked\n",
1188 pipe_name(pipe));
1189}
1190
1191static void assert_pipe(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, bool state)
1193{
1194 int reg;
1195 u32 val;
1196 bool cur_state;
1197
1198 reg = PIPECONF(pipe);
1199 val = I915_READ(reg);
1200 cur_state = !!(val & PIPECONF_ENABLE);
1201 WARN(cur_state != state,
1202 "pipe %c assertion failure (expected %s, current %s)\n",
1203 pipe_name(pipe), state_string(state), state_string(cur_state));
1204}
1205#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1207
1208static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1209 enum plane plane)
1210{
1211 int reg;
1212 u32 val;
1213
1214 reg = DSPCNTR(plane);
1215 val = I915_READ(reg);
1216 WARN(!(val & DISPLAY_PLANE_ENABLE),
1217 "plane %c assertion failure, should be active but is disabled\n",
1218 plane_name(plane));
1219}
1220
1221static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1222 enum pipe pipe)
1223{
1224 int reg, i;
1225 u32 val;
1226 int cur_pipe;
1227
1228 /* Planes are fixed to pipes on ILK+ */
1229 if (HAS_PCH_SPLIT(dev_priv->dev))
1230 return;
1231
1232 /* Need to check both planes against the pipe */
1233 for (i = 0; i < 2; i++) {
1234 reg = DSPCNTR(i);
1235 val = I915_READ(reg);
1236 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1237 DISPPLANE_SEL_PIPE_SHIFT;
1238 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1239 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1240 plane_name(i), pipe_name(pipe));
1241 }
1242}
1243
1244static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1245{
1246 u32 val;
1247 bool enabled;
1248
1249 val = I915_READ(PCH_DREF_CONTROL);
1250 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1251 DREF_SUPERSPREAD_SOURCE_MASK));
1252 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1253}
1254
1255static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1256 enum pipe pipe)
1257{
1258 int reg;
1259 u32 val;
1260 bool enabled;
1261
1262 reg = TRANSCONF(pipe);
1263 val = I915_READ(reg);
1264 enabled = !!(val & TRANS_ENABLE);
1265 WARN(enabled,
1266 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1267 pipe_name(pipe));
1268}
1269
1270static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1271 enum pipe pipe, int reg)
1272{
1273 u32 val = I915_READ(reg);
1274 WARN(DP_PIPE_ENABLED(val, pipe),
1275 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1276 reg, pipe_name(pipe));
1277}
1278
1279static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, int reg)
1281{
1282 u32 val = I915_READ(reg);
1283 WARN(HDMI_PIPE_ENABLED(val, pipe),
1284 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1285 reg, pipe_name(pipe));
1286}
1287
1288static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1289 enum pipe pipe)
1290{
1291 int reg;
1292 u32 val;
1293
1294 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1295 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1296 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1297
1298 reg = PCH_ADPA;
1299 val = I915_READ(reg);
1300 WARN(ADPA_PIPE_ENABLED(val, pipe),
1301 "PCH VGA enabled on transcoder %c, should be disabled\n",
1302 pipe_name(pipe));
1303
1304 reg = PCH_LVDS;
1305 val = I915_READ(reg);
1306 WARN(LVDS_PIPE_ENABLED(val, pipe),
1307 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1308 pipe_name(pipe));
1309
1310 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1311 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1312 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1313}
1314
1315/**
1316 * intel_enable_pll - enable a PLL
1317 * @dev_priv: i915 private structure
1318 * @pipe: pipe PLL to enable
1319 *
1320 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1321 * make sure the PLL reg is writable first though, since the panel write
1322 * protect mechanism may be enabled.
1323 *
1324 * Note! This is for pre-ILK only.
1325 */
1326static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1327{
1328 int reg;
1329 u32 val;
1330
1331 /* No really, not for ILK+ */
1332 BUG_ON(dev_priv->info->gen >= 5);
1333
1334 /* PLL is protected by panel, make sure we can write it */
1335 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1336 assert_panel_unlocked(dev_priv, pipe);
1337
1338 reg = DPLL(pipe);
1339 val = I915_READ(reg);
1340 val |= DPLL_VCO_ENABLE;
1341
1342 /* We do this three times for luck */
1343 I915_WRITE(reg, val);
1344 POSTING_READ(reg);
1345 udelay(150); /* wait for warmup */
1346 I915_WRITE(reg, val);
1347 POSTING_READ(reg);
1348 udelay(150); /* wait for warmup */
1349 I915_WRITE(reg, val);
1350 POSTING_READ(reg);
1351 udelay(150); /* wait for warmup */
1352}
1353
1354/**
1355 * intel_disable_pll - disable a PLL
1356 * @dev_priv: i915 private structure
1357 * @pipe: pipe PLL to disable
1358 *
1359 * Disable the PLL for @pipe, making sure the pipe is off first.
1360 *
1361 * Note! This is for pre-ILK only.
1362 */
1363static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1364{
1365 int reg;
1366 u32 val;
1367
1368 /* Don't disable pipe A or pipe A PLLs if needed */
1369 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1370 return;
1371
1372 /* Make sure the pipe isn't still relying on us */
1373 assert_pipe_disabled(dev_priv, pipe);
1374
1375 reg = DPLL(pipe);
1376 val = I915_READ(reg);
1377 val &= ~DPLL_VCO_ENABLE;
1378 I915_WRITE(reg, val);
1379 POSTING_READ(reg);
1380}
1381
1382/**
1383 * intel_enable_pch_pll - enable PCH PLL
1384 * @dev_priv: i915 private structure
1385 * @pipe: pipe PLL to enable
1386 *
1387 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1388 * drives the transcoder clock.
1389 */
1390static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1391 enum pipe pipe)
1392{
1393 int reg;
1394 u32 val;
1395
1396 /* PCH only available on ILK+ */
1397 BUG_ON(dev_priv->info->gen < 5);
1398
1399 /* PCH refclock must be enabled first */
1400 assert_pch_refclk_enabled(dev_priv);
1401
1402 reg = PCH_DPLL(pipe);
1403 val = I915_READ(reg);
1404 val |= DPLL_VCO_ENABLE;
1405 I915_WRITE(reg, val);
1406 POSTING_READ(reg);
1407 udelay(200);
1408}
1409
1410static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1411 enum pipe pipe)
1412{
1413 int reg;
1414 u32 val;
1415
1416 /* PCH only available on ILK+ */
1417 BUG_ON(dev_priv->info->gen < 5);
1418
1419 /* Make sure transcoder isn't still depending on us */
1420 assert_transcoder_disabled(dev_priv, pipe);
1421
1422 reg = PCH_DPLL(pipe);
1423 val = I915_READ(reg);
1424 val &= ~DPLL_VCO_ENABLE;
1425 I915_WRITE(reg, val);
1426 POSTING_READ(reg);
1427 udelay(200);
1428}
1429
1430static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1431 enum pipe pipe)
1432{
1433 int reg;
1434 u32 val;
1435
1436 /* PCH only available on ILK+ */
1437 BUG_ON(dev_priv->info->gen < 5);
1438
1439 /* Make sure PCH DPLL is enabled */
1440 assert_pch_pll_enabled(dev_priv, pipe);
1441
1442 /* FDI must be feeding us bits for PCH ports */
1443 assert_fdi_tx_enabled(dev_priv, pipe);
1444 assert_fdi_rx_enabled(dev_priv, pipe);
1445
1446 reg = TRANSCONF(pipe);
1447 val = I915_READ(reg);
1448 /*
1449 * make the BPC in transcoder be consistent with
1450 * that in pipeconf reg.
1451 */
1452 val &= ~PIPE_BPC_MASK;
1453 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1454 I915_WRITE(reg, val | TRANS_ENABLE);
1455 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1456 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1457}
1458
1459static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1460 enum pipe pipe)
1461{
1462 int reg;
1463 u32 val;
1464
1465 /* FDI relies on the transcoder */
1466 assert_fdi_tx_disabled(dev_priv, pipe);
1467 assert_fdi_rx_disabled(dev_priv, pipe);
1468
1469 /* Ports must be off as well */
1470 assert_pch_ports_disabled(dev_priv, pipe);
1471
1472 reg = TRANSCONF(pipe);
1473 val = I915_READ(reg);
1474 val &= ~TRANS_ENABLE;
1475 I915_WRITE(reg, val);
1476 /* wait for PCH transcoder off, transcoder state */
1477 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1478 DRM_ERROR("failed to disable transcoder\n");
1479}
1480
1481/**
1482 * intel_enable_pipe - enable a pipe, asserting requirements
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe to enable
1485 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1486 *
1487 * Enable @pipe, making sure that various hardware specific requirements
1488 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1489 *
1490 * @pipe should be %PIPE_A or %PIPE_B.
1491 *
1492 * Will wait until the pipe is actually running (i.e. first vblank) before
1493 * returning.
1494 */
1495static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1496 bool pch_port)
1497{
1498 int reg;
1499 u32 val;
1500
1501 /*
1502 * A pipe without a PLL won't actually be able to drive bits from
1503 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1504 * need the check.
1505 */
1506 if (!HAS_PCH_SPLIT(dev_priv->dev))
1507 assert_pll_enabled(dev_priv, pipe);
1508 else {
1509 if (pch_port) {
1510 /* if driving the PCH, we need FDI enabled */
1511 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1512 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1513 }
1514 /* FIXME: assert CPU port conditions for SNB+ */
1515 }
1516
1517 reg = PIPECONF(pipe);
1518 val = I915_READ(reg);
1519 val |= PIPECONF_ENABLE;
1520 I915_WRITE(reg, val);
1521 POSTING_READ(reg);
1522 intel_wait_for_vblank(dev_priv->dev, pipe);
1523}
1524
1525/**
1526 * intel_disable_pipe - disable a pipe, asserting requirements
1527 * @dev_priv: i915 private structure
1528 * @pipe: pipe to disable
1529 *
1530 * Disable @pipe, making sure that various hardware specific requirements
1531 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1532 *
1533 * @pipe should be %PIPE_A or %PIPE_B.
1534 *
1535 * Will wait until the pipe has shut down before returning.
1536 */
1537static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1538 enum pipe pipe)
1539{
1540 int reg;
1541 u32 val;
1542
1543 /*
1544 * Make sure planes won't keep trying to pump pixels to us,
1545 * or we might hang the display.
1546 */
1547 assert_planes_disabled(dev_priv, pipe);
1548
1549 /* Don't disable pipe A or pipe A PLLs if needed */
1550 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1551 return;
1552
1553 reg = PIPECONF(pipe);
1554 val = I915_READ(reg);
1555 val &= ~PIPECONF_ENABLE;
1556 I915_WRITE(reg, val);
1557 POSTING_READ(reg);
1558 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1559}
1560
1561/**
1562 * intel_enable_plane - enable a display plane on a given pipe
1563 * @dev_priv: i915 private structure
1564 * @plane: plane to enable
1565 * @pipe: pipe being fed
1566 *
1567 * Enable @plane on @pipe, making sure that @pipe is running first.
1568 */
1569static void intel_enable_plane(struct drm_i915_private *dev_priv,
1570 enum plane plane, enum pipe pipe)
1571{
1572 int reg;
1573 u32 val;
1574
1575 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1576 assert_pipe_enabled(dev_priv, pipe);
1577
1578 reg = DSPCNTR(plane);
1579 val = I915_READ(reg);
1580 val |= DISPLAY_PLANE_ENABLE;
1581 I915_WRITE(reg, val);
1582 POSTING_READ(reg);
1583 intel_wait_for_vblank(dev_priv->dev, pipe);
1584}
1585
1586/*
1587 * Plane regs are double buffered, going from enabled->disabled needs a
1588 * trigger in order to latch. The display address reg provides this.
1589 */
1590static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1591 enum plane plane)
1592{
1593 u32 reg = DSPADDR(plane);
1594 I915_WRITE(reg, I915_READ(reg));
1595}
1596
1597/**
1598 * intel_disable_plane - disable a display plane
1599 * @dev_priv: i915 private structure
1600 * @plane: plane to disable
1601 * @pipe: pipe consuming the data
1602 *
1603 * Disable @plane; should be an independent operation.
1604 */
1605static void intel_disable_plane(struct drm_i915_private *dev_priv,
1606 enum plane plane, enum pipe pipe)
1607{
1608 int reg;
1609 u32 val;
1610
1611 reg = DSPCNTR(plane);
1612 val = I915_READ(reg);
1613 val &= ~DISPLAY_PLANE_ENABLE;
1614 I915_WRITE(reg, val);
1615 POSTING_READ(reg);
1616 intel_flush_display_plane(dev_priv, plane);
1617 intel_wait_for_vblank(dev_priv->dev, pipe);
1618}
1619
1620static void disable_pch_dp(struct drm_i915_private *dev_priv,
1621 enum pipe pipe, int reg)
1622{
1623 u32 val = I915_READ(reg);
1624 if (DP_PIPE_ENABLED(val, pipe))
1625 I915_WRITE(reg, val & ~DP_PORT_EN);
1626}
1627
1628static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1629 enum pipe pipe, int reg)
1630{
1631 u32 val = I915_READ(reg);
1632 if (HDMI_PIPE_ENABLED(val, pipe))
1633 I915_WRITE(reg, val & ~PORT_ENABLE);
1634}
1635
1636/* Disable any ports connected to this transcoder */
1637static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1638 enum pipe pipe)
1639{
1640 u32 reg, val;
1641
1642 val = I915_READ(PCH_PP_CONTROL);
1643 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1644
1645 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1646 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1647 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1648
1649 reg = PCH_ADPA;
1650 val = I915_READ(reg);
1651 if (ADPA_PIPE_ENABLED(val, pipe))
1652 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1653
1654 reg = PCH_LVDS;
1655 val = I915_READ(reg);
1656 if (LVDS_PIPE_ENABLED(val, pipe)) {
1657 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1658 POSTING_READ(reg);
1659 udelay(100);
1660 }
1661
1662 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1663 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1664 disable_pch_hdmi(dev_priv, pipe, HDMID);
1665}
1666
1061static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 1667static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1062{ 1668{
1063 struct drm_device *dev = crtc->dev; 1669 struct drm_device *dev = crtc->dev;
@@ -1390,7 +1996,7 @@ static void intel_update_fbc(struct drm_device *dev)
1390 * - going to an unsupported config (interlace, pixel multiply, etc.) 1996 * - going to an unsupported config (interlace, pixel multiply, etc.)
1391 */ 1997 */
1392 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { 1998 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1393 if (tmp_crtc->enabled) { 1999 if (tmp_crtc->enabled && tmp_crtc->fb) {
1394 if (crtc) { 2000 if (crtc) {
1395 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); 2001 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1396 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; 2002 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
@@ -1753,8 +2359,13 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1753 struct drm_i915_private *dev_priv = dev->dev_private; 2359 struct drm_i915_private *dev_priv = dev->dev_private;
1754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1755 int pipe = intel_crtc->pipe; 2361 int pipe = intel_crtc->pipe;
2362 int plane = intel_crtc->plane;
1756 u32 reg, temp, tries; 2363 u32 reg, temp, tries;
1757 2364
2365 /* FDI needs bits from pipe & plane first */
2366 assert_pipe_enabled(dev_priv, pipe);
2367 assert_plane_enabled(dev_priv, plane);
2368
1758 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2369 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1759 for train result */ 2370 for train result */
1760 reg = FDI_RX_IMR(pipe); 2371 reg = FDI_RX_IMR(pipe);
@@ -1784,7 +2395,11 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1784 udelay(150); 2395 udelay(150);
1785 2396
1786 /* Ironlake workaround, enable clock pointer after FDI enable*/ 2397 /* Ironlake workaround, enable clock pointer after FDI enable*/
1787 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE); 2398 if (HAS_PCH_IBX(dev)) {
2399 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2400 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2401 FDI_RX_PHASE_SYNC_POINTER_EN);
2402 }
1788 2403
1789 reg = FDI_RX_IIR(pipe); 2404 reg = FDI_RX_IIR(pipe);
1790 for (tries = 0; tries < 5; tries++) { 2405 for (tries = 0; tries < 5; tries++) {
@@ -1834,7 +2449,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1834 2449
1835} 2450}
1836 2451
1837static const int const snb_b_fdi_train_param [] = { 2452static const int snb_b_fdi_train_param [] = {
1838 FDI_LINK_TRAIN_400MV_0DB_SNB_B, 2453 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1839 FDI_LINK_TRAIN_400MV_6DB_SNB_B, 2454 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1840 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, 2455 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
@@ -2003,12 +2618,60 @@ static void ironlake_fdi_enable(struct drm_crtc *crtc)
2003 } 2618 }
2004} 2619}
2005 2620
2006static void intel_flush_display_plane(struct drm_device *dev, 2621static void ironlake_fdi_disable(struct drm_crtc *crtc)
2007 int plane)
2008{ 2622{
2623 struct drm_device *dev = crtc->dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private; 2624 struct drm_i915_private *dev_priv = dev->dev_private;
2010 u32 reg = DSPADDR(plane); 2625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2011 I915_WRITE(reg, I915_READ(reg)); 2626 int pipe = intel_crtc->pipe;
2627 u32 reg, temp;
2628
2629 /* disable CPU FDI tx and PCH FDI rx */
2630 reg = FDI_TX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2633 POSTING_READ(reg);
2634
2635 reg = FDI_RX_CTL(pipe);
2636 temp = I915_READ(reg);
2637 temp &= ~(0x7 << 16);
2638 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2639 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2640
2641 POSTING_READ(reg);
2642 udelay(100);
2643
2644 /* Ironlake workaround, disable clock pointer after downing FDI */
2645 if (HAS_PCH_IBX(dev)) {
2646 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2647 I915_WRITE(FDI_RX_CHICKEN(pipe),
2648 I915_READ(FDI_RX_CHICKEN(pipe) &
2649 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2650 }
2651
2652 /* still set train pattern 1 */
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_LINK_TRAIN_NONE;
2656 temp |= FDI_LINK_TRAIN_PATTERN_1;
2657 I915_WRITE(reg, temp);
2658
2659 reg = FDI_RX_CTL(pipe);
2660 temp = I915_READ(reg);
2661 if (HAS_PCH_CPT(dev)) {
2662 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2663 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2664 } else {
2665 temp &= ~FDI_LINK_TRAIN_NONE;
2666 temp |= FDI_LINK_TRAIN_PATTERN_1;
2667 }
2668 /* BPC in FDI rx is consistent with that in PIPECONF */
2669 temp &= ~(0x07 << 16);
2670 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2671 I915_WRITE(reg, temp);
2672
2673 POSTING_READ(reg);
2674 udelay(100);
2012} 2675}
2013 2676
2014/* 2677/*
@@ -2045,60 +2708,46 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2045 atomic_read(&obj->pending_flip) == 0); 2708 atomic_read(&obj->pending_flip) == 0);
2046} 2709}
2047 2710
2048static void ironlake_crtc_enable(struct drm_crtc *crtc) 2711static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2049{ 2712{
2050 struct drm_device *dev = crtc->dev; 2713 struct drm_device *dev = crtc->dev;
2051 struct drm_i915_private *dev_priv = dev->dev_private; 2714 struct drm_mode_config *mode_config = &dev->mode_config;
2052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2715 struct intel_encoder *encoder;
2053 int pipe = intel_crtc->pipe;
2054 int plane = intel_crtc->plane;
2055 u32 reg, temp;
2056
2057 if (intel_crtc->active)
2058 return;
2059
2060 intel_crtc->active = true;
2061 intel_update_watermarks(dev);
2062
2063 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2064 temp = I915_READ(PCH_LVDS);
2065 if ((temp & LVDS_PORT_EN) == 0)
2066 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2067 }
2068 2716
2069 ironlake_fdi_enable(crtc); 2717 /*
2718 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2719 * must be driven by its own crtc; no sharing is possible.
2720 */
2721 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2722 if (encoder->base.crtc != crtc)
2723 continue;
2070 2724
2071 /* Enable panel fitting for LVDS */ 2725 switch (encoder->type) {
2072 if (dev_priv->pch_pf_size && 2726 case INTEL_OUTPUT_EDP:
2073 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { 2727 if (!intel_encoder_is_pch_edp(&encoder->base))
2074 /* Force use of hard-coded filter coefficients 2728 return false;
2075 * as some pre-programmed values are broken, 2729 continue;
2076 * e.g. x201. 2730 }
2077 */
2078 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2079 PF_ENABLE | PF_FILTER_MED_3x3);
2080 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2081 dev_priv->pch_pf_pos);
2082 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2083 dev_priv->pch_pf_size);
2084 } 2731 }
2085 2732
2086 /* Enable CPU pipe */ 2733 return true;
2087 reg = PIPECONF(pipe); 2734}
2088 temp = I915_READ(reg);
2089 if ((temp & PIPECONF_ENABLE) == 0) {
2090 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2091 POSTING_READ(reg);
2092 intel_wait_for_vblank(dev, intel_crtc->pipe);
2093 }
2094 2735
2095 /* configure and enable CPU plane */ 2736/*
2096 reg = DSPCNTR(plane); 2737 * Enable PCH resources required for PCH ports:
2097 temp = I915_READ(reg); 2738 * - PCH PLLs
2098 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { 2739 * - FDI training & RX/TX
2099 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE); 2740 * - update transcoder timings
2100 intel_flush_display_plane(dev, plane); 2741 * - DP transcoding bits
2101 } 2742 * - transcoder
2743 */
2744static void ironlake_pch_enable(struct drm_crtc *crtc)
2745{
2746 struct drm_device *dev = crtc->dev;
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2749 int pipe = intel_crtc->pipe;
2750 u32 reg, temp;
2102 2751
2103 /* For PCH output, training FDI link */ 2752 /* For PCH output, training FDI link */
2104 if (IS_GEN6(dev)) 2753 if (IS_GEN6(dev))
@@ -2106,14 +2755,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
2106 else 2755 else
2107 ironlake_fdi_link_train(crtc); 2756 ironlake_fdi_link_train(crtc);
2108 2757
2109 /* enable PCH DPLL */ 2758 intel_enable_pch_pll(dev_priv, pipe);
2110 reg = PCH_DPLL(pipe);
2111 temp = I915_READ(reg);
2112 if ((temp & DPLL_VCO_ENABLE) == 0) {
2113 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2114 POSTING_READ(reg);
2115 udelay(200);
2116 }
2117 2759
2118 if (HAS_PCH_CPT(dev)) { 2760 if (HAS_PCH_CPT(dev)) {
2119 /* Be sure PCH DPLL SEL is set */ 2761 /* Be sure PCH DPLL SEL is set */
@@ -2125,7 +2767,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
2125 I915_WRITE(PCH_DPLL_SEL, temp); 2767 I915_WRITE(PCH_DPLL_SEL, temp);
2126 } 2768 }
2127 2769
2128 /* set transcoder timing */ 2770 /* set transcoder timing, panel must allow it */
2771 assert_panel_unlocked(dev_priv, pipe);
2129 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); 2772 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2130 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); 2773 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2131 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); 2774 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
@@ -2172,18 +2815,55 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
2172 I915_WRITE(reg, temp); 2815 I915_WRITE(reg, temp);
2173 } 2816 }
2174 2817
2175 /* enable PCH transcoder */ 2818 intel_enable_transcoder(dev_priv, pipe);
2176 reg = TRANSCONF(pipe); 2819}
2177 temp = I915_READ(reg); 2820
2178 /* 2821static void ironlake_crtc_enable(struct drm_crtc *crtc)
2179 * make the BPC in transcoder be consistent with 2822{
2180 * that in pipeconf reg. 2823 struct drm_device *dev = crtc->dev;
2181 */ 2824 struct drm_i915_private *dev_priv = dev->dev_private;
2182 temp &= ~PIPE_BPC_MASK; 2825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2183 temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; 2826 int pipe = intel_crtc->pipe;
2184 I915_WRITE(reg, temp | TRANS_ENABLE); 2827 int plane = intel_crtc->plane;
2185 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) 2828 u32 temp;
2186 DRM_ERROR("failed to enable transcoder %d\n", pipe); 2829 bool is_pch_port;
2830
2831 if (intel_crtc->active)
2832 return;
2833
2834 intel_crtc->active = true;
2835 intel_update_watermarks(dev);
2836
2837 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2838 temp = I915_READ(PCH_LVDS);
2839 if ((temp & LVDS_PORT_EN) == 0)
2840 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2841 }
2842
2843 is_pch_port = intel_crtc_driving_pch(crtc);
2844
2845 if (is_pch_port)
2846 ironlake_fdi_enable(crtc);
2847 else
2848 ironlake_fdi_disable(crtc);
2849
2850 /* Enable panel fitting for LVDS */
2851 if (dev_priv->pch_pf_size &&
2852 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2853 /* Force use of hard-coded filter coefficients
2854 * as some pre-programmed values are broken,
2855 * e.g. x201.
2856 */
2857 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2858 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2859 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2860 }
2861
2862 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2863 intel_enable_plane(dev_priv, plane, pipe);
2864
2865 if (is_pch_port)
2866 ironlake_pch_enable(crtc);
2187 2867
2188 intel_crtc_load_lut(crtc); 2868 intel_crtc_load_lut(crtc);
2189 intel_update_fbc(dev); 2869 intel_update_fbc(dev);
@@ -2206,116 +2886,58 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
2206 drm_vblank_off(dev, pipe); 2886 drm_vblank_off(dev, pipe);
2207 intel_crtc_update_cursor(crtc, false); 2887 intel_crtc_update_cursor(crtc, false);
2208 2888
2209 /* Disable display plane */ 2889 intel_disable_plane(dev_priv, plane, pipe);
2210 reg = DSPCNTR(plane);
2211 temp = I915_READ(reg);
2212 if (temp & DISPLAY_PLANE_ENABLE) {
2213 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2214 intel_flush_display_plane(dev, plane);
2215 }
2216 2890
2217 if (dev_priv->cfb_plane == plane && 2891 if (dev_priv->cfb_plane == plane &&
2218 dev_priv->display.disable_fbc) 2892 dev_priv->display.disable_fbc)
2219 dev_priv->display.disable_fbc(dev); 2893 dev_priv->display.disable_fbc(dev);
2220 2894
2221 /* disable cpu pipe, disable after all planes disabled */ 2895 intel_disable_pipe(dev_priv, pipe);
2222 reg = PIPECONF(pipe);
2223 temp = I915_READ(reg);
2224 if (temp & PIPECONF_ENABLE) {
2225 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2226 POSTING_READ(reg);
2227 /* wait for cpu pipe off, pipe state */
2228 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2229 }
2230 2896
2231 /* Disable PF */ 2897 /* Disable PF */
2232 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0); 2898 I915_WRITE(PF_CTL(pipe), 0);
2233 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0); 2899 I915_WRITE(PF_WIN_SZ(pipe), 0);
2234
2235 /* disable CPU FDI tx and PCH FDI rx */
2236 reg = FDI_TX_CTL(pipe);
2237 temp = I915_READ(reg);
2238 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2239 POSTING_READ(reg);
2240
2241 reg = FDI_RX_CTL(pipe);
2242 temp = I915_READ(reg);
2243 temp &= ~(0x7 << 16);
2244 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2245 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2246 2900
2247 POSTING_READ(reg); 2901 ironlake_fdi_disable(crtc);
2248 udelay(100);
2249 2902
2250 /* Ironlake workaround, disable clock pointer after downing FDI */ 2903 /* This is a horrible layering violation; we should be doing this in
2251 if (HAS_PCH_IBX(dev)) 2904 * the connector/encoder ->prepare instead, but we don't always have
2252 I915_WRITE(FDI_RX_CHICKEN(pipe), 2905 * enough information there about the config to know whether it will
2253 I915_READ(FDI_RX_CHICKEN(pipe) & 2906 * actually be necessary or just cause undesired flicker.
2254 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE)); 2907 */
2255 2908 intel_disable_pch_ports(dev_priv, pipe);
2256 /* still set train pattern 1 */
2257 reg = FDI_TX_CTL(pipe);
2258 temp = I915_READ(reg);
2259 temp &= ~FDI_LINK_TRAIN_NONE;
2260 temp |= FDI_LINK_TRAIN_PATTERN_1;
2261 I915_WRITE(reg, temp);
2262
2263 reg = FDI_RX_CTL(pipe);
2264 temp = I915_READ(reg);
2265 if (HAS_PCH_CPT(dev)) {
2266 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2267 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2268 } else {
2269 temp &= ~FDI_LINK_TRAIN_NONE;
2270 temp |= FDI_LINK_TRAIN_PATTERN_1;
2271 }
2272 /* BPC in FDI rx is consistent with that in PIPECONF */
2273 temp &= ~(0x07 << 16);
2274 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2275 I915_WRITE(reg, temp);
2276
2277 POSTING_READ(reg);
2278 udelay(100);
2279
2280 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2281 temp = I915_READ(PCH_LVDS);
2282 if (temp & LVDS_PORT_EN) {
2283 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2284 POSTING_READ(PCH_LVDS);
2285 udelay(100);
2286 }
2287 }
2288 2909
2289 /* disable PCH transcoder */ 2910 intel_disable_transcoder(dev_priv, pipe);
2290 reg = TRANSCONF(plane);
2291 temp = I915_READ(reg);
2292 if (temp & TRANS_ENABLE) {
2293 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2294 /* wait for PCH transcoder off, transcoder state */
2295 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2296 DRM_ERROR("failed to disable transcoder\n");
2297 }
2298 2911
2299 if (HAS_PCH_CPT(dev)) { 2912 if (HAS_PCH_CPT(dev)) {
2300 /* disable TRANS_DP_CTL */ 2913 /* disable TRANS_DP_CTL */
2301 reg = TRANS_DP_CTL(pipe); 2914 reg = TRANS_DP_CTL(pipe);
2302 temp = I915_READ(reg); 2915 temp = I915_READ(reg);
2303 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); 2916 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2917 temp |= TRANS_DP_PORT_SEL_NONE;
2304 I915_WRITE(reg, temp); 2918 I915_WRITE(reg, temp);
2305 2919
2306 /* disable DPLL_SEL */ 2920 /* disable DPLL_SEL */
2307 temp = I915_READ(PCH_DPLL_SEL); 2921 temp = I915_READ(PCH_DPLL_SEL);
2308 if (pipe == 0) 2922 switch (pipe) {
2309 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); 2923 case 0:
2310 else 2924 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2925 break;
2926 case 1:
2311 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 2927 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2928 break;
2929 case 2:
2930 /* FIXME: manage transcoder PLLs? */
2931 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2932 break;
2933 default:
2934 BUG(); /* wtf */
2935 }
2312 I915_WRITE(PCH_DPLL_SEL, temp); 2936 I915_WRITE(PCH_DPLL_SEL, temp);
2313 } 2937 }
2314 2938
2315 /* disable PCH DPLL */ 2939 /* disable PCH DPLL */
2316 reg = PCH_DPLL(pipe); 2940 intel_disable_pch_pll(dev_priv, pipe);
2317 temp = I915_READ(reg);
2318 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2319 2941
2320 /* Switch from PCDclk to Rawclk */ 2942 /* Switch from PCDclk to Rawclk */
2321 reg = FDI_RX_CTL(pipe); 2943 reg = FDI_RX_CTL(pipe);
@@ -2390,7 +3012,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
2390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391 int pipe = intel_crtc->pipe; 3013 int pipe = intel_crtc->pipe;
2392 int plane = intel_crtc->plane; 3014 int plane = intel_crtc->plane;
2393 u32 reg, temp;
2394 3015
2395 if (intel_crtc->active) 3016 if (intel_crtc->active)
2396 return; 3017 return;
@@ -2398,42 +3019,9 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
2398 intel_crtc->active = true; 3019 intel_crtc->active = true;
2399 intel_update_watermarks(dev); 3020 intel_update_watermarks(dev);
2400 3021
2401 /* Enable the DPLL */ 3022 intel_enable_pll(dev_priv, pipe);
2402 reg = DPLL(pipe); 3023 intel_enable_pipe(dev_priv, pipe, false);
2403 temp = I915_READ(reg); 3024 intel_enable_plane(dev_priv, plane, pipe);
2404 if ((temp & DPLL_VCO_ENABLE) == 0) {
2405 I915_WRITE(reg, temp);
2406
2407 /* Wait for the clocks to stabilize. */
2408 POSTING_READ(reg);
2409 udelay(150);
2410
2411 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2412
2413 /* Wait for the clocks to stabilize. */
2414 POSTING_READ(reg);
2415 udelay(150);
2416
2417 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2418
2419 /* Wait for the clocks to stabilize. */
2420 POSTING_READ(reg);
2421 udelay(150);
2422 }
2423
2424 /* Enable the pipe */
2425 reg = PIPECONF(pipe);
2426 temp = I915_READ(reg);
2427 if ((temp & PIPECONF_ENABLE) == 0)
2428 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2429
2430 /* Enable the plane */
2431 reg = DSPCNTR(plane);
2432 temp = I915_READ(reg);
2433 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2434 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2435 intel_flush_display_plane(dev, plane);
2436 }
2437 3025
2438 intel_crtc_load_lut(crtc); 3026 intel_crtc_load_lut(crtc);
2439 intel_update_fbc(dev); 3027 intel_update_fbc(dev);
@@ -2450,7 +3038,6 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
2450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2451 int pipe = intel_crtc->pipe; 3039 int pipe = intel_crtc->pipe;
2452 int plane = intel_crtc->plane; 3040 int plane = intel_crtc->plane;
2453 u32 reg, temp;
2454 3041
2455 if (!intel_crtc->active) 3042 if (!intel_crtc->active)
2456 return; 3043 return;
@@ -2465,45 +3052,10 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
2465 dev_priv->display.disable_fbc) 3052 dev_priv->display.disable_fbc)
2466 dev_priv->display.disable_fbc(dev); 3053 dev_priv->display.disable_fbc(dev);
2467 3054
2468 /* Disable display plane */ 3055 intel_disable_plane(dev_priv, plane, pipe);
2469 reg = DSPCNTR(plane); 3056 intel_disable_pipe(dev_priv, pipe);
2470 temp = I915_READ(reg); 3057 intel_disable_pll(dev_priv, pipe);
2471 if (temp & DISPLAY_PLANE_ENABLE) {
2472 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2473 /* Flush the plane changes */
2474 intel_flush_display_plane(dev, plane);
2475
2476 /* Wait for vblank for the disable to take effect */
2477 if (IS_GEN2(dev))
2478 intel_wait_for_vblank(dev, pipe);
2479 }
2480
2481 /* Don't disable pipe A or pipe A PLLs if needed */
2482 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2483 goto done;
2484
2485 /* Next, disable display pipes */
2486 reg = PIPECONF(pipe);
2487 temp = I915_READ(reg);
2488 if (temp & PIPECONF_ENABLE) {
2489 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2490
2491 /* Wait for the pipe to turn off */
2492 POSTING_READ(reg);
2493 intel_wait_for_pipe_off(dev, pipe);
2494 }
2495
2496 reg = DPLL(pipe);
2497 temp = I915_READ(reg);
2498 if (temp & DPLL_VCO_ENABLE) {
2499 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2500 3058
2501 /* Wait for the clocks to turn off. */
2502 POSTING_READ(reg);
2503 udelay(150);
2504 }
2505
2506done:
2507 intel_crtc->active = false; 3059 intel_crtc->active = false;
2508 intel_update_fbc(dev); 3060 intel_update_fbc(dev);
2509 intel_update_watermarks(dev); 3061 intel_update_watermarks(dev);
@@ -2565,7 +3117,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2565 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; 3117 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2566 break; 3118 break;
2567 default: 3119 default:
2568 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); 3120 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
2569 break; 3121 break;
2570 } 3122 }
2571} 3123}
@@ -2762,77 +3314,77 @@ struct intel_watermark_params {
2762}; 3314};
2763 3315
2764/* Pineview has different values for various configs */ 3316/* Pineview has different values for various configs */
2765static struct intel_watermark_params pineview_display_wm = { 3317static const struct intel_watermark_params pineview_display_wm = {
2766 PINEVIEW_DISPLAY_FIFO, 3318 PINEVIEW_DISPLAY_FIFO,
2767 PINEVIEW_MAX_WM, 3319 PINEVIEW_MAX_WM,
2768 PINEVIEW_DFT_WM, 3320 PINEVIEW_DFT_WM,
2769 PINEVIEW_GUARD_WM, 3321 PINEVIEW_GUARD_WM,
2770 PINEVIEW_FIFO_LINE_SIZE 3322 PINEVIEW_FIFO_LINE_SIZE
2771}; 3323};
2772static struct intel_watermark_params pineview_display_hplloff_wm = { 3324static const struct intel_watermark_params pineview_display_hplloff_wm = {
2773 PINEVIEW_DISPLAY_FIFO, 3325 PINEVIEW_DISPLAY_FIFO,
2774 PINEVIEW_MAX_WM, 3326 PINEVIEW_MAX_WM,
2775 PINEVIEW_DFT_HPLLOFF_WM, 3327 PINEVIEW_DFT_HPLLOFF_WM,
2776 PINEVIEW_GUARD_WM, 3328 PINEVIEW_GUARD_WM,
2777 PINEVIEW_FIFO_LINE_SIZE 3329 PINEVIEW_FIFO_LINE_SIZE
2778}; 3330};
2779static struct intel_watermark_params pineview_cursor_wm = { 3331static const struct intel_watermark_params pineview_cursor_wm = {
2780 PINEVIEW_CURSOR_FIFO, 3332 PINEVIEW_CURSOR_FIFO,
2781 PINEVIEW_CURSOR_MAX_WM, 3333 PINEVIEW_CURSOR_MAX_WM,
2782 PINEVIEW_CURSOR_DFT_WM, 3334 PINEVIEW_CURSOR_DFT_WM,
2783 PINEVIEW_CURSOR_GUARD_WM, 3335 PINEVIEW_CURSOR_GUARD_WM,
2784 PINEVIEW_FIFO_LINE_SIZE, 3336 PINEVIEW_FIFO_LINE_SIZE,
2785}; 3337};
2786static struct intel_watermark_params pineview_cursor_hplloff_wm = { 3338static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
2787 PINEVIEW_CURSOR_FIFO, 3339 PINEVIEW_CURSOR_FIFO,
2788 PINEVIEW_CURSOR_MAX_WM, 3340 PINEVIEW_CURSOR_MAX_WM,
2789 PINEVIEW_CURSOR_DFT_WM, 3341 PINEVIEW_CURSOR_DFT_WM,
2790 PINEVIEW_CURSOR_GUARD_WM, 3342 PINEVIEW_CURSOR_GUARD_WM,
2791 PINEVIEW_FIFO_LINE_SIZE 3343 PINEVIEW_FIFO_LINE_SIZE
2792}; 3344};
2793static struct intel_watermark_params g4x_wm_info = { 3345static const struct intel_watermark_params g4x_wm_info = {
2794 G4X_FIFO_SIZE, 3346 G4X_FIFO_SIZE,
2795 G4X_MAX_WM, 3347 G4X_MAX_WM,
2796 G4X_MAX_WM, 3348 G4X_MAX_WM,
2797 2, 3349 2,
2798 G4X_FIFO_LINE_SIZE, 3350 G4X_FIFO_LINE_SIZE,
2799}; 3351};
2800static struct intel_watermark_params g4x_cursor_wm_info = { 3352static const struct intel_watermark_params g4x_cursor_wm_info = {
2801 I965_CURSOR_FIFO, 3353 I965_CURSOR_FIFO,
2802 I965_CURSOR_MAX_WM, 3354 I965_CURSOR_MAX_WM,
2803 I965_CURSOR_DFT_WM, 3355 I965_CURSOR_DFT_WM,
2804 2, 3356 2,
2805 G4X_FIFO_LINE_SIZE, 3357 G4X_FIFO_LINE_SIZE,
2806}; 3358};
2807static struct intel_watermark_params i965_cursor_wm_info = { 3359static const struct intel_watermark_params i965_cursor_wm_info = {
2808 I965_CURSOR_FIFO, 3360 I965_CURSOR_FIFO,
2809 I965_CURSOR_MAX_WM, 3361 I965_CURSOR_MAX_WM,
2810 I965_CURSOR_DFT_WM, 3362 I965_CURSOR_DFT_WM,
2811 2, 3363 2,
2812 I915_FIFO_LINE_SIZE, 3364 I915_FIFO_LINE_SIZE,
2813}; 3365};
2814static struct intel_watermark_params i945_wm_info = { 3366static const struct intel_watermark_params i945_wm_info = {
2815 I945_FIFO_SIZE, 3367 I945_FIFO_SIZE,
2816 I915_MAX_WM, 3368 I915_MAX_WM,
2817 1, 3369 1,
2818 2, 3370 2,
2819 I915_FIFO_LINE_SIZE 3371 I915_FIFO_LINE_SIZE
2820}; 3372};
2821static struct intel_watermark_params i915_wm_info = { 3373static const struct intel_watermark_params i915_wm_info = {
2822 I915_FIFO_SIZE, 3374 I915_FIFO_SIZE,
2823 I915_MAX_WM, 3375 I915_MAX_WM,
2824 1, 3376 1,
2825 2, 3377 2,
2826 I915_FIFO_LINE_SIZE 3378 I915_FIFO_LINE_SIZE
2827}; 3379};
2828static struct intel_watermark_params i855_wm_info = { 3380static const struct intel_watermark_params i855_wm_info = {
2829 I855GM_FIFO_SIZE, 3381 I855GM_FIFO_SIZE,
2830 I915_MAX_WM, 3382 I915_MAX_WM,
2831 1, 3383 1,
2832 2, 3384 2,
2833 I830_FIFO_LINE_SIZE 3385 I830_FIFO_LINE_SIZE
2834}; 3386};
2835static struct intel_watermark_params i830_wm_info = { 3387static const struct intel_watermark_params i830_wm_info = {
2836 I830_FIFO_SIZE, 3388 I830_FIFO_SIZE,
2837 I915_MAX_WM, 3389 I915_MAX_WM,
2838 1, 3390 1,
@@ -2840,31 +3392,28 @@ static struct intel_watermark_params i830_wm_info = {
2840 I830_FIFO_LINE_SIZE 3392 I830_FIFO_LINE_SIZE
2841}; 3393};
2842 3394
2843static struct intel_watermark_params ironlake_display_wm_info = { 3395static const struct intel_watermark_params ironlake_display_wm_info = {
2844 ILK_DISPLAY_FIFO, 3396 ILK_DISPLAY_FIFO,
2845 ILK_DISPLAY_MAXWM, 3397 ILK_DISPLAY_MAXWM,
2846 ILK_DISPLAY_DFTWM, 3398 ILK_DISPLAY_DFTWM,
2847 2, 3399 2,
2848 ILK_FIFO_LINE_SIZE 3400 ILK_FIFO_LINE_SIZE
2849}; 3401};
2850 3402static const struct intel_watermark_params ironlake_cursor_wm_info = {
2851static struct intel_watermark_params ironlake_cursor_wm_info = {
2852 ILK_CURSOR_FIFO, 3403 ILK_CURSOR_FIFO,
2853 ILK_CURSOR_MAXWM, 3404 ILK_CURSOR_MAXWM,
2854 ILK_CURSOR_DFTWM, 3405 ILK_CURSOR_DFTWM,
2855 2, 3406 2,
2856 ILK_FIFO_LINE_SIZE 3407 ILK_FIFO_LINE_SIZE
2857}; 3408};
2858 3409static const struct intel_watermark_params ironlake_display_srwm_info = {
2859static struct intel_watermark_params ironlake_display_srwm_info = {
2860 ILK_DISPLAY_SR_FIFO, 3410 ILK_DISPLAY_SR_FIFO,
2861 ILK_DISPLAY_MAX_SRWM, 3411 ILK_DISPLAY_MAX_SRWM,
2862 ILK_DISPLAY_DFT_SRWM, 3412 ILK_DISPLAY_DFT_SRWM,
2863 2, 3413 2,
2864 ILK_FIFO_LINE_SIZE 3414 ILK_FIFO_LINE_SIZE
2865}; 3415};
2866 3416static const struct intel_watermark_params ironlake_cursor_srwm_info = {
2867static struct intel_watermark_params ironlake_cursor_srwm_info = {
2868 ILK_CURSOR_SR_FIFO, 3417 ILK_CURSOR_SR_FIFO,
2869 ILK_CURSOR_MAX_SRWM, 3418 ILK_CURSOR_MAX_SRWM,
2870 ILK_CURSOR_DFT_SRWM, 3419 ILK_CURSOR_DFT_SRWM,
@@ -2872,31 +3421,28 @@ static struct intel_watermark_params ironlake_cursor_srwm_info = {
2872 ILK_FIFO_LINE_SIZE 3421 ILK_FIFO_LINE_SIZE
2873}; 3422};
2874 3423
2875static struct intel_watermark_params sandybridge_display_wm_info = { 3424static const struct intel_watermark_params sandybridge_display_wm_info = {
2876 SNB_DISPLAY_FIFO, 3425 SNB_DISPLAY_FIFO,
2877 SNB_DISPLAY_MAXWM, 3426 SNB_DISPLAY_MAXWM,
2878 SNB_DISPLAY_DFTWM, 3427 SNB_DISPLAY_DFTWM,
2879 2, 3428 2,
2880 SNB_FIFO_LINE_SIZE 3429 SNB_FIFO_LINE_SIZE
2881}; 3430};
2882 3431static const struct intel_watermark_params sandybridge_cursor_wm_info = {
2883static struct intel_watermark_params sandybridge_cursor_wm_info = {
2884 SNB_CURSOR_FIFO, 3432 SNB_CURSOR_FIFO,
2885 SNB_CURSOR_MAXWM, 3433 SNB_CURSOR_MAXWM,
2886 SNB_CURSOR_DFTWM, 3434 SNB_CURSOR_DFTWM,
2887 2, 3435 2,
2888 SNB_FIFO_LINE_SIZE 3436 SNB_FIFO_LINE_SIZE
2889}; 3437};
2890 3438static const struct intel_watermark_params sandybridge_display_srwm_info = {
2891static struct intel_watermark_params sandybridge_display_srwm_info = {
2892 SNB_DISPLAY_SR_FIFO, 3439 SNB_DISPLAY_SR_FIFO,
2893 SNB_DISPLAY_MAX_SRWM, 3440 SNB_DISPLAY_MAX_SRWM,
2894 SNB_DISPLAY_DFT_SRWM, 3441 SNB_DISPLAY_DFT_SRWM,
2895 2, 3442 2,
2896 SNB_FIFO_LINE_SIZE 3443 SNB_FIFO_LINE_SIZE
2897}; 3444};
2898 3445static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
2899static struct intel_watermark_params sandybridge_cursor_srwm_info = {
2900 SNB_CURSOR_SR_FIFO, 3446 SNB_CURSOR_SR_FIFO,
2901 SNB_CURSOR_MAX_SRWM, 3447 SNB_CURSOR_MAX_SRWM,
2902 SNB_CURSOR_DFT_SRWM, 3448 SNB_CURSOR_DFT_SRWM,
@@ -2924,7 +3470,8 @@ static struct intel_watermark_params sandybridge_cursor_srwm_info = {
2924 * will occur, and a display engine hang could result. 3470 * will occur, and a display engine hang could result.
2925 */ 3471 */
2926static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 3472static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2927 struct intel_watermark_params *wm, 3473 const struct intel_watermark_params *wm,
3474 int fifo_size,
2928 int pixel_size, 3475 int pixel_size,
2929 unsigned long latency_ns) 3476 unsigned long latency_ns)
2930{ 3477{
@@ -2942,7 +3489,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2942 3489
2943 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); 3490 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2944 3491
2945 wm_size = wm->fifo_size - (entries_required + wm->guard_size); 3492 wm_size = fifo_size - (entries_required + wm->guard_size);
2946 3493
2947 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); 3494 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2948 3495
@@ -3115,15 +3662,28 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
3115 return size; 3662 return size;
3116} 3663}
3117 3664
3118static void pineview_update_wm(struct drm_device *dev, int planea_clock, 3665static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3119 int planeb_clock, int sr_hdisplay, int unused, 3666{
3120 int pixel_size) 3667 struct drm_crtc *crtc, *enabled = NULL;
3668
3669 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3670 if (crtc->enabled && crtc->fb) {
3671 if (enabled)
3672 return NULL;
3673 enabled = crtc;
3674 }
3675 }
3676
3677 return enabled;
3678}
3679
3680static void pineview_update_wm(struct drm_device *dev)
3121{ 3681{
3122 struct drm_i915_private *dev_priv = dev->dev_private; 3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 struct drm_crtc *crtc;
3123 const struct cxsr_latency *latency; 3684 const struct cxsr_latency *latency;
3124 u32 reg; 3685 u32 reg;
3125 unsigned long wm; 3686 unsigned long wm;
3126 int sr_clock;
3127 3687
3128 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 3688 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3129 dev_priv->fsb_freq, dev_priv->mem_freq); 3689 dev_priv->fsb_freq, dev_priv->mem_freq);
@@ -3133,11 +3693,14 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3133 return; 3693 return;
3134 } 3694 }
3135 3695
3136 if (!planea_clock || !planeb_clock) { 3696 crtc = single_enabled_crtc(dev);
3137 sr_clock = planea_clock ? planea_clock : planeb_clock; 3697 if (crtc) {
3698 int clock = crtc->mode.clock;
3699 int pixel_size = crtc->fb->bits_per_pixel / 8;
3138 3700
3139 /* Display SR */ 3701 /* Display SR */
3140 wm = intel_calculate_wm(sr_clock, &pineview_display_wm, 3702 wm = intel_calculate_wm(clock, &pineview_display_wm,
3703 pineview_display_wm.fifo_size,
3141 pixel_size, latency->display_sr); 3704 pixel_size, latency->display_sr);
3142 reg = I915_READ(DSPFW1); 3705 reg = I915_READ(DSPFW1);
3143 reg &= ~DSPFW_SR_MASK; 3706 reg &= ~DSPFW_SR_MASK;
@@ -3146,7 +3709,8 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3146 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 3709 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3147 3710
3148 /* cursor SR */ 3711 /* cursor SR */
3149 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm, 3712 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3713 pineview_display_wm.fifo_size,
3150 pixel_size, latency->cursor_sr); 3714 pixel_size, latency->cursor_sr);
3151 reg = I915_READ(DSPFW3); 3715 reg = I915_READ(DSPFW3);
3152 reg &= ~DSPFW_CURSOR_SR_MASK; 3716 reg &= ~DSPFW_CURSOR_SR_MASK;
@@ -3154,7 +3718,8 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3154 I915_WRITE(DSPFW3, reg); 3718 I915_WRITE(DSPFW3, reg);
3155 3719
3156 /* Display HPLL off SR */ 3720 /* Display HPLL off SR */
3157 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm, 3721 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3722 pineview_display_hplloff_wm.fifo_size,
3158 pixel_size, latency->display_hpll_disable); 3723 pixel_size, latency->display_hpll_disable);
3159 reg = I915_READ(DSPFW3); 3724 reg = I915_READ(DSPFW3);
3160 reg &= ~DSPFW_HPLL_SR_MASK; 3725 reg &= ~DSPFW_HPLL_SR_MASK;
@@ -3162,7 +3727,8 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3162 I915_WRITE(DSPFW3, reg); 3727 I915_WRITE(DSPFW3, reg);
3163 3728
3164 /* cursor HPLL off SR */ 3729 /* cursor HPLL off SR */
3165 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm, 3730 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3731 pineview_display_hplloff_wm.fifo_size,
3166 pixel_size, latency->cursor_hpll_disable); 3732 pixel_size, latency->cursor_hpll_disable);
3167 reg = I915_READ(DSPFW3); 3733 reg = I915_READ(DSPFW3);
3168 reg &= ~DSPFW_HPLL_CURSOR_MASK; 3734 reg &= ~DSPFW_HPLL_CURSOR_MASK;
@@ -3180,125 +3746,229 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3180 } 3746 }
3181} 3747}
3182 3748
3183static void g4x_update_wm(struct drm_device *dev, int planea_clock, 3749static bool g4x_compute_wm0(struct drm_device *dev,
3184 int planeb_clock, int sr_hdisplay, int sr_htotal, 3750 int plane,
3185 int pixel_size) 3751 const struct intel_watermark_params *display,
3752 int display_latency_ns,
3753 const struct intel_watermark_params *cursor,
3754 int cursor_latency_ns,
3755 int *plane_wm,
3756 int *cursor_wm)
3186{ 3757{
3187 struct drm_i915_private *dev_priv = dev->dev_private; 3758 struct drm_crtc *crtc;
3188 int total_size, cacheline_size; 3759 int htotal, hdisplay, clock, pixel_size;
3189 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr; 3760 int line_time_us, line_count;
3190 struct intel_watermark_params planea_params, planeb_params; 3761 int entries, tlb_miss;
3191 unsigned long line_time_us;
3192 int sr_clock, sr_entries = 0, entries_required;
3193 3762
3194 /* Create copies of the base settings for each pipe */ 3763 crtc = intel_get_crtc_for_plane(dev, plane);
3195 planea_params = planeb_params = g4x_wm_info; 3764 if (crtc->fb == NULL || !crtc->enabled)
3765 return false;
3196 3766
3197 /* Grab a couple of global values before we overwrite them */ 3767 htotal = crtc->mode.htotal;
3198 total_size = planea_params.fifo_size; 3768 hdisplay = crtc->mode.hdisplay;
3199 cacheline_size = planea_params.cacheline_size; 3769 clock = crtc->mode.clock;
3770 pixel_size = crtc->fb->bits_per_pixel / 8;
3200 3771
3201 /* 3772 /* Use the small buffer method to calculate plane watermark */
3202 * Note: we need to make sure we don't overflow for various clock & 3773 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3203 * latency values. 3774 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3204 * clocks go from a few thousand to several hundred thousand. 3775 if (tlb_miss > 0)
3205 * latency is usually a few thousand 3776 entries += tlb_miss;
3206 */ 3777 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3207 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) / 3778 *plane_wm = entries + display->guard_size;
3208 1000; 3779 if (*plane_wm > (int)display->max_wm)
3209 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); 3780 *plane_wm = display->max_wm;
3210 planea_wm = entries_required + planea_params.guard_size;
3211 3781
3212 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) / 3782 /* Use the large buffer method to calculate cursor watermark */
3213 1000; 3783 line_time_us = ((htotal * 1000) / clock);
3214 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); 3784 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3215 planeb_wm = entries_required + planeb_params.guard_size; 3785 entries = line_count * 64 * pixel_size;
3786 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3787 if (tlb_miss > 0)
3788 entries += tlb_miss;
3789 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3790 *cursor_wm = entries + cursor->guard_size;
3791 if (*cursor_wm > (int)cursor->max_wm)
3792 *cursor_wm = (int)cursor->max_wm;
3793
3794 return true;
3795}
3216 3796
3217 cursora_wm = cursorb_wm = 16; 3797/*
3218 cursor_sr = 32; 3798 * Check the wm result.
3799 *
3800 * If any calculated watermark values is larger than the maximum value that
3801 * can be programmed into the associated watermark register, that watermark
3802 * must be disabled.
3803 */
3804static bool g4x_check_srwm(struct drm_device *dev,
3805 int display_wm, int cursor_wm,
3806 const struct intel_watermark_params *display,
3807 const struct intel_watermark_params *cursor)
3808{
3809 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3810 display_wm, cursor_wm);
3219 3811
3220 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 3812 if (display_wm > display->max_wm) {
3813 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3814 display_wm, display->max_wm);
3815 return false;
3816 }
3221 3817
3222 /* Calc sr entries for one plane configs */ 3818 if (cursor_wm > cursor->max_wm) {
3223 if (sr_hdisplay && (!planea_clock || !planeb_clock)) { 3819 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3224 /* self-refresh has much higher latency */ 3820 cursor_wm, cursor->max_wm);
3225 static const int sr_latency_ns = 12000; 3821 return false;
3822 }
3226 3823
3227 sr_clock = planea_clock ? planea_clock : planeb_clock; 3824 if (!(display_wm || cursor_wm)) {
3228 line_time_us = ((sr_htotal * 1000) / sr_clock); 3825 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3826 return false;
3827 }
3229 3828
3230 /* Use ns/us then divide to preserve precision */ 3829 return true;
3231 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 3830}
3232 pixel_size * sr_hdisplay;
3233 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3234
3235 entries_required = (((sr_latency_ns / line_time_us) +
3236 1000) / 1000) * pixel_size * 64;
3237 entries_required = DIV_ROUND_UP(entries_required,
3238 g4x_cursor_wm_info.cacheline_size);
3239 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3240
3241 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3242 cursor_sr = g4x_cursor_wm_info.max_wm;
3243 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3244 "cursor %d\n", sr_entries, cursor_sr);
3245 3831
3246 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 3832static bool g4x_compute_srwm(struct drm_device *dev,
3247 } else { 3833 int plane,
3248 /* Turn off self refresh if both pipes are enabled */ 3834 int latency_ns,
3249 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) 3835 const struct intel_watermark_params *display,
3250 & ~FW_BLC_SELF_EN); 3836 const struct intel_watermark_params *cursor,
3837 int *display_wm, int *cursor_wm)
3838{
3839 struct drm_crtc *crtc;
3840 int hdisplay, htotal, pixel_size, clock;
3841 unsigned long line_time_us;
3842 int line_count, line_size;
3843 int small, large;
3844 int entries;
3845
3846 if (!latency_ns) {
3847 *display_wm = *cursor_wm = 0;
3848 return false;
3251 } 3849 }
3252 3850
3253 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", 3851 crtc = intel_get_crtc_for_plane(dev, plane);
3254 planea_wm, planeb_wm, sr_entries); 3852 hdisplay = crtc->mode.hdisplay;
3853 htotal = crtc->mode.htotal;
3854 clock = crtc->mode.clock;
3855 pixel_size = crtc->fb->bits_per_pixel / 8;
3856
3857 line_time_us = (htotal * 1000) / clock;
3858 line_count = (latency_ns / line_time_us + 1000) / 1000;
3859 line_size = hdisplay * pixel_size;
3255 3860
3256 planea_wm &= 0x3f; 3861 /* Use the minimum of the small and large buffer method for primary */
3257 planeb_wm &= 0x3f; 3862 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3863 large = line_count * line_size;
3258 3864
3259 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) | 3865 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3866 *display_wm = entries + display->guard_size;
3867
3868 /* calculate the self-refresh watermark for display cursor */
3869 entries = line_count * pixel_size * 64;
3870 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3871 *cursor_wm = entries + cursor->guard_size;
3872
3873 return g4x_check_srwm(dev,
3874 *display_wm, *cursor_wm,
3875 display, cursor);
3876}
3877
3878static inline bool single_plane_enabled(unsigned int mask)
3879{
3880 return mask && (mask & -mask) == 0;
3881}
3882
3883static void g4x_update_wm(struct drm_device *dev)
3884{
3885 static const int sr_latency_ns = 12000;
3886 struct drm_i915_private *dev_priv = dev->dev_private;
3887 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3888 int plane_sr, cursor_sr;
3889 unsigned int enabled = 0;
3890
3891 if (g4x_compute_wm0(dev, 0,
3892 &g4x_wm_info, latency_ns,
3893 &g4x_cursor_wm_info, latency_ns,
3894 &planea_wm, &cursora_wm))
3895 enabled |= 1;
3896
3897 if (g4x_compute_wm0(dev, 1,
3898 &g4x_wm_info, latency_ns,
3899 &g4x_cursor_wm_info, latency_ns,
3900 &planeb_wm, &cursorb_wm))
3901 enabled |= 2;
3902
3903 plane_sr = cursor_sr = 0;
3904 if (single_plane_enabled(enabled) &&
3905 g4x_compute_srwm(dev, ffs(enabled) - 1,
3906 sr_latency_ns,
3907 &g4x_wm_info,
3908 &g4x_cursor_wm_info,
3909 &plane_sr, &cursor_sr))
3910 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3911 else
3912 I915_WRITE(FW_BLC_SELF,
3913 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3914
3915 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3916 planea_wm, cursora_wm,
3917 planeb_wm, cursorb_wm,
3918 plane_sr, cursor_sr);
3919
3920 I915_WRITE(DSPFW1,
3921 (plane_sr << DSPFW_SR_SHIFT) |
3260 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 3922 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3261 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm); 3923 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3262 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | 3924 planea_wm);
3925 I915_WRITE(DSPFW2,
3926 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3263 (cursora_wm << DSPFW_CURSORA_SHIFT)); 3927 (cursora_wm << DSPFW_CURSORA_SHIFT));
3264 /* HPLL off in SR has some issues on G4x... disable it */ 3928 /* HPLL off in SR has some issues on G4x... disable it */
3265 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | 3929 I915_WRITE(DSPFW3,
3930 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3266 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 3931 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3267} 3932}
3268 3933
3269static void i965_update_wm(struct drm_device *dev, int planea_clock, 3934static void i965_update_wm(struct drm_device *dev)
3270 int planeb_clock, int sr_hdisplay, int sr_htotal,
3271 int pixel_size)
3272{ 3935{
3273 struct drm_i915_private *dev_priv = dev->dev_private; 3936 struct drm_i915_private *dev_priv = dev->dev_private;
3274 unsigned long line_time_us; 3937 struct drm_crtc *crtc;
3275 int sr_clock, sr_entries, srwm = 1; 3938 int srwm = 1;
3276 int cursor_sr = 16; 3939 int cursor_sr = 16;
3277 3940
3278 /* Calc sr entries for one plane configs */ 3941 /* Calc sr entries for one plane configs */
3279 if (sr_hdisplay && (!planea_clock || !planeb_clock)) { 3942 crtc = single_enabled_crtc(dev);
3943 if (crtc) {
3280 /* self-refresh has much higher latency */ 3944 /* self-refresh has much higher latency */
3281 static const int sr_latency_ns = 12000; 3945 static const int sr_latency_ns = 12000;
3946 int clock = crtc->mode.clock;
3947 int htotal = crtc->mode.htotal;
3948 int hdisplay = crtc->mode.hdisplay;
3949 int pixel_size = crtc->fb->bits_per_pixel / 8;
3950 unsigned long line_time_us;
3951 int entries;
3282 3952
3283 sr_clock = planea_clock ? planea_clock : planeb_clock; 3953 line_time_us = ((htotal * 1000) / clock);
3284 line_time_us = ((sr_htotal * 1000) / sr_clock);
3285 3954
3286 /* Use ns/us then divide to preserve precision */ 3955 /* Use ns/us then divide to preserve precision */
3287 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 3956 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3288 pixel_size * sr_hdisplay; 3957 pixel_size * hdisplay;
3289 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE); 3958 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3290 DRM_DEBUG("self-refresh entries: %d\n", sr_entries); 3959 srwm = I965_FIFO_SIZE - entries;
3291 srwm = I965_FIFO_SIZE - sr_entries;
3292 if (srwm < 0) 3960 if (srwm < 0)
3293 srwm = 1; 3961 srwm = 1;
3294 srwm &= 0x1ff; 3962 srwm &= 0x1ff;
3963 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3964 entries, srwm);
3295 3965
3296 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 3966 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3297 pixel_size * 64; 3967 pixel_size * 64;
3298 sr_entries = DIV_ROUND_UP(sr_entries, 3968 entries = DIV_ROUND_UP(entries,
3299 i965_cursor_wm_info.cacheline_size); 3969 i965_cursor_wm_info.cacheline_size);
3300 cursor_sr = i965_cursor_wm_info.fifo_size - 3970 cursor_sr = i965_cursor_wm_info.fifo_size -
3301 (sr_entries + i965_cursor_wm_info.guard_size); 3971 (entries + i965_cursor_wm_info.guard_size);
3302 3972
3303 if (cursor_sr > i965_cursor_wm_info.max_wm) 3973 if (cursor_sr > i965_cursor_wm_info.max_wm)
3304 cursor_sr = i965_cursor_wm_info.max_wm; 3974 cursor_sr = i965_cursor_wm_info.max_wm;
@@ -3319,46 +3989,56 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
3319 srwm); 3989 srwm);
3320 3990
3321 /* 965 has limitations... */ 3991 /* 965 has limitations... */
3322 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) | 3992 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3323 (8 << 0)); 3993 (8 << 16) | (8 << 8) | (8 << 0));
3324 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); 3994 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3325 /* update cursor SR watermark */ 3995 /* update cursor SR watermark */
3326 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 3996 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3327} 3997}
3328 3998
3329static void i9xx_update_wm(struct drm_device *dev, int planea_clock, 3999static void i9xx_update_wm(struct drm_device *dev)
3330 int planeb_clock, int sr_hdisplay, int sr_htotal,
3331 int pixel_size)
3332{ 4000{
3333 struct drm_i915_private *dev_priv = dev->dev_private; 4001 struct drm_i915_private *dev_priv = dev->dev_private;
4002 const struct intel_watermark_params *wm_info;
3334 uint32_t fwater_lo; 4003 uint32_t fwater_lo;
3335 uint32_t fwater_hi; 4004 uint32_t fwater_hi;
3336 int total_size, cacheline_size, cwm, srwm = 1; 4005 int cwm, srwm = 1;
4006 int fifo_size;
3337 int planea_wm, planeb_wm; 4007 int planea_wm, planeb_wm;
3338 struct intel_watermark_params planea_params, planeb_params; 4008 struct drm_crtc *crtc, *enabled = NULL;
3339 unsigned long line_time_us;
3340 int sr_clock, sr_entries = 0;
3341 4009
3342 /* Create copies of the base settings for each pipe */ 4010 if (IS_I945GM(dev))
3343 if (IS_CRESTLINE(dev) || IS_I945GM(dev)) 4011 wm_info = &i945_wm_info;
3344 planea_params = planeb_params = i945_wm_info;
3345 else if (!IS_GEN2(dev)) 4012 else if (!IS_GEN2(dev))
3346 planea_params = planeb_params = i915_wm_info; 4013 wm_info = &i915_wm_info;
3347 else 4014 else
3348 planea_params = planeb_params = i855_wm_info; 4015 wm_info = &i855_wm_info;
3349 4016
3350 /* Grab a couple of global values before we overwrite them */ 4017 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3351 total_size = planea_params.fifo_size; 4018 crtc = intel_get_crtc_for_plane(dev, 0);
3352 cacheline_size = planea_params.cacheline_size; 4019 if (crtc->enabled && crtc->fb) {
3353 4020 planea_wm = intel_calculate_wm(crtc->mode.clock,
3354 /* Update per-plane FIFO sizes */ 4021 wm_info, fifo_size,
3355 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0); 4022 crtc->fb->bits_per_pixel / 8,
3356 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1); 4023 latency_ns);
4024 enabled = crtc;
4025 } else
4026 planea_wm = fifo_size - wm_info->guard_size;
4027
4028 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4029 crtc = intel_get_crtc_for_plane(dev, 1);
4030 if (crtc->enabled && crtc->fb) {
4031 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4032 wm_info, fifo_size,
4033 crtc->fb->bits_per_pixel / 8,
4034 latency_ns);
4035 if (enabled == NULL)
4036 enabled = crtc;
4037 else
4038 enabled = NULL;
4039 } else
4040 planeb_wm = fifo_size - wm_info->guard_size;
3357 4041
3358 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3359 pixel_size, latency_ns);
3360 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3361 pixel_size, latency_ns);
3362 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 4042 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3363 4043
3364 /* 4044 /*
@@ -3366,39 +4046,39 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3366 */ 4046 */
3367 cwm = 2; 4047 cwm = 2;
3368 4048
4049 /* Play safe and disable self-refresh before adjusting watermarks. */
4050 if (IS_I945G(dev) || IS_I945GM(dev))
4051 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4052 else if (IS_I915GM(dev))
4053 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4054
3369 /* Calc sr entries for one plane configs */ 4055 /* Calc sr entries for one plane configs */
3370 if (HAS_FW_BLC(dev) && sr_hdisplay && 4056 if (HAS_FW_BLC(dev) && enabled) {
3371 (!planea_clock || !planeb_clock)) {
3372 /* self-refresh has much higher latency */ 4057 /* self-refresh has much higher latency */
3373 static const int sr_latency_ns = 6000; 4058 static const int sr_latency_ns = 6000;
4059 int clock = enabled->mode.clock;
4060 int htotal = enabled->mode.htotal;
4061 int hdisplay = enabled->mode.hdisplay;
4062 int pixel_size = enabled->fb->bits_per_pixel / 8;
4063 unsigned long line_time_us;
4064 int entries;
3374 4065
3375 sr_clock = planea_clock ? planea_clock : planeb_clock; 4066 line_time_us = (htotal * 1000) / clock;
3376 line_time_us = ((sr_htotal * 1000) / sr_clock);
3377 4067
3378 /* Use ns/us then divide to preserve precision */ 4068 /* Use ns/us then divide to preserve precision */
3379 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 4069 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3380 pixel_size * sr_hdisplay; 4070 pixel_size * hdisplay;
3381 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); 4071 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3382 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries); 4072 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3383 srwm = total_size - sr_entries; 4073 srwm = wm_info->fifo_size - entries;
3384 if (srwm < 0) 4074 if (srwm < 0)
3385 srwm = 1; 4075 srwm = 1;
3386 4076
3387 if (IS_I945G(dev) || IS_I945GM(dev)) 4077 if (IS_I945G(dev) || IS_I945GM(dev))
3388 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 4078 I915_WRITE(FW_BLC_SELF,
3389 else if (IS_I915GM(dev)) { 4079 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3390 /* 915M has a smaller SRWM field */ 4080 else if (IS_I915GM(dev))
3391 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 4081 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3392 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3393 }
3394 } else {
3395 /* Turn off self refresh if both pipes are enabled */
3396 if (IS_I945G(dev) || IS_I945GM(dev)) {
3397 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3398 & ~FW_BLC_SELF_EN);
3399 } else if (IS_I915GM(dev)) {
3400 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3401 }
3402 } 4082 }
3403 4083
3404 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 4084 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
@@ -3413,19 +4093,36 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3413 4093
3414 I915_WRITE(FW_BLC, fwater_lo); 4094 I915_WRITE(FW_BLC, fwater_lo);
3415 I915_WRITE(FW_BLC2, fwater_hi); 4095 I915_WRITE(FW_BLC2, fwater_hi);
4096
4097 if (HAS_FW_BLC(dev)) {
4098 if (enabled) {
4099 if (IS_I945G(dev) || IS_I945GM(dev))
4100 I915_WRITE(FW_BLC_SELF,
4101 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4102 else if (IS_I915GM(dev))
4103 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4104 DRM_DEBUG_KMS("memory self refresh enabled\n");
4105 } else
4106 DRM_DEBUG_KMS("memory self refresh disabled\n");
4107 }
3416} 4108}
3417 4109
3418static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused, 4110static void i830_update_wm(struct drm_device *dev)
3419 int unused2, int unused3, int pixel_size)
3420{ 4111{
3421 struct drm_i915_private *dev_priv = dev->dev_private; 4112 struct drm_i915_private *dev_priv = dev->dev_private;
3422 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; 4113 struct drm_crtc *crtc;
4114 uint32_t fwater_lo;
3423 int planea_wm; 4115 int planea_wm;
3424 4116
3425 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0); 4117 crtc = single_enabled_crtc(dev);
4118 if (crtc == NULL)
4119 return;
3426 4120
3427 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, 4121 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3428 pixel_size, latency_ns); 4122 dev_priv->display.get_fifo_size(dev, 0),
4123 crtc->fb->bits_per_pixel / 8,
4124 latency_ns);
4125 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3429 fwater_lo |= (3<<8) | planea_wm; 4126 fwater_lo |= (3<<8) | planea_wm;
3430 4127
3431 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 4128 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
@@ -3534,15 +4231,15 @@ static bool ironlake_check_srwm(struct drm_device *dev, int level,
3534/* 4231/*
3535 * Compute watermark values of WM[1-3], 4232 * Compute watermark values of WM[1-3],
3536 */ 4233 */
3537static bool ironlake_compute_srwm(struct drm_device *dev, int level, 4234static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
3538 int hdisplay, int htotal, 4235 int latency_ns,
3539 int pixel_size, int clock, int latency_ns,
3540 const struct intel_watermark_params *display, 4236 const struct intel_watermark_params *display,
3541 const struct intel_watermark_params *cursor, 4237 const struct intel_watermark_params *cursor,
3542 int *fbc_wm, int *display_wm, int *cursor_wm) 4238 int *fbc_wm, int *display_wm, int *cursor_wm)
3543{ 4239{
3544 4240 struct drm_crtc *crtc;
3545 unsigned long line_time_us; 4241 unsigned long line_time_us;
4242 int hdisplay, htotal, pixel_size, clock;
3546 int line_count, line_size; 4243 int line_count, line_size;
3547 int small, large; 4244 int small, large;
3548 int entries; 4245 int entries;
@@ -3552,6 +4249,12 @@ static bool ironlake_compute_srwm(struct drm_device *dev, int level,
3552 return false; 4249 return false;
3553 } 4250 }
3554 4251
4252 crtc = intel_get_crtc_for_plane(dev, plane);
4253 hdisplay = crtc->mode.hdisplay;
4254 htotal = crtc->mode.htotal;
4255 clock = crtc->mode.clock;
4256 pixel_size = crtc->fb->bits_per_pixel / 8;
4257
3555 line_time_us = (htotal * 1000) / clock; 4258 line_time_us = (htotal * 1000) / clock;
3556 line_count = (latency_ns / line_time_us + 1000) / 1000; 4259 line_count = (latency_ns / line_time_us + 1000) / 1000;
3557 line_size = hdisplay * pixel_size; 4260 line_size = hdisplay * pixel_size;
@@ -3579,14 +4282,11 @@ static bool ironlake_compute_srwm(struct drm_device *dev, int level,
3579 display, cursor); 4282 display, cursor);
3580} 4283}
3581 4284
3582static void ironlake_update_wm(struct drm_device *dev, 4285static void ironlake_update_wm(struct drm_device *dev)
3583 int planea_clock, int planeb_clock,
3584 int hdisplay, int htotal,
3585 int pixel_size)
3586{ 4286{
3587 struct drm_i915_private *dev_priv = dev->dev_private; 4287 struct drm_i915_private *dev_priv = dev->dev_private;
3588 int fbc_wm, plane_wm, cursor_wm, enabled; 4288 int fbc_wm, plane_wm, cursor_wm;
3589 int clock; 4289 unsigned int enabled;
3590 4290
3591 enabled = 0; 4291 enabled = 0;
3592 if (ironlake_compute_wm0(dev, 0, 4292 if (ironlake_compute_wm0(dev, 0,
@@ -3600,7 +4300,7 @@ static void ironlake_update_wm(struct drm_device *dev,
3600 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 4300 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3601 " plane %d, " "cursor: %d\n", 4301 " plane %d, " "cursor: %d\n",
3602 plane_wm, cursor_wm); 4302 plane_wm, cursor_wm);
3603 enabled++; 4303 enabled |= 1;
3604 } 4304 }
3605 4305
3606 if (ironlake_compute_wm0(dev, 1, 4306 if (ironlake_compute_wm0(dev, 1,
@@ -3614,7 +4314,7 @@ static void ironlake_update_wm(struct drm_device *dev,
3614 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 4314 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3615 " plane %d, cursor: %d\n", 4315 " plane %d, cursor: %d\n",
3616 plane_wm, cursor_wm); 4316 plane_wm, cursor_wm);
3617 enabled++; 4317 enabled |= 2;
3618 } 4318 }
3619 4319
3620 /* 4320 /*
@@ -3625,14 +4325,13 @@ static void ironlake_update_wm(struct drm_device *dev,
3625 I915_WRITE(WM2_LP_ILK, 0); 4325 I915_WRITE(WM2_LP_ILK, 0);
3626 I915_WRITE(WM1_LP_ILK, 0); 4326 I915_WRITE(WM1_LP_ILK, 0);
3627 4327
3628 if (enabled != 1) 4328 if (!single_plane_enabled(enabled))
3629 return; 4329 return;
3630 4330 enabled = ffs(enabled) - 1;
3631 clock = planea_clock ? planea_clock : planeb_clock;
3632 4331
3633 /* WM1 */ 4332 /* WM1 */
3634 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size, 4333 if (!ironlake_compute_srwm(dev, 1, enabled,
3635 clock, ILK_READ_WM1_LATENCY() * 500, 4334 ILK_READ_WM1_LATENCY() * 500,
3636 &ironlake_display_srwm_info, 4335 &ironlake_display_srwm_info,
3637 &ironlake_cursor_srwm_info, 4336 &ironlake_cursor_srwm_info,
3638 &fbc_wm, &plane_wm, &cursor_wm)) 4337 &fbc_wm, &plane_wm, &cursor_wm))
@@ -3646,8 +4345,8 @@ static void ironlake_update_wm(struct drm_device *dev,
3646 cursor_wm); 4345 cursor_wm);
3647 4346
3648 /* WM2 */ 4347 /* WM2 */
3649 if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size, 4348 if (!ironlake_compute_srwm(dev, 2, enabled,
3650 clock, ILK_READ_WM2_LATENCY() * 500, 4349 ILK_READ_WM2_LATENCY() * 500,
3651 &ironlake_display_srwm_info, 4350 &ironlake_display_srwm_info,
3652 &ironlake_cursor_srwm_info, 4351 &ironlake_cursor_srwm_info,
3653 &fbc_wm, &plane_wm, &cursor_wm)) 4352 &fbc_wm, &plane_wm, &cursor_wm))
@@ -3666,15 +4365,12 @@ static void ironlake_update_wm(struct drm_device *dev,
3666 */ 4365 */
3667} 4366}
3668 4367
3669static void sandybridge_update_wm(struct drm_device *dev, 4368static void sandybridge_update_wm(struct drm_device *dev)
3670 int planea_clock, int planeb_clock,
3671 int hdisplay, int htotal,
3672 int pixel_size)
3673{ 4369{
3674 struct drm_i915_private *dev_priv = dev->dev_private; 4370 struct drm_i915_private *dev_priv = dev->dev_private;
3675 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 4371 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
3676 int fbc_wm, plane_wm, cursor_wm, enabled; 4372 int fbc_wm, plane_wm, cursor_wm;
3677 int clock; 4373 unsigned int enabled;
3678 4374
3679 enabled = 0; 4375 enabled = 0;
3680 if (ironlake_compute_wm0(dev, 0, 4376 if (ironlake_compute_wm0(dev, 0,
@@ -3686,7 +4382,7 @@ static void sandybridge_update_wm(struct drm_device *dev,
3686 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 4382 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3687 " plane %d, " "cursor: %d\n", 4383 " plane %d, " "cursor: %d\n",
3688 plane_wm, cursor_wm); 4384 plane_wm, cursor_wm);
3689 enabled++; 4385 enabled |= 1;
3690 } 4386 }
3691 4387
3692 if (ironlake_compute_wm0(dev, 1, 4388 if (ironlake_compute_wm0(dev, 1,
@@ -3698,7 +4394,7 @@ static void sandybridge_update_wm(struct drm_device *dev,
3698 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 4394 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3699 " plane %d, cursor: %d\n", 4395 " plane %d, cursor: %d\n",
3700 plane_wm, cursor_wm); 4396 plane_wm, cursor_wm);
3701 enabled++; 4397 enabled |= 2;
3702 } 4398 }
3703 4399
3704 /* 4400 /*
@@ -3715,14 +4411,13 @@ static void sandybridge_update_wm(struct drm_device *dev,
3715 I915_WRITE(WM2_LP_ILK, 0); 4411 I915_WRITE(WM2_LP_ILK, 0);
3716 I915_WRITE(WM1_LP_ILK, 0); 4412 I915_WRITE(WM1_LP_ILK, 0);
3717 4413
3718 if (enabled != 1) 4414 if (!single_plane_enabled(enabled))
3719 return; 4415 return;
3720 4416 enabled = ffs(enabled) - 1;
3721 clock = planea_clock ? planea_clock : planeb_clock;
3722 4417
3723 /* WM1 */ 4418 /* WM1 */
3724 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size, 4419 if (!ironlake_compute_srwm(dev, 1, enabled,
3725 clock, SNB_READ_WM1_LATENCY() * 500, 4420 SNB_READ_WM1_LATENCY() * 500,
3726 &sandybridge_display_srwm_info, 4421 &sandybridge_display_srwm_info,
3727 &sandybridge_cursor_srwm_info, 4422 &sandybridge_cursor_srwm_info,
3728 &fbc_wm, &plane_wm, &cursor_wm)) 4423 &fbc_wm, &plane_wm, &cursor_wm))
@@ -3736,9 +4431,8 @@ static void sandybridge_update_wm(struct drm_device *dev,
3736 cursor_wm); 4431 cursor_wm);
3737 4432
3738 /* WM2 */ 4433 /* WM2 */
3739 if (!ironlake_compute_srwm(dev, 2, 4434 if (!ironlake_compute_srwm(dev, 2, enabled,
3740 hdisplay, htotal, pixel_size, 4435 SNB_READ_WM2_LATENCY() * 500,
3741 clock, SNB_READ_WM2_LATENCY() * 500,
3742 &sandybridge_display_srwm_info, 4436 &sandybridge_display_srwm_info,
3743 &sandybridge_cursor_srwm_info, 4437 &sandybridge_cursor_srwm_info,
3744 &fbc_wm, &plane_wm, &cursor_wm)) 4438 &fbc_wm, &plane_wm, &cursor_wm))
@@ -3752,9 +4446,8 @@ static void sandybridge_update_wm(struct drm_device *dev,
3752 cursor_wm); 4446 cursor_wm);
3753 4447
3754 /* WM3 */ 4448 /* WM3 */
3755 if (!ironlake_compute_srwm(dev, 3, 4449 if (!ironlake_compute_srwm(dev, 3, enabled,
3756 hdisplay, htotal, pixel_size, 4450 SNB_READ_WM3_LATENCY() * 500,
3757 clock, SNB_READ_WM3_LATENCY() * 500,
3758 &sandybridge_display_srwm_info, 4451 &sandybridge_display_srwm_info,
3759 &sandybridge_cursor_srwm_info, 4452 &sandybridge_cursor_srwm_info,
3760 &fbc_wm, &plane_wm, &cursor_wm)) 4453 &fbc_wm, &plane_wm, &cursor_wm))
@@ -3803,49 +4496,89 @@ static void sandybridge_update_wm(struct drm_device *dev,
3803static void intel_update_watermarks(struct drm_device *dev) 4496static void intel_update_watermarks(struct drm_device *dev)
3804{ 4497{
3805 struct drm_i915_private *dev_priv = dev->dev_private; 4498 struct drm_i915_private *dev_priv = dev->dev_private;
4499
4500 if (dev_priv->display.update_wm)
4501 dev_priv->display.update_wm(dev);
4502}
4503
4504static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4505{
4506 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4507}
4508
4509static void intel_update_dref(struct drm_i915_private *dev_priv)
4510{
4511 struct drm_device *dev = dev_priv->dev;
4512 struct drm_mode_config *mode_config = &dev->mode_config;
4513 struct intel_encoder *encoder;
3806 struct drm_crtc *crtc; 4514 struct drm_crtc *crtc;
3807 int sr_hdisplay = 0; 4515 u32 temp;
3808 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; 4516 bool lvds_on = false, edp_on = false, pch_edp_on = false, other_on = false;
3809 int enabled = 0, pixel_size = 0;
3810 int sr_htotal = 0;
3811 4517
3812 if (!dev_priv->display.update_wm) 4518 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3813 return; 4519 crtc = encoder->base.crtc;
3814 4520
3815 /* Get the clock config from both planes */ 4521 if (!crtc || !crtc->enabled)
3816 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 4522 continue;
3817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4523
3818 if (intel_crtc->active) { 4524 switch (encoder->type) {
3819 enabled++; 4525 case INTEL_OUTPUT_LVDS:
3820 if (intel_crtc->plane == 0) { 4526 lvds_on = true;
3821 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", 4527 break;
3822 intel_crtc->pipe, crtc->mode.clock); 4528 case INTEL_OUTPUT_EDP:
3823 planea_clock = crtc->mode.clock; 4529 edp_on = true;
4530 if (!pch_edp_on)
4531 pch_edp_on = intel_encoder_is_pch_edp(&encoder->base);
4532 break;
4533 default:
4534 other_on = true;
4535 break;
4536 }
4537 }
4538
4539 /*XXX BIOS treats 16:31 as a mask for 0:15 */
4540
4541 temp = I915_READ(PCH_DREF_CONTROL);
4542
4543 /* First clear the current state for output switching */
4544 temp &= ~DREF_SSC1_ENABLE;
4545 temp &= ~DREF_SSC4_ENABLE;
4546 temp &= ~DREF_SUPERSPREAD_SOURCE_MASK;
4547 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4548 temp &= ~DREF_SSC_SOURCE_MASK;
4549 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4550 I915_WRITE(PCH_DREF_CONTROL, temp);
4551
4552 POSTING_READ(PCH_DREF_CONTROL);
4553 udelay(200);
4554
4555 if ((lvds_on || edp_on) && intel_panel_use_ssc(dev_priv)) {
4556 temp |= DREF_SSC_SOURCE_ENABLE;
4557 if (edp_on) {
4558 if (!pch_edp_on) {
4559 /* Enable CPU source on CPU attached eDP */
4560 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3824 } else { 4561 } else {
3825 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n", 4562 /* Enable SSC on PCH eDP if needed */
3826 intel_crtc->pipe, crtc->mode.clock); 4563 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3827 planeb_clock = crtc->mode.clock;
3828 } 4564 }
3829 sr_hdisplay = crtc->mode.hdisplay; 4565 I915_WRITE(PCH_DREF_CONTROL, temp);
3830 sr_clock = crtc->mode.clock;
3831 sr_htotal = crtc->mode.htotal;
3832 if (crtc->fb)
3833 pixel_size = crtc->fb->bits_per_pixel / 8;
3834 else
3835 pixel_size = 4; /* by default */
3836 } 4566 }
4567 if (!dev_priv->display_clock_mode)
4568 temp |= DREF_SSC1_ENABLE;
3837 } 4569 }
3838 4570
3839 if (enabled <= 0) 4571 if (other_on && dev_priv->display_clock_mode)
3840 return; 4572 temp |= DREF_NONSPREAD_CK505_ENABLE;
3841 4573 else if (other_on) {
3842 dev_priv->display.update_wm(dev, planea_clock, planeb_clock, 4574 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3843 sr_hdisplay, sr_htotal, pixel_size); 4575 if (edp_on && !pch_edp_on)
3844} 4576 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4577 }
3845 4578
3846static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) 4579 I915_WRITE(PCH_DREF_CONTROL, temp);
3847{ 4580 POSTING_READ(PCH_DREF_CONTROL);
3848 return dev_priv->lvds_use_ssc && i915_panel_use_ssc; 4581 udelay(200);
3849} 4582}
3850 4583
3851static int intel_crtc_mode_set(struct drm_crtc *crtc, 4584static int intel_crtc_mode_set(struct drm_crtc *crtc,
@@ -3872,6 +4605,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3872 int ret; 4605 int ret;
3873 struct fdi_m_n m_n = {0}; 4606 struct fdi_m_n m_n = {0};
3874 u32 reg, temp; 4607 u32 reg, temp;
4608 u32 lvds_sync = 0;
3875 int target_clock; 4609 int target_clock;
3876 4610
3877 drm_vblank_pre_modeset(dev, pipe); 4611 drm_vblank_pre_modeset(dev, pipe);
@@ -4072,46 +4806,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4072 * PCH B stepping, previous chipset stepping should be 4806 * PCH B stepping, previous chipset stepping should be
4073 * ignoring this setting. 4807 * ignoring this setting.
4074 */ 4808 */
4075 if (HAS_PCH_SPLIT(dev)) { 4809 if (HAS_PCH_SPLIT(dev))
4076 temp = I915_READ(PCH_DREF_CONTROL); 4810 intel_update_dref(dev_priv);
4077 /* Always enable nonspread source */
4078 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4079 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4080 temp &= ~DREF_SSC_SOURCE_MASK;
4081 temp |= DREF_SSC_SOURCE_ENABLE;
4082 I915_WRITE(PCH_DREF_CONTROL, temp);
4083
4084 POSTING_READ(PCH_DREF_CONTROL);
4085 udelay(200);
4086
4087 if (has_edp_encoder) {
4088 if (intel_panel_use_ssc(dev_priv)) {
4089 temp |= DREF_SSC1_ENABLE;
4090 I915_WRITE(PCH_DREF_CONTROL, temp);
4091
4092 POSTING_READ(PCH_DREF_CONTROL);
4093 udelay(200);
4094 }
4095 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4096
4097 /* Enable CPU source on CPU attached eDP */
4098 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4099 if (intel_panel_use_ssc(dev_priv))
4100 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4101 else
4102 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4103 } else {
4104 /* Enable SSC on PCH eDP if needed */
4105 if (intel_panel_use_ssc(dev_priv)) {
4106 DRM_ERROR("enabling SSC on PCH\n");
4107 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4108 }
4109 }
4110 I915_WRITE(PCH_DREF_CONTROL, temp);
4111 POSTING_READ(PCH_DREF_CONTROL);
4112 udelay(200);
4113 }
4114 }
4115 4811
4116 if (IS_PINEVIEW(dev)) { 4812 if (IS_PINEVIEW(dev)) {
4117 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; 4813 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
@@ -4243,9 +4939,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4243 pipeconf &= ~PIPECONF_DOUBLE_WIDE; 4939 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4244 } 4940 }
4245 4941
4246 dspcntr |= DISPLAY_PLANE_ENABLE; 4942 if (!HAS_PCH_SPLIT(dev))
4247 pipeconf |= PIPECONF_ENABLE; 4943 dpll |= DPLL_VCO_ENABLE;
4248 dpll |= DPLL_VCO_ENABLE;
4249 4944
4250 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 4945 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4251 drm_mode_debug_printmodeline(mode); 4946 drm_mode_debug_printmodeline(mode);
@@ -4271,10 +4966,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4271 /* enable transcoder DPLL */ 4966 /* enable transcoder DPLL */
4272 if (HAS_PCH_CPT(dev)) { 4967 if (HAS_PCH_CPT(dev)) {
4273 temp = I915_READ(PCH_DPLL_SEL); 4968 temp = I915_READ(PCH_DPLL_SEL);
4274 if (pipe == 0) 4969 switch (pipe) {
4970 case 0:
4275 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; 4971 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4276 else 4972 break;
4973 case 1:
4277 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; 4974 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4975 break;
4976 case 2:
4977 /* FIXME: manage transcoder PLLs? */
4978 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
4979 break;
4980 default:
4981 BUG();
4982 }
4278 I915_WRITE(PCH_DPLL_SEL, temp); 4983 I915_WRITE(PCH_DPLL_SEL, temp);
4279 4984
4280 POSTING_READ(PCH_DPLL_SEL); 4985 POSTING_READ(PCH_DPLL_SEL);
@@ -4324,6 +5029,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4324 else 5029 else
4325 temp &= ~LVDS_ENABLE_DITHER; 5030 temp &= ~LVDS_ENABLE_DITHER;
4326 } 5031 }
5032 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5033 lvds_sync |= LVDS_HSYNC_POLARITY;
5034 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5035 lvds_sync |= LVDS_VSYNC_POLARITY;
5036 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5037 != lvds_sync) {
5038 char flags[2] = "-+";
5039 DRM_INFO("Changing LVDS panel from "
5040 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5041 flags[!(temp & LVDS_HSYNC_POLARITY)],
5042 flags[!(temp & LVDS_VSYNC_POLARITY)],
5043 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5044 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5045 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5046 temp |= lvds_sync;
5047 }
4327 I915_WRITE(reg, temp); 5048 I915_WRITE(reg, temp);
4328 } 5049 }
4329 5050
@@ -4341,17 +5062,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4341 intel_dp_set_m_n(crtc, mode, adjusted_mode); 5062 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4342 } else if (HAS_PCH_SPLIT(dev)) { 5063 } else if (HAS_PCH_SPLIT(dev)) {
4343 /* For non-DP output, clear any trans DP clock recovery setting.*/ 5064 /* For non-DP output, clear any trans DP clock recovery setting.*/
4344 if (pipe == 0) { 5065 I915_WRITE(TRANSDATA_M1(pipe), 0);
4345 I915_WRITE(TRANSA_DATA_M1, 0); 5066 I915_WRITE(TRANSDATA_N1(pipe), 0);
4346 I915_WRITE(TRANSA_DATA_N1, 0); 5067 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4347 I915_WRITE(TRANSA_DP_LINK_M1, 0); 5068 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4348 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4349 } else {
4350 I915_WRITE(TRANSB_DATA_M1, 0);
4351 I915_WRITE(TRANSB_DATA_N1, 0);
4352 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4353 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4354 }
4355 } 5069 }
4356 5070
4357 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 5071 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
@@ -4454,6 +5168,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4454 5168
4455 I915_WRITE(PIPECONF(pipe), pipeconf); 5169 I915_WRITE(PIPECONF(pipe), pipeconf);
4456 POSTING_READ(PIPECONF(pipe)); 5170 POSTING_READ(PIPECONF(pipe));
5171 if (!HAS_PCH_SPLIT(dev))
5172 intel_enable_pipe(dev_priv, pipe, false);
4457 5173
4458 intel_wait_for_vblank(dev, pipe); 5174 intel_wait_for_vblank(dev, pipe);
4459 5175
@@ -4464,6 +5180,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4464 } 5180 }
4465 5181
4466 I915_WRITE(DSPCNTR(plane), dspcntr); 5182 I915_WRITE(DSPCNTR(plane), dspcntr);
5183 POSTING_READ(DSPCNTR(plane));
5184 if (!HAS_PCH_SPLIT(dev))
5185 intel_enable_plane(dev_priv, plane, pipe);
4467 5186
4468 ret = intel_pipe_set_base(crtc, x, y, old_fb); 5187 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4469 5188
@@ -4480,7 +5199,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
4480 struct drm_device *dev = crtc->dev; 5199 struct drm_device *dev = crtc->dev;
4481 struct drm_i915_private *dev_priv = dev->dev_private; 5200 struct drm_i915_private *dev_priv = dev->dev_private;
4482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4483 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; 5202 int palreg = PALETTE(intel_crtc->pipe);
4484 int i; 5203 int i;
4485 5204
4486 /* The clocks have to be on to load the palette. */ 5205 /* The clocks have to be on to load the palette. */
@@ -4489,8 +5208,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
4489 5208
4490 /* use legacy palette for Ironlake */ 5209 /* use legacy palette for Ironlake */
4491 if (HAS_PCH_SPLIT(dev)) 5210 if (HAS_PCH_SPLIT(dev))
4492 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : 5211 palreg = LGC_PALETTE(intel_crtc->pipe);
4493 LGC_PALETTE_B;
4494 5212
4495 for (i = 0; i < 256; i++) { 5213 for (i = 0; i < 256; i++) {
4496 I915_WRITE(palreg + 4 * i, 5214 I915_WRITE(palreg + 4 * i,
@@ -4511,12 +5229,12 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4511 if (intel_crtc->cursor_visible == visible) 5229 if (intel_crtc->cursor_visible == visible)
4512 return; 5230 return;
4513 5231
4514 cntl = I915_READ(CURACNTR); 5232 cntl = I915_READ(_CURACNTR);
4515 if (visible) { 5233 if (visible) {
4516 /* On these chipsets we can only modify the base whilst 5234 /* On these chipsets we can only modify the base whilst
4517 * the cursor is disabled. 5235 * the cursor is disabled.
4518 */ 5236 */
4519 I915_WRITE(CURABASE, base); 5237 I915_WRITE(_CURABASE, base);
4520 5238
4521 cntl &= ~(CURSOR_FORMAT_MASK); 5239 cntl &= ~(CURSOR_FORMAT_MASK);
4522 /* XXX width must be 64, stride 256 => 0x00 << 28 */ 5240 /* XXX width must be 64, stride 256 => 0x00 << 28 */
@@ -4525,7 +5243,7 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4525 CURSOR_FORMAT_ARGB; 5243 CURSOR_FORMAT_ARGB;
4526 } else 5244 } else
4527 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); 5245 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4528 I915_WRITE(CURACNTR, cntl); 5246 I915_WRITE(_CURACNTR, cntl);
4529 5247
4530 intel_crtc->cursor_visible = visible; 5248 intel_crtc->cursor_visible = visible;
4531} 5249}
@@ -4539,7 +5257,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4539 bool visible = base != 0; 5257 bool visible = base != 0;
4540 5258
4541 if (intel_crtc->cursor_visible != visible) { 5259 if (intel_crtc->cursor_visible != visible) {
4542 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); 5260 uint32_t cntl = CURCNTR(pipe);
4543 if (base) { 5261 if (base) {
4544 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); 5262 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4545 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 5263 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
@@ -4548,12 +5266,12 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4548 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 5266 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4549 cntl |= CURSOR_MODE_DISABLE; 5267 cntl |= CURSOR_MODE_DISABLE;
4550 } 5268 }
4551 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl); 5269 I915_WRITE(CURCNTR(pipe), cntl);
4552 5270
4553 intel_crtc->cursor_visible = visible; 5271 intel_crtc->cursor_visible = visible;
4554 } 5272 }
4555 /* and commit changes on next vblank */ 5273 /* and commit changes on next vblank */
4556 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base); 5274 I915_WRITE(CURBASE(pipe), base);
4557} 5275}
4558 5276
4559/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 5277/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
@@ -4603,7 +5321,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4603 if (!visible && !intel_crtc->cursor_visible) 5321 if (!visible && !intel_crtc->cursor_visible)
4604 return; 5322 return;
4605 5323
4606 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); 5324 I915_WRITE(CURPOS(pipe), pos);
4607 if (IS_845G(dev) || IS_I865G(dev)) 5325 if (IS_845G(dev) || IS_I865G(dev))
4608 i845_update_cursor(crtc, base); 5326 i845_update_cursor(crtc, base);
4609 else 5327 else
@@ -4909,14 +5627,14 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4909 struct drm_i915_private *dev_priv = dev->dev_private; 5627 struct drm_i915_private *dev_priv = dev->dev_private;
4910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4911 int pipe = intel_crtc->pipe; 5629 int pipe = intel_crtc->pipe;
4912 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); 5630 u32 dpll = DPLL(pipe);
4913 u32 fp; 5631 u32 fp;
4914 intel_clock_t clock; 5632 intel_clock_t clock;
4915 5633
4916 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 5634 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4917 fp = I915_READ((pipe == 0) ? FPA0 : FPB0); 5635 fp = FP0(pipe);
4918 else 5636 else
4919 fp = I915_READ((pipe == 0) ? FPA1 : FPB1); 5637 fp = FP1(pipe);
4920 5638
4921 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 5639 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4922 if (IS_PINEVIEW(dev)) { 5640 if (IS_PINEVIEW(dev)) {
@@ -4994,14 +5712,13 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4994struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 5712struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4995 struct drm_crtc *crtc) 5713 struct drm_crtc *crtc)
4996{ 5714{
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4999 int pipe = intel_crtc->pipe; 5716 int pipe = intel_crtc->pipe;
5000 struct drm_display_mode *mode; 5717 struct drm_display_mode *mode;
5001 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); 5718 int htot = HTOTAL(pipe);
5002 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); 5719 int hsync = HSYNC(pipe);
5003 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); 5720 int vtot = VTOTAL(pipe);
5004 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); 5721 int vsync = VSYNC(pipe);
5005 5722
5006 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 5723 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5007 if (!mode) 5724 if (!mode)
@@ -5110,7 +5827,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
5110 drm_i915_private_t *dev_priv = dev->dev_private; 5827 drm_i915_private_t *dev_priv = dev->dev_private;
5111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5112 int pipe = intel_crtc->pipe; 5829 int pipe = intel_crtc->pipe;
5113 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 5830 int dpll_reg = DPLL(pipe);
5114 int dpll = I915_READ(dpll_reg); 5831 int dpll = I915_READ(dpll_reg);
5115 5832
5116 if (HAS_PCH_SPLIT(dev)) 5833 if (HAS_PCH_SPLIT(dev))
@@ -5158,7 +5875,6 @@ static void intel_idle_update(struct work_struct *work)
5158 struct drm_device *dev = dev_priv->dev; 5875 struct drm_device *dev = dev_priv->dev;
5159 struct drm_crtc *crtc; 5876 struct drm_crtc *crtc;
5160 struct intel_crtc *intel_crtc; 5877 struct intel_crtc *intel_crtc;
5161 int enabled = 0;
5162 5878
5163 if (!i915_powersave) 5879 if (!i915_powersave)
5164 return; 5880 return;
@@ -5172,16 +5888,11 @@ static void intel_idle_update(struct work_struct *work)
5172 if (!crtc->fb) 5888 if (!crtc->fb)
5173 continue; 5889 continue;
5174 5890
5175 enabled++;
5176 intel_crtc = to_intel_crtc(crtc); 5891 intel_crtc = to_intel_crtc(crtc);
5177 if (!intel_crtc->busy) 5892 if (!intel_crtc->busy)
5178 intel_decrease_pllclock(crtc); 5893 intel_decrease_pllclock(crtc);
5179 } 5894 }
5180 5895
5181 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
5182 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
5183 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
5184 }
5185 5896
5186 mutex_unlock(&dev->struct_mutex); 5897 mutex_unlock(&dev->struct_mutex);
5187} 5898}
@@ -5206,17 +5917,9 @@ void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5206 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 5917 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5207 return; 5918 return;
5208 5919
5209 if (!dev_priv->busy) { 5920 if (!dev_priv->busy)
5210 if (IS_I945G(dev) || IS_I945GM(dev)) {
5211 u32 fw_blc_self;
5212
5213 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5214 fw_blc_self = I915_READ(FW_BLC_SELF);
5215 fw_blc_self &= ~FW_BLC_SELF_EN;
5216 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5217 }
5218 dev_priv->busy = true; 5921 dev_priv->busy = true;
5219 } else 5922 else
5220 mod_timer(&dev_priv->idle_timer, jiffies + 5923 mod_timer(&dev_priv->idle_timer, jiffies +
5221 msecs_to_jiffies(GPU_IDLE_TIMEOUT)); 5924 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5222 5925
@@ -5228,14 +5931,6 @@ void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5228 intel_fb = to_intel_framebuffer(crtc->fb); 5931 intel_fb = to_intel_framebuffer(crtc->fb);
5229 if (intel_fb->obj == obj) { 5932 if (intel_fb->obj == obj) {
5230 if (!intel_crtc->busy) { 5933 if (!intel_crtc->busy) {
5231 if (IS_I945G(dev) || IS_I945GM(dev)) {
5232 u32 fw_blc_self;
5233
5234 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5235 fw_blc_self = I915_READ(FW_BLC_SELF);
5236 fw_blc_self &= ~FW_BLC_SELF_EN;
5237 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5238 }
5239 /* Non-busy -> busy, upclock */ 5934 /* Non-busy -> busy, upclock */
5240 intel_increase_pllclock(crtc); 5935 intel_increase_pllclock(crtc);
5241 intel_crtc->busy = true; 5936 intel_crtc->busy = true;
@@ -5513,7 +6208,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
5513 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 6208 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5514 */ 6209 */
5515 pf = 0; 6210 pf = 0;
5516 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; 6211 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
5517 OUT_RING(pf | pipesrc); 6212 OUT_RING(pf | pipesrc);
5518 break; 6213 break;
5519 6214
@@ -5523,8 +6218,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
5523 OUT_RING(fb->pitch | obj->tiling_mode); 6218 OUT_RING(fb->pitch | obj->tiling_mode);
5524 OUT_RING(obj->gtt_offset); 6219 OUT_RING(obj->gtt_offset);
5525 6220
5526 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 6221 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
5527 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; 6222 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
5528 OUT_RING(pf | pipesrc); 6223 OUT_RING(pf | pipesrc);
5529 break; 6224 break;
5530 } 6225 }
@@ -5613,22 +6308,8 @@ static void intel_sanitize_modesetting(struct drm_device *dev,
5613 pipe = !pipe; 6308 pipe = !pipe;
5614 6309
5615 /* Disable the plane and wait for it to stop reading from the pipe. */ 6310 /* Disable the plane and wait for it to stop reading from the pipe. */
5616 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); 6311 intel_disable_plane(dev_priv, plane, pipe);
5617 intel_flush_display_plane(dev, plane); 6312 intel_disable_pipe(dev_priv, pipe);
5618
5619 if (IS_GEN2(dev))
5620 intel_wait_for_vblank(dev, pipe);
5621
5622 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
5623 return;
5624
5625 /* Switch off the pipe. */
5626 reg = PIPECONF(pipe);
5627 val = I915_READ(reg);
5628 if (val & PIPECONF_ENABLE) {
5629 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
5630 intel_wait_for_pipe_off(dev, pipe);
5631 }
5632} 6313}
5633 6314
5634static void intel_crtc_init(struct drm_device *dev, int pipe) 6315static void intel_crtc_init(struct drm_device *dev, int pipe)
@@ -6240,18 +6921,18 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
6240 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 6921 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6241 18 << 24 | 6922 18 << 24 |
6242 6 << 16); 6923 6 << 16);
6243 I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000); 6924 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
6244 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000); 6925 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
6245 I915_WRITE(GEN6_RP_UP_EI, 100000); 6926 I915_WRITE(GEN6_RP_UP_EI, 100000);
6246 I915_WRITE(GEN6_RP_DOWN_EI, 300000); 6927 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
6247 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 6928 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6248 I915_WRITE(GEN6_RP_CONTROL, 6929 I915_WRITE(GEN6_RP_CONTROL,
6249 GEN6_RP_MEDIA_TURBO | 6930 GEN6_RP_MEDIA_TURBO |
6250 GEN6_RP_USE_NORMAL_FREQ | 6931 GEN6_RP_USE_NORMAL_FREQ |
6251 GEN6_RP_MEDIA_IS_GFX | 6932 GEN6_RP_MEDIA_IS_GFX |
6252 GEN6_RP_ENABLE | 6933 GEN6_RP_ENABLE |
6253 GEN6_RP_UP_BUSY_MAX | 6934 GEN6_RP_UP_BUSY_AVG |
6254 GEN6_RP_DOWN_BUSY_MIN); 6935 GEN6_RP_DOWN_IDLE_CONT);
6255 6936
6256 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 6937 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6257 500)) 6938 500))
@@ -6307,6 +6988,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
6307void intel_enable_clock_gating(struct drm_device *dev) 6988void intel_enable_clock_gating(struct drm_device *dev)
6308{ 6989{
6309 struct drm_i915_private *dev_priv = dev->dev_private; 6990 struct drm_i915_private *dev_priv = dev->dev_private;
6991 int pipe;
6310 6992
6311 /* 6993 /*
6312 * Disable clock gating reported to work incorrectly according to the 6994 * Disable clock gating reported to work incorrectly according to the
@@ -6416,12 +7098,10 @@ void intel_enable_clock_gating(struct drm_device *dev)
6416 ILK_DPARB_CLK_GATE | 7098 ILK_DPARB_CLK_GATE |
6417 ILK_DPFD_CLK_GATE); 7099 ILK_DPFD_CLK_GATE);
6418 7100
6419 I915_WRITE(DSPACNTR, 7101 for_each_pipe(pipe)
6420 I915_READ(DSPACNTR) | 7102 I915_WRITE(DSPCNTR(pipe),
6421 DISPPLANE_TRICKLE_FEED_DISABLE); 7103 I915_READ(DSPCNTR(pipe)) |
6422 I915_WRITE(DSPBCNTR, 7104 DISPPLANE_TRICKLE_FEED_DISABLE);
6423 I915_READ(DSPBCNTR) |
6424 DISPPLANE_TRICKLE_FEED_DISABLE);
6425 } 7105 }
6426 } else if (IS_G4X(dev)) { 7106 } else if (IS_G4X(dev)) {
6427 uint32_t dspclk_gate; 7107 uint32_t dspclk_gate;
@@ -6776,10 +7456,6 @@ void intel_modeset_init(struct drm_device *dev)
6776 } 7456 }
6777 dev->mode_config.fb_base = dev->agp->base; 7457 dev->mode_config.fb_base = dev->agp->base;
6778 7458
6779 if (IS_MOBILE(dev) || !IS_GEN2(dev))
6780 dev_priv->num_pipe = 2;
6781 else
6782 dev_priv->num_pipe = 1;
6783 DRM_DEBUG_KMS("%d display pipe%s available.\n", 7459 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6784 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); 7460 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6785 7461
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 51cb4e36997f..7ffb324b6a7d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -685,6 +685,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
686 int lane_count = 4, bpp = 24; 686 int lane_count = 4, bpp = 24;
687 struct intel_dp_m_n m_n; 687 struct intel_dp_m_n m_n;
688 int pipe = intel_crtc->pipe;
688 689
689 /* 690 /*
690 * Find the lane count in the intel_encoder private 691 * Find the lane count in the intel_encoder private
@@ -715,39 +716,19 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
715 mode->clock, adjusted_mode->clock, &m_n); 716 mode->clock, adjusted_mode->clock, &m_n);
716 717
717 if (HAS_PCH_SPLIT(dev)) { 718 if (HAS_PCH_SPLIT(dev)) {
718 if (intel_crtc->pipe == 0) { 719 I915_WRITE(TRANSDATA_M1(pipe),
719 I915_WRITE(TRANSA_DATA_M1, 720 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
720 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 721 m_n.gmch_m);
721 m_n.gmch_m); 722 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
722 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); 723 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
723 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); 724 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
724 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
725 } else {
726 I915_WRITE(TRANSB_DATA_M1,
727 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
728 m_n.gmch_m);
729 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
730 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
731 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
732 }
733 } else { 725 } else {
734 if (intel_crtc->pipe == 0) { 726 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
735 I915_WRITE(PIPEA_GMCH_DATA_M, 727 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
736 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 728 m_n.gmch_m);
737 m_n.gmch_m); 729 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
738 I915_WRITE(PIPEA_GMCH_DATA_N, 730 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
739 m_n.gmch_n); 731 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
740 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
741 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
742 } else {
743 I915_WRITE(PIPEB_GMCH_DATA_M,
744 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
745 m_n.gmch_m);
746 I915_WRITE(PIPEB_GMCH_DATA_N,
747 m_n.gmch_n);
748 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
749 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
750 }
751 } 732 }
752} 733}
753 734
@@ -813,6 +794,40 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
813 } 794 }
814} 795}
815 796
797static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
798{
799 struct drm_device *dev = intel_dp->base.base.dev;
800 struct drm_i915_private *dev_priv = dev->dev_private;
801 u32 pp;
802
803 /*
804 * If the panel wasn't on, make sure there's not a currently
805 * active PP sequence before enabling AUX VDD.
806 */
807 if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
808 msleep(dev_priv->panel_t3);
809
810 pp = I915_READ(PCH_PP_CONTROL);
811 pp |= EDP_FORCE_VDD;
812 I915_WRITE(PCH_PP_CONTROL, pp);
813 POSTING_READ(PCH_PP_CONTROL);
814}
815
816static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
817{
818 struct drm_device *dev = intel_dp->base.base.dev;
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 u32 pp;
821
822 pp = I915_READ(PCH_PP_CONTROL);
823 pp &= ~EDP_FORCE_VDD;
824 I915_WRITE(PCH_PP_CONTROL, pp);
825 POSTING_READ(PCH_PP_CONTROL);
826
827 /* Make sure sequencer is idle before allowing subsequent activity */
828 msleep(dev_priv->panel_t12);
829}
830
816/* Returns true if the panel was already on when called */ 831/* Returns true if the panel was already on when called */
817static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) 832static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
818{ 833{
@@ -834,11 +849,6 @@ static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
834 I915_WRITE(PCH_PP_CONTROL, pp); 849 I915_WRITE(PCH_PP_CONTROL, pp);
835 POSTING_READ(PCH_PP_CONTROL); 850 POSTING_READ(PCH_PP_CONTROL);
836 851
837 /* Ouch. We need to wait here for some panels, like Dell e6510
838 * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
839 */
840 msleep(300);
841
842 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, 852 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
843 5000)) 853 5000))
844 DRM_ERROR("panel on wait timed out: 0x%08x\n", 854 DRM_ERROR("panel on wait timed out: 0x%08x\n",
@@ -875,11 +885,6 @@ static void ironlake_edp_panel_off (struct drm_device *dev)
875 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 885 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
876 I915_WRITE(PCH_PP_CONTROL, pp); 886 I915_WRITE(PCH_PP_CONTROL, pp);
877 POSTING_READ(PCH_PP_CONTROL); 887 POSTING_READ(PCH_PP_CONTROL);
878
879 /* Ouch. We need to wait here for some panels, like Dell e6510
880 * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
881 */
882 msleep(300);
883} 888}
884 889
885static void ironlake_edp_backlight_on (struct drm_device *dev) 890static void ironlake_edp_backlight_on (struct drm_device *dev)
@@ -945,7 +950,7 @@ static void intel_dp_prepare(struct drm_encoder *encoder)
945 950
946 if (is_edp(intel_dp)) { 951 if (is_edp(intel_dp)) {
947 ironlake_edp_backlight_off(dev); 952 ironlake_edp_backlight_off(dev);
948 ironlake_edp_panel_on(intel_dp); 953 ironlake_edp_panel_off(dev);
949 if (!is_pch_edp(intel_dp)) 954 if (!is_pch_edp(intel_dp))
950 ironlake_edp_pll_on(encoder); 955 ironlake_edp_pll_on(encoder);
951 else 956 else
@@ -959,10 +964,15 @@ static void intel_dp_commit(struct drm_encoder *encoder)
959 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 964 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
960 struct drm_device *dev = encoder->dev; 965 struct drm_device *dev = encoder->dev;
961 966
967 if (is_edp(intel_dp))
968 ironlake_edp_panel_vdd_on(intel_dp);
969
962 intel_dp_start_link_train(intel_dp); 970 intel_dp_start_link_train(intel_dp);
963 971
964 if (is_edp(intel_dp)) 972 if (is_edp(intel_dp)) {
965 ironlake_edp_panel_on(intel_dp); 973 ironlake_edp_panel_on(intel_dp);
974 ironlake_edp_panel_vdd_off(intel_dp);
975 }
966 976
967 intel_dp_complete_link_train(intel_dp); 977 intel_dp_complete_link_train(intel_dp);
968 978
@@ -988,9 +998,13 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
988 ironlake_edp_pll_off(encoder); 998 ironlake_edp_pll_off(encoder);
989 } else { 999 } else {
990 if (is_edp(intel_dp)) 1000 if (is_edp(intel_dp))
991 ironlake_edp_panel_on(intel_dp); 1001 ironlake_edp_panel_vdd_on(intel_dp);
992 if (!(dp_reg & DP_PORT_EN)) { 1002 if (!(dp_reg & DP_PORT_EN)) {
993 intel_dp_start_link_train(intel_dp); 1003 intel_dp_start_link_train(intel_dp);
1004 if (is_edp(intel_dp)) {
1005 ironlake_edp_panel_on(intel_dp);
1006 ironlake_edp_panel_vdd_off(intel_dp);
1007 }
994 intel_dp_complete_link_train(intel_dp); 1008 intel_dp_complete_link_train(intel_dp);
995 } 1009 }
996 if (is_edp(intel_dp)) 1010 if (is_edp(intel_dp))
@@ -1508,9 +1522,13 @@ ironlake_dp_detect(struct intel_dp *intel_dp)
1508{ 1522{
1509 enum drm_connector_status status; 1523 enum drm_connector_status status;
1510 1524
1511 /* Can't disconnect eDP */ 1525 /* Can't disconnect eDP, but you can close the lid... */
1512 if (is_edp(intel_dp)) 1526 if (is_edp(intel_dp)) {
1513 return connector_status_connected; 1527 status = intel_panel_detect(intel_dp->base.base.dev);
1528 if (status == connector_status_unknown)
1529 status = connector_status_connected;
1530 return status;
1531 }
1514 1532
1515 status = connector_status_disconnected; 1533 status = connector_status_disconnected;
1516 if (intel_dp_aux_native_read(intel_dp, 1534 if (intel_dp_aux_native_read(intel_dp,
@@ -1906,9 +1924,18 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1906 /* Cache some DPCD data in the eDP case */ 1924 /* Cache some DPCD data in the eDP case */
1907 if (is_edp(intel_dp)) { 1925 if (is_edp(intel_dp)) {
1908 int ret; 1926 int ret;
1909 bool was_on; 1927 u32 pp_on, pp_div;
1910 1928
1911 was_on = ironlake_edp_panel_on(intel_dp); 1929 pp_on = I915_READ(PCH_PP_ON_DELAYS);
1930 pp_div = I915_READ(PCH_PP_DIVISOR);
1931
1932 /* Get T3 & T12 values (note: VESA not bspec terminology) */
1933 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
1934 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
1935 dev_priv->panel_t12 = pp_div & 0xf;
1936 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
1937
1938 ironlake_edp_panel_vdd_on(intel_dp);
1912 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV, 1939 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
1913 intel_dp->dpcd, 1940 intel_dp->dpcd,
1914 sizeof(intel_dp->dpcd)); 1941 sizeof(intel_dp->dpcd));
@@ -1919,8 +1946,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1919 } else { 1946 } else {
1920 DRM_ERROR("failed to retrieve link info\n"); 1947 DRM_ERROR("failed to retrieve link info\n");
1921 } 1948 }
1922 if (!was_on) 1949 ironlake_edp_panel_vdd_off(intel_dp);
1923 ironlake_edp_panel_off(dev);
1924 } 1950 }
1925 1951
1926 intel_encoder->hot_plug = intel_dp_hot_plug; 1952 intel_encoder->hot_plug = intel_dp_hot_plug;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2c431049963c..aae4806203db 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -217,6 +217,13 @@ intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
217 return dev_priv->pipe_to_crtc_mapping[pipe]; 217 return dev_priv->pipe_to_crtc_mapping[pipe];
218} 218}
219 219
220static inline struct drm_crtc *
221intel_get_crtc_for_plane(struct drm_device *dev, int plane)
222{
223 struct drm_i915_private *dev_priv = dev->dev_private;
224 return dev_priv->plane_to_crtc_mapping[plane];
225}
226
220struct intel_unpin_work { 227struct intel_unpin_work {
221 struct work_struct work; 228 struct work_struct work;
222 struct drm_device *dev; 229 struct drm_device *dev;
@@ -260,6 +267,7 @@ extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
260extern void intel_panel_setup_backlight(struct drm_device *dev); 267extern void intel_panel_setup_backlight(struct drm_device *dev);
261extern void intel_panel_enable_backlight(struct drm_device *dev); 268extern void intel_panel_enable_backlight(struct drm_device *dev);
262extern void intel_panel_disable_backlight(struct drm_device *dev); 269extern void intel_panel_disable_backlight(struct drm_device *dev);
270extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
263 271
264extern void intel_crtc_load_lut(struct drm_crtc *crtc); 272extern void intel_crtc_load_lut(struct drm_crtc *crtc);
265extern void intel_encoder_prepare (struct drm_encoder *encoder); 273extern void intel_encoder_prepare (struct drm_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index ea373283c93b..6eda1b51c636 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -178,7 +178,7 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
178 int pipe = intel_crtc->pipe; 178 int pipe = intel_crtc->pipe;
179 u32 dvo_val; 179 u32 dvo_val;
180 u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg; 180 u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
181 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 181 int dpll_reg = DPLL(pipe);
182 182
183 switch (dvo_reg) { 183 switch (dvo_reg) {
184 case DVOA: 184 case DVOA:
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 58040f68ed7a..82d04c5899d2 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -384,7 +384,8 @@ int intel_setup_gmbus(struct drm_device *dev)
384 bus->reg0 = i | GMBUS_RATE_100KHZ; 384 bus->reg0 = i | GMBUS_RATE_100KHZ;
385 385
386 /* XXX force bit banging until GMBUS is fully debugged */ 386 /* XXX force bit banging until GMBUS is fully debugged */
387 bus->force_bit = intel_gpio_create(dev_priv, i); 387 if (IS_GEN2(dev))
388 bus->force_bit = intel_gpio_create(dev_priv, i);
388 } 389 }
389 390
390 intel_i2c_reset(dev_priv->dev); 391 intel_i2c_reset(dev_priv->dev);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index bcdba7bd5cfa..1a311ad01116 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -231,6 +231,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
231 struct intel_lvds *intel_lvds = to_intel_lvds(encoder); 231 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
232 struct drm_encoder *tmp_encoder; 232 struct drm_encoder *tmp_encoder;
233 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; 233 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
234 int pipe;
234 235
235 /* Should never happen!! */ 236 /* Should never happen!! */
236 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { 237 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
@@ -277,8 +278,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
277 * to register description and PRM. 278 * to register description and PRM.
278 * Change the value here to see the borders for debugging 279 * Change the value here to see the borders for debugging
279 */ 280 */
280 I915_WRITE(BCLRPAT_A, 0); 281 for_each_pipe(pipe)
281 I915_WRITE(BCLRPAT_B, 0); 282 I915_WRITE(BCLRPAT(pipe), 0);
282 283
283 switch (intel_lvds->fitting_mode) { 284 switch (intel_lvds->fitting_mode) {
284 case DRM_MODE_SCALE_CENTER: 285 case DRM_MODE_SCALE_CENTER:
@@ -474,6 +475,10 @@ intel_lvds_detect(struct drm_connector *connector, bool force)
474 struct drm_device *dev = connector->dev; 475 struct drm_device *dev = connector->dev;
475 enum drm_connector_status status = connector_status_connected; 476 enum drm_connector_status status = connector_status_connected;
476 477
478 status = intel_panel_detect(dev);
479 if (status != connector_status_unknown)
480 return status;
481
477 /* ACPI lid methods were generally unreliable in this generation, so 482 /* ACPI lid methods were generally unreliable in this generation, so
478 * don't even bother. 483 * don't even bother.
479 */ 484 */
@@ -496,7 +501,7 @@ static int intel_lvds_get_modes(struct drm_connector *connector)
496 return drm_add_edid_modes(connector, intel_lvds->edid); 501 return drm_add_edid_modes(connector, intel_lvds->edid);
497 502
498 mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode); 503 mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode);
499 if (mode == 0) 504 if (mode == NULL)
500 return 0; 505 return 0;
501 506
502 drm_mode_probed_add(connector, mode); 507 drm_mode_probed_add(connector, mode);
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 64fd64443ca6..9efccb95fd58 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -489,6 +489,8 @@ int intel_opregion_setup(struct drm_device *dev)
489 opregion->header = base; 489 opregion->header = base;
490 opregion->vbt = base + OPREGION_VBT_OFFSET; 490 opregion->vbt = base + OPREGION_VBT_OFFSET;
491 491
492 opregion->lid_state = base + 0x01ac;
493
492 mboxes = opregion->header->mboxes; 494 mboxes = opregion->header->mboxes;
493 if (mboxes & MBOX_ACPI) { 495 if (mboxes & MBOX_ACPI) {
494 DRM_DEBUG_DRIVER("Public ACPI methods supported\n"); 496 DRM_DEBUG_DRIVER("Public ACPI methods supported\n");
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 3fbb98b948d6..29fb2174eaaa 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -221,16 +221,15 @@ static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
221 int ret; 221 int ret;
222 222
223 BUG_ON(overlay->last_flip_req); 223 BUG_ON(overlay->last_flip_req);
224 ret = i915_add_request(dev, NULL, request, LP_RING(dev_priv)); 224 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
225 if (ret) { 225 if (ret) {
226 kfree(request); 226 kfree(request);
227 return ret; 227 return ret;
228 } 228 }
229 overlay->last_flip_req = request->seqno; 229 overlay->last_flip_req = request->seqno;
230 overlay->flip_tail = tail; 230 overlay->flip_tail = tail;
231 ret = i915_do_wait_request(dev, 231 ret = i915_wait_request(LP_RING(dev_priv),
232 overlay->last_flip_req, true, 232 overlay->last_flip_req, true);
233 LP_RING(dev_priv));
234 if (ret) 233 if (ret)
235 return ret; 234 return ret;
236 235
@@ -256,7 +255,7 @@ i830_activate_pipe_a(struct drm_device *dev)
256 return 0; 255 return 0;
257 256
258 /* most i8xx have pipe a forced on, so don't trust dpms mode */ 257 /* most i8xx have pipe a forced on, so don't trust dpms mode */
259 if (I915_READ(PIPEACONF) & PIPECONF_ENABLE) 258 if (I915_READ(_PIPEACONF) & PIPECONF_ENABLE)
260 return 0; 259 return 0;
261 260
262 crtc_funcs = crtc->base.helper_private; 261 crtc_funcs = crtc->base.helper_private;
@@ -364,7 +363,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
364 OUT_RING(flip_addr); 363 OUT_RING(flip_addr);
365 ADVANCE_LP_RING(); 364 ADVANCE_LP_RING();
366 365
367 ret = i915_add_request(dev, NULL, request, LP_RING(dev_priv)); 366 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
368 if (ret) { 367 if (ret) {
369 kfree(request); 368 kfree(request);
370 return ret; 369 return ret;
@@ -453,8 +452,8 @@ static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
453 if (overlay->last_flip_req == 0) 452 if (overlay->last_flip_req == 0)
454 return 0; 453 return 0;
455 454
456 ret = i915_do_wait_request(dev, overlay->last_flip_req, 455 ret = i915_wait_request(LP_RING(dev_priv),
457 interruptible, LP_RING(dev_priv)); 456 overlay->last_flip_req, interruptible);
458 if (ret) 457 if (ret)
459 return ret; 458 return ret;
460 459
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index c65992df458d..286995a9a84a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -281,3 +281,17 @@ void intel_panel_setup_backlight(struct drm_device *dev)
281 dev_priv->backlight_level = intel_panel_get_backlight(dev); 281 dev_priv->backlight_level = intel_panel_get_backlight(dev);
282 dev_priv->backlight_enabled = dev_priv->backlight_level != 0; 282 dev_priv->backlight_enabled = dev_priv->backlight_level != 0;
283} 283}
284
285enum drm_connector_status
286intel_panel_detect(struct drm_device *dev)
287{
288 struct drm_i915_private *dev_priv = dev->dev_private;
289
290 /* Assume that the BIOS does not lie through the OpRegion... */
291 if (dev_priv->opregion.lid_state)
292 return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
293 connector_status_connected :
294 connector_status_disconnected;
295
296 return connector_status_unknown;
297}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 445f27efe677..789c47801ba8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -62,18 +62,9 @@ render_ring_flush(struct intel_ring_buffer *ring,
62 u32 flush_domains) 62 u32 flush_domains)
63{ 63{
64 struct drm_device *dev = ring->dev; 64 struct drm_device *dev = ring->dev;
65 drm_i915_private_t *dev_priv = dev->dev_private;
66 u32 cmd; 65 u32 cmd;
67 int ret; 66 int ret;
68 67
69#if WATCH_EXEC
70 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
71 invalidate_domains, flush_domains);
72#endif
73
74 trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
75 invalidate_domains, flush_domains);
76
77 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { 68 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
78 /* 69 /*
79 * read/write caches: 70 * read/write caches:
@@ -122,9 +113,6 @@ render_ring_flush(struct intel_ring_buffer *ring,
122 (IS_G4X(dev) || IS_GEN5(dev))) 113 (IS_G4X(dev) || IS_GEN5(dev)))
123 cmd |= MI_INVALIDATE_ISP; 114 cmd |= MI_INVALIDATE_ISP;
124 115
125#if WATCH_EXEC
126 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
127#endif
128 ret = intel_ring_begin(ring, 2); 116 ret = intel_ring_begin(ring, 2);
129 if (ret) 117 if (ret)
130 return ret; 118 return ret;
@@ -612,7 +600,6 @@ ring_add_request(struct intel_ring_buffer *ring,
612 intel_ring_emit(ring, MI_USER_INTERRUPT); 600 intel_ring_emit(ring, MI_USER_INTERRUPT);
613 intel_ring_advance(ring); 601 intel_ring_advance(ring);
614 602
615 DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
616 *result = seqno; 603 *result = seqno;
617 return 0; 604 return 0;
618} 605}
@@ -715,11 +702,8 @@ render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
715 u32 offset, u32 len) 702 u32 offset, u32 len)
716{ 703{
717 struct drm_device *dev = ring->dev; 704 struct drm_device *dev = ring->dev;
718 drm_i915_private_t *dev_priv = dev->dev_private;
719 int ret; 705 int ret;
720 706
721 trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
722
723 if (IS_I830(dev) || IS_845G(dev)) { 707 if (IS_I830(dev) || IS_845G(dev)) {
724 ret = intel_ring_begin(ring, 4); 708 ret = intel_ring_begin(ring, 4);
725 if (ret) 709 if (ret)
@@ -894,6 +878,10 @@ void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
894 /* Disable the ring buffer. The ring must be idle at this point */ 878 /* Disable the ring buffer. The ring must be idle at this point */
895 dev_priv = ring->dev->dev_private; 879 dev_priv = ring->dev->dev_private;
896 ret = intel_wait_ring_buffer(ring, ring->size - 8); 880 ret = intel_wait_ring_buffer(ring, ring->size - 8);
881 if (ret)
882 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
883 ring->name, ret);
884
897 I915_WRITE_CTL(ring, 0); 885 I915_WRITE_CTL(ring, 0);
898 886
899 drm_core_ioremapfree(&ring->map, ring->dev); 887 drm_core_ioremapfree(&ring->map, ring->dev);
@@ -950,13 +938,13 @@ int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
950 return 0; 938 return 0;
951 } 939 }
952 940
953 trace_i915_ring_wait_begin (dev); 941 trace_i915_ring_wait_begin(ring);
954 end = jiffies + 3 * HZ; 942 end = jiffies + 3 * HZ;
955 do { 943 do {
956 ring->head = I915_READ_HEAD(ring); 944 ring->head = I915_READ_HEAD(ring);
957 ring->space = ring_space(ring); 945 ring->space = ring_space(ring);
958 if (ring->space >= n) { 946 if (ring->space >= n) {
959 trace_i915_ring_wait_end(dev); 947 trace_i915_ring_wait_end(ring);
960 return 0; 948 return 0;
961 } 949 }
962 950
@@ -970,16 +958,20 @@ int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
970 if (atomic_read(&dev_priv->mm.wedged)) 958 if (atomic_read(&dev_priv->mm.wedged))
971 return -EAGAIN; 959 return -EAGAIN;
972 } while (!time_after(jiffies, end)); 960 } while (!time_after(jiffies, end));
973 trace_i915_ring_wait_end (dev); 961 trace_i915_ring_wait_end(ring);
974 return -EBUSY; 962 return -EBUSY;
975} 963}
976 964
977int intel_ring_begin(struct intel_ring_buffer *ring, 965int intel_ring_begin(struct intel_ring_buffer *ring,
978 int num_dwords) 966 int num_dwords)
979{ 967{
968 struct drm_i915_private *dev_priv = ring->dev->dev_private;
980 int n = 4*num_dwords; 969 int n = 4*num_dwords;
981 int ret; 970 int ret;
982 971
972 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
973 return -EIO;
974
983 if (unlikely(ring->tail + n > ring->effective_size)) { 975 if (unlikely(ring->tail + n > ring->effective_size)) {
984 ret = intel_wrap_ring_buffer(ring); 976 ret = intel_wrap_ring_buffer(ring);
985 if (unlikely(ret)) 977 if (unlikely(ret))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 6d6fde85a636..bd6a5fbfa929 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -43,7 +43,7 @@ struct intel_ring_buffer {
43 RING_BLT = 0x4, 43 RING_BLT = 0x4,
44 } id; 44 } id;
45 u32 mmio_base; 45 u32 mmio_base;
46 void *virtual_start; 46 void __iomem *virtual_start;
47 struct drm_device *dev; 47 struct drm_device *dev;
48 struct drm_i915_gem_object *obj; 48 struct drm_i915_gem_object *obj;
49 49
@@ -58,6 +58,7 @@ struct intel_ring_buffer {
58 u32 irq_refcount; 58 u32 irq_refcount;
59 u32 irq_mask; 59 u32 irq_mask;
60 u32 irq_seqno; /* last seq seem at irq time */ 60 u32 irq_seqno; /* last seq seem at irq time */
61 u32 trace_irq_seqno;
61 u32 waiting_seqno; 62 u32 waiting_seqno;
62 u32 sync_seqno[I915_NUM_RINGS-1]; 63 u32 sync_seqno[I915_NUM_RINGS-1];
63 bool __must_check (*irq_get)(struct intel_ring_buffer *ring); 64 bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
@@ -141,6 +142,26 @@ intel_read_status_page(struct intel_ring_buffer *ring,
141 return ioread32(ring->status_page.page_addr + reg); 142 return ioread32(ring->status_page.page_addr + reg);
142} 143}
143 144
145/**
146 * Reads a dword out of the status page, which is written to from the command
147 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
148 * MI_STORE_DATA_IMM.
149 *
150 * The following dwords have a reserved meaning:
151 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
152 * 0x04: ring 0 head pointer
153 * 0x05: ring 1 head pointer (915-class)
154 * 0x06: ring 2 head pointer (915-class)
155 * 0x10-0x1b: Context status DWords (GM45)
156 * 0x1f: Last written status offset. (GM45)
157 *
158 * The area from dword 0x20 to 0x3ff is available for driver usage.
159 */
160#define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg)
161#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
162#define I915_GEM_HWS_INDEX 0x20
163#define I915_BREADCRUMB_INDEX 0x21
164
144void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); 165void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
145int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); 166int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
146int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); 167int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
@@ -166,6 +187,12 @@ int intel_init_blt_ring_buffer(struct drm_device *dev);
166u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); 187u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
167void intel_ring_setup_status_page(struct intel_ring_buffer *ring); 188void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
168 189
190static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
191{
192 if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
193 ring->trace_irq_seqno = seqno;
194}
195
169/* DRI warts */ 196/* DRI warts */
170int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); 197int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
171 198
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 7c50cdce84f0..19c817a2df0c 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -585,6 +585,7 @@ static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *i
585{ 585{
586 struct intel_sdvo_get_trained_inputs_response response; 586 struct intel_sdvo_get_trained_inputs_response response;
587 587
588 BUILD_BUG_ON(sizeof(response) != 1);
588 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 589 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
589 &response, sizeof(response))) 590 &response, sizeof(response)))
590 return false; 591 return false;
@@ -632,6 +633,7 @@ static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo
632{ 633{
633 struct intel_sdvo_pixel_clock_range clocks; 634 struct intel_sdvo_pixel_clock_range clocks;
634 635
636 BUILD_BUG_ON(sizeof(clocks) != 4);
635 if (!intel_sdvo_get_value(intel_sdvo, 637 if (!intel_sdvo_get_value(intel_sdvo,
636 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 638 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
637 &clocks, sizeof(clocks))) 639 &clocks, sizeof(clocks)))
@@ -699,6 +701,8 @@ intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
699static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 701static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
700 struct intel_sdvo_dtd *dtd) 702 struct intel_sdvo_dtd *dtd)
701{ 703{
704 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
705 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
702 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 706 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
703 &dtd->part1, sizeof(dtd->part1)) && 707 &dtd->part1, sizeof(dtd->part1)) &&
704 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 708 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
@@ -796,6 +800,7 @@ static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
796{ 800{
797 struct intel_sdvo_encode encode; 801 struct intel_sdvo_encode encode;
798 802
803 BUILD_BUG_ON(sizeof(encode) != 2);
799 return intel_sdvo_get_value(intel_sdvo, 804 return intel_sdvo_get_value(intel_sdvo,
800 SDVO_CMD_GET_SUPP_ENCODE, 805 SDVO_CMD_GET_SUPP_ENCODE,
801 &encode, sizeof(encode)); 806 &encode, sizeof(encode));
@@ -1162,6 +1167,7 @@ static int intel_sdvo_mode_valid(struct drm_connector *connector,
1162 1167
1163static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1168static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1164{ 1169{
1170 BUILD_BUG_ON(sizeof(*caps) != 8);
1165 if (!intel_sdvo_get_value(intel_sdvo, 1171 if (!intel_sdvo_get_value(intel_sdvo,
1166 SDVO_CMD_GET_DEVICE_CAPS, 1172 SDVO_CMD_GET_DEVICE_CAPS,
1167 caps, sizeof(*caps))) 1173 caps, sizeof(*caps)))
@@ -1268,33 +1274,9 @@ void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1268static bool 1274static bool
1269intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1275intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1270{ 1276{
1271 int caps = 0; 1277 /* Is there more than one type of output? */
1272 1278 int caps = intel_sdvo->caps.output_flags & 0xf;
1273 if (intel_sdvo->caps.output_flags & 1279 return caps & -caps;
1274 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1275 caps++;
1276 if (intel_sdvo->caps.output_flags &
1277 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1278 caps++;
1279 if (intel_sdvo->caps.output_flags &
1280 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1281 caps++;
1282 if (intel_sdvo->caps.output_flags &
1283 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1284 caps++;
1285 if (intel_sdvo->caps.output_flags &
1286 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1287 caps++;
1288
1289 if (intel_sdvo->caps.output_flags &
1290 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1291 caps++;
1292
1293 if (intel_sdvo->caps.output_flags &
1294 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1295 caps++;
1296
1297 return (caps > 1);
1298} 1280}
1299 1281
1300static struct edid * 1282static struct edid *
@@ -2268,6 +2250,7 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2268 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2250 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2269 return false; 2251 return false;
2270 2252
2253 BUILD_BUG_ON(sizeof(format) != 6);
2271 if (!intel_sdvo_get_value(intel_sdvo, 2254 if (!intel_sdvo_get_value(intel_sdvo,
2272 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2255 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2273 &format, sizeof(format))) 2256 &format, sizeof(format)))
@@ -2474,6 +2457,8 @@ static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2474 uint16_t response; 2457 uint16_t response;
2475 } enhancements; 2458 } enhancements;
2476 2459
2460 BUILD_BUG_ON(sizeof(enhancements) != 2);
2461
2477 enhancements.response = 0; 2462 enhancements.response = 0;
2478 intel_sdvo_get_value(intel_sdvo, 2463 intel_sdvo_get_value(intel_sdvo,
2479 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2464 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index fe4a53a50b83..4256b8ef3947 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1006,6 +1006,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1006 const struct video_levels *video_levels; 1006 const struct video_levels *video_levels;
1007 const struct color_conversion *color_conversion; 1007 const struct color_conversion *color_conversion;
1008 bool burst_ena; 1008 bool burst_ena;
1009 int pipe = intel_crtc->pipe;
1009 1010
1010 if (!tv_mode) 1011 if (!tv_mode)
1011 return; /* can't happen (mode_prepare prevents this) */ 1012 return; /* can't happen (mode_prepare prevents this) */
@@ -1149,14 +1150,11 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1149 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | 1150 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
1150 (video_levels->blank << TV_BLANK_LEVEL_SHIFT))); 1151 (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
1151 { 1152 {
1152 int pipeconf_reg = (intel_crtc->pipe == 0) ? 1153 int pipeconf_reg = PIPECONF(pipe);
1153 PIPEACONF : PIPEBCONF; 1154 int dspcntr_reg = DSPCNTR(pipe);
1154 int dspcntr_reg = (intel_crtc->plane == 0) ?
1155 DSPACNTR : DSPBCNTR;
1156 int pipeconf = I915_READ(pipeconf_reg); 1155 int pipeconf = I915_READ(pipeconf_reg);
1157 int dspcntr = I915_READ(dspcntr_reg); 1156 int dspcntr = I915_READ(dspcntr_reg);
1158 int dspbase_reg = (intel_crtc->plane == 0) ? 1157 int dspbase_reg = DSPADDR(pipe);
1159 DSPAADDR : DSPBADDR;
1160 int xpos = 0x0, ypos = 0x0; 1158 int xpos = 0x0, ypos = 0x0;
1161 unsigned int xsize, ysize; 1159 unsigned int xsize, ysize;
1162 /* Pipe must be off here */ 1160 /* Pipe must be off here */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 19:24:23 -0400