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-rw-r--r--arch/sh/oprofile/op_model_sh7750.c6
-rw-r--r--drivers/serial/sh-sci.c17
-rw-r--r--drivers/serial/sh-sci.h82
3 files changed, 18 insertions, 87 deletions
diff --git a/arch/sh/oprofile/op_model_sh7750.c b/arch/sh/oprofile/op_model_sh7750.c
index 6b9a98e07004..008b3b03750a 100644
--- a/arch/sh/oprofile/op_model_sh7750.c
+++ b/arch/sh/oprofile/op_model_sh7750.c
@@ -255,10 +255,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
255 return -ENODEV; 255 return -ENODEV;
256 256
257 ops = &sh7750_perf_counter_ops; 257 ops = &sh7750_perf_counter_ops;
258 ops->cpu_type = (char *)get_cpu_subtype(&current_cpu_data); 258 ops->cpu_type = "sh/sh7750";
259 259
260 printk(KERN_INFO "oprofile: using SH-4 (%s) performance monitoring.\n", 260 printk(KERN_INFO "oprofile: using SH-4 performance monitoring.\n");
261 sh7750_perf_counter_ops.cpu_type);
262 261
263 /* Clear the counters */ 262 /* Clear the counters */
264 ctrl_outw(ctrl_inw(PMCR1) | PMCR_PMCLR, PMCR1); 263 ctrl_outw(ctrl_inw(PMCR1) | PMCR_PMCLR, PMCR1);
@@ -270,4 +269,3 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
270void oprofile_arch_exit(void) 269void oprofile_arch_exit(void)
271{ 270{
272} 271}
273
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index f0658d2c45b2..47816e68c903 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -250,8 +250,7 @@ static inline void h8300_sci_disable(struct uart_port *port)
250} 250}
251#endif 251#endif
252 252
253#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \ 253#if defined(__H8300H__) || defined(__H8300S__)
254 defined(__H8300H__) || defined(__H8300S__)
255static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) 254static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
256{ 255{
257 int ch = (port->mapbase - SMR0) >> 3; 256 int ch = (port->mapbase - SMR0) >> 3;
@@ -285,11 +284,6 @@ static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
285#define sci_init_pins_irda NULL 284#define sci_init_pins_irda NULL
286#endif 285#endif
287 286
288#ifdef SCI_ONLY
289#define sci_init_pins_scif NULL
290#endif
291
292#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
293#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 287#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
294static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag) 288static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
295{ 289{
@@ -449,7 +443,6 @@ static inline int scif_rxroom(struct uart_port *port)
449 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; 443 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
450} 444}
451#endif 445#endif
452#endif /* SCIF_ONLY || SCI_AND_SCIF */
453 446
454static inline int sci_txroom(struct uart_port *port) 447static inline int sci_txroom(struct uart_port *port)
455{ 448{
@@ -485,11 +478,9 @@ static void sci_transmit_chars(struct uart_port *port)
485 return; 478 return;
486 } 479 }
487 480
488#ifndef SCI_ONLY
489 if (port->type == PORT_SCIF) 481 if (port->type == PORT_SCIF)
490 count = scif_txroom(port); 482 count = scif_txroom(port);
491 else 483 else
492#endif
493 count = sci_txroom(port); 484 count = sci_txroom(port);
494 485
495 do { 486 do {
@@ -519,12 +510,10 @@ static void sci_transmit_chars(struct uart_port *port)
519 } else { 510 } else {
520 ctrl = sci_in(port, SCSCR); 511 ctrl = sci_in(port, SCSCR);
521 512
522#if !defined(SCI_ONLY)
523 if (port->type == PORT_SCIF) { 513 if (port->type == PORT_SCIF) {
524 sci_in(port, SCxSR); /* Dummy read */ 514 sci_in(port, SCxSR); /* Dummy read */
525 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 515 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
526 } 516 }
527#endif
528 517
529 ctrl |= SCI_CTRL_FLAGS_TIE; 518 ctrl |= SCI_CTRL_FLAGS_TIE;
530 sci_out(port, SCSCR, ctrl); 519 sci_out(port, SCSCR, ctrl);
@@ -547,11 +536,9 @@ static inline void sci_receive_chars(struct uart_port *port)
547 return; 536 return;
548 537
549 while (1) { 538 while (1) {
550#if !defined(SCI_ONLY)
551 if (port->type == PORT_SCIF) 539 if (port->type == PORT_SCIF)
552 count = scif_rxroom(port); 540 count = scif_rxroom(port);
553 else 541 else
554#endif
555 count = sci_rxroom(port); 542 count = sci_rxroom(port);
556 543
557 /* Don't copy more bytes than there is room for in the buffer */ 544 /* Don't copy more bytes than there is room for in the buffer */
@@ -1054,10 +1041,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1054 1041
1055 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1042 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1056 1043
1057#if !defined(SCI_ONLY)
1058 if (port->type == PORT_SCIF) 1044 if (port->type == PORT_SCIF)
1059 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1045 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1060#endif
1061 1046
1062 smr_val = sci_in(port, SCSMR) & 3; 1047 smr_val = sci_in(port, SCSMR) & 3;
1063 if ((termios->c_cflag & CSIZE) == CS7) 1048 if ((termios->c_cflag & CSIZE) == CS7)
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 44e952bca1ef..36ce9de4b2cd 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -16,7 +16,6 @@
16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19# define SCI_AND_SCIF
20#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 19#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
21# define SCIF0 0xA4400000 20# define SCIF0 0xA4400000
22# define SCIF2 0xA4410000 21# define SCIF2 0xA4410000
@@ -30,17 +29,14 @@
30 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output 29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
31 */ 30 */
32# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
33# define SCIF_ONLY
34#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7721) 33 defined(CONFIG_CPU_SUBTYPE_SH7721)
36# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 34# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
37# define SCIF_ONLY
38#define SCIF_ORER 0x0200 /* overrun error bit */ 35#define SCIF_ORER 0x0200 /* overrun error bit */
39#elif defined(CONFIG_SH_RTS7751R2D) 36#elif defined(CONFIG_SH_RTS7751R2D)
40# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 37# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
41# define SCIF_ORER 0x0001 /* overrun error bit */ 38# define SCIF_ORER 0x0001 /* overrun error bit */
42# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 39# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
43# define SCIF_ONLY
44#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 40#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 41 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 42 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
@@ -53,28 +49,24 @@
53# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 49# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
54 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 50 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
55 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) 51 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
56# define SCI_AND_SCIF
57#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 52#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
58# define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 53# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
59# define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 54# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
60# define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 55# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
61# define SCIF_ORER 0x0001 /* overrun error bit */ 56# define SCIF_ORER 0x0001 /* overrun error bit */
62# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 57# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
63# define SCIF_ONLY
64#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 58#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
65# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 59# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
66# define SCIF_ORER 0x0001 /* overrun error bit */ 60# define SCIF_ORER 0x0001 /* overrun error bit */
67# define PACR 0xa4050100 61# define PACR 0xa4050100
68# define PBCR 0xa4050102 62# define PBCR 0xa4050102
69# define SCSCR_INIT(port) 0x3B 63# define SCSCR_INIT(port) 0x3B
70# define SCIF_ONLY
71#elif defined(CONFIG_CPU_SUBTYPE_SH7343) 64#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
72# define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 65# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
73# define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 66# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
74# define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 67# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
75# define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 68# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
76# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 69# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
77# define SCIF_ONLY
78#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 70#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
79# define PADR 0xA4050120 71# define PADR 0xA4050120
80# define PSDR 0xA405013e 72# define PSDR 0xA405013e
@@ -82,7 +74,6 @@
82# define PSCR 0xA405011E 74# define PSCR 0xA405011E
83# define SCIF_ORER 0x0001 /* overrun error bit */ 75# define SCIF_ORER 0x0001 /* overrun error bit */
84# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 76# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
85# define SCIF_ONLY
86#elif defined(CONFIG_CPU_SUBTYPE_SH7366) 77#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
87# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 78# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
88# define SCSPTR0 SCPDR0 79# define SCSPTR0 SCPDR0
@@ -98,12 +89,10 @@
98# define SCSPTR5 0xa4050128 89# define SCSPTR5 0xa4050128
99# define SCIF_ORER 0x0001 /* overrun error bit */ 90# define SCIF_ORER 0x0001 /* overrun error bit */
100# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 91# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
101# define SCIF_ONLY
102#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 92#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
103# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 93# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
104# define SCIF_ORER 0x0001 /* overrun error bit */ 94# define SCIF_ORER 0x0001 /* overrun error bit */
105# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 95# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
106# define SCIF_ONLY
107#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 96#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
108# define SCIF_BASE_ADDR 0x01030000 97# define SCIF_BASE_ADDR 0x01030000
109# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR 98# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
@@ -112,14 +101,11 @@
112# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 101# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
113# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 102# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
114# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ 103# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
115# define SCIF_ONLY
116#elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 104#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
117# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 105# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
118# define SCI_ONLY
119# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 106# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
120#elif defined(CONFIG_H8S2678) 107#elif defined(CONFIG_H8S2678)
121# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 108# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
122# define SCI_ONLY
123# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 109# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
124#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 110#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
125# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 111# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
@@ -127,20 +113,17 @@
127# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 113# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
128# define SCIF_ORER 0x0001 /* overrun error bit */ 114# define SCIF_ORER 0x0001 /* overrun error bit */
129# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 115# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
130# define SCIF_ONLY
131#elif defined(CONFIG_CPU_SUBTYPE_SH7770) 116#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
132# define SCSPTR0 0xff923020 /* 16 bit SCIF */ 117# define SCSPTR0 0xff923020 /* 16 bit SCIF */
133# define SCSPTR1 0xff924020 /* 16 bit SCIF */ 118# define SCSPTR1 0xff924020 /* 16 bit SCIF */
134# define SCSPTR2 0xff925020 /* 16 bit SCIF */ 119# define SCSPTR2 0xff925020 /* 16 bit SCIF */
135# define SCIF_ORER 0x0001 /* overrun error bit */ 120# define SCIF_ORER 0x0001 /* overrun error bit */
136# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ 121# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
137# define SCIF_ONLY
138#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 122#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
139# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 123# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
140# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 124# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
141# define SCIF_ORER 0x0001 /* Overrun error bit */ 125# define SCIF_ORER 0x0001 /* Overrun error bit */
142# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 126# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
143# define SCIF_ONLY
144#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 127#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
145# define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 128# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
146# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 129# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
@@ -150,7 +133,6 @@
150# define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 133# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
151# define SCIF_OPER 0x0001 /* Overrun error bit */ 134# define SCIF_OPER 0x0001 /* Overrun error bit */
152# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 135# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
153# define SCIF_ONLY
154#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ 136#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
155 defined(CONFIG_CPU_SUBTYPE_SH7206) || \ 137 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
156 defined(CONFIG_CPU_SUBTYPE_SH7263) 138 defined(CONFIG_CPU_SUBTYPE_SH7263)
@@ -159,14 +141,12 @@
159# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 141# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
160# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 142# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
161# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 143# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
162# define SCIF_ONLY
163#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 144#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
164# define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 145# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
165# define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 146# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
166# define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 147# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
167# define SCIF_ORER 0x0001 /* overrun error bit */ 148# define SCIF_ORER 0x0001 /* overrun error bit */
168# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 149# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
169# define SCIF_ONLY
170#elif defined(CONFIG_CPU_SUBTYPE_SHX3) 150#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
171# define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 151# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
172# define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 152# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
@@ -174,7 +154,6 @@
174# define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 154# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
175# define SCIF_ORER 0x0001 /* Overrun error bit */ 155# define SCIF_ORER 0x0001 /* Overrun error bit */
176# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 156# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
177# define SCIF_ONLY
178#else 157#else
179# error CPU subtype not defined 158# error CPU subtype not defined
180#endif 159#endif
@@ -245,55 +224,28 @@
245# define SCIF_TXROOM_MAX 16 224# define SCIF_TXROOM_MAX 16
246#endif 225#endif
247 226
248#if defined(SCI_ONLY) 227#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
249# define SCxSR_TEND(port) SCI_TEND 228#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
250# define SCxSR_ERRORS(port) SCI_ERRORS 229#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
251# define SCxSR_RDxF(port) SCI_RDRF 230#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
252# define SCxSR_TDxE(port) SCI_TDRE 231#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
253# define SCxSR_ORER(port) SCI_ORER 232#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
254# define SCxSR_FER(port) SCI_FER 233#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
255# define SCxSR_PER(port) SCI_PER 234
256# define SCxSR_BRK(port) 0x00
257# define SCxSR_RDxF_CLEAR(port) 0xbc
258# define SCxSR_ERROR_CLEAR(port) 0xc4
259# define SCxSR_TDxE_CLEAR(port) 0x78
260# define SCxSR_BREAK_CLEAR(port) 0xc4
261#elif defined(SCIF_ONLY)
262# define SCxSR_TEND(port) SCIF_TEND
263# define SCxSR_ERRORS(port) SCIF_ERRORS
264# define SCxSR_RDxF(port) SCIF_RDF
265# define SCxSR_TDxE(port) SCIF_TDFE
266#if defined(CONFIG_CPU_SUBTYPE_SH7705) 235#if defined(CONFIG_CPU_SUBTYPE_SH7705)
267# define SCxSR_ORER(port) SCIF_ORER 236# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
268#else 237#else
269# define SCxSR_ORER(port) 0x0000 238# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
270#endif 239#endif
271# define SCxSR_FER(port) SCIF_FER 240
272# define SCxSR_PER(port) SCIF_PER
273# define SCxSR_BRK(port) SCIF_BRK
274#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 241#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
275 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 242 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
276 defined(CONFIG_CPU_SUBTYPE_SH7721) 243 defined(CONFIG_CPU_SUBTYPE_SH7721)
277# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) 244# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
278# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) 245# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
279# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) 246# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
280# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) 247# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
281#else
282/* SH7705 can also use this, clearing is same between 7705 and 7709 */
283# define SCxSR_RDxF_CLEAR(port) 0x00fc
284# define SCxSR_ERROR_CLEAR(port) 0x0073
285# define SCxSR_TDxE_CLEAR(port) 0x00df
286# define SCxSR_BREAK_CLEAR(port) 0x00e3
287#endif
288#else 248#else
289# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
290# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
291# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
292# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
293# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
294# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
295# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
296# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
297# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 249# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
298# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 250# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
299# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) 251# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
@@ -579,14 +531,10 @@ static inline int sci_rxd_in(struct uart_port *port)
579 defined(CONFIG_CPU_SUBTYPE_SH4_202) 531 defined(CONFIG_CPU_SUBTYPE_SH4_202)
580static inline int sci_rxd_in(struct uart_port *port) 532static inline int sci_rxd_in(struct uart_port *port)
581{ 533{
582#ifndef SCIF_ONLY
583 if (port->mapbase == 0xffe00000) 534 if (port->mapbase == 0xffe00000)
584 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 535 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
585#endif
586#ifndef SCI_ONLY
587 if (port->mapbase == 0xffe80000) 536 if (port->mapbase == 0xffe80000)
588 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 537 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
589#endif
590 return 1; 538 return 1;
591} 539}
592#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 540#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-13 05:57:09 -0400