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-rw-r--r--drivers/staging/Kconfig2
-rw-r--r--drivers/staging/Makefile1
-rw-r--r--drivers/staging/winbond/Kconfig7
-rw-r--r--drivers/staging/winbond/Makefile18
-rw-r--r--drivers/staging/winbond/README10
-rw-r--r--drivers/staging/winbond/adapter.h23
-rw-r--r--drivers/staging/winbond/bss_f.h59
-rw-r--r--drivers/staging/winbond/bssdscpt.h156
-rw-r--r--drivers/staging/winbond/ds_tkip.h33
-rw-r--r--drivers/staging/winbond/gl_80211.h125
-rw-r--r--drivers/staging/winbond/ioctls.h678
-rw-r--r--drivers/staging/winbond/linux/common.h143
-rw-r--r--drivers/staging/winbond/linux/sysdef.h73
-rw-r--r--drivers/staging/winbond/linux/wb35reg.c747
-rw-r--r--drivers/staging/winbond/linux/wb35reg_f.h56
-rw-r--r--drivers/staging/winbond/linux/wb35reg_s.h170
-rw-r--r--drivers/staging/winbond/linux/wb35rx.c337
-rw-r--r--drivers/staging/winbond/linux/wb35rx_f.h17
-rw-r--r--drivers/staging/winbond/linux/wb35rx_s.h48
-rw-r--r--drivers/staging/winbond/linux/wb35tx.c313
-rw-r--r--drivers/staging/winbond/linux/wb35tx_f.h20
-rw-r--r--drivers/staging/winbond/linux/wb35tx_s.h47
-rw-r--r--drivers/staging/winbond/linux/wbusb.c404
-rw-r--r--drivers/staging/winbond/linux/wbusb_f.h34
-rw-r--r--drivers/staging/winbond/linux/wbusb_s.h42
-rw-r--r--drivers/staging/winbond/localpara.h275
-rw-r--r--drivers/staging/winbond/mac_structures.h670
-rw-r--r--drivers/staging/winbond/mds.c630
-rw-r--r--drivers/staging/winbond/mds_f.h33
-rw-r--r--drivers/staging/winbond/mds_s.h183
-rw-r--r--drivers/staging/winbond/mlme_mib.h84
-rw-r--r--drivers/staging/winbond/mlme_s.h195
-rw-r--r--drivers/staging/winbond/mlmetxrx.c150
-rw-r--r--drivers/staging/winbond/mlmetxrx_f.h52
-rw-r--r--drivers/staging/winbond/mto.c1229
-rw-r--r--drivers/staging/winbond/mto.h265
-rw-r--r--drivers/staging/winbond/mto_f.h7
-rw-r--r--drivers/staging/winbond/os_common.h2
-rw-r--r--drivers/staging/winbond/phy_calibration.c1759
-rw-r--r--drivers/staging/winbond/phy_calibration.h101
-rw-r--r--drivers/staging/winbond/reg.c2683
-rw-r--r--drivers/staging/winbond/rxisr.c30
-rw-r--r--drivers/staging/winbond/scan_s.h115
-rw-r--r--drivers/staging/winbond/sme_api.c13
-rw-r--r--drivers/staging/winbond/sme_api.h265
-rw-r--r--drivers/staging/winbond/sme_s.h228
-rw-r--r--drivers/staging/winbond/wb35_ver.h30
-rw-r--r--drivers/staging/winbond/wbhal.c878
-rw-r--r--drivers/staging/winbond/wbhal_f.h122
-rw-r--r--drivers/staging/winbond/wbhal_s.h615
-rw-r--r--drivers/staging/winbond/wblinux.c277
-rw-r--r--drivers/staging/winbond/wblinux_f.h23
-rw-r--r--drivers/staging/winbond/wblinux_s.h45
53 files changed, 14522 insertions, 0 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 4dbf795df744..fdbdf84e3077 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -35,4 +35,6 @@ source "drivers/staging/go7007/Kconfig"
35 35
36source "drivers/staging/usbip/Kconfig" 36source "drivers/staging/usbip/Kconfig"
37 37
38source "drivers/staging/winbond/Kconfig"
39
38endif # STAGING 40endif # STAGING
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index be42c0d4db0e..9b576c91b15e 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_SXG) += sxg/
6obj-$(CONFIG_ME4000) += me4000/ 6obj-$(CONFIG_ME4000) += me4000/
7obj-$(CONFIG_VIDEO_GO7007) += go7007/ 7obj-$(CONFIG_VIDEO_GO7007) += go7007/
8obj-$(CONFIG_USB_IP_COMMON) += usbip/ 8obj-$(CONFIG_USB_IP_COMMON) += usbip/
9obj-$(CONFIG_W35UND) += winbond/
diff --git a/drivers/staging/winbond/Kconfig b/drivers/staging/winbond/Kconfig
new file mode 100644
index 000000000000..10d72bec88a9
--- /dev/null
+++ b/drivers/staging/winbond/Kconfig
@@ -0,0 +1,7 @@
1config W35UND
2 tristate "Winbond driver"
3 depends on MAC80211 && WLAN_80211 && EXPERIMENTAL && !4KSTACKS
4 default n
5 ---help---
6 This is highly experimental driver for winbond wifi card on some Kohjinsha notebooks
7 Check http://code.google.com/p/winbondport/ for new version
diff --git a/drivers/staging/winbond/Makefile b/drivers/staging/winbond/Makefile
new file mode 100644
index 000000000000..29c98bf1bc98
--- /dev/null
+++ b/drivers/staging/winbond/Makefile
@@ -0,0 +1,18 @@
1 DRIVER_DIR=./linux
2
3w35und-objs := $(DRIVER_DIR)/wbusb.o $(DRIVER_DIR)/wb35reg.o $(DRIVER_DIR)/wb35rx.o $(DRIVER_DIR)/wb35tx.o \
4 mds.o \
5 mlmetxrx.o \
6 mto.o \
7 phy_calibration.o \
8 reg.o \
9 rxisr.o \
10 sme_api.o \
11 wbhal.o \
12 wblinux.o \
13
14
15obj-$(CONFIG_W35UND) += w35und.o
16
17
18
diff --git a/drivers/staging/winbond/README b/drivers/staging/winbond/README
new file mode 100644
index 000000000000..707b6b354dc5
--- /dev/null
+++ b/drivers/staging/winbond/README
@@ -0,0 +1,10 @@
1TODO:
2 - sparse cleanups
3 - checkpatch cleanups
4 - kerneldoc cleanups
5 - remove typedefs
6 - remove unused ioctls
7 - use cfg80211 for regulatory stuff
8
9Please send patches to Greg Kroah-Hartman <greg@kroah.com> and
10Pavel Machek <pavel@suse.cz>
diff --git a/drivers/staging/winbond/adapter.h b/drivers/staging/winbond/adapter.h
new file mode 100644
index 000000000000..609701d21cf0
--- /dev/null
+++ b/drivers/staging/winbond/adapter.h
@@ -0,0 +1,23 @@
1//
2// ADAPTER.H -
3// Windows NDIS global variable 'Adapter' typedef
4//
5#define MAX_ANSI_STRING 40
6typedef struct WB32_ADAPTER
7{
8 u32 AdapterIndex; // 20060703.4 Add for using pAdapterContext global Adapter point
9
10 WB_LOCALDESCRIPT sLocalPara; // Myself connected parameters
11 PWB_BSSDESCRIPTION asBSSDescriptElement;
12
13 MLME_FRAME sMlmeFrame; // connect to peerSTA parameters
14
15 MTO_PARAMETERS sMtoPara; // MTO_struct ...
16 hw_data_t sHwData; //For HAL
17 MDS Mds;
18
19 WBLINUX WbLinux;
20 struct iw_statistics iw_stats;
21
22 u8 LinkName[MAX_ANSI_STRING];
23} WB32_ADAPTER, ADAPTER, *PWB32_ADAPTER, *PADAPTER;
diff --git a/drivers/staging/winbond/bss_f.h b/drivers/staging/winbond/bss_f.h
new file mode 100644
index 000000000000..c957bc94f08d
--- /dev/null
+++ b/drivers/staging/winbond/bss_f.h
@@ -0,0 +1,59 @@
1//
2// BSS descriptor DataBase management global function
3//
4
5void vBSSdescriptionInit(PWB32_ADAPTER Adapter);
6void vBSSfoundList(PWB32_ADAPTER Adapter);
7u8 boChanFilter(PWB32_ADAPTER Adapter, u8 ChanNo);
8u16 wBSSallocateEntry(PWB32_ADAPTER Adapter);
9u16 wBSSGetEntry(PWB32_ADAPTER Adapter);
10void vSimpleHouseKeeping(PWB32_ADAPTER Adapter);
11u16 wBSShouseKeeping(PWB32_ADAPTER Adapter);
12void ClearBSSdescpt(PWB32_ADAPTER Adapter, u16 i);
13u16 wBSSfindBssID(PWB32_ADAPTER Adapter, u8 *pbBssid);
14u16 wBSSfindDedicateCandidate(PWB32_ADAPTER Adapter, struct SSID_Element *psSsid, u8 *pbBssid);
15u16 wBSSfindMACaddr(PWB32_ADAPTER Adapter, u8 *pbMacAddr);
16u16 wBSSsearchMACaddr(PWB32_ADAPTER Adapter, u8 *pbMacAddr, u8 band);
17u16 wBSSaddScanData(PWB32_ADAPTER, u16, psRXDATA);
18u16 wBSSUpdateScanData(PWB32_ADAPTER Adapter, u16 wBssIdx, psRXDATA psRcvData);
19u16 wBSScreateIBSSdata(PWB32_ADAPTER Adapter, PWB_BSSDESCRIPTION psDesData);
20void DesiredRate2BSSdescriptor(PWB32_ADAPTER Adapter, PWB_BSSDESCRIPTION psDesData,
21 u8 *pBasicRateSet, u8 BasicRateCount,
22 u8 *pOperationRateSet, u8 OperationRateCount);
23void DesiredRate2InfoElement(PWB32_ADAPTER Adapter, u8 *addr, u16 *iFildOffset,
24 u8 *pBasicRateSet, u8 BasicRateCount,
25 u8 *pOperationRateSet, u8 OperationRateCount);
26void BSSAddIBSSdata(PWB32_ADAPTER Adapter, PWB_BSSDESCRIPTION psDesData);
27unsigned char boCmpMacAddr( PUCHAR, PUCHAR );
28unsigned char boCmpSSID(struct SSID_Element *psSSID1, struct SSID_Element *psSSID2);
29u16 wBSSfindSSID(PWB32_ADAPTER Adapter, struct SSID_Element *psSsid);
30u16 wRoamingQuery(PWB32_ADAPTER Adapter);
31void vRateToBitmap(PWB32_ADAPTER Adapter, u16 index);
32u8 bRateToBitmapIndex(PWB32_ADAPTER Adapter, u8 bRate);
33u8 bBitmapToRate(u8 i);
34unsigned char boIsERPsta(PWB32_ADAPTER Adapter, u16 i);
35unsigned char boCheckConnect(PWB32_ADAPTER Adapter);
36unsigned char boCheckSignal(PWB32_ADAPTER Adapter);
37void AddIBSSIe(PWB32_ADAPTER Adapter,PWB_BSSDESCRIPTION psDesData );//added by ws for WPA_None06/01/04
38void BssScanUpToDate(PWB32_ADAPTER Adapter);
39void BssUpToDate(PWB32_ADAPTER Adapter);
40void RateSort(u8 *RateArray, u8 num, u8 mode);
41void RateReSortForSRate(PWB32_ADAPTER Adapter, u8 *RateArray, u8 num);
42void Assemble_IE(PWB32_ADAPTER Adapter, u16 wBssIdx);
43void SetMaxTxRate(PWB32_ADAPTER Adapter);
44
45void CreateWpaIE(PWB32_ADAPTER Adapter, u16* iFildOffset, PUCHAR msg, struct Management_Frame* msgHeader,
46 struct Association_Request_Frame_Body* msgBody, u16 iMSindex); //added by WS 05/14/05
47
48#ifdef _WPA2_
49void CreateRsnIE(PWB32_ADAPTER Adapter, u16* iFildOffset, PUCHAR msg, struct Management_Frame* msgHeader,
50 struct Association_Request_Frame_Body* msgBody, u16 iMSindex);//added by WS 05/14/05
51
52u16 SearchPmkid(PWB32_ADAPTER Adapter, struct Management_Frame* msgHeader,
53 struct PMKID_Information_Element * AssoReq_PMKID );
54#endif
55
56
57
58
59
diff --git a/drivers/staging/winbond/bssdscpt.h b/drivers/staging/winbond/bssdscpt.h
new file mode 100644
index 000000000000..97150a2655fb
--- /dev/null
+++ b/drivers/staging/winbond/bssdscpt.h
@@ -0,0 +1,156 @@
1//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2// bssdscpt.c
3// BSS descriptor data base
4// history :
5//
6// Description:
7// BSS descriptor data base will store the information of the stations at the
8// surrounding environment. The first entry( psBSS(0) ) will not be used and the
9// second one( psBSS(1) ) will be used for the broadcast address.
10//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
11
12//#define MAX_ACC_RSSI_COUNT 10
13#define MAX_ACC_RSSI_COUNT 6
14
15///////////////////////////////////////////////////////////////////////////
16//
17// BSS Description set Element , to store scan received Beacon information
18//
19// Our's differs slightly from the specs. The specify a PHY_Parameter_Set.
20// Since we're only doing a DS design right now, we just have a DS structure.
21//////////////////////////////////////////////////////////////////////////////
22typedef struct BSSDescriptionElement
23{
24 u32 SlotValid;
25 u32 PowerSaveMode;
26 RXLAYER1 RxLayer1;
27
28 u8 abPeerAddress[ MAC_ADDR_LENGTH + 2 ]; // peer MAC Address associated with this session. 6-OCTET value
29 u32 dwBgScanStamp; // BgScan Sequence Counter stamp, record psROAM->dwScanCounter.
30
31 u16 Beacon_Period;
32 u16 wATIM_Window;
33
34 u8 abBssID[ MAC_ADDR_LENGTH + 2 ]; // 6B
35
36 u8 bBssType;
37 u8 DTIM_Period; // 1 octet usually from TIM element, if present
38 u8 boInTimerHandler;
39 u8 boERP; // analysis ERP or (extended) supported rate element
40
41 u8 Timestamp[8];
42 u8 BasicRate[32];
43 u8 OperationalRate[32];
44 u32 dwBasicRateBitmap; //bit map, retrieve from SupportedRateSet
45 u32 dwOperationalRateBitmap; //bit map, retrieve from SupportedRateSet and
46 // ExtendedSupportedRateSet
47 // For RSSI calculating
48 u32 HalRssi[MAX_ACC_RSSI_COUNT]; // Encode. It must use MACRO of HAL to get the LNA and AGC data
49 u32 HalRssiIndex;
50
51 ////From beacon/probe response
52 struct SSID_Element SSID; // 34B
53 u8 reserved_1[ 2 ];
54
55 struct Capability_Information_Element CapabilityInformation; // 2B
56 u8 reserved_2[ 2 ];
57
58 struct CF_Parameter_Set_Element CF_Parameter_Set; // 8B
59 struct IBSS_Parameter_Set_Element IBSS_Parameter_Set; // 4B
60 struct TIM_Element TIM_Element_Set; // 256B
61
62 struct DS_Parameter_Set_Element DS_Parameter_Set; // 3B
63 u8 reserved_3;
64
65 struct ERP_Information_Element ERP_Information_Set; // 3B
66 u8 reserved_4;
67
68 struct Supported_Rates_Element SupportedRateSet; // 10B
69 u8 reserved_5[2];
70
71 struct Extended_Supported_Rates_Element ExtendedSupportedRateSet; // 257B
72 u8 reserved_6[3];
73
74 u8 band;
75 u8 reserved_7[3];
76
77 // for MLME module
78 u16 wState; // the current state of the system
79 u16 wIndex; // THIS BSS element entry index
80
81 void* psAdapter; // pointer to THIS Adapter
82 OS_TIMER nTimer; // MLME timer
83
84 // Authentication
85 u16 wAuthAlgo; // peer MAC MLME use Auth algorithm, default OPEN_AUTH
86 u16 wAuthSeqNum; // current local MAC sendout AuthReq sequence number
87
88 u8 auth_challengeText[128];
89
90 ////For XP:
91 u32 ies_len; // information element length
92 u8 ies[256]; // information element
93
94 ////For WPA
95 u8 RsnIe_Type[2]; //added by ws for distinguish WPA and WPA2 05/14/04
96 u8 RsnIe_len;
97 u8 Rsn_Num;
98
99 // to record the rsn cipher suites,addded by ws 09/05/04
100 SUITE_SELECTOR group_cipher; // 4B
101 SUITE_SELECTOR pairwise_key_cipher_suites[WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT];
102 SUITE_SELECTOR auth_key_mgt_suites[WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT];
103
104 u16 pairwise_key_cipher_suite_count;
105 u16 auth_key_mgt_suite_count;
106
107 u8 pairwise_key_cipher_suite_selected;
108 u8 auth_key_mgt_suite_selected;
109 u8 reserved_8[2];
110
111 struct RSN_Capability_Element rsn_capabilities; // 2B
112 u8 reserved_9[2];
113
114 //to record the rsn cipher suites for WPA2
115 #ifdef _WPA2_
116 u32 pre_auth; //added by WS for distinguish for 05/04/04
117 SUITE_SELECTOR wpa2_group_cipher; // 4B
118 SUITE_SELECTOR wpa2_pairwise_key_cipher_suites[WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT];
119 SUITE_SELECTOR wpa2_auth_key_mgt_suites[WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT];
120
121 u16 wpa2_pairwise_key_cipher_suite_count;
122 u16 wpa2_auth_key_mgt_suite_count;
123
124 u8 wpa2_pairwise_key_cipher_suite_selected;
125 u8 wpa2_auth_key_mgt_suite_selected;
126 u8 reserved_10[2];
127
128 struct RSN_Capability_Element wpa2_rsn_capabilities; // 2B
129 u8 reserved_11[2];
130 #endif //endif _WPA2_
131
132 //For Replay protection
133// u8 PairwiseTSC[6];
134// u8 GroupTSC[6];
135
136 ////For up-to-date
137 u32 ScanTimeStamp; //for the decision whether the station/AP(may exist at
138 //different channels) has left. It must be detected by
139 //scanning. Local device may connected or disconnected.
140 u32 BssTimeStamp; //Only for the decision whether the station/AP(exist in
141 //the same channel, and no scanning) if local device has
142 //connected successfully.
143
144 // 20061108 Add for storing WPS_IE. [E id][Length][OUI][Data]
145 u8 WPS_IE_Data[MAX_IE_APPEND_SIZE];
146 u16 WPS_IE_length;
147 u16 WPS_IE_length_tmp; // For verify there is an WPS_IE in Beacon or probe response
148
149} WB_BSSDESCRIPTION, *PWB_BSSDESCRIPTION;
150
151#define wBSSConnectedSTA(Adapter) \
152 ((u16)(Adapter)->sLocalPara.wConnectedSTAindex)
153
154#define psBSS(i) (&(Adapter->asBSSDescriptElement[(i)]))
155
156
diff --git a/drivers/staging/winbond/ds_tkip.h b/drivers/staging/winbond/ds_tkip.h
new file mode 100644
index 000000000000..29e5055b45a1
--- /dev/null
+++ b/drivers/staging/winbond/ds_tkip.h
@@ -0,0 +1,33 @@
1// Rotation functions on 32 bit values
2#define ROL32( A, n ) \
3 ( ((A) << (n)) | ( ((A)>>(32-(n))) & ( (1UL << (n)) - 1 ) ) )
4
5#define ROR32( A, n ) ROL32( (A), 32-(n) )
6
7
8typedef struct tkip
9{
10 u32 K0, K1; // Key
11 union
12 {
13 struct // Current state
14 {
15 u32 L;
16 u32 R;
17 };
18 u8 LR[8];
19 };
20 union
21 {
22 u32 M; // Message accumulator (single word)
23 u8 Mb[4];
24 };
25 s32 bytes_in_M; // # bytes in M
26} tkip_t;
27
28//void _append_data( PUCHAR pData, u16 size, tkip_t *p );
29void Mds_MicGet( void* Adapter, void* pRxLayer1, PUCHAR pKey, PUCHAR pMic );
30void Mds_MicFill( void* Adapter, void* pDes, PUCHAR XmitBufAddress );
31
32
33
diff --git a/drivers/staging/winbond/gl_80211.h b/drivers/staging/winbond/gl_80211.h
new file mode 100644
index 000000000000..1806d817496e
--- /dev/null
+++ b/drivers/staging/winbond/gl_80211.h
@@ -0,0 +1,125 @@
1
2#ifndef __GL_80211_H__
3#define __GL_80211_H__
4
5/****************** CONSTANT AND MACRO SECTION ******************************/
6
7/* BSS Type */
8enum {
9 WLAN_BSSTYPE_INFRASTRUCTURE = 0,
10 WLAN_BSSTYPE_INDEPENDENT,
11 WLAN_BSSTYPE_ANY_BSS,
12};
13
14
15
16/* Preamble_Type, see <SFS-802.11G-MIB-203> */
17typedef enum preamble_type {
18 WLAN_PREAMBLE_TYPE_SHORT,
19 WLAN_PREAMBLE_TYPE_LONG,
20} preamble_type_e;
21
22
23/* Slot_Time_Type, see <SFS-802.11G-MIB-208> */
24typedef enum slot_time_type {
25 WLAN_SLOT_TIME_TYPE_LONG,
26 WLAN_SLOT_TIME_TYPE_SHORT,
27} slot_time_type_e;
28
29/*--------------------------------------------------------------------------*/
30/* Encryption Mode */
31typedef enum {
32 WEP_DISABLE = 0,
33 WEP_64,
34 WEP_128,
35
36 ENCRYPT_DISABLE,
37 ENCRYPT_WEP,
38 ENCRYPT_WEP_NOKEY,
39 ENCRYPT_TKIP,
40 ENCRYPT_TKIP_NOKEY,
41 ENCRYPT_CCMP,
42 ENCRYPT_CCMP_NOKEY,
43} encryption_mode_e;
44
45typedef enum _WLAN_RADIO {
46 WLAN_RADIO_ON,
47 WLAN_RADIO_OFF,
48 WLAN_RADIO_MAX, // not a real type, defined as an upper bound
49} WLAN_RADIO;
50
51typedef struct _WLAN_RADIO_STATUS {
52 WLAN_RADIO HWStatus;
53 WLAN_RADIO SWStatus;
54} WLAN_RADIO_STATUS;
55
56//----------------------------------------------------------------------------
57// 20041021 1.1.81.1000 ybjiang
58// add for radio notification
59typedef
60void (*RADIO_NOTIFICATION_HANDLER)(
61 void *Data,
62 void *RadioStatusBuffer,
63 u32 RadioStatusBufferLen
64 );
65
66typedef struct _WLAN_RADIO_NOTIFICATION
67{
68 RADIO_NOTIFICATION_HANDLER RadioChangeHandler;
69 void *Data;
70} WLAN_RADIO_NOTIFICATION;
71
72//----------------------------------------------------------------------------
73// 20041102 1.1.91.1000 ybjiang
74// add for OID_802_11_CUST_REGION_CAPABILITIES and OID_802_11_OID_REGION
75typedef enum _WLAN_REGION_CODE
76{
77 WLAN_REGION_UNKNOWN,
78 WLAN_REGION_EUROPE,
79 WLAN_REGION_JAPAN,
80 WLAN_REGION_USA,
81 WLAN_REGION_FRANCE,
82 WLAN_REGION_SPAIN,
83 WLAN_REGION_ISRAEL,
84 WLAN_REGION_MAX, // not a real type, defined as an upper bound
85} WLAN_REGION_CODE;
86
87#define REGION_NAME_MAX_LENGTH 256
88
89typedef struct _WLAN_REGION_CHANNELS
90{
91 u32 Length;
92 u32 NameLength;
93 u8 Name[REGION_NAME_MAX_LENGTH];
94 WLAN_REGION_CODE Code;
95 u32 Frequency[1];
96} WLAN_REGION_CHANNELS;
97
98typedef struct _WLAN_REGION_CAPABILITIES
99{
100 u32 NumberOfItems;
101 WLAN_REGION_CHANNELS Region[1];
102} WLAN_REGION_CAPABILITIES;
103
104typedef struct _region_name_map {
105 WLAN_REGION_CODE region;
106 u8 *name;
107 u32 *channels;
108} region_name_map;
109
110/*--------------------------------------------------------------------------*/
111#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
112#define MACSTR "%02X:%02X:%02X:%02X:%02X:%02X"
113
114// TODO: 0627 kevin
115#define MIC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5], (a)[6], (a)[7]
116#define MICSTR "%02X %02X %02X %02X %02X %02X %02X %02X"
117
118#define MICKEY2STR(a) MIC2STR(a)
119#define MICKEYSTR MICSTR
120
121
122#endif /* __GL_80211_H__ */
123/*** end of file ***/
124
125
diff --git a/drivers/staging/winbond/ioctls.h b/drivers/staging/winbond/ioctls.h
new file mode 100644
index 000000000000..e8b35dc7e321
--- /dev/null
+++ b/drivers/staging/winbond/ioctls.h
@@ -0,0 +1,678 @@
1//============================================================================
2// IOCTLS.H -
3//
4// Description:
5// Define the IOCTL codes.
6//
7// Revision history:
8// --------------------------------------------------------------------------
9//
10// Copyright (c) 2002-2004 Winbond Electronics Corp. All rights reserved.
11//=============================================================================
12
13#ifndef _IOCTLS_H
14#define _IOCTLS_H
15
16// PD43 Keep it - Used with the Win33 application
17// #include <winioctl.h>
18
19//========================================================
20// 20040108 ADD the follow for test
21//========================================================
22#define INFORMATION_LENGTH sizeof(unsigned int)
23
24#define WB32_IOCTL_INDEX 0x0900 //­×§ďĽHŤKŹŰŽe//
25
26#define Wb32_RegisterRead CTL_CODE( \
27 FILE_DEVICE_UNKNOWN, \
28 WB32_IOCTL_INDEX + 0, \
29 METHOD_BUFFERED, \
30 FILE_ANY_ACCESS)
31
32#define Wb32_RegisterWrite CTL_CODE( \
33 FILE_DEVICE_UNKNOWN, \
34 WB32_IOCTL_INDEX + 1, \
35 METHOD_BUFFERED, \
36 FILE_ANY_ACCESS)
37
38#define Wb32_SendPacket CTL_CODE( \
39 FILE_DEVICE_UNKNOWN, \
40 WB32_IOCTL_INDEX + 2, \
41 METHOD_BUFFERED, \
42 FILE_ANY_ACCESS)
43
44#define Wb32_QuerySendResult CTL_CODE( \
45 FILE_DEVICE_UNKNOWN, \
46 WB32_IOCTL_INDEX + 3, \
47 METHOD_BUFFERED, \
48 FILE_ANY_ACCESS)
49
50#define Wb32_SetFragmentThreshold CTL_CODE( \
51 FILE_DEVICE_UNKNOWN, \
52 WB32_IOCTL_INDEX + 4, \
53 METHOD_BUFFERED, \
54 FILE_ANY_ACCESS)
55
56#define Wb32_SetLinkStatus CTL_CODE( \
57 FILE_DEVICE_UNKNOWN, \
58 WB32_IOCTL_INDEX + 5, \
59 METHOD_BUFFERED, \
60 FILE_ANY_ACCESS)
61
62#define Wb32_SetBulkIn CTL_CODE( \
63 FILE_DEVICE_UNKNOWN, \
64 WB32_IOCTL_INDEX + 6, \
65 METHOD_BUFFERED, \
66 FILE_ANY_ACCESS)
67
68#define Wb32_LoopbackTest CTL_CODE( \
69 FILE_DEVICE_UNKNOWN, \
70 WB32_IOCTL_INDEX + 7, \
71 METHOD_BUFFERED, \
72 FILE_ANY_ACCESS)
73
74#define Wb35_EEPromRead CTL_CODE( \
75 FILE_DEVICE_UNKNOWN, \
76 WB32_IOCTL_INDEX + 8, \
77 METHOD_BUFFERED, \
78 FILE_ANY_ACCESS)
79
80#define Wb35_EEPromWrite CTL_CODE( \
81 FILE_DEVICE_UNKNOWN, \
82 WB32_IOCTL_INDEX + 9, \
83 METHOD_BUFFERED, \
84 FILE_ANY_ACCESS)
85
86#define Wb35_FlashReadData CTL_CODE( \
87 FILE_DEVICE_UNKNOWN, \
88 WB32_IOCTL_INDEX + 10, \
89 METHOD_BUFFERED, \
90 FILE_ANY_ACCESS)
91
92#define Wb35_FlashWrite CTL_CODE( \
93 FILE_DEVICE_UNKNOWN, \
94 WB32_IOCTL_INDEX + 11, \
95 METHOD_BUFFERED, \
96 FILE_ANY_ACCESS)
97
98#define Wb35_FlashWriteBurst CTL_CODE( \
99 FILE_DEVICE_UNKNOWN, \
100 WB32_IOCTL_INDEX + 12, \
101 METHOD_BUFFERED, \
102 FILE_ANY_ACCESS)
103
104#define Wb35_TxBurstStart CTL_CODE( \
105 FILE_DEVICE_UNKNOWN, \
106 WB32_IOCTL_INDEX + 13, \
107 METHOD_BUFFERED, \
108 FILE_ANY_ACCESS)
109
110#define Wb35_TxBurstStop CTL_CODE( \
111 FILE_DEVICE_UNKNOWN, \
112 WB32_IOCTL_INDEX + 14, \
113 METHOD_BUFFERED, \
114 FILE_ANY_ACCESS)
115
116#define Wb35_TxBurstStatus CTL_CODE( \
117 FILE_DEVICE_UNKNOWN, \
118 WB32_IOCTL_INDEX + 15, \
119 METHOD_BUFFERED, \
120 FILE_ANY_ACCESS)
121
122// For IOCTL interface
123//================================================
124#define LINKNAME_STRING "\\DosDevices\\W35UND"
125#define NTDEVICE_STRING "\\Device\\W35UND"
126#define APPLICATION_LINK "\\\\.\\W35UND"
127
128#define WB_IOCTL_INDEX 0x0800
129#define WB_IOCTL_TS_INDEX WB_IOCTL_INDEX + 60
130#define WB_IOCTL_DUT_INDEX WB_IOCTL_TS_INDEX + 40
131
132//=============================================================================
133// IOCTLS defined for DUT (Device Under Test)
134
135// IOCTL_WB_802_11_DUT_MAC_ADDRESS
136// Query: Return the dot11StationID
137// Set : Set the dot11StationID. Demo only.
138//
139#define IOCTL_WB_802_11_DUT_MAC_ADDRESS CTL_CODE( \
140 FILE_DEVICE_UNKNOWN, \
141 WB_IOCTL_DUT_INDEX + 1, \
142 METHOD_BUFFERED, \
143 FILE_ANY_ACCESS)
144
145// IOCTL_WB_802_11_DUT_BSS_DESCRIPTION
146// Query: Return the info. of the current connected BSS.
147// Set : None.
148//
149#define IOCTL_WB_802_11_DUT_BSS_DESCRIPTION CTL_CODE( \
150 FILE_DEVICE_UNKNOWN, \
151 WB_IOCTL_DUT_INDEX + 2, \
152 METHOD_BUFFERED, \
153 FILE_ANY_ACCESS)
154
155// IOCTL_WB_802_11_DUT_TX_RATE
156// Query: Return the current transmission rate.
157// Set : Set the transmission rate of the Tx packets.
158//
159#define IOCTL_WB_802_11_DUT_TX_RATE CTL_CODE( \
160 FILE_DEVICE_UNKNOWN, \
161 WB_IOCTL_DUT_INDEX + 3, \
162 METHOD_BUFFERED, \
163 FILE_ANY_ACCESS)
164
165// IOCTL_WB_802_11_DUT_CURRENT_STA_STATE
166// Query: Return the current STA state. (WB_STASTATE type)
167// Set : None.
168//
169#define IOCTL_WB_802_11_DUT_CURRENT_STA_STATE CTL_CODE( \
170 FILE_DEVICE_UNKNOWN, \
171 WB_IOCTL_DUT_INDEX + 4, \
172 METHOD_BUFFERED, \
173 FILE_ANY_ACCESS)
174
175/////////// 10/31/02' Added /////////////////////
176
177// IOCTL_WB_802_11_DUT_START_IBSS_REQUEST
178// Query: None.
179// Set : Start a new IBSS
180//
181#define IOCTL_WB_802_11_DUT_START_IBSS_REQUEST CTL_CODE( \
182 FILE_DEVICE_UNKNOWN, \
183 WB_IOCTL_DUT_INDEX + 5, \
184 METHOD_BUFFERED, \
185 FILE_ANY_ACCESS)
186
187// IOCTL_WB_802_11_DUT_JOIN_REQUEST
188// Query: None.
189// Set : Synchronize with the selected BSS
190//
191#define IOCTL_WB_802_11_DUT_JOIN_REQUEST CTL_CODE( \
192 FILE_DEVICE_UNKNOWN, \
193 WB_IOCTL_DUT_INDEX + 6, \
194 METHOD_BUFFERED, \
195 FILE_ANY_ACCESS)
196
197// IOCTL_WB_802_11_DUT_AUTHEN_REQUEST
198// Query: None.
199// Set : Authenticate with the BSS
200//
201#define IOCTL_WB_802_11_DUT_AUTHEN_REQUEST CTL_CODE( \
202 FILE_DEVICE_UNKNOWN, \
203 WB_IOCTL_DUT_INDEX + 7, \
204 METHOD_BUFFERED, \
205 FILE_ANY_ACCESS)
206
207// IOCTL_WB_802_11_DUT_DEAUTHEN_REQUEST
208// Query: None.
209// Set : DeAuthenticate withe the BSS
210//
211#define IOCTL_WB_802_11_DUT_DEAUTHEN_REQUEST CTL_CODE( \
212 FILE_DEVICE_UNKNOWN, \
213 WB_IOCTL_DUT_INDEX + 8, \
214 METHOD_BUFFERED, \
215 FILE_ANY_ACCESS)
216
217// IOCTL_WB_802_11_DUT_ASSOC_REQUEST
218// Query: None.
219// Set : Associate withe the BSS
220//
221#define IOCTL_WB_802_11_DUT_ASSOC_REQUEST CTL_CODE( \
222 FILE_DEVICE_UNKNOWN, \
223 WB_IOCTL_DUT_INDEX + 9, \
224 METHOD_BUFFERED, \
225 FILE_ANY_ACCESS)
226
227// IOCTL_WB_802_11_DUT_REASSOC_REQUEST
228// Query: None.
229// Set : ReAssociate withe the BSS
230//
231#define IOCTL_WB_802_11_DUT_REASSOC_REQUEST CTL_CODE( \
232 FILE_DEVICE_UNKNOWN, \
233 WB_IOCTL_DUT_INDEX + 10, \
234 METHOD_BUFFERED, \
235 FILE_ANY_ACCESS)
236
237
238// IOCTL_WB_802_11_DUT_DISASSOC_REQUEST
239// Query: None.
240// Set : DisAssociate withe the BSS
241//
242#define IOCTL_WB_802_11_DUT_DISASSOC_REQUEST CTL_CODE( \
243 FILE_DEVICE_UNKNOWN, \
244 WB_IOCTL_DUT_INDEX + 11, \
245 METHOD_BUFFERED, \
246 FILE_ANY_ACCESS)
247
248// IOCTL_WB_802_11_DUT_FRAG_THRESHOLD
249// Query: Return the dot11FragmentThreshold
250// Set : Set the dot11FragmentThreshold
251//
252#define IOCTL_WB_802_11_DUT_FRAG_THRESHOLD CTL_CODE( \
253 FILE_DEVICE_UNKNOWN, \
254 WB_IOCTL_DUT_INDEX + 12, \
255 METHOD_BUFFERED, \
256 FILE_ANY_ACCESS)
257
258// IOCTL_WB_802_11_DUT_RTS_THRESHOLD
259// Query: Return the dot11RTSThreshold
260// Set : Set the dot11RTSThresold
261//
262#define IOCTL_WB_802_11_DUT_RTS_THRESHOLD CTL_CODE( \
263 FILE_DEVICE_UNKNOWN, \
264 WB_IOCTL_DUT_INDEX + 13, \
265 METHOD_BUFFERED, \
266 FILE_ANY_ACCESS)
267
268// IOCTL_WB_802_11_DUT_WEP_KEYMODE
269// Query: Get the WEP key mode.
270// Set : Set the WEP key mode: disable/64 bits/128 bits
271//
272#define IOCTL_WB_802_11_DUT_WEP_KEYMODE CTL_CODE( \
273 FILE_DEVICE_UNKNOWN, \
274 WB_IOCTL_DUT_INDEX + 14, \
275 METHOD_BUFFERED, \
276 FILE_ANY_ACCESS)
277
278// IOCTL_WB_802_11_DUT_WEP_KEYVALUE
279// Query: None.
280// Set : fill in the WEP key value
281//
282#define IOCTL_WB_802_11_DUT_WEP_KEYVALUE CTL_CODE( \
283 FILE_DEVICE_UNKNOWN, \
284 WB_IOCTL_DUT_INDEX + 15, \
285 METHOD_BUFFERED, \
286 FILE_ANY_ACCESS)
287
288// IOCTL_WB_802_11_DUT_RESET
289// Query: None.
290// Set : Reset S/W and H/W
291//
292#define IOCTL_WB_802_11_DUT_RESET CTL_CODE( \
293 FILE_DEVICE_UNKNOWN, \
294 WB_IOCTL_DUT_INDEX + 16, \
295 METHOD_BUFFERED, \
296 FILE_ANY_ACCESS)
297
298// IOCTL_WB_802_11_DUT_POWER_SAVE
299// Query: None.
300// Set : Set Power Save Mode
301//
302#define IOCTL_WB_802_11_DUT_POWER_SAVE CTL_CODE( \
303 FILE_DEVICE_UNKNOWN, \
304 WB_IOCTL_DUT_INDEX + 17, \
305 METHOD_BUFFERED, \
306 FILE_ANY_ACCESS)
307
308// IOCTL_WB_802_11_DUT_BSSID_LIST_SCAN
309// Query: None.
310// Set :
311//
312#define IOCTL_WB_802_11_DUT_BSSID_LIST_SCAN CTL_CODE( \
313 FILE_DEVICE_UNKNOWN, \
314 WB_IOCTL_DUT_INDEX + 18, \
315 METHOD_BUFFERED, \
316 FILE_ANY_ACCESS)
317
318// IOCTL_WB_802_11_DUT_BSSID_LIST
319// Query: Return the BSS info of BSSs in the last scanning process
320// Set : None.
321//
322#define IOCTL_WB_802_11_DUT_BSSID_LIST CTL_CODE( \
323 FILE_DEVICE_UNKNOWN, \
324 WB_IOCTL_DUT_INDEX + 19, \
325 METHOD_BUFFERED, \
326 FILE_ANY_ACCESS)
327
328// IOCTL_WB_802_11_DUT_STATISTICS
329// Query: Return the statistics of Tx/Rx.
330// Set : None.
331//
332#define IOCTL_WB_802_11_DUT_STATISTICS CTL_CODE( \
333 FILE_DEVICE_UNKNOWN, \
334 WB_IOCTL_DUT_INDEX + 20, \
335 METHOD_BUFFERED, \
336 FILE_ANY_ACCESS)
337
338// IOCTL_WB_802_11_DUT_ACCEPT_BEACON
339// Query: Return the current mode to accept beacon or not.
340// Set : Enable or disable allowing the HW-MAC to pass the beacon to the SW-MAC
341// Arguments: unsigned char
342//
343#define IOCTL_WB_802_11_DUT_ACCEPT_BEACON CTL_CODE( \
344 FILE_DEVICE_UNKNOWN, \
345 WB_IOCTL_DUT_INDEX + 21, \
346 METHOD_BUFFERED, \
347 FILE_ANY_ACCESS)
348
349// IOCTL_WB_802_11_DUT_ROAMING
350// Query: Return the roaming function status
351// Set : Enable/Disable the roaming function.
352#define IOCTL_WB_802_11_DUT_ROAMING CTL_CODE( \
353 FILE_DEVICE_UNKNOWN, \
354 WB_IOCTL_DUT_INDEX + 22, \
355 METHOD_BUFFERED, \
356 FILE_ANY_ACCESS)
357
358// IOCTL_WB_802_11_DUT_DTO
359// Query: Return the DTO(Data Throughput Optimization)
360// function status (TRUE or FALSE)
361// Set : Enable/Disable the DTO function.
362//
363#define IOCTL_WB_802_11_DUT_DTO CTL_CODE( \
364 FILE_DEVICE_UNKNOWN, \
365 WB_IOCTL_DUT_INDEX + 23, \
366 METHOD_BUFFERED, \
367 FILE_ANY_ACCESS)
368
369// IOCTL_WB_802_11_DUT_ANTENNA_DIVERSITY
370// Query: Return the antenna diversity status. (TRUE/ON or FALSE/OFF)
371// Set : Enable/Disable the antenna diversity.
372//
373#define IOCTL_WB_802_11_DUT_ANTENNA_DIVERSITY CTL_CODE( \
374 FILE_DEVICE_UNKNOWN, \
375 WB_IOCTL_DUT_INDEX + 24, \
376 METHOD_BUFFERED, \
377 FILE_ANY_ACCESS)
378
379//-------------- new added for a+b+g ---------------------
380// IOCTL_WB_802_11_DUT_MAC_OPERATION_MODE
381// Query: Return the MAC operation mode. (MODE_802_11_BG, MODE_802_11_A,
382// MODE_802_11_ABG, MODE_802_11_BG_IBSS)
383// Set : Set the MAC operation mode.
384//
385#define IOCTL_WB_802_11_DUT_MAC_OPERATION_MODE CTL_CODE( \
386 FILE_DEVICE_UNKNOWN, \
387 WB_IOCTL_DUT_INDEX + 25, \
388 METHOD_BUFFERED, \
389 FILE_ANY_ACCESS)
390
391// IOCTL_WB_802_11_DUT_TX_RATE_REDEFINED
392// Query: Return the current tx rate which follows the definition in spec. (for
393// example, 5.5M => 0x0b)
394// Set : None
395//
396#define IOCTL_WB_802_11_DUT_TX_RATE_REDEFINED CTL_CODE( \
397 FILE_DEVICE_UNKNOWN, \
398 WB_IOCTL_DUT_INDEX + 26, \
399 METHOD_BUFFERED, \
400 FILE_ANY_ACCESS)
401
402// IOCTL_WB_802_11_DUT_PREAMBLE_MODE
403// Query: Return the preamble mode. (auto or long)
404// Set : Set the preamble mode.
405//
406#define IOCTL_WB_802_11_DUT_PREAMBLE_MODE CTL_CODE( \
407 FILE_DEVICE_UNKNOWN, \
408 WB_IOCTL_DUT_INDEX + 27, \
409 METHOD_BUFFERED, \
410 FILE_ANY_ACCESS)
411
412// IOCTL_WB_802_11_DUT_SLOT_TIME_MODE
413// Query: Return the slot time mode. (auto or long)
414// Set : Set the slot time mode.
415//
416#define IOCTL_WB_802_11_DUT_SLOT_TIME_MODE CTL_CODE( \
417 FILE_DEVICE_UNKNOWN, \
418 WB_IOCTL_DUT_INDEX + 28, \
419 METHOD_BUFFERED, \
420 FILE_ANY_ACCESS)
421//------------------------------------------------------------------
422
423// IOCTL_WB_802_11_DUT_ADVANCE_STATUS
424// Query:
425// Set : NONE
426//
427#define IOCTL_WB_802_11_DUT_ADVANCE_STATUS CTL_CODE( \
428 FILE_DEVICE_UNKNOWN, \
429 WB_IOCTL_DUT_INDEX + 29, \
430 METHOD_BUFFERED, \
431 FILE_ANY_ACCESS)
432
433// IOCTL_WB_802_11_DUT_TX_RATE_MODE
434// Query: Return the tx rate mode. (RATE_AUTO, RATE_1M, .., RATE_54M, RATE_MAX)
435// Set : Set the tx rate mode. (RATE_AUTO, RATE_1M, .., RATE_54M, RATE_MAX)
436//
437#define IOCTL_WB_802_11_DUT_TX_RATE_MODE CTL_CODE( \
438 FILE_DEVICE_UNKNOWN, \
439 WB_IOCTL_DUT_INDEX + 30, \
440 METHOD_BUFFERED, \
441 FILE_ANY_ACCESS)
442
443// IOCTL_WB_802_11_DUT_DTO_PARA
444// Query: Return the DTO parameters
445// Set : Set the DTO parameters
446//
447#define IOCTL_WB_802_11_DUT_DTO_PARA CTL_CODE( \
448 FILE_DEVICE_UNKNOWN, \
449 WB_IOCTL_DUT_INDEX + 31, \
450 METHOD_BUFFERED, \
451 FILE_ANY_ACCESS)
452
453// IOCTL_WB_802_11_DUT_EVENT_LOG
454// Query: Return event log
455// Set : Reset event log
456//
457#define IOCTL_WB_802_11_DUT_EVENT_LOG CTL_CODE( \
458 FILE_DEVICE_UNKNOWN, \
459 WB_IOCTL_DUT_INDEX + 32, \
460 METHOD_BUFFERED, \
461 FILE_ANY_ACCESS)
462
463// IOCTL_WB_802_11_DUT_CWMIN
464// Query: NONE(It will be obtained by IOCTL_WB_802_11_DUT_ADVANCE_STATUS)
465// Set : Set CWMin value
466//
467#define IOCTL_WB_802_11_DUT_CWMIN CTL_CODE( \
468 FILE_DEVICE_UNKNOWN, \
469 WB_IOCTL_DUT_INDEX + 33, \
470 METHOD_BUFFERED, \
471 FILE_ANY_ACCESS)
472
473// IOCTL_WB_802_11_DUT_CWMAX
474// Query: NONE(It will be obtained by IOCTL_WB_802_11_DUT_ADVANCE_STATUS)
475// Set : Set CWMax value
476//
477#define IOCTL_WB_802_11_DUT_CWMAX CTL_CODE( \
478 FILE_DEVICE_UNKNOWN, \
479 WB_IOCTL_DUT_INDEX + 34, \
480 METHOD_BUFFERED, \
481 FILE_ANY_ACCESS)
482
483
484//==========================================================
485// IOCTLs for Testing
486
487// IOCTL_WB_802_11_TS_SET_CXX_REG
488// Query: None
489// Set : Write the value to one of Cxx register.
490//
491#define IOCTL_WB_802_11_TS_SET_CXX_REG CTL_CODE( \
492 FILE_DEVICE_UNKNOWN, \
493 WB_IOCTL_TS_INDEX + 0, \
494 METHOD_BUFFERED, \
495 FILE_ANY_ACCESS)
496
497// IOCTL_WB_802_11_TS_GET_CXX_REG
498// Query: Return the value of the Cxx register.
499// Set : Write the reg no. (0x00, 0x04, 0x08 etc)
500//
501#define IOCTL_WB_802_11_TS_GET_CXX_REG CTL_CODE( \
502 FILE_DEVICE_UNKNOWN, \
503 WB_IOCTL_TS_INDEX + 1, \
504 METHOD_BUFFERED, \
505 FILE_ANY_ACCESS)
506
507// IOCTL_WB_802_11_TS_SET_DXX_REG
508// Query: None
509// Set : Write the value to one of Dxx register.
510//
511#define IOCTL_WB_802_11_TS_SET_DXX_REG CTL_CODE( \
512 FILE_DEVICE_UNKNOWN, \
513 WB_IOCTL_TS_INDEX + 2, \
514 METHOD_BUFFERED, \
515 FILE_ANY_ACCESS)
516
517// IOCTL_WB_802_11_TS_GET_DXX_REG
518// Query: Return the value of the Dxx register.
519// Set : Write the reg no. (0x00, 0x04, 0x08 etc)
520//
521#define IOCTL_WB_802_11_TS_GET_DXX_REG CTL_CODE( \
522 FILE_DEVICE_UNKNOWN, \
523 WB_IOCTL_TS_INDEX + 3, \
524 METHOD_BUFFERED, \
525 FILE_ANY_ACCESS)
526
527//============================================================
528// [TS]
529
530#define IOCTL_WB_802_11_TS_TX_RATE CTL_CODE( \
531 FILE_DEVICE_UNKNOWN, \
532 WB_IOCTL_TS_INDEX + 4, \
533 METHOD_BUFFERED, \
534 FILE_ANY_ACCESS)
535
536#define IOCTL_WB_802_11_TS_CURRENT_CHANNEL CTL_CODE( \
537 FILE_DEVICE_UNKNOWN, \
538 WB_IOCTL_TS_INDEX + 5, \
539 METHOD_BUFFERED, \
540 FILE_ANY_ACCESS)
541
542#define IOCTL_WB_802_11_TS_ENABLE_SEQNO CTL_CODE( \
543 FILE_DEVICE_UNKNOWN, \
544 WB_IOCTL_TS_INDEX + 6, \
545 METHOD_BUFFERED, \
546 FILE_ANY_ACCESS)
547
548#define IOCTL_WB_802_11_TS_ENALBE_ACKEDPACKET CTL_CODE( \
549 FILE_DEVICE_UNKNOWN, \
550 WB_IOCTL_TS_INDEX + 7, \
551 METHOD_BUFFERED, \
552 FILE_ANY_ACCESS)
553
554#define IOCTL_WB_802_11_TS_INHIBIT_CRC CTL_CODE( \
555 FILE_DEVICE_UNKNOWN, \
556 WB_IOCTL_TS_INDEX + 8, \
557 METHOD_BUFFERED, \
558 FILE_ANY_ACCESS)
559
560#define IOCTL_WB_802_11_TS_RESET_RCV_COUNTER CTL_CODE( \
561 FILE_DEVICE_UNKNOWN, \
562 WB_IOCTL_TS_INDEX + 9, \
563 METHOD_BUFFERED, \
564 FILE_ANY_ACCESS)
565
566#define IOCTL_WB_802_11_TS_SET_TX_TRIGGER CTL_CODE( \
567 FILE_DEVICE_UNKNOWN, \
568 WB_IOCTL_TS_INDEX + 10, \
569 METHOD_BUFFERED, \
570 FILE_ANY_ACCESS)
571
572#define IOCTL_WB_802_11_TS_FAILED_TX_COUNT CTL_CODE( \
573 FILE_DEVICE_UNKNOWN, \
574 WB_IOCTL_TS_INDEX + 11, \
575 METHOD_BUFFERED, \
576 FILE_ANY_ACCESS)
577
578// [TS1]
579#define IOCTL_WB_802_11_TS_TX_POWER CTL_CODE( \
580 FILE_DEVICE_UNKNOWN, \
581 WB_IOCTL_TS_INDEX + 12, \
582 METHOD_BUFFERED, \
583 FILE_ANY_ACCESS)
584
585#define IOCTL_WB_802_11_TS_MODE_ENABLE CTL_CODE( \
586 FILE_DEVICE_UNKNOWN, \
587 WB_IOCTL_TS_INDEX + 13, \
588 METHOD_BUFFERED, \
589 FILE_ANY_ACCESS)
590
591#define IOCTL_WB_802_11_TS_MODE_DISABLE CTL_CODE( \
592 FILE_DEVICE_UNKNOWN, \
593 WB_IOCTL_TS_INDEX + 14, \
594 METHOD_BUFFERED, \
595 FILE_ANY_ACCESS)
596
597#define IOCTL_WB_802_11_TS_ANTENNA CTL_CODE( \
598 FILE_DEVICE_UNKNOWN, \
599 WB_IOCTL_TS_INDEX + 15, \
600 METHOD_BUFFERED, \
601 FILE_ANY_ACCESS)
602
603#define IOCTL_WB_802_11_TS_ADAPTER_INFO CTL_CODE( \
604 FILE_DEVICE_UNKNOWN, \
605 WB_IOCTL_TS_INDEX + 16, \
606 METHOD_BUFFERED, \
607 FILE_ANY_ACCESS)
608
609#define IOCTL_WB_802_11_TS_MAC_ADDRESS CTL_CODE( \
610 FILE_DEVICE_UNKNOWN, \
611 WB_IOCTL_TS_INDEX + 17, \
612 METHOD_BUFFERED, \
613 FILE_ANY_ACCESS)
614
615#define IOCTL_WB_802_11_TS_BSSID CTL_CODE( \
616 FILE_DEVICE_UNKNOWN, \
617 WB_IOCTL_TS_INDEX + 18, \
618 METHOD_BUFFERED, \
619 FILE_ANY_ACCESS)
620
621#define IOCTL_WB_802_11_TS_RF_PARAMETER CTL_CODE( \
622 FILE_DEVICE_UNKNOWN, \
623 WB_IOCTL_TS_INDEX + 19, \
624 METHOD_BUFFERED, \
625 FILE_ANY_ACCESS)
626
627#define IOCTL_WB_802_11_TS_FILTER CTL_CODE( \
628 FILE_DEVICE_UNKNOWN, \
629 WB_IOCTL_TS_INDEX + 20, \
630 METHOD_BUFFERED, \
631 FILE_ANY_ACCESS)
632
633#define IOCTL_WB_802_11_TS_CALIBRATION CTL_CODE( \
634 FILE_DEVICE_UNKNOWN, \
635 WB_IOCTL_TS_INDEX + 21, \
636 METHOD_BUFFERED, \
637 FILE_ANY_ACCESS)
638
639#define IOCTL_WB_802_11_TS_BSS_MODE CTL_CODE( \
640 FILE_DEVICE_UNKNOWN, \
641 WB_IOCTL_TS_INDEX + 22, \
642 METHOD_BUFFERED, \
643 FILE_ANY_ACCESS)
644
645#define IOCTL_WB_802_11_TS_SET_SSID CTL_CODE( \
646 FILE_DEVICE_UNKNOWN, \
647 WB_IOCTL_TS_INDEX + 23, \
648 METHOD_BUFFERED, \
649 FILE_ANY_ACCESS)
650
651#define IOCTL_WB_802_11_TS_IBSS_CHANNEL CTL_CODE( \
652 FILE_DEVICE_UNKNOWN, \
653 WB_IOCTL_TS_INDEX + 24, \
654 METHOD_BUFFERED, \
655 FILE_ANY_ACCESS)
656
657// set/query the slot time value(short or long slot time)
658#define IOCTL_WB_802_11_TS_SLOT_TIME CTL_CODE( \
659 FILE_DEVICE_UNKNOWN, \
660 WB_IOCTL_TS_INDEX + 25, \
661 METHOD_BUFFERED, \
662 FILE_ANY_ACCESS)
663
664#define IOCTL_WB_802_11_TS_SLOT_TIME CTL_CODE( \
665 FILE_DEVICE_UNKNOWN, \
666 WB_IOCTL_TS_INDEX + 25, \
667 METHOD_BUFFERED, \
668 FILE_ANY_ACCESS)
669
670#define IOCTL_WB_802_11_TS_RX_STATISTICS CTL_CODE( \
671 FILE_DEVICE_UNKNOWN, \
672 WB_IOCTL_TS_INDEX + 26, \
673 METHOD_BUFFERED, \
674 FILE_ANY_ACCESS)
675
676#endif // #ifndef _IOCTLS_H
677
678
diff --git a/drivers/staging/winbond/linux/common.h b/drivers/staging/winbond/linux/common.h
new file mode 100644
index 000000000000..6b00bad74f78
--- /dev/null
+++ b/drivers/staging/winbond/linux/common.h
@@ -0,0 +1,143 @@
1//
2// common.h
3//
4// This file contains the OS dependant definition and function.
5// Every OS has this file individual.
6//
7
8#define DebugUsbdStatusInformation( _A )
9
10#ifndef COMMON_DEF
11#define COMMON_DEF
12
13#include <linux/version.h>
14#include <linux/usb.h>
15#include <linux/kernel.h> //need for kernel alert
16#include <linux/autoconf.h>
17#include <linux/sched.h>
18#include <linux/signal.h>
19#include <linux/slab.h> //memory allocate
20#include <linux/module.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/init.h>//need for init and exit modules marco
24#include <linux/ctype.h>
25#include <linux/wait.h>
26#include <linux/list.h>
27#include <linux/wireless.h>
28#include <linux/if_arp.h>
29#include <asm/uaccess.h>
30#include <net/iw_handler.h>
31#include <linux/skbuff.h>
32
33
34//#define DEBUG_ENABLED 1
35
36
37
38//===============================================================
39// Common type definition
40//===============================================================
41
42typedef u8* PUCHAR;
43typedef s8* PCHAR;
44typedef u8* PBOOLEAN;
45typedef u16* PUSHORT;
46typedef u32* PULONG;
47typedef s16* PSHORT;
48
49
50//===========================================
51#define IGNORE 2
52#define SUCCESS 1
53#define FAILURE 0
54
55
56#ifndef true
57#define true 1
58#endif
59
60#ifndef false
61#define false 0
62#endif
63
64// PD43 20021108
65#ifndef TRUE
66#define TRUE 1
67#endif
68
69#ifndef FALSE
70#define FALSE 0
71#endif
72
73#define STATUS_MEDIA_CONNECT 1
74#define STATUS_MEDIA_DISCONNECT 0
75
76#ifndef BIT
77#define BIT(x) (1 << (x))
78#endif
79
80typedef struct urb * PURB;
81
82
83
84//==================================================================================================
85// Common function definition
86//==================================================================================================
87#ifndef abs
88#define abs(_T) ((_T) < 0 ? -_T : _T)
89#endif
90#define DEBUG_ENABLED
91#define ETH_LENGTH_OF_ADDRESS 6
92#ifdef DEBUG_ENABLED
93#define WBDEBUG( _M ) printk _M
94#else
95#define WBDEBUG( _M ) 0
96#endif
97
98#define OS_DISCONNECTED 0
99#define OS_CONNECTED 1
100
101
102#define OS_EVENT_INDICATE( _A, _B, _F )
103#define OS_PMKID_STATUS_EVENT( _A )
104
105
106/* Uff, no, longs are not atomic on all architectures Linux
107 * supports. This should really use atomic_t */
108
109#define OS_ATOMIC u32
110#define OS_ATOMIC_READ( _A, _V ) _V
111#define OS_ATOMIC_INC( _A, _V ) EncapAtomicInc( _A, (void*)_V )
112#define OS_ATOMIC_DEC( _A, _V ) EncapAtomicDec( _A, (void*)_V )
113#define OS_MEMORY_CLEAR( _A, _S ) memset( (PUCHAR)_A,0,_S)
114#define OS_MEMORY_COMPARE( _A, _B, _S ) (memcmp(_A,_B,_S)? 0 : 1) // Definition is reverse with Ndis 1: the same 0: different
115
116
117#define OS_SPIN_LOCK spinlock_t
118#define OS_SPIN_LOCK_ALLOCATE( _S ) spin_lock_init( _S );
119#define OS_SPIN_LOCK_FREE( _S )
120#define OS_SPIN_LOCK_ACQUIRED( _S ) spin_lock_irq( _S )
121#define OS_SPIN_LOCK_RELEASED( _S ) spin_unlock_irq( _S );
122
123#define OS_TIMER struct timer_list
124#define OS_TIMER_INITIAL( _T, _F, _P ) \
125{ \
126 init_timer( _T ); \
127 (_T)->function = (void *)_F##_1a; \
128 (_T)->data = (unsigned long)_P; \
129}
130
131// _S : Millisecond
132// 20060420 At least 1 large than jiffies
133#define OS_TIMER_SET( _T, _S ) \
134{ \
135 (_T)->expires = jiffies + ((_S*HZ+999)/1000);\
136 add_timer( _T ); \
137}
138#define OS_TIMER_CANCEL( _T, _B ) del_timer_sync( _T )
139#define OS_TIMER_GET_SYS_TIME( _T ) (*_T=jiffies)
140
141
142#endif // COMMON_DEF
143
diff --git a/drivers/staging/winbond/linux/sysdef.h b/drivers/staging/winbond/linux/sysdef.h
new file mode 100644
index 000000000000..d46d63e5c673
--- /dev/null
+++ b/drivers/staging/winbond/linux/sysdef.h
@@ -0,0 +1,73 @@
1
2
3//
4// Winbond WLAN System Configuration defines
5//
6
7//=====================================================================
8// Current directory is Linux
9// The definition WB_LINUX is a keyword for this OS
10//=====================================================================
11#ifndef SYS_DEF_H
12#define SYS_DEF_H
13#define WB_LINUX
14#define WB_LINUX_WPA_PSK
15
16
17//#define _IBSS_BEACON_SEQ_STICK_
18#define _USE_FALLBACK_RATE_
19//#define ANTDIV_DEFAULT_ON
20
21#define _WPA2_ // 20061122 It's needed for current Linux driver
22
23
24#ifndef _WPA_PSK_DEBUG
25#undef _WPA_PSK_DEBUG
26#endif
27
28// debug print options, mark what debug you don't need
29
30#ifdef FULL_DEBUG
31#define _PE_STATE_DUMP_
32#define _PE_TX_DUMP_
33#define _PE_RX_DUMP_
34#define _PE_OID_DUMP_
35#define _PE_DTO_DUMP_
36#define _PE_REG_DUMP_
37#define _PE_USB_INI_DUMP_
38#endif
39
40
41
42#include "common.h" // Individual file depends on OS
43
44#include "../wb35_ver.h"
45#include "../mac_structures.h"
46#include "../ds_tkip.h"
47#include "../localpara.h"
48#include "../sme_s.h"
49#include "../scan_s.h"
50#include "../mds_s.h"
51#include "../mlme_s.h"
52#include "../bssdscpt.h"
53#include "../sme_api.h"
54#include "../gl_80211.h"
55#include "../mto.h"
56#include "../wblinux_s.h"
57#include "../wbhal_s.h"
58
59
60#include "../adapter.h"
61
62#include "../mlme_mib.h"
63#include "../mds_f.h"
64#include "../bss_f.h"
65#include "../mlmetxrx_f.h"
66#include "../mto_f.h"
67#include "../wbhal_f.h"
68#include "../wblinux_f.h"
69// Kernel Timer resolution, NDIS is 10ms, 10000us
70#define MIN_TIMEOUT_VAL (10) //ms
71
72
73#endif
diff --git a/drivers/staging/winbond/linux/wb35reg.c b/drivers/staging/winbond/linux/wb35reg.c
new file mode 100644
index 000000000000..2c0b454e8cad
--- /dev/null
+++ b/drivers/staging/winbond/linux/wb35reg.c
@@ -0,0 +1,747 @@
1#include "sysdef.h"
2
3extern void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency);
4
5// TRUE : read command process successfully
6// FALSE : register not support
7// RegisterNo : start base
8// pRegisterData : data point
9// NumberOfData : number of register data
10// Flag : AUTO_INCREMENT - RegisterNo will auto increment 4
11// NO_INCREMENT - Function will write data into the same register
12unsigned char
13Wb35Reg_BurstWrite(phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterData, u8 NumberOfData, u8 Flag)
14{
15 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
16 PURB pUrb = NULL;
17 PREG_QUEUE pRegQueue = NULL;
18 u16 UrbSize;
19 struct usb_ctrlrequest *dr;
20 u16 i, DataSize = NumberOfData*4;
21
22 // Module shutdown
23 if (pHwData->SurpriseRemove)
24 return FALSE;
25
26 // Trying to use burst write function if use new hardware
27 UrbSize = sizeof(REG_QUEUE) + DataSize + sizeof(struct usb_ctrlrequest);
28 OS_MEMORY_ALLOC( (void* *)&pRegQueue, UrbSize );
29 pUrb = wb_usb_alloc_urb(0);
30 if( pUrb && pRegQueue ) {
31 pRegQueue->DIRECT = 2;// burst write register
32 pRegQueue->INDEX = RegisterNo;
33 pRegQueue->pBuffer = (PULONG)((PUCHAR)pRegQueue + sizeof(REG_QUEUE));
34 memcpy( pRegQueue->pBuffer, pRegisterData, DataSize );
35 //the function for reversing register data from little endian to big endian
36 for( i=0; i<NumberOfData ; i++ )
37 pRegQueue->pBuffer[i] = cpu_to_le32( pRegQueue->pBuffer[i] );
38
39 dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE) + DataSize);
40 dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE;
41 dr->bRequest = 0x04; // USB or vendor-defined request code, burst mode
42 dr->wValue = cpu_to_le16( Flag ); // 0: Register number auto-increment, 1: No auto increment
43 dr->wIndex = cpu_to_le16( RegisterNo );
44 dr->wLength = cpu_to_le16( DataSize );
45 pRegQueue->Next = NULL;
46 pRegQueue->pUsbReq = dr;
47 pRegQueue->pUrb = pUrb;
48
49 OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock );
50 if (pWb35Reg->pRegFirst == NULL)
51 pWb35Reg->pRegFirst = pRegQueue;
52 else
53 pWb35Reg->pRegLast->Next = pRegQueue;
54 pWb35Reg->pRegLast = pRegQueue;
55
56 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
57
58 // Start EP0VM
59 Wb35Reg_EP0VM_start(pHwData);
60
61 return TRUE;
62 } else {
63 if (pUrb)
64 usb_free_urb(pUrb);
65 if (pRegQueue)
66 kfree(pRegQueue);
67 return FALSE;
68 }
69 return FALSE;
70}
71
72void
73Wb35Reg_Update(phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue)
74{
75 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
76 switch (RegisterNo) {
77 case 0x3b0: pWb35Reg->U1B0 = RegisterValue; break;
78 case 0x3bc: pWb35Reg->U1BC_LEDConfigure = RegisterValue; break;
79 case 0x400: pWb35Reg->D00_DmaControl = RegisterValue; break;
80 case 0x800: pWb35Reg->M00_MacControl = RegisterValue; break;
81 case 0x804: pWb35Reg->M04_MulticastAddress1 = RegisterValue; break;
82 case 0x808: pWb35Reg->M08_MulticastAddress2 = RegisterValue; break;
83 case 0x824: pWb35Reg->M24_MacControl = RegisterValue; break;
84 case 0x828: pWb35Reg->M28_MacControl = RegisterValue; break;
85 case 0x82c: pWb35Reg->M2C_MacControl = RegisterValue; break;
86 case 0x838: pWb35Reg->M38_MacControl = RegisterValue; break;
87 case 0x840: pWb35Reg->M40_MacControl = RegisterValue; break;
88 case 0x844: pWb35Reg->M44_MacControl = RegisterValue; break;
89 case 0x848: pWb35Reg->M48_MacControl = RegisterValue; break;
90 case 0x84c: pWb35Reg->M4C_MacStatus = RegisterValue; break;
91 case 0x860: pWb35Reg->M60_MacControl = RegisterValue; break;
92 case 0x868: pWb35Reg->M68_MacControl = RegisterValue; break;
93 case 0x870: pWb35Reg->M70_MacControl = RegisterValue; break;
94 case 0x874: pWb35Reg->M74_MacControl = RegisterValue; break;
95 case 0x878: pWb35Reg->M78_ERPInformation = RegisterValue; break;
96 case 0x87C: pWb35Reg->M7C_MacControl = RegisterValue; break;
97 case 0x880: pWb35Reg->M80_MacControl = RegisterValue; break;
98 case 0x884: pWb35Reg->M84_MacControl = RegisterValue; break;
99 case 0x888: pWb35Reg->M88_MacControl = RegisterValue; break;
100 case 0x898: pWb35Reg->M98_MacControl = RegisterValue; break;
101 case 0x100c: pWb35Reg->BB0C = RegisterValue; break;
102 case 0x102c: pWb35Reg->BB2C = RegisterValue; break;
103 case 0x1030: pWb35Reg->BB30 = RegisterValue; break;
104 case 0x103c: pWb35Reg->BB3C = RegisterValue; break;
105 case 0x1048: pWb35Reg->BB48 = RegisterValue; break;
106 case 0x104c: pWb35Reg->BB4C = RegisterValue; break;
107 case 0x1050: pWb35Reg->BB50 = RegisterValue; break;
108 case 0x1054: pWb35Reg->BB54 = RegisterValue; break;
109 case 0x1058: pWb35Reg->BB58 = RegisterValue; break;
110 case 0x105c: pWb35Reg->BB5C = RegisterValue; break;
111 case 0x1060: pWb35Reg->BB60 = RegisterValue; break;
112 }
113}
114
115// TRUE : read command process successfully
116// FALSE : register not support
117unsigned char
118Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
119{
120 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
121 int ret = -1;
122
123 // Module shutdown
124 if (pHwData->SurpriseRemove)
125 return FALSE;
126
127 RegisterValue = cpu_to_le32(RegisterValue);
128
129 // update the register by send usb message------------------------------------
130 pWb35Reg->SyncIoPause = 1;
131
132 // 20060717.5 Wait until EP0VM stop
133 while (pWb35Reg->EP0vm_state != VM_STOP)
134 OS_SLEEP(10000);
135
136 // Sync IoCallDriver
137 pWb35Reg->EP0vm_state = VM_RUNNING;
138 ret = usb_control_msg( pHwData->WbUsb.udev,
139 usb_sndctrlpipe( pHwData->WbUsb.udev, 0 ),
140 0x03, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
141 0x0,RegisterNo, &RegisterValue, 4, HZ*100 );
142 pWb35Reg->EP0vm_state = VM_STOP;
143 pWb35Reg->SyncIoPause = 0;
144
145 Wb35Reg_EP0VM_start(pHwData);
146
147 if (ret < 0) {
148 #ifdef _PE_REG_DUMP_
149 WBDEBUG(("EP0 Write register usb message sending error\n"));
150 #endif
151
152 pHwData->SurpriseRemove = 1; // 20060704.2
153 return FALSE;
154 }
155
156 return TRUE;
157}
158
159// TRUE : read command process successfully
160// FALSE : register not support
161unsigned char
162Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
163{
164 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
165 struct usb_ctrlrequest *dr;
166 PURB pUrb = NULL;
167 PREG_QUEUE pRegQueue = NULL;
168 u16 UrbSize;
169
170
171 // Module shutdown
172 if (pHwData->SurpriseRemove)
173 return FALSE;
174
175 // update the register by send urb request------------------------------------
176 UrbSize = sizeof(REG_QUEUE) + sizeof(struct usb_ctrlrequest);
177 OS_MEMORY_ALLOC( (void* *)&pRegQueue, UrbSize );
178 pUrb = wb_usb_alloc_urb(0);
179 if (pUrb && pRegQueue) {
180 pRegQueue->DIRECT = 1;// burst write register
181 pRegQueue->INDEX = RegisterNo;
182 pRegQueue->VALUE = cpu_to_le32(RegisterValue);
183 pRegQueue->RESERVED_VALID = FALSE;
184 dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE));
185 dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE;
186 dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode
187 dr->wValue = cpu_to_le16(0x0);
188 dr->wIndex = cpu_to_le16(RegisterNo);
189 dr->wLength = cpu_to_le16(4);
190
191 // Enter the sending queue
192 pRegQueue->Next = NULL;
193 pRegQueue->pUsbReq = dr;
194 pRegQueue->pUrb = pUrb;
195
196 OS_SPIN_LOCK_ACQUIRED(&pWb35Reg->EP0VM_spin_lock );
197 if (pWb35Reg->pRegFirst == NULL)
198 pWb35Reg->pRegFirst = pRegQueue;
199 else
200 pWb35Reg->pRegLast->Next = pRegQueue;
201 pWb35Reg->pRegLast = pRegQueue;
202
203 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
204
205 // Start EP0VM
206 Wb35Reg_EP0VM_start(pHwData);
207
208 return TRUE;
209 } else {
210 if (pUrb)
211 usb_free_urb(pUrb);
212 kfree(pRegQueue);
213 return FALSE;
214 }
215}
216
217//This command will be executed with a user defined value. When it completes,
218//this value is useful. For example, hal_set_current_channel will use it.
219// TRUE : read command process successfully
220// FALSE : register not support
221unsigned char
222Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue,
223 PCHAR pValue, s8 Len)
224{
225 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
226 struct usb_ctrlrequest *dr;
227 PURB pUrb = NULL;
228 PREG_QUEUE pRegQueue = NULL;
229 u16 UrbSize;
230
231 // Module shutdown
232 if (pHwData->SurpriseRemove)
233 return FALSE;
234
235 // update the register by send urb request------------------------------------
236 UrbSize = sizeof(REG_QUEUE) + sizeof(struct usb_ctrlrequest);
237 OS_MEMORY_ALLOC((void* *) &pRegQueue, UrbSize );
238 pUrb = wb_usb_alloc_urb(0);
239 if (pUrb && pRegQueue) {
240 pRegQueue->DIRECT = 1;// burst write register
241 pRegQueue->INDEX = RegisterNo;
242 pRegQueue->VALUE = cpu_to_le32(RegisterValue);
243 //NOTE : Users must guarantee the size of value will not exceed the buffer size.
244 memcpy(pRegQueue->RESERVED, pValue, Len);
245 pRegQueue->RESERVED_VALID = TRUE;
246 dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE));
247 dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE;
248 dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode
249 dr->wValue = cpu_to_le16(0x0);
250 dr->wIndex = cpu_to_le16(RegisterNo);
251 dr->wLength = cpu_to_le16(4);
252
253 // Enter the sending queue
254 pRegQueue->Next = NULL;
255 pRegQueue->pUsbReq = dr;
256 pRegQueue->pUrb = pUrb;
257 OS_SPIN_LOCK_ACQUIRED (&pWb35Reg->EP0VM_spin_lock );
258 if( pWb35Reg->pRegFirst == NULL )
259 pWb35Reg->pRegFirst = pRegQueue;
260 else
261 pWb35Reg->pRegLast->Next = pRegQueue;
262 pWb35Reg->pRegLast = pRegQueue;
263
264 OS_SPIN_LOCK_RELEASED ( &pWb35Reg->EP0VM_spin_lock );
265
266 // Start EP0VM
267 Wb35Reg_EP0VM_start(pHwData);
268 return TRUE;
269 } else {
270 if (pUrb)
271 usb_free_urb(pUrb);
272 kfree(pRegQueue);
273 return FALSE;
274 }
275}
276
277// TRUE : read command process successfully
278// FALSE : register not support
279// pRegisterValue : It must be a resident buffer due to asynchronous read register.
280unsigned char
281Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue )
282{
283 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
284 PULONG pltmp = pRegisterValue;
285 int ret = -1;
286
287 // Module shutdown
288 if (pHwData->SurpriseRemove)
289 return FALSE;
290
291 // Read the register by send usb message------------------------------------
292
293 pWb35Reg->SyncIoPause = 1;
294
295 // 20060717.5 Wait until EP0VM stop
296 while (pWb35Reg->EP0vm_state != VM_STOP)
297 OS_SLEEP(10000);
298
299 pWb35Reg->EP0vm_state = VM_RUNNING;
300 ret = usb_control_msg( pHwData->WbUsb.udev,
301 usb_rcvctrlpipe(pHwData->WbUsb.udev, 0),
302 0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN,
303 0x0, RegisterNo, pltmp, 4, HZ*100 );
304
305 *pRegisterValue = cpu_to_le32(*pltmp);
306
307 pWb35Reg->EP0vm_state = VM_STOP;
308
309 Wb35Reg_Update( pHwData, RegisterNo, *pRegisterValue );
310 pWb35Reg->SyncIoPause = 0;
311
312 Wb35Reg_EP0VM_start( pHwData );
313
314 if (ret < 0) {
315 #ifdef _PE_REG_DUMP_
316 WBDEBUG(("EP0 Read register usb message sending error\n"));
317 #endif
318
319 pHwData->SurpriseRemove = 1; // 20060704.2
320 return FALSE;
321 }
322
323 return TRUE;
324}
325
326// TRUE : read command process successfully
327// FALSE : register not support
328// pRegisterValue : It must be a resident buffer due to asynchronous read register.
329unsigned char
330Wb35Reg_Read(phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue )
331{
332 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
333 struct usb_ctrlrequest * dr;
334 PURB pUrb;
335 PREG_QUEUE pRegQueue;
336 u16 UrbSize;
337
338 // Module shutdown
339 if (pHwData->SurpriseRemove)
340 return FALSE;
341
342 // update the variable by send Urb to read register ------------------------------------
343 UrbSize = sizeof(REG_QUEUE) + sizeof(struct usb_ctrlrequest);
344 OS_MEMORY_ALLOC( (void* *)&pRegQueue, UrbSize );
345 pUrb = wb_usb_alloc_urb(0);
346 if( pUrb && pRegQueue )
347 {
348 pRegQueue->DIRECT = 0;// read register
349 pRegQueue->INDEX = RegisterNo;
350 pRegQueue->pBuffer = pRegisterValue;
351 dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE));
352 dr->bRequestType = USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN;
353 dr->bRequest = 0x01; // USB or vendor-defined request code, burst mode
354 dr->wValue = cpu_to_le16(0x0);
355 dr->wIndex = cpu_to_le16 (RegisterNo);
356 dr->wLength = cpu_to_le16 (4);
357
358 // Enter the sending queue
359 pRegQueue->Next = NULL;
360 pRegQueue->pUsbReq = dr;
361 pRegQueue->pUrb = pUrb;
362 OS_SPIN_LOCK_ACQUIRED ( &pWb35Reg->EP0VM_spin_lock );
363 if( pWb35Reg->pRegFirst == NULL )
364 pWb35Reg->pRegFirst = pRegQueue;
365 else
366 pWb35Reg->pRegLast->Next = pRegQueue;
367 pWb35Reg->pRegLast = pRegQueue;
368
369 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
370
371 // Start EP0VM
372 Wb35Reg_EP0VM_start( pHwData );
373
374 return TRUE;
375 } else {
376 if (pUrb)
377 usb_free_urb( pUrb );
378 kfree(pRegQueue);
379 return FALSE;
380 }
381}
382
383
384void
385Wb35Reg_EP0VM_start( phw_data_t pHwData )
386{
387 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
388
389 if (OS_ATOMIC_INC( pHwData->Adapter, &pWb35Reg->RegFireCount) == 1) {
390 pWb35Reg->EP0vm_state = VM_RUNNING;
391 Wb35Reg_EP0VM(pHwData);
392 } else
393 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Reg->RegFireCount );
394}
395
396void
397Wb35Reg_EP0VM(phw_data_t pHwData )
398{
399 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
400 PURB pUrb;
401 struct usb_ctrlrequest *dr;
402 PULONG pBuffer;
403 int ret = -1;
404 PREG_QUEUE pRegQueue;
405
406
407 if (pWb35Reg->SyncIoPause)
408 goto cleanup;
409
410 if (pHwData->SurpriseRemove)
411 goto cleanup;
412
413 // Get the register data and send to USB through Irp
414 OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock );
415 pRegQueue = pWb35Reg->pRegFirst;
416 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
417
418 if (!pRegQueue)
419 goto cleanup;
420
421 // Get an Urb, send it
422 pUrb = (PURB)pRegQueue->pUrb;
423
424 dr = pRegQueue->pUsbReq;
425 pUrb = pRegQueue->pUrb;
426 pBuffer = pRegQueue->pBuffer;
427 if (pRegQueue->DIRECT == 1) // output
428 pBuffer = &pRegQueue->VALUE;
429
430 usb_fill_control_urb( pUrb, pHwData->WbUsb.udev,
431 REG_DIRECTION(pHwData->WbUsb.udev,pRegQueue),
432 (PUCHAR)dr,pBuffer,cpu_to_le16(dr->wLength),
433 Wb35Reg_EP0VM_complete, (void*)pHwData);
434
435 pWb35Reg->EP0vm_state = VM_RUNNING;
436
437 ret = wb_usb_submit_urb( pUrb );
438
439 if (ret < 0) {
440#ifdef _PE_REG_DUMP_
441 WBDEBUG(("EP0 Irp sending error\n"));
442#endif
443 goto cleanup;
444 }
445
446 return;
447
448 cleanup:
449 pWb35Reg->EP0vm_state = VM_STOP;
450 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Reg->RegFireCount );
451}
452
453
454void
455Wb35Reg_EP0VM_complete(PURB pUrb)
456{
457 phw_data_t pHwData = (phw_data_t)pUrb->context;
458 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
459 PREG_QUEUE pRegQueue;
460
461
462 // Variable setting
463 pWb35Reg->EP0vm_state = VM_COMPLETED;
464 pWb35Reg->EP0VM_status = pUrb->status;
465
466 if (pHwData->SurpriseRemove) { // Let WbWlanHalt to handle surprise remove
467 pWb35Reg->EP0vm_state = VM_STOP;
468 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Reg->RegFireCount );
469 } else {
470 // Complete to send, remove the URB from the first
471 OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock );
472 pRegQueue = pWb35Reg->pRegFirst;
473 if (pRegQueue == pWb35Reg->pRegLast)
474 pWb35Reg->pRegLast = NULL;
475 pWb35Reg->pRegFirst = pWb35Reg->pRegFirst->Next;
476 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
477
478 if (pWb35Reg->EP0VM_status) {
479#ifdef _PE_REG_DUMP_
480 WBDEBUG(("EP0 IoCompleteRoutine return error\n"));
481 DebugUsbdStatusInformation( pWb35Reg->EP0VM_status );
482#endif
483 pWb35Reg->EP0vm_state = VM_STOP;
484 pHwData->SurpriseRemove = 1;
485 } else {
486 // Success. Update the result
487
488 // Start the next send
489 Wb35Reg_EP0VM(pHwData);
490 }
491
492 kfree(pRegQueue);
493 }
494
495 usb_free_urb(pUrb);
496}
497
498
499void
500Wb35Reg_destroy(phw_data_t pHwData)
501{
502 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
503 PURB pUrb;
504 PREG_QUEUE pRegQueue;
505
506
507 Uxx_power_off_procedure(pHwData);
508
509 // Wait for Reg operation completed
510 do {
511 OS_SLEEP(10000); // Delay for waiting function enter 940623.1.a
512 } while (pWb35Reg->EP0vm_state != VM_STOP);
513 OS_SLEEP(10000); // Delay for waiting function enter 940623.1.b
514
515 // Release all the data in RegQueue
516 OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock );
517 pRegQueue = pWb35Reg->pRegFirst;
518 while (pRegQueue) {
519 if (pRegQueue == pWb35Reg->pRegLast)
520 pWb35Reg->pRegLast = NULL;
521 pWb35Reg->pRegFirst = pWb35Reg->pRegFirst->Next;
522
523 pUrb = pRegQueue->pUrb;
524 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
525 if (pUrb) {
526 usb_free_urb(pUrb);
527 kfree(pRegQueue);
528 } else {
529 #ifdef _PE_REG_DUMP_
530 WBDEBUG(("EP0 queue release error\n"));
531 #endif
532 }
533 OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock );
534
535 pRegQueue = pWb35Reg->pRegFirst;
536 }
537 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock );
538
539 // Free resource
540 OS_SPIN_LOCK_FREE( &pWb35Reg->EP0VM_spin_lock );
541}
542
543//====================================================================================
544// The function can be run in passive-level only.
545//====================================================================================
546unsigned char Wb35Reg_initial(phw_data_t pHwData)
547{
548 PWB35REG pWb35Reg=&pHwData->Wb35Reg;
549 u32 ltmp;
550 u32 SoftwareSet, VCO_trim, TxVga, Region_ScanInterval;
551
552 // Spin lock is acquired for read and write IRP command
553 OS_SPIN_LOCK_ALLOCATE( &pWb35Reg->EP0VM_spin_lock );
554
555 // Getting RF module type from EEPROM ------------------------------------
556 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x080d0000 ); // Start EEPROM access + Read + address(0x0d)
557 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
558
559 //Update RF module type and determine the PHY type by inf or EEPROM
560 pWb35Reg->EEPROMPhyType = (u8)( ltmp & 0xff );
561 // 0 V MAX2825, 1 V MAX2827, 2 V MAX2828, 3 V MAX2829
562 // 16V AL2230, 17 - AL7230, 18 - AL2230S
563 // 32 Reserved
564 // 33 - W89RF242(TxVGA 0~19), 34 - W89RF242(TxVGA 0~34)
565 if (pWb35Reg->EEPROMPhyType != RF_DECIDE_BY_INF) {
566 if( (pWb35Reg->EEPROMPhyType == RF_MAXIM_2825) ||
567 (pWb35Reg->EEPROMPhyType == RF_MAXIM_2827) ||
568 (pWb35Reg->EEPROMPhyType == RF_MAXIM_2828) ||
569 (pWb35Reg->EEPROMPhyType == RF_MAXIM_2829) ||
570 (pWb35Reg->EEPROMPhyType == RF_MAXIM_V1) ||
571 (pWb35Reg->EEPROMPhyType == RF_AIROHA_2230) ||
572 (pWb35Reg->EEPROMPhyType == RF_AIROHA_2230S) ||
573 (pWb35Reg->EEPROMPhyType == RF_AIROHA_7230) ||
574 (pWb35Reg->EEPROMPhyType == RF_WB_242) ||
575 (pWb35Reg->EEPROMPhyType == RF_WB_242_1))
576 pHwData->phy_type = pWb35Reg->EEPROMPhyType;
577 }
578
579 // Power On procedure running. The relative parameter will be set according to phy_type
580 Uxx_power_on_procedure( pHwData );
581
582 // Reading MAC address
583 Uxx_ReadEthernetAddress( pHwData );
584
585 // Read VCO trim for RF parameter
586 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08200000 );
587 Wb35Reg_ReadSync( pHwData, 0x03b4, &VCO_trim );
588
589 // Read Antenna On/Off of software flag
590 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08210000 );
591 Wb35Reg_ReadSync( pHwData, 0x03b4, &SoftwareSet );
592
593 // Read TXVGA
594 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 );
595 Wb35Reg_ReadSync( pHwData, 0x03b4, &TxVga );
596
597 // Get Scan interval setting from EEPROM offset 0x1c
598 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x081d0000 );
599 Wb35Reg_ReadSync( pHwData, 0x03b4, &Region_ScanInterval );
600
601 // Update Ethernet address
602 memcpy( pHwData->CurrentMacAddress, pHwData->PermanentMacAddress, ETH_LENGTH_OF_ADDRESS );
603
604 // Update software variable
605 pHwData->SoftwareSet = (u16)(SoftwareSet & 0xffff);
606 TxVga &= 0x000000ff;
607 pHwData->PowerIndexFromEEPROM = (u8)TxVga;
608 pHwData->VCO_trim = (u8)VCO_trim & 0xff;
609 if (pHwData->VCO_trim == 0xff)
610 pHwData->VCO_trim = 0x28;
611
612 pWb35Reg->EEPROMRegion = (u8)(Region_ScanInterval>>8); // 20060720
613 if( pWb35Reg->EEPROMRegion<1 || pWb35Reg->EEPROMRegion>6 )
614 pWb35Reg->EEPROMRegion = REGION_AUTO;
615
616 //For Get Tx VGA from EEPROM 20060315.5 move here
617 GetTxVgaFromEEPROM( pHwData );
618
619 // Set Scan Interval
620 pHwData->Scan_Interval = (u8)(Region_ScanInterval & 0xff) * 10;
621 if ((pHwData->Scan_Interval == 2550) || (pHwData->Scan_Interval < 10)) // Is default setting 0xff * 10
622 pHwData->Scan_Interval = SCAN_MAX_CHNL_TIME;
623
624 // Initial register
625 RFSynthesizer_initial(pHwData);
626
627 BBProcessor_initial(pHwData); // Async write, must wait until complete
628
629 Wb35Reg_phy_calibration(pHwData);
630
631 Mxx_initial(pHwData);
632 Dxx_initial(pHwData);
633
634 if (pHwData->SurpriseRemove)
635 return FALSE;
636 else
637 return TRUE; // Initial fail
638}
639
640//===================================================================================
641// CardComputeCrc --
642//
643// Description:
644// Runs the AUTODIN II CRC algorithm on buffer Buffer of length, Length.
645//
646// Arguments:
647// Buffer - the input buffer
648// Length - the length of Buffer
649//
650// Return Value:
651// The 32-bit CRC value.
652//
653// Note:
654// This is adapted from the comments in the assembly language
655// version in _GENREQ.ASM of the DWB NE1000/2000 driver.
656//==================================================================================
657u32
658CardComputeCrc(PUCHAR Buffer, u32 Length)
659{
660 u32 Crc, Carry;
661 u32 i, j;
662 u8 CurByte;
663
664 Crc = 0xffffffff;
665
666 for (i = 0; i < Length; i++) {
667
668 CurByte = Buffer[i];
669
670 for (j = 0; j < 8; j++) {
671
672 Carry = ((Crc & 0x80000000) ? 1 : 0) ^ (CurByte & 0x01);
673 Crc <<= 1;
674 CurByte >>= 1;
675
676 if (Carry) {
677 Crc =(Crc ^ 0x04c11db6) | Carry;
678 }
679 }
680 }
681
682 return Crc;
683}
684
685
686//==================================================================
687// BitReverse --
688// Reverse the bits in the input argument, dwData, which is
689// regarded as a string of bits with the length, DataLength.
690//
691// Arguments:
692// dwData :
693// DataLength :
694//
695// Return:
696// The converted value.
697//==================================================================
698u32 BitReverse( u32 dwData, u32 DataLength)
699{
700 u32 HalfLength, i, j;
701 u32 BitA, BitB;
702
703 if ( DataLength <= 0) return 0; // No conversion is done.
704 dwData = dwData & (0xffffffff >> (32 - DataLength));
705
706 HalfLength = DataLength / 2;
707 for ( i = 0, j = DataLength-1 ; i < HalfLength; i++, j--)
708 {
709 BitA = GetBit( dwData, i);
710 BitB = GetBit( dwData, j);
711 if (BitA && !BitB) {
712 dwData = ClearBit( dwData, i);
713 dwData = SetBit( dwData, j);
714 } else if (!BitA && BitB) {
715 dwData = SetBit( dwData, i);
716 dwData = ClearBit( dwData, j);
717 } else
718 {
719 // Do nothing since these two bits are of the save values.
720 }
721 }
722
723 return dwData;
724}
725
726void Wb35Reg_phy_calibration( phw_data_t pHwData )
727{
728 u32 BB3c, BB54;
729
730 if ((pHwData->phy_type == RF_WB_242) ||
731 (pHwData->phy_type == RF_WB_242_1)) {
732 phy_calibration_winbond ( pHwData, 2412 ); // Sync operation
733 Wb35Reg_ReadSync( pHwData, 0x103c, &BB3c );
734 Wb35Reg_ReadSync( pHwData, 0x1054, &BB54 );
735
736 pHwData->BB3c_cal = BB3c;
737 pHwData->BB54_cal = BB54;
738
739 RFSynthesizer_initial(pHwData);
740 BBProcessor_initial(pHwData); // Async operation
741
742 Wb35Reg_WriteSync( pHwData, 0x103c, BB3c );
743 Wb35Reg_WriteSync( pHwData, 0x1054, BB54 );
744 }
745}
746
747
diff --git a/drivers/staging/winbond/linux/wb35reg_f.h b/drivers/staging/winbond/linux/wb35reg_f.h
new file mode 100644
index 000000000000..38e2906b51a7
--- /dev/null
+++ b/drivers/staging/winbond/linux/wb35reg_f.h
@@ -0,0 +1,56 @@
1//====================================
2// Interface function declare
3//====================================
4unsigned char Wb35Reg_initial( phw_data_t pHwData );
5void Uxx_power_on_procedure( phw_data_t pHwData );
6void Uxx_power_off_procedure( phw_data_t pHwData );
7void Uxx_ReadEthernetAddress( phw_data_t pHwData );
8void Dxx_initial( phw_data_t pHwData );
9void Mxx_initial( phw_data_t pHwData );
10void RFSynthesizer_initial( phw_data_t pHwData );
11//void RFSynthesizer_SwitchingChannel( phw_data_t pHwData, s8 Channel );
12void RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel );
13void BBProcessor_initial( phw_data_t pHwData );
14void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ); // 20060613.1
15//void RF_RateChanging( phw_data_t pHwData, u8 rate ); // 20060626.5.c Add
16u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex );
17u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t, u8 index );
18u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t, u8 index );
19u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t, u8 index );
20u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t, u8 index );
21u8 RFSynthesizer_SetMaxim2825Power( phw_data_t, u8 index );
22u8 RFSynthesizer_SetAiroha2230Power( phw_data_t, u8 index );
23u8 RFSynthesizer_SetAiroha7230Power( phw_data_t, u8 index );
24u8 RFSynthesizer_SetWinbond242Power( phw_data_t, u8 index );
25void GetTxVgaFromEEPROM( phw_data_t pHwData );
26void EEPROMTxVgaAdjust( phw_data_t pHwData ); // 20060619.5 Add
27
28#define RFWriteControlData( _A, _V ) Wb35Reg_Write( _A, 0x0864, _V )
29
30void Wb35Reg_destroy( phw_data_t pHwData );
31
32unsigned char Wb35Reg_Read( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue );
33unsigned char Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue );
34unsigned char Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
35unsigned char Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
36unsigned char Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData,
37 u16 RegisterNo,
38 u32 RegisterValue,
39 PCHAR pValue,
40 s8 Len);
41unsigned char Wb35Reg_BurstWrite( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterData, u8 NumberOfData, u8 Flag );
42
43void Wb35Reg_EP0VM( phw_data_t pHwData );
44void Wb35Reg_EP0VM_start( phw_data_t pHwData );
45void Wb35Reg_EP0VM_complete( PURB pUrb );
46
47u32 BitReverse( u32 dwData, u32 DataLength);
48
49void CardGetMulticastBit( u8 Address[MAC_ADDR_LENGTH], u8 *Byte, u8 *Value );
50u32 CardComputeCrc( PUCHAR Buffer, u32 Length );
51
52void Wb35Reg_phy_calibration( phw_data_t pHwData );
53void Wb35Reg_Update( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
54unsigned char adjust_TXVGA_for_iq_mag( phw_data_t pHwData );
55
56
diff --git a/drivers/staging/winbond/linux/wb35reg_s.h b/drivers/staging/winbond/linux/wb35reg_s.h
new file mode 100644
index 000000000000..a7595b1e7336
--- /dev/null
+++ b/drivers/staging/winbond/linux/wb35reg_s.h
@@ -0,0 +1,170 @@
1//=======================================================================================
2/*
3 HAL setting function
4
5 ========================================
6 |Uxx| |Dxx| |Mxx| |BB| |RF|
7 ========================================
8 | |
9 Wb35Reg_Read Wb35Reg_Write
10
11 ----------------------------------------
12 WbUsb_CallUSBDASync supplied By WbUsb module
13*/
14//=======================================================================================
15
16#define GetBit( dwData, i) ( dwData & (0x00000001 << i))
17#define SetBit( dwData, i) ( dwData | (0x00000001 << i))
18#define ClearBit( dwData, i) ( dwData & ~(0x00000001 << i))
19
20#define IGNORE_INCREMENT 0
21#define AUTO_INCREMENT 0
22#define NO_INCREMENT 1
23#define REG_DIRECTION(_x,_y) ((_y)->DIRECT ==0 ? usb_rcvctrlpipe(_x,0) : usb_sndctrlpipe(_x,0))
24#define REG_BUF_SIZE(_x) ((_x)->bRequest== 0x04 ? cpu_to_le16((_x)->wLength) : 4)
25
26// 20060613.2 Add the follow definition
27#define BB48_DEFAULT_AL2230_11B 0x0033447c
28#define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF
29#define BB48_DEFAULT_AL2230_11G 0x00332C1B
30#define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF
31
32
33#define BB48_DEFAULT_WB242_11B 0x00292315 //backoff 2dB
34#define BB4C_DEFAULT_WB242_11B 0x0800FEFF //backoff 2dB
35//#define BB48_DEFAULT_WB242_11B 0x00201B11 //backoff 4dB
36//#define BB4C_DEFAULT_WB242_11B 0x0600FF00 //backoff 4dB
37#define BB48_DEFAULT_WB242_11G 0x00453B24
38#define BB4C_DEFAULT_WB242_11G 0x0E00FEFF
39
40//====================================
41// Default setting for Mxx
42//====================================
43#define DEFAULT_CWMIN 31 //(M2C) CWmin. Its value is in the range 0-31.
44#define DEFAULT_CWMAX 1023 //(M2C) CWmax. Its value is in the range 0-1023.
45#define DEFAULT_AID 1 //(M34) AID. Its value is in the range 1-2007.
46
47#ifdef _USE_FALLBACK_RATE_
48#define DEFAULT_RATE_RETRY_LIMIT 2 //(M38) as named
49#else
50#define DEFAULT_RATE_RETRY_LIMIT 7 //(M38) as named
51#endif
52
53#define DEFAULT_LONG_RETRY_LIMIT 7 //(M38) LongRetryLimit. Its value is in the range 0-15.
54#define DEFAULT_SHORT_RETRY_LIMIT 7 //(M38) ShortRetryLimit. Its value is in the range 0-15.
55#define DEFAULT_PIFST 25 //(M3C) PIFS Time. Its value is in the range 0-65535.
56#define DEFAULT_EIFST 354 //(M3C) EIFS Time. Its value is in the range 0-1048575.
57#define DEFAULT_DIFST 45 //(M3C) DIFS Time. Its value is in the range 0-65535.
58#define DEFAULT_SIFST 5 //(M3C) SIFS Time. Its value is in the range 0-65535.
59#define DEFAULT_OSIFST 10 //(M3C) Original SIFS Time. Its value is in the range 0-15.
60#define DEFAULT_ATIMWD 0 //(M40) ATIM Window. Its value is in the range 0-65535.
61#define DEFAULT_SLOT_TIME 20 //(M40) ($) SlotTime. Its value is in the range 0-255.
62#define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 //(M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295.
63#define DEFAULT_BEACON_INTERVAL 500 //(M48) Beacon Interval. Its value is in the range 0-65535.
64#define DEFAULT_PROBE_DELAY_TIME 200 //(M48) Probe Delay Time. Its value is in the range 0-65535.
65#define DEFAULT_PROTOCOL_VERSION 0 //(M4C)
66#define DEFAULT_MAC_POWER_STATE 2 //(M4C) 2: MAC at power active
67#define DEFAULT_DTIM_ALERT_TIME 0
68
69
70typedef struct _REG_QUEUE
71{
72 struct urb *pUrb;
73 void* pUsbReq;
74 void* Next;
75 union
76 {
77 u32 VALUE;
78 PULONG pBuffer;
79 };
80 u8 RESERVED[4];// space reserved for communication
81
82 u16 INDEX; // For storing the register index
83 u8 RESERVED_VALID; //Indicate whether the RESERVED space is valid at this command.
84 u8 DIRECT; // 0:In 1:Out
85
86} REG_QUEUE, *PREG_QUEUE;
87
88//====================================
89// Internal variable for module
90//====================================
91#define MAX_SQ3_FILTER_SIZE 5
92typedef struct _WB35REG
93{
94 //============================
95 // Register Bank backup
96 //============================
97 u32 U1B0; //bit16 record the h/w radio on/off status
98 u32 U1BC_LEDConfigure;
99 u32 D00_DmaControl;
100 u32 M00_MacControl;
101 union {
102 struct {
103 u32 M04_MulticastAddress1;
104 u32 M08_MulticastAddress2;
105 };
106 u8 Multicast[8]; // contents of card multicast registers
107 };
108
109 u32 M24_MacControl;
110 u32 M28_MacControl;
111 u32 M2C_MacControl;
112 u32 M38_MacControl;
113 u32 M3C_MacControl; // 20060214 backup only
114 u32 M40_MacControl;
115 u32 M44_MacControl; // 20060214 backup only
116 u32 M48_MacControl; // 20060214 backup only
117 u32 M4C_MacStatus;
118 u32 M60_MacControl; // 20060214 backup only
119 u32 M68_MacControl; // 20060214 backup only
120 u32 M70_MacControl; // 20060214 backup only
121 u32 M74_MacControl; // 20060214 backup only
122 u32 M78_ERPInformation;//930206.2.b
123 u32 M7C_MacControl; // 20060214 backup only
124 u32 M80_MacControl; // 20060214 backup only
125 u32 M84_MacControl; // 20060214 backup only
126 u32 M88_MacControl; // 20060214 backup only
127 u32 M98_MacControl; // 20060214 backup only
128
129 //[20040722 WK]
130 //Baseband register
131 u32 BB0C; // Used for LNA calculation
132 u32 BB2C; //
133 u32 BB30; //11b acquisition control register
134 u32 BB3C;
135 u32 BB48; // 20051221.1.a 20060613.1 Fix OBW issue of 11b/11g rate
136 u32 BB4C; // 20060613.1 Fix OBW issue of 11b/11g rate
137 u32 BB50; //mode control register
138 u32 BB54;
139 u32 BB58; //IQ_ALPHA
140 u32 BB5C; // For test
141 u32 BB60; // for WTO read value
142
143 //-------------------
144 // VM
145 //-------------------
146 OS_SPIN_LOCK EP0VM_spin_lock; // 4B
147 u32 EP0VM_status;//$$
148 PREG_QUEUE pRegFirst;
149 PREG_QUEUE pRegLast;
150 OS_ATOMIC RegFireCount;
151
152 // Hardware status
153 u8 EP0vm_state;
154 u8 mac_power_save;
155 u8 EEPROMPhyType; // 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829),
156 // 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230)
157 // 32 ~ Reserved
158 // 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step)
159 // 48 ~ 255 ARE RESERVED.
160 u8 EEPROMRegion; //Region setting in EEPROM
161
162 u32 SyncIoPause; // If user use the Sync Io to access Hw, then pause the async access
163
164 u8 LNAValue[4]; //Table for speed up running
165 u32 SQ3_filter[MAX_SQ3_FILTER_SIZE];
166 u32 SQ3_index;
167
168} WB35REG, *PWB35REG;
169
170
diff --git a/drivers/staging/winbond/linux/wb35rx.c b/drivers/staging/winbond/linux/wb35rx.c
new file mode 100644
index 000000000000..26157eb3d5a2
--- /dev/null
+++ b/drivers/staging/winbond/linux/wb35rx.c
@@ -0,0 +1,337 @@
1//============================================================================
2// Copyright (c) 1996-2002 Winbond Electronic Corporation
3//
4// Module Name:
5// Wb35Rx.c
6//
7// Abstract:
8// Processing the Rx message from down layer
9//
10//============================================================================
11#include "sysdef.h"
12
13
14void Wb35Rx_start(phw_data_t pHwData)
15{
16 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
17
18 // Allow only one thread to run into the Wb35Rx() function
19 if (OS_ATOMIC_INC(pHwData->Adapter, &pWb35Rx->RxFireCounter) == 1) {
20 pWb35Rx->EP3vm_state = VM_RUNNING;
21 Wb35Rx(pHwData);
22 } else
23 OS_ATOMIC_DEC(pHwData->Adapter, &pWb35Rx->RxFireCounter);
24}
25
26// This function cannot reentrain
27void Wb35Rx( phw_data_t pHwData )
28{
29 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
30 PUCHAR pRxBufferAddress;
31 PURB pUrb = (PURB)pWb35Rx->RxUrb;
32 int retv;
33 u32 RxBufferId;
34
35 //
36 // Issuing URB
37 //
38 do {
39 if (pHwData->SurpriseRemove || pHwData->HwStop)
40 break;
41
42 if (pWb35Rx->rx_halt)
43 break;
44
45 // Get RxBuffer's ID
46 RxBufferId = pWb35Rx->RxBufferId;
47 if (!pWb35Rx->RxOwner[RxBufferId]) {
48 // It's impossible to run here.
49 #ifdef _PE_RX_DUMP_
50 WBDEBUG(("Rx driver fifo unavailable\n"));
51 #endif
52 break;
53 }
54
55 // Update buffer point, then start to bulkin the data from USB
56 pWb35Rx->RxBufferId++;
57 pWb35Rx->RxBufferId %= MAX_USB_RX_BUFFER_NUMBER;
58
59 pWb35Rx->CurrentRxBufferId = RxBufferId;
60
61 if (1 != OS_MEMORY_ALLOC((void* *)&pWb35Rx->pDRx, MAX_USB_RX_BUFFER)) {
62 printk("w35und: Rx memory alloc failed\n");
63 break;
64 }
65 pRxBufferAddress = pWb35Rx->pDRx;
66
67 usb_fill_bulk_urb(pUrb, pHwData->WbUsb.udev,
68 usb_rcvbulkpipe(pHwData->WbUsb.udev, 3),
69 pRxBufferAddress, MAX_USB_RX_BUFFER,
70 Wb35Rx_Complete, pHwData);
71
72 pWb35Rx->EP3vm_state = VM_RUNNING;
73
74 retv = wb_usb_submit_urb(pUrb);
75
76 if (retv != 0) {
77 printk("Rx URB sending error\n");
78 break;
79 }
80 return;
81 } while(FALSE);
82
83 // VM stop
84 pWb35Rx->EP3vm_state = VM_STOP;
85 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Rx->RxFireCounter );
86}
87
88void Wb35Rx_Complete(PURB pUrb)
89{
90 phw_data_t pHwData = pUrb->context;
91 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
92 PUCHAR pRxBufferAddress;
93 u32 SizeCheck;
94 u16 BulkLength;
95 u32 RxBufferId;
96 R00_DESCRIPTOR R00;
97
98 // Variable setting
99 pWb35Rx->EP3vm_state = VM_COMPLETED;
100 pWb35Rx->EP3VM_status = pUrb->status;//Store the last result of Irp
101
102 do {
103 RxBufferId = pWb35Rx->CurrentRxBufferId;
104
105 pRxBufferAddress = pWb35Rx->pDRx;
106 BulkLength = (u16)pUrb->actual_length;
107
108 // The IRP is completed
109 pWb35Rx->EP3vm_state = VM_COMPLETED;
110
111 if (pHwData->SurpriseRemove || pHwData->HwStop) // Must be here, or RxBufferId is invalid
112 break;
113
114 if (pWb35Rx->rx_halt)
115 break;
116
117 // Start to process the data only in successful condition
118 pWb35Rx->RxOwner[ RxBufferId ] = 0; // Set the owner to driver
119 R00.value = le32_to_cpu(*(PULONG)pRxBufferAddress);
120
121 // The URB is completed, check the result
122 if (pWb35Rx->EP3VM_status != 0) {
123 #ifdef _PE_USB_STATE_DUMP_
124 WBDEBUG(("EP3 IoCompleteRoutine return error\n"));
125 DebugUsbdStatusInformation( pWb35Rx->EP3VM_status );
126 #endif
127 pWb35Rx->EP3vm_state = VM_STOP;
128 break;
129 }
130
131 // 20060220 For recovering. check if operating in single USB mode
132 if (!HAL_USB_MODE_BURST(pHwData)) {
133 SizeCheck = R00.R00_receive_byte_count; //20060926 anson's endian
134 if ((SizeCheck & 0x03) > 0)
135 SizeCheck -= 4;
136 SizeCheck = (SizeCheck + 3) & ~0x03;
137 SizeCheck += 12; // 8 + 4 badbeef
138 if ((BulkLength > 1600) ||
139 (SizeCheck > 1600) ||
140 (BulkLength != SizeCheck) ||
141 (BulkLength == 0)) { // Add for fail Urb
142 pWb35Rx->EP3vm_state = VM_STOP;
143 pWb35Rx->Ep3ErrorCount2++;
144 }
145 }
146
147 // Indicating the receiving data
148 pWb35Rx->ByteReceived += BulkLength;
149 pWb35Rx->RxBufferSize[ RxBufferId ] = BulkLength;
150
151 if (!pWb35Rx->RxOwner[ RxBufferId ])
152 Wb35Rx_indicate(pHwData);
153
154 kfree(pWb35Rx->pDRx);
155 // Do the next receive
156 Wb35Rx(pHwData);
157 return;
158
159 } while(FALSE);
160
161 pWb35Rx->RxOwner[ RxBufferId ] = 1; // Set the owner to hardware
162 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Rx->RxFireCounter );
163 pWb35Rx->EP3vm_state = VM_STOP;
164}
165
166//=====================================================================================
167unsigned char Wb35Rx_initial(phw_data_t pHwData)
168{
169 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
170
171 // Initial the Buffer Queue
172 Wb35Rx_reset_descriptor( pHwData );
173
174 pWb35Rx->RxUrb = wb_usb_alloc_urb(0);
175 return (!!pWb35Rx->RxUrb);
176}
177
178void Wb35Rx_stop(phw_data_t pHwData)
179{
180 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
181
182 // Canceling the Irp if already sends it out.
183 if (pWb35Rx->EP3vm_state == VM_RUNNING) {
184 usb_unlink_urb( pWb35Rx->RxUrb ); // Only use unlink, let Wb35Rx_destroy to free them
185 #ifdef _PE_RX_DUMP_
186 WBDEBUG(("EP3 Rx stop\n"));
187 #endif
188 }
189}
190
191// Needs process context
192void Wb35Rx_destroy(phw_data_t pHwData)
193{
194 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
195
196 do {
197 OS_SLEEP(10000); // Delay for waiting function enter 940623.1.a
198 } while (pWb35Rx->EP3vm_state != VM_STOP);
199 OS_SLEEP(10000); // Delay for waiting function exit 940623.1.b
200
201 if (pWb35Rx->RxUrb)
202 usb_free_urb( pWb35Rx->RxUrb );
203 #ifdef _PE_RX_DUMP_
204 WBDEBUG(("Wb35Rx_destroy OK\n"));
205 #endif
206}
207
208void Wb35Rx_reset_descriptor( phw_data_t pHwData )
209{
210 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
211 u32 i;
212
213 pWb35Rx->ByteReceived = 0;
214 pWb35Rx->RxProcessIndex = 0;
215 pWb35Rx->RxBufferId = 0;
216 pWb35Rx->EP3vm_state = VM_STOP;
217 pWb35Rx->rx_halt = 0;
218
219 // Initial the Queue. The last buffer is reserved for used if the Rx resource is unavailable.
220 for( i=0; i<MAX_USB_RX_BUFFER_NUMBER; i++ )
221 pWb35Rx->RxOwner[i] = 1;
222}
223
224void Wb35Rx_adjust(PDESCRIPTOR pRxDes)
225{
226 PULONG pRxBufferAddress;
227 u32 DecryptionMethod;
228 u32 i;
229 u16 BufferSize;
230
231 DecryptionMethod = pRxDes->R01.R01_decryption_method;
232 pRxBufferAddress = pRxDes->buffer_address[0];
233 BufferSize = pRxDes->buffer_size[0];
234
235 // Adjust the last part of data. Only data left
236 BufferSize -= 4; // For CRC-32
237 if (DecryptionMethod)
238 BufferSize -= 4;
239 if (DecryptionMethod == 3) // For CCMP
240 BufferSize -= 4;
241
242 // Adjust the IV field which after 802.11 header and ICV field.
243 if (DecryptionMethod == 1) // For WEP
244 {
245 for( i=6; i>0; i-- )
246 pRxBufferAddress[i] = pRxBufferAddress[i-1];
247 pRxDes->buffer_address[0] = pRxBufferAddress + 1;
248 BufferSize -= 4; // 4 byte for IV
249 }
250 else if( DecryptionMethod ) // For TKIP and CCMP
251 {
252 for (i=7; i>1; i--)
253 pRxBufferAddress[i] = pRxBufferAddress[i-2];
254 pRxDes->buffer_address[0] = pRxBufferAddress + 2;//Update the descriptor, shift 8 byte
255 BufferSize -= 8; // 8 byte for IV + ICV
256 }
257 pRxDes->buffer_size[0] = BufferSize;
258}
259
260extern void packet_came(char *pRxBufferAddress, int PacketSize);
261
262
263u16 Wb35Rx_indicate(phw_data_t pHwData)
264{
265 DESCRIPTOR RxDes;
266 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
267 PUCHAR pRxBufferAddress;
268 u16 PacketSize;
269 u16 stmp, BufferSize, stmp2 = 0;
270 u32 RxBufferId;
271
272 // Only one thread be allowed to run into the following
273 do {
274 RxBufferId = pWb35Rx->RxProcessIndex;
275 if (pWb35Rx->RxOwner[ RxBufferId ]) //Owner by VM
276 break;
277
278 pWb35Rx->RxProcessIndex++;
279 pWb35Rx->RxProcessIndex %= MAX_USB_RX_BUFFER_NUMBER;
280
281 pRxBufferAddress = pWb35Rx->pDRx;
282 BufferSize = pWb35Rx->RxBufferSize[ RxBufferId ];
283
284 // Parse the bulkin buffer
285 while (BufferSize >= 4) {
286 if ((cpu_to_le32(*(PULONG)pRxBufferAddress) & 0x0fffffff) == RX_END_TAG) //Is ending? 921002.9.a
287 break;
288
289 // Get the R00 R01 first
290 RxDes.R00.value = le32_to_cpu(*(PULONG)pRxBufferAddress);
291 PacketSize = (u16)RxDes.R00.R00_receive_byte_count;
292 RxDes.R01.value = le32_to_cpu(*((PULONG)(pRxBufferAddress+4)));
293 // For new DMA 4k
294 if ((PacketSize & 0x03) > 0)
295 PacketSize -= 4;
296
297 // Basic check for Rx length. Is length valid?
298 if (PacketSize > MAX_PACKET_SIZE) {
299 #ifdef _PE_RX_DUMP_
300 WBDEBUG(("Serious ERROR : Rx data size too long, size =%d\n", PacketSize));
301 #endif
302
303 pWb35Rx->EP3vm_state = VM_STOP;
304 pWb35Rx->Ep3ErrorCount2++;
305 break;
306 }
307
308 // Start to process Rx buffer
309// RxDes.Descriptor_ID = RxBufferId; // Due to synchronous indicate, the field doesn't necessary to use.
310 BufferSize -= 8; //subtract 8 byte for 35's USB header length
311 pRxBufferAddress += 8;
312
313 RxDes.buffer_address[0] = pRxBufferAddress;
314 RxDes.buffer_size[0] = PacketSize;
315 RxDes.buffer_number = 1;
316 RxDes.buffer_start_index = 0;
317 RxDes.buffer_total_size = RxDes.buffer_size[0];
318 Wb35Rx_adjust(&RxDes);
319
320 packet_came(pRxBufferAddress, PacketSize);
321
322 // Move RxBuffer point to the next
323 stmp = PacketSize + 3;
324 stmp &= ~0x03; // 4n alignment
325 pRxBufferAddress += stmp;
326 BufferSize -= stmp;
327 stmp2 += stmp;
328 }
329
330 // Reclaim resource
331 pWb35Rx->RxOwner[ RxBufferId ] = 1;
332 } while(TRUE);
333
334 return stmp2;
335}
336
337
diff --git a/drivers/staging/winbond/linux/wb35rx_f.h b/drivers/staging/winbond/linux/wb35rx_f.h
new file mode 100644
index 000000000000..daa3e73042bd
--- /dev/null
+++ b/drivers/staging/winbond/linux/wb35rx_f.h
@@ -0,0 +1,17 @@
1//====================================
2// Interface function declare
3//====================================
4void Wb35Rx_reset_descriptor( phw_data_t pHwData );
5unsigned char Wb35Rx_initial( phw_data_t pHwData );
6void Wb35Rx_destroy( phw_data_t pHwData );
7void Wb35Rx_stop( phw_data_t pHwData );
8u16 Wb35Rx_indicate( phw_data_t pHwData );
9void Wb35Rx_adjust( PDESCRIPTOR pRxDes );
10void Wb35Rx_start( phw_data_t pHwData );
11
12void Wb35Rx( phw_data_t pHwData );
13void Wb35Rx_Complete( PURB pUrb );
14
15
16
17
diff --git a/drivers/staging/winbond/linux/wb35rx_s.h b/drivers/staging/winbond/linux/wb35rx_s.h
new file mode 100644
index 000000000000..53b831fdeb78
--- /dev/null
+++ b/drivers/staging/winbond/linux/wb35rx_s.h
@@ -0,0 +1,48 @@
1//============================================================================
2// wb35rx.h --
3//============================================================================
4
5// Definition for this module used
6#define MAX_USB_RX_BUFFER 4096 // This parameter must be 4096 931130.4.f
7
8#define MAX_USB_RX_BUFFER_NUMBER ETHERNET_RX_DESCRIPTORS // Maximum 254, 255 is RESERVED ID
9#define RX_INTERFACE 0 // Interface 1
10#define RX_PIPE 2 // Pipe 3
11#define MAX_PACKET_SIZE 1600 //1568 // 8 + 1532 + 4 + 24(IV EIV MIC ICV CRC) for check DMA data 931130.4.g
12#define RX_END_TAG 0x0badbeef
13
14
15//====================================
16// Internal variable for module
17//====================================
18typedef struct _WB35RX
19{
20 u32 ByteReceived;// For calculating throughput of BulkIn
21 OS_ATOMIC RxFireCounter;// Does Wb35Rx module fire?
22
23 u8 RxBuffer[ MAX_USB_RX_BUFFER_NUMBER ][ ((MAX_USB_RX_BUFFER+3) & ~0x03 ) ];
24 u16 RxBufferSize[ ((MAX_USB_RX_BUFFER_NUMBER+1) & ~0x01) ];
25 u8 RxOwner[ ((MAX_USB_RX_BUFFER_NUMBER+3) & ~0x03 ) ];//Ownership of buffer 0: SW 1:HW
26
27 u32 RxProcessIndex;//The next index to process
28 u32 RxBufferId;
29 u32 EP3vm_state;
30
31 u32 rx_halt; // For VM stopping
32
33 u16 MoreDataSize;
34 u16 PacketSize;
35
36 u32 CurrentRxBufferId; // For complete routine usage
37 u32 Rx3UrbCancel;
38
39 u32 LastR1; // For RSSI reporting
40 struct urb * RxUrb;
41 u32 Ep3ErrorCount2; // 20060625.1 Usbd for Rx DMA error count
42
43 int EP3VM_status;
44 PUCHAR pDRx;
45
46} WB35RX, *PWB35RX;
47
48
diff --git a/drivers/staging/winbond/linux/wb35tx.c b/drivers/staging/winbond/linux/wb35tx.c
new file mode 100644
index 000000000000..cf19c3bc524a
--- /dev/null
+++ b/drivers/staging/winbond/linux/wb35tx.c
@@ -0,0 +1,313 @@
1//============================================================================
2// Copyright (c) 1996-2002 Winbond Electronic Corporation
3//
4// Module Name:
5// Wb35Tx.c
6//
7// Abstract:
8// Processing the Tx message and put into down layer
9//
10//============================================================================
11#include "sysdef.h"
12
13
14unsigned char
15Wb35Tx_get_tx_buffer(phw_data_t pHwData, PUCHAR *pBuffer )
16{
17 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
18
19 *pBuffer = pWb35Tx->TxBuffer[0];
20 return TRUE;
21}
22
23void Wb35Tx_start(phw_data_t pHwData)
24{
25 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
26
27 // Allow only one thread to run into function
28 if (OS_ATOMIC_INC(pHwData->Adapter, &pWb35Tx->TxFireCounter) == 1) {
29 pWb35Tx->EP4vm_state = VM_RUNNING;
30 Wb35Tx(pHwData);
31 } else
32 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxFireCounter );
33}
34
35
36void Wb35Tx(phw_data_t pHwData)
37{
38 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
39 PADAPTER Adapter = pHwData->Adapter;
40 PUCHAR pTxBufferAddress;
41 PMDS pMds = &Adapter->Mds;
42 struct urb * pUrb = (struct urb *)pWb35Tx->Tx4Urb;
43 int retv;
44 u32 SendIndex;
45
46
47 if (pHwData->SurpriseRemove || pHwData->HwStop)
48 goto cleanup;
49
50 if (pWb35Tx->tx_halt)
51 goto cleanup;
52
53 // Ownership checking
54 SendIndex = pWb35Tx->TxSendIndex;
55 if (!pMds->TxOwner[SendIndex]) //No more data need to be sent, return immediately
56 goto cleanup;
57
58 pTxBufferAddress = pWb35Tx->TxBuffer[SendIndex];
59 //
60 // Issuing URB
61 //
62 usb_fill_bulk_urb(pUrb, pHwData->WbUsb.udev,
63 usb_sndbulkpipe(pHwData->WbUsb.udev, 4),
64 pTxBufferAddress, pMds->TxBufferSize[ SendIndex ],
65 Wb35Tx_complete, pHwData);
66
67 pWb35Tx->EP4vm_state = VM_RUNNING;
68 retv = wb_usb_submit_urb( pUrb );
69 if (retv<0) {
70 printk("EP4 Tx Irp sending error\n");
71 goto cleanup;
72 }
73
74 // Check if driver needs issue Irp for EP2
75 pWb35Tx->TxFillCount += pMds->TxCountInBuffer[SendIndex];
76 if (pWb35Tx->TxFillCount > 12)
77 Wb35Tx_EP2VM_start( pHwData );
78
79 pWb35Tx->ByteTransfer += pMds->TxBufferSize[SendIndex];
80 return;
81
82 cleanup:
83 pWb35Tx->EP4vm_state = VM_STOP;
84 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxFireCounter );
85}
86
87
88void Wb35Tx_complete(struct urb * pUrb)
89{
90 phw_data_t pHwData = pUrb->context;
91 PADAPTER Adapter = (PADAPTER)pHwData->Adapter;
92 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
93 PMDS pMds = &Adapter->Mds;
94
95 printk("wb35: tx complete\n");
96 // Variable setting
97 pWb35Tx->EP4vm_state = VM_COMPLETED;
98 pWb35Tx->EP4VM_status = pUrb->status; //Store the last result of Irp
99 pMds->TxOwner[ pWb35Tx->TxSendIndex ] = 0;// Set the owner. Free the owner bit always.
100 pWb35Tx->TxSendIndex++;
101 pWb35Tx->TxSendIndex %= MAX_USB_TX_BUFFER_NUMBER;
102
103 do {
104 if (pHwData->SurpriseRemove || pHwData->HwStop) // Let WbWlanHalt to handle surprise remove
105 break;
106
107 if (pWb35Tx->tx_halt)
108 break;
109
110 // The URB is completed, check the result
111 if (pWb35Tx->EP4VM_status != 0) {
112 printk("URB submission failed\n");
113 pWb35Tx->EP4vm_state = VM_STOP;
114 break; // Exit while(FALSE);
115 }
116
117 Mds_Tx(Adapter);
118 Wb35Tx(pHwData);
119 return;
120 } while(FALSE);
121
122 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxFireCounter );
123 pWb35Tx->EP4vm_state = VM_STOP;
124}
125
126void Wb35Tx_reset_descriptor( phw_data_t pHwData )
127{
128 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
129
130 pWb35Tx->TxSendIndex = 0;
131 pWb35Tx->tx_halt = 0;
132}
133
134unsigned char Wb35Tx_initial(phw_data_t pHwData)
135{
136 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
137
138 pWb35Tx->Tx4Urb = wb_usb_alloc_urb(0);
139 if (!pWb35Tx->Tx4Urb)
140 return FALSE;
141
142 pWb35Tx->Tx2Urb = wb_usb_alloc_urb(0);
143 if (!pWb35Tx->Tx2Urb)
144 {
145 usb_free_urb( pWb35Tx->Tx4Urb );
146 return FALSE;
147 }
148
149 return TRUE;
150}
151
152//======================================================
153void Wb35Tx_stop(phw_data_t pHwData)
154{
155 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
156
157 // Trying to canceling the Trp of EP2
158 if (pWb35Tx->EP2vm_state == VM_RUNNING)
159 usb_unlink_urb( pWb35Tx->Tx2Urb ); // Only use unlink, let Wb35Tx_destrot to free them
160 #ifdef _PE_TX_DUMP_
161 WBDEBUG(("EP2 Tx stop\n"));
162 #endif
163
164 // Trying to canceling the Irp of EP4
165 if (pWb35Tx->EP4vm_state == VM_RUNNING)
166 usb_unlink_urb( pWb35Tx->Tx4Urb ); // Only use unlink, let Wb35Tx_destrot to free them
167 #ifdef _PE_TX_DUMP_
168 WBDEBUG(("EP4 Tx stop\n"));
169 #endif
170}
171
172//======================================================
173void Wb35Tx_destroy(phw_data_t pHwData)
174{
175 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
176
177 // Wait for VM stop
178 do {
179 OS_SLEEP(10000); // Delay for waiting function enter 940623.1.a
180 } while( (pWb35Tx->EP2vm_state != VM_STOP) && (pWb35Tx->EP4vm_state != VM_STOP) );
181 OS_SLEEP(10000); // Delay for waiting function enter 940623.1.b
182
183 if (pWb35Tx->Tx4Urb)
184 usb_free_urb( pWb35Tx->Tx4Urb );
185
186 if (pWb35Tx->Tx2Urb)
187 usb_free_urb( pWb35Tx->Tx2Urb );
188
189 #ifdef _PE_TX_DUMP_
190 WBDEBUG(("Wb35Tx_destroy OK\n"));
191 #endif
192}
193
194void Wb35Tx_CurrentTime(phw_data_t pHwData, u32 TimeCount)
195{
196 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
197 unsigned char Trigger = FALSE;
198
199 if (pWb35Tx->TxTimer > TimeCount)
200 Trigger = TRUE;
201 else if (TimeCount > (pWb35Tx->TxTimer+500))
202 Trigger = TRUE;
203
204 if (Trigger) {
205 pWb35Tx->TxTimer = TimeCount;
206 Wb35Tx_EP2VM_start( pHwData );
207 }
208}
209
210void Wb35Tx_EP2VM_start(phw_data_t pHwData)
211{
212 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
213
214 // Allow only one thread to run into function
215 if (OS_ATOMIC_INC( pHwData->Adapter, &pWb35Tx->TxResultCount ) == 1) {
216 pWb35Tx->EP2vm_state = VM_RUNNING;
217 Wb35Tx_EP2VM( pHwData );
218 }
219 else
220 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxResultCount );
221}
222
223
224void Wb35Tx_EP2VM(phw_data_t pHwData)
225{
226 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
227 struct urb * pUrb = (struct urb *)pWb35Tx->Tx2Urb;
228 PULONG pltmp = (PULONG)pWb35Tx->EP2_buf;
229 int retv;
230
231 do {
232 if (pHwData->SurpriseRemove || pHwData->HwStop)
233 break;
234
235 if (pWb35Tx->tx_halt)
236 break;
237
238 //
239 // Issuing URB
240 //
241 usb_fill_int_urb( pUrb, pHwData->WbUsb.udev, usb_rcvintpipe(pHwData->WbUsb.udev,2),
242 pltmp, MAX_INTERRUPT_LENGTH, Wb35Tx_EP2VM_complete, pHwData, 32);
243
244 pWb35Tx->EP2vm_state = VM_RUNNING;
245 retv = wb_usb_submit_urb( pUrb );
246
247 if(retv < 0) {
248 #ifdef _PE_TX_DUMP_
249 WBDEBUG(("EP2 Tx Irp sending error\n"));
250 #endif
251 break;
252 }
253
254 return;
255
256 } while(FALSE);
257
258 pWb35Tx->EP2vm_state = VM_STOP;
259 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxResultCount );
260}
261
262
263void Wb35Tx_EP2VM_complete(struct urb * pUrb)
264{
265 phw_data_t pHwData = pUrb->context;
266 T02_DESCRIPTOR T02, TSTATUS;
267 PADAPTER Adapter = (PADAPTER)pHwData->Adapter;
268 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
269 PULONG pltmp = (PULONG)pWb35Tx->EP2_buf;
270 u32 i;
271 u16 InterruptInLength;
272
273
274 // Variable setting
275 pWb35Tx->EP2vm_state = VM_COMPLETED;
276 pWb35Tx->EP2VM_status = pUrb->status;
277
278 do {
279 // For Linux 2.4. Interrupt will always trigger
280 if( pHwData->SurpriseRemove || pHwData->HwStop ) // Let WbWlanHalt to handle surprise remove
281 break;
282
283 if( pWb35Tx->tx_halt )
284 break;
285
286 //The Urb is completed, check the result
287 if (pWb35Tx->EP2VM_status != 0) {
288 WBDEBUG(("EP2 IoCompleteRoutine return error\n"));
289 pWb35Tx->EP2vm_state= VM_STOP;
290 break; // Exit while(FALSE);
291 }
292
293 // Update the Tx result
294 InterruptInLength = pUrb->actual_length;
295 // Modify for minimum memory access and DWORD alignment.
296 T02.value = cpu_to_le32(pltmp[0]) >> 8; // [31:8] -> [24:0]
297 InterruptInLength -= 1;// 20051221.1.c Modify the follow for more stable
298 InterruptInLength >>= 2; // InterruptInLength/4
299 for (i=1; i<=InterruptInLength; i++) {
300 T02.value |= ((cpu_to_le32(pltmp[i]) & 0xff) << 24);
301
302 TSTATUS.value = T02.value; //20061009 anson's endian
303 Mds_SendComplete( Adapter, &TSTATUS );
304 T02.value = cpu_to_le32(pltmp[i]) >> 8;
305 }
306
307 return;
308 } while(FALSE);
309
310 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxResultCount );
311 pWb35Tx->EP2vm_state = VM_STOP;
312}
313
diff --git a/drivers/staging/winbond/linux/wb35tx_f.h b/drivers/staging/winbond/linux/wb35tx_f.h
new file mode 100644
index 000000000000..7705a8454dcb
--- /dev/null
+++ b/drivers/staging/winbond/linux/wb35tx_f.h
@@ -0,0 +1,20 @@
1//====================================
2// Interface function declare
3//====================================
4unsigned char Wb35Tx_initial( phw_data_t pHwData );
5void Wb35Tx_destroy( phw_data_t pHwData );
6unsigned char Wb35Tx_get_tx_buffer( phw_data_t pHwData, PUCHAR *pBuffer );
7
8void Wb35Tx_EP2VM( phw_data_t pHwData );
9void Wb35Tx_EP2VM_start( phw_data_t pHwData );
10void Wb35Tx_EP2VM_complete( PURB purb );
11
12void Wb35Tx_start( phw_data_t pHwData );
13void Wb35Tx_stop( phw_data_t pHwData );
14void Wb35Tx( phw_data_t pHwData );
15void Wb35Tx_complete( PURB purb );
16void Wb35Tx_reset_descriptor( phw_data_t pHwData );
17
18void Wb35Tx_CurrentTime( phw_data_t pHwData, u32 TimeCount );
19
20
diff --git a/drivers/staging/winbond/linux/wb35tx_s.h b/drivers/staging/winbond/linux/wb35tx_s.h
new file mode 100644
index 000000000000..ac4325736760
--- /dev/null
+++ b/drivers/staging/winbond/linux/wb35tx_s.h
@@ -0,0 +1,47 @@
1//====================================
2// IS89C35 Tx related definition
3//====================================
4#define TX_INTERFACE 0 // Interface 1
5#define TX_PIPE 3 // endpoint 4
6#define TX_INTERRUPT 1 // endpoint 2
7#define MAX_INTERRUPT_LENGTH 64 // It must be 64 for EP2 hardware
8
9
10
11//====================================
12// Internal variable for module
13//====================================
14
15
16typedef struct _WB35TX
17{
18 // For Tx buffer
19 u8 TxBuffer[ MAX_USB_TX_BUFFER_NUMBER ][ MAX_USB_TX_BUFFER ];
20
21 // For Interrupt pipe
22 u8 EP2_buf[MAX_INTERRUPT_LENGTH];
23
24 OS_ATOMIC TxResultCount;// For thread control of EP2 931130.4.m
25 OS_ATOMIC TxFireCounter;// For thread control of EP4 931130.4.n
26 u32 ByteTransfer;
27
28 u32 TxSendIndex;// The next index of Mds array to be sent
29 u32 EP2vm_state; // for EP2vm state
30 u32 EP4vm_state; // for EP4vm state
31 u32 tx_halt; // Stopping VM
32
33 struct urb * Tx4Urb;
34 struct urb * Tx2Urb;
35
36 int EP2VM_status;
37 int EP4VM_status;
38
39 u32 TxFillCount; // 20060928
40 u32 TxTimer; // 20060928 Add if sending packet not great than 13
41
42} WB35TX, *PWB35TX;
43
44
45
46
47
diff --git a/drivers/staging/winbond/linux/wbusb.c b/drivers/staging/winbond/linux/wbusb.c
new file mode 100644
index 000000000000..cbad5fb05959
--- /dev/null
+++ b/drivers/staging/winbond/linux/wbusb.c
@@ -0,0 +1,404 @@
1/*
2 * Copyright 2008 Pavel Machek <pavel@suse.cz>
3 *
4 * Distribute under GPLv2.
5 */
6#include "sysdef.h"
7#include <net/mac80211.h>
8
9
10MODULE_AUTHOR( DRIVER_AUTHOR );
11MODULE_DESCRIPTION( DRIVER_DESC );
12MODULE_LICENSE("GPL");
13MODULE_VERSION("0.1");
14
15
16//============================================================
17// vendor ID and product ID can into here for others
18//============================================================
19static struct usb_device_id Id_Table[] =
20{
21 {USB_DEVICE( 0x0416, 0x0035 )},
22 {USB_DEVICE( 0x18E8, 0x6201 )},
23 {USB_DEVICE( 0x18E8, 0x6206 )},
24 {USB_DEVICE( 0x18E8, 0x6217 )},
25 {USB_DEVICE( 0x18E8, 0x6230 )},
26 {USB_DEVICE( 0x18E8, 0x6233 )},
27 {USB_DEVICE( 0x1131, 0x2035 )},
28 { }
29};
30
31MODULE_DEVICE_TABLE(usb, Id_Table);
32
33static struct usb_driver wb35_driver = {
34 .name = "w35und",
35 .probe = wb35_probe,
36 .disconnect = wb35_disconnect,
37 .id_table = Id_Table,
38};
39
40static const struct ieee80211_rate wbsoft_rates[] = {
41 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
42};
43
44static const struct ieee80211_channel wbsoft_channels[] = {
45 { .center_freq = 2412},
46};
47
48int wbsoft_enabled;
49struct ieee80211_hw *my_dev;
50PADAPTER my_adapter;
51
52static int wbsoft_add_interface(struct ieee80211_hw *dev,
53 struct ieee80211_if_init_conf *conf)
54{
55 printk("wbsoft_add interface called\n");
56 return 0;
57}
58
59static void wbsoft_remove_interface(struct ieee80211_hw *dev,
60 struct ieee80211_if_init_conf *conf)
61{
62 printk("wbsoft_remove interface called\n");
63}
64
65static int wbsoft_nop(void)
66{
67 printk("wbsoft_nop called\n");
68 return 0;
69}
70
71static void wbsoft_configure_filter(struct ieee80211_hw *dev,
72 unsigned int changed_flags,
73 unsigned int *total_flags,
74 int mc_count, struct dev_mc_list *mclist)
75{
76 unsigned int bit_nr, new_flags;
77 u32 mc_filter[2];
78 int i;
79
80 new_flags = 0;
81
82 if (*total_flags & FIF_PROMISC_IN_BSS) {
83 new_flags |= FIF_PROMISC_IN_BSS;
84 mc_filter[1] = mc_filter[0] = ~0;
85 } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) {
86 new_flags |= FIF_ALLMULTI;
87 mc_filter[1] = mc_filter[0] = ~0;
88 } else {
89 mc_filter[1] = mc_filter[0] = 0;
90 for (i = 0; i < mc_count; i++) {
91 if (!mclist)
92 break;
93 printk("Should call ether_crc here\n");
94 //bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
95 bit_nr = 0;
96
97 bit_nr &= 0x3F;
98 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
99 mclist = mclist->next;
100 }
101 }
102
103 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
104
105 *total_flags = new_flags;
106}
107
108static int wbsoft_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
109 struct ieee80211_tx_control *control)
110{
111 char *buffer = kmalloc(skb->len, GFP_ATOMIC);
112 printk("Sending frame %d bytes\n", skb->len);
113 memcpy(buffer, skb->data, skb->len);
114 if (1 == MLMESendFrame(my_adapter, buffer, skb->len, FRAME_TYPE_802_11_MANAGEMENT))
115 printk("frame sent ok (%d bytes)?\n", skb->len);
116 return NETDEV_TX_OK;
117}
118
119
120static int wbsoft_start(struct ieee80211_hw *dev)
121{
122 wbsoft_enabled = 1;
123 printk("wbsoft_start called\n");
124 return 0;
125}
126
127static int wbsoft_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
128{
129 ChanInfo ch;
130 printk("wbsoft_config called\n");
131
132 ch.band = 1;
133 ch.ChanNo = 1; /* Should use channel_num, or something, as that is already pre-translated */
134
135
136 hal_set_current_channel(&my_adapter->sHwData, ch);
137 hal_set_beacon_period(&my_adapter->sHwData, conf->beacon_int);
138// hal_set_cap_info(&my_adapter->sHwData, ?? );
139// hal_set_ssid(phw_data_t pHwData, PUCHAR pssid, u8 ssid_len); ??
140 hal_set_accept_broadcast(&my_adapter->sHwData, 1);
141 hal_set_accept_promiscuous(&my_adapter->sHwData, 1);
142 hal_set_accept_multicast(&my_adapter->sHwData, 1);
143 hal_set_accept_beacon(&my_adapter->sHwData, 1);
144 hal_set_radio_mode(&my_adapter->sHwData, 0);
145 //hal_set_antenna_number( phw_data_t pHwData, u8 number )
146 //hal_set_rf_power(phw_data_t pHwData, u8 PowerIndex)
147
148
149// hal_start_bss(&my_adapter->sHwData, WLAN_BSSTYPE_INFRASTRUCTURE); ??
150
151//void hal_set_rates(phw_data_t pHwData, PUCHAR pbss_rates,
152// u8 length, unsigned char basic_rate_set)
153
154 return 0;
155}
156
157static int wbsoft_config_interface(struct ieee80211_hw *dev,
158 struct ieee80211_vif *vif,
159 struct ieee80211_if_conf *conf)
160{
161 printk("wbsoft_config_interface called\n");
162 return 0;
163}
164
165static u64 wbsoft_get_tsf(struct ieee80211_hw *dev)
166{
167 printk("wbsoft_get_tsf called\n");
168 return 0;
169}
170
171static const struct ieee80211_ops wbsoft_ops = {
172 .tx = wbsoft_tx,
173 .start = wbsoft_start, /* Start can be pretty much empty as we do WbWLanInitialize() during probe? */
174 .stop = wbsoft_nop,
175 .add_interface = wbsoft_add_interface,
176 .remove_interface = wbsoft_remove_interface,
177 .config = wbsoft_config,
178 .config_interface = wbsoft_config_interface,
179 .configure_filter = wbsoft_configure_filter,
180 .get_stats = wbsoft_nop,
181 .get_tx_stats = wbsoft_nop,
182 .get_tsf = wbsoft_get_tsf,
183// conf_tx: hal_set_cwmin()/hal_set_cwmax;
184};
185
186struct wbsoft_priv {
187};
188
189
190int __init wb35_init(void)
191{
192 printk("[w35und]driver init\n");
193 return usb_register(&wb35_driver);
194}
195
196void __exit wb35_exit(void)
197{
198 printk("[w35und]driver exit\n");
199 usb_deregister( &wb35_driver );
200}
201
202module_init(wb35_init);
203module_exit(wb35_exit);
204
205// Usb kernel subsystem will call this function when a new device is plugged into.
206int wb35_probe(struct usb_interface *intf, const struct usb_device_id *id_table)
207{
208 PADAPTER Adapter;
209 PWBLINUX pWbLinux;
210 PWBUSB pWbUsb;
211 struct usb_host_interface *interface;
212 struct usb_endpoint_descriptor *endpoint;
213 int i, ret = -1;
214 u32 ltmp;
215 struct usb_device *udev = interface_to_usbdev(intf);
216
217 usb_get_dev(udev);
218
219 printk("[w35und]wb35_probe ->\n");
220
221 do {
222 for (i=0; i<(sizeof(Id_Table)/sizeof(struct usb_device_id)); i++ ) {
223 if ((udev->descriptor.idVendor == Id_Table[i].idVendor) &&
224 (udev->descriptor.idProduct == Id_Table[i].idProduct)) {
225 printk("[w35und]Found supported hardware\n");
226 break;
227 }
228 }
229 if ((i == (sizeof(Id_Table)/sizeof(struct usb_device_id)))) {
230 #ifdef _PE_USB_INI_DUMP_
231 WBDEBUG(("[w35und] This is not the one we are interested about\n"));
232 #endif
233 return -ENODEV;
234 }
235
236 // 20060630.2 Check the device if it already be opened
237 ret = usb_control_msg(udev, usb_rcvctrlpipe( udev, 0 ),
238 0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN,
239 0x0, 0x400, &ltmp, 4, HZ*100 );
240 if( ret < 0 )
241 break;
242
243 ltmp = cpu_to_le32(ltmp);
244 if (ltmp) // Is already initialized?
245 break;
246
247
248 Adapter = kzalloc(sizeof(ADAPTER), GFP_KERNEL);
249
250 my_adapter = Adapter;
251 pWbLinux = &Adapter->WbLinux;
252 pWbUsb = &Adapter->sHwData.WbUsb;
253 pWbUsb->udev = udev;
254
255 interface = intf->cur_altsetting;
256 endpoint = &interface->endpoint[0].desc;
257
258 if (endpoint[2].wMaxPacketSize == 512) {
259 printk("[w35und] Working on USB 2.0\n");
260 pWbUsb->IsUsb20 = 1;
261 }
262
263 if (!WbWLanInitialize(Adapter)) {
264 printk("[w35und]WbWLanInitialize fail\n");
265 break;
266 }
267
268 {
269 struct wbsoft_priv *priv;
270 struct ieee80211_hw *dev;
271 int res;
272
273 dev = ieee80211_alloc_hw(sizeof(*priv), &wbsoft_ops);
274
275 if (!dev) {
276 printk("w35und: ieee80211 alloc failed\n" );
277 BUG();
278 }
279
280 my_dev = dev;
281
282 SET_IEEE80211_DEV(dev, &udev->dev);
283 {
284 phw_data_t pHwData = &Adapter->sHwData;
285 unsigned char dev_addr[MAX_ADDR_LEN];
286 hal_get_permanent_address(pHwData, dev_addr);
287 SET_IEEE80211_PERM_ADDR(dev, dev_addr);
288 }
289
290
291 dev->extra_tx_headroom = 12; /* FIXME */
292 dev->flags = 0;
293
294 dev->channel_change_time = 1000;
295// dev->max_rssi = 100;
296
297 dev->queues = 1;
298
299 static struct ieee80211_supported_band band;
300
301 band.channels = wbsoft_channels;
302 band.n_channels = ARRAY_SIZE(wbsoft_channels);
303 band.bitrates = wbsoft_rates;
304 band.n_bitrates = ARRAY_SIZE(wbsoft_rates);
305
306 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band;
307#if 0
308 wbsoft_modes[0].num_channels = 1;
309 wbsoft_modes[0].channels = wbsoft_channels;
310 wbsoft_modes[0].mode = MODE_IEEE80211B;
311 wbsoft_modes[0].num_rates = ARRAY_SIZE(wbsoft_rates);
312 wbsoft_modes[0].rates = wbsoft_rates;
313
314 res = ieee80211_register_hwmode(dev, &wbsoft_modes[0]);
315 BUG_ON(res);
316#endif
317
318 res = ieee80211_register_hw(dev);
319 BUG_ON(res);
320 }
321
322 usb_set_intfdata( intf, Adapter );
323
324 printk("[w35und] _probe OK\n");
325 return 0;
326
327 } while(FALSE);
328
329 return -ENOMEM;
330}
331
332void packet_came(char *pRxBufferAddress, int PacketSize)
333{
334 struct sk_buff *skb;
335 struct ieee80211_rx_status rx_status = {0};
336
337 if (!wbsoft_enabled)
338 return;
339
340 skb = dev_alloc_skb(PacketSize);
341 if (!skb) {
342 printk("Not enough memory for packet, FIXME\n");
343 return;
344 }
345
346 memcpy(skb_put(skb, PacketSize),
347 pRxBufferAddress,
348 PacketSize);
349
350/*
351 rx_status.rate = 10;
352 rx_status.channel = 1;
353 rx_status.freq = 12345;
354 rx_status.phymode = MODE_IEEE80211B;
355*/
356
357 ieee80211_rx_irqsafe(my_dev, skb, &rx_status);
358}
359
360unsigned char
361WbUsb_initial(phw_data_t pHwData)
362{
363 return 1;
364}
365
366
367void
368WbUsb_destroy(phw_data_t pHwData)
369{
370}
371
372int wb35_open(struct net_device *netdev)
373{
374 PADAPTER Adapter = (PADAPTER)netdev->priv;
375 phw_data_t pHwData = &Adapter->sHwData;
376
377 netif_start_queue(netdev);
378
379 //TODO : put here temporarily
380 hal_set_accept_broadcast(pHwData, 1); // open accept broadcast
381
382 return 0;
383}
384
385int wb35_close(struct net_device *netdev)
386{
387 netif_stop_queue(netdev);
388 return 0;
389}
390
391void wb35_disconnect(struct usb_interface *intf)
392{
393 PWBLINUX pWbLinux;
394 PADAPTER Adapter = usb_get_intfdata(intf);
395 usb_set_intfdata(intf, NULL);
396
397 pWbLinux = &Adapter->WbLinux;
398
399 // Card remove
400 WbWlanHalt(Adapter);
401
402}
403
404
diff --git a/drivers/staging/winbond/linux/wbusb_f.h b/drivers/staging/winbond/linux/wbusb_f.h
new file mode 100644
index 000000000000..cae29e107e11
--- /dev/null
+++ b/drivers/staging/winbond/linux/wbusb_f.h
@@ -0,0 +1,34 @@
1//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2// Copyright (c) 1996-2004 Winbond Electronic Corporation
3//
4// Module Name:
5// wbusb_f.h
6//
7// Abstract:
8// Linux driver.
9//
10// Author:
11//
12//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
13
14int wb35_open(struct net_device *netdev);
15int wb35_close(struct net_device *netdev);
16unsigned char WbUsb_initial(phw_data_t pHwData);
17void WbUsb_destroy(phw_data_t pHwData);
18unsigned char WbWLanInitialize(PADAPTER Adapter);
19#define WbUsb_Stop( _A )
20
21int wb35_probe(struct usb_interface *intf,const struct usb_device_id *id_table);
22void wb35_disconnect(struct usb_interface *intf);
23
24
25#define wb_usb_submit_urb(_A) usb_submit_urb(_A, GFP_ATOMIC)
26#define wb_usb_alloc_urb(_A) usb_alloc_urb(_A, GFP_ATOMIC)
27
28#define WbUsb_CheckForHang( _P )
29#define WbUsb_DetectStart( _P, _I )
30
31
32
33
34
diff --git a/drivers/staging/winbond/linux/wbusb_s.h b/drivers/staging/winbond/linux/wbusb_s.h
new file mode 100644
index 000000000000..d5c1d53de70b
--- /dev/null
+++ b/drivers/staging/winbond/linux/wbusb_s.h
@@ -0,0 +1,42 @@
1//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2// Copyright (c) 1996-2004 Winbond Electronic Corporation
3//
4// Module Name:
5// wbusb_s.h
6//
7// Abstract:
8// Linux driver.
9//
10// Author:
11//
12//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
13
14#define OS_SLEEP( _MT ) { set_current_state(TASK_INTERRUPTIBLE); \
15 schedule_timeout( _MT*HZ/1000000 ); }
16
17
18//---------------------------------------------------------------------------
19// RW_CONTEXT --
20//
21// Used to track driver-generated io irps
22//---------------------------------------------------------------------------
23typedef struct _RW_CONTEXT
24{
25 void* pHwData;
26 PURB pUrb;
27 void* pCallBackFunctionParameter;
28} RW_CONTEXT, *PRW_CONTEXT;
29
30
31
32
33#define DRIVER_AUTHOR "Original by: Jeff Lee<YY_Lee@issc.com.tw> Adapted to 2.6.x by Costantino Leandro (Rxart Desktop) <le_costantino@pixartargentina.com.ar>"
34#define DRIVER_DESC "IS89C35 802.11bg WLAN USB Driver"
35
36
37
38typedef struct _WBUSB {
39 u32 IsUsb20;
40 struct usb_device *udev;
41 u32 DetectCount;
42} WBUSB, *PWBUSB;
diff --git a/drivers/staging/winbond/localpara.h b/drivers/staging/winbond/localpara.h
new file mode 100644
index 000000000000..268cf916ab48
--- /dev/null
+++ b/drivers/staging/winbond/localpara.h
@@ -0,0 +1,275 @@
1//=============================================================
2// LocalPara.h -
3//=============================================================
4//Define the local ability
5
6#define LOCAL_DEFAULT_BEACON_PERIOD 100 //ms
7#define LOCAL_DEFAULT_ATIM_WINDOW 0
8#define LOCAL_DEFAULT_ERP_CAPABILITY 0x0431 //0x0001: ESS
9 //0x0010: Privacy
10 //0x0020: short preamble
11 //0x0400: short slot time
12#define LOCAL_DEFAULT_LISTEN_INTERVAL 5
13
14//#define LOCAL_DEFAULT_24_CHANNEL_NUM 11 // channel 1..11
15#define LOCAL_DEFAULT_24_CHANNEL_NUM 13 // channel 1..13
16#define LOCAL_DEFAULT_5_CHANNEL_NUM 8 // channel 36..64
17
18#define LOCAL_USA_24_CHANNEL_NUM 11
19#define LOCAL_USA_5_CHANNEL_NUM 12
20#define LOCAL_EUROPE_24_CHANNEL_NUM 13
21#define LOCAL_EUROPE_5_CHANNEL_NUM 19
22#define LOCAL_JAPAN_24_CHANNEL_NUM 14
23#define LOCAL_JAPAN_5_CHANNEL_NUM 11
24#define LOCAL_UNKNOWN_24_CHANNEL_NUM 14
25#define LOCAL_UNKNOWN_5_CHANNEL_NUM 34 //not include 165
26
27
28#define psLOCAL (&(Adapter->sLocalPara))
29
30#define MODE_802_11_BG 0
31#define MODE_802_11_A 1
32#define MODE_802_11_ABG 2
33#define MODE_802_11_BG_IBSS 3
34#define MODE_802_11_B 4
35#define MODE_AUTO 255
36
37#define BAND_TYPE_DSSS 0
38#define BAND_TYPE_OFDM_24 1
39#define BAND_TYPE_OFDM_5 2
40
41//refer Bitmap2RateValue table
42#define LOCAL_ALL_SUPPORTED_RATES_BITMAP 0x130c1a66 //the bitmap value of all the H/W supported rates
43 //1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54
44#define LOCAL_OFDM_SUPPORTED_RATES_BITMAP 0x130c1240 //the bitmap value of all the H/W supported rates
45 //except to non-OFDM rates
46 //6, 9, 12, 18, 24, 36, 48, 54
47
48#define LOCAL_11B_SUPPORTED_RATE_BITMAP 0x826
49#define LOCAL_11B_BASIC_RATE_BITMAP 0x826
50#define LOCAL_11B_OPERATION_RATE_BITMAP 0x826
51#define LOCAL_11G_BASIC_RATE_BITMAP 0x826 //1, 2, 5.5, 11
52#define LOCAL_11G_OPERATION_RATE_BITMAP 0x130c1240 //6, 9, 12, 18, 24, 36, 48, 54
53#define LOCAL_11A_BASIC_RATE_BITMAP 0x01001040 //6, 12, 24
54#define LOCAL_11A_OPERATION_RATE_BITMAP 0x120c0200 //9, 18, 36, 48, 54
55
56
57
58#define PWR_ACTIVE 0
59#define PWR_SAVE 1
60#define PWR_TX_IDLE_CYCLE 6
61
62//bPreambleMode and bSlotTimeMode
63#define AUTO_MODE 0
64#define LONG_MODE 1
65
66//Region definition
67#define REGION_AUTO 0xff
68#define REGION_UNKNOWN 0
69#define REGION_EUROPE 1 //ETSI
70#define REGION_JAPAN 2 //MKK
71#define REGION_USA 3 //FCC
72#define REGION_FRANCE 4 //FRANCE
73#define REGION_SPAIN 5 //SPAIN
74#define REGION_ISRAEL 6 //ISRAEL
75//#define REGION_CANADA 7 //IC
76
77#define MAX_BSS_DESCRIPT_ELEMENT 32
78#define MAX_PMKID_CandidateList 16
79
80//High byte : Event number, low byte : reason
81//Event definition
82//-- SME/MLME event
83#define EVENT_RCV_DEAUTH 0x0100
84#define EVENT_JOIN_FAIL 0x0200
85#define EVENT_AUTH_FAIL 0x0300
86#define EVENT_ASSOC_FAIL 0x0400
87#define EVENT_LOST_SIGNAL 0x0500
88#define EVENT_BSS_DESCRIPT_LACK 0x0600
89#define EVENT_COUNTERMEASURE 0x0700
90#define EVENT_JOIN_FILTER 0x0800
91//-- TX/RX event
92#define EVENT_RX_BUFF_UNAVAILABLE 0x4100
93
94#define EVENT_CONNECT 0x8100
95#define EVENT_DISCONNECT 0x8200
96#define EVENT_SCAN_REQ 0x8300
97
98//Reason of Event
99#define EVENT_REASON_FILTER_BASIC_RATE 0x0001
100#define EVENT_REASON_FILTER_PRIVACY 0x0002
101#define EVENT_REASON_FILTER_AUTH_MODE 0x0003
102#define EVENT_REASON_TIMEOUT 0x00ff
103
104// 20061108 WPS IE buffer
105#define MAX_IE_APPEND_SIZE 256 + 4 // Due to [E id][Length][OUI][Data] may 257 bytes
106
107typedef struct _EVENTLOG
108{
109 u16 Count; //Total count from start
110 u16 index; //Buffer index, 0 ~ 63
111 u32 EventValue[64]; //BYTE 3~2 : count, BYTE 1 : Event, BYTE 0 : reason
112} Event_Log, *pEvent_Log;
113
114typedef struct _ChanInfo
115{
116 u8 band;
117 u8 ChanNo;
118} ChanInfo, *pChanInfo;
119
120typedef struct _CHAN_LIST
121{
122 u16 Count;
123 ChanInfo Channel[50]; // 100B
124} CHAN_LIST, *psCHAN_LIST;
125
126typedef struct _RadioOff
127{
128 u8 boHwRadioOff;
129 u8 boSwRadioOff;
130} RadioOff, *psRadioOff;
131
132//===========================================================================
133typedef struct LOCAL_PARA
134{
135 u8 PermanentAddress[ MAC_ADDR_LENGTH + 2 ]; // read from EPROM, manufacture set for each NetCard
136 u8 ThisMacAddress[ MAC_ADDR_LENGTH + 2 ]; // the driver will use actually.
137
138 u32 MTUsize; // Ind to Uplayer, Max transmission unit size
139
140 u8 region_INF; //region setting from INF
141 u8 region; //real region setting of the device
142 u8 Reserved_1[2];
143
144 //// power-save variables
145 u8 iPowerSaveMode; // 0 indicates it is on, 1 indicates it is off
146 u8 ShutDowned;
147 u8 ATIMmode;
148 u8 ExcludeUnencrypted;
149
150 u16 CheckCountForPS; //Unit ime count for the decision to enter PS mode
151 u8 boHasTxActivity; //tx activity has occurred
152 u8 boMacPsValid; //Power save mode obtained from H/W is valid or not
153
154 //// Rate
155 u8 TxRateMode; // Initial, input from Registry, may be updated by GUI
156 //Tx Rate Mode: auto(DTO on), max, 1M, 2M, ..
157 u8 CurrentTxRate; // The current Tx rate
158 u8 CurrentTxRateForMng; // The current Tx rate for management frames
159 // It will be decided before connection succeeds.
160 u8 CurrentTxFallbackRate;
161
162 //for Rate handler
163 u8 BRateSet[32]; //basic rate set
164 u8 SRateSet[32]; //support rate set
165
166 u8 NumOfBRate;
167 u8 NumOfSRate;
168 u8 NumOfDsssRateInSRate; //number of DSSS rates in supported rate set
169 u8 reserved1;
170
171 u32 dwBasicRateBitmap; //bit map of basic rates
172 u32 dwSupportRateBitmap; //bit map of all support rates including
173 //basic and operational rates
174
175 ////For SME/MLME handler
176 u16 wOldSTAindex; // valid when boHandover=TRUE, store old connected STA index
177 u16 wConnectedSTAindex; // Index of peerly connected AP or IBSS in
178 // the descriptionset.
179 u16 Association_ID; // The Association ID in the (Re)Association
180 // Response frame.
181 u16 ListenInterval; // The listen interval when SME invoking MLME_
182 // (Re)Associate_Request().
183
184 RadioOff RadioOffStatus;
185 u8 Reserved0[2];
186
187 u8 boMsRadioOff; // Ndis demands to be true when set Disassoc. OID and be false when set SSID OID.
188 u8 boAntennaDiversity; //TRUE/ON or FALSE/OFF
189 u8 bAntennaNo; //which antenna
190 u8 bConnectFlag; //the connect status flag for roaming task
191
192 u8 RoamStatus;
193 u8 reserved7[3];
194
195 ChanInfo CurrentChan; //Current channel no. and channel band. It may be changed by scanning.
196 u8 boHandover; // Roaming, Hnadover to other AP.
197 u8 boCCAbusy;
198
199 u16 CWMax; // It may not be the real value that H/W used
200 u8 CWMin; // 255: set according to 802.11 spec.
201 u8 reserved2;
202
203 //11G:
204 u8 bMacOperationMode; // operation in 802.11b or 802.11g
205 u8 bSlotTimeMode; //AUTO, s32
206 u8 bPreambleMode; //AUTO, s32
207 u8 boNonERPpresent;
208
209 u8 boProtectMechanism; // H/W will take the necessary action based on this variable
210 u8 boShortPreamble; // H/W will take the necessary action based on this variable
211 u8 boShortSlotTime; // H/W will take the necessary action based on this variable
212 u8 reserved_3;
213
214 u32 RSN_IE_Bitmap; //added by WS
215 u32 RSN_OUI_Type; //added by WS
216
217 //For the BSSID
218 u8 HwBssid[MAC_ADDR_LENGTH + 2];
219 u32 HwBssidValid;
220
221 //For scan list
222 u8 BssListCount; //Total count of valid descriptor indexes
223 u8 boReceiveUncorrectInfo; //important settings in beacon/probe resp. have been changed
224 u8 NoOfJoinerInIbss;
225 u8 reserved_4;
226
227 u8 BssListIndex[ (MAX_BSS_DESCRIPT_ELEMENT+3) & ~0x03 ]; //Store the valid descriptor indexes obtained from scannings
228 u8 JoinerInIbss[ (MAX_BSS_DESCRIPT_ELEMENT+3) & ~0x03 ]; //save the BssDescriptor index in this
229 //IBSS. The index 0 is local descriptor
230 //(psLOCAL->wConnectedSTAindex).
231 //If CONNECTED : NoOfJoinerInIbss >=2
232 // else : NoOfJoinerInIbss <=1
233
234 //// General Statistics, count at Rx_handler or Tx_callback interrupt handler
235 u64 GS_XMIT_OK; // Good Frames Transmitted
236 u64 GS_RCV_OK; // Good Frames Received
237 u32 GS_RCV_ERROR; // Frames received with crc error
238 u32 GS_XMIT_ERROR; // Bad Frames Transmitted
239 u32 GS_RCV_NO_BUFFER; // Receive Buffer underrun
240 u32 GS_XMIT_ONE_COLLISION; // one collision
241 u32 GS_XMIT_MORE_COLLISIONS;// more collisions
242
243 //================================================================
244 // Statistics (no matter whether it had done successfully) -wkchen
245 //================================================================
246 u32 _NumRxMSDU;
247 u32 _NumTxMSDU;
248 u32 _dot11WEPExcludedCount;
249 u32 _dot11WEPUndecryptableCount;
250 u32 _dot11FrameDuplicateCount;
251
252 ChanInfo IbssChanSetting; // 2B. Start IBSS Channel setting by registry or WWU.
253 u8 reserved_5[2]; //It may not be used after considering RF type,
254 //region and modulation type.
255
256 CHAN_LIST sSupportChanList; // 86B. It will be obtained according to RF type and region
257 u8 reserved_6[2]; //two variables are for wep key error detection added by ws 02/02/04
258
259 u32 bWepKeyError;
260 u32 bToSelfPacketReceived;
261 u32 WepKeyDetectTimerCount;
262
263 Event_Log EventLog;
264
265 u16 SignalLostTh;
266 u16 SignalRoamTh;
267
268 // 20061108 WPS IE Append
269 u8 IE_Append_data[MAX_IE_APPEND_SIZE];
270 u16 IE_Append_size;
271 u16 reserved_7;
272
273} WB_LOCALDESCRIPT, *PWB_LOCALDESCRIPT;
274
275
diff --git a/drivers/staging/winbond/mac_structures.h b/drivers/staging/winbond/mac_structures.h
new file mode 100644
index 000000000000..031d2cb6cd63
--- /dev/null
+++ b/drivers/staging/winbond/mac_structures.h
@@ -0,0 +1,670 @@
1//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2// MAC_Structures.h
3//
4// This file contains the definitions and data structures used by SW-MAC.
5//
6// Revision Histoy
7//=================
8// 0.1 2002 UN00
9// 0.2 20021004 PD43 CCLiu6
10// 20021018 PD43 CCLiu6
11// Add enum_TxRate type
12// Modify enum_STAState type
13// 0.3 20021023 PE23 CYLiu update MAC session struct
14// 20021108
15// 20021122 PD43 Austin
16// Deleted some unused.
17// 20021129 PD43 Austin
18// 20030617 increase the 802.11g definition
19//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
20
21#ifndef _MAC_Structures_H_
22#define _MAC_Structures_H_
23
24
25//=========================================================
26// Some miscellaneous definitions
27//-----
28#define MAX_CHANNELS 30
29#define MAC_ADDR_LENGTH 6
30#define MAX_WEP_KEY_SIZE 16 // 128 bits
31#define MAX_802_11_FRAGMENT_NUMBER 10 // By spec
32
33//========================================================
34// 802.11 Frame define
35//-----
36#define MASK_PROTOCOL_VERSION_TYPE 0x0F
37#define MASK_FRAGMENT_NUMBER 0x000F
38#define SEQUENCE_NUMBER_SHIFT 4
39#define DIFFER_11_TO_3 18
40#define DOT_11_MAC_HEADER_SIZE 24
41#define DOT_11_SNAP_SIZE 6
42#define DOT_11_DURATION_OFFSET 2
43#define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset
44#define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame//
45#define DOT_11_DATA_OFFSET 24
46#define DOT_11_DA_OFFSET 4
47#define DOT_3_TYPE_ARP 0x80F3
48#define DOT_3_TYPE_IPX 0x8137
49#define DOT_3_TYPE_OFFSET 12
50
51
52#define ETHERNET_HEADER_SIZE 14
53#define MAX_ETHERNET_PACKET_SIZE 1514
54
55
56//----- management : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
57#define MAC_SUBTYPE_MNGMNT_ASSOC_REQUEST 0x00
58#define MAC_SUBTYPE_MNGMNT_ASSOC_RESPONSE 0x10
59#define MAC_SUBTYPE_MNGMNT_REASSOC_REQUEST 0x20
60#define MAC_SUBTYPE_MNGMNT_REASSOC_RESPONSE 0x30
61#define MAC_SUBTYPE_MNGMNT_PROBE_REQUEST 0x40
62#define MAC_SUBTYPE_MNGMNT_PROBE_RESPONSE 0x50
63#define MAC_SUBTYPE_MNGMNT_BEACON 0x80
64#define MAC_SUBTYPE_MNGMNT_ATIM 0x90
65#define MAC_SUBTYPE_MNGMNT_DISASSOCIATION 0xA0
66#define MAC_SUBTYPE_MNGMNT_AUTHENTICATION 0xB0
67#define MAC_SUBTYPE_MNGMNT_DEAUTHENTICATION 0xC0
68
69//----- control : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
70#define MAC_SUBTYPE_CONTROL_PSPOLL 0xA4
71#define MAC_SUBTYPE_CONTROL_RTS 0xB4
72#define MAC_SUBTYPE_CONTROL_CTS 0xC4
73#define MAC_SUBTYPE_CONTROL_ACK 0xD4
74#define MAC_SUBTYPE_CONTROL_CFEND 0xE4
75#define MAC_SUBTYPE_CONTROL_CFEND_CFACK 0xF4
76
77//----- data : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
78#define MAC_SUBTYPE_DATA 0x08
79#define MAC_SUBTYPE_DATA_CFACK 0x18
80#define MAC_SUBTYPE_DATA_CFPOLL 0x28
81#define MAC_SUBTYPE_DATA_CFACK_CFPOLL 0x38
82#define MAC_SUBTYPE_DATA_NULL 0x48
83#define MAC_SUBTYPE_DATA_CFACK_NULL 0x58
84#define MAC_SUBTYPE_DATA_CFPOLL_NULL 0x68
85#define MAC_SUBTYPE_DATA_CFACK_CFPOLL_NULL 0x78
86
87//----- Frame Type of Bits (2, 3)
88#define MAC_TYPE_MANAGEMENT 0x00
89#define MAC_TYPE_CONTROL 0x04
90#define MAC_TYPE_DATA 0x08
91
92//----- definitions for Management Frame Element ID (1 BYTE)
93#define ELEMENT_ID_SSID 0
94#define ELEMENT_ID_SUPPORTED_RATES 1
95#define ELEMENT_ID_FH_PARAMETER_SET 2
96#define ELEMENT_ID_DS_PARAMETER_SET 3
97#define ELEMENT_ID_CF_PARAMETER_SET 4
98#define ELEMENT_ID_TIM 5
99#define ELEMENT_ID_IBSS_PARAMETER_SET 6
100// 7~15 reserverd
101#define ELEMENT_ID_CHALLENGE_TEXT 16
102// 17~31 reserved for challenge text extension
103// 32~255 reserved
104//-- 11G --
105#define ELEMENT_ID_ERP_INFORMATION 42
106#define ELEMENT_ID_EXTENDED_SUPPORTED_RATES 50
107
108//-- WPA --
109
110#define ELEMENT_ID_RSN_WPA 221
111#ifdef _WPA2_
112#define ELEMENT_ID_RSN_WPA2 48
113#endif //endif WPA2
114
115#define WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT ((u16) 6)
116#define WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT ((u16) 2)
117
118#ifdef WB_LINUX
119#define UNALIGNED
120#endif
121
122//========================================================
123typedef enum enum_PowerManagementMode
124{
125 ACTIVE = 0,
126 POWER_SAVE
127} WB_PM_Mode, *PWB_PM_MODE;
128
129//===================================================================
130// Reason Code (Table 18): indicate the reason of DisAssoc, DeAuthen
131// length of ReasonCode is 2 Octs.
132//===================================================================
133#define REASON_REASERED 0
134#define REASON_UNSPECIDIED 1
135#define REASON_PREAUTH_INVALID 2
136#define DEAUTH_REASON_LEFT_BSS 3
137#define DISASS_REASON_AP_INACTIVE 4
138#define DISASS_REASON_AP_BUSY 5
139#define REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
140#define REASON_CLASS3_FRAME_FROM_NONASSO_STA 7
141#define DISASS_REASON_LEFT_BSS 8
142#define REASON_NOT_AUTH_YET 9
143//802.11i define
144#define REASON_INVALID_IE 13
145#define REASON_MIC_ERROR 14
146#define REASON_4WAY_HANDSHAKE_TIMEOUT 15
147#define REASON_GROUPKEY_UPDATE_TIMEOUT 16
148#define REASON_IE_DIFF_4WAY_ASSOC 17
149#define REASON_INVALID_MULTICAST_CIPHER 18
150#define REASON_INVALID_UNICAST_CIPHER 19
151#define REASON_INVALID_AKMP 20
152#define REASON_UNSUPPORTED_RSNIE_VERSION 21
153#define REASON_INVALID_RSNIE_CAPABILITY 22
154#define REASON_802_1X_AUTH_FAIL 23
155#define REASON_CIPHER_REJECT_PER_SEC_POLICY 14
156
157/*
158//===========================================================
159// enum_MMPDUResultCode --
160// Status code (2 Octs) in the MMPDU's frame body. Table.19
161//
162//===========================================================
163enum enum_MMPDUResultCode
164{
165// SUCCESS = 0, // Redefined
166 UNSPECIFIED_FAILURE = 1,
167
168 // 2 - 9 Reserved
169
170 NOT_SUPPROT_CAPABILITIES = 10,
171
172 //REASSOCIATION_DENIED
173 //
174 REASSOC_DENIED_UNABLE_CFM_ASSOC_EXIST = 11,
175
176 //ASSOCIATION_DENIED_NOT_IN_STANDARD
177 //
178 ASSOC_DENIED_REASON_NOT_IN_STANDARD = 12,
179 PEER_NOT_SUPPORT_AUTH_ALGORITHM = 13,
180 AUTH_SEQNUM_OUT_OF_EXPECT = 14,
181 AUTH_REJECT_REASON_CHALLENGE_FAIL = 15,
182 AUTH_REJECT_REASON_WAIT_TIMEOUT = 16,
183 ASSOC_DENIED_REASON_AP_BUSY = 17,
184 ASSOC_DENIED_REASON_NOT_SUPPORT_BASIC_RATE = 18
185} WB_MMPDURESULTCODE, *PWB_MMPDURESULTCODE;
186*/
187
188//===========================================================
189// enum_TxRate --
190// Define the transmission constants based on W89C32 MAC
191// target specification.
192//===========================================================
193typedef enum enum_TxRate
194{
195 TXRATE_1M = 0,
196 TXRATE_2MLONG = 2,
197 TXRATE_2MSHORT = 3,
198 TXRATE_55MLONG = 4,
199 TXRATE_55MSHORT = 5,
200 TXRATE_11MLONG = 6,
201 TXRATE_11MSHORT = 7,
202 TXRATE_AUTO = 255 // PD43 20021108
203} WB_TXRATE, *PWB_TXRATE;
204
205
206#define RATE_BITMAP_1M 1
207#define RATE_BITMAP_2M 2
208#define RATE_BITMAP_5dot5M 5
209#define RATE_BITMAP_6M 6
210#define RATE_BITMAP_9M 9
211#define RATE_BITMAP_11M 11
212#define RATE_BITMAP_12M 12
213#define RATE_BITMAP_18M 18
214#define RATE_BITMAP_22M 22
215#define RATE_BITMAP_24M 24
216#define RATE_BITMAP_33M 17
217#define RATE_BITMAP_36M 19
218#define RATE_BITMAP_48M 25
219#define RATE_BITMAP_54M 28
220
221#define RATE_AUTO 0
222#define RATE_1M 2
223#define RATE_2M 4
224#define RATE_5dot5M 11
225#define RATE_6M 12
226#define RATE_9M 18
227#define RATE_11M 22
228#define RATE_12M 24
229#define RATE_18M 36
230#define RATE_22M 44
231#define RATE_24M 48
232#define RATE_33M 66
233#define RATE_36M 72
234#define RATE_48M 96
235#define RATE_54M 108
236#define RATE_MAX 255
237
238//CAPABILITY
239#define CAPABILITY_ESS_BIT 0x0001
240#define CAPABILITY_IBSS_BIT 0x0002
241#define CAPABILITY_CF_POLL_BIT 0x0004
242#define CAPABILITY_CF_POLL_REQ_BIT 0x0008
243#define CAPABILITY_PRIVACY_BIT 0x0010
244#define CAPABILITY_SHORT_PREAMBLE_BIT 0x0020
245#define CAPABILITY_PBCC_BIT 0x0040
246#define CAPABILITY_CHAN_AGILITY_BIT 0x0080
247#define CAPABILITY_SHORT_SLOT_TIME_BIT 0x0400
248#define CAPABILITY_DSSS_OFDM_BIT 0x2000
249
250
251struct Capability_Information_Element
252{
253 union
254 {
255 u16 __attribute__ ((packed)) wValue;
256 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
257 struct _Capability
258 {
259 //-- 11G --
260 u8 Reserved3 : 2;
261 u8 DSSS_OFDM : 1;
262 u8 Reserved2 : 2;
263 u8 Short_Slot_Time : 1;
264 u8 Reserved1 : 2;
265 u8 Channel_Agility : 1;
266 u8 PBCC : 1;
267 u8 ShortPreamble : 1;
268 u8 CF_Privacy : 1;
269 u8 CF_Poll_Request : 1;
270 u8 CF_Pollable : 1;
271 u8 IBSS : 1;
272 u8 ESS : 1;
273 } __attribute__ ((packed)) Capability;
274 #else
275 struct _Capability
276 {
277 u8 ESS : 1;
278 u8 IBSS : 1;
279 u8 CF_Pollable : 1;
280 u8 CF_Poll_Request : 1;
281 u8 CF_Privacy : 1;
282 u8 ShortPreamble : 1;
283 u8 PBCC : 1;
284 u8 Channel_Agility : 1;
285 u8 Reserved1 : 2;
286 //-- 11G --
287 u8 Short_Slot_Time : 1;
288 u8 Reserved2 : 2;
289 u8 DSSS_OFDM : 1;
290 u8 Reserved3 : 2;
291 } __attribute__ ((packed)) Capability;
292 #endif
293 }__attribute__ ((packed)) ;
294}__attribute__ ((packed));
295
296struct FH_Parameter_Set_Element
297{
298 u8 Element_ID;
299 u8 Length;
300 u8 Dwell_Time[2];
301 u8 Hop_Set;
302 u8 Hop_Pattern;
303 u8 Hop_Index;
304};
305
306struct DS_Parameter_Set_Element
307{
308 u8 Element_ID;
309 u8 Length;
310 u8 Current_Channel;
311};
312
313struct Supported_Rates_Element
314{
315 u8 Element_ID;
316 u8 Length;
317 u8 SupportedRates[8];
318}__attribute__ ((packed));
319
320struct SSID_Element
321{
322 u8 Element_ID;
323 u8 Length;
324 u8 SSID[32];
325}__attribute__ ((packed)) ;
326
327struct CF_Parameter_Set_Element
328{
329 u8 Element_ID;
330 u8 Length;
331 u8 CFP_Count;
332 u8 CFP_Period;
333 u8 CFP_MaxDuration[2]; // in Time Units
334 u8 CFP_DurRemaining[2]; // in time units
335};
336
337struct TIM_Element
338{
339 u8 Element_ID;
340 u8 Length;
341 u8 DTIM_Count;
342 u8 DTIM_Period;
343 u8 Bitmap_Control;
344 u8 Partial_Virtual_Bitmap[251];
345};
346
347struct IBSS_Parameter_Set_Element
348{
349 u8 Element_ID;
350 u8 Length;
351 u8 ATIM_Window[2];
352};
353
354struct Challenge_Text_Element
355{
356 u8 Element_ID;
357 u8 Length;
358 u8 Challenge_Text[253];
359};
360
361struct PHY_Parameter_Set_Element
362{
363// int aSlotTime;
364// int aSifsTime;
365 s32 aCCATime;
366 s32 aRxTxTurnaroundTime;
367 s32 aTxPLCPDelay;
368 s32 RxPLCPDelay;
369 s32 aRxTxSwitchTime;
370 s32 aTxRampOntime;
371 s32 aTxRampOffTime;
372 s32 aTxRFDelay;
373 s32 aRxRFDelay;
374 s32 aAirPropagationTime;
375 s32 aMACProcessingDelay;
376 s32 aPreambleLength;
377 s32 aPLCPHeaderLength;
378 s32 aMPDUDurationFactor;
379 s32 aMPDUMaxLength;
380// int aCWmin;
381// int aCWmax;
382};
383
384//-- 11G --
385struct ERP_Information_Element
386{
387 u8 Element_ID;
388 u8 Length;
389 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
390 u8 Reserved:5; //20060926 add by anson
391 u8 Barker_Preamble_Mode:1;
392 u8 Use_Protection:1;
393 u8 NonERP_Present:1;
394 #else
395 u8 NonERP_Present:1;
396 u8 Use_Protection:1;
397 u8 Barker_Preamble_Mode:1;
398 u8 Reserved:5;
399 #endif
400};
401
402struct Extended_Supported_Rates_Element
403{
404 u8 Element_ID;
405 u8 Length;
406 u8 ExtendedSupportedRates[255];
407}__attribute__ ((packed));
408
409//WPA(802.11i draft 3.0)
410#define VERSION_WPA 1
411#ifdef _WPA2_
412#define VERSION_WPA2 1
413#endif //end def _WPA2_
414#define OUI_WPA 0x00F25000 //WPA2.0 OUI=00:50:F2, the MSB is reserved for suite type
415#ifdef _WPA2_
416#define OUI_WPA2 0x00AC0F00 // for wpa2 change to 0x00ACOF04 by Ws 26/04/04
417#endif //end def _WPA2_
418
419#define OUI_WPA_ADDITIONAL 0x01
420#define WLAN_MIN_RSN_WPA_LENGTH 6 //added by ws 09/10/04
421#ifdef _WPA2_
422#define WLAN_MIN_RSN_WPA2_LENGTH 2 // Fix to 2 09/14/05
423#endif //end def _WPA2_
424
425#define oui_wpa (u32)(OUI_WPA|OUI_WPA_ADDITIONAL)
426
427#define WPA_OUI_BIG ((u32) 0x01F25000)//added by ws 09/23/04
428#define WPA_OUI_LITTLE ((u32) 0x01F25001)//added by ws 09/23/04
429
430#define WPA_WPS_OUI cpu_to_le32(0x04F25000) // 20061108 For WPS. It's little endian. Big endian is 0x0050F204
431
432//-----WPA2-----
433#ifdef _WPA2_
434#define WPA2_OUI_BIG ((u32)0x01AC0F00)
435#define WPA2_OUI_LITTLE ((u32)0x01AC0F01)
436#endif //end def _WPA2_
437
438//Authentication suite
439#define OUI_AUTH_WPA_NONE 0x00 //for WPA_NONE
440#define OUI_AUTH_8021X 0x01
441#define OUI_AUTH_PSK 0x02
442//Cipher suite
443#define OUI_CIPHER_GROUP_KEY 0x00 //added by ws 05/21/04
444#define OUI_CIPHER_WEP_40 0x01
445#define OUI_CIPHER_TKIP 0x02
446#define OUI_CIPHER_CCMP 0x04
447#define OUI_CIPHER_WEP_104 0x05
448
449typedef struct _SUITE_SELECTOR_
450{
451 union
452 {
453 u8 Value[4];
454 struct _SUIT_
455 {
456 u8 OUI[3];
457 u8 Type;
458 }SuitSelector;
459 };
460}SUITE_SELECTOR;
461
462//-- WPA --
463struct RSN_Information_Element
464{
465 u8 Element_ID;
466 u8 Length;
467 UNALIGNED SUITE_SELECTOR OuiWPAAdditional;//WPA version 2.0 additional field, and should be 00:50:F2:01
468 u16 Version;
469 SUITE_SELECTOR GroupKeySuite;
470 u16 PairwiseKeySuiteCount;
471 SUITE_SELECTOR PairwiseKeySuite[1];
472}__attribute__ ((packed));
473struct RSN_Auth_Sub_Information_Element
474{
475 u16 AuthKeyMngtSuiteCount;
476 SUITE_SELECTOR AuthKeyMngtSuite[1];
477}__attribute__ ((packed));
478
479//-- WPA2 --
480struct RSN_Capability_Element
481{
482 union
483 {
484 u16 __attribute__ ((packed)) wValue;
485 #ifdef _BIG_ENDIAN_ //20060927 add by anson's endian
486 struct _RSN_Capability
487 {
488 u16 __attribute__ ((packed)) Reserved2 : 8; // 20051201
489 u16 __attribute__ ((packed)) Reserved1 : 2;
490 u16 __attribute__ ((packed)) GTK_Replay_Counter : 2;
491 u16 __attribute__ ((packed)) PTK_Replay_Counter : 2;
492 u16 __attribute__ ((packed)) No_Pairwise : 1;
493 u16 __attribute__ ((packed)) Pre_Auth : 1;
494 }__attribute__ ((packed)) RSN_Capability;
495 #else
496 struct _RSN_Capability
497 {
498 u16 __attribute__ ((packed)) Pre_Auth : 1;
499 u16 __attribute__ ((packed)) No_Pairwise : 1;
500 u16 __attribute__ ((packed)) PTK_Replay_Counter : 2;
501 u16 __attribute__ ((packed)) GTK_Replay_Counter : 2;
502 u16 __attribute__ ((packed)) Reserved1 : 2;
503 u16 __attribute__ ((packed)) Reserved2 : 8; // 20051201
504 }__attribute__ ((packed)) RSN_Capability;
505 #endif
506
507 }__attribute__ ((packed)) ;
508}__attribute__ ((packed)) ;
509
510#ifdef _WPA2_
511typedef struct _PMKID
512{
513 u8 pValue[16];
514}PMKID;
515
516struct WPA2_RSN_Information_Element
517{
518 u8 Element_ID;
519 u8 Length;
520 u16 Version;
521 SUITE_SELECTOR GroupKeySuite;
522 u16 PairwiseKeySuiteCount;
523 SUITE_SELECTOR PairwiseKeySuite[1];
524
525}__attribute__ ((packed));
526
527struct WPA2_RSN_Auth_Sub_Information_Element
528{
529 u16 AuthKeyMngtSuiteCount;
530 SUITE_SELECTOR AuthKeyMngtSuite[1];
531}__attribute__ ((packed));
532
533
534struct PMKID_Information_Element
535{
536 u16 PMKID_Count;
537 PMKID pmkid [16] ;
538}__attribute__ ((packed));
539
540#endif //enddef _WPA2_
541//============================================================
542// MAC Frame structure (different type) and subfield structure
543//============================================================
544struct MAC_frame_control
545{
546 u8 mac_frame_info; // a combination of the [Protocol Version, Control Type, Control Subtype]
547 #ifdef _BIG_ENDIAN_ //20060927 add by anson's endian
548 u8 order:1;
549 u8 WEP:1;
550 u8 more_data:1;
551 u8 pwr_mgt:1;
552 u8 retry:1;
553 u8 more_frag:1;
554 u8 from_ds:1;
555 u8 to_ds:1;
556 #else
557 u8 to_ds:1;
558 u8 from_ds:1;
559 u8 more_frag:1;
560 u8 retry:1;
561 u8 pwr_mgt:1;
562 u8 more_data:1;
563 u8 WEP:1;
564 u8 order:1;
565 #endif
566} __attribute__ ((packed));
567
568struct Management_Frame {
569 struct MAC_frame_control frame_control; // 2B, ToDS,FromDS,MoreFrag,MoreData,Order=0
570 u16 duration;
571 u8 DA[MAC_ADDR_LENGTH]; // Addr1
572 u8 SA[MAC_ADDR_LENGTH]; // Addr2
573 u8 BSSID[MAC_ADDR_LENGTH]; // Addr3
574 u16 Sequence_Control;
575 // Management Frame Body <= 325 bytes
576 // FCS 4 bytes
577}__attribute__ ((packed));
578
579// SW-MAC don't Tx/Rx Control-Frame, HW-MAC do it.
580struct Control_Frame {
581 struct MAC_frame_control frame_control; // ToDS,FromDS,MoreFrag,Retry,MoreData,WEP,Order=0
582 u16 duration;
583 u8 RA[MAC_ADDR_LENGTH];
584 u8 TA[MAC_ADDR_LENGTH];
585 u16 FCS;
586}__attribute__ ((packed));
587
588struct Data_Frame {
589 struct MAC_frame_control frame_control;
590 u16 duration;
591 u8 Addr1[MAC_ADDR_LENGTH];
592 u8 Addr2[MAC_ADDR_LENGTH];
593 u8 Addr3[MAC_ADDR_LENGTH];
594 u16 Sequence_Control;
595 u8 Addr4[MAC_ADDR_LENGTH]; // only exist when ToDS=FromDS=1
596 // Data Frame Body <= 2312
597 // FCS
598}__attribute__ ((packed));
599
600struct Disassociation_Frame_Body
601{
602 u16 reasonCode;
603}__attribute__ ((packed));
604
605struct Association_Request_Frame_Body
606{
607 u16 capability_information;
608 u16 listenInterval;
609 u8 Current_AP_Address[MAC_ADDR_LENGTH];//for reassociation only
610 // SSID (2+32 bytes)
611 // Supported_Rates (2+8 bytes)
612}__attribute__ ((packed));
613
614struct Association_Response_Frame_Body
615{
616 u16 capability_information;
617 u16 statusCode;
618 u16 Association_ID;
619 struct Supported_Rates_Element supportedRates;
620}__attribute__ ((packed));
621
622/*struct Reassociation_Request_Frame_Body
623{
624 u16 capability_information;
625 u16 listenInterval;
626 u8 Current_AP_Address[MAC_ADDR_LENGTH];
627 // SSID (2+32 bytes)
628 // Supported_Rates (2+8 bytes)
629};*/
630// eliminated by WS 07/22/04 comboined with associateion request frame.
631
632struct Reassociation_Response_Frame_Body
633{
634 u16 capability_information;
635 u16 statusCode;
636 u16 Association_ID;
637 struct Supported_Rates_Element supportedRates;
638}__attribute__ ((packed));
639
640struct Deauthentication_Frame_Body
641{
642 u16 reasonCode;
643}__attribute__ ((packed));
644
645
646struct Probe_Response_Frame_Body
647{
648 u16 Timestamp;
649 u16 Beacon_Interval;
650 u16 Capability_Information;
651 // SSID
652 // Supported_Rates
653 // PHY parameter Set (DS Parameters)
654 // CF parameter Set
655 // IBSS parameter Set
656}__attribute__ ((packed));
657
658struct Authentication_Frame_Body
659{
660 u16 algorithmNumber;
661 u16 sequenceNumber;
662 u16 statusCode;
663 // NB: don't include ChallengeText in this structure
664 // struct Challenge_Text_Element sChallengeTextElement; // wkchen added
665}__attribute__ ((packed));
666
667
668#endif // _MAC_Structure_H_
669
670
diff --git a/drivers/staging/winbond/mds.c b/drivers/staging/winbond/mds.c
new file mode 100644
index 000000000000..8ce6389c4135
--- /dev/null
+++ b/drivers/staging/winbond/mds.c
@@ -0,0 +1,630 @@
1#include "os_common.h"
2
3void
4Mds_reset_descriptor(PADAPTER Adapter)
5{
6 PMDS pMds = &Adapter->Mds;
7
8 pMds->TxPause = 0;
9 pMds->TxThreadCount = 0;
10 pMds->TxFillIndex = 0;
11 pMds->TxDesIndex = 0;
12 pMds->ScanTxPause = 0;
13 memset(pMds->TxOwner, 0, ((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03));
14}
15
16unsigned char
17Mds_initial(PADAPTER Adapter)
18{
19 PMDS pMds = &Adapter->Mds;
20
21 pMds->TxPause = FALSE;
22 pMds->TxRTSThreshold = DEFAULT_RTSThreshold;
23 pMds->TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD;
24
25 vRxTimerInit(Adapter);//for WPA countermeasure
26
27 return hal_get_tx_buffer( &Adapter->sHwData, &pMds->pTxBuffer );
28}
29
30void
31Mds_Destroy(PADAPTER Adapter)
32{
33 vRxTimerStop(Adapter);
34}
35
36void
37Mds_Tx(PADAPTER Adapter)
38{
39 phw_data_t pHwData = &Adapter->sHwData;
40 PMDS pMds = &Adapter->Mds;
41 DESCRIPTOR TxDes;
42 PDESCRIPTOR pTxDes = &TxDes;
43 PUCHAR XmitBufAddress;
44 u16 XmitBufSize, PacketSize, stmp, CurrentSize, FragmentThreshold;
45 u8 FillIndex, TxDesIndex, FragmentCount, FillCount;
46 unsigned char BufferFilled = FALSE, MICAdd = 0;
47
48
49 if (pMds->TxPause)
50 return;
51 if (!hal_driver_init_OK(pHwData))
52 return;
53
54 //Only one thread can be run here
55 if (!OS_ATOMIC_INC( Adapter, &pMds->TxThreadCount) == 1)
56 goto cleanup;
57
58 // Start to fill the data
59 do {
60 FillIndex = pMds->TxFillIndex;
61 if (pMds->TxOwner[FillIndex]) { // Is owned by software 0:Yes 1:No
62#ifdef _PE_TX_DUMP_
63 WBDEBUG(("[Mds_Tx] Tx Owner is H/W.\n"));
64#endif
65 break;
66 }
67
68 XmitBufAddress = pMds->pTxBuffer + (MAX_USB_TX_BUFFER * FillIndex); //Get buffer
69 XmitBufSize = 0;
70 FillCount = 0;
71 do {
72 PacketSize = Adapter->sMlmeFrame.len;
73 if (!PacketSize)
74 break;
75
76 //For Check the buffer resource
77 FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD;
78 //931130.5.b
79 FragmentCount = PacketSize/FragmentThreshold + 1;
80 stmp = PacketSize + FragmentCount*32 + 8;//931130.5.c 8:MIC
81 if ((XmitBufSize + stmp) >= MAX_USB_TX_BUFFER) {
82 printk("[Mds_Tx] Excess max tx buffer.\n");
83 break; // buffer is not enough
84 }
85
86
87 //
88 // Start transmitting
89 //
90 BufferFilled = TRUE;
91
92 /* Leaves first u8 intact */
93 memset((PUCHAR)pTxDes + 1, 0, sizeof(DESCRIPTOR) - 1);
94
95 TxDesIndex = pMds->TxDesIndex;//Get the current ID
96 pTxDes->Descriptor_ID = TxDesIndex;
97 pMds->TxDesFrom[ TxDesIndex ] = 2;//Storing the information of source comming from
98 pMds->TxDesIndex++;
99 pMds->TxDesIndex %= MAX_USB_TX_DESCRIPTOR;
100
101 MLME_GetNextPacket( Adapter, pTxDes );
102
103 // Copy header. 8byte USB + 24byte 802.11Hdr. Set TxRate, Preamble type
104 Mds_HeaderCopy( Adapter, pTxDes, XmitBufAddress );
105
106 // For speed up Key setting
107 if (pTxDes->EapFix) {
108#ifdef _PE_TX_DUMP_
109 WBDEBUG(("35: EPA 4th frame detected. Size = %d\n", PacketSize));
110#endif
111 pHwData->IsKeyPreSet = 1;
112 }
113
114 // Copy (fragment) frame body, and set USB, 802.11 hdr flag
115 CurrentSize = Mds_BodyCopy(Adapter, pTxDes, XmitBufAddress);
116
117 // Set RTS/CTS and Normal duration field into buffer
118 Mds_DurationSet(Adapter, pTxDes, XmitBufAddress);
119
120 //
121 // Calculation MIC from buffer which maybe fragment, then fill into temporary address 8 byte
122 // 931130.5.e
123 if (MICAdd)
124 Mds_MicFill( Adapter, pTxDes, XmitBufAddress );
125
126 //Shift to the next address
127 XmitBufSize += CurrentSize;
128 XmitBufAddress += CurrentSize;
129
130#ifdef _IBSS_BEACON_SEQ_STICK_
131 if ((XmitBufAddress[ DOT_11_DA_OFFSET+8 ] & 0xfc) != MAC_SUBTYPE_MNGMNT_PROBE_REQUEST) // +8 for USB hdr
132#endif
133 pMds->TxToggle = TRUE;
134
135 // Get packet to transmit completed, 1:TESTSTA 2:MLME 3: Ndis data
136 MLME_SendComplete(Adapter, 0, TRUE);
137
138 // Software TSC count 20060214
139 pMds->TxTsc++;
140 if (pMds->TxTsc == 0)
141 pMds->TxTsc_2++;
142
143 FillCount++; // 20060928
144 } while (HAL_USB_MODE_BURST(pHwData)); // End of multiple MSDU copy loop. FALSE = single TRUE = multiple sending
145
146 // Move to the next one, if necessary
147 if (BufferFilled) {
148 // size setting
149 pMds->TxBufferSize[ FillIndex ] = XmitBufSize;
150
151 // 20060928 set Tx count
152 pMds->TxCountInBuffer[FillIndex] = FillCount;
153
154 // Set owner flag
155 pMds->TxOwner[FillIndex] = 1;
156
157 pMds->TxFillIndex++;
158 pMds->TxFillIndex %= MAX_USB_TX_BUFFER_NUMBER;
159 BufferFilled = FALSE;
160 } else
161 break;
162
163 if (!PacketSize) // No more pk for transmitting
164 break;
165
166 } while(TRUE);
167
168 //
169 // Start to send by lower module
170 //
171 if (!pHwData->IsKeyPreSet)
172 Wb35Tx_start(pHwData);
173
174 cleanup:
175 OS_ATOMIC_DEC( Adapter, &pMds->TxThreadCount );
176}
177
178void
179Mds_SendComplete(PADAPTER Adapter, PT02_DESCRIPTOR pT02)
180{
181 PMDS pMds = &Adapter->Mds;
182 phw_data_t pHwData = &Adapter->sHwData;
183 u8 PacketId = (u8)pT02->T02_Tx_PktID;
184 unsigned char SendOK = TRUE;
185 u8 RetryCount, TxRate;
186
187 if (pT02->T02_IgnoreResult) // Don't care the result
188 return;
189 if (pT02->T02_IsLastMpdu) {
190 //TODO: DTO -- get the retry count and fragment count
191 // Tx rate
192 TxRate = pMds->TxRate[ PacketId ][ 0 ];
193 RetryCount = (u8)pT02->T02_MPDU_Cnt;
194 if (pT02->value & FLAG_ERROR_TX_MASK) {
195 SendOK = FALSE;
196
197 if (pT02->T02_transmit_abort || pT02->T02_out_of_MaxTxMSDULiftTime) {
198 //retry error
199 pHwData->dto_tx_retry_count += (RetryCount+1);
200 //[for tx debug]
201 if (RetryCount<7)
202 pHwData->tx_retry_count[RetryCount] += RetryCount;
203 else
204 pHwData->tx_retry_count[7] += RetryCount;
205 #ifdef _PE_STATE_DUMP_
206 WBDEBUG(("dto_tx_retry_count =%d\n", pHwData->dto_tx_retry_count));
207 #endif
208 MTO_SetTxCount(Adapter, TxRate, RetryCount);
209 }
210 pHwData->dto_tx_frag_count += (RetryCount+1);
211
212 //[for tx debug]
213 if (pT02->T02_transmit_abort_due_to_TBTT)
214 pHwData->tx_TBTT_start_count++;
215 if (pT02->T02_transmit_without_encryption_due_to_wep_on_false)
216 pHwData->tx_WepOn_false_count++;
217 if (pT02->T02_discard_due_to_null_wep_key)
218 pHwData->tx_Null_key_count++;
219 } else {
220 if (pT02->T02_effective_transmission_rate)
221 pHwData->tx_ETR_count++;
222 MTO_SetTxCount(Adapter, TxRate, RetryCount);
223 }
224
225 // Clear send result buffer
226 pMds->TxResult[ PacketId ] = 0;
227 } else
228 pMds->TxResult[ PacketId ] |= ((u16)(pT02->value & 0x0ffff));
229}
230
231void
232Mds_HeaderCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer)
233{
234 PMDS pMds = &Adapter->Mds;
235 PUCHAR src_buffer = pDes->buffer_address[0];//931130.5.g
236 PT00_DESCRIPTOR pT00;
237 PT01_DESCRIPTOR pT01;
238 u16 stmp;
239 u8 i, ctmp1, ctmp2, ctmpf;
240 u16 FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD;
241
242
243 stmp = pDes->buffer_total_size;
244 //
245 // Set USB header 8 byte
246 //
247 pT00 = (PT00_DESCRIPTOR)TargetBuffer;
248 TargetBuffer += 4;
249 pT01 = (PT01_DESCRIPTOR)TargetBuffer;
250 TargetBuffer += 4;
251
252 pT00->value = 0;// Clear
253 pT01->value = 0;// Clear
254
255 pT00->T00_tx_packet_id = pDes->Descriptor_ID;// Set packet ID
256 pT00->T00_header_length = 24;// Set header length
257 pT01->T01_retry_abort_ebable = 1;//921013 931130.5.h
258
259 // Key ID setup
260 pT01->T01_wep_id = 0;
261
262 FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; //Do not fragment
263 // Copy full data, the 1'st buffer contain all the data 931130.5.j
264 memcpy( TargetBuffer, src_buffer, DOT_11_MAC_HEADER_SIZE );// Copy header
265 pDes->buffer_address[0] = src_buffer + DOT_11_MAC_HEADER_SIZE;
266 pDes->buffer_total_size -= DOT_11_MAC_HEADER_SIZE;
267 pDes->buffer_size[0] = pDes->buffer_total_size;
268
269 // Set fragment threshold
270 FragmentThreshold -= (DOT_11_MAC_HEADER_SIZE + 4);
271 pDes->FragmentThreshold = FragmentThreshold;
272
273 // Set more frag bit
274 TargetBuffer[1] |= 0x04;// Set more frag bit
275
276 //
277 // Set tx rate
278 //
279 stmp = *(PUSHORT)(TargetBuffer+30); // 2n alignment address
280
281 //Use basic rate
282 ctmp1 = ctmpf = CURRENT_TX_RATE_FOR_MNG;
283
284 pDes->TxRate = ctmp1;
285 #ifdef _PE_TX_DUMP_
286 WBDEBUG(("Tx rate =%x\n", ctmp1));
287 #endif
288
289 pT01->T01_modulation_type = (ctmp1%3) ? 0 : 1;
290
291 for( i=0; i<2; i++ ) {
292 if( i == 1 )
293 ctmp1 = ctmpf;
294
295 pMds->TxRate[pDes->Descriptor_ID][i] = ctmp1; // backup the ta rate and fall back rate
296
297 if( ctmp1 == 108) ctmp2 = 7;
298 else if( ctmp1 == 96 ) ctmp2 = 6; // Rate convert for USB
299 else if( ctmp1 == 72 ) ctmp2 = 5;
300 else if( ctmp1 == 48 ) ctmp2 = 4;
301 else if( ctmp1 == 36 ) ctmp2 = 3;
302 else if( ctmp1 == 24 ) ctmp2 = 2;
303 else if( ctmp1 == 18 ) ctmp2 = 1;
304 else if( ctmp1 == 12 ) ctmp2 = 0;
305 else if( ctmp1 == 22 ) ctmp2 = 3;
306 else if( ctmp1 == 11 ) ctmp2 = 2;
307 else if( ctmp1 == 4 ) ctmp2 = 1;
308 else ctmp2 = 0; // if( ctmp1 == 2 ) or default
309
310 if( i == 0 )
311 pT01->T01_transmit_rate = ctmp2;
312 else
313 pT01->T01_fall_back_rate = ctmp2;
314 }
315
316 //
317 // Set preamble type
318 //
319 if ((pT01->T01_modulation_type == 0) && (pT01->T01_transmit_rate == 0)) // RATE_1M
320 pDes->PreambleMode = WLAN_PREAMBLE_TYPE_LONG;
321 else
322 pDes->PreambleMode = CURRENT_PREAMBLE_MODE;
323 pT01->T01_plcp_header_length = pDes->PreambleMode; // Set preamble
324
325}
326
327// The function return the 4n size of usb pk
328u16
329Mds_BodyCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer)
330{
331 PT00_DESCRIPTOR pT00;
332 PMDS pMds = &Adapter->Mds;
333 PUCHAR buffer, src_buffer, pctmp;
334 u16 Size = 0;
335 u16 SizeLeft, CopySize, CopyLeft, stmp;
336 u8 buf_index, FragmentCount = 0;
337
338
339 // Copy fragment body
340 buffer = TargetBuffer; // shift 8B usb + 24B 802.11
341 SizeLeft = pDes->buffer_total_size;
342 buf_index = pDes->buffer_start_index;
343
344 pT00 = (PT00_DESCRIPTOR)buffer;
345 while (SizeLeft) {
346 pT00 = (PT00_DESCRIPTOR)buffer;
347 CopySize = SizeLeft;
348 if (SizeLeft > pDes->FragmentThreshold) {
349 CopySize = pDes->FragmentThreshold;
350 pT00->T00_frame_length = 24 + CopySize;//Set USB length
351 } else
352 pT00->T00_frame_length = 24 + SizeLeft;//Set USB length
353
354 SizeLeft -= CopySize;
355
356 // 1 Byte operation
357 pctmp = (PUCHAR)( buffer + 8 + DOT_11_SEQUENCE_OFFSET );
358 *pctmp &= 0xf0;
359 *pctmp |= FragmentCount;//931130.5.m
360 if( !FragmentCount )
361 pT00->T00_first_mpdu = 1;
362
363 buffer += 32; // 8B usb + 24B 802.11 header
364 Size += 32;
365
366 // Copy into buffer
367 stmp = CopySize + 3;
368 stmp &= ~0x03;//4n Alignment
369 Size += stmp;// Current 4n offset of mpdu
370
371 while (CopySize) {
372 // Copy body
373 src_buffer = pDes->buffer_address[buf_index];
374 CopyLeft = CopySize;
375 if (CopySize >= pDes->buffer_size[buf_index]) {
376 CopyLeft = pDes->buffer_size[buf_index];
377
378 // Get the next buffer of descriptor
379 buf_index++;
380 buf_index %= MAX_DESCRIPTOR_BUFFER_INDEX;
381 } else {
382 PUCHAR pctmp = pDes->buffer_address[buf_index];
383 pctmp += CopySize;
384 pDes->buffer_address[buf_index] = pctmp;
385 pDes->buffer_size[buf_index] -= CopySize;
386 }
387
388 memcpy(buffer, src_buffer, CopyLeft);
389 buffer += CopyLeft;
390 CopySize -= CopyLeft;
391 }
392
393 // 931130.5.n
394 if (pMds->MicAdd) {
395 if (!SizeLeft) {
396 pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - pMds->MicAdd;
397 pMds->MicWriteSize[ pMds->MicWriteIndex ] = pMds->MicAdd;
398 pMds->MicAdd = 0;
399 }
400 else if( SizeLeft < 8 ) //931130.5.p
401 {
402 pMds->MicAdd = SizeLeft;
403 pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - ( 8 - SizeLeft );
404 pMds->MicWriteSize[ pMds->MicWriteIndex ] = 8 - SizeLeft;
405 pMds->MicWriteIndex++;
406 }
407 }
408
409 // Does it need to generate the new header for next mpdu?
410 if (SizeLeft) {
411 buffer = TargetBuffer + Size; // Get the next 4n start address
412 memcpy( buffer, TargetBuffer, 32 );//Copy 8B USB +24B 802.11
413 pT00 = (PT00_DESCRIPTOR)buffer;
414 pT00->T00_first_mpdu = 0;
415 }
416
417 FragmentCount++;
418 }
419
420 pT00->T00_last_mpdu = 1;
421 pT00->T00_IsLastMpdu = 1;
422 buffer = (PUCHAR)pT00 + 8; // +8 for USB hdr
423 buffer[1] &= ~0x04; // Clear more frag bit of 802.11 frame control
424 pDes->FragmentCount = FragmentCount; // Update the correct fragment number
425 return Size;
426}
427
428
429void
430Mds_DurationSet( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR buffer )
431{
432 PT00_DESCRIPTOR pT00;
433 PT01_DESCRIPTOR pT01;
434 u16 Duration, NextBodyLen, OffsetSize;
435 u8 Rate, i;
436 unsigned char CTS_on = FALSE, RTS_on = FALSE;
437 PT00_DESCRIPTOR pNextT00;
438 u16 BodyLen;
439 unsigned char boGroupAddr = FALSE;
440
441
442 OffsetSize = pDes->FragmentThreshold + 32 + 3;
443 OffsetSize &= ~0x03;
444 Rate = pDes->TxRate >> 1;
445 if (!Rate)
446 Rate = 1;
447
448 pT00 = (PT00_DESCRIPTOR)buffer;
449 pT01 = (PT01_DESCRIPTOR)(buffer+4);
450 pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize);
451
452 if( buffer[ DOT_11_DA_OFFSET+8 ] & 0x1 ) // +8 for USB hdr
453 boGroupAddr = TRUE;
454
455 //========================================
456 // Set RTS/CTS mechanism
457 //========================================
458 if (!boGroupAddr)
459 {
460 //NOTE : If the protection mode is enabled and the MSDU will be fragmented,
461 // the tx rates of MPDUs will all be DSSS rates. So it will not use
462 // CTS-to-self in this case. CTS-To-self will only be used when without
463 // fragmentation. -- 20050112
464 BodyLen = (u16)pT00->T00_frame_length; //include 802.11 header
465 BodyLen += 4; //CRC
466
467 if( BodyLen >= CURRENT_RTS_THRESHOLD )
468 RTS_on = TRUE; // Using RTS
469 else
470 {
471 if( pT01->T01_modulation_type ) // Is using OFDM
472 {
473 if( CURRENT_PROTECT_MECHANISM ) // Is using protect
474 CTS_on = TRUE; // Using CTS
475 }
476 }
477 }
478
479 if( RTS_on || CTS_on )
480 {
481 if( pT01->T01_modulation_type) // Is using OFDM
482 {
483 //CTS duration
484 // 2 SIFS + DATA transmit time + 1 ACK
485 // ACK Rate : 24 Mega bps
486 // ACK frame length = 14 bytes
487 Duration = 2*DEFAULT_SIFSTIME +
488 2*PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION +
489 ((BodyLen*8 + 22 + Rate*4 - 1)/(Rate*4))*Tsym +
490 ((112 + 22 + 95)/96)*Tsym;
491 }
492 else //DSSS
493 {
494 //CTS duration
495 // 2 SIFS + DATA transmit time + 1 ACK
496 // Rate : ?? Mega bps
497 // ACK frame length = 14 bytes
498 if( pT01->T01_plcp_header_length ) //long preamble
499 Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*2;
500 else
501 Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*2;
502
503 Duration += ( ((BodyLen + 14)*8 + Rate-1) / Rate +
504 DEFAULT_SIFSTIME*2 );
505 }
506
507 if( RTS_on )
508 {
509 if( pT01->T01_modulation_type ) // Is using OFDM
510 {
511 //CTS + 1 SIFS + CTS duration
512 //CTS Rate : 24 Mega bps
513 //CTS frame length = 14 bytes
514 Duration += (DEFAULT_SIFSTIME +
515 PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION +
516 ((112 + 22 + 95)/96)*Tsym);
517 }
518 else
519 {
520 //CTS + 1 SIFS + CTS duration
521 //CTS Rate : ?? Mega bps
522 //CTS frame length = 14 bytes
523 if( pT01->T01_plcp_header_length ) //long preamble
524 Duration += LONG_PREAMBLE_PLUS_PLCPHEADER_TIME;
525 else
526 Duration += SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME;
527
528 Duration += ( ((112 + Rate-1) / Rate) + DEFAULT_SIFSTIME );
529 }
530 }
531
532 // Set the value into USB descriptor
533 pT01->T01_add_rts = RTS_on ? 1 : 0;
534 pT01->T01_add_cts = CTS_on ? 1 : 0;
535 pT01->T01_rts_cts_duration = Duration;
536 }
537
538 //=====================================
539 // Fill the more fragment descriptor
540 //=====================================
541 if( boGroupAddr )
542 Duration = 0;
543 else
544 {
545 for( i=pDes->FragmentCount-1; i>0; i-- )
546 {
547 NextBodyLen = (u16)pNextT00->T00_frame_length;
548 NextBodyLen += 4; //CRC
549
550 if( pT01->T01_modulation_type )
551 {
552 //OFDM
553 // data transmit time + 3 SIFS + 2 ACK
554 // Rate : ??Mega bps
555 // ACK frame length = 14 bytes, tx rate = 24M
556 Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION * 3;
557 Duration += (((NextBodyLen*8 + 22 + Rate*4 - 1)/(Rate*4)) * Tsym +
558 (((2*14)*8 + 22 + 95)/96)*Tsym +
559 DEFAULT_SIFSTIME*3);
560 }
561 else
562 {
563 //DSSS
564 // data transmit time + 2 ACK + 3 SIFS
565 // Rate : ??Mega bps
566 // ACK frame length = 14 bytes
567 //TODO :
568 if( pT01->T01_plcp_header_length ) //long preamble
569 Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*3;
570 else
571 Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*3;
572
573 Duration += ( ((NextBodyLen + (2*14))*8 + Rate-1) / Rate +
574 DEFAULT_SIFSTIME*3 );
575 }
576
577 ((PUSHORT)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration
578
579 //----20061009 add by anson's endian
580 pNextT00->value = cpu_to_le32(pNextT00->value);
581 pT01->value = cpu_to_le32( pT01->value );
582 //----end 20061009 add by anson's endian
583
584 buffer += OffsetSize;
585 pT01 = (PT01_DESCRIPTOR)(buffer+4);
586 if (i != 1) //The last fragment will not have the next fragment
587 pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize);
588 }
589
590 //=====================================
591 // Fill the last fragment descriptor
592 //=====================================
593 if( pT01->T01_modulation_type )
594 {
595 //OFDM
596 // 1 SIFS + 1 ACK
597 // Rate : 24 Mega bps
598 // ACK frame length = 14 bytes
599 Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION;
600 //The Tx rate of ACK use 24M
601 Duration += (((112 + 22 + 95)/96)*Tsym + DEFAULT_SIFSTIME );
602 }
603 else
604 {
605 // DSSS
606 // 1 ACK + 1 SIFS
607 // Rate : ?? Mega bps
608 // ACK frame length = 14 bytes(112 bits)
609 if( pT01->T01_plcp_header_length ) //long preamble
610 Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME;
611 else
612 Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME;
613
614 Duration += ( (112 + Rate-1)/Rate + DEFAULT_SIFSTIME );
615 }
616 }
617
618 ((PUSHORT)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration
619 pT00->value = cpu_to_le32(pT00->value);
620 pT01->value = cpu_to_le32(pT01->value);
621 //--end 20061009 add
622
623}
624
625void MDS_EthernetPacketReceive( PADAPTER Adapter, PRXLAYER1 pRxLayer1 )
626{
627 OS_RECEIVE_PACKET_INDICATE( Adapter, pRxLayer1 );
628}
629
630
diff --git a/drivers/staging/winbond/mds_f.h b/drivers/staging/winbond/mds_f.h
new file mode 100644
index 000000000000..651188be1065
--- /dev/null
+++ b/drivers/staging/winbond/mds_f.h
@@ -0,0 +1,33 @@
1unsigned char Mds_initial( PADAPTER Adapter );
2void Mds_Destroy( PADAPTER Adapter );
3void Mds_Tx( PADAPTER Adapter );
4void Mds_HeaderCopy( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer );
5u16 Mds_BodyCopy( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer );
6void Mds_DurationSet( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer );
7void Mds_SendComplete( PADAPTER Adapter, PT02_DESCRIPTOR pT02 );
8void Mds_MpduProcess( PADAPTER Adapter, PDESCRIPTOR pRxDes );
9void Mds_reset_descriptor( PADAPTER Adapter );
10extern void DataDmp(u8 *pdata, u32 len, u32 offset);
11
12
13void vRxTimerInit(PWB32_ADAPTER Adapter);
14void vRxTimerStart(PWB32_ADAPTER Adapter, int timeout_value);
15void RxTimerHandler_1a( PADAPTER Adapter);
16void vRxTimerStop(PWB32_ADAPTER Adapter);
17void RxTimerHandler( void* SystemSpecific1,
18 PWB32_ADAPTER Adapter,
19 void* SystemSpecific2,
20 void* SystemSpecific3);
21
22
23// For Asynchronous indicating. The routine collocates with USB.
24void Mds_MsduProcess( PWB32_ADAPTER Adapter, PRXLAYER1 pRxLayer1, u8 SlotIndex);
25
26// For data frame sending 20060802
27u16 MDS_GetPacketSize( PADAPTER Adapter );
28void MDS_GetNextPacket( PADAPTER Adapter, PDESCRIPTOR pDes );
29void MDS_GetNextPacketComplete( PADAPTER Adapter, PDESCRIPTOR pDes );
30void MDS_SendResult( PADAPTER Adapter, u8 PacketId, unsigned char SendOK );
31void MDS_EthernetPacketReceive( PADAPTER Adapter, PRXLAYER1 pRxLayer1 );
32
33
diff --git a/drivers/staging/winbond/mds_s.h b/drivers/staging/winbond/mds_s.h
new file mode 100644
index 000000000000..4738279d5f39
--- /dev/null
+++ b/drivers/staging/winbond/mds_s.h
@@ -0,0 +1,183 @@
1////////////////////////////////////////////////////////////////////////////////////////////////////////
2#define MAX_USB_TX_DESCRIPTOR 15 // IS89C35 ability
3#define MAX_USB_TX_BUFFER_NUMBER 4 // Virtual pre-buffer number of MAX_USB_TX_BUFFER
4#define MAX_USB_TX_BUFFER 4096 // IS89C35 ability 4n alignment is required for hardware
5
6#define MDS_EVENT_INDICATE( _A, _B, _F ) OS_EVENT_INDICATE( _A, _B, _F )
7#define AUTH_REQUEST_PAIRWISE_ERROR 0 // _F flag setting
8#define AUTH_REQUEST_GROUP_ERROR 1 // _F flag setting
9
10// For variable setting
11#define CURRENT_BSS_TYPE psBSS(psLOCAL->wConnectedSTAindex)->bBssType
12#define CURRENT_WEP_MODE psSME->_dot11PrivacyInvoked
13#define CURRENT_BSSID psBSS(psLOCAL->wConnectedSTAindex)->abBssID
14#define CURRENT_DESIRED_WPA_ENABLE ((psSME->bDesiredAuthMode==WPA_AUTH)||(psSME->bDesiredAuthMode==WPAPSK_AUTH))
15#ifdef _WPA2_
16#define CURRENT_DESIRED_WPA2_ENABLE ((psSME->bDesiredAuthMode==WPA2_AUTH)||(psSME->bDesiredAuthMode==WPA2PSK_AUTH))
17#endif //end def _WPA2_
18#define CURRENT_PAIRWISE_KEY_OK psSME->pairwise_key_ok
19//[20040712 WS]
20#define CURRENT_GROUP_KEY_OK psSME->group_key_ok
21#define CURRENT_PAIRWISE_KEY psSME->tx_mic_key
22#define CURRENT_GROUP_KEY psSME->group_tx_mic_key
23#define CURRENT_ENCRYPT_STATUS psSME->encrypt_status
24#define CURRENT_WEP_ID Adapter->sSmePara._dot11WEPDefaultKeyID
25#define CURRENT_CONTROL_PORT_BLOCK ( psSME->wpa_ok!=1 || (Adapter->Mds.boCounterMeasureBlock==1 && (CURRENT_ENCRYPT_STATUS==ENCRYPT_TKIP)) )
26#define CURRENT_FRAGMENT_THRESHOLD (Adapter->Mds.TxFragmentThreshold & ~0x1)
27#define CURRENT_PREAMBLE_MODE psLOCAL->boShortPreamble?WLAN_PREAMBLE_TYPE_SHORT:WLAN_PREAMBLE_TYPE_LONG
28#define CURRENT_LINK_ON OS_LINK_STATUS
29#define CURRENT_TX_RATE Adapter->sLocalPara.CurrentTxRate
30#define CURRENT_FALL_BACK_TX_RATE Adapter->sLocalPara.CurrentTxFallbackRate
31#define CURRENT_TX_RATE_FOR_MNG Adapter->sLocalPara.CurrentTxRateForMng
32#define CURRENT_PROTECT_MECHANISM psLOCAL->boProtectMechanism
33#define CURRENT_RTS_THRESHOLD Adapter->Mds.TxRTSThreshold
34
35#define MIB_GS_XMIT_OK_INC Adapter->sLocalPara.GS_XMIT_OK++
36#define MIB_GS_RCV_OK_INC Adapter->sLocalPara.GS_RCV_OK++
37#define MIB_GS_XMIT_ERROR_INC Adapter->sLocalPara.GS_XMIT_ERROR
38
39//---------- TX -----------------------------------
40#define ETHERNET_TX_DESCRIPTORS MAX_USB_TX_BUFFER_NUMBER
41
42//---------- RX ------------------------------------
43#define ETHERNET_RX_DESCRIPTORS 8 //It's not necessary to allocate more than 2 in sync indicate
44
45//================================================================
46// Configration default value
47//================================================================
48#define DEFAULT_MULTICASTLISTMAX 32 // standard
49#define DEFAULT_TX_BURSTLENGTH 3 // 32 Longwords
50#define DEFAULT_RX_BURSTLENGTH 3 // 32 Longwords
51#define DEFAULT_TX_THRESHOLD 0 // Full Packet
52#define DEFAULT_RX_THRESHOLD 0 // Full Packet
53#define DEFAULT_MAXTXRATE 6 // 11 Mbps (Long)
54#define DEFAULT_CHANNEL 3 // Chennel 3
55#define DEFAULT_RTSThreshold 2347 // Disable RTS
56//#define DEFAULT_PME 1 // Enable
57#define DEFAULT_PME 0 // Disable
58#define DEFAULT_SIFSTIME 10
59#define DEFAULT_ACKTIME_1ML 304 // 148+44+112 911220 by LCC
60#define DEFAULT_ACKTIME_2ML 248 // 148+44+56 911220 by LCC
61#define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment
62#define DEFAULT_PREAMBLE_LENGTH 72
63#define DEFAULT_PLCPHEADERTIME_LENGTH 24
64
65/*------------------------------------------------------------------------
66 0.96 sec since time unit of the R03 for the current, W89C32 is about 60ns
67 instead of 960 ns. This shall be fixed in the future W89C32
68 -------------------------------------------------------------------------*/
69#define DEFAULT_MAX_RECEIVE_TIME 16440000
70
71#define RX_BUF_SIZE 2352 // 600 // For 301 must be multiple of 8
72#define MAX_RX_DESCRIPTORS 18 // Rx Layer 2
73#define MAX_BUFFER_QUEUE 8 // The value is always equal 8 due to NDIS_PACKET's MiniportReserved field size
74
75
76// For brand-new rx system
77#define MDS_ID_IGNORE ETHERNET_RX_DESCRIPTORS
78
79// For Tx Packet status classify
80#define PACKET_FREE_TO_USE 0
81#define PACKET_COME_FROM_NDIS 0x08
82#define PACKET_COME_FROM_MLME 0x80
83#define PACKET_SEND_COMPLETE 0xff
84
85typedef struct _MDS
86{
87 // For Tx usage
88 u8 TxOwner[ ((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03) ];
89 PUCHAR pTxBuffer;
90 u16 TxBufferSize[ ((MAX_USB_TX_BUFFER_NUMBER + 1) & ~0x01) ];
91 u8 TxDesFrom[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ];//931130.4.u // 1: MLME 2: NDIS control 3: NDIS data
92 u8 TxCountInBuffer[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ]; // 20060928
93
94 u8 TxFillIndex;//the next index of TxBuffer can be used
95 u8 TxDesIndex;//The next index of TxDes can be used
96 u8 ScanTxPause; //data Tx pause because the scanning is progressing, but probe request Tx won't.
97 u8 TxPause;//For pause the Mds_Tx modult
98
99 OS_ATOMIC TxThreadCount;//For thread counting 931130.4.v
100//950301 delete due to HW
101// OS_ATOMIC TxConcurrentCount;//931130.4.w
102
103 u16 TxResult[ ((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01) ];//Collect the sending result of Mpdu
104
105 u8 MicRedundant[8]; // For tmp use
106 PUCHAR MicWriteAddress[2]; //The start address to fill the Mic, use 2 point due to Mic maybe fragment
107
108 u16 MicWriteSize[2]; //931130.4.x
109
110 u16 MicAdd; // If want to add the Mic, this variable equal to 8
111 u16 MicWriteIndex;//The number of MicWriteAddress 931130.4.y
112
113 u8 TxRate[ ((MAX_USB_TX_DESCRIPTOR+1)&~0x01) ][2]; // [0] current tx rate, [1] fall back rate
114 u8 TxInfo[ ((MAX_USB_TX_DESCRIPTOR+1)&~0x01) ]; //Store information for callback function
115
116 //WKCHEN added for scanning mechanism
117 u8 TxToggle; //It is TRUE if there are tx activities in some time interval
118 u8 Reserved_[3];
119
120 //---------- for Tx Parameter
121 u16 TxFragmentThreshold; // For frame body only
122 u16 TxRTSThreshold;
123
124 u32 MaxReceiveTime;//911220.3 Add
125
126 // depend on OS,
127 u32 MulticastListNo;
128 u32 PacketFilter; // Setting by NDIS, the current packet filter in use.
129 u8 MulticastAddressesArray[DEFAULT_MULTICASTLISTMAX][MAC_ADDR_LENGTH];
130
131 //COUNTERMEASURE
132 u8 bMICfailCount;
133 u8 boCounterMeasureBlock;
134 u8 reserved_4[2];
135
136 //NDIS_MINIPORT_TIMER nTimer;
137 OS_TIMER nTimer;
138
139 u32 TxTsc; // 20060214
140 u32 TxTsc_2; // 20060214
141
142} MDS, *PMDS;
143
144
145typedef struct _RxBuffer
146{
147 PUCHAR pBufferAddress; // Pointer the received data buffer.
148 u16 BufferSize;
149 u8 RESERVED;
150 u8 BufferIndex;// Only 1 byte
151} RXBUFFER, *PRXBUFFER;
152
153//
154// Reveive Layer 1 Format.
155//----------------------------
156typedef struct _RXLAYER1
157{
158 u16 SequenceNumber; // The sequence number of the last received packet.
159 u16 BufferTotalSize;
160
161 u32 InUsed;
162 u32 DecryptionMethod; // The desired defragment number of the next incoming packet.
163
164 u8 DeFragmentNumber;
165 u8 FrameType;
166 u8 TypeEncapsulated;
167 u8 BufferNumber;
168
169 u32 FirstFrameArrivedTime;
170
171 RXBUFFER BufferQueue[ MAX_BUFFER_QUEUE ];
172
173 u8 LastFrameType; // 20061004 for fix intel 3945 's bug
174 u8 RESERVED[3]; //@@ anson
175
176 /////////////////////////////////////////////////////////////////////////////////////////////
177 // For brand-new Rx system
178 u8 ReservedBuffer[ 2400 ];//If Buffer ID is reserved one, it must copy the data into this area
179 PUCHAR ReservedBufferPoint;// Point to the next availabe address of reserved buffer
180
181}RXLAYER1, * PRXLAYER1;
182
183
diff --git a/drivers/staging/winbond/mlme_mib.h b/drivers/staging/winbond/mlme_mib.h
new file mode 100644
index 000000000000..89759739cbac
--- /dev/null
+++ b/drivers/staging/winbond/mlme_mib.h
@@ -0,0 +1,84 @@
1//============================================================================
2// MLMEMIB.H -
3//
4// Description:
5// Get and Set some of MLME MIB attributes.
6//
7// Revision history:
8// --------------------------------------------------------------------------
9// 20030117 PD43 Austin Liu
10// Initial release
11//
12// Copyright (c) 2003 Winbond Electronics Corp. All rights reserved.
13//============================================================================
14
15#ifndef _MLME_MIB_H
16#define _MLME_MIB_H
17
18//============================================================================
19// MLMESetExcludeUnencrypted --
20//
21// Description:
22// Set the dot11ExcludeUnencrypted value.
23//
24// Arguments:
25// Adapter - The pointer to the miniport adapter context.
26// ExUnencrypted - unsigned char type. The value to be set.
27//
28// Return values:
29// None.
30//============================================================================
31#define MLMESetExcludeUnencrypted(Adapter, ExUnencrypted) \
32{ \
33 (Adapter)->sLocalPara.ExcludeUnencrypted = ExUnencrypted; \
34}
35
36//============================================================================
37// MLMEGetExcludeUnencrypted --
38//
39// Description:
40// Get the dot11ExcludeUnencrypted value.
41//
42// Arguments:
43// Adapter - The pointer to the miniport adapter context.
44//
45// Return values:
46// unsigned char type. The current dot11ExcludeUnencrypted value.
47//============================================================================
48#define MLMEGetExcludeUnencrypted(Adapter) ((unsigned char) (Adapter)->sLocalPara.ExcludeUnencrypted)
49
50//============================================================================
51// MLMESetMaxReceiveLifeTime --
52//
53// Description:
54// Set the dot11MaxReceiveLifeTime value.
55//
56// Arguments:
57// Adapter - The pointer to the miniport adapter context.
58// ReceiveLifeTime- u32 type. The value to be set.
59//
60// Return values:
61// None.
62//============================================================================
63#define MLMESetMaxReceiveLifeTime(Adapter, ReceiveLifeTime) \
64{ \
65 (Adapter)->Mds.MaxReceiveTime = ReceiveLifeTime; \
66}
67
68//============================================================================
69// MLMESetMaxReceiveLifeTime --
70//
71// Description:
72// Get the dot11MaxReceiveLifeTime value.
73//
74// Arguments:
75// Adapter - The pointer to the miniport adapter context.
76//
77// Return values:
78// u32 type. The current dot11MaxReceiveLifeTime value.
79//============================================================================
80#define MLMEGetMaxReceiveLifeTime(Adapter) ((u32) (Adapter)->Mds.MaxReceiveTime)
81
82#endif
83
84
diff --git a/drivers/staging/winbond/mlme_s.h b/drivers/staging/winbond/mlme_s.h
new file mode 100644
index 000000000000..58094f61c032
--- /dev/null
+++ b/drivers/staging/winbond/mlme_s.h
@@ -0,0 +1,195 @@
1//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2// Mlme.h
3// Define the related definitions of MLME module
4// history -- 01/14/03' created
5//
6//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
7
8#define AUTH_REJECT_REASON_CHALLENGE_FAIL 1
9
10//====== the state of MLME module
11#define INACTIVE 0x0
12#define IDLE_SCAN 0x1
13
14//====== the state of MLME/ESS module
15#define STATE_1 0x2
16#define AUTH_REQ 0x3
17#define AUTH_WEP 0x4
18#define STATE_2 0x5
19#define ASSOC_REQ 0x6
20#define STATE_3 0x7
21
22//====== the state of MLME/IBSS module
23#define IBSS_JOIN_SYNC 0x8
24#define IBSS_AUTH_REQ 0x9
25#define IBSS_AUTH_CHANLGE 0xa
26#define IBSS_AUTH_WEP 0xb
27#define IBSS_AUTH_IND 0xc
28#define IBSS_STATE_2 0xd
29
30
31
32//=========================================
33//depend on D5C(MAC timing control 03 register): MaxTxMSDULifeTime default 0x80000us
34#define AUTH_FAIL_TIMEOUT 550
35#define ASSOC_FAIL_TIMEOUT 550
36#define REASSOC_FAIL_TIMEOUT 550
37
38
39
40//
41// MLME task global CONSTANTS, STRUCTURE, variables
42//
43
44
45/////////////////////////////////////////////////////////////
46// enum_ResultCode --
47// Result code returned from MLME to SME.
48//
49/////////////////////////////////////////////////////////////
50// PD43 20030829 Modifiled
51//#define SUCCESS 0
52#define MLME_SUCCESS 0 //follow spec.
53#define INVALID_PARAMETERS 1 //Not following spec.
54#define NOT_SUPPPORTED 2
55#define TIMEOUT 3
56#define TOO_MANY_SIMULTANEOUS_REQUESTS 4
57#define REFUSED 5
58#define BSS_ALREADY_STARTED_OR_JOINED 6
59#define TRANSMIT_FRAME_FAIL 7
60#define NO_BSS_FOUND 8
61#define RETRY 9
62#define GIVE_UP 10
63
64
65#define OPEN_AUTH 0
66#define SHARE_AUTH 1
67#define ANY_AUTH 2
68#define WPA_AUTH 3 //for WPA
69#define WPAPSK_AUTH 4
70#define WPANONE_AUTH 5
71///////////////////////////////////////////// added by ws 04/19/04
72#ifdef _WPA2_
73#define WPA2_AUTH 6//for WPA2
74#define WPA2PSK_AUTH 7
75#endif //end def _WPA2_
76
77//////////////////////////////////////////////////////////////////
78//define the msg type of MLME module
79//////////////////////////////////////////////////////////////////
80//--------------------------------------------------------
81//from SME
82
83#define MLMEMSG_AUTH_REQ 0x0b
84#define MLMEMSG_DEAUTH_REQ 0x0c
85#define MLMEMSG_ASSOC_REQ 0x0d
86#define MLMEMSG_REASSOC_REQ 0x0e
87#define MLMEMSG_DISASSOC_REQ 0x0f
88#define MLMEMSG_START_IBSS_REQ 0x10
89#define MLMEMSG_IBSS_NET_CFM 0x11
90
91//from RX :
92#define MLMEMSG_RCV_MLMEFRAME 0x20
93#define MLMEMSG_RCV_ASSOCRSP 0x22
94#define MLMEMSG_RCV_REASSOCRSP 0x24
95#define MLMEMSG_RCV_DISASSOC 0x2b
96#define MLMEMSG_RCV_AUTH 0x2c
97#define MLMEMSG_RCV_DEAUTH 0x2d
98
99
100//from TX callback
101#define MLMEMSG_TX_CALLBACK 0x40
102#define MLMEMSG_ASSOCREQ_CALLBACK 0x41
103#define MLMEMSG_REASSOCREQ_CALLBACK 0x43
104#define MLMEMSG_DISASSOC_CALLBACK 0x4a
105#define MLMEMSG_AUTH_CALLBACK 0x4c
106#define MLMEMSG_DEAUTH_CALLBACK 0x4d
107
108//#define MLMEMSG_JOIN_FAIL 4
109//#define MLMEMSG_AUTHEN_FAIL 18
110#define MLMEMSG_TIMEOUT 0x50
111
112///////////////////////////////////////////////////////////////////////////
113//Global data structures
114#define MAX_NUM_TX_MMPDU 2
115#define MAX_MMPDU_SIZE 1512
116#define MAX_NUM_RX_MMPDU 6
117
118
119///////////////////////////////////////////////////////////////////////////
120//MACRO
121#define boMLME_InactiveState(_AA_) (_AA_->wState==INACTIVE)
122#define boMLME_IdleScanState(_BB_) (_BB_->wState==IDLE_SCAN)
123#define boMLME_FoundSTAinfo(_CC_) (_CC_->wState>=IDLE_SCAN)
124
125typedef struct _MLME_FRAME
126{
127 //NDIS_PACKET MLME_Packet;
128 PCHAR pMMPDU;
129 u16 len;
130 u8 DataType;
131 u8 IsInUsed;
132
133 OS_SPIN_LOCK MLMESpinLock;
134
135 u8 TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE];
136 u8 TxMMPDUInUse[ (MAX_NUM_TX_MMPDU+3) & ~0x03 ];
137
138 u16 wNumTxMMPDU;
139 u16 wNumTxMMPDUDiscarded;
140
141 u8 RxMMPDU[MAX_NUM_RX_MMPDU][MAX_MMPDU_SIZE];
142 u8 SaveRxBufSlotInUse[ (MAX_NUM_RX_MMPDU+3) & ~0x03 ];
143
144 u16 wNumRxMMPDU;
145 u16 wNumRxMMPDUDiscarded;
146
147 u16 wNumRxMMPDUInMLME; // Number of the Rx MMPDU
148 u16 reserved_1; // in MLME.
149 // excluding the discarded
150} MLME_FRAME, *psMLME_FRAME;
151
152typedef struct _AUTHREQ {
153
154 u8 peerMACaddr[MAC_ADDR_LENGTH];
155 u16 wAuthAlgorithm;
156
157} MLME_AUTHREQ_PARA, *psMLME_AUTHREQ_PARA;
158
159struct _Reason_Code {
160
161 u8 peerMACaddr[MAC_ADDR_LENGTH];
162 u16 wReasonCode;
163};
164typedef struct _Reason_Code MLME_DEAUTHREQ_PARA, *psMLME_DEAUTHREQ_PARA;
165typedef struct _Reason_Code MLME_DISASSOCREQ_PARA, *psMLME_DISASSOCREQ_PARA;
166
167typedef struct _ASSOCREQ {
168 u8 PeerSTAAddr[MAC_ADDR_LENGTH];
169 u16 CapabilityInfo;
170 u16 ListenInterval;
171
172}__attribute__ ((packed)) MLME_ASSOCREQ_PARA, *psMLME_ASSOCREQ_PARA;
173
174typedef struct _REASSOCREQ {
175 u8 NewAPAddr[MAC_ADDR_LENGTH];
176 u16 CapabilityInfo;
177 u16 ListenInterval;
178
179}__attribute__ ((packed)) MLME_REASSOCREQ_PARA, *psMLME_REASSOCREQ_PARA;
180
181typedef struct _MLMECALLBACK {
182
183 u8 *psFramePtr;
184 u8 bResult;
185
186} MLME_TXCALLBACK, *psMLME_TXCALLBACK;
187
188typedef struct _RXDATA
189{
190 s32 FrameLength;
191 u8 __attribute__ ((packed)) *pbFramePtr;
192
193}__attribute__ ((packed)) RXDATA, *psRXDATA;
194
195
diff --git a/drivers/staging/winbond/mlmetxrx.c b/drivers/staging/winbond/mlmetxrx.c
new file mode 100644
index 000000000000..46b091e96794
--- /dev/null
+++ b/drivers/staging/winbond/mlmetxrx.c
@@ -0,0 +1,150 @@
1//============================================================================
2// Module Name:
3// MLMETxRx.C
4//
5// Description:
6// The interface between MDS (MAC Data Service) and MLME.
7//
8// Revision History:
9// --------------------------------------------------------------------------
10// 200209 UN20 Jennifer Xu
11// Initial Release
12// 20021108 PD43 Austin Liu
13// 20030117 PD43 Austin Liu
14// Deleted MLMEReturnPacket and MLMEProcThread()
15//
16// Copyright (c) 1996-2002 Winbond Electronics Corp. All Rights Reserved.
17//============================================================================
18#include "os_common.h"
19
20void MLMEResetTxRx(PWB32_ADAPTER Adapter)
21{
22 s32 i;
23
24 // Reset the interface between MDS and MLME
25 for (i = 0; i < MAX_NUM_TX_MMPDU; i++)
26 Adapter->sMlmeFrame.TxMMPDUInUse[i] = FALSE;
27 for (i = 0; i < MAX_NUM_RX_MMPDU; i++)
28 Adapter->sMlmeFrame.SaveRxBufSlotInUse[i] = FALSE;
29
30 Adapter->sMlmeFrame.wNumRxMMPDUInMLME = 0;
31 Adapter->sMlmeFrame.wNumRxMMPDUDiscarded = 0;
32 Adapter->sMlmeFrame.wNumRxMMPDU = 0;
33 Adapter->sMlmeFrame.wNumTxMMPDUDiscarded = 0;
34 Adapter->sMlmeFrame.wNumTxMMPDU = 0;
35 Adapter->sLocalPara.boCCAbusy = FALSE;
36 Adapter->sLocalPara.iPowerSaveMode = PWR_ACTIVE; // Power active
37}
38
39//=============================================================================
40// Function:
41// MLMEGetMMPDUBuffer()
42//
43// Description:
44// Return the pointer to an available data buffer with
45// the size MAX_MMPDU_SIZE for a MMPDU.
46//
47// Arguments:
48// Adapter - pointer to the miniport adapter context.
49//
50// Return value:
51// NULL : No available data buffer available
52// Otherwise: Pointer to the data buffer
53//=============================================================================
54
55/* FIXME: Should this just be replaced with kmalloc() and kfree()? */
56u8 *MLMEGetMMPDUBuffer(PWB32_ADAPTER Adapter)
57{
58 s32 i;
59 u8 *returnVal;
60
61 for (i = 0; i< MAX_NUM_TX_MMPDU; i++) {
62 if (Adapter->sMlmeFrame.TxMMPDUInUse[i] == FALSE)
63 break;
64 }
65 if (i >= MAX_NUM_TX_MMPDU) return NULL;
66
67 returnVal = (u8 *)&(Adapter->sMlmeFrame.TxMMPDU[i]);
68 Adapter->sMlmeFrame.TxMMPDUInUse[i] = TRUE;
69
70 return returnVal;
71}
72
73//=============================================================================
74u8 MLMESendFrame(PWB32_ADAPTER Adapter, u8 *pMMPDU, u16 len, u8 DataType)
75/* DataType : FRAME_TYPE_802_11_MANAGEMENT, FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE,
76 FRAME_TYPE_802_11_DATA */
77{
78 if (Adapter->sMlmeFrame.IsInUsed != PACKET_FREE_TO_USE) {
79 Adapter->sMlmeFrame.wNumTxMMPDUDiscarded++;
80 return FALSE;
81 }
82 Adapter->sMlmeFrame.IsInUsed = PACKET_COME_FROM_MLME;
83
84 // Keep information for sending
85 Adapter->sMlmeFrame.pMMPDU = pMMPDU;
86 Adapter->sMlmeFrame.DataType = DataType;
87 // len must be the last setting due to QUERY_SIZE_SECOND of Mds
88 Adapter->sMlmeFrame.len = len;
89 Adapter->sMlmeFrame.wNumTxMMPDU++;
90
91 // H/W will enter power save by set the register. S/W don't send null frame
92 //with PWRMgt bit enbled to enter power save now.
93
94 // Transmit NDIS packet
95 Mds_Tx(Adapter);
96 return TRUE;
97}
98
99void
100MLME_GetNextPacket(PADAPTER Adapter, PDESCRIPTOR pDes)
101{
102#define DESCRIPTOR_ADD_BUFFER( _D, _A, _S ) \
103{\
104 _D->InternalUsed = _D->buffer_start_index + _D->buffer_number; \
105 _D->InternalUsed %= MAX_DESCRIPTOR_BUFFER_INDEX; \
106 _D->buffer_address[ _D->InternalUsed ] = _A; \
107 _D->buffer_size[ _D->InternalUsed ] = _S; \
108 _D->buffer_total_size += _S; \
109 _D->buffer_number++;\
110}
111
112 DESCRIPTOR_ADD_BUFFER( pDes, Adapter->sMlmeFrame.pMMPDU, Adapter->sMlmeFrame.len );
113 pDes->Type = Adapter->sMlmeFrame.DataType;
114}
115
116void MLMEfreeMMPDUBuffer(PWB32_ADAPTER Adapter, PCHAR pData)
117{
118 int i;
119
120 // Reclaim the data buffer
121 for (i = 0; i < MAX_NUM_TX_MMPDU; i++) {
122 if (pData == (PCHAR)&(Adapter->sMlmeFrame.TxMMPDU[i]))
123 break;
124 }
125 if (Adapter->sMlmeFrame.TxMMPDUInUse[i])
126 Adapter->sMlmeFrame.TxMMPDUInUse[i] = FALSE;
127 else {
128 // Something wrong
129 // PD43 Add debug code here???
130 }
131}
132
133void
134MLME_SendComplete(PADAPTER Adapter, u8 PacketID, unsigned char SendOK)
135{
136 MLME_TXCALLBACK TxCallback;
137
138 // Reclaim the data buffer
139 Adapter->sMlmeFrame.len = 0;
140 MLMEfreeMMPDUBuffer( Adapter, Adapter->sMlmeFrame.pMMPDU );
141
142
143 TxCallback.bResult = MLME_SUCCESS;
144
145 // Return resource
146 Adapter->sMlmeFrame.IsInUsed = PACKET_FREE_TO_USE;
147}
148
149
150
diff --git a/drivers/staging/winbond/mlmetxrx_f.h b/drivers/staging/winbond/mlmetxrx_f.h
new file mode 100644
index 000000000000..d74e225be215
--- /dev/null
+++ b/drivers/staging/winbond/mlmetxrx_f.h
@@ -0,0 +1,52 @@
1//================================================================
2// MLMETxRx.H --
3//
4// Functions defined in MLMETxRx.c.
5//
6// Copyright (c) 2002 Winbond Electrics Corp. All Rights Reserved.
7//================================================================
8#ifndef _MLMETXRX_H
9#define _MLMETXRX_H
10
11void
12MLMEProcThread(
13 PWB32_ADAPTER Adapter
14 );
15
16void MLMEResetTxRx( PWB32_ADAPTER Adapter);
17
18u8 *
19MLMEGetMMPDUBuffer(
20 PWB32_ADAPTER Adapter
21 );
22
23void MLMEfreeMMPDUBuffer( PWB32_ADAPTER Adapter, PCHAR pData);
24
25void MLME_GetNextPacket( PADAPTER Adapter, PDESCRIPTOR pDes );
26u8 MLMESendFrame( PWB32_ADAPTER Adapter,
27 u8 *pMMPDU,
28 u16 len,
29 u8 DataType);
30
31void
32MLME_SendComplete( PWB32_ADAPTER Adapter, u8 PacketID, unsigned char SendOK );
33
34void
35MLMERcvFrame(
36 PWB32_ADAPTER Adapter,
37 PRXBUFFER pRxBufferArray,
38 u8 NumOfBuffer,
39 u8 ReturnSlotIndex
40 );
41
42void
43MLMEReturnPacket(
44 PWB32_ADAPTER Adapter,
45 PUCHAR pRxBufer
46 );
47#ifdef _IBSS_BEACON_SEQ_STICK_
48s8 SendBCNullData(PWB32_ADAPTER Adapter, u16 wIdx);
49#endif
50
51#endif
52
diff --git a/drivers/staging/winbond/mto.c b/drivers/staging/winbond/mto.c
new file mode 100644
index 000000000000..2ef60e5120cc
--- /dev/null
+++ b/drivers/staging/winbond/mto.c
@@ -0,0 +1,1229 @@
1//============================================================================
2// MTO.C -
3//
4// Description:
5// MAC Throughput Optimization for W89C33 802.11g WLAN STA.
6//
7// The following MIB attributes or internal variables will be affected
8// while the MTO is being executed:
9// dot11FragmentationThreshold,
10// dot11RTSThreshold,
11// transmission rate and PLCP preamble type,
12// CCA mode,
13// antenna diversity.
14//
15// Revision history:
16// --------------------------------------------------------------------------
17// 20031227 UN20 Pete Chao
18// First draft
19// 20031229 Turbo copy from PD43
20// 20040210 Kevin revised
21// Copyright (c) 2003 Winbond Electronics Corp. All rights reserved.
22//============================================================================
23
24// LA20040210_DTO kevin
25#include "os_common.h"
26
27// Declare SQ3 to rate and fragmentation threshold table
28// Declare fragmentation thresholds table
29#define MTO_MAX_SQ3_LEVELS 14
30#define MTO_MAX_FRAG_TH_LEVELS 5
31#define MTO_MAX_DATA_RATE_LEVELS 12
32
33u16 MTO_Frag_Th_Tbl[MTO_MAX_FRAG_TH_LEVELS] =
34{
35 256, 384, 512, 768, 1536
36};
37
38u8 MTO_SQ3_Level[MTO_MAX_SQ3_LEVELS] =
39{
40 0, 26, 30, 32, 34, 35, 37, 42, 44, 46, 54, 62, 78, 81
41};
42u8 MTO_SQ3toRate[MTO_MAX_SQ3_LEVELS] =
43{
44 0, 1, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
45};
46u8 MTO_SQ3toFrag[MTO_MAX_SQ3_LEVELS] =
47{
48 0, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4
49};
50
51// One Exchange Time table
52//
53u16 MTO_One_Exchange_Time_Tbl_l[MTO_MAX_FRAG_TH_LEVELS][MTO_MAX_DATA_RATE_LEVELS] =
54{
55 { 2554, 1474, 822, 0, 0, 636, 0, 0, 0, 0, 0, 0},
56 { 3578, 1986, 1009, 0, 0, 729, 0, 0, 0, 0, 0, 0},
57 { 4602, 2498, 1195, 0, 0, 822, 0, 0, 0, 0, 0, 0},
58 { 6650, 3522, 1567, 0, 0, 1009, 0, 0, 0, 0, 0, 0},
59 {12794, 6594, 2684, 0, 0, 1567, 0, 0, 0, 0, 0, 0}
60};
61
62u16 MTO_One_Exchange_Time_Tbl_s[MTO_MAX_FRAG_TH_LEVELS][MTO_MAX_DATA_RATE_LEVELS] =
63{
64 { 0, 1282, 630, 404, 288, 444, 232, 172, 144, 116, 100, 96},
65 { 0, 1794, 817, 572, 400, 537, 316, 228, 188, 144, 124, 116},
66 { 0, 2306, 1003, 744, 516, 630, 400, 288, 228, 172, 144, 136},
67 { 0, 3330, 1375, 1084, 744, 817, 572, 400, 316, 228, 188, 172},
68 { 0, 6402, 2492, 2108, 1424, 1375, 1084, 740, 572, 400, 316, 284}
69};
70
71#define MTO_ONE_EXCHANGE_TIME(preamble_type, frag_th_lvl, data_rate_lvl) \
72 (preamble_type) ? MTO_One_Exchange_Time_Tbl_s[frag_th_lvl][data_rate_lvl] : \
73 MTO_One_Exchange_Time_Tbl_l[frag_th_lvl][data_rate_lvl]
74
75// Declare data rate table
76//The following table will be changed at anytime if the opration rate supported by AP don't
77//match the table
78u8 MTO_Data_Rate_Tbl[MTO_MAX_DATA_RATE_LEVELS] =
79{
80 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
81};
82
83//The Stardard_Data_Rate_Tbl and Level2PerTbl table is used to indirectly retreive PER
84//information from Rate_PER_TBL
85//The default settings is AP can support full rate set.
86static u8 Stardard_Data_Rate_Tbl[MTO_MAX_DATA_RATE_LEVELS] =
87{
88 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
89};
90static u8 Level2PerTbl[MTO_MAX_DATA_RATE_LEVELS] =
91{
92 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
93};
94//How many kind of tx rate can be supported by AP
95//DTO will change Rate between MTO_Data_Rate_Tbl[0] and MTO_Data_Rate_Tbl[MTO_DataRateAvailableLevel-1]
96static u8 MTO_DataRateAvailableLevel = MTO_MAX_DATA_RATE_LEVELS;
97//Smoothed PER table for each different RATE based on packet length of 1514
98static int Rate_PER_TBL[91][MTO_MAX_DATA_RATE_LEVELS] = {
99// 1M 2M 5.5M 11M 6M 9M 12M 18M 24M 36M 48M 54M
100/* 0% */{ 93, 177, 420, 538, 690, 774, 1001, 1401, 1768, 2358, 2838, 3039},
101/* 1% */{ 92, 176, 416, 533, 683, 767, 992, 1389, 1752, 2336, 2811, 3010},
102/* 2% */{ 91, 174, 412, 528, 675, 760, 983, 1376, 1735, 2313, 2783, 2979},
103/* 3% */{ 90, 172, 407, 523, 667, 753, 973, 1363, 1719, 2290, 2755, 2948},
104/* 4% */{ 90, 170, 403, 518, 659, 746, 964, 1350, 1701, 2266, 2726, 2916},
105/* 5% */{ 89, 169, 398, 512, 651, 738, 954, 1336, 1684, 2242, 2696, 2884},
106/* 6% */{ 88, 167, 394, 507, 643, 731, 944, 1322, 1666, 2217, 2665, 2851},
107/* 7% */{ 87, 165, 389, 502, 635, 723, 935, 1308, 1648, 2192, 2634, 2817},
108/* 8% */{ 86, 163, 384, 497, 626, 716, 924, 1294, 1629, 2166, 2602, 2782},
109/* 9% */{ 85, 161, 380, 491, 618, 708, 914, 1279, 1611, 2140, 2570, 2747},
110/* 10% */{ 84, 160, 375, 486, 609, 700, 904, 1265, 1591, 2113, 2537, 2711},
111/* 11% */{ 83, 158, 370, 480, 600, 692, 894, 1250, 1572, 2086, 2503, 2675},
112/* 12% */{ 82, 156, 365, 475, 592, 684, 883, 1234, 1552, 2059, 2469, 2638},
113/* 13% */{ 81, 154, 360, 469, 583, 676, 872, 1219, 1532, 2031, 2435, 2600},
114/* 14% */{ 80, 152, 355, 464, 574, 668, 862, 1204, 1512, 2003, 2400, 2562},
115/* 15% */{ 79, 150, 350, 458, 565, 660, 851, 1188, 1492, 1974, 2365, 2524},
116/* 16% */{ 78, 148, 345, 453, 556, 652, 840, 1172, 1471, 1945, 2329, 2485},
117/* 17% */{ 77, 146, 340, 447, 547, 643, 829, 1156, 1450, 1916, 2293, 2446},
118/* 18% */{ 76, 144, 335, 441, 538, 635, 818, 1140, 1429, 1887, 2256, 2406},
119/* 19% */{ 75, 143, 330, 436, 529, 627, 807, 1124, 1408, 1857, 2219, 2366},
120/* 20% */{ 74, 141, 325, 430, 520, 618, 795, 1107, 1386, 1827, 2182, 2326},
121/* 21% */{ 73, 139, 320, 424, 510, 610, 784, 1091, 1365, 1797, 2145, 2285},
122/* 22% */{ 72, 137, 314, 418, 501, 601, 772, 1074, 1343, 1766, 2107, 2244},
123/* 23% */{ 71, 135, 309, 412, 492, 592, 761, 1057, 1321, 1736, 2069, 2203},
124/* 24% */{ 70, 133, 304, 407, 482, 584, 749, 1040, 1299, 1705, 2031, 2161},
125/* 25% */{ 69, 131, 299, 401, 473, 575, 738, 1023, 1277, 1674, 1992, 2120},
126/* 26% */{ 68, 129, 293, 395, 464, 566, 726, 1006, 1254, 1642, 1953, 2078},
127/* 27% */{ 67, 127, 288, 389, 454, 557, 714, 989, 1232, 1611, 1915, 2035},
128/* 28% */{ 66, 125, 283, 383, 445, 549, 703, 972, 1209, 1579, 1876, 1993},
129/* 29% */{ 65, 123, 278, 377, 436, 540, 691, 955, 1187, 1548, 1836, 1951},
130/* 30% */{ 64, 121, 272, 371, 426, 531, 679, 937, 1164, 1516, 1797, 1908},
131/* 31% */{ 63, 119, 267, 365, 417, 522, 667, 920, 1141, 1484, 1758, 1866},
132/* 32% */{ 62, 117, 262, 359, 407, 513, 655, 902, 1118, 1453, 1719, 1823},
133/* 33% */{ 61, 115, 256, 353, 398, 504, 643, 885, 1095, 1421, 1679, 1781},
134/* 34% */{ 60, 113, 251, 347, 389, 495, 631, 867, 1072, 1389, 1640, 1738},
135/* 35% */{ 59, 111, 246, 341, 379, 486, 619, 850, 1049, 1357, 1600, 1695},
136/* 36% */{ 58, 108, 240, 335, 370, 477, 607, 832, 1027, 1325, 1561, 1653},
137/* 37% */{ 57, 106, 235, 329, 361, 468, 595, 815, 1004, 1293, 1522, 1610},
138/* 38% */{ 56, 104, 230, 323, 351, 459, 584, 797, 981, 1261, 1483, 1568},
139/* 39% */{ 55, 102, 224, 317, 342, 450, 572, 780, 958, 1230, 1443, 1526},
140/* 40% */{ 54, 100, 219, 311, 333, 441, 560, 762, 935, 1198, 1404, 1484},
141/* 41% */{ 53, 98, 214, 305, 324, 432, 548, 744, 912, 1166, 1366, 1442},
142/* 42% */{ 52, 96, 209, 299, 315, 423, 536, 727, 889, 1135, 1327, 1400},
143/* 43% */{ 51, 94, 203, 293, 306, 414, 524, 709, 866, 1104, 1289, 1358},
144/* 44% */{ 50, 92, 198, 287, 297, 405, 512, 692, 844, 1072, 1250, 1317},
145/* 45% */{ 49, 90, 193, 281, 288, 396, 500, 675, 821, 1041, 1212, 1276},
146/* 46% */{ 48, 88, 188, 275, 279, 387, 488, 657, 799, 1011, 1174, 1236},
147/* 47% */{ 47, 86, 183, 269, 271, 378, 476, 640, 777, 980, 1137, 1195},
148/* 48% */{ 46, 84, 178, 262, 262, 369, 464, 623, 754, 949, 1100, 1155},
149/* 49% */{ 45, 82, 173, 256, 254, 360, 452, 606, 732, 919, 1063, 1116},
150/* 50% */{ 44, 80, 168, 251, 245, 351, 441, 589, 710, 889, 1026, 1076},
151/* 51% */{ 43, 78, 163, 245, 237, 342, 429, 572, 689, 860, 990, 1038},
152/* 52% */{ 42, 76, 158, 239, 228, 333, 417, 555, 667, 830, 955, 999},
153/* 53% */{ 41, 74, 153, 233, 220, 324, 406, 538, 645, 801, 919, 961},
154/* 54% */{ 40, 72, 148, 227, 212, 315, 394, 522, 624, 773, 884, 924},
155/* 55% */{ 39, 70, 143, 221, 204, 307, 383, 505, 603, 744, 850, 887},
156/* 56% */{ 38, 68, 138, 215, 196, 298, 371, 489, 582, 716, 816, 851},
157/* 57% */{ 37, 67, 134, 209, 189, 289, 360, 473, 562, 688, 783, 815},
158/* 58% */{ 36, 65, 129, 203, 181, 281, 349, 457, 541, 661, 750, 780},
159/* 59% */{ 35, 63, 124, 197, 174, 272, 338, 441, 521, 634, 717, 745},
160/* 60% */{ 34, 61, 120, 192, 166, 264, 327, 425, 501, 608, 686, 712},
161/* 61% */{ 33, 59, 115, 186, 159, 255, 316, 409, 482, 582, 655, 678},
162/* 62% */{ 32, 57, 111, 180, 152, 247, 305, 394, 462, 556, 624, 646},
163/* 63% */{ 31, 55, 107, 174, 145, 238, 294, 379, 443, 531, 594, 614},
164/* 64% */{ 30, 53, 102, 169, 138, 230, 283, 364, 425, 506, 565, 583},
165/* 65% */{ 29, 52, 98, 163, 132, 222, 273, 349, 406, 482, 536, 553},
166/* 66% */{ 28, 50, 94, 158, 125, 214, 262, 334, 388, 459, 508, 523},
167/* 67% */{ 27, 48, 90, 152, 119, 206, 252, 320, 370, 436, 481, 495},
168/* 68% */{ 26, 46, 86, 147, 113, 198, 242, 306, 353, 413, 455, 467},
169/* 69% */{ 26, 44, 82, 141, 107, 190, 231, 292, 336, 391, 429, 440},
170/* 70% */{ 25, 43, 78, 136, 101, 182, 221, 278, 319, 370, 405, 414},
171/* 71% */{ 24, 41, 74, 130, 95, 174, 212, 265, 303, 350, 381, 389},
172/* 72% */{ 23, 39, 71, 125, 90, 167, 202, 252, 287, 329, 358, 365},
173/* 73% */{ 22, 37, 67, 119, 85, 159, 192, 239, 271, 310, 335, 342},
174/* 74% */{ 21, 36, 63, 114, 80, 151, 183, 226, 256, 291, 314, 320},
175/* 75% */{ 20, 34, 60, 109, 75, 144, 174, 214, 241, 273, 294, 298},
176/* 76% */{ 19, 32, 57, 104, 70, 137, 164, 202, 227, 256, 274, 278},
177/* 77% */{ 18, 31, 53, 99, 66, 130, 155, 190, 213, 239, 256, 259},
178/* 78% */{ 17, 29, 50, 94, 62, 122, 146, 178, 200, 223, 238, 241},
179/* 79% */{ 16, 28, 47, 89, 58, 115, 138, 167, 187, 208, 222, 225},
180/* 80% */{ 16, 26, 44, 84, 54, 109, 129, 156, 175, 194, 206, 209},
181/* 81% */{ 15, 24, 41, 79, 50, 102, 121, 146, 163, 180, 192, 194},
182/* 82% */{ 14, 23, 39, 74, 47, 95, 113, 136, 151, 167, 178, 181},
183/* 83% */{ 13, 21, 36, 69, 44, 89, 105, 126, 140, 155, 166, 169},
184/* 84% */{ 12, 20, 33, 64, 41, 82, 97, 116, 130, 144, 155, 158},
185/* 85% */{ 11, 19, 31, 60, 39, 76, 89, 107, 120, 134, 145, 149},
186/* 86% */{ 11, 17, 29, 55, 36, 70, 82, 98, 110, 125, 136, 140},
187/* 87% */{ 10, 16, 26, 51, 34, 64, 75, 90, 102, 116, 128, 133},
188/* 88% */{ 9, 14, 24, 46, 32, 58, 68, 81, 93, 108, 121, 128},
189/* 89% */{ 8, 13, 22, 42, 31, 52, 61, 74, 86, 102, 116, 124},
190/* 90% */{ 7, 12, 21, 37, 29, 46, 54, 66, 79, 96, 112, 121}
191};
192
193#define RSSIBUF_NUM 10
194#define RSSI2RATE_SIZE 9
195
196static TXRETRY_REC TxRateRec={MTO_MAX_DATA_RATE_LEVELS - 1, 0}; //new record=>TxRateRec
197static int TxRetryRate;
198//static int SQ3, BSS_PK_CNT, NIDLESLOT, SLOT_CNT, INTERF_CNT, GAP_CNT, DS_EVM;
199static s32 RSSIBuf[RSSIBUF_NUM]={-70, -70, -70, -70, -70, -70, -70, -70, -70, -70};
200static s32 RSSISmoothed=-700;
201static int RSSIBufIndex=0;
202static u8 max_rssi_rate;
203static int rate_tbl[13] = {0,1,2,5,11,6,9,12,18,24,36,48,54};
204//[WKCHEN]static core_data_t *pMTOcore_data=NULL;
205
206static int TotalTxPkt = 0;
207static int TotalTxPktRetry = 0;
208static int TxPktPerAnt[3] = {0,0,0};
209static int RXRSSIANT[3] ={-70,-70,-70};
210static int TxPktRetryPerAnt[3] = {0,0,0};
211//static int TxDominateFlag=FALSE;
212static u8 old_antenna[4]={1 ,0 ,1 ,0};
213static int retryrate_rec[MTO_MAX_DATA_RATE_LEVELS];//this record the retry rate at different data rate
214
215static int PeriodTotalTxPkt = 0;
216static int PeriodTotalTxPktRetry = 0;
217
218typedef struct
219{
220 s32 RSSI;
221 u8 TxRate;
222}RSSI2RATE;
223
224static RSSI2RATE RSSI2RateTbl[RSSI2RATE_SIZE] =
225{
226 {-740, 108}, // 54M
227 {-760, 96}, // 48M
228 {-820, 72}, // 36M
229 {-850, 48}, // 24M
230 {-870, 36}, // 18M
231 {-890, 24}, // 12M
232 {-900, 12}, // 6M
233 {-920, 11}, // 5.5M
234 {-950, 4}, // 2M
235};
236static u8 untogglecount;
237static u8 last_rate_ant; //this is used for antenna backoff-hh
238
239u8 boSparseTxTraffic = FALSE;
240
241void MTO_Init(MTO_FUNC_INPUT);
242void AntennaToggleInitiator(MTO_FUNC_INPUT);
243void AntennaToggleState(MTO_FUNC_INPUT);
244void TxPwrControl(MTO_FUNC_INPUT);
245void GetFreshAntennaData(MTO_FUNC_INPUT);
246void TxRateReductionCtrl(MTO_FUNC_INPUT);
247/** 1.1.31.1000 Turbo modify */
248//void MTO_SetDTORateRange(int type);
249void MTO_SetDTORateRange(MTO_FUNC_INPUT, u8 *pRateArray, u8 ArraySize);
250void MTO_SetTxCount(MTO_FUNC_INPUT, u8 t0, u8 index);
251void MTO_TxFailed(MTO_FUNC_INPUT);
252void SmoothRSSI(s32 new_rssi);
253void hal_get_dto_para(MTO_FUNC_INPUT, char *buffer);
254u8 CalcNewRate(MTO_FUNC_INPUT, u8 old_rate, u32 retry_cnt, u32 tx_frag_cnt);
255u8 GetMaxRateLevelFromRSSI(void);
256u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT);
257int Divide(int a, int b);
258void multiagc(MTO_FUNC_INPUT, u8 high_gain_mode);
259
260//===========================================================================
261// MTO_Init --
262//
263// Description:
264// Set DTO Tx Rate Scope because different AP could have different Rate set.
265// After our staion join with AP, LM core will call this function to initialize
266// Tx Rate table.
267//
268// Arguments:
269// pRateArray - The pointer to the Tx Rate Array by the following order
270// - 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
271// - DTO won't check whether rate order is invalid or not
272// ArraySize - The array size to indicate how many tx rate we can choose
273//
274// sample code:
275// {
276// u8 RateArray[4] = {2, 4, 11, 22};
277// MTO_SetDTORateRange(RateArray, 4);
278// }
279//
280// Return Value:
281// None
282//============================================================================
283void MTO_SetDTORateRange(MTO_FUNC_INPUT,u8 *pRateArray, u8 ArraySize)
284{
285 u8 i, j=0;
286
287 for(i=0;i<ArraySize;i++)
288 {
289 if(pRateArray[i] == 22)
290 break;
291 }
292 if(i < ArraySize) //we need adjust the order of rate list because 11Mbps rate exists
293 {
294 for(;i>0;i--)
295 {
296 if(pRateArray[i-1] <= 11)
297 break;
298 pRateArray[i] = pRateArray[i-1];
299 }
300 pRateArray[i] = 22;
301 MTO_OFDM_RATE_LEVEL() = i;
302 }
303 else
304 {
305 for(i=0; i<ArraySize; i++)
306 {
307 if (pRateArray[i] >= 12)
308 break;
309 }
310 MTO_OFDM_RATE_LEVEL() = i;
311 }
312
313 for(i=0;i<ArraySize;i++)
314 {
315 MTO_Data_Rate_Tbl[i] = pRateArray[i];
316 for(;j<MTO_MAX_DATA_RATE_LEVELS;j++)
317 {
318 if(Stardard_Data_Rate_Tbl[j] == pRateArray[i])
319 break;
320 }
321 Level2PerTbl[i] = j;
322 #ifdef _PE_DTO_DUMP_
323 WBDEBUG(("[MTO]:Op Rate[%d]: %d\n",i, MTO_Data_Rate_Tbl[i]));
324 #endif
325 }
326 MTO_DataRateAvailableLevel = ArraySize;
327 if( MTO_DATA().RatePolicy ) // 0 means that no registry setting
328 {
329 if( MTO_DATA().RatePolicy == 1 )
330 TxRateRec.tx_rate = 0; //ascent
331 else
332 TxRateRec.tx_rate = MTO_DataRateAvailableLevel -1 ; //descent
333 }
334 else
335 {
336 if( MTO_INITTXRATE_MODE )
337 TxRateRec.tx_rate = 0; //ascent
338 else
339 TxRateRec.tx_rate = MTO_DataRateAvailableLevel -1 ; //descent
340 }
341 TxRateRec.tx_retry_rate = 0;
342 //set default rate for initial use
343 MTO_RATE_LEVEL() = TxRateRec.tx_rate;
344 MTO_FALLBACK_RATE_LEVEL() = MTO_RATE_LEVEL();
345}
346
347//===========================================================================
348// MTO_Init --
349//
350// Description:
351// Initialize MTO parameters.
352//
353// This function should be invoked during system initialization.
354//
355// Arguments:
356// Adapter - The pointer to the Miniport Adapter Context
357//
358// Return Value:
359// None
360//============================================================================
361void MTO_Init(MTO_FUNC_INPUT)
362{
363 int i;
364 //WBDEBUG(("[MTO] -> MTO_Init()\n"));
365 //[WKCHEN]pMTOcore_data = pcore_data;
366// 20040510 Turbo add for global variable
367 MTO_TMR_CNT() = 0;
368 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
369 MTO_TX_RATE_REDUCTION_STATE() = RATE_CHGSTATE_IDLE;
370 MTO_BACKOFF_TMR() = 0;
371 MTO_LAST_RATE() = 11;
372 MTO_CO_EFFICENT() = 0;
373
374 //MTO_TH_FIXANT() = MTO_DEFAULT_TH_FIXANT;
375 MTO_TH_CNT() = MTO_DEFAULT_TH_CNT;
376 MTO_TH_SQ3() = MTO_DEFAULT_TH_SQ3;
377 MTO_TH_IDLE_SLOT() = MTO_DEFAULT_TH_IDLE_SLOT;
378 MTO_TH_PR_INTERF() = MTO_DEFAULT_TH_PR_INTERF;
379
380 MTO_TMR_AGING() = MTO_DEFAULT_TMR_AGING;
381 MTO_TMR_PERIODIC() = MTO_DEFAULT_TMR_PERIODIC;
382
383 //[WKCHEN]MTO_CCA_MODE_SETUP()= (u8) hal_get_cca_mode(MTO_HAL());
384 //[WKCHEN]MTO_CCA_MODE() = MTO_CCA_MODE_SETUP();
385
386 //MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_LONG;
387 MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_SHORT; // for test
388
389 MTO_ANT_SEL() = hal_get_antenna_number(MTO_HAL());
390 MTO_ANT_MAC() = MTO_ANT_SEL();
391 MTO_CNT_ANT(0) = 0;
392 MTO_CNT_ANT(1) = 0;
393 MTO_SQ_ANT(0) = 0;
394 MTO_SQ_ANT(1) = 0;
395 MTO_ANT_DIVERSITY() = MTO_ANTENNA_DIVERSITY_ON;
396 //CardSet_AntennaDiversity(Adapter, MTO_ANT_DIVERSITY());
397 //PLMESetAntennaDiversity( Adapter, MTO_ANT_DIVERSITY());
398
399 MTO_AGING_TIMEOUT() = 0;//MTO_TMR_AGING() / MTO_TMR_PERIODIC();
400
401 // The following parameters should be initialized to the values set by user
402 //
403 //MTO_RATE_LEVEL() = 10;
404 MTO_RATE_LEVEL() = 0;
405 MTO_FALLBACK_RATE_LEVEL() = MTO_RATE_LEVEL();
406 MTO_FRAG_TH_LEVEL() = 4;
407 /** 1.1.23.1000 Turbo modify from -1 to +1
408 MTO_RTS_THRESHOLD() = MTO_FRAG_TH() - 1;
409 MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() - 1;
410 */
411 MTO_RTS_THRESHOLD() = MTO_FRAG_TH() + 1;
412 MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() + 1;
413 // 1.1.23.1000 Turbo add for mto change preamble from 0 to 1
414 MTO_RATE_CHANGE_ENABLE() = 1;
415 MTO_FRAG_CHANGE_ENABLE() = 0; // 1.1.29.1000 Turbo add don't support frag
416 //The default valud of ANTDIV_DEFAULT_ON will be decided by EEPROM
417 //#ifdef ANTDIV_DEFAULT_ON
418 //MTO_ANT_DIVERSITY_ENABLE() = 1;
419 //#else
420 //MTO_ANT_DIVERSITY_ENABLE() = 0;
421 //#endif
422 MTO_POWER_CHANGE_ENABLE() = 1;
423 MTO_PREAMBLE_CHANGE_ENABLE()= 1;
424 MTO_RTS_CHANGE_ENABLE() = 0; // 1.1.29.1000 Turbo add don't support frag
425 // 20040512 Turbo add
426 //old_antenna[0] = 1;
427 //old_antenna[1] = 0;
428 //old_antenna[2] = 1;
429 //old_antenna[3] = 0;
430 for (i=0;i<MTO_MAX_DATA_RATE_LEVELS;i++)
431 retryrate_rec[i]=5;
432
433 MTO_TXFLOWCOUNT() = 0;
434 //--------- DTO threshold parameters -------------
435 //MTOPARA_PERIODIC_CHECK_CYCLE() = 50;
436 MTOPARA_PERIODIC_CHECK_CYCLE() = 10;
437 MTOPARA_RSSI_TH_FOR_ANTDIV() = 10;
438 MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() = 50;
439 MTOPARA_TXRATE_INC_TH() = 10;
440 MTOPARA_TXRATE_DEC_TH() = 30;
441 MTOPARA_TXRATE_EQ_TH() = 40;
442 MTOPARA_TXRATE_BACKOFF() = 12;
443 MTOPARA_TXRETRYRATE_REDUCE() = 6;
444 if ( MTO_TXPOWER_FROM_EEPROM == 0xff)
445 {
446 switch( MTO_HAL()->phy_type)
447 {
448 case RF_AIROHA_2230:
449 case RF_AIROHA_2230S: // 20060420 Add this
450 MTOPARA_TXPOWER_INDEX() = 46; // MAX-8 // @@ Only for AL 2230
451 break;
452 case RF_AIROHA_7230:
453 MTOPARA_TXPOWER_INDEX() = 49;
454 break;
455 case RF_WB_242:
456 MTOPARA_TXPOWER_INDEX() = 10;
457 break;
458 case RF_WB_242_1:
459 MTOPARA_TXPOWER_INDEX() = 24; // ->10 20060316.1 modify
460 break;
461 }
462 }
463 else //follow the setting from EEPROM
464 MTOPARA_TXPOWER_INDEX() = MTO_TXPOWER_FROM_EEPROM;
465 hal_set_rf_power(MTO_HAL(), (u8)MTOPARA_TXPOWER_INDEX());
466 //------------------------------------------------
467
468 // For RSSI turning 20060808.4 Cancel load from EEPROM
469 MTO_DATA().RSSI_high = -41;
470 MTO_DATA().RSSI_low = -60;
471}
472
473//---------------------------------------------------------------------------//
474static u32 DTO_Rx_Info[13][3];
475static u32 DTO_RxCRCFail_Info[13][3];
476static u32 AntennaToggleBkoffTimer=5;
477typedef struct{
478 int RxRate;
479 int RxRatePkts;
480 int index;
481}RXRATE_ANT;
482RXRATE_ANT RxRatePeakAnt[3];
483
484#define ANT0 0
485#define ANT1 1
486#define OLD_ANT 2
487
488void SearchPeakRxRate(int index)
489{
490 int i;
491 RxRatePeakAnt[index].RxRatePkts=0;
492 //Find out the best rx rate which is used on different antenna
493 for(i=1;i<13;i++)
494 {
495 if(DTO_Rx_Info[i][index] > (u32) RxRatePeakAnt[index].RxRatePkts)
496 {
497 RxRatePeakAnt[index].RxRatePkts = DTO_Rx_Info[i][index];
498 RxRatePeakAnt[index].RxRate = rate_tbl[i];
499 RxRatePeakAnt[index].index = i;
500 }
501 }
502}
503
504void ResetDTO_RxInfo(int index, MTO_FUNC_INPUT)
505{
506 int i;
507
508 #ifdef _PE_DTO_DUMP_
509 WBDEBUG(("ResetDTOrx\n"));
510 #endif
511
512 for(i=0;i<13;i++)
513 DTO_Rx_Info[i][index] = MTO_HAL()->rx_ok_count[i];
514
515 for(i=0;i<13;i++)
516 DTO_RxCRCFail_Info[i][index] = MTO_HAL()->rx_err_count[i];
517
518 TotalTxPkt = 0;
519 TotalTxPktRetry = 0;
520}
521
522void GetDTO_RxInfo(int index, MTO_FUNC_INPUT)
523{
524 int i;
525
526 #ifdef _PE_DTO_DUMP_
527 WBDEBUG(("GetDTOrx\n"));
528 #endif
529
530 //PDEBUG(("[MTO]:DTO_Rx_Info[%d]=%d, rx_ok_count=%d\n", index, DTO_Rx_Info[0][index], phw_data->rx_ok_count[0]));
531 for(i=0;i<13;i++)
532 DTO_Rx_Info[i][index] = abs(MTO_HAL()->rx_ok_count[i] - DTO_Rx_Info[i][index]);
533 if(DTO_Rx_Info[0][index]==0) DTO_Rx_Info[0][index] = 1;
534
535 for(i=0;i<13;i++)
536 DTO_RxCRCFail_Info[i][index] = MTO_HAL()->rx_err_count[i] - DTO_RxCRCFail_Info[i][index];
537
538 TxPktPerAnt[index] = TotalTxPkt;
539 TxPktRetryPerAnt[index] = TotalTxPktRetry;
540 TotalTxPkt = 0;
541 TotalTxPktRetry = 0;
542}
543
544void OutputDebugInfo(int index1, int index2)
545{
546 #ifdef _PE_DTO_DUMP_
547 WBDEBUG(("[HHDTO]:Total Rx (%d)\t\t(%d) \n ", DTO_Rx_Info[0][index1], DTO_Rx_Info[0][index2]));
548 WBDEBUG(("[HHDTO]:RECEIVE RSSI: (%d)\t\t(%d) \n ", RXRSSIANT[index1], RXRSSIANT[index2]));
549 WBDEBUG(("[HHDTO]:TX packet correct rate: (%d)%%\t\t(%d)%% \n ",Divide(TxPktPerAnt[index1]*100,TxPktRetryPerAnt[index1]), Divide(TxPktPerAnt[index2]*100,TxPktRetryPerAnt[index2])));
550 #endif
551 {
552 int tmp1, tmp2;
553 #ifdef _PE_DTO_DUMP_
554 WBDEBUG(("[HHDTO]:Total Tx (%d)\t\t(%d) \n ", TxPktPerAnt[index1], TxPktPerAnt[index2]));
555 WBDEBUG(("[HHDTO]:Total Tx retry (%d)\t\t(%d) \n ", TxPktRetryPerAnt[index1], TxPktRetryPerAnt[index2]));
556 #endif
557 tmp1 = TxPktPerAnt[index1] + DTO_Rx_Info[0][index1];
558 tmp2 = TxPktPerAnt[index2] + DTO_Rx_Info[0][index2];
559 #ifdef _PE_DTO_DUMP_
560 WBDEBUG(("[HHDTO]:Total Tx+RX (%d)\t\t(%d) \n ", tmp1, tmp2));
561 #endif
562 }
563}
564
565unsigned char TxDominate(int index)
566{
567 int tmp;
568
569 tmp = TxPktPerAnt[index] + DTO_Rx_Info[0][index];
570
571 if(Divide(TxPktPerAnt[index]*100, tmp) > 40)
572 return TRUE;
573 else
574 return FALSE;
575}
576
577unsigned char CmpTxRetryRate(int index1, int index2)
578{
579 int tx_retry_rate1, tx_retry_rate2;
580 tx_retry_rate1 = Divide((TxPktRetryPerAnt[index1] - TxPktPerAnt[index1])*100, TxPktRetryPerAnt[index1]);
581 tx_retry_rate2 = Divide((TxPktRetryPerAnt[index2] - TxPktPerAnt[index2])*100, TxPktRetryPerAnt[index2]);
582 #ifdef _PE_DTO_DUMP_
583 WBDEBUG(("[MTO]:TxRetry Ant0: (%d%%) Ant1: (%d%%) \n ", tx_retry_rate1, tx_retry_rate2));
584 #endif
585
586 if(tx_retry_rate1 > tx_retry_rate2)
587 return TRUE;
588 else
589 return FALSE;
590}
591
592void GetFreshAntennaData(MTO_FUNC_INPUT)
593{
594 u8 x;
595
596 x = hal_get_antenna_number(MTO_HAL());
597 //hal_get_bss_pk_cnt(MTO_HAL());
598 //hal_get_est_sq3(MTO_HAL(), 1);
599 old_antenna[0] = x;
600 //if this is the function for timer
601 ResetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
602 if(AntennaToggleBkoffTimer)
603 AntennaToggleBkoffTimer--;
604 if (abs(last_rate_ant-MTO_RATE_LEVEL())>1) //backoff timer reset
605 AntennaToggleBkoffTimer=0;
606
607 if (MTO_ANT_DIVERSITY() != MTO_ANTENNA_DIVERSITY_ON ||
608 MTO_ANT_DIVERSITY_ENABLE() != 1)
609 AntennaToggleBkoffTimer=1;
610 #ifdef _PE_DTO_DUMP_
611 WBDEBUG(("[HHDTO]:**last data rate=%d,now data rate=%d**antenna toggle timer=%d",last_rate_ant,MTO_RATE_LEVEL(),AntennaToggleBkoffTimer));
612 #endif
613 last_rate_ant=MTO_RATE_LEVEL();
614 if(AntennaToggleBkoffTimer==0)
615 {
616 MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT0;
617 #ifdef _PE_DTO_DUMP_
618 WBDEBUG(("[HHDTO]:===state is starting==for antenna toggle==="));
619 #endif
620 }
621 else
622 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
623
624 if ((MTO_BACKOFF_TMR()!=0)&&(MTO_RATE_LEVEL()>MTO_DataRateAvailableLevel - 3))
625 {
626 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
627 #ifdef _PE_DTO_DUMP_
628 WBDEBUG(("[HHDTO]:===the data rate is %d (good)and will not toogle ===",MTO_DATA_RATE()>>1));
629 #endif
630 }
631
632
633}
634
635int WB_PCR[2]; //packet correct rate
636
637void AntennaToggleState(MTO_FUNC_INPUT)
638{
639 int decideantflag = 0;
640 u8 x;
641 s32 rssi;
642
643 if(MTO_ANT_DIVERSITY_ENABLE() != 1)
644 return;
645 x = hal_get_antenna_number(MTO_HAL());
646 switch(MTO_TOGGLE_STATE())
647 {
648
649 //Missing.....
650 case TOGGLE_STATE_IDLE:
651 case TOGGLE_STATE_BKOFF:
652 break;;
653
654 case TOGGLE_STATE_WAIT0://========
655 GetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
656 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
657 RXRSSIANT[x] = rssi;
658 #ifdef _PE_DTO_DUMP_
659 WBDEBUG(("[HHDTO] **wait0==== Collecting Ant%d--rssi=%d\n", x,RXRSSIANT[x]));
660 #endif
661
662 //change antenna and reset the data at changed antenna
663 x = (~x) & 0x01;
664 MTO_ANT_SEL() = x;
665 hal_set_antenna_number(MTO_HAL(), MTO_ANT_SEL());
666 LOCAL_ANTENNA_NO() = x;
667
668 MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT1;//go to wait1
669 ResetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
670 break;
671 case TOGGLE_STATE_WAIT1://=====wait1
672 //MTO_CNT_ANT(x) = hal_get_bss_pk_cnt(MTO_HAL());
673 //RXRSSIANT[x] = hal_get_rssi(MTO_HAL());
674 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
675 RXRSSIANT[x] = rssi;
676 GetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
677 #ifdef _PE_DTO_DUMP_
678 WBDEBUG(("[HHDTO] **wait1==== Collecting Ant%d--rssi=%d\n", x,RXRSSIANT[x]));
679 #endif
680 MTO_TOGGLE_STATE() = TOGGLE_STATE_MAKEDESISION;
681 break;
682 case TOGGLE_STATE_MAKEDESISION:
683 #ifdef _PE_DTO_DUMP_
684 WBDEBUG(("[HHDTO]:Ant--0-----------------1---\n"));
685 OutputDebugInfo(ANT0,ANT1);
686 #endif
687 //PDEBUG(("[HHDTO] **decision====\n "));
688
689 //=====following is the decision produrce
690 //
691 // first: compare the rssi if difference >10
692 // select the larger one
693 // ,others go to second
694 // second: comapre the tx+rx packet count if difference >100
695 // use larger total packets antenna
696 // third::compare the tx PER if packets>20
697 // if difference >5% using the bigger one
698 //
699 // fourth:compare the RX PER if packets>20
700 // if PER difference <5%
701 // using old antenna
702 //
703 //
704 if (abs(RXRSSIANT[ANT0]-RXRSSIANT[ANT1]) > MTOPARA_RSSI_TH_FOR_ANTDIV())//====rssi_th
705 {
706 if (RXRSSIANT[ANT0]>RXRSSIANT[ANT1])
707 {
708 decideantflag=1;
709 MTO_ANT_MAC() = ANT0;
710 }
711 else
712 {
713 decideantflag=1;
714 MTO_ANT_MAC() = ANT1;
715 }
716 #ifdef _PE_DTO_DUMP_
717 WBDEBUG(("Select antenna by RSSI\n"));
718 #endif
719 }
720 else if (abs(TxPktPerAnt[ANT0] + DTO_Rx_Info[0][ANT0]-TxPktPerAnt[ANT1]-DTO_Rx_Info[0][ANT1])<50)//=====total packet_th
721 {
722 #ifdef _PE_DTO_DUMP_
723 WBDEBUG(("Total tx/rx is close\n"));
724 #endif
725 if (TxDominate(ANT0) && TxDominate(ANT1))
726 {
727 if ((TxPktPerAnt[ANT0]>10) && (TxPktPerAnt[ANT1]>10))//====tx packet_th
728 {
729 WB_PCR[ANT0]=Divide(TxPktPerAnt[ANT0]*100,TxPktRetryPerAnt[ANT0]);
730 WB_PCR[ANT1]=Divide(TxPktPerAnt[ANT1]*100,TxPktRetryPerAnt[ANT1]);
731 if (abs(WB_PCR[ANT0]-WB_PCR[ANT1])>5)// tx PER_th
732 {
733 #ifdef _PE_DTO_DUMP_
734 WBDEBUG(("Decide by Tx correct rate\n"));
735 #endif
736 if (WB_PCR[ANT0]>WB_PCR[ANT1])
737 {
738 decideantflag=1;
739 MTO_ANT_MAC() = ANT0;
740 }
741 else
742 {
743 decideantflag=1;
744 MTO_ANT_MAC() = ANT1;
745 }
746 }
747 else
748 {
749 decideantflag=0;
750 untogglecount++;
751 MTO_ANT_MAC() = old_antenna[0];
752 }
753 }
754 else
755 {
756 decideantflag=0;
757 MTO_ANT_MAC() = old_antenna[0];
758 }
759 }
760 else if ((DTO_Rx_Info[0][ANT0]>10)&&(DTO_Rx_Info[0][ANT1]>10))//rx packet th
761 {
762 #ifdef _PE_DTO_DUMP_
763 WBDEBUG(("Decide by Rx\n"));
764 #endif
765 if (abs(DTO_Rx_Info[0][ANT0] - DTO_Rx_Info[0][ANT1])>50)
766 {
767 if (DTO_Rx_Info[0][ANT0] > DTO_Rx_Info[0][ANT1])
768 {
769 decideantflag=1;
770 MTO_ANT_MAC() = ANT0;
771 }
772 else
773 {
774 decideantflag=1;
775 MTO_ANT_MAC() = ANT1;
776 }
777 }
778 else
779 {
780 decideantflag=0;
781 untogglecount++;
782 MTO_ANT_MAC() = old_antenna[0];
783 }
784 }
785 else
786 {
787 decideantflag=0;
788 MTO_ANT_MAC() = old_antenna[0];
789 }
790 }
791 else if ((TxPktPerAnt[ANT0]+DTO_Rx_Info[0][ANT0])>(TxPktPerAnt[ANT1]+DTO_Rx_Info[0][ANT1]))//use more packekts
792 {
793 #ifdef _PE_DTO_DUMP_
794 WBDEBUG(("decide by total tx/rx : ANT 0\n"));
795 #endif
796
797 decideantflag=1;
798 MTO_ANT_MAC() = ANT0;
799 }
800 else
801 {
802 #ifdef _PE_DTO_DUMP_
803 WBDEBUG(("decide by total tx/rx : ANT 1\n"));
804 #endif
805 decideantflag=1;
806 MTO_ANT_MAC() = ANT1;
807
808 }
809 //this is force ant toggle
810 if (decideantflag==1)
811 untogglecount=0;
812
813 untogglecount=untogglecount%4;
814 if (untogglecount==3) //change antenna
815 MTO_ANT_MAC() = ((~old_antenna[0]) & 0x1);
816 #ifdef _PE_DTO_DUMP_
817 WBDEBUG(("[HHDTO]:==================untoggle-count=%d",untogglecount));
818 #endif
819
820
821
822
823 //PDEBUG(("[HHDTO] **********************************DTO ENABLE=%d",MTO_ANT_DIVERSITY_ENABLE()));
824 if(MTO_ANT_DIVERSITY_ENABLE() == 1)
825 {
826 MTO_ANT_SEL() = MTO_ANT_MAC();
827 hal_set_antenna_number(MTO_HAL(), MTO_ANT_SEL());
828 LOCAL_ANTENNA_NO() = MTO_ANT_SEL();
829 #ifdef _PE_DTO_DUMP_
830 WBDEBUG(("[HHDTO] ==decision==*******antflag=%d******************selected antenna=%d\n",decideantflag,MTO_ANT_SEL()));
831 #endif
832 }
833 if (decideantflag)
834 {
835 old_antenna[3]=old_antenna[2];//store antenna info
836 old_antenna[2]=old_antenna[1];
837 old_antenna[1]=old_antenna[0];
838 old_antenna[0]= MTO_ANT_MAC();
839 }
840 #ifdef _PE_DTO_DUMP_
841 WBDEBUG(("[HHDTO]:**old antenna=[%d][%d][%d][%d]\n",old_antenna[0],old_antenna[1],old_antenna[2],old_antenna[3]));
842 #endif
843 if (old_antenna[0]!=old_antenna[1])
844 AntennaToggleBkoffTimer=0;
845 else if (old_antenna[1]!=old_antenna[2])
846 AntennaToggleBkoffTimer=1;
847 else if (old_antenna[2]!=old_antenna[3])
848 AntennaToggleBkoffTimer=2;
849 else
850 AntennaToggleBkoffTimer=4;
851
852 #ifdef _PE_DTO_DUMP_
853 WBDEBUG(("[HHDTO]:**back off timer=%d",AntennaToggleBkoffTimer));
854 #endif
855
856 ResetDTO_RxInfo(MTO_ANT_MAC(), MTO_FUNC_INPUT_DATA);
857 if (AntennaToggleBkoffTimer==0 && decideantflag)
858 MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT0;
859 else
860 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
861 break;
862 }
863
864}
865
866void multiagc(MTO_FUNC_INPUT, u8 high_gain_mode )
867{
868 s32 rssi;
869 hw_data_t *pHwData = MTO_HAL();
870
871 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
872
873 if( (RF_WB_242 == pHwData->phy_type) ||
874 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
875 {
876 if (high_gain_mode==1)
877 {
878 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230);
879 //hw_set_dxx_reg(phw_data, 0x20, 0x06C43440);
880 Wb35Reg_Write( pHwData, 0x100C, 0xF2F32232 ); // 940916 0xf8f52230 );
881 Wb35Reg_Write( pHwData, 0x1020, 0x04cb3440 ); // 940915 0x06C43440
882 }
883 else if (high_gain_mode==0)
884 {
885 //hw_set_dxx_reg(phw_data, 0x0C, 0xEEEE000D);
886 //hw_set_dxx_reg(phw_data, 0x20, 0x06c41440);
887 Wb35Reg_Write( pHwData, 0x100C, 0xEEEE000D );
888 Wb35Reg_Write( pHwData, 0x1020, 0x04cb1440 ); // 940915 0x06c41440
889 }
890 #ifdef _PE_DTO_DUMP_
891 WBDEBUG(("[HHDTOAGC] **rssi=%d, high gain mode=%d", rssi, high_gain_mode));
892 #endif
893 }
894}
895
896void TxPwrControl(MTO_FUNC_INPUT)
897{
898 s32 rssi;
899 hw_data_t *pHwData = MTO_HAL();
900
901 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
902 if( (RF_WB_242 == pHwData->phy_type) ||
903 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
904 {
905 static u8 high_gain_mode; //this is for winbond RF switch LNA
906 //using different register setting
907
908 if (high_gain_mode==1)
909 {
910 if( rssi > MTO_DATA().RSSI_high )
911 {
912 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230);
913 //hw_set_dxx_reg(phw_data, 0x20, 0x05541640);
914 high_gain_mode=0;
915 }
916 else
917 {
918 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f51830);
919 //hw_set_dxx_reg(phw_data, 0x20, 0x05543E40);
920 high_gain_mode=1;
921 }
922 }
923 else //if (high_gain_mode==0)
924 {
925 if( rssi < MTO_DATA().RSSI_low )
926 {
927 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f51830);
928 //hw_set_dxx_reg(phw_data, 0x20, 0x05543E40);
929 high_gain_mode=1;
930 }
931 else
932 {
933 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230);
934 //hw_set_dxx_reg(phw_data, 0x20, 0x05541640);
935 high_gain_mode=0;
936 }
937 }
938
939 // Always high gain 20051014. Using the initial value only.
940 multiagc(MTO_FUNC_INPUT_DATA, high_gain_mode);
941 }
942}
943
944
945u8 CalcNewRate(MTO_FUNC_INPUT, u8 old_rate, u32 retry_cnt, u32 tx_frag_cnt)
946{
947 int i;
948 u8 new_rate;
949 u32 retry_rate;
950 int TxThrouput1, TxThrouput2, TxThrouput3, BestThroupht;
951
952 if(tx_frag_cnt < MTOPARA_TXCOUNT_TH_FOR_CALC_RATE()) //too few packets transmit
953 {
954 return 0xff;
955 }
956 retry_rate = Divide(retry_cnt * 100, tx_frag_cnt);
957
958 if(retry_rate > 90) retry_rate = 90; //always truncate to 90% due to lookup table size
959 #ifdef _PE_DTO_DUMP_
960 WBDEBUG(("##### Current level =%d, Retry count =%d, Frag count =%d\n",
961 old_rate, retry_cnt, tx_frag_cnt));
962 WBDEBUG(("*##* Retry rate =%d, throughput =%d\n",
963 retry_rate, Rate_PER_TBL[retry_rate][old_rate]));
964 WBDEBUG(("TxRateRec.tx_rate =%d, Retry rate = %d, throughput = %d\n",
965 TxRateRec.tx_rate, TxRateRec.tx_retry_rate,
966 Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]]));
967 WBDEBUG(("old_rate-1 =%d, Retry rate = %d, throughput = %d\n",
968 old_rate-1, retryrate_rec[old_rate-1],
969 Rate_PER_TBL[retryrate_rec[old_rate-1]][old_rate-1]));
970 WBDEBUG(("old_rate+1 =%d, Retry rate = %d, throughput = %d\n",
971 old_rate+1, retryrate_rec[old_rate+1],
972 Rate_PER_TBL[retryrate_rec[old_rate+1]][old_rate+1]));
973 #endif
974
975 //following is for record the retry rate at the different data rate
976 if (abs(retry_rate-retryrate_rec[old_rate])<50)//---the per TH
977 retryrate_rec[old_rate] = retry_rate; //update retry rate
978 else
979 {
980 for (i=0;i<MTO_DataRateAvailableLevel;i++) //reset all retry rate
981 retryrate_rec[i]=0;
982 retryrate_rec[old_rate] = retry_rate;
983 #ifdef _PE_DTO_DUMP_
984 WBDEBUG(("Reset retry rate table\n"));
985 #endif
986 }
987
988 if(TxRateRec.tx_rate > old_rate) //Decrease Tx Rate
989 {
990 TxThrouput1 = Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]];
991 TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]];
992 if(TxThrouput1 > TxThrouput2)
993 {
994 new_rate = TxRateRec.tx_rate;
995 BestThroupht = TxThrouput1;
996 }
997 else
998 {
999 new_rate = old_rate;
1000 BestThroupht = TxThrouput2;
1001 }
1002 if((old_rate > 0) &&(retry_rate>MTOPARA_TXRATE_DEC_TH())) //Min Rate
1003 {
1004 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate-1]][Level2PerTbl[old_rate-1]];
1005 if(BestThroupht < TxThrouput3)
1006 {
1007 new_rate = old_rate - 1;
1008 #ifdef _PE_DTO_DUMP_
1009 WBDEBUG(("--------\n"));
1010 #endif
1011 BestThroupht = TxThrouput3;
1012 }
1013 }
1014 }
1015 else if(TxRateRec.tx_rate < old_rate) //Increase Tx Rate
1016 {
1017 TxThrouput1 = Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]];
1018 TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]];
1019 if(TxThrouput1 > TxThrouput2)
1020 {
1021 new_rate = TxRateRec.tx_rate;
1022 BestThroupht = TxThrouput1;
1023 }
1024 else
1025 {
1026 new_rate = old_rate;
1027 BestThroupht = TxThrouput2;
1028 }
1029 if ((old_rate < MTO_DataRateAvailableLevel - 1)&&(retry_rate<MTOPARA_TXRATE_INC_TH()))
1030 {
1031 //TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
1032 if (retryrate_rec[old_rate+1] > MTOPARA_TXRETRYRATE_REDUCE())
1033 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]-MTOPARA_TXRETRYRATE_REDUCE()][Level2PerTbl[old_rate+1]];
1034 else
1035 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
1036 if(BestThroupht < TxThrouput3)
1037 {
1038 new_rate = old_rate + 1;
1039 #ifdef _PE_DTO_DUMP_
1040 WBDEBUG(("++++++++++\n"));
1041 #endif
1042 BestThroupht = TxThrouput3;
1043 }
1044 }
1045 }
1046 else //Tx Rate no change
1047 {
1048 TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]];
1049 new_rate = old_rate;
1050 BestThroupht = TxThrouput2;
1051
1052 if (retry_rate <MTOPARA_TXRATE_EQ_TH()) //th for change higher rate
1053 {
1054 if(old_rate < MTO_DataRateAvailableLevel - 1)
1055 {
1056 //TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
1057 if (retryrate_rec[old_rate+1] > MTOPARA_TXRETRYRATE_REDUCE())
1058 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]-MTOPARA_TXRETRYRATE_REDUCE()][Level2PerTbl[old_rate+1]];
1059 else
1060 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
1061 if(BestThroupht < TxThrouput3)
1062 {
1063 new_rate = old_rate + 1;
1064 BestThroupht = TxThrouput3;
1065 #ifdef _PE_DTO_DUMP_
1066 WBDEBUG(("=++++++++++\n"));
1067 #endif
1068 }
1069 }
1070 }
1071 else
1072 if(old_rate > 0) //Min Rate
1073 {
1074 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate-1]][Level2PerTbl[old_rate-1]];
1075 if(BestThroupht < TxThrouput3)
1076 {
1077 new_rate = old_rate - 1;
1078 #ifdef _PE_DTO_DUMP_
1079 WBDEBUG(("=--------\n"));
1080 #endif
1081 BestThroupht = TxThrouput3;
1082 }
1083 }
1084 }
1085
1086 if (!LOCAL_IS_IBSS_MODE())
1087 {
1088 max_rssi_rate = GetMaxRateLevelFromRSSI();
1089 #ifdef _PE_DTO_DUMP_
1090 WBDEBUG(("[MTO]:RSSI2Rate=%d\n", MTO_Data_Rate_Tbl[max_rssi_rate]));
1091 #endif
1092 if(new_rate > max_rssi_rate)
1093 new_rate = max_rssi_rate;
1094 }
1095
1096 //save new rate;
1097 TxRateRec.tx_rate = old_rate;
1098 TxRateRec.tx_retry_rate = (u8) retry_rate;
1099 TxRetryRate = retry_rate;
1100 return new_rate;
1101}
1102
1103void SmoothRSSI(s32 new_rssi)
1104{
1105 RSSISmoothed = RSSISmoothed + new_rssi - RSSIBuf[RSSIBufIndex];
1106 RSSIBuf[RSSIBufIndex] = new_rssi;
1107 RSSIBufIndex = (RSSIBufIndex + 1) % 10;
1108}
1109
1110u8 GetMaxRateLevelFromRSSI(void)
1111{
1112 u8 i;
1113 u8 TxRate;
1114
1115 for(i=0;i<RSSI2RATE_SIZE;i++)
1116 {
1117 if(RSSISmoothed > RSSI2RateTbl[i].RSSI)
1118 break;
1119 }
1120 #ifdef _PE_DTO_DUMP_
1121 WBDEBUG(("[MTO]:RSSI=%d\n", Divide(RSSISmoothed, 10)));
1122 #endif
1123 if(i < RSSI2RATE_SIZE)
1124 TxRate = RSSI2RateTbl[i].TxRate;
1125 else
1126 TxRate = 2; //divided by 2 = 1Mbps
1127
1128 for(i=MTO_DataRateAvailableLevel-1;i>0;i--)
1129 {
1130 if(TxRate >=MTO_Data_Rate_Tbl[i])
1131 break;
1132 }
1133 return i;
1134}
1135
1136//===========================================================================
1137// Description:
1138// If we enable DTO, we will ignore the tx count with different tx rate from
1139// DTO rate. This is because when we adjust DTO tx rate, there could be some
1140// packets in the tx queue with previous tx rate
1141void MTO_SetTxCount(MTO_FUNC_INPUT, u8 tx_rate, u8 index)
1142{
1143 MTO_TXFLOWCOUNT()++;
1144 if ((MTO_ENABLE==1) && (MTO_RATE_CHANGE_ENABLE()==1))
1145 {
1146 if(tx_rate == MTO_DATA_RATE())
1147 {
1148 if (index == 0)
1149 {
1150 if (boSparseTxTraffic)
1151 MTO_HAL()->dto_tx_frag_count += MTOPARA_PERIODIC_CHECK_CYCLE();
1152 else
1153 MTO_HAL()->dto_tx_frag_count += 1;
1154 }
1155 else
1156 {
1157 if (index<8)
1158 {
1159 MTO_HAL()->dto_tx_retry_count += index;
1160 MTO_HAL()->dto_tx_frag_count += (index+1);
1161 }
1162 else
1163 {
1164 MTO_HAL()->dto_tx_retry_count += 7;
1165 MTO_HAL()->dto_tx_frag_count += 7;
1166 }
1167 }
1168 }
1169 else if(MTO_DATA_RATE()>48 && tx_rate ==48)
1170 {//ALFRED
1171 if (index<3) //for reduciing data rate scheme ,
1172 //do not calcu different data rate
1173 //3 is the reducing data rate at retry
1174 {
1175 MTO_HAL()->dto_tx_retry_count += index;
1176 MTO_HAL()->dto_tx_frag_count += (index+1);
1177 }
1178 else
1179 {
1180 MTO_HAL()->dto_tx_retry_count += 3;
1181 MTO_HAL()->dto_tx_frag_count += 3;
1182 }
1183
1184 }
1185 }
1186 else
1187 {
1188 MTO_HAL()->dto_tx_retry_count += index;
1189 MTO_HAL()->dto_tx_frag_count += (index+1);
1190 }
1191 TotalTxPkt ++;
1192 TotalTxPktRetry += (index+1);
1193
1194 PeriodTotalTxPkt ++;
1195 PeriodTotalTxPktRetry += (index+1);
1196}
1197
1198u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT)
1199{
1200 return MTO_DATA_FALLBACK_RATE();
1201}
1202
1203
1204//===========================================================================
1205// MTO_TxFailed --
1206//
1207// Description:
1208// Failure of transmitting a packet indicates that certain MTO parmeters
1209// may need to be adjusted. This function is called when NIC just failed
1210// to transmit a packet or when MSDULifeTime expired.
1211//
1212// Arguments:
1213// Adapter - The pointer to the Miniport Adapter Context
1214//
1215// Return Value:
1216// None
1217//============================================================================
1218void MTO_TxFailed(MTO_FUNC_INPUT)
1219{
1220 return;
1221}
1222
1223int Divide(int a, int b)
1224{
1225 if (b==0) b=1;
1226 return a/b;
1227}
1228
1229
diff --git a/drivers/staging/winbond/mto.h b/drivers/staging/winbond/mto.h
new file mode 100644
index 000000000000..f47936f46d1e
--- /dev/null
+++ b/drivers/staging/winbond/mto.h
@@ -0,0 +1,265 @@
1//==================================================================
2// MTO.H
3//
4// Revision history
5//=================================
6// 20030110 UN20 Pete Chao
7// Initial Release
8//
9// Copyright (c) 2003 Winbond Electronics Corp. All rights reserved.
10//==================================================================
11#ifndef __MTO_H__
12#define __MTO_H__
13
14#define MTO_DEFAULT_TH_CNT 5
15#define MTO_DEFAULT_TH_SQ3 112 //OLD IS 13 reference JohnXu
16#define MTO_DEFAULT_TH_IDLE_SLOT 15
17#define MTO_DEFAULT_TH_PR_INTERF 30
18#define MTO_DEFAULT_TMR_AGING 25 // unit: slot time 10 reference JohnXu
19#define MTO_DEFAULT_TMR_PERIODIC 5 // unit: slot time
20
21#define MTO_ANTENNA_DIVERSITY_OFF 0
22#define MTO_ANTENNA_DIVERSITY_ON 1
23
24// LA20040210_DTO kevin
25//#define MTO_PREAMBLE_LONG 0
26//#define MTO_PREAMBLE_SHORT 1
27#define MTO_PREAMBLE_LONG WLAN_PREAMBLE_TYPE_LONG
28#define MTO_PREAMBLE_SHORT WLAN_PREAMBLE_TYPE_SHORT
29
30typedef enum {
31 TOGGLE_STATE_IDLE = 0,
32 TOGGLE_STATE_WAIT0 = 1,
33 TOGGLE_STATE_WAIT1 = 2,
34 TOGGLE_STATE_MAKEDESISION = 3,
35 TOGGLE_STATE_BKOFF = 4
36} TOGGLE_STATE;
37
38typedef enum {
39 RATE_CHGSTATE_IDLE = 0,
40 RATE_CHGSTATE_CALCULATE = 1,
41 RATE_CHGSTATE_BACKOFF = 2
42} TX_RATE_REDUCTION_STATE;
43
44//============================================================================
45// struct _MTOParameters --
46//
47// Defines the parameters used in the MAC Throughput Optimization algorithm
48//============================================================================
49typedef struct _MTO_PARAMETERS
50{
51 u8 Th_Fixant;
52 u8 Th_Cnt;
53 u8 Th_SQ3;
54 u8 Th_IdleSlot;
55
56 u16 Tmr_Aging;
57 u8 Th_PrInterf;
58 u8 Tmr_Periodic;
59
60 //--------- wkchen added -------------
61 u32 TxFlowCount; //to judge what kind the tx flow(sparse or busy) is
62 //------------------------------------------------
63
64 //--------- DTO threshold parameters -------------
65 u16 DTO_PeriodicCheckCycle;
66 u16 DTO_RssiThForAntDiv;
67
68 u16 DTO_TxCountThForCalcNewRate;
69 u16 DTO_TxRateIncTh;
70
71 u16 DTO_TxRateDecTh;
72 u16 DTO_TxRateEqTh;
73
74 u16 DTO_TxRateBackOff;
75 u16 DTO_TxRetryRateReduce;
76
77 u16 DTO_TxPowerIndex; //0 ~ 31
78 u16 reserved_1;
79 //------------------------------------------------
80
81 u8 PowerChangeEnable;
82 u8 AntDiversityEnable;
83 u8 Ant_mac;
84 u8 Ant_div;
85
86 u8 CCA_Mode;
87 u8 CCA_Mode_Setup;
88 u8 Preamble_Type;
89 u8 PreambleChangeEnable;
90
91 u8 DataRateLevel;
92 u8 DataRateChangeEnable;
93 u8 FragThresholdLevel;
94 u8 FragThresholdChangeEnable;
95
96 u16 RTSThreshold;
97 u16 RTSThreshold_Setup;
98
99 u32 AvgIdleSlot;
100 u32 Pr_Interf;
101 u32 AvgGapBtwnInterf;
102
103 u8 RTSChangeEnable;
104 u8 Ant_sel;
105 u8 aging_timeout;
106 u8 reserved_2;
107
108 u32 Cnt_Ant[2];
109 u32 SQ_Ant[2];
110
111// 20040510 remove from globe vairable
112 u32 TmrCnt;
113 u32 BackoffTmr;
114 TOGGLE_STATE ToggleState;
115 TX_RATE_REDUCTION_STATE TxRateReductionState;
116
117 u8 Last_Rate;
118 u8 Co_efficent;
119 u8 FallbackRateLevel;
120 u8 OfdmRateLevel;
121
122 u8 RatePolicy;
123 u8 reserved_3[3];
124
125 // For RSSI turning
126 s32 RSSI_high;
127 s32 RSSI_low;
128
129} MTO_PARAMETERS, *PMTO_PARAMETERS;
130
131
132#define MTO_FUNC_INPUT PWB32_ADAPTER Adapter
133#define MTO_FUNC_INPUT_DATA Adapter
134#define MTO_DATA() (Adapter->sMtoPara)
135#define MTO_HAL() (&Adapter->sHwData)
136#define MTO_SET_PREAMBLE_TYPE(x) // 20040511 Turbo mark LM_PREAMBLE_TYPE(&pcore_data->lm_data) = (x)
137#define MTO_ENABLE (Adapter->sLocalPara.TxRateMode == RATE_AUTO)
138#define MTO_TXPOWER_FROM_EEPROM (Adapter->sHwData.PowerIndexFromEEPROM)
139#define LOCAL_ANTENNA_NO() (Adapter->sLocalPara.bAntennaNo)
140#define LOCAL_IS_CONNECTED() (Adapter->sLocalPara.wConnectedSTAindex != 0)
141#define LOCAL_IS_IBSS_MODE() (Adapter->asBSSDescriptElement[Adapter->sLocalPara.wConnectedSTAindex].bBssType == IBSS_NET)
142#define MTO_INITTXRATE_MODE (Adapter->sHwData.SoftwareSet&0x2) //bit 1
143// 20040510 Turbo add
144#define MTO_TMR_CNT() MTO_DATA().TmrCnt
145#define MTO_TOGGLE_STATE() MTO_DATA().ToggleState
146#define MTO_TX_RATE_REDUCTION_STATE() MTO_DATA().TxRateReductionState
147#define MTO_BACKOFF_TMR() MTO_DATA().BackoffTmr
148#define MTO_LAST_RATE() MTO_DATA().Last_Rate
149#define MTO_CO_EFFICENT() MTO_DATA().Co_efficent
150
151#define MTO_TH_CNT() MTO_DATA().Th_Cnt
152#define MTO_TH_SQ3() MTO_DATA().Th_SQ3
153#define MTO_TH_IDLE_SLOT() MTO_DATA().Th_IdleSlot
154#define MTO_TH_PR_INTERF() MTO_DATA().Th_PrInterf
155
156#define MTO_TMR_AGING() MTO_DATA().Tmr_Aging
157#define MTO_TMR_PERIODIC() MTO_DATA().Tmr_Periodic
158
159#define MTO_POWER_CHANGE_ENABLE() MTO_DATA().PowerChangeEnable
160#define MTO_ANT_DIVERSITY_ENABLE() Adapter->sLocalPara.boAntennaDiversity
161#define MTO_ANT_MAC() MTO_DATA().Ant_mac
162#define MTO_ANT_DIVERSITY() MTO_DATA().Ant_div
163#define MTO_CCA_MODE() MTO_DATA().CCA_Mode
164#define MTO_CCA_MODE_SETUP() MTO_DATA().CCA_Mode_Setup
165#define MTO_PREAMBLE_TYPE() MTO_DATA().Preamble_Type
166#define MTO_PREAMBLE_CHANGE_ENABLE() MTO_DATA().PreambleChangeEnable
167
168#define MTO_RATE_LEVEL() MTO_DATA().DataRateLevel
169#define MTO_FALLBACK_RATE_LEVEL() MTO_DATA().FallbackRateLevel
170#define MTO_OFDM_RATE_LEVEL() MTO_DATA().OfdmRateLevel
171#define MTO_RATE_CHANGE_ENABLE() MTO_DATA().DataRateChangeEnable
172#define MTO_FRAG_TH_LEVEL() MTO_DATA().FragThresholdLevel
173#define MTO_FRAG_CHANGE_ENABLE() MTO_DATA().FragThresholdChangeEnable
174#define MTO_RTS_THRESHOLD() MTO_DATA().RTSThreshold
175#define MTO_RTS_CHANGE_ENABLE() MTO_DATA().RTSChangeEnable
176#define MTO_RTS_THRESHOLD_SETUP() MTO_DATA().RTSThreshold_Setup
177
178#define MTO_AVG_IDLE_SLOT() MTO_DATA().AvgIdleSlot
179#define MTO_PR_INTERF() MTO_DATA().Pr_Interf
180#define MTO_AVG_GAP_BTWN_INTERF() MTO_DATA().AvgGapBtwnInterf
181
182#define MTO_ANT_SEL() MTO_DATA().Ant_sel
183#define MTO_CNT_ANT(x) MTO_DATA().Cnt_Ant[(x)]
184#define MTO_SQ_ANT(x) MTO_DATA().SQ_Ant[(x)]
185#define MTO_AGING_TIMEOUT() MTO_DATA().aging_timeout
186
187
188#define MTO_TXFLOWCOUNT() MTO_DATA().TxFlowCount
189//--------- DTO threshold parameters -------------
190#define MTOPARA_PERIODIC_CHECK_CYCLE() MTO_DATA().DTO_PeriodicCheckCycle
191#define MTOPARA_RSSI_TH_FOR_ANTDIV() MTO_DATA().DTO_RssiThForAntDiv
192#define MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() MTO_DATA().DTO_TxCountThForCalcNewRate
193#define MTOPARA_TXRATE_INC_TH() MTO_DATA().DTO_TxRateIncTh
194#define MTOPARA_TXRATE_DEC_TH() MTO_DATA().DTO_TxRateDecTh
195#define MTOPARA_TXRATE_EQ_TH() MTO_DATA().DTO_TxRateEqTh
196#define MTOPARA_TXRATE_BACKOFF() MTO_DATA().DTO_TxRateBackOff
197#define MTOPARA_TXRETRYRATE_REDUCE() MTO_DATA().DTO_TxRetryRateReduce
198#define MTOPARA_TXPOWER_INDEX() MTO_DATA().DTO_TxPowerIndex
199//------------------------------------------------
200
201
202extern u8 MTO_Data_Rate_Tbl[];
203extern u16 MTO_Frag_Th_Tbl[];
204
205#define MTO_DATA_RATE() MTO_Data_Rate_Tbl[MTO_RATE_LEVEL()]
206#define MTO_DATA_FALLBACK_RATE() MTO_Data_Rate_Tbl[MTO_FALLBACK_RATE_LEVEL()] //next level
207#define MTO_FRAG_TH() MTO_Frag_Th_Tbl[MTO_FRAG_TH_LEVEL()]
208
209typedef struct {
210 u8 tx_rate;
211 u8 tx_retry_rate;
212} TXRETRY_REC;
213
214typedef struct _STATISTICS_INFO {
215 u32 Rate54M;
216 u32 Rate48M;
217 u32 Rate36M;
218 u32 Rate24M;
219 u32 Rate18M;
220 u32 Rate12M;
221 u32 Rate9M;
222 u32 Rate6M;
223 u32 Rate11MS;
224 u32 Rate11ML;
225 u32 Rate55MS;
226 u32 Rate55ML;
227 u32 Rate2MS;
228 u32 Rate2ML;
229 u32 Rate1M;
230 u32 Rate54MOK;
231 u32 Rate48MOK;
232 u32 Rate36MOK;
233 u32 Rate24MOK;
234 u32 Rate18MOK;
235 u32 Rate12MOK;
236 u32 Rate9MOK;
237 u32 Rate6MOK;
238 u32 Rate11MSOK;
239 u32 Rate11MLOK;
240 u32 Rate55MSOK;
241 u32 Rate55MLOK;
242 u32 Rate2MSOK;
243 u32 Rate2MLOK;
244 u32 Rate1MOK;
245 u32 SQ3;
246 s32 RSSIAVG;
247 s32 RSSIMAX;
248 s32 TXRATE;
249 s32 TxRetryRate;
250 s32 BSS_PK_CNT;
251 s32 NIDLESLOT;
252 s32 SLOT_CNT;
253 s32 INTERF_CNT;
254 s32 GAP_CNT;
255 s32 DS_EVM;
256 s32 RcvBeaconNum;
257 s32 RXRATE;
258 s32 RxBytes;
259 s32 TxBytes;
260 s32 Antenna;
261} STATISTICS_INFO, *PSTATISTICS_INFO;
262
263#endif //__MTO_H__
264
265
diff --git a/drivers/staging/winbond/mto_f.h b/drivers/staging/winbond/mto_f.h
new file mode 100644
index 000000000000..30b3df2ccb3c
--- /dev/null
+++ b/drivers/staging/winbond/mto_f.h
@@ -0,0 +1,7 @@
1extern void MTO_Init(PWB32_ADAPTER);
2extern void MTO_PeriodicTimerExpired(PWB32_ADAPTER);
3extern void MTO_SetDTORateRange(PWB32_ADAPTER, u8 *, u8);
4extern u8 MTO_GetTxRate(MTO_FUNC_INPUT, u32 fpdu_len);
5extern u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT);
6extern void MTO_SetTxCount(MTO_FUNC_INPUT, u8 t0, u8 index);
7
diff --git a/drivers/staging/winbond/os_common.h b/drivers/staging/winbond/os_common.h
new file mode 100644
index 000000000000..e24ff41e871e
--- /dev/null
+++ b/drivers/staging/winbond/os_common.h
@@ -0,0 +1,2 @@
1#include "linux/sysdef.h"
2
diff --git a/drivers/staging/winbond/phy_calibration.c b/drivers/staging/winbond/phy_calibration.c
new file mode 100644
index 000000000000..272a65066aba
--- /dev/null
+++ b/drivers/staging/winbond/phy_calibration.c
@@ -0,0 +1,1759 @@
1/*
2 * phy_302_calibration.c
3 *
4 * Copyright (C) 2002, 2005 Winbond Electronics Corp.
5 *
6 * modification history
7 * ---------------------------------------------------------------------------
8 * 0.01.001, 2003-04-16, Kevin created
9 *
10 */
11
12/****************** INCLUDE FILES SECTION ***********************************/
13#include "os_common.h"
14#include "phy_calibration.h"
15
16
17/****************** DEBUG CONSTANT AND MACRO SECTION ************************/
18
19/****************** LOCAL CONSTANT AND MACRO SECTION ************************/
20#define LOOP_TIMES 20
21#define US 1000//MICROSECOND
22
23#define AG_CONST 0.6072529350
24#define FIXED(X) ((s32)((X) * 32768.0))
25#define DEG2RAD(X) 0.017453 * (X)
26
27/****************** LOCAL TYPE DEFINITION SECTION ***************************/
28typedef s32 fixed; /* 16.16 fixed-point */
29
30static const fixed Angles[]=
31{
32 FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)),
33 FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)),
34 FIXED(DEG2RAD(0.895174)),FIXED(DEG2RAD(0.447614)),FIXED(DEG2RAD(0.223811)),
35 FIXED(DEG2RAD(0.111906)),FIXED(DEG2RAD(0.055953)),FIXED(DEG2RAD(0.027977))
36};
37
38/****************** LOCAL FUNCTION DECLARATION SECTION **********************/
39//void _phy_rf_write_delay(hw_data_t *phw_data);
40//void phy_init_rf(hw_data_t *phw_data);
41
42/****************** FUNCTION DEFINITION SECTION *****************************/
43
44s32 _s13_to_s32(u32 data)
45{
46 u32 val;
47
48 val = (data & 0x0FFF);
49
50 if ((data & BIT(12)) != 0)
51 {
52 val |= 0xFFFFF000;
53 }
54
55 return ((s32) val);
56}
57
58u32 _s32_to_s13(s32 data)
59{
60 u32 val;
61
62 if (data > 4095)
63 {
64 data = 4095;
65 }
66 else if (data < -4096)
67 {
68 data = -4096;
69 }
70
71 val = data & 0x1FFF;
72
73 return val;
74}
75
76/****************************************************************************/
77s32 _s4_to_s32(u32 data)
78{
79 s32 val;
80
81 val = (data & 0x0007);
82
83 if ((data & BIT(3)) != 0)
84 {
85 val |= 0xFFFFFFF8;
86 }
87
88 return val;
89}
90
91u32 _s32_to_s4(s32 data)
92{
93 u32 val;
94
95 if (data > 7)
96 {
97 data = 7;
98 }
99 else if (data < -8)
100 {
101 data = -8;
102 }
103
104 val = data & 0x000F;
105
106 return val;
107}
108
109/****************************************************************************/
110s32 _s5_to_s32(u32 data)
111{
112 s32 val;
113
114 val = (data & 0x000F);
115
116 if ((data & BIT(4)) != 0)
117 {
118 val |= 0xFFFFFFF0;
119 }
120
121 return val;
122}
123
124u32 _s32_to_s5(s32 data)
125{
126 u32 val;
127
128 if (data > 15)
129 {
130 data = 15;
131 }
132 else if (data < -16)
133 {
134 data = -16;
135 }
136
137 val = data & 0x001F;
138
139 return val;
140}
141
142/****************************************************************************/
143s32 _s6_to_s32(u32 data)
144{
145 s32 val;
146
147 val = (data & 0x001F);
148
149 if ((data & BIT(5)) != 0)
150 {
151 val |= 0xFFFFFFE0;
152 }
153
154 return val;
155}
156
157u32 _s32_to_s6(s32 data)
158{
159 u32 val;
160
161 if (data > 31)
162 {
163 data = 31;
164 }
165 else if (data < -32)
166 {
167 data = -32;
168 }
169
170 val = data & 0x003F;
171
172 return val;
173}
174
175/****************************************************************************/
176s32 _s9_to_s32(u32 data)
177{
178 s32 val;
179
180 val = data & 0x00FF;
181
182 if ((data & BIT(8)) != 0)
183 {
184 val |= 0xFFFFFF00;
185 }
186
187 return val;
188}
189
190u32 _s32_to_s9(s32 data)
191{
192 u32 val;
193
194 if (data > 255)
195 {
196 data = 255;
197 }
198 else if (data < -256)
199 {
200 data = -256;
201 }
202
203 val = data & 0x01FF;
204
205 return val;
206}
207
208/****************************************************************************/
209s32 _floor(s32 n)
210{
211 if (n > 0)
212 {
213 n += 5;
214 }
215 else
216 {
217 n -= 5;
218 }
219
220 return (n/10);
221}
222
223/****************************************************************************/
224// The following code is sqare-root function.
225// sqsum is the input and the output is sq_rt;
226// The maximum of sqsum = 2^27 -1;
227u32 _sqrt(u32 sqsum)
228{
229 u32 sq_rt;
230
231 int g0, g1, g2, g3, g4;
232 int seed;
233 int next;
234 int step;
235
236 g4 = sqsum / 100000000;
237 g3 = (sqsum - g4*100000000) /1000000;
238 g2 = (sqsum - g4*100000000 - g3*1000000) /10000;
239 g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) /100;
240 g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100);
241
242 next = g4;
243 step = 0;
244 seed = 0;
245 while (((seed+1)*(step+1)) <= next)
246 {
247 step++;
248 seed++;
249 }
250
251 sq_rt = seed * 10000;
252 next = (next-(seed*step))*100 + g3;
253
254 step = 0;
255 seed = 2 * seed * 10;
256 while (((seed+1)*(step+1)) <= next)
257 {
258 step++;
259 seed++;
260 }
261
262 sq_rt = sq_rt + step * 1000;
263 next = (next - seed * step) * 100 + g2;
264 seed = (seed + step) * 10;
265 step = 0;
266 while (((seed+1)*(step+1)) <= next)
267 {
268 step++;
269 seed++;
270 }
271
272 sq_rt = sq_rt + step * 100;
273 next = (next - seed * step) * 100 + g1;
274 seed = (seed + step) * 10;
275 step = 0;
276
277 while (((seed+1)*(step+1)) <= next)
278 {
279 step++;
280 seed++;
281 }
282
283 sq_rt = sq_rt + step * 10;
284 next = (next - seed* step) * 100 + g0;
285 seed = (seed + step) * 10;
286 step = 0;
287
288 while (((seed+1)*(step+1)) <= next)
289 {
290 step++;
291 seed++;
292 }
293
294 sq_rt = sq_rt + step;
295
296 return sq_rt;
297}
298
299/****************************************************************************/
300void _sin_cos(s32 angle, s32 *sin, s32 *cos)
301{
302 fixed X, Y, TargetAngle, CurrAngle;
303 unsigned Step;
304
305 X=FIXED(AG_CONST); // AG_CONST * cos(0)
306 Y=0; // AG_CONST * sin(0)
307 TargetAngle=abs(angle);
308 CurrAngle=0;
309
310 for (Step=0; Step < 12; Step++)
311 {
312 fixed NewX;
313
314 if(TargetAngle > CurrAngle)
315 {
316 NewX=X - (Y >> Step);
317 Y=(X >> Step) + Y;
318 X=NewX;
319 CurrAngle += Angles[Step];
320 }
321 else
322 {
323 NewX=X + (Y >> Step);
324 Y=-(X >> Step) + Y;
325 X=NewX;
326 CurrAngle -= Angles[Step];
327 }
328 }
329
330 if (angle > 0)
331 {
332 *cos = X;
333 *sin = Y;
334 }
335 else
336 {
337 *cos = X;
338 *sin = -Y;
339 }
340}
341
342
343void _reset_rx_cal(hw_data_t *phw_data)
344{
345 u32 val;
346
347 hw_get_dxx_reg(phw_data, 0x54, &val);
348
349 if (phw_data->revision == 0x2002) // 1st-cut
350 {
351 val &= 0xFFFF0000;
352 }
353 else // 2nd-cut
354 {
355 val &= 0x000003FF;
356 }
357
358 hw_set_dxx_reg(phw_data, 0x54, val);
359}
360
361
362// ************for winbond calibration*********
363//
364
365//
366//
367// *********************************************
368void _rxadc_dc_offset_cancellation_winbond(hw_data_t *phw_data, u32 frequency)
369{
370 u32 reg_agc_ctrl3;
371 u32 reg_a_acq_ctrl;
372 u32 reg_b_acq_ctrl;
373 u32 val;
374
375 PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n"));
376 phy_init_rf(phw_data);
377
378 // set calibration channel
379 if( (RF_WB_242 == phw_data->phy_type) ||
380 (RF_WB_242_1 == phw_data->phy_type) ) // 20060619.5 Add
381 {
382 if ((frequency >= 2412) && (frequency <= 2484))
383 {
384 // w89rf242 change frequency to 2390Mhz
385 PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n"));
386 phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
387
388 }
389 }
390 else
391 {
392
393 }
394
395 // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
396 hw_get_dxx_reg(phw_data, 0x5C, &val);
397 val &= ~(0x03FF);
398 hw_set_dxx_reg(phw_data, 0x5C, val);
399
400 // reset the TX and RX IQ calibration data
401 hw_set_dxx_reg(phw_data, 0x3C, 0);
402 hw_set_dxx_reg(phw_data, 0x54, 0);
403
404 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
405
406 // a. Disable AGC
407 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
408 reg_agc_ctrl3 &= ~BIT(2);
409 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
410 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
411
412 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
413 val |= MASK_AGC_FIX_GAIN;
414 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
415
416 // b. Turn off BB RX
417 hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl);
418 reg_a_acq_ctrl |= MASK_AMER_OFF_REG;
419 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
420
421 hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl);
422 reg_b_acq_ctrl |= MASK_BMER_OFF_REG;
423 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
424
425 // c. Make sure MAC is in receiving mode
426 // d. Turn ON ADC calibration
427 // - ADC calibrator is triggered by this signal rising from 0 to 1
428 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
429 val &= ~MASK_ADC_DC_CAL_STR;
430 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
431
432 val |= MASK_ADC_DC_CAL_STR;
433 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
434 pa_stall_execution(US); // *MUST* wait for a while
435
436 // e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]"
437#ifdef _DEBUG
438 hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val);
439 PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val));
440
441 PHY_DEBUG(("[CAL] ** adc_dc_cal_i = %d (0x%04X)\n",
442 _s9_to_s32(val&0x000001FF), val&0x000001FF));
443 PHY_DEBUG(("[CAL] ** adc_dc_cal_q = %d (0x%04X)\n",
444 _s9_to_s32((val&0x0003FE00)>>9), (val&0x0003FE00)>>9));
445#endif
446
447 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
448 val &= ~MASK_ADC_DC_CAL_STR;
449 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
450
451 // f. Turn on BB RX
452 //hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl);
453 reg_a_acq_ctrl &= ~MASK_AMER_OFF_REG;
454 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
455
456 //hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl);
457 reg_b_acq_ctrl &= ~MASK_BMER_OFF_REG;
458 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
459
460 // g. Enable AGC
461 //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val);
462 reg_agc_ctrl3 |= BIT(2);
463 reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
464 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
465}
466
467////////////////////////////////////////////////////////
468void _txidac_dc_offset_cancellation_winbond(hw_data_t *phw_data)
469{
470 u32 reg_agc_ctrl3;
471 u32 reg_mode_ctrl;
472 u32 reg_dc_cancel;
473 s32 iqcal_image_i;
474 s32 iqcal_image_q;
475 u32 sqsum;
476 s32 mag_0;
477 s32 mag_1;
478 s32 fix_cancel_dc_i = 0;
479 u32 val;
480 int loop;
481
482 PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n"));
483
484 // a. Set to "TX calibration mode"
485
486 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
487 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
488 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
489 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
490 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
491 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
492 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
493 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
494 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
495 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
496
497 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
498
499 // a. Disable AGC
500 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
501 reg_agc_ctrl3 &= ~BIT(2);
502 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
503 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
504
505 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
506 val |= MASK_AGC_FIX_GAIN;
507 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
508
509 // b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0
510 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
511
512 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
513 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
514
515 // mode=2, tone=0
516 //reg_mode_ctrl |= (MASK_CALIB_START|2);
517
518 // mode=2, tone=1
519 //reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2));
520
521 // mode=2, tone=2
522 reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2));
523 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
524 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
525 pa_stall_execution(US);
526
527 hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel);
528 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
529
530 for (loop = 0; loop < LOOP_TIMES; loop++)
531 {
532 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
533
534 // c.
535 // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
536 reg_dc_cancel &= ~(0x03FF);
537 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
538 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
539 pa_stall_execution(US);
540
541 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
542 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
543
544 iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
545 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
546 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
547 mag_0 = (s32) _sqrt(sqsum);
548 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
549 mag_0, iqcal_image_i, iqcal_image_q));
550
551 // d.
552 reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT);
553 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
554 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
555 pa_stall_execution(US);
556
557 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
558 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
559
560 iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
561 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
562 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
563 mag_1 = (s32) _sqrt(sqsum);
564 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
565 mag_1, iqcal_image_i, iqcal_image_q));
566
567 // e. Calculate the correct DC offset cancellation value for I
568 if (mag_0 != mag_1)
569 {
570 fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
571 }
572 else
573 {
574 if (mag_0 == mag_1)
575 {
576 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
577 }
578
579 fix_cancel_dc_i = 0;
580 }
581
582 PHY_DEBUG(("[CAL] ** fix_cancel_dc_i = %d (0x%04X)\n",
583 fix_cancel_dc_i, _s32_to_s5(fix_cancel_dc_i)));
584
585 if ((abs(mag_1-mag_0)*6) > mag_0)
586 {
587 break;
588 }
589 }
590
591 if ( loop >= 19 )
592 fix_cancel_dc_i = 0;
593
594 reg_dc_cancel &= ~(0x03FF);
595 reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_i) << CANCEL_DC_I_SHIFT);
596 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
597 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
598
599 // g.
600 reg_mode_ctrl &= ~MASK_CALIB_START;
601 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
602 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
603 pa_stall_execution(US);
604}
605
606///////////////////////////////////////////////////////
607void _txqdac_dc_offset_cacellation_winbond(hw_data_t *phw_data)
608{
609 u32 reg_agc_ctrl3;
610 u32 reg_mode_ctrl;
611 u32 reg_dc_cancel;
612 s32 iqcal_image_i;
613 s32 iqcal_image_q;
614 u32 sqsum;
615 s32 mag_0;
616 s32 mag_1;
617 s32 fix_cancel_dc_q = 0;
618 u32 val;
619 int loop;
620
621 PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n"));
622 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
623 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
624 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
625 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
626 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
627 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
628 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
629 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
630 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
631 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
632
633 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
634
635 // a. Disable AGC
636 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
637 reg_agc_ctrl3 &= ~BIT(2);
638 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
639 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
640
641 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
642 val |= MASK_AGC_FIX_GAIN;
643 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
644
645 // a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0
646 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
647 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
648
649 //reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
650 reg_mode_ctrl &= ~(MASK_IQCAL_MODE);
651 reg_mode_ctrl |= (MASK_CALIB_START|3);
652 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
653 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
654 pa_stall_execution(US);
655
656 hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel);
657 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
658
659 for (loop = 0; loop < LOOP_TIMES; loop++)
660 {
661 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
662
663 // b.
664 // reset cancel_dc_q[4:0] in register DC_Cancel
665 reg_dc_cancel &= ~(0x001F);
666 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
667 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
668 pa_stall_execution(US);
669
670 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
671 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
672 pa_stall_execution(US);
673
674 iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
675 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
676 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
677 mag_0 = _sqrt(sqsum);
678 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
679 mag_0, iqcal_image_i, iqcal_image_q));
680
681 // c.
682 reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT);
683 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
684 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
685 pa_stall_execution(US);
686
687 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
688 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
689 pa_stall_execution(US);
690
691 iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
692 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
693 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
694 mag_1 = _sqrt(sqsum);
695 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
696 mag_1, iqcal_image_i, iqcal_image_q));
697
698 // d. Calculate the correct DC offset cancellation value for I
699 if (mag_0 != mag_1)
700 {
701 fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
702 }
703 else
704 {
705 if (mag_0 == mag_1)
706 {
707 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
708 }
709
710 fix_cancel_dc_q = 0;
711 }
712
713 PHY_DEBUG(("[CAL] ** fix_cancel_dc_q = %d (0x%04X)\n",
714 fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q)));
715
716 if ((abs(mag_1-mag_0)*6) > mag_0)
717 {
718 break;
719 }
720 }
721
722 if ( loop >= 19 )
723 fix_cancel_dc_q = 0;
724
725 reg_dc_cancel &= ~(0x001F);
726 reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_q) << CANCEL_DC_Q_SHIFT);
727 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
728 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
729
730
731 // f.
732 reg_mode_ctrl &= ~MASK_CALIB_START;
733 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
734 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
735 pa_stall_execution(US);
736}
737
738//20060612.1.a 20060718.1 Modify
739u8 _tx_iq_calibration_loop_winbond(hw_data_t *phw_data,
740 s32 a_2_threshold,
741 s32 b_2_threshold)
742{
743 u32 reg_mode_ctrl;
744 s32 iq_mag_0_tx;
745 s32 iqcal_tone_i0;
746 s32 iqcal_tone_q0;
747 s32 iqcal_tone_i;
748 s32 iqcal_tone_q;
749 u32 sqsum;
750 s32 rot_i_b;
751 s32 rot_q_b;
752 s32 tx_cal_flt_b[4];
753 s32 tx_cal[4];
754 s32 tx_cal_reg[4];
755 s32 a_2, b_2;
756 s32 sin_b, sin_2b;
757 s32 cos_b, cos_2b;
758 s32 divisor;
759 s32 temp1, temp2;
760 u32 val;
761 u16 loop;
762 s32 iqcal_tone_i_avg,iqcal_tone_q_avg;
763 u8 verify_count;
764 int capture_time;
765
766 PHY_DEBUG(("[CAL] -> _tx_iq_calibration_loop()\n"));
767 PHY_DEBUG(("[CAL] ** a_2_threshold = %d\n", a_2_threshold));
768 PHY_DEBUG(("[CAL] ** b_2_threshold = %d\n", b_2_threshold));
769
770 verify_count = 0;
771
772 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
773 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
774
775 loop = LOOP_TIMES;
776
777 while (loop > 0)
778 {
779 PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
780
781 iqcal_tone_i_avg=0;
782 iqcal_tone_q_avg=0;
783 if( !hw_set_dxx_reg(phw_data, 0x3C, 0x00) ) // 20060718.1 modify
784 return 0;
785 for(capture_time=0;capture_time<10;capture_time++)
786 {
787 // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
788 // enable "IQ alibration Mode II"
789 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
790 reg_mode_ctrl &= ~MASK_IQCAL_MODE;
791 reg_mode_ctrl |= (MASK_CALIB_START|0x02);
792 reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2);
793 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
794 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
795 pa_stall_execution(US);
796
797 // b.
798 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
799 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
800 pa_stall_execution(US);
801
802 iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF);
803 iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13);
804 PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n",
805 iqcal_tone_i0, iqcal_tone_q0));
806
807 sqsum = iqcal_tone_i0*iqcal_tone_i0 +
808 iqcal_tone_q0*iqcal_tone_q0;
809 iq_mag_0_tx = (s32) _sqrt(sqsum);
810 PHY_DEBUG(("[CAL] ** iq_mag_0_tx=%d\n", iq_mag_0_tx));
811
812 // c. Set "calib_start" to 0x0
813 reg_mode_ctrl &= ~MASK_CALIB_START;
814 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
815 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
816 pa_stall_execution(US);
817
818 // d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to
819 // enable "IQ alibration Mode II"
820 //hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
821 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
822 reg_mode_ctrl &= ~MASK_IQCAL_MODE;
823 reg_mode_ctrl |= (MASK_CALIB_START|0x03);
824 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
825 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
826 pa_stall_execution(US);
827
828 // e.
829 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
830 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
831 pa_stall_execution(US);
832
833 iqcal_tone_i = _s13_to_s32(val & 0x00001FFF);
834 iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
835 PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
836 iqcal_tone_i, iqcal_tone_q));
837 if( capture_time == 0)
838 {
839 continue;
840 }
841 else
842 {
843 iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time;
844 iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time;
845 }
846 }
847
848 iqcal_tone_i = iqcal_tone_i_avg;
849 iqcal_tone_q = iqcal_tone_q_avg;
850
851
852 rot_i_b = (iqcal_tone_i * iqcal_tone_i0 +
853 iqcal_tone_q * iqcal_tone_q0) / 1024;
854 rot_q_b = (iqcal_tone_i * iqcal_tone_q0 * (-1) +
855 iqcal_tone_q * iqcal_tone_i0) / 1024;
856 PHY_DEBUG(("[CAL] ** rot_i_b = %d, rot_q_b = %d\n",
857 rot_i_b, rot_q_b));
858
859 // f.
860 divisor = ((iq_mag_0_tx * iq_mag_0_tx * 2)/1024 - rot_i_b) * 2;
861
862 if (divisor == 0)
863 {
864 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
865 PHY_DEBUG(("[CAL] ** divisor=0 to calculate EPS and THETA !!\n"));
866 PHY_DEBUG(("[CAL] ******************************************\n"));
867 break;
868 }
869
870 a_2 = (rot_i_b * 32768) / divisor;
871 b_2 = (rot_q_b * (-32768)) / divisor;
872 PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2));
873 PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2));
874
875 phw_data->iq_rsdl_gain_tx_d2 = a_2;
876 phw_data->iq_rsdl_phase_tx_d2 = b_2;
877
878 //if ((abs(a_2) < 150) && (abs(b_2) < 100))
879 //if ((abs(a_2) < 200) && (abs(b_2) < 200))
880 if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold))
881 {
882 verify_count++;
883
884 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
885 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count));
886 PHY_DEBUG(("[CAL] ******************************************\n"));
887
888 if (verify_count > 2)
889 {
890 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
891 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION (EPS,THETA) OK !!\n"));
892 PHY_DEBUG(("[CAL] **************************************\n"));
893 return 0;
894 }
895
896 continue;
897 }
898 else
899 {
900 verify_count = 0;
901 }
902
903 _sin_cos(b_2, &sin_b, &cos_b);
904 _sin_cos(b_2*2, &sin_2b, &cos_2b);
905 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b));
906 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b));
907
908 if (cos_2b == 0)
909 {
910 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
911 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
912 PHY_DEBUG(("[CAL] ******************************************\n"));
913 break;
914 }
915
916 // 1280 * 32768 = 41943040
917 temp1 = (41943040/cos_2b)*cos_b;
918
919 //temp2 = (41943040/cos_2b)*sin_b*(-1);
920 if (phw_data->revision == 0x2002) // 1st-cut
921 {
922 temp2 = (41943040/cos_2b)*sin_b*(-1);
923 }
924 else // 2nd-cut
925 {
926 temp2 = (41943040*4/cos_2b)*sin_b*(-1);
927 }
928
929 tx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
930 tx_cal_flt_b[1] = _floor(temp2/(32768+a_2));
931 tx_cal_flt_b[2] = _floor(temp2/(32768-a_2));
932 tx_cal_flt_b[3] = _floor(temp1/(32768-a_2));
933 PHY_DEBUG(("[CAL] ** tx_cal_flt_b[0] = %d\n", tx_cal_flt_b[0]));
934 PHY_DEBUG(("[CAL] tx_cal_flt_b[1] = %d\n", tx_cal_flt_b[1]));
935 PHY_DEBUG(("[CAL] tx_cal_flt_b[2] = %d\n", tx_cal_flt_b[2]));
936 PHY_DEBUG(("[CAL] tx_cal_flt_b[3] = %d\n", tx_cal_flt_b[3]));
937
938 tx_cal[2] = tx_cal_flt_b[2];
939 tx_cal[2] = tx_cal[2] +3;
940 tx_cal[1] = tx_cal[2];
941 tx_cal[3] = tx_cal_flt_b[3] - 128;
942 tx_cal[0] = -tx_cal[3]+1;
943
944 PHY_DEBUG(("[CAL] tx_cal[0] = %d\n", tx_cal[0]));
945 PHY_DEBUG(("[CAL] tx_cal[1] = %d\n", tx_cal[1]));
946 PHY_DEBUG(("[CAL] tx_cal[2] = %d\n", tx_cal[2]));
947 PHY_DEBUG(("[CAL] tx_cal[3] = %d\n", tx_cal[3]));
948
949 //if ((tx_cal[0] == 0) && (tx_cal[1] == 0) &&
950 // (tx_cal[2] == 0) && (tx_cal[3] == 0))
951 //{
952 // PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
953 // PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n"));
954 // PHY_DEBUG(("[CAL] ******************************************\n"));
955 // return 0;
956 //}
957
958 // g.
959 if (phw_data->revision == 0x2002) // 1st-cut
960 {
961 hw_get_dxx_reg(phw_data, 0x54, &val);
962 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
963 tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
964 tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
965 tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
966 tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
967 }
968 else // 2nd-cut
969 {
970 hw_get_dxx_reg(phw_data, 0x3C, &val);
971 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
972 tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
973 tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
974 tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
975 tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
976
977 }
978
979 PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0]));
980 PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1]));
981 PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2]));
982 PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3]));
983
984 if (phw_data->revision == 0x2002) // 1st-cut
985 {
986 if (((tx_cal_reg[0]==7) || (tx_cal_reg[0]==(-8))) &&
987 ((tx_cal_reg[3]==7) || (tx_cal_reg[3]==(-8))))
988 {
989 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
990 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
991 PHY_DEBUG(("[CAL] **************************************\n"));
992 break;
993 }
994 }
995 else // 2nd-cut
996 {
997 if (((tx_cal_reg[0]==31) || (tx_cal_reg[0]==(-32))) &&
998 ((tx_cal_reg[3]==31) || (tx_cal_reg[3]==(-32))))
999 {
1000 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
1001 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
1002 PHY_DEBUG(("[CAL] **************************************\n"));
1003 break;
1004 }
1005 }
1006
1007 tx_cal[0] = tx_cal[0] + tx_cal_reg[0];
1008 tx_cal[1] = tx_cal[1] + tx_cal_reg[1];
1009 tx_cal[2] = tx_cal[2] + tx_cal_reg[2];
1010 tx_cal[3] = tx_cal[3] + tx_cal_reg[3];
1011 PHY_DEBUG(("[CAL] ** apply tx_cal[0] = %d\n", tx_cal[0]));
1012 PHY_DEBUG(("[CAL] apply tx_cal[1] = %d\n", tx_cal[1]));
1013 PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal[2]));
1014 PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal[3]));
1015
1016 if (phw_data->revision == 0x2002) // 1st-cut
1017 {
1018 val &= 0x0000FFFF;
1019 val |= ((_s32_to_s4(tx_cal[0]) << 28)|
1020 (_s32_to_s4(tx_cal[1]) << 24)|
1021 (_s32_to_s4(tx_cal[2]) << 20)|
1022 (_s32_to_s4(tx_cal[3]) << 16));
1023 hw_set_dxx_reg(phw_data, 0x54, val);
1024 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val));
1025 return 0;
1026 }
1027 else // 2nd-cut
1028 {
1029 val &= 0x000003FF;
1030 val |= ((_s32_to_s5(tx_cal[0]) << 27)|
1031 (_s32_to_s6(tx_cal[1]) << 21)|
1032 (_s32_to_s6(tx_cal[2]) << 15)|
1033 (_s32_to_s5(tx_cal[3]) << 10));
1034 hw_set_dxx_reg(phw_data, 0x3C, val);
1035 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION = 0x%08X\n", val));
1036 return 0;
1037 }
1038
1039 // i. Set "calib_start" to 0x0
1040 reg_mode_ctrl &= ~MASK_CALIB_START;
1041 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1042 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1043
1044 loop--;
1045 }
1046
1047 return 1;
1048}
1049
1050void _tx_iq_calibration_winbond(hw_data_t *phw_data)
1051{
1052 u32 reg_agc_ctrl3;
1053#ifdef _DEBUG
1054 s32 tx_cal_reg[4];
1055
1056#endif
1057 u32 reg_mode_ctrl;
1058 u32 val;
1059 u8 result;
1060
1061 PHY_DEBUG(("[CAL] -> [4]_tx_iq_calibration()\n"));
1062
1063 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
1064 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
1065 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
1066 phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); // 20060612.1.a 0x1905D6);
1067 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
1068 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); //0x24C60A (high temperature)
1069 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
1070 phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); // 20060612.1.a 0x06890C);
1071 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
1072 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
1073 //; [BB-chip]: Calibration (6f).Send test pattern
1074 //; [BB-chip]: Calibration (6g). Search RXGCL optimal value
1075 //; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table
1076 //phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
1077
1078 OS_SLEEP(30000); // 20060612.1.a 30ms delay. Add the follow 2 lines
1079 //To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750
1080 adjust_TXVGA_for_iq_mag( phw_data );
1081
1082 // a. Disable AGC
1083 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
1084 reg_agc_ctrl3 &= ~BIT(2);
1085 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
1086 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
1087
1088 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
1089 val |= MASK_AGC_FIX_GAIN;
1090 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
1091
1092 result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100);
1093
1094 if (result > 0)
1095 {
1096 if (phw_data->revision == 0x2002) // 1st-cut
1097 {
1098 hw_get_dxx_reg(phw_data, 0x54, &val);
1099 val &= 0x0000FFFF;
1100 hw_set_dxx_reg(phw_data, 0x54, val);
1101 }
1102 else // 2nd-cut
1103 {
1104 hw_get_dxx_reg(phw_data, 0x3C, &val);
1105 val &= 0x000003FF;
1106 hw_set_dxx_reg(phw_data, 0x3C, val);
1107 }
1108
1109 result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200);
1110
1111 if (result > 0)
1112 {
1113 if (phw_data->revision == 0x2002) // 1st-cut
1114 {
1115 hw_get_dxx_reg(phw_data, 0x54, &val);
1116 val &= 0x0000FFFF;
1117 hw_set_dxx_reg(phw_data, 0x54, val);
1118 }
1119 else // 2nd-cut
1120 {
1121 hw_get_dxx_reg(phw_data, 0x3C, &val);
1122 val &= 0x000003FF;
1123 hw_set_dxx_reg(phw_data, 0x3C, val);
1124 }
1125
1126 result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400);
1127 if (result > 0)
1128 {
1129 if (phw_data->revision == 0x2002) // 1st-cut
1130 {
1131 hw_get_dxx_reg(phw_data, 0x54, &val);
1132 val &= 0x0000FFFF;
1133 hw_set_dxx_reg(phw_data, 0x54, val);
1134 }
1135 else // 2nd-cut
1136 {
1137 hw_get_dxx_reg(phw_data, 0x3C, &val);
1138 val &= 0x000003FF;
1139 hw_set_dxx_reg(phw_data, 0x3C, val);
1140 }
1141
1142
1143 result = _tx_iq_calibration_loop_winbond(phw_data, 700, 500);
1144
1145 if (result > 0)
1146 {
1147 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration> **************\n"));
1148 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n"));
1149 PHY_DEBUG(("[CAL] **************************************\n"));
1150
1151 if (phw_data->revision == 0x2002) // 1st-cut
1152 {
1153 hw_get_dxx_reg(phw_data, 0x54, &val);
1154 val &= 0x0000FFFF;
1155 hw_set_dxx_reg(phw_data, 0x54, val);
1156 }
1157 else // 2nd-cut
1158 {
1159 hw_get_dxx_reg(phw_data, 0x3C, &val);
1160 val &= 0x000003FF;
1161 hw_set_dxx_reg(phw_data, 0x3C, val);
1162 }
1163 }
1164 }
1165 }
1166 }
1167
1168 // i. Set "calib_start" to 0x0
1169 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
1170 reg_mode_ctrl &= ~MASK_CALIB_START;
1171 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1172 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1173
1174 // g. Enable AGC
1175 //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val);
1176 reg_agc_ctrl3 |= BIT(2);
1177 reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
1178 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
1179
1180#ifdef _DEBUG
1181 if (phw_data->revision == 0x2002) // 1st-cut
1182 {
1183 hw_get_dxx_reg(phw_data, 0x54, &val);
1184 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
1185 tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
1186 tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
1187 tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
1188 tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
1189 }
1190 else // 2nd-cut
1191 {
1192 hw_get_dxx_reg(phw_data, 0x3C, &val);
1193 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
1194 tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
1195 tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
1196 tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
1197 tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
1198
1199 }
1200
1201 PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0]));
1202 PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1]));
1203 PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2]));
1204 PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3]));
1205#endif
1206
1207
1208 // for test - BEN
1209 // RF Control Override
1210}
1211
1212/////////////////////////////////////////////////////////////////////////////////////////
1213u8 _rx_iq_calibration_loop_winbond(hw_data_t *phw_data, u16 factor, u32 frequency)
1214{
1215 u32 reg_mode_ctrl;
1216 s32 iqcal_tone_i;
1217 s32 iqcal_tone_q;
1218 s32 iqcal_image_i;
1219 s32 iqcal_image_q;
1220 s32 rot_tone_i_b;
1221 s32 rot_tone_q_b;
1222 s32 rot_image_i_b;
1223 s32 rot_image_q_b;
1224 s32 rx_cal_flt_b[4];
1225 s32 rx_cal[4];
1226 s32 rx_cal_reg[4];
1227 s32 a_2, b_2;
1228 s32 sin_b, sin_2b;
1229 s32 cos_b, cos_2b;
1230 s32 temp1, temp2;
1231 u32 val;
1232 u16 loop;
1233
1234 u32 pwr_tone;
1235 u32 pwr_image;
1236 u8 verify_count;
1237
1238 s32 iqcal_tone_i_avg,iqcal_tone_q_avg;
1239 s32 iqcal_image_i_avg,iqcal_image_q_avg;
1240 u16 capture_time;
1241
1242 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration_loop()\n"));
1243 PHY_DEBUG(("[CAL] ** factor = %d\n", factor));
1244
1245
1246// RF Control Override
1247 hw_get_cxx_reg(phw_data, 0x80, &val);
1248 val |= BIT(19);
1249 hw_set_cxx_reg(phw_data, 0x80, val);
1250
1251// RF_Ctrl
1252 hw_get_cxx_reg(phw_data, 0xE4, &val);
1253 val |= BIT(0);
1254 hw_set_cxx_reg(phw_data, 0xE4, val);
1255 PHY_DEBUG(("[CAL] ** RF_CTRL(0xE4) = 0x%08X", val));
1256
1257 hw_set_dxx_reg(phw_data, 0x58, 0x44444444); // IQ_Alpha
1258
1259 // b.
1260
1261 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
1262 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
1263
1264 verify_count = 0;
1265
1266 //for (loop = 0; loop < 1; loop++)
1267 //for (loop = 0; loop < LOOP_TIMES; loop++)
1268 loop = LOOP_TIMES;
1269 while (loop > 0)
1270 {
1271 PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
1272 iqcal_tone_i_avg=0;
1273 iqcal_tone_q_avg=0;
1274 iqcal_image_i_avg=0;
1275 iqcal_image_q_avg=0;
1276 capture_time=0;
1277
1278 for(capture_time=0; capture_time<10; capture_time++)
1279 {
1280 // i. Set "calib_start" to 0x0
1281 reg_mode_ctrl &= ~MASK_CALIB_START;
1282 if( !hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl) )//20060718.1 modify
1283 return 0;
1284 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1285 pa_stall_execution(US);
1286
1287 reg_mode_ctrl &= ~MASK_IQCAL_MODE;
1288 reg_mode_ctrl |= (MASK_CALIB_START|0x1);
1289 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1290 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1291 pa_stall_execution(US); //Should be read out after 450us
1292
1293 // c.
1294 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
1295 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
1296
1297 iqcal_tone_i = _s13_to_s32(val & 0x00001FFF);
1298 iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
1299 PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
1300 iqcal_tone_i, iqcal_tone_q));
1301
1302 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
1303 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
1304
1305 iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
1306 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
1307 PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n",
1308 iqcal_image_i, iqcal_image_q));
1309 if( capture_time == 0)
1310 {
1311 continue;
1312 }
1313 else
1314 {
1315 iqcal_image_i_avg=( iqcal_image_i_avg*(capture_time-1) +iqcal_image_i)/capture_time;
1316 iqcal_image_q_avg=( iqcal_image_q_avg*(capture_time-1) +iqcal_image_q)/capture_time;
1317 iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time;
1318 iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time;
1319 }
1320 }
1321
1322
1323 iqcal_image_i = iqcal_image_i_avg;
1324 iqcal_image_q = iqcal_image_q_avg;
1325 iqcal_tone_i = iqcal_tone_i_avg;
1326 iqcal_tone_q = iqcal_tone_q_avg;
1327
1328 // d.
1329 rot_tone_i_b = (iqcal_tone_i * iqcal_tone_i +
1330 iqcal_tone_q * iqcal_tone_q) / 1024;
1331 rot_tone_q_b = (iqcal_tone_i * iqcal_tone_q * (-1) +
1332 iqcal_tone_q * iqcal_tone_i) / 1024;
1333 rot_image_i_b = (iqcal_image_i * iqcal_tone_i -
1334 iqcal_image_q * iqcal_tone_q) / 1024;
1335 rot_image_q_b = (iqcal_image_i * iqcal_tone_q +
1336 iqcal_image_q * iqcal_tone_i) / 1024;
1337
1338 PHY_DEBUG(("[CAL] ** rot_tone_i_b = %d\n", rot_tone_i_b));
1339 PHY_DEBUG(("[CAL] ** rot_tone_q_b = %d\n", rot_tone_q_b));
1340 PHY_DEBUG(("[CAL] ** rot_image_i_b = %d\n", rot_image_i_b));
1341 PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b));
1342
1343 // f.
1344 if (rot_tone_i_b == 0)
1345 {
1346 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
1347 PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n"));
1348 PHY_DEBUG(("[CAL] ******************************************\n"));
1349 break;
1350 }
1351
1352 a_2 = (rot_image_i_b * 32768) / rot_tone_i_b -
1353 phw_data->iq_rsdl_gain_tx_d2;
1354 b_2 = (rot_image_q_b * 32768) / rot_tone_i_b -
1355 phw_data->iq_rsdl_phase_tx_d2;
1356
1357 PHY_DEBUG(("[CAL] ** iq_rsdl_gain_tx_d2 = %d\n", phw_data->iq_rsdl_gain_tx_d2));
1358 PHY_DEBUG(("[CAL] ** iq_rsdl_phase_tx_d2= %d\n", phw_data->iq_rsdl_phase_tx_d2));
1359 PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2));
1360 PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2));
1361
1362 _sin_cos(b_2, &sin_b, &cos_b);
1363 _sin_cos(b_2*2, &sin_2b, &cos_2b);
1364 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b));
1365 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b));
1366
1367 if (cos_2b == 0)
1368 {
1369 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
1370 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
1371 PHY_DEBUG(("[CAL] ******************************************\n"));
1372 break;
1373 }
1374
1375 // 1280 * 32768 = 41943040
1376 temp1 = (41943040/cos_2b)*cos_b;
1377
1378 //temp2 = (41943040/cos_2b)*sin_b*(-1);
1379 if (phw_data->revision == 0x2002) // 1st-cut
1380 {
1381 temp2 = (41943040/cos_2b)*sin_b*(-1);
1382 }
1383 else // 2nd-cut
1384 {
1385 temp2 = (41943040*4/cos_2b)*sin_b*(-1);
1386 }
1387
1388 rx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
1389 rx_cal_flt_b[1] = _floor(temp2/(32768-a_2));
1390 rx_cal_flt_b[2] = _floor(temp2/(32768+a_2));
1391 rx_cal_flt_b[3] = _floor(temp1/(32768-a_2));
1392
1393 PHY_DEBUG(("[CAL] ** rx_cal_flt_b[0] = %d\n", rx_cal_flt_b[0]));
1394 PHY_DEBUG(("[CAL] rx_cal_flt_b[1] = %d\n", rx_cal_flt_b[1]));
1395 PHY_DEBUG(("[CAL] rx_cal_flt_b[2] = %d\n", rx_cal_flt_b[2]));
1396 PHY_DEBUG(("[CAL] rx_cal_flt_b[3] = %d\n", rx_cal_flt_b[3]));
1397
1398 rx_cal[0] = rx_cal_flt_b[0] - 128;
1399 rx_cal[1] = rx_cal_flt_b[1];
1400 rx_cal[2] = rx_cal_flt_b[2];
1401 rx_cal[3] = rx_cal_flt_b[3] - 128;
1402 PHY_DEBUG(("[CAL] ** rx_cal[0] = %d\n", rx_cal[0]));
1403 PHY_DEBUG(("[CAL] rx_cal[1] = %d\n", rx_cal[1]));
1404 PHY_DEBUG(("[CAL] rx_cal[2] = %d\n", rx_cal[2]));
1405 PHY_DEBUG(("[CAL] rx_cal[3] = %d\n", rx_cal[3]));
1406
1407 // e.
1408 pwr_tone = (iqcal_tone_i*iqcal_tone_i + iqcal_tone_q*iqcal_tone_q);
1409 pwr_image = (iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q)*factor;
1410
1411 PHY_DEBUG(("[CAL] ** pwr_tone = %d\n", pwr_tone));
1412 PHY_DEBUG(("[CAL] ** pwr_image = %d\n", pwr_image));
1413
1414 if (pwr_tone > pwr_image)
1415 {
1416 verify_count++;
1417
1418 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *************\n"));
1419 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count));
1420 PHY_DEBUG(("[CAL] ******************************************\n"));
1421
1422 if (verify_count > 2)
1423 {
1424 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1425 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION OK !!\n"));
1426 PHY_DEBUG(("[CAL] **************************************\n"));
1427 return 0;
1428 }
1429
1430 continue;
1431 }
1432 // g.
1433 hw_get_dxx_reg(phw_data, 0x54, &val);
1434 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
1435
1436 if (phw_data->revision == 0x2002) // 1st-cut
1437 {
1438 rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
1439 rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
1440 rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
1441 rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
1442 }
1443 else // 2nd-cut
1444 {
1445 rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
1446 rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
1447 rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
1448 rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
1449 }
1450
1451 PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0]));
1452 PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1]));
1453 PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2]));
1454 PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3]));
1455
1456 if (phw_data->revision == 0x2002) // 1st-cut
1457 {
1458 if (((rx_cal_reg[0]==7) || (rx_cal_reg[0]==(-8))) &&
1459 ((rx_cal_reg[3]==7) || (rx_cal_reg[3]==(-8))))
1460 {
1461 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1462 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
1463 PHY_DEBUG(("[CAL] **************************************\n"));
1464 break;
1465 }
1466 }
1467 else // 2nd-cut
1468 {
1469 if (((rx_cal_reg[0]==31) || (rx_cal_reg[0]==(-32))) &&
1470 ((rx_cal_reg[3]==31) || (rx_cal_reg[3]==(-32))))
1471 {
1472 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1473 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
1474 PHY_DEBUG(("[CAL] **************************************\n"));
1475 break;
1476 }
1477 }
1478
1479 rx_cal[0] = rx_cal[0] + rx_cal_reg[0];
1480 rx_cal[1] = rx_cal[1] + rx_cal_reg[1];
1481 rx_cal[2] = rx_cal[2] + rx_cal_reg[2];
1482 rx_cal[3] = rx_cal[3] + rx_cal_reg[3];
1483 PHY_DEBUG(("[CAL] ** apply rx_cal[0] = %d\n", rx_cal[0]));
1484 PHY_DEBUG(("[CAL] apply rx_cal[1] = %d\n", rx_cal[1]));
1485 PHY_DEBUG(("[CAL] apply rx_cal[2] = %d\n", rx_cal[2]));
1486 PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal[3]));
1487
1488 hw_get_dxx_reg(phw_data, 0x54, &val);
1489 if (phw_data->revision == 0x2002) // 1st-cut
1490 {
1491 val &= 0x0000FFFF;
1492 val |= ((_s32_to_s4(rx_cal[0]) << 12)|
1493 (_s32_to_s4(rx_cal[1]) << 8)|
1494 (_s32_to_s4(rx_cal[2]) << 4)|
1495 (_s32_to_s4(rx_cal[3])));
1496 hw_set_dxx_reg(phw_data, 0x54, val);
1497 }
1498 else // 2nd-cut
1499 {
1500 val &= 0x000003FF;
1501 val |= ((_s32_to_s5(rx_cal[0]) << 27)|
1502 (_s32_to_s6(rx_cal[1]) << 21)|
1503 (_s32_to_s6(rx_cal[2]) << 15)|
1504 (_s32_to_s5(rx_cal[3]) << 10));
1505 hw_set_dxx_reg(phw_data, 0x54, val);
1506
1507 if( loop == 3 )
1508 return 0;
1509 }
1510 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val));
1511
1512 loop--;
1513 }
1514
1515 return 1;
1516}
1517
1518//////////////////////////////////////////////////////////
1519
1520//////////////////////////////////////////////////////////////////////////
1521void _rx_iq_calibration_winbond(hw_data_t *phw_data, u32 frequency)
1522{
1523// figo 20050523 marked thsi flag for can't compile for relesase
1524#ifdef _DEBUG
1525 s32 rx_cal_reg[4];
1526 u32 val;
1527#endif
1528
1529 u8 result;
1530
1531 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration()\n"));
1532// a. Set RFIC to "RX calibration mode"
1533 //; ----- Calibration (7). RX path IQ imbalance calibration loop
1534 // 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits
1535 phy_set_rf_data(phw_data, 1, (1<<24)|0xEFBFC2);
1536 // 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuit
1537 phy_set_rf_data(phw_data, 11, (11<<24)|0x1A05D6);
1538 //0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized
1539 phy_set_rf_data(phw_data, 5, (5<<24)| phw_data->txvga_setting_for_cal);
1540 //0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized
1541 phy_set_rf_data(phw_data, 6, (6<<24)|0x06834C);
1542 //0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode
1543 phy_set_rf_data(phw_data, 0, (0<<24)|0xFFF1C0);
1544
1545 // ; [BB-chip]: Calibration (7f). Send test pattern
1546 // ; [BB-chip]: Calibration (7g). Search RXGCL optimal value
1547 // ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table
1548
1549 result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency);
1550
1551 if (result > 0)
1552 {
1553 _reset_rx_cal(phw_data);
1554 result = _rx_iq_calibration_loop_winbond(phw_data, 7943, frequency);
1555
1556 if (result > 0)
1557 {
1558 _reset_rx_cal(phw_data);
1559 result = _rx_iq_calibration_loop_winbond(phw_data, 5011, frequency);
1560
1561 if (result > 0)
1562 {
1563 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration> **************\n"));
1564 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION FAILURE !!\n"));
1565 PHY_DEBUG(("[CAL] **************************************\n"));
1566 _reset_rx_cal(phw_data);
1567 }
1568 }
1569 }
1570
1571#ifdef _DEBUG
1572 hw_get_dxx_reg(phw_data, 0x54, &val);
1573 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
1574
1575 if (phw_data->revision == 0x2002) // 1st-cut
1576 {
1577 rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
1578 rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
1579 rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
1580 rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
1581 }
1582 else // 2nd-cut
1583 {
1584 rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
1585 rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
1586 rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
1587 rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
1588 }
1589
1590 PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0]));
1591 PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1]));
1592 PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2]));
1593 PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3]));
1594#endif
1595
1596}
1597
1598////////////////////////////////////////////////////////////////////////
1599void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency)
1600{
1601 u32 reg_mode_ctrl;
1602 u32 iq_alpha;
1603
1604 PHY_DEBUG(("[CAL] -> phy_calibration_winbond()\n"));
1605
1606 // 20040701 1.1.25.1000 kevin
1607 hw_get_cxx_reg(phw_data, 0x80, &mac_ctrl);
1608 hw_get_cxx_reg(phw_data, 0xE4, &rf_ctrl);
1609 hw_get_dxx_reg(phw_data, 0x58, &iq_alpha);
1610
1611
1612
1613 _rxadc_dc_offset_cancellation_winbond(phw_data, frequency);
1614 //_txidac_dc_offset_cancellation_winbond(phw_data);
1615 //_txqdac_dc_offset_cacellation_winbond(phw_data);
1616
1617 _tx_iq_calibration_winbond(phw_data);
1618 _rx_iq_calibration_winbond(phw_data, frequency);
1619
1620 //------------------------------------------------------------------------
1621 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
1622 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); // set when finish
1623 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1624 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1625
1626 // i. Set RFIC to "Normal mode"
1627 hw_set_cxx_reg(phw_data, 0x80, mac_ctrl);
1628 hw_set_cxx_reg(phw_data, 0xE4, rf_ctrl);
1629 hw_set_dxx_reg(phw_data, 0x58, iq_alpha);
1630
1631
1632 //------------------------------------------------------------------------
1633 phy_init_rf(phw_data);
1634
1635}
1636
1637//===========================
1638void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value )
1639{
1640 u32 ltmp=0;
1641
1642 switch( pHwData->phy_type )
1643 {
1644 case RF_MAXIM_2825:
1645 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1646 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
1647 break;
1648
1649 case RF_MAXIM_2827:
1650 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
1651 break;
1652
1653 case RF_MAXIM_2828:
1654 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
1655 break;
1656
1657 case RF_MAXIM_2829:
1658 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
1659 break;
1660
1661 case RF_AIROHA_2230:
1662 case RF_AIROHA_2230S: // 20060420 Add this
1663 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( value, 20 );
1664 break;
1665
1666 case RF_AIROHA_7230:
1667 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff);
1668 break;
1669
1670 case RF_WB_242:
1671 case RF_WB_242_1: // 20060619.5 Add
1672 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( value, 24 );
1673 break;
1674 }
1675
1676 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1677}
1678
1679// 20060717 modify as Bruce's mail
1680unsigned char adjust_TXVGA_for_iq_mag(hw_data_t *phw_data)
1681{
1682 int init_txvga = 0;
1683 u32 reg_mode_ctrl;
1684 u32 val;
1685 s32 iqcal_tone_i0;
1686 s32 iqcal_tone_q0;
1687 u32 sqsum;
1688 s32 iq_mag_0_tx;
1689 u8 reg_state;
1690 int current_txvga;
1691
1692
1693 reg_state = 0;
1694 for( init_txvga=0; init_txvga<10; init_txvga++)
1695 {
1696 current_txvga = ( 0x24C40A|(init_txvga<<6) );
1697 phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga) );
1698 phw_data->txvga_setting_for_cal = current_txvga;
1699
1700 //pa_stall_execution(30000);//Sleep(30);
1701 OS_SLEEP(30000); // 20060612.1.a
1702
1703 if( !hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl) ) // 20060718.1 modify
1704 return FALSE;
1705
1706 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
1707
1708 // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
1709 // enable "IQ alibration Mode II"
1710 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
1711 reg_mode_ctrl &= ~MASK_IQCAL_MODE;
1712 reg_mode_ctrl |= (MASK_CALIB_START|0x02);
1713 reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2);
1714 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1715 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1716
1717 //pa_stall_execution(US);
1718 OS_SLEEP(1); // 20060612.1.a
1719
1720 //pa_stall_execution(300);//Sleep(30);
1721 OS_SLEEP(300); // 20060612.1.a
1722
1723 // b.
1724 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
1725
1726 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
1727 //pa_stall_execution(US);
1728 //pa_stall_execution(300);//Sleep(30);
1729 OS_SLEEP(300); // 20060612.1.a
1730
1731 iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF);
1732 iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13);
1733 PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n",
1734 iqcal_tone_i0, iqcal_tone_q0));
1735
1736 sqsum = iqcal_tone_i0*iqcal_tone_i0 + iqcal_tone_q0*iqcal_tone_q0;
1737 iq_mag_0_tx = (s32) _sqrt(sqsum);
1738 PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", iq_mag_0_tx));
1739
1740 if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 )
1741 break;
1742 else if(iq_mag_0_tx > 1750)
1743 {
1744 init_txvga=-2;
1745 continue;
1746 }
1747 else
1748 continue;
1749
1750 }
1751
1752 if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 )
1753 return TRUE;
1754 else
1755 return FALSE;
1756}
1757
1758
1759
diff --git a/drivers/staging/winbond/phy_calibration.h b/drivers/staging/winbond/phy_calibration.h
new file mode 100644
index 000000000000..b6a65d313019
--- /dev/null
+++ b/drivers/staging/winbond/phy_calibration.h
@@ -0,0 +1,101 @@
1// 20031229 Turbo add
2#define REG_AGC_CTRL1 0x1000
3#define REG_AGC_CTRL2 0x1004
4#define REG_AGC_CTRL3 0x1008
5#define REG_AGC_CTRL4 0x100C
6#define REG_AGC_CTRL5 0x1010
7#define REG_AGC_CTRL6 0x1014
8#define REG_AGC_CTRL7 0x1018
9#define REG_AGC_CTRL8 0x101C
10#define REG_AGC_CTRL9 0x1020
11#define REG_AGC_CTRL10 0x1024
12#define REG_CCA_CTRL 0x1028
13#define REG_A_ACQ_CTRL 0x102C
14#define REG_B_ACQ_CTRL 0x1030
15#define REG_A_TXRX_CTRL 0x1034
16#define REG_B_TXRX_CTRL 0x1038
17#define REG_A_TX_COEF3 0x103C
18#define REG_A_TX_COEF2 0x1040
19#define REG_A_TX_COEF1 0x1044
20#define REG_B_TX_COEF2 0x1048
21#define REG_B_TX_COEF1 0x104C
22#define REG_MODE_CTRL 0x1050
23#define REG_CALIB_DATA 0x1054
24#define REG_IQ_ALPHA 0x1058
25#define REG_DC_CANCEL 0x105C
26#define REG_WTO_READ 0x1060
27#define REG_OFFSET_READ 0x1064
28#define REG_CALIB_READ1 0x1068
29#define REG_CALIB_READ2 0x106C
30#define REG_A_FREQ_EST 0x1070
31
32
33
34
35// 20031101 Turbo add
36#define MASK_AMER_OFF_REG BIT(31)
37
38#define MASK_BMER_OFF_REG BIT(31)
39
40#define MASK_LNA_FIX_GAIN (BIT(3)|BIT(4))
41#define MASK_AGC_FIX BIT(1)
42
43#define MASK_AGC_FIX_GAIN 0xFF00
44
45#define MASK_ADC_DC_CAL_STR BIT(10)
46#define MASK_CALIB_START BIT(4)
47#define MASK_IQCAL_TONE_SEL (BIT(3)|BIT(2))
48#define MASK_IQCAL_MODE (BIT(1)|BIT(0))
49
50#define MASK_TX_CAL_0 0xF0000000
51#define TX_CAL_0_SHIFT 28
52#define MASK_TX_CAL_1 0x0F000000
53#define TX_CAL_1_SHIFT 24
54#define MASK_TX_CAL_2 0x00F00000
55#define TX_CAL_2_SHIFT 20
56#define MASK_TX_CAL_3 0x000F0000
57#define TX_CAL_3_SHIFT 16
58#define MASK_RX_CAL_0 0x0000F000
59#define RX_CAL_0_SHIFT 12
60#define MASK_RX_CAL_1 0x00000F00
61#define RX_CAL_1_SHIFT 8
62#define MASK_RX_CAL_2 0x000000F0
63#define RX_CAL_2_SHIFT 4
64#define MASK_RX_CAL_3 0x0000000F
65#define RX_CAL_3_SHIFT 0
66
67#define MASK_CANCEL_DC_I 0x3E0
68#define CANCEL_DC_I_SHIFT 5
69#define MASK_CANCEL_DC_Q 0x01F
70#define CANCEL_DC_Q_SHIFT 0
71
72// LA20040210 kevin
73//#define MASK_ADC_DC_CAL_I(x) (((x)&0x1FE00)>>9)
74//#define MASK_ADC_DC_CAL_Q(x) ((x)&0x1FF)
75#define MASK_ADC_DC_CAL_I(x) (((x)&0x0003FE00)>>9)
76#define MASK_ADC_DC_CAL_Q(x) ((x)&0x000001FF)
77
78// LA20040210 kevin (Turbo has wrong definition)
79//#define MASK_IQCAL_TONE_I 0x7FFC000
80//#define SHIFT_IQCAL_TONE_I(x) ((x)>>13)
81//#define MASK_IQCAL_TONE_Q 0x1FFF
82//#define SHIFT_IQCAL_TONE_Q(x) ((x)>>0)
83#define MASK_IQCAL_TONE_I 0x00001FFF
84#define SHIFT_IQCAL_TONE_I(x) ((x)>>0)
85#define MASK_IQCAL_TONE_Q 0x03FFE000
86#define SHIFT_IQCAL_TONE_Q(x) ((x)>>13)
87
88// LA20040210 kevin (Turbo has wrong definition)
89//#define MASK_IQCAL_IMAGE_I 0x7FFC000
90//#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>13)
91//#define MASK_IQCAL_IMAGE_Q 0x1FFF
92//#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>0)
93
94//#define MASK_IQCAL_IMAGE_I 0x00001FFF
95//#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>0)
96//#define MASK_IQCAL_IMAGE_Q 0x03FFE000
97//#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>13)
98
99void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value );
100#define phy_init_rf( _A ) //RFSynthesizer_initial( _A )
101
diff --git a/drivers/staging/winbond/reg.c b/drivers/staging/winbond/reg.c
new file mode 100644
index 000000000000..b475c7a7c424
--- /dev/null
+++ b/drivers/staging/winbond/reg.c
@@ -0,0 +1,2683 @@
1#include "os_common.h"
2
3///////////////////////////////////////////////////////////////////////////////////////////////////
4// Original Phy.h
5//*****************************************************************************
6
7/*****************************************************************************
8; For MAXIM2825/6/7 Ver. 331 or more
9; Edited by Tiger, Sep-17-2003
10; revised by Ben, Sep-18-2003
11
120x00 0x000a2
130x01 0x21cc0
14;0x02 0x13802
150x02 0x1383a
16
17;channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333;
18;channe1 02 ;0x03 0x32141 ;0x04 0x08444;
19;channe1 03 ;0x03 0x32143 ;0x04 0x0aeee;
20;channe1 04 ;0x03 0x32142 ;0x04 0x0b333;
21;channe1 05 ;0x03 0x31141 ;0x04 0x08444;
22;channe1 06 ;
230x03 0x31143;
240x04 0x0aeee;
25;channe1 07 ;0x03 0x31142 ;0x04 0x0b333;
26;channe1 08 ;0x03 0x33141 ;0x04 0x08444;
27;channe1 09 ;0x03 0x33143 ;0x04 0x0aeee;
28;channe1 10 ;0x03 0x33142 ;0x04 0x0b333;
29;channe1 11 ;0x03 0x30941 ;0x04 0x08444;
30;channe1 12 ;0x03 0x30943 ;0x04 0x0aeee;
31;channe1 13 ;0x03 0x30942 ;0x04 0x0b333;
32
330x05 0x28986
340x06 0x18008
350x07 0x38400
360x08 0x05100; 100 Hz DC
37;0x08 0x05900; 30 KHz DC
380x09 0x24f08
390x0a 0x17e00, 0x17ea0
400x0b 0x37d80
410x0c 0x0c900 // 0x0ca00 (lager power 9db than 0x0c000), 0x0c000
42*****************************************************************************/
43// MAX2825 (pure b/g)
44u32 max2825_rf_data[] =
45{
46 (0x00<<18)|0x000a2,
47 (0x01<<18)|0x21cc0,
48 (0x02<<18)|0x13806,
49 (0x03<<18)|0x30142,
50 (0x04<<18)|0x0b333,
51 (0x05<<18)|0x289A6,
52 (0x06<<18)|0x18008,
53 (0x07<<18)|0x38000,
54 (0x08<<18)|0x05100,
55 (0x09<<18)|0x24f08,
56 (0x0A<<18)|0x14000,
57 (0x0B<<18)|0x37d80,
58 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
59};
60
61u32 max2825_channel_data_24[][3] =
62{
63 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
64 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
65 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
66 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
67 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
68 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
69 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
70 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
71 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
72 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
73 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
74 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
75 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
76 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
77};
78
79u32 max2825_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
80
81/****************************************************************************/
82// MAX2827 (a/b/g)
83u32 max2827_rf_data[] =
84{
85 (0x00<<18)|0x000a2,
86 (0x01<<18)|0x21cc0,
87 (0x02<<18)|0x13806,
88 (0x03<<18)|0x30142,
89 (0x04<<18)|0x0b333,
90 (0x05<<18)|0x289A6,
91 (0x06<<18)|0x18008,
92 (0x07<<18)|0x38000,
93 (0x08<<18)|0x05100,
94 (0x09<<18)|0x24f08,
95 (0x0A<<18)|0x14000,
96 (0x0B<<18)|0x37d80,
97 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
98};
99
100u32 max2827_channel_data_24[][3] =
101{
102 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
103 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
104 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
105 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
106 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
107 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
108 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
109 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
110 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
111 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
112 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
113 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
114 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
115 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
116};
117
118u32 max2827_channel_data_50[][3] =
119{
120 {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 36
121 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 40
122 {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6}, // channel 44
123 {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x2A9A6}, // channel 48
124 {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x2A9A6}, // channel 52
125 {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 56
126 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 60
127 {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6} // channel 64
128};
129
130u32 max2827_power_data_24[] = {(0x0C<<18)|0x0C000, (0x0C<<18)|0x0D600, (0x0C<<18)|0x0C100};
131u32 max2827_power_data_50[] = {(0x0C<<18)|0x0C400, (0x0C<<18)|0x0D500, (0x0C<<18)|0x0C300};
132
133/****************************************************************************/
134// MAX2828 (a/b/g)
135u32 max2828_rf_data[] =
136{
137 (0x00<<18)|0x000a2,
138 (0x01<<18)|0x21cc0,
139 (0x02<<18)|0x13806,
140 (0x03<<18)|0x30142,
141 (0x04<<18)|0x0b333,
142 (0x05<<18)|0x289A6,
143 (0x06<<18)|0x18008,
144 (0x07<<18)|0x38000,
145 (0x08<<18)|0x05100,
146 (0x09<<18)|0x24f08,
147 (0x0A<<18)|0x14000,
148 (0x0B<<18)|0x37d80,
149 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
150};
151
152u32 max2828_channel_data_24[][3] =
153{
154 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
155 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
156 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
157 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
158 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
159 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
160 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
161 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
162 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
163 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
164 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
165 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
166 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
167 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
168};
169
170u32 max2828_channel_data_50[][3] =
171{
172 {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 36
173 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 40
174 {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channel 44
175 {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x289A6}, // channel 48
176 {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x289A6}, // channel 52
177 {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 56
178 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 60
179 {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6} // channel 64
180};
181
182u32 max2828_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
183u32 max2828_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
184
185/****************************************************************************/
186// LA20040728 kevin
187// MAX2829 (a/b/g)
188u32 max2829_rf_data[] =
189{
190 (0x00<<18)|0x000a2,
191 (0x01<<18)|0x23520,
192 (0x02<<18)|0x13802,
193 (0x03<<18)|0x30142,
194 (0x04<<18)|0x0b333,
195 (0x05<<18)|0x28906,
196 (0x06<<18)|0x18008,
197 (0x07<<18)|0x3B500,
198 (0x08<<18)|0x05100,
199 (0x09<<18)|0x24f08,
200 (0x0A<<18)|0x14000,
201 (0x0B<<18)|0x37d80,
202 (0x0C<<18)|0x0F300 //TXVGA=51, (MAX-6 dB)
203};
204
205u32 max2829_channel_data_24[][3] =
206{
207 {(3<<18)|0x30142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 01 (2412MHz)
208 {(3<<18)|0x32141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 02 (2417MHz)
209 {(3<<18)|0x32143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 03 (2422MHz)
210 {(3<<18)|0x32142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 04 (2427MHz)
211 {(3<<18)|0x31141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 05 (2432MHz)
212 {(3<<18)|0x31143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 06 (2437MHz)
213 {(3<<18)|0x31142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 07 (2442MHz)
214 {(3<<18)|0x33141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 08 (2447MHz)
215 {(3<<18)|0x33143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 09 (2452MHz)
216 {(3<<18)|0x33142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 10 (2457MHz)
217 {(3<<18)|0x30941, (4<<18)|0x08444, (5<<18)|0x289C6}, // 11 (2462MHz)
218 {(3<<18)|0x30943, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 12 (2467MHz)
219 {(3<<18)|0x30942, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 13 (2472MHz)
220 {(3<<18)|0x32941, (4<<18)|0x09999, (5<<18)|0x289C6}, // 14 (2484MHz) hh-modify
221};
222
223u32 max2829_channel_data_50[][4] =
224{
225 {36, (3<<18)|0x33cc3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 36 (5.180GHz)
226 {40, (3<<18)|0x302c0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 40 (5.200GHz)
227 {44, (3<<18)|0x302c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 44 (5.220GHz)
228 {48, (3<<18)|0x322c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 48 (5.240GHz)
229 {52, (3<<18)|0x312c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 52 (5.260GHz)
230 {56, (3<<18)|0x332c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 56 (5.280GHz)
231 {60, (3<<18)|0x30ac0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 60 (5.300GHz)
232 {64, (3<<18)|0x30ac2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 64 (5.320GHz)
233
234 {100, (3<<18)|0x30ec0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 100 (5.500GHz)
235 {104, (3<<18)|0x30ec2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 104 (5.520GHz)
236 {108, (3<<18)|0x32ec1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 108 (5.540GHz)
237 {112, (3<<18)|0x31ec1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 112 (5.560GHz)
238 {116, (3<<18)|0x33ec3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 116 (5.580GHz)
239 {120, (3<<18)|0x301c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 120 (5.600GHz)
240 {124, (3<<18)|0x301c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 124 (5.620GHz)
241 {128, (3<<18)|0x321c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 128 (5.640GHz)
242 {132, (3<<18)|0x311c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 132 (5.660GHz)
243 {136, (3<<18)|0x331c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 136 (5.680GHz)
244 {140, (3<<18)|0x309c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 140 (5.700GHz)
245
246 {149, (3<<18)|0x329c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 149 (5.745GHz)
247 {153, (3<<18)|0x319c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 153 (5.765GHz)
248 {157, (3<<18)|0x339c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 157 (5.785GHz)
249 {161, (3<<18)|0x305c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 161 (5.805GHz)
250
251 // Japan
252 { 184, (3<<18)|0x308c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 184 (4.920GHz)
253 { 188, (3<<18)|0x328c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 188 (4.940GHz)
254 { 192, (3<<18)|0x318c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 192 (4.960GHz)
255 { 196, (3<<18)|0x338c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 196 (4.980GHz)
256 { 8, (3<<18)|0x324c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 8 (5.040GHz)
257 { 12, (3<<18)|0x314c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 12 (5.060GHz)
258 { 16, (3<<18)|0x334c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 16 (5.080GHz)
259 { 34, (3<<18)|0x31cc2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 34 (5.170GHz)
260 { 38, (3<<18)|0x33cc1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 38 (5.190GHz)
261 { 42, (3<<18)|0x302c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 42 (5.210GHz)
262 { 46, (3<<18)|0x322c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 46 (5.230GHz)
263};
264
265/*****************************************************************************
266; For MAXIM2825/6/7 Ver. 317 or less
267; Edited by Tiger, Sep-17-2003 for 2.4Ghz channels
268; Updated by Tiger, Sep-22-2003 for 5.0Ghz channels
269; Corrected by Tiger, Sep-23-2003, for 0x03 and 0x04 of 5.0Ghz channels
270
2710x00 0x00080
2720x01 0x214c0
2730x02 0x13802
274
275;2.4GHz Channels
276;channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc
277;channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111
278;channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb
279;channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc
280;channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111
281;channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb
282;channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc
283;channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111
284;channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb
285;channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc
286;channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111
287;channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb
288;channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc
289
290;5.0Ghz Channels
291;channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333
292;channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000
293;channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333
294;channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999
295;channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666
296;channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc
297;channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000
298;channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333
299
300;2.4GHz band ;0x05 0x28986;
301;5.0GHz band
3020x05 0x2a986
303
3040x06 0x18008
3050x07 0x38400
3060x08 0x05108
3070x09 0x27ff8
3080x0a 0x14000
3090x0b 0x37f99
3100x0c 0x0c000
311*****************************************************************************/
312u32 maxim_317_rf_data[] =
313{
314 (0x00<<18)|0x000a2,
315 (0x01<<18)|0x214c0,
316 (0x02<<18)|0x13802,
317 (0x03<<18)|0x30143,
318 (0x04<<18)|0x0accc,
319 (0x05<<18)|0x28986,
320 (0x06<<18)|0x18008,
321 (0x07<<18)|0x38400,
322 (0x08<<18)|0x05108,
323 (0x09<<18)|0x27ff8,
324 (0x0A<<18)|0x14000,
325 (0x0B<<18)|0x37f99,
326 (0x0C<<18)|0x0c000
327};
328
329u32 maxim_317_channel_data_24[][3] =
330{
331 {(0x03<<18)|0x30143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 01
332 {(0x03<<18)|0x32140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 02
333 {(0x03<<18)|0x32142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 03
334 {(0x03<<18)|0x32143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 04
335 {(0x03<<18)|0x31140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 05
336 {(0x03<<18)|0x31142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 06
337 {(0x03<<18)|0x31143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 07
338 {(0x03<<18)|0x33140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 08
339 {(0x03<<18)|0x33142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 09
340 {(0x03<<18)|0x33143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 10
341 {(0x03<<18)|0x30940, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 11
342 {(0x03<<18)|0x30942, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 12
343 {(0x03<<18)|0x30943, (0x04<<18)|0x0accc, (0x05<<18)|0x28986} // channe1 13
344};
345
346u32 maxim_317_channel_data_50[][3] =
347{
348 {(0x03<<18)|0x33cc0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a986}, // channel 36
349 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2a986}, // channel 40
350 {(0x03<<18)|0x302c3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a986}, // channel 44
351 {(0x03<<18)|0x322c1, (0x04<<18)|0x09666, (0x05<<18)|0x2a986}, // channel 48
352 {(0x03<<18)|0x312c2, (0x04<<18)|0x09999, (0x05<<18)|0x2a986}, // channel 52
353 {(0x03<<18)|0x332c0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a99e}, // channel 56
354 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2a99e}, // channel 60
355 {(0x03<<18)|0x30ac3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a99e} // channel 64
356};
357
358u32 maxim_317_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
359u32 maxim_317_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
360
361/*****************************************************************************
362;;AL2230 MP (Mass Production Version)
363;;RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004
364;;Updated by Tiger Huang (June 1st, 2004)
365;;20-bit length and LSB first
366
367;;Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC;
368;;Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD;
369;;Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC;
370;;Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD;
371;;Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC;
372;;Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD;
373;;Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC;
374;;Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD;
375;;Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC;
376;;Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD;
377;;Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC;
378;;Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD;
379;;Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC;
380;;Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666;
381
3820x02 0x401D8; RXDCOC BW 100Hz for RXHP low
383;;0x02 0x481DC; RXDCOC BW 30Khz for RXHP low
384
3850x03 0xCFFF0
3860x04 0x23800
3870x05 0xA3B72
3880x06 0x6DA01
3890x07 0xE1688
3900x08 0x11600
3910x09 0x99E02
3920x0A 0x5DDB0
3930x0B 0xD9900
3940x0C 0x3FFBD
3950x0D 0xB0000
3960x0F 0xF00A0
397
398;RF Calibration for Airoha AL2230
399;Edit by Ben Chang (01/30/04)
400;Updated by Tiger Huang (03/03/04)
4010x0f 0xf00a0 ; Initial Setting
4020x0f 0xf00b0 ; Activate TX DCC
4030x0f 0xf02a0 ; Activate Phase Calibration
4040x0f 0xf00e0 ; Activate Filter RC Calibration
4050x0f 0xf00a0 ; Restore Initial Setting
406*****************************************************************************/
407
408u32 al2230_rf_data[] =
409{
410 (0x00<<20)|0x09EFC,
411 (0x01<<20)|0x8CCCC,
412 (0x02<<20)|0x40058,// 20060627 Anson 0x401D8,
413 (0x03<<20)|0xCFFF0,
414 (0x04<<20)|0x24100,// 20060627 Anson 0x23800,
415 (0x05<<20)|0xA3B2F,// 20060627 Anson 0xA3B72
416 (0x06<<20)|0x6DA01,
417 (0x07<<20)|0xE3628,// 20060627 Anson 0xE1688,
418 (0x08<<20)|0x11600,
419 (0x09<<20)|0x9DC02,// 20060627 Anosn 0x97602,//0x99E02, //0x9AE02
420 (0x0A<<20)|0x5ddb0, // 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth
421 (0x0B<<20)|0xD9900,
422 (0x0C<<20)|0x3FFBD,
423 (0x0D<<20)|0xB0000,
424 (0x0F<<20)|0xF01A0 // 20060627 Anson 0xF00A0
425};
426
427u32 al2230s_rf_data[] =
428{
429 (0x00<<20)|0x09EFC,
430 (0x01<<20)|0x8CCCC,
431 (0x02<<20)|0x40058,// 20060419 0x401D8,
432 (0x03<<20)|0xCFFF0,
433 (0x04<<20)|0x24100,// 20060419 0x23800,
434 (0x05<<20)|0xA3B2F,// 20060419 0xA3B72,
435 (0x06<<20)|0x6DA01,
436 (0x07<<20)|0xE3628,// 20060419 0xE1688,
437 (0x08<<20)|0x11600,
438 (0x09<<20)|0x9DC02,// 20060419 0x97602,//0x99E02, //0x9AE02
439 (0x0A<<20)|0x5DDB0,// 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth
440 (0x0B<<20)|0xD9900,
441 (0x0C<<20)|0x3FFBD,
442 (0x0D<<20)|0xB0000,
443 (0x0F<<20)|0xF01A0 // 20060419 0xF00A0
444};
445
446u32 al2230_channel_data_24[][2] =
447{
448 {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCC}, // channe1 01
449 {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCD}, // channe1 02
450 {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCC}, // channe1 03
451 {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCD}, // channe1 04
452 {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCC}, // channe1 05
453 {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCD}, // channe1 06
454 {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCC}, // channe1 07
455 {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCD}, // channe1 08
456 {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCC}, // channe1 09
457 {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCD}, // channe1 10
458 {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCC}, // channe1 11
459 {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCD}, // channe1 12
460 {(0x00<<20)|0x03EFC, (0x01<<20)|0x8CCCC}, // channe1 13
461 {(0x00<<20)|0x03E7C, (0x01<<20)|0x86666} // channe1 14
462};
463
464// Current setting. u32 airoha_power_data_24[] = {(0x09<<20)|0x90202, (0x09<<20)|0x96602, (0x09<<20)|0x97602};
465#define AIROHA_TXVGA_LOW_INDEX 31 // Index for 0x90202
466#define AIROHA_TXVGA_MIDDLE_INDEX 12 // Index for 0x96602
467#define AIROHA_TXVGA_HIGH_INDEX 8 // Index for 0x97602 1.0.24.0 1.0.28.0
468/*
469u32 airoha_power_data_24[] =
470{
471 0x9FE02, // Max - 0 dB
472 0x9BE02, // Max - 1 dB
473 0x9DE02, // Max - 2 dB
474 0x99E02, // Max - 3 dB
475 0x9EE02, // Max - 4 dB
476 0x9AE02, // Max - 5 dB
477 0x9CE02, // Max - 6 dB
478 0x98E02, // Max - 7 dB
479 0x97602, // Max - 8 dB
480 0x93602, // Max - 9 dB
481 0x95602, // Max - 10 dB
482 0x91602, // Max - 11 dB
483 0x96602, // Max - 12 dB
484 0x92602, // Max - 13 dB
485 0x94602, // Max - 14 dB
486 0x90602, // Max - 15 dB
487 0x97A02, // Max - 16 dB
488 0x93A02, // Max - 17 dB
489 0x95A02, // Max - 18 dB
490 0x91A02, // Max - 19 dB
491 0x96A02, // Max - 20 dB
492 0x92A02, // Max - 21 dB
493 0x94A02, // Max - 22 dB
494 0x90A02, // Max - 23 dB
495 0x97202, // Max - 24 dB
496 0x93202, // Max - 25 dB
497 0x95202, // Max - 26 dB
498 0x91202, // Max - 27 dB
499 0x96202, // Max - 28 dB
500 0x92202, // Max - 29 dB
501 0x94202, // Max - 30 dB
502 0x90202 // Max - 31 dB
503};
504*/
505
506// 20040927 1.1.69.1000 ybjiang
507// from John
508u32 al2230_txvga_data[][2] =
509{
510 //value , index
511 {0x090202, 0},
512 {0x094202, 2},
513 {0x092202, 4},
514 {0x096202, 6},
515 {0x091202, 8},
516 {0x095202, 10},
517 {0x093202, 12},
518 {0x097202, 14},
519 {0x090A02, 16},
520 {0x094A02, 18},
521 {0x092A02, 20},
522 {0x096A02, 22},
523 {0x091A02, 24},
524 {0x095A02, 26},
525 {0x093A02, 28},
526 {0x097A02, 30},
527 {0x090602, 32},
528 {0x094602, 34},
529 {0x092602, 36},
530 {0x096602, 38},
531 {0x091602, 40},
532 {0x095602, 42},
533 {0x093602, 44},
534 {0x097602, 46},
535 {0x090E02, 48},
536 {0x098E02, 49},
537 {0x094E02, 50},
538 {0x09CE02, 51},
539 {0x092E02, 52},
540 {0x09AE02, 53},
541 {0x096E02, 54},
542 {0x09EE02, 55},
543 {0x091E02, 56},
544 {0x099E02, 57},
545 {0x095E02, 58},
546 {0x09DE02, 59},
547 {0x093E02, 60},
548 {0x09BE02, 61},
549 {0x097E02, 62},
550 {0x09FE02, 63}
551};
552
553//--------------------------------
554// For Airoha AL7230, 2.4Ghz band
555// Edit by Tiger, (March, 9, 2005)
556// 24bit, MSB first
557
558//channel independent registers:
559u32 al7230_rf_data_24[] =
560{
561 (0x00<<24)|0x003790,
562 (0x01<<24)|0x133331,
563 (0x02<<24)|0x841FF2,
564 (0x03<<24)|0x3FDFA3,
565 (0x04<<24)|0x7FD784,
566 (0x05<<24)|0x802B55,
567 (0x06<<24)|0x56AF36,
568 (0x07<<24)|0xCE0207,
569 (0x08<<24)|0x6EBC08,
570 (0x09<<24)|0x221BB9,
571 (0x0A<<24)|0xE0000A,
572 (0x0B<<24)|0x08071B,
573 (0x0C<<24)|0x000A3C,
574 (0x0D<<24)|0xFFFFFD,
575 (0x0E<<24)|0x00000E,
576 (0x0F<<24)|0x1ABA8F
577};
578
579u32 al7230_channel_data_24[][2] =
580{
581 {(0x00<<24)|0x003790, (0x01<<24)|0x133331}, // channe1 01
582 {(0x00<<24)|0x003790, (0x01<<24)|0x1B3331}, // channe1 02
583 {(0x00<<24)|0x003790, (0x01<<24)|0x033331}, // channe1 03
584 {(0x00<<24)|0x003790, (0x01<<24)|0x0B3331}, // channe1 04
585 {(0x00<<24)|0x0037A0, (0x01<<24)|0x133331}, // channe1 05
586 {(0x00<<24)|0x0037A0, (0x01<<24)|0x1B3331}, // channe1 06
587 {(0x00<<24)|0x0037A0, (0x01<<24)|0x033331}, // channe1 07
588 {(0x00<<24)|0x0037A0, (0x01<<24)|0x0B3331}, // channe1 08
589 {(0x00<<24)|0x0037B0, (0x01<<24)|0x133331}, // channe1 09
590 {(0x00<<24)|0x0037B0, (0x01<<24)|0x1B3331}, // channe1 10
591 {(0x00<<24)|0x0037B0, (0x01<<24)|0x033331}, // channe1 11
592 {(0x00<<24)|0x0037B0, (0x01<<24)|0x0B3331}, // channe1 12
593 {(0x00<<24)|0x0037C0, (0x01<<24)|0x133331}, // channe1 13
594 {(0x00<<24)|0x0037C0, (0x01<<24)|0x066661} // channel 14
595};
596
597//channel independent registers:
598u32 al7230_rf_data_50[] =
599{
600 (0x00<<24)|0x0FF520,
601 (0x01<<24)|0x000001,
602 (0x02<<24)|0x451FE2,
603 (0x03<<24)|0x5FDFA3,
604 (0x04<<24)|0x6FD784,
605 (0x05<<24)|0x853F55,
606 (0x06<<24)|0x56AF36,
607 (0x07<<24)|0xCE0207,
608 (0x08<<24)|0x6EBC08,
609 (0x09<<24)|0x221BB9,
610 (0x0A<<24)|0xE0600A,
611 (0x0B<<24)|0x08044B,
612 (0x0C<<24)|0x00143C,
613 (0x0D<<24)|0xFFFFFD,
614 (0x0E<<24)|0x00000E,
615 (0x0F<<24)|0x12BACF //5Ghz default state
616};
617
618u32 al7230_channel_data_5[][4] =
619{
620 //channel dependent registers: 0x00, 0x01 and 0x04
621 //11J ===========
622 {184, (0x00<<24)|0x0FF520, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 184
623 {188, (0x00<<24)|0x0FF520, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 188
624 {192, (0x00<<24)|0x0FF530, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 192
625 {196, (0x00<<24)|0x0FF530, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 196
626 {8, (0x00<<24)|0x0FF540, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 008
627 {12, (0x00<<24)|0x0FF540, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 012
628 {16, (0x00<<24)|0x0FF550, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 016
629 {34, (0x00<<24)|0x0FF560, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 034
630 {38, (0x00<<24)|0x0FF570, (0x01<<24)|0x100001, (0x04<<24)|0x77F784}, // channel 038
631 {42, (0x00<<24)|0x0FF570, (0x01<<24)|0x1AAAA1, (0x04<<24)|0x77F784}, // channel 042
632 {46, (0x00<<24)|0x0FF570, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 046
633 //11 A/H =========
634 {36, (0x00<<24)|0x0FF560, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 036
635 {40, (0x00<<24)|0x0FF570, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 040
636 {44, (0x00<<24)|0x0FF570, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 044
637 {48, (0x00<<24)|0x0FF570, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 048
638 {52, (0x00<<24)|0x0FF580, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 052
639 {56, (0x00<<24)|0x0FF580, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 056
640 {60, (0x00<<24)|0x0FF580, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 060
641 {64, (0x00<<24)|0x0FF590, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 064
642 {100, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 100
643 {104, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 104
644 {108, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 108
645 {112, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 112
646 {116, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 116
647 {120, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 120
648 {124, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 124
649 {128, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 128
650 {132, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 132
651 {136, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 136
652 {140, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 140
653 {149, (0x00<<24)|0x0FF600, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 149
654 {153, (0x00<<24)|0x0FF600, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784}, // channel 153
655 {157, (0x00<<24)|0x0FF600, (0x01<<24)|0x0D5551, (0x04<<24)|0x77F784}, // channel 157
656 {161, (0x00<<24)|0x0FF610, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 161
657 {165, (0x00<<24)|0x0FF610, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784} // channel 165
658};
659
660//; RF Calibration <=== Register 0x0F
661//0x0F 0x1ABA8F; start from 2.4Ghz default state
662//0x0F 0x9ABA8F; TXDC compensation
663//0x0F 0x3ABA8F; RXFIL adjustment
664//0x0F 0x1ABA8F; restore 2.4Ghz default state
665
666//;TXVGA Mapping Table <=== Register 0x0B
667u32 al7230_txvga_data[][2] =
668{
669 {0x08040B, 0}, //TXVGA=0;
670 {0x08041B, 1}, //TXVGA=1;
671 {0x08042B, 2}, //TXVGA=2;
672 {0x08043B, 3}, //TXVGA=3;
673 {0x08044B, 4}, //TXVGA=4;
674 {0x08045B, 5}, //TXVGA=5;
675 {0x08046B, 6}, //TXVGA=6;
676 {0x08047B, 7}, //TXVGA=7;
677 {0x08048B, 8}, //TXVGA=8;
678 {0x08049B, 9}, //TXVGA=9;
679 {0x0804AB, 10}, //TXVGA=10;
680 {0x0804BB, 11}, //TXVGA=11;
681 {0x0804CB, 12}, //TXVGA=12;
682 {0x0804DB, 13}, //TXVGA=13;
683 {0x0804EB, 14}, //TXVGA=14;
684 {0x0804FB, 15}, //TXVGA=15;
685 {0x08050B, 16}, //TXVGA=16;
686 {0x08051B, 17}, //TXVGA=17;
687 {0x08052B, 18}, //TXVGA=18;
688 {0x08053B, 19}, //TXVGA=19;
689 {0x08054B, 20}, //TXVGA=20;
690 {0x08055B, 21}, //TXVGA=21;
691 {0x08056B, 22}, //TXVGA=22;
692 {0x08057B, 23}, //TXVGA=23;
693 {0x08058B, 24}, //TXVGA=24;
694 {0x08059B, 25}, //TXVGA=25;
695 {0x0805AB, 26}, //TXVGA=26;
696 {0x0805BB, 27}, //TXVGA=27;
697 {0x0805CB, 28}, //TXVGA=28;
698 {0x0805DB, 29}, //TXVGA=29;
699 {0x0805EB, 30}, //TXVGA=30;
700 {0x0805FB, 31}, //TXVGA=31;
701 {0x08060B, 32}, //TXVGA=32;
702 {0x08061B, 33}, //TXVGA=33;
703 {0x08062B, 34}, //TXVGA=34;
704 {0x08063B, 35}, //TXVGA=35;
705 {0x08064B, 36}, //TXVGA=36;
706 {0x08065B, 37}, //TXVGA=37;
707 {0x08066B, 38}, //TXVGA=38;
708 {0x08067B, 39}, //TXVGA=39;
709 {0x08068B, 40}, //TXVGA=40;
710 {0x08069B, 41}, //TXVGA=41;
711 {0x0806AB, 42}, //TXVGA=42;
712 {0x0806BB, 43}, //TXVGA=43;
713 {0x0806CB, 44}, //TXVGA=44;
714 {0x0806DB, 45}, //TXVGA=45;
715 {0x0806EB, 46}, //TXVGA=46;
716 {0x0806FB, 47}, //TXVGA=47;
717 {0x08070B, 48}, //TXVGA=48;
718 {0x08071B, 49}, //TXVGA=49;
719 {0x08072B, 50}, //TXVGA=50;
720 {0x08073B, 51}, //TXVGA=51;
721 {0x08074B, 52}, //TXVGA=52;
722 {0x08075B, 53}, //TXVGA=53;
723 {0x08076B, 54}, //TXVGA=54;
724 {0x08077B, 55}, //TXVGA=55;
725 {0x08078B, 56}, //TXVGA=56;
726 {0x08079B, 57}, //TXVGA=57;
727 {0x0807AB, 58}, //TXVGA=58;
728 {0x0807BB, 59}, //TXVGA=59;
729 {0x0807CB, 60}, //TXVGA=60;
730 {0x0807DB, 61}, //TXVGA=61;
731 {0x0807EB, 62}, //TXVGA=62;
732 {0x0807FB, 63}, //TXVGA=63;
733};
734//--------------------------------
735
736
737//; W89RF242 RFIC SPI programming initial data
738//; Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b
739//; Update Date: Ocotber 3, 2005 by PP10 Hsiang-Te Ho
740//;
741//; Version 1.3b revision items: (Oct. 1, 2005 by HTHo) for FA5976A
742u32 w89rf242_rf_data[] =
743{
744 (0x00<<24)|0xF86100, // 20060721 0xF86100, //; 3E184; MODA (0x00) -- Normal mode ; calibration off
745 (0x01<<24)|0xEFFFC2, //; 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on
746 (0x02<<24)|0x102504, //; 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA
747 (0x03<<24)|0x026286, //; 0098A; FCHN (0x03) -- default CH7, 2442MHz
748 (0x04<<24)|0x000208, // 20060612.1.a 0x0002C8, // 20050818 // 20050816 0x000388
749 //; 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C
750 (0x05<<24)|0x24C60A, // 20060612.1.a 0x24C58A, // 941003 0x24C48A, // 20050818.2 0x24848A, // 20050818 // 20050816 0x24C48A
751 //; 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D
752 (0x06<<24)|0x3432CC, // 941003 0x26C34C, // 20050818 0x06B40C
753 //; 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input
754 (0x07<<24)|0x0C68CE, // 20050818.2 0x0C66CE, // 20050818 // 20050816 0x0C68CE
755 //; 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100
756 (0x08<<24)|0x100010, //; 04000; TCAL (0x08) -- //for LO
757 (0x09<<24)|0x004012, // 20060612.1.a 0x6E4012, // 0x004012,
758 //; 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C)
759 (0x0A<<24)|0x704014, //; 1C100; RCALB (0x0A)
760 (0x0B<<24)|0x18BDD6, // 941003 0x1805D6, // 20050818.2 0x1801D6, // 20050818 // 20050816 0x1805D6
761 //; 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B (2005/09/29)
762 (0x0C<<24)|0x575558, // 20050818.2 0x555558, // 20050818 // 20050816 0x575558
763 //; 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner
764 (0x0D<<24)|0x55545A, // 20060612.1.a 0x55555A,
765 //; 15555 ; IBSB (0x0D)
766 (0x0E<<24)|0x5557DC, // 20060612.1.a 0x55555C, // 941003 0x5557DC,
767 //; 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F (2005/11/25)
768 (0x10<<24)|0x000C20, // 941003 0x000020, // 20050818
769 //; 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB
770 (0x11<<24)|0x0C0022, // 941003 0x030022 // 20050818.2 0x030022 // 20050818 // 20050816 0x0C0022
771 //; 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C)
772 (0x12<<24)|0x000024 // 20060612.1.a 0x001824 // 941003 add
773 //; TMODC (0x12) -- Turn OFF Tempearure sensor
774};
775
776u32 w89rf242_channel_data_24[][2] =
777{
778 {(0x03<<24)|0x025B06, (0x04<<24)|0x080408}, // channe1 01
779 {(0x03<<24)|0x025C46, (0x04<<24)|0x080408}, // channe1 02
780 {(0x03<<24)|0x025D86, (0x04<<24)|0x080408}, // channe1 03
781 {(0x03<<24)|0x025EC6, (0x04<<24)|0x080408}, // channe1 04
782 {(0x03<<24)|0x026006, (0x04<<24)|0x080408}, // channe1 05
783 {(0x03<<24)|0x026146, (0x04<<24)|0x080408}, // channe1 06
784 {(0x03<<24)|0x026286, (0x04<<24)|0x080408}, // channe1 07
785 {(0x03<<24)|0x0263C6, (0x04<<24)|0x080408}, // channe1 08
786 {(0x03<<24)|0x026506, (0x04<<24)|0x080408}, // channe1 09
787 {(0x03<<24)|0x026646, (0x04<<24)|0x080408}, // channe1 10
788 {(0x03<<24)|0x026786, (0x04<<24)|0x080408}, // channe1 11
789 {(0x03<<24)|0x0268C6, (0x04<<24)|0x080408}, // channe1 12
790 {(0x03<<24)|0x026A06, (0x04<<24)|0x080408}, // channe1 13
791 {(0x03<<24)|0x026D06, (0x04<<24)|0x080408} // channe1 14
792};
793
794u32 w89rf242_power_data_24[] = {(0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A};
795
796// 20060315.6 Enlarge for new scale
797// 20060316.6 20060619.2.a add mapping array
798u32 w89rf242_txvga_old_mapping[][2] =
799{
800 {0, 0} , // New <-> Old
801 {1, 1} ,
802 {2, 2} ,
803 {3, 3} ,
804 {4, 4} ,
805 {6, 5} ,
806 {8, 6 },
807 {10, 7 },
808 {12, 8 },
809 {14, 9 },
810 {16, 10},
811 {18, 11},
812 {20, 12},
813 {22, 13},
814 {24, 14},
815 {26, 15},
816 {28, 16},
817 {30, 17},
818 {32, 18},
819 {34, 19},
820
821
822};
823
824// 20060619.3 modify from Bruce's mail
825u32 w89rf242_txvga_data[][5] =
826{
827 //low gain mode
828 { (0x05<<24)|0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131 },// ; min gain
829 { (0x05<<24)|0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131 },
830 { (0x05<<24)|0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131 },// (default) +14dBm (ANT)
831 { (0x05<<24)|0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131 },
832
833 //TXVGA=0x10
834 { (0x05<<24)|0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838 },
835 { (0x05<<24)|0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B },
836
837 //TXVGA=0x11
838 { (0x05<<24)|0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333 },
839 { (0x05<<24)|0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737 },
840
841 //TXVGA=0x12
842 { (0x05<<24)|0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030 },
843 { (0x05<<24)|0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434 },
844
845 //TXVGA=0x13
846 { (0x05<<24)|0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030 },
847 { (0x05<<24)|0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232 },
848
849 //TXVGA=0x14
850 { (0x05<<24)|0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131 },
851 { (0x05<<24)|0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434 },
852
853 //TXVGA=0x15
854 { (0x05<<24)|0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131 },
855 { (0x05<<24)|0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434 },
856
857 //TXVGA=0x16
858 { (0x05<<24)|0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131 },
859 { (0x05<<24)|0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535 },
860
861 //TXVGA=0x17
862 { (0x05<<24)|0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F },
863 { (0x05<<24)|0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131 },
864
865 //TXVGA=0x18
866 { (0x05<<24)|0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E },
867 { (0x05<<24)|0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030 },
868
869 //TXVGA=0x19
870 { (0x05<<24)|0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D },
871 { (0x05<<24)|0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030 },
872
873 //TXVGA=0x1A
874 { (0x05<<24)|0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E },
875 { (0x05<<24)|0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131 },
876
877 //TXVGA=0x1B
878 { (0x05<<24)|0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030 },
879 { (0x05<<24)|0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434 },
880
881 //TXVGA=0x1C
882 { (0x05<<24)|0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131 },
883 { (0x05<<24)|0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636 },
884
885 //TXVGA=0x1D
886 { (0x05<<24)|0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737 },
887 { (0x05<<24)|0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B },
888
889 //TXVGA=0x1E
890 { (0x05<<24)|0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B },
891 { (0x05<<24)|0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141 },
892
893 //TXVGA=0x1F
894 { (0x05<<24)|0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242 }
895};
896
897///////////////////////////////////////////////////////////////////////////////////////////////////
898///////////////////////////////////////////////////////////////////////////////////////////////////
899///////////////////////////////////////////////////////////////////////////////////////////////////
900
901
902
903//=============================================================================================================
904// Uxx_ReadEthernetAddress --
905//
906// Routine Description:
907// Reads in the Ethernet address from the IC.
908//
909// Arguments:
910// pHwData - The pHwData structure
911//
912// Return Value:
913//
914// The address is stored in EthernetIDAddr.
915//=============================================================================================================
916void
917Uxx_ReadEthernetAddress( phw_data_t pHwData )
918{
919 u32 ltmp;
920
921 // Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change.
922 // Only unplug and plug again can make hardware read EEPROM again. 20060727
923 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08000000 ); // Start EEPROM access + Read + address(0x0d)
924 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
925 *(PUSHORT)pHwData->PermanentMacAddress = cpu_to_le16((u16)ltmp); //20060926 anson's endian
926 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08010000 ); // Start EEPROM access + Read + address(0x0d)
927 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
928 *(PUSHORT)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16)ltmp); //20060926 anson's endian
929 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08020000 ); // Start EEPROM access + Read + address(0x0d)
930 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
931 *(PUSHORT)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16)ltmp); //20060926 anson's endian
932 *(PUSHORT)(pHwData->PermanentMacAddress + 6) = 0;
933 Wb35Reg_WriteSync( pHwData, 0x03e8, cpu_to_le32(*(PULONG)pHwData->PermanentMacAddress) ); //20060926 anson's endian
934 Wb35Reg_WriteSync( pHwData, 0x03ec, cpu_to_le32(*(PULONG)(pHwData->PermanentMacAddress+4)) ); //20060926 anson's endian
935}
936
937
938//===============================================================================================================
939// CardGetMulticastBit --
940// Description:
941// For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to.
942// Calls CardComputeCrc() to determine the CRC value.
943// Arguments:
944// Address - the address
945// Byte - the byte that it hashes to
946// Value - will have a 1 in the relevant bit
947// Return Value:
948// None.
949//==============================================================================================================
950void CardGetMulticastBit( u8 Address[ETH_LENGTH_OF_ADDRESS],
951 u8 *Byte, u8 *Value )
952{
953 u32 Crc;
954 u32 BitNumber;
955
956 // First compute the CRC.
957 Crc = CardComputeCrc(Address, ETH_LENGTH_OF_ADDRESS);
958
959 // The computed CRC is bit0~31 from left to right
960 //At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128
961 BitNumber = (u32) ((Crc >> 26) & 0x3f);
962
963 *Byte = (u8) (BitNumber >> 3);// 900514 original (BitNumber / 8)
964 *Value = (u8) ((u8)1 << (BitNumber % 8));
965}
966
967void Uxx_power_on_procedure( phw_data_t pHwData )
968{
969 u32 ltmp, loop;
970
971 if( pHwData->phy_type <= RF_MAXIM_V1 )
972 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xffffff38 );
973 else
974 {
975 Wb35Reg_WriteSync( pHwData, 0x03f4, 0xFF5807FF );// 20060721 For NEW IC 0xFF5807FF
976
977 // 20060511.1 Fix the following 4 steps for Rx of RF 2230 initial fail
978 Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
979 OS_SLEEP(10000); // Modify 20051221.1.b
980 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xb8 );// REG_ON RF_RSTN on, and
981 OS_SLEEP(10000); // Modify 20051221.1.b
982
983 ltmp = 0x4968;
984 if( (pHwData->phy_type == RF_WB_242) ||
985 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
986 ltmp = 0x4468;
987 Wb35Reg_WriteSync( pHwData, 0x03d0, ltmp );
988
989 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
990
991 OS_SLEEP(20000); // Modify 20051221.1.b
992 Wb35Reg_ReadSync( pHwData, 0x03d0, &ltmp );
993 loop = 500; // Wait for 5 second 20061101
994 while( !(ltmp & 0x20) && loop-- )
995 {
996 OS_SLEEP(10000); // Modify 20051221.1.b
997 if( !Wb35Reg_ReadSync( pHwData, 0x03d0, &ltmp ) )
998 break;
999 }
1000
1001 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN
1002 }
1003
1004 Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
1005 OS_SLEEP(10000); // Add this 20051221.1.b
1006
1007 // Set burst write delay
1008 Wb35Reg_WriteSync( pHwData, 0x03f8, 0x7ff );
1009}
1010
1011void Set_ChanIndep_RfData_al7230_24( phw_data_t pHwData, u32 *pltmp ,char number)
1012{
1013 u8 i;
1014
1015 for( i=0; i<number; i++ )
1016 {
1017 pHwData->phy_para[i] = al7230_rf_data_24[i];
1018 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i]&0xffffff);
1019 }
1020}
1021
1022void Set_ChanIndep_RfData_al7230_50( phw_data_t pHwData, u32 *pltmp, char number)
1023{
1024 u8 i;
1025
1026 for( i=0; i<number; i++ )
1027 {
1028 pHwData->phy_para[i] = al7230_rf_data_50[i];
1029 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i]&0xffffff);
1030 }
1031}
1032
1033
1034//=============================================================================================================
1035// RFSynthesizer_initial --
1036//=============================================================================================================
1037void
1038RFSynthesizer_initial(phw_data_t pHwData)
1039{
1040 u32 altmp[32];
1041 PULONG pltmp = altmp;
1042 u32 ltmp;
1043 u8 number=0x00; // The number of register vale
1044 u8 i;
1045
1046 //
1047 // bit[31] SPI Enable.
1048 // 1=perform synthesizer program operation. This bit will
1049 // cleared automatically after the operation is completed.
1050 // bit[30] SPI R/W Control
1051 // 0=write, 1=read
1052 // bit[29:24] SPI Data Format Length
1053 // bit[17:4 ] RF Data bits.
1054 // bit[3 :0 ] RF address.
1055 switch( pHwData->phy_type )
1056 {
1057 case RF_MAXIM_2825:
1058 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1059 number = sizeof(max2825_rf_data)/sizeof(max2825_rf_data[0]);
1060 for( i=0; i<number; i++ )
1061 {
1062 pHwData->phy_para[i] = max2825_rf_data[i];// Backup Rf parameter
1063 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_rf_data[i], 18);
1064 }
1065 break;
1066
1067 case RF_MAXIM_2827:
1068 number = sizeof(max2827_rf_data)/sizeof(max2827_rf_data[0]);
1069 for( i=0; i<number; i++ )
1070 {
1071 pHwData->phy_para[i] = max2827_rf_data[i];
1072 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_rf_data[i], 18);
1073 }
1074 break;
1075
1076 case RF_MAXIM_2828:
1077 number = sizeof(max2828_rf_data)/sizeof(max2828_rf_data[0]);
1078 for( i=0; i<number; i++ )
1079 {
1080 pHwData->phy_para[i] = max2828_rf_data[i];
1081 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_rf_data[i], 18);
1082 }
1083 break;
1084
1085 case RF_MAXIM_2829:
1086 number = sizeof(max2829_rf_data)/sizeof(max2829_rf_data[0]);
1087 for( i=0; i<number; i++ )
1088 {
1089 pHwData->phy_para[i] = max2829_rf_data[i];
1090 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_rf_data[i], 18);
1091 }
1092 break;
1093
1094 case RF_AIROHA_2230:
1095 number = sizeof(al2230_rf_data)/sizeof(al2230_rf_data[0]);
1096 for( i=0; i<number; i++ )
1097 {
1098 pHwData->phy_para[i] = al2230_rf_data[i];
1099 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[i], 20);
1100 }
1101 break;
1102
1103 case RF_AIROHA_2230S:
1104 number = sizeof(al2230s_rf_data)/sizeof(al2230s_rf_data[0]);
1105 for( i=0; i<number; i++ )
1106 {
1107 pHwData->phy_para[i] = al2230s_rf_data[i];
1108 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230s_rf_data[i], 20);
1109 }
1110 break;
1111
1112 case RF_AIROHA_7230:
1113
1114 //Start to fill RF parameters, PLL_ON should be pulled low.
1115 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 );
1116#ifdef _PE_STATE_DUMP_
1117 WBDEBUG(("* PLL_ON low\n"));
1118#endif
1119
1120 number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]);
1121 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
1122 break;
1123
1124 case RF_WB_242:
1125 case RF_WB_242_1: // 20060619.5 Add
1126 number = sizeof(w89rf242_rf_data)/sizeof(w89rf242_rf_data[0]);
1127 for( i=0; i<number; i++ )
1128 {
1129 ltmp = w89rf242_rf_data[i];
1130 if( i == 4 ) // Update the VCO trim from EEPROM
1131 {
1132 ltmp &= ~0xff0; // Mask bit4 ~bit11
1133 ltmp |= pHwData->VCO_trim<<4;
1134 }
1135
1136 pHwData->phy_para[i] = ltmp;
1137 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( ltmp, 24);
1138 }
1139 break;
1140 }
1141
1142 pHwData->phy_number = number;
1143
1144 // The 16 is the maximum capability of hardware. Here use 12
1145 if( number > 12 ) {
1146 //Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 12, NO_INCREMENT );
1147 for( i=0; i<12; i++ ) // For Al2230
1148 Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] );
1149
1150 pltmp += 12;
1151 number -= 12;
1152 }
1153
1154 // Write to register. number must less and equal than 16
1155 for( i=0; i<number; i++ )
1156 Wb35Reg_WriteSync( pHwData, 0x864, pltmp[i] );
1157
1158 // 20060630.1 Calibration only 1 time
1159 if( pHwData->CalOneTime )
1160 return;
1161 pHwData->CalOneTime = 1;
1162
1163 switch( pHwData->phy_type )
1164 {
1165 case RF_AIROHA_2230:
1166
1167 // 20060511.1 --- Modifying the follow step for Rx issue-----------------
1168 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x07<<20)|0xE168E, 20);
1169 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1170 OS_SLEEP(10000);
1171 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[7], 20);
1172 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1173 OS_SLEEP(10000);
1174
1175 case RF_AIROHA_2230S: // 20060420 Add this
1176
1177 // 20060511.1 --- Modifying the follow step for Rx issue-----------------
1178 Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
1179 OS_SLEEP(10000); // Modify 20051221.1.b
1180
1181 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
1182 OS_SLEEP(10000); // Modify 20051221.1.b
1183
1184 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN
1185 Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
1186 OS_SLEEP(10000); // Add this 20051221.1.b
1187 //------------------------------------------------------------------------
1188
1189 // The follow code doesn't use the burst-write mode
1190 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Raise Initial Setting
1191 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20);
1192 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1193
1194 ltmp = pHwData->Wb35Reg.BB5C & 0xfffff000;
1195 Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
1196 pHwData->Wb35Reg.BB50 |= 0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060315.1 modify
1197 Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
1198 OS_SLEEP(5000);
1199
1200 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01B0); //Activate Filter Cal.
1201 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01B0, 20);
1202 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1203 OS_SLEEP(5000);
1204
1205 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01e0); //Activate TX DCC
1206 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01E0, 20);
1207 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1208 OS_SLEEP(5000);
1209
1210 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Resotre Initial Setting
1211 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20);
1212 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1213
1214// //Force TXI(Q)P(N) to normal control
1215 Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->Wb35Reg.BB5C );
1216 pHwData->Wb35Reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);
1217 Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
1218 break;
1219
1220 case RF_AIROHA_7230:
1221
1222 //RF parameters have filled completely, PLL_ON should be
1223 //pulled high
1224 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
1225 #ifdef _PE_STATE_DUMP_
1226 WBDEBUG(("* PLL_ON high\n"));
1227 #endif
1228
1229 //2.4GHz
1230 //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
1231 //Wb35Reg_WriteSync pHwData, 0x0864, ltmp );
1232 //OS_SLEEP(1000); // Sleep 1 ms
1233 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1234 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1235 OS_SLEEP(5000);
1236 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1237 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1238 OS_SLEEP(5000);
1239 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
1240 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1241 OS_SLEEP(5000);
1242
1243 //5GHz
1244 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 );
1245 #ifdef _PE_STATE_DUMP_
1246 WBDEBUG(("* PLL_ON low\n"));
1247 #endif
1248
1249 number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]);
1250 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
1251 // Write to register. number must less and equal than 16
1252 for( i=0; i<number; i++ )
1253 Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] );
1254 OS_SLEEP(5000);
1255
1256 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
1257 #ifdef _PE_STATE_DUMP_
1258 WBDEBUG(("* PLL_ON high\n"));
1259 #endif
1260
1261 //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
1262 //Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1263 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1264 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1265 OS_SLEEP(5000);
1266 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1267 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1268 OS_SLEEP(5000);
1269 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
1270 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1271 OS_SLEEP(5000);
1272
1273 //Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
1274 //WBDEBUG(("* PLL_ON high\n"));
1275 break;
1276
1277 case RF_WB_242:
1278 case RF_WB_242_1: // 20060619.5 Add
1279
1280 //
1281 // ; Version 1.3B revision items: for FA5976A , October 3, 2005 by HTHo
1282 //
1283 ltmp = pHwData->Wb35Reg.BB5C & 0xfffff000;
1284 Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
1285 Wb35Reg_WriteSync( pHwData, 0x1058, 0 );
1286 pHwData->Wb35Reg.BB50 |= 0x3;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060630
1287 Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
1288
1289 //----- Calibration (1). VCO frequency calibration
1290 //Calibration (1a.0). Synthesizer reset (HTHo corrected 2005/05/10)
1291 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00101E, 24);
1292 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1293 OS_SLEEP( 5000 ); // Sleep 5ms
1294 //Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time
1295 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFE69c0, 24);
1296 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1297 OS_SLEEP( 2000 ); // Sleep 2ms
1298
1299 //----- Calibration (2). TX baseband Gm-C filter auto-tuning
1300 //Calibration (2a). turn off ENCAL signal
1301 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24);
1302 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1303 //Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default)
1304 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24);
1305 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1306 //Calibration (2b). send TX reset signal (HTHo corrected May 10, 2005)
1307 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00201E, 24);
1308 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1309 //Calibration (2c). turn-on TX Gm-C filter auto-tuning
1310 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFCEBC0, 24);
1311 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1312 OS_SLEEP( 150 ); // Sleep 150 us
1313 //turn off ENCAL signal
1314 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24);
1315 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1316
1317 //----- Calibration (3). RX baseband Gm-C filter auto-tuning
1318 //Calibration (3a). turn off ENCAL signal
1319 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1320 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1321 //Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default; July 26, 2005)
1322 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24);
1323 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1324 //Calibration (3b). send RX reset signal (HTHo corrected May 10, 2005)
1325 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00401E, 24);
1326 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1327 //Calibration (3c). turn-on RX Gm-C filter auto-tuning
1328 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFEEDC0, 24);
1329 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1330 OS_SLEEP( 150 ); // Sleep 150 us
1331 //Calibration (3e). turn off ENCAL signal
1332 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1333 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1334
1335 //----- Calibration (4). TX LO leakage calibration
1336 //Calibration (4a). TX LO leakage calibration
1337 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFD6BC0, 24);
1338 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1339 OS_SLEEP( 150 ); // Sleep 150 us
1340
1341 //----- Calibration (5). RX DC offset calibration
1342 //Calibration (5a). turn off ENCAL signal and set to RX SW DC caliration mode
1343 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1344 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1345 //Calibration (5b). turn off AGC servo-loop & RSSI
1346 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEBFFC2, 24);
1347 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1348
1349 //; for LNA=11 --------
1350 //Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111
1351 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x343FCC, 24);
1352 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1353 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1354 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1355 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1356 OS_SLEEP(2000); // Sleep 2ms
1357 //Calibration (5f). turn off ENCAL signal
1358 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1359 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1360
1361 //; for LNA=10 --------
1362 //Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111
1363 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x342FCC, 24);
1364 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1365 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1366 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1367 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1368 OS_SLEEP(2000); // Sleep 2ms
1369 //Calibration (5f). turn off ENCAL signal
1370 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1371 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1372
1373 //; for LNA=01 --------
1374 //Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111
1375 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x341FCC, 24);
1376 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1377 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1378 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1379 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1380 OS_SLEEP(2000); // Sleep 2ms
1381 //Calibration (5f). turn off ENCAL signal
1382 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1383 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1384
1385 //; for LNA=00 --------
1386 //Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111
1387 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x340FCC, 24);
1388 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1389 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1390 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1391 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1392 OS_SLEEP(2000); // Sleep 2ms
1393 //Calibration (5f). turn off ENCAL signal
1394 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1395 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1396 //Calibration (5g). turn on AGC servo-loop
1397 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEFFFC2, 24);
1398 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1399
1400 //; ----- Calibration (7). Switch RF chip to normal mode
1401 //0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode
1402// OS_SLEEP(10000); // @@ 20060721
1403 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF86100, 24);
1404 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1405 OS_SLEEP(5000); // Sleep 5 ms
1406
1407// //write back
1408// Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->Wb35Reg.BB5C );
1409// pHwData->Wb35Reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); // 20060315.1 fix
1410// Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
1411// OS_SLEEP(1000); // Sleep 1 ms
1412 break;
1413 }
1414}
1415
1416void BBProcessor_AL7230_2400( phw_data_t pHwData)
1417{
1418 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1419 u32 pltmp[12];
1420
1421 pltmp[0] = 0x16A8337A; // 0x16a5215f; // 0x1000 AGC_Ctrl1
1422 pltmp[1] = 0x9AFF9AA6; // 0x9aff9ca6; // 0x1004 AGC_Ctrl2
1423 pltmp[2] = 0x55D00A04; // 0x55d00a04; // 0x1008 AGC_Ctrl3
1424 pltmp[3] = 0xFFF72031; // 0xFfFf2138; // 0x100c AGC_Ctrl4
1425 pWb35Reg->BB0C = 0xFFF72031;
1426 pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7
1427 pltmp[5] = 0x00CAA333; // 0x00eaa333; // 0x1014 AGC_Ctrl6
1428 pltmp[6] = 0xF2211111; // 0x11111111; // 0x1018 AGC_Ctrl7
1429 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1430 pltmp[8] = 0x06443440; // 0x1020 AGC_Ctrl9
1431 pltmp[9] = 0xA8002A79; // 0xa9002A79; // 0x1024 AGC_Ctrl10
1432 pltmp[10] = 0x40000528; // 20050927 0x40000228
1433 pltmp[11] = 0x232D7F30; // 0x23457f30;// 0x102c A_ACQ_Ctrl
1434 pWb35Reg->BB2C = 0x232D7F30;
1435 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1436
1437 pltmp[0] = 0x00002c54; // 0x1030 B_ACQ_Ctrl
1438 pWb35Reg->BB30 = 0x00002c54;
1439 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1440 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1441 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1442 pWb35Reg->BB3C = 0x00000000;
1443 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1444 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1445 pltmp[6] = 0x00332C1B; // 0x00453B24; // 0x1048 11b TX RC filter
1446 pltmp[7] = 0x0A00FEFF; // 0x0E00FEFF; // 0x104c 11b TX RC filter
1447 pltmp[8] = 0x2B106208; // 0x1050 MODE_Ctrl
1448 pWb35Reg->BB50 = 0x2B106208;
1449 pltmp[9] = 0; // 0x1054
1450 pWb35Reg->BB54 = 0x00000000;
1451 pltmp[10] = 0x52524242; // 0x64645252; // 0x1058 IQ_Alpha
1452 pWb35Reg->BB58 = 0x52524242;
1453 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1454 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1455
1456}
1457
1458void BBProcessor_AL7230_5000( phw_data_t pHwData)
1459{
1460 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1461 u32 pltmp[12];
1462
1463 pltmp[0] = 0x16AA6678; // 0x1000 AGC_Ctrl1
1464 pltmp[1] = 0x9AFFA0B2; // 0x1004 AGC_Ctrl2
1465 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
1466 pltmp[3] = 0xEFFF233E; // 0x100c AGC_Ctrl4
1467 pWb35Reg->BB0C = 0xEFFF233E;
1468 pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7
1469 pltmp[5] = 0x00CAA333; // 0x1014 AGC_Ctrl6
1470 pltmp[6] = 0xF2432111; // 0x1018 AGC_Ctrl7
1471 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1472 pltmp[8] = 0x05C43440; // 0x1020 AGC_Ctrl9
1473 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1474 pltmp[10] = 0x40000528; // 20050927 0x40000228
1475 pltmp[11] = 0x232FDF30;// 0x102c A_ACQ_Ctrl
1476 pWb35Reg->BB2C = 0x232FDF30;
1477 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1478
1479 pltmp[0] = 0x80002C7C; // 0x1030 B_ACQ_Ctrl
1480 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1481 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1482 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1483 pWb35Reg->BB3C = 0x00000000;
1484 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1485 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1486 pltmp[6] = 0x00332C1B; // 0x1048 11b TX RC filter
1487 pltmp[7] = 0x0A00FEFF; // 0x104c 11b TX RC filter
1488 pltmp[8] = 0x2B107208; // 0x1050 MODE_Ctrl
1489 pWb35Reg->BB50 = 0x2B107208;
1490 pltmp[9] = 0; // 0x1054
1491 pWb35Reg->BB54 = 0x00000000;
1492 pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha
1493 pWb35Reg->BB58 = 0x52524242;
1494 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1495 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1496
1497}
1498
1499//=============================================================================================================
1500// BBProcessorPowerupInit --
1501//
1502// Description:
1503// Initialize the Baseband processor.
1504//
1505// Arguments:
1506// pHwData - Handle of the USB Device.
1507//
1508// Return values:
1509// None.
1510//=============================================================================================================
1511void
1512BBProcessor_initial( phw_data_t pHwData )
1513{
1514 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1515 u32 i, pltmp[12];
1516
1517 switch( pHwData->phy_type )
1518 {
1519 case RF_MAXIM_V1: // Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1520
1521 pltmp[0] = 0x16F47E77; // 0x1000 AGC_Ctrl1
1522 pltmp[1] = 0x9AFFAEA4; // 0x1004 AGC_Ctrl2
1523 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
1524 pltmp[3] = 0xEFFF1A34; // 0x100c AGC_Ctrl4
1525 pWb35Reg->BB0C = 0xEFFF1A34;
1526 pltmp[4] = 0x0FABE0B7; // 0x1010 AGC_Ctrl5
1527 pltmp[5] = 0x00CAA332; // 0x1014 AGC_Ctrl6
1528 pltmp[6] = 0xF6632111; // 0x1018 AGC_Ctrl7
1529 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1530 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
1531 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1532 pltmp[10] = (pHwData->phy_type==3) ? 0x40000a28 : 0x40000228; // 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0)
1533 pltmp[11] = 0x232FDF30; // 0x102c A_ACQ_Ctrl
1534 pWb35Reg->BB2C = 0x232FDF30; //Modify for 33's 1.0.95.xxx version, antenna 1
1535 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1536
1537 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1538 pWb35Reg->BB30 = 0x00002C54;
1539 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1540 pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl
1541 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1542 pWb35Reg->BB3C = 0x00000000;
1543 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1544 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1545 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
1546 pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter
1547 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1548 pWb35Reg->BB50 = 0x27106208;
1549 pltmp[9] = 0; // 0x1054
1550 pWb35Reg->BB54 = 0x00000000;
1551 pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha
1552 pWb35Reg->BB58 = 0x64646464;
1553 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1554 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1555
1556 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1557 break;
1558
1559 //------------------------------------------------------------------
1560 //[20040722 WK]
1561 //Only for baseband version 2
1562// case RF_MAXIM_317:
1563 case RF_MAXIM_2825:
1564 case RF_MAXIM_2827:
1565 case RF_MAXIM_2828:
1566
1567 pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1
1568 pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2
1569 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1570 pltmp[3] = 0xefff1a34; // 0x100c AGC_Ctrl4
1571 pWb35Reg->BB0C = 0xefff1a34;
1572 pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5
1573 pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6
1574 pltmp[6] = 0xf6632111; // 0x1018 AGC_Ctrl7
1575 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1576 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
1577 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1578 pltmp[10] = 0x40000528; // 0x40000128; Modify for 33's 1.0.95
1579 pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl
1580 pWb35Reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
1581 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1582
1583 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1584 pWb35Reg->BB30 = 0x00002C54;
1585 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1586 pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl
1587 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1588 pWb35Reg->BB3C = 0x00000000;
1589 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1590 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1591 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
1592 pltmp[7] = 0x0D00FDFF; // 0x104c 11b TX RC filter
1593 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1594 pWb35Reg->BB50 = 0x27106208;
1595 pltmp[9] = 0; // 0x1054
1596 pWb35Reg->BB54 = 0x00000000;
1597 pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha
1598 pWb35Reg->BB58 = 0x64646464;
1599 pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel
1600 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1601
1602 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1603 break;
1604
1605 case RF_MAXIM_2829:
1606
1607 pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1
1608 pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2
1609 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1610 pltmp[3] = 0xf4ff1632; // 0xefff1a34; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95
1611 pWb35Reg->BB0C = 0xf4ff1632; // 0xefff1a34; Modify for 33's 1.0.95
1612 pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5
1613 pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6
1614 pltmp[6] = 0xf8632112; // 0xf6632111; // 0x1018 AGC_Ctrl7 Modify for 33's 1.0.95
1615 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1616 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
1617 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1618 pltmp[10] = 0x40000528; // 0x40000128; modify for 33's 1.0.95
1619 pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl
1620 pWb35Reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
1621 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1622
1623 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1624 pWb35Reg->BB30 = 0x00002C54;
1625 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1626 pltmp[2] = 0x5b2c8769; // 0x5B6C8769; // 0x1038 B_TXRX_Ctrl Modify for 33's 1.0.95
1627 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1628 pWb35Reg->BB3C = 0x00000000;
1629 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1630 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1631 pltmp[6] = 0x002c2617; // 0x00453B24; // 0x1048 11b TX RC filter Modify for 33's 1.0.95
1632 pltmp[7] = 0x0800feff; // 0x0D00FDFF; // 0x104c 11b TX RC filter Modify for 33's 1.0.95
1633 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1634 pWb35Reg->BB50 = 0x27106208;
1635 pltmp[9] = 0; // 0x1054
1636 pWb35Reg->BB54 = 0x00000000;
1637 pltmp[10] = 0x64644a4a; // 0x64646464; // 0x1058 IQ_Alpha Modify for 33's 1.0.95
1638 pWb35Reg->BB58 = 0x64646464;
1639 pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel
1640 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1641
1642 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1643 break;
1644
1645 case RF_AIROHA_2230:
1646
1647 pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77
1648 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
1649 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1650 pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version
1651 pWb35Reg->BB0C = 0xFFFd203c;
1652 pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version
1653 pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version
1654 pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version
1655 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1656 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
1657 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1658 pltmp[10] = 0X40000528; //0x40000228
1659 pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730
1660 pWb35Reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
1661 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1662
1663 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1664 pWb35Reg->BB30 = 0x00002C54;
1665 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1666 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769
1667 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1668 pWb35Reg->BB3C = 0x00000000;
1669 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1670 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1671 pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2
1672 pWb35Reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
1673 pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2
1674 pWb35Reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 20060613.2
1675 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
1676 pWb35Reg->BB50 = 0x27106200;
1677 pltmp[9] = 0; // 0x1054
1678 pWb35Reg->BB54 = 0x00000000;
1679 pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha
1680 pWb35Reg->BB58 = 0x52524242;
1681 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1682 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1683
1684 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1685 break;
1686
1687 case RF_AIROHA_2230S: // 20060420 Add this
1688
1689 pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77
1690 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
1691 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1692 pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version
1693 pWb35Reg->BB0C = 0xFFFd203c;
1694 pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version
1695 pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version
1696 pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version
1697 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1698 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
1699 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1700 pltmp[10] = 0X40000528; //0x40000228
1701 pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730
1702 pWb35Reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
1703 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1704
1705 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1706 pWb35Reg->BB30 = 0x00002C54;
1707 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1708 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769
1709 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1710 pWb35Reg->BB3C = 0x00000000;
1711 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1712 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1713 pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2
1714 pWb35Reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
1715 pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2
1716 pWb35Reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1
1717 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
1718 pWb35Reg->BB50 = 0x27106200;
1719 pltmp[9] = 0; // 0x1054
1720 pWb35Reg->BB54 = 0x00000000;
1721 pltmp[10] = 0x52523232; // 20060419 0x52524242; // 0x1058 IQ_Alpha
1722 pWb35Reg->BB58 = 0x52523232; // 20060419 0x52524242;
1723 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1724 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1725
1726 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1727 break;
1728
1729 case RF_AIROHA_7230:
1730/*
1731 pltmp[0] = 0x16a84a77; // 0x1000 AGC_Ctrl1
1732 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
1733 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1734 pltmp[3] = 0xFFFb203a; // 0x100c AGC_Ctrl4
1735 pWb35Reg->BB0c = 0xFFFb203a;
1736 pltmp[4] = 0x0FBFDCB7; // 0x1010 AGC_Ctrl5
1737 pltmp[5] = 0x00caa333; // 0x1014 AGC_Ctrl6
1738 pltmp[6] = 0xf6632112; // 0x1018 AGC_Ctrl7
1739 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1740 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
1741 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1742 pltmp[10] = 0x40000228;
1743 pltmp[11] = 0x232A9F30;// 0x102c A_ACQ_Ctrl
1744 pWb35Reg->BB2c = 0x232A9F30;
1745 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1746
1747 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1748 pWb35Reg->BB30 = 0x00002C54;
1749 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1750 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1751 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1752 pWb35Reg->BB3c = 0x00000000;
1753 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1754 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1755 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
1756 pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter
1757 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
1758 pWb35Reg->BB50 = 0x27106200;
1759 pltmp[9] = 0; // 0x1054
1760 pWb35Reg->BB54 = 0x00000000;
1761 pltmp[10] = 0x64645252; // 0x1058 IQ_Alpha
1762 pWb35Reg->BB58 = 0x64645252;
1763 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1764 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1765*/
1766 BBProcessor_AL7230_2400( pHwData );
1767
1768 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1769 break;
1770
1771 case RF_WB_242:
1772 case RF_WB_242_1: // 20060619.5 Add
1773
1774 pltmp[0] = 0x16A8525D; // 0x1000 AGC_Ctrl1
1775 pltmp[1] = 0x9AFF9ABA; // 0x1004 AGC_Ctrl2
1776 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
1777 pltmp[3] = 0xEEE91C32; // 0x100c AGC_Ctrl4
1778 pWb35Reg->BB0C = 0xEEE91C32;
1779 pltmp[4] = 0x0FACDCC5; // 0x1010 AGC_Ctrl5
1780 pltmp[5] = 0x000AA344; // 0x1014 AGC_Ctrl6
1781 pltmp[6] = 0x22222221; // 0x1018 AGC_Ctrl7
1782 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1783 pltmp[8] = 0x04CC3440; // 20051018 0x03CB3440; // 0x1020 AGC_Ctrl9 20051014 0x03C33440
1784 pltmp[9] = 0xA9002A79; // 0x1024 AGC_Ctrl10
1785 pltmp[10] = 0x40000528; // 0x1028
1786 pltmp[11] = 0x23457F30; // 0x102c A_ACQ_Ctrl
1787 pWb35Reg->BB2C = 0x23457F30;
1788 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1789
1790 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1791 pWb35Reg->BB30 = 0x00002C54;
1792 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1793 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1794 pltmp[3] = pHwData->BB3c_cal; // 0x103c 11a TX LS filter
1795 pWb35Reg->BB3C = pHwData->BB3c_cal;
1796 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1797 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1798 pltmp[6] = BB48_DEFAULT_WB242_11G; // 0x1048 11b TX RC filter 20060613.2
1799 pWb35Reg->BB48 = BB48_DEFAULT_WB242_11G; // 20060613.1 20060613.2
1800 pltmp[7] = BB4C_DEFAULT_WB242_11G; // 0x104c 11b TX RC filter 20060613.2
1801 pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11G; // 20060613.1 20060613.2
1802 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1803 pWb35Reg->BB50 = 0x27106208;
1804 pltmp[9] = pHwData->BB54_cal; // 0x1054
1805 pWb35Reg->BB54 = pHwData->BB54_cal;
1806 pltmp[10] = 0x52523131; // 0x1058 IQ_Alpha
1807 pWb35Reg->BB58 = 0x52523131;
1808 pltmp[11] = 0xAA0AC000; // 20060825 0xAA2AC000; // 0x105c DC_Cancel
1809 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1810
1811 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1812 break;
1813 }
1814
1815 // Fill the LNA table
1816 pWb35Reg->LNAValue[0] = (u8)(pWb35Reg->BB0C & 0xff);
1817 pWb35Reg->LNAValue[1] = 0;
1818 pWb35Reg->LNAValue[2] = (u8)((pWb35Reg->BB0C & 0xff00)>>8);
1819 pWb35Reg->LNAValue[3] = 0;
1820
1821 // Fill SQ3 table
1822 for( i=0; i<MAX_SQ3_FILTER_SIZE; i++ )
1823 pWb35Reg->SQ3_filter[i] = 0x2f; // half of Bit 0 ~ 6
1824}
1825
1826void set_tx_power_per_channel_max2829( phw_data_t pHwData, ChanInfo Channel)
1827{
1828 RFSynthesizer_SetPowerIndex( pHwData, 100 ); // 20060620.1 Modify
1829}
1830
1831void set_tx_power_per_channel_al2230( phw_data_t pHwData, ChanInfo Channel )
1832{
1833 u8 index = 100;
1834
1835 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) // 20060620.1 Add
1836 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1837
1838 RFSynthesizer_SetPowerIndex( pHwData, index );
1839}
1840
1841void set_tx_power_per_channel_al7230( phw_data_t pHwData, ChanInfo Channel)
1842{
1843 u8 i, index = 100;
1844
1845 switch ( Channel.band )
1846 {
1847 case BAND_TYPE_DSSS:
1848 case BAND_TYPE_OFDM_24:
1849 {
1850 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1851 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1852 }
1853 break;
1854 case BAND_TYPE_OFDM_5:
1855 {
1856 for (i =0; i<35; i++)
1857 {
1858 if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo)
1859 {
1860 if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff)
1861 index = pHwData->TxVgaFor50[i].TxVgaValue;
1862 break;
1863 }
1864 }
1865 }
1866 break;
1867 }
1868 RFSynthesizer_SetPowerIndex( pHwData, index );
1869}
1870
1871void set_tx_power_per_channel_wb242( phw_data_t pHwData, ChanInfo Channel)
1872{
1873 u8 index = 100;
1874
1875 switch ( Channel.band )
1876 {
1877 case BAND_TYPE_DSSS:
1878 case BAND_TYPE_OFDM_24:
1879 {
1880 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1881 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1882 }
1883 break;
1884 case BAND_TYPE_OFDM_5:
1885 break;
1886 }
1887 RFSynthesizer_SetPowerIndex( pHwData, index );
1888}
1889
1890//=============================================================================================================
1891// RFSynthesizer_SwitchingChannel --
1892//
1893// Description:
1894// Swithch the RF channel.
1895//
1896// Arguments:
1897// pHwData - Handle of the USB Device.
1898// Channel - The channel no.
1899//
1900// Return values:
1901// None.
1902//=============================================================================================================
1903void
1904RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel )
1905{
1906 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
1907 u32 pltmp[16]; // The 16 is the maximum capability of hardware
1908 u32 count, ltmp;
1909 u8 i, j, number;
1910 u8 ChnlTmp;
1911
1912 switch( pHwData->phy_type )
1913 {
1914 case RF_MAXIM_2825:
1915 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1916
1917 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
1918 {
1919 for( i=0; i<3; i++ )
1920 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_channel_data_24[Channel.ChanNo-1][i], 18);
1921 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1922 }
1923 RFSynthesizer_SetPowerIndex( pHwData, 100 );
1924 break;
1925
1926 case RF_MAXIM_2827:
1927
1928 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
1929 {
1930 for( i=0; i<3; i++ )
1931 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_24[Channel.ChanNo-1][i], 18);
1932 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1933 }
1934 else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64
1935 {
1936 ChnlTmp = (Channel.ChanNo - 36) / 4;
1937 for( i=0; i<3; i++ )
1938 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_50[ChnlTmp][i], 18);
1939 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1940 }
1941 RFSynthesizer_SetPowerIndex( pHwData, 100 );
1942 break;
1943
1944 case RF_MAXIM_2828:
1945
1946 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
1947 {
1948 for( i=0; i<3; i++ )
1949 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_24[Channel.ChanNo-1][i], 18);
1950 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1951 }
1952 else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64
1953 {
1954 ChnlTmp = (Channel.ChanNo - 36) / 4;
1955 for ( i = 0; i < 3; i++)
1956 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_50[ChnlTmp][i], 18);
1957 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1958 }
1959 RFSynthesizer_SetPowerIndex( pHwData, 100 );
1960 break;
1961
1962 case RF_MAXIM_2829:
1963
1964 if( Channel.band <= BAND_TYPE_OFDM_24)
1965 {
1966 for( i=0; i<3; i++ )
1967 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_24[Channel.ChanNo-1][i], 18);
1968 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1969 }
1970 else if( Channel.band == BAND_TYPE_OFDM_5 )
1971 {
1972 count = sizeof(max2829_channel_data_50) / sizeof(max2829_channel_data_50[0]);
1973
1974 for( i=0; i<count; i++ )
1975 {
1976 if( max2829_channel_data_50[i][0] == Channel.ChanNo )
1977 {
1978 for( j=0; j<3; j++ )
1979 pltmp[j] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_50[i][j+1], 18);
1980 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1981
1982 if( (max2829_channel_data_50[i][3] & 0x3FFFF) == 0x2A946 )
1983 {
1984 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A906, 18);
1985 Wb35Reg_Write( pHwData, 0x0864, ltmp );
1986 }
1987 else // 0x2A9C6
1988 {
1989 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A986, 18);
1990 Wb35Reg_Write( pHwData, 0x0864, ltmp );
1991 }
1992 }
1993 }
1994 }
1995 set_tx_power_per_channel_max2829( pHwData, Channel );
1996 break;
1997
1998 case RF_AIROHA_2230:
1999 case RF_AIROHA_2230S: // 20060420 Add this
2000
2001 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
2002 {
2003 for( i=0; i<2; i++ )
2004 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_channel_data_24[Channel.ChanNo-1][i], 20);
2005 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT );
2006 }
2007 set_tx_power_per_channel_al2230( pHwData, Channel );
2008 break;
2009
2010 case RF_AIROHA_7230:
2011
2012 //Start to fill RF parameters, PLL_ON should be pulled low.
2013 //Wb35Reg_Write( pHwData, 0x03dc, 0x00000000 );
2014 //WBDEBUG(("* PLL_ON low\n"));
2015
2016 //Channel independent registers
2017 if( Channel.band != pHwData->band)
2018 {
2019 if (Channel.band <= BAND_TYPE_OFDM_24)
2020 {
2021 //Update BB register
2022 BBProcessor_AL7230_2400(pHwData);
2023
2024 number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]);
2025 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
2026 }
2027 else
2028 {
2029 //Update BB register
2030 BBProcessor_AL7230_5000(pHwData);
2031
2032 number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]);
2033 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
2034 }
2035
2036 // Write to register. number must less and equal than 16
2037 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, number, NO_INCREMENT );
2038 #ifdef _PE_STATE_DUMP_
2039 WBDEBUG(("Band changed\n"));
2040 #endif
2041 }
2042
2043 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
2044 {
2045 for( i=0; i<2; i++ )
2046 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24[Channel.ChanNo-1][i]&0xffffff);
2047 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT );
2048 }
2049 else if( Channel.band == BAND_TYPE_OFDM_5 )
2050 {
2051 //Update Reg12
2052 if ((Channel.ChanNo > 64) && (Channel.ChanNo <= 165))
2053 {
2054 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c;
2055 Wb35Reg_Write( pHwData, 0x0864, ltmp );
2056 }
2057 else //reg12 = 0x00147c at Channel 4920 ~ 5320
2058 {
2059 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c;
2060 Wb35Reg_Write( pHwData, 0x0864, ltmp );
2061 }
2062
2063 count = sizeof(al7230_channel_data_5) / sizeof(al7230_channel_data_5[0]);
2064
2065 for (i=0; i<count; i++)
2066 {
2067 if (al7230_channel_data_5[i][0] == Channel.ChanNo)
2068 {
2069 for( j=0; j<3; j++ )
2070 pltmp[j] = (1 << 31) | (0 << 30) | (24 << 24) | ( al7230_channel_data_5[i][j+1]&0xffffff);
2071 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
2072 }
2073 }
2074 }
2075 set_tx_power_per_channel_al7230(pHwData, Channel);
2076 break;
2077
2078 case RF_WB_242:
2079 case RF_WB_242_1: // 20060619.5 Add
2080
2081 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
2082 {
2083 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_channel_data_24[Channel.ChanNo-1][0], 24);
2084 Wb35Reg_Write( pHwData, 0x864, ltmp );
2085 }
2086 set_tx_power_per_channel_wb242(pHwData, Channel);
2087 break;
2088 }
2089
2090 if( Channel.band <= BAND_TYPE_OFDM_24 )
2091 {
2092 // BB: select 2.4 GHz, bit[12-11]=00
2093 pWb35Reg->BB50 &= ~(BIT(11)|BIT(12));
2094 Wb35Reg_Write( pHwData, 0x1050, pWb35Reg->BB50 ); // MODE_Ctrl
2095 // MAC: select 2.4 GHz, bit[5]=0
2096 pWb35Reg->M78_ERPInformation &= ~BIT(5);
2097 Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation );
2098 // enable 11b Baseband
2099 pWb35Reg->BB30 &= ~BIT(31);
2100 Wb35Reg_Write( pHwData, 0x1030, pWb35Reg->BB30 );
2101 }
2102 else if( (Channel.band == BAND_TYPE_OFDM_5) )
2103 {
2104 // BB: select 5 GHz
2105 pWb35Reg->BB50 &= ~(BIT(11)|BIT(12));
2106 if (Channel.ChanNo <=64 )
2107 pWb35Reg->BB50 |= BIT(12); // 10-5.25GHz
2108 else if ((Channel.ChanNo >= 100) && (Channel.ChanNo <= 124))
2109 pWb35Reg->BB50 |= BIT(11); // 01-5.48GHz
2110 else if ((Channel.ChanNo >=128) && (Channel.ChanNo <= 161))
2111 pWb35Reg->BB50 |= (BIT(12)|BIT(11)); // 11-5.775GHz
2112 else //Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25
2113 pWb35Reg->BB50 |= BIT(12);
2114 Wb35Reg_Write( pHwData, 0x1050, pWb35Reg->BB50 ); // MODE_Ctrl
2115
2116 //(1) M78 should alway use 2.4G setting when using RF_AIROHA_7230
2117 //(2) BB30 has been updated previously.
2118 if (pHwData->phy_type != RF_AIROHA_7230)
2119 {
2120 // MAC: select 5 GHz, bit[5]=1
2121 pWb35Reg->M78_ERPInformation |= BIT(5);
2122 Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation );
2123
2124 // disable 11b Baseband
2125 pWb35Reg->BB30 |= BIT(31);
2126 Wb35Reg_Write( pHwData, 0x1030, pWb35Reg->BB30 );
2127 }
2128 }
2129}
2130
2131//Set the tx power directly from DUT GUI, not from the EEPROM. Return the current setting
2132u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex )
2133{
2134 u32 Band = pHwData->band;
2135 u8 index=0;
2136
2137 if( pHwData->power_index == PowerIndex ) // 20060620.1 Add
2138 return PowerIndex;
2139
2140 if (RF_MAXIM_2825 == pHwData->phy_type)
2141 {
2142 // Channel 1 - 13
2143 index = RFSynthesizer_SetMaxim2825Power( pHwData, PowerIndex );
2144 }
2145 else if (RF_MAXIM_2827 == pHwData->phy_type)
2146 {
2147 if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13
2148 index = RFSynthesizer_SetMaxim2827_24Power( pHwData, PowerIndex );
2149 else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64
2150 index = RFSynthesizer_SetMaxim2827_50Power( pHwData, PowerIndex );
2151 }
2152 else if (RF_MAXIM_2828 == pHwData->phy_type)
2153 {
2154 if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13
2155 index = RFSynthesizer_SetMaxim2828_24Power( pHwData, PowerIndex );
2156 else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64
2157 index = RFSynthesizer_SetMaxim2828_50Power( pHwData, PowerIndex );
2158 }
2159 else if( RF_AIROHA_2230 == pHwData->phy_type )
2160 {
2161 //Power index: 0 ~ 63 // Channel 1 - 14
2162 index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex );
2163 index = (u8)al2230_txvga_data[index][1];
2164 }
2165 else if( RF_AIROHA_2230S == pHwData->phy_type ) // 20060420 Add this
2166 {
2167 //Power index: 0 ~ 63 // Channel 1 - 14
2168 index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex );
2169 index = (u8)al2230_txvga_data[index][1];
2170 }
2171 else if( RF_AIROHA_7230 == pHwData->phy_type )
2172 {
2173 //Power index: 0 ~ 63
2174 index = RFSynthesizer_SetAiroha7230Power( pHwData, PowerIndex );
2175 index = (u8)al7230_txvga_data[index][1];
2176 }
2177 else if( (RF_WB_242 == pHwData->phy_type) ||
2178 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
2179 {
2180 //Power index: 0 ~ 19 for original. New range is 0 ~ 33
2181 index = RFSynthesizer_SetWinbond242Power( pHwData, PowerIndex );
2182 index = (u8)w89rf242_txvga_data[index][1];
2183 }
2184
2185 pHwData->power_index = index; // Backup current
2186 return index;
2187}
2188
2189//-- Sub function
2190u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t pHwData, u8 index )
2191{
2192 u32 PowerData;
2193 if( index > 1 ) index = 1;
2194 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_24[index], 18);
2195 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2196 return index;
2197}
2198//--
2199u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t pHwData, u8 index )
2200{
2201 u32 PowerData;
2202 if( index > 1 ) index = 1;
2203 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_50[index], 18);
2204 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2205 return index;
2206}
2207//--
2208u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t pHwData, u8 index )
2209{
2210 u32 PowerData;
2211 if( index > 1 ) index = 1;
2212 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_24[index], 18);
2213 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2214 return index;
2215}
2216//--
2217u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t pHwData, u8 index )
2218{
2219 u32 PowerData;
2220 if( index > 1 ) index = 1;
2221 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_50[index], 18);
2222 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2223 return index;
2224}
2225//--
2226u8 RFSynthesizer_SetMaxim2825Power( phw_data_t pHwData, u8 index )
2227{
2228 u32 PowerData;
2229 if( index > 1 ) index = 1;
2230 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_power_data_24[index], 18);
2231 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2232 return index;
2233}
2234//--
2235u8 RFSynthesizer_SetAiroha2230Power( phw_data_t pHwData, u8 index )
2236{
2237 u32 PowerData;
2238 u8 i,count;
2239
2240 count = sizeof(al2230_txvga_data) / sizeof(al2230_txvga_data[0]);
2241 for (i=0; i<count; i++)
2242 {
2243 if (al2230_txvga_data[i][1] >= index)
2244 break;
2245 }
2246 if (i == count)
2247 i--;
2248
2249 PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_txvga_data[i][0], 20);
2250 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2251 return i;
2252}
2253//--
2254u8 RFSynthesizer_SetAiroha7230Power( phw_data_t pHwData, u8 index )
2255{
2256 u32 PowerData;
2257 u8 i,count;
2258
2259 //PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( airoha_power_data_24[index], 20);
2260 count = sizeof(al7230_txvga_data) / sizeof(al7230_txvga_data[0]);
2261 for (i=0; i<count; i++)
2262 {
2263 if (al7230_txvga_data[i][1] >= index)
2264 break;
2265 }
2266 if (i == count)
2267 i--;
2268 PowerData = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data[i][0]&0xffffff);
2269 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2270 return i;
2271}
2272
2273u8 RFSynthesizer_SetWinbond242Power( phw_data_t pHwData, u8 index )
2274{
2275 u32 PowerData;
2276 u8 i,count;
2277
2278 count = sizeof(w89rf242_txvga_data) / sizeof(w89rf242_txvga_data[0]);
2279 for (i=0; i<count; i++)
2280 {
2281 if (w89rf242_txvga_data[i][1] >= index)
2282 break;
2283 }
2284 if (i == count)
2285 i--;
2286
2287 // Set TxVga into RF
2288 PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_txvga_data[i][0], 24);
2289 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2290
2291 // Update BB48 BB4C BB58 for high precision txvga
2292 Wb35Reg_Write( pHwData, 0x1048, w89rf242_txvga_data[i][2] );
2293 Wb35Reg_Write( pHwData, 0x104c, w89rf242_txvga_data[i][3] );
2294 Wb35Reg_Write( pHwData, 0x1058, w89rf242_txvga_data[i][4] );
2295
2296// Rf vga 0 ~ 3 for temperature compensate. It will affect the scan Bss.
2297// The i value equals to 8 or 7 usually. So It's not necessary to setup this RF register.
2298// if( i <= 3 )
2299// PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x000024, 24 );
2300// else
2301// PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x001824, 24 );
2302// Wb35Reg_Write( pHwData, 0x0864, PowerData );
2303 return i;
2304}
2305
2306//===========================================================================================================
2307// Dxx_initial --
2308// Mxx_initial --
2309 //
2310// Routine Description:
2311// Initial the hardware setting and module variable
2312 //
2313//===========================================================================================================
2314void Dxx_initial( phw_data_t pHwData )
2315{
2316 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
2317
2318 // Old IC:Single mode only.
2319 // New IC: operation decide by Software set bit[4]. 1:multiple 0: single
2320 pWb35Reg->D00_DmaControl = 0xc0000004; //Txon, Rxon, multiple Rx for new 4k DMA
2321 //Txon, Rxon, single Rx for old 8k ASIC
2322 if( !HAL_USB_MODE_BURST( pHwData ) )
2323 pWb35Reg->D00_DmaControl = 0xc0000000;//Txon, Rxon, single Rx for new 4k DMA
2324
2325 Wb35Reg_WriteSync( pHwData, 0x0400, pWb35Reg->D00_DmaControl );
2326}
2327
2328void Mxx_initial( phw_data_t pHwData )
2329{
2330 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
2331 u32 tmp;
2332 u32 pltmp[11];
2333 u16 i;
2334
2335
2336 //======================================================
2337 // Initial Mxx register
2338 //======================================================
2339
2340 // M00 bit set
2341#ifdef _IBSS_BEACON_SEQ_STICK_
2342 pWb35Reg->M00_MacControl = 0; // Solve beacon sequence number stop by software
2343#else
2344 pWb35Reg->M00_MacControl = 0x80000000; // Solve beacon sequence number stop by hardware
2345#endif
2346
2347 // M24 disable enter power save, BB RxOn and enable NAV attack
2348 pWb35Reg->M24_MacControl = 0x08040042;
2349 pltmp[0] = pWb35Reg->M24_MacControl;
2350
2351 pltmp[1] = 0; // Skip M28, because no initialize value is required.
2352
2353 // M2C CWmin and CWmax setting
2354 pHwData->cwmin = DEFAULT_CWMIN;
2355 pHwData->cwmax = DEFAULT_CWMAX;
2356 pWb35Reg->M2C_MacControl = DEFAULT_CWMIN << 10;
2357 pWb35Reg->M2C_MacControl |= DEFAULT_CWMAX;
2358 pltmp[2] = pWb35Reg->M2C_MacControl;
2359
2360 // M30 BSSID
2361 pltmp[3] = *(PULONG)pHwData->bssid;
2362
2363 // M34
2364 pHwData->AID = DEFAULT_AID;
2365 tmp = *(PUSHORT)(pHwData->bssid+4);
2366 tmp |= DEFAULT_AID << 16;
2367 pltmp[4] = tmp;
2368
2369 // M38
2370 pWb35Reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT<<8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT;
2371 pltmp[5] = pWb35Reg->M38_MacControl;
2372
2373 // M3C
2374 tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ;
2375 pWb35Reg->M3C_MacControl = tmp;
2376 pltmp[6] = tmp;
2377
2378 // M40
2379 pHwData->slot_time_select = DEFAULT_SLOT_TIME;
2380 tmp = (DEFAULT_ATIMWD << 16) | DEFAULT_SLOT_TIME;
2381 pWb35Reg->M40_MacControl = tmp;
2382 pltmp[7] = tmp;
2383
2384 // M44
2385 tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; // *1024
2386 pWb35Reg->M44_MacControl = tmp;
2387 pltmp[8] = tmp;
2388
2389 // M48
2390 pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL;
2391 pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME;
2392 tmp = (DEFAULT_BEACON_INTERVAL << 16) | DEFAULT_PROBE_DELAY_TIME;
2393 pWb35Reg->M48_MacControl = tmp;
2394 pltmp[9] = tmp;
2395
2396 //M4C
2397 pWb35Reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24);
2398 pltmp[10] = pWb35Reg->M4C_MacStatus;
2399
2400 // Burst write
2401 //Wb35Reg_BurstWrite( pHwData, 0x0824, pltmp, 11, AUTO_INCREMENT );
2402 for( i=0; i<11; i++ )
2403 Wb35Reg_WriteSync( pHwData, 0x0824 + i*4, pltmp[i] );
2404
2405 // M60
2406 Wb35Reg_WriteSync( pHwData, 0x0860, 0x12481248 );
2407 pWb35Reg->M60_MacControl = 0x12481248;
2408
2409 // M68
2410 Wb35Reg_WriteSync( pHwData, 0x0868, 0x00050900 ); // 20051018 0x000F0F00 ); // 940930 0x00131300
2411 pWb35Reg->M68_MacControl = 0x00050900;
2412
2413 // M98
2414 Wb35Reg_WriteSync( pHwData, 0x0898, 0xffff8888 );
2415 pWb35Reg->M98_MacControl = 0xffff8888;
2416}
2417
2418
2419void Uxx_power_off_procedure( phw_data_t pHwData )
2420{
2421 // SW, PMU reset and turn off clock
2422 Wb35Reg_WriteSync( pHwData, 0x03b0, 3 );
2423 Wb35Reg_WriteSync( pHwData, 0x03f0, 0xf9 );
2424}
2425
2426//Decide the TxVga of every channel
2427void GetTxVgaFromEEPROM( phw_data_t pHwData )
2428{
2429 u32 i, j, ltmp;
2430 u16 Value[MAX_TXVGA_EEPROM];
2431 PUCHAR pctmp;
2432 u8 ctmp=0;
2433
2434 // Get the entire TxVga setting in EEPROM
2435 for( i=0; i<MAX_TXVGA_EEPROM; i++ )
2436 {
2437 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 + 0x00010000*i );
2438 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
2439 Value[i] = (u16)( ltmp & 0xffff ); // Get 16 bit available
2440 Value[i] = cpu_to_le16( Value[i] ); // [7:0]2412 [7:0]2417 ....
2441 }
2442
2443 // Adjust the filed which fills with reserved value.
2444 pctmp = (PUCHAR)Value;
2445 for( i=0; i<(MAX_TXVGA_EEPROM*2); i++ )
2446 {
2447 if( pctmp[i] != 0xff )
2448 ctmp = pctmp[i];
2449 else
2450 pctmp[i] = ctmp;
2451 }
2452
2453 // Adjust WB_242 to WB_242_1 TxVga scale
2454 if( pHwData->phy_type == RF_WB_242 )
2455 {
2456 for( i=0; i<4; i++ ) // Only 2412 2437 2462 2484 case must be modified
2457 {
2458 for( j=0; j<(sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])); j++ )
2459 {
2460 if( pctmp[i] < (u8)w89rf242_txvga_old_mapping[j][1] )
2461 {
2462 pctmp[i] = (u8)w89rf242_txvga_old_mapping[j][0];
2463 break;
2464 }
2465 }
2466
2467 if( j == (sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])) )
2468 pctmp[i] = (u8)w89rf242_txvga_old_mapping[j-1][0];
2469 }
2470 }
2471
2472 // 20060621 Add
2473 memcpy( pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM*2 ); //MAX_TXVGA_EEPROM is u16 count
2474 EEPROMTxVgaAdjust( pHwData );
2475}
2476
2477// This function will affect the TxVga parameter in HAL. If hal_set_current_channel
2478// or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect.
2479// TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35
2480// This function will use default TxVgaSettingInEEPROM data to calculate new TxVga.
2481void EEPROMTxVgaAdjust( phw_data_t pHwData ) // 20060619.5 Add
2482{
2483 PUCHAR pTxVga = pHwData->TxVgaSettingInEEPROM;
2484 s16 i, stmp;
2485
2486 //-- 2.4G -- 20060704.2 Request from Tiger
2487 //channel 1 ~ 5
2488 stmp = pTxVga[1] - pTxVga[0];
2489 for( i=0; i<5; i++ )
2490 pHwData->TxVgaFor24[i] = pTxVga[0] + stmp*i/4;
2491 //channel 6 ~ 10
2492 stmp = pTxVga[2] - pTxVga[1];
2493 for( i=5; i<10; i++ )
2494 pHwData->TxVgaFor24[i] = pTxVga[1] + stmp*(i-5)/4;
2495 //channel 11 ~ 13
2496 stmp = pTxVga[3] - pTxVga[2];
2497 for( i=10; i<13; i++ )
2498 pHwData->TxVgaFor24[i] = pTxVga[2] + stmp*(i-10)/2;
2499 //channel 14
2500 pHwData->TxVgaFor24[13] = pTxVga[3];
2501
2502 //-- 5G --
2503 if( pHwData->phy_type == RF_AIROHA_7230 )
2504 {
2505 //channel 184
2506 pHwData->TxVgaFor50[0].ChanNo = 184;
2507 pHwData->TxVgaFor50[0].TxVgaValue = pTxVga[4];
2508 //channel 196
2509 pHwData->TxVgaFor50[3].ChanNo = 196;
2510 pHwData->TxVgaFor50[3].TxVgaValue = pTxVga[5];
2511 //interpolate
2512 pHwData->TxVgaFor50[1].ChanNo = 188;
2513 pHwData->TxVgaFor50[2].ChanNo = 192;
2514 stmp = pTxVga[5] - pTxVga[4];
2515 pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp/3;
2516 pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp*2/3;
2517
2518 //channel 16
2519 pHwData->TxVgaFor50[6].ChanNo = 16;
2520 pHwData->TxVgaFor50[6].TxVgaValue = pTxVga[6];
2521 pHwData->TxVgaFor50[4].ChanNo = 8;
2522 pHwData->TxVgaFor50[4].TxVgaValue = pTxVga[6];
2523 pHwData->TxVgaFor50[5].ChanNo = 12;
2524 pHwData->TxVgaFor50[5].TxVgaValue = pTxVga[6];
2525
2526 //channel 36
2527 pHwData->TxVgaFor50[8].ChanNo = 36;
2528 pHwData->TxVgaFor50[8].TxVgaValue = pTxVga[7];
2529 pHwData->TxVgaFor50[7].ChanNo = 34;
2530 pHwData->TxVgaFor50[7].TxVgaValue = pTxVga[7];
2531 pHwData->TxVgaFor50[9].ChanNo = 38;
2532 pHwData->TxVgaFor50[9].TxVgaValue = pTxVga[7];
2533
2534 //channel 40
2535 pHwData->TxVgaFor50[10].ChanNo = 40;
2536 pHwData->TxVgaFor50[10].TxVgaValue = pTxVga[8];
2537 //channel 48
2538 pHwData->TxVgaFor50[14].ChanNo = 48;
2539 pHwData->TxVgaFor50[14].TxVgaValue = pTxVga[9];
2540 //interpolate
2541 pHwData->TxVgaFor50[11].ChanNo = 42;
2542 pHwData->TxVgaFor50[12].ChanNo = 44;
2543 pHwData->TxVgaFor50[13].ChanNo = 46;
2544 stmp = pTxVga[9] - pTxVga[8];
2545 pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp/4;
2546 pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp*2/4;
2547 pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp*3/4;
2548
2549 //channel 52
2550 pHwData->TxVgaFor50[15].ChanNo = 52;
2551 pHwData->TxVgaFor50[15].TxVgaValue = pTxVga[10];
2552 //channel 64
2553 pHwData->TxVgaFor50[18].ChanNo = 64;
2554 pHwData->TxVgaFor50[18].TxVgaValue = pTxVga[11];
2555 //interpolate
2556 pHwData->TxVgaFor50[16].ChanNo = 56;
2557 pHwData->TxVgaFor50[17].ChanNo = 60;
2558 stmp = pTxVga[11] - pTxVga[10];
2559 pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp/3;
2560 pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp*2/3;
2561
2562 //channel 100
2563 pHwData->TxVgaFor50[19].ChanNo = 100;
2564 pHwData->TxVgaFor50[19].TxVgaValue = pTxVga[12];
2565 //channel 112
2566 pHwData->TxVgaFor50[22].ChanNo = 112;
2567 pHwData->TxVgaFor50[22].TxVgaValue = pTxVga[13];
2568 //interpolate
2569 pHwData->TxVgaFor50[20].ChanNo = 104;
2570 pHwData->TxVgaFor50[21].ChanNo = 108;
2571 stmp = pTxVga[13] - pTxVga[12];
2572 pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp/3;
2573 pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp*2/3;
2574
2575 //channel 128
2576 pHwData->TxVgaFor50[26].ChanNo = 128;
2577 pHwData->TxVgaFor50[26].TxVgaValue = pTxVga[14];
2578 //interpolate
2579 pHwData->TxVgaFor50[23].ChanNo = 116;
2580 pHwData->TxVgaFor50[24].ChanNo = 120;
2581 pHwData->TxVgaFor50[25].ChanNo = 124;
2582 stmp = pTxVga[14] - pTxVga[13];
2583 pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp/4;
2584 pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp*2/4;
2585 pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp*3/4;
2586
2587 //channel 140
2588 pHwData->TxVgaFor50[29].ChanNo = 140;
2589 pHwData->TxVgaFor50[29].TxVgaValue = pTxVga[15];
2590 //interpolate
2591 pHwData->TxVgaFor50[27].ChanNo = 132;
2592 pHwData->TxVgaFor50[28].ChanNo = 136;
2593 stmp = pTxVga[15] - pTxVga[14];
2594 pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp/3;
2595 pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp*2/3;
2596
2597 //channel 149
2598 pHwData->TxVgaFor50[30].ChanNo = 149;
2599 pHwData->TxVgaFor50[30].TxVgaValue = pTxVga[16];
2600 //channel 165
2601 pHwData->TxVgaFor50[34].ChanNo = 165;
2602 pHwData->TxVgaFor50[34].TxVgaValue = pTxVga[17];
2603 //interpolate
2604 pHwData->TxVgaFor50[31].ChanNo = 153;
2605 pHwData->TxVgaFor50[32].ChanNo = 157;
2606 pHwData->TxVgaFor50[33].ChanNo = 161;
2607 stmp = pTxVga[17] - pTxVga[16];
2608 pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp/4;
2609 pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp*2/4;
2610 pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp*3/4;
2611 }
2612
2613 #ifdef _PE_STATE_DUMP_
2614 WBDEBUG((" TxVgaFor24 : \n"));
2615 DataDmp((u8 *)pHwData->TxVgaFor24, 14 ,0);
2616 WBDEBUG((" TxVgaFor50 : \n"));
2617 DataDmp((u8 *)pHwData->TxVgaFor50, 70 ,0);
2618 #endif
2619}
2620
2621void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ) // 20060613.1
2622{
2623 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
2624 unsigned char Is11bRate;
2625
2626 Is11bRate = (rate % 6) ? 1 : 0;
2627 switch( pHwData->phy_type )
2628 {
2629 case RF_AIROHA_2230:
2630 case RF_AIROHA_2230S: // 20060420 Add this
2631 if( Is11bRate )
2632 {
2633 if( (pWb35Reg->BB48 != BB48_DEFAULT_AL2230_11B) &&
2634 (pWb35Reg->BB4C != BB4C_DEFAULT_AL2230_11B) )
2635 {
2636 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11B );
2637 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B );
2638 }
2639 }
2640 else
2641 {
2642 if( (pWb35Reg->BB48 != BB48_DEFAULT_AL2230_11G) &&
2643 (pWb35Reg->BB4C != BB4C_DEFAULT_AL2230_11G) )
2644 {
2645 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11G );
2646 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G );
2647 }
2648 }
2649 break;
2650
2651 case RF_WB_242: // 20060623 The fix only for old TxVGA setting
2652 if( Is11bRate )
2653 {
2654 if( (pWb35Reg->BB48 != BB48_DEFAULT_WB242_11B) &&
2655 (pWb35Reg->BB4C != BB4C_DEFAULT_WB242_11B) )
2656 {
2657 pWb35Reg->BB48 = BB48_DEFAULT_WB242_11B;
2658 pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11B;
2659 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11B );
2660 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11B );
2661 }
2662 }
2663 else
2664 {
2665 if( (pWb35Reg->BB48 != BB48_DEFAULT_WB242_11G) &&
2666 (pWb35Reg->BB4C != BB4C_DEFAULT_WB242_11G) )
2667 {
2668 pWb35Reg->BB48 = BB48_DEFAULT_WB242_11G;
2669 pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11G;
2670 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11G );
2671 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11G );
2672 }
2673 }
2674 break;
2675 }
2676}
2677
2678
2679
2680
2681
2682
2683
diff --git a/drivers/staging/winbond/rxisr.c b/drivers/staging/winbond/rxisr.c
new file mode 100644
index 000000000000..18e942c9b821
--- /dev/null
+++ b/drivers/staging/winbond/rxisr.c
@@ -0,0 +1,30 @@
1#include "os_common.h"
2
3void vRxTimerInit(PWB32_ADAPTER Adapter)
4{
5 OS_TIMER_INITIAL(&(Adapter->Mds.nTimer), (void*) RxTimerHandler, (void*) Adapter);
6}
7
8void vRxTimerStart(PWB32_ADAPTER Adapter, int timeout_value)
9{
10 if (timeout_value<MIN_TIMEOUT_VAL)
11 timeout_value=MIN_TIMEOUT_VAL;
12
13 OS_TIMER_SET( &(Adapter->Mds.nTimer), timeout_value );
14}
15
16void vRxTimerStop(PWB32_ADAPTER Adapter)
17{
18 OS_TIMER_CANCEL( &(Adapter->Mds.nTimer), 0 );
19}
20
21void RxTimerHandler_1a( PADAPTER Adapter)
22{
23 RxTimerHandler(NULL, Adapter, NULL, NULL);
24}
25
26void RxTimerHandler(void* SystemSpecific1, PWB32_ADAPTER Adapter,
27 void* SystemSpecific2, void* SystemSpecific3)
28{
29 WARN_ON(1);
30}
diff --git a/drivers/staging/winbond/scan_s.h b/drivers/staging/winbond/scan_s.h
new file mode 100644
index 000000000000..1d1b0c4fec17
--- /dev/null
+++ b/drivers/staging/winbond/scan_s.h
@@ -0,0 +1,115 @@
1//
2// SCAN task global CONSTANTS, STRUCTURES, variables
3//
4
5//////////////////////////////////////////////////////////////////////////
6//define the msg type of SCAN module
7#define SCANMSG_SCAN_REQ 0x01
8#define SCANMSG_BEACON 0x02
9#define SCANMSG_PROBE_RESPONSE 0x03
10#define SCANMSG_TIMEOUT 0x04
11#define SCANMSG_TXPROBE_FAIL 0x05
12#define SCANMSG_ENABLE_BGSCAN 0x06
13#define SCANMSG_STOP_SCAN 0x07
14
15// BSS Type =>conform to
16// IBSS : ToDS/FromDS = 00
17// Infrastructure : ToDS/FromDS = 01
18#define IBSS_NET 0
19#define ESS_NET 1
20#define ANYBSS_NET 2
21
22// Scan Type
23#define ACTIVE_SCAN 0
24#define PASSIVE_SCAN 1
25
26///////////////////////////////////////////////////////////////////////////
27//Global data structures, Initial Scan & Background Scan
28typedef struct _SCAN_REQ_PARA //mandatory parameters for SCAN request
29{
30 u32 ScanType; //passive/active scan
31
32 CHAN_LIST sChannelList; // 86B
33 u8 reserved_1[2];
34
35 struct SSID_Element sSSID; // 34B. scan only for this SSID
36 u8 reserved_2[2];
37
38} SCAN_REQ_PARA, *psSCAN_REQ_PARA;
39
40typedef struct _SCAN_PARAMETERS
41{
42 u16 wState;
43 u16 iCurrentChannelIndex;
44
45 SCAN_REQ_PARA sScanReq;
46
47 u8 BSSID[MAC_ADDR_LENGTH + 2]; //scan only for this BSSID
48
49 u32 BssType; //scan only for this BSS type
50
51 //struct SSID_Element sSSID; //scan only for this SSID
52 u16 ProbeDelay;
53 u16 MinChannelTime;
54
55 u16 MaxChannelTime;
56 u16 reserved_1;
57
58 s32 iBgScanPeriod; // XP: 5 sec
59
60 u8 boBgScan; // Wb: enable BG scan, For XP, this value must be FALSE
61 u8 boFastScan; // Wb: reserved
62 u8 boCCAbusy; // Wb: HWMAC CCA busy status
63 u8 reserved_2;
64
65 //NDIS_MINIPORT_TIMER nTimer;
66 OS_TIMER nTimer;
67
68 u32 ScanTimeStamp; //Increase 1 per background scan(1 minute)
69 u32 BssTimeStamp; //Increase 1 per connect status check
70 u32 RxNumPerAntenna[2]; //
71
72 u8 AntennaToggle; //
73 u8 boInTimerHandler;
74 u8 boTimerActive; // Wb: reserved
75 u8 boSave;
76
77 u32 BScanEnable; // Background scan enable. Default is On
78
79} SCAN_PARAMETERS, *psSCAN_PARAMETERS;
80
81// Encapsulate 'Adapter' data structure
82#define psSCAN (&(Adapter->sScanPara))
83#define psSCANREQ (&(Adapter->sScanPara.sScanReq))
84
85//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
86// scan.h
87// Define the related definitions of scan module
88// history -- 01/14/03' created
89//
90//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
91
92//Define the state of scan module
93#define SCAN_INACTIVE 0
94#define WAIT_PROBE_DELAY 1
95#define WAIT_RESPONSE_MIN 2
96#define WAIT_RESPONSE_MAX_ACTIVE 3
97#define WAIT_BEACON_MAX_PASSIVE 4
98#define SCAN_COMPLETE 5
99#define BG_SCAN 6
100#define BG_SCANNING 7
101
102
103// The value will load from EEPROM
104// If 0xff is set in EEPOM, the driver will use SCAN_MAX_CHNL_TIME instead.
105// The definition is in WbHal.h
106// #define SCAN_MAX_CHNL_TIME (50)
107
108
109
110// static functions
111
112//static void ScanTimerHandler(PWB32_ADAPTER Adapter);
113//static void vScanTimerStart(PWB32_ADAPTER Adapter, int timeout_value);
114//static void vScanTimerStop(PWB32_ADAPTER Adapter);
115
diff --git a/drivers/staging/winbond/sme_api.c b/drivers/staging/winbond/sme_api.c
new file mode 100644
index 000000000000..40e93b7600eb
--- /dev/null
+++ b/drivers/staging/winbond/sme_api.c
@@ -0,0 +1,13 @@
1//------------------------------------------------------------------------------------
2// sme_api.c
3//
4// Copyright(C) 2002 Winbond Electronics Corp.
5//
6//
7//------------------------------------------------------------------------------------
8#include "os_common.h"
9
10s8 sme_get_rssi(void *pcore_data, s32 *prssi)
11{
12 BUG();
13}
diff --git a/drivers/staging/winbond/sme_api.h b/drivers/staging/winbond/sme_api.h
new file mode 100644
index 000000000000..016b225ca4a4
--- /dev/null
+++ b/drivers/staging/winbond/sme_api.h
@@ -0,0 +1,265 @@
1/*
2 * sme_api.h
3 *
4 * Copyright(C) 2002 Winbond Electronics Corp.
5 *
6 * modification history
7 * ---------------------------------------------------------------------------
8 * 1.00.001, 2003-04-21, Kevin created
9 * 1.00.002, 2003-05-14, PD43 & PE20 modified
10 *
11 */
12
13#ifndef __SME_API_H__
14#define __SME_API_H__
15
16/****************** INCLUDE FILES SECTION ***********************************/
17//#include "GL\gl_core.h"
18
19/****************** CONSTANT AND MACRO SECTION ******************************/
20#define _INLINE __inline
21
22#define MEDIA_STATE_DISCONNECTED 0
23#define MEDIA_STATE_CONNECTED 1
24
25//ARRAY CHECK
26#define MAX_POWER_TO_DB 32
27
28/****************** TYPE DEFINITION SECTION *********************************/
29
30/****************** EXPORTED FUNCTION DECLARATION SECTION *******************/
31
32// OID_802_11_BSSID
33s8 sme_get_bssid(void *pcore_data, u8 *pbssid);
34s8 sme_get_desired_bssid(void *pcore_data, u8 *pbssid);//Not use
35s8 sme_set_desired_bssid(void *pcore_data, u8 *pbssid);
36
37// OID_802_11_SSID
38s8 sme_get_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);
39s8 sme_get_desired_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);// Not use
40s8 sme_set_desired_ssid(void *pcore_data, u8 *pssid, u8 ssid_len);
41
42// OID_802_11_INFRASTRUCTURE_MODE
43s8 sme_get_bss_type(void *pcore_data, u8 *pbss_type);
44s8 sme_get_desired_bss_type(void *pcore_data, u8 *pbss_type);//Not use
45s8 sme_set_desired_bss_type(void *pcore_data, u8 bss_type);
46
47// OID_802_11_FRAGMENTATION_THRESHOLD
48s8 sme_get_fragment_threshold(void *pcore_data, u32 *pthreshold);
49s8 sme_set_fragment_threshold(void *pcore_data, u32 threshold);
50
51// OID_802_11_RTS_THRESHOLD
52s8 sme_get_rts_threshold(void *pcore_data, u32 *pthreshold);
53s8 sme_set_rts_threshold(void *pcore_data, u32 threshold);
54
55// OID_802_11_RSSI
56s8 sme_get_rssi(void *pcore_data, s32 *prssi);
57
58// OID_802_11_CONFIGURATION
59s8 sme_get_beacon_period(void *pcore_data, u16 *pbeacon_period);
60s8 sme_set_beacon_period(void *pcore_data, u16 beacon_period);
61
62s8 sme_get_atim_window(void *pcore_data, u16 *patim_window);
63s8 sme_set_atim_window(void *pcore_data, u16 atim_window);
64
65s8 sme_get_current_channel(void *pcore_data, u8 *pcurrent_channel);
66s8 sme_get_current_band(void *pcore_data, u8 *pcurrent_band);
67s8 sme_set_current_channel(void *pcore_data, u8 current_channel);
68
69// OID_802_11_BSSID_LIST
70s8 sme_get_scan_bss_count(void *pcore_data, u8 *pcount);
71s8 sme_get_scan_bss(void *pcore_data, u8 index, void **ppbss);
72
73s8 sme_get_connected_bss(void *pcore_data, void **ppbss_now);
74
75// OID_802_11_AUTHENTICATION_MODE
76s8 sme_get_auth_mode(void *pcore_data, u8 *pauth_mode);
77s8 sme_set_auth_mode(void *pcore_data, u8 auth_mode);
78
79// OID_802_11_WEP_STATUS / OID_802_11_ENCRYPTION_STATUS
80s8 sme_get_wep_mode(void *pcore_data, u8 *pwep_mode);
81s8 sme_set_wep_mode(void *pcore_data, u8 wep_mode);
82//s8 sme_get_encryption_status(void *pcore_data, u8 *pstatus);
83//s8 sme_set_encryption_status(void *pcore_data, u8 status);
84
85// ???????????????????????????????????????
86
87// OID_GEN_VENDOR_ID
88// OID_802_3_PERMANENT_ADDRESS
89s8 sme_get_permanent_mac_addr(void *pcore_data, u8 *pmac_addr);
90
91// OID_802_3_CURRENT_ADDRESS
92s8 sme_get_current_mac_addr(void *pcore_data, u8 *pmac_addr);
93
94// OID_802_11_NETWORK_TYPE_IN_USE
95s8 sme_get_network_type_in_use(void *pcore_data, u8 *ptype);
96s8 sme_set_network_type_in_use(void *pcore_data, u8 type);
97
98// OID_802_11_SUPPORTED_RATES
99s8 sme_get_supported_rate(void *pcore_data, u8 *prates);
100
101// OID_802_11_ADD_WEP
102//12/29/03' wkchen
103s8 sme_set_add_wep(void *pcore_data, u32 key_index, u32 key_len,
104 u8 *Address, u8 *key);
105
106// OID_802_11_REMOVE_WEP
107s8 sme_set_remove_wep(void *pcre_data, u32 key_index);
108
109// OID_802_11_DISASSOCIATE
110s8 sme_set_disassociate(void *pcore_data);
111
112// OID_802_11_POWER_MODE
113s8 sme_get_power_mode(void *pcore_data, u8 *pmode);
114s8 sme_set_power_mode(void *pcore_data, u8 mode);
115
116// OID_802_11_BSSID_LIST_SCAN
117s8 sme_set_bssid_list_scan(void *pcore_data, void *pscan_para);
118
119// OID_802_11_RELOAD_DEFAULTS
120s8 sme_set_reload_defaults(void *pcore_data, u8 reload_type);
121
122
123// The following SME API functions are used for WPA
124//
125// Mandatory OIDs for WPA
126//
127
128// OID_802_11_ADD_KEY
129//s8 sme_set_add_key(void *pcore_data, NDIS_802_11_KEY *pkey);
130
131// OID_802_11_REMOVE_KEY
132//s8 sme_set_remove_key(void *pcore_data, NDIS_802_11_REMOVE_KEY *pkey);
133
134// OID_802_11_ASSOCIATION_INFORMATION
135//s8 sme_set_association_information(void *pcore_data,
136// NDIS_802_11_ASSOCIATION_INFORMATION *pinfo);
137
138// OID_802_11_TEST
139//s8 sme_set_test(void *pcore_data, NDIS_802_11_TEST *ptest_data);
140
141//--------------------------------------------------------------------------//
142/*
143// The left OIDs
144
145// OID_802_11_NETWORK_TYPES_SUPPORTED
146// OID_802_11_TX_POWER_LEVEL
147// OID_802_11_RSSI_TRIGGER
148// OID_802_11_NUMBER_OF_ANTENNAS
149// OID_802_11_RX_ANTENNA_SELECTED
150// OID_802_11_TX_ANTENNA_SELECTED
151// OID_802_11_STATISTICS
152// OID_802_11_DESIRED_RATES
153// OID_802_11_PRIVACY_FILTER
154
155*/
156
157/*------------------------- none-standard ----------------------------------*/
158s8 sme_get_connect_status(void *pcore_data, u8 *pstatus);
159
160/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
161//s8 sme_get_scan_type(void *pcore_data, u8 *pscan_type);
162//s8 sme_set_scan_type(void *pcore_data, u8 scan_type);
163
164//s8 sme_get_scan_channel_list(void *pcore_data, u8 *pscan_type);
165//s8 sme_set_scan_channel_list(void *pcore_data, u8 scan_type);
166
167
168void sme_get_encryption_status(void *pcore_data, u8 *EncryptStatus);
169void sme_set_encryption_status(void *pcore_data, u8 EncryptStatus);
170s8 sme_add_key(void *pcore_data,
171 u32 key_index,
172 u8 key_len,
173 u8 key_type,
174 u8 *key_bssid,
175 //u8 *key_rsc,
176 u8 *ptx_tsc,
177 u8 *prx_tsc,
178 u8 *key_material);
179void sme_remove_default_key(void *pcore_data, int index);
180void sme_remove_mapping_key(void *pcore_data, u8 *pmac_addr);
181void sme_clear_all_mapping_key(void *pcore_data);
182void sme_clear_all_default_key(void *pcore_data);
183
184
185
186s8 sme_set_preamble_mode(void *pcore_data, u8 mode);
187s8 sme_get_preamble_mode(void *pcore_data, u8 *mode);
188s8 sme_get_preamble_type(void *pcore_data, u8 *type);
189s8 sme_set_slottime_mode(void *pcore_data, u8 mode);
190s8 sme_get_slottime_mode(void *pcore_data, u8 *mode);
191s8 sme_get_slottime_type(void *pcore_data, u8 *type);
192s8 sme_set_txrate_policy(void *pcore_data, u8 policy);
193s8 sme_get_txrate_policy(void *pcore_data, u8 *policy);
194s8 sme_get_cwmin_value(void *pcore_data, u8 *cwmin);
195s8 sme_get_cwmax_value(void *pcore_data, u16 *cwmax);
196s8 sme_get_ms_radio_mode(void *pcore_data, u8 * pMsRadioOff);
197s8 sme_set_ms_radio_mode(void *pcore_data, u8 boMsRadioOff);
198s8 sme_get_radio_mode(void *pcore_data, psRadioOff pRadioOffData);
199s8 sme_set_radio_mode(void *pcore_data, RadioOff RadioOffData);
200
201void sme_get_tx_power_level(void *pcore_data, u32 *TxPower);
202u8 sme_set_tx_power_level(void *pcore_data, u32 TxPower);
203void sme_get_antenna_count(void *pcore_data, u32 *AntennaCount);
204void sme_get_rx_antenna(void *pcore_data, u32 *RxAntenna);
205u8 sme_set_rx_antenna(void *pcore_data, u32 RxAntenna);
206void sme_get_tx_antenna(void *pcore_data, u32 *TxAntenna);
207s8 sme_set_tx_antenna(void *pcore_data, u32 TxAntenna);
208s8 sme_set_IBSS_chan(void *pcore_data, ChanInfo chan);
209
210//20061108 WPS
211s8 sme_set_IE_append(void *pcore_data, PUCHAR buffer, u16 buf_len);
212
213
214
215
216//================== Local functions ======================
217//#ifdef _HSINCHU
218//void drv_translate_rssi(); // HW RSSI bit -> NDIS RSSI representation
219//void drv_translate_bss_description(); // Local bss desc -> NDIS bss desc
220//void drv_translate_channel(u8 NetworkType, u8 ChannelNumber, u32 *freq); // channel number -> channel /freq.
221//#endif _HSINCHU
222//
223static const u32 PowerDbToMw[] =
224{
225 56, //mW, MAX - 0, 17.5 dbm
226 40, //mW, MAX - 1, 16.0 dbm
227 30, //mW, MAX - 2, 14.8 dbm
228 20, //mW, MAX - 3, 13.0 dbm
229 15, //mW, MAX - 4, 11.8 dbm
230 12, //mW, MAX - 5, 10.6 dbm
231 9, //mW, MAX - 6, 9.4 dbm
232 7, //mW, MAX - 7, 8.3 dbm
233 5, //mW, MAX - 8, 6.4 dbm
234 4, //mW, MAX - 9, 5.3 dbm
235 3, //mW, MAX - 10, 4.0 dbm
236 2, //mW, MAX - 11, ? dbm
237 2, //mW, MAX - 12, ? dbm
238 2, //mW, MAX - 13, ? dbm
239 2, //mW, MAX - 14, ? dbm
240 2, //mW, MAX - 15, ? dbm
241 2, //mW, MAX - 16, ? dbm
242 2, //mW, MAX - 17, ? dbm
243 2, //mW, MAX - 18, ? dbm
244 1, //mW, MAX - 19, ? dbm
245 1, //mW, MAX - 20, ? dbm
246 1, //mW, MAX - 21, ? dbm
247 1, //mW, MAX - 22, ? dbm
248 1, //mW, MAX - 23, ? dbm
249 1, //mW, MAX - 24, ? dbm
250 1, //mW, MAX - 25, ? dbm
251 1, //mW, MAX - 26, ? dbm
252 1, //mW, MAX - 27, ? dbm
253 1, //mW, MAX - 28, ? dbm
254 1, //mW, MAX - 29, ? dbm
255 1, //mW, MAX - 30, ? dbm
256 1 //mW, MAX - 31, ? dbm
257};
258
259
260
261
262
263#endif /* __SME_API_H__ */
264
265
diff --git a/drivers/staging/winbond/sme_s.h b/drivers/staging/winbond/sme_s.h
new file mode 100644
index 000000000000..dfd2fbc4edef
--- /dev/null
+++ b/drivers/staging/winbond/sme_s.h
@@ -0,0 +1,228 @@
1//
2// SME_S.H -
3// SME task global CONSTANTS, STRUCTURES, variables
4//
5
6//////////////////////////////////////////////////////////////////////////
7//define the msg type of SME module
8// 0x00~0x1F : MSG from GUI dispatch
9// 0x20~0x3F : MSG from MLME
10// 0x40~0x5F : MSG from SCAN
11// 0x60~0x6F : MSG from TX/RX
12// 0x70~0x7F : MSG from ROAMING
13// 0x80~0x8F : MSG from ISR
14// 0x90 : MSG TimeOut
15
16// from GUI
17#define SMEMSG_SCAN_REQ 0x01
18//#define SMEMSG_PASSIVE_SCAN_REQ 0x02
19#define SMEMSG_JOIN_REQ 0x03
20#define SMEMSG_START_IBSS 0x04
21#define SMEMSG_DISCONNECT_REQ 0x05
22#define SMEMSG_AUTHEN_REQ 0x06
23#define SMEMSG_DEAUTHEN_REQ 0x07
24#define SMEMSG_ASSOC_REQ 0x08
25#define SMEMSG_REASSOC_REQ 0x09
26#define SMEMSG_DISASSOC_REQ 0x0a
27#define SMEMSG_POWERSAVE_REQ 0x0b
28
29
30// from MLME
31#define SMEMSG_AUTHEN_CFM 0x21
32#define SMEMSG_AUTHEN_IND 0x22
33#define SMEMSG_ASSOC_CFM 0x23
34#define SMEMSG_DEAUTHEN_IND 0x24
35#define SMEMSG_DISASSOC_IND 0x25
36// from SCAN
37#define SMEMSG_SCAN_CFM 0x41
38#define SMEMSG_START_IBSS_CFM 0x42
39// from MTO, function call to set SME parameters
40
41// 0x60~0x6F : MSG from TX/RX
42//#define SMEMSG_IBSS_JOIN_UPDATE_BSSID 0x61
43#define SMEMSG_COUNTERMEASURE_MICFAIL_TIMEOUT 0x62
44#define SMEMSG_COUNTERMEASURE_BLOCK_TIMEOUT 0x63
45// from ROAMING
46#define SMEMSG_HANDOVER_JOIN_REQ 0x71
47#define SMEMSG_END_ROAMING 0x72
48#define SMEMSG_SCAN_JOIN_REQ 0x73
49// from ISR
50#define SMEMSG_TSF_SYNC_IND 0x81
51// from TimeOut
52#define SMEMSG_TIMEOUT 0x91
53
54
55
56#define MAX_PMKID_Accunt 16
57//@added by ws 04/22/05
58#define Cipher_Disabled 0
59#define Cipher_Wep 1
60#define Cipher_Tkip 2
61#define Cipher_Ccmp 4
62
63
64///////////////////////////////////////////////////////////////////////////
65//Constants
66
67///////////////////////////////////////////////////////////////////////////
68//Global data structures
69
70#define NUMOFWEPENTRIES 64
71
72typedef enum _WEPKeyMode
73{
74 WEPKEY_DISABLED = 0,
75 WEPKEY_64 = 1,
76 WEPKEY_128 = 2
77
78} WEPKEYMODE, *pWEPKEYMODE;
79
80#ifdef _WPA2_
81
82typedef struct _BSSInfo
83{
84 u8 PreAuthBssID[6];
85 PMKID pmkid_value;
86}BSSID_Info;
87
88typedef struct _PMKID_Table //added by ws 05/05/04
89{
90 u32 Length;
91 u32 BSSIDInfoCount;
92 BSSID_Info BSSIDInfo[16];
93
94} PMKID_Table;
95
96#endif //end def _WPA2_
97
98#define MAX_BASIC_RATE_SET 15
99#define MAX_OPT_RATE_SET MAX_BASIC_RATE_SET
100
101
102typedef struct _SME_PARAMETERS
103{
104 u16 wState;
105 u8 boDUTmode;
106 u8 bDesiredPowerSave;
107
108 // SME timer and timeout value
109 //NDIS_MINIPORT_TIMER nTimer;
110 OS_TIMER nTimer;
111
112 u8 boInTimerHandler;
113 u8 boAuthRetryActive;
114 u8 reserved_0[2];
115
116 u32 AuthenRetryTimerVal; // NOTE: Assoc don't fail timeout
117 u32 JoinFailTimerVal; // 10*Beacon-Interval
118
119 //Rates
120 u8 BSSBasicRateSet[(MAX_BASIC_RATE_SET + 3) & ~0x03 ]; // BSS basic rate set
121 u8 OperationalRateSet[(MAX_OPT_RATE_SET + 3) & ~0x03 ]; // Operational rate set
122
123 u8 NumOfBSSBasicRate;
124 u8 NumOfOperationalRate;
125 u8 reserved_1[2];
126
127 u32 BasicRateBitmap;
128 u32 OpRateBitmap;
129
130 // System parameters Set by GUI
131 //-------------------- start IBSS parameter ---------------------------//
132 u32 boStartIBSS; //Start IBSS toggle
133
134 u16 wBeaconPeriod;
135 u16 wATIM_Window;
136
137 ChanInfo IbssChan; // 2B //channel setting when start IBSS
138 u8 reserved_2[2];
139
140 // Join related
141 u16 wDesiredJoinBSS; // BSS index which desire to join
142 u8 boJoinReq; //Join request toggle
143 u8 bDesiredBSSType; //for Join request
144
145 u16 wCapabilityInfo; // Used when invoking the MLME_Associate_request().
146 u16 wNonERPcapabilityInfo;
147
148 struct SSID_Element sDesiredSSID; // 34 B
149 u8 reserved_3[2];
150
151 u8 abDesiredBSSID[MAC_ADDR_LENGTH + 2];
152
153 u8 bJoinScanCount; // the time of scan-join action need to do
154 u8 bDesiredAuthMode; // AUTH_OPEN_SYSTEM or AUTH_SHARED_KEY
155 u8 reserved_4[2];
156
157 // Encryption parameters
158 u8 _dot11PrivacyInvoked;
159 u8 _dot11PrivacyOptionImplemented;
160 u8 reserved_5[2];
161
162 //@ ws added
163 u8 DesiredEncrypt;
164 u8 encrypt_status; //ENCRYPT_DISABLE, ENCRYPT_WEP, ENCRYPT_WEP_NOKEY, ENCRYPT_TKIP, ...
165 u8 key_length;
166 u8 pairwise_key_ok;
167
168 u8 group_key_ok;
169 u8 wpa_ok; // indicate the control port of 802.1x is open or close
170 u8 pairwise_key_type;
171 u8 group_key_type;
172
173 u32 _dot11WEPDefaultKeyID;
174
175 u8 tx_mic_key[8]; // TODO: 0627 kevin-TKIP
176 u8 rx_mic_key[8]; // TODO: 0627 kevin-TKIP
177 u8 group_tx_mic_key[8];
178 u8 group_rx_mic_key[8];
179
180// #ifdef _WPA_
181 u8 AssocReqVarIE[200];
182 u8 AssocRespVarIE[200];
183
184 u16 AssocReqVarLen;
185 u16 AssocRespVarLen;
186 u8 boReassoc; //use assoc. or reassoc.
187 u8 reserved_6[3];
188 u16 AssocRespCapability;
189 u16 AssocRespStatus;
190// #endif
191
192 #ifdef _WPA2_
193 u8 PmkIdTable[256];
194 u32 PmkidTableIndex;
195 #endif //end def _WPA2_
196
197} SME_PARAMETERS, *PSME_PARAMETERS;
198
199#define psSME (&(Adapter->sSmePara))
200
201#define wSMEGetCurrentSTAState(Adapter) ((u16)(Adapter)->sSmePara.wState)
202
203
204
205//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
206// SmeModule.h
207// Define the related definitions of SME module
208// history -- 01/14/03' created
209//
210//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
211
212//Define the state of SME module
213#define DISABLED 0
214#define INIT_SCAN 1
215#define SCAN_READY 2
216#define START_IBSS 3
217#define JOIN_PENDING 4
218#define JOIN_CFM 5
219#define AUTHENTICATE_PENDING 6
220#define AUTHENTICATED 7
221#define CONNECTED 8
222//#define EAP_STARTING 9
223//#define EAPOL_AUTHEN_PENDING 10
224//#define SECURE_CONNECTED 11
225
226
227// Static function
228
diff --git a/drivers/staging/winbond/wb35_ver.h b/drivers/staging/winbond/wb35_ver.h
new file mode 100644
index 000000000000..2433bc073004
--- /dev/null
+++ b/drivers/staging/winbond/wb35_ver.h
@@ -0,0 +1,30 @@
1//
2// Only define one of follow
3//
4
5#ifdef WB_WIN
6 #define VER_FILEVERSION 1,00,47,00
7 #define VER_FILEVERSION_STR "1.00.47.00"
8 #define WB32_DRIVER_MAJOR_VERSION 0x0100
9 #define WB32_DRIVER_MINOR_VERSION 0x4700
10#endif
11
12#ifdef WB_CE
13 #define VER_FILEVERSION 2,00,47,00
14 #define VER_FILEVERSION_STR "2.00.47.00"
15 #define WB32_DRIVER_MAJOR_VERSION 0x0200
16 #define WB32_DRIVER_MINOR_VERSION 0x4700
17#endif
18
19#ifdef WB_LINUX
20 #define VER_FILEVERSION 3,00,47,00
21 #define VER_FILEVERSION_STR "3.00.47.00"
22 #define WB32_DRIVER_MAJOR_VERSION 0x0300
23 #define WB32_DRIVER_MINOR_VERSION 0x4700
24#endif
25
26
27
28
29
30
diff --git a/drivers/staging/winbond/wbhal.c b/drivers/staging/winbond/wbhal.c
new file mode 100644
index 000000000000..daf442247558
--- /dev/null
+++ b/drivers/staging/winbond/wbhal.c
@@ -0,0 +1,878 @@
1#include "os_common.h"
2
3void hal_get_ethernet_address( phw_data_t pHwData, PUCHAR current_address )
4{
5 if( pHwData->SurpriseRemove ) return;
6
7 memcpy( current_address, pHwData->CurrentMacAddress, ETH_LENGTH_OF_ADDRESS );
8}
9
10void hal_set_ethernet_address( phw_data_t pHwData, PUCHAR current_address )
11{
12 u32 ltmp[2];
13
14 if( pHwData->SurpriseRemove ) return;
15
16 memcpy( pHwData->CurrentMacAddress, current_address, ETH_LENGTH_OF_ADDRESS );
17
18 ltmp[0]= cpu_to_le32( *(PULONG)pHwData->CurrentMacAddress );
19 ltmp[1]= cpu_to_le32( *(PULONG)(pHwData->CurrentMacAddress + 4) ) & 0xffff;
20
21 Wb35Reg_BurstWrite( pHwData, 0x03e8, ltmp, 2, AUTO_INCREMENT );
22}
23
24void hal_get_permanent_address( phw_data_t pHwData, PUCHAR pethernet_address )
25{
26 if( pHwData->SurpriseRemove ) return;
27
28 memcpy( pethernet_address, pHwData->PermanentMacAddress, 6 );
29}
30
31u8 hal_init_hardware(phw_data_t pHwData, PWB32_ADAPTER Adapter)
32{
33 u16 SoftwareSet;
34 pHwData->Adapter = Adapter;
35
36 // Initial the variable
37 pHwData->MaxReceiveLifeTime = DEFAULT_MSDU_LIFE_TIME; // Setting Rx maximum MSDU life time
38 pHwData->FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; // Setting default fragment threshold
39
40 if (WbUsb_initial(pHwData)) {
41 pHwData->InitialResource = 1;
42 if( Wb35Reg_initial(pHwData)) {
43 pHwData->InitialResource = 2;
44 if (Wb35Tx_initial(pHwData)) {
45 pHwData->InitialResource = 3;
46 if (Wb35Rx_initial(pHwData)) {
47 pHwData->InitialResource = 4;
48 OS_TIMER_INITIAL( &pHwData->LEDTimer, hal_led_control, pHwData );
49 OS_TIMER_SET( &pHwData->LEDTimer, 1000 ); // 20060623
50
51 //
52 // For restrict to vendor's hardware
53 //
54 SoftwareSet = hal_software_set( pHwData );
55
56 #ifdef Vendor2
57 // Try to make sure the EEPROM contain
58 SoftwareSet >>= 8;
59 if( SoftwareSet != 0x82 )
60 return FALSE;
61 #endif
62
63 Wb35Rx_start( pHwData );
64 Wb35Tx_EP2VM_start( pHwData );
65
66 return TRUE;
67 }
68 }
69 }
70 }
71
72 pHwData->SurpriseRemove = 1;
73 return FALSE;
74}
75
76
77void hal_halt(phw_data_t pHwData, void *ppa_data)
78{
79 switch( pHwData->InitialResource )
80 {
81 case 4:
82 case 3: OS_TIMER_CANCEL( &pHwData->LEDTimer, &cancel );
83 OS_SLEEP(100000); // Wait for Timer DPC exit 940623.2
84 Wb35Rx_destroy( pHwData ); // Release the Rx
85 case 2: Wb35Tx_destroy( pHwData ); // Release the Tx
86 case 1: Wb35Reg_destroy( pHwData ); // Release the Wb35 Regisster resources
87 WbUsb_destroy( pHwData );// Release the WbUsb
88 }
89}
90
91//---------------------------------------------------------------------------------------------------
92void hal_set_rates(phw_data_t pHwData, PUCHAR pbss_rates,
93 u8 length, unsigned char basic_rate_set)
94{
95 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
96 u32 tmp, tmp1;
97 u8 Rate[12]={ 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 };
98 u8 SupportedRate[16];
99 u8 i, j, k, Count1, Count2, Byte;
100
101 if( pHwData->SurpriseRemove ) return;
102
103 if (basic_rate_set) {
104 pWb35Reg->M28_MacControl &= ~0x000fff00;
105 tmp1 = 0x00000100;
106 } else {
107 pWb35Reg->M28_MacControl &= ~0xfff00000;
108 tmp1 = 0x00100000;
109 }
110
111 tmp = 0;
112 for (i=0; i<length; i++) {
113 Byte = pbss_rates[i] & 0x7f;
114 for (j=0; j<12; j++) {
115 if( Byte == Rate[j] )
116 break;
117 }
118
119 if (j < 12)
120 tmp |= (tmp1<<j);
121 }
122
123 pWb35Reg->M28_MacControl |= tmp;
124 Wb35Reg_Write( pHwData, 0x0828, pWb35Reg->M28_MacControl );
125
126 // 930206.2.c M78 setting
127 j = k = Count1 = Count2 = 0;
128 memset( SupportedRate, 0, 16 );
129 tmp = 0x00100000;
130 tmp1 = 0x00000100;
131 for (i=0; i<12; i++) { // Get the supported rate
132 if (tmp & pWb35Reg->M28_MacControl) {
133 SupportedRate[j] = Rate[i];
134
135 if (tmp1 & pWb35Reg->M28_MacControl)
136 SupportedRate[j] |= 0x80;
137
138 if (k)
139 Count2++;
140 else
141 Count1++;
142
143 j++;
144 }
145
146 if (i==4 && k==0) {
147 if( !(pWb35Reg->M28_MacControl & 0x000ff000) ) // if basic rate in 11g domain)
148 {
149 k = 1;
150 j = 8;
151 }
152 }
153
154 tmp <<= 1;
155 tmp1 <<= 1;
156 }
157
158 // Fill data into support rate until buffer full
159 //---20060926 add by anson's endian
160 for (i=0; i<4; i++)
161 *(PULONG)(SupportedRate+(i<<2)) = cpu_to_le32( *(PULONG)(SupportedRate+(i<<2)) );
162 //--- end 20060926 add by anson's endian
163 Wb35Reg_BurstWrite( pHwData,0x087c, (PULONG)SupportedRate, 4, AUTO_INCREMENT );
164 pWb35Reg->M7C_MacControl = ((PULONG)SupportedRate)[0];
165 pWb35Reg->M80_MacControl = ((PULONG)SupportedRate)[1];
166 pWb35Reg->M84_MacControl = ((PULONG)SupportedRate)[2];
167 pWb35Reg->M88_MacControl = ((PULONG)SupportedRate)[3];
168
169 // Fill length
170 tmp = Count1<<28 | Count2<<24;
171 pWb35Reg->M78_ERPInformation &= ~0xff000000;
172 pWb35Reg->M78_ERPInformation |= tmp;
173 Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation );
174}
175
176
177//---------------------------------------------------------------------------------------------------
178void hal_set_beacon_period( phw_data_t pHwData, u16 beacon_period )
179{
180 u32 tmp;
181
182 if( pHwData->SurpriseRemove ) return;
183
184 pHwData->BeaconPeriod = beacon_period;
185 tmp = pHwData->BeaconPeriod << 16;
186 tmp |= pHwData->ProbeDelay;
187 Wb35Reg_Write( pHwData, 0x0848, tmp );
188}
189
190
191void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel )
192{
193 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
194
195 if( pHwData->SurpriseRemove )
196 return;
197
198 printk("Going to channel: %d/%d\n", channel.band, channel.ChanNo);
199
200 RFSynthesizer_SwitchingChannel( pHwData, channel );// Switch channel
201 pHwData->Channel = channel.ChanNo;
202 pHwData->band = channel.band;
203 #ifdef _PE_STATE_DUMP_
204 WBDEBUG(("Set channel is %d, band =%d\n", pHwData->Channel, pHwData->band));
205 #endif
206 pWb35Reg->M28_MacControl &= ~0xff; // Clean channel information field
207 pWb35Reg->M28_MacControl |= channel.ChanNo;
208 Wb35Reg_WriteWithCallbackValue( pHwData, 0x0828, pWb35Reg->M28_MacControl,
209 (PCHAR)&channel, sizeof(ChanInfo));
210}
211//---------------------------------------------------------------------------------------------------
212void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel )
213{
214 hal_set_current_channel_ex( pHwData, channel );
215}
216//---------------------------------------------------------------------------------------------------
217void hal_get_current_channel( phw_data_t pHwData, ChanInfo *channel )
218{
219 channel->ChanNo = pHwData->Channel;
220 channel->band = pHwData->band;
221}
222//---------------------------------------------------------------------------------------------------
223void hal_set_accept_broadcast( phw_data_t pHwData, u8 enable )
224{
225 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
226
227 if( pHwData->SurpriseRemove ) return;
228
229 pWb35Reg->M00_MacControl &= ~0x02000000;//The HW value
230
231 if (enable)
232 pWb35Reg->M00_MacControl |= 0x02000000;//The HW value
233
234 Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
235}
236
237//for wep key error detection, we need to accept broadcast packets to be received temporary.
238void hal_set_accept_promiscuous( phw_data_t pHwData, u8 enable)
239{
240 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
241
242 if (pHwData->SurpriseRemove) return;
243 if (enable) {
244 pWb35Reg->M00_MacControl |= 0x00400000;
245 Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
246 } else {
247 pWb35Reg->M00_MacControl&=~0x00400000;
248 Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
249 }
250}
251
252void hal_set_accept_multicast( phw_data_t pHwData, u8 enable )
253{
254 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
255
256 if( pHwData->SurpriseRemove ) return;
257
258 pWb35Reg->M00_MacControl &= ~0x01000000;//The HW value
259 if (enable) pWb35Reg->M00_MacControl |= 0x01000000;//The HW value
260 Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
261}
262
263void hal_set_accept_beacon( phw_data_t pHwData, u8 enable )
264{
265 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
266
267 if( pHwData->SurpriseRemove ) return;
268
269 // 20040108 debug
270 if( !enable )//Due to SME and MLME are not suitable for 35
271 return;
272
273 pWb35Reg->M00_MacControl &= ~0x04000000;//The HW value
274 if( enable )
275 pWb35Reg->M00_MacControl |= 0x04000000;//The HW value
276
277 Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
278}
279//---------------------------------------------------------------------------------------------------
280void hal_set_multicast_address( phw_data_t pHwData, PUCHAR address, u8 number )
281{
282 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
283 u8 Byte, Bit;
284
285 if( pHwData->SurpriseRemove ) return;
286
287 //Erases and refills the card multicast registers. Used when an address
288 // has been deleted and all bits must be recomputed.
289 pWb35Reg->M04_MulticastAddress1 = 0;
290 pWb35Reg->M08_MulticastAddress2 = 0;
291
292 while( number )
293 {
294 number--;
295 CardGetMulticastBit( (address+(number*ETH_LENGTH_OF_ADDRESS)), &Byte, &Bit);
296 pWb35Reg->Multicast[Byte] |= Bit;
297 }
298
299 // Updating register
300 Wb35Reg_BurstWrite( pHwData, 0x0804, (PULONG)pWb35Reg->Multicast, 2, AUTO_INCREMENT );
301}
302//---------------------------------------------------------------------------------------------------
303u8 hal_get_accept_beacon( phw_data_t pHwData )
304{
305 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
306
307 if( pHwData->SurpriseRemove ) return 0;
308
309 if( pWb35Reg->M00_MacControl & 0x04000000 )
310 return 1;
311 else
312 return 0;
313}
314
315unsigned char hal_reset_hardware( phw_data_t pHwData, void* ppa )
316{
317 // Not implement yet
318 return TRUE;
319}
320
321void hal_stop( phw_data_t pHwData )
322{
323 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
324
325 pHwData->Wb35Rx.rx_halt = 1;
326 Wb35Rx_stop( pHwData );
327
328 pHwData->Wb35Tx.tx_halt = 1;
329 Wb35Tx_stop( pHwData );
330
331 pWb35Reg->D00_DmaControl &= ~0xc0000000;//Tx Off, Rx Off
332 Wb35Reg_Write( pHwData, 0x0400, pWb35Reg->D00_DmaControl );
333
334 WbUsb_Stop( pHwData ); // 20051230 Add.4
335}
336
337unsigned char hal_idle(phw_data_t pHwData)
338{
339 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
340 PWBUSB pWbUsb = &pHwData->WbUsb;
341
342 if( !pHwData->SurpriseRemove && ( pWbUsb->DetectCount || pWb35Reg->EP0vm_state!=VM_STOP ) )
343 return FALSE;
344
345 return TRUE;
346}
347//---------------------------------------------------------------------------------------------------
348void hal_set_cwmin( phw_data_t pHwData, u8 cwin_min )
349{
350 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
351
352 if( pHwData->SurpriseRemove ) return;
353
354 pHwData->cwmin = cwin_min;
355 pWb35Reg->M2C_MacControl &= ~0x7c00; //bit 10 ~ 14
356 pWb35Reg->M2C_MacControl |= (pHwData->cwmin<<10);
357 Wb35Reg_Write( pHwData, 0x082c, pWb35Reg->M2C_MacControl );
358}
359
360s32 hal_get_rssi( phw_data_t pHwData, u32 *HalRssiArry, u8 Count )
361{
362 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
363 R01_DESCRIPTOR r01;
364 s32 ltmp = 0, tmp;
365 u8 i;
366
367 if( pHwData->SurpriseRemove ) return -200;
368 if( Count > MAX_ACC_RSSI_COUNT ) // Because the TS may use this funtion
369 Count = MAX_ACC_RSSI_COUNT;
370
371 // RSSI = C1 + C2 * (agc_state[7:0] + offset_map(lna_state[1:0]))
372 // C1 = -195, C2 = 0.66 = 85/128
373 for (i=0; i<Count; i++)
374 {
375 r01.value = HalRssiArry[i];
376 tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
377 ltmp += tmp;
378 }
379 ltmp /= Count;
380 if( pHwData->phy_type == RF_AIROHA_2230 ) ltmp -= 5; // 10;
381 if( pHwData->phy_type == RF_AIROHA_2230S ) ltmp -= 5; // 10; 20060420 Add this
382
383 //if( ltmp < -200 ) ltmp = -200;
384 if( ltmp < -110 ) ltmp = -110;// 1.0.24.0 For NJRC
385
386 return ltmp;
387}
388//----------------------------------------------------------------------------------------------------
389s32 hal_get_rssi_bss( phw_data_t pHwData, u16 idx, u8 Count )
390{
391 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
392 R01_DESCRIPTOR r01;
393 s32 ltmp = 0, tmp;
394 u8 i, j;
395 PADAPTER Adapter = pHwData->Adapter;
396// u32 *HalRssiArry = psBSS(idx)->HalRssi;
397
398 if( pHwData->SurpriseRemove ) return -200;
399 if( Count > MAX_ACC_RSSI_COUNT ) // Because the TS may use this funtion
400 Count = MAX_ACC_RSSI_COUNT;
401
402 // RSSI = C1 + C2 * (agc_state[7:0] + offset_map(lna_state[1:0]))
403 // C1 = -195, C2 = 0.66 = 85/128
404#if 0
405 for (i=0; i<Count; i++)
406 {
407 r01.value = HalRssiArry[i];
408 tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
409 ltmp += tmp;
410 }
411#else
412 if (psBSS(idx)->HalRssiIndex == 0)
413 psBSS(idx)->HalRssiIndex = MAX_ACC_RSSI_COUNT;
414 j = (u8)psBSS(idx)->HalRssiIndex-1;
415
416 for (i=0; i<Count; i++)
417 {
418 r01.value = psBSS(idx)->HalRssi[j];
419 tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
420 ltmp += tmp;
421 if (j == 0)
422 {
423 j = MAX_ACC_RSSI_COUNT;
424 }
425 j--;
426 }
427#endif
428 ltmp /= Count;
429 if( pHwData->phy_type == RF_AIROHA_2230 ) ltmp -= 5; // 10;
430 if( pHwData->phy_type == RF_AIROHA_2230S ) ltmp -= 5; // 10; 20060420 Add this
431
432 //if( ltmp < -200 ) ltmp = -200;
433 if( ltmp < -110 ) ltmp = -110;// 1.0.24.0 For NJRC
434
435 return ltmp;
436}
437
438//---------------------------------------------------------------------------
439void hal_led_control_1a( phw_data_t pHwData )
440{
441 hal_led_control( NULL, pHwData, NULL, NULL );
442}
443
444void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
445{
446 PADAPTER Adapter = pHwData->Adapter;
447 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
448 u32 LEDSet = (pHwData->SoftwareSet & HAL_LED_SET_MASK) >> HAL_LED_SET_SHIFT;
449 u8 LEDgray[20] = { 0,3,4,6,8,10,11,12,13,14,15,14,13,12,11,10,8,6,4,2 };
450 u8 LEDgray2[30] = { 7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,15,14,13,12,11,10,9,8 };
451 u32 TimeInterval = 500, ltmp, ltmp2;
452 ltmp=0;
453
454 if( pHwData->SurpriseRemove ) return;
455
456 if( pHwData->LED_control ) {
457 ltmp2 = pHwData->LED_control & 0xff;
458 if( ltmp2 == 5 ) // 5 is WPS mode
459 {
460 TimeInterval = 100;
461 ltmp2 = (pHwData->LED_control>>8) & 0xff;
462 switch( ltmp2 )
463 {
464 case 1: // [0.2 On][0.1 Off]...
465 pHwData->LED_Blinking %= 3;
466 ltmp = 0x1010; // Led 1 & 0 Green and Red
467 if( pHwData->LED_Blinking == 2 ) // Turn off
468 ltmp = 0;
469 break;
470 case 2: // [0.1 On][0.1 Off]...
471 pHwData->LED_Blinking %= 2;
472 ltmp = 0x0010; // Led 0 red color
473 if( pHwData->LED_Blinking ) // Turn off
474 ltmp = 0;
475 break;
476 case 3: // [0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.5 Off]...
477 pHwData->LED_Blinking %= 15;
478 ltmp = 0x0010; // Led 0 red color
479 if( (pHwData->LED_Blinking >= 9) || (pHwData->LED_Blinking%2) ) // Turn off 0.6 sec
480 ltmp = 0;
481 break;
482 case 4: // [300 On][ off ]
483 ltmp = 0x1000; // Led 1 Green color
484 if( pHwData->LED_Blinking >= 3000 )
485 ltmp = 0; // led maybe on after 300sec * 32bit counter overlap.
486 break;
487 }
488 pHwData->LED_Blinking++;
489
490 pWb35Reg->U1BC_LEDConfigure = ltmp;
491 if( LEDSet != 7 ) // Only 111 mode has 2 LEDs on PCB.
492 {
493 pWb35Reg->U1BC_LEDConfigure |= (ltmp &0xff)<<8; // Copy LED result to each LED control register
494 pWb35Reg->U1BC_LEDConfigure |= (ltmp &0xff00)>>8;
495 }
496 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
497 }
498 }
499 else if( pHwData->CurrentRadioSw || pHwData->CurrentRadioHw ) // If radio off
500 {
501 if( pWb35Reg->U1BC_LEDConfigure & 0x1010 )
502 {
503 pWb35Reg->U1BC_LEDConfigure &= ~0x1010;
504 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
505 }
506 }
507 else
508 {
509 switch( LEDSet )
510 {
511 case 4: // [100] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing
512 if( !pHwData->LED_LinkOn ) // Blink only if not Link On
513 {
514 // Blinking if scanning is on progress
515 if( pHwData->LED_Scanning )
516 {
517 if( pHwData->LED_Blinking == 0 )
518 {
519 pWb35Reg->U1BC_LEDConfigure |= 0x10;
520 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 On
521 pHwData->LED_Blinking = 1;
522 TimeInterval = 300;
523 }
524 else
525 {
526 pWb35Reg->U1BC_LEDConfigure &= ~0x10;
527 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
528 pHwData->LED_Blinking = 0;
529 TimeInterval = 300;
530 }
531 }
532 else
533 {
534 //Turn Off LED_0
535 if( pWb35Reg->U1BC_LEDConfigure & 0x10 )
536 {
537 pWb35Reg->U1BC_LEDConfigure &= ~0x10;
538 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
539 }
540 }
541 }
542 else
543 {
544 // Turn On LED_0
545 if( (pWb35Reg->U1BC_LEDConfigure & 0x10) == 0 )
546 {
547 pWb35Reg->U1BC_LEDConfigure |= 0x10;
548 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
549 }
550 }
551 break;
552
553 case 6: // [110] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing
554 if( !pHwData->LED_LinkOn ) // Blink only if not Link On
555 {
556 // Blinking if scanning is on progress
557 if( pHwData->LED_Scanning )
558 {
559 if( pHwData->LED_Blinking == 0 )
560 {
561 pWb35Reg->U1BC_LEDConfigure &= ~0xf;
562 pWb35Reg->U1BC_LEDConfigure |= 0x10;
563 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 On
564 pHwData->LED_Blinking = 1;
565 TimeInterval = 300;
566 }
567 else
568 {
569 pWb35Reg->U1BC_LEDConfigure &= ~0x1f;
570 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
571 pHwData->LED_Blinking = 0;
572 TimeInterval = 300;
573 }
574 }
575 else
576 {
577 // 20060901 Gray blinking if in disconnect state and not scanning
578 ltmp = pWb35Reg->U1BC_LEDConfigure;
579 pWb35Reg->U1BC_LEDConfigure &= ~0x1f;
580 if( LEDgray2[(pHwData->LED_Blinking%30)] )
581 {
582 pWb35Reg->U1BC_LEDConfigure |= 0x10;
583 pWb35Reg->U1BC_LEDConfigure |= LEDgray2[ (pHwData->LED_Blinking%30) ];
584 }
585 pHwData->LED_Blinking++;
586 if( pWb35Reg->U1BC_LEDConfigure != ltmp )
587 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
588 TimeInterval = 100;
589 }
590 }
591 else
592 {
593 // Turn On LED_0
594 if( (pWb35Reg->U1BC_LEDConfigure & 0x10) == 0 )
595 {
596 pWb35Reg->U1BC_LEDConfigure |= 0x10;
597 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
598 }
599 }
600 break;
601
602 case 5: // [101] Only 1 Led be placed on PCB and use LED_1 for showing
603 if( !pHwData->LED_LinkOn ) // Blink only if not Link On
604 {
605 // Blinking if scanning is on progress
606 if( pHwData->LED_Scanning )
607 {
608 if( pHwData->LED_Blinking == 0 )
609 {
610 pWb35Reg->U1BC_LEDConfigure |= 0x1000;
611 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
612 pHwData->LED_Blinking = 1;
613 TimeInterval = 300;
614 }
615 else
616 {
617 pWb35Reg->U1BC_LEDConfigure &= ~0x1000;
618 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 Off
619 pHwData->LED_Blinking = 0;
620 TimeInterval = 300;
621 }
622 }
623 else
624 {
625 //Turn Off LED_1
626 if( pWb35Reg->U1BC_LEDConfigure & 0x1000 )
627 {
628 pWb35Reg->U1BC_LEDConfigure &= ~0x1000;
629 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 Off
630 }
631 }
632 }
633 else
634 {
635 // Is transmitting/receiving ??
636 if( (OS_CURRENT_RX_BYTE( Adapter ) != pHwData->RxByteCountLast ) ||
637 (OS_CURRENT_TX_BYTE( Adapter ) != pHwData->TxByteCountLast ) )
638 {
639 if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
640 {
641 pWb35Reg->U1BC_LEDConfigure |= 0x3000;
642 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
643 }
644
645 // Update variable
646 pHwData->RxByteCountLast = OS_CURRENT_RX_BYTE( Adapter );
647 pHwData->TxByteCountLast = OS_CURRENT_TX_BYTE( Adapter );
648 TimeInterval = 200;
649 }
650 else
651 {
652 // Turn On LED_1 and blinking if transmitting/receiving
653 if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x1000 )
654 {
655 pWb35Reg->U1BC_LEDConfigure &= ~0x3000;
656 pWb35Reg->U1BC_LEDConfigure |= 0x1000;
657 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
658 }
659 }
660 }
661 break;
662
663 default: // Default setting. 2 LED be placed on PCB. LED_0: Link On LED_1 Active
664 if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
665 {
666 pWb35Reg->U1BC_LEDConfigure |= 0x3000;// LED_1 is always on and event enable
667 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
668 }
669
670 if( pHwData->LED_Blinking )
671 {
672 // Gray blinking
673 pWb35Reg->U1BC_LEDConfigure &= ~0x0f;
674 pWb35Reg->U1BC_LEDConfigure |= 0x10;
675 pWb35Reg->U1BC_LEDConfigure |= LEDgray[ (pHwData->LED_Blinking-1)%20 ];
676 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
677
678 pHwData->LED_Blinking += 2;
679 if( pHwData->LED_Blinking < 40 )
680 TimeInterval = 100;
681 else
682 {
683 pHwData->LED_Blinking = 0; // Stop blinking
684 pWb35Reg->U1BC_LEDConfigure &= ~0x0f;
685 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
686 }
687 break;
688 }
689
690 if( pHwData->LED_LinkOn )
691 {
692 if( !(pWb35Reg->U1BC_LEDConfigure & 0x10) ) // Check the LED_0
693 {
694 //Try to turn ON LED_0 after gray blinking
695 pWb35Reg->U1BC_LEDConfigure |= 0x10;
696 pHwData->LED_Blinking = 1; //Start blinking
697 TimeInterval = 50;
698 }
699 }
700 else
701 {
702 if( pWb35Reg->U1BC_LEDConfigure & 0x10 ) // Check the LED_0
703 {
704 pWb35Reg->U1BC_LEDConfigure &= ~0x10;
705 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
706 }
707 }
708 break;
709 }
710
711 //20060828.1 Active send null packet to avoid AP disconnect
712 if( pHwData->LED_LinkOn )
713 {
714 pHwData->NullPacketCount += TimeInterval;
715 if( pHwData->NullPacketCount >= DEFAULT_NULL_PACKET_COUNT )
716 {
717 pHwData->NullPacketCount = 0;
718 }
719 }
720 }
721
722 pHwData->time_count += TimeInterval;
723 Wb35Tx_CurrentTime( pHwData, pHwData->time_count ); // 20060928 add
724 OS_TIMER_SET( &pHwData->LEDTimer, TimeInterval ); // 20060623.1
725}
726
727
728void hal_set_phy_type( phw_data_t pHwData, u8 PhyType )
729{
730 pHwData->phy_type = PhyType;
731}
732
733void hal_get_phy_type( phw_data_t pHwData, u8 *PhyType )
734{
735 *PhyType = pHwData->phy_type;
736}
737
738void hal_reset_counter( phw_data_t pHwData )
739{
740 pHwData->dto_tx_retry_count = 0;
741 pHwData->dto_tx_frag_count = 0;
742 memset( pHwData->tx_retry_count, 0, 8);
743}
744
745void hal_set_radio_mode( phw_data_t pHwData, unsigned char radio_off)
746{
747 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
748
749 if( pHwData->SurpriseRemove ) return;
750
751 if (radio_off) //disable Baseband receive off
752 {
753 pHwData->CurrentRadioSw = 1; // off
754 pWb35Reg->M24_MacControl &= 0xffffffbf;
755 }
756 else
757 {
758 pHwData->CurrentRadioSw = 0; // on
759 pWb35Reg->M24_MacControl |= 0x00000040;
760 }
761 Wb35Reg_Write( pHwData, 0x0824, pWb35Reg->M24_MacControl );
762}
763
764u8 hal_get_antenna_number( phw_data_t pHwData )
765{
766 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
767
768 if ((pWb35Reg->BB2C & BIT(11)) == 0)
769 return 0;
770 else
771 return 1;
772}
773
774void hal_set_antenna_number( phw_data_t pHwData, u8 number )
775{
776
777 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
778
779 if (number == 1) {
780 pWb35Reg->BB2C |= BIT(11);
781 } else {
782 pWb35Reg->BB2C &= ~BIT(11);
783 }
784 Wb35Reg_Write( pHwData, 0x102c, pWb35Reg->BB2C );
785#ifdef _PE_STATE_DUMP_
786 WBDEBUG(("Current antenna number : %d\n", number));
787#endif
788}
789
790//----------------------------------------------------------------------------------------------------
791//0 : radio on; 1: radio off
792u8 hal_get_hw_radio_off( phw_data_t pHwData )
793{
794 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
795
796 if( pHwData->SurpriseRemove ) return 1;
797
798 //read the bit16 of register U1B0
799 Wb35Reg_Read( pHwData, 0x3b0, &pWb35Reg->U1B0 );
800 if ((pWb35Reg->U1B0 & 0x00010000)) {
801 pHwData->CurrentRadioHw = 1;
802 return 1;
803 } else {
804 pHwData->CurrentRadioHw = 0;
805 return 0;
806 }
807}
808
809unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, PULONG pValue )
810{
811 if( number < 0x1000 )
812 number += 0x1000;
813 return Wb35Reg_ReadSync( pHwData, number, pValue );
814}
815
816unsigned char hal_set_dxx_reg( phw_data_t pHwData, u16 number, u32 value )
817{
818 unsigned char ret;
819
820 if( number < 0x1000 )
821 number += 0x1000;
822 ret = Wb35Reg_WriteSync( pHwData, number, value );
823 return ret;
824}
825
826void hal_scan_status_indicate(phw_data_t pHwData, unsigned char IsOnProgress)
827{
828 if( pHwData->SurpriseRemove ) return;
829 pHwData->LED_Scanning = IsOnProgress ? 1 : 0;
830}
831
832void hal_system_power_change(phw_data_t pHwData, u32 PowerState)
833{
834 if( PowerState != 0 )
835 {
836 pHwData->SurpriseRemove = 1;
837 if( pHwData->WbUsb.IsUsb20 )
838 hal_stop( pHwData );
839 }
840 else
841 {
842 if( !pHwData->WbUsb.IsUsb20 )
843 hal_stop( pHwData );
844 }
845}
846
847void hal_surprise_remove( phw_data_t pHwData )
848{
849 PADAPTER Adapter = pHwData->Adapter;
850 if (OS_ATOMIC_INC( Adapter, &pHwData->SurpriseRemoveCount ) == 1) {
851 #ifdef _PE_STATE_DUMP_
852 WBDEBUG(("Calling hal_surprise_remove\n"));
853 #endif
854 OS_STOP( Adapter );
855 }
856}
857
858void hal_rate_change( phw_data_t pHwData ) // Notify the HAL rate is changing 20060613.1
859{
860 PADAPTER Adapter = pHwData->Adapter;
861 u8 rate = CURRENT_TX_RATE;
862
863 BBProcessor_RateChanging( pHwData, rate );
864}
865
866void hal_set_rf_power(phw_data_t pHwData, u8 PowerIndex)
867{
868 RFSynthesizer_SetPowerIndex( pHwData, PowerIndex );
869}
870
871unsigned char hal_set_LED(phw_data_t pHwData, u32 Mode) // 20061108 for WPS led control
872{
873 pHwData->LED_Blinking = 0;
874 pHwData->LED_control = Mode;
875 OS_TIMER_SET( &pHwData->LEDTimer, 10 ); // 20060623
876 return TRUE;
877}
878
diff --git a/drivers/staging/winbond/wbhal_f.h b/drivers/staging/winbond/wbhal_f.h
new file mode 100644
index 000000000000..fe25f97af724
--- /dev/null
+++ b/drivers/staging/winbond/wbhal_f.h
@@ -0,0 +1,122 @@
1//=====================================================================
2// Device related include
3//=====================================================================
4#ifdef WB_LINUX
5 #include "linux/wbusb_f.h"
6 #include "linux/wb35reg_f.h"
7 #include "linux/wb35tx_f.h"
8 #include "linux/wb35rx_f.h"
9#else
10 #include "wbusb_f.h"
11 #include "wb35reg_f.h"
12 #include "wb35tx_f.h"
13 #include "wb35rx_f.h"
14#endif
15
16//====================================================================================
17// Function declaration
18//====================================================================================
19void hal_remove_mapping_key( phw_data_t pHwData, PUCHAR pmac_addr );
20void hal_remove_default_key( phw_data_t pHwData, u32 index );
21unsigned char hal_set_mapping_key( phw_data_t Adapter, PUCHAR pmac_addr, u8 null_key, u8 wep_on, PUCHAR ptx_tsc, PUCHAR prx_tsc, u8 key_type, u8 key_len, PUCHAR pkey_data );
22unsigned char hal_set_default_key( phw_data_t Adapter, u8 index, u8 null_key, u8 wep_on, PUCHAR ptx_tsc, PUCHAR prx_tsc, u8 key_type, u8 key_len, PUCHAR pkey_data );
23void hal_clear_all_default_key( phw_data_t pHwData );
24void hal_clear_all_group_key( phw_data_t pHwData );
25void hal_clear_all_mapping_key( phw_data_t pHwData );
26void hal_clear_all_key( phw_data_t pHwData );
27void hal_get_ethernet_address( phw_data_t pHwData, PUCHAR current_address );
28void hal_set_ethernet_address( phw_data_t pHwData, PUCHAR current_address );
29void hal_get_permanent_address( phw_data_t pHwData, PUCHAR pethernet_address );
30unsigned char hal_init_hardware( phw_data_t pHwData, PADAPTER Adapter );
31void hal_set_power_save_mode( phw_data_t pHwData, unsigned char power_save, unsigned char wakeup, unsigned char dtim );
32void hal_get_power_save_mode( phw_data_t pHwData, PBOOLEAN pin_pwr_save );
33void hal_set_slot_time( phw_data_t pHwData, u8 type );
34#define hal_set_atim_window( _A, _ATM )
35void hal_set_rates( phw_data_t pHwData, PUCHAR pbss_rates, u8 length, unsigned char basic_rate_set );
36#define hal_set_basic_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, TRUE )
37#define hal_set_op_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, FALSE )
38void hal_start_bss( phw_data_t pHwData, u8 mac_op_mode );
39void hal_join_request( phw_data_t pHwData, u8 bss_type ); // 0:BSS STA 1:IBSS STA//
40void hal_stop_sync_bss( phw_data_t pHwData );
41void hal_resume_sync_bss( phw_data_t pHwData);
42void hal_set_aid( phw_data_t pHwData, u16 aid );
43void hal_set_bssid( phw_data_t pHwData, PUCHAR pbssid );
44void hal_get_bssid( phw_data_t pHwData, PUCHAR pbssid );
45void hal_set_beacon_period( phw_data_t pHwData, u16 beacon_period );
46void hal_set_listen_interval( phw_data_t pHwData, u16 listen_interval );
47void hal_set_cap_info( phw_data_t pHwData, u16 capability_info );
48void hal_set_ssid( phw_data_t pHwData, PUCHAR pssid, u8 ssid_len );
49void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel );
50void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel );
51void hal_get_current_channel( phw_data_t pHwData, ChanInfo *channel );
52void hal_set_accept_broadcast( phw_data_t pHwData, u8 enable );
53void hal_set_accept_multicast( phw_data_t pHwData, u8 enable );
54void hal_set_accept_beacon( phw_data_t pHwData, u8 enable );
55void hal_set_multicast_address( phw_data_t pHwData, PUCHAR address, u8 number );
56u8 hal_get_accept_beacon( phw_data_t pHwData );
57void hal_stop( phw_data_t pHwData );
58void hal_halt( phw_data_t pHwData, void *ppa_data );
59void hal_start_tx0( phw_data_t pHwData );
60void hal_set_phy_type( phw_data_t pHwData, u8 PhyType );
61void hal_get_phy_type( phw_data_t pHwData, u8 *PhyType );
62unsigned char hal_reset_hardware( phw_data_t pHwData, void* ppa );
63void hal_set_cwmin( phw_data_t pHwData, u8 cwin_min );
64#define hal_get_cwmin( _A ) ( (_A)->cwmin )
65void hal_set_cwmax( phw_data_t pHwData, u16 cwin_max );
66#define hal_get_cwmax( _A ) ( (_A)->cwmax )
67void hal_set_rsn_wpa( phw_data_t pHwData, u32 * RSN_IE_Bitmap , u32 * RSN_OUI_type , unsigned char bDesiredAuthMode);
68//s32 hal_get_rssi( phw_data_t pHwData, u32 HalRssi );
69s32 hal_get_rssi( phw_data_t pHwData, u32 *HalRssiArry, u8 Count );
70s32 hal_get_rssi_bss( phw_data_t pHwData, u16 idx, u8 Count );
71void hal_set_connect_info( phw_data_t pHwData, unsigned char boConnect );
72u8 hal_get_est_sq3( phw_data_t pHwData, u8 Count );
73void hal_led_control_1a( phw_data_t pHwData );
74void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 );
75void hal_set_rf_power( phw_data_t pHwData, u8 PowerIndex ); // 20060621 Modify
76void hal_reset_counter( phw_data_t pHwData );
77void hal_set_radio_mode( phw_data_t pHwData, unsigned char boValue);
78void hal_descriptor_indicate( phw_data_t pHwData, PDESCRIPTOR pDes );
79u8 hal_get_antenna_number( phw_data_t pHwData );
80void hal_set_antenna_number( phw_data_t pHwData, u8 number );
81u32 hal_get_bss_pk_cnt( phw_data_t pHwData );
82#define hal_get_region_from_EEPROM( _A ) ( (_A)->Wb35Reg.EEPROMRegion )
83void hal_set_accept_promiscuous ( phw_data_t pHwData, u8 enable);
84#define hal_get_tx_buffer( _A, _B ) Wb35Tx_get_tx_buffer( _A, _B )
85u8 hal_get_hw_radio_off ( phw_data_t pHwData );
86#define hal_software_set( _A ) (_A->SoftwareSet)
87#define hal_driver_init_OK( _A ) (_A->IsInitOK)
88#define hal_rssi_boundary_high( _A ) (_A->RSSI_high)
89#define hal_rssi_boundary_low( _A ) (_A->RSSI_low)
90#define hal_scan_interval( _A ) (_A->Scan_Interval)
91void hal_scan_status_indicate( phw_data_t pHwData, u8 status); // 0: complete, 1: in progress
92void hal_system_power_change( phw_data_t pHwData, u32 PowerState ); // 20051230 -=D0 1=D1 ..
93void hal_surprise_remove( phw_data_t pHwData );
94
95#define PHY_DEBUG( msg, args... )
96
97
98
99void hal_rate_change( phw_data_t pHwData ); // Notify the HAL rate is changing 20060613.1
100unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, PULONG pValue );
101unsigned char hal_set_dxx_reg( phw_data_t pHwData, u16 number, u32 value );
102#define hal_get_time_count( _P ) (_P->time_count/10) // return 100ms count
103#define hal_detect_error( _P ) (_P->WbUsb.DetectCount)
104unsigned char hal_set_LED( phw_data_t pHwData, u32 Mode ); // 20061108 for WPS led control
105
106//-------------------------------------------------------------------------
107// The follow function is unused for IS89C35
108//-------------------------------------------------------------------------
109#define hal_disable_interrupt(_A)
110#define hal_enable_interrupt(_A)
111#define hal_get_interrupt_type( _A)
112#define hal_get_clear_interrupt(_A)
113#define hal_ibss_disconnect(_A) hal_stop_sync_bss(_A)
114#define hal_join_request_stop(_A)
115unsigned char hal_idle( phw_data_t pHwData );
116#define pa_stall_execution( _A ) //OS_SLEEP( 1 )
117#define hw_get_cxx_reg( _A, _B, _C )
118#define hw_set_cxx_reg( _A, _B, _C )
119#define hw_get_dxx_reg( _A, _B, _C ) hal_get_dxx_reg( _A, _B, (PULONG)_C )
120#define hw_set_dxx_reg( _A, _B, _C ) hal_set_dxx_reg( _A, _B, (u32)_C )
121
122
diff --git a/drivers/staging/winbond/wbhal_s.h b/drivers/staging/winbond/wbhal_s.h
new file mode 100644
index 000000000000..5b862ff357bd
--- /dev/null
+++ b/drivers/staging/winbond/wbhal_s.h
@@ -0,0 +1,615 @@
1//[20040722 WK]
2#define HAL_LED_SET_MASK 0x001c //20060901 Extend
3#define HAL_LED_SET_SHIFT 2
4
5//supported RF type
6#define RF_MAXIM_2825 0
7#define RF_MAXIM_2827 1
8#define RF_MAXIM_2828 2
9#define RF_MAXIM_2829 3
10#define RF_MAXIM_V1 15
11#define RF_AIROHA_2230 16
12#define RF_AIROHA_7230 17
13#define RF_AIROHA_2230S 18 // 20060420 Add this
14// #define RF_RFMD_2959 32 // 20060626 Remove all about RFMD
15#define RF_WB_242 33
16#define RF_WB_242_1 34 // 20060619.5 Add
17#define RF_DECIDE_BY_INF 255
18
19//----------------------------------------------------------------
20// The follow define connect to upper layer
21// User must modify for connection between HAL and upper layer
22//----------------------------------------------------------------
23
24
25
26
27/////////////////////////////////////////////////////////////////////////////////////////////////////
28//================================================================================================
29// Common define
30//================================================================================================
31#define HAL_USB_MODE_BURST( _H ) (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify
32
33// Scan interval
34#define SCAN_MAX_CHNL_TIME (50)
35
36// For TxL2 Frame typr recognise
37#define FRAME_TYPE_802_3_DATA 0
38#define FRAME_TYPE_802_11_MANAGEMENT 1
39#define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2
40#define FRAME_TYPE_802_11_CONTROL 3
41#define FRAME_TYPE_802_11_DATA 4
42#define FRAME_TYPE_PROMISCUOUS 5
43
44// The follow definition is used for convert the frame--------------------
45#define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset
46#define DOT_3_TYPE_OFFSET 12
47#define DOT_11_MAC_HEADER_SIZE 24
48#define DOT_11_SNAP_SIZE 6
49#define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame. Type encapsulatuin.
50#define DEFAULT_SIFSTIME 10
51#define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment
52#define DEFAULT_MSDU_LIFE_TIME 0xffff
53
54#define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144+48)
55#define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72+24)
56#define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16+4+6)
57#define Tsym 4
58
59// Frame Type of Bits (2, 3)---------------------------------------------
60#define MAC_TYPE_MANAGEMENT 0x00
61#define MAC_TYPE_CONTROL 0x04
62#define MAC_TYPE_DATA 0x08
63#define MASK_FRAGMENT_NUMBER 0x000F
64#define SEQUENCE_NUMBER_SHIFT 4
65
66#define HAL_WOL_TYPE_WAKEUP_FRAME 0x01
67#define HAL_WOL_TYPE_MAGIC_PACKET 0x02
68
69// 20040106 ADDED
70#define HAL_KEYTYPE_WEP40 0
71#define HAL_KEYTYPE_WEP104 1
72#define HAL_KEYTYPE_TKIP 2 // 128 bit key
73#define HAL_KEYTYPE_AES_CCMP 3 // 128 bit key
74
75// For VM state
76enum {
77 VM_STOP = 0,
78 VM_RUNNING,
79 VM_COMPLETED
80};
81
82// Be used for 802.11 mac header
83typedef struct _MAC_FRAME_CONTROL {
84 u8 mac_frame_info; // this is a combination of the protovl version, type and subtype
85 u8 to_ds:1;
86 u8 from_ds:1;
87 u8 more_frag:1;
88 u8 retry:1;
89 u8 pwr_mgt:1;
90 u8 more_data:1;
91 u8 WEP:1;
92 u8 order:1;
93} MAC_FRAME_CONTROL, *PMAC_FRAME_CONTROL;
94
95//-----------------------------------------------------
96// Normal Key table format
97//-----------------------------------------------------
98// The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX
99#define MAX_KEY_TABLE 24 // 24 entry for storing key data
100#define GROUP_KEY_START_INDEX 4
101#define MAPPING_KEY_START_INDEX 8
102typedef struct _KEY_TABLE
103{
104 u32 DW0_Valid:1;
105 u32 DW0_NullKey:1;
106 u32 DW0_Security_Mode:2;//0:WEP 40 bit 1:WEP 104 bit 2:TKIP 128 bit 3:CCMP 128 bit
107 u32 DW0_WEPON:1;
108 u32 DW0_RESERVED:11;
109 u32 DW0_Address1:16;
110
111 u32 DW1_Address2;
112
113 u32 DW2_RxSequenceCount1;
114
115 u32 DW3_RxSequenceCount2:16;
116 u32 DW3_RESERVED:16;
117
118 u32 DW4_TxSequenceCount1;
119
120 u32 DW5_TxSequenceCount2:16;
121 u32 DW5_RESERVED:16;
122
123} KEY_TABLE, *PKEY_TABLE;
124
125//--------------------------------------------------------
126// Descriptor
127//--------------------------------------------------------
128#define MAX_DESCRIPTOR_BUFFER_INDEX 8 // Have to multiple of 2
129//#define FLAG_ERROR_TX_MASK cpu_to_le32(0x000000bf) //20061009 marked by anson's endian
130#define FLAG_ERROR_TX_MASK 0x000000bf //20061009 anson's endian
131//#define FLAG_ERROR_RX_MASK 0x00000c3f
132//#define FLAG_ERROR_RX_MASK cpu_to_le32(0x0000083f) //20061009 marked by anson's endian
133 //Don't care replay error,
134 //it is handled by S/W
135#define FLAG_ERROR_RX_MASK 0x0000083f //20060926 anson's endian
136
137#define FLAG_BAND_RX_MASK 0x10000000 //Bit 28
138
139typedef struct _R00_DESCRIPTOR
140{
141 union
142 {
143 u32 value;
144 #ifdef _BIG_ENDIAN_ //20060926 anson's endian
145 struct
146 {
147 u32 R00_packet_or_buffer_status:1;
148 u32 R00_packet_in_fifo:1;
149 u32 R00_RESERVED:2;
150 u32 R00_receive_byte_count:12;
151 u32 R00_receive_time_index:16;
152 };
153 #else
154 struct
155 {
156 u32 R00_receive_time_index:16;
157 u32 R00_receive_byte_count:12;
158 u32 R00_RESERVED:2;
159 u32 R00_packet_in_fifo:1;
160 u32 R00_packet_or_buffer_status:1;
161 };
162 #endif
163 };
164} R00_DESCRIPTOR, *PR00_DESCRIPTOR;
165
166typedef struct _T00_DESCRIPTOR
167{
168 union
169 {
170 u32 value;
171 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
172 struct
173 {
174 u32 T00_first_mpdu:1; // for hardware use
175 u32 T00_last_mpdu:1; // for hardware use
176 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
177 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
178 u32 T00_RESERVED_ID:2;//3 bit ID reserved
179 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
180 u32 T00_RESERVED:4;
181 u32 T00_header_length:6;
182 u32 T00_frame_length:12;
183 };
184 #else
185 struct
186 {
187 u32 T00_frame_length:12;
188 u32 T00_header_length:6;
189 u32 T00_RESERVED:4;
190 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
191 u32 T00_RESERVED_ID:2;//3 bit ID reserved
192 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
193 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
194 u32 T00_last_mpdu:1; // for hardware use
195 u32 T00_first_mpdu:1; // for hardware use
196 };
197 #endif
198 };
199} T00_DESCRIPTOR, *PT00_DESCRIPTOR;
200
201typedef struct _R01_DESCRIPTOR
202{
203 union
204 {
205 u32 value;
206 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
207 struct
208 {
209 u32 R01_RESERVED:3;
210 u32 R01_mod_type:1;
211 u32 R01_pre_type:1;
212 u32 R01_data_rate:3;
213 u32 R01_AGC_state:8;
214 u32 R01_LNA_state:2;
215 u32 R01_decryption_method:2;
216 u32 R01_mic_error:1;
217 u32 R01_replay:1;
218 u32 R01_broadcast_frame:1;
219 u32 R01_multicast_frame:1;
220 u32 R01_directed_frame:1;
221 u32 R01_receive_frame_antenna_selection:1;
222 u32 R01_frame_receive_during_atim_window:1;
223 u32 R01_protocol_version_error:1;
224 u32 R01_authentication_frame_icv_error:1;
225 u32 R01_null_key_to_authentication_frame:1;
226 u32 R01_icv_error:1;
227 u32 R01_crc_error:1;
228 };
229 #else
230 struct
231 {
232 u32 R01_crc_error:1;
233 u32 R01_icv_error:1;
234 u32 R01_null_key_to_authentication_frame:1;
235 u32 R01_authentication_frame_icv_error:1;
236 u32 R01_protocol_version_error:1;
237 u32 R01_frame_receive_during_atim_window:1;
238 u32 R01_receive_frame_antenna_selection:1;
239 u32 R01_directed_frame:1;
240 u32 R01_multicast_frame:1;
241 u32 R01_broadcast_frame:1;
242 u32 R01_replay:1;
243 u32 R01_mic_error:1;
244 u32 R01_decryption_method:2;
245 u32 R01_LNA_state:2;
246 u32 R01_AGC_state:8;
247 u32 R01_data_rate:3;
248 u32 R01_pre_type:1;
249 u32 R01_mod_type:1;
250 u32 R01_RESERVED:3;
251 };
252 #endif
253 };
254} R01_DESCRIPTOR, *PR01_DESCRIPTOR;
255
256typedef struct _T01_DESCRIPTOR
257{
258 union
259 {
260 u32 value;
261 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
262 struct
263 {
264 u32 T01_rts_cts_duration:16;
265 u32 T01_fall_back_rate:3;
266 u32 T01_add_rts:1;
267 u32 T01_add_cts:1;
268 u32 T01_modulation_type:1;
269 u32 T01_plcp_header_length:1;
270 u32 T01_transmit_rate:3;
271 u32 T01_wep_id:2;
272 u32 T01_add_challenge_text:1;
273 u32 T01_inhibit_crc:1;
274 u32 T01_loop_back_wep_mode:1;
275 u32 T01_retry_abort_ebable:1;
276 };
277 #else
278 struct
279 {
280 u32 T01_retry_abort_ebable:1;
281 u32 T01_loop_back_wep_mode:1;
282 u32 T01_inhibit_crc:1;
283 u32 T01_add_challenge_text:1;
284 u32 T01_wep_id:2;
285 u32 T01_transmit_rate:3;
286 u32 T01_plcp_header_length:1;
287 u32 T01_modulation_type:1;
288 u32 T01_add_cts:1;
289 u32 T01_add_rts:1;
290 u32 T01_fall_back_rate:3;
291 u32 T01_rts_cts_duration:16;
292 };
293 #endif
294 };
295} T01_DESCRIPTOR, *PT01_DESCRIPTOR;
296
297typedef struct _T02_DESCRIPTOR
298{
299 union
300 {
301 u32 value;
302 #ifdef _BIG_ENDIAN_ //20061009 add by anson's endian
303 struct
304 {
305 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
306 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
307 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
308 u32 T02_Tx_PktID:4;
309 u32 T02_MPDU_Cnt:4;
310 u32 T02_RTS_Cnt:4;
311 u32 T02_RESERVED:7;
312 u32 T02_transmit_complete:1;
313 u32 T02_transmit_abort_due_to_TBTT:1;
314 u32 T02_effective_transmission_rate:1;
315 u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
316 u32 T02_discard_due_to_null_wep_key:1;
317 u32 T02_RESERVED_1:1;
318 u32 T02_out_of_MaxTxMSDULiftTime:1;
319 u32 T02_transmit_abort:1;
320 u32 T02_transmit_fail:1;
321 };
322 #else
323 struct
324 {
325 u32 T02_transmit_fail:1;
326 u32 T02_transmit_abort:1;
327 u32 T02_out_of_MaxTxMSDULiftTime:1;
328 u32 T02_RESERVED_1:1;
329 u32 T02_discard_due_to_null_wep_key:1;
330 u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
331 u32 T02_effective_transmission_rate:1;
332 u32 T02_transmit_abort_due_to_TBTT:1;
333 u32 T02_transmit_complete:1;
334 u32 T02_RESERVED:7;
335 u32 T02_RTS_Cnt:4;
336 u32 T02_MPDU_Cnt:4;
337 u32 T02_Tx_PktID:4;
338 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
339 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
340 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
341 };
342 #endif
343 };
344} T02_DESCRIPTOR, *PT02_DESCRIPTOR;
345
346typedef struct _DESCRIPTOR { // Skip length = 8 DWORD
347 // ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition
348 u8 Descriptor_ID;
349 //----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------
350 u8 RESERVED[3];
351
352 u16 FragmentThreshold;
353 u8 InternalUsed;//Only can be used by operation of descriptor definition
354 u8 Type;// 0: 802.3 1:802.11 data frame 2:802.11 management frame
355
356 u8 PreambleMode;// 0: short 1:long
357 u8 TxRate;
358 u8 FragmentCount;
359 u8 EapFix; // For speed up key install
360
361 // For R00 and T00 ----------------------------------------------
362 union
363 {
364 R00_DESCRIPTOR R00;
365 T00_DESCRIPTOR T00;
366 };
367
368 // For R01 and T01 ----------------------------------------------
369 union
370 {
371 R01_DESCRIPTOR R01;
372 T01_DESCRIPTOR T01;
373 };
374
375 // For R02 and T02 ----------------------------------------------
376 union
377 {
378 u32 R02;
379 T02_DESCRIPTOR T02;
380 };
381
382 // For R03 and T03 ----------------------------------------------
383 // For software used
384 union
385 {
386 u32 R03;
387 u32 T03;
388 struct
389 {
390 u8 buffer_number;
391 u8 buffer_start_index;
392 u16 buffer_total_size;
393 };
394 };
395
396 // For storing the buffer
397 u16 buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ];
398 void* buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q
399
400} DESCRIPTOR, *PDESCRIPTOR;
401
402
403#define DEFAULT_NULL_PACKET_COUNT 180000 //20060828.1 Add. 180 seconds
404
405#define MAX_TXVGA_EEPROM 9 //How many word(u16) of EEPROM will be used for TxVGA
406#define MAX_RF_PARAMETER 32
407
408typedef struct _TXVGA_FOR_50 {
409 u8 ChanNo;
410 u8 TxVgaValue;
411} TXVGA_FOR_50;
412
413
414//=====================================================================
415// Device related include
416//=====================================================================
417
418#include "linux/wbusb_s.h"
419#include "linux/wb35reg_s.h"
420#include "linux/wb35tx_s.h"
421#include "linux/wb35rx_s.h"
422
423
424// For Hal using ==================================================================
425typedef struct _HW_DATA_T
426{
427 // For compatible with 33
428 u32 revision;
429 u32 BB3c_cal; // The value for Tx calibration comes from EEPROM
430 u32 BB54_cal; // The value for Rx calibration comes from EEPROM
431
432
433 // For surprise remove
434 u32 SurpriseRemove; // 0: Normal 1: Surprise remove
435 u8 InitialResource;
436 u8 IsKeyPreSet;
437 u8 CalOneTime; // 20060630.1
438
439 u8 VCO_trim;
440
441 // For Fix 1'st DMA bug
442 u32 FragCount;
443 u32 DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2.
444
445 //=======================================================================================
446 // For USB driver, hal need more variables. Due to
447 // 1. NDIS-WDM operation
448 // 2. The SME, MLME and OLD MDS need Adapter structure, but the driver under HAL doesn't
449 // have that parameter when receiving and indicating packet.
450 // The MDS must input the Adapter pointer as the second parameter of hal_init_hardware.
451 // The function usage is different than PCI driver.
452 //=======================================================================================
453 void* Adapter;
454
455 //===============================================
456 // Definition for MAC address
457 //===============================================
458 u8 PermanentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are stored in EEPROM. + 2 to 8-byte alignment
459 u8 CurrentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are in used. + 2 to 8-byte alignment
460
461 //=====================================================================
462 // Definition for 802.11
463 //=====================================================================
464 PUCHAR bssid_pointer; // Used by hal_get_bssid for return value
465 u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer
466 u8 ssid[32];// maximum ssid length is 32 byte
467
468 u16 AID;
469 u8 ssid_length;
470 u8 Channel;
471
472 u16 ListenInterval;
473 u16 CapabilityInformation;
474
475 u16 BeaconPeriod;
476 u16 ProbeDelay;
477
478 u8 bss_type;// 0: IBSS_NET or 1:ESS_NET
479 u8 preamble;// 0: short preamble, 1: long preamble
480 u8 slot_time_select;// 9 or 20 value
481 u8 phy_type;// Phy select
482
483 u32 phy_para[MAX_RF_PARAMETER];
484 u32 phy_number;
485
486 u32 CurrentRadioSw; // 20060320.2 0:On 1:Off
487 u32 CurrentRadioHw; // 20060825 0:On 1:Off
488
489 PUCHAR power_save_point; // Used by hal_get_power_save_mode for return value
490 u8 cwmin;
491 u8 desired_power_save;
492 u8 dtim;// Is running dtim
493 u8 mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r
494
495 u16 MaxReceiveLifeTime;
496 u16 FragmentThreshold;
497 u16 FragmentThreshold_tmp;
498 u16 cwmax;
499
500 u8 Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment
501 u32 Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit)
502 u8 CurrentDefaultKeyIndex;
503 u32 CurrentDefaultKeyLength;
504
505 //========================================================================
506 // Variable for each module
507 //========================================================================
508 WBUSB WbUsb; // Need WbUsb.h
509 WB35REG Wb35Reg; // Need Wb35Reg.h
510 WB35TX Wb35Tx; // Need Wb35Tx.h
511 WB35RX Wb35Rx; // Need Wb35Rx.h
512
513 OS_TIMER LEDTimer;// For LED
514
515 u32 LEDpoint;// For LED
516
517 u32 dto_tx_retry_count; // LA20040210_DTO kevin
518 u32 dto_tx_frag_count; // LA20040210_DTO kevin
519 u32 rx_ok_count[13]; // index=0: total rx ok
520 //u32 rx_ok_bytes[13]; // index=0, total rx ok bytes
521 u32 rx_err_count[13]; // index=0: total rx err
522
523 //for Tx debug
524 u32 tx_TBTT_start_count;
525 u32 tx_ETR_count;
526 u32 tx_WepOn_false_count;
527 u32 tx_Null_key_count;
528 u32 tx_retry_count[8];
529
530 u8 PowerIndexFromEEPROM; // For 2412MHz
531 u8 power_index;
532 u8 IsWaitJoinComplete; // TRUE: set join request
533 u8 band;
534
535 u16 SoftwareSet;
536 u16 Reserved_s;
537
538 u32 IsInitOK; // 0: Driver starting 1: Driver init OK
539
540 // For Phy calibration
541 s32 iq_rsdl_gain_tx_d2;
542 s32 iq_rsdl_phase_tx_d2;
543 u32 txvga_setting_for_cal; // 20060703.1 Add
544
545 u8 TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value
546 u8 TxVgaFor24[16]; // Max is 14, 2 for alignment
547 TXVGA_FOR_50 TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments
548
549 u16 Scan_Interval;
550 u16 RESERVED6;
551
552 // LED control
553 u32 LED_control;
554 // LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0]
555 // Gray_Led
556 // For Led gray setting
557 // Led
558 // 0: normal control, LED behavior will decide by EEPROM setting
559 // 1: Turn off specific LED
560 // 2: Always on specific LED
561 // 3: slow blinking specific LED
562 // 4: fast blinking specific LED
563 // 5: WPS led control is set. Led0 is Red, Led1 id Green
564 // Led[1] is parameter for WPS LED mode
565 // // 1:InProgress 2: Error 3: Session overlap 4: Success 20061108 control
566
567 u32 LED_LinkOn; //Turn LED on control
568 u32 LED_Scanning; // Let LED in scan process control
569 u32 LED_Blinking; // Temp variable for shining
570 u32 RxByteCountLast;
571 u32 TxByteCountLast;
572
573 s32 SurpriseRemoveCount;
574
575 // For global timer
576 u32 time_count;//TICK_TIME_100ms 1 = 100ms
577
578 // For error recover
579 u32 HwStop;
580
581 // 20060828.1 for avoid AP disconnect
582 u32 NullPacketCount;
583
584} hw_data_t, *phw_data_t;
585
586// The mapping of Rx and Tx descriptor field
587typedef struct _HAL_RATE
588{
589 // DSSS
590 u32 RESERVED_0;
591 u32 NumRate2MS;
592 u32 NumRate55MS;
593 u32 NumRate11MS;
594
595 u32 RESERVED_1[4];
596
597 u32 NumRate1M;
598 u32 NumRate2ML;
599 u32 NumRate55ML;
600 u32 NumRate11ML;
601
602 u32 RESERVED_2[4];
603
604 // OFDM
605 u32 NumRate6M;
606 u32 NumRate9M;
607 u32 NumRate12M;
608 u32 NumRate18M;
609 u32 NumRate24M;
610 u32 NumRate36M;
611 u32 NumRate48M;
612 u32 NumRate54M;
613} HAL_RATE, *PHAL_RATE;
614
615
diff --git a/drivers/staging/winbond/wblinux.c b/drivers/staging/winbond/wblinux.c
new file mode 100644
index 000000000000..2eade5a47b19
--- /dev/null
+++ b/drivers/staging/winbond/wblinux.c
@@ -0,0 +1,277 @@
1//============================================================================
2// Copyright (c) 1996-2005 Winbond Electronic Corporation
3//
4// Module Name:
5// wblinux.c
6//
7// Abstract:
8// Linux releated routines
9//
10//============================================================================
11#include "os_common.h"
12
13u32
14WBLINUX_MemoryAlloc(void* *VirtualAddress, u32 Length)
15{
16 *VirtualAddress = kzalloc( Length, GFP_ATOMIC ); //GFP_KERNEL is not suitable
17
18 if (*VirtualAddress == NULL)
19 return 0;
20 return 1;
21}
22
23s32
24EncapAtomicInc(PADAPTER Adapter, void* pAtomic)
25{
26 PWBLINUX pWbLinux = &Adapter->WbLinux;
27 u32 ltmp;
28 PULONG pltmp = (PULONG)pAtomic;
29 OS_SPIN_LOCK_ACQUIRED( &pWbLinux->AtomicSpinLock );
30 (*pltmp)++;
31 ltmp = (*pltmp);
32 OS_SPIN_LOCK_RELEASED( &pWbLinux->AtomicSpinLock );
33 return ltmp;
34}
35
36s32
37EncapAtomicDec(PADAPTER Adapter, void* pAtomic)
38{
39 PWBLINUX pWbLinux = &Adapter->WbLinux;
40 u32 ltmp;
41 PULONG pltmp = (PULONG)pAtomic;
42 OS_SPIN_LOCK_ACQUIRED( &pWbLinux->AtomicSpinLock );
43 (*pltmp)--;
44 ltmp = (*pltmp);
45 OS_SPIN_LOCK_RELEASED( &pWbLinux->AtomicSpinLock );
46 return ltmp;
47}
48
49unsigned char
50WBLINUX_Initial(PADAPTER Adapter)
51{
52 PWBLINUX pWbLinux = &Adapter->WbLinux;
53
54 OS_SPIN_LOCK_ALLOCATE( &pWbLinux->SpinLock );
55 OS_SPIN_LOCK_ALLOCATE( &pWbLinux->AtomicSpinLock );
56 return TRUE;
57}
58
59void
60WBLinux_ReceivePacket(PADAPTER Adapter, PRXLAYER1 pRxLayer1)
61{
62 BUG();
63}
64
65
66void
67WBLINUX_GetNextPacket(PADAPTER Adapter, PDESCRIPTOR pDes)
68{
69 BUG();
70}
71
72void
73WBLINUX_GetNextPacketCompleted(PADAPTER Adapter, PDESCRIPTOR pDes)
74{
75 BUG();
76}
77
78void
79WBLINUX_Destroy(PADAPTER Adapter)
80{
81 WBLINUX_stop( Adapter );
82 OS_SPIN_LOCK_FREE( &pWbNdis->SpinLock );
83#ifdef _PE_USB_INI_DUMP_
84 WBDEBUG(("[w35und] unregister_netdev!\n"));
85#endif
86}
87
88void
89WBLINUX_stop( PADAPTER Adapter )
90{
91 PWBLINUX pWbLinux = &Adapter->WbLinux;
92 struct sk_buff *pSkb;
93
94 if (OS_ATOMIC_INC( Adapter, &pWbLinux->ThreadCount ) == 1) {
95 // Shutdown module immediately
96 pWbLinux->shutdown = 1;
97
98 while (pWbLinux->skb_array[ pWbLinux->skb_GetIndex ]) {
99 // Trying to free the un-sending packet
100 pSkb = pWbLinux->skb_array[ pWbLinux->skb_GetIndex ];
101 pWbLinux->skb_array[ pWbLinux->skb_GetIndex ] = NULL;
102 if( in_irq() )
103 dev_kfree_skb_irq( pSkb );
104 else
105 dev_kfree_skb( pSkb );
106
107 pWbLinux->skb_GetIndex++;
108 pWbLinux->skb_GetIndex %= WBLINUX_PACKET_ARRAY_SIZE;
109 }
110
111#ifdef _PE_STATE_DUMP_
112 WBDEBUG(( "[w35und] SKB_RELEASE OK\n" ));
113#endif
114 }
115
116 OS_ATOMIC_DEC( Adapter, &pWbLinux->ThreadCount );
117}
118
119void
120WbWlanHalt( PADAPTER Adapter )
121{
122 //---------------------
123 Adapter->sLocalPara.ShutDowned = TRUE;
124
125 Mds_Destroy( Adapter );
126
127 // Turn off Rx and Tx hardware ability
128 hal_stop( &Adapter->sHwData );
129#ifdef _PE_USB_INI_DUMP_
130 WBDEBUG(("[w35und] Hal_stop O.K.\n"));
131#endif
132 OS_SLEEP(100000);// Waiting Irp completed
133
134 // Destroy the NDIS module
135 WBLINUX_Destroy( Adapter );
136
137 // Halt the HAL
138 hal_halt(&Adapter->sHwData, NULL);
139}
140
141unsigned char
142WbWLanInitialize(PADAPTER Adapter)
143{
144 phw_data_t pHwData;
145 PUCHAR pMacAddr, pMacAddr2;
146 u32 InitStep = 0;
147 u8 EEPROM_region;
148 u8 HwRadioOff;
149
150 do {
151 //
152 // Setting default value for Linux
153 //
154 Adapter->sLocalPara.region_INF = REGION_AUTO;
155 Adapter->sLocalPara.TxRateMode = RATE_AUTO;
156 psLOCAL->bMacOperationMode = MODE_802_11_BG; // B/G mode
157 Adapter->Mds.TxRTSThreshold = DEFAULT_RTSThreshold;
158 Adapter->Mds.TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD;
159 hal_set_phy_type( &Adapter->sHwData, RF_WB_242_1 );
160 Adapter->sLocalPara.MTUsize = MAX_ETHERNET_PACKET_SIZE;
161 psLOCAL->bPreambleMode = AUTO_MODE;
162 Adapter->sLocalPara.RadioOffStatus.boSwRadioOff = FALSE;
163 pHwData = &Adapter->sHwData;
164 hal_set_phy_type( pHwData, RF_DECIDE_BY_INF );
165
166 //
167 // Initial each module and variable
168 //
169 if (!WBLINUX_Initial(Adapter)) {
170#ifdef _PE_USB_INI_DUMP_
171 WBDEBUG(("[w35und]WBNDIS initialization failed\n"));
172#endif
173 break;
174 }
175
176 // Initial Software variable
177 Adapter->sLocalPara.ShutDowned = FALSE;
178
179 //added by ws for wep key error detection
180 Adapter->sLocalPara.bWepKeyError= FALSE;
181 Adapter->sLocalPara.bToSelfPacketReceived = FALSE;
182 Adapter->sLocalPara.WepKeyDetectTimerCount= 2 * 100; /// 2 seconds
183
184 // Initial USB hal
185 InitStep = 1;
186 pHwData = &Adapter->sHwData;
187 if (!hal_init_hardware(pHwData, Adapter))
188 break;
189
190 EEPROM_region = hal_get_region_from_EEPROM( pHwData );
191 if (EEPROM_region != REGION_AUTO)
192 psLOCAL->region = EEPROM_region;
193 else {
194 if (psLOCAL->region_INF != REGION_AUTO)
195 psLOCAL->region = psLOCAL->region_INF;
196 else
197 psLOCAL->region = REGION_USA; //default setting
198 }
199
200 // Get Software setting flag from hal
201 Adapter->sLocalPara.boAntennaDiversity = FALSE;
202 if (hal_software_set(pHwData) & 0x00000001)
203 Adapter->sLocalPara.boAntennaDiversity = TRUE;
204
205 //
206 // For TS module
207 //
208 InitStep = 2;
209
210 // For MDS module
211 InitStep = 3;
212 Mds_initial(Adapter);
213
214 //=======================================
215 // Initialize the SME, SCAN, MLME, ROAM
216 //=======================================
217 InitStep = 4;
218 InitStep = 5;
219 InitStep = 6;
220
221 // If no user-defined address in the registry, use the addresss "burned" on the NIC instead.
222 pMacAddr = Adapter->sLocalPara.ThisMacAddress;
223 pMacAddr2 = Adapter->sLocalPara.PermanentAddress;
224 hal_get_permanent_address( pHwData, Adapter->sLocalPara.PermanentAddress );// Reading ethernet address from EEPROM
225 if (OS_MEMORY_COMPARE(pMacAddr, "\x00\x00\x00\x00\x00\x00", MAC_ADDR_LENGTH )) // Is equal
226 {
227 memcpy( pMacAddr, pMacAddr2, MAC_ADDR_LENGTH );
228 } else {
229 // Set the user define MAC address
230 hal_set_ethernet_address( pHwData, Adapter->sLocalPara.ThisMacAddress );
231 }
232
233 //get current antenna
234 psLOCAL->bAntennaNo = hal_get_antenna_number(pHwData);
235#ifdef _PE_STATE_DUMP_
236 WBDEBUG(("Driver init, antenna no = %d\n", psLOCAL->bAntennaNo));
237#endif
238 hal_get_hw_radio_off( pHwData );
239
240 // Waiting for HAL setting OK
241 while (!hal_idle(pHwData))
242 OS_SLEEP(10000);
243
244 MTO_Init(Adapter);
245
246 HwRadioOff = hal_get_hw_radio_off( pHwData );
247 psLOCAL->RadioOffStatus.boHwRadioOff = !!HwRadioOff;
248
249 hal_set_radio_mode( pHwData, (unsigned char)(psLOCAL->RadioOffStatus.boSwRadioOff || psLOCAL->RadioOffStatus.boHwRadioOff) );
250
251 hal_driver_init_OK(pHwData) = 1; // Notify hal that the driver is ready now.
252 //set a tx power for reference.....
253// sme_set_tx_power_level(Adapter, 12); FIXME?
254 return TRUE;
255 }
256 while(FALSE);
257
258 switch (InitStep) {
259 case 5:
260 case 4:
261 case 3: Mds_Destroy( Adapter );
262 case 2:
263 case 1: WBLINUX_Destroy( Adapter );
264 hal_halt( pHwData, NULL );
265 case 0: break;
266 }
267
268 return FALSE;
269}
270
271void WBLINUX_ConnectStatus(PADAPTER Adapter, u32 flag)
272{
273 PWBLINUX pWbLinux = &Adapter->WbLinux;
274
275 pWbLinux->LinkStatus = flag; // OS_DISCONNECTED or OS_CONNECTED
276}
277
diff --git a/drivers/staging/winbond/wblinux_f.h b/drivers/staging/winbond/wblinux_f.h
new file mode 100644
index 000000000000..68240c5fc80d
--- /dev/null
+++ b/drivers/staging/winbond/wblinux_f.h
@@ -0,0 +1,23 @@
1//=========================================================================
2// Copyright (c) 1996-2004 Winbond Electronic Corporation
3//
4// wblinux_f.h
5//
6u32 WBLINUX_MemoryAlloc( void* *VirtualAddress, u32 Length );
7s32 EncapAtomicInc( PADAPTER Adapter, void* pAtomic );
8s32 EncapAtomicDec( PADAPTER Adapter, void* pAtomic );
9void WBLinux_ReceivePacket( PADAPTER Adapter, PRXLAYER1 pRxLayer1 );
10unsigned char WBLINUX_Initial( PADAPTER Adapter );
11int wb35_start_xmit(struct sk_buff *skb, struct net_device *netdev );
12void WBLINUX_GetNextPacket( PADAPTER Adapter, PDESCRIPTOR pDes );
13void WBLINUX_GetNextPacketCompleted( PADAPTER Adapter, PDESCRIPTOR pDes );
14void WBLINUX_stop( PADAPTER Adapter );
15void WBLINUX_Destroy( PADAPTER Adapter );
16void wb35_set_multicast( struct net_device *netdev );
17struct net_device_stats * wb35_netdev_stats( struct net_device *netdev );
18void WBLINUX_stop( PADAPTER Adapter );
19void WbWlanHalt( PADAPTER Adapter );
20void WBLINUX_ConnectStatus( PADAPTER Adapter, u32 flag );
21
22
23
diff --git a/drivers/staging/winbond/wblinux_s.h b/drivers/staging/winbond/wblinux_s.h
new file mode 100644
index 000000000000..97e9167ab839
--- /dev/null
+++ b/drivers/staging/winbond/wblinux_s.h
@@ -0,0 +1,45 @@
1//============================================================
2// wblinux_s.h
3//
4#define OS_MEMORY_ALLOC( _V, _S ) WBLINUX_MemoryAlloc( _V, _S )
5#define OS_LINK_STATUS (Adapter->WbLinux.LinkStatus == OS_CONNECTED)
6#define OS_SET_SHUTDOWN( _A ) _A->WbLinux.shutdown=1
7#define OS_SET_RESUME( _A ) _A->WbLinux.shutdown=0
8#define OS_CONNECT_STATUS_INDICATE( _A, _F ) WBLINUX_ConnectStatus( _A, _F )
9#define OS_DISCONNECTED 0
10#define OS_CONNECTED 1
11#define OS_STOP( _A ) WBLINUX_stop( _A )
12
13#define OS_CURRENT_RX_BYTE( _A ) _A->WbLinux.RxByteCount
14#define OS_CURRENT_TX_BYTE( _A ) _A->WbLinux.TxByteCount
15#define OS_EVENT_INDICATE( _A, _B, _F )
16#define OS_PMKID_STATUS_EVENT( _A )
17#define OS_RECEIVE_PACKET_INDICATE( _A, _D ) WBLinux_ReceivePacket( _A, _D )
18#define OS_RECEIVE_802_1X_PACKET_INDICATE( _A, _D ) EAP_ReceivePacket( _A, _D )
19#define OS_GET_PACKET( _A, _D ) WBLINUX_GetNextPacket( _A, _D )
20#define OS_GET_PACKET_COMPLETE( _A, _D ) WBLINUX_GetNextPacketCompleted( _A, _D )
21#define OS_SEND_RESULT( _A, _ID, _R )
22
23#define WBLINUX_PACKET_ARRAY_SIZE (ETHERNET_TX_DESCRIPTORS*4)
24
25typedef struct _WBLINUX
26{
27 OS_SPIN_LOCK AtomicSpinLock;
28 OS_SPIN_LOCK SpinLock;
29 u32 shutdown;
30
31 OS_ATOMIC ThreadCount;
32
33 u32 LinkStatus; // OS_DISCONNECTED or OS_CONNECTED
34
35 u32 RxByteCount;
36 u32 TxByteCount;
37
38 struct sk_buff *skb_array[ WBLINUX_PACKET_ARRAY_SIZE ];
39 struct sk_buff *packet_return;
40 s32 skb_SetIndex;
41 s32 skb_GetIndex;
42 s32 netif_state_stop; // 1: stop 0: normal
43} WBLINUX, *PWBLINUX;
44
45
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 00:13:37 -0400