diff options
-rw-r--r-- | arch/arm/kernel/perf_event.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index acc4e91dd300..ac4e9a1ed80b 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c | |||
@@ -69,18 +69,9 @@ struct cpu_hw_events { | |||
69 | }; | 69 | }; |
70 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); | 70 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
71 | 71 | ||
72 | /* PMU names. */ | ||
73 | static const char *arm_pmu_names[] = { | ||
74 | [ARM_PERF_PMU_ID_XSCALE1] = "xscale1", | ||
75 | [ARM_PERF_PMU_ID_XSCALE2] = "xscale2", | ||
76 | [ARM_PERF_PMU_ID_V6] = "v6", | ||
77 | [ARM_PERF_PMU_ID_V6MP] = "v6mpcore", | ||
78 | [ARM_PERF_PMU_ID_CA8] = "ARMv7 Cortex-A8", | ||
79 | [ARM_PERF_PMU_ID_CA9] = "ARMv7 Cortex-A9", | ||
80 | }; | ||
81 | |||
82 | struct arm_pmu { | 72 | struct arm_pmu { |
83 | enum arm_perf_pmu_ids id; | 73 | enum arm_perf_pmu_ids id; |
74 | const char *name; | ||
84 | irqreturn_t (*handle_irq)(int irq_num, void *dev); | 75 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
85 | void (*enable)(struct hw_perf_event *evt, int idx); | 76 | void (*enable)(struct hw_perf_event *evt, int idx); |
86 | void (*disable)(struct hw_perf_event *evt, int idx); | 77 | void (*disable)(struct hw_perf_event *evt, int idx); |
@@ -1225,6 +1216,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc, | |||
1225 | 1216 | ||
1226 | static const struct arm_pmu armv6pmu = { | 1217 | static const struct arm_pmu armv6pmu = { |
1227 | .id = ARM_PERF_PMU_ID_V6, | 1218 | .id = ARM_PERF_PMU_ID_V6, |
1219 | .name = "v6", | ||
1228 | .handle_irq = armv6pmu_handle_irq, | 1220 | .handle_irq = armv6pmu_handle_irq, |
1229 | .enable = armv6pmu_enable_event, | 1221 | .enable = armv6pmu_enable_event, |
1230 | .disable = armv6pmu_disable_event, | 1222 | .disable = armv6pmu_disable_event, |
@@ -1254,6 +1246,7 @@ const struct arm_pmu *__init armv6pmu_init(void) | |||
1254 | */ | 1246 | */ |
1255 | static const struct arm_pmu armv6mpcore_pmu = { | 1247 | static const struct arm_pmu armv6mpcore_pmu = { |
1256 | .id = ARM_PERF_PMU_ID_V6MP, | 1248 | .id = ARM_PERF_PMU_ID_V6MP, |
1249 | .name = "v6mpcore", | ||
1257 | .handle_irq = armv6pmu_handle_irq, | 1250 | .handle_irq = armv6pmu_handle_irq, |
1258 | .enable = armv6pmu_enable_event, | 1251 | .enable = armv6pmu_enable_event, |
1259 | .disable = armv6mpcore_pmu_disable_event, | 1252 | .disable = armv6mpcore_pmu_disable_event, |
@@ -2149,6 +2142,7 @@ static u32 __init armv7_reset_read_pmnc(void) | |||
2149 | const struct arm_pmu *__init armv7_a8_pmu_init(void) | 2142 | const struct arm_pmu *__init armv7_a8_pmu_init(void) |
2150 | { | 2143 | { |
2151 | armv7pmu.id = ARM_PERF_PMU_ID_CA8; | 2144 | armv7pmu.id = ARM_PERF_PMU_ID_CA8; |
2145 | armv7pmu.name = "ARMv7 Cortex-A8"; | ||
2152 | armv7pmu.cache_map = &armv7_a8_perf_cache_map; | 2146 | armv7pmu.cache_map = &armv7_a8_perf_cache_map; |
2153 | armv7pmu.event_map = &armv7_a8_perf_map; | 2147 | armv7pmu.event_map = &armv7_a8_perf_map; |
2154 | armv7pmu.num_events = armv7_reset_read_pmnc(); | 2148 | armv7pmu.num_events = armv7_reset_read_pmnc(); |
@@ -2158,6 +2152,7 @@ const struct arm_pmu *__init armv7_a8_pmu_init(void) | |||
2158 | const struct arm_pmu *__init armv7_a9_pmu_init(void) | 2152 | const struct arm_pmu *__init armv7_a9_pmu_init(void) |
2159 | { | 2153 | { |
2160 | armv7pmu.id = ARM_PERF_PMU_ID_CA9; | 2154 | armv7pmu.id = ARM_PERF_PMU_ID_CA9; |
2155 | armv7pmu.name = "ARMv7 Cortex-A9"; | ||
2161 | armv7pmu.cache_map = &armv7_a9_perf_cache_map; | 2156 | armv7pmu.cache_map = &armv7_a9_perf_cache_map; |
2162 | armv7pmu.event_map = &armv7_a9_perf_map; | 2157 | armv7pmu.event_map = &armv7_a9_perf_map; |
2163 | armv7pmu.num_events = armv7_reset_read_pmnc(); | 2158 | armv7pmu.num_events = armv7_reset_read_pmnc(); |
@@ -2578,6 +2573,7 @@ xscale1pmu_write_counter(int counter, u32 val) | |||
2578 | 2573 | ||
2579 | static const struct arm_pmu xscale1pmu = { | 2574 | static const struct arm_pmu xscale1pmu = { |
2580 | .id = ARM_PERF_PMU_ID_XSCALE1, | 2575 | .id = ARM_PERF_PMU_ID_XSCALE1, |
2576 | .name = "xscale1", | ||
2581 | .handle_irq = xscale1pmu_handle_irq, | 2577 | .handle_irq = xscale1pmu_handle_irq, |
2582 | .enable = xscale1pmu_enable_event, | 2578 | .enable = xscale1pmu_enable_event, |
2583 | .disable = xscale1pmu_disable_event, | 2579 | .disable = xscale1pmu_disable_event, |
@@ -2939,6 +2935,7 @@ xscale2pmu_write_counter(int counter, u32 val) | |||
2939 | 2935 | ||
2940 | static const struct arm_pmu xscale2pmu = { | 2936 | static const struct arm_pmu xscale2pmu = { |
2941 | .id = ARM_PERF_PMU_ID_XSCALE2, | 2937 | .id = ARM_PERF_PMU_ID_XSCALE2, |
2938 | .name = "xscale2", | ||
2942 | .handle_irq = xscale2pmu_handle_irq, | 2939 | .handle_irq = xscale2pmu_handle_irq, |
2943 | .enable = xscale2pmu_enable_event, | 2940 | .enable = xscale2pmu_enable_event, |
2944 | .disable = xscale2pmu_disable_event, | 2941 | .disable = xscale2pmu_disable_event, |
@@ -2999,7 +2996,7 @@ init_hw_perf_events(void) | |||
2999 | 2996 | ||
3000 | if (armpmu) { | 2997 | if (armpmu) { |
3001 | pr_info("enabled with %s PMU driver, %d counters available\n", | 2998 | pr_info("enabled with %s PMU driver, %d counters available\n", |
3002 | arm_pmu_names[armpmu->id], armpmu->num_events); | 2999 | armpmu->name, armpmu->num_events); |
3003 | } else { | 3000 | } else { |
3004 | pr_info("no hardware support available\n"); | 3001 | pr_info("no hardware support available\n"); |
3005 | } | 3002 | } |