diff options
| -rw-r--r-- | arch/arm/plat-s3c24xx/clock.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c index 79cda0faec86..99a44746f8f2 100644 --- a/arch/arm/plat-s3c24xx/clock.c +++ b/arch/arm/plat-s3c24xx/clock.c | |||
| @@ -172,6 +172,15 @@ int clk_set_rate(struct clk *clk, unsigned long rate) | |||
| 172 | if (IS_ERR(clk)) | 172 | if (IS_ERR(clk)) |
| 173 | return -EINVAL; | 173 | return -EINVAL; |
| 174 | 174 | ||
| 175 | /* We do not default just do a clk->rate = rate as | ||
| 176 | * the clock may have been made this way by choice. | ||
| 177 | */ | ||
| 178 | |||
| 179 | WARN_ON(clk->set_rate == NULL); | ||
| 180 | |||
| 181 | if (clk->set_rate == NULL) | ||
| 182 | return -EINVAL; | ||
| 183 | |||
| 175 | mutex_lock(&clocks_mutex); | 184 | mutex_lock(&clocks_mutex); |
| 176 | ret = (clk->set_rate)(clk, rate); | 185 | ret = (clk->set_rate)(clk, rate); |
| 177 | mutex_unlock(&clocks_mutex); | 186 | mutex_unlock(&clocks_mutex); |
| @@ -213,6 +222,12 @@ EXPORT_SYMBOL(clk_set_parent); | |||
| 213 | 222 | ||
| 214 | /* base clocks */ | 223 | /* base clocks */ |
| 215 | 224 | ||
| 225 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | ||
| 226 | { | ||
| 227 | clk->rate = rate; | ||
| 228 | return 0; | ||
| 229 | } | ||
| 230 | |||
| 216 | struct clk clk_xtal = { | 231 | struct clk clk_xtal = { |
| 217 | .name = "xtal", | 232 | .name = "xtal", |
| 218 | .id = -1, | 233 | .id = -1, |
| @@ -224,6 +239,7 @@ struct clk clk_xtal = { | |||
| 224 | struct clk clk_mpll = { | 239 | struct clk clk_mpll = { |
| 225 | .name = "mpll", | 240 | .name = "mpll", |
| 226 | .id = -1, | 241 | .id = -1, |
| 242 | .set_rate = clk_default_setrate, | ||
| 227 | }; | 243 | }; |
| 228 | 244 | ||
| 229 | struct clk clk_upll = { | 245 | struct clk clk_upll = { |
| @@ -239,6 +255,7 @@ struct clk clk_f = { | |||
| 239 | .rate = 0, | 255 | .rate = 0, |
| 240 | .parent = &clk_mpll, | 256 | .parent = &clk_mpll, |
| 241 | .ctrlbit = 0, | 257 | .ctrlbit = 0, |
| 258 | .set_rate = clk_default_setrate, | ||
| 242 | }; | 259 | }; |
| 243 | 260 | ||
| 244 | struct clk clk_h = { | 261 | struct clk clk_h = { |
| @@ -247,6 +264,7 @@ struct clk clk_h = { | |||
| 247 | .rate = 0, | 264 | .rate = 0, |
| 248 | .parent = NULL, | 265 | .parent = NULL, |
| 249 | .ctrlbit = 0, | 266 | .ctrlbit = 0, |
| 267 | .set_rate = clk_default_setrate, | ||
| 250 | }; | 268 | }; |
| 251 | 269 | ||
| 252 | struct clk clk_p = { | 270 | struct clk clk_p = { |
| @@ -255,6 +273,7 @@ struct clk clk_p = { | |||
| 255 | .rate = 0, | 273 | .rate = 0, |
| 256 | .parent = NULL, | 274 | .parent = NULL, |
| 257 | .ctrlbit = 0, | 275 | .ctrlbit = 0, |
| 276 | .set_rate = clk_default_setrate, | ||
| 258 | }; | 277 | }; |
| 259 | 278 | ||
| 260 | struct clk clk_usb_bus = { | 279 | struct clk clk_usb_bus = { |
