diff options
| -rw-r--r-- | arch/arm/mach-at91/clock.c | 42 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91/at91_pmc.h | 7 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91/board.h | 4 |
3 files changed, 51 insertions, 2 deletions
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index a33dfe450726..b87772cd3d32 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c | |||
| @@ -112,12 +112,34 @@ static void pmc_sys_mode(struct clk *clk, int is_on) | |||
| 112 | at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); | 112 | at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); |
| 113 | } | 113 | } |
| 114 | 114 | ||
| 115 | static void pmc_uckr_mode(struct clk *clk, int is_on) | ||
| 116 | { | ||
| 117 | unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); | ||
| 118 | |||
| 119 | if (is_on) { | ||
| 120 | is_on = AT91_PMC_LOCKU; | ||
| 121 | at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); | ||
| 122 | } else | ||
| 123 | at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); | ||
| 124 | |||
| 125 | do { | ||
| 126 | cpu_relax(); | ||
| 127 | } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); | ||
| 128 | } | ||
| 129 | |||
| 115 | /* USB function clocks (PLLB must be 48 MHz) */ | 130 | /* USB function clocks (PLLB must be 48 MHz) */ |
| 116 | static struct clk udpck = { | 131 | static struct clk udpck = { |
| 117 | .name = "udpck", | 132 | .name = "udpck", |
| 118 | .parent = &pllb, | 133 | .parent = &pllb, |
| 119 | .mode = pmc_sys_mode, | 134 | .mode = pmc_sys_mode, |
| 120 | }; | 135 | }; |
| 136 | static struct clk utmi_clk = { | ||
| 137 | .name = "utmi_clk", | ||
| 138 | .parent = &main_clk, | ||
| 139 | .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */ | ||
| 140 | .mode = pmc_uckr_mode, | ||
| 141 | .type = CLK_TYPE_PLL, | ||
| 142 | }; | ||
| 121 | static struct clk uhpck = { | 143 | static struct clk uhpck = { |
| 122 | .name = "uhpck", | 144 | .name = "uhpck", |
| 123 | .parent = &pllb, | 145 | .parent = &pllb, |
| @@ -361,7 +383,7 @@ static void __init init_programmable_clock(struct clk *clk) | |||
| 361 | 383 | ||
| 362 | static int at91_clk_show(struct seq_file *s, void *unused) | 384 | static int at91_clk_show(struct seq_file *s, void *unused) |
| 363 | { | 385 | { |
| 364 | u32 scsr, pcsr, sr; | 386 | u32 scsr, pcsr, uckr = 0, sr; |
| 365 | struct clk *clk; | 387 | struct clk *clk; |
| 366 | 388 | ||
| 367 | seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); | 389 | seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); |
| @@ -370,6 +392,8 @@ static int at91_clk_show(struct seq_file *s, void *unused) | |||
| 370 | seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); | 392 | seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); |
| 371 | seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); | 393 | seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); |
| 372 | seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); | 394 | seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); |
| 395 | if (cpu_is_at91cap9()) | ||
| 396 | seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); | ||
| 373 | seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); | 397 | seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); |
| 374 | seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); | 398 | seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); |
| 375 | 399 | ||
| @@ -382,6 +406,8 @@ static int at91_clk_show(struct seq_file *s, void *unused) | |||
| 382 | state = (scsr & clk->pmc_mask) ? "on" : "off"; | 406 | state = (scsr & clk->pmc_mask) ? "on" : "off"; |
| 383 | else if (clk->mode == pmc_periph_mode) | 407 | else if (clk->mode == pmc_periph_mode) |
| 384 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; | 408 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; |
| 409 | else if (clk->mode == pmc_uckr_mode) | ||
| 410 | state = (uckr & clk->pmc_mask) ? "on" : "off"; | ||
| 385 | else if (clk->pmc_mask) | 411 | else if (clk->pmc_mask) |
| 386 | state = (sr & clk->pmc_mask) ? "on" : "off"; | 412 | state = (sr & clk->pmc_mask) ? "on" : "off"; |
| 387 | else if (clk == &clk32k || clk == &main_clk) | 413 | else if (clk == &clk32k || clk == &main_clk) |
| @@ -582,6 +608,17 @@ int __init at91_clock_init(unsigned long main_clock) | |||
| 582 | uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); | 608 | uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); |
| 583 | 609 | ||
| 584 | /* | 610 | /* |
| 611 | * USB HS clock init | ||
| 612 | */ | ||
| 613 | if (cpu_is_at91cap9()) { | ||
| 614 | /* | ||
| 615 | * multiplier is hard-wired to 40 | ||
| 616 | * (obtain the USB High Speed 480 MHz when input is 12 MHz) | ||
| 617 | */ | ||
| 618 | utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; | ||
| 619 | } | ||
| 620 | |||
| 621 | /* | ||
| 585 | * MCK and CPU derive from one of those primary clocks. | 622 | * MCK and CPU derive from one of those primary clocks. |
| 586 | * For now, assume this parentage won't change. | 623 | * For now, assume this parentage won't change. |
| 587 | */ | 624 | */ |
| @@ -598,6 +635,9 @@ int __init at91_clock_init(unsigned long main_clock) | |||
| 598 | for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) | 635 | for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) |
| 599 | list_add_tail(&standard_pmc_clocks[i]->node, &clocks); | 636 | list_add_tail(&standard_pmc_clocks[i]->node, &clocks); |
| 600 | 637 | ||
| 638 | if (cpu_is_at91cap9()) | ||
| 639 | list_add_tail(&utmi_clk.node, &clocks); | ||
| 640 | |||
| 601 | /* MCK and CPU clock are "always on" */ | 641 | /* MCK and CPU clock are "always on" */ |
| 602 | clk_enable(&mck); | 642 | clk_enable(&mck); |
| 603 | 643 | ||
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index c2b13c280155..2001e81f2267 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h | |||
| @@ -39,10 +39,14 @@ | |||
| 39 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | 39 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ |
| 40 | 40 | ||
| 41 | #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ | 41 | #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ |
| 42 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ | ||
| 43 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ | ||
| 44 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ | ||
| 45 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ | ||
| 42 | 46 | ||
| 43 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ | 47 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ |
| 44 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | 48 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
| 45 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ | 49 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ |
| 46 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | 50 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ |
| 47 | 51 | ||
| 48 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | 52 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ |
| @@ -97,6 +101,7 @@ | |||
| 97 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | 101 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ |
| 98 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | 102 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ |
| 99 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | 103 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ |
| 104 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ | ||
| 100 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | 105 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ |
| 101 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | 106 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ |
| 102 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | 107 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ |
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h index dc189f01c5b3..1f247028686d 100644 --- a/include/asm-arm/arch-at91/board.h +++ b/include/asm-arm/arch-at91/board.h | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | #include <linux/i2c.h> | 36 | #include <linux/i2c.h> |
| 37 | #include <linux/leds.h> | 37 | #include <linux/leds.h> |
| 38 | #include <linux/spi/spi.h> | 38 | #include <linux/spi/spi.h> |
| 39 | #include <linux/usb/atmel_usba_udc.h> | ||
| 39 | 40 | ||
| 40 | /* USB Device */ | 41 | /* USB Device */ |
| 41 | struct at91_udc_data { | 42 | struct at91_udc_data { |
| @@ -45,6 +46,9 @@ struct at91_udc_data { | |||
| 45 | }; | 46 | }; |
| 46 | extern void __init at91_add_device_udc(struct at91_udc_data *data); | 47 | extern void __init at91_add_device_udc(struct at91_udc_data *data); |
| 47 | 48 | ||
| 49 | /* USB High Speed Device */ | ||
| 50 | extern void __init at91_add_device_usba(struct usba_platform_data *data); | ||
| 51 | |||
| 48 | /* Compact Flash */ | 52 | /* Compact Flash */ |
| 49 | struct at91_cf_data { | 53 | struct at91_cf_data { |
| 50 | u8 irq_pin; /* I/O IRQ */ | 54 | u8 irq_pin; /* I/O IRQ */ |
