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-rw-r--r--arch/arm/mach-omap1/Makefile2
-rw-r--r--arch/arm/mach-omap1/mcbsp.c280
-rw-r--r--arch/arm/mach-omap2/clock24xx.h30
3 files changed, 302 insertions, 10 deletions
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 5e9416e024dd..1bda8f5d7546 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -5,6 +5,8 @@
5# Common support 5# Common support
6obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o 6obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o
7 7
8obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
9
8obj-$(CONFIG_OMAP_MPU_TIMER) += time.o 10obj-$(CONFIG_OMAP_MPU_TIMER) += time.o
9obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o 11obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
10 12
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
new file mode 100644
index 000000000000..2d2c2522b048
--- /dev/null
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -0,0 +1,280 @@
1/*
2 * linux/arch/arm/mach-omap1/mcbsp.c
3 *
4 * Copyright (C) 2008 Instituto Nokia de Tecnologia
5 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Multichannel mode not supported.
12 */
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/platform_device.h>
19
20#include <asm/arch/dma.h>
21#include <asm/arch/mux.h>
22#include <asm/arch/cpu.h>
23#include <asm/arch/mcbsp.h>
24#include <asm/arch/dsp_common.h>
25
26#define DPS_RSTCT2_PER_EN (1 << 0)
27#define DSP_RSTCT2_WD_PER_EN (1 << 1)
28
29struct mcbsp_internal_clk {
30 struct clk clk;
31 struct clk **childs;
32 int n_childs;
33};
34
35#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
36static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
37{
38 const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
39 int i;
40
41 mclk->n_childs = ARRAY_SIZE(clk_names);
42 mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
43 GFP_KERNEL);
44
45 for (i = 0; i < mclk->n_childs; i++) {
46 /* We fake a platform device to get correct device id */
47 struct platform_device pdev;
48
49 pdev.dev.bus = &platform_bus_type;
50 pdev.id = mclk->clk.id;
51 mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
52 if (IS_ERR(mclk->childs[i]))
53 printk(KERN_ERR "Could not get clock %s (%d).\n",
54 clk_names[i], mclk->clk.id);
55 }
56}
57
58static int omap_mcbsp_clk_enable(struct clk *clk)
59{
60 struct mcbsp_internal_clk *mclk = container_of(clk,
61 struct mcbsp_internal_clk, clk);
62 int i;
63
64 for (i = 0; i < mclk->n_childs; i++)
65 clk_enable(mclk->childs[i]);
66 return 0;
67}
68
69static void omap_mcbsp_clk_disable(struct clk *clk)
70{
71 struct mcbsp_internal_clk *mclk = container_of(clk,
72 struct mcbsp_internal_clk, clk);
73 int i;
74
75 for (i = 0; i < mclk->n_childs; i++)
76 clk_disable(mclk->childs[i]);
77}
78
79static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
80 {
81 .clk = {
82 .name = "mcbsp_clk",
83 .id = 1,
84 .enable = omap_mcbsp_clk_enable,
85 .disable = omap_mcbsp_clk_disable,
86 },
87 },
88 {
89 .clk = {
90 .name = "mcbsp_clk",
91 .id = 3,
92 .enable = omap_mcbsp_clk_enable,
93 .disable = omap_mcbsp_clk_disable,
94 },
95 },
96};
97
98#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
99#else
100#define omap_mcbsp_clks_size 0
101static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
102static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
103{ }
104#endif
105
106static int omap1_mcbsp_check(unsigned int id)
107{
108 /* REVISIT: Check correctly for number of registered McBSPs */
109 if (cpu_is_omap730()) {
110 if (id > OMAP_MAX_MCBSP_COUNT - 2) {
111 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
112 id + 1);
113 return -ENODEV;
114 }
115 return 0;
116 }
117
118 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
119 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
120 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
121 id + 1);
122 return -ENODEV;
123 }
124 return 0;
125 }
126
127 return -ENODEV;
128}
129
130static void omap1_mcbsp_request(unsigned int id)
131{
132 /*
133 * On 1510, 1610 and 1710, McBSP1 and McBSP3
134 * are DSP public peripherals.
135 */
136 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
137 omap_dsp_request_mem();
138 /*
139 * DSP external peripheral reset
140 * FIXME: This should be moved to dsp code
141 */
142 __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
143 DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
144 }
145}
146
147static void omap1_mcbsp_free(unsigned int id)
148{
149 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
150 omap_dsp_release_mem();
151}
152
153static struct omap_mcbsp_ops omap1_mcbsp_ops = {
154 .check = omap1_mcbsp_check,
155 .request = omap1_mcbsp_request,
156 .free = omap1_mcbsp_free,
157};
158
159#ifdef CONFIG_ARCH_OMAP730
160static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
161 {
162 .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
163 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
164 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
165 .rx_irq = INT_730_McBSP1RX,
166 .tx_irq = INT_730_McBSP1TX,
167 .ops = &omap1_mcbsp_ops,
168 },
169 {
170 .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
171 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
172 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
173 .rx_irq = INT_730_McBSP2RX,
174 .tx_irq = INT_730_McBSP2TX,
175 .ops = &omap1_mcbsp_ops,
176 },
177};
178#define OMAP730_MCBSP_PDATA_SZ ARRAY_SIZE(omap730_mcbsp_pdata)
179#else
180#define omap730_mcbsp_pdata NULL
181#define OMAP730_MCBSP_PDATA_SZ 0
182#endif
183
184#ifdef CONFIG_ARCH_OMAP15XX
185static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
186 {
187 .virt_base = OMAP1510_MCBSP1_BASE,
188 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
189 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
190 .rx_irq = INT_McBSP1RX,
191 .tx_irq = INT_McBSP1TX,
192 .ops = &omap1_mcbsp_ops,
193 .clk_name = "mcbsp_clk",
194 },
195 {
196 .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
197 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
198 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
199 .rx_irq = INT_1510_SPI_RX,
200 .tx_irq = INT_1510_SPI_TX,
201 .ops = &omap1_mcbsp_ops,
202 },
203 {
204 .virt_base = OMAP1510_MCBSP3_BASE,
205 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
206 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
207 .rx_irq = INT_McBSP3RX,
208 .tx_irq = INT_McBSP3TX,
209 .ops = &omap1_mcbsp_ops,
210 .clk_name = "mcbsp_clk",
211 },
212};
213#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata)
214#else
215#define omap15xx_mcbsp_pdata NULL
216#define OMAP15XX_MCBSP_PDATA_SZ 0
217#endif
218
219#ifdef CONFIG_ARCH_OMAP16XX
220static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
221 {
222 .virt_base = OMAP1610_MCBSP1_BASE,
223 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
224 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
225 .rx_irq = INT_McBSP1RX,
226 .tx_irq = INT_McBSP1TX,
227 .ops = &omap1_mcbsp_ops,
228 .clk_name = "mcbsp_clk",
229 },
230 {
231 .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
232 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
233 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
234 .rx_irq = INT_1610_McBSP2_RX,
235 .tx_irq = INT_1610_McBSP2_TX,
236 .ops = &omap1_mcbsp_ops,
237 },
238 {
239 .virt_base = OMAP1610_MCBSP3_BASE,
240 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
241 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
242 .rx_irq = INT_McBSP3RX,
243 .tx_irq = INT_McBSP3TX,
244 .ops = &omap1_mcbsp_ops,
245 .clk_name = "mcbsp_clk",
246 },
247};
248#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata)
249#else
250#define omap16xx_mcbsp_pdata NULL
251#define OMAP16XX_MCBSP_PDATA_SZ 0
252#endif
253
254int __init omap1_mcbsp_init(void)
255{
256 int i;
257
258 for (i = 0; i < omap_mcbsp_clks_size; i++) {
259 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
260 omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
261 clk_register(&omap_mcbsp_clks[i].clk);
262 }
263 }
264
265 if (cpu_is_omap730())
266 omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
267 OMAP730_MCBSP_PDATA_SZ);
268
269 if (cpu_is_omap15xx())
270 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
271 OMAP15XX_MCBSP_PDATA_SZ);
272
273 if (cpu_is_omap16xx())
274 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
275 OMAP16XX_MCBSP_PDATA_SZ);
276
277 return omap_mcbsp_init();
278}
279
280arch_initcall(omap1_mcbsp_init);
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 88081ed13f96..06e1118ddba2 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -1747,7 +1747,8 @@ static struct clk gpt12_fck = {
1747}; 1747};
1748 1748
1749static struct clk mcbsp1_ick = { 1749static struct clk mcbsp1_ick = {
1750 .name = "mcbsp1_ick", 1750 .name = "mcbsp_ick",
1751 .id = 1,
1751 .parent = &l4_ck, 1752 .parent = &l4_ck,
1752 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1753 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1753 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1756,7 +1757,8 @@ static struct clk mcbsp1_ick = {
1756}; 1757};
1757 1758
1758static struct clk mcbsp1_fck = { 1759static struct clk mcbsp1_fck = {
1759 .name = "mcbsp1_fck", 1760 .name = "mcbsp_fck",
1761 .id = 1,
1760 .parent = &func_96m_ck, 1762 .parent = &func_96m_ck,
1761 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1763 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1762 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1764 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1765,7 +1767,8 @@ static struct clk mcbsp1_fck = {
1765}; 1767};
1766 1768
1767static struct clk mcbsp2_ick = { 1769static struct clk mcbsp2_ick = {
1768 .name = "mcbsp2_ick", 1770 .name = "mcbsp_ick",
1771 .id = 2,
1769 .parent = &l4_ck, 1772 .parent = &l4_ck,
1770 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1774 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1774,7 +1777,8 @@ static struct clk mcbsp2_ick = {
1774}; 1777};
1775 1778
1776static struct clk mcbsp2_fck = { 1779static struct clk mcbsp2_fck = {
1777 .name = "mcbsp2_fck", 1780 .name = "mcbsp_fck",
1781 .id = 2,
1778 .parent = &func_96m_ck, 1782 .parent = &func_96m_ck,
1779 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1783 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1783,7 +1787,8 @@ static struct clk mcbsp2_fck = {
1783}; 1787};
1784 1788
1785static struct clk mcbsp3_ick = { 1789static struct clk mcbsp3_ick = {
1786 .name = "mcbsp3_ick", 1790 .name = "mcbsp_ick",
1791 .id = 3,
1787 .parent = &l4_ck, 1792 .parent = &l4_ck,
1788 .flags = CLOCK_IN_OMAP243X, 1793 .flags = CLOCK_IN_OMAP243X,
1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1792,7 +1797,8 @@ static struct clk mcbsp3_ick = {
1792}; 1797};
1793 1798
1794static struct clk mcbsp3_fck = { 1799static struct clk mcbsp3_fck = {
1795 .name = "mcbsp3_fck", 1800 .name = "mcbsp_fck",
1801 .id = 3,
1796 .parent = &func_96m_ck, 1802 .parent = &func_96m_ck,
1797 .flags = CLOCK_IN_OMAP243X, 1803 .flags = CLOCK_IN_OMAP243X,
1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1804 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1801,7 +1807,8 @@ static struct clk mcbsp3_fck = {
1801}; 1807};
1802 1808
1803static struct clk mcbsp4_ick = { 1809static struct clk mcbsp4_ick = {
1804 .name = "mcbsp4_ick", 1810 .name = "mcbsp_ick",
1811 .id = 4,
1805 .parent = &l4_ck, 1812 .parent = &l4_ck,
1806 .flags = CLOCK_IN_OMAP243X, 1813 .flags = CLOCK_IN_OMAP243X,
1807 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1810,7 +1817,8 @@ static struct clk mcbsp4_ick = {
1810}; 1817};
1811 1818
1812static struct clk mcbsp4_fck = { 1819static struct clk mcbsp4_fck = {
1813 .name = "mcbsp4_fck", 1820 .name = "mcbsp_fck",
1821 .id = 4,
1814 .parent = &func_96m_ck, 1822 .parent = &func_96m_ck,
1815 .flags = CLOCK_IN_OMAP243X, 1823 .flags = CLOCK_IN_OMAP243X,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1824 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1819,7 +1827,8 @@ static struct clk mcbsp4_fck = {
1819}; 1827};
1820 1828
1821static struct clk mcbsp5_ick = { 1829static struct clk mcbsp5_ick = {
1822 .name = "mcbsp5_ick", 1830 .name = "mcbsp_ick",
1831 .id = 5,
1823 .parent = &l4_ck, 1832 .parent = &l4_ck,
1824 .flags = CLOCK_IN_OMAP243X, 1833 .flags = CLOCK_IN_OMAP243X,
1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1834 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1828,7 +1837,8 @@ static struct clk mcbsp5_ick = {
1828}; 1837};
1829 1838
1830static struct clk mcbsp5_fck = { 1839static struct clk mcbsp5_fck = {
1831 .name = "mcbsp5_fck", 1840 .name = "mcbsp_fck",
1841 .id = 5,
1832 .parent = &func_96m_ck, 1842 .parent = &func_96m_ck,
1833 .flags = CLOCK_IN_OMAP243X, 1843 .flags = CLOCK_IN_OMAP243X,
1834 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1844 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-03 09:28:38 -0500