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-rw-r--r--drivers/net/igb/e1000_82575.c20
1 files changed, 0 insertions, 20 deletions
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index 0bc990ec4a8e..ea944f518215 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -1446,7 +1446,6 @@ void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1446 **/ 1446 **/
1447static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 1447static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1448{ 1448{
1449 u32 mdicnfg = 0;
1450 s32 ret_val; 1449 s32 ret_val;
1451 1450
1452 1451
@@ -1454,15 +1453,6 @@ static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1454 if (ret_val) 1453 if (ret_val)
1455 goto out; 1454 goto out;
1456 1455
1457 /*
1458 * We config the phy address in MDICNFG register now. Same bits
1459 * as before. The values in MDIC can be written but will be
1460 * ignored. This allows us to call the old function after
1461 * configuring the PHY address in the new register
1462 */
1463 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1464 wr32(E1000_MDICNFG, mdicnfg);
1465
1466 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 1456 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1467 1457
1468 hw->phy.ops.release(hw); 1458 hw->phy.ops.release(hw);
@@ -1481,7 +1471,6 @@ out:
1481 **/ 1471 **/
1482static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 1472static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1483{ 1473{
1484 u32 mdicnfg = 0;
1485 s32 ret_val; 1474 s32 ret_val;
1486 1475
1487 1476
@@ -1489,15 +1478,6 @@ static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1489 if (ret_val) 1478 if (ret_val)
1490 goto out; 1479 goto out;
1491 1480
1492 /*
1493 * We config the phy address in MDICNFG register now. Same bits
1494 * as before. The values in MDIC can be written but will be
1495 * ignored. This allows us to call the old function after
1496 * configuring the PHY address in the new register
1497 */
1498 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1499 wr32(E1000_MDICNFG, mdicnfg);
1500
1501 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 1481 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1502 1482
1503 hw->phy.ops.release(hw); 1483 hw->phy.ops.release(hw);