5 files changed, 101 insertions, 35 deletions

diff --git a/arch/x86/include/asm/system.h b/arch/x86/include/asm/system.h
index 12569e691ce3..c2ff2a1d845e 100644
--- a/arch/x86/include/asm/system.h
+++ b/arch/x86/include/asm/system.h
@@ -303,24 +303,81 @@ static inline void native_wbinvd(void)
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
 #else
-#define read_cr0()      (native_read_cr0())
-#define write_cr0(x)    (native_write_cr0(x))
-#define read_cr2()      (native_read_cr2())
-#define write_cr2(x)    (native_write_cr2(x))
-#define read_cr3()      (native_read_cr3())
-#define write_cr3(x)    (native_write_cr3(x))
-#define read_cr4()      (native_read_cr4())
-#define read_cr4_safe() (native_read_cr4_safe())
-#define write_cr4(x)    (native_write_cr4(x))
-#define wbinvd()        (native_wbinvd())
+
+static inline unsigned long read_cr0(void)
+{
+        return native_read_cr0();
+}
+
+static inline void write_cr0(unsigned long x)
+{
+        native_write_cr0(x);
+}
+
+static inline unsigned long read_cr2(void)
+{
+        return native_read_cr2();
+}
+
+static inline void write_cr2(unsigned long x)
+{
+        native_write_cr2(x);
+}
+
+static inline unsigned long read_cr3(void)
+{
+        return native_read_cr3();
+}
+
+static inline void write_cr3(unsigned long x)
+{
+        native_write_cr3(x);
+}
+
+static inline unsigned long read_cr4(void)
+{
+        return native_read_cr4();
+}
+
+static inline unsigned long read_cr4_safe(void)
+{
+        return native_read_cr4_safe();
+}
+
+static inline void write_cr4(unsigned long x)
+{
+        native_write_cr4(x);
+}
+
+static inline void wbinvd(void)
+{
+        native_wbinvd();
+}
+
 #ifdef CONFIG_X86_64
-#define read_cr8()      (native_read_cr8())
-#define write_cr8(x)    (native_write_cr8(x))
-#define load_gs_index   native_load_gs_index
+
+static inline unsigned long read_cr8(void)
+{
+        return native_read_cr8();
+}
+
+static inline void write_cr8(unsigned long x)
+{
+        native_write_cr8(x);
+}
+
+static inline void load_gs_index(unsigned selector)
+{
+        native_load_gs_index(selector);
+}
+
 #endif
 
 /* Clear the 'TS' bit */
-#define clts()          (native_clts())
+static inline void clts(void)
+{
+        native_clts();
+}
 
 #endif/* CONFIG_PARAVIRT */
 
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index fabf01eff771..ae147126b7b7 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1812,30 +1812,41 @@ void smp_spurious_interrupt(struct pt_regs *regs)
  */
 void smp_error_interrupt(struct pt_regs *regs)
 {
-        u32 v, v1;
+        u32 v0, v1;
+        u32 i = 0;
+        static const char * const error_interrupt_reason[] = {
+                "Send CS error",                /* APIC Error Bit 0 */
+                "Receive CS error",             /* APIC Error Bit 1 */
+                "Send accept error",            /* APIC Error Bit 2 */
+                "Receive accept error",         /* APIC Error Bit 3 */
+                "Redirectable IPI",             /* APIC Error Bit 4 */
+                "Send illegal vector",          /* APIC Error Bit 5 */
+                "Received illegal vector",      /* APIC Error Bit 6 */
+                "Illegal register address",     /* APIC Error Bit 7 */
+        };
 
         exit_idle();
         irq_enter();
         /* First tickle the hardware, only then report what went on. -- REW */
-        v = apic_read(APIC_ESR);
+        v0 = apic_read(APIC_ESR);
         apic_write(APIC_ESR, 0);
         v1 = apic_read(APIC_ESR);
         ack_APIC_irq();
         atomic_inc(&irq_err_count);
 
-        /*
-         * Here is what the APIC error bits mean:
-         * 0: Send CS error
-         * 1: Receive CS error
-         * 2: Send accept error
-         * 3: Receive accept error
-         * 4: Reserved
-         * 5: Send illegal vector
-         * 6: Received illegal vector
-         * 7: Illegal register address
-         */
-        pr_debug("APIC error on CPU%d: %02x(%02x)\n",
-                smp_processor_id(), v , v1);
+        apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
+                    smp_processor_id(), v0 , v1);
+
+        v1 = v1 & 0xff;
+        while (v1) {
+                if (v1 & 0x1)
+                        apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
+                i++;
+                v1 >>= 1;
+        };
+
+        apic_printk(APIC_DEBUG, KERN_CONT "\n");
+
         irq_exit();
 }
 
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 5a532ce646bf..ef59817357fc 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -718,14 +718,12 @@ static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare)
 static int
 check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count)
 {
-        int ret = 0;
-
         if (!mpc_new_phys || count <= mpc_new_length) {
                 WARN(1, "update_mptable: No spare slots (length: %x)\n", count);
                 return -1;
         }
 
-        return ret;
+        return 0;
 }
 #else /* CONFIG_X86_IO_APIC */
 static
diff --git a/arch/x86/lib/memcpy_64.S b/arch/x86/lib/memcpy_64.S
index daab21dae2d1..efbf2a0ecdea 100644
--- a/arch/x86/lib/memcpy_64.S
+++ b/arch/x86/lib/memcpy_64.S
@@ -67,7 +67,7 @@ ENTRY(memcpy)
         jb .Lhandle_tail
 
         /*
-         * We check whether memory false dependece could occur,
+         * We check whether memory false dependence could occur,
          * then jump to corresponding copy mode.
          */
         cmp  %dil, %sil
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
index 275dbc19e2cf..7000e74b3087 100644
--- a/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@ -194,7 +194,7 @@ static unsigned long __init mrst_calibrate_tsc(void)
         return 0;
 }
 
-void __init mrst_time_init(void)
+static void __init mrst_time_init(void)
 {
         sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
         switch (mrst_timer_options) {
@@ -216,7 +216,7 @@ void __init mrst_time_init(void)
         apbt_time_init();
 }
 
-void __cpuinit mrst_arch_setup(void)
+static void __cpuinit mrst_arch_setup(void)
 {
         if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
                 __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;