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-rw-r--r--arch/mips/Kconfig3
-rw-r--r--arch/mips/kernel/Makefile1
-rw-r--r--arch/mips/kernel/irq_txx9.c196
-rw-r--r--include/asm-mips/txx9irq.h30
4 files changed, 230 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2775dd666320..cec0d8411269 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -767,6 +767,9 @@ config IRQ_MSP_SLP
767config IRQ_MSP_CIC 767config IRQ_MSP_CIC
768 bool 768 bool
769 769
770config IRQ_TXX9
771 bool
772
770config MIPS_BOARDS_GEN 773config MIPS_BOARDS_GEN
771 bool 774 bool
772 775
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 07344cb37596..2fd96d95a39c 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
50obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o 50obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
51obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o 51obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
52obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o 52obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o
53obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
53 54
54obj-$(CONFIG_32BIT) += scall32-o32.o 55obj-$(CONFIG_32BIT) += scall32-o32.o
55obj-$(CONFIG_64BIT) += scall64-64.o 56obj-$(CONFIG_64BIT) += scall64-64.o
diff --git a/arch/mips/kernel/irq_txx9.c b/arch/mips/kernel/irq_txx9.c
new file mode 100644
index 000000000000..172e14b461df
--- /dev/null
+++ b/arch/mips/kernel/irq_txx9.c
@@ -0,0 +1,196 @@
1/*
2 * linux/arch/mips/kernel/irq_txx9.c
3 *
4 * Based on linux/arch/mips/jmr3927/rbhma3100/irq.c,
5 * linux/arch/mips/tx4927/common/tx4927_irq.c,
6 * linux/arch/mips/tx4938/common/irq.c
7 *
8 * Copyright 2001, 2003-2005 MontaVista Software Inc.
9 * Author: MontaVista Software, Inc.
10 * ahennessy@mvista.com
11 * source@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
16 * for more details.
17 */
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/types.h>
21#include <asm/txx9irq.h>
22
23struct txx9_irc_reg {
24 u32 cer;
25 u32 cr[2];
26 u32 unused0;
27 u32 ilr[8];
28 u32 unused1[4];
29 u32 imr;
30 u32 unused2[7];
31 u32 scr;
32 u32 unused3[7];
33 u32 ssr;
34 u32 unused4[7];
35 u32 csr;
36};
37
38/* IRCER : Int. Control Enable */
39#define TXx9_IRCER_ICE 0x00000001
40
41/* IRCR : Int. Control */
42#define TXx9_IRCR_LOW 0x00000000
43#define TXx9_IRCR_HIGH 0x00000001
44#define TXx9_IRCR_DOWN 0x00000002
45#define TXx9_IRCR_UP 0x00000003
46#define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002)
47
48/* IRSCR : Int. Status Control */
49#define TXx9_IRSCR_EIClrE 0x00000100
50#define TXx9_IRSCR_EIClr_MASK 0x0000000f
51
52/* IRCSR : Int. Current Status */
53#define TXx9_IRCSR_IF 0x00010000
54#define TXx9_IRCSR_ILV_MASK 0x00000700
55#define TXx9_IRCSR_IVL_MASK 0x0000001f
56
57#define irc_dlevel 0
58#define irc_elevel 1
59
60static struct txx9_irc_reg __iomem *txx9_ircptr __read_mostly;
61
62static struct {
63 unsigned char level;
64 unsigned char mode;
65} txx9irq[TXx9_MAX_IR] __read_mostly;
66
67static void txx9_irq_unmask(unsigned int irq)
68{
69 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
70 u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16 ) / 2];
71 int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
72
73 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
74 | (txx9irq[irq_nr].level << ofs),
75 ilrp);
76#ifdef CONFIG_CPU_TX39XX
77 /* update IRCSR */
78 __raw_writel(0, &txx9_ircptr->imr);
79 __raw_writel(irc_elevel, &txx9_ircptr->imr);
80#endif
81}
82
83static inline void txx9_irq_mask(unsigned int irq)
84{
85 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
86 u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16) / 2];
87 int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
88
89 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
90 | (irc_dlevel << ofs),
91 ilrp);
92#ifdef CONFIG_CPU_TX39XX
93 /* update IRCSR */
94 __raw_writel(0, &txx9_ircptr->imr);
95 __raw_writel(irc_elevel, &txx9_ircptr->imr);
96 /* flush write buffer */
97 __raw_readl(&txx9_ircptr->ssr);
98#else
99 mmiowb();
100#endif
101}
102
103static void txx9_irq_mask_ack(unsigned int irq)
104{
105 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
106
107 txx9_irq_mask(irq);
108 if (TXx9_IRCR_EDGE(txx9irq[irq_nr].mode)) {
109 /* clear edge detection */
110 u32 cr = __raw_readl(&txx9_ircptr->cr[irq_nr / 8]);
111 cr = (cr >> ((irq_nr & (8 - 1)) * 2)) & 3;
112 __raw_writel(TXx9_IRSCR_EIClrE | irq_nr,
113 &txx9_ircptr->scr);
114 }
115}
116
117static int txx9_irq_set_type(unsigned int irq, unsigned int flow_type)
118{
119 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
120 u32 cr;
121 u32 __iomem *crp;
122 int ofs;
123 int mode;
124
125 if (flow_type & IRQF_TRIGGER_PROBE)
126 return 0;
127 switch (flow_type & IRQF_TRIGGER_MASK) {
128 case IRQF_TRIGGER_RISING: mode = TXx9_IRCR_UP; break;
129 case IRQF_TRIGGER_FALLING: mode = TXx9_IRCR_DOWN; break;
130 case IRQF_TRIGGER_HIGH: mode = TXx9_IRCR_HIGH; break;
131 case IRQF_TRIGGER_LOW: mode = TXx9_IRCR_LOW; break;
132 default:
133 return -EINVAL;
134 }
135 crp = &txx9_ircptr->cr[(unsigned int)irq_nr / 8];
136 cr = __raw_readl(crp);
137 ofs = (irq_nr & (8 - 1)) * 2;
138 cr &= ~(0x3 << ofs);
139 cr |= (mode & 0x3) << ofs;
140 __raw_writel(cr, crp);
141 txx9irq[irq_nr].mode = mode;
142 return 0;
143}
144
145static struct irq_chip txx9_irq_chip = {
146 .name = "TXX9",
147 .ack = txx9_irq_mask_ack,
148 .mask = txx9_irq_mask,
149 .mask_ack = txx9_irq_mask_ack,
150 .unmask = txx9_irq_unmask,
151 .set_type = txx9_irq_set_type,
152};
153
154void __init txx9_irq_init(unsigned long baseaddr)
155{
156 int i;
157
158 txx9_ircptr = ioremap(baseaddr, sizeof(struct txx9_irc_reg));
159 for (i = 0; i < TXx9_MAX_IR; i++) {
160 txx9irq[i].level = 4; /* middle level */
161 txx9irq[i].mode = TXx9_IRCR_LOW;
162 set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
163 &txx9_irq_chip, handle_level_irq);
164 }
165
166 /* mask all IRC interrupts */
167 __raw_writel(0, &txx9_ircptr->imr);
168 for (i = 0; i < 8; i++)
169 __raw_writel(0, &txx9_ircptr->ilr[i]);
170 /* setup IRC interrupt mode (Low Active) */
171 for (i = 0; i < 2; i++)
172 __raw_writel(0, &txx9_ircptr->cr[i]);
173 /* enable interrupt control */
174 __raw_writel(TXx9_IRCER_ICE, &txx9_ircptr->cer);
175 __raw_writel(irc_elevel, &txx9_ircptr->imr);
176}
177
178int __init txx9_irq_set_pri(int irc_irq, int new_pri)
179{
180 int old_pri;
181
182 if ((unsigned int)irc_irq >= TXx9_MAX_IR)
183 return 0;
184 old_pri = txx9irq[irc_irq].level;
185 txx9irq[irc_irq].level = new_pri;
186 return old_pri;
187}
188
189int txx9_irq(void)
190{
191 u32 csr = __raw_readl(&txx9_ircptr->csr);
192
193 if (likely(!(csr & TXx9_IRCSR_IF)))
194 return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1));
195 return -1;
196}
diff --git a/include/asm-mips/txx9irq.h b/include/asm-mips/txx9irq.h
new file mode 100644
index 000000000000..1c439e51b875
--- /dev/null
+++ b/include/asm-mips/txx9irq.h
@@ -0,0 +1,30 @@
1/*
2 * include/asm-mips/txx9irq.h
3 * TX39/TX49 interrupt controller definitions.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#ifndef __ASM_TXX9IRQ_H
10#define __ASM_TXX9IRQ_H
11
12#include <irq.h>
13
14#ifdef CONFIG_IRQ_CPU
15#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
16#else
17#define TXX9_IRQ_BASE 0
18#endif
19
20#ifdef CONFIG_CPU_TX39XX
21#define TXx9_MAX_IR 16
22#else
23#define TXx9_MAX_IR 32
24#endif
25
26void txx9_irq_init(unsigned long baseaddr);
27int txx9_irq(void);
28int txx9_irq_set_pri(int irc_irq, int new_pri);
29
30#endif /* __ASM_TXX9IRQ_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 13:21:42 -0500