diff options
-rw-r--r-- | drivers/net/b44.c | 64 | ||||
-rw-r--r-- | drivers/net/bnx2.c | 2 | ||||
-rw-r--r-- | drivers/net/hydra.h | 177 | ||||
-rw-r--r-- | drivers/net/ixgb/ixgb_main.c | 13 | ||||
-rw-r--r-- | drivers/net/mv643xx_eth.c | 19 | ||||
-rw-r--r-- | drivers/net/natsemi.c | 2 | ||||
-rw-r--r-- | drivers/net/pcmcia/axnet_cs.c | 2 | ||||
-rw-r--r-- | drivers/net/skge.c | 2 | ||||
-rw-r--r-- | drivers/net/sky2.c | 6 | ||||
-rw-r--r-- | drivers/net/sky2.h | 2 | ||||
-rw-r--r-- | drivers/net/starfire.c | 2 | ||||
-rw-r--r-- | drivers/net/typhoon.c | 2 | ||||
-rw-r--r-- | drivers/net/via-rhine.c | 7 |
13 files changed, 67 insertions, 233 deletions
diff --git a/drivers/net/b44.c b/drivers/net/b44.c index c4e12b5cbb92..3d306681919e 100644 --- a/drivers/net/b44.c +++ b/drivers/net/b44.c | |||
@@ -2,6 +2,7 @@ | |||
2 | * | 2 | * |
3 | * Copyright (C) 2002 David S. Miller (davem@redhat.com) | 3 | * Copyright (C) 2002 David S. Miller (davem@redhat.com) |
4 | * Fixed by Pekka Pietikainen (pp@ee.oulu.fi) | 4 | * Fixed by Pekka Pietikainen (pp@ee.oulu.fi) |
5 | * Copyright (C) 2006 Broadcom Corporation. | ||
5 | * | 6 | * |
6 | * Distribute under GPL. | 7 | * Distribute under GPL. |
7 | */ | 8 | */ |
@@ -28,8 +29,8 @@ | |||
28 | 29 | ||
29 | #define DRV_MODULE_NAME "b44" | 30 | #define DRV_MODULE_NAME "b44" |
30 | #define PFX DRV_MODULE_NAME ": " | 31 | #define PFX DRV_MODULE_NAME ": " |
31 | #define DRV_MODULE_VERSION "0.97" | 32 | #define DRV_MODULE_VERSION "1.00" |
32 | #define DRV_MODULE_RELDATE "Nov 30, 2005" | 33 | #define DRV_MODULE_RELDATE "Apr 7, 2006" |
33 | 34 | ||
34 | #define B44_DEF_MSG_ENABLE \ | 35 | #define B44_DEF_MSG_ENABLE \ |
35 | (NETIF_MSG_DRV | \ | 36 | (NETIF_MSG_DRV | \ |
@@ -136,7 +137,7 @@ static inline unsigned long br32(const struct b44 *bp, unsigned long reg) | |||
136 | return readl(bp->regs + reg); | 137 | return readl(bp->regs + reg); |
137 | } | 138 | } |
138 | 139 | ||
139 | static inline void bw32(const struct b44 *bp, | 140 | static inline void bw32(const struct b44 *bp, |
140 | unsigned long reg, unsigned long val) | 141 | unsigned long reg, unsigned long val) |
141 | { | 142 | { |
142 | writel(val, bp->regs + reg); | 143 | writel(val, bp->regs + reg); |
@@ -286,13 +287,13 @@ static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index) | |||
286 | val |= ((u32) data[4]) << 8; | 287 | val |= ((u32) data[4]) << 8; |
287 | val |= ((u32) data[5]) << 0; | 288 | val |= ((u32) data[5]) << 0; |
288 | bw32(bp, B44_CAM_DATA_LO, val); | 289 | bw32(bp, B44_CAM_DATA_LO, val); |
289 | val = (CAM_DATA_HI_VALID | | 290 | val = (CAM_DATA_HI_VALID | |
290 | (((u32) data[0]) << 8) | | 291 | (((u32) data[0]) << 8) | |
291 | (((u32) data[1]) << 0)); | 292 | (((u32) data[1]) << 0)); |
292 | bw32(bp, B44_CAM_DATA_HI, val); | 293 | bw32(bp, B44_CAM_DATA_HI, val); |
293 | bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE | | 294 | bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE | |
294 | (index << CAM_CTRL_INDEX_SHIFT))); | 295 | (index << CAM_CTRL_INDEX_SHIFT))); |
295 | b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1); | 296 | b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1); |
296 | } | 297 | } |
297 | 298 | ||
298 | static inline void __b44_disable_ints(struct b44 *bp) | 299 | static inline void __b44_disable_ints(struct b44 *bp) |
@@ -410,25 +411,18 @@ static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags) | |||
410 | 411 | ||
411 | static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote) | 412 | static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote) |
412 | { | 413 | { |
413 | u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE | | 414 | u32 pause_enab = 0; |
414 | B44_FLAG_RX_PAUSE); | ||
415 | 415 | ||
416 | if (local & ADVERTISE_PAUSE_CAP) { | 416 | /* The driver supports only rx pause by default because |
417 | if (local & ADVERTISE_PAUSE_ASYM) { | 417 | the b44 mac tx pause mechanism generates excessive |
418 | if (remote & LPA_PAUSE_CAP) | 418 | pause frames. |
419 | pause_enab |= (B44_FLAG_TX_PAUSE | | 419 | Use ethtool to turn on b44 tx pause if necessary. |
420 | B44_FLAG_RX_PAUSE); | 420 | */ |
421 | else if (remote & LPA_PAUSE_ASYM) | 421 | if ((local & ADVERTISE_PAUSE_CAP) && |
422 | pause_enab |= B44_FLAG_RX_PAUSE; | 422 | (local & ADVERTISE_PAUSE_ASYM)){ |
423 | } else { | 423 | if ((remote & LPA_PAUSE_ASYM) && |
424 | if (remote & LPA_PAUSE_CAP) | 424 | !(remote & LPA_PAUSE_CAP)) |
425 | pause_enab |= (B44_FLAG_TX_PAUSE | | 425 | pause_enab |= B44_FLAG_RX_PAUSE; |
426 | B44_FLAG_RX_PAUSE); | ||
427 | } | ||
428 | } else if (local & ADVERTISE_PAUSE_ASYM) { | ||
429 | if ((remote & LPA_PAUSE_CAP) && | ||
430 | (remote & LPA_PAUSE_ASYM)) | ||
431 | pause_enab |= B44_FLAG_TX_PAUSE; | ||
432 | } | 426 | } |
433 | 427 | ||
434 | __b44_set_flow_ctrl(bp, pause_enab); | 428 | __b44_set_flow_ctrl(bp, pause_enab); |
@@ -1063,7 +1057,7 @@ static int b44_change_mtu(struct net_device *dev, int new_mtu) | |||
1063 | spin_unlock_irq(&bp->lock); | 1057 | spin_unlock_irq(&bp->lock); |
1064 | 1058 | ||
1065 | b44_enable_ints(bp); | 1059 | b44_enable_ints(bp); |
1066 | 1060 | ||
1067 | return 0; | 1061 | return 0; |
1068 | } | 1062 | } |
1069 | 1063 | ||
@@ -1381,7 +1375,7 @@ static void b44_init_hw(struct b44 *bp) | |||
1381 | bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset); | 1375 | bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset); |
1382 | 1376 | ||
1383 | bw32(bp, B44_DMARX_PTR, bp->rx_pending); | 1377 | bw32(bp, B44_DMARX_PTR, bp->rx_pending); |
1384 | bp->rx_prod = bp->rx_pending; | 1378 | bp->rx_prod = bp->rx_pending; |
1385 | 1379 | ||
1386 | bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ); | 1380 | bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ); |
1387 | 1381 | ||
@@ -1553,9 +1547,9 @@ static void __b44_set_rx_mode(struct net_device *dev) | |||
1553 | val |= RXCONFIG_ALLMULTI; | 1547 | val |= RXCONFIG_ALLMULTI; |
1554 | else | 1548 | else |
1555 | i = __b44_load_mcast(bp, dev); | 1549 | i = __b44_load_mcast(bp, dev); |
1556 | 1550 | ||
1557 | for (; i < 64; i++) { | 1551 | for (; i < 64; i++) { |
1558 | __b44_cam_write(bp, zero, i); | 1552 | __b44_cam_write(bp, zero, i); |
1559 | } | 1553 | } |
1560 | bw32(bp, B44_RXCONFIG, val); | 1554 | bw32(bp, B44_RXCONFIG, val); |
1561 | val = br32(bp, B44_CAM_CTRL); | 1555 | val = br32(bp, B44_CAM_CTRL); |
@@ -1737,7 +1731,7 @@ static int b44_set_ringparam(struct net_device *dev, | |||
1737 | spin_unlock_irq(&bp->lock); | 1731 | spin_unlock_irq(&bp->lock); |
1738 | 1732 | ||
1739 | b44_enable_ints(bp); | 1733 | b44_enable_ints(bp); |
1740 | 1734 | ||
1741 | return 0; | 1735 | return 0; |
1742 | } | 1736 | } |
1743 | 1737 | ||
@@ -1782,7 +1776,7 @@ static int b44_set_pauseparam(struct net_device *dev, | |||
1782 | spin_unlock_irq(&bp->lock); | 1776 | spin_unlock_irq(&bp->lock); |
1783 | 1777 | ||
1784 | b44_enable_ints(bp); | 1778 | b44_enable_ints(bp); |
1785 | 1779 | ||
1786 | return 0; | 1780 | return 0; |
1787 | } | 1781 | } |
1788 | 1782 | ||
@@ -1898,7 +1892,7 @@ static int __devinit b44_get_invariants(struct b44 *bp) | |||
1898 | bp->core_unit = ssb_core_unit(bp); | 1892 | bp->core_unit = ssb_core_unit(bp); |
1899 | bp->dma_offset = SB_PCI_DMA; | 1893 | bp->dma_offset = SB_PCI_DMA; |
1900 | 1894 | ||
1901 | /* XXX - really required? | 1895 | /* XXX - really required? |
1902 | bp->flags |= B44_FLAG_BUGGY_TXPTR; | 1896 | bp->flags |= B44_FLAG_BUGGY_TXPTR; |
1903 | */ | 1897 | */ |
1904 | out: | 1898 | out: |
@@ -1946,7 +1940,7 @@ static int __devinit b44_init_one(struct pci_dev *pdev, | |||
1946 | "aborting.\n"); | 1940 | "aborting.\n"); |
1947 | goto err_out_free_res; | 1941 | goto err_out_free_res; |
1948 | } | 1942 | } |
1949 | 1943 | ||
1950 | err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK); | 1944 | err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK); |
1951 | if (err) { | 1945 | if (err) { |
1952 | printk(KERN_ERR PFX "No usable DMA configuration, " | 1946 | printk(KERN_ERR PFX "No usable DMA configuration, " |
@@ -2041,9 +2035,9 @@ static int __devinit b44_init_one(struct pci_dev *pdev, | |||
2041 | 2035 | ||
2042 | pci_save_state(bp->pdev); | 2036 | pci_save_state(bp->pdev); |
2043 | 2037 | ||
2044 | /* Chip reset provides power to the b44 MAC & PCI cores, which | 2038 | /* Chip reset provides power to the b44 MAC & PCI cores, which |
2045 | * is necessary for MAC register access. | 2039 | * is necessary for MAC register access. |
2046 | */ | 2040 | */ |
2047 | b44_chip_reset(bp); | 2041 | b44_chip_reset(bp); |
2048 | 2042 | ||
2049 | printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name); | 2043 | printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name); |
@@ -2091,10 +2085,10 @@ static int b44_suspend(struct pci_dev *pdev, pm_message_t state) | |||
2091 | 2085 | ||
2092 | del_timer_sync(&bp->timer); | 2086 | del_timer_sync(&bp->timer); |
2093 | 2087 | ||
2094 | spin_lock_irq(&bp->lock); | 2088 | spin_lock_irq(&bp->lock); |
2095 | 2089 | ||
2096 | b44_halt(bp); | 2090 | b44_halt(bp); |
2097 | netif_carrier_off(bp->dev); | 2091 | netif_carrier_off(bp->dev); |
2098 | netif_device_detach(bp->dev); | 2092 | netif_device_detach(bp->dev); |
2099 | b44_free_rings(bp); | 2093 | b44_free_rings(bp); |
2100 | 2094 | ||
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 2671da20a496..5ca99e26660a 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c | |||
@@ -63,7 +63,7 @@ | |||
63 | /* Time in jiffies before concluding the transmitter is hung. */ | 63 | /* Time in jiffies before concluding the transmitter is hung. */ |
64 | #define TX_TIMEOUT (5*HZ) | 64 | #define TX_TIMEOUT (5*HZ) |
65 | 65 | ||
66 | static char version[] __devinitdata = | 66 | static const char version[] __devinitdata = |
67 | "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | 67 | "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
68 | 68 | ||
69 | MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); | 69 | MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); |
diff --git a/drivers/net/hydra.h b/drivers/net/hydra.h deleted file mode 100644 index 37414146258d..000000000000 --- a/drivers/net/hydra.h +++ /dev/null | |||
@@ -1,177 +0,0 @@ | |||
1 | /* $Linux: hydra.h,v 1.0 1994/10/26 02:03:47 cgd Exp $ */ | ||
2 | |||
3 | /* | ||
4 | * Copyright (c) 1994 Timo Rossi | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * Redistribution and use in source and binary forms, with or without | ||
8 | * modification, are permitted provided that the following conditions | ||
9 | * are met: | ||
10 | * 1. Redistributions of source code must retain the above copyright | ||
11 | * notice, this list of conditions and the following disclaimer. | ||
12 | * 2. Redistributions in binary form must reproduce the above copyright | ||
13 | * notice, this list of conditions and the following disclaimer in the | ||
14 | * documentation and/or other materials provided with the distribution. | ||
15 | * 3. All advertising materials mentioning features or use of this software | ||
16 | * must display the following acknowledgement: | ||
17 | * This product includes software developed by Timo Rossi | ||
18 | * 4. The name of the author may not be used to endorse or promote products | ||
19 | * derived from this software without specific prior written permission | ||
20 | * | ||
21 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | ||
22 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | ||
23 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | ||
24 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
26 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
30 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
31 | */ | ||
32 | |||
33 | /* | ||
34 | * The Hydra Systems card uses the National Semiconductor | ||
35 | * 8390 NIC (Network Interface Controller) chip, located | ||
36 | * at card base address + 0xffe1. NIC registers are accessible | ||
37 | * only at odd byte addresses, so the register offsets must | ||
38 | * be multiplied by two. | ||
39 | * | ||
40 | * Card address PROM is located at card base + 0xffc0 (even byte addresses) | ||
41 | * | ||
42 | * RAM starts at the card base address, and is 16K or 64K. | ||
43 | * The current Amiga NetBSD hydra driver is hardwired for 16K. | ||
44 | * It seems that the RAM should be accessed as words or longwords only. | ||
45 | * | ||
46 | */ | ||
47 | |||
48 | /* adapted for Linux by Topi Kanerva 03/29/95 | ||
49 | with original author's permission */ | ||
50 | |||
51 | #define HYDRA_NIC_BASE 0xffe1 | ||
52 | |||
53 | /* Page0 registers */ | ||
54 | |||
55 | #define NIC_CR 0 /* Command register */ | ||
56 | #define NIC_PSTART (1*2) /* Page start (write) */ | ||
57 | #define NIC_PSTOP (2*2) /* Page stop (write) */ | ||
58 | #define NIC_BNDRY (3*2) /* Boundary pointer */ | ||
59 | #define NIC_TSR (4*2) /* Transmit status (read) */ | ||
60 | #define NIC_TPSR (4*2) /* Transmit page start (write) */ | ||
61 | #define NIC_NCR (5*2) /* Number of collisions, read */ | ||
62 | #define NIC_TBCR0 (5*2) /* Transmit byte count low (write) */ | ||
63 | #define NIC_FIFO (6*2) /* FIFO reg. (read) */ | ||
64 | #define NIC_TBCR1 (6*2) /* Transmit byte count high (write) */ | ||
65 | #define NIC_ISR (7*2) /* Interrupt status register */ | ||
66 | #define NIC_RBCR0 (0xa*2) /* Remote byte count low (write) */ | ||
67 | #define NIC_RBCR1 (0xb*2) /* Remote byte count high (write) */ | ||
68 | #define NIC_RSR (0xc*2) /* Receive status (read) */ | ||
69 | #define NIC_RCR (0xc*2) /* Receive config (write) */ | ||
70 | #define NIC_CNTR0 (0xd*2) /* Frame alignment error count (read) */ | ||
71 | #define NIC_TCR (0xd*2) /* Transmit config (write) */ | ||
72 | #define NIC_CNTR1 (0xe*2) /* CRC error counter (read) */ | ||
73 | #define NIC_DCR (0xe*2) /* Data config (write) */ | ||
74 | #define NIC_CNTR2 (0xf*2) /* missed packet counter (read) */ | ||
75 | #define NIC_IMR (0xf*2) /* Interrupt mask reg. (write) */ | ||
76 | |||
77 | /* Page1 registers */ | ||
78 | |||
79 | #define NIC_PAR0 (1*2) /* Physical address */ | ||
80 | #define NIC_PAR1 (2*2) | ||
81 | #define NIC_PAR2 (3*2) | ||
82 | #define NIC_PAR3 (4*2) | ||
83 | #define NIC_PAR4 (5*2) | ||
84 | #define NIC_PAR5 (6*2) | ||
85 | #define NIC_CURR (7*2) /* Current RX ring-buffer page */ | ||
86 | #define NIC_MAR0 (8*2) /* Multicast address */ | ||
87 | #define NIC_MAR1 (9*2) | ||
88 | #define NIC_MAR2 (0xa*2) | ||
89 | #define NIC_MAR3 (0xb*2) | ||
90 | #define NIC_MAR4 (0xc*2) | ||
91 | #define NIC_MAR5 (0xd*2) | ||
92 | #define NIC_MAR6 (0xe*2) | ||
93 | #define NIC_MAR7 (0xf*2) | ||
94 | |||
95 | /* Command register definitions */ | ||
96 | |||
97 | #define CR_STOP 0x01 /* Stop -- software reset command */ | ||
98 | #define CR_START 0x02 /* Start */ | ||
99 | #define CR_TXP 0x04 /* Transmit packet */ | ||
100 | |||
101 | #define CR_RD0 0x08 /* Remote DMA cmd */ | ||
102 | #define CR_RD1 0x10 | ||
103 | #define CR_RD2 0x20 | ||
104 | |||
105 | #define CR_NODMA CR_RD2 | ||
106 | |||
107 | #define CR_PS0 0x40 /* Page select */ | ||
108 | #define CR_PS1 0x80 | ||
109 | |||
110 | #define CR_PAGE0 0 | ||
111 | #define CR_PAGE1 CR_PS0 | ||
112 | #define CR_PAGE2 CR_PS1 | ||
113 | |||
114 | /* Interrupt status reg. definitions */ | ||
115 | |||
116 | #define ISR_PRX 0x01 /* Packet received without errors */ | ||
117 | #define ISR_PTX 0x02 /* Packet transmitted without errors */ | ||
118 | #define ISR_RXE 0x04 /* Receive error */ | ||
119 | #define ISR_TXE 0x08 /* Transmit error */ | ||
120 | #define ISR_OVW 0x10 /* Ring buffer overrun */ | ||
121 | #define ISR_CNT 0x20 /* Counter overflow */ | ||
122 | #define ISR_RDC 0x40 /* Remote DMA compile */ | ||
123 | #define ISR_RST 0x80 /* Reset status */ | ||
124 | |||
125 | /* Data config reg. definitions */ | ||
126 | |||
127 | #define DCR_WTS 0x01 /* Word transfer select */ | ||
128 | #define DCR_BOS 0x02 /* Byte order select */ | ||
129 | #define DCR_LAS 0x04 /* Long address select */ | ||
130 | #define DCR_LS 0x08 /* Loopback select */ | ||
131 | #define DCR_AR 0x10 /* Auto-init remote */ | ||
132 | #define DCR_FT0 0x20 /* FIFO threshold select */ | ||
133 | #define DCR_FT1 0x40 | ||
134 | |||
135 | /* Transmit config reg. definitions */ | ||
136 | |||
137 | #define TCR_CRC 0x01 /* Inhibit CRC */ | ||
138 | #define TCR_LB0 0x02 /* Loopback control */ | ||
139 | #define TCR_LB1 0x04 | ||
140 | #define TCR_ATD 0x08 /* Auto transmit disable */ | ||
141 | #define TCR_OFST 0x10 /* Collision offset enable */ | ||
142 | |||
143 | /* Transmit status reg. definitions */ | ||
144 | |||
145 | #define TSR_PTX 0x01 /* Packet transmitted */ | ||
146 | #define TSR_COL 0x04 /* Transmit collided */ | ||
147 | #define TSR_ABT 0x08 /* Transmit aborted */ | ||
148 | #define TSR_CRS 0x10 /* Carrier sense lost */ | ||
149 | #define TSR_FU 0x20 /* FIFO underrun */ | ||
150 | #define TSR_CDH 0x40 /* CD Heartbeat */ | ||
151 | #define TSR_OWC 0x80 /* Out of Window Collision */ | ||
152 | |||
153 | /* Receiver config register definitions */ | ||
154 | |||
155 | #define RCR_SEP 0x01 /* Save errored packets */ | ||
156 | #define RCR_AR 0x02 /* Accept runt packets */ | ||
157 | #define RCR_AB 0x04 /* Accept broadcast */ | ||
158 | #define RCR_AM 0x08 /* Accept multicast */ | ||
159 | #define RCR_PRO 0x10 /* Promiscuous mode */ | ||
160 | #define RCR_MON 0x20 /* Monitor mode */ | ||
161 | |||
162 | /* Receiver status register definitions */ | ||
163 | |||
164 | #define RSR_PRX 0x01 /* Packet received without error */ | ||
165 | #define RSR_CRC 0x02 /* CRC error */ | ||
166 | #define RSR_FAE 0x04 /* Frame alignment error */ | ||
167 | #define RSR_FO 0x08 /* FIFO overrun */ | ||
168 | #define RSR_MPA 0x10 /* Missed packet */ | ||
169 | #define RSR_PHY 0x20 /* Physical address */ | ||
170 | #define RSR_DIS 0x40 /* Received disabled */ | ||
171 | #define RSR_DFR 0x80 /* Deferring (jabber) */ | ||
172 | |||
173 | /* Hydra System card address PROM offset */ | ||
174 | |||
175 | #define HYDRA_ADDRPROM 0xffc0 | ||
176 | |||
177 | |||
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c index f9f77e4f5965..cfd67d812f0d 100644 --- a/drivers/net/ixgb/ixgb_main.c +++ b/drivers/net/ixgb/ixgb_main.c | |||
@@ -357,18 +357,20 @@ ixgb_probe(struct pci_dev *pdev, | |||
357 | if((err = pci_enable_device(pdev))) | 357 | if((err = pci_enable_device(pdev))) |
358 | return err; | 358 | return err; |
359 | 359 | ||
360 | if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { | 360 | if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) && |
361 | !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) { | ||
361 | pci_using_dac = 1; | 362 | pci_using_dac = 1; |
362 | } else { | 363 | } else { |
363 | if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) { | 364 | if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) || |
365 | (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) { | ||
364 | IXGB_ERR("No usable DMA configuration, aborting\n"); | 366 | IXGB_ERR("No usable DMA configuration, aborting\n"); |
365 | return err; | 367 | goto err_dma_mask; |
366 | } | 368 | } |
367 | pci_using_dac = 0; | 369 | pci_using_dac = 0; |
368 | } | 370 | } |
369 | 371 | ||
370 | if((err = pci_request_regions(pdev, ixgb_driver_name))) | 372 | if((err = pci_request_regions(pdev, ixgb_driver_name))) |
371 | return err; | 373 | goto err_request_regions; |
372 | 374 | ||
373 | pci_set_master(pdev); | 375 | pci_set_master(pdev); |
374 | 376 | ||
@@ -502,6 +504,9 @@ err_ioremap: | |||
502 | free_netdev(netdev); | 504 | free_netdev(netdev); |
503 | err_alloc_etherdev: | 505 | err_alloc_etherdev: |
504 | pci_release_regions(pdev); | 506 | pci_release_regions(pdev); |
507 | err_request_regions: | ||
508 | err_dma_mask: | ||
509 | pci_disable_device(pdev); | ||
505 | return err; | 510 | return err; |
506 | } | 511 | } |
507 | 512 | ||
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index 9f2661355a4a..ea62a3e7d586 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c | |||
@@ -281,10 +281,16 @@ static void mv643xx_eth_tx_timeout_task(struct net_device *dev) | |||
281 | { | 281 | { |
282 | struct mv643xx_private *mp = netdev_priv(dev); | 282 | struct mv643xx_private *mp = netdev_priv(dev); |
283 | 283 | ||
284 | netif_device_detach(dev); | 284 | if (!netif_running(dev)) |
285 | return; | ||
286 | |||
287 | netif_stop_queue(dev); | ||
288 | |||
285 | eth_port_reset(mp->port_num); | 289 | eth_port_reset(mp->port_num); |
286 | eth_port_start(dev); | 290 | eth_port_start(dev); |
287 | netif_device_attach(dev); | 291 | |
292 | if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | ||
293 | netif_wake_queue(dev); | ||
288 | } | 294 | } |
289 | 295 | ||
290 | /** | 296 | /** |
@@ -552,9 +558,9 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id, | |||
552 | #else | 558 | #else |
553 | if (eth_int_cause & ETH_INT_CAUSE_RX) | 559 | if (eth_int_cause & ETH_INT_CAUSE_RX) |
554 | mv643xx_eth_receive_queue(dev, INT_MAX); | 560 | mv643xx_eth_receive_queue(dev, INT_MAX); |
561 | #endif | ||
555 | if (eth_int_cause_ext & ETH_INT_CAUSE_TX) | 562 | if (eth_int_cause_ext & ETH_INT_CAUSE_TX) |
556 | mv643xx_eth_free_completed_tx_descs(dev); | 563 | mv643xx_eth_free_completed_tx_descs(dev); |
557 | #endif | ||
558 | 564 | ||
559 | /* | 565 | /* |
560 | * If no real interrupt occured, exit. | 566 | * If no real interrupt occured, exit. |
@@ -1186,7 +1192,12 @@ static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
1186 | 1192 | ||
1187 | BUG_ON(netif_queue_stopped(dev)); | 1193 | BUG_ON(netif_queue_stopped(dev)); |
1188 | BUG_ON(skb == NULL); | 1194 | BUG_ON(skb == NULL); |
1189 | BUG_ON(mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB); | 1195 | |
1196 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { | ||
1197 | printk(KERN_ERR "%s: transmit with queue full\n", dev->name); | ||
1198 | netif_stop_queue(dev); | ||
1199 | return 1; | ||
1200 | } | ||
1190 | 1201 | ||
1191 | if (has_tiny_unaligned_frags(skb)) { | 1202 | if (has_tiny_unaligned_frags(skb)) { |
1192 | if ((skb_linearize(skb, GFP_ATOMIC) != 0)) { | 1203 | if ((skb_linearize(skb, GFP_ATOMIC) != 0)) { |
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c index 7826afbb9db9..90627756d6fa 100644 --- a/drivers/net/natsemi.c +++ b/drivers/net/natsemi.c | |||
@@ -238,7 +238,7 @@ static int full_duplex[MAX_UNITS]; | |||
238 | #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */ | 238 | #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */ |
239 | 239 | ||
240 | /* These identify the driver base version and may not be removed. */ | 240 | /* These identify the driver base version and may not be removed. */ |
241 | static char version[] __devinitdata = | 241 | static const char version[] __devinitdata = |
242 | KERN_INFO DRV_NAME " dp8381x driver, version " | 242 | KERN_INFO DRV_NAME " dp8381x driver, version " |
243 | DRV_VERSION ", " DRV_RELDATE "\n" | 243 | DRV_VERSION ", " DRV_RELDATE "\n" |
244 | KERN_INFO " originally by Donald Becker <becker@scyld.com>\n" | 244 | KERN_INFO " originally by Donald Becker <becker@scyld.com>\n" |
diff --git a/drivers/net/pcmcia/axnet_cs.c b/drivers/net/pcmcia/axnet_cs.c index 56233afcb2b3..448a09488529 100644 --- a/drivers/net/pcmcia/axnet_cs.c +++ b/drivers/net/pcmcia/axnet_cs.c | |||
@@ -1560,7 +1560,7 @@ static void ei_receive(struct net_device *dev) | |||
1560 | 1560 | ||
1561 | static void ei_rx_overrun(struct net_device *dev) | 1561 | static void ei_rx_overrun(struct net_device *dev) |
1562 | { | 1562 | { |
1563 | axnet_dev_t *info = (axnet_dev_t *)dev; | 1563 | axnet_dev_t *info = PRIV(dev); |
1564 | long e8390_base = dev->base_addr; | 1564 | long e8390_base = dev->base_addr; |
1565 | unsigned char was_txing, must_resend = 0; | 1565 | unsigned char was_txing, must_resend = 0; |
1566 | struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev); | 1566 | struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev); |
diff --git a/drivers/net/skge.c b/drivers/net/skge.c index 35dbf05c7f06..a70c2b0cc104 100644 --- a/drivers/net/skge.c +++ b/drivers/net/skge.c | |||
@@ -78,6 +78,8 @@ static const struct pci_device_id skge_id_table[] = { | |||
78 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) }, | 78 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) }, |
79 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) }, | 79 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) }, |
80 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), }, | 80 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), }, |
81 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, | ||
82 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, | ||
81 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, | 83 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, |
82 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */ | 84 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */ |
83 | { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) }, | 85 | { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) }, |
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index 68f9c206a620..67b0eab16589 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c | |||
@@ -99,8 +99,6 @@ MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |||
99 | static const struct pci_device_id sky2_id_table[] = { | 99 | static const struct pci_device_id sky2_id_table[] = { |
100 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, | 100 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, |
101 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, | 101 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, |
102 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, | ||
103 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, | ||
104 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, | 102 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, |
105 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, | 103 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, |
106 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, | 104 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, |
@@ -579,8 +577,8 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port) | |||
579 | reg = gma_read16(hw, port, GM_PHY_ADDR); | 577 | reg = gma_read16(hw, port, GM_PHY_ADDR); |
580 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | 578 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); |
581 | 579 | ||
582 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | 580 | for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) |
583 | gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i); | 581 | gma_read16(hw, port, i); |
584 | gma_write16(hw, port, GM_PHY_ADDR, reg); | 582 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
585 | 583 | ||
586 | /* transmit control */ | 584 | /* transmit control */ |
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index 62532b4e45c5..89dd18cd12f0 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h | |||
@@ -1375,7 +1375,7 @@ enum { | |||
1375 | GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */ | 1375 | GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */ |
1376 | /* MIB Counters */ | 1376 | /* MIB Counters */ |
1377 | GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */ | 1377 | GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */ |
1378 | GM_MIB_CNT_SIZE = 256, | 1378 | GM_MIB_CNT_END = 0x025C, /* Last MIB counter */ |
1379 | }; | 1379 | }; |
1380 | 1380 | ||
1381 | 1381 | ||
diff --git a/drivers/net/starfire.c b/drivers/net/starfire.c index 45ad036733e2..9b7805be21da 100644 --- a/drivers/net/starfire.c +++ b/drivers/net/starfire.c | |||
@@ -335,7 +335,7 @@ do { \ | |||
335 | 335 | ||
336 | 336 | ||
337 | /* These identify the driver base version and may not be removed. */ | 337 | /* These identify the driver base version and may not be removed. */ |
338 | static char version[] __devinitdata = | 338 | static const char version[] __devinitdata = |
339 | KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n" | 339 | KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n" |
340 | KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n"; | 340 | KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n"; |
341 | 341 | ||
diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c index c1ce87a5f8d3..d9258d42090c 100644 --- a/drivers/net/typhoon.c +++ b/drivers/net/typhoon.c | |||
@@ -134,7 +134,7 @@ static const int multicast_filter_limit = 32; | |||
134 | #include "typhoon.h" | 134 | #include "typhoon.h" |
135 | #include "typhoon-firmware.h" | 135 | #include "typhoon-firmware.h" |
136 | 136 | ||
137 | static char version[] __devinitdata = | 137 | static const char version[] __devinitdata = |
138 | "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | 138 | "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
139 | 139 | ||
140 | MODULE_AUTHOR("David Dillow <dave@thedillows.org>"); | 140 | MODULE_AUTHOR("David Dillow <dave@thedillows.org>"); |
diff --git a/drivers/net/via-rhine.c b/drivers/net/via-rhine.c index a9b2150909d6..6a23964c1317 100644 --- a/drivers/net/via-rhine.c +++ b/drivers/net/via-rhine.c | |||
@@ -469,7 +469,7 @@ struct rhine_private { | |||
469 | struct sk_buff *tx_skbuff[TX_RING_SIZE]; | 469 | struct sk_buff *tx_skbuff[TX_RING_SIZE]; |
470 | dma_addr_t tx_skbuff_dma[TX_RING_SIZE]; | 470 | dma_addr_t tx_skbuff_dma[TX_RING_SIZE]; |
471 | 471 | ||
472 | /* Tx bounce buffers */ | 472 | /* Tx bounce buffers (Rhine-I only) */ |
473 | unsigned char *tx_buf[TX_RING_SIZE]; | 473 | unsigned char *tx_buf[TX_RING_SIZE]; |
474 | unsigned char *tx_bufs; | 474 | unsigned char *tx_bufs; |
475 | dma_addr_t tx_bufs_dma; | 475 | dma_addr_t tx_bufs_dma; |
@@ -1043,7 +1043,8 @@ static void alloc_tbufs(struct net_device* dev) | |||
1043 | rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC); | 1043 | rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC); |
1044 | next += sizeof(struct tx_desc); | 1044 | next += sizeof(struct tx_desc); |
1045 | rp->tx_ring[i].next_desc = cpu_to_le32(next); | 1045 | rp->tx_ring[i].next_desc = cpu_to_le32(next); |
1046 | rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ]; | 1046 | if (rp->quirks & rqRhineI) |
1047 | rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ]; | ||
1047 | } | 1048 | } |
1048 | rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma); | 1049 | rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma); |
1049 | 1050 | ||
@@ -1091,7 +1092,7 @@ static void rhine_check_media(struct net_device *dev, unsigned int init_media) | |||
1091 | } | 1092 | } |
1092 | 1093 | ||
1093 | /* Called after status of force_media possibly changed */ | 1094 | /* Called after status of force_media possibly changed */ |
1094 | void rhine_set_carrier(struct mii_if_info *mii) | 1095 | static void rhine_set_carrier(struct mii_if_info *mii) |
1095 | { | 1096 | { |
1096 | if (mii->force_media) { | 1097 | if (mii->force_media) { |
1097 | /* autoneg is off: Link is always assumed to be up */ | 1098 | /* autoneg is off: Link is always assumed to be up */ |