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-rw-r--r--arch/microblaze/Kconfig.debug4
-rw-r--r--arch/microblaze/Makefile2
-rw-r--r--arch/microblaze/configs/mmu_defconfig1
-rw-r--r--arch/microblaze/include/asm/pvr.h185
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo.c1
-rw-r--r--arch/microblaze/kernel/entry.S46
-rw-r--r--arch/microblaze/kernel/exceptions.c3
-rw-r--r--arch/microblaze/kernel/hw_exception_handler.S9
-rw-r--r--arch/microblaze/kernel/prom.c4
-rw-r--r--arch/microblaze/kernel/vmlinux.lds.S16
-rw-r--r--arch/microblaze/lib/memmove.c2
-rw-r--r--arch/microblaze/lib/muldi3.S121
-rw-r--r--arch/microblaze/lib/muldi3.c60
13 files changed, 214 insertions, 240 deletions
diff --git a/arch/microblaze/Kconfig.debug b/arch/microblaze/Kconfig.debug
index e66e25c4b0b2..012e377330cd 100644
--- a/arch/microblaze/Kconfig.debug
+++ b/arch/microblaze/Kconfig.debug
@@ -23,8 +23,4 @@ config HEART_BEAT
23 This option turns on/off heart beat kernel functionality. 23 This option turns on/off heart beat kernel functionality.
24 First GPIO node is taken. 24 First GPIO node is taken.
25 25
26config DEBUG_BOOTMEM
27 depends on DEBUG_KERNEL
28 bool "Debug BOOTMEM initialization"
29
30endmenu 26endmenu
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
index 15f1f1d1840d..6f432e6df9af 100644
--- a/arch/microblaze/Makefile
+++ b/arch/microblaze/Makefile
@@ -17,7 +17,7 @@ export CPU_VER CPU_MAJOR CPU_MINOR CPU_REV
17# The various CONFIG_XILINX cpu features options are integers 0/1/2... 17# The various CONFIG_XILINX cpu features options are integers 0/1/2...
18# rather than bools y/n 18# rather than bools y/n
19 19
20# Work out HW multipler support. This is icky. 20# Work out HW multipler support. This is tricky.
21# 1. Spartan2 has no HW multiplers. 21# 1. Spartan2 has no HW multiplers.
22# 2. MicroBlaze v3.x always uses them, except in Spartan 2 22# 2. MicroBlaze v3.x always uses them, except in Spartan 2
23# 3. All other FPGa/CPU ver combos, we can trust the CONFIG_ settings 23# 3. All other FPGa/CPU ver combos, we can trust the CONFIG_ settings
diff --git a/arch/microblaze/configs/mmu_defconfig b/arch/microblaze/configs/mmu_defconfig
index 8b422b12ef78..ab8fbe7ad90b 100644
--- a/arch/microblaze/configs/mmu_defconfig
+++ b/arch/microblaze/configs/mmu_defconfig
@@ -66,5 +66,4 @@ CONFIG_DEBUG_SPINLOCK=y
66CONFIG_DEBUG_INFO=y 66CONFIG_DEBUG_INFO=y
67# CONFIG_RCU_CPU_STALL_DETECTOR is not set 67# CONFIG_RCU_CPU_STALL_DETECTOR is not set
68CONFIG_EARLY_PRINTK=y 68CONFIG_EARLY_PRINTK=y
69CONFIG_DEBUG_BOOTMEM=y
70# CONFIG_CRYPTO_ANSI_CPRNG is not set 69# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h
index 37db96a15b45..a10bec62e857 100644
--- a/arch/microblaze/include/asm/pvr.h
+++ b/arch/microblaze/include/asm/pvr.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * Support for the MicroBlaze PVR (Processor Version Register) 2 * Support for the MicroBlaze PVR (Processor Version Register)
3 * 3 *
4 * Copyright (C) 2009 Michal Simek <monstr@monstr.eu> 4 * Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu>
5 * Copyright (C) 2007 John Williams <john.williams@petalogix.com> 5 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
6 * Copyright (C) 2007 - 2009 PetaLogix 6 * Copyright (C) 2007 - 2011 PetaLogix
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General 8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this 9 * Public License. See the file COPYING in the main directory of this
@@ -46,11 +46,11 @@ struct pvr_s {
46#define PVR2_I_LMB_MASK 0x10000000 46#define PVR2_I_LMB_MASK 0x10000000
47#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 47#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
48#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 48#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
49#define PVR2_D_PLB_MASK 0x02000000 /* new */ 49#define PVR2_D_PLB_MASK 0x02000000 /* new */
50#define PVR2_I_PLB_MASK 0x01000000 /* new */ 50#define PVR2_I_PLB_MASK 0x01000000 /* new */
51#define PVR2_INTERCONNECT 0x00800000 /* new */ 51#define PVR2_INTERCONNECT 0x00800000 /* new */
52#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ 52#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
53#define PVR2_USE_FSL_EXC 0x00040000 /* new */ 53#define PVR2_USE_FSL_EXC 0x00040000 /* new */
54#define PVR2_USE_MSR_INSTR 0x00020000 54#define PVR2_USE_MSR_INSTR 0x00020000
55#define PVR2_USE_PCMP_INSTR 0x00010000 55#define PVR2_USE_PCMP_INSTR 0x00010000
56#define PVR2_AREA_OPTIMISED 0x00008000 56#define PVR2_AREA_OPTIMISED 0x00008000
@@ -59,7 +59,7 @@ struct pvr_s {
59#define PVR2_USE_HW_MUL_MASK 0x00001000 59#define PVR2_USE_HW_MUL_MASK 0x00001000
60#define PVR2_USE_FPU_MASK 0x00000800 60#define PVR2_USE_FPU_MASK 0x00000800
61#define PVR2_USE_MUL64_MASK 0x00000400 61#define PVR2_USE_MUL64_MASK 0x00000400
62#define PVR2_USE_FPU2_MASK 0x00000200 /* new */ 62#define PVR2_USE_FPU2_MASK 0x00000200 /* new */
63#define PVR2_USE_IPLBEXC 0x00000100 63#define PVR2_USE_IPLBEXC 0x00000100
64#define PVR2_USE_DPLBEXC 0x00000080 64#define PVR2_USE_DPLBEXC 0x00000080
65#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 65#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
@@ -122,96 +122,103 @@ struct pvr_s {
122 122
123 123
124/* PVR access macros */ 124/* PVR access macros */
125#define PVR_IS_FULL(pvr) (pvr.pvr[0] & PVR0_PVR_FULL_MASK) 125#define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK)
126#define PVR_USE_BARREL(pvr) (pvr.pvr[0] & PVR0_USE_BARREL_MASK) 126#define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
127#define PVR_USE_DIV(pvr) (pvr.pvr[0] & PVR0_USE_DIV_MASK) 127#define PVR_USE_DIV(_pvr) (_pvr.pvr[0] & PVR0_USE_DIV_MASK)
128#define PVR_USE_HW_MUL(pvr) (pvr.pvr[0] & PVR0_USE_HW_MUL_MASK) 128#define PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
129#define PVR_USE_FPU(pvr) (pvr.pvr[0] & PVR0_USE_FPU_MASK) 129#define PVR_USE_FPU(_pvr) (_pvr.pvr[0] & PVR0_USE_FPU_MASK)
130#define PVR_USE_FPU2(pvr) (pvr.pvr[2] & PVR2_USE_FPU2_MASK) 130#define PVR_USE_FPU2(_pvr) (_pvr.pvr[2] & PVR2_USE_FPU2_MASK)
131#define PVR_USE_ICACHE(pvr) (pvr.pvr[0] & PVR0_USE_ICACHE_MASK) 131#define PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
132#define PVR_USE_DCACHE(pvr) (pvr.pvr[0] & PVR0_USE_DCACHE_MASK) 132#define PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
133#define PVR_VERSION(pvr) ((pvr.pvr[0] & PVR0_VERSION_MASK) >> 8) 133#define PVR_VERSION(_pvr) ((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
134#define PVR_USER1(pvr) (pvr.pvr[0] & PVR0_USER1_MASK) 134#define PVR_USER1(_pvr) (_pvr.pvr[0] & PVR0_USER1_MASK)
135#define PVR_USER2(pvr) (pvr.pvr[1] & PVR1_USER2_MASK) 135#define PVR_USER2(_pvr) (_pvr.pvr[1] & PVR1_USER2_MASK)
136 136
137#define PVR_D_OPB(pvr) (pvr.pvr[2] & PVR2_D_OPB_MASK) 137#define PVR_D_OPB(_pvr) (_pvr.pvr[2] & PVR2_D_OPB_MASK)
138#define PVR_D_LMB(pvr) (pvr.pvr[2] & PVR2_D_LMB_MASK) 138#define PVR_D_LMB(_pvr) (_pvr.pvr[2] & PVR2_D_LMB_MASK)
139#define PVR_I_OPB(pvr) (pvr.pvr[2] & PVR2_I_OPB_MASK) 139#define PVR_I_OPB(_pvr) (_pvr.pvr[2] & PVR2_I_OPB_MASK)
140#define PVR_I_LMB(pvr) (pvr.pvr[2] & PVR2_I_LMB_MASK) 140#define PVR_I_LMB(_pvr) (_pvr.pvr[2] & PVR2_I_LMB_MASK)
141#define PVR_INTERRUPT_IS_EDGE(pvr) \ 141#define PVR_INTERRUPT_IS_EDGE(_pvr) \
142 (pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK) 142 (_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
143#define PVR_EDGE_IS_POSITIVE(pvr) \ 143#define PVR_EDGE_IS_POSITIVE(_pvr) \
144 (pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK) 144 (_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
145#define PVR_USE_MSR_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_MSR_INSTR) 145#define PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_MSR_INSTR)
146#define PVR_USE_PCMP_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_PCMP_INSTR) 146#define PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
147#define PVR_AREA_OPTIMISED(pvr) (pvr.pvr[2] & PVR2_AREA_OPTIMISED) 147#define PVR_AREA_OPTIMISED(_pvr) (_pvr.pvr[2] & PVR2_AREA_OPTIMISED)
148#define PVR_USE_MUL64(pvr) (pvr.pvr[2] & PVR2_USE_MUL64_MASK) 148#define PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & PVR2_USE_MUL64_MASK)
149#define PVR_OPCODE_0x0_ILLEGAL(pvr) \ 149#define PVR_OPCODE_0x0_ILLEGAL(_pvr) \
150 (pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK) 150 (_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
151#define PVR_UNALIGNED_EXCEPTION(pvr) \ 151#define PVR_UNALIGNED_EXCEPTION(_pvr) \
152 (pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK) 152 (_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
153#define PVR_ILL_OPCODE_EXCEPTION(pvr) \ 153#define PVR_ILL_OPCODE_EXCEPTION(_pvr) \
154 (pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK) 154 (_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
155#define PVR_IOPB_BUS_EXCEPTION(pvr) \ 155#define PVR_IOPB_BUS_EXCEPTION(_pvr) \
156 (pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK) 156 (_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
157#define PVR_DOPB_BUS_EXCEPTION(pvr) \ 157#define PVR_DOPB_BUS_EXCEPTION(_pvr) \
158 (pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK) 158 (_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
159#define PVR_DIV_ZERO_EXCEPTION(pvr) \ 159#define PVR_DIV_ZERO_EXCEPTION(_pvr) \
160 (pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK) 160 (_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
161#define PVR_FPU_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_FPU_EXC_MASK) 161#define PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_FPU_EXC_MASK)
162#define PVR_FSL_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_USE_EXTEND_FSL) 162#define PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
163 163
164#define PVR_DEBUG_ENABLED(pvr) (pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK) 164#define PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
165#define PVR_NUMBER_OF_PC_BRK(pvr) \ 165#define PVR_NUMBER_OF_PC_BRK(_pvr) \
166 ((pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) 166 ((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
167#define PVR_NUMBER_OF_RD_ADDR_BRK(pvr) \ 167#define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \
168 ((pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) 168 ((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
169#define PVR_NUMBER_OF_WR_ADDR_BRK(pvr) \ 169#define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \
170 ((pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) 170 ((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
171#define PVR_FSL_LINKS(pvr) ((pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7) 171#define PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
172 172
173#define PVR_ICACHE_ADDR_TAG_BITS(pvr) \ 173#define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \
174 ((pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) 174 ((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
175#define PVR_ICACHE_USE_FSL(pvr) (pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK) 175#define PVR_ICACHE_USE_FSL(_pvr) \
176#define PVR_ICACHE_ALLOW_WR(pvr) (pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK) 176 (_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
177#define PVR_ICACHE_LINE_LEN(pvr) \ 177#define PVR_ICACHE_ALLOW_WR(_pvr) \
178 (1 << ((pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) 178 (_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
179#define PVR_ICACHE_BYTE_SIZE(pvr) \ 179#define PVR_ICACHE_LINE_LEN(_pvr) \
180 (1 << ((pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) 180 (1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
181 181#define PVR_ICACHE_BYTE_SIZE(_pvr) \
182#define PVR_DCACHE_ADDR_TAG_BITS(pvr) \ 182 (1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
183 ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) 183
184#define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) 184#define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \
185#define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) 185 ((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
186#define PVR_DCACHE_USE_FSL(_pvr) (_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
187#define PVR_DCACHE_ALLOW_WR(_pvr) \
188 (_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
186/* FIXME two shifts on one line needs any comment */ 189/* FIXME two shifts on one line needs any comment */
187#define PVR_DCACHE_LINE_LEN(pvr) \ 190#define PVR_DCACHE_LINE_LEN(_pvr) \
188 (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) 191 (1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
189#define PVR_DCACHE_BYTE_SIZE(pvr) \ 192#define PVR_DCACHE_BYTE_SIZE(_pvr) \
190 (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) 193 (1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
191 194
192#define PVR_DCACHE_USE_WRITEBACK(pvr) \ 195#define PVR_DCACHE_USE_WRITEBACK(_pvr) \
193 ((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14) 196 ((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
194 197
195#define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) 198#define PVR_ICACHE_BASEADDR(_pvr) \
196#define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) 199 (_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
200#define PVR_ICACHE_HIGHADDR(_pvr) \
201 (_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
202#define PVR_DCACHE_BASEADDR(_pvr) \
203 (_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
204#define PVR_DCACHE_HIGHADDR(_pvr) \
205 (_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
197 206
198#define PVR_DCACHE_BASEADDR(pvr) (pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK) 207#define PVR_TARGET_FAMILY(_pvr) \
199#define PVR_DCACHE_HIGHADDR(pvr) (pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK) 208 ((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
200 209
201#define PVR_TARGET_FAMILY(pvr) ((pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) 210#define PVR_MSR_RESET_VALUE(_pvr) \
202 211 (_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
203#define PVR_MSR_RESET_VALUE(pvr) \
204 (pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
205 212
206/* mmu */ 213/* mmu */
207#define PVR_USE_MMU(pvr) ((pvr.pvr[11] & PVR11_USE_MMU) >> 30) 214#define PVR_USE_MMU(_pvr) ((_pvr.pvr[11] & PVR11_USE_MMU) >> 30)
208#define PVR_MMU_ITLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_ITLB_SIZE) 215#define PVR_MMU_ITLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
209#define PVR_MMU_DTLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) 216#define PVR_MMU_DTLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
210#define PVR_MMU_TLB_ACCESS(pvr) (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) 217#define PVR_MMU_TLB_ACCESS(_pvr) (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
211#define PVR_MMU_ZONES(pvr) (pvr.pvr[11] & PVR11_MMU_ZONES) 218#define PVR_MMU_ZONES(_pvr) (_pvr.pvr[11] & PVR11_MMU_ZONES)
212 219
213/* endian */ 220/* endian */
214#define PVR_ENDIAN(pvr) (pvr.pvr[0] & PVR0_ENDI) 221#define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI)
215 222
216int cpu_has_pvr(void); 223int cpu_has_pvr(void);
217void get_pvr(struct pvr_s *pvr); 224void get_pvr(struct pvr_s *pvr);
diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c b/arch/microblaze/kernel/cpu/cpuinfo.c
index 87c79fa275c3..2c309fccf230 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo.c
@@ -32,6 +32,7 @@ const struct cpu_ver_key cpu_ver_lookup[] = {
32 {"7.30.a", 0x10}, 32 {"7.30.a", 0x10},
33 {"7.30.b", 0x11}, 33 {"7.30.b", 0x11},
34 {"8.00.a", 0x12}, 34 {"8.00.a", 0x12},
35 {"8.00.b", 0x13},
35 {NULL, 0}, 36 {NULL, 0},
36}; 37};
37 38
diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S
index 819238b8a429..41c30cdb2704 100644
--- a/arch/microblaze/kernel/entry.S
+++ b/arch/microblaze/kernel/entry.S
@@ -287,25 +287,44 @@
287 * are masked. This is nice, means we don't have to CLI before state save 287 * are masked. This is nice, means we don't have to CLI before state save
288 */ 288 */
289C_ENTRY(_user_exception): 289C_ENTRY(_user_exception):
290 addi r14, r14, 4 /* return address is 4 byte after call */
291 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */ 290 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
291 addi r14, r14, 4 /* return address is 4 byte after call */
292
293 mfs r1, rmsr
294 nop
295 andi r1, r1, MSR_UMS
296 bnei r1, 1f
297
298/* Kernel-mode state save - kernel execve */
299 lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
300 tophys(r1,r1);
301
302 addik r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */
303 SAVE_REGS
292 304
305 swi r1, r1, PTO + PT_MODE; /* pt_regs -> kernel mode */
306 brid 2f;
307 nop; /* Fill delay slot */
308
309/* User-mode state save. */
3101:
293 lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */ 311 lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
294 tophys(r1,r1); 312 tophys(r1,r1);
295 lwi r1, r1, TS_THREAD_INFO; /* get stack from task_struct */ 313 lwi r1, r1, TS_THREAD_INFO; /* get stack from task_struct */
296 /* MS these three instructions can be added to one */ 314/* calculate kernel stack pointer from task struct 8k */
297 /* addik r1, r1, THREAD_SIZE; */ 315 addik r1, r1, THREAD_SIZE;
298 /* tophys(r1,r1); */ 316 tophys(r1,r1);
299 /* addik r1, r1, -STATE_SAVE_SIZE; */ 317
300 addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; 318 addik r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */
301 SAVE_REGS 319 SAVE_REGS
302 swi r0, r1, PTO + PT_R3 320 swi r0, r1, PTO + PT_R3
303 swi r0, r1, PTO + PT_R4 321 swi r0, r1, PTO + PT_R4
304 322
323 swi r0, r1, PTO + PT_MODE; /* Was in user-mode. */
305 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); 324 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
306 swi r11, r1, PTO+PT_R1; /* Store user SP. */ 325 swi r11, r1, PTO+PT_R1; /* Store user SP. */
307 clear_ums; 326 clear_ums;
308 lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); 3272: lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
309 /* Save away the syscall number. */ 328 /* Save away the syscall number. */
310 swi r12, r1, PTO+PT_R0; 329 swi r12, r1, PTO+PT_R0;
311 tovirt(r1,r1) 330 tovirt(r1,r1)
@@ -375,6 +394,9 @@ C_ENTRY(ret_from_trap):
375 swi r3, r1, PTO + PT_R3 394 swi r3, r1, PTO + PT_R3
376 swi r4, r1, PTO + PT_R4 395 swi r4, r1, PTO + PT_R4
377 396
397 lwi r11, r1, PTO + PT_MODE;
398/* See if returning to kernel mode, if so, skip resched &c. */
399 bnei r11, 2f;
378 /* We're returning to user mode, so check for various conditions that 400 /* We're returning to user mode, so check for various conditions that
379 * trigger rescheduling. */ 401 * trigger rescheduling. */
380 /* FIXME: Restructure all these flag checks. */ 402 /* FIXME: Restructure all these flag checks. */
@@ -417,6 +439,16 @@ C_ENTRY(ret_from_trap):
417 RESTORE_REGS; 439 RESTORE_REGS;
418 addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */ 440 addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */
419 lwi r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */ 441 lwi r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */
442 bri 6f;
443
444/* Return to kernel state. */
4452: set_bip; /* Ints masked for state restore */
446 VM_OFF;
447 tophys(r1,r1);
448 RESTORE_REGS;
449 addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */
450 tovirt(r1,r1);
4516:
420TRAP_return: /* Make global symbol for debugging */ 452TRAP_return: /* Make global symbol for debugging */
421 rtbd r14, 0; /* Instructions to return from an IRQ */ 453 rtbd r14, 0; /* Instructions to return from an IRQ */
422 nop; 454 nop;
diff --git a/arch/microblaze/kernel/exceptions.c b/arch/microblaze/kernel/exceptions.c
index 478f2943ede7..a7fa6ae76d89 100644
--- a/arch/microblaze/kernel/exceptions.c
+++ b/arch/microblaze/kernel/exceptions.c
@@ -25,6 +25,7 @@
25#include <linux/errno.h> 25#include <linux/errno.h>
26#include <linux/ptrace.h> 26#include <linux/ptrace.h>
27#include <asm/current.h> 27#include <asm/current.h>
28#include <asm/cacheflush.h>
28 29
29#define MICROBLAZE_ILL_OPCODE_EXCEPTION 0x02 30#define MICROBLAZE_ILL_OPCODE_EXCEPTION 0x02
30#define MICROBLAZE_IBUS_EXCEPTION 0x03 31#define MICROBLAZE_IBUS_EXCEPTION 0x03
@@ -52,6 +53,8 @@ void die(const char *str, struct pt_regs *fp, long err)
52void sw_exception(struct pt_regs *regs) 53void sw_exception(struct pt_regs *regs)
53{ 54{
54 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16); 55 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16);
56 flush_dcache_range(regs->r16, regs->r16 + 0x4);
57 flush_icache_range(regs->r16, regs->r16 + 0x4);
55} 58}
56 59
57void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 60void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 781195438ee6..25f6e07d8de8 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -945,11 +945,20 @@ store3: sbi r3, r4, 2;
945store4: sbi r3, r4, 3; /* Delay slot */ 945store4: sbi r3, r4, 3; /* Delay slot */
946ex_shw_vm: 946ex_shw_vm:
947 /* Store the lower half-word, byte-by-byte into destination address */ 947 /* Store the lower half-word, byte-by-byte into destination address */
948#ifdef __MICROBLAZEEL__
949 lbui r3, r5, 0;
950store5: sbi r3, r4, 0;
951 lbui r3, r5, 1;
952 brid ret_from_exc;
953store6: sbi r3, r4, 1; /* Delay slot */
954#else
948 lbui r3, r5, 2; 955 lbui r3, r5, 2;
949store5: sbi r3, r4, 0; 956store5: sbi r3, r4, 0;
950 lbui r3, r5, 3; 957 lbui r3, r5, 3;
951 brid ret_from_exc; 958 brid ret_from_exc;
952store6: sbi r3, r4, 1; /* Delay slot */ 959store6: sbi r3, r4, 1; /* Delay slot */
960#endif
961
953ex_sw_end_vm: /* Exception handling of store word, ends. */ 962ex_sw_end_vm: /* Exception handling of store word, ends. */
954 963
955/* We have to prevent cases that get/put_user macros get unaligned pointer 964/* We have to prevent cases that get/put_user macros get unaligned pointer
diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c
index a105301e2b7f..c881393f07fd 100644
--- a/arch/microblaze/kernel/prom.c
+++ b/arch/microblaze/kernel/prom.c
@@ -61,14 +61,12 @@ static int __init early_init_dt_scan_serial(unsigned long node,
61 char *p; 61 char *p;
62 int *addr; 62 int *addr;
63 63
64 pr_debug("search \"chosen\", depth: %d, uname: %s\n", depth, uname); 64 pr_debug("search \"serial\", depth: %d, uname: %s\n", depth, uname);
65 65
66/* find all serial nodes */ 66/* find all serial nodes */
67 if (strncmp(uname, "serial", 6) != 0) 67 if (strncmp(uname, "serial", 6) != 0)
68 return 0; 68 return 0;
69 69
70 early_init_dt_check_for_initrd(node);
71
72/* find compatible node with uartlite */ 70/* find compatible node with uartlite */
73 p = of_get_flat_dt_prop(node, "compatible", &l); 71 p = of_get_flat_dt_prop(node, "compatible", &l);
74 if ((strncmp(p, "xlnx,xps-uartlite", 17) != 0) && 72 if ((strncmp(p, "xlnx,xps-uartlite", 17) != 0) &&
diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S
index 96a88c31fe48..3451bdec9f05 100644
--- a/arch/microblaze/kernel/vmlinux.lds.S
+++ b/arch/microblaze/kernel/vmlinux.lds.S
@@ -123,20 +123,10 @@ SECTIONS {
123 123
124 __init_end_before_initramfs = .; 124 __init_end_before_initramfs = .;
125 125
126 .init.ramfs ALIGN(PAGE_SIZE) : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { 126 .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
127 __initramfs_start = .; 127 INIT_RAM_FS
128 *(.init.ramfs)
129 __initramfs_end = .;
130 . = ALIGN(4);
131 LONG(0);
132/*
133 * FIXME this can break initramfs for MMU.
134 * Pad init.ramfs up to page boundary,
135 * so that __init_end == __bss_start. This will make image.elf
136 * consistent with the image.bin
137 */
138 /* . = ALIGN(PAGE_SIZE); */
139 } 128 }
129
140 __init_end = .; 130 __init_end = .;
141 131
142 .bss ALIGN (PAGE_SIZE) : AT(ADDR(.bss) - LOAD_OFFSET) { 132 .bss ALIGN (PAGE_SIZE) : AT(ADDR(.bss) - LOAD_OFFSET) {
diff --git a/arch/microblaze/lib/memmove.c b/arch/microblaze/lib/memmove.c
index 123e3616f2dd..810fd68775e3 100644
--- a/arch/microblaze/lib/memmove.c
+++ b/arch/microblaze/lib/memmove.c
@@ -182,7 +182,7 @@ void *memmove(void *v_dst, const void *v_src, __kernel_size_t c)
182 for (; c >= 4; c -= 4) { 182 for (; c >= 4; c -= 4) {
183 value = *--i_src; 183 value = *--i_src;
184 *--i_dst = buf_hold | ((value & 0xFF000000)>> 24); 184 *--i_dst = buf_hold | ((value & 0xFF000000)>> 24);
185 buf_hold = (value & 0xFFFFFF) << 8;; 185 buf_hold = (value & 0xFFFFFF) << 8;
186 } 186 }
187#endif 187#endif
188 /* Realign the source */ 188 /* Realign the source */
diff --git a/arch/microblaze/lib/muldi3.S b/arch/microblaze/lib/muldi3.S
deleted file mode 100644
index ceeaa8c407f2..000000000000
--- a/arch/microblaze/lib/muldi3.S
+++ /dev/null
@@ -1,121 +0,0 @@
1#include <linux/linkage.h>
2
3/*
4 * Multiply operation for 64 bit integers, for devices with hard multiply
5 * Input : Operand1[H] in Reg r5
6 * Operand1[L] in Reg r6
7 * Operand2[H] in Reg r7
8 * Operand2[L] in Reg r8
9 * Output: Result[H] in Reg r3
10 * Result[L] in Reg r4
11 *
12 * Explaination:
13 *
14 * Both the input numbers are divided into 16 bit number as follows
15 * op1 = A B C D
16 * op2 = E F G H
17 * result = D * H
18 * + (C * H + D * G) << 16
19 * + (B * H + C * G + D * F) << 32
20 * + (A * H + B * G + C * F + D * E) << 48
21 *
22 * Only 64 bits of the output are considered
23 */
24
25 .text
26 .globl __muldi3
27 .type __muldi3, @function
28 .ent __muldi3
29
30__muldi3:
31 addi r1, r1, -40
32
33/* Save the input operands on the caller's stack */
34 swi r5, r1, 44
35 swi r6, r1, 48
36 swi r7, r1, 52
37 swi r8, r1, 56
38
39/* Store all the callee saved registers */
40 sw r20, r1, r0
41 swi r21, r1, 4
42 swi r22, r1, 8
43 swi r23, r1, 12
44 swi r24, r1, 16
45 swi r25, r1, 20
46 swi r26, r1, 24
47 swi r27, r1, 28
48
49/* Load all the 16 bit values for A thru H */
50 lhui r20, r1, 44 /* A */
51 lhui r21, r1, 46 /* B */
52 lhui r22, r1, 48 /* C */
53 lhui r23, r1, 50 /* D */
54 lhui r24, r1, 52 /* E */
55 lhui r25, r1, 54 /* F */
56 lhui r26, r1, 56 /* G */
57 lhui r27, r1, 58 /* H */
58
59/* D * H ==> LSB of the result on stack ==> Store1 */
60 mul r9, r23, r27
61 swi r9, r1, 36 /* Pos2 and Pos3 */
62
63/* Hi (Store1) + C * H + D * G ==> Store2 ==> Pos1 and Pos2 */
64/* Store the carry generated in position 2 for Pos 3 */
65 lhui r11, r1, 36 /* Pos2 */
66 mul r9, r22, r27 /* C * H */
67 mul r10, r23, r26 /* D * G */
68 add r9, r9, r10
69 addc r12, r0, r0
70 add r9, r9, r11
71 addc r12, r12, r0 /* Store the Carry */
72 shi r9, r1, 36 /* Store Pos2 */
73 swi r9, r1, 32
74 lhui r11, r1, 32
75 shi r11, r1, 34 /* Store Pos1 */
76
77/* Hi (Store2) + B * H + C * G + D * F ==> Store3 ==> Pos0 and Pos1 */
78 mul r9, r21, r27 /* B * H */
79 mul r10, r22, r26 /* C * G */
80 mul r7, r23, r25 /* D * F */
81 add r9, r9, r11
82 add r9, r9, r10
83 add r9, r9, r7
84 swi r9, r1, 32 /* Pos0 and Pos1 */
85
86/* Hi (Store3) + A * H + B * G + C * F + D * E ==> Store3 ==> Pos0 */
87 lhui r11, r1, 32 /* Pos0 */
88 mul r9, r20, r27 /* A * H */
89 mul r10, r21, r26 /* B * G */
90 mul r7, r22, r25 /* C * F */
91 mul r8, r23, r24 /* D * E */
92 add r9, r9, r11
93 add r9, r9, r10
94 add r9, r9, r7
95 add r9, r9, r8
96 sext16 r9, r9 /* Sign extend the MSB */
97 shi r9, r1, 32
98
99/* Move results to r3 and r4 */
100 lhui r3, r1, 32
101 add r3, r3, r12
102 shi r3, r1, 32
103 lwi r3, r1, 32 /* Hi Part */
104 lwi r4, r1, 36 /* Lo Part */
105
106/* Restore Callee saved registers */
107 lw r20, r1, r0
108 lwi r21, r1, 4
109 lwi r22, r1, 8
110 lwi r23, r1, 12
111 lwi r24, r1, 16
112 lwi r25, r1, 20
113 lwi r26, r1, 24
114 lwi r27, r1, 28
115
116/* Restore Frame and return */
117 rtsd r15, 8
118 addi r1, r1, 40
119
120.size __muldi3, . - __muldi3
121.end __muldi3
diff --git a/arch/microblaze/lib/muldi3.c b/arch/microblaze/lib/muldi3.c
new file mode 100644
index 000000000000..d4860e154d29
--- /dev/null
+++ b/arch/microblaze/lib/muldi3.c
@@ -0,0 +1,60 @@
1#include <linux/module.h>
2
3#include "libgcc.h"
4
5#define DWtype long long
6#define UWtype unsigned long
7#define UHWtype unsigned short
8
9#define W_TYPE_SIZE 32
10
11#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
12#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
13#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
14
15/* If we still don't have umul_ppmm, define it using plain C. */
16#if !defined(umul_ppmm)
17#define umul_ppmm(w1, w0, u, v) \
18 do { \
19 UWtype __x0, __x1, __x2, __x3; \
20 UHWtype __ul, __vl, __uh, __vh; \
21 \
22 __ul = __ll_lowpart(u); \
23 __uh = __ll_highpart(u); \
24 __vl = __ll_lowpart(v); \
25 __vh = __ll_highpart(v); \
26 \
27 __x0 = (UWtype) __ul * __vl; \
28 __x1 = (UWtype) __ul * __vh; \
29 __x2 = (UWtype) __uh * __vl; \
30 __x3 = (UWtype) __uh * __vh; \
31 \
32 __x1 += __ll_highpart(__x0); /* this can't give carry */\
33 __x1 += __x2; /* but this indeed can */ \
34 if (__x1 < __x2) /* did we get it? */ \
35 __x3 += __ll_B; /* yes, add it in the proper pos */ \
36 \
37 (w1) = __x3 + __ll_highpart(__x1); \
38 (w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0);\
39 } while (0)
40#endif
41
42#if !defined(__umulsidi3)
43#define __umulsidi3(u, v) ({ \
44 DWunion __w; \
45 umul_ppmm(__w.s.high, __w.s.low, u, v); \
46 __w.ll; \
47 })
48#endif
49
50DWtype __muldi3(DWtype u, DWtype v)
51{
52 const DWunion uu = {.ll = u};
53 const DWunion vv = {.ll = v};
54 DWunion w = {.ll = __umulsidi3(uu.s.low, vv.s.low)};
55
56 w.s.high += ((UWtype) uu.s.low * (UWtype) vv.s.high
57 + (UWtype) uu.s.high * (UWtype) vv.s.low);
58
59 return w.ll;
60}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 16:50:52 -0500