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-rw-r--r--drivers/serial/sh-sci.c1146
-rw-r--r--drivers/serial/sh-sci.h90
2 files changed, 467 insertions, 769 deletions
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index cbede06cac27..f336ba6778dd 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * 5 *
6 * Copyright (C) 2002, 2003, 2004 Paul Mundt 6 * Copyright (C) 2002 - 2006 Paul Mundt
7 * 7 *
8 * based off of the old drivers/char/sh-sci.c by: 8 * based off of the old drivers/char/sh-sci.c by:
9 * 9 *
@@ -20,10 +20,9 @@
20 20
21#undef DEBUG 21#undef DEBUG
22 22
23#include <linux/config.h>
23#include <linux/module.h> 24#include <linux/module.h>
24#include <linux/errno.h> 25#include <linux/errno.h>
25#include <linux/signal.h>
26#include <linux/sched.h>
27#include <linux/timer.h> 26#include <linux/timer.h>
28#include <linux/interrupt.h> 27#include <linux/interrupt.h>
29#include <linux/tty.h> 28#include <linux/tty.h>
@@ -32,71 +31,77 @@
32#include <linux/major.h> 31#include <linux/major.h>
33#include <linux/string.h> 32#include <linux/string.h>
34#include <linux/sysrq.h> 33#include <linux/sysrq.h>
35#include <linux/fcntl.h>
36#include <linux/ptrace.h>
37#include <linux/ioport.h> 34#include <linux/ioport.h>
38#include <linux/mm.h> 35#include <linux/mm.h>
39#include <linux/slab.h>
40#include <linux/init.h> 36#include <linux/init.h>
41#include <linux/delay.h> 37#include <linux/delay.h>
42#include <linux/console.h> 38#include <linux/console.h>
43#include <linux/bitops.h> 39#include <linux/platform_device.h>
44#include <linux/generic_serial.h>
45 40
46#ifdef CONFIG_CPU_FREQ 41#ifdef CONFIG_CPU_FREQ
47#include <linux/notifier.h> 42#include <linux/notifier.h>
48#include <linux/cpufreq.h> 43#include <linux/cpufreq.h>
49#endif 44#endif
50 45
51#include <asm/system.h>
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/uaccess.h>
55
56#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64) 46#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
57#include <asm/clock.h> 47#include <asm/clock.h>
58#endif
59
60#ifdef CONFIG_SH_STANDARD_BIOS
61#include <asm/sh_bios.h> 48#include <asm/sh_bios.h>
49#include <asm/kgdb.h>
62#endif 50#endif
63 51
52#include <asm/sci.h>
53
64#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 54#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
65#define SUPPORT_SYSRQ 55#define SUPPORT_SYSRQ
66#endif 56#endif
67 57
68#include "sh-sci.h" 58#include "sh-sci.h"
69 59
70#ifdef CONFIG_SH_KGDB 60struct sci_port {
71#include <asm/kgdb.h> 61 struct uart_port port;
62
63 /* Port type */
64 unsigned int type;
65
66 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
67 unsigned int irqs[SCIx_NR_IRQS];
68
69 /* Port pin configuration */
70 void (*init_pins)(struct uart_port *port,
71 unsigned int cflag);
72 72
73static int kgdb_get_char(struct sci_port *port); 73 /* Port enable callback */
74static void kgdb_put_char(struct sci_port *port, char c); 74 void (*enable)(struct uart_port *port);
75static void kgdb_handle_error(struct sci_port *port); 75
76 /* Port disable callback */
77 void (*disable)(struct uart_port *port);
78
79 /* Break timer */
80 struct timer_list break_timer;
81 int break_flag;
82};
83
84#ifdef CONFIG_SH_KGDB
76static struct sci_port *kgdb_sci_port; 85static struct sci_port *kgdb_sci_port;
77#endif /* CONFIG_SH_KGDB */ 86#endif
78 87
79#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 88#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
80static struct sci_port *serial_console_port = 0; 89static struct sci_port *serial_console_port;
81#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 90#endif
82 91
83/* Function prototypes */ 92/* Function prototypes */
84static void sci_stop_tx(struct uart_port *port); 93static void sci_stop_tx(struct uart_port *port);
85static void sci_start_tx(struct uart_port *port);
86static void sci_start_rx(struct uart_port *port, unsigned int tty_start);
87static void sci_stop_rx(struct uart_port *port);
88static int sci_request_irq(struct sci_port *port);
89static void sci_free_irq(struct sci_port *port);
90
91static struct sci_port sci_ports[];
92static struct uart_driver sci_uart_driver;
93 94
94#define SCI_NPORTS sci_uart_driver.nr 95#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
95 96
96#if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) 97static struct sci_port sci_ports[SCI_NPORTS];
98static struct uart_driver sci_uart_driver;
97 99
98static void handle_error(struct uart_port *port) 100#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
99{ /* Clear error flags */ 101 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
102static inline void handle_error(struct uart_port *port)
103{
104 /* Clear error flags */
100 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 105 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
101} 106}
102 107
@@ -106,8 +111,8 @@ static int get_char(struct uart_port *port)
106 unsigned short status; 111 unsigned short status;
107 int c; 112 int c;
108 113
109 local_irq_save(flags); 114 spin_lock_irqsave(&port->lock, flags);
110 do { 115 do {
111 status = sci_in(port, SCxSR); 116 status = sci_in(port, SCxSR);
112 if (status & SCxSR_ERRORS(port)) { 117 if (status & SCxSR_ERRORS(port)) {
113 handle_error(port); 118 handle_error(port);
@@ -117,38 +122,19 @@ static int get_char(struct uart_port *port)
117 c = sci_in(port, SCxRDR); 122 c = sci_in(port, SCxRDR);
118 sci_in(port, SCxSR); /* Dummy read */ 123 sci_in(port, SCxSR); /* Dummy read */
119 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 124 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
120 local_irq_restore(flags); 125 spin_unlock_irqrestore(&port->lock, flags);
121 126
122 return c; 127 return c;
123} 128}
124
125/* Taken from sh-stub.c of GDB 4.18 */
126static const char hexchars[] = "0123456789abcdef";
127
128static __inline__ char highhex(int x)
129{
130 return hexchars[(x >> 4) & 0xf];
131}
132
133static __inline__ char lowhex(int x)
134{
135 return hexchars[x & 0xf];
136}
137
138#endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ 129#endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
139 130
140/* 131#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
141 * Send the packet in buffer. The host gets one chance to read it.
142 * This routine does not wait for a positive acknowledge.
143 */
144
145#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
146static void put_char(struct uart_port *port, char c) 132static void put_char(struct uart_port *port, char c)
147{ 133{
148 unsigned long flags; 134 unsigned long flags;
149 unsigned short status; 135 unsigned short status;
150 136
151 local_irq_save(flags); 137 spin_lock_irqsave(&port->lock, flags);
152 138
153 do { 139 do {
154 status = sci_in(port, SCxSR); 140 status = sci_in(port, SCxSR);
@@ -158,9 +144,11 @@ static void put_char(struct uart_port *port, char c)
158 sci_in(port, SCxSR); /* Dummy read */ 144 sci_in(port, SCxSR); /* Dummy read */
159 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 145 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
160 146
161 local_irq_restore(flags); 147 spin_unlock_irqrestore(&port->lock, flags);
162} 148}
149#endif
163 150
151#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
164static void put_string(struct sci_port *sci_port, const char *buffer, int count) 152static void put_string(struct sci_port *sci_port, const char *buffer, int count)
165{ 153{
166 struct uart_port *port = &sci_port->port; 154 struct uart_port *port = &sci_port->port;
@@ -213,96 +201,28 @@ static void put_string(struct sci_port *sci_port, const char *buffer, int count)
213} 201}
214#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 202#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
215 203
216
217#ifdef CONFIG_SH_KGDB 204#ifdef CONFIG_SH_KGDB
218
219/* Is the SCI ready, ie is there a char waiting? */
220static int kgdb_is_char_ready(struct sci_port *port)
221{
222 unsigned short status = sci_in(port, SCxSR);
223
224 if (status & (SCxSR_ERRORS(port) | SCxSR_BRK(port)))
225 kgdb_handle_error(port);
226
227 return (status & SCxSR_RDxF(port));
228}
229
230/* Write a char */
231static void kgdb_put_char(struct sci_port *port, char c)
232{
233 unsigned short status;
234
235 do
236 status = sci_in(port, SCxSR);
237 while (!(status & SCxSR_TDxE(port)));
238
239 sci_out(port, SCxTDR, c);
240 sci_in(port, SCxSR); /* Dummy read */
241 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
242}
243
244/* Get a char if there is one, else ret -1 */
245static int kgdb_get_char(struct sci_port *port)
246{
247 int c;
248
249 if (kgdb_is_char_ready(port) == 0)
250 c = -1;
251 else {
252 c = sci_in(port, SCxRDR);
253 sci_in(port, SCxSR); /* Dummy read */
254 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
255 }
256
257 return c;
258}
259
260/* Called from kgdbstub.c to get a character, i.e. is blocking */
261static int kgdb_sci_getchar(void) 205static int kgdb_sci_getchar(void)
262{ 206{
263 volatile int c; 207 int c;
264 208
265 /* Keep trying to read a character, this could be neater */ 209 /* Keep trying to read a character, this could be neater */
266 while ((c = kgdb_get_char(kgdb_sci_port)) < 0); 210 while ((c = get_char(kgdb_sci_port)) < 0)
211 cpu_relax();
267 212
268 return c; 213 return c;
269} 214}
270 215
271/* Called from kgdbstub.c to put a character, just a wrapper */ 216static inline void kgdb_sci_putchar(int c)
272static void kgdb_sci_putchar(int c)
273{
274
275 kgdb_put_char(kgdb_sci_port, c);
276}
277
278/* Clear any errors on the SCI */
279static void kgdb_handle_error(struct sci_port *port)
280{ 217{
281 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); /* Clear error flags */ 218 put_char(kgdb_sci_port, c);
282} 219}
283
284/* Breakpoint if there's a break sent on the serial port */
285static void kgdb_break_interrupt(int irq, void *ptr, struct pt_regs *regs)
286{
287 struct sci_port *port = ptr;
288 unsigned short status = sci_in(port, SCxSR);
289
290 if (status & SCxSR_BRK(port)) {
291
292 /* Break into the debugger if a break is detected */
293 BREAKPOINT();
294
295 /* Clear */
296 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
297 }
298}
299
300#endif /* CONFIG_SH_KGDB */ 220#endif /* CONFIG_SH_KGDB */
301 221
302#if defined(__H8300S__) 222#if defined(__H8300S__)
303enum { sci_disable, sci_enable }; 223enum { sci_disable, sci_enable };
304 224
305static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl) 225static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
306{ 226{
307 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL; 227 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
308 int ch = (port->mapbase - SMR0) >> 3; 228 int ch = (port->mapbase - SMR0) >> 3;
@@ -314,32 +234,66 @@ static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl)
314 *mstpcrl &= ~mask; 234 *mstpcrl &= ~mask;
315 } 235 }
316} 236}
237
238static inline void h8300_sci_enable(struct uart_port *port)
239{
240 h8300_sci_config(port, sci_enable);
241}
242
243static inline void h8300_sci_disable(struct uart_port *port)
244{
245 h8300_sci_config(port, sci_disable);
246}
317#endif 247#endif
318 248
319#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) 249#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
320#if defined(__H8300H__) || defined(__H8300S__) 250 defined(__H8300H__) || defined(__H8300S__)
321static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) 251static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
322{ 252{
323 int ch = (port->mapbase - SMR0) >> 3; 253 int ch = (port->mapbase - SMR0) >> 3;
324 254
325 /* set DDR regs */ 255 /* set DDR regs */
326 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].rx,H8300_GPIO_INPUT); 256 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
327 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].tx,H8300_GPIO_OUTPUT); 257 h8300_sci_pins[ch].rx,
258 H8300_GPIO_INPUT);
259 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
260 h8300_sci_pins[ch].tx,
261 H8300_GPIO_OUTPUT);
262
328 /* tx mark output*/ 263 /* tx mark output*/
329 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; 264 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
330} 265}
266#else
267#define sci_init_pins_sci NULL
268#endif
269
270#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
271static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
272{
273 unsigned int fcr_val = 0;
274
275 if (cflag & CRTSCTS)
276 fcr_val |= SCFCR_MCE;
277
278 sci_out(port, SCFCR, fcr_val);
279}
280#else
281#define sci_init_pins_irda NULL
331#endif 282#endif
283
284#ifdef SCI_ONLY
285#define sci_init_pins_scif NULL
332#endif 286#endif
333 287
334#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) 288#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
335#if defined(CONFIG_CPU_SUBTYPE_SH7300) 289#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
336/* SH7300 doesn't use RTS/CTS */ 290/* SH7300 doesn't use RTS/CTS */
337static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 291static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
338{ 292{
339 sci_out(port, SCFCR, 0); 293 sci_out(port, SCFCR, 0);
340} 294}
341#elif defined(CONFIG_CPU_SH3) 295#elif defined(CONFIG_CPU_SH3)
342/* For SH7705, SH7707, SH7709, SH7709A, SH7729 */ 296/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
343static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 297static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
344{ 298{
345 unsigned int fcr_val = 0; 299 unsigned int fcr_val = 0;
@@ -366,20 +320,7 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
366 320
367 sci_out(port, SCFCR, fcr_val); 321 sci_out(port, SCFCR, fcr_val);
368} 322}
369
370#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
371static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
372{
373 unsigned int fcr_val = 0;
374
375 if (cflag & CRTSCTS)
376 fcr_val |= SCFCR_MCE;
377
378 sci_out(port, SCFCR, fcr_val);
379}
380#endif
381#else 323#else
382
383/* For SH7750 */ 324/* For SH7750 */
384static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 325static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
385{ 326{
@@ -388,7 +329,9 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
388 if (cflag & CRTSCTS) { 329 if (cflag & CRTSCTS) {
389 fcr_val |= SCFCR_MCE; 330 fcr_val |= SCFCR_MCE;
390 } else { 331 } else {
391#ifdef CONFIG_CPU_SUBTYPE_SH7780 332#ifdef CONFIG_CPU_SUBTYPE_SH7343
333 /* Nothing */
334#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
392 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ 335 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
393#else 336#else
394 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */ 337 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
@@ -396,10 +339,41 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
396 } 339 }
397 sci_out(port, SCFCR, fcr_val); 340 sci_out(port, SCFCR, fcr_val);
398} 341}
342#endif
343
344#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
345static inline int scif_txroom(struct uart_port *port)
346{
347 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
348}
349
350static inline int scif_rxroom(struct uart_port *port)
351{
352 return sci_in(port, SCRFDR) & 0x7f;
353}
354#else
355static inline int scif_txroom(struct uart_port *port)
356{
357 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
358}
399 359
360static inline int scif_rxroom(struct uart_port *port)
361{
362 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
363}
400#endif 364#endif
401#endif /* SCIF_ONLY || SCI_AND_SCIF */ 365#endif /* SCIF_ONLY || SCI_AND_SCIF */
402 366
367static inline int sci_txroom(struct uart_port *port)
368{
369 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
370}
371
372static inline int sci_rxroom(struct uart_port *port)
373{
374 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
375}
376
403/* ********************************************************************** * 377/* ********************************************************************** *
404 * the interrupt related routines * 378 * the interrupt related routines *
405 * ********************************************************************** */ 379 * ********************************************************************** */
@@ -408,14 +382,12 @@ static void sci_transmit_chars(struct uart_port *port)
408{ 382{
409 struct circ_buf *xmit = &port->info->xmit; 383 struct circ_buf *xmit = &port->info->xmit;
410 unsigned int stopped = uart_tx_stopped(port); 384 unsigned int stopped = uart_tx_stopped(port);
411 unsigned long flags;
412 unsigned short status; 385 unsigned short status;
413 unsigned short ctrl; 386 unsigned short ctrl;
414 int count, txroom; 387 int count;
415 388
416 status = sci_in(port, SCxSR); 389 status = sci_in(port, SCxSR);
417 if (!(status & SCxSR_TDxE(port))) { 390 if (!(status & SCxSR_TDxE(port))) {
418 local_irq_save(flags);
419 ctrl = sci_in(port, SCSCR); 391 ctrl = sci_in(port, SCSCR);
420 if (uart_circ_empty(xmit)) { 392 if (uart_circ_empty(xmit)) {
421 ctrl &= ~SCI_CTRL_FLAGS_TIE; 393 ctrl &= ~SCI_CTRL_FLAGS_TIE;
@@ -423,25 +395,15 @@ static void sci_transmit_chars(struct uart_port *port)
423 ctrl |= SCI_CTRL_FLAGS_TIE; 395 ctrl |= SCI_CTRL_FLAGS_TIE;
424 } 396 }
425 sci_out(port, SCSCR, ctrl); 397 sci_out(port, SCSCR, ctrl);
426 local_irq_restore(flags);
427 return; 398 return;
428 } 399 }
429 400
430#if !defined(SCI_ONLY) 401#ifndef SCI_ONLY
431 if (port->type == PORT_SCIF) { 402 if (port->type == PORT_SCIF)
432#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) 403 count = scif_txroom(port);
433 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f); 404 else
434#else
435 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCFDR)>>8);
436#endif
437 } else {
438 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
439 }
440#else
441 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
442#endif 405#endif
443 406 count = sci_txroom(port);
444 count = txroom;
445 407
446 do { 408 do {
447 unsigned char c; 409 unsigned char c;
@@ -468,7 +430,6 @@ static void sci_transmit_chars(struct uart_port *port)
468 if (uart_circ_empty(xmit)) { 430 if (uart_circ_empty(xmit)) {
469 sci_stop_tx(port); 431 sci_stop_tx(port);
470 } else { 432 } else {
471 local_irq_save(flags);
472 ctrl = sci_in(port, SCSCR); 433 ctrl = sci_in(port, SCSCR);
473 434
474#if !defined(SCI_ONLY) 435#if !defined(SCI_ONLY)
@@ -480,7 +441,6 @@ static void sci_transmit_chars(struct uart_port *port)
480 441
481 ctrl |= SCI_CTRL_FLAGS_TIE; 442 ctrl |= SCI_CTRL_FLAGS_TIE;
482 sci_out(port, SCSCR, ctrl); 443 sci_out(port, SCSCR, ctrl);
483 local_irq_restore(flags);
484 } 444 }
485} 445}
486 446
@@ -490,6 +450,7 @@ static void sci_transmit_chars(struct uart_port *port)
490static inline void sci_receive_chars(struct uart_port *port, 450static inline void sci_receive_chars(struct uart_port *port,
491 struct pt_regs *regs) 451 struct pt_regs *regs)
492{ 452{
453 struct sci_port *sci_port = (struct sci_port *)port;
493 struct tty_struct *tty = port->info->tty; 454 struct tty_struct *tty = port->info->tty;
494 int i, count, copied = 0; 455 int i, count, copied = 0;
495 unsigned short status; 456 unsigned short status;
@@ -501,18 +462,11 @@ static inline void sci_receive_chars(struct uart_port *port,
501 462
502 while (1) { 463 while (1) {
503#if !defined(SCI_ONLY) 464#if !defined(SCI_ONLY)
504 if (port->type == PORT_SCIF) { 465 if (port->type == PORT_SCIF)
505#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) 466 count = scif_rxroom(port);
506 count = sci_in(port, SCRFDR) & 0x7f; 467 else
507#else
508 count = sci_in(port, SCFDR)&SCIF_RFDC_MASK ;
509#endif
510 } else {
511 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
512 }
513#else
514 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
515#endif 468#endif
469 count = sci_rxroom(port);
516 470
517 /* Don't copy more bytes than there is room for in the buffer */ 471 /* Don't copy more bytes than there is room for in the buffer */
518 count = tty_buffer_request_room(tty, count); 472 count = tty_buffer_request_room(tty, count);
@@ -523,11 +477,10 @@ static inline void sci_receive_chars(struct uart_port *port,
523 477
524 if (port->type == PORT_SCI) { 478 if (port->type == PORT_SCI) {
525 char c = sci_in(port, SCxRDR); 479 char c = sci_in(port, SCxRDR);
526 if(((struct sci_port *)port)->break_flag 480 if (uart_handle_sysrq_char(port, c, regs) || sci_port->break_flag)
527 || uart_handle_sysrq_char(port, c, regs)) {
528 count = 0; 481 count = 0;
529 } else { 482 else {
530 tty_insert_flip_char(tty, c, TTY_NORMAL); 483 tty_insert_flip_char(tty, c, TTY_NORMAL);
531 } 484 }
532 } else { 485 } else {
533 for (i=0; i<count; i++) { 486 for (i=0; i<count; i++) {
@@ -535,15 +488,17 @@ static inline void sci_receive_chars(struct uart_port *port,
535 status = sci_in(port, SCxSR); 488 status = sci_in(port, SCxSR);
536#if defined(CONFIG_CPU_SH3) 489#if defined(CONFIG_CPU_SH3)
537 /* Skip "chars" during break */ 490 /* Skip "chars" during break */
538 if (((struct sci_port *)port)->break_flag) { 491 if (sci_port->break_flag) {
539 if ((c == 0) && 492 if ((c == 0) &&
540 (status & SCxSR_FER(port))) { 493 (status & SCxSR_FER(port))) {
541 count--; i--; 494 count--; i--;
542 continue; 495 continue;
543 } 496 }
497
544 /* Nonzero => end-of-break */ 498 /* Nonzero => end-of-break */
545 pr_debug("scif: debounce<%02x>\n", c); 499 pr_debug("scif: debounce<%02x>\n", c);
546 ((struct sci_port *)port)->break_flag = 0; 500 sci_port->break_flag = 0;
501
547 if (STEPFN(c)) { 502 if (STEPFN(c)) {
548 count--; i--; 503 count--; i--;
549 continue; 504 continue;
@@ -600,15 +555,17 @@ static void sci_schedule_break_timer(struct sci_port *port)
600/* Ensure that two consecutive samples find the break over. */ 555/* Ensure that two consecutive samples find the break over. */
601static void sci_break_timer(unsigned long data) 556static void sci_break_timer(unsigned long data)
602{ 557{
603 struct sci_port * port = (struct sci_port *)data; 558 struct sci_port *port = (struct sci_port *)data;
604 if(sci_rxd_in(&port->port) == 0) { 559
560 if (sci_rxd_in(&port->port) == 0) {
605 port->break_flag = 1; 561 port->break_flag = 1;
606 sci_schedule_break_timer(port); 562 sci_schedule_break_timer(port);
607 } else if(port->break_flag == 1){ 563 } else if (port->break_flag == 1) {
608 /* break is over. */ 564 /* break is over. */
609 port->break_flag = 2; 565 port->break_flag = 2;
610 sci_schedule_break_timer(port); 566 sci_schedule_break_timer(port);
611 } else port->break_flag = 0; 567 } else
568 port->break_flag = 0;
612} 569}
613 570
614static inline int sci_handle_errors(struct uart_port *port) 571static inline int sci_handle_errors(struct uart_port *port)
@@ -617,40 +574,41 @@ static inline int sci_handle_errors(struct uart_port *port)
617 unsigned short status = sci_in(port, SCxSR); 574 unsigned short status = sci_in(port, SCxSR);
618 struct tty_struct *tty = port->info->tty; 575 struct tty_struct *tty = port->info->tty;
619 576
620 if (status&SCxSR_ORER(port)) { 577 if (status & SCxSR_ORER(port)) {
621 /* overrun error */ 578 /* overrun error */
622 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 579 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
623 copied++; 580 copied++;
624 pr_debug("sci: overrun error\n"); 581 pr_debug("sci: overrun error\n");
625 } 582 }
626 583
627 if (status&SCxSR_FER(port)) { 584 if (status & SCxSR_FER(port)) {
628 if (sci_rxd_in(port) == 0) { 585 if (sci_rxd_in(port) == 0) {
629 /* Notify of BREAK */ 586 /* Notify of BREAK */
630 struct sci_port * sci_port = (struct sci_port *)port; 587 struct sci_port *sci_port = (struct sci_port *)port;
631 if(!sci_port->break_flag) { 588
632 sci_port->break_flag = 1; 589 if (!sci_port->break_flag) {
633 sci_schedule_break_timer((struct sci_port *)port); 590 sci_port->break_flag = 1;
591 sci_schedule_break_timer(sci_port);
592
634 /* Do sysrq handling. */ 593 /* Do sysrq handling. */
635 if(uart_handle_break(port)) 594 if (uart_handle_break(port))
636 return 0; 595 return 0;
637 pr_debug("sci: BREAK detected\n"); 596 pr_debug("sci: BREAK detected\n");
638 if(tty_insert_flip_char(tty, 0, TTY_BREAK)) 597 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
639 copied++; 598 copied++;
640 } 599 }
641 } 600 } else {
642 else {
643 /* frame error */ 601 /* frame error */
644 if(tty_insert_flip_char(tty, 0, TTY_FRAME)) 602 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
645 copied++; 603 copied++;
646 pr_debug("sci: frame error\n"); 604 pr_debug("sci: frame error\n");
647 } 605 }
648 } 606 }
649 607
650 if (status&SCxSR_PER(port)) { 608 if (status & SCxSR_PER(port)) {
651 if(tty_insert_flip_char(tty, 0, TTY_PARITY))
652 copied++;
653 /* parity error */ 609 /* parity error */
610 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
611 copied++;
654 pr_debug("sci: parity error\n"); 612 pr_debug("sci: parity error\n");
655 } 613 }
656 614
@@ -673,7 +631,7 @@ static inline int sci_handle_breaks(struct uart_port *port)
673 s->break_flag = 1; 631 s->break_flag = 1;
674#endif 632#endif
675 /* Notify of BREAK */ 633 /* Notify of BREAK */
676 if(tty_insert_flip_char(tty, 0, TTY_BREAK)) 634 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
677 copied++; 635 copied++;
678 pr_debug("sci: BREAK detected\n"); 636 pr_debug("sci: BREAK detected\n");
679 } 637 }
@@ -682,7 +640,7 @@ static inline int sci_handle_breaks(struct uart_port *port)
682 /* XXX: Handle SCIF overrun error */ 640 /* XXX: Handle SCIF overrun error */
683 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) { 641 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
684 sci_out(port, SCLSR, 0); 642 sci_out(port, SCLSR, 0);
685 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN)) { 643 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
686 copied++; 644 copied++;
687 pr_debug("sci: overrun error\n"); 645 pr_debug("sci: overrun error\n");
688 } 646 }
@@ -691,13 +649,12 @@ static inline int sci_handle_breaks(struct uart_port *port)
691 649
692 if (copied) 650 if (copied)
693 tty_flip_buffer_push(tty); 651 tty_flip_buffer_push(tty);
652
694 return copied; 653 return copied;
695} 654}
696 655
697static irqreturn_t sci_rx_interrupt(int irq, void *ptr, struct pt_regs *regs) 656static irqreturn_t sci_rx_interrupt(int irq, void *port, struct pt_regs *regs)
698{ 657{
699 struct uart_port *port = ptr;
700
701 /* I think sci_receive_chars has to be called irrespective 658 /* I think sci_receive_chars has to be called irrespective
702 * of whether the I_IXOFF is set, otherwise, how is the interrupt 659 * of whether the I_IXOFF is set, otherwise, how is the interrupt
703 * to be disabled? 660 * to be disabled?
@@ -711,7 +668,9 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr, struct pt_regs *regs)
711{ 668{
712 struct uart_port *port = ptr; 669 struct uart_port *port = ptr;
713 670
671 spin_lock_irq(&port->lock);
714 sci_transmit_chars(port); 672 sci_transmit_chars(port);
673 spin_unlock_irq(&port->lock);
715 674
716 return IRQ_HANDLED; 675 return IRQ_HANDLED;
717} 676}
@@ -755,6 +714,12 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr, struct pt_regs *regs)
755 714
756 /* Handle BREAKs */ 715 /* Handle BREAKs */
757 sci_handle_breaks(port); 716 sci_handle_breaks(port);
717
718#ifdef CONFIG_SH_KGDB
719 /* Break into the debugger if a break is detected */
720 BREAKPOINT();
721#endif
722
758 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 723 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
759 724
760 return IRQ_HANDLED; 725 return IRQ_HANDLED;
@@ -769,16 +734,16 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
769 scr_status = sci_in(port,SCSCR); 734 scr_status = sci_in(port,SCSCR);
770 735
771 /* Tx Interrupt */ 736 /* Tx Interrupt */
772 if ((ssr_status&0x0020) && (scr_status&0x0080)) 737 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
773 sci_tx_interrupt(irq, ptr, regs); 738 sci_tx_interrupt(irq, ptr, regs);
774 /* Rx Interrupt */ 739 /* Rx Interrupt */
775 if ((ssr_status&0x0002) && (scr_status&0x0040)) 740 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
776 sci_rx_interrupt(irq, ptr, regs); 741 sci_rx_interrupt(irq, ptr, regs);
777 /* Error Interrupt */ 742 /* Error Interrupt */
778 if ((ssr_status&0x0080) && (scr_status&0x0400)) 743 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
779 sci_er_interrupt(irq, ptr, regs); 744 sci_er_interrupt(irq, ptr, regs);
780 /* Break Interrupt */ 745 /* Break Interrupt */
781 if ((ssr_status&0x0010) && (scr_status&0x0200)) 746 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
782 sci_br_interrupt(irq, ptr, regs); 747 sci_br_interrupt(irq, ptr, regs);
783 748
784 return IRQ_HANDLED; 749 return IRQ_HANDLED;
@@ -789,7 +754,8 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
789 * Here we define a transistion notifier so that we can update all of our 754 * Here we define a transistion notifier so that we can update all of our
790 * ports' baud rate when the peripheral clock changes. 755 * ports' baud rate when the peripheral clock changes.
791 */ 756 */
792static int sci_notifier(struct notifier_block *self, unsigned long phase, void *p) 757static int sci_notifier(struct notifier_block *self,
758 unsigned long phase, void *p)
793{ 759{
794 struct cpufreq_freqs *freqs = p; 760 struct cpufreq_freqs *freqs = p;
795 int i; 761 int i;
@@ -816,8 +782,9 @@ static int sci_notifier(struct notifier_block *self, unsigned long phase, void *
816 clk_put(clk); 782 clk_put(clk);
817 } 783 }
818 784
819 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n", 785 printk(KERN_INFO "%s: got a postchange notification "
820 __FUNCTION__, freqs->cpu, freqs->old, freqs->new); 786 "for cpu %d (old %d, new %d)\n",
787 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
821 } 788 }
822 789
823 return NOTIFY_OK; 790 return NOTIFY_OK;
@@ -841,8 +808,9 @@ static int sci_request_irq(struct sci_port *port)
841 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n"); 808 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
842 return -ENODEV; 809 return -ENODEV;
843 } 810 }
844 if (request_irq(port->irqs[0], sci_mpxed_interrupt, IRQF_DISABLED, 811
845 "sci", port)) { 812 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
813 SA_INTERRUPT, "sci", port)) {
846 printk(KERN_ERR "sci: Cannot allocate irq.\n"); 814 printk(KERN_ERR "sci: Cannot allocate irq.\n");
847 return -ENODEV; 815 return -ENODEV;
848 } 816 }
@@ -850,8 +818,8 @@ static int sci_request_irq(struct sci_port *port)
850 for (i = 0; i < ARRAY_SIZE(handlers); i++) { 818 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
851 if (!port->irqs[i]) 819 if (!port->irqs[i])
852 continue; 820 continue;
853 if (request_irq(port->irqs[i], handlers[i], IRQF_DISABLED, 821 if (request_irq(port->irqs[i], handlers[i],
854 desc[i], port)) { 822 SA_INTERRUPT, desc[i], port)) {
855 printk(KERN_ERR "sci: Cannot allocate irq.\n"); 823 printk(KERN_ERR "sci: Cannot allocate irq.\n");
856 return -ENODEV; 824 return -ENODEV;
857 } 825 }
@@ -903,50 +871,42 @@ static unsigned int sci_get_mctrl(struct uart_port *port)
903 871
904static void sci_start_tx(struct uart_port *port) 872static void sci_start_tx(struct uart_port *port)
905{ 873{
906 struct sci_port *s = &sci_ports[port->line]; 874 unsigned short ctrl;
907 875
908 disable_irq(s->irqs[SCIx_TXI_IRQ]); 876 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
909 sci_transmit_chars(port); 877 ctrl = sci_in(port, SCSCR);
910 enable_irq(s->irqs[SCIx_TXI_IRQ]); 878 ctrl |= SCI_CTRL_FLAGS_TIE;
879 sci_out(port, SCSCR, ctrl);
911} 880}
912 881
913static void sci_stop_tx(struct uart_port *port) 882static void sci_stop_tx(struct uart_port *port)
914{ 883{
915 unsigned long flags;
916 unsigned short ctrl; 884 unsigned short ctrl;
917 885
918 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 886 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
919 local_irq_save(flags);
920 ctrl = sci_in(port, SCSCR); 887 ctrl = sci_in(port, SCSCR);
921 ctrl &= ~SCI_CTRL_FLAGS_TIE; 888 ctrl &= ~SCI_CTRL_FLAGS_TIE;
922 sci_out(port, SCSCR, ctrl); 889 sci_out(port, SCSCR, ctrl);
923 local_irq_restore(flags);
924} 890}
925 891
926static void sci_start_rx(struct uart_port *port, unsigned int tty_start) 892static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
927{ 893{
928 unsigned long flags;
929 unsigned short ctrl; 894 unsigned short ctrl;
930 895
931 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ 896 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
932 local_irq_save(flags);
933 ctrl = sci_in(port, SCSCR); 897 ctrl = sci_in(port, SCSCR);
934 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; 898 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
935 sci_out(port, SCSCR, ctrl); 899 sci_out(port, SCSCR, ctrl);
936 local_irq_restore(flags);
937} 900}
938 901
939static void sci_stop_rx(struct uart_port *port) 902static void sci_stop_rx(struct uart_port *port)
940{ 903{
941 unsigned long flags;
942 unsigned short ctrl; 904 unsigned short ctrl;
943 905
944 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ 906 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
945 local_irq_save(flags);
946 ctrl = sci_in(port, SCSCR); 907 ctrl = sci_in(port, SCSCR);
947 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); 908 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
948 sci_out(port, SCSCR, ctrl); 909 sci_out(port, SCSCR, ctrl);
949 local_irq_restore(flags);
950} 910}
951 911
952static void sci_enable_ms(struct uart_port *port) 912static void sci_enable_ms(struct uart_port *port)
@@ -963,9 +923,8 @@ static int sci_startup(struct uart_port *port)
963{ 923{
964 struct sci_port *s = &sci_ports[port->line]; 924 struct sci_port *s = &sci_ports[port->line];
965 925
966#if defined(__H8300S__) 926 if (s->enable)
967 h8300_sci_enable(port, sci_enable); 927 s->enable(port);
968#endif
969 928
970 sci_request_irq(s); 929 sci_request_irq(s);
971 sci_start_tx(port); 930 sci_start_tx(port);
@@ -982,9 +941,8 @@ static void sci_shutdown(struct uart_port *port)
982 sci_stop_tx(port); 941 sci_stop_tx(port);
983 sci_free_irq(s); 942 sci_free_irq(s);
984 943
985#if defined(__H8300S__) 944 if (s->disable)
986 h8300_sci_enable(port, sci_disable); 945 s->disable(port);
987#endif
988} 946}
989 947
990static void sci_set_termios(struct uart_port *port, struct termios *termios, 948static void sci_set_termios(struct uart_port *port, struct termios *termios,
@@ -997,6 +955,23 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
997 955
998 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 956 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
999 957
958 switch (baud) {
959 case 0:
960 t = -1;
961 break;
962 default:
963 {
964#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
965 struct clk *clk = clk_get("module_clk");
966 t = SCBRR_VALUE(baud, clk_get_rate(clk));
967 clk_put(clk);
968#else
969 t = SCBRR_VALUE(baud);
970#endif
971 }
972 break;
973 }
974
1000 spin_lock_irqsave(&port->lock, flags); 975 spin_lock_irqsave(&port->lock, flags);
1001 976
1002 do { 977 do {
@@ -1006,9 +981,8 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
1006 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 981 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1007 982
1008#if !defined(SCI_ONLY) 983#if !defined(SCI_ONLY)
1009 if (port->type == PORT_SCIF) { 984 if (port->type == PORT_SCIF)
1010 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 985 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1011 }
1012#endif 986#endif
1013 987
1014 smr_val = sci_in(port, SCSMR) & 3; 988 smr_val = sci_in(port, SCSMR) & 3;
@@ -1025,23 +999,6 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
1025 999
1026 sci_out(port, SCSMR, smr_val); 1000 sci_out(port, SCSMR, smr_val);
1027 1001
1028 switch (baud) {
1029 case 0:
1030 t = -1;
1031 break;
1032 default:
1033 {
1034#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1035 struct clk *clk = clk_get("module_clk");
1036 t = SCBRR_VALUE(baud, clk_get_rate(clk));
1037 clk_put(clk);
1038#else
1039 t = SCBRR_VALUE(baud);
1040#endif
1041 }
1042 break;
1043 }
1044
1045 if (t > 0) { 1002 if (t > 0) {
1046 if(t >= 256) { 1003 if(t >= 256) {
1047 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); 1004 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
@@ -1092,11 +1049,23 @@ static void sci_config_port(struct uart_port *port, int flags)
1092 1049
1093 port->type = s->type; 1050 port->type = s->type;
1094 1051
1052 switch (port->type) {
1053 case PORT_SCI:
1054 s->init_pins = sci_init_pins_sci;
1055 break;
1056 case PORT_SCIF:
1057 s->init_pins = sci_init_pins_scif;
1058 break;
1059 case PORT_IRDA:
1060 s->init_pins = sci_init_pins_irda;
1061 break;
1062 }
1063
1095#if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 1064#if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1096 if (port->mapbase == 0) 1065 if (port->mapbase == 0)
1097 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF"); 1066 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1098 1067
1099 port->membase = (void *)port->mapbase; 1068 port->membase = (void __iomem *)port->mapbase;
1100#endif 1069#endif
1101} 1070}
1102 1071
@@ -1132,412 +1101,61 @@ static struct uart_ops sci_uart_ops = {
1132 .verify_port = sci_verify_port, 1101 .verify_port = sci_verify_port,
1133}; 1102};
1134 1103
1135static struct sci_port sci_ports[] = { 1104static void __init sci_init_ports(void)
1136#if defined(CONFIG_CPU_SUBTYPE_SH7708) 1105{
1137 { 1106 static int first = 1;
1138 .port = { 1107 int i;
1139 .membase = (void *)0xfffffe80, 1108
1140 .mapbase = 0xfffffe80, 1109 if (!first)
1141 .iotype = UPIO_MEM, 1110 return;
1142 .irq = 25, 1111
1143 .ops = &sci_uart_ops, 1112 first = 0;
1144 .flags = UPF_BOOT_AUTOCONF, 1113
1145 .line = 0, 1114 for (i = 0; i < SCI_NPORTS; i++) {
1146 }, 1115 sci_ports[i].port.ops = &sci_uart_ops;
1147 .type = PORT_SCI, 1116 sci_ports[i].port.iotype = UPIO_MEM;
1148 .irqs = SCI_IRQS, 1117 sci_ports[i].port.line = i;
1149 }, 1118 sci_ports[i].port.fifosize = 1;
1150#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 1119
1151 { 1120#if defined(__H8300H__) || defined(__H8300S__)
1152 .port = { 1121#ifdef __H8300S__
1153 .membase = (void *)SCIF0, 1122 sci_ports[i].enable = h8300_sci_enable;
1154 .mapbase = SCIF0, 1123 sci_ports[i].disable = h8300_sci_disable;
1155 .iotype = UPIO_MEM, 1124#endif
1156 .irq = 55, 1125 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1157 .ops = &sci_uart_ops, 1126#elif defined(CONFIG_SUPERH64)
1158 .flags = UPF_BOOT_AUTOCONF, 1127 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1159 .line = 0,
1160 },
1161 .type = PORT_SCIF,
1162 .irqs = SH3_IRDA_IRQS,
1163 .init_pins = sci_init_pins_scif,
1164 },
1165 {
1166 .port = {
1167 .membase = (void *)SCIF2,
1168 .mapbase = SCIF2,
1169 .iotype = UPIO_MEM,
1170 .irq = 59,
1171 .ops = &sci_uart_ops,
1172 .flags = UPF_BOOT_AUTOCONF,
1173 .line = 1,
1174 },
1175 .type = PORT_SCIF,
1176 .irqs = SH3_SCIF_IRQS,
1177 .init_pins = sci_init_pins_scif,
1178 }
1179#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
1180 {
1181 .port = {
1182 .membase = (void *)0xfffffe80,
1183 .mapbase = 0xfffffe80,
1184 .iotype = UPIO_MEM,
1185 .irq = 25,
1186 .ops = &sci_uart_ops,
1187 .flags = UPF_BOOT_AUTOCONF,
1188 .line = 0,
1189 },
1190 .type = PORT_SCI,
1191 .irqs = SCI_IRQS,
1192 },
1193 {
1194 .port = {
1195 .membase = (void *)0xa4000150,
1196 .mapbase = 0xa4000150,
1197 .iotype = UPIO_MEM,
1198 .irq = 59,
1199 .ops = &sci_uart_ops,
1200 .flags = UPF_BOOT_AUTOCONF,
1201 .line = 1,
1202 },
1203 .type = PORT_SCIF,
1204 .irqs = SH3_SCIF_IRQS,
1205 .init_pins = sci_init_pins_scif,
1206 },
1207 {
1208 .port = {
1209 .membase = (void *)0xa4000140,
1210 .mapbase = 0xa4000140,
1211 .iotype = UPIO_MEM,
1212 .irq = 55,
1213 .ops = &sci_uart_ops,
1214 .flags = UPF_BOOT_AUTOCONF,
1215 .line = 2,
1216 },
1217 .type = PORT_IRDA,
1218 .irqs = SH3_IRDA_IRQS,
1219 .init_pins = sci_init_pins_irda,
1220 }
1221#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
1222 {
1223 .port = {
1224 .membase = (void *)0xA4430000,
1225 .mapbase = 0xA4430000,
1226 .iotype = UPIO_MEM,
1227 .irq = 25,
1228 .ops = &sci_uart_ops,
1229 .flags = UPF_BOOT_AUTOCONF,
1230 .line = 0,
1231 },
1232 .type = PORT_SCIF,
1233 .irqs = SH7300_SCIF0_IRQS,
1234 .init_pins = sci_init_pins_scif,
1235 },
1236#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
1237 {
1238 .port = {
1239 .membase = (void *)0xffe00000,
1240 .mapbase = 0xffe00000,
1241 .iotype = UPIO_MEM,
1242 .irq = 25,
1243 .ops = &sci_uart_ops,
1244 .flags = UPF_BOOT_AUTOCONF,
1245 .line = 0,
1246 },
1247 .type = PORT_SCIF,
1248 .irqs = SH73180_SCIF_IRQS,
1249 .init_pins = sci_init_pins_scif,
1250 },
1251#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1252 {
1253 .port = {
1254 .membase = (void *)0xffe80000,
1255 .mapbase = 0xffe80000,
1256 .iotype = UPIO_MEM,
1257 .irq = 43,
1258 .ops = &sci_uart_ops,
1259 .flags = UPF_BOOT_AUTOCONF,
1260 .line = 0,
1261 },
1262 .type = PORT_SCIF,
1263 .irqs = SH4_SCIF_IRQS,
1264 .init_pins = sci_init_pins_scif,
1265 },
1266#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1267 {
1268 .port = {
1269 .membase = (void *)0xffe00000,
1270 .mapbase = 0xffe00000,
1271 .iotype = UPIO_MEM,
1272 .irq = 25,
1273 .ops = &sci_uart_ops,
1274 .flags = UPF_BOOT_AUTOCONF,
1275 .line = 0,
1276 },
1277 .type = PORT_SCI,
1278 .irqs = SCI_IRQS,
1279 },
1280 {
1281 .port = {
1282 .membase = (void *)0xffe80000,
1283 .mapbase = 0xffe80000,
1284 .iotype = UPIO_MEM,
1285 .irq = 43,
1286 .ops = &sci_uart_ops,
1287 .flags = UPF_BOOT_AUTOCONF,
1288 .line = 1,
1289 },
1290 .type = PORT_SCIF,
1291 .irqs = SH4_SCIF_IRQS,
1292 .init_pins = sci_init_pins_scif,
1293 },
1294#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
1295 {
1296 .port = {
1297 .membase = (void *)0xfe600000,
1298 .mapbase = 0xfe600000,
1299 .iotype = UPIO_MEM,
1300 .irq = 55,
1301 .ops = &sci_uart_ops,
1302 .flags = UPF_BOOT_AUTOCONF,
1303 .line = 0,
1304 },
1305 .type = PORT_SCIF,
1306 .irqs = SH7760_SCIF0_IRQS,
1307 .init_pins = sci_init_pins_scif,
1308 },
1309 {
1310 .port = {
1311 .membase = (void *)0xfe610000,
1312 .mapbase = 0xfe610000,
1313 .iotype = UPIO_MEM,
1314 .irq = 75,
1315 .ops = &sci_uart_ops,
1316 .flags = UPF_BOOT_AUTOCONF,
1317 .line = 1,
1318 },
1319 .type = PORT_SCIF,
1320 .irqs = SH7760_SCIF1_IRQS,
1321 .init_pins = sci_init_pins_scif,
1322 },
1323 {
1324 .port = {
1325 .membase = (void *)0xfe620000,
1326 .mapbase = 0xfe620000,
1327 .iotype = UPIO_MEM,
1328 .irq = 79,
1329 .ops = &sci_uart_ops,
1330 .flags = UPF_BOOT_AUTOCONF,
1331 .line = 2,
1332 },
1333 .type = PORT_SCIF,
1334 .irqs = SH7760_SCIF2_IRQS,
1335 .init_pins = sci_init_pins_scif,
1336 },
1337#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1338 {
1339 .port = {
1340 .membase = (void *)0xffe00000,
1341 .mapbase = 0xffe00000,
1342 .iotype = UPIO_MEM,
1343 .irq = 26,
1344 .ops = &sci_uart_ops,
1345 .flags = UPF_BOOT_AUTOCONF,
1346 .line = 0,
1347 },
1348 .type = PORT_SCIF,
1349 .irqs = STB1_SCIF1_IRQS,
1350 .init_pins = sci_init_pins_scif,
1351 },
1352 {
1353 .port = {
1354 .membase = (void *)0xffe80000,
1355 .mapbase = 0xffe80000,
1356 .iotype = UPIO_MEM,
1357 .irq = 43,
1358 .ops = &sci_uart_ops,
1359 .flags = UPF_BOOT_AUTOCONF,
1360 .line = 1,
1361 },
1362 .type = PORT_SCIF,
1363 .irqs = SH4_SCIF_IRQS,
1364 .init_pins = sci_init_pins_scif,
1365 },
1366#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1367 {
1368 .port = {
1369 .iotype = UPIO_MEM,
1370 .irq = 42,
1371 .ops = &sci_uart_ops,
1372 .flags = UPF_BOOT_AUTOCONF,
1373 .line = 0,
1374 },
1375 .type = PORT_SCIF,
1376 .irqs = SH5_SCIF_IRQS,
1377 .init_pins = sci_init_pins_scif,
1378 },
1379#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1380 {
1381 .port = {
1382 .membase = (void *)0x00ffffb0,
1383 .mapbase = 0x00ffffb0,
1384 .iotype = UPIO_MEM,
1385 .irq = 54,
1386 .ops = &sci_uart_ops,
1387 .flags = UPF_BOOT_AUTOCONF,
1388 .line = 0,
1389 },
1390 .type = PORT_SCI,
1391 .irqs = H8300H_SCI_IRQS0,
1392 .init_pins = sci_init_pins_sci,
1393 },
1394 {
1395 .port = {
1396 .membase = (void *)0x00ffffb8,
1397 .mapbase = 0x00ffffb8,
1398 .iotype = UPIO_MEM,
1399 .irq = 58,
1400 .ops = &sci_uart_ops,
1401 .flags = UPF_BOOT_AUTOCONF,
1402 .line = 1,
1403 },
1404 .type = PORT_SCI,
1405 .irqs = H8300H_SCI_IRQS1,
1406 .init_pins = sci_init_pins_sci,
1407 },
1408 {
1409 .port = {
1410 .membase = (void *)0x00ffffc0,
1411 .mapbase = 0x00ffffc0,
1412 .iotype = UPIO_MEM,
1413 .irq = 62,
1414 .ops = &sci_uart_ops,
1415 .flags = UPF_BOOT_AUTOCONF,
1416 .line = 2,
1417 },
1418 .type = PORT_SCI,
1419 .irqs = H8300H_SCI_IRQS2,
1420 .init_pins = sci_init_pins_sci,
1421 },
1422#elif defined(CONFIG_H8S2678)
1423 {
1424 .port = {
1425 .membase = (void *)0x00ffff78,
1426 .mapbase = 0x00ffff78,
1427 .iotype = UPIO_MEM,
1428 .irq = 90,
1429 .ops = &sci_uart_ops,
1430 .flags = UPF_BOOT_AUTOCONF,
1431 .line = 0,
1432 },
1433 .type = PORT_SCI,
1434 .irqs = H8S_SCI_IRQS0,
1435 .init_pins = sci_init_pins_sci,
1436 },
1437 {
1438 .port = {
1439 .membase = (void *)0x00ffff80,
1440 .mapbase = 0x00ffff80,
1441 .iotype = UPIO_MEM,
1442 .irq = 94,
1443 .ops = &sci_uart_ops,
1444 .flags = UPF_BOOT_AUTOCONF,
1445 .line = 1,
1446 },
1447 .type = PORT_SCI,
1448 .irqs = H8S_SCI_IRQS1,
1449 .init_pins = sci_init_pins_sci,
1450 },
1451 {
1452 .port = {
1453 .membase = (void *)0x00ffff88,
1454 .mapbase = 0x00ffff88,
1455 .iotype = UPIO_MEM,
1456 .irq = 98,
1457 .ops = &sci_uart_ops,
1458 .flags = UPF_BOOT_AUTOCONF,
1459 .line = 2,
1460 },
1461 .type = PORT_SCI,
1462 .irqs = H8S_SCI_IRQS2,
1463 .init_pins = sci_init_pins_sci,
1464 },
1465#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
1466 {
1467 .port = {
1468 .membase = (void *)0xff923000,
1469 .mapbase = 0xff923000,
1470 .iotype = UPIO_MEM,
1471 .irq = 61,
1472 .ops = &sci_uart_ops,
1473 .flags = UPF_BOOT_AUTOCONF,
1474 .line = 0,
1475 },
1476 .type = PORT_SCIF,
1477 .irqs = SH7770_SCIF0_IRQS,
1478 .init_pins = sci_init_pins_scif,
1479 },
1480 {
1481 .port = {
1482 .membase = (void *)0xff924000,
1483 .mapbase = 0xff924000,
1484 .iotype = UPIO_MEM,
1485 .irq = 62,
1486 .ops = &sci_uart_ops,
1487 .flags = UPF_BOOT_AUTOCONF,
1488 .line = 1,
1489 },
1490 .type = PORT_SCIF,
1491 .irqs = SH7770_SCIF1_IRQS,
1492 .init_pins = sci_init_pins_scif,
1493 },
1494 {
1495 .port = {
1496 .membase = (void *)0xff925000,
1497 .mapbase = 0xff925000,
1498 .iotype = UPIO_MEM,
1499 .irq = 63,
1500 .ops = &sci_uart_ops,
1501 .flags = UPF_BOOT_AUTOCONF,
1502 .line = 2,
1503 },
1504 .type = PORT_SCIF,
1505 .irqs = SH7770_SCIF2_IRQS,
1506 .init_pins = sci_init_pins_scif,
1507 },
1508#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
1509 {
1510 .port = {
1511 .membase = (void *)0xffe00000,
1512 .mapbase = 0xffe00000,
1513 .iotype = UPIO_MEM,
1514 .irq = 43,
1515 .ops = &sci_uart_ops,
1516 .flags = UPF_BOOT_AUTOCONF,
1517 .line = 0,
1518 },
1519 .type = PORT_SCIF,
1520 .irqs = SH7780_SCIF0_IRQS,
1521 .init_pins = sci_init_pins_scif,
1522 },
1523 {
1524 .port = {
1525 .membase = (void *)0xffe10000,
1526 .mapbase = 0xffe10000,
1527 .iotype = UPIO_MEM,
1528 .irq = 79,
1529 .ops = &sci_uart_ops,
1530 .flags = UPF_BOOT_AUTOCONF,
1531 .line = 1,
1532 },
1533 .type = PORT_SCIF,
1534 .irqs = SH7780_SCIF1_IRQS,
1535 .init_pins = sci_init_pins_scif,
1536 },
1537#else 1128#else
1538#error "CPU subtype not defined" 1129 /*
1130 * XXX: We should use a proper SCI/SCIF clock
1131 */
1132 {
1133 struct clk *clk = clk_get("module_clk");
1134 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1135 clk_put(clk);
1136 }
1539#endif 1137#endif
1540}; 1138
1139 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1140 sci_ports[i].break_timer.function = sci_break_timer;
1141
1142 init_timer(&sci_ports[i].break_timer);
1143 }
1144}
1145
1146int __init early_sci_setup(struct uart_port *port)
1147{
1148 if (unlikely(port->line > SCI_NPORTS))
1149 return -ENODEV;
1150
1151 sci_init_ports();
1152
1153 sci_ports[port->line].port.membase = port->membase;
1154 sci_ports[port->line].port.mapbase = port->mapbase;
1155 sci_ports[port->line].port.type = port->type;
1156
1157 return 0;
1158}
1541 1159
1542#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1160#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1543/* 1161/*
@@ -1559,34 +1177,38 @@ static int __init serial_console_setup(struct console *co, char *options)
1559 int flow = 'n'; 1177 int flow = 'n';
1560 int ret; 1178 int ret;
1561 1179
1180 /*
1181 * Check whether an invalid uart number has been specified, and
1182 * if so, search for the first available port that does have
1183 * console support.
1184 */
1185 if (co->index >= SCI_NPORTS)
1186 co->index = 0;
1187
1562 serial_console_port = &sci_ports[co->index]; 1188 serial_console_port = &sci_ports[co->index];
1563 port = &serial_console_port->port; 1189 port = &serial_console_port->port;
1564 port->type = serial_console_port->type;
1565
1566#ifdef CONFIG_SUPERH64
1567 /* This is especially needed on sh64 to remap the SCIF */
1568 sci_config_port(port, 0);
1569#endif
1570 1190
1571 /* 1191 /*
1572 * We need to set the initial uartclk here, since otherwise it will 1192 * Also need to check port->type, we don't actually have any
1573 * only ever be setup at sci_init() time. 1193 * UPIO_PORT ports, but uart_report_port() handily misreports
1194 * it anyways if we don't have a port available by the time this is
1195 * called.
1574 */ 1196 */
1575#if defined(__H8300H__) || defined(__H8300S__) 1197 if (!port->type)
1576 port->uartclk = CONFIG_CPU_CLOCK; 1198 return -ENODEV;
1199 if (!port->membase || !port->mapbase)
1200 return -ENODEV;
1201
1202 spin_lock_init(&port->lock);
1203
1204 port->type = serial_console_port->type;
1205
1206 if (port->flags & UPF_IOREMAP)
1207 sci_config_port(port, 0);
1208
1209 if (serial_console_port->enable)
1210 serial_console_port->enable(port);
1577 1211
1578#if defined(__H8300S__)
1579 h8300_sci_enable(port, sci_enable);
1580#endif
1581#elif defined(CONFIG_SUPERH64)
1582 port->uartclk = current_cpu_data.module_clock * 16;
1583#else
1584 {
1585 struct clk *clk = clk_get("module_clk");
1586 port->uartclk = clk_get_rate(clk) * 16;
1587 clk_put(clk);
1588 }
1589#endif
1590 if (options) 1212 if (options)
1591 uart_parse_options(options, &baud, &parity, &bits, &flow); 1213 uart_parse_options(options, &baud, &parity, &bits, &flow);
1592 1214
@@ -1604,17 +1226,17 @@ static struct console serial_console = {
1604 .device = uart_console_device, 1226 .device = uart_console_device,
1605 .write = serial_console_write, 1227 .write = serial_console_write,
1606 .setup = serial_console_setup, 1228 .setup = serial_console_setup,
1607 .flags = CON_PRINTBUFFER, 1229 .flags = CON_PRINTBUFFER,
1608 .index = -1, 1230 .index = -1,
1609 .data = &sci_uart_driver, 1231 .data = &sci_uart_driver,
1610}; 1232};
1611 1233
1612static int __init sci_console_init(void) 1234static int __init sci_console_init(void)
1613{ 1235{
1236 sci_init_ports();
1614 register_console(&serial_console); 1237 register_console(&serial_console);
1615 return 0; 1238 return 0;
1616} 1239}
1617
1618console_initcall(sci_console_init); 1240console_initcall(sci_console_init);
1619#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 1241#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1620 1242
@@ -1649,6 +1271,8 @@ int __init kgdb_console_setup(struct console *co, char *options)
1649 int parity = 'n'; 1271 int parity = 'n';
1650 int flow = 'n'; 1272 int flow = 'n';
1651 1273
1274 spin_lock_init(&port->lock);
1275
1652 if (co->index != kgdb_portnum) 1276 if (co->index != kgdb_portnum)
1653 co->index = kgdb_portnum; 1277 co->index = kgdb_portnum;
1654 1278
@@ -1677,10 +1301,10 @@ static struct console kgdb_console = {
1677/* Register the KGDB console so we get messages (d'oh!) */ 1301/* Register the KGDB console so we get messages (d'oh!) */
1678static int __init kgdb_console_init(void) 1302static int __init kgdb_console_init(void)
1679{ 1303{
1304 sci_init_ports();
1680 register_console(&kgdb_console); 1305 register_console(&kgdb_console);
1681 return 0; 1306 return 0;
1682} 1307}
1683
1684console_initcall(kgdb_console_init); 1308console_initcall(kgdb_console_init);
1685#endif /* CONFIG_SH_KGDB_CONSOLE */ 1309#endif /* CONFIG_SH_KGDB_CONSOLE */
1686 1310
@@ -1701,60 +1325,132 @@ static struct uart_driver sci_uart_driver = {
1701 .dev_name = "ttySC", 1325 .dev_name = "ttySC",
1702 .major = SCI_MAJOR, 1326 .major = SCI_MAJOR,
1703 .minor = SCI_MINOR_START, 1327 .minor = SCI_MINOR_START,
1328 .nr = SCI_NPORTS,
1704 .cons = SCI_CONSOLE, 1329 .cons = SCI_CONSOLE,
1705}; 1330};
1706 1331
1707static int __init sci_init(void) 1332/*
1333 * Register a set of serial devices attached to a platform device. The
1334 * list is terminated with a zero flags entry, which means we expect
1335 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1336 * remapping (such as sh64) should also set UPF_IOREMAP.
1337 */
1338static int __devinit sci_probe(struct platform_device *dev)
1708{ 1339{
1709 int chan, ret; 1340 struct plat_sci_port *p = dev->dev.platform_data;
1341 int i;
1710 1342
1711 printk("%s", banner); 1343 for (i = 0; p && p->flags != 0 && i < SCI_NPORTS; p++, i++) {
1344 struct sci_port *sciport = &sci_ports[i];
1712 1345
1713 sci_uart_driver.nr = ARRAY_SIZE(sci_ports); 1346 sciport->port.mapbase = p->mapbase;
1714 1347
1715 ret = uart_register_driver(&sci_uart_driver); 1348 /*
1716 if (ret == 0) { 1349 * For the simple (and majority of) cases where we don't need
1717 for (chan = 0; chan < SCI_NPORTS; chan++) { 1350 * to do any remapping, just cast the cookie directly.
1718 struct sci_port *sciport = &sci_ports[chan]; 1351 */
1352 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1353 p->membase = (void __iomem *)p->mapbase;
1719 1354
1720#if defined(__H8300H__) || defined(__H8300S__) 1355 sciport->port.membase = p->membase;
1721 sciport->port.uartclk = CONFIG_CPU_CLOCK; 1356
1722#elif defined(CONFIG_SUPERH64) 1357 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1723 sciport->port.uartclk = current_cpu_data.module_clock * 16; 1358 sciport->port.flags = p->flags;
1724#else 1359 sciport->port.dev = &dev->dev;
1725 struct clk *clk = clk_get("module_clk"); 1360
1726 sciport->port.uartclk = clk_get_rate(clk) * 16; 1361 sciport->type = sciport->port.type = p->type;
1727 clk_put(clk); 1362
1728#endif 1363 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1729 uart_add_one_port(&sci_uart_driver, &sciport->port); 1364
1730 sciport->break_timer.data = (unsigned long)sciport; 1365 uart_add_one_port(&sci_uart_driver, &sciport->port);
1731 sciport->break_timer.function = sci_break_timer;
1732 init_timer(&sciport->break_timer);
1733 }
1734 } 1366 }
1735 1367
1736#ifdef CONFIG_CPU_FREQ 1368#ifdef CONFIG_CPU_FREQ
1737 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER); 1369 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1738 printk("sci: CPU frequency notifier registered\n"); 1370 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n");
1739#endif 1371#endif
1740 1372
1741#ifdef CONFIG_SH_STANDARD_BIOS 1373#ifdef CONFIG_SH_STANDARD_BIOS
1742 sh_bios_gdb_detach(); 1374 sh_bios_gdb_detach();
1743#endif 1375#endif
1744 1376
1745 return ret; 1377 return 0;
1746} 1378}
1747 1379
1748static void __exit sci_exit(void) 1380static int __devexit sci_remove(struct platform_device *dev)
1381{
1382 int i;
1383
1384 for (i = 0; i < SCI_NPORTS; i++)
1385 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1386
1387 return 0;
1388}
1389
1390static int sci_suspend(struct platform_device *dev, pm_message_t state)
1749{ 1391{
1750 int chan; 1392 int i;
1393
1394 for (i = 0; i < SCI_NPORTS; i++) {
1395 struct sci_port *p = &sci_ports[i];
1396
1397 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1398 uart_suspend_port(&sci_uart_driver, &p->port);
1399 }
1751 1400
1752 for (chan = 0; chan < SCI_NPORTS; chan++) 1401 return 0;
1753 uart_remove_one_port(&sci_uart_driver, &sci_ports[chan].port); 1402}
1754 1403
1404static int sci_resume(struct platform_device *dev)
1405{
1406 int i;
1407
1408 for (i = 0; i < SCI_NPORTS; i++) {
1409 struct sci_port *p = &sci_ports[i];
1410
1411 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1412 uart_resume_port(&sci_uart_driver, &p->port);
1413 }
1414
1415 return 0;
1416}
1417
1418static struct platform_driver sci_driver = {
1419 .probe = sci_probe,
1420 .remove = __devexit_p(sci_remove),
1421 .suspend = sci_suspend,
1422 .resume = sci_resume,
1423 .driver = {
1424 .name = "sh-sci",
1425 .owner = THIS_MODULE,
1426 },
1427};
1428
1429static int __init sci_init(void)
1430{
1431 int ret;
1432
1433 printk(banner);
1434
1435 sci_init_ports();
1436
1437 ret = uart_register_driver(&sci_uart_driver);
1438 if (likely(ret == 0)) {
1439 ret = platform_driver_register(&sci_driver);
1440 if (unlikely(ret))
1441 uart_unregister_driver(&sci_uart_driver);
1442 }
1443
1444 return ret;
1445}
1446
1447static void __exit sci_exit(void)
1448{
1449 platform_driver_unregister(&sci_driver);
1755 uart_unregister_driver(&sci_uart_driver); 1450 uart_unregister_driver(&sci_uart_driver);
1756} 1451}
1757 1452
1758module_init(sci_init); 1453module_init(sci_init);
1759module_exit(sci_exit); 1454module_exit(sci_exit);
1760 1455
1456MODULE_LICENSE("GPL");
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index ab320fa3237c..28643c4dc850 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -10,7 +10,9 @@
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003). 10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004). 11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 */ 12 */
13#include <linux/config.h>
13#include <linux/serial_core.h> 14#include <linux/serial_core.h>
15#include <asm/io.h>
14 16
15#if defined(__H8300H__) || defined(__H8300S__) 17#if defined(__H8300H__) || defined(__H8300S__)
16#include <asm/gpio.h> 18#include <asm/gpio.h>
@@ -22,40 +24,13 @@
22#endif 24#endif
23#endif 25#endif
24 26
25/* Offsets into the sci_port->irqs array */
26#define SCIx_ERI_IRQ 0
27#define SCIx_RXI_IRQ 1
28#define SCIx_TXI_IRQ 2
29
30/* ERI, RXI, TXI, BRI */
31#define SCI_IRQS { 23, 24, 25, 0 }
32#define SH3_SCIF_IRQS { 56, 57, 59, 58 }
33#define SH3_IRDA_IRQS { 52, 53, 55, 54 }
34#define SH4_SCIF_IRQS { 40, 41, 43, 42 }
35#define STB1_SCIF1_IRQS {23, 24, 26, 25 }
36#define SH7760_SCIF0_IRQS { 52, 53, 55, 54 }
37#define SH7760_SCIF1_IRQS { 72, 73, 75, 74 }
38#define SH7760_SCIF2_IRQS { 76, 77, 79, 78 }
39#define SH7300_SCIF0_IRQS {80, 80, 80, 80 }
40#define SH73180_SCIF_IRQS {80, 81, 83, 82 }
41#define H8300H_SCI_IRQS0 {52, 53, 54, 0 }
42#define H8300H_SCI_IRQS1 {56, 57, 58, 0 }
43#define H8300H_SCI_IRQS2 {60, 61, 62, 0 }
44#define H8S_SCI_IRQS0 {88, 89, 90, 0 }
45#define H8S_SCI_IRQS1 {92, 93, 94, 0 }
46#define H8S_SCI_IRQS2 {96, 97, 98, 0 }
47#define SH5_SCIF_IRQS {39, 40, 42, 0 }
48#define SH7770_SCIF0_IRQS {61, 61, 61, 61 }
49#define SH7770_SCIF1_IRQS {62, 62, 62, 62 }
50#define SH7770_SCIF2_IRQS {63, 63, 63, 63 }
51#define SH7780_SCIF0_IRQS {40, 41, 43, 42 }
52#define SH7780_SCIF1_IRQS {76, 77, 79, 78 }
53
54#if defined(CONFIG_CPU_SUBTYPE_SH7708) 27#if defined(CONFIG_CPU_SUBTYPE_SH7708)
55# define SCSPTR 0xffffff7c /* 8 bit */ 28# define SCSPTR 0xffffff7c /* 8 bit */
56# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 29# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
57# define SCI_ONLY 30# define SCI_ONLY
58#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) 31#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7706)
59# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 34# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
60# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 35# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
61# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 36# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
@@ -99,12 +74,23 @@
99# define SCPDR 0xA4050136 /* 16 bit SCIF */ 74# define SCPDR 0xA4050136 /* 16 bit SCIF */
100# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 75# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
101# define SCIF_ONLY 76# define SCIF_ONLY
77#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
78# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
79# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
80# define SCIF_ONLY
102#elif defined(CONFIG_CPU_SUBTYPE_SH73180) 81#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
103# define SCPDR 0xA4050138 /* 16 bit SCIF */ 82# define SCPDR 0xA4050138 /* 16 bit SCIF */
104# define SCSPTR2 SCPDR 83# define SCSPTR2 SCPDR
105# define SCIF_ORER 0x0001 /* overrun error bit */ 84# define SCIF_ORER 0x0001 /* overrun error bit */
106# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */ 85# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
107# define SCIF_ONLY 86# define SCIF_ONLY
87#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
88# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
89# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
90# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
91# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
92# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
93# define SCIF_ONLY
108#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 94#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
109# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 95# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
110# define SCIF_ORER 0x0001 /* overrun error bit */ 96# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -145,7 +131,7 @@
145#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 131#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
146# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 132# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
147# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 133# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
148# define SCIF_OPER 0x0001 /* Overrun error bit */ 134# define SCIF_ORER 0x0001 /* Overrun error bit */
149# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 135# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
150# define SCIF_ONLY 136# define SCIF_ONLY
151#else 137#else
@@ -273,15 +259,6 @@
273 */ 259 */
274#define SCI_EVENT_WRITE_WAKEUP 0 260#define SCI_EVENT_WRITE_WAKEUP 0
275 261
276struct sci_port {
277 struct uart_port port;
278 int type;
279 unsigned char irqs[4]; /* ERI, RXI, TXI, BRI */
280 void (*init_pins)(struct uart_port *port, unsigned int cflag);
281 int break_flag;
282 struct timer_list break_timer;
283};
284
285#define SCI_IN(size, offset) \ 262#define SCI_IN(size, offset) \
286 unsigned int addr = port->mapbase + (offset); \ 263 unsigned int addr = port->mapbase + (offset); \
287 if ((size) == 8) { \ 264 if ((size) == 8) { \
@@ -336,7 +313,9 @@ struct sci_port {
336 } 313 }
337 314
338#ifdef CONFIG_CPU_SH3 315#ifdef CONFIG_CPU_SH3
339#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 316#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
317 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
318 defined(CONFIG_CPU_SUBTYPE_SH7710)
340#define SCIF_FNS(name, scif_offset, scif_size) \ 319#define SCIF_FNS(name, scif_offset, scif_size) \
341 CPU_SCIF_FNS(name, scif_offset, scif_size) 320 CPU_SCIF_FNS(name, scif_offset, scif_size)
342#else 321#else
@@ -362,7 +341,9 @@ struct sci_port {
362 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 341 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
363#endif 342#endif
364 343
365#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 344#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
345 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
346 defined(CONFIG_CPU_SUBTYPE_SH7710)
366SCIF_FNS(SCSMR, 0x00, 16) 347SCIF_FNS(SCSMR, 0x00, 16)
367SCIF_FNS(SCBRR, 0x04, 8) 348SCIF_FNS(SCBRR, 0x04, 8)
368SCIF_FNS(SCSCR, 0x08, 16) 349SCIF_FNS(SCSCR, 0x08, 16)
@@ -447,7 +428,9 @@ static inline int sci_rxd_in(struct uart_port *port)
447 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */ 428 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
448 return 1; 429 return 1;
449} 430}
450#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) 431#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
432 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
433 defined(CONFIG_CPU_SUBTYPE_SH7706)
451static inline int sci_rxd_in(struct uart_port *port) 434static inline int sci_rxd_in(struct uart_port *port)
452{ 435{
453 if (port->mapbase == 0xfffffe80) 436 if (port->mapbase == 0xfffffe80)
@@ -467,6 +450,13 @@ static inline int sci_rxd_in(struct uart_port *port)
467 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 450 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
468 return 1; 451 return 1;
469} 452}
453#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
454static inline int sci_rxd_in(struct uart_port *port)
455{
456 if (port->mapbase == SCSPTR0)
457 return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0;
458 return 1;
459}
470#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 460#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
471 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 461 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
472 defined(CONFIG_CPU_SUBTYPE_SH4_202) 462 defined(CONFIG_CPU_SUBTYPE_SH4_202)
@@ -504,6 +494,19 @@ static inline int sci_rxd_in(struct uart_port *port)
504{ 494{
505 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */ 495 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
506} 496}
497#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
498static inline int sci_rxd_in(struct uart_port *port)
499{
500 if (port->mapbase == 0xffe00000)
501 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
502 if (port->mapbase == 0xffe10000)
503 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
504 if (port->mapbase == 0xffe20000)
505 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
506 if (port->mapbase == 0xffe30000)
507 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
508 return 1;
509}
507#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) 510#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
508static inline int sci_rxd_in(struct uart_port *port) 511static inline int sci_rxd_in(struct uart_port *port)
509{ 512{
@@ -587,4 +590,3 @@ static inline int sci_rxd_in(struct uart_port *port)
587#else /* Generic SH */ 590#else /* Generic SH */
588#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 591#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
589#endif 592#endif
590
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