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-rw-r--r--arch/arm/mach-iop32x/Kconfig9
-rw-r--r--arch/arm/mach-iop32x/iq31244.c22
-rw-r--r--arch/arm/mach-iop32x/iq80321.c14
-rw-r--r--arch/arm/mach-iop32x/irq.c54
-rw-r--r--arch/arm/mach-iop33x/iq80331.c12
-rw-r--r--arch/arm/mach-iop33x/iq80332.c12
-rw-r--r--arch/arm/mach-iop33x/irq.c95
-rw-r--r--arch/arm/mach-iop33x/uart.c37
-rw-r--r--arch/arm/oprofile/op_model_xscale.c6
-rw-r--r--arch/arm/plat-iop/i2c.c8
-rw-r--r--arch/arm/plat-iop/time.c4
-rw-r--r--include/asm-arm/arch-iop32x/debug-macro.S14
-rw-r--r--include/asm-arm/arch-iop32x/dma.h4
-rw-r--r--include/asm-arm/arch-iop32x/entry-macro.S11
-rw-r--r--include/asm-arm/arch-iop32x/hardware.h24
-rw-r--r--include/asm-arm/arch-iop32x/io.h11
-rw-r--r--include/asm-arm/arch-iop32x/iop321.h86
-rw-r--r--include/asm-arm/arch-iop32x/iop32x.h28
-rw-r--r--include/asm-arm/arch-iop32x/iq31244.h8
-rw-r--r--include/asm-arm/arch-iop32x/iq80321.h8
-rw-r--r--include/asm-arm/arch-iop32x/irqs.h66
-rw-r--r--include/asm-arm/arch-iop32x/memory.h7
-rw-r--r--include/asm-arm/arch-iop32x/system.h17
-rw-r--r--include/asm-arm/arch-iop32x/timex.h5
-rw-r--r--include/asm-arm/arch-iop32x/uncompress.h7
-rw-r--r--include/asm-arm/arch-iop32x/vmalloc.h15
-rw-r--r--include/asm-arm/arch-iop33x/debug-macro.S12
-rw-r--r--include/asm-arm/arch-iop33x/dma.h4
-rw-r--r--include/asm-arm/arch-iop33x/entry-macro.S8
-rw-r--r--include/asm-arm/arch-iop33x/hardware.h19
-rw-r--r--include/asm-arm/arch-iop33x/io.h12
-rw-r--r--include/asm-arm/arch-iop33x/iop331.h110
-rw-r--r--include/asm-arm/arch-iop33x/iop33x.h33
-rw-r--r--include/asm-arm/arch-iop33x/iq80331.h8
-rw-r--r--include/asm-arm/arch-iop33x/iq80332.h8
-rw-r--r--include/asm-arm/arch-iop33x/irqs.h86
-rw-r--r--include/asm-arm/arch-iop33x/memory.h6
-rw-r--r--include/asm-arm/arch-iop33x/system.h17
-rw-r--r--include/asm-arm/arch-iop33x/timex.h3
-rw-r--r--include/asm-arm/arch-iop33x/uncompress.h9
-rw-r--r--include/asm-arm/arch-iop33x/vmalloc.h15
41 files changed, 376 insertions, 558 deletions
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
index ff8a77a8866e..d7abfaa525c3 100644
--- a/arch/arm/mach-iop32x/Kconfig
+++ b/arch/arm/mach-iop32x/Kconfig
@@ -8,13 +8,14 @@ config ARCH_IQ80321
8 bool "Enable support for IQ80321" 8 bool "Enable support for IQ80321"
9 help 9 help
10 Say Y here if you want to run your kernel on the Intel IQ80321 10 Say Y here if you want to run your kernel on the Intel IQ80321
11 evaluation kit for the IOP321 chipset. 11 evaluation kit for the IOP321 processor.
12 12
13config ARCH_IQ31244 13config ARCH_IQ31244
14 bool "Enable support for IQ31244" 14 bool "Enable support for EP80219/IQ31244"
15 help 15 help
16 Say Y here if you want to run your kernel on the Intel IQ31244 16 Say Y here if you want to run your kernel on the Intel EP80219
17 evaluation kit for the IOP321 chipset. 17 evaluation kit for the Intel 80219 processor (a IOP321 variant)
18 or the IQ31244 evaluation kit for the IOP321 processor.
18 19
19endmenu 20endmenu
20 21
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 88b77d32b0ac..be4aedfa0de6 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -98,16 +98,16 @@ ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
98 98
99 if (slot == 0) { 99 if (slot == 0) {
100 /* CFlash */ 100 /* CFlash */
101 irq = IRQ_IOP321_XINT1; 101 irq = IRQ_IOP32X_XINT1;
102 } else if (slot == 1) { 102 } else if (slot == 1) {
103 /* 82551 Pro 100 */ 103 /* 82551 Pro 100 */
104 irq = IRQ_IOP321_XINT0; 104 irq = IRQ_IOP32X_XINT0;
105 } else if (slot == 2) { 105 } else if (slot == 2) {
106 /* PCI-X Slot */ 106 /* PCI-X Slot */
107 irq = IRQ_IOP321_XINT3; 107 irq = IRQ_IOP32X_XINT3;
108 } else if (slot == 3) { 108 } else if (slot == 3) {
109 /* SATA */ 109 /* SATA */
110 irq = IRQ_IOP321_XINT2; 110 irq = IRQ_IOP32X_XINT2;
111 } else { 111 } else {
112 printk(KERN_ERR "ep80219_pci_map_irq() called for unknown " 112 printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
113 "device PCI:%d:%d:%d\n", dev->bus->number, 113 "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -134,18 +134,18 @@ iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
134 134
135 if (slot == 0) { 135 if (slot == 0) {
136 /* CFlash */ 136 /* CFlash */
137 irq = IRQ_IOP321_XINT1; 137 irq = IRQ_IOP32X_XINT1;
138 } else if (slot == 1) { 138 } else if (slot == 1) {
139 /* SATA */ 139 /* SATA */
140 irq = IRQ_IOP321_XINT2; 140 irq = IRQ_IOP32X_XINT2;
141 } else if (slot == 2) { 141 } else if (slot == 2) {
142 /* PCI-X Slot */ 142 /* PCI-X Slot */
143 irq = IRQ_IOP321_XINT3; 143 irq = IRQ_IOP32X_XINT3;
144 } else if (slot == 3) { 144 } else if (slot == 3) {
145 /* 82546 GigE */ 145 /* 82546 GigE */
146 irq = IRQ_IOP321_XINT0; 146 irq = IRQ_IOP32X_XINT0;
147 } else { 147 } else {
148 printk(KERN_ERR "iq31244_pci_map_irq() called for unknown " 148 printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
149 "device PCI:%d:%d:%d\n", dev->bus->number, 149 "device PCI:%d:%d:%d\n", dev->bus->number,
150 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 150 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
151 irq = -1; 151 irq = -1;
@@ -206,7 +206,7 @@ static struct plat_serial8250_port iq31244_serial_port[] = {
206 { 206 {
207 .mapbase = IQ31244_UART, 207 .mapbase = IQ31244_UART,
208 .membase = (char *)IQ31244_UART, 208 .membase = (char *)IQ31244_UART,
209 .irq = IRQ_IOP321_XINT1, 209 .irq = IRQ_IOP32X_XINT1,
210 .flags = UPF_SKIP_TEST, 210 .flags = UPF_SKIP_TEST,
211 .iotype = UPIO_MEM, 211 .iotype = UPIO_MEM,
212 .regshift = 0, 212 .regshift = 0,
@@ -287,7 +287,7 @@ MACHINE_START(IQ31244, "Intel IQ31244")
287 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc, 287 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
288 .boot_params = 0xa0000100, 288 .boot_params = 0xa0000100,
289 .map_io = iq31244_map_io, 289 .map_io = iq31244_map_io,
290 .init_irq = iop321_init_irq, 290 .init_irq = iop32x_init_irq,
291 .timer = &iq31244_timer, 291 .timer = &iq31244_timer,
292 .init_machine = iq31244_init_machine, 292 .init_machine = iq31244_init_machine,
293MACHINE_END 293MACHINE_END
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 3c9b86271759..1f37b5501888 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -78,19 +78,19 @@ iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
78 78
79 if ((slot == 2 || slot == 6) && pin == 1) { 79 if ((slot == 2 || slot == 6) && pin == 1) {
80 /* PCI-X Slot INTA */ 80 /* PCI-X Slot INTA */
81 irq = IRQ_IOP321_XINT2; 81 irq = IRQ_IOP32X_XINT2;
82 } else if ((slot == 2 || slot == 6) && pin == 2) { 82 } else if ((slot == 2 || slot == 6) && pin == 2) {
83 /* PCI-X Slot INTA */ 83 /* PCI-X Slot INTA */
84 irq = IRQ_IOP321_XINT3; 84 irq = IRQ_IOP32X_XINT3;
85 } else if ((slot == 2 || slot == 6) && pin == 3) { 85 } else if ((slot == 2 || slot == 6) && pin == 3) {
86 /* PCI-X Slot INTA */ 86 /* PCI-X Slot INTA */
87 irq = IRQ_IOP321_XINT0; 87 irq = IRQ_IOP32X_XINT0;
88 } else if ((slot == 2 || slot == 6) && pin == 4) { 88 } else if ((slot == 2 || slot == 6) && pin == 4) {
89 /* PCI-X Slot INTA */ 89 /* PCI-X Slot INTA */
90 irq = IRQ_IOP321_XINT1; 90 irq = IRQ_IOP32X_XINT1;
91 } else if (slot == 4 || slot == 8) { 91 } else if (slot == 4 || slot == 8) {
92 /* Gig-E */ 92 /* Gig-E */
93 irq = IRQ_IOP321_XINT0; 93 irq = IRQ_IOP32X_XINT0;
94 } else { 94 } else {
95 printk(KERN_ERR "iq80321_pci_map_irq() called for unknown " 95 printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
96 "device PCI:%d:%d:%d\n", dev->bus->number, 96 "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -148,7 +148,7 @@ static struct plat_serial8250_port iq80321_serial_port[] = {
148 { 148 {
149 .mapbase = IQ80321_UART, 149 .mapbase = IQ80321_UART,
150 .membase = (char *)IQ80321_UART, 150 .membase = (char *)IQ80321_UART,
151 .irq = IRQ_IOP321_XINT1, 151 .irq = IRQ_IOP32X_XINT1,
152 .flags = UPF_SKIP_TEST, 152 .flags = UPF_SKIP_TEST,
153 .iotype = UPIO_MEM, 153 .iotype = UPIO_MEM,
154 .regshift = 0, 154 .regshift = 0,
@@ -187,7 +187,7 @@ MACHINE_START(IQ80321, "Intel IQ80321")
187 .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc, 187 .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
188 .boot_params = 0xa0000100, 188 .boot_params = 0xa0000100,
189 .map_io = iq80321_map_io, 189 .map_io = iq80321_map_io,
190 .init_irq = iop321_init_irq, 190 .init_irq = iop32x_init_irq,
191 .timer = &iq80321_timer, 191 .timer = &iq80321_timer,
192 .init_machine = iq80321_init_machine, 192 .init_machine = iq80321_init_machine,
193MACHINE_END 193MACHINE_END
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index ff049e02f5f7..21294be5a369 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-iop32x/irq.c 2 * arch/arm/mach-iop32x/irq.c
3 * 3 *
4 * Generic IOP32X IRQ handling functionality 4 * Generic IOP32X IRQ handling functionality
5 * 5 *
@@ -9,76 +9,66 @@
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 *
13 * Added IOP3XX chipset and IQ80321 board masking code.
14 *
15 */ 12 */
13
16#include <linux/init.h> 14#include <linux/init.h>
17#include <linux/interrupt.h> 15#include <linux/interrupt.h>
18#include <linux/list.h> 16#include <linux/list.h>
19
20#include <asm/mach/irq.h> 17#include <asm/mach/irq.h>
21#include <asm/irq.h> 18#include <asm/irq.h>
22#include <asm/hardware.h> 19#include <asm/hardware.h>
23
24#include <asm/mach-types.h> 20#include <asm/mach-types.h>
25 21
26static u32 iop321_mask /* = 0 */; 22static u32 iop32x_mask;
27 23
28static inline void intctl_write(u32 val) 24static inline void intctl_write(u32 val)
29{ 25{
30 iop3xx_cp6_enable(); 26 iop3xx_cp6_enable();
31 asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); 27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
32 iop3xx_cp6_disable(); 28 iop3xx_cp6_disable();
33} 29}
34 30
35static inline void intstr_write(u32 val) 31static inline void intstr_write(u32 val)
36{ 32{
37 iop3xx_cp6_enable(); 33 iop3xx_cp6_enable();
38 asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); 34 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
39 iop3xx_cp6_disable(); 35 iop3xx_cp6_disable();
40} 36}
41 37
42static void 38static void
43iop321_irq_mask (unsigned int irq) 39iop32x_irq_mask(unsigned int irq)
44{ 40{
45 41 iop32x_mask &= ~(1 << irq);
46 iop321_mask &= ~(1 << irq); 42 intctl_write(iop32x_mask);
47
48 intctl_write(iop321_mask);
49} 43}
50 44
51static void 45static void
52iop321_irq_unmask (unsigned int irq) 46iop32x_irq_unmask(unsigned int irq)
53{ 47{
54 iop321_mask |= (1 << irq); 48 iop32x_mask |= 1 << irq;
55 49 intctl_write(iop32x_mask);
56 intctl_write(iop321_mask);
57} 50}
58 51
59struct irq_chip ext_chip = { 52struct irq_chip ext_chip = {
60 .name = "IOP", 53 .name = "IOP32x",
61 .ack = iop321_irq_mask, 54 .ack = iop32x_irq_mask,
62 .mask = iop321_irq_mask, 55 .mask = iop32x_irq_mask,
63 .unmask = iop321_irq_unmask, 56 .unmask = iop32x_irq_unmask,
64}; 57};
65 58
66void __init iop321_init_irq(void) 59void __init iop32x_init_irq(void)
67{ 60{
68 unsigned int i; 61 int i;
69 62
70 intctl_write(0); // disable all interrupts 63 intctl_write(0);
71 intstr_write(0); // treat all as IRQ 64 intstr_write(0);
72 if(machine_is_iq80321() || 65 if (machine_is_iq80321() ||
73 machine_is_iq31244()) // all interrupts are inputs to chip 66 machine_is_iq31244())
74 *IOP3XX_PCIIRSR = 0x0f; 67 *IOP3XX_PCIIRSR = 0x0f;
75 68
76 for(i = 0; i < NR_IRQS; i++) 69 for (i = 0; i < NR_IRQS; i++) {
77 {
78 set_irq_chip(i, &ext_chip); 70 set_irq_chip(i, &ext_chip);
79 set_irq_handler(i, do_level_IRQ); 71 set_irq_handler(i, do_level_IRQ);
80 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 72 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
81
82 } 73 }
83} 74}
84
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 6b8475da3df6..97a7b7488264 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -61,19 +61,19 @@ iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
61 61
62 if (slot == 1 && pin == 1) { 62 if (slot == 1 && pin == 1) {
63 /* PCI-X Slot INTA */ 63 /* PCI-X Slot INTA */
64 irq = IRQ_IOP331_XINT1; 64 irq = IRQ_IOP33X_XINT1;
65 } else if (slot == 1 && pin == 2) { 65 } else if (slot == 1 && pin == 2) {
66 /* PCI-X Slot INTB */ 66 /* PCI-X Slot INTB */
67 irq = IRQ_IOP331_XINT2; 67 irq = IRQ_IOP33X_XINT2;
68 } else if (slot == 1 && pin == 3) { 68 } else if (slot == 1 && pin == 3) {
69 /* PCI-X Slot INTC */ 69 /* PCI-X Slot INTC */
70 irq = IRQ_IOP331_XINT3; 70 irq = IRQ_IOP33X_XINT3;
71 } else if (slot == 1 && pin == 4) { 71 } else if (slot == 1 && pin == 4) {
72 /* PCI-X Slot INTD */ 72 /* PCI-X Slot INTD */
73 irq = IRQ_IOP331_XINT0; 73 irq = IRQ_IOP33X_XINT0;
74 } else if (slot == 2) { 74 } else if (slot == 2) {
75 /* GigE */ 75 /* GigE */
76 irq = IRQ_IOP331_XINT2; 76 irq = IRQ_IOP33X_XINT2;
77 } else { 77 } else {
78 printk(KERN_ERR "iq80331_pci_map_irq() called for unknown " 78 printk(KERN_ERR "iq80331_pci_map_irq() called for unknown "
79 "device PCI:%d:%d:%d\n", dev->bus->number, 79 "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -142,7 +142,7 @@ MACHINE_START(IQ80331, "Intel IQ80331")
142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, 142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
143 .boot_params = 0x00000100, 143 .boot_params = 0x00000100,
144 .map_io = iop3xx_map_io, 144 .map_io = iop3xx_map_io,
145 .init_irq = iop331_init_irq, 145 .init_irq = iop33x_init_irq,
146 .timer = &iq80331_timer, 146 .timer = &iq80331_timer,
147 .init_machine = iq80331_init_machine, 147 .init_machine = iq80331_init_machine,
148MACHINE_END 148MACHINE_END
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 150f3fd5de0b..9887bfc1c078 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -61,19 +61,19 @@ iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
61 61
62 if (slot == 4 && pin == 1) { 62 if (slot == 4 && pin == 1) {
63 /* PCI-X Slot INTA */ 63 /* PCI-X Slot INTA */
64 irq = IRQ_IOP331_XINT0; 64 irq = IRQ_IOP33X_XINT0;
65 } else if (slot == 4 && pin == 2) { 65 } else if (slot == 4 && pin == 2) {
66 /* PCI-X Slot INTB */ 66 /* PCI-X Slot INTB */
67 irq = IRQ_IOP331_XINT1; 67 irq = IRQ_IOP33X_XINT1;
68 } else if (slot == 4 && pin == 3) { 68 } else if (slot == 4 && pin == 3) {
69 /* PCI-X Slot INTC */ 69 /* PCI-X Slot INTC */
70 irq = IRQ_IOP331_XINT2; 70 irq = IRQ_IOP33X_XINT2;
71 } else if (slot == 4 && pin == 4) { 71 } else if (slot == 4 && pin == 4) {
72 /* PCI-X Slot INTD */ 72 /* PCI-X Slot INTD */
73 irq = IRQ_IOP331_XINT3; 73 irq = IRQ_IOP33X_XINT3;
74 } else if (slot == 6) { 74 } else if (slot == 6) {
75 /* GigE */ 75 /* GigE */
76 irq = IRQ_IOP331_XINT2; 76 irq = IRQ_IOP33X_XINT2;
77 } else { 77 } else {
78 printk(KERN_ERR "iq80332_pci_map_irq() called for unknown " 78 printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
79 "device PCI:%d:%d:%d\n", dev->bus->number, 79 "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -142,7 +142,7 @@ MACHINE_START(IQ80332, "Intel IQ80332")
142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, 142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
143 .boot_params = 0x00000100, 143 .boot_params = 0x00000100,
144 .map_io = iop3xx_map_io, 144 .map_io = iop3xx_map_io,
145 .init_irq = iop331_init_irq, 145 .init_irq = iop33x_init_irq,
146 .timer = &iq80332_timer, 146 .timer = &iq80332_timer,
147 .init_machine = iq80332_init_machine, 147 .init_machine = iq80332_init_machine,
148MACHINE_END 148MACHINE_END
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 3c720551ac12..63304b3d0d76 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-iop33x/irq.c 2 * arch/arm/mach-iop33x/irq.c
3 * 3 *
4 * Generic IOP331 IRQ handling functionality 4 * Generic IOP331 IRQ handling functionality
5 * 5 *
@@ -9,51 +9,44 @@
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 *
13 *
14 */ 12 */
13
15#include <linux/init.h> 14#include <linux/init.h>
16#include <linux/interrupt.h> 15#include <linux/interrupt.h>
17#include <linux/list.h> 16#include <linux/list.h>
18
19#include <asm/mach/irq.h> 17#include <asm/mach/irq.h>
20#include <asm/irq.h> 18#include <asm/irq.h>
21#include <asm/hardware.h> 19#include <asm/hardware.h>
22
23#include <asm/mach-types.h> 20#include <asm/mach-types.h>
24 21
25static u32 iop331_mask0 = 0; 22static u32 iop33x_mask0;
26static u32 iop331_mask1 = 0; 23static u32 iop33x_mask1;
27 24
28static inline void intctl_write0(u32 val) 25static inline void intctl0_write(u32 val)
29{ 26{
30 // INTCTL0
31 iop3xx_cp6_enable(); 27 iop3xx_cp6_enable();
32 asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); 28 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
33 iop3xx_cp6_disable(); 29 iop3xx_cp6_disable();
34} 30}
35 31
36static inline void intctl_write1(u32 val) 32static inline void intctl1_write(u32 val)
37{ 33{
38 // INTCTL1
39 iop3xx_cp6_enable(); 34 iop3xx_cp6_enable();
40 asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val)); 35 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
41 iop3xx_cp6_disable(); 36 iop3xx_cp6_disable();
42} 37}
43 38
44static inline void intstr_write0(u32 val) 39static inline void intstr0_write(u32 val)
45{ 40{
46 // INTSTR0
47 iop3xx_cp6_enable(); 41 iop3xx_cp6_enable();
48 asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val)); 42 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
49 iop3xx_cp6_disable(); 43 iop3xx_cp6_disable();
50} 44}
51 45
52static inline void intstr_write1(u32 val) 46static inline void intstr1_write(u32 val)
53{ 47{
54 // INTSTR1
55 iop3xx_cp6_enable(); 48 iop3xx_cp6_enable();
56 asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val)); 49 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
57 iop3xx_cp6_disable(); 50 iop3xx_cp6_disable();
58} 51}
59 52
@@ -72,65 +65,63 @@ static inline void intsize_write(u32 val)
72} 65}
73 66
74static void 67static void
75iop331_irq_mask1 (unsigned int irq) 68iop33x_irq_mask1 (unsigned int irq)
76{ 69{
77 iop331_mask0 &= ~(1 << irq); 70 iop33x_mask0 &= ~(1 << irq);
78 intctl_write0(iop331_mask0); 71 intctl0_write(iop33x_mask0);
79} 72}
80 73
81static void 74static void
82iop331_irq_mask2 (unsigned int irq) 75iop33x_irq_mask2 (unsigned int irq)
83{ 76{
84 iop331_mask1 &= ~(1 << (irq - 32)); 77 iop33x_mask1 &= ~(1 << (irq - 32));
85 intctl_write1(iop331_mask1); 78 intctl1_write(iop33x_mask1);
86} 79}
87 80
88static void 81static void
89iop331_irq_unmask1(unsigned int irq) 82iop33x_irq_unmask1(unsigned int irq)
90{ 83{
91 iop331_mask0 |= (1 << irq); 84 iop33x_mask0 |= 1 << irq;
92 intctl_write0(iop331_mask0); 85 intctl0_write(iop33x_mask0);
93} 86}
94 87
95static void 88static void
96iop331_irq_unmask2(unsigned int irq) 89iop33x_irq_unmask2(unsigned int irq)
97{ 90{
98 iop331_mask1 |= (1 << (irq - 32)); 91 iop33x_mask1 |= (1 << (irq - 32));
99 intctl_write1(iop331_mask1); 92 intctl1_write(iop33x_mask1);
100} 93}
101 94
102struct irq_chip iop331_irqchip1 = { 95struct irq_chip iop33x_irqchip1 = {
103 .name = "IOP-1", 96 .name = "IOP33x-1",
104 .ack = iop331_irq_mask1, 97 .ack = iop33x_irq_mask1,
105 .mask = iop331_irq_mask1, 98 .mask = iop33x_irq_mask1,
106 .unmask = iop331_irq_unmask1, 99 .unmask = iop33x_irq_unmask1,
107}; 100};
108 101
109struct irq_chip iop331_irqchip2 = { 102struct irq_chip iop33x_irqchip2 = {
110 .name = "IOP-2", 103 .name = "IOP33x-2",
111 .ack = iop331_irq_mask2, 104 .ack = iop33x_irq_mask2,
112 .mask = iop331_irq_mask2, 105 .mask = iop33x_irq_mask2,
113 .unmask = iop331_irq_unmask2, 106 .unmask = iop33x_irq_unmask2,
114}; 107};
115 108
116void __init iop331_init_irq(void) 109void __init iop33x_init_irq(void)
117{ 110{
118 unsigned int i; 111 int i;
119 112
120 intctl_write0(0); // disable all interrupts 113 intctl0_write(0);
121 intctl_write1(0); 114 intctl1_write(0);
122 intstr_write0(0); // treat all as IRQ 115 intstr0_write(0);
123 intstr_write1(0); 116 intstr1_write(0);
124 intbase_write(0); 117 intbase_write(0);
125 intsize_write(1); 118 intsize_write(1);
126 if(machine_is_iq80331()) // all interrupts are inputs to chip 119 if (machine_is_iq80331())
127 *IOP3XX_PCIIRSR = 0x0f; 120 *IOP3XX_PCIIRSR = 0x0f;
128 121
129 for(i = 0; i < NR_IRQS; i++) 122 for (i = 0; i < NR_IRQS; i++) {
130 { 123 set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
131 set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
132 set_irq_handler(i, do_level_IRQ); 124 set_irq_handler(i, do_level_IRQ);
133 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
134 } 126 }
135} 127}
136
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
index d221d4abaa87..ac297cd0276c 100644
--- a/arch/arm/mach-iop33x/uart.c
+++ b/arch/arm/mach-iop33x/uart.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-iop33x/uart.c 2 * arch/arm/mach-iop33x/uart.c
3 * 3 *
4 * Author: Dave Jiang (dave.jiang@intel.com) 4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright (C) 2004 Intel Corporation. 5 * Copyright (C) 2004 Intel Corporation.
@@ -17,7 +17,6 @@
17#include <linux/serial.h> 17#include <linux/serial.h>
18#include <linux/tty.h> 18#include <linux/tty.h>
19#include <linux/serial_8250.h> 19#include <linux/serial_8250.h>
20
21#include <asm/io.h> 20#include <asm/io.h>
22#include <asm/pgtable.h> 21#include <asm/pgtable.h>
23#include <asm/page.h> 22#include <asm/page.h>
@@ -30,14 +29,14 @@
30#include <asm/mach-types.h> 29#include <asm/mach-types.h>
31#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
32 31
33#define IOP331_UART_XTAL 33334000 32#define IOP33X_UART_XTAL 33334000
34 33
35static struct plat_serial8250_port iop33x_uart0_data[] = { 34static struct plat_serial8250_port iop33x_uart0_data[] = {
36 { 35 {
37 .membase = (char *)IOP331_UART0_VIRT, 36 .membase = (char *)IOP33X_UART0_VIRT,
38 .mapbase = IOP331_UART0_PHYS, 37 .mapbase = IOP33X_UART0_PHYS,
39 .irq = IRQ_IOP331_UART0, 38 .irq = IRQ_IOP33X_UART0,
40 .uartclk = IOP331_UART_XTAL, 39 .uartclk = IOP33X_UART_XTAL,
41 .regshift = 2, 40 .regshift = 2,
42 .iotype = UPIO_MEM, 41 .iotype = UPIO_MEM,
43 .flags = UPF_SKIP_TEST, 42 .flags = UPF_SKIP_TEST,
@@ -47,13 +46,13 @@ static struct plat_serial8250_port iop33x_uart0_data[] = {
47 46
48static struct resource iop33x_uart0_resources[] = { 47static struct resource iop33x_uart0_resources[] = {
49 [0] = { 48 [0] = {
50 .start = IOP331_UART0_PHYS, 49 .start = IOP33X_UART0_PHYS,
51 .end = IOP331_UART0_PHYS + 0x3f, 50 .end = IOP33X_UART0_PHYS + 0x3f,
52 .flags = IORESOURCE_MEM, 51 .flags = IORESOURCE_MEM,
53 }, 52 },
54 [1] = { 53 [1] = {
55 .start = IRQ_IOP331_UART0, 54 .start = IRQ_IOP33X_UART0,
56 .end = IRQ_IOP331_UART0, 55 .end = IRQ_IOP33X_UART0,
57 .flags = IORESOURCE_IRQ, 56 .flags = IORESOURCE_IRQ,
58 }, 57 },
59}; 58};
@@ -71,23 +70,23 @@ struct platform_device iop33x_uart0_device = {
71 70
72static struct resource iop33x_uart1_resources[] = { 71static struct resource iop33x_uart1_resources[] = {
73 [0] = { 72 [0] = {
74 .start = IOP331_UART1_PHYS, 73 .start = IOP33X_UART1_PHYS,
75 .end = IOP331_UART1_PHYS + 0x3f, 74 .end = IOP33X_UART1_PHYS + 0x3f,
76 .flags = IORESOURCE_MEM, 75 .flags = IORESOURCE_MEM,
77 }, 76 },
78 [1] = { 77 [1] = {
79 .start = IRQ_IOP331_UART1, 78 .start = IRQ_IOP33X_UART1,
80 .end = IRQ_IOP331_UART1, 79 .end = IRQ_IOP33X_UART1,
81 .flags = IORESOURCE_IRQ, 80 .flags = IORESOURCE_IRQ,
82 }, 81 },
83}; 82};
84 83
85static struct plat_serial8250_port iop33x_uart1_data[] = { 84static struct plat_serial8250_port iop33x_uart1_data[] = {
86 { 85 {
87 .membase = (char *)IOP331_UART1_VIRT, 86 .membase = (char *)IOP33X_UART1_VIRT,
88 .mapbase = IOP331_UART1_PHYS, 87 .mapbase = IOP33X_UART1_PHYS,
89 .irq = IRQ_IOP331_UART1, 88 .irq = IRQ_IOP33X_UART1,
90 .uartclk = IOP331_UART_XTAL, 89 .uartclk = IOP33X_UART_XTAL,
91 .regshift = 2, 90 .regshift = 2,
92 .iotype = UPIO_MEM, 91 .iotype = UPIO_MEM,
93 .flags = UPF_SKIP_TEST, 92 .flags = UPF_SKIP_TEST,
diff --git a/arch/arm/oprofile/op_model_xscale.c b/arch/arm/oprofile/op_model_xscale.c
index 7e0cc5b15b15..6576143f2559 100644
--- a/arch/arm/oprofile/op_model_xscale.c
+++ b/arch/arm/oprofile/op_model_xscale.c
@@ -37,10 +37,10 @@
37#define XSCALE_PMU_IRQ IRQ_XS80200_PMU 37#define XSCALE_PMU_IRQ IRQ_XS80200_PMU
38#endif 38#endif
39#ifdef CONFIG_ARCH_IOP32X 39#ifdef CONFIG_ARCH_IOP32X
40#define XSCALE_PMU_IRQ IRQ_IOP321_CORE_PMU 40#define XSCALE_PMU_IRQ IRQ_IOP32X_CORE_PMU
41#endif 41#endif
42#ifdef CONFIG_ARCH_IOP33X 42#ifdef CONFIG_ARCH_IOP33X
43#define XSCALE_PMU_IRQ IRQ_IOP331_CORE_PMU 43#define XSCALE_PMU_IRQ IRQ_IOP33X_CORE_PMU
44#endif 44#endif
45#ifdef CONFIG_ARCH_PXA 45#ifdef CONFIG_ARCH_PXA
46#define XSCALE_PMU_IRQ IRQ_PMU 46#define XSCALE_PMU_IRQ IRQ_PMU
@@ -88,7 +88,7 @@ static struct pmu_counter results[MAX_COUNTERS];
88/* 88/*
89 * There are two versions of the PMU in current XScale processors 89 * There are two versions of the PMU in current XScale processors
90 * with differing register layouts and number of performance counters. 90 * with differing register layouts and number of performance counters.
91 * e.g. IOP321 is xsc1 whilst IOP331 is xsc2. 91 * e.g. IOP32x is xsc1 whilst IOP33x is xsc2.
92 * We detect which register layout to use in xscale_detect_pmu() 92 * We detect which register layout to use in xscale_detect_pmu()
93 */ 93 */
94enum { PMU_XSC1, PMU_XSC2 }; 94enum { PMU_XSC1, PMU_XSC2 };
diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c
index 7ae149c2e982..e99909bdba71 100644
--- a/arch/arm/plat-iop/i2c.c
+++ b/arch/arm/plat-iop/i2c.c
@@ -31,12 +31,12 @@
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
32 32
33#ifdef CONFIG_ARCH_IOP32X 33#ifdef CONFIG_ARCH_IOP32X
34#define IRQ_IOP3XX_I2C_0 IRQ_IOP321_I2C_0 34#define IRQ_IOP3XX_I2C_0 IRQ_IOP32X_I2C_0
35#define IRQ_IOP3XX_I2C_1 IRQ_IOP321_I2C_1 35#define IRQ_IOP3XX_I2C_1 IRQ_IOP32X_I2C_1
36#endif 36#endif
37#ifdef CONFIG_ARCH_IOP33X 37#ifdef CONFIG_ARCH_IOP33X
38#define IRQ_IOP3XX_I2C_0 IRQ_IOP331_I2C_0 38#define IRQ_IOP3XX_I2C_0 IRQ_IOP33X_I2C_0
39#define IRQ_IOP3XX_I2C_1 IRQ_IOP331_I2C_1 39#define IRQ_IOP3XX_I2C_1 IRQ_IOP33X_I2C_1
40#endif 40#endif
41 41
42static struct resource iop3xx_i2c0_resources[] = { 42static struct resource iop3xx_i2c0_resources[] = {
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index bed20f3669f4..06282dffbdc6 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -26,10 +26,10 @@
26#include <asm/mach/time.h> 26#include <asm/mach/time.h>
27 27
28#ifdef CONFIG_ARCH_IOP32X 28#ifdef CONFIG_ARCH_IOP32X
29#define IRQ_IOP3XX_TIMER0 IRQ_IOP321_TIMER0 29#define IRQ_IOP3XX_TIMER0 IRQ_IOP32X_TIMER0
30#else 30#else
31#ifdef CONFIG_ARCH_IOP33X 31#ifdef CONFIG_ARCH_IOP33X
32#define IRQ_IOP3XX_TIMER0 IRQ_IOP331_TIMER0 32#define IRQ_IOP3XX_TIMER0 IRQ_IOP33X_TIMER0
33#endif 33#endif
34#endif 34#endif
35 35
diff --git a/include/asm-arm/arch-iop32x/debug-macro.S b/include/asm-arm/arch-iop32x/debug-macro.S
index 75ab2e0d8c67..9022b6849e23 100644
--- a/include/asm-arm/arch-iop32x/debug-macro.S
+++ b/include/asm-arm/arch-iop32x/debug-macro.S
@@ -1,18 +1,18 @@
1/* linux/include/asm-arm/arch-iop32x/debug-macro.S 1/*
2 * include/asm-arm/arch-iop32x/debug-macro.S
2 * 3 *
3 * Debugging macro include header 4 * Debugging macro include header
4 * 5 *
5 * Copyright (C) 1994-1999 Russell King 6 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks 7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
11 * 12 */
12*/
13 13
14 .macro addruart,rx 14 .macro addruart, rx
15 mov \rx, #0xfe000000 @ physical 15 mov \rx, #0xfe000000 @ physical as well as virtual
16 orr \rx, \rx, #0x00800000 @ location of the UART 16 orr \rx, \rx, #0x00800000 @ location of the UART
17 .endm 17 .endm
18 18
diff --git a/include/asm-arm/arch-iop32x/dma.h b/include/asm-arm/arch-iop32x/dma.h
index 5be36676e58f..e977a9ef3160 100644
--- a/include/asm-arm/arch-iop32x/dma.h
+++ b/include/asm-arm/arch-iop32x/dma.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop32x/dma.h 2 * include/asm-arm/arch-iop32x/dma.h
3 * 3 *
4 * Copyright (C) 2004 Intel Corp. 4 * Copyright (C) 2004 Intel Corp.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S
index 3497fef0b890..1500cbbd2295 100644
--- a/include/asm-arm/arch-iop32x/entry-macro.S
+++ b/include/asm-arm/arch-iop32x/entry-macro.S
@@ -3,19 +3,16 @@
3 * 3 *
4 * Low-level IRQ helper macros for IOP32x-based platforms 4 * Low-level IRQ helper macros for IOP32x-based platforms
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any 7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10#include <asm/arch/irqs.h> 10#include <asm/arch/iop32x.h>
11 11
12 .macro disable_fiq 12 .macro disable_fiq
13 .endm 13 .endm
14 14
15 /* 15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
16 * Note: only deal with normal interrupts, not FIQ
17 */
18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
19 ldr \base, =IOP3XX_REG_ADDR(0x07D8) 16 ldr \base, =IOP3XX_REG_ADDR(0x07D8)
20 ldr \irqstat, [\base] @ Read IINTSRC 17 ldr \irqstat, [\base] @ Read IINTSRC
21 cmp \irqstat, #0 18 cmp \irqstat, #0
diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h
index 16d0630ab252..6a3001f2f7e0 100644
--- a/include/asm-arm/arch-iop32x/hardware.h
+++ b/include/asm-arm/arch-iop32x/hardware.h
@@ -1,8 +1,9 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop32x/hardware.h 2 * include/asm-arm/arch-iop32x/hardware.h
3 */ 3 */
4#ifndef __ASM_ARCH_HARDWARE_H 4
5#define __ASM_ARCH_HARDWARE_H 5#ifndef __HARDWARE_H
6#define __HARDWARE_H
6 7
7#include <asm/types.h> 8#include <asm/types.h>
8 9
@@ -13,21 +14,23 @@
13 * the IO resources. 14 * the IO resources.
14 * 15 *
15 * The PCI IO space is located at virtual 0xfe000000 from physical 16 * The PCI IO space is located at virtual 0xfe000000 from physical
16 * 0x90000000. The PCI BARs must be programmed with physical addresses, 17 * 0x90000000. The PCI BARs must be programmed with physical addresses,
17 * but when we read them, we convert them to virtual addresses. See 18 * but when we read them, we convert them to virtual addresses. See
18 * arch/arm/mach-iop3xx/iop3xx-pci.c 19 * arch/arm/plat-iop/pci.c.
19 */ 20 */
20
21#define pcibios_assign_all_busses() 1 21#define pcibios_assign_all_busses() 1
22#define PCIBIOS_MIN_IO 0x00000000 22#define PCIBIOS_MIN_IO 0x00000000
23#define PCIBIOS_MIN_MEM 0x00000000 23#define PCIBIOS_MIN_MEM 0x00000000
24 24
25#ifndef __ASSEMBLY__
26void iop32x_init_irq(void);
27#endif
28
25 29
26/* 30/*
27 * Generic chipset bits 31 * Generic chipset bits
28 *
29 */ 32 */
30#include "iop321.h" 33#include "iop32x.h"
31 34
32/* 35/*
33 * Board specific bits 36 * Board specific bits
@@ -35,4 +38,5 @@
35#include "iq80321.h" 38#include "iq80321.h"
36#include "iq31244.h" 39#include "iq31244.h"
37 40
38#endif /* _ASM_ARCH_HARDWARE_H */ 41
42#endif
diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h
index 36d05ada12c4..12d9ee02cde3 100644
--- a/include/asm-arm/arch-iop32x/io.h
+++ b/include/asm-arm/arch-iop32x/io.h
@@ -1,21 +1,22 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop32x/io.h 2 * include/asm-arm/arch-iop32x/io.h
3 * 3 *
4 * Copyright (C) 2001 MontaVista Software, Inc. 4 * Copyright (C) 2001 MontaVista Software, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#ifndef __ASM_ARM_ARCH_IO_H 11#ifndef __IO_H
12#define __ASM_ARM_ARCH_IO_H 12#define __IO_H
13 13
14#include <asm/hardware.h> 14#include <asm/hardware.h>
15 15
16#define IO_SPACE_LIMIT 0xffffffff 16#define IO_SPACE_LIMIT 0xffffffff
17 17
18#define __io(p) ((void __iomem *)(p)) 18#define __io(p) ((void __iomem *)(p))
19#define __mem_pci(a) (a) 19#define __mem_pci(a) (a)
20 20
21
21#endif 22#endif
diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h
deleted file mode 100644
index 1757222a4cad..000000000000
--- a/include/asm-arm/arch-iop32x/iop321.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * linux/include/asm/arch-iop32x/iop321.h
3 *
4 * Intel IOP321 Chip definitions
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef _IOP321_HW_H_
16#define _IOP321_HW_H_
17
18
19/*
20 * This is needed for mixed drivers that need to work on all
21 * IOP3xx variants but behave slightly differently on each.
22 */
23#ifndef __ASSEMBLY__
24#define iop_is_321() 1
25#endif
26
27/*
28 * IOP321 chipset registers
29 */
30#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
31#define IOP321_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
32#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
33
34/* Reserved 0x00000000 through 0x000000FF */
35
36/* Address Translation Unit 0x00000100 through 0x000001FF */
37
38/* Messaging Unit 0x00000300 through 0x000003FF */
39
40/* DMA Controller 0x00000400 through 0x000004FF */
41
42/* Memory controller 0x00000500 through 0x0005FF */
43
44/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
45
46/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
47
48/* Internal arbitration unit 0x00000780 through 0x0007BF */
49#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780)
50#define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784)
51#define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788)
52
53/* General Purpose I/O Registers */
54#define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
55#define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8)
56#define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC)
57
58/* Interrupt Controller */
59#define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0)
60#define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4)
61#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
62#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
63
64/* Application accelerator unit 0x00000800 - 0x000008FF */
65
66/* SSP serial port unit 0x00001600 - 0x0000167F */
67/* I2C bus interface unit 0x00001680 - 0x000016FF */
68
69/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
70
71/*
72 * Peripherals that are shared between the iop32x and iop33x but
73 * located at different addresses.
74 */
75#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg))
76#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
77
78#include <asm/hardware/iop3xx.h>
79
80
81#ifndef __ASSEMBLY__
82extern void iop321_init_irq(void);
83extern void iop321_time_init(void);
84#endif
85
86#endif // _IOP321_HW_H_
diff --git a/include/asm-arm/arch-iop32x/iop32x.h b/include/asm-arm/arch-iop32x/iop32x.h
new file mode 100644
index 000000000000..4bbd85f3ed2a
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/iop32x.h
@@ -0,0 +1,28 @@
1/*
2 * include/asm-arm/arch-iop32x/iop32x.h
3 *
4 * Intel IOP32X Chip definitions
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __IOP32X_H
16#define __IOP32X_H
17
18/*
19 * Peripherals that are shared between the iop32x and iop33x but
20 * located at different addresses.
21 */
22#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg))
23#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
24
25#include <asm/hardware/iop3xx.h>
26
27
28#endif
diff --git a/include/asm-arm/arch-iop32x/iq31244.h b/include/asm-arm/arch-iop32x/iq31244.h
index cf2d2343398d..fff4eafa1f6b 100644
--- a/include/asm-arm/arch-iop32x/iq31244.h
+++ b/include/asm-arm/arch-iop32x/iq31244.h
@@ -1,11 +1,11 @@
1/* 1/*
2 * linux/include/asm/arch-iop32x/iq31244.h 2 * include/asm-arm/arch-iop32x/iq31244.h
3 * 3 *
4 * Intel IQ31244 evaluation board registers 4 * Intel IQ31244 evaluation board registers
5 */ 5 */
6 6
7#ifndef _IQ31244_H_ 7#ifndef __IQ31244_H
8#define _IQ31244_H_ 8#define __IQ31244_H
9 9
10#define IQ31244_UART 0xfe800000 /* UART #1 */ 10#define IQ31244_UART 0xfe800000 /* UART #1 */
11#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ 11#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */
@@ -14,4 +14,4 @@
14#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ 14#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */
15 15
16 16
17#endif // _IQ31244_H_ 17#endif
diff --git a/include/asm-arm/arch-iop32x/iq80321.h b/include/asm-arm/arch-iop32x/iq80321.h
index 55d70f49b7fd..eb69db9b9a06 100644
--- a/include/asm-arm/arch-iop32x/iq80321.h
+++ b/include/asm-arm/arch-iop32x/iq80321.h
@@ -1,11 +1,11 @@
1/* 1/*
2 * linux/include/asm/arch-iop32x/iq80321.h 2 * include/asm-arm/arch-iop32x/iq80321.h
3 * 3 *
4 * Intel IQ80321 evaluation board registers 4 * Intel IQ80321 evaluation board registers
5 */ 5 */
6 6
7#ifndef _IQ80321_H_ 7#ifndef __IQ80321_H
8#define _IQ80321_H_ 8#define __IQ80321_H
9 9
10#define IQ80321_UART 0xfe800000 /* UART #1 */ 10#define IQ80321_UART 0xfe800000 /* UART #1 */
11#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ 11#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */
@@ -14,4 +14,4 @@
14#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ 14#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */
15 15
16 16
17#endif // _IQ80321_H_ 17#endif
diff --git a/include/asm-arm/arch-iop32x/irqs.h b/include/asm-arm/arch-iop32x/irqs.h
index a48327ced92e..bbaef873afce 100644
--- a/include/asm-arm/arch-iop32x/irqs.h
+++ b/include/asm-arm/arch-iop32x/irqs.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop32x/irqs.h 2 * include/asm-arm/arch-iop32x/irqs.h
3 * 3 *
4 * Author: Rory Bolt <rorybolt@pacbell.net> 4 * Author: Rory Bolt <rorybolt@pacbell.net>
5 * Copyright: (C) 2002 Rory Bolt 5 * Copyright: (C) 2002 Rory Bolt
@@ -7,44 +7,44 @@
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 *
11 */ 10 */
12#ifndef _IRQS_H_ 11
13#define _IRQS_H_ 12#ifndef __IRQS_H
13#define __IRQS_H
14 14
15/* 15/*
16 * IOP80321 chipset interrupts 16 * IOP80321 chipset interrupts
17 */ 17 */
18#define IRQ_IOP321_DMA0_EOT 0 18#define IRQ_IOP32X_DMA0_EOT 0
19#define IRQ_IOP321_DMA0_EOC 1 19#define IRQ_IOP32X_DMA0_EOC 1
20#define IRQ_IOP321_DMA1_EOT 2 20#define IRQ_IOP32X_DMA1_EOT 2
21#define IRQ_IOP321_DMA1_EOC 3 21#define IRQ_IOP32X_DMA1_EOC 3
22#define IRQ_IOP321_AA_EOT 6 22#define IRQ_IOP32X_AA_EOT 6
23#define IRQ_IOP321_AA_EOC 7 23#define IRQ_IOP32X_AA_EOC 7
24#define IRQ_IOP321_CORE_PMON 8 24#define IRQ_IOP32X_CORE_PMON 8
25#define IRQ_IOP321_TIMER0 9 25#define IRQ_IOP32X_TIMER0 9
26#define IRQ_IOP321_TIMER1 10 26#define IRQ_IOP32X_TIMER1 10
27#define IRQ_IOP321_I2C_0 11 27#define IRQ_IOP32X_I2C_0 11
28#define IRQ_IOP321_I2C_1 12 28#define IRQ_IOP32X_I2C_1 12
29#define IRQ_IOP321_MESSAGING 13 29#define IRQ_IOP32X_MESSAGING 13
30#define IRQ_IOP321_ATU_BIST 14 30#define IRQ_IOP32X_ATU_BIST 14
31#define IRQ_IOP321_PERFMON 15 31#define IRQ_IOP32X_PERFMON 15
32#define IRQ_IOP321_CORE_PMU 16 32#define IRQ_IOP32X_CORE_PMU 16
33#define IRQ_IOP321_BIU_ERR 17 33#define IRQ_IOP32X_BIU_ERR 17
34#define IRQ_IOP321_ATU_ERR 18 34#define IRQ_IOP32X_ATU_ERR 18
35#define IRQ_IOP321_MCU_ERR 19 35#define IRQ_IOP32X_MCU_ERR 19
36#define IRQ_IOP321_DMA0_ERR 20 36#define IRQ_IOP32X_DMA0_ERR 20
37#define IRQ_IOP321_DMA1_ERR 21 37#define IRQ_IOP32X_DMA1_ERR 21
38#define IRQ_IOP321_AA_ERR 23 38#define IRQ_IOP32X_AA_ERR 23
39#define IRQ_IOP321_MSG_ERR 24 39#define IRQ_IOP32X_MSG_ERR 24
40#define IRQ_IOP321_SSP 25 40#define IRQ_IOP32X_SSP 25
41#define IRQ_IOP321_XINT0 27 41#define IRQ_IOP32X_XINT0 27
42#define IRQ_IOP321_XINT1 28 42#define IRQ_IOP32X_XINT1 28
43#define IRQ_IOP321_XINT2 29 43#define IRQ_IOP32X_XINT2 29
44#define IRQ_IOP321_XINT3 30 44#define IRQ_IOP32X_XINT3 30
45#define IRQ_IOP321_HPI 31 45#define IRQ_IOP32X_HPI 31
46 46
47#define NR_IRQS 32 47#define NR_IRQS 32
48 48
49 49
50#endif // _IRQ_H_ 50#endif
diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h
index 4c64d9e7229b..764cd3f0d416 100644
--- a/include/asm-arm/arch-iop32x/memory.h
+++ b/include/asm-arm/arch-iop32x/memory.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop32x/memory.h 2 * include/asm-arm/arch-iop32x/memory.h
3 */ 3 */
4 4
5#ifndef __ASM_ARCH_MEMORY_H 5#ifndef __MEMORY_H
6#define __ASM_ARCH_MEMORY_H 6#define __MEMORY_H
7 7
8#include <asm/hardware.h> 8#include <asm/hardware.h>
9 9
@@ -19,7 +19,6 @@
19 * bus_to_virt: Used to convert an address for DMA operations 19 * bus_to_virt: Used to convert an address for DMA operations
20 * to an address that the kernel can use. 20 * to an address that the kernel can use.
21 */ 21 */
22
23#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0)) 22#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
24#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2))) 23#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
25 24
diff --git a/include/asm-arm/arch-iop32x/system.h b/include/asm-arm/arch-iop32x/system.h
index 1ac207a0d52e..c65ede3e627a 100644
--- a/include/asm-arm/arch-iop32x/system.h
+++ b/include/asm-arm/arch-iop32x/system.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop32x/system.h 2 * include/asm-arm/arch-iop32x/system.h
3 * 3 *
4 * Copyright (C) 2001 MontaVista Software, Inc. 4 * Copyright (C) 2001 MontaVista Software, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -13,17 +13,10 @@ static inline void arch_idle(void)
13 cpu_do_idle(); 13 cpu_do_idle();
14} 14}
15 15
16
17static inline void arch_reset(char mode) 16static inline void arch_reset(char mode)
18{ 17{
19 *IOP3XX_PCSR = 0x30; 18 *IOP3XX_PCSR = 0x30;
20 19
21 if ( 1 && mode == 's') { 20 /* Jump into ROM at address 0 */
22 /* Jump into ROM at address 0 */ 21 cpu_reset(0);
23 cpu_reset(0);
24 } else {
25 /* No on-chip reset capability */
26 cpu_reset(0);
27 }
28} 22}
29
diff --git a/include/asm-arm/arch-iop32x/timex.h b/include/asm-arm/arch-iop32x/timex.h
index 328f37282c3e..9934b087311b 100644
--- a/include/asm-arm/arch-iop32x/timex.h
+++ b/include/asm-arm/arch-iop32x/timex.h
@@ -1,8 +1,9 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop32x/timex.h 2 * include/asm-arm/arch-iop32x/timex.h
3 * 3 *
4 * IOP3xx architecture timex specifications 4 * IOP32x architecture timex specifications
5 */ 5 */
6
6#include <asm/hardware.h> 7#include <asm/hardware.h>
7 8
8#define CLOCK_TICK_RATE (100 * HZ) 9#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h
index 4a85f20c796f..e64f52bf2bce 100644
--- a/include/asm-arm/arch-iop32x/uncompress.h
+++ b/include/asm-arm/arch-iop32x/uncompress.h
@@ -1,6 +1,7 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop32x/uncompress.h 2 * include/asm-arm/arch-iop32x/uncompress.h
3 */ 3 */
4
4#include <asm/types.h> 5#include <asm/types.h>
5#include <asm/mach-types.h> 6#include <asm/mach-types.h>
6#include <linux/serial_reg.h> 7#include <linux/serial_reg.h>
@@ -8,13 +9,13 @@
8 9
9static volatile u8 *uart_base; 10static volatile u8 *uart_base;
10 11
11#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) 12#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
12 13
13static inline void putc(char c) 14static inline void putc(char c)
14{ 15{
15 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) 16 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
16 barrier(); 17 barrier();
17 *uart_base = c; 18 uart_base[UART_TX] = c;
18} 19}
19 20
20static inline void flush(void) 21static inline void flush(void)
diff --git a/include/asm-arm/arch-iop32x/vmalloc.h b/include/asm-arm/arch-iop32x/vmalloc.h
index 8492e1708a63..0a70baa19517 100644
--- a/include/asm-arm/arch-iop32x/vmalloc.h
+++ b/include/asm-arm/arch-iop32x/vmalloc.h
@@ -1,16 +1,5 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop32x/vmalloc.h 2 * include/asm-arm/arch-iop32x/vmalloc.h
3 */ 3 */
4 4
5/* 5#define VMALLOC_END 0xfe000000
6 * Just any arbitrary offset to the start of the vmalloc VM area: the
7 * current 8MB value just means that there will be a 8MB "hole" after the
8 * physical memory until the kernel virtual memory starts. That means that
9 * any out-of-bounds memory accesses will hopefully be caught.
10 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
11 * area for the same reason. ;)
12 */
13//#define VMALLOC_END (0xe8000000)
14/* increase usable physical RAM to ~992M per RMK */
15#define VMALLOC_END (0xfe000000)
16
diff --git a/include/asm-arm/arch-iop33x/debug-macro.S b/include/asm-arm/arch-iop33x/debug-macro.S
index b647edff475d..9e7132ebe6a7 100644
--- a/include/asm-arm/arch-iop33x/debug-macro.S
+++ b/include/asm-arm/arch-iop33x/debug-macro.S
@@ -1,17 +1,17 @@
1/* linux/include/asm-arm/arch-iop33x/debug-macro.S 1/*
2 * include/asm-arm/arch-iop33x/debug-macro.S
2 * 3 *
3 * Debugging macro include header 4 * Debugging macro include header
4 * 5 *
5 * Copyright (C) 1994-1999 Russell King 6 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks 7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
11 * 12 */
12*/
13 13
14 .macro addruart,rx 14 .macro addruart, rx
15 mrc p15, 0, \rx, c1, c0 15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ mmu enabled? 16 tst \rx, #1 @ mmu enabled?
17 moveq \rx, #0xff000000 @ physical 17 moveq \rx, #0xff000000 @ physical
diff --git a/include/asm-arm/arch-iop33x/dma.h b/include/asm-arm/arch-iop33x/dma.h
index d577ca59f4b0..b7775fdc5ad3 100644
--- a/include/asm-arm/arch-iop33x/dma.h
+++ b/include/asm-arm/arch-iop33x/dma.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop33x/dma.h 2 * include/asm-arm/arch-iop33x/dma.h
3 * 3 *
4 * Copyright (C) 2004 Intel Corp. 4 * Copyright (C) 2004 Intel Corp.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S
index 4750e98e9b4a..92b791702e34 100644
--- a/include/asm-arm/arch-iop33x/entry-macro.S
+++ b/include/asm-arm/arch-iop33x/entry-macro.S
@@ -3,16 +3,16 @@
3 * 3 *
4 * Low-level IRQ helper macros for IOP33x-based platforms 4 * Low-level IRQ helper macros for IOP33x-based platforms
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any 7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10#include <asm/arch/irqs.h> 10#include <asm/arch/iop33x.h>
11 11
12 .macro disable_fiq 12 .macro disable_fiq
13 .endm 13 .endm
14 14
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
16 ldr \base, =IOP3XX_REG_ADDR(0x07C8) 16 ldr \base, =IOP3XX_REG_ADDR(0x07C8)
17 ldr \irqstat, [\base] @ Read IINTVEC 17 ldr \irqstat, [\base] @ Read IINTVEC
18 cmp \irqstat, #0 18 cmp \irqstat, #0
diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h
index 3ebfdc6fea99..0659cf94d040 100644
--- a/include/asm-arm/arch-iop33x/hardware.h
+++ b/include/asm-arm/arch-iop33x/hardware.h
@@ -1,8 +1,9 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop33x/hardware.h 2 * include/asm-arm/arch-iop33x/hardware.h
3 */ 3 */
4#ifndef __ASM_ARCH_HARDWARE_H 4
5#define __ASM_ARCH_HARDWARE_H 5#ifndef __HARDWARE_H
6#define __HARDWARE_H
6 7
7#include <asm/types.h> 8#include <asm/types.h>
8 9
@@ -15,14 +16,15 @@
15 * The PCI IO space is located at virtual 0xfe000000 from physical 16 * The PCI IO space is located at virtual 0xfe000000 from physical
16 * 0x90000000. The PCI BARs must be programmed with physical addresses, 17 * 0x90000000. The PCI BARs must be programmed with physical addresses,
17 * but when we read them, we convert them to virtual addresses. See 18 * but when we read them, we convert them to virtual addresses. See
18 * arch/arm/mach-iop33x/pci.c 19 * arch/arm/mach-iop3xx/iop3xx-pci.c
19 */ 20 */
20 21#define pcibios_assign_all_busses() 1
21#define pcibios_assign_all_busses() 1
22#define PCIBIOS_MIN_IO 0x00000000 22#define PCIBIOS_MIN_IO 0x00000000
23#define PCIBIOS_MIN_MEM 0x00000000 23#define PCIBIOS_MIN_MEM 0x00000000
24 24
25#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
26void iop33x_init_irq(void);
27
26extern struct platform_device iop33x_uart0_device; 28extern struct platform_device iop33x_uart0_device;
27extern struct platform_device iop33x_uart1_device; 29extern struct platform_device iop33x_uart1_device;
28#endif 30#endif
@@ -32,7 +34,7 @@ extern struct platform_device iop33x_uart1_device;
32 * Generic chipset bits 34 * Generic chipset bits
33 * 35 *
34 */ 36 */
35#include "iop331.h" 37#include "iop33x.h"
36 38
37/* 39/*
38 * Board specific bits 40 * Board specific bits
@@ -40,4 +42,5 @@ extern struct platform_device iop33x_uart1_device;
40#include "iq80331.h" 42#include "iq80331.h"
41#include "iq80332.h" 43#include "iq80332.h"
42 44
43#endif /* _ASM_ARCH_HARDWARE_H */ 45
46#endif
diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h
index a9949d5d4953..c017402bab96 100644
--- a/include/asm-arm/arch-iop33x/io.h
+++ b/include/asm-arm/arch-iop33x/io.h
@@ -1,21 +1,21 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop33x/io.h 2 * include/asm-arm/arch-iop33x/io.h
3 * 3 *
4 * Copyright (C) 2001 MontaVista Software, Inc. 4 * Copyright (C) 2001 MontaVista Software, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#ifndef __ASM_ARM_ARCH_IO_H 11#ifndef __IO_H
12#define __ASM_ARM_ARCH_IO_H 12#define __IO_H
13 13
14#include <asm/hardware.h> 14#include <asm/hardware.h>
15 15
16#define IO_SPACE_LIMIT 0xffffffff 16#define IO_SPACE_LIMIT 0xffffffff
17
18#define __io(p) ((void __iomem *)(p)) 17#define __io(p) ((void __iomem *)(p))
19#define __mem_pci(a) (a) 18#define __mem_pci(a) (a)
20 19
20
21#endif 21#endif
diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h
deleted file mode 100644
index 8c7ec583615f..000000000000
--- a/include/asm-arm/arch-iop33x/iop331.h
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * linux/include/asm/arch-iop33x/iop331.h
3 *
4 * Intel IOP331 Chip definitions
5 *
6 * Author: Dave Jiang (dave.jiang@intel.com)
7 * Copyright (C) 2003, 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef _IOP331_HW_H_
15#define _IOP331_HW_H_
16
17
18/*
19 * This is needed for mixed drivers that need to work on all
20 * IOP3xx variants but behave slightly differently on each.
21 */
22#ifndef __ASSEMBLY__
23#define iop_is_331() 1
24#endif
25
26/*
27 * IOP331 chipset registers
28 */
29#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
30#define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
31#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
32
33/* Reserved 0x00000000 through 0x000000FF */
34
35/* Address Translation Unit 0x00000100 through 0x000001FF */
36
37/* Messaging Unit 0x00000300 through 0x000003FF */
38
39/* DMA Controller 0x00000400 through 0x000004FF */
40
41/* Memory controller 0x00000500 through 0x0005FF */
42
43/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
44
45/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
46/* Internal arbitration unit 0x00000780 through 0x0007BF */
47
48/* Interrupt Controller */
49#define IOP331_INTCTL0 (volatile u32 *)IOP331_REG_ADDR(0x00000790)
50#define IOP331_INTCTL1 (volatile u32 *)IOP331_REG_ADDR(0x00000794)
51#define IOP331_INTSTR0 (volatile u32 *)IOP331_REG_ADDR(0x00000798)
52#define IOP331_INTSTR1 (volatile u32 *)IOP331_REG_ADDR(0x0000079C)
53#define IOP331_IINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A0)
54#define IOP331_IINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007A4)
55#define IOP331_FINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A8)
56#define IOP331_FINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007AC)
57#define IOP331_IPR0 (volatile u32 *)IOP331_REG_ADDR(0x000007B0)
58#define IOP331_IPR1 (volatile u32 *)IOP331_REG_ADDR(0x000007B4)
59#define IOP331_IPR2 (volatile u32 *)IOP331_REG_ADDR(0x000007B8)
60#define IOP331_IPR3 (volatile u32 *)IOP331_REG_ADDR(0x000007BC)
61#define IOP331_INTBASE (volatile u32 *)IOP331_REG_ADDR(0x000007C0)
62#define IOP331_INTSIZE (volatile u32 *)IOP331_REG_ADDR(0x000007C4)
63#define IOP331_IINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007C8)
64#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
65
66
67/* Application accelerator unit 0x00000800 - 0x000008FF */
68
69#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
70#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
71/* SSP serial port unit 0x00001600 - 0x0000167F */
72
73/* I2C bus interface unit 0x00001680 - 0x000016FF */
74
75/* 0x00001700 through 0x0000172C UART 0 */
76
77/* Reserved 0x00001730 through 0x0000173F */
78
79/* 0x00001740 through 0x0000176C UART 1 */
80
81#define IOP331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */
82#define IOP331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */
83#define IOP331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
84#define IOP331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
85
86/* Reserved 0x00001770 through 0x0000177F */
87
88/* General Purpose I/O Registers */
89#define IOP331_GPOE (volatile u32 *)IOP331_REG_ADDR(0x00001780)
90#define IOP331_GPID (volatile u32 *)IOP331_REG_ADDR(0x00001784)
91#define IOP331_GPOD (volatile u32 *)IOP331_REG_ADDR(0x00001788)
92
93/* Reserved 0x0000178c through 0x000019ff */
94
95/*
96 * Peripherals that are shared between the iop32x and iop33x but
97 * located at different addresses.
98 */
99#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
100#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
101
102#include <asm/hardware/iop3xx.h>
103
104
105#ifndef __ASSEMBLY__
106extern void iop331_init_irq(void);
107extern void iop331_time_init(void);
108#endif
109
110#endif // _IOP331_HW_H_
diff --git a/include/asm-arm/arch-iop33x/iop33x.h b/include/asm-arm/arch-iop33x/iop33x.h
new file mode 100644
index 000000000000..7ac6e93db5ff
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/iop33x.h
@@ -0,0 +1,33 @@
1/*
2 * include/asm-arm/arch-iop33x/iop33x.h
3 *
4 * Intel IOP33X Chip definitions
5 *
6 * Author: Dave Jiang (dave.jiang@intel.com)
7 * Copyright (C) 2003, 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __IOP33X_H
15#define __IOP33X_H
16
17/*
18 * Peripherals that are shared between the iop32x and iop33x but
19 * located at different addresses.
20 */
21#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
22#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
23
24#include <asm/hardware/iop3xx.h>
25
26/* UARTs */
27#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
28#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
29#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
30#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
31
32
33#endif
diff --git a/include/asm-arm/arch-iop33x/iq80331.h b/include/asm-arm/arch-iop33x/iq80331.h
index 186762bf8944..79b9302017ea 100644
--- a/include/asm-arm/arch-iop33x/iq80331.h
+++ b/include/asm-arm/arch-iop33x/iq80331.h
@@ -1,11 +1,11 @@
1/* 1/*
2 * linux/include/asm/arch-iop33x/iq80331.h 2 * include/asm-arm/arch-iop33x/iq80331.h
3 * 3 *
4 * Intel IQ80331 evaluation board registers 4 * Intel IQ80331 evaluation board registers
5 */ 5 */
6 6
7#ifndef _IQ80331_H_ 7#ifndef __IQ80331_H
8#define _IQ80331_H_ 8#define __IQ80331_H
9 9
10#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ 10#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
11#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ 11#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
@@ -13,4 +13,4 @@
13#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ 13#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
14 14
15 15
16#endif // _IQ80331_H_ 16#endif
diff --git a/include/asm-arm/arch-iop33x/iq80332.h b/include/asm-arm/arch-iop33x/iq80332.h
index 2a5d4ee01df9..053165629492 100644
--- a/include/asm-arm/arch-iop33x/iq80332.h
+++ b/include/asm-arm/arch-iop33x/iq80332.h
@@ -1,11 +1,11 @@
1/* 1/*
2 * linux/include/asm/arch-iop33x/iq80332.h 2 * include/asm-arm/arch-iop33x/iq80332.h
3 * 3 *
4 * Intel IQ80332 evaluation board registers 4 * Intel IQ80332 evaluation board registers
5 */ 5 */
6 6
7#ifndef _IQ80332_H_ 7#ifndef __IQ80332_H
8#define _IQ80332_H_ 8#define __IQ80332_H
9 9
10#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ 10#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
11#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ 11#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
@@ -13,4 +13,4 @@
13#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ 13#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
14 14
15 15
16#endif // _IQ80332_H_ 16#endif
diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h
index a875404a07fc..d045f8403396 100644
--- a/include/asm-arm/arch-iop33x/irqs.h
+++ b/include/asm-arm/arch-iop33x/irqs.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop33x/irqs.h 2 * include/asm-arm/arch-iop33x/irqs.h
3 * 3 *
4 * Author: Dave Jiang (dave.jiang@intel.com) 4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright: (C) 2003 Intel Corp. 5 * Copyright: (C) 2003 Intel Corp.
@@ -7,54 +7,54 @@
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 *
11 */ 10 */
12#ifndef _IRQS_H_ 11
13#define _IRQS_H_ 12#ifndef __IRQS_H
13#define __IRQS_H
14 14
15/* 15/*
16 * IOP80331 chipset interrupts 16 * IOP80331 chipset interrupts
17 */ 17 */
18#define IRQ_IOP331_DMA0_EOT 0 18#define IRQ_IOP33X_DMA0_EOT 0
19#define IRQ_IOP331_DMA0_EOC 1 19#define IRQ_IOP33X_DMA0_EOC 1
20#define IRQ_IOP331_DMA1_EOT 2 20#define IRQ_IOP33X_DMA1_EOT 2
21#define IRQ_IOP331_DMA1_EOC 3 21#define IRQ_IOP33X_DMA1_EOC 3
22#define IRQ_IOP331_AA_EOT 6 22#define IRQ_IOP33X_AA_EOT 6
23#define IRQ_IOP331_AA_EOC 7 23#define IRQ_IOP33X_AA_EOC 7
24#define IRQ_IOP331_TIMER0 8 24#define IRQ_IOP33X_TIMER0 8
25#define IRQ_IOP331_TIMER1 9 25#define IRQ_IOP33X_TIMER1 9
26#define IRQ_IOP331_I2C_0 10 26#define IRQ_IOP33X_I2C_0 10
27#define IRQ_IOP331_I2C_1 11 27#define IRQ_IOP33X_I2C_1 11
28#define IRQ_IOP331_MSG 12 28#define IRQ_IOP33X_MSG 12
29#define IRQ_IOP331_MSGIBQ 13 29#define IRQ_IOP33X_MSGIBQ 13
30#define IRQ_IOP331_ATU_BIST 14 30#define IRQ_IOP33X_ATU_BIST 14
31#define IRQ_IOP331_PERFMON 15 31#define IRQ_IOP33X_PERFMON 15
32#define IRQ_IOP331_CORE_PMU 16 32#define IRQ_IOP33X_CORE_PMU 16
33#define IRQ_IOP331_XINT0 24 33#define IRQ_IOP33X_XINT0 24
34#define IRQ_IOP331_XINT1 25 34#define IRQ_IOP33X_XINT1 25
35#define IRQ_IOP331_XINT2 26 35#define IRQ_IOP33X_XINT2 26
36#define IRQ_IOP331_XINT3 27 36#define IRQ_IOP33X_XINT3 27
37#define IRQ_IOP331_XINT8 32 37#define IRQ_IOP33X_XINT8 32
38#define IRQ_IOP331_XINT9 33 38#define IRQ_IOP33X_XINT9 33
39#define IRQ_IOP331_XINT10 34 39#define IRQ_IOP33X_XINT10 34
40#define IRQ_IOP331_XINT11 35 40#define IRQ_IOP33X_XINT11 35
41#define IRQ_IOP331_XINT12 36 41#define IRQ_IOP33X_XINT12 36
42#define IRQ_IOP331_XINT13 37 42#define IRQ_IOP33X_XINT13 37
43#define IRQ_IOP331_XINT14 38 43#define IRQ_IOP33X_XINT14 38
44#define IRQ_IOP331_XINT15 39 44#define IRQ_IOP33X_XINT15 39
45#define IRQ_IOP331_UART0 51 45#define IRQ_IOP33X_UART0 51
46#define IRQ_IOP331_UART1 52 46#define IRQ_IOP33X_UART1 52
47#define IRQ_IOP331_PBIE 53 47#define IRQ_IOP33X_PBIE 53
48#define IRQ_IOP331_ATU_CRW 54 48#define IRQ_IOP33X_ATU_CRW 54
49#define IRQ_IOP331_ATU_ERR 55 49#define IRQ_IOP33X_ATU_ERR 55
50#define IRQ_IOP331_MCU_ERR 56 50#define IRQ_IOP33X_MCU_ERR 56
51#define IRQ_IOP331_DMA0_ERR 57 51#define IRQ_IOP33X_DMA0_ERR 57
52#define IRQ_IOP331_DMA1_ERR 58 52#define IRQ_IOP33X_DMA1_ERR 58
53#define IRQ_IOP331_AA_ERR 60 53#define IRQ_IOP33X_AA_ERR 60
54#define IRQ_IOP331_MSG_ERR 62 54#define IRQ_IOP33X_MSG_ERR 62
55#define IRQ_IOP331_HPI 63 55#define IRQ_IOP33X_HPI 63
56 56
57#define NR_IRQS 64 57#define NR_IRQS 64
58 58
59 59
60#endif // _IRQ_H_ 60#endif
diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h
index de208d2cca4e..0d39139b241e 100644
--- a/include/asm-arm/arch-iop33x/memory.h
+++ b/include/asm-arm/arch-iop33x/memory.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop33x/memory.h 2 * include/asm-arm/arch-iop33x/memory.h
3 */ 3 */
4 4
5#ifndef __ASM_ARCH_MEMORY_H 5#ifndef __MEMORY_H
6#define __ASM_ARCH_MEMORY_H 6#define __MEMORY_H
7 7
8#include <asm/hardware.h> 8#include <asm/hardware.h>
9 9
diff --git a/include/asm-arm/arch-iop33x/system.h b/include/asm-arm/arch-iop33x/system.h
index 8270ad9f86c8..00dd07ece262 100644
--- a/include/asm-arm/arch-iop33x/system.h
+++ b/include/asm-arm/arch-iop33x/system.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop33x/system.h 2 * include/asm-arm/arch-iop33x/system.h
3 * 3 *
4 * Copyright (C) 2001 MontaVista Software, Inc. 4 * Copyright (C) 2001 MontaVista Software, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -13,17 +13,10 @@ static inline void arch_idle(void)
13 cpu_do_idle(); 13 cpu_do_idle();
14} 14}
15 15
16
17static inline void arch_reset(char mode) 16static inline void arch_reset(char mode)
18{ 17{
19 *IOP3XX_PCSR = 0x30; 18 *IOP3XX_PCSR = 0x30;
20 19
21 if ( 1 && mode == 's') { 20 /* Jump into ROM at address 0 */
22 /* Jump into ROM at address 0 */ 21 cpu_reset(0);
23 cpu_reset(0);
24 } else {
25 /* No on-chip reset capability */
26 cpu_reset(0);
27 }
28} 22}
29
diff --git a/include/asm-arm/arch-iop33x/timex.h b/include/asm-arm/arch-iop33x/timex.h
index 8994322a09f4..fe3e1e369ff9 100644
--- a/include/asm-arm/arch-iop33x/timex.h
+++ b/include/asm-arm/arch-iop33x/timex.h
@@ -1,8 +1,9 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop33x/timex.h 2 * include/asm-arm/arch-iop33x/timex.h
3 * 3 *
4 * IOP3xx architecture timex specifications 4 * IOP3xx architecture timex specifications
5 */ 5 */
6
6#include <asm/hardware.h> 7#include <asm/hardware.h>
7 8
8#define CLOCK_TICK_RATE (100 * HZ) 9#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop33x/uncompress.h b/include/asm-arm/arch-iop33x/uncompress.h
index 62904ae3b038..e17fbc05877b 100644
--- a/include/asm-arm/arch-iop33x/uncompress.h
+++ b/include/asm-arm/arch-iop33x/uncompress.h
@@ -1,6 +1,7 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop33x/uncompress.h 2 * include/asm-arm/arch-iop33x/uncompress.h
3 */ 3 */
4
4#include <asm/types.h> 5#include <asm/types.h>
5#include <asm/mach-types.h> 6#include <asm/mach-types.h>
6#include <linux/serial_reg.h> 7#include <linux/serial_reg.h>
@@ -8,13 +9,13 @@
8 9
9static volatile u32 *uart_base; 10static volatile u32 *uart_base;
10 11
11#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) 12#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
12 13
13static inline void putc(char c) 14static inline void putc(char c)
14{ 15{
15 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) 16 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
16 barrier(); 17 barrier();
17 *uart_base = c; 18 uart_base[UART_TX] = c;
18} 19}
19 20
20static inline void flush(void) 21static inline void flush(void)
@@ -24,7 +25,7 @@ static inline void flush(void)
24static __inline__ void __arch_decomp_setup(unsigned long arch_id) 25static __inline__ void __arch_decomp_setup(unsigned long arch_id)
25{ 26{
26 if (machine_is_iq80331() || machine_is_iq80332()) 27 if (machine_is_iq80331() || machine_is_iq80332())
27 uart_base = (volatile u32 *)IOP331_UART0_PHYS; 28 uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
28 else 29 else
29 uart_base = (volatile u32 *)0xfe800000; 30 uart_base = (volatile u32 *)0xfe800000;
30} 31}
diff --git a/include/asm-arm/arch-iop33x/vmalloc.h b/include/asm-arm/arch-iop33x/vmalloc.h
index b5092027449e..66f545a7f4fc 100644
--- a/include/asm-arm/arch-iop33x/vmalloc.h
+++ b/include/asm-arm/arch-iop33x/vmalloc.h
@@ -1,16 +1,5 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop33x/vmalloc.h 2 * include/asm-arm/arch-iop33x/vmalloc.h
3 */ 3 */
4 4
5/* 5#define VMALLOC_END 0xfe000000
6 * Just any arbitrary offset to the start of the vmalloc VM area: the
7 * current 8MB value just means that there will be a 8MB "hole" after the
8 * physical memory until the kernel virtual memory starts. That means that
9 * any out-of-bounds memory accesses will hopefully be caught.
10 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
11 * area for the same reason. ;)
12 */
13//#define VMALLOC_END (0xe8000000)
14/* increase usable physical RAM to ~992M per RMK */
15#define VMALLOC_END (0xfe000000)
16